From 964d3960a2627602c2feae305badd4ad4fe548d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Tue, 24 Nov 2020 13:19:06 +0500 Subject: [PATCH] dec update --- el2_swerv_wrapper.fir | 4847 ++++++++--------- el2_swerv_wrapper.v | 3894 ++++++------- firrtl_black_box_resource_files.f | 4 +- ..._Wrapper.scala => el2_swerv_wrapper.scala} | 0 src/main/scala/lib/el2_lib.scala | 2 +- target/scala-2.12/classes/SWERV_Wrp$.class | Bin 3859 -> 3863 bytes .../classes/SWERV_Wrp$delayedInit$body.class | Bin 722 -> 726 bytes target/scala-2.12/classes/SWERV_Wrp.class | Bin 781 -> 785 bytes .../classes/el2_swerv_wrapper$$anon$1.class | Bin 29571 -> 29575 bytes .../classes/el2_swerv_wrapper.class | Bin 263178 -> 263182 bytes 10 files changed, 4441 insertions(+), 4306 deletions(-) rename src/main/scala/{SweRV_Wrapper.scala => el2_swerv_wrapper.scala} (100%) diff --git a/el2_swerv_wrapper.fir b/el2_swerv_wrapper.fir index c495b688..eb381342 100644 --- a/el2_swerv_wrapper.fir +++ b/el2_swerv_wrapper.fir @@ -67013,967 +67013,965 @@ circuit el2_swerv_wrapper : node _T_15 = or(_T_13, _T_14) @[el2_dec_decode_ctl.scala 217:56] node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[el2_dec_decode_ctl.scala 219:32] node data_gate_en = or(_T_15, _T_16) @[el2_dec_decode_ctl.scala 218:56] - inst data_gated_cgc of rvclkhdr_661 @[el2_dec_decode_ctl.scala 222:29] - data_gated_cgc.clock <= clock - data_gated_cgc.reset <= reset - data_gated_cgc.io.en <= data_gate_en @[el2_dec_decode_ctl.scala 223:31] - data_gated_cgc.io.scan_mode <= io.scan_mode @[el2_dec_decode_ctl.scala 224:31] - data_gated_cgc.io.clk <= clock @[el2_dec_decode_ctl.scala 225:31] - node _T_17 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 230:62] - node i0_brp_valid = and(io.dec_i0_brp.valid, _T_17) @[el2_dec_decode_ctl.scala 230:60] - io.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 231:43] - io.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 232:43] - io.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 233:43] - io.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 234:43] - io.dec_i0_predict_p_d.bits.pja <= i0_pja @[el2_dec_decode_ctl.scala 235:43] - io.dec_i0_predict_p_d.bits.pret <= i0_pret @[el2_dec_decode_ctl.scala 236:43] - io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[el2_dec_decode_ctl.scala 237:43] - io.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 238:43] - io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[el2_dec_decode_ctl.scala 239:43] - node _T_18 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 240:55] - io.dec_i0_predict_p_d.valid <= _T_18 @[el2_dec_decode_ctl.scala 240:38] - node _T_19 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 241:75] - node _T_20 = or(_T_19, i0_pja_raw) @[el2_dec_decode_ctl.scala 241:90] - node _T_21 = or(_T_20, i0_pret_raw) @[el2_dec_decode_ctl.scala 241:103] - node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:56] - node i0_notbr_error = and(i0_brp_valid, _T_22) @[el2_dec_decode_ctl.scala 241:54] - node _T_23 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 244:72] - node _T_24 = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 244:47] - node _T_25 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 244:106] - node _T_26 = and(_T_24, _T_25) @[el2_dec_decode_ctl.scala 244:76] - node _T_27 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:126] - node i0_br_toffset_error = and(_T_26, _T_27) @[el2_dec_decode_ctl.scala 244:124] - node _T_28 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[el2_dec_decode_ctl.scala 245:47] - node _T_29 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 245:74] - node i0_ret_error = and(_T_28, _T_29) @[el2_dec_decode_ctl.scala 245:72] - node _T_30 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 246:62] - node _T_31 = or(_T_30, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 246:79] - node i0_br_error = or(_T_31, i0_ret_error) @[el2_dec_decode_ctl.scala 246:101] - node _T_32 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 247:72] - node _T_33 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:94] - node _T_34 = and(_T_32, _T_33) @[el2_dec_decode_ctl.scala 247:92] - io.dec_i0_predict_p_d.bits.br_error <= _T_34 @[el2_dec_decode_ctl.scala 247:56] - node _T_35 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 248:94] - node _T_36 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 248:116] - node _T_37 = and(_T_35, _T_36) @[el2_dec_decode_ctl.scala 248:114] - io.dec_i0_predict_p_d.bits.br_start_error <= _T_37 @[el2_dec_decode_ctl.scala 248:56] - io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 249:32] - io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 250:32] - node _T_38 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[el2_dec_decode_ctl.scala 251:47] - node _T_39 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 251:86] - node i0_br_error_all = and(_T_38, _T_39) @[el2_dec_decode_ctl.scala 251:84] - io.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 252:49] - io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 253:32] - io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[el2_dec_decode_ctl.scala 254:56] - node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 260:36] - i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 263:9] - i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 263:9] - i0_dp.fence_i <= i0_dp_raw.fence_i @[el2_dec_decode_ctl.scala 263:9] - i0_dp.fence <= i0_dp_raw.fence @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rem <= i0_dp_raw.rem @[el2_dec_decode_ctl.scala 263:9] - i0_dp.div <= i0_dp_raw.div @[el2_dec_decode_ctl.scala 263:9] - i0_dp.low <= i0_dp_raw.low @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[el2_dec_decode_ctl.scala 263:9] - i0_dp.mul <= i0_dp_raw.mul @[el2_dec_decode_ctl.scala 263:9] - i0_dp.mret <= i0_dp_raw.mret @[el2_dec_decode_ctl.scala 263:9] - i0_dp.ecall <= i0_dp_raw.ecall @[el2_dec_decode_ctl.scala 263:9] - i0_dp.ebreak <= i0_dp_raw.ebreak @[el2_dec_decode_ctl.scala 263:9] - i0_dp.postsync <= i0_dp_raw.postsync @[el2_dec_decode_ctl.scala 263:9] - i0_dp.presync <= i0_dp_raw.presync @[el2_dec_decode_ctl.scala 263:9] - i0_dp.csr_imm <= i0_dp_raw.csr_imm @[el2_dec_decode_ctl.scala 263:9] - i0_dp.csr_write <= i0_dp_raw.csr_write @[el2_dec_decode_ctl.scala 263:9] - i0_dp.csr_set <= i0_dp_raw.csr_set @[el2_dec_decode_ctl.scala 263:9] - i0_dp.csr_clr <= i0_dp_raw.csr_clr @[el2_dec_decode_ctl.scala 263:9] - i0_dp.csr_read <= i0_dp_raw.csr_read @[el2_dec_decode_ctl.scala 263:9] - i0_dp.word <= i0_dp_raw.word @[el2_dec_decode_ctl.scala 263:9] - i0_dp.half <= i0_dp_raw.half @[el2_dec_decode_ctl.scala 263:9] - i0_dp.by <= i0_dp_raw.by @[el2_dec_decode_ctl.scala 263:9] - i0_dp.jal <= i0_dp_raw.jal @[el2_dec_decode_ctl.scala 263:9] - i0_dp.blt <= i0_dp_raw.blt @[el2_dec_decode_ctl.scala 263:9] - i0_dp.bge <= i0_dp_raw.bge @[el2_dec_decode_ctl.scala 263:9] - i0_dp.bne <= i0_dp_raw.bne @[el2_dec_decode_ctl.scala 263:9] - i0_dp.beq <= i0_dp_raw.beq @[el2_dec_decode_ctl.scala 263:9] - i0_dp.condbr <= i0_dp_raw.condbr @[el2_dec_decode_ctl.scala 263:9] - i0_dp.unsign <= i0_dp_raw.unsign @[el2_dec_decode_ctl.scala 263:9] - i0_dp.slt <= i0_dp_raw.slt @[el2_dec_decode_ctl.scala 263:9] - i0_dp.srl <= i0_dp_raw.srl @[el2_dec_decode_ctl.scala 263:9] - i0_dp.sra <= i0_dp_raw.sra @[el2_dec_decode_ctl.scala 263:9] - i0_dp.sll <= i0_dp_raw.sll @[el2_dec_decode_ctl.scala 263:9] - i0_dp.lxor <= i0_dp_raw.lxor @[el2_dec_decode_ctl.scala 263:9] - i0_dp.lor <= i0_dp_raw.lor @[el2_dec_decode_ctl.scala 263:9] - i0_dp.land <= i0_dp_raw.land @[el2_dec_decode_ctl.scala 263:9] - i0_dp.sub <= i0_dp_raw.sub @[el2_dec_decode_ctl.scala 263:9] - i0_dp.add <= i0_dp_raw.add @[el2_dec_decode_ctl.scala 263:9] - i0_dp.lsu <= i0_dp_raw.lsu @[el2_dec_decode_ctl.scala 263:9] - i0_dp.store <= i0_dp_raw.store @[el2_dec_decode_ctl.scala 263:9] - i0_dp.load <= i0_dp_raw.load @[el2_dec_decode_ctl.scala 263:9] - i0_dp.pc <= i0_dp_raw.pc @[el2_dec_decode_ctl.scala 263:9] - i0_dp.imm20 <= i0_dp_raw.imm20 @[el2_dec_decode_ctl.scala 263:9] - i0_dp.shimm5 <= i0_dp_raw.shimm5 @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rd <= i0_dp_raw.rd @[el2_dec_decode_ctl.scala 263:9] - i0_dp.imm12 <= i0_dp_raw.imm12 @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rs2 <= i0_dp_raw.rs2 @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rs1 <= i0_dp_raw.rs1 @[el2_dec_decode_ctl.scala 263:9] - i0_dp.alu <= i0_dp_raw.alu @[el2_dec_decode_ctl.scala 263:9] - node _T_40 = or(i0_br_error_all, i0_icaf_d) @[el2_dec_decode_ctl.scala 264:25] - node _T_41 = bits(_T_40, 0, 0) @[el2_dec_decode_ctl.scala 264:43] - when _T_41 : @[el2_dec_decode_ctl.scala 264:50] - wire _T_42 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 265:35] - _T_42.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.pm_alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.fence <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rem <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.div <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.mret <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.ecall <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.ebreak <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.postsync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.presync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.csr_imm <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.csr_write <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.csr_set <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.csr_clr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.csr_read <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.jal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.blt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.bge <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.bne <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.beq <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.condbr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.slt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.srl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.sra <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.sll <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.lxor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.lor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.land <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.sub <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.add <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.lsu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.pc <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.imm20 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.shimm5 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rd <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.imm12 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rs2 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rs1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - i0_dp.legal <= _T_42.legal @[el2_dec_decode_ctl.scala 265:20] - i0_dp.pm_alu <= _T_42.pm_alu @[el2_dec_decode_ctl.scala 265:20] - i0_dp.fence_i <= _T_42.fence_i @[el2_dec_decode_ctl.scala 265:20] - i0_dp.fence <= _T_42.fence @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rem <= _T_42.rem @[el2_dec_decode_ctl.scala 265:20] - i0_dp.div <= _T_42.div @[el2_dec_decode_ctl.scala 265:20] - i0_dp.low <= _T_42.low @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rs2_sign <= _T_42.rs2_sign @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rs1_sign <= _T_42.rs1_sign @[el2_dec_decode_ctl.scala 265:20] - i0_dp.mul <= _T_42.mul @[el2_dec_decode_ctl.scala 265:20] - i0_dp.mret <= _T_42.mret @[el2_dec_decode_ctl.scala 265:20] - i0_dp.ecall <= _T_42.ecall @[el2_dec_decode_ctl.scala 265:20] - i0_dp.ebreak <= _T_42.ebreak @[el2_dec_decode_ctl.scala 265:20] - i0_dp.postsync <= _T_42.postsync @[el2_dec_decode_ctl.scala 265:20] - i0_dp.presync <= _T_42.presync @[el2_dec_decode_ctl.scala 265:20] - i0_dp.csr_imm <= _T_42.csr_imm @[el2_dec_decode_ctl.scala 265:20] - i0_dp.csr_write <= _T_42.csr_write @[el2_dec_decode_ctl.scala 265:20] - i0_dp.csr_set <= _T_42.csr_set @[el2_dec_decode_ctl.scala 265:20] - i0_dp.csr_clr <= _T_42.csr_clr @[el2_dec_decode_ctl.scala 265:20] - i0_dp.csr_read <= _T_42.csr_read @[el2_dec_decode_ctl.scala 265:20] - i0_dp.word <= _T_42.word @[el2_dec_decode_ctl.scala 265:20] - i0_dp.half <= _T_42.half @[el2_dec_decode_ctl.scala 265:20] - i0_dp.by <= _T_42.by @[el2_dec_decode_ctl.scala 265:20] - i0_dp.jal <= _T_42.jal @[el2_dec_decode_ctl.scala 265:20] - i0_dp.blt <= _T_42.blt @[el2_dec_decode_ctl.scala 265:20] - i0_dp.bge <= _T_42.bge @[el2_dec_decode_ctl.scala 265:20] - i0_dp.bne <= _T_42.bne @[el2_dec_decode_ctl.scala 265:20] - i0_dp.beq <= _T_42.beq @[el2_dec_decode_ctl.scala 265:20] - i0_dp.condbr <= _T_42.condbr @[el2_dec_decode_ctl.scala 265:20] - i0_dp.unsign <= _T_42.unsign @[el2_dec_decode_ctl.scala 265:20] - i0_dp.slt <= _T_42.slt @[el2_dec_decode_ctl.scala 265:20] - i0_dp.srl <= _T_42.srl @[el2_dec_decode_ctl.scala 265:20] - i0_dp.sra <= _T_42.sra @[el2_dec_decode_ctl.scala 265:20] - i0_dp.sll <= _T_42.sll @[el2_dec_decode_ctl.scala 265:20] - i0_dp.lxor <= _T_42.lxor @[el2_dec_decode_ctl.scala 265:20] - i0_dp.lor <= _T_42.lor @[el2_dec_decode_ctl.scala 265:20] - i0_dp.land <= _T_42.land @[el2_dec_decode_ctl.scala 265:20] - i0_dp.sub <= _T_42.sub @[el2_dec_decode_ctl.scala 265:20] - i0_dp.add <= _T_42.add @[el2_dec_decode_ctl.scala 265:20] - i0_dp.lsu <= _T_42.lsu @[el2_dec_decode_ctl.scala 265:20] - i0_dp.store <= _T_42.store @[el2_dec_decode_ctl.scala 265:20] - i0_dp.load <= _T_42.load @[el2_dec_decode_ctl.scala 265:20] - i0_dp.pc <= _T_42.pc @[el2_dec_decode_ctl.scala 265:20] - i0_dp.imm20 <= _T_42.imm20 @[el2_dec_decode_ctl.scala 265:20] - i0_dp.shimm5 <= _T_42.shimm5 @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rd <= _T_42.rd @[el2_dec_decode_ctl.scala 265:20] - i0_dp.imm12 <= _T_42.imm12 @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rs2 <= _T_42.rs2 @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rs1 <= _T_42.rs1 @[el2_dec_decode_ctl.scala 265:20] - i0_dp.alu <= _T_42.alu @[el2_dec_decode_ctl.scala 265:20] - i0_dp.alu <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 266:20] - i0_dp.rs1 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 267:20] - i0_dp.rs2 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 268:20] - i0_dp.lor <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 269:20] - i0_dp.legal <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 270:20] - i0_dp.postsync <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 271:20] - skip @[el2_dec_decode_ctl.scala 264:50] - io.dec_i0_select_pc_d <= i0_dp.pc @[el2_dec_decode_ctl.scala 275:25] - node _T_43 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 278:38] - node _T_44 = or(_T_43, i0_pja) @[el2_dec_decode_ctl.scala 278:49] - node i0_predict_br = or(_T_44, i0_pret) @[el2_dec_decode_ctl.scala 278:58] - node _T_45 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 280:51] - node _T_46 = and(_T_45, i0_brp_valid) @[el2_dec_decode_ctl.scala 280:55] - node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 280:26] - node i0_predict_nt = and(_T_47, i0_predict_br) @[el2_dec_decode_ctl.scala 280:71] - node _T_48 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 281:51] - node _T_49 = and(_T_48, i0_brp_valid) @[el2_dec_decode_ctl.scala 281:55] - node i0_predict_t = and(_T_49, i0_predict_br) @[el2_dec_decode_ctl.scala 281:71] - node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 282:20] - io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 284:26] - io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 285:26] - io.i0_ap.add <= i0_dp.add @[el2_dec_decode_ctl.scala 287:20] - io.i0_ap.sub <= i0_dp.sub @[el2_dec_decode_ctl.scala 288:20] - io.i0_ap.land <= i0_dp.land @[el2_dec_decode_ctl.scala 289:20] - io.i0_ap.lor <= i0_dp.lor @[el2_dec_decode_ctl.scala 290:20] - io.i0_ap.lxor <= i0_dp.lxor @[el2_dec_decode_ctl.scala 291:20] - io.i0_ap.sll <= i0_dp.sll @[el2_dec_decode_ctl.scala 292:20] - io.i0_ap.srl <= i0_dp.srl @[el2_dec_decode_ctl.scala 293:20] - io.i0_ap.sra <= i0_dp.sra @[el2_dec_decode_ctl.scala 294:20] - io.i0_ap.slt <= i0_dp.slt @[el2_dec_decode_ctl.scala 295:20] - io.i0_ap.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 296:20] - io.i0_ap.beq <= i0_dp.beq @[el2_dec_decode_ctl.scala 297:20] - io.i0_ap.bne <= i0_dp.bne @[el2_dec_decode_ctl.scala 298:20] - io.i0_ap.blt <= i0_dp.blt @[el2_dec_decode_ctl.scala 299:20] - io.i0_ap.bge <= i0_dp.bge @[el2_dec_decode_ctl.scala 300:20] - io.i0_ap.csr_write <= i0_csr_write_only_d @[el2_dec_decode_ctl.scala 301:22] - io.i0_ap.csr_imm <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 302:22] - io.i0_ap.jal <= i0_jal @[el2_dec_decode_ctl.scala 303:22] - node _T_50 = eq(cam[0].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] - node _T_51 = bits(_T_50, 0, 0) @[el2_dec_decode_ctl.scala 307:137] - node _T_52 = shl(cam_write, 0) @[el2_dec_decode_ctl.scala 307:158] - node _T_53 = eq(cam[1].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] - node _T_54 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_55 = bits(_T_53, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_56 = and(_T_54, _T_55) @[el2_dec_decode_ctl.scala 307:126] - node _T_57 = bits(_T_56, 0, 0) @[el2_dec_decode_ctl.scala 307:137] - node _T_58 = shl(cam_write, 1) @[el2_dec_decode_ctl.scala 307:158] - node _T_59 = eq(cam[2].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] - node _T_60 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_61 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_62 = and(_T_60, _T_61) @[el2_dec_decode_ctl.scala 307:126] - node _T_63 = bits(_T_62, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_64 = bits(_T_59, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_65 = and(_T_63, _T_64) @[el2_dec_decode_ctl.scala 307:126] - node _T_66 = bits(_T_65, 0, 0) @[el2_dec_decode_ctl.scala 307:137] - node _T_67 = shl(cam_write, 2) @[el2_dec_decode_ctl.scala 307:158] - node _T_68 = eq(cam[3].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] - node _T_69 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_70 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_71 = and(_T_69, _T_70) @[el2_dec_decode_ctl.scala 307:126] - node _T_72 = bits(_T_71, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_73 = bits(cam[2].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_74 = and(_T_72, _T_73) @[el2_dec_decode_ctl.scala 307:126] - node _T_75 = bits(_T_74, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_76 = bits(_T_68, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_77 = and(_T_75, _T_76) @[el2_dec_decode_ctl.scala 307:126] - node _T_78 = bits(_T_77, 0, 0) @[el2_dec_decode_ctl.scala 307:137] - node _T_79 = shl(cam_write, 3) @[el2_dec_decode_ctl.scala 307:158] - node _T_80 = mux(_T_51, _T_52, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_81 = mux(_T_57, _T_58, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_82 = mux(_T_66, _T_67, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_83 = mux(_T_78, _T_79, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_84 = or(_T_80, _T_81) @[Mux.scala 27:72] - node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72] + node _T_17 = bits(data_gate_en, 0, 0) @[el2_dec_decode_ctl.scala 222:56] + inst rvclkhdr of rvclkhdr_661 @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= _T_17 @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 226:62] + node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[el2_dec_decode_ctl.scala 226:60] + io.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 227:43] + io.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 228:43] + io.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 229:43] + io.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 230:43] + io.dec_i0_predict_p_d.bits.pja <= i0_pja @[el2_dec_decode_ctl.scala 231:43] + io.dec_i0_predict_p_d.bits.pret <= i0_pret @[el2_dec_decode_ctl.scala 232:43] + io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[el2_dec_decode_ctl.scala 233:43] + io.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 234:43] + io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[el2_dec_decode_ctl.scala 235:43] + node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 236:55] + io.dec_i0_predict_p_d.valid <= _T_19 @[el2_dec_decode_ctl.scala 236:38] + node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 237:75] + node _T_21 = or(_T_20, i0_pja_raw) @[el2_dec_decode_ctl.scala 237:90] + node _T_22 = or(_T_21, i0_pret_raw) @[el2_dec_decode_ctl.scala 237:103] + node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 237:56] + node i0_notbr_error = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 237:54] + node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:72] + node _T_25 = and(i0_brp_valid, _T_24) @[el2_dec_decode_ctl.scala 240:47] + node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:106] + node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:76] + node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:126] + node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:124] + node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[el2_dec_decode_ctl.scala 241:47] + node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:74] + node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:72] + node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:62] + node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:79] + node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:101] + node _T_33 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 243:72] + node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 243:94] + node _T_35 = and(_T_33, _T_34) @[el2_dec_decode_ctl.scala 243:92] + io.dec_i0_predict_p_d.bits.br_error <= _T_35 @[el2_dec_decode_ctl.scala 243:56] + node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:94] + node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:116] + node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:114] + io.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[el2_dec_decode_ctl.scala 244:56] + io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 245:32] + io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 246:32] + node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[el2_dec_decode_ctl.scala 247:47] + node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:86] + node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:84] + io.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 248:49] + io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 249:32] + io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[el2_dec_decode_ctl.scala 250:56] + node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 256:36] + i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 259:9] + i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 259:9] + i0_dp.fence_i <= i0_dp_raw.fence_i @[el2_dec_decode_ctl.scala 259:9] + i0_dp.fence <= i0_dp_raw.fence @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rem <= i0_dp_raw.rem @[el2_dec_decode_ctl.scala 259:9] + i0_dp.div <= i0_dp_raw.div @[el2_dec_decode_ctl.scala 259:9] + i0_dp.low <= i0_dp_raw.low @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[el2_dec_decode_ctl.scala 259:9] + i0_dp.mul <= i0_dp_raw.mul @[el2_dec_decode_ctl.scala 259:9] + i0_dp.mret <= i0_dp_raw.mret @[el2_dec_decode_ctl.scala 259:9] + i0_dp.ecall <= i0_dp_raw.ecall @[el2_dec_decode_ctl.scala 259:9] + i0_dp.ebreak <= i0_dp_raw.ebreak @[el2_dec_decode_ctl.scala 259:9] + i0_dp.postsync <= i0_dp_raw.postsync @[el2_dec_decode_ctl.scala 259:9] + i0_dp.presync <= i0_dp_raw.presync @[el2_dec_decode_ctl.scala 259:9] + i0_dp.csr_imm <= i0_dp_raw.csr_imm @[el2_dec_decode_ctl.scala 259:9] + i0_dp.csr_write <= i0_dp_raw.csr_write @[el2_dec_decode_ctl.scala 259:9] + i0_dp.csr_set <= i0_dp_raw.csr_set @[el2_dec_decode_ctl.scala 259:9] + i0_dp.csr_clr <= i0_dp_raw.csr_clr @[el2_dec_decode_ctl.scala 259:9] + i0_dp.csr_read <= i0_dp_raw.csr_read @[el2_dec_decode_ctl.scala 259:9] + i0_dp.word <= i0_dp_raw.word @[el2_dec_decode_ctl.scala 259:9] + i0_dp.half <= i0_dp_raw.half @[el2_dec_decode_ctl.scala 259:9] + i0_dp.by <= i0_dp_raw.by @[el2_dec_decode_ctl.scala 259:9] + i0_dp.jal <= i0_dp_raw.jal @[el2_dec_decode_ctl.scala 259:9] + i0_dp.blt <= i0_dp_raw.blt @[el2_dec_decode_ctl.scala 259:9] + i0_dp.bge <= i0_dp_raw.bge @[el2_dec_decode_ctl.scala 259:9] + i0_dp.bne <= i0_dp_raw.bne @[el2_dec_decode_ctl.scala 259:9] + i0_dp.beq <= i0_dp_raw.beq @[el2_dec_decode_ctl.scala 259:9] + i0_dp.condbr <= i0_dp_raw.condbr @[el2_dec_decode_ctl.scala 259:9] + i0_dp.unsign <= i0_dp_raw.unsign @[el2_dec_decode_ctl.scala 259:9] + i0_dp.slt <= i0_dp_raw.slt @[el2_dec_decode_ctl.scala 259:9] + i0_dp.srl <= i0_dp_raw.srl @[el2_dec_decode_ctl.scala 259:9] + i0_dp.sra <= i0_dp_raw.sra @[el2_dec_decode_ctl.scala 259:9] + i0_dp.sll <= i0_dp_raw.sll @[el2_dec_decode_ctl.scala 259:9] + i0_dp.lxor <= i0_dp_raw.lxor @[el2_dec_decode_ctl.scala 259:9] + i0_dp.lor <= i0_dp_raw.lor @[el2_dec_decode_ctl.scala 259:9] + i0_dp.land <= i0_dp_raw.land @[el2_dec_decode_ctl.scala 259:9] + i0_dp.sub <= i0_dp_raw.sub @[el2_dec_decode_ctl.scala 259:9] + i0_dp.add <= i0_dp_raw.add @[el2_dec_decode_ctl.scala 259:9] + i0_dp.lsu <= i0_dp_raw.lsu @[el2_dec_decode_ctl.scala 259:9] + i0_dp.store <= i0_dp_raw.store @[el2_dec_decode_ctl.scala 259:9] + i0_dp.load <= i0_dp_raw.load @[el2_dec_decode_ctl.scala 259:9] + i0_dp.pc <= i0_dp_raw.pc @[el2_dec_decode_ctl.scala 259:9] + i0_dp.imm20 <= i0_dp_raw.imm20 @[el2_dec_decode_ctl.scala 259:9] + i0_dp.shimm5 <= i0_dp_raw.shimm5 @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rd <= i0_dp_raw.rd @[el2_dec_decode_ctl.scala 259:9] + i0_dp.imm12 <= i0_dp_raw.imm12 @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rs2 <= i0_dp_raw.rs2 @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rs1 <= i0_dp_raw.rs1 @[el2_dec_decode_ctl.scala 259:9] + i0_dp.alu <= i0_dp_raw.alu @[el2_dec_decode_ctl.scala 259:9] + node _T_41 = or(i0_br_error_all, i0_icaf_d) @[el2_dec_decode_ctl.scala 260:25] + node _T_42 = bits(_T_41, 0, 0) @[el2_dec_decode_ctl.scala 260:43] + when _T_42 : @[el2_dec_decode_ctl.scala 260:50] + wire _T_43 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 261:35] + _T_43.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.pm_alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.fence <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rem <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.div <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.mret <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.ecall <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.ebreak <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.postsync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.presync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.csr_imm <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.csr_write <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.csr_set <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.csr_clr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.csr_read <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.jal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.blt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.bge <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.bne <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.beq <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.condbr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.slt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.srl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.sra <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.sll <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.lxor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.lor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.land <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.sub <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.add <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.lsu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.pc <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.imm20 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.shimm5 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rd <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.imm12 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rs2 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rs1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + i0_dp.legal <= _T_43.legal @[el2_dec_decode_ctl.scala 261:20] + i0_dp.pm_alu <= _T_43.pm_alu @[el2_dec_decode_ctl.scala 261:20] + i0_dp.fence_i <= _T_43.fence_i @[el2_dec_decode_ctl.scala 261:20] + i0_dp.fence <= _T_43.fence @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rem <= _T_43.rem @[el2_dec_decode_ctl.scala 261:20] + i0_dp.div <= _T_43.div @[el2_dec_decode_ctl.scala 261:20] + i0_dp.low <= _T_43.low @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rs2_sign <= _T_43.rs2_sign @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rs1_sign <= _T_43.rs1_sign @[el2_dec_decode_ctl.scala 261:20] + i0_dp.mul <= _T_43.mul @[el2_dec_decode_ctl.scala 261:20] + i0_dp.mret <= _T_43.mret @[el2_dec_decode_ctl.scala 261:20] + i0_dp.ecall <= _T_43.ecall @[el2_dec_decode_ctl.scala 261:20] + i0_dp.ebreak <= _T_43.ebreak @[el2_dec_decode_ctl.scala 261:20] + i0_dp.postsync <= _T_43.postsync @[el2_dec_decode_ctl.scala 261:20] + i0_dp.presync <= _T_43.presync @[el2_dec_decode_ctl.scala 261:20] + i0_dp.csr_imm <= _T_43.csr_imm @[el2_dec_decode_ctl.scala 261:20] + i0_dp.csr_write <= _T_43.csr_write @[el2_dec_decode_ctl.scala 261:20] + i0_dp.csr_set <= _T_43.csr_set @[el2_dec_decode_ctl.scala 261:20] + i0_dp.csr_clr <= _T_43.csr_clr @[el2_dec_decode_ctl.scala 261:20] + i0_dp.csr_read <= _T_43.csr_read @[el2_dec_decode_ctl.scala 261:20] + i0_dp.word <= _T_43.word @[el2_dec_decode_ctl.scala 261:20] + i0_dp.half <= _T_43.half @[el2_dec_decode_ctl.scala 261:20] + i0_dp.by <= _T_43.by @[el2_dec_decode_ctl.scala 261:20] + i0_dp.jal <= _T_43.jal @[el2_dec_decode_ctl.scala 261:20] + i0_dp.blt <= _T_43.blt @[el2_dec_decode_ctl.scala 261:20] + i0_dp.bge <= _T_43.bge @[el2_dec_decode_ctl.scala 261:20] + i0_dp.bne <= _T_43.bne @[el2_dec_decode_ctl.scala 261:20] + i0_dp.beq <= _T_43.beq @[el2_dec_decode_ctl.scala 261:20] + i0_dp.condbr <= _T_43.condbr @[el2_dec_decode_ctl.scala 261:20] + i0_dp.unsign <= _T_43.unsign @[el2_dec_decode_ctl.scala 261:20] + i0_dp.slt <= _T_43.slt @[el2_dec_decode_ctl.scala 261:20] + i0_dp.srl <= _T_43.srl @[el2_dec_decode_ctl.scala 261:20] + i0_dp.sra <= _T_43.sra @[el2_dec_decode_ctl.scala 261:20] + i0_dp.sll <= _T_43.sll @[el2_dec_decode_ctl.scala 261:20] + i0_dp.lxor <= _T_43.lxor @[el2_dec_decode_ctl.scala 261:20] + i0_dp.lor <= _T_43.lor @[el2_dec_decode_ctl.scala 261:20] + i0_dp.land <= _T_43.land @[el2_dec_decode_ctl.scala 261:20] + i0_dp.sub <= _T_43.sub @[el2_dec_decode_ctl.scala 261:20] + i0_dp.add <= _T_43.add @[el2_dec_decode_ctl.scala 261:20] + i0_dp.lsu <= _T_43.lsu @[el2_dec_decode_ctl.scala 261:20] + i0_dp.store <= _T_43.store @[el2_dec_decode_ctl.scala 261:20] + i0_dp.load <= _T_43.load @[el2_dec_decode_ctl.scala 261:20] + i0_dp.pc <= _T_43.pc @[el2_dec_decode_ctl.scala 261:20] + i0_dp.imm20 <= _T_43.imm20 @[el2_dec_decode_ctl.scala 261:20] + i0_dp.shimm5 <= _T_43.shimm5 @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rd <= _T_43.rd @[el2_dec_decode_ctl.scala 261:20] + i0_dp.imm12 <= _T_43.imm12 @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rs2 <= _T_43.rs2 @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rs1 <= _T_43.rs1 @[el2_dec_decode_ctl.scala 261:20] + i0_dp.alu <= _T_43.alu @[el2_dec_decode_ctl.scala 261:20] + i0_dp.alu <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 262:20] + i0_dp.rs1 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 263:20] + i0_dp.rs2 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 264:20] + i0_dp.lor <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 265:20] + i0_dp.legal <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 266:20] + i0_dp.postsync <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 267:20] + skip @[el2_dec_decode_ctl.scala 260:50] + io.dec_i0_select_pc_d <= i0_dp.pc @[el2_dec_decode_ctl.scala 271:25] + node _T_44 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 274:38] + node _T_45 = or(_T_44, i0_pja) @[el2_dec_decode_ctl.scala 274:49] + node i0_predict_br = or(_T_45, i0_pret) @[el2_dec_decode_ctl.scala 274:58] + node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:51] + node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:55] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 276:26] + node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:71] + node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:51] + node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:55] + node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:71] + node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 278:20] + io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 280:26] + io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 281:26] + io.i0_ap.add <= i0_dp.add @[el2_dec_decode_ctl.scala 283:20] + io.i0_ap.sub <= i0_dp.sub @[el2_dec_decode_ctl.scala 284:20] + io.i0_ap.land <= i0_dp.land @[el2_dec_decode_ctl.scala 285:20] + io.i0_ap.lor <= i0_dp.lor @[el2_dec_decode_ctl.scala 286:20] + io.i0_ap.lxor <= i0_dp.lxor @[el2_dec_decode_ctl.scala 287:20] + io.i0_ap.sll <= i0_dp.sll @[el2_dec_decode_ctl.scala 288:20] + io.i0_ap.srl <= i0_dp.srl @[el2_dec_decode_ctl.scala 289:20] + io.i0_ap.sra <= i0_dp.sra @[el2_dec_decode_ctl.scala 290:20] + io.i0_ap.slt <= i0_dp.slt @[el2_dec_decode_ctl.scala 291:20] + io.i0_ap.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 292:20] + io.i0_ap.beq <= i0_dp.beq @[el2_dec_decode_ctl.scala 293:20] + io.i0_ap.bne <= i0_dp.bne @[el2_dec_decode_ctl.scala 294:20] + io.i0_ap.blt <= i0_dp.blt @[el2_dec_decode_ctl.scala 295:20] + io.i0_ap.bge <= i0_dp.bge @[el2_dec_decode_ctl.scala 296:20] + io.i0_ap.csr_write <= i0_csr_write_only_d @[el2_dec_decode_ctl.scala 297:22] + io.i0_ap.csr_imm <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 298:22] + io.i0_ap.jal <= i0_jal @[el2_dec_decode_ctl.scala 299:22] + node _T_51 = eq(cam[0].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78] + node _T_52 = bits(_T_51, 0, 0) @[el2_dec_decode_ctl.scala 303:137] + node _T_53 = shl(cam_write, 0) @[el2_dec_decode_ctl.scala 303:158] + node _T_54 = eq(cam[1].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78] + node _T_55 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_56 = bits(_T_54, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_57 = and(_T_55, _T_56) @[el2_dec_decode_ctl.scala 303:126] + node _T_58 = bits(_T_57, 0, 0) @[el2_dec_decode_ctl.scala 303:137] + node _T_59 = shl(cam_write, 1) @[el2_dec_decode_ctl.scala 303:158] + node _T_60 = eq(cam[2].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78] + node _T_61 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_62 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_63 = and(_T_61, _T_62) @[el2_dec_decode_ctl.scala 303:126] + node _T_64 = bits(_T_63, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_65 = bits(_T_60, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_66 = and(_T_64, _T_65) @[el2_dec_decode_ctl.scala 303:126] + node _T_67 = bits(_T_66, 0, 0) @[el2_dec_decode_ctl.scala 303:137] + node _T_68 = shl(cam_write, 2) @[el2_dec_decode_ctl.scala 303:158] + node _T_69 = eq(cam[3].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78] + node _T_70 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_71 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_72 = and(_T_70, _T_71) @[el2_dec_decode_ctl.scala 303:126] + node _T_73 = bits(_T_72, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_74 = bits(cam[2].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_75 = and(_T_73, _T_74) @[el2_dec_decode_ctl.scala 303:126] + node _T_76 = bits(_T_75, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_77 = bits(_T_69, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_78 = and(_T_76, _T_77) @[el2_dec_decode_ctl.scala 303:126] + node _T_79 = bits(_T_78, 0, 0) @[el2_dec_decode_ctl.scala 303:137] + node _T_80 = shl(cam_write, 3) @[el2_dec_decode_ctl.scala 303:158] + node _T_81 = mux(_T_52, _T_53, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_82 = mux(_T_58, _T_59, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_83 = mux(_T_67, _T_68, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_84 = mux(_T_79, _T_80, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_85 = or(_T_81, _T_82) @[Mux.scala 27:72] node _T_86 = or(_T_85, _T_83) @[Mux.scala 27:72] - wire _T_87 : UInt<4> @[Mux.scala 27:72] - _T_87 <= _T_86 @[Mux.scala 27:72] - cam_wen <= _T_87 @[el2_dec_decode_ctl.scala 307:11] - cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 309:25] - node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 310:54] - node cam_inv_reset_tag = bits(io.lsu_nonblock_load_inv_tag_r, 1, 0) @[el2_dec_decode_ctl.scala 313:59] - node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 315:63] - node cam_data_reset_tag = bits(io.lsu_nonblock_load_data_tag, 1, 0) @[el2_dec_decode_ctl.scala 316:60] - node _T_88 = bits(x_d.bits.i0load, 0, 0) @[el2_dec_decode_ctl.scala 318:48] - node nonblock_load_rd = mux(_T_88, x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 318:31] - node _T_89 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 322:116] + node _T_87 = or(_T_86, _T_84) @[Mux.scala 27:72] + wire _T_88 : UInt<4> @[Mux.scala 27:72] + _T_88 <= _T_87 @[Mux.scala 27:72] + cam_wen <= _T_88 @[el2_dec_decode_ctl.scala 303:11] + cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 305:25] + node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 306:54] + node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 311:63] + node _T_89 = bits(x_d.bits.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:48] + node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] + node _T_90 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 318:116] reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_89 : @[Reg.scala 28:19] + when _T_90 : @[Reg.scala 28:19] nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 323:56] - node _T_90 = eq(cam_inv_reset_tag, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 325:66] - node _T_91 = and(io.lsu_nonblock_load_inv_r, _T_90) @[el2_dec_decode_ctl.scala 325:45] - node _T_92 = and(_T_91, cam[0].valid) @[el2_dec_decode_ctl.scala 325:87] - cam_inv_reset_val[0] <= _T_92 @[el2_dec_decode_ctl.scala 325:26] - node _T_93 = eq(cam_data_reset_tag, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 326:67] - node _T_94 = and(cam_data_reset, _T_93) @[el2_dec_decode_ctl.scala 326:45] - node _T_95 = and(_T_94, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 326:88] - cam_data_reset_val[0] <= _T_95 @[el2_dec_decode_ctl.scala 326:27] - wire _T_96 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 327:28] - _T_96.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_96.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_96.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_96.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - cam_in[0].bits.rd <= _T_96.bits.rd @[el2_dec_decode_ctl.scala 327:14] - cam_in[0].bits.tag <= _T_96.bits.tag @[el2_dec_decode_ctl.scala 327:14] - cam_in[0].bits.wb <= _T_96.bits.wb @[el2_dec_decode_ctl.scala 327:14] - cam_in[0].valid <= _T_96.valid @[el2_dec_decode_ctl.scala 327:14] - cam[0].bits.rd <= cam_raw[0].bits.rd @[el2_dec_decode_ctl.scala 328:11] - cam[0].bits.tag <= cam_raw[0].bits.tag @[el2_dec_decode_ctl.scala 328:11] - cam[0].bits.wb <= cam_raw[0].bits.wb @[el2_dec_decode_ctl.scala 328:11] - cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 328:11] - node _T_97 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 330:32] - when _T_97 : @[el2_dec_decode_ctl.scala 330:39] - cam[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] - skip @[el2_dec_decode_ctl.scala 330:39] - node _T_98 = bits(cam_wen, 0, 0) @[el2_dec_decode_ctl.scala 333:17] - node _T_99 = bits(_T_98, 0, 0) @[el2_dec_decode_ctl.scala 333:21] - when _T_99 : @[el2_dec_decode_ctl.scala 333:28] - cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] - cam_in[0].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:32] - cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:32] - cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:32] - skip @[el2_dec_decode_ctl.scala 333:28] - else : @[el2_dec_decode_ctl.scala 338:131] - node _T_100 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 338:37] - node _T_101 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] - node _T_102 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 338:85] - node _T_103 = and(_T_101, _T_102) @[el2_dec_decode_ctl.scala 338:64] - node _T_104 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 338:123] - node _T_105 = and(_T_103, _T_104) @[el2_dec_decode_ctl.scala 338:105] - node _T_106 = or(_T_100, _T_105) @[el2_dec_decode_ctl.scala 338:44] - when _T_106 : @[el2_dec_decode_ctl.scala 338:131] - cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] - skip @[el2_dec_decode_ctl.scala 338:131] - else : @[el2_dec_decode_ctl.scala 340:16] - cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 341:22] - cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 341:22] - cam_in[0].bits.wb <= cam[0].bits.wb @[el2_dec_decode_ctl.scala 341:22] - cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 341:22] - skip @[el2_dec_decode_ctl.scala 340:16] - node _T_107 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] - node _T_108 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 343:79] - node _T_109 = and(_T_107, _T_108) @[el2_dec_decode_ctl.scala 343:44] - node _T_110 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:115] - node _T_111 = and(_T_109, _T_110) @[el2_dec_decode_ctl.scala 343:100] - when _T_111 : @[el2_dec_decode_ctl.scala 343:122] - cam_in[0].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:25] - skip @[el2_dec_decode_ctl.scala 343:122] - when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] - cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] - skip @[el2_dec_decode_ctl.scala 347:32] - wire _T_112 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 351:70] - _T_112.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_112.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_112.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_112.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - reg _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_112)) @[el2_dec_decode_ctl.scala 351:47] - _T_113.bits.rd <= cam_in[0].bits.rd @[el2_dec_decode_ctl.scala 351:47] - _T_113.bits.tag <= cam_in[0].bits.tag @[el2_dec_decode_ctl.scala 351:47] - _T_113.bits.wb <= cam_in[0].bits.wb @[el2_dec_decode_ctl.scala 351:47] - _T_113.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 351:47] - cam_raw[0].bits.rd <= _T_113.bits.rd @[el2_dec_decode_ctl.scala 351:15] - cam_raw[0].bits.tag <= _T_113.bits.tag @[el2_dec_decode_ctl.scala 351:15] - cam_raw[0].bits.wb <= _T_113.bits.wb @[el2_dec_decode_ctl.scala 351:15] - cam_raw[0].valid <= _T_113.valid @[el2_dec_decode_ctl.scala 351:15] - node _T_114 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[el2_dec_decode_ctl.scala 352:46] - node _T_115 = and(_T_114, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 352:71] - nonblock_load_write[0] <= _T_115 @[el2_dec_decode_ctl.scala 352:28] - node _T_116 = eq(cam_inv_reset_tag, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 325:66] - node _T_117 = and(io.lsu_nonblock_load_inv_r, _T_116) @[el2_dec_decode_ctl.scala 325:45] - node _T_118 = and(_T_117, cam[1].valid) @[el2_dec_decode_ctl.scala 325:87] - cam_inv_reset_val[1] <= _T_118 @[el2_dec_decode_ctl.scala 325:26] - node _T_119 = eq(cam_data_reset_tag, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 326:67] - node _T_120 = and(cam_data_reset, _T_119) @[el2_dec_decode_ctl.scala 326:45] - node _T_121 = and(_T_120, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 326:88] - cam_data_reset_val[1] <= _T_121 @[el2_dec_decode_ctl.scala 326:27] - wire _T_122 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 327:28] - _T_122.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_122.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_122.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_122.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - cam_in[1].bits.rd <= _T_122.bits.rd @[el2_dec_decode_ctl.scala 327:14] - cam_in[1].bits.tag <= _T_122.bits.tag @[el2_dec_decode_ctl.scala 327:14] - cam_in[1].bits.wb <= _T_122.bits.wb @[el2_dec_decode_ctl.scala 327:14] - cam_in[1].valid <= _T_122.valid @[el2_dec_decode_ctl.scala 327:14] - cam[1].bits.rd <= cam_raw[1].bits.rd @[el2_dec_decode_ctl.scala 328:11] - cam[1].bits.tag <= cam_raw[1].bits.tag @[el2_dec_decode_ctl.scala 328:11] - cam[1].bits.wb <= cam_raw[1].bits.wb @[el2_dec_decode_ctl.scala 328:11] - cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 328:11] - node _T_123 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 330:32] - when _T_123 : @[el2_dec_decode_ctl.scala 330:39] - cam[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] - skip @[el2_dec_decode_ctl.scala 330:39] - node _T_124 = bits(cam_wen, 1, 1) @[el2_dec_decode_ctl.scala 333:17] - node _T_125 = bits(_T_124, 0, 0) @[el2_dec_decode_ctl.scala 333:21] - when _T_125 : @[el2_dec_decode_ctl.scala 333:28] - cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] - cam_in[1].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:32] - cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:32] - cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:32] - skip @[el2_dec_decode_ctl.scala 333:28] - else : @[el2_dec_decode_ctl.scala 338:131] - node _T_126 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 338:37] - node _T_127 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] - node _T_128 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 338:85] - node _T_129 = and(_T_127, _T_128) @[el2_dec_decode_ctl.scala 338:64] - node _T_130 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 338:123] - node _T_131 = and(_T_129, _T_130) @[el2_dec_decode_ctl.scala 338:105] - node _T_132 = or(_T_126, _T_131) @[el2_dec_decode_ctl.scala 338:44] - when _T_132 : @[el2_dec_decode_ctl.scala 338:131] - cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] - skip @[el2_dec_decode_ctl.scala 338:131] - else : @[el2_dec_decode_ctl.scala 340:16] - cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 341:22] - cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 341:22] - cam_in[1].bits.wb <= cam[1].bits.wb @[el2_dec_decode_ctl.scala 341:22] - cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 341:22] - skip @[el2_dec_decode_ctl.scala 340:16] - node _T_133 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] - node _T_134 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 343:79] - node _T_135 = and(_T_133, _T_134) @[el2_dec_decode_ctl.scala 343:44] - node _T_136 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:115] - node _T_137 = and(_T_135, _T_136) @[el2_dec_decode_ctl.scala 343:100] - when _T_137 : @[el2_dec_decode_ctl.scala 343:122] - cam_in[1].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:25] - skip @[el2_dec_decode_ctl.scala 343:122] - when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] - cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] - skip @[el2_dec_decode_ctl.scala 347:32] - wire _T_138 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 351:70] - _T_138.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_138.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_138.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_138.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - reg _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_138)) @[el2_dec_decode_ctl.scala 351:47] - _T_139.bits.rd <= cam_in[1].bits.rd @[el2_dec_decode_ctl.scala 351:47] - _T_139.bits.tag <= cam_in[1].bits.tag @[el2_dec_decode_ctl.scala 351:47] - _T_139.bits.wb <= cam_in[1].bits.wb @[el2_dec_decode_ctl.scala 351:47] - _T_139.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 351:47] - cam_raw[1].bits.rd <= _T_139.bits.rd @[el2_dec_decode_ctl.scala 351:15] - cam_raw[1].bits.tag <= _T_139.bits.tag @[el2_dec_decode_ctl.scala 351:15] - cam_raw[1].bits.wb <= _T_139.bits.wb @[el2_dec_decode_ctl.scala 351:15] - cam_raw[1].valid <= _T_139.valid @[el2_dec_decode_ctl.scala 351:15] - node _T_140 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[el2_dec_decode_ctl.scala 352:46] - node _T_141 = and(_T_140, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 352:71] - nonblock_load_write[1] <= _T_141 @[el2_dec_decode_ctl.scala 352:28] - node _T_142 = eq(cam_inv_reset_tag, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 325:66] - node _T_143 = and(io.lsu_nonblock_load_inv_r, _T_142) @[el2_dec_decode_ctl.scala 325:45] - node _T_144 = and(_T_143, cam[2].valid) @[el2_dec_decode_ctl.scala 325:87] - cam_inv_reset_val[2] <= _T_144 @[el2_dec_decode_ctl.scala 325:26] - node _T_145 = eq(cam_data_reset_tag, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 326:67] - node _T_146 = and(cam_data_reset, _T_145) @[el2_dec_decode_ctl.scala 326:45] - node _T_147 = and(_T_146, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 326:88] - cam_data_reset_val[2] <= _T_147 @[el2_dec_decode_ctl.scala 326:27] - wire _T_148 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 327:28] - _T_148.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_148.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_148.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_148.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - cam_in[2].bits.rd <= _T_148.bits.rd @[el2_dec_decode_ctl.scala 327:14] - cam_in[2].bits.tag <= _T_148.bits.tag @[el2_dec_decode_ctl.scala 327:14] - cam_in[2].bits.wb <= _T_148.bits.wb @[el2_dec_decode_ctl.scala 327:14] - cam_in[2].valid <= _T_148.valid @[el2_dec_decode_ctl.scala 327:14] - cam[2].bits.rd <= cam_raw[2].bits.rd @[el2_dec_decode_ctl.scala 328:11] - cam[2].bits.tag <= cam_raw[2].bits.tag @[el2_dec_decode_ctl.scala 328:11] - cam[2].bits.wb <= cam_raw[2].bits.wb @[el2_dec_decode_ctl.scala 328:11] - cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 328:11] - node _T_149 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 330:32] - when _T_149 : @[el2_dec_decode_ctl.scala 330:39] - cam[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] - skip @[el2_dec_decode_ctl.scala 330:39] - node _T_150 = bits(cam_wen, 2, 2) @[el2_dec_decode_ctl.scala 333:17] - node _T_151 = bits(_T_150, 0, 0) @[el2_dec_decode_ctl.scala 333:21] - when _T_151 : @[el2_dec_decode_ctl.scala 333:28] - cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] - cam_in[2].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:32] - cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:32] - cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:32] - skip @[el2_dec_decode_ctl.scala 333:28] - else : @[el2_dec_decode_ctl.scala 338:131] - node _T_152 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 338:37] - node _T_153 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] - node _T_154 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 338:85] - node _T_155 = and(_T_153, _T_154) @[el2_dec_decode_ctl.scala 338:64] - node _T_156 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 338:123] - node _T_157 = and(_T_155, _T_156) @[el2_dec_decode_ctl.scala 338:105] - node _T_158 = or(_T_152, _T_157) @[el2_dec_decode_ctl.scala 338:44] - when _T_158 : @[el2_dec_decode_ctl.scala 338:131] - cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] - skip @[el2_dec_decode_ctl.scala 338:131] - else : @[el2_dec_decode_ctl.scala 340:16] - cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 341:22] - cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 341:22] - cam_in[2].bits.wb <= cam[2].bits.wb @[el2_dec_decode_ctl.scala 341:22] - cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 341:22] - skip @[el2_dec_decode_ctl.scala 340:16] - node _T_159 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] - node _T_160 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 343:79] - node _T_161 = and(_T_159, _T_160) @[el2_dec_decode_ctl.scala 343:44] - node _T_162 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:115] - node _T_163 = and(_T_161, _T_162) @[el2_dec_decode_ctl.scala 343:100] - when _T_163 : @[el2_dec_decode_ctl.scala 343:122] - cam_in[2].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:25] - skip @[el2_dec_decode_ctl.scala 343:122] - when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] - cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] - skip @[el2_dec_decode_ctl.scala 347:32] - wire _T_164 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 351:70] - _T_164.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_164.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_164.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_164.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - reg _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_164)) @[el2_dec_decode_ctl.scala 351:47] - _T_165.bits.rd <= cam_in[2].bits.rd @[el2_dec_decode_ctl.scala 351:47] - _T_165.bits.tag <= cam_in[2].bits.tag @[el2_dec_decode_ctl.scala 351:47] - _T_165.bits.wb <= cam_in[2].bits.wb @[el2_dec_decode_ctl.scala 351:47] - _T_165.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 351:47] - cam_raw[2].bits.rd <= _T_165.bits.rd @[el2_dec_decode_ctl.scala 351:15] - cam_raw[2].bits.tag <= _T_165.bits.tag @[el2_dec_decode_ctl.scala 351:15] - cam_raw[2].bits.wb <= _T_165.bits.wb @[el2_dec_decode_ctl.scala 351:15] - cam_raw[2].valid <= _T_165.valid @[el2_dec_decode_ctl.scala 351:15] - node _T_166 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[el2_dec_decode_ctl.scala 352:46] - node _T_167 = and(_T_166, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 352:71] - nonblock_load_write[2] <= _T_167 @[el2_dec_decode_ctl.scala 352:28] - node _T_168 = eq(cam_inv_reset_tag, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 325:66] - node _T_169 = and(io.lsu_nonblock_load_inv_r, _T_168) @[el2_dec_decode_ctl.scala 325:45] - node _T_170 = and(_T_169, cam[3].valid) @[el2_dec_decode_ctl.scala 325:87] - cam_inv_reset_val[3] <= _T_170 @[el2_dec_decode_ctl.scala 325:26] - node _T_171 = eq(cam_data_reset_tag, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 326:67] - node _T_172 = and(cam_data_reset, _T_171) @[el2_dec_decode_ctl.scala 326:45] - node _T_173 = and(_T_172, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 326:88] - cam_data_reset_val[3] <= _T_173 @[el2_dec_decode_ctl.scala 326:27] - wire _T_174 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 327:28] - _T_174.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_174.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_174.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_174.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - cam_in[3].bits.rd <= _T_174.bits.rd @[el2_dec_decode_ctl.scala 327:14] - cam_in[3].bits.tag <= _T_174.bits.tag @[el2_dec_decode_ctl.scala 327:14] - cam_in[3].bits.wb <= _T_174.bits.wb @[el2_dec_decode_ctl.scala 327:14] - cam_in[3].valid <= _T_174.valid @[el2_dec_decode_ctl.scala 327:14] - cam[3].bits.rd <= cam_raw[3].bits.rd @[el2_dec_decode_ctl.scala 328:11] - cam[3].bits.tag <= cam_raw[3].bits.tag @[el2_dec_decode_ctl.scala 328:11] - cam[3].bits.wb <= cam_raw[3].bits.wb @[el2_dec_decode_ctl.scala 328:11] - cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 328:11] - node _T_175 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 330:32] - when _T_175 : @[el2_dec_decode_ctl.scala 330:39] - cam[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] - skip @[el2_dec_decode_ctl.scala 330:39] - node _T_176 = bits(cam_wen, 3, 3) @[el2_dec_decode_ctl.scala 333:17] - node _T_177 = bits(_T_176, 0, 0) @[el2_dec_decode_ctl.scala 333:21] - when _T_177 : @[el2_dec_decode_ctl.scala 333:28] - cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] - cam_in[3].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:32] - cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:32] - cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:32] - skip @[el2_dec_decode_ctl.scala 333:28] - else : @[el2_dec_decode_ctl.scala 338:131] - node _T_178 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 338:37] - node _T_179 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] - node _T_180 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 338:85] - node _T_181 = and(_T_179, _T_180) @[el2_dec_decode_ctl.scala 338:64] - node _T_182 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 338:123] - node _T_183 = and(_T_181, _T_182) @[el2_dec_decode_ctl.scala 338:105] - node _T_184 = or(_T_178, _T_183) @[el2_dec_decode_ctl.scala 338:44] - when _T_184 : @[el2_dec_decode_ctl.scala 338:131] - cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] - skip @[el2_dec_decode_ctl.scala 338:131] - else : @[el2_dec_decode_ctl.scala 340:16] - cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 341:22] - cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 341:22] - cam_in[3].bits.wb <= cam[3].bits.wb @[el2_dec_decode_ctl.scala 341:22] - cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 341:22] - skip @[el2_dec_decode_ctl.scala 340:16] - node _T_185 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] - node _T_186 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 343:79] - node _T_187 = and(_T_185, _T_186) @[el2_dec_decode_ctl.scala 343:44] - node _T_188 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:115] - node _T_189 = and(_T_187, _T_188) @[el2_dec_decode_ctl.scala 343:100] - when _T_189 : @[el2_dec_decode_ctl.scala 343:122] - cam_in[3].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:25] - skip @[el2_dec_decode_ctl.scala 343:122] - when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] - cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] - skip @[el2_dec_decode_ctl.scala 347:32] - wire _T_190 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 351:70] - _T_190.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_190.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_190.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_190.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - reg _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_190)) @[el2_dec_decode_ctl.scala 351:47] - _T_191.bits.rd <= cam_in[3].bits.rd @[el2_dec_decode_ctl.scala 351:47] - _T_191.bits.tag <= cam_in[3].bits.tag @[el2_dec_decode_ctl.scala 351:47] - _T_191.bits.wb <= cam_in[3].bits.wb @[el2_dec_decode_ctl.scala 351:47] - _T_191.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 351:47] - cam_raw[3].bits.rd <= _T_191.bits.rd @[el2_dec_decode_ctl.scala 351:15] - cam_raw[3].bits.tag <= _T_191.bits.tag @[el2_dec_decode_ctl.scala 351:15] - cam_raw[3].bits.wb <= _T_191.bits.wb @[el2_dec_decode_ctl.scala 351:15] - cam_raw[3].valid <= _T_191.valid @[el2_dec_decode_ctl.scala 351:15] - node _T_192 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[el2_dec_decode_ctl.scala 352:46] - node _T_193 = and(_T_192, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 352:71] - nonblock_load_write[3] <= _T_193 @[el2_dec_decode_ctl.scala 352:28] - io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 355:29] - node _T_194 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 357:49] - node nonblock_load_cancel = and(_T_194, i0_wen_r) @[el2_dec_decode_ctl.scala 357:81] - node _T_195 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 358:95] - node _T_196 = or(_T_195, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 358:95] - node _T_197 = or(_T_196, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 358:95] - node _T_198 = bits(_T_197, 0, 0) @[el2_dec_decode_ctl.scala 358:99] - node _T_199 = and(io.lsu_nonblock_load_data_valid, _T_198) @[el2_dec_decode_ctl.scala 358:64] - node _T_200 = eq(nonblock_load_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 358:109] - node _T_201 = and(_T_199, _T_200) @[el2_dec_decode_ctl.scala 358:106] - io.dec_nonblock_load_wen <= _T_201 @[el2_dec_decode_ctl.scala 358:28] - node _T_202 = eq(nonblock_load_rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:54] - node _T_203 = and(_T_202, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 359:66] - node _T_204 = and(_T_203, io.dec_i0_rs1_en_d) @[el2_dec_decode_ctl.scala 359:97] - node _T_205 = eq(nonblock_load_rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:137] - node _T_206 = and(_T_205, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 359:149] - node _T_207 = and(_T_206, io.dec_i0_rs2_en_d) @[el2_dec_decode_ctl.scala 359:180] - node i0_nonblock_boundary_stall = or(_T_204, _T_207) @[el2_dec_decode_ctl.scala 359:118] - i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 361:26] - node _T_208 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] - node _T_209 = mux(_T_208, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_210 = and(_T_209, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 363:88] - node _T_211 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 363:126] - node _T_212 = eq(cam[0].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:159] - node _T_213 = and(_T_211, _T_212) @[el2_dec_decode_ctl.scala 363:141] - node _T_214 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 363:192] - node _T_215 = eq(cam[0].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:225] - node _T_216 = and(_T_214, _T_215) @[el2_dec_decode_ctl.scala 363:207] - node _T_217 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] - node _T_218 = mux(_T_217, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_219 = and(_T_218, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 363:88] - node _T_220 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 363:126] - node _T_221 = eq(cam[1].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:159] - node _T_222 = and(_T_220, _T_221) @[el2_dec_decode_ctl.scala 363:141] - node _T_223 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 363:192] - node _T_224 = eq(cam[1].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:225] - node _T_225 = and(_T_223, _T_224) @[el2_dec_decode_ctl.scala 363:207] - node _T_226 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] - node _T_227 = mux(_T_226, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_228 = and(_T_227, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 363:88] - node _T_229 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 363:126] - node _T_230 = eq(cam[2].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:159] - node _T_231 = and(_T_229, _T_230) @[el2_dec_decode_ctl.scala 363:141] - node _T_232 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 363:192] - node _T_233 = eq(cam[2].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:225] - node _T_234 = and(_T_232, _T_233) @[el2_dec_decode_ctl.scala 363:207] - node _T_235 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] - node _T_236 = mux(_T_235, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_237 = and(_T_236, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 363:88] - node _T_238 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 363:126] - node _T_239 = eq(cam[3].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:159] - node _T_240 = and(_T_238, _T_239) @[el2_dec_decode_ctl.scala 363:141] - node _T_241 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 363:192] - node _T_242 = eq(cam[3].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:225] - node _T_243 = and(_T_241, _T_242) @[el2_dec_decode_ctl.scala 363:207] - node _T_244 = or(_T_210, _T_219) @[el2_dec_decode_ctl.scala 364:69] - node _T_245 = or(_T_244, _T_228) @[el2_dec_decode_ctl.scala 364:69] - node waddr = or(_T_245, _T_237) @[el2_dec_decode_ctl.scala 364:69] - node _T_246 = or(_T_213, _T_222) @[el2_dec_decode_ctl.scala 364:102] - node _T_247 = or(_T_246, _T_231) @[el2_dec_decode_ctl.scala 364:102] - node ld_stall_1 = or(_T_247, _T_240) @[el2_dec_decode_ctl.scala 364:102] - node _T_248 = or(_T_216, _T_225) @[el2_dec_decode_ctl.scala 364:134] - node _T_249 = or(_T_248, _T_234) @[el2_dec_decode_ctl.scala 364:134] - node ld_stall_2 = or(_T_249, _T_243) @[el2_dec_decode_ctl.scala 364:134] - io.dec_nonblock_load_waddr <= waddr @[el2_dec_decode_ctl.scala 365:29] - node _T_250 = or(ld_stall_1, ld_stall_2) @[el2_dec_decode_ctl.scala 366:38] - node _T_251 = or(_T_250, i0_nonblock_boundary_stall) @[el2_dec_decode_ctl.scala 366:51] - i0_nonblock_load_stall <= _T_251 @[el2_dec_decode_ctl.scala 366:25] - node _T_252 = eq(i0_predict_br, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 375:34] - node i0_br_unpred = and(i0_dp.jal, _T_252) @[el2_dec_decode_ctl.scala 375:32] - node _T_253 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] - node _T_254 = mux(_T_253, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_255 = and(csr_read, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 387:16] - node _T_256 = bits(_T_255, 0, 0) @[el2_dec_decode_ctl.scala 387:30] - node _T_257 = eq(csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 388:6] - node _T_258 = and(_T_257, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 388:16] - node _T_259 = bits(_T_258, 0, 0) @[el2_dec_decode_ctl.scala 388:30] - node _T_260 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 389:18] - node _T_261 = and(csr_read, _T_260) @[el2_dec_decode_ctl.scala 389:16] - node _T_262 = bits(_T_261, 0, 0) @[el2_dec_decode_ctl.scala 389:30] - node _T_263 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] - node _T_264 = mux(i0_dp.load, UInt<4>("h02"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(i0_dp.store, UInt<4>("h03"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_262, UInt<4>("h05"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_259, UInt<4>("h06"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_256, UInt<4>("h07"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_269) @[Mux.scala 98:16] - node _T_271 = mux(i0_dp.ecall, UInt<4>("h09"), _T_270) @[Mux.scala 98:16] - node _T_272 = mux(i0_dp.fence, UInt<4>("h0a"), _T_271) @[Mux.scala 98:16] - node _T_273 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_272) @[Mux.scala 98:16] - node _T_274 = mux(i0_dp.mret, UInt<4>("h0c"), _T_273) @[Mux.scala 98:16] - node _T_275 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_274) @[Mux.scala 98:16] - node _T_276 = mux(i0_dp.jal, UInt<4>("h0e"), _T_275) @[Mux.scala 98:16] - node _T_277 = and(_T_254, _T_276) @[el2_dec_decode_ctl.scala 379:49] - d_t.pmu_i0_itype <= _T_277 @[el2_dec_decode_ctl.scala 379:21] - inst i0_dec of el2_dec_dec_ctl @[el2_dec_decode_ctl.scala 396:22] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 319:56] + node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45] + node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:87] + cam_inv_reset_val[0] <= _T_93 @[el2_dec_decode_ctl.scala 321:26] + node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_95 = and(cam_data_reset, _T_94) @[el2_dec_decode_ctl.scala 322:45] + node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:88] + cam_data_reset_val[0] <= _T_96 @[el2_dec_decode_ctl.scala 322:27] + wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] + _T_97.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + cam_in[0].bits.rd <= _T_97.bits.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].bits.tag <= _T_97.bits.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].bits.wb <= _T_97.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].valid <= _T_97.valid @[el2_dec_decode_ctl.scala 323:14] + cam[0].bits.rd <= cam_raw[0].bits.rd @[el2_dec_decode_ctl.scala 324:11] + cam[0].bits.tag <= cam_raw[0].bits.tag @[el2_dec_decode_ctl.scala 324:11] + cam[0].bits.wb <= cam_raw[0].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 324:11] + node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 326:32] + when _T_98 : @[el2_dec_decode_ctl.scala 326:39] + cam[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20] + skip @[el2_dec_decode_ctl.scala 326:39] + node _T_99 = bits(cam_wen, 0, 0) @[el2_dec_decode_ctl.scala 329:17] + node _T_100 = bits(_T_99, 0, 0) @[el2_dec_decode_ctl.scala 329:21] + when _T_100 : @[el2_dec_decode_ctl.scala 329:28] + cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] + cam_in[0].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] + cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] + cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + skip @[el2_dec_decode_ctl.scala 329:28] + else : @[el2_dec_decode_ctl.scala 334:131] + node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37] + node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] + node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64] + node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] + node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:105] + node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44] + when _T_107 : @[el2_dec_decode_ctl.scala 334:131] + cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] + skip @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 336:16] + cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].bits.wb <= cam[0].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 337:22] + skip @[el2_dec_decode_ctl.scala 336:16] + node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] + node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_110 = and(_T_108, _T_109) @[el2_dec_decode_ctl.scala 339:44] + node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] + node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:100] + when _T_112 : @[el2_dec_decode_ctl.scala 339:122] + cam_in[0].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] + skip @[el2_dec_decode_ctl.scala 339:122] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] + cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] + skip @[el2_dec_decode_ctl.scala 343:32] + wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] + _T_113.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47] + _T_114.bits.rd <= cam_in[0].bits.rd @[el2_dec_decode_ctl.scala 347:47] + _T_114.bits.tag <= cam_in[0].bits.tag @[el2_dec_decode_ctl.scala 347:47] + _T_114.bits.wb <= cam_in[0].bits.wb @[el2_dec_decode_ctl.scala 347:47] + _T_114.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 347:47] + cam_raw[0].bits.rd <= _T_114.bits.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].bits.tag <= _T_114.bits.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].bits.wb <= _T_114.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].valid <= _T_114.valid @[el2_dec_decode_ctl.scala 347:15] + node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:71] + nonblock_load_write[0] <= _T_116 @[el2_dec_decode_ctl.scala 348:28] + node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_118 = and(io.lsu_nonblock_load_inv_r, _T_117) @[el2_dec_decode_ctl.scala 321:45] + node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:87] + cam_inv_reset_val[1] <= _T_119 @[el2_dec_decode_ctl.scala 321:26] + node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_121 = and(cam_data_reset, _T_120) @[el2_dec_decode_ctl.scala 322:45] + node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:88] + cam_data_reset_val[1] <= _T_122 @[el2_dec_decode_ctl.scala 322:27] + wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] + _T_123.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + cam_in[1].bits.rd <= _T_123.bits.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].bits.tag <= _T_123.bits.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].bits.wb <= _T_123.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].valid <= _T_123.valid @[el2_dec_decode_ctl.scala 323:14] + cam[1].bits.rd <= cam_raw[1].bits.rd @[el2_dec_decode_ctl.scala 324:11] + cam[1].bits.tag <= cam_raw[1].bits.tag @[el2_dec_decode_ctl.scala 324:11] + cam[1].bits.wb <= cam_raw[1].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 324:11] + node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 326:32] + when _T_124 : @[el2_dec_decode_ctl.scala 326:39] + cam[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20] + skip @[el2_dec_decode_ctl.scala 326:39] + node _T_125 = bits(cam_wen, 1, 1) @[el2_dec_decode_ctl.scala 329:17] + node _T_126 = bits(_T_125, 0, 0) @[el2_dec_decode_ctl.scala 329:21] + when _T_126 : @[el2_dec_decode_ctl.scala 329:28] + cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] + cam_in[1].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] + cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] + cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + skip @[el2_dec_decode_ctl.scala 329:28] + else : @[el2_dec_decode_ctl.scala 334:131] + node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37] + node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] + node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64] + node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] + node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:105] + node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44] + when _T_133 : @[el2_dec_decode_ctl.scala 334:131] + cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] + skip @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 336:16] + cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].bits.wb <= cam[1].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 337:22] + skip @[el2_dec_decode_ctl.scala 336:16] + node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] + node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_136 = and(_T_134, _T_135) @[el2_dec_decode_ctl.scala 339:44] + node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] + node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:100] + when _T_138 : @[el2_dec_decode_ctl.scala 339:122] + cam_in[1].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] + skip @[el2_dec_decode_ctl.scala 339:122] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] + cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] + skip @[el2_dec_decode_ctl.scala 343:32] + wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] + _T_139.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47] + _T_140.bits.rd <= cam_in[1].bits.rd @[el2_dec_decode_ctl.scala 347:47] + _T_140.bits.tag <= cam_in[1].bits.tag @[el2_dec_decode_ctl.scala 347:47] + _T_140.bits.wb <= cam_in[1].bits.wb @[el2_dec_decode_ctl.scala 347:47] + _T_140.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 347:47] + cam_raw[1].bits.rd <= _T_140.bits.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].bits.tag <= _T_140.bits.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].bits.wb <= _T_140.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].valid <= _T_140.valid @[el2_dec_decode_ctl.scala 347:15] + node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:71] + nonblock_load_write[1] <= _T_142 @[el2_dec_decode_ctl.scala 348:28] + node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_144 = and(io.lsu_nonblock_load_inv_r, _T_143) @[el2_dec_decode_ctl.scala 321:45] + node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:87] + cam_inv_reset_val[2] <= _T_145 @[el2_dec_decode_ctl.scala 321:26] + node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_147 = and(cam_data_reset, _T_146) @[el2_dec_decode_ctl.scala 322:45] + node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:88] + cam_data_reset_val[2] <= _T_148 @[el2_dec_decode_ctl.scala 322:27] + wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] + _T_149.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + cam_in[2].bits.rd <= _T_149.bits.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].bits.tag <= _T_149.bits.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].bits.wb <= _T_149.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].valid <= _T_149.valid @[el2_dec_decode_ctl.scala 323:14] + cam[2].bits.rd <= cam_raw[2].bits.rd @[el2_dec_decode_ctl.scala 324:11] + cam[2].bits.tag <= cam_raw[2].bits.tag @[el2_dec_decode_ctl.scala 324:11] + cam[2].bits.wb <= cam_raw[2].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 324:11] + node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 326:32] + when _T_150 : @[el2_dec_decode_ctl.scala 326:39] + cam[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20] + skip @[el2_dec_decode_ctl.scala 326:39] + node _T_151 = bits(cam_wen, 2, 2) @[el2_dec_decode_ctl.scala 329:17] + node _T_152 = bits(_T_151, 0, 0) @[el2_dec_decode_ctl.scala 329:21] + when _T_152 : @[el2_dec_decode_ctl.scala 329:28] + cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] + cam_in[2].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] + cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] + cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + skip @[el2_dec_decode_ctl.scala 329:28] + else : @[el2_dec_decode_ctl.scala 334:131] + node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37] + node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] + node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64] + node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] + node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:105] + node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44] + when _T_159 : @[el2_dec_decode_ctl.scala 334:131] + cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] + skip @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 336:16] + cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].bits.wb <= cam[2].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 337:22] + skip @[el2_dec_decode_ctl.scala 336:16] + node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] + node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_162 = and(_T_160, _T_161) @[el2_dec_decode_ctl.scala 339:44] + node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] + node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:100] + when _T_164 : @[el2_dec_decode_ctl.scala 339:122] + cam_in[2].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] + skip @[el2_dec_decode_ctl.scala 339:122] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] + cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] + skip @[el2_dec_decode_ctl.scala 343:32] + wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] + _T_165.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47] + _T_166.bits.rd <= cam_in[2].bits.rd @[el2_dec_decode_ctl.scala 347:47] + _T_166.bits.tag <= cam_in[2].bits.tag @[el2_dec_decode_ctl.scala 347:47] + _T_166.bits.wb <= cam_in[2].bits.wb @[el2_dec_decode_ctl.scala 347:47] + _T_166.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 347:47] + cam_raw[2].bits.rd <= _T_166.bits.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].bits.tag <= _T_166.bits.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].bits.wb <= _T_166.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].valid <= _T_166.valid @[el2_dec_decode_ctl.scala 347:15] + node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:71] + nonblock_load_write[2] <= _T_168 @[el2_dec_decode_ctl.scala 348:28] + node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_170 = and(io.lsu_nonblock_load_inv_r, _T_169) @[el2_dec_decode_ctl.scala 321:45] + node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:87] + cam_inv_reset_val[3] <= _T_171 @[el2_dec_decode_ctl.scala 321:26] + node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_173 = and(cam_data_reset, _T_172) @[el2_dec_decode_ctl.scala 322:45] + node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:88] + cam_data_reset_val[3] <= _T_174 @[el2_dec_decode_ctl.scala 322:27] + wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] + _T_175.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + cam_in[3].bits.rd <= _T_175.bits.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].bits.tag <= _T_175.bits.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].bits.wb <= _T_175.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].valid <= _T_175.valid @[el2_dec_decode_ctl.scala 323:14] + cam[3].bits.rd <= cam_raw[3].bits.rd @[el2_dec_decode_ctl.scala 324:11] + cam[3].bits.tag <= cam_raw[3].bits.tag @[el2_dec_decode_ctl.scala 324:11] + cam[3].bits.wb <= cam_raw[3].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 324:11] + node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 326:32] + when _T_176 : @[el2_dec_decode_ctl.scala 326:39] + cam[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20] + skip @[el2_dec_decode_ctl.scala 326:39] + node _T_177 = bits(cam_wen, 3, 3) @[el2_dec_decode_ctl.scala 329:17] + node _T_178 = bits(_T_177, 0, 0) @[el2_dec_decode_ctl.scala 329:21] + when _T_178 : @[el2_dec_decode_ctl.scala 329:28] + cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] + cam_in[3].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] + cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] + cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + skip @[el2_dec_decode_ctl.scala 329:28] + else : @[el2_dec_decode_ctl.scala 334:131] + node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37] + node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] + node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64] + node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] + node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:105] + node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44] + when _T_185 : @[el2_dec_decode_ctl.scala 334:131] + cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] + skip @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 336:16] + cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].bits.wb <= cam[3].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 337:22] + skip @[el2_dec_decode_ctl.scala 336:16] + node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] + node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_188 = and(_T_186, _T_187) @[el2_dec_decode_ctl.scala 339:44] + node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] + node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:100] + when _T_190 : @[el2_dec_decode_ctl.scala 339:122] + cam_in[3].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] + skip @[el2_dec_decode_ctl.scala 339:122] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] + cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] + skip @[el2_dec_decode_ctl.scala 343:32] + wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] + _T_191.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47] + _T_192.bits.rd <= cam_in[3].bits.rd @[el2_dec_decode_ctl.scala 347:47] + _T_192.bits.tag <= cam_in[3].bits.tag @[el2_dec_decode_ctl.scala 347:47] + _T_192.bits.wb <= cam_in[3].bits.wb @[el2_dec_decode_ctl.scala 347:47] + _T_192.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 347:47] + cam_raw[3].bits.rd <= _T_192.bits.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].bits.tag <= _T_192.bits.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].bits.wb <= _T_192.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].valid <= _T_192.valid @[el2_dec_decode_ctl.scala 347:15] + node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:71] + nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28] + io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29] + node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:49] + node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:81] + node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 354:95] + node _T_197 = or(_T_196, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 354:95] + node _T_198 = or(_T_197, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 354:95] + node _T_199 = bits(_T_198, 0, 0) @[el2_dec_decode_ctl.scala 354:99] + node _T_200 = and(io.lsu_nonblock_load_data_valid, _T_199) @[el2_dec_decode_ctl.scala 354:64] + node _T_201 = eq(nonblock_load_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 354:109] + node _T_202 = and(_T_200, _T_201) @[el2_dec_decode_ctl.scala 354:106] + io.dec_nonblock_load_wen <= _T_202 @[el2_dec_decode_ctl.scala 354:28] + node _T_203 = eq(nonblock_load_rd, i0r.rs1) @[el2_dec_decode_ctl.scala 355:54] + node _T_204 = and(_T_203, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 355:66] + node _T_205 = and(_T_204, io.dec_i0_rs1_en_d) @[el2_dec_decode_ctl.scala 355:97] + node _T_206 = eq(nonblock_load_rd, i0r.rs2) @[el2_dec_decode_ctl.scala 355:137] + node _T_207 = and(_T_206, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 355:149] + node _T_208 = and(_T_207, io.dec_i0_rs2_en_d) @[el2_dec_decode_ctl.scala 355:180] + node i0_nonblock_boundary_stall = or(_T_205, _T_208) @[el2_dec_decode_ctl.scala 355:118] + i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 357:26] + node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] + node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_211 = and(_T_210, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:126] + node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] + node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:141] + node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:192] + node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] + node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:207] + node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] + node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_220 = and(_T_219, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:126] + node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] + node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:141] + node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:192] + node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] + node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:207] + node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] + node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_229 = and(_T_228, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:126] + node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] + node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:141] + node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:192] + node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] + node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:207] + node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] + node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_238 = and(_T_237, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:126] + node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] + node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:141] + node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:192] + node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] + node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:207] + node _T_245 = or(_T_211, _T_220) @[el2_dec_decode_ctl.scala 360:69] + node _T_246 = or(_T_245, _T_229) @[el2_dec_decode_ctl.scala 360:69] + node waddr = or(_T_246, _T_238) @[el2_dec_decode_ctl.scala 360:69] + node _T_247 = or(_T_214, _T_223) @[el2_dec_decode_ctl.scala 360:102] + node _T_248 = or(_T_247, _T_232) @[el2_dec_decode_ctl.scala 360:102] + node ld_stall_1 = or(_T_248, _T_241) @[el2_dec_decode_ctl.scala 360:102] + node _T_249 = or(_T_217, _T_226) @[el2_dec_decode_ctl.scala 360:134] + node _T_250 = or(_T_249, _T_235) @[el2_dec_decode_ctl.scala 360:134] + node ld_stall_2 = or(_T_250, _T_244) @[el2_dec_decode_ctl.scala 360:134] + io.dec_nonblock_load_waddr <= waddr @[el2_dec_decode_ctl.scala 361:29] + node _T_251 = or(ld_stall_1, ld_stall_2) @[el2_dec_decode_ctl.scala 362:38] + node _T_252 = or(_T_251, i0_nonblock_boundary_stall) @[el2_dec_decode_ctl.scala 362:51] + i0_nonblock_load_stall <= _T_252 @[el2_dec_decode_ctl.scala 362:25] + node _T_253 = eq(i0_predict_br, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 371:34] + node i0_br_unpred = and(i0_dp.jal, _T_253) @[el2_dec_decode_ctl.scala 371:32] + node _T_254 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] + node _T_255 = mux(_T_254, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_256 = and(csr_read, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 383:16] + node _T_257 = bits(_T_256, 0, 0) @[el2_dec_decode_ctl.scala 383:30] + node _T_258 = eq(csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 384:6] + node _T_259 = and(_T_258, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 384:16] + node _T_260 = bits(_T_259, 0, 0) @[el2_dec_decode_ctl.scala 384:30] + node _T_261 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 385:18] + node _T_262 = and(csr_read, _T_261) @[el2_dec_decode_ctl.scala 385:16] + node _T_263 = bits(_T_262, 0, 0) @[el2_dec_decode_ctl.scala 385:30] + node _T_264 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] + node _T_265 = mux(i0_dp.load, UInt<4>("h02"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(i0_dp.store, UInt<4>("h03"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_263, UInt<4>("h05"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_260, UInt<4>("h06"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_257, UInt<4>("h07"), _T_269) @[Mux.scala 98:16] + node _T_271 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_270) @[Mux.scala 98:16] + node _T_272 = mux(i0_dp.ecall, UInt<4>("h09"), _T_271) @[Mux.scala 98:16] + node _T_273 = mux(i0_dp.fence, UInt<4>("h0a"), _T_272) @[Mux.scala 98:16] + node _T_274 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_273) @[Mux.scala 98:16] + node _T_275 = mux(i0_dp.mret, UInt<4>("h0c"), _T_274) @[Mux.scala 98:16] + node _T_276 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_275) @[Mux.scala 98:16] + node _T_277 = mux(i0_dp.jal, UInt<4>("h0e"), _T_276) @[Mux.scala 98:16] + node _T_278 = and(_T_255, _T_277) @[el2_dec_decode_ctl.scala 375:49] + d_t.pmu_i0_itype <= _T_278 @[el2_dec_decode_ctl.scala 375:21] + inst i0_dec of el2_dec_dec_ctl @[el2_dec_decode_ctl.scala 392:22] i0_dec.clock <= clock i0_dec.reset <= reset - i0_dec.io.ins <= io.dec_i0_instr_d @[el2_dec_decode_ctl.scala 397:16] - i0_dp_raw.legal <= i0_dec.io.out.legal @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.fence <= i0_dec.io.out.fence @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rem <= i0_dec.io.out.rem @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.div <= i0_dec.io.out.div @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.low <= i0_dec.io.out.low @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.mul <= i0_dec.io.out.mul @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.mret <= i0_dec.io.out.mret @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.ecall <= i0_dec.io.out.ecall @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.postsync <= i0_dec.io.out.postsync @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.presync <= i0_dec.io.out.presync @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.word <= i0_dec.io.out.word @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.half <= i0_dec.io.out.half @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.by <= i0_dec.io.out.by @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.jal <= i0_dec.io.out.jal @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.blt <= i0_dec.io.out.blt @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.bge <= i0_dec.io.out.bge @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.bne <= i0_dec.io.out.bne @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.beq <= i0_dec.io.out.beq @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.condbr <= i0_dec.io.out.condbr @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.unsign <= i0_dec.io.out.unsign @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.slt <= i0_dec.io.out.slt @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.srl <= i0_dec.io.out.srl @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.sra <= i0_dec.io.out.sra @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.sll <= i0_dec.io.out.sll @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.lxor <= i0_dec.io.out.lxor @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.lor <= i0_dec.io.out.lor @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.land <= i0_dec.io.out.land @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.sub <= i0_dec.io.out.sub @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.add <= i0_dec.io.out.add @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.lsu <= i0_dec.io.out.lsu @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.store <= i0_dec.io.out.store @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.load <= i0_dec.io.out.load @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.pc <= i0_dec.io.out.pc @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rd <= i0_dec.io.out.rd @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.alu <= i0_dec.io.out.alu @[el2_dec_decode_ctl.scala 398:12] - reg _T_278 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 400:45] - _T_278 <= io.lsu_idle_any @[el2_dec_decode_ctl.scala 400:45] - lsu_idle <= _T_278 @[el2_dec_decode_ctl.scala 400:11] - node _T_279 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 403:73] - node _T_280 = and(leak1_i1_stall, _T_279) @[el2_dec_decode_ctl.scala 403:71] - node _T_281 = or(io.dec_tlu_flush_leak_one_r, _T_280) @[el2_dec_decode_ctl.scala 403:53] - leak1_i1_stall_in <= _T_281 @[el2_dec_decode_ctl.scala 403:21] - reg _T_282 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 404:56] - _T_282 <= leak1_i1_stall_in @[el2_dec_decode_ctl.scala 404:56] - leak1_i1_stall <= _T_282 @[el2_dec_decode_ctl.scala 404:21] - leak1_mode <= leak1_i1_stall @[el2_dec_decode_ctl.scala 405:14] - node _T_283 = and(io.dec_i0_decode_d, leak1_i1_stall) @[el2_dec_decode_ctl.scala 406:45] - node _T_284 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 406:83] - node _T_285 = and(leak1_i0_stall, _T_284) @[el2_dec_decode_ctl.scala 406:81] - node _T_286 = or(_T_283, _T_285) @[el2_dec_decode_ctl.scala 406:63] - leak1_i0_stall_in <= _T_286 @[el2_dec_decode_ctl.scala 406:21] - reg _T_287 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 407:56] - _T_287 <= leak1_i0_stall_in @[el2_dec_decode_ctl.scala 407:56] - leak1_i0_stall <= _T_287 @[el2_dec_decode_ctl.scala 407:21] - node _T_288 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 411:29] - node _T_289 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 411:36] - node _T_290 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 411:46] - node _T_291 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 411:53] - node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_293 = cat(_T_288, _T_289) @[Cat.scala 29:58] - node _T_294 = cat(_T_293, _T_290) @[Cat.scala 29:58] - node i0_pcall_imm = cat(_T_294, _T_292) @[Cat.scala 29:58] - node _T_295 = bits(i0_pcall_imm, 12, 12) @[el2_dec_decode_ctl.scala 412:46] - node _T_296 = bits(_T_295, 0, 0) @[el2_dec_decode_ctl.scala 412:51] - node _T_297 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 412:71] - node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[el2_dec_decode_ctl.scala 412:79] - node _T_299 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 412:104] - node _T_300 = eq(_T_299, UInt<8>("h00")) @[el2_dec_decode_ctl.scala 412:112] - node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[el2_dec_decode_ctl.scala 412:33] - node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 413:47] - node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 413:76] - node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 413:98] - node _T_304 = or(_T_302, _T_303) @[el2_dec_decode_ctl.scala 413:89] - node i0_pcall_case = and(_T_301, _T_304) @[el2_dec_decode_ctl.scala 413:65] - node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 414:47] - node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 414:76] - node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 414:98] - node _T_308 = or(_T_306, _T_307) @[el2_dec_decode_ctl.scala 414:89] - node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 414:67] - node i0_pja_case = and(_T_305, _T_309) @[el2_dec_decode_ctl.scala 414:65] - node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 415:38] - i0_pcall_raw <= _T_310 @[el2_dec_decode_ctl.scala 415:20] - node _T_311 = and(i0_dp.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 416:38] - i0_pcall <= _T_311 @[el2_dec_decode_ctl.scala 416:20] - node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 417:38] - i0_pja_raw <= _T_312 @[el2_dec_decode_ctl.scala 417:20] - node _T_313 = and(i0_dp.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 418:38] - i0_pja <= _T_313 @[el2_dec_decode_ctl.scala 418:20] - node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[el2_dec_decode_ctl.scala 419:41] - node _T_315 = bits(_T_314, 0, 0) @[el2_dec_decode_ctl.scala 419:55] - node _T_316 = bits(i0_pcall_imm, 12, 1) @[el2_dec_decode_ctl.scala 419:75] - node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 419:90] - node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[el2_dec_decode_ctl.scala 419:97] - node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[el2_dec_decode_ctl.scala 419:103] - node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[el2_dec_decode_ctl.scala 419:113] + i0_dec.io.ins <= io.dec_i0_instr_d @[el2_dec_decode_ctl.scala 393:16] + i0_dp_raw.legal <= i0_dec.io.out.legal @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.fence <= i0_dec.io.out.fence @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rem <= i0_dec.io.out.rem @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.div <= i0_dec.io.out.div @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.low <= i0_dec.io.out.low @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.mul <= i0_dec.io.out.mul @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.mret <= i0_dec.io.out.mret @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.ecall <= i0_dec.io.out.ecall @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.postsync <= i0_dec.io.out.postsync @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.presync <= i0_dec.io.out.presync @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.word <= i0_dec.io.out.word @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.half <= i0_dec.io.out.half @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.by <= i0_dec.io.out.by @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.jal <= i0_dec.io.out.jal @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.blt <= i0_dec.io.out.blt @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.bge <= i0_dec.io.out.bge @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.bne <= i0_dec.io.out.bne @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.beq <= i0_dec.io.out.beq @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.condbr <= i0_dec.io.out.condbr @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.unsign <= i0_dec.io.out.unsign @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.slt <= i0_dec.io.out.slt @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.srl <= i0_dec.io.out.srl @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.sra <= i0_dec.io.out.sra @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.sll <= i0_dec.io.out.sll @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.lxor <= i0_dec.io.out.lxor @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.lor <= i0_dec.io.out.lor @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.land <= i0_dec.io.out.land @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.sub <= i0_dec.io.out.sub @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.add <= i0_dec.io.out.add @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.lsu <= i0_dec.io.out.lsu @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.store <= i0_dec.io.out.store @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.load <= i0_dec.io.out.load @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.pc <= i0_dec.io.out.pc @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rd <= i0_dec.io.out.rd @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.alu <= i0_dec.io.out.alu @[el2_dec_decode_ctl.scala 394:12] + reg _T_279 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 396:45] + _T_279 <= io.lsu_idle_any @[el2_dec_decode_ctl.scala 396:45] + lsu_idle <= _T_279 @[el2_dec_decode_ctl.scala 396:11] + node _T_280 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 399:73] + node _T_281 = and(leak1_i1_stall, _T_280) @[el2_dec_decode_ctl.scala 399:71] + node _T_282 = or(io.dec_tlu_flush_leak_one_r, _T_281) @[el2_dec_decode_ctl.scala 399:53] + leak1_i1_stall_in <= _T_282 @[el2_dec_decode_ctl.scala 399:21] + reg _T_283 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 400:56] + _T_283 <= leak1_i1_stall_in @[el2_dec_decode_ctl.scala 400:56] + leak1_i1_stall <= _T_283 @[el2_dec_decode_ctl.scala 400:21] + leak1_mode <= leak1_i1_stall @[el2_dec_decode_ctl.scala 401:14] + node _T_284 = and(io.dec_i0_decode_d, leak1_i1_stall) @[el2_dec_decode_ctl.scala 402:45] + node _T_285 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 402:83] + node _T_286 = and(leak1_i0_stall, _T_285) @[el2_dec_decode_ctl.scala 402:81] + node _T_287 = or(_T_284, _T_286) @[el2_dec_decode_ctl.scala 402:63] + leak1_i0_stall_in <= _T_287 @[el2_dec_decode_ctl.scala 402:21] + reg _T_288 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 403:56] + _T_288 <= leak1_i0_stall_in @[el2_dec_decode_ctl.scala 403:56] + leak1_i0_stall <= _T_288 @[el2_dec_decode_ctl.scala 403:21] + node _T_289 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 407:29] + node _T_290 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 407:36] + node _T_291 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 407:46] + node _T_292 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 407:53] + node _T_293 = cat(_T_291, _T_292) @[Cat.scala 29:58] + node _T_294 = cat(_T_289, _T_290) @[Cat.scala 29:58] + node i0_pcall_imm = cat(_T_294, _T_293) @[Cat.scala 29:58] + node _T_295 = bits(i0_pcall_imm, 11, 11) @[el2_dec_decode_ctl.scala 408:46] + node _T_296 = bits(_T_295, 0, 0) @[el2_dec_decode_ctl.scala 408:51] + node _T_297 = bits(i0_pcall_imm, 19, 12) @[el2_dec_decode_ctl.scala 408:71] + node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[el2_dec_decode_ctl.scala 408:79] + node _T_299 = bits(i0_pcall_imm, 19, 12) @[el2_dec_decode_ctl.scala 408:104] + node _T_300 = eq(_T_299, UInt<8>("h00")) @[el2_dec_decode_ctl.scala 408:112] + node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[el2_dec_decode_ctl.scala 408:33] + node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 409:47] + node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 409:76] + node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 409:98] + node _T_304 = or(_T_302, _T_303) @[el2_dec_decode_ctl.scala 409:89] + node i0_pcall_case = and(_T_301, _T_304) @[el2_dec_decode_ctl.scala 409:65] + node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 410:47] + node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 410:76] + node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 410:98] + node _T_308 = or(_T_306, _T_307) @[el2_dec_decode_ctl.scala 410:89] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 410:67] + node i0_pja_case = and(_T_305, _T_309) @[el2_dec_decode_ctl.scala 410:65] + node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 411:38] + i0_pcall_raw <= _T_310 @[el2_dec_decode_ctl.scala 411:20] + node _T_311 = and(i0_dp.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 412:38] + i0_pcall <= _T_311 @[el2_dec_decode_ctl.scala 412:20] + node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 413:38] + i0_pja_raw <= _T_312 @[el2_dec_decode_ctl.scala 413:20] + node _T_313 = and(i0_dp.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 414:38] + i0_pja <= _T_313 @[el2_dec_decode_ctl.scala 414:20] + node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[el2_dec_decode_ctl.scala 415:41] + node _T_315 = bits(_T_314, 0, 0) @[el2_dec_decode_ctl.scala 415:55] + node _T_316 = bits(i0_pcall_imm, 11, 0) @[el2_dec_decode_ctl.scala 415:75] + node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 415:90] + node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[el2_dec_decode_ctl.scala 415:97] + node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[el2_dec_decode_ctl.scala 415:103] + node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[el2_dec_decode_ctl.scala 415:113] node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58] node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58] node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58] - node _T_324 = mux(_T_315, _T_316, _T_323) @[el2_dec_decode_ctl.scala 419:26] - i0_br_offset <= _T_324 @[el2_dec_decode_ctl.scala 419:20] - node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[el2_dec_decode_ctl.scala 421:37] - node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 421:65] - node _T_327 = and(_T_325, _T_326) @[el2_dec_decode_ctl.scala 421:55] - node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 421:89] - node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 421:111] - node _T_330 = or(_T_328, _T_329) @[el2_dec_decode_ctl.scala 421:101] - node i0_pret_case = and(_T_327, _T_330) @[el2_dec_decode_ctl.scala 421:79] - node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 422:32] - i0_pret_raw <= _T_331 @[el2_dec_decode_ctl.scala 422:15] - node _T_332 = and(i0_dp.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 423:32] - i0_pret <= _T_332 @[el2_dec_decode_ctl.scala 423:15] - node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:35] - node _T_334 = and(i0_dp.jal, _T_333) @[el2_dec_decode_ctl.scala 424:32] - node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:52] - node _T_336 = and(_T_334, _T_335) @[el2_dec_decode_ctl.scala 424:50] - node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:67] - node _T_338 = and(_T_336, _T_337) @[el2_dec_decode_ctl.scala 424:65] - i0_jal <= _T_338 @[el2_dec_decode_ctl.scala 424:15] - io.div_p.valid <= div_decode_d @[el2_dec_decode_ctl.scala 427:21] - io.div_p.bits.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 428:26] - io.div_p.bits.rem <= i0_dp.rem @[el2_dec_decode_ctl.scala 429:26] - io.mul_p.valid <= mul_decode_d @[el2_dec_decode_ctl.scala 431:21] - io.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[el2_dec_decode_ctl.scala 432:26] - io.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[el2_dec_decode_ctl.scala 433:26] - io.mul_p.bits.low <= i0_dp.low @[el2_dec_decode_ctl.scala 434:26] - reg _T_339 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 436:58] - _T_339 <= io.dec_tlu_flush_extint @[el2_dec_decode_ctl.scala 436:58] - io.dec_extint_stall <= _T_339 @[el2_dec_decode_ctl.scala 436:23] - wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.dma <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.dword <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.fast_int <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.dma <= _T_340.bits.dma @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.unsign <= _T_340.bits.unsign @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.store <= _T_340.bits.store @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.load <= _T_340.bits.load @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.dword <= _T_340.bits.dword @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.word <= _T_340.bits.word @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.half <= _T_340.bits.half @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.by <= _T_340.bits.by @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.valid <= _T_340.valid @[el2_dec_decode_ctl.scala 438:12] - when io.dec_extint_stall : @[el2_dec_decode_ctl.scala 439:29] - io.lsu_p.bits.load <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 440:29] - io.lsu_p.bits.word <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 441:29] - io.lsu_p.bits.fast_int <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 442:29] - io.lsu_p.valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 443:24] - skip @[el2_dec_decode_ctl.scala 439:29] - else : @[el2_dec_decode_ctl.scala 444:15] - io.lsu_p.valid <= lsu_decode_d @[el2_dec_decode_ctl.scala 445:35] - io.lsu_p.bits.load <= i0_dp.load @[el2_dec_decode_ctl.scala 446:40] - io.lsu_p.bits.store <= i0_dp.store @[el2_dec_decode_ctl.scala 447:40] - io.lsu_p.bits.by <= i0_dp.by @[el2_dec_decode_ctl.scala 448:40] - io.lsu_p.bits.half <= i0_dp.half @[el2_dec_decode_ctl.scala 449:40] - io.lsu_p.bits.word <= i0_dp.word @[el2_dec_decode_ctl.scala 450:40] - io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[el2_dec_decode_ctl.scala 451:40] - io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[el2_dec_decode_ctl.scala 452:40] - io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[el2_dec_decode_ctl.scala 453:40] - io.lsu_p.bits.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 454:40] - skip @[el2_dec_decode_ctl.scala 444:15] - io.dec_csr_ren_d <= i0_dp.csr_read @[el2_dec_decode_ctl.scala 458:21] - node _T_341 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 459:56] - node _T_342 = and(i0_dp.csr_read, _T_341) @[el2_dec_decode_ctl.scala 459:36] - csr_read <= _T_342 @[el2_dec_decode_ctl.scala 459:18] - node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 461:42] - node i0_csr_write = and(i0_dp.csr_write, _T_343) @[el2_dec_decode_ctl.scala 461:40] - node _T_344 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 462:61] - node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[el2_dec_decode_ctl.scala 462:41] - node _T_345 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 463:59] - node csr_set_d = and(i0_dp.csr_set, _T_345) @[el2_dec_decode_ctl.scala 463:39] - node _T_346 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 464:59] - node csr_write_d = and(i0_csr_write, _T_346) @[el2_dec_decode_ctl.scala 464:39] - node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 466:41] - node _T_348 = and(i0_csr_write, _T_347) @[el2_dec_decode_ctl.scala 466:39] - i0_csr_write_only_d <= _T_348 @[el2_dec_decode_ctl.scala 466:23] - node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[el2_dec_decode_ctl.scala 467:42] - node _T_350 = or(_T_349, i0_csr_write) @[el2_dec_decode_ctl.scala 467:58] - io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 467:24] - node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 470:30] - io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 470:24] - io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 471:23] - node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[el2_dec_decode_ctl.scala 475:39] - node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 475:53] - node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 475:51] - io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 475:20] - node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 478:50] - node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 478:85] - node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 478:64] - node _T_358 = and(_T_357, r_d.bits.csrwen) @[el2_dec_decode_ctl.scala 478:100] - node _T_359 = and(_T_358, r_d.valid) @[el2_dec_decode_ctl.scala 478:118] - node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 478:132] - node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 478:130] - io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 478:27] - reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 480:52] - csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 480:52] - reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 481:51] - csr_clr_x <= csr_clr_d @[el2_dec_decode_ctl.scala 481:51] - reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 482:51] - csr_set_x <= csr_set_d @[el2_dec_decode_ctl.scala 482:51] - reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 483:53] - csr_write_x <= csr_write_d @[el2_dec_decode_ctl.scala 483:53] - reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 484:51] - csr_imm_x <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 484:51] - node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 487:27] - node _T_363 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 487:48] - inst rvclkhdr of rvclkhdr_662 @[el2_lib.scala 508:23] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_363 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg csrimm_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - csrimm_x <= _T_362 @[el2_lib.scala 514:16] - node _T_364 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 488:62] - inst rvclkhdr_1 of rvclkhdr_663 @[el2_lib.scala 508:23] + node _T_324 = mux(_T_315, _T_316, _T_323) @[el2_dec_decode_ctl.scala 415:26] + i0_br_offset <= _T_324 @[el2_dec_decode_ctl.scala 415:20] + node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[el2_dec_decode_ctl.scala 417:37] + node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 417:65] + node _T_327 = and(_T_325, _T_326) @[el2_dec_decode_ctl.scala 417:55] + node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 417:89] + node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 417:111] + node _T_330 = or(_T_328, _T_329) @[el2_dec_decode_ctl.scala 417:101] + node i0_pret_case = and(_T_327, _T_330) @[el2_dec_decode_ctl.scala 417:79] + node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 418:32] + i0_pret_raw <= _T_331 @[el2_dec_decode_ctl.scala 418:15] + node _T_332 = and(i0_dp.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 419:32] + i0_pret <= _T_332 @[el2_dec_decode_ctl.scala 419:15] + node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 420:35] + node _T_334 = and(i0_dp.jal, _T_333) @[el2_dec_decode_ctl.scala 420:32] + node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 420:52] + node _T_336 = and(_T_334, _T_335) @[el2_dec_decode_ctl.scala 420:50] + node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 420:67] + node _T_338 = and(_T_336, _T_337) @[el2_dec_decode_ctl.scala 420:65] + i0_jal <= _T_338 @[el2_dec_decode_ctl.scala 420:15] + io.div_p.valid <= div_decode_d @[el2_dec_decode_ctl.scala 423:21] + io.div_p.bits.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 424:26] + io.div_p.bits.rem <= i0_dp.rem @[el2_dec_decode_ctl.scala 425:26] + io.mul_p.valid <= mul_decode_d @[el2_dec_decode_ctl.scala 427:21] + io.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[el2_dec_decode_ctl.scala 428:26] + io.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[el2_dec_decode_ctl.scala 429:26] + io.mul_p.bits.low <= i0_dp.low @[el2_dec_decode_ctl.scala 430:26] + reg _T_339 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 432:58] + _T_339 <= io.dec_tlu_flush_extint @[el2_dec_decode_ctl.scala 432:58] + io.dec_extint_stall <= _T_339 @[el2_dec_decode_ctl.scala 432:23] + wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.dma <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.dword <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.fast_int <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.dma <= _T_340.bits.dma @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.unsign <= _T_340.bits.unsign @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.store <= _T_340.bits.store @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.load <= _T_340.bits.load @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.dword <= _T_340.bits.dword @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.word <= _T_340.bits.word @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.half <= _T_340.bits.half @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.by <= _T_340.bits.by @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.valid <= _T_340.valid @[el2_dec_decode_ctl.scala 434:12] + when io.dec_extint_stall : @[el2_dec_decode_ctl.scala 435:29] + io.lsu_p.bits.load <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 436:29] + io.lsu_p.bits.word <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 437:29] + io.lsu_p.bits.fast_int <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 438:29] + io.lsu_p.valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 439:24] + skip @[el2_dec_decode_ctl.scala 435:29] + else : @[el2_dec_decode_ctl.scala 440:15] + io.lsu_p.valid <= lsu_decode_d @[el2_dec_decode_ctl.scala 441:35] + io.lsu_p.bits.load <= i0_dp.load @[el2_dec_decode_ctl.scala 442:40] + io.lsu_p.bits.store <= i0_dp.store @[el2_dec_decode_ctl.scala 443:40] + io.lsu_p.bits.by <= i0_dp.by @[el2_dec_decode_ctl.scala 444:40] + io.lsu_p.bits.half <= i0_dp.half @[el2_dec_decode_ctl.scala 445:40] + io.lsu_p.bits.word <= i0_dp.word @[el2_dec_decode_ctl.scala 446:40] + io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[el2_dec_decode_ctl.scala 447:40] + io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[el2_dec_decode_ctl.scala 448:40] + io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[el2_dec_decode_ctl.scala 449:40] + io.lsu_p.bits.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 450:40] + skip @[el2_dec_decode_ctl.scala 440:15] + io.dec_csr_ren_d <= i0_dp.csr_read @[el2_dec_decode_ctl.scala 454:21] + node _T_341 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 455:56] + node _T_342 = and(i0_dp.csr_read, _T_341) @[el2_dec_decode_ctl.scala 455:36] + csr_read <= _T_342 @[el2_dec_decode_ctl.scala 455:18] + node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 457:42] + node i0_csr_write = and(i0_dp.csr_write, _T_343) @[el2_dec_decode_ctl.scala 457:40] + node _T_344 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 458:61] + node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[el2_dec_decode_ctl.scala 458:41] + node _T_345 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 459:59] + node csr_set_d = and(i0_dp.csr_set, _T_345) @[el2_dec_decode_ctl.scala 459:39] + node _T_346 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 460:59] + node csr_write_d = and(i0_csr_write, _T_346) @[el2_dec_decode_ctl.scala 460:39] + node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 462:41] + node _T_348 = and(i0_csr_write, _T_347) @[el2_dec_decode_ctl.scala 462:39] + i0_csr_write_only_d <= _T_348 @[el2_dec_decode_ctl.scala 462:23] + node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[el2_dec_decode_ctl.scala 463:42] + node _T_350 = or(_T_349, i0_csr_write) @[el2_dec_decode_ctl.scala 463:58] + io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 463:24] + node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 466:30] + io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 466:24] + io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 467:23] + node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[el2_dec_decode_ctl.scala 471:39] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:53] + node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:51] + io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 471:20] + node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:50] + node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:85] + node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:64] + node _T_358 = and(_T_357, r_d.bits.csrwen) @[el2_dec_decode_ctl.scala 474:100] + node _T_359 = and(_T_358, r_d.valid) @[el2_dec_decode_ctl.scala 474:118] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:132] + node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:130] + io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 474:27] + reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 476:52] + csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 476:52] + reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 477:51] + csr_clr_x <= csr_clr_d @[el2_dec_decode_ctl.scala 477:51] + reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 478:51] + csr_set_x <= csr_set_d @[el2_dec_decode_ctl.scala 478:51] + reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 479:53] + csr_write_x <= csr_write_d @[el2_dec_decode_ctl.scala 479:53] + reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 480:51] + csr_imm_x <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 480:51] + node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 483:27] + node _T_363 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 483:48] + inst rvclkhdr_1 of rvclkhdr_662 @[el2_lib.scala 508:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_364 @[el2_lib.scala 511:17] + rvclkhdr_1.io.en <= _T_363 @[el2_lib.scala 511:17] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg csr_rddata_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + reg csrimm_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + csrimm_x <= _T_362 @[el2_lib.scala 514:16] + node _T_364 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 484:62] + inst rvclkhdr_2 of rvclkhdr_663 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= _T_364 @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg csr_rddata_x : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] csr_rddata_x <= io.dec_csr_rddata_d @[el2_lib.scala 514:16] - node _T_365 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 491:15] + node _T_365 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 487:15] wire _T_366 : UInt<1>[27] @[el2_lib.scala 162:48] _T_366[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_366[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68028,18 +68026,18 @@ circuit el2_swerv_wrapper : node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58] node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58] node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58] - node _T_393 = bits(csrimm_x, 4, 0) @[el2_dec_decode_ctl.scala 491:53] + node _T_393 = bits(csrimm_x, 4, 0) @[el2_dec_decode_ctl.scala 487:53] node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58] - node _T_395 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 492:16] - node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 492:5] + node _T_395 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 488:16] + node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 488:5] node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72] node _T_398 = mux(_T_396, io.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72] node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72] wire csr_mask_x : UInt<32> @[Mux.scala 27:72] csr_mask_x <= _T_399 @[Mux.scala 27:72] - node _T_400 = not(csr_mask_x) @[el2_dec_decode_ctl.scala 495:38] - node _T_401 = and(csr_rddata_x, _T_400) @[el2_dec_decode_ctl.scala 495:35] - node _T_402 = or(csr_rddata_x, csr_mask_x) @[el2_dec_decode_ctl.scala 496:35] + node _T_400 = not(csr_mask_x) @[el2_dec_decode_ctl.scala 491:38] + node _T_401 = and(csr_rddata_x, _T_400) @[el2_dec_decode_ctl.scala 491:35] + node _T_402 = or(csr_rddata_x, csr_mask_x) @[el2_dec_decode_ctl.scala 492:35] node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72] node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72] node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -68047,74 +68045,74 @@ circuit el2_swerv_wrapper : node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72] wire write_csr_data_x : UInt @[Mux.scala 27:72] write_csr_data_x <= _T_407 @[Mux.scala 27:72] - node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 499:49] - node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[el2_dec_decode_ctl.scala 499:47] - node _T_410 = eq(write_csr_data, UInt<31>("h00")) @[el2_dec_decode_ctl.scala 499:109] - node _T_411 = and(pause_stall, _T_410) @[el2_dec_decode_ctl.scala 499:91] - node clear_pause = or(_T_409, _T_411) @[el2_dec_decode_ctl.scala 499:76] - node _T_412 = or(io.dec_tlu_wr_pause_r, pause_stall) @[el2_dec_decode_ctl.scala 500:44] - node _T_413 = eq(clear_pause, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 500:61] - node _T_414 = and(_T_412, _T_413) @[el2_dec_decode_ctl.scala 500:59] - pause_state_in <= _T_414 @[el2_dec_decode_ctl.scala 500:18] - reg _T_415 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 501:50] - _T_415 <= pause_state_in @[el2_dec_decode_ctl.scala 501:50] - pause_stall <= _T_415 @[el2_dec_decode_ctl.scala 501:15] - io.dec_pause_state <= pause_stall @[el2_dec_decode_ctl.scala 502:22] - reg _T_416 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 503:29] - _T_416 <= io.dec_tlu_wr_pause_r @[el2_dec_decode_ctl.scala 503:29] - tlu_wr_pause_r1 <= _T_416 @[el2_dec_decode_ctl.scala 503:19] - reg _T_417 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 504:29] - _T_417 <= tlu_wr_pause_r1 @[el2_dec_decode_ctl.scala 504:29] - tlu_wr_pause_r2 <= _T_417 @[el2_dec_decode_ctl.scala 504:19] - node _T_418 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 506:44] - node _T_419 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 506:64] - node _T_420 = and(_T_418, _T_419) @[el2_dec_decode_ctl.scala 506:61] - node _T_421 = and(pause_stall, _T_420) @[el2_dec_decode_ctl.scala 506:41] - io.dec_pause_state_cg <= _T_421 @[el2_dec_decode_ctl.scala 506:25] - node _T_422 = sub(write_csr_data, UInt<32>("h01")) @[el2_dec_decode_ctl.scala 509:59] - node _T_423 = tail(_T_422, 1) @[el2_dec_decode_ctl.scala 509:59] - node _T_424 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[el2_dec_decode_ctl.scala 510:8] - node write_csr_data_in = mux(pause_stall, _T_423, _T_424) @[el2_dec_decode_ctl.scala 509:30] - node _T_425 = or(csr_clr_x, csr_set_x) @[el2_dec_decode_ctl.scala 511:34] - node _T_426 = or(_T_425, csr_write_x) @[el2_dec_decode_ctl.scala 511:46] - node _T_427 = and(_T_426, csr_read_x) @[el2_dec_decode_ctl.scala 511:61] - node _T_428 = or(_T_427, io.dec_tlu_wr_pause_r) @[el2_dec_decode_ctl.scala 511:75] - node csr_data_wen = or(_T_428, pause_stall) @[el2_dec_decode_ctl.scala 511:99] - inst rvclkhdr_2 of rvclkhdr_664 @[el2_lib.scala 508:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= csr_data_wen @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_429 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 495:49] + node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[el2_dec_decode_ctl.scala 495:47] + node _T_410 = eq(write_csr_data, UInt<31>("h00")) @[el2_dec_decode_ctl.scala 495:109] + node _T_411 = and(pause_stall, _T_410) @[el2_dec_decode_ctl.scala 495:91] + node clear_pause = or(_T_409, _T_411) @[el2_dec_decode_ctl.scala 495:76] + node _T_412 = or(io.dec_tlu_wr_pause_r, pause_stall) @[el2_dec_decode_ctl.scala 496:44] + node _T_413 = eq(clear_pause, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 496:61] + node _T_414 = and(_T_412, _T_413) @[el2_dec_decode_ctl.scala 496:59] + pause_state_in <= _T_414 @[el2_dec_decode_ctl.scala 496:18] + reg _T_415 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 497:50] + _T_415 <= pause_state_in @[el2_dec_decode_ctl.scala 497:50] + pause_stall <= _T_415 @[el2_dec_decode_ctl.scala 497:15] + io.dec_pause_state <= pause_stall @[el2_dec_decode_ctl.scala 498:22] + reg _T_416 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 499:55] + _T_416 <= io.dec_tlu_wr_pause_r @[el2_dec_decode_ctl.scala 499:55] + tlu_wr_pause_r1 <= _T_416 @[el2_dec_decode_ctl.scala 499:19] + reg _T_417 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 500:55] + _T_417 <= tlu_wr_pause_r1 @[el2_dec_decode_ctl.scala 500:55] + tlu_wr_pause_r2 <= _T_417 @[el2_dec_decode_ctl.scala 500:19] + node _T_418 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 502:44] + node _T_419 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 502:64] + node _T_420 = and(_T_418, _T_419) @[el2_dec_decode_ctl.scala 502:61] + node _T_421 = and(pause_stall, _T_420) @[el2_dec_decode_ctl.scala 502:41] + io.dec_pause_state_cg <= _T_421 @[el2_dec_decode_ctl.scala 502:25] + node _T_422 = sub(write_csr_data, UInt<32>("h01")) @[el2_dec_decode_ctl.scala 505:59] + node _T_423 = tail(_T_422, 1) @[el2_dec_decode_ctl.scala 505:59] + node _T_424 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[el2_dec_decode_ctl.scala 506:8] + node write_csr_data_in = mux(pause_stall, _T_423, _T_424) @[el2_dec_decode_ctl.scala 505:30] + node _T_425 = or(csr_clr_x, csr_set_x) @[el2_dec_decode_ctl.scala 507:34] + node _T_426 = or(_T_425, csr_write_x) @[el2_dec_decode_ctl.scala 507:46] + node _T_427 = and(_T_426, csr_read_x) @[el2_dec_decode_ctl.scala 507:61] + node _T_428 = or(_T_427, io.dec_tlu_wr_pause_r) @[el2_dec_decode_ctl.scala 507:75] + node csr_data_wen = or(_T_428, pause_stall) @[el2_dec_decode_ctl.scala 507:99] + inst rvclkhdr_3 of rvclkhdr_664 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= csr_data_wen @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_429 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_429 <= write_csr_data_in @[el2_lib.scala 514:16] - write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 512:18] - node _T_430 = bits(r_d.bits.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 518:49] - node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 518:30] - io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 518:24] - node _T_432 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[el2_dec_decode_ctl.scala 520:43] - node prior_csr_write = or(_T_432, wbd.bits.csrwonly) @[el2_dec_decode_ctl.scala 520:63] - node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 522:67] - node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 522:48] - node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 523:67] - node debug_fence_raw = and(io.dec_debug_fence_d, _T_434) @[el2_dec_decode_ctl.scala 523:48] - node _T_435 = or(debug_fence_raw, debug_fence_i) @[el2_dec_decode_ctl.scala 524:40] - debug_fence <= _T_435 @[el2_dec_decode_ctl.scala 524:21] - node _T_436 = or(i0_dp.presync, io.dec_tlu_presync_d) @[el2_dec_decode_ctl.scala 527:34] - node _T_437 = or(_T_436, debug_fence_i) @[el2_dec_decode_ctl.scala 527:57] - node _T_438 = or(_T_437, debug_fence_raw) @[el2_dec_decode_ctl.scala 527:73] - node i0_presync = or(_T_438, io.dec_tlu_pipelining_disable) @[el2_dec_decode_ctl.scala 527:91] - node _T_439 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[el2_dec_decode_ctl.scala 530:36] - node _T_440 = or(_T_439, debug_fence_i) @[el2_dec_decode_ctl.scala 530:60] - node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 530:104] - node _T_442 = eq(_T_441, UInt<11>("h07c2")) @[el2_dec_decode_ctl.scala 530:112] - node _T_443 = and(i0_csr_write_only_d, _T_442) @[el2_dec_decode_ctl.scala 530:99] - node i0_postsync = or(_T_440, _T_443) @[el2_dec_decode_ctl.scala 530:76] - node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[el2_dec_decode_ctl.scala 532:34] - io.dec_csr_any_unq_d <= any_csr_d @[el2_dec_decode_ctl.scala 533:24] - node _T_444 = eq(any_csr_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 534:40] - node _T_445 = or(_T_444, io.dec_csr_legal_d) @[el2_dec_decode_ctl.scala 534:51] - node i0_legal = and(i0_dp.legal, _T_445) @[el2_dec_decode_ctl.scala 534:37] + write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 508:18] + node _T_430 = bits(r_d.bits.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:49] + node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 514:30] + io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 514:24] + node _T_432 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:43] + node prior_csr_write = or(_T_432, wbd.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:63] + node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 518:67] + node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 518:48] + node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 519:67] + node debug_fence_raw = and(io.dec_debug_fence_d, _T_434) @[el2_dec_decode_ctl.scala 519:48] + node _T_435 = or(debug_fence_raw, debug_fence_i) @[el2_dec_decode_ctl.scala 520:40] + debug_fence <= _T_435 @[el2_dec_decode_ctl.scala 520:21] + node _T_436 = or(i0_dp.presync, io.dec_tlu_presync_d) @[el2_dec_decode_ctl.scala 523:34] + node _T_437 = or(_T_436, debug_fence_i) @[el2_dec_decode_ctl.scala 523:57] + node _T_438 = or(_T_437, debug_fence_raw) @[el2_dec_decode_ctl.scala 523:73] + node i0_presync = or(_T_438, io.dec_tlu_pipelining_disable) @[el2_dec_decode_ctl.scala 523:91] + node _T_439 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[el2_dec_decode_ctl.scala 526:36] + node _T_440 = or(_T_439, debug_fence_i) @[el2_dec_decode_ctl.scala 526:60] + node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 526:104] + node _T_442 = eq(_T_441, UInt<11>("h07c2")) @[el2_dec_decode_ctl.scala 526:112] + node _T_443 = and(i0_csr_write_only_d, _T_442) @[el2_dec_decode_ctl.scala 526:99] + node i0_postsync = or(_T_440, _T_443) @[el2_dec_decode_ctl.scala 526:76] + node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[el2_dec_decode_ctl.scala 528:34] + io.dec_csr_any_unq_d <= any_csr_d @[el2_dec_decode_ctl.scala 529:24] + node _T_444 = eq(any_csr_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 530:40] + node _T_445 = or(_T_444, io.dec_csr_legal_d) @[el2_dec_decode_ctl.scala 530:51] + node i0_legal = and(i0_dp.legal, _T_445) @[el2_dec_decode_ctl.scala 530:37] wire _T_446 : UInt<1>[16] @[el2_lib.scala 162:48] _T_446[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_446[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68148,107 +68146,107 @@ circuit el2_swerv_wrapper : node _T_460 = cat(_T_459, _T_446[14]) @[Cat.scala 29:58] node _T_461 = cat(_T_460, _T_446[15]) @[Cat.scala 29:58] node _T_462 = cat(_T_461, io.ifu_i0_cinst) @[Cat.scala 29:58] - node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_462) @[el2_dec_decode_ctl.scala 535:27] - node _T_463 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 538:49] - node shift_illegal = and(io.dec_i0_decode_d, _T_463) @[el2_dec_decode_ctl.scala 538:47] - node _T_464 = eq(illegal_lockout, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 539:44] - node illegal_inst_en = and(shift_illegal, _T_464) @[el2_dec_decode_ctl.scala 539:42] - inst rvclkhdr_3 of rvclkhdr_665 @[el2_lib.scala 508:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= illegal_inst_en @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_465 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_462) @[el2_dec_decode_ctl.scala 531:27] + node _T_463 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 534:49] + node shift_illegal = and(io.dec_i0_decode_d, _T_463) @[el2_dec_decode_ctl.scala 534:47] + node _T_464 = eq(illegal_lockout, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 535:44] + node illegal_inst_en = and(shift_illegal, _T_464) @[el2_dec_decode_ctl.scala 535:42] + inst rvclkhdr_4 of rvclkhdr_665 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= illegal_inst_en @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_465 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_465 <= i0_inst_d @[el2_lib.scala 514:16] - io.dec_illegal_inst <= _T_465 @[el2_dec_decode_ctl.scala 540:23] - node _T_466 = or(shift_illegal, illegal_lockout) @[el2_dec_decode_ctl.scala 541:40] - node _T_467 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 541:61] - node _T_468 = and(_T_466, _T_467) @[el2_dec_decode_ctl.scala 541:59] - illegal_lockout_in <= _T_468 @[el2_dec_decode_ctl.scala 541:22] - reg _T_469 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 542:54] - _T_469 <= illegal_lockout_in @[el2_dec_decode_ctl.scala 542:54] - illegal_lockout <= _T_469 @[el2_dec_decode_ctl.scala 542:19] - node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[el2_dec_decode_ctl.scala 543:42] - node _T_470 = and(i0_dp.csr_read, prior_csr_write) @[el2_dec_decode_ctl.scala 545:40] - node _T_471 = or(_T_470, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 545:59] - node _T_472 = or(_T_471, pause_stall) @[el2_dec_decode_ctl.scala 545:81] - node _T_473 = or(_T_472, leak1_i0_stall) @[el2_dec_decode_ctl.scala 545:95] - node _T_474 = or(_T_473, io.dec_tlu_debug_stall) @[el2_dec_decode_ctl.scala 546:20] - node _T_475 = or(_T_474, postsync_stall) @[el2_dec_decode_ctl.scala 546:45] - node _T_476 = or(_T_475, presync_stall) @[el2_dec_decode_ctl.scala 546:62] - node _T_477 = or(i0_dp.fence, debug_fence) @[el2_dec_decode_ctl.scala 547:19] - node _T_478 = eq(lsu_idle, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 547:36] - node _T_479 = and(_T_477, _T_478) @[el2_dec_decode_ctl.scala 547:34] - node _T_480 = or(_T_476, _T_479) @[el2_dec_decode_ctl.scala 546:79] - node _T_481 = or(_T_480, i0_nonblock_load_stall) @[el2_dec_decode_ctl.scala 547:47] - node _T_482 = or(_T_481, i0_load_block_d) @[el2_dec_decode_ctl.scala 547:72] - node _T_483 = or(_T_482, i0_nonblock_div_stall) @[el2_dec_decode_ctl.scala 548:21] - node i0_block_raw_d = or(_T_483, i0_div_prior_div_stall) @[el2_dec_decode_ctl.scala 548:45] - node _T_484 = or(io.lsu_store_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 550:65] - node i0_store_stall_d = and(i0_dp.store, _T_484) @[el2_dec_decode_ctl.scala 550:39] - node _T_485 = or(io.lsu_load_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 551:63] - node i0_load_stall_d = and(i0_dp.load, _T_485) @[el2_dec_decode_ctl.scala 551:38] - node _T_486 = or(i0_block_raw_d, i0_store_stall_d) @[el2_dec_decode_ctl.scala 552:38] - node i0_block_d = or(_T_486, i0_load_stall_d) @[el2_dec_decode_ctl.scala 552:57] - node _T_487 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:46] - node _T_488 = and(io.dec_ib0_valid_d, _T_487) @[el2_dec_decode_ctl.scala 556:44] - node _T_489 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:63] - node _T_490 = and(_T_488, _T_489) @[el2_dec_decode_ctl.scala 556:61] - node _T_491 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:91] - node _T_492 = and(_T_490, _T_491) @[el2_dec_decode_ctl.scala 556:89] - io.dec_i0_decode_d <= _T_492 @[el2_dec_decode_ctl.scala 556:22] - node _T_493 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:46] - node _T_494 = and(io.dec_ib0_valid_d, _T_493) @[el2_dec_decode_ctl.scala 557:44] - node _T_495 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:63] - node _T_496 = and(_T_494, _T_495) @[el2_dec_decode_ctl.scala 557:61] - node _T_497 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:91] - node i0_exudecode_d = and(_T_496, _T_497) @[el2_dec_decode_ctl.scala 557:89] - node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[el2_dec_decode_ctl.scala 558:46] - io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 561:28] - node _T_498 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 562:51] - node _T_499 = and(io.dec_ib0_valid_d, _T_498) @[el2_dec_decode_ctl.scala 562:49] - io.dec_pmu_decode_stall <= _T_499 @[el2_dec_decode_ctl.scala 562:27] - node _T_500 = bits(postsync_stall, 0, 0) @[el2_dec_decode_ctl.scala 563:47] - io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 563:29] - node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 564:46] - io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 564:29] - node prior_inflight = or(x_d.valid, r_d.valid) @[el2_dec_decode_ctl.scala 568:41] - node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[el2_dec_decode_ctl.scala 569:31] - node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 571:37] - presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 571:22] - reg _T_503 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 572:53] - _T_503 <= ps_stall_in @[el2_dec_decode_ctl.scala 572:53] - postsync_stall <= _T_503 @[el2_dec_decode_ctl.scala 572:18] - node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 574:56] - node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 574:54] - node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 574:39] - node _T_507 = and(postsync_stall, x_d.valid) @[el2_dec_decode_ctl.scala 574:88] - node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 574:69] - ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 574:15] - node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 576:50] - io.dec_i0_alu_decode_d <= _T_509 @[el2_dec_decode_ctl.scala 576:26] - node _T_510 = and(i0_legal_decode_d, i0_dp.lsu) @[el2_dec_decode_ctl.scala 578:40] - lsu_decode_d <= _T_510 @[el2_dec_decode_ctl.scala 578:16] - node _T_511 = and(i0_exulegal_decode_d, i0_dp.mul) @[el2_dec_decode_ctl.scala 579:40] - mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 579:16] - node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 580:40] - div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 580:16] - node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 582:45] - node _T_514 = and(r_d.valid, _T_513) @[el2_dec_decode_ctl.scala 582:43] - io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 582:29] - d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 585:26] - node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 586:40] - d_t.icaf <= _T_515 @[el2_dec_decode_ctl.scala 586:26] - node _T_516 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 587:50] - d_t.icaf_f1 <= _T_516 @[el2_dec_decode_ctl.scala 587:26] - d_t.icaf_type <= io.dec_i0_icaf_type_d @[el2_dec_decode_ctl.scala 588:26] - node _T_517 = or(i0_dp.fence_i, debug_fence_i) @[el2_dec_decode_ctl.scala 590:44] - node _T_518 = and(_T_517, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 590:61] - d_t.fence_i <= _T_518 @[el2_dec_decode_ctl.scala 590:26] - d_t.pmu_i0_br_unpred <= i0_br_unpred @[el2_dec_decode_ctl.scala 593:26] - d_t.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 594:26] - d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 595:26] + io.dec_illegal_inst <= _T_465 @[el2_dec_decode_ctl.scala 536:23] + node _T_466 = or(shift_illegal, illegal_lockout) @[el2_dec_decode_ctl.scala 537:40] + node _T_467 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 537:61] + node _T_468 = and(_T_466, _T_467) @[el2_dec_decode_ctl.scala 537:59] + illegal_lockout_in <= _T_468 @[el2_dec_decode_ctl.scala 537:22] + reg _T_469 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 538:54] + _T_469 <= illegal_lockout_in @[el2_dec_decode_ctl.scala 538:54] + illegal_lockout <= _T_469 @[el2_dec_decode_ctl.scala 538:19] + node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[el2_dec_decode_ctl.scala 539:42] + node _T_470 = and(i0_dp.csr_read, prior_csr_write) @[el2_dec_decode_ctl.scala 541:40] + node _T_471 = or(_T_470, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 541:59] + node _T_472 = or(_T_471, pause_stall) @[el2_dec_decode_ctl.scala 541:81] + node _T_473 = or(_T_472, leak1_i0_stall) @[el2_dec_decode_ctl.scala 541:95] + node _T_474 = or(_T_473, io.dec_tlu_debug_stall) @[el2_dec_decode_ctl.scala 542:20] + node _T_475 = or(_T_474, postsync_stall) @[el2_dec_decode_ctl.scala 542:45] + node _T_476 = or(_T_475, presync_stall) @[el2_dec_decode_ctl.scala 542:62] + node _T_477 = or(i0_dp.fence, debug_fence) @[el2_dec_decode_ctl.scala 543:19] + node _T_478 = eq(lsu_idle, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 543:36] + node _T_479 = and(_T_477, _T_478) @[el2_dec_decode_ctl.scala 543:34] + node _T_480 = or(_T_476, _T_479) @[el2_dec_decode_ctl.scala 542:79] + node _T_481 = or(_T_480, i0_nonblock_load_stall) @[el2_dec_decode_ctl.scala 543:47] + node _T_482 = or(_T_481, i0_load_block_d) @[el2_dec_decode_ctl.scala 543:72] + node _T_483 = or(_T_482, i0_nonblock_div_stall) @[el2_dec_decode_ctl.scala 544:21] + node i0_block_raw_d = or(_T_483, i0_div_prior_div_stall) @[el2_dec_decode_ctl.scala 544:45] + node _T_484 = or(io.lsu_store_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 546:65] + node i0_store_stall_d = and(i0_dp.store, _T_484) @[el2_dec_decode_ctl.scala 546:39] + node _T_485 = or(io.lsu_load_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 547:63] + node i0_load_stall_d = and(i0_dp.load, _T_485) @[el2_dec_decode_ctl.scala 547:38] + node _T_486 = or(i0_block_raw_d, i0_store_stall_d) @[el2_dec_decode_ctl.scala 548:38] + node i0_block_d = or(_T_486, i0_load_stall_d) @[el2_dec_decode_ctl.scala 548:57] + node _T_487 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 552:46] + node _T_488 = and(io.dec_ib0_valid_d, _T_487) @[el2_dec_decode_ctl.scala 552:44] + node _T_489 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 552:63] + node _T_490 = and(_T_488, _T_489) @[el2_dec_decode_ctl.scala 552:61] + node _T_491 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 552:91] + node _T_492 = and(_T_490, _T_491) @[el2_dec_decode_ctl.scala 552:89] + io.dec_i0_decode_d <= _T_492 @[el2_dec_decode_ctl.scala 552:22] + node _T_493 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 553:46] + node _T_494 = and(io.dec_ib0_valid_d, _T_493) @[el2_dec_decode_ctl.scala 553:44] + node _T_495 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 553:63] + node _T_496 = and(_T_494, _T_495) @[el2_dec_decode_ctl.scala 553:61] + node _T_497 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 553:91] + node i0_exudecode_d = and(_T_496, _T_497) @[el2_dec_decode_ctl.scala 553:89] + node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[el2_dec_decode_ctl.scala 554:46] + io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 557:28] + node _T_498 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 558:51] + node _T_499 = and(io.dec_ib0_valid_d, _T_498) @[el2_dec_decode_ctl.scala 558:49] + io.dec_pmu_decode_stall <= _T_499 @[el2_dec_decode_ctl.scala 558:27] + node _T_500 = bits(postsync_stall, 0, 0) @[el2_dec_decode_ctl.scala 559:47] + io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 559:29] + node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 560:46] + io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 560:29] + node prior_inflight = or(x_d.valid, r_d.valid) @[el2_dec_decode_ctl.scala 564:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] + node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 567:37] + presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 567:22] + reg _T_503 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 568:53] + _T_503 <= ps_stall_in @[el2_dec_decode_ctl.scala 568:53] + postsync_stall <= _T_503 @[el2_dec_decode_ctl.scala 568:18] + node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 570:56] + node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 570:54] + node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 570:39] + node _T_507 = and(postsync_stall, x_d.valid) @[el2_dec_decode_ctl.scala 570:88] + node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 570:69] + ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 570:15] + node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 572:50] + io.dec_i0_alu_decode_d <= _T_509 @[el2_dec_decode_ctl.scala 572:26] + node _T_510 = and(i0_legal_decode_d, i0_dp.lsu) @[el2_dec_decode_ctl.scala 574:40] + lsu_decode_d <= _T_510 @[el2_dec_decode_ctl.scala 574:16] + node _T_511 = and(i0_exulegal_decode_d, i0_dp.mul) @[el2_dec_decode_ctl.scala 575:40] + mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 575:16] + node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 576:40] + div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 576:16] + node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:45] + node _T_514 = and(r_d.valid, _T_513) @[el2_dec_decode_ctl.scala 578:43] + io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 578:29] + d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 581:26] + node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 582:40] + d_t.icaf <= _T_515 @[el2_dec_decode_ctl.scala 582:26] + node _T_516 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 583:50] + d_t.icaf_f1 <= _T_516 @[el2_dec_decode_ctl.scala 583:26] + d_t.icaf_type <= io.dec_i0_icaf_type_d @[el2_dec_decode_ctl.scala 584:26] + node _T_517 = or(i0_dp.fence_i, debug_fence_i) @[el2_dec_decode_ctl.scala 586:44] + node _T_518 = and(_T_517, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 586:61] + d_t.fence_i <= _T_518 @[el2_dec_decode_ctl.scala 586:26] + d_t.pmu_i0_br_unpred <= i0_br_unpred @[el2_dec_decode_ctl.scala 589:26] + d_t.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 590:26] + d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 591:26] wire _T_519 : UInt<1>[4] @[el2_lib.scala 162:48] _T_519[0] <= io.dec_i0_decode_d @[el2_lib.scala 162:48] _T_519[1] <= io.dec_i0_decode_d @[el2_lib.scala 162:48] @@ -68257,15 +68255,15 @@ circuit el2_swerv_wrapper : node _T_520 = cat(_T_519[0], _T_519[1]) @[Cat.scala 29:58] node _T_521 = cat(_T_520, _T_519[2]) @[Cat.scala 29:58] node _T_522 = cat(_T_521, _T_519[3]) @[Cat.scala 29:58] - node _T_523 = and(io.dec_i0_trigger_match_d, _T_522) @[el2_dec_decode_ctl.scala 597:56] - d_t.i0trigger <= _T_523 @[el2_dec_decode_ctl.scala 597:26] - node _T_524 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 600:33] - inst rvclkhdr_4 of rvclkhdr_666 @[el2_lib.scala 518:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_4.io.en <= _T_524 @[el2_lib.scala 521:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + node _T_523 = and(io.dec_i0_trigger_match_d, _T_522) @[el2_dec_decode_ctl.scala 593:56] + d_t.i0trigger <= _T_523 @[el2_dec_decode_ctl.scala 593:26] + node _T_524 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 596:33] + inst rvclkhdr_5 of rvclkhdr_666 @[el2_lib.scala 518:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_5.io.en <= _T_524 @[el2_lib.scala 521:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] wire _T_525 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33] _T_525.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_525.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33] @@ -68277,7 +68275,7 @@ circuit el2_swerv_wrapper : _T_525.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_525.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_525.legal <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_526 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_4.io.l1clk with : (reset => (reset, _T_525)) @[el2_lib.scala 524:16] + reg _T_526 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_525)) @[el2_lib.scala 524:16] _T_526.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[el2_lib.scala 524:16] _T_526.pmu_divide <= d_t.pmu_divide @[el2_lib.scala 524:16] _T_526.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[el2_lib.scala 524:16] @@ -68288,26 +68286,26 @@ circuit el2_swerv_wrapper : _T_526.icaf_f1 <= d_t.icaf_f1 @[el2_lib.scala 524:16] _T_526.icaf <= d_t.icaf @[el2_lib.scala 524:16] _T_526.legal <= d_t.legal @[el2_lib.scala 524:16] - x_t.pmu_lsu_misaligned <= _T_526.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 600:7] - x_t.pmu_divide <= _T_526.pmu_divide @[el2_dec_decode_ctl.scala 600:7] - x_t.pmu_i0_br_unpred <= _T_526.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 600:7] - x_t.pmu_i0_itype <= _T_526.pmu_i0_itype @[el2_dec_decode_ctl.scala 600:7] - x_t.i0trigger <= _T_526.i0trigger @[el2_dec_decode_ctl.scala 600:7] - x_t.fence_i <= _T_526.fence_i @[el2_dec_decode_ctl.scala 600:7] - x_t.icaf_type <= _T_526.icaf_type @[el2_dec_decode_ctl.scala 600:7] - x_t.icaf_f1 <= _T_526.icaf_f1 @[el2_dec_decode_ctl.scala 600:7] - x_t.icaf <= _T_526.icaf @[el2_dec_decode_ctl.scala 600:7] - x_t.legal <= _T_526.legal @[el2_dec_decode_ctl.scala 600:7] - x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 602:10] - x_t_in.pmu_divide <= x_t.pmu_divide @[el2_dec_decode_ctl.scala 602:10] - x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 602:10] - x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 602:10] - x_t_in.i0trigger <= x_t.i0trigger @[el2_dec_decode_ctl.scala 602:10] - x_t_in.fence_i <= x_t.fence_i @[el2_dec_decode_ctl.scala 602:10] - x_t_in.icaf_type <= x_t.icaf_type @[el2_dec_decode_ctl.scala 602:10] - x_t_in.icaf_f1 <= x_t.icaf_f1 @[el2_dec_decode_ctl.scala 602:10] - x_t_in.icaf <= x_t.icaf @[el2_dec_decode_ctl.scala 602:10] - x_t_in.legal <= x_t.legal @[el2_dec_decode_ctl.scala 602:10] + x_t.pmu_lsu_misaligned <= _T_526.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 596:7] + x_t.pmu_divide <= _T_526.pmu_divide @[el2_dec_decode_ctl.scala 596:7] + x_t.pmu_i0_br_unpred <= _T_526.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 596:7] + x_t.pmu_i0_itype <= _T_526.pmu_i0_itype @[el2_dec_decode_ctl.scala 596:7] + x_t.i0trigger <= _T_526.i0trigger @[el2_dec_decode_ctl.scala 596:7] + x_t.fence_i <= _T_526.fence_i @[el2_dec_decode_ctl.scala 596:7] + x_t.icaf_type <= _T_526.icaf_type @[el2_dec_decode_ctl.scala 596:7] + x_t.icaf_f1 <= _T_526.icaf_f1 @[el2_dec_decode_ctl.scala 596:7] + x_t.icaf <= _T_526.icaf @[el2_dec_decode_ctl.scala 596:7] + x_t.legal <= _T_526.legal @[el2_dec_decode_ctl.scala 596:7] + x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 598:10] + x_t_in.pmu_divide <= x_t.pmu_divide @[el2_dec_decode_ctl.scala 598:10] + x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 598:10] + x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 598:10] + x_t_in.i0trigger <= x_t.i0trigger @[el2_dec_decode_ctl.scala 598:10] + x_t_in.fence_i <= x_t.fence_i @[el2_dec_decode_ctl.scala 598:10] + x_t_in.icaf_type <= x_t.icaf_type @[el2_dec_decode_ctl.scala 598:10] + x_t_in.icaf_f1 <= x_t.icaf_f1 @[el2_dec_decode_ctl.scala 598:10] + x_t_in.icaf <= x_t.icaf @[el2_dec_decode_ctl.scala 598:10] + x_t_in.legal <= x_t.legal @[el2_dec_decode_ctl.scala 598:10] wire _T_527 : UInt<1>[4] @[el2_lib.scala 162:48] _T_527[0] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48] _T_527[1] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48] @@ -68316,16 +68314,16 @@ circuit el2_swerv_wrapper : node _T_528 = cat(_T_527[0], _T_527[1]) @[Cat.scala 29:58] node _T_529 = cat(_T_528, _T_527[2]) @[Cat.scala 29:58] node _T_530 = cat(_T_529, _T_527[3]) @[Cat.scala 29:58] - node _T_531 = not(_T_530) @[el2_dec_decode_ctl.scala 603:39] - node _T_532 = and(x_t.i0trigger, _T_531) @[el2_dec_decode_ctl.scala 603:37] - x_t_in.i0trigger <= _T_532 @[el2_dec_decode_ctl.scala 603:20] - node _T_533 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 605:36] - inst rvclkhdr_5 of rvclkhdr_667 @[el2_lib.scala 518:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_5.io.en <= _T_533 @[el2_lib.scala 521:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + node _T_531 = not(_T_530) @[el2_dec_decode_ctl.scala 599:39] + node _T_532 = and(x_t.i0trigger, _T_531) @[el2_dec_decode_ctl.scala 599:37] + x_t_in.i0trigger <= _T_532 @[el2_dec_decode_ctl.scala 599:20] + node _T_533 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 601:36] + inst rvclkhdr_6 of rvclkhdr_667 @[el2_lib.scala 518:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_6.io.en <= _T_533 @[el2_lib.scala 521:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] wire _T_534 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33] _T_534.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_534.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33] @@ -68337,7 +68335,7 @@ circuit el2_swerv_wrapper : _T_534.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_534.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_534.legal <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_535 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_534)) @[el2_lib.scala 524:16] + reg _T_535 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_534)) @[el2_lib.scala 524:16] _T_535.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[el2_lib.scala 524:16] _T_535.pmu_divide <= x_t_in.pmu_divide @[el2_lib.scala 524:16] _T_535.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[el2_lib.scala 524:16] @@ -68348,31 +68346,31 @@ circuit el2_swerv_wrapper : _T_535.icaf_f1 <= x_t_in.icaf_f1 @[el2_lib.scala 524:16] _T_535.icaf <= x_t_in.icaf @[el2_lib.scala 524:16] _T_535.legal <= x_t_in.legal @[el2_lib.scala 524:16] - r_t.pmu_lsu_misaligned <= _T_535.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 605:7] - r_t.pmu_divide <= _T_535.pmu_divide @[el2_dec_decode_ctl.scala 605:7] - r_t.pmu_i0_br_unpred <= _T_535.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 605:7] - r_t.pmu_i0_itype <= _T_535.pmu_i0_itype @[el2_dec_decode_ctl.scala 605:7] - r_t.i0trigger <= _T_535.i0trigger @[el2_dec_decode_ctl.scala 605:7] - r_t.fence_i <= _T_535.fence_i @[el2_dec_decode_ctl.scala 605:7] - r_t.icaf_type <= _T_535.icaf_type @[el2_dec_decode_ctl.scala 605:7] - r_t.icaf_f1 <= _T_535.icaf_f1 @[el2_dec_decode_ctl.scala 605:7] - r_t.icaf <= _T_535.icaf @[el2_dec_decode_ctl.scala 605:7] - r_t.legal <= _T_535.legal @[el2_dec_decode_ctl.scala 605:7] - reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 606:36] - lsu_trigger_match_r <= io.lsu_trigger_match_m @[el2_dec_decode_ctl.scala 606:36] - reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 607:37] - lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[el2_dec_decode_ctl.scala 607:37] - r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 609:10] - r_t_in.pmu_divide <= r_t.pmu_divide @[el2_dec_decode_ctl.scala 609:10] - r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 609:10] - r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 609:10] - r_t_in.i0trigger <= r_t.i0trigger @[el2_dec_decode_ctl.scala 609:10] - r_t_in.fence_i <= r_t.fence_i @[el2_dec_decode_ctl.scala 609:10] - r_t_in.icaf_type <= r_t.icaf_type @[el2_dec_decode_ctl.scala 609:10] - r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 609:10] - r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 609:10] - r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 609:10] - node _T_536 = or(r_d.bits.i0load, r_d.bits.i0store) @[el2_dec_decode_ctl.scala 611:61] + r_t.pmu_lsu_misaligned <= _T_535.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 601:7] + r_t.pmu_divide <= _T_535.pmu_divide @[el2_dec_decode_ctl.scala 601:7] + r_t.pmu_i0_br_unpred <= _T_535.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 601:7] + r_t.pmu_i0_itype <= _T_535.pmu_i0_itype @[el2_dec_decode_ctl.scala 601:7] + r_t.i0trigger <= _T_535.i0trigger @[el2_dec_decode_ctl.scala 601:7] + r_t.fence_i <= _T_535.fence_i @[el2_dec_decode_ctl.scala 601:7] + r_t.icaf_type <= _T_535.icaf_type @[el2_dec_decode_ctl.scala 601:7] + r_t.icaf_f1 <= _T_535.icaf_f1 @[el2_dec_decode_ctl.scala 601:7] + r_t.icaf <= _T_535.icaf @[el2_dec_decode_ctl.scala 601:7] + r_t.legal <= _T_535.legal @[el2_dec_decode_ctl.scala 601:7] + reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 602:36] + lsu_trigger_match_r <= io.lsu_trigger_match_m @[el2_dec_decode_ctl.scala 602:36] + reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 603:37] + lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[el2_dec_decode_ctl.scala 603:37] + r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 605:10] + r_t_in.pmu_divide <= r_t.pmu_divide @[el2_dec_decode_ctl.scala 605:10] + r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 605:10] + r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 605:10] + r_t_in.i0trigger <= r_t.i0trigger @[el2_dec_decode_ctl.scala 605:10] + r_t_in.fence_i <= r_t.fence_i @[el2_dec_decode_ctl.scala 605:10] + r_t_in.icaf_type <= r_t.icaf_type @[el2_dec_decode_ctl.scala 605:10] + r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 605:10] + r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 605:10] + r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 605:10] + node _T_536 = or(r_d.bits.i0load, r_d.bits.i0store) @[el2_dec_decode_ctl.scala 607:61] wire _T_537 : UInt<1>[4] @[el2_lib.scala 162:48] _T_537[0] <= _T_536 @[el2_lib.scala 162:48] _T_537[1] <= _T_536 @[el2_lib.scala 162:48] @@ -68381,83 +68379,83 @@ circuit el2_swerv_wrapper : node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] - node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 611:82] - node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 611:105] - r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 611:33] - r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 612:33] - node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 614:35] - when _T_543 : @[el2_dec_decode_ctl.scala 614:43] - wire _T_544 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 614:66] - _T_544.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.pmu_i0_itype <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.i0trigger <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.icaf_type <= UInt<2>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.icaf_f1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.icaf <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - r_t_in.pmu_lsu_misaligned <= _T_544.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 614:51] - r_t_in.pmu_divide <= _T_544.pmu_divide @[el2_dec_decode_ctl.scala 614:51] - r_t_in.pmu_i0_br_unpred <= _T_544.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 614:51] - r_t_in.pmu_i0_itype <= _T_544.pmu_i0_itype @[el2_dec_decode_ctl.scala 614:51] - r_t_in.i0trigger <= _T_544.i0trigger @[el2_dec_decode_ctl.scala 614:51] - r_t_in.fence_i <= _T_544.fence_i @[el2_dec_decode_ctl.scala 614:51] - r_t_in.icaf_type <= _T_544.icaf_type @[el2_dec_decode_ctl.scala 614:51] - r_t_in.icaf_f1 <= _T_544.icaf_f1 @[el2_dec_decode_ctl.scala 614:51] - r_t_in.icaf <= _T_544.icaf @[el2_dec_decode_ctl.scala 614:51] - r_t_in.legal <= _T_544.legal @[el2_dec_decode_ctl.scala 614:51] - skip @[el2_dec_decode_ctl.scala 614:43] - io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 616:39] - node _T_545 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 617:58] - io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 617:39] - reg _T_546 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 620:52] - _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 620:52] - flush_final_r <= _T_546 @[el2_dec_decode_ctl.scala 620:17] - node _T_547 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:46] - node _T_548 = and(io.dec_ib0_valid_d, _T_547) @[el2_dec_decode_ctl.scala 622:44] - node _T_549 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:60] - node _T_550 = and(_T_548, _T_549) @[el2_dec_decode_ctl.scala 622:58] - node _T_551 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:88] - node _T_552 = and(_T_550, _T_551) @[el2_dec_decode_ctl.scala 622:86] - io.dec_i0_decode_d <= _T_552 @[el2_dec_decode_ctl.scala 622:22] - node _T_553 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 624:16] - i0r.rs1 <= _T_553 @[el2_dec_decode_ctl.scala 624:11] - node _T_554 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 625:16] - i0r.rs2 <= _T_554 @[el2_dec_decode_ctl.scala 625:11] - node _T_555 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 626:16] - i0r.rd <= _T_555 @[el2_dec_decode_ctl.scala 626:11] - node _T_556 = neq(i0r.rs1, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 628:49] - node _T_557 = and(i0_dp.rs1, _T_556) @[el2_dec_decode_ctl.scala 628:38] - io.dec_i0_rs1_en_d <= _T_557 @[el2_dec_decode_ctl.scala 628:24] - node _T_558 = neq(i0r.rs2, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 629:49] - node _T_559 = and(i0_dp.rs2, _T_558) @[el2_dec_decode_ctl.scala 629:38] - io.dec_i0_rs2_en_d <= _T_559 @[el2_dec_decode_ctl.scala 629:24] - node _T_560 = neq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 630:48] - node i0_rd_en_d = and(i0_dp.rd, _T_560) @[el2_dec_decode_ctl.scala 630:37] - io.dec_i0_rs1_d <= i0r.rs1 @[el2_dec_decode_ctl.scala 631:19] - io.dec_i0_rs2_d <= i0r.rs2 @[el2_dec_decode_ctl.scala 632:19] - node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[el2_dec_decode_ctl.scala 634:38] - node _T_561 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 635:27] - node i0_uiimm20 = and(_T_561, i0_dp.imm20) @[el2_dec_decode_ctl.scala 635:38] - node _T_562 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 639:5] + node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:82] + node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:105] + r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 607:33] + r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 608:33] + node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 610:35] + when _T_543 : @[el2_dec_decode_ctl.scala 610:43] + wire _T_544 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 610:66] + _T_544.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.pmu_i0_itype <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.i0trigger <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.icaf_type <= UInt<2>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.icaf_f1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.icaf <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + r_t_in.pmu_lsu_misaligned <= _T_544.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 610:51] + r_t_in.pmu_divide <= _T_544.pmu_divide @[el2_dec_decode_ctl.scala 610:51] + r_t_in.pmu_i0_br_unpred <= _T_544.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 610:51] + r_t_in.pmu_i0_itype <= _T_544.pmu_i0_itype @[el2_dec_decode_ctl.scala 610:51] + r_t_in.i0trigger <= _T_544.i0trigger @[el2_dec_decode_ctl.scala 610:51] + r_t_in.fence_i <= _T_544.fence_i @[el2_dec_decode_ctl.scala 610:51] + r_t_in.icaf_type <= _T_544.icaf_type @[el2_dec_decode_ctl.scala 610:51] + r_t_in.icaf_f1 <= _T_544.icaf_f1 @[el2_dec_decode_ctl.scala 610:51] + r_t_in.icaf <= _T_544.icaf @[el2_dec_decode_ctl.scala 610:51] + r_t_in.legal <= _T_544.legal @[el2_dec_decode_ctl.scala 610:51] + skip @[el2_dec_decode_ctl.scala 610:43] + io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 612:39] + node _T_545 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 613:58] + io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 613:39] + reg _T_546 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 616:52] + _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 616:52] + flush_final_r <= _T_546 @[el2_dec_decode_ctl.scala 616:17] + node _T_547 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 618:46] + node _T_548 = and(io.dec_ib0_valid_d, _T_547) @[el2_dec_decode_ctl.scala 618:44] + node _T_549 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 618:60] + node _T_550 = and(_T_548, _T_549) @[el2_dec_decode_ctl.scala 618:58] + node _T_551 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 618:88] + node _T_552 = and(_T_550, _T_551) @[el2_dec_decode_ctl.scala 618:86] + io.dec_i0_decode_d <= _T_552 @[el2_dec_decode_ctl.scala 618:22] + node _T_553 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 620:16] + i0r.rs1 <= _T_553 @[el2_dec_decode_ctl.scala 620:11] + node _T_554 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 621:16] + i0r.rs2 <= _T_554 @[el2_dec_decode_ctl.scala 621:11] + node _T_555 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 622:16] + i0r.rd <= _T_555 @[el2_dec_decode_ctl.scala 622:11] + node _T_556 = neq(i0r.rs1, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 624:49] + node _T_557 = and(i0_dp.rs1, _T_556) @[el2_dec_decode_ctl.scala 624:38] + io.dec_i0_rs1_en_d <= _T_557 @[el2_dec_decode_ctl.scala 624:24] + node _T_558 = neq(i0r.rs2, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 625:49] + node _T_559 = and(i0_dp.rs2, _T_558) @[el2_dec_decode_ctl.scala 625:38] + io.dec_i0_rs2_en_d <= _T_559 @[el2_dec_decode_ctl.scala 625:24] + node _T_560 = neq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 626:48] + node i0_rd_en_d = and(i0_dp.rd, _T_560) @[el2_dec_decode_ctl.scala 626:37] + io.dec_i0_rs1_d <= i0r.rs1 @[el2_dec_decode_ctl.scala 627:19] + io.dec_i0_rs2_d <= i0r.rs2 @[el2_dec_decode_ctl.scala 628:19] + node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[el2_dec_decode_ctl.scala 630:38] + node _T_561 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 631:27] + node i0_uiimm20 = and(_T_561, i0_dp.imm20) @[el2_dec_decode_ctl.scala 631:38] + node _T_562 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 635:5] node _T_563 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_564 = mux(_T_562, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_565 = or(_T_563, _T_564) @[Mux.scala 27:72] wire _T_566 : UInt<32> @[Mux.scala 27:72] _T_566 <= _T_565 @[Mux.scala 27:72] - io.dec_i0_immed_d <= _T_566 @[el2_dec_decode_ctl.scala 637:21] - node _T_567 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 642:38] + io.dec_i0_immed_d <= _T_566 @[el2_dec_decode_ctl.scala 633:21] + node _T_567 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 638:38] wire _T_568 : UInt<1>[20] @[el2_lib.scala 162:48] _T_568[0] <= _T_567 @[el2_lib.scala 162:48] _T_568[1] <= _T_567 @[el2_lib.scala 162:48] @@ -68498,7 +68496,7 @@ circuit el2_swerv_wrapper : node _T_585 = cat(_T_584, _T_568[17]) @[Cat.scala 29:58] node _T_586 = cat(_T_585, _T_568[18]) @[Cat.scala 29:58] node _T_587 = cat(_T_586, _T_568[19]) @[Cat.scala 29:58] - node _T_588 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 642:46] + node _T_588 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 638:46] node _T_589 = cat(_T_587, _T_588) @[Cat.scala 29:58] wire _T_590 : UInt<1>[27] @[el2_lib.scala 162:48] _T_590[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68554,9 +68552,9 @@ circuit el2_swerv_wrapper : node _T_614 = cat(_T_613, _T_590[24]) @[Cat.scala 29:58] node _T_615 = cat(_T_614, _T_590[25]) @[Cat.scala 29:58] node _T_616 = cat(_T_615, _T_590[26]) @[Cat.scala 29:58] - node _T_617 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 643:43] + node _T_617 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 639:43] node _T_618 = cat(_T_616, _T_617) @[Cat.scala 29:58] - node _T_619 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 644:38] + node _T_619 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 640:38] wire _T_620 : UInt<1>[12] @[el2_lib.scala 162:48] _T_620[0] <= _T_619 @[el2_lib.scala 162:48] _T_620[1] <= _T_619 @[el2_lib.scala 162:48] @@ -68581,14 +68579,14 @@ circuit el2_swerv_wrapper : node _T_629 = cat(_T_628, _T_620[9]) @[Cat.scala 29:58] node _T_630 = cat(_T_629, _T_620[10]) @[Cat.scala 29:58] node _T_631 = cat(_T_630, _T_620[11]) @[Cat.scala 29:58] - node _T_632 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 644:46] - node _T_633 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 644:56] - node _T_634 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 644:63] + node _T_632 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 640:46] + node _T_633 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 640:56] + node _T_634 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 640:63] node _T_635 = cat(_T_634, UInt<1>("h00")) @[Cat.scala 29:58] node _T_636 = cat(_T_631, _T_632) @[Cat.scala 29:58] node _T_637 = cat(_T_636, _T_633) @[Cat.scala 29:58] node _T_638 = cat(_T_637, _T_635) @[Cat.scala 29:58] - node _T_639 = bits(io.dec_i0_instr_d, 31, 12) @[el2_dec_decode_ctl.scala 645:30] + node _T_639 = bits(io.dec_i0_instr_d, 31, 12) @[el2_dec_decode_ctl.scala 641:30] wire _T_640 : UInt<1>[12] @[el2_lib.scala 162:48] _T_640[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_640[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68614,8 +68612,8 @@ circuit el2_swerv_wrapper : node _T_650 = cat(_T_649, _T_640[10]) @[Cat.scala 29:58] node _T_651 = cat(_T_650, _T_640[11]) @[Cat.scala 29:58] node _T_652 = cat(_T_639, _T_651) @[Cat.scala 29:58] - node _T_653 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[el2_dec_decode_ctl.scala 646:26] - node _T_654 = bits(_T_653, 0, 0) @[el2_dec_decode_ctl.scala 646:43] + node _T_653 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[el2_dec_decode_ctl.scala 642:26] + node _T_654 = bits(_T_653, 0, 0) @[el2_dec_decode_ctl.scala 642:43] wire _T_655 : UInt<1>[27] @[el2_lib.scala 162:48] _T_655[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_655[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68670,7 +68668,7 @@ circuit el2_swerv_wrapper : node _T_679 = cat(_T_678, _T_655[24]) @[Cat.scala 29:58] node _T_680 = cat(_T_679, _T_655[25]) @[Cat.scala 29:58] node _T_681 = cat(_T_680, _T_655[26]) @[Cat.scala 29:58] - node _T_682 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 646:72] + node _T_682 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 642:72] node _T_683 = cat(_T_681, _T_682) @[Cat.scala 29:58] node _T_684 = mux(i0_dp.imm12, _T_589, UInt<1>("h00")) @[Mux.scala 27:72] node _T_685 = mux(i0_dp.shimm5, _T_618, UInt<1>("h00")) @[Mux.scala 27:72] @@ -68683,85 +68681,85 @@ circuit el2_swerv_wrapper : node _T_692 = or(_T_691, _T_688) @[Mux.scala 27:72] wire _T_693 : UInt<32> @[Mux.scala 27:72] _T_693 <= _T_692 @[Mux.scala 27:72] - i0_immed_d <= _T_693 @[el2_dec_decode_ctl.scala 641:14] - node _T_694 = and(io.dec_i0_decode_d, i0_legal) @[el2_dec_decode_ctl.scala 648:46] - i0_legal_decode_d <= _T_694 @[el2_dec_decode_ctl.scala 648:24] - node _T_695 = and(i0_dp.mul, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 650:44] - i0_d_c.mul <= _T_695 @[el2_dec_decode_ctl.scala 650:29] - node _T_696 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 651:44] - i0_d_c.load <= _T_696 @[el2_dec_decode_ctl.scala 651:29] - node _T_697 = and(i0_dp.alu, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 652:44] - i0_d_c.alu <= _T_697 @[el2_dec_decode_ctl.scala 652:29] - node _T_698 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 654:71] + i0_immed_d <= _T_693 @[el2_dec_decode_ctl.scala 637:14] + node _T_694 = and(io.dec_i0_decode_d, i0_legal) @[el2_dec_decode_ctl.scala 644:46] + i0_legal_decode_d <= _T_694 @[el2_dec_decode_ctl.scala 644:24] + node _T_695 = and(i0_dp.mul, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 646:44] + i0_d_c.mul <= _T_695 @[el2_dec_decode_ctl.scala 646:29] + node _T_696 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 647:44] + i0_d_c.load <= _T_696 @[el2_dec_decode_ctl.scala 647:29] + node _T_697 = and(i0_dp.alu, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 648:44] + i0_d_c.alu <= _T_697 @[el2_dec_decode_ctl.scala 648:29] + node _T_698 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 650:71] reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] when _T_698 : @[Reg.scala 16:19] i0_x_c.alu <= i0_d_c.alu @[Reg.scala 16:23] i0_x_c.load <= i0_d_c.load @[Reg.scala 16:23] i0_x_c.mul <= i0_d_c.mul @[Reg.scala 16:23] skip @[Reg.scala 16:19] - node _T_699 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 655:71] + node _T_699 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 651:71] reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] when _T_699 : @[Reg.scala 16:19] i0_r_c.alu <= i0_x_c.alu @[Reg.scala 16:23] i0_r_c.load <= i0_x_c.load @[Reg.scala 16:23] i0_r_c.mul <= i0_x_c.mul @[Reg.scala 16:23] skip @[Reg.scala 16:19] - node _T_700 = bits(i0_pipe_en, 3, 1) @[el2_dec_decode_ctl.scala 656:83] - reg _T_701 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 656:72] - _T_701 <= _T_700 @[el2_dec_decode_ctl.scala 656:72] + node _T_700 = bits(i0_pipe_en, 3, 1) @[el2_dec_decode_ctl.scala 652:83] + reg _T_701 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 652:72] + _T_701 <= _T_700 @[el2_dec_decode_ctl.scala 652:72] node _T_702 = cat(io.dec_i0_decode_d, _T_701) @[Cat.scala 29:58] - i0_pipe_en <= _T_702 @[el2_dec_decode_ctl.scala 656:14] - node _T_703 = bits(i0_pipe_en, 3, 2) @[el2_dec_decode_ctl.scala 658:43] - node _T_704 = orr(_T_703) @[el2_dec_decode_ctl.scala 658:49] - node _T_705 = or(_T_704, io.clk_override) @[el2_dec_decode_ctl.scala 658:53] - i0_x_ctl_en <= _T_705 @[el2_dec_decode_ctl.scala 658:29] - node _T_706 = bits(i0_pipe_en, 2, 1) @[el2_dec_decode_ctl.scala 659:43] - node _T_707 = orr(_T_706) @[el2_dec_decode_ctl.scala 659:49] - node _T_708 = or(_T_707, io.clk_override) @[el2_dec_decode_ctl.scala 659:53] - i0_r_ctl_en <= _T_708 @[el2_dec_decode_ctl.scala 659:29] - node _T_709 = bits(i0_pipe_en, 1, 0) @[el2_dec_decode_ctl.scala 660:43] - node _T_710 = orr(_T_709) @[el2_dec_decode_ctl.scala 660:49] - node _T_711 = or(_T_710, io.clk_override) @[el2_dec_decode_ctl.scala 660:53] - i0_wb_ctl_en <= _T_711 @[el2_dec_decode_ctl.scala 660:29] - node _T_712 = bits(i0_pipe_en, 3, 3) @[el2_dec_decode_ctl.scala 661:44] - node _T_713 = or(_T_712, io.clk_override) @[el2_dec_decode_ctl.scala 661:50] - i0_x_data_en <= _T_713 @[el2_dec_decode_ctl.scala 661:29] - node _T_714 = bits(i0_pipe_en, 2, 2) @[el2_dec_decode_ctl.scala 662:44] - node _T_715 = or(_T_714, io.clk_override) @[el2_dec_decode_ctl.scala 662:50] - i0_r_data_en <= _T_715 @[el2_dec_decode_ctl.scala 662:29] - node _T_716 = bits(i0_pipe_en, 1, 1) @[el2_dec_decode_ctl.scala 663:44] - node _T_717 = or(_T_716, io.clk_override) @[el2_dec_decode_ctl.scala 663:50] - i0_wb_data_en <= _T_717 @[el2_dec_decode_ctl.scala 663:29] - node _T_718 = bits(i0_pipe_en, 0, 0) @[el2_dec_decode_ctl.scala 664:44] - node _T_719 = or(_T_718, io.clk_override) @[el2_dec_decode_ctl.scala 664:50] - i0_wb1_data_en <= _T_719 @[el2_dec_decode_ctl.scala 664:29] + i0_pipe_en <= _T_702 @[el2_dec_decode_ctl.scala 652:14] + node _T_703 = bits(i0_pipe_en, 3, 2) @[el2_dec_decode_ctl.scala 654:43] + node _T_704 = orr(_T_703) @[el2_dec_decode_ctl.scala 654:49] + node _T_705 = or(_T_704, io.clk_override) @[el2_dec_decode_ctl.scala 654:53] + i0_x_ctl_en <= _T_705 @[el2_dec_decode_ctl.scala 654:29] + node _T_706 = bits(i0_pipe_en, 2, 1) @[el2_dec_decode_ctl.scala 655:43] + node _T_707 = orr(_T_706) @[el2_dec_decode_ctl.scala 655:49] + node _T_708 = or(_T_707, io.clk_override) @[el2_dec_decode_ctl.scala 655:53] + i0_r_ctl_en <= _T_708 @[el2_dec_decode_ctl.scala 655:29] + node _T_709 = bits(i0_pipe_en, 1, 0) @[el2_dec_decode_ctl.scala 656:43] + node _T_710 = orr(_T_709) @[el2_dec_decode_ctl.scala 656:49] + node _T_711 = or(_T_710, io.clk_override) @[el2_dec_decode_ctl.scala 656:53] + i0_wb_ctl_en <= _T_711 @[el2_dec_decode_ctl.scala 656:29] + node _T_712 = bits(i0_pipe_en, 3, 3) @[el2_dec_decode_ctl.scala 657:44] + node _T_713 = or(_T_712, io.clk_override) @[el2_dec_decode_ctl.scala 657:50] + i0_x_data_en <= _T_713 @[el2_dec_decode_ctl.scala 657:29] + node _T_714 = bits(i0_pipe_en, 2, 2) @[el2_dec_decode_ctl.scala 658:44] + node _T_715 = or(_T_714, io.clk_override) @[el2_dec_decode_ctl.scala 658:50] + i0_r_data_en <= _T_715 @[el2_dec_decode_ctl.scala 658:29] + node _T_716 = bits(i0_pipe_en, 1, 1) @[el2_dec_decode_ctl.scala 659:44] + node _T_717 = or(_T_716, io.clk_override) @[el2_dec_decode_ctl.scala 659:50] + i0_wb_data_en <= _T_717 @[el2_dec_decode_ctl.scala 659:29] + node _T_718 = bits(i0_pipe_en, 0, 0) @[el2_dec_decode_ctl.scala 660:44] + node _T_719 = or(_T_718, io.clk_override) @[el2_dec_decode_ctl.scala 660:50] + i0_wb1_data_en <= _T_719 @[el2_dec_decode_ctl.scala 660:29] node _T_720 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] - io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 666:27] + io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 662:27] node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] - io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 667:27] - d_d.bits.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 669:34] - node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:50] - d_d.bits.i0v <= _T_722 @[el2_dec_decode_ctl.scala 670:34] - d_d.valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 671:27] - node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:50] - d_d.bits.i0load <= _T_723 @[el2_dec_decode_ctl.scala 673:34] - node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 674:50] - d_d.bits.i0store <= _T_724 @[el2_dec_decode_ctl.scala 674:34] - node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 675:50] - d_d.bits.i0div <= _T_725 @[el2_dec_decode_ctl.scala 675:34] - node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 677:61] - d_d.bits.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 677:34] - node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 678:58] - d_d.bits.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 678:34] - node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 679:40] - d_d.bits.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 679:34] - node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 681:34] - inst rvclkhdr_6 of rvclkhdr_668 @[el2_lib.scala 518:23] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_6.io.en <= _T_729 @[el2_lib.scala 521:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 663:27] + d_d.bits.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:34] + node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:50] + d_d.bits.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:34] + d_d.valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:27] + node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:50] + d_d.bits.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:34] + node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:50] + d_d.bits.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:34] + node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:50] + d_d.bits.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:34] + node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:61] + d_d.bits.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:34] + node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:58] + d_d.bits.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:34] + node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:40] + d_d.bits.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:34] + node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 677:34] + inst rvclkhdr_7 of rvclkhdr_668 @[el2_lib.scala 518:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_7.io.en <= _T_729 @[el2_lib.scala 521:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] wire _T_730 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] _T_730.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] _T_730.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] @@ -68772,7 +68770,7 @@ circuit el2_swerv_wrapper : _T_730.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_730.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] _T_730.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_731 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] + reg _T_731 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] _T_731.bits.csrwaddr <= d_d.bits.csrwaddr @[el2_lib.scala 524:16] _T_731.bits.csrwonly <= d_d.bits.csrwonly @[el2_lib.scala 524:16] _T_731.bits.csrwen <= d_d.bits.csrwen @[el2_lib.scala 524:16] @@ -68782,42 +68780,42 @@ circuit el2_swerv_wrapper : _T_731.bits.i0load <= d_d.bits.i0load @[el2_lib.scala 524:16] _T_731.bits.i0rd <= d_d.bits.i0rd @[el2_lib.scala 524:16] _T_731.valid <= d_d.valid @[el2_lib.scala 524:16] - x_d.bits.csrwaddr <= _T_731.bits.csrwaddr @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.csrwonly <= _T_731.bits.csrwonly @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.csrwen <= _T_731.bits.csrwen @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.i0v <= _T_731.bits.i0v @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.i0div <= _T_731.bits.i0div @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.i0store <= _T_731.bits.i0store @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.i0load <= _T_731.bits.i0load @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.i0rd <= _T_731.bits.i0rd @[el2_dec_decode_ctl.scala 681:7] - x_d.valid <= _T_731.valid @[el2_dec_decode_ctl.scala 681:7] - wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 682:20] - x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.csrwen <= x_d.bits.csrwen @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.i0v <= x_d.bits.i0v @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.i0div <= x_d.bits.i0div @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.i0store <= x_d.bits.i0store @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.i0load <= x_d.bits.i0load @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.i0rd <= x_d.bits.i0rd @[el2_dec_decode_ctl.scala 683:10] - x_d_in.valid <= x_d.valid @[el2_dec_decode_ctl.scala 683:10] - node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:49] - node _T_733 = and(x_d.bits.i0v, _T_732) @[el2_dec_decode_ctl.scala 684:47] - node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:78] - node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 684:76] - x_d_in.bits.i0v <= _T_735 @[el2_dec_decode_ctl.scala 684:27] - node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 685:35] - node _T_737 = and(x_d.valid, _T_736) @[el2_dec_decode_ctl.scala 685:33] - node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 685:64] - node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 685:62] - x_d_in.valid <= _T_739 @[el2_dec_decode_ctl.scala 685:20] - node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 687:36] - inst rvclkhdr_7 of rvclkhdr_669 @[el2_lib.scala 518:23] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_7.io.en <= _T_740 @[el2_lib.scala 521:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + x_d.bits.csrwaddr <= _T_731.bits.csrwaddr @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.csrwonly <= _T_731.bits.csrwonly @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.csrwen <= _T_731.bits.csrwen @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.i0v <= _T_731.bits.i0v @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.i0div <= _T_731.bits.i0div @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.i0store <= _T_731.bits.i0store @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.i0load <= _T_731.bits.i0load @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.i0rd <= _T_731.bits.i0rd @[el2_dec_decode_ctl.scala 677:7] + x_d.valid <= _T_731.valid @[el2_dec_decode_ctl.scala 677:7] + wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 678:20] + x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.csrwen <= x_d.bits.csrwen @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.i0v <= x_d.bits.i0v @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.i0div <= x_d.bits.i0div @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.i0store <= x_d.bits.i0store @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.i0load <= x_d.bits.i0load @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.i0rd <= x_d.bits.i0rd @[el2_dec_decode_ctl.scala 679:10] + x_d_in.valid <= x_d.valid @[el2_dec_decode_ctl.scala 679:10] + node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:49] + node _T_733 = and(x_d.bits.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:47] + node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:78] + node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:76] + x_d_in.bits.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:27] + node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:35] + node _T_737 = and(x_d.valid, _T_736) @[el2_dec_decode_ctl.scala 681:33] + node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:64] + node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:62] + x_d_in.valid <= _T_739 @[el2_dec_decode_ctl.scala 681:20] + node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 683:36] + inst rvclkhdr_8 of rvclkhdr_669 @[el2_lib.scala 518:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_8.io.en <= _T_740 @[el2_lib.scala 521:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] wire _T_741 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] _T_741.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] _T_741.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] @@ -68828,7 +68826,7 @@ circuit el2_swerv_wrapper : _T_741.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_741.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] _T_741.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_742 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] + reg _T_742 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] _T_742.bits.csrwaddr <= x_d_in.bits.csrwaddr @[el2_lib.scala 524:16] _T_742.bits.csrwonly <= x_d_in.bits.csrwonly @[el2_lib.scala 524:16] _T_742.bits.csrwen <= x_d_in.bits.csrwen @[el2_lib.scala 524:16] @@ -68838,44 +68836,44 @@ circuit el2_swerv_wrapper : _T_742.bits.i0load <= x_d_in.bits.i0load @[el2_lib.scala 524:16] _T_742.bits.i0rd <= x_d_in.bits.i0rd @[el2_lib.scala 524:16] _T_742.valid <= x_d_in.valid @[el2_lib.scala 524:16] - r_d.bits.csrwaddr <= _T_742.bits.csrwaddr @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.csrwonly <= _T_742.bits.csrwonly @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.csrwen <= _T_742.bits.csrwen @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.i0v <= _T_742.bits.i0v @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.i0div <= _T_742.bits.i0div @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.i0store <= _T_742.bits.i0store @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.i0load <= _T_742.bits.i0load @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.i0rd <= _T_742.bits.i0rd @[el2_dec_decode_ctl.scala 687:7] - r_d.valid <= _T_742.valid @[el2_dec_decode_ctl.scala 687:7] - r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.csrwen <= r_d.bits.csrwen @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0v <= r_d.bits.i0v @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0div <= r_d.bits.i0div @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0store <= r_d.bits.i0store @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0load <= r_d.bits.i0load @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 688:10] - r_d_in.valid <= r_d.valid @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 689:22] - node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 691:51] - node _T_744 = and(r_d.bits.i0v, _T_743) @[el2_dec_decode_ctl.scala 691:49] - r_d_in.bits.i0v <= _T_744 @[el2_dec_decode_ctl.scala 691:27] - node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 692:37] - node _T_746 = and(r_d.valid, _T_745) @[el2_dec_decode_ctl.scala 692:35] - r_d_in.valid <= _T_746 @[el2_dec_decode_ctl.scala 692:20] - node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 693:51] - node _T_748 = and(r_d.bits.i0load, _T_747) @[el2_dec_decode_ctl.scala 693:49] - r_d_in.bits.i0load <= _T_748 @[el2_dec_decode_ctl.scala 693:27] - node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 694:51] - node _T_750 = and(r_d.bits.i0store, _T_749) @[el2_dec_decode_ctl.scala 694:49] - r_d_in.bits.i0store <= _T_750 @[el2_dec_decode_ctl.scala 694:27] - node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 696:37] - inst rvclkhdr_8 of rvclkhdr_670 @[el2_lib.scala 518:23] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_8.io.en <= _T_751 @[el2_lib.scala 521:17] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + r_d.bits.csrwaddr <= _T_742.bits.csrwaddr @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.csrwonly <= _T_742.bits.csrwonly @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.csrwen <= _T_742.bits.csrwen @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.i0v <= _T_742.bits.i0v @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.i0div <= _T_742.bits.i0div @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.i0store <= _T_742.bits.i0store @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.i0load <= _T_742.bits.i0load @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.i0rd <= _T_742.bits.i0rd @[el2_dec_decode_ctl.scala 683:7] + r_d.valid <= _T_742.valid @[el2_dec_decode_ctl.scala 683:7] + r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.csrwen <= r_d.bits.csrwen @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0v <= r_d.bits.i0v @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0div <= r_d.bits.i0div @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0store <= r_d.bits.i0store @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0load <= r_d.bits.i0load @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 684:10] + r_d_in.valid <= r_d.valid @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 685:22] + node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:51] + node _T_744 = and(r_d.bits.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:49] + r_d_in.bits.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:27] + node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:37] + node _T_746 = and(r_d.valid, _T_745) @[el2_dec_decode_ctl.scala 688:35] + r_d_in.valid <= _T_746 @[el2_dec_decode_ctl.scala 688:20] + node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:51] + node _T_748 = and(r_d.bits.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:49] + r_d_in.bits.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:27] + node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:51] + node _T_750 = and(r_d.bits.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:49] + r_d_in.bits.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:27] + node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 692:37] + inst rvclkhdr_9 of rvclkhdr_670 @[el2_lib.scala 518:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_9.io.en <= _T_751 @[el2_lib.scala 521:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] wire _T_752 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] _T_752.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] _T_752.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] @@ -68886,7 +68884,7 @@ circuit el2_swerv_wrapper : _T_752.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_752.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] _T_752.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_753 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] + reg _T_753 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] _T_753.bits.csrwaddr <= r_d_in.bits.csrwaddr @[el2_lib.scala 524:16] _T_753.bits.csrwonly <= r_d_in.bits.csrwonly @[el2_lib.scala 524:16] _T_753.bits.csrwen <= r_d_in.bits.csrwen @[el2_lib.scala 524:16] @@ -68896,46 +68894,46 @@ circuit el2_swerv_wrapper : _T_753.bits.i0load <= r_d_in.bits.i0load @[el2_lib.scala 524:16] _T_753.bits.i0rd <= r_d_in.bits.i0rd @[el2_lib.scala 524:16] _T_753.valid <= r_d_in.valid @[el2_lib.scala 524:16] - wbd.bits.csrwaddr <= _T_753.bits.csrwaddr @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.csrwonly <= _T_753.bits.csrwonly @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.csrwen <= _T_753.bits.csrwen @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.i0v <= _T_753.bits.i0v @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.i0div <= _T_753.bits.i0div @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.i0store <= _T_753.bits.i0store @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.i0load <= _T_753.bits.i0load @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.i0rd <= _T_753.bits.i0rd @[el2_dec_decode_ctl.scala 696:7] - wbd.valid <= _T_753.valid @[el2_dec_decode_ctl.scala 696:7] - io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[el2_dec_decode_ctl.scala 698:27] - node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 699:47] - node _T_755 = and(r_d_in.bits.i0v, _T_754) @[el2_dec_decode_ctl.scala 699:45] - i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 699:25] - node _T_756 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 700:49] - node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 700:47] - node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 700:70] - node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 700:68] - io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 700:32] - io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 701:26] - node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 703:57] - inst rvclkhdr_9 of rvclkhdr_671 @[el2_lib.scala 508:23] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_9.io.en <= _T_760 @[el2_lib.scala 511:17] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_result_r_raw : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + wbd.bits.csrwaddr <= _T_753.bits.csrwaddr @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.csrwonly <= _T_753.bits.csrwonly @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.csrwen <= _T_753.bits.csrwen @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.i0v <= _T_753.bits.i0v @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.i0div <= _T_753.bits.i0div @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.i0store <= _T_753.bits.i0store @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.i0load <= _T_753.bits.i0load @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.i0rd <= _T_753.bits.i0rd @[el2_dec_decode_ctl.scala 692:7] + wbd.valid <= _T_753.valid @[el2_dec_decode_ctl.scala 692:7] + io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[el2_dec_decode_ctl.scala 694:27] + node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:47] + node _T_755 = and(r_d_in.bits.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:45] + i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 695:25] + node _T_756 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] + node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 696:47] + node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:70] + node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:68] + io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 696:32] + io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 697:26] + node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 699:57] + inst rvclkhdr_10 of rvclkhdr_671 @[el2_lib.scala 508:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_10.io.en <= _T_760 @[el2_lib.scala 511:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16] - node _T_761 = and(x_d.bits.i0v, x_d.bits.i0load) @[el2_dec_decode_ctl.scala 709:47] - node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 709:66] - node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 709:32] - i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 709:26] - i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 710:26] - node _T_764 = and(r_d.bits.i0v, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 714:42] - node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 714:61] - node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 714:27] - i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 714:21] - node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 715:54] - node _T_768 = and(io.i0_ap.predict_nt, _T_767) @[el2_dec_decode_ctl.scala 715:52] - node _T_769 = bits(_T_768, 0, 0) @[el2_dec_decode_ctl.scala 715:66] + node _T_761 = and(x_d.bits.i0v, x_d.bits.i0load) @[el2_dec_decode_ctl.scala 705:47] + node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:66] + node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 705:32] + i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 705:26] + i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 706:26] + node _T_764 = and(r_d.bits.i0v, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 710:42] + node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:61] + node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 710:27] + i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 710:21] + node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 711:54] + node _T_768 = and(io.i0_ap.predict_nt, _T_767) @[el2_dec_decode_ctl.scala 711:52] + node _T_769 = bits(_T_768, 0, 0) @[el2_dec_decode_ctl.scala 711:66] wire _T_770 : UInt<1>[10] @[el2_lib.scala 162:48] _T_770[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_770[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68958,11 +68956,11 @@ circuit el2_swerv_wrapper : node _T_779 = cat(_T_778, _T_770[9]) @[Cat.scala 29:58] node _T_780 = cat(_T_779, io.dec_i0_pc4_d) @[Cat.scala 29:58] node _T_781 = cat(_T_780, i0_ap_pc2) @[Cat.scala 29:58] - node _T_782 = mux(_T_769, i0_br_offset, _T_781) @[el2_dec_decode_ctl.scala 715:30] - io.dec_i0_br_immed_d <= _T_782 @[el2_dec_decode_ctl.scala 715:24] + node _T_782 = mux(_T_769, i0_br_offset, _T_781) @[el2_dec_decode_ctl.scala 711:30] + io.dec_i0_br_immed_d <= _T_782 @[el2_dec_decode_ctl.scala 711:24] wire last_br_immed_d : UInt<12> last_br_immed_d <= UInt<1>("h00") - node _T_783 = bits(io.i0_ap.predict_nt, 0, 0) @[el2_dec_decode_ctl.scala 717:48] + node _T_783 = bits(io.i0_ap.predict_nt, 0, 0) @[el2_dec_decode_ctl.scala 713:48] wire _T_784 : UInt<1>[10] @[el2_lib.scala 162:48] _T_784[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_784[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68985,141 +68983,141 @@ circuit el2_swerv_wrapper : node _T_793 = cat(_T_792, _T_784[9]) @[Cat.scala 29:58] node _T_794 = cat(_T_793, io.dec_i0_pc4_d) @[Cat.scala 29:58] node _T_795 = cat(_T_794, i0_ap_pc2) @[Cat.scala 29:58] - node _T_796 = mux(_T_783, _T_795, i0_br_offset) @[el2_dec_decode_ctl.scala 717:25] - last_br_immed_d <= _T_796 @[el2_dec_decode_ctl.scala 717:19] + node _T_796 = mux(_T_783, _T_795, i0_br_offset) @[el2_dec_decode_ctl.scala 713:25] + last_br_immed_d <= _T_796 @[el2_dec_decode_ctl.scala 713:19] wire last_br_immed_x : UInt<12> last_br_immed_x <= UInt<1>("h00") - node _T_797 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 719:58] - inst rvclkhdr_10 of rvclkhdr_672 @[el2_lib.scala 508:23] - rvclkhdr_10.clock <= clock - rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_10.io.en <= _T_797 @[el2_lib.scala 511:17] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_798 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + node _T_797 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 715:58] + inst rvclkhdr_11 of rvclkhdr_672 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= _T_797 @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_798 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_798 <= last_br_immed_d @[el2_lib.scala 514:16] - last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 719:19] - node _T_799 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 723:45] - node _T_800 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 723:76] - node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 723:58] - node _T_801 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 725:48] - node _T_802 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 725:77] - node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 725:60] - node _T_804 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 726:21] - node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 726:33] - node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 725:94] - node _T_807 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 727:21] - node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 727:33] - node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 727:60] - node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 726:62] - node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 731:51] - node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 732:26] - node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 732:24] - node _T_813 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 732:56] - node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 732:39] - node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 732:77] - node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 731:65] - node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 734:53] - io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 734:29] - node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 735:55] - node _T_817 = eq(io.exu_div_wren, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 737:62] - node _T_818 = and(io.dec_div_active, _T_817) @[el2_dec_decode_ctl.scala 737:60] - node _T_819 = eq(nonblock_div_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 737:81] - node _T_820 = and(_T_818, _T_819) @[el2_dec_decode_ctl.scala 737:79] - node div_active_in = or(i0_div_decode_d, _T_820) @[el2_dec_decode_ctl.scala 737:39] - reg _T_821 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 739:54] - _T_821 <= div_active_in @[el2_dec_decode_ctl.scala 739:54] - io.dec_div_active <= _T_821 @[el2_dec_decode_ctl.scala 739:21] - node _T_822 = and(io.dec_i0_rs1_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 742:49] - node _T_823 = eq(io.div_waddr_wb, i0r.rs1) @[el2_dec_decode_ctl.scala 742:88] - node _T_824 = and(_T_822, _T_823) @[el2_dec_decode_ctl.scala 742:69] - node _T_825 = and(io.dec_i0_rs2_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 743:25] - node _T_826 = eq(io.div_waddr_wb, i0r.rs2) @[el2_dec_decode_ctl.scala 743:64] - node _T_827 = and(_T_825, _T_826) @[el2_dec_decode_ctl.scala 743:45] - node _T_828 = or(_T_824, _T_827) @[el2_dec_decode_ctl.scala 742:102] - i0_nonblock_div_stall <= _T_828 @[el2_dec_decode_ctl.scala 742:26] - node _T_829 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 745:59] + last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 715:19] + node _T_799 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 719:45] + node _T_800 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 719:76] + node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:58] + node _T_801 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 721:48] + node _T_802 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:77] + node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:60] + node _T_804 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 722:21] + node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:33] + node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:94] + node _T_807 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 723:21] + node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:33] + node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:60] + node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:62] + node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 727:51] + node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 728:26] + node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 728:24] + node _T_813 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:56] + node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 728:39] + node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:77] + node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 727:65] + node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 730:53] + io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 730:29] + node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 731:55] + node _T_817 = eq(io.exu_div_wren, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 733:62] + node _T_818 = and(io.dec_div_active, _T_817) @[el2_dec_decode_ctl.scala 733:60] + node _T_819 = eq(nonblock_div_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 733:81] + node _T_820 = and(_T_818, _T_819) @[el2_dec_decode_ctl.scala 733:79] + node div_active_in = or(i0_div_decode_d, _T_820) @[el2_dec_decode_ctl.scala 733:39] + reg _T_821 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 735:54] + _T_821 <= div_active_in @[el2_dec_decode_ctl.scala 735:54] + io.dec_div_active <= _T_821 @[el2_dec_decode_ctl.scala 735:21] + node _T_822 = and(io.dec_i0_rs1_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 738:49] + node _T_823 = eq(io.div_waddr_wb, i0r.rs1) @[el2_dec_decode_ctl.scala 738:88] + node _T_824 = and(_T_822, _T_823) @[el2_dec_decode_ctl.scala 738:69] + node _T_825 = and(io.dec_i0_rs2_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 739:25] + node _T_826 = eq(io.div_waddr_wb, i0r.rs2) @[el2_dec_decode_ctl.scala 739:64] + node _T_827 = and(_T_825, _T_826) @[el2_dec_decode_ctl.scala 739:45] + node _T_828 = or(_T_824, _T_827) @[el2_dec_decode_ctl.scala 738:102] + i0_nonblock_div_stall <= _T_828 @[el2_dec_decode_ctl.scala 738:26] + node _T_829 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 741:59] reg _T_830 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_829 : @[Reg.scala 28:19] _T_830 <= i0r.rd @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.div_waddr_wb <= _T_830 @[el2_dec_decode_ctl.scala 745:19] - node _T_831 = bits(i0_inst_d, 24, 7) @[el2_dec_decode_ctl.scala 752:34] - node _T_832 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 752:57] - inst rvclkhdr_11 of rvclkhdr_673 @[el2_lib.scala 508:23] - rvclkhdr_11.clock <= clock - rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_11.io.en <= _T_832 @[el2_lib.scala 511:17] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg div_inst : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - div_inst <= _T_831 @[el2_lib.scala 514:16] - node _T_833 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 753:49] - inst rvclkhdr_12 of rvclkhdr_674 @[el2_lib.scala 508:23] + io.div_waddr_wb <= _T_830 @[el2_dec_decode_ctl.scala 741:19] + node _T_831 = bits(i0_inst_d, 24, 7) @[el2_dec_decode_ctl.scala 748:34] + node _T_832 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 748:57] + inst rvclkhdr_12 of rvclkhdr_673 @[el2_lib.scala 508:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_12.io.en <= _T_833 @[el2_lib.scala 511:17] + rvclkhdr_12.io.en <= _T_832 @[el2_lib.scala 511:17] rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_inst_x : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_inst_x <= i0_inst_d @[el2_lib.scala 514:16] - node _T_834 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 754:49] - inst rvclkhdr_13 of rvclkhdr_675 @[el2_lib.scala 508:23] + reg div_inst : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + div_inst <= _T_831 @[el2_lib.scala 514:16] + node _T_833 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 749:49] + inst rvclkhdr_13 of rvclkhdr_674 @[el2_lib.scala 508:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_13.io.en <= _T_834 @[el2_lib.scala 511:17] + rvclkhdr_13.io.en <= _T_833 @[el2_lib.scala 511:17] rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_inst_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_inst_r <= i0_inst_x @[el2_lib.scala 514:16] - node _T_835 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 756:50] - inst rvclkhdr_14 of rvclkhdr_676 @[el2_lib.scala 508:23] + reg i0_inst_x : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_inst_x <= i0_inst_d @[el2_lib.scala 514:16] + node _T_834 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 750:49] + inst rvclkhdr_14 of rvclkhdr_675 @[el2_lib.scala 508:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_14.io.en <= _T_835 @[el2_lib.scala 511:17] + rvclkhdr_14.io.en <= _T_834 @[el2_lib.scala 511:17] rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_inst_wb : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_inst_wb <= i0_inst_r @[el2_lib.scala 514:16] - node _T_836 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 757:53] - inst rvclkhdr_15 of rvclkhdr_677 @[el2_lib.scala 508:23] + reg i0_inst_r : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_inst_r <= i0_inst_x @[el2_lib.scala 514:16] + node _T_835 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 752:50] + inst rvclkhdr_15 of rvclkhdr_676 @[el2_lib.scala 508:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_15.io.en <= _T_836 @[el2_lib.scala 511:17] + rvclkhdr_15.io.en <= _T_835 @[el2_lib.scala 511:17] rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_837 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_837 <= i0_inst_wb @[el2_lib.scala 514:16] - io.dec_i0_inst_wb1 <= _T_837 @[el2_dec_decode_ctl.scala 757:22] - node _T_838 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 758:53] - inst rvclkhdr_16 of rvclkhdr_678 @[el2_lib.scala 508:23] + reg i0_inst_wb : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_inst_wb <= i0_inst_r @[el2_lib.scala 514:16] + node _T_836 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 753:53] + inst rvclkhdr_16 of rvclkhdr_677 @[el2_lib.scala 508:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_16.io.en <= _T_838 @[el2_lib.scala 511:17] + rvclkhdr_16.io.en <= _T_836 @[el2_lib.scala 511:17] rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_pc_wb : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_pc_wb <= io.dec_tlu_i0_pc_r @[el2_lib.scala 514:16] - node _T_839 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 760:49] - inst rvclkhdr_17 of rvclkhdr_679 @[el2_lib.scala 508:23] + reg _T_837 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_837 <= i0_inst_wb @[el2_lib.scala 514:16] + io.dec_i0_inst_wb1 <= _T_837 @[el2_dec_decode_ctl.scala 753:22] + node _T_838 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 754:53] + inst rvclkhdr_17 of rvclkhdr_678 @[el2_lib.scala 508:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_17.io.en <= _T_839 @[el2_lib.scala 511:17] + rvclkhdr_17.io.en <= _T_838 @[el2_lib.scala 511:17] rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_840 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_840 <= i0_pc_wb @[el2_lib.scala 514:16] - io.dec_i0_pc_wb1 <= _T_840 @[el2_dec_decode_ctl.scala 760:20] - node _T_841 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 761:56] - inst rvclkhdr_18 of rvclkhdr_680 @[el2_lib.scala 508:23] + reg i0_pc_wb : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_pc_wb <= io.dec_tlu_i0_pc_r @[el2_lib.scala 514:16] + node _T_839 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 756:49] + inst rvclkhdr_18 of rvclkhdr_679 @[el2_lib.scala 508:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_18.io.en <= _T_841 @[el2_lib.scala 511:17] + rvclkhdr_18.io.en <= _T_839 @[el2_lib.scala 511:17] rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg dec_i0_pc_r : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + reg _T_840 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_840 <= i0_pc_wb @[el2_lib.scala 514:16] + io.dec_i0_pc_wb1 <= _T_840 @[el2_dec_decode_ctl.scala 756:20] + node _T_841 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 757:56] + inst rvclkhdr_19 of rvclkhdr_680 @[el2_lib.scala 508:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_19.io.en <= _T_841 @[el2_lib.scala 511:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg dec_i0_pc_r : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] dec_i0_pc_r <= io.exu_i0_pc_x @[el2_lib.scala 514:16] - io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[el2_dec_decode_ctl.scala 763:27] + io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[el2_dec_decode_ctl.scala 759:27] node _T_842 = cat(io.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] node _T_843 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] node _T_844 = bits(_T_842, 12, 1) @[el2_lib.scala 208:24] @@ -69155,124 +69153,124 @@ circuit el2_swerv_wrapper : node _T_873 = bits(_T_846, 11, 0) @[el2_lib.scala 214:94] node _T_874 = cat(_T_872, _T_873) @[Cat.scala 29:58] node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 768:51] - io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 768:25] - node _T_876 = and(io.dec_i0_rs1_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 772:48] - node _T_877 = eq(x_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 772:80] - node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 772:63] - node _T_878 = and(io.dec_i0_rs1_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 773:48] - node _T_879 = eq(r_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 773:80] - node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 773:63] - node _T_880 = and(io.dec_i0_rs2_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 775:48] - node _T_881 = eq(x_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 775:80] - node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 775:63] - node _T_882 = and(io.dec_i0_rs2_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 776:48] - node _T_883 = eq(r_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 776:80] - node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 776:63] - node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 778:44] - node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 778:81] - wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 778:109] - _T_886.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109] - _T_886.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109] - _T_886.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109] - node _T_887 = mux(_T_885, i0_r_c, _T_886) @[el2_dec_decode_ctl.scala 778:61] - node _T_888 = mux(_T_884, i0_x_c, _T_887) @[el2_dec_decode_ctl.scala 778:24] - i0_rs1_class_d.alu <= _T_888.alu @[el2_dec_decode_ctl.scala 778:18] - i0_rs1_class_d.load <= _T_888.load @[el2_dec_decode_ctl.scala 778:18] - i0_rs1_class_d.mul <= _T_888.mul @[el2_dec_decode_ctl.scala 778:18] - node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 779:44] - node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 779:83] - node _T_891 = mux(_T_890, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 779:63] - node _T_892 = mux(_T_889, UInt<2>("h01"), _T_891) @[el2_dec_decode_ctl.scala 779:24] - i0_rs1_depth_d <= _T_892 @[el2_dec_decode_ctl.scala 779:18] - node _T_893 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 780:44] - node _T_894 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 780:81] - wire _T_895 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 780:109] - _T_895.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109] - _T_895.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109] - _T_895.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109] - node _T_896 = mux(_T_894, i0_r_c, _T_895) @[el2_dec_decode_ctl.scala 780:61] - node _T_897 = mux(_T_893, i0_x_c, _T_896) @[el2_dec_decode_ctl.scala 780:24] - i0_rs2_class_d.alu <= _T_897.alu @[el2_dec_decode_ctl.scala 780:18] - i0_rs2_class_d.load <= _T_897.load @[el2_dec_decode_ctl.scala 780:18] - i0_rs2_class_d.mul <= _T_897.mul @[el2_dec_decode_ctl.scala 780:18] - node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 781:44] - node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 781:83] - node _T_900 = mux(_T_899, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 781:63] - node _T_901 = mux(_T_898, UInt<2>("h01"), _T_900) @[el2_dec_decode_ctl.scala 781:24] - i0_rs2_depth_d <= _T_901 @[el2_dec_decode_ctl.scala 781:18] - i0_load_block_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 791:21] - node _T_902 = or(i0_dp.load, i0_dp.store) @[el2_dec_decode_ctl.scala 792:43] - node _T_903 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 792:74] - node _T_904 = and(_T_902, _T_903) @[el2_dec_decode_ctl.scala 792:58] - node _T_905 = and(_T_904, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 792:78] - load_ldst_bypass_d <= _T_905 @[el2_dec_decode_ctl.scala 792:27] - node _T_906 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 793:59] - node _T_907 = and(i0_dp.store, _T_906) @[el2_dec_decode_ctl.scala 793:43] - node _T_908 = and(_T_907, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 793:63] - store_data_bypass_d <= _T_908 @[el2_dec_decode_ctl.scala 793:25] - store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 794:25] - node _T_909 = and(io.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 798:62] - node _T_910 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[el2_dec_decode_ctl.scala 798:119] - node i0_rs1_nonblock_load_bypass_en_d = and(_T_909, _T_910) @[el2_dec_decode_ctl.scala 798:89] - node _T_911 = and(io.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 800:62] - node _T_912 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[el2_dec_decode_ctl.scala 800:119] - node i0_rs2_nonblock_load_bypass_en_d = and(_T_911, _T_912) @[el2_dec_decode_ctl.scala 800:89] - node _T_913 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 803:41] - node _T_914 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 803:66] - node _T_915 = and(_T_913, _T_914) @[el2_dec_decode_ctl.scala 803:45] - node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 803:104] - node _T_917 = and(_T_916, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 803:108] - node _T_918 = bits(i0_rs1_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 803:149] - node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 803:175] - node _T_920 = or(_T_919, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 803:196] - node _T_921 = and(_T_918, _T_920) @[el2_dec_decode_ctl.scala 803:153] + node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 764:51] + io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 764:25] + node _T_876 = and(io.dec_i0_rs1_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 768:48] + node _T_877 = eq(x_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:80] + node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:63] + node _T_878 = and(io.dec_i0_rs1_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 769:48] + node _T_879 = eq(r_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:80] + node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:63] + node _T_880 = and(io.dec_i0_rs2_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 771:48] + node _T_881 = eq(x_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:80] + node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:63] + node _T_882 = and(io.dec_i0_rs2_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 772:48] + node _T_883 = eq(r_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:80] + node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:63] + node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 774:44] + node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 774:81] + wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 774:109] + _T_886.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 774:109] + _T_886.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 774:109] + _T_886.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 774:109] + node _T_887 = mux(_T_885, i0_r_c, _T_886) @[el2_dec_decode_ctl.scala 774:61] + node _T_888 = mux(_T_884, i0_x_c, _T_887) @[el2_dec_decode_ctl.scala 774:24] + i0_rs1_class_d.alu <= _T_888.alu @[el2_dec_decode_ctl.scala 774:18] + i0_rs1_class_d.load <= _T_888.load @[el2_dec_decode_ctl.scala 774:18] + i0_rs1_class_d.mul <= _T_888.mul @[el2_dec_decode_ctl.scala 774:18] + node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 775:44] + node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 775:83] + node _T_891 = mux(_T_890, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 775:63] + node _T_892 = mux(_T_889, UInt<2>("h01"), _T_891) @[el2_dec_decode_ctl.scala 775:24] + i0_rs1_depth_d <= _T_892 @[el2_dec_decode_ctl.scala 775:18] + node _T_893 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 776:44] + node _T_894 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 776:81] + wire _T_895 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 776:109] + _T_895.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 776:109] + _T_895.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 776:109] + _T_895.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 776:109] + node _T_896 = mux(_T_894, i0_r_c, _T_895) @[el2_dec_decode_ctl.scala 776:61] + node _T_897 = mux(_T_893, i0_x_c, _T_896) @[el2_dec_decode_ctl.scala 776:24] + i0_rs2_class_d.alu <= _T_897.alu @[el2_dec_decode_ctl.scala 776:18] + i0_rs2_class_d.load <= _T_897.load @[el2_dec_decode_ctl.scala 776:18] + i0_rs2_class_d.mul <= _T_897.mul @[el2_dec_decode_ctl.scala 776:18] + node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 777:44] + node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 777:83] + node _T_900 = mux(_T_899, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 777:63] + node _T_901 = mux(_T_898, UInt<2>("h01"), _T_900) @[el2_dec_decode_ctl.scala 777:24] + i0_rs2_depth_d <= _T_901 @[el2_dec_decode_ctl.scala 777:18] + i0_load_block_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 787:21] + node _T_902 = or(i0_dp.load, i0_dp.store) @[el2_dec_decode_ctl.scala 788:43] + node _T_903 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 788:74] + node _T_904 = and(_T_902, _T_903) @[el2_dec_decode_ctl.scala 788:58] + node _T_905 = and(_T_904, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 788:78] + load_ldst_bypass_d <= _T_905 @[el2_dec_decode_ctl.scala 788:27] + node _T_906 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 789:59] + node _T_907 = and(i0_dp.store, _T_906) @[el2_dec_decode_ctl.scala 789:43] + node _T_908 = and(_T_907, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 789:63] + store_data_bypass_d <= _T_908 @[el2_dec_decode_ctl.scala 789:25] + store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 790:25] + node _T_909 = and(io.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 794:62] + node _T_910 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[el2_dec_decode_ctl.scala 794:119] + node i0_rs1_nonblock_load_bypass_en_d = and(_T_909, _T_910) @[el2_dec_decode_ctl.scala 794:89] + node _T_911 = and(io.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 796:62] + node _T_912 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[el2_dec_decode_ctl.scala 796:119] + node i0_rs2_nonblock_load_bypass_en_d = and(_T_911, _T_912) @[el2_dec_decode_ctl.scala 796:89] + node _T_913 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 799:41] + node _T_914 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 799:66] + node _T_915 = and(_T_913, _T_914) @[el2_dec_decode_ctl.scala 799:45] + node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 799:104] + node _T_917 = and(_T_916, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 799:108] + node _T_918 = bits(i0_rs1_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 799:149] + node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 799:175] + node _T_920 = or(_T_919, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 799:196] + node _T_921 = and(_T_918, _T_920) @[el2_dec_decode_ctl.scala 799:153] node _T_922 = cat(_T_915, _T_917) @[Cat.scala 29:58] node _T_923 = cat(_T_922, _T_921) @[Cat.scala 29:58] - i0_rs1bypass <= _T_923 @[el2_dec_decode_ctl.scala 803:18] - node _T_924 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 805:41] - node _T_925 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 805:67] - node _T_926 = and(_T_924, _T_925) @[el2_dec_decode_ctl.scala 805:45] - node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 805:105] - node _T_928 = and(_T_927, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 805:109] - node _T_929 = bits(i0_rs2_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 805:149] - node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 805:175] - node _T_931 = or(_T_930, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 805:196] - node _T_932 = and(_T_929, _T_931) @[el2_dec_decode_ctl.scala 805:153] + i0_rs1bypass <= _T_923 @[el2_dec_decode_ctl.scala 799:18] + node _T_924 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 801:41] + node _T_925 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 801:67] + node _T_926 = and(_T_924, _T_925) @[el2_dec_decode_ctl.scala 801:45] + node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 801:105] + node _T_928 = and(_T_927, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 801:109] + node _T_929 = bits(i0_rs2_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 801:149] + node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 801:175] + node _T_931 = or(_T_930, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 801:196] + node _T_932 = and(_T_929, _T_931) @[el2_dec_decode_ctl.scala 801:153] node _T_933 = cat(_T_926, _T_928) @[Cat.scala 29:58] node _T_934 = cat(_T_933, _T_932) @[Cat.scala 29:58] - i0_rs2bypass <= _T_934 @[el2_dec_decode_ctl.scala 805:18] - node _T_935 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:54] - node _T_936 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 807:71] - node _T_937 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 807:89] - node _T_938 = or(_T_936, _T_937) @[el2_dec_decode_ctl.scala 807:75] - node _T_939 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:109] - node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 807:96] - node _T_941 = and(_T_940, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 807:113] - node _T_942 = or(_T_938, _T_941) @[el2_dec_decode_ctl.scala 807:93] + i0_rs2bypass <= _T_934 @[el2_dec_decode_ctl.scala 801:18] + node _T_935 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 803:54] + node _T_936 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 803:71] + node _T_937 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 803:89] + node _T_938 = or(_T_936, _T_937) @[el2_dec_decode_ctl.scala 803:75] + node _T_939 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 803:109] + node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 803:96] + node _T_941 = and(_T_940, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 803:113] + node _T_942 = or(_T_938, _T_941) @[el2_dec_decode_ctl.scala 803:93] node _T_943 = cat(_T_935, _T_942) @[Cat.scala 29:58] - io.dec_i0_rs1_bypass_en_d <= _T_943 @[el2_dec_decode_ctl.scala 807:34] - node _T_944 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 808:54] - node _T_945 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 808:71] - node _T_946 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 808:89] - node _T_947 = or(_T_945, _T_946) @[el2_dec_decode_ctl.scala 808:75] - node _T_948 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 808:109] - node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 808:96] - node _T_950 = and(_T_949, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 808:113] - node _T_951 = or(_T_947, _T_950) @[el2_dec_decode_ctl.scala 808:93] + io.dec_i0_rs1_bypass_en_d <= _T_943 @[el2_dec_decode_ctl.scala 803:34] + node _T_944 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 804:54] + node _T_945 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 804:71] + node _T_946 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 804:89] + node _T_947 = or(_T_945, _T_946) @[el2_dec_decode_ctl.scala 804:75] + node _T_948 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 804:109] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 804:96] + node _T_950 = and(_T_949, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 804:113] + node _T_951 = or(_T_947, _T_950) @[el2_dec_decode_ctl.scala 804:93] node _T_952 = cat(_T_944, _T_951) @[Cat.scala 29:58] - io.dec_i0_rs2_bypass_en_d <= _T_952 @[el2_dec_decode_ctl.scala 808:34] - node _T_953 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 811:17] - node _T_954 = bits(_T_953, 0, 0) @[el2_dec_decode_ctl.scala 811:21] - node _T_955 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 812:17] - node _T_956 = bits(_T_955, 0, 0) @[el2_dec_decode_ctl.scala 812:21] - node _T_957 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 813:19] - node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 813:6] - node _T_959 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 813:38] - node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 813:25] - node _T_961 = and(_T_958, _T_960) @[el2_dec_decode_ctl.scala 813:23] - node _T_962 = and(_T_961, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 813:42] - node _T_963 = bits(_T_962, 0, 0) @[el2_dec_decode_ctl.scala 813:78] + io.dec_i0_rs2_bypass_en_d <= _T_952 @[el2_dec_decode_ctl.scala 804:34] + node _T_953 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 808:17] + node _T_954 = bits(_T_953, 0, 0) @[el2_dec_decode_ctl.scala 808:21] + node _T_955 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 809:17] + node _T_956 = bits(_T_955, 0, 0) @[el2_dec_decode_ctl.scala 809:21] + node _T_957 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 810:19] + node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 810:6] + node _T_959 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 810:38] + node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 810:25] + node _T_961 = and(_T_958, _T_960) @[el2_dec_decode_ctl.scala 810:23] + node _T_962 = and(_T_961, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 810:42] + node _T_963 = bits(_T_962, 0, 0) @[el2_dec_decode_ctl.scala 810:78] node _T_964 = mux(_T_954, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_965 = mux(_T_956, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_966 = mux(_T_963, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] @@ -69280,18 +69278,18 @@ circuit el2_swerv_wrapper : node _T_968 = or(_T_967, _T_966) @[Mux.scala 27:72] wire _T_969 : UInt<32> @[Mux.scala 27:72] _T_969 <= _T_968 @[Mux.scala 27:72] - io.dec_i0_rs1_bypass_data_d <= _T_969 @[el2_dec_decode_ctl.scala 810:31] - node _T_970 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 816:17] - node _T_971 = bits(_T_970, 0, 0) @[el2_dec_decode_ctl.scala 816:21] - node _T_972 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 817:17] - node _T_973 = bits(_T_972, 0, 0) @[el2_dec_decode_ctl.scala 817:21] - node _T_974 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 818:19] - node _T_975 = eq(_T_974, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 818:6] - node _T_976 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 818:38] - node _T_977 = eq(_T_976, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 818:25] - node _T_978 = and(_T_975, _T_977) @[el2_dec_decode_ctl.scala 818:23] - node _T_979 = and(_T_978, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 818:42] - node _T_980 = bits(_T_979, 0, 0) @[el2_dec_decode_ctl.scala 818:78] + io.dec_i0_rs1_bypass_data_d <= _T_969 @[el2_dec_decode_ctl.scala 807:31] + node _T_970 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 813:17] + node _T_971 = bits(_T_970, 0, 0) @[el2_dec_decode_ctl.scala 813:21] + node _T_972 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 814:17] + node _T_973 = bits(_T_972, 0, 0) @[el2_dec_decode_ctl.scala 814:21] + node _T_974 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 815:19] + node _T_975 = eq(_T_974, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 815:6] + node _T_976 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 815:38] + node _T_977 = eq(_T_976, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 815:25] + node _T_978 = and(_T_975, _T_977) @[el2_dec_decode_ctl.scala 815:23] + node _T_979 = and(_T_978, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 815:42] + node _T_980 = bits(_T_979, 0, 0) @[el2_dec_decode_ctl.scala 815:78] node _T_981 = mux(_T_971, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_982 = mux(_T_973, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_983 = mux(_T_980, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] @@ -69299,33 +69297,33 @@ circuit el2_swerv_wrapper : node _T_985 = or(_T_984, _T_983) @[Mux.scala 27:72] wire _T_986 : UInt<32> @[Mux.scala 27:72] _T_986 <= _T_985 @[Mux.scala 27:72] - io.dec_i0_rs2_bypass_data_d <= _T_986 @[el2_dec_decode_ctl.scala 815:31] - node _T_987 = or(i0_dp_raw.load, i0_dp_raw.store) @[el2_dec_decode_ctl.scala 820:68] - node _T_988 = and(io.dec_ib0_valid_d, _T_987) @[el2_dec_decode_ctl.scala 820:50] - node _T_989 = eq(io.dma_dccm_stall_any, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:89] - node _T_990 = and(_T_988, _T_989) @[el2_dec_decode_ctl.scala 820:87] - node _T_991 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:114] - node _T_992 = and(_T_990, _T_991) @[el2_dec_decode_ctl.scala 820:112] - node _T_993 = or(_T_992, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 820:131] - io.dec_lsu_valid_raw_d <= _T_993 @[el2_dec_decode_ctl.scala 820:26] - node _T_994 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 822:6] - node _T_995 = and(_T_994, i0_dp.lsu) @[el2_dec_decode_ctl.scala 822:27] - node _T_996 = and(_T_995, i0_dp.load) @[el2_dec_decode_ctl.scala 822:39] - node _T_997 = bits(_T_996, 0, 0) @[el2_dec_decode_ctl.scala 822:53] - node _T_998 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 822:70] - node _T_999 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 823:6] - node _T_1000 = and(_T_999, i0_dp.lsu) @[el2_dec_decode_ctl.scala 823:27] - node _T_1001 = and(_T_1000, i0_dp.store) @[el2_dec_decode_ctl.scala 823:39] - node _T_1002 = bits(_T_1001, 0, 0) @[el2_dec_decode_ctl.scala 823:54] - node _T_1003 = bits(io.dec_i0_instr_d, 31, 25) @[el2_dec_decode_ctl.scala 823:74] - node _T_1004 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 823:84] + io.dec_i0_rs2_bypass_data_d <= _T_986 @[el2_dec_decode_ctl.scala 812:31] + node _T_987 = or(i0_dp_raw.load, i0_dp_raw.store) @[el2_dec_decode_ctl.scala 817:68] + node _T_988 = and(io.dec_ib0_valid_d, _T_987) @[el2_dec_decode_ctl.scala 817:50] + node _T_989 = eq(io.dma_dccm_stall_any, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 817:89] + node _T_990 = and(_T_988, _T_989) @[el2_dec_decode_ctl.scala 817:87] + node _T_991 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 817:114] + node _T_992 = and(_T_990, _T_991) @[el2_dec_decode_ctl.scala 817:112] + node _T_993 = or(_T_992, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 817:131] + io.dec_lsu_valid_raw_d <= _T_993 @[el2_dec_decode_ctl.scala 817:26] + node _T_994 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 819:6] + node _T_995 = and(_T_994, i0_dp.lsu) @[el2_dec_decode_ctl.scala 819:27] + node _T_996 = and(_T_995, i0_dp.load) @[el2_dec_decode_ctl.scala 819:39] + node _T_997 = bits(_T_996, 0, 0) @[el2_dec_decode_ctl.scala 819:53] + node _T_998 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 819:70] + node _T_999 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:6] + node _T_1000 = and(_T_999, i0_dp.lsu) @[el2_dec_decode_ctl.scala 820:27] + node _T_1001 = and(_T_1000, i0_dp.store) @[el2_dec_decode_ctl.scala 820:39] + node _T_1002 = bits(_T_1001, 0, 0) @[el2_dec_decode_ctl.scala 820:54] + node _T_1003 = bits(io.dec_i0_instr_d, 31, 25) @[el2_dec_decode_ctl.scala 820:74] + node _T_1004 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 820:84] node _T_1005 = cat(_T_1003, _T_1004) @[Cat.scala 29:58] node _T_1006 = mux(_T_997, _T_998, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1007 = mux(_T_1002, _T_1005, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1008 = or(_T_1006, _T_1007) @[Mux.scala 27:72] wire _T_1009 : UInt<12> @[Mux.scala 27:72] _T_1009 <= _T_1008 @[Mux.scala 27:72] - io.dec_lsu_offset_d <= _T_1009 @[el2_dec_decode_ctl.scala 821:23] + io.dec_lsu_offset_d <= _T_1009 @[el2_dec_decode_ctl.scala 818:23] extmodule gated_latch_681 : output Q : Clock @@ -78451,7 +78449,7 @@ circuit el2_swerv_wrapper : lsu_exc_valid_r_d1 <= _T_407 @[el2_dec_tlu_ctl.scala 693:41] reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 694:73] lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 694:73] - node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 695:39] + node _T_408 = eq(io.lsu_error_pkt_r.bits.exc_type, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 695:39] node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[el2_dec_tlu_ctl.scala 695:37] node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 696:37] node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[el2_dec_tlu_ctl.scala 697:37] @@ -80889,9 +80887,8 @@ circuit el2_swerv_wrapper : module el2_dec : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<32>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<32>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<32>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<32>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<9>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<32>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<32>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<32>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<70>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<32>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<13>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<32>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<32>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<32>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<9>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} - io.dec_i0_pc_d <= UInt<1>("h00") @[el2_dec.scala 273:18] wire dec_i0_inst_wb1 : UInt<32> dec_i0_inst_wb1 <= UInt<1>("h00") wire dec_i0_pc_wb1 : UInt<32> @@ -80906,509 +80903,445 @@ circuit el2_swerv_wrapper : dec_tlu_mtval_wb1 <= UInt<1>("h00") wire dec_tlu_i0_exc_valid_wb1 : UInt<1> dec_tlu_i0_exc_valid_wb1 <= UInt<1>("h00") - inst instbuff of el2_dec_ib_ctl @[el2_dec.scala 353:24] + inst instbuff of el2_dec_ib_ctl @[el2_dec.scala 285:24] instbuff.clock <= clock instbuff.reset <= reset - inst decode of el2_dec_decode_ctl @[el2_dec.scala 354:22] + inst decode of el2_dec_decode_ctl @[el2_dec.scala 286:22] decode.clock <= clock decode.reset <= reset - inst gpr of el2_dec_gpr_ctl @[el2_dec.scala 355:19] + inst gpr of el2_dec_gpr_ctl @[el2_dec.scala 287:19] gpr.clock <= clock gpr.reset <= reset - inst tlu of el2_dec_tlu_ctl @[el2_dec.scala 356:19] + inst tlu of el2_dec_tlu_ctl @[el2_dec.scala 288:19] tlu.clock <= clock tlu.reset <= reset - inst dec_trigger of el2_dec_trigger @[el2_dec.scala 357:27] + inst dec_trigger of el2_dec_trigger @[el2_dec.scala 289:27] dec_trigger.clock <= clock dec_trigger.reset <= reset - instbuff.io.dbg_cmd_valid <= io.dbg_cmd_valid @[el2_dec.scala 364:45] - instbuff.io.dbg_cmd_write <= io.dbg_cmd_write @[el2_dec.scala 365:45] - instbuff.io.dbg_cmd_type <= io.dbg_cmd_type @[el2_dec.scala 366:45] - instbuff.io.dbg_cmd_addr <= io.dbg_cmd_addr @[el2_dec.scala 367:45] - instbuff.io.i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec.scala 368:55] - instbuff.io.i0_brp.valid <= io.i0_brp.valid @[el2_dec.scala 368:55] - instbuff.io.ifu_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec.scala 369:35] - instbuff.io.ifu_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec.scala 370:35] - instbuff.io.ifu_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec.scala 371:35] - instbuff.io.ifu_i0_pc4 <= io.ifu_i0_pc4 @[el2_dec.scala 372:35] - instbuff.io.ifu_i0_valid <= io.ifu_i0_valid @[el2_dec.scala 373:35] - instbuff.io.ifu_i0_icaf <= io.ifu_i0_icaf @[el2_dec.scala 374:35] - instbuff.io.ifu_i0_icaf_type <= io.ifu_i0_icaf_type @[el2_dec.scala 375:35] - instbuff.io.ifu_i0_icaf_f1 <= io.ifu_i0_icaf_f1 @[el2_dec.scala 376:35] - instbuff.io.ifu_i0_dbecc <= io.ifu_i0_dbecc @[el2_dec.scala 377:35] - instbuff.io.ifu_i0_instr <= io.ifu_i0_instr @[el2_dec.scala 378:35] - instbuff.io.ifu_i0_pc <= io.ifu_i0_pc @[el2_dec.scala 379:35] - decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[el2_dec.scala 381:38] - decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 382:38] - decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[el2_dec.scala 383:38] - decode.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 384:38] - decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[el2_dec.scala 385:38] - decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 386:38] - decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 387:38] - decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 388:38] - decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[el2_dec.scala 389:38] - decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[el2_dec.scala 390:38] - decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 391:38] - decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 392:38] - io.dec_debug_wdata_rs1_d <= instbuff.io.dec_debug_wdata_rs1_d @[el2_dec.scala 393:38] - decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[el2_dec.scala 394:38] - dec_trigger.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 400:30] - dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 401:34] - decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[el2_dec.scala 410:48] - decode.io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 411:48] - decode.io.ifu_i0_cinst <= io.ifu_i0_cinst @[el2_dec.scala 412:48] - decode.io.lsu_nonblock_load_valid_m <= io.lsu_nonblock_load_valid_m @[el2_dec.scala 413:48] - decode.io.lsu_nonblock_load_tag_m <= io.lsu_nonblock_load_tag_m @[el2_dec.scala 414:48] - decode.io.lsu_nonblock_load_inv_r <= io.lsu_nonblock_load_inv_r @[el2_dec.scala 415:48] - decode.io.lsu_nonblock_load_inv_tag_r <= io.lsu_nonblock_load_inv_tag_r @[el2_dec.scala 416:48] - decode.io.lsu_nonblock_load_data_valid <= io.lsu_nonblock_load_data_valid @[el2_dec.scala 417:48] - decode.io.lsu_nonblock_load_data_error <= io.lsu_nonblock_load_data_error @[el2_dec.scala 418:48] - decode.io.lsu_nonblock_load_data_tag <= io.lsu_nonblock_load_data_tag @[el2_dec.scala 419:48] - decode.io.lsu_nonblock_load_data <= io.lsu_nonblock_load_data @[el2_dec.scala 420:48] - decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[el2_dec.scala 421:48] - decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[el2_dec.scala 422:48] - decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[el2_dec.scala 423:48] - decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[el2_dec.scala 424:48] - decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_bus_misaligned @[el2_dec.scala 425:48] - decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[el2_dec.scala 426:48] - decode.io.dec_tlu_flush_leak_one_r <= tlu.io.dec_tlu_flush_leak_one_r @[el2_dec.scala 427:48] - decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[el2_dec.scala 428:48] - decode.io.dbg_cmd_wrdata <= io.dbg_cmd_wrdata @[el2_dec.scala 429:48] - decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[el2_dec.scala 430:48] - decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 431:48] - decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 432:48] - decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 433:48] - decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 434:48] - decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 435:48] - decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 436:48] - decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[el2_dec.scala 437:48] - decode.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 438:48] - decode.io.lsu_idle_any <= io.lsu_idle_any @[el2_dec.scala 439:48] - decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[el2_dec.scala 440:48] - decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec.scala 441:48] - decode.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec.scala 442:48] - decode.io.exu_div_wren <= io.exu_div_wren @[el2_dec.scala 443:48] - decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[el2_dec.scala 444:48] - decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[el2_dec.scala 445:48] - decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 446:48] - decode.io.dec_tlu_flush_lower_r <= tlu.io.dec_tlu_flush_lower_r @[el2_dec.scala 447:48] - decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[el2_dec.scala 448:48] - decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[el2_dec.scala 449:48] - decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[el2_dec.scala 450:48] - decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 451:48] - decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[el2_dec.scala 452:48] - decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[el2_dec.scala 453:48] - decode.io.exu_csr_rs1_x <= io.exu_csr_rs1_x @[el2_dec.scala 454:48] - decode.io.lsu_result_m <= io.lsu_result_m @[el2_dec.scala 455:48] - decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[el2_dec.scala 456:48] - decode.io.exu_flush_final <= io.exu_flush_final @[el2_dec.scala 457:48] - decode.io.exu_i0_pc_x <= io.exu_i0_pc_x @[el2_dec.scala 458:48] - decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[el2_dec.scala 459:48] - decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[el2_dec.scala 460:48] - decode.io.exu_i0_result_x <= io.exu_i0_result_x @[el2_dec.scala 461:48] - decode.io.free_clk <= io.free_clk @[el2_dec.scala 463:48] - decode.io.active_clk <= io.active_clk @[el2_dec.scala 464:48] - decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[el2_dec.scala 465:48] - decode.io.scan_mode <= io.scan_mode @[el2_dec.scala 467:48] - io.dec_extint_stall <= decode.io.dec_extint_stall @[el2_dec.scala 469:40] - dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb1 @[el2_dec.scala 470:40] - dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb1 @[el2_dec.scala 471:40] - io.dec_i0_rs1_en_d <= decode.io.dec_i0_rs1_en_d @[el2_dec.scala 472:40] - io.dec_i0_rs2_en_d <= decode.io.dec_i0_rs2_en_d @[el2_dec.scala 473:40] - gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[el2_dec.scala 474:40] - gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[el2_dec.scala 475:40] - io.dec_i0_immed_d <= decode.io.dec_i0_immed_d @[el2_dec.scala 476:40] - io.dec_i0_br_immed_d <= decode.io.dec_i0_br_immed_d @[el2_dec.scala 477:40] - io.i0_ap.csr_imm <= decode.io.i0_ap.csr_imm @[el2_dec.scala 478:40] - io.i0_ap.csr_write <= decode.io.i0_ap.csr_write @[el2_dec.scala 478:40] - io.i0_ap.predict_nt <= decode.io.i0_ap.predict_nt @[el2_dec.scala 478:40] - io.i0_ap.predict_t <= decode.io.i0_ap.predict_t @[el2_dec.scala 478:40] - io.i0_ap.jal <= decode.io.i0_ap.jal @[el2_dec.scala 478:40] - io.i0_ap.unsign <= decode.io.i0_ap.unsign @[el2_dec.scala 478:40] - io.i0_ap.slt <= decode.io.i0_ap.slt @[el2_dec.scala 478:40] - io.i0_ap.sub <= decode.io.i0_ap.sub @[el2_dec.scala 478:40] - io.i0_ap.add <= decode.io.i0_ap.add @[el2_dec.scala 478:40] - io.i0_ap.bge <= decode.io.i0_ap.bge @[el2_dec.scala 478:40] - io.i0_ap.blt <= decode.io.i0_ap.blt @[el2_dec.scala 478:40] - io.i0_ap.bne <= decode.io.i0_ap.bne @[el2_dec.scala 478:40] - io.i0_ap.beq <= decode.io.i0_ap.beq @[el2_dec.scala 478:40] - io.i0_ap.sra <= decode.io.i0_ap.sra @[el2_dec.scala 478:40] - io.i0_ap.srl <= decode.io.i0_ap.srl @[el2_dec.scala 478:40] - io.i0_ap.sll <= decode.io.i0_ap.sll @[el2_dec.scala 478:40] - io.i0_ap.lxor <= decode.io.i0_ap.lxor @[el2_dec.scala 478:40] - io.i0_ap.lor <= decode.io.i0_ap.lor @[el2_dec.scala 478:40] - io.i0_ap.land <= decode.io.i0_ap.land @[el2_dec.scala 478:40] - io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[el2_dec.scala 479:40] - io.dec_i0_alu_decode_d <= decode.io.dec_i0_alu_decode_d @[el2_dec.scala 480:40] - io.dec_i0_rs1_bypass_data_d <= decode.io.dec_i0_rs1_bypass_data_d @[el2_dec.scala 481:40] - io.dec_i0_rs2_bypass_data_d <= decode.io.dec_i0_rs2_bypass_data_d @[el2_dec.scala 482:40] - gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[el2_dec.scala 483:40] - gpr.io.wen0 <= decode.io.dec_i0_wen_r @[el2_dec.scala 484:40] - gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[el2_dec.scala 485:40] - io.dec_i0_select_pc_d <= decode.io.dec_i0_select_pc_d @[el2_dec.scala 486:40] - io.dec_i0_rs1_bypass_en_d <= decode.io.dec_i0_rs1_bypass_en_d @[el2_dec.scala 487:40] - io.dec_i0_rs2_bypass_en_d <= decode.io.dec_i0_rs2_bypass_en_d @[el2_dec.scala 488:40] - io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[el2_dec.scala 489:40] - io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[el2_dec.scala 489:40] - io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[el2_dec.scala 489:40] - io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[el2_dec.scala 489:40] - io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[el2_dec.scala 489:40] - io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[el2_dec.scala 489:40] - io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[el2_dec.scala 489:40] - io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[el2_dec.scala 489:40] - io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[el2_dec.scala 489:40] - io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[el2_dec.scala 489:40] - io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[el2_dec.scala 489:40] - io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[el2_dec.scala 489:40] - io.lsu_p.valid <= decode.io.lsu_p.valid @[el2_dec.scala 489:40] - io.mul_p.bits.bfp <= decode.io.mul_p.bits.bfp @[el2_dec.scala 490:40] - io.mul_p.bits.crc32c_w <= decode.io.mul_p.bits.crc32c_w @[el2_dec.scala 490:40] - io.mul_p.bits.crc32c_h <= decode.io.mul_p.bits.crc32c_h @[el2_dec.scala 490:40] - io.mul_p.bits.crc32c_b <= decode.io.mul_p.bits.crc32c_b @[el2_dec.scala 490:40] - io.mul_p.bits.crc32_w <= decode.io.mul_p.bits.crc32_w @[el2_dec.scala 490:40] - io.mul_p.bits.crc32_h <= decode.io.mul_p.bits.crc32_h @[el2_dec.scala 490:40] - io.mul_p.bits.crc32_b <= decode.io.mul_p.bits.crc32_b @[el2_dec.scala 490:40] - io.mul_p.bits.unshfl <= decode.io.mul_p.bits.unshfl @[el2_dec.scala 490:40] - io.mul_p.bits.shfl <= decode.io.mul_p.bits.shfl @[el2_dec.scala 490:40] - io.mul_p.bits.grev <= decode.io.mul_p.bits.grev @[el2_dec.scala 490:40] - io.mul_p.bits.clmulr <= decode.io.mul_p.bits.clmulr @[el2_dec.scala 490:40] - io.mul_p.bits.clmulh <= decode.io.mul_p.bits.clmulh @[el2_dec.scala 490:40] - io.mul_p.bits.clmul <= decode.io.mul_p.bits.clmul @[el2_dec.scala 490:40] - io.mul_p.bits.bdep <= decode.io.mul_p.bits.bdep @[el2_dec.scala 490:40] - io.mul_p.bits.bext <= decode.io.mul_p.bits.bext @[el2_dec.scala 490:40] - io.mul_p.bits.low <= decode.io.mul_p.bits.low @[el2_dec.scala 490:40] - io.mul_p.bits.rs2_sign <= decode.io.mul_p.bits.rs2_sign @[el2_dec.scala 490:40] - io.mul_p.bits.rs1_sign <= decode.io.mul_p.bits.rs1_sign @[el2_dec.scala 490:40] - io.mul_p.valid <= decode.io.mul_p.valid @[el2_dec.scala 490:40] - io.div_p.bits.rem <= decode.io.div_p.bits.rem @[el2_dec.scala 491:40] - io.div_p.bits.unsign <= decode.io.div_p.bits.unsign @[el2_dec.scala 491:40] - io.div_p.valid <= decode.io.div_p.valid @[el2_dec.scala 491:40] - gpr.io.waddr2 <= decode.io.div_waddr_wb @[el2_dec.scala 492:40] - io.dec_div_cancel <= decode.io.dec_div_cancel @[el2_dec.scala 493:40] - io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[el2_dec.scala 494:40] - io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[el2_dec.scala 495:40] - io.dec_csr_ren_d <= decode.io.dec_csr_ren_d @[el2_dec.scala 496:40] - tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[el2_dec.scala 497:40] - tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[el2_dec.scala 498:40] - tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[el2_dec.scala 499:40] - tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[el2_dec.scala 500:40] - tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[el2_dec.scala 501:40] - tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[el2_dec.scala 502:40] - tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[el2_dec.scala 503:40] - tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[el2_dec.scala 504:40] - tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[el2_dec.scala 505:40] - tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[el2_dec.scala 506:40] - tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[el2_dec.scala 507:40] - io.pred_correct_npc_x <= decode.io.pred_correct_npc_x @[el2_dec.scala 508:40] - io.dec_i0_predict_p_d.bits.way <= decode.io.dec_i0_predict_p_d.bits.way @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.pja <= decode.io.dec_i0_predict_p_d.bits.pja @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.pret <= decode.io.dec_i0_predict_p_d.bits.pret @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.pcall <= decode.io.dec_i0_predict_p_d.bits.pcall @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.prett <= decode.io.dec_i0_predict_p_d.bits.prett @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.br_start_error <= decode.io.dec_i0_predict_p_d.bits.br_start_error @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.br_error <= decode.io.dec_i0_predict_p_d.bits.br_error @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.toffset <= decode.io.dec_i0_predict_p_d.bits.toffset @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.hist <= decode.io.dec_i0_predict_p_d.bits.hist @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.pc4 <= decode.io.dec_i0_predict_p_d.bits.pc4 @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.boffset <= decode.io.dec_i0_predict_p_d.bits.boffset @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.ataken <= decode.io.dec_i0_predict_p_d.bits.ataken @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.misp <= decode.io.dec_i0_predict_p_d.bits.misp @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.valid <= decode.io.dec_i0_predict_p_d.valid @[el2_dec.scala 509:40] - io.i0_predict_fghr_d <= decode.io.i0_predict_fghr_d @[el2_dec.scala 510:40] - io.i0_predict_index_d <= decode.io.i0_predict_index_d @[el2_dec.scala 511:40] - io.i0_predict_btag_d <= decode.io.i0_predict_btag_d @[el2_dec.scala 512:40] - io.dec_data_en <= decode.io.dec_data_en @[el2_dec.scala 513:40] - io.dec_ctl_en <= decode.io.dec_ctl_en @[el2_dec.scala 514:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_instr_decoded @[el2_dec.scala 515:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_decode_stall @[el2_dec.scala 516:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_presync_stall @[el2_dec.scala 517:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[el2_dec.scala 518:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_nonblock_load_wen @[el2_dec.scala 519:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_nonblock_load_waddr @[el2_dec.scala 520:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pause_state @[el2_dec.scala 521:40] - io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[el2_dec.scala 522:40] - tlu.io.dec_div_active <= decode.io.dec_div_active @[el2_dec.scala 523:40] - gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[el2_dec.scala 530:23] - gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[el2_dec.scala 531:23] - gpr.io.wen0 <= decode.io.dec_i0_wen_r @[el2_dec.scala 532:23] - gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[el2_dec.scala 533:23] - gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[el2_dec.scala 534:23] - gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[el2_dec.scala 535:23] - gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[el2_dec.scala 536:23] - gpr.io.wd1 <= io.lsu_nonblock_load_data @[el2_dec.scala 537:23] - gpr.io.wen2 <= io.exu_div_wren @[el2_dec.scala 538:23] - gpr.io.waddr2 <= decode.io.div_waddr_wb @[el2_dec.scala 539:23] - gpr.io.wd2 <= io.exu_div_result @[el2_dec.scala 540:23] - gpr.io.scan_mode <= io.scan_mode @[el2_dec.scala 543:23] - io.gpr_i0_rs1_d <= gpr.io.rd0 @[el2_dec.scala 545:19] - io.gpr_i0_rs2_d <= gpr.io.rd1 @[el2_dec.scala 546:19] - tlu.io.active_clk <= io.active_clk @[el2_dec.scala 555:45] - tlu.io.free_clk <= io.free_clk @[el2_dec.scala 556:45] - tlu.io.scan_mode <= io.scan_mode @[el2_dec.scala 558:45] - tlu.io.rst_vec <= io.rst_vec @[el2_dec.scala 559:45] - tlu.io.nmi_int <= io.nmi_int @[el2_dec.scala 560:45] - tlu.io.nmi_vec <= io.nmi_vec @[el2_dec.scala 561:45] - tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[el2_dec.scala 562:45] - tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[el2_dec.scala 563:45] - tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[el2_dec.scala 564:45] - tlu.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[el2_dec.scala 565:45] - tlu.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[el2_dec.scala 566:45] - tlu.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[el2_dec.scala 567:45] - tlu.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[el2_dec.scala 568:45] - tlu.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[el2_dec.scala 569:45] - tlu.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[el2_dec.scala 570:45] - tlu.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[el2_dec.scala 571:45] - tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[el2_dec.scala 572:45] - tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[el2_dec.scala 573:45] - tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[el2_dec.scala 574:45] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[el2_dec.scala 575:45] - tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec.scala 576:45] - tlu.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec.scala 577:45] - tlu.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[el2_dec.scala 578:45] - tlu.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[el2_dec.scala 579:45] - tlu.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[el2_dec.scala 580:45] - tlu.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[el2_dec.scala 581:45] - tlu.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[el2_dec.scala 582:45] - tlu.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[el2_dec.scala 583:45] - tlu.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[el2_dec.scala 584:45] - tlu.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[el2_dec.scala 585:45] - tlu.io.lsu_pmu_load_external_m <= io.lsu_pmu_load_external_m @[el2_dec.scala 586:45] - tlu.io.lsu_pmu_store_external_m <= io.lsu_pmu_store_external_m @[el2_dec.scala 587:45] - tlu.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[el2_dec.scala 588:45] - tlu.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[el2_dec.scala 589:45] - tlu.io.dma_pmu_any_read <= io.dma_pmu_any_read @[el2_dec.scala 590:45] - tlu.io.dma_pmu_any_write <= io.dma_pmu_any_write @[el2_dec.scala 591:45] - tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[el2_dec.scala 592:45] - tlu.io.lsu_fir_error <= io.lsu_fir_error @[el2_dec.scala 593:45] - tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[el2_dec.scala 594:45] - tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[el2_dec.scala 595:45] - tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[el2_dec.scala 595:45] - tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[el2_dec.scala 595:45] - tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[el2_dec.scala 595:45] - tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[el2_dec.scala 595:45] - tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[el2_dec.scala 595:45] - tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[el2_dec.scala 596:45] - tlu.io.dec_pause_state <= decode.io.dec_pause_state @[el2_dec.scala 597:45] - tlu.io.lsu_imprecise_error_store_any <= io.lsu_imprecise_error_store_any @[el2_dec.scala 598:45] - tlu.io.lsu_imprecise_error_load_any <= io.lsu_imprecise_error_load_any @[el2_dec.scala 599:45] - tlu.io.lsu_imprecise_error_addr_any <= io.lsu_imprecise_error_addr_any @[el2_dec.scala 600:45] - tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[el2_dec.scala 601:45] - tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[el2_dec.scala 602:45] - tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[el2_dec.scala 603:45] - tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[el2_dec.scala 604:45] - tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[el2_dec.scala 605:45] - tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[el2_dec.scala 606:45] - tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[el2_dec.scala 607:45] - tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[el2_dec.scala 608:45] - tlu.io.exu_npc_r <= io.exu_npc_r @[el2_dec.scala 609:45] - tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[el2_dec.scala 610:45] - tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[el2_dec.scala 611:45] - tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[el2_dec.scala 612:45] - tlu.io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[el2_dec.scala 613:45] - tlu.io.exu_i0_br_hist_r <= io.exu_i0_br_hist_r @[el2_dec.scala 614:45] - tlu.io.exu_i0_br_error_r <= io.exu_i0_br_error_r @[el2_dec.scala 615:45] - tlu.io.exu_i0_br_start_error_r <= io.exu_i0_br_start_error_r @[el2_dec.scala 616:45] - tlu.io.exu_i0_br_valid_r <= io.exu_i0_br_valid_r @[el2_dec.scala 617:45] - tlu.io.exu_i0_br_mp_r <= io.exu_i0_br_mp_r @[el2_dec.scala 618:45] - tlu.io.exu_i0_br_middle_r <= io.exu_i0_br_middle_r @[el2_dec.scala 619:45] - tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[el2_dec.scala 620:45] - tlu.io.dbg_halt_req <= io.dbg_halt_req @[el2_dec.scala 621:45] - tlu.io.dbg_resume_req <= io.dbg_resume_req @[el2_dec.scala 622:45] - tlu.io.ifu_miss_state_idle <= io.ifu_miss_state_idle @[el2_dec.scala 623:45] - tlu.io.lsu_idle_any <= io.lsu_idle_any @[el2_dec.scala 624:45] - tlu.io.dec_div_active <= decode.io.dec_div_active @[el2_dec.scala 625:45] - tlu.io.ifu_ic_error_start <= io.ifu_ic_error_start @[el2_dec.scala 626:45] - tlu.io.ifu_iccm_rd_ecc_single_err <= io.ifu_iccm_rd_ecc_single_err @[el2_dec.scala 627:45] - tlu.io.ifu_ic_debug_rd_data <= io.ifu_ic_debug_rd_data @[el2_dec.scala 628:45] - tlu.io.ifu_ic_debug_rd_data_valid <= io.ifu_ic_debug_rd_data_valid @[el2_dec.scala 629:45] - tlu.io.pic_claimid <= io.pic_claimid @[el2_dec.scala 630:45] - tlu.io.pic_pl <= io.pic_pl @[el2_dec.scala 631:45] - tlu.io.mhwakeup <= io.mhwakeup @[el2_dec.scala 632:45] - tlu.io.mexintpend <= io.mexintpend @[el2_dec.scala 633:45] - tlu.io.timer_int <= io.timer_int @[el2_dec.scala 634:45] - tlu.io.soft_int <= io.soft_int @[el2_dec.scala 635:45] - tlu.io.core_id <= io.core_id @[el2_dec.scala 636:45] - tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[el2_dec.scala 637:45] - tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[el2_dec.scala 638:45] - tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec.scala 639:45] - io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[el2_dec.scala 641:28] - io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[el2_dec.scala 642:28] - io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[el2_dec.scala 643:28] - io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[el2_dec.scala 644:28] - io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[el2_dec.scala 645:28] - decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[el2_dec.scala 646:36] - io.dec_tlu_flush_noredir_r <= tlu.io.dec_tlu_flush_noredir_r @[el2_dec.scala 647:34] - io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[el2_dec.scala 648:34] - io.dec_tlu_flush_leak_one_r <= tlu.io.dec_tlu_flush_leak_one_r @[el2_dec.scala 649:34] - io.dec_tlu_flush_err_r <= tlu.io.dec_tlu_flush_err_r @[el2_dec.scala 650:34] - decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[el2_dec.scala 651:37] - io.dec_tlu_meihap <= tlu.io.dec_tlu_meihap @[el2_dec.scala 652:29] - io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 653:29] - io.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec.scala 654:29] - io.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec.scala 654:29] - io.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_dec.scala 654:29] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_dec.scala 654:29] - io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[el2_dec.scala 655:29] - io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[el2_dec.scala 656:29] - io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[el2_dec.scala 657:29] - io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[el2_dec.scala 658:29] - io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[el2_dec.scala 659:29] - io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[el2_dec.scala 660:29] - io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[el2_dec.scala 661:29] - io.dec_tlu_meicurpl <= tlu.io.dec_tlu_meicurpl @[el2_dec.scala 662:29] - io.dec_tlu_meipt <= tlu.io.dec_tlu_meipt @[el2_dec.scala 663:29] - decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[el2_dec.scala 664:33] - decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[el2_dec.scala 665:33] - io.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.dec_tlu_br0_r_pkt.bits.middle @[el2_dec.scala 666:42] - io.dec_tlu_br0_r_pkt.bits.way <= tlu.io.dec_tlu_br0_r_pkt.bits.way @[el2_dec.scala 666:42] - io.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_dec.scala 666:42] - io.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_error @[el2_dec.scala 666:42] - io.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.dec_tlu_br0_r_pkt.bits.hist @[el2_dec.scala 666:42] - io.dec_tlu_br0_r_pkt.valid <= tlu.io.dec_tlu_br0_r_pkt.valid @[el2_dec.scala 666:42] - decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[el2_dec.scala 667:42] - decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[el2_dec.scala 668:42] - io.dec_tlu_i0_commit_cmt <= tlu.io.dec_tlu_i0_commit_cmt @[el2_dec.scala 669:34] - io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 670:34] - io.dec_tlu_flush_lower_r <= tlu.io.dec_tlu_flush_lower_r @[el2_dec.scala 671:34] - io.dec_tlu_flush_path_r <= tlu.io.dec_tlu_flush_path_r @[el2_dec.scala 672:34] - io.dec_tlu_fence_i_r <= tlu.io.dec_tlu_fence_i_r @[el2_dec.scala 673:34] - decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[el2_dec.scala 674:35] - decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[el2_dec.scala 675:35] - decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[el2_dec.scala 676:35] - decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[el2_dec.scala 677:35] - io.dec_tlu_mrac_ff <= tlu.io.dec_tlu_mrac_ff @[el2_dec.scala 678:29] - io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 679:29] - io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[el2_dec.scala 680:29] - io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[el2_dec.scala 681:29] - io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[el2_dec.scala 682:29] - io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[el2_dec.scala 683:29] - dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[el2_dec.scala 684:32] - dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[el2_dec.scala 685:32] - dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[el2_dec.scala 686:32] - dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[el2_dec.scala 687:32] - dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[el2_dec.scala 688:32] - io.dec_tlu_external_ldfwd_disable <= tlu.io.dec_tlu_external_ldfwd_disable @[el2_dec.scala 689:43] - io.dec_tlu_sideeffect_posted_disable <= tlu.io.dec_tlu_sideeffect_posted_disable @[el2_dec.scala 690:43] - io.dec_tlu_core_ecc_disable <= tlu.io.dec_tlu_core_ecc_disable @[el2_dec.scala 691:43] - io.dec_tlu_bpred_disable <= tlu.io.dec_tlu_bpred_disable @[el2_dec.scala 692:43] - io.dec_tlu_wb_coalescing_disable <= tlu.io.dec_tlu_wb_coalescing_disable @[el2_dec.scala 693:43] - io.dec_tlu_dma_qos_prty <= tlu.io.dec_tlu_dma_qos_prty @[el2_dec.scala 695:35] - io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[el2_dec.scala 696:35] - io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[el2_dec.scala 698:36] - io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[el2_dec.scala 699:36] - io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[el2_dec.scala 700:36] - io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[el2_dec.scala 701:36] - io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[el2_dec.scala 702:36] - io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[el2_dec.scala 703:36] - io.rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb1 @[el2_dec.scala 707:32] + io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 291:18] + instbuff.io.dbg_cmd_valid <= io.dbg_cmd_valid @[el2_dec.scala 297:45] + instbuff.io.dbg_cmd_write <= io.dbg_cmd_write @[el2_dec.scala 298:45] + instbuff.io.dbg_cmd_type <= io.dbg_cmd_type @[el2_dec.scala 299:45] + instbuff.io.dbg_cmd_addr <= io.dbg_cmd_addr @[el2_dec.scala 300:45] + instbuff.io.i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec.scala 301:55] + instbuff.io.i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec.scala 301:55] + instbuff.io.i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec.scala 301:55] + instbuff.io.i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec.scala 301:55] + instbuff.io.i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec.scala 301:55] + instbuff.io.i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec.scala 301:55] + instbuff.io.i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec.scala 301:55] + instbuff.io.i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec.scala 301:55] + instbuff.io.i0_brp.valid <= io.i0_brp.valid @[el2_dec.scala 301:55] + instbuff.io.ifu_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec.scala 302:35] + instbuff.io.ifu_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec.scala 303:35] + instbuff.io.ifu_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec.scala 304:35] + instbuff.io.ifu_i0_pc4 <= io.ifu_i0_pc4 @[el2_dec.scala 305:35] + instbuff.io.ifu_i0_valid <= io.ifu_i0_valid @[el2_dec.scala 306:35] + instbuff.io.ifu_i0_icaf <= io.ifu_i0_icaf @[el2_dec.scala 307:35] + instbuff.io.ifu_i0_icaf_type <= io.ifu_i0_icaf_type @[el2_dec.scala 308:35] + instbuff.io.ifu_i0_icaf_f1 <= io.ifu_i0_icaf_f1 @[el2_dec.scala 309:35] + instbuff.io.ifu_i0_dbecc <= io.ifu_i0_dbecc @[el2_dec.scala 310:35] + instbuff.io.ifu_i0_instr <= io.ifu_i0_instr @[el2_dec.scala 311:35] + instbuff.io.ifu_i0_pc <= io.ifu_i0_pc @[el2_dec.scala 312:35] + io.dec_debug_wdata_rs1_d <= instbuff.io.dec_debug_wdata_rs1_d @[el2_dec.scala 314:38] + dec_trigger.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 320:30] + dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 321:34] + decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[el2_dec.scala 330:48] + decode.io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 331:48] + decode.io.ifu_i0_cinst <= io.ifu_i0_cinst @[el2_dec.scala 332:48] + decode.io.lsu_nonblock_load_valid_m <= io.lsu_nonblock_load_valid_m @[el2_dec.scala 333:48] + decode.io.lsu_nonblock_load_tag_m <= io.lsu_nonblock_load_tag_m @[el2_dec.scala 334:48] + decode.io.lsu_nonblock_load_inv_r <= io.lsu_nonblock_load_inv_r @[el2_dec.scala 335:48] + decode.io.lsu_nonblock_load_inv_tag_r <= io.lsu_nonblock_load_inv_tag_r @[el2_dec.scala 336:48] + decode.io.lsu_nonblock_load_data_valid <= io.lsu_nonblock_load_data_valid @[el2_dec.scala 337:48] + decode.io.lsu_nonblock_load_data_error <= io.lsu_nonblock_load_data_error @[el2_dec.scala 338:48] + decode.io.lsu_nonblock_load_data_tag <= io.lsu_nonblock_load_data_tag @[el2_dec.scala 339:48] + decode.io.lsu_nonblock_load_data <= io.lsu_nonblock_load_data @[el2_dec.scala 340:48] + decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[el2_dec.scala 341:48] + decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[el2_dec.scala 342:48] + decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[el2_dec.scala 343:48] + decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[el2_dec.scala 344:48] + decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_bus_misaligned @[el2_dec.scala 345:48] + decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[el2_dec.scala 346:48] + decode.io.dec_tlu_flush_leak_one_r <= tlu.io.dec_tlu_flush_leak_one_r @[el2_dec.scala 347:48] + decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[el2_dec.scala 348:48] + decode.io.dbg_cmd_wrdata <= io.dbg_cmd_wrdata @[el2_dec.scala 349:48] + decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[el2_dec.scala 350:48] + decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 351:48] + decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 352:48] + decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 353:48] + decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 354:48] + decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 355:48] + decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 356:48] + decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[el2_dec.scala 357:48] + decode.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 358:48] + decode.io.lsu_idle_any <= io.lsu_idle_any @[el2_dec.scala 359:48] + decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[el2_dec.scala 360:48] + decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec.scala 361:48] + decode.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec.scala 362:48] + decode.io.exu_div_wren <= io.exu_div_wren @[el2_dec.scala 363:48] + decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[el2_dec.scala 364:48] + decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[el2_dec.scala 365:48] + decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 366:48] + decode.io.dec_tlu_flush_lower_r <= tlu.io.dec_tlu_flush_lower_r @[el2_dec.scala 367:48] + decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[el2_dec.scala 368:48] + decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[el2_dec.scala 369:48] + decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[el2_dec.scala 370:48] + decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[el2_dec.scala 371:48] + decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[el2_dec.scala 372:48] + decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[el2_dec.scala 373:48] + decode.io.exu_csr_rs1_x <= io.exu_csr_rs1_x @[el2_dec.scala 374:48] + decode.io.lsu_result_m <= io.lsu_result_m @[el2_dec.scala 375:48] + decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[el2_dec.scala 376:48] + decode.io.exu_flush_final <= io.exu_flush_final @[el2_dec.scala 377:48] + decode.io.exu_i0_pc_x <= io.exu_i0_pc_x @[el2_dec.scala 378:48] + decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[el2_dec.scala 379:48] + decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[el2_dec.scala 380:48] + decode.io.exu_i0_result_x <= io.exu_i0_result_x @[el2_dec.scala 381:48] + decode.io.free_clk <= io.free_clk @[el2_dec.scala 383:48] + decode.io.active_clk <= io.active_clk @[el2_dec.scala 384:48] + decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[el2_dec.scala 385:48] + decode.io.scan_mode <= io.scan_mode @[el2_dec.scala 387:48] + io.dec_extint_stall <= decode.io.dec_extint_stall @[el2_dec.scala 389:40] + dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb1 @[el2_dec.scala 390:40] + dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb1 @[el2_dec.scala 391:40] + io.dec_i0_rs1_en_d <= decode.io.dec_i0_rs1_en_d @[el2_dec.scala 392:40] + io.dec_i0_rs2_en_d <= decode.io.dec_i0_rs2_en_d @[el2_dec.scala 393:40] + io.dec_i0_immed_d <= decode.io.dec_i0_immed_d @[el2_dec.scala 394:40] + io.dec_i0_br_immed_d <= decode.io.dec_i0_br_immed_d @[el2_dec.scala 395:40] + io.i0_ap.csr_imm <= decode.io.i0_ap.csr_imm @[el2_dec.scala 396:40] + io.i0_ap.csr_write <= decode.io.i0_ap.csr_write @[el2_dec.scala 396:40] + io.i0_ap.predict_nt <= decode.io.i0_ap.predict_nt @[el2_dec.scala 396:40] + io.i0_ap.predict_t <= decode.io.i0_ap.predict_t @[el2_dec.scala 396:40] + io.i0_ap.jal <= decode.io.i0_ap.jal @[el2_dec.scala 396:40] + io.i0_ap.unsign <= decode.io.i0_ap.unsign @[el2_dec.scala 396:40] + io.i0_ap.slt <= decode.io.i0_ap.slt @[el2_dec.scala 396:40] + io.i0_ap.sub <= decode.io.i0_ap.sub @[el2_dec.scala 396:40] + io.i0_ap.add <= decode.io.i0_ap.add @[el2_dec.scala 396:40] + io.i0_ap.bge <= decode.io.i0_ap.bge @[el2_dec.scala 396:40] + io.i0_ap.blt <= decode.io.i0_ap.blt @[el2_dec.scala 396:40] + io.i0_ap.bne <= decode.io.i0_ap.bne @[el2_dec.scala 396:40] + io.i0_ap.beq <= decode.io.i0_ap.beq @[el2_dec.scala 396:40] + io.i0_ap.sra <= decode.io.i0_ap.sra @[el2_dec.scala 396:40] + io.i0_ap.srl <= decode.io.i0_ap.srl @[el2_dec.scala 396:40] + io.i0_ap.sll <= decode.io.i0_ap.sll @[el2_dec.scala 396:40] + io.i0_ap.lxor <= decode.io.i0_ap.lxor @[el2_dec.scala 396:40] + io.i0_ap.lor <= decode.io.i0_ap.lor @[el2_dec.scala 396:40] + io.i0_ap.land <= decode.io.i0_ap.land @[el2_dec.scala 396:40] + io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[el2_dec.scala 397:40] + io.dec_i0_alu_decode_d <= decode.io.dec_i0_alu_decode_d @[el2_dec.scala 398:40] + io.dec_i0_rs1_bypass_data_d <= decode.io.dec_i0_rs1_bypass_data_d @[el2_dec.scala 399:40] + io.dec_i0_rs2_bypass_data_d <= decode.io.dec_i0_rs2_bypass_data_d @[el2_dec.scala 400:40] + io.dec_i0_select_pc_d <= decode.io.dec_i0_select_pc_d @[el2_dec.scala 401:40] + io.dec_i0_rs1_bypass_en_d <= decode.io.dec_i0_rs1_bypass_en_d @[el2_dec.scala 402:40] + io.dec_i0_rs2_bypass_en_d <= decode.io.dec_i0_rs2_bypass_en_d @[el2_dec.scala 403:40] + io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[el2_dec.scala 404:40] + io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[el2_dec.scala 404:40] + io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[el2_dec.scala 404:40] + io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[el2_dec.scala 404:40] + io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[el2_dec.scala 404:40] + io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[el2_dec.scala 404:40] + io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[el2_dec.scala 404:40] + io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[el2_dec.scala 404:40] + io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[el2_dec.scala 404:40] + io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[el2_dec.scala 404:40] + io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[el2_dec.scala 404:40] + io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[el2_dec.scala 404:40] + io.lsu_p.valid <= decode.io.lsu_p.valid @[el2_dec.scala 404:40] + io.mul_p.bits.bfp <= decode.io.mul_p.bits.bfp @[el2_dec.scala 405:40] + io.mul_p.bits.crc32c_w <= decode.io.mul_p.bits.crc32c_w @[el2_dec.scala 405:40] + io.mul_p.bits.crc32c_h <= decode.io.mul_p.bits.crc32c_h @[el2_dec.scala 405:40] + io.mul_p.bits.crc32c_b <= decode.io.mul_p.bits.crc32c_b @[el2_dec.scala 405:40] + io.mul_p.bits.crc32_w <= decode.io.mul_p.bits.crc32_w @[el2_dec.scala 405:40] + io.mul_p.bits.crc32_h <= decode.io.mul_p.bits.crc32_h @[el2_dec.scala 405:40] + io.mul_p.bits.crc32_b <= decode.io.mul_p.bits.crc32_b @[el2_dec.scala 405:40] + io.mul_p.bits.unshfl <= decode.io.mul_p.bits.unshfl @[el2_dec.scala 405:40] + io.mul_p.bits.shfl <= decode.io.mul_p.bits.shfl @[el2_dec.scala 405:40] + io.mul_p.bits.grev <= decode.io.mul_p.bits.grev @[el2_dec.scala 405:40] + io.mul_p.bits.clmulr <= decode.io.mul_p.bits.clmulr @[el2_dec.scala 405:40] + io.mul_p.bits.clmulh <= decode.io.mul_p.bits.clmulh @[el2_dec.scala 405:40] + io.mul_p.bits.clmul <= decode.io.mul_p.bits.clmul @[el2_dec.scala 405:40] + io.mul_p.bits.bdep <= decode.io.mul_p.bits.bdep @[el2_dec.scala 405:40] + io.mul_p.bits.bext <= decode.io.mul_p.bits.bext @[el2_dec.scala 405:40] + io.mul_p.bits.low <= decode.io.mul_p.bits.low @[el2_dec.scala 405:40] + io.mul_p.bits.rs2_sign <= decode.io.mul_p.bits.rs2_sign @[el2_dec.scala 405:40] + io.mul_p.bits.rs1_sign <= decode.io.mul_p.bits.rs1_sign @[el2_dec.scala 405:40] + io.mul_p.valid <= decode.io.mul_p.valid @[el2_dec.scala 405:40] + io.div_p.bits.rem <= decode.io.div_p.bits.rem @[el2_dec.scala 406:40] + io.div_p.bits.unsign <= decode.io.div_p.bits.unsign @[el2_dec.scala 406:40] + io.div_p.valid <= decode.io.div_p.valid @[el2_dec.scala 406:40] + io.dec_div_cancel <= decode.io.dec_div_cancel @[el2_dec.scala 407:40] + io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[el2_dec.scala 408:40] + io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[el2_dec.scala 409:40] + io.dec_csr_ren_d <= decode.io.dec_csr_ren_d @[el2_dec.scala 410:40] + io.pred_correct_npc_x <= decode.io.pred_correct_npc_x @[el2_dec.scala 411:40] + io.dec_i0_predict_p_d.bits.way <= decode.io.dec_i0_predict_p_d.bits.way @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.pja <= decode.io.dec_i0_predict_p_d.bits.pja @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.pret <= decode.io.dec_i0_predict_p_d.bits.pret @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.pcall <= decode.io.dec_i0_predict_p_d.bits.pcall @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.prett <= decode.io.dec_i0_predict_p_d.bits.prett @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.br_start_error <= decode.io.dec_i0_predict_p_d.bits.br_start_error @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.br_error <= decode.io.dec_i0_predict_p_d.bits.br_error @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.toffset <= decode.io.dec_i0_predict_p_d.bits.toffset @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.hist <= decode.io.dec_i0_predict_p_d.bits.hist @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.pc4 <= decode.io.dec_i0_predict_p_d.bits.pc4 @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.boffset <= decode.io.dec_i0_predict_p_d.bits.boffset @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.ataken <= decode.io.dec_i0_predict_p_d.bits.ataken @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.misp <= decode.io.dec_i0_predict_p_d.bits.misp @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.valid <= decode.io.dec_i0_predict_p_d.valid @[el2_dec.scala 412:40] + io.i0_predict_fghr_d <= decode.io.i0_predict_fghr_d @[el2_dec.scala 413:40] + io.i0_predict_index_d <= decode.io.i0_predict_index_d @[el2_dec.scala 414:40] + io.i0_predict_btag_d <= decode.io.i0_predict_btag_d @[el2_dec.scala 415:40] + io.dec_data_en <= decode.io.dec_data_en @[el2_dec.scala 416:40] + io.dec_ctl_en <= decode.io.dec_ctl_en @[el2_dec.scala 417:40] + io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[el2_dec.scala 418:40] + gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[el2_dec.scala 425:23] + gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[el2_dec.scala 426:23] + gpr.io.wen0 <= decode.io.dec_i0_wen_r @[el2_dec.scala 427:23] + gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[el2_dec.scala 428:23] + gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[el2_dec.scala 429:23] + gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[el2_dec.scala 430:23] + gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[el2_dec.scala 431:23] + gpr.io.wd1 <= io.lsu_nonblock_load_data @[el2_dec.scala 432:23] + gpr.io.wen2 <= io.exu_div_wren @[el2_dec.scala 433:23] + gpr.io.waddr2 <= decode.io.div_waddr_wb @[el2_dec.scala 434:23] + gpr.io.wd2 <= io.exu_div_result @[el2_dec.scala 435:23] + gpr.io.scan_mode <= io.scan_mode @[el2_dec.scala 438:23] + io.gpr_i0_rs1_d <= gpr.io.rd0 @[el2_dec.scala 440:19] + io.gpr_i0_rs2_d <= gpr.io.rd1 @[el2_dec.scala 441:19] + tlu.io.active_clk <= io.active_clk @[el2_dec.scala 450:45] + tlu.io.free_clk <= io.free_clk @[el2_dec.scala 451:45] + tlu.io.scan_mode <= io.scan_mode @[el2_dec.scala 453:45] + tlu.io.rst_vec <= io.rst_vec @[el2_dec.scala 454:45] + tlu.io.nmi_int <= io.nmi_int @[el2_dec.scala 455:45] + tlu.io.nmi_vec <= io.nmi_vec @[el2_dec.scala 456:45] + tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[el2_dec.scala 457:45] + tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[el2_dec.scala 458:45] + tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[el2_dec.scala 459:45] + tlu.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[el2_dec.scala 460:45] + tlu.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[el2_dec.scala 461:45] + tlu.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[el2_dec.scala 462:45] + tlu.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[el2_dec.scala 463:45] + tlu.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[el2_dec.scala 464:45] + tlu.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[el2_dec.scala 465:45] + tlu.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[el2_dec.scala 466:45] + tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[el2_dec.scala 467:45] + tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[el2_dec.scala 468:45] + tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[el2_dec.scala 469:45] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[el2_dec.scala 470:45] + tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec.scala 471:45] + tlu.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec.scala 472:45] + tlu.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[el2_dec.scala 473:45] + tlu.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[el2_dec.scala 474:45] + tlu.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[el2_dec.scala 475:45] + tlu.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[el2_dec.scala 476:45] + tlu.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[el2_dec.scala 477:45] + tlu.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[el2_dec.scala 478:45] + tlu.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[el2_dec.scala 479:45] + tlu.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[el2_dec.scala 480:45] + tlu.io.lsu_pmu_load_external_m <= io.lsu_pmu_load_external_m @[el2_dec.scala 481:45] + tlu.io.lsu_pmu_store_external_m <= io.lsu_pmu_store_external_m @[el2_dec.scala 482:45] + tlu.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[el2_dec.scala 483:45] + tlu.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[el2_dec.scala 484:45] + tlu.io.dma_pmu_any_read <= io.dma_pmu_any_read @[el2_dec.scala 485:45] + tlu.io.dma_pmu_any_write <= io.dma_pmu_any_write @[el2_dec.scala 486:45] + tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[el2_dec.scala 487:45] + tlu.io.lsu_fir_error <= io.lsu_fir_error @[el2_dec.scala 488:45] + tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[el2_dec.scala 489:45] + tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[el2_dec.scala 490:45] + tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[el2_dec.scala 490:45] + tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[el2_dec.scala 490:45] + tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[el2_dec.scala 490:45] + tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[el2_dec.scala 490:45] + tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[el2_dec.scala 490:45] + tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[el2_dec.scala 491:45] + tlu.io.dec_pause_state <= decode.io.dec_pause_state @[el2_dec.scala 492:45] + tlu.io.lsu_imprecise_error_store_any <= io.lsu_imprecise_error_store_any @[el2_dec.scala 493:45] + tlu.io.lsu_imprecise_error_load_any <= io.lsu_imprecise_error_load_any @[el2_dec.scala 494:45] + tlu.io.lsu_imprecise_error_addr_any <= io.lsu_imprecise_error_addr_any @[el2_dec.scala 495:45] + tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[el2_dec.scala 496:45] + tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[el2_dec.scala 497:45] + tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[el2_dec.scala 498:45] + tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[el2_dec.scala 499:45] + tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[el2_dec.scala 500:45] + tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[el2_dec.scala 501:45] + tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[el2_dec.scala 502:45] + tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[el2_dec.scala 503:45] + tlu.io.exu_npc_r <= io.exu_npc_r @[el2_dec.scala 504:45] + tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[el2_dec.scala 505:45] + tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[el2_dec.scala 506:45] + tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[el2_dec.scala 507:45] + tlu.io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[el2_dec.scala 508:45] + tlu.io.exu_i0_br_hist_r <= io.exu_i0_br_hist_r @[el2_dec.scala 509:45] + tlu.io.exu_i0_br_error_r <= io.exu_i0_br_error_r @[el2_dec.scala 510:45] + tlu.io.exu_i0_br_start_error_r <= io.exu_i0_br_start_error_r @[el2_dec.scala 511:45] + tlu.io.exu_i0_br_valid_r <= io.exu_i0_br_valid_r @[el2_dec.scala 512:45] + tlu.io.exu_i0_br_mp_r <= io.exu_i0_br_mp_r @[el2_dec.scala 513:45] + tlu.io.exu_i0_br_middle_r <= io.exu_i0_br_middle_r @[el2_dec.scala 514:45] + tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[el2_dec.scala 515:45] + tlu.io.dbg_halt_req <= io.dbg_halt_req @[el2_dec.scala 516:45] + tlu.io.dbg_resume_req <= io.dbg_resume_req @[el2_dec.scala 517:45] + tlu.io.ifu_miss_state_idle <= io.ifu_miss_state_idle @[el2_dec.scala 518:45] + tlu.io.lsu_idle_any <= io.lsu_idle_any @[el2_dec.scala 519:45] + tlu.io.dec_div_active <= decode.io.dec_div_active @[el2_dec.scala 520:45] + tlu.io.ifu_ic_error_start <= io.ifu_ic_error_start @[el2_dec.scala 521:45] + tlu.io.ifu_iccm_rd_ecc_single_err <= io.ifu_iccm_rd_ecc_single_err @[el2_dec.scala 522:45] + tlu.io.ifu_ic_debug_rd_data <= io.ifu_ic_debug_rd_data @[el2_dec.scala 523:45] + tlu.io.ifu_ic_debug_rd_data_valid <= io.ifu_ic_debug_rd_data_valid @[el2_dec.scala 524:45] + tlu.io.pic_claimid <= io.pic_claimid @[el2_dec.scala 525:45] + tlu.io.pic_pl <= io.pic_pl @[el2_dec.scala 526:45] + tlu.io.mhwakeup <= io.mhwakeup @[el2_dec.scala 527:45] + tlu.io.mexintpend <= io.mexintpend @[el2_dec.scala 528:45] + tlu.io.timer_int <= io.timer_int @[el2_dec.scala 529:45] + tlu.io.soft_int <= io.soft_int @[el2_dec.scala 530:45] + tlu.io.core_id <= io.core_id @[el2_dec.scala 531:45] + tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[el2_dec.scala 532:45] + tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[el2_dec.scala 533:45] + tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec.scala 534:45] + io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[el2_dec.scala 536:28] + io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[el2_dec.scala 537:28] + io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[el2_dec.scala 538:28] + io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[el2_dec.scala 539:28] + io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[el2_dec.scala 540:28] + io.dec_tlu_flush_noredir_r <= tlu.io.dec_tlu_flush_noredir_r @[el2_dec.scala 541:34] + io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[el2_dec.scala 542:34] + io.dec_tlu_flush_leak_one_r <= tlu.io.dec_tlu_flush_leak_one_r @[el2_dec.scala 543:34] + io.dec_tlu_flush_err_r <= tlu.io.dec_tlu_flush_err_r @[el2_dec.scala 544:34] + io.dec_tlu_meihap <= tlu.io.dec_tlu_meihap @[el2_dec.scala 545:29] + io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 546:29] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec.scala 547:29] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec.scala 547:29] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_dec.scala 547:29] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_dec.scala 547:29] + io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[el2_dec.scala 548:29] + io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[el2_dec.scala 549:29] + io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[el2_dec.scala 550:29] + io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[el2_dec.scala 551:29] + io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[el2_dec.scala 552:29] + io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[el2_dec.scala 553:29] + io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[el2_dec.scala 554:29] + io.dec_tlu_meicurpl <= tlu.io.dec_tlu_meicurpl @[el2_dec.scala 555:29] + io.dec_tlu_meipt <= tlu.io.dec_tlu_meipt @[el2_dec.scala 556:29] + io.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.dec_tlu_br0_r_pkt.bits.middle @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.bits.way <= tlu.io.dec_tlu_br0_r_pkt.bits.way @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_error @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.dec_tlu_br0_r_pkt.bits.hist @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.valid <= tlu.io.dec_tlu_br0_r_pkt.valid @[el2_dec.scala 557:42] + io.dec_tlu_i0_commit_cmt <= tlu.io.dec_tlu_i0_commit_cmt @[el2_dec.scala 558:34] + io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 559:34] + io.dec_tlu_flush_lower_r <= tlu.io.dec_tlu_flush_lower_r @[el2_dec.scala 560:34] + io.dec_tlu_flush_path_r <= tlu.io.dec_tlu_flush_path_r @[el2_dec.scala 561:34] + io.dec_tlu_fence_i_r <= tlu.io.dec_tlu_fence_i_r @[el2_dec.scala 562:34] + io.dec_tlu_mrac_ff <= tlu.io.dec_tlu_mrac_ff @[el2_dec.scala 563:29] + io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 564:29] + io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[el2_dec.scala 565:29] + io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[el2_dec.scala 566:29] + io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[el2_dec.scala 567:29] + io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[el2_dec.scala 568:29] + dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[el2_dec.scala 569:32] + dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[el2_dec.scala 570:32] + dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[el2_dec.scala 571:32] + dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[el2_dec.scala 572:32] + dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[el2_dec.scala 573:32] + io.dec_tlu_external_ldfwd_disable <= tlu.io.dec_tlu_external_ldfwd_disable @[el2_dec.scala 574:43] + io.dec_tlu_sideeffect_posted_disable <= tlu.io.dec_tlu_sideeffect_posted_disable @[el2_dec.scala 575:43] + io.dec_tlu_core_ecc_disable <= tlu.io.dec_tlu_core_ecc_disable @[el2_dec.scala 576:43] + io.dec_tlu_bpred_disable <= tlu.io.dec_tlu_bpred_disable @[el2_dec.scala 577:43] + io.dec_tlu_wb_coalescing_disable <= tlu.io.dec_tlu_wb_coalescing_disable @[el2_dec.scala 578:43] + io.dec_tlu_dma_qos_prty <= tlu.io.dec_tlu_dma_qos_prty @[el2_dec.scala 579:35] + io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[el2_dec.scala 580:35] + io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[el2_dec.scala 581:36] + io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[el2_dec.scala 582:36] + io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[el2_dec.scala 583:36] + io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[el2_dec.scala 584:36] + io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[el2_dec.scala 585:36] + io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[el2_dec.scala 586:36] + io.rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb1 @[el2_dec.scala 590:32] node _T = cat(decode.io.dec_i0_pc_wb1, UInt<1>("h00")) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_address_ip <= _T @[el2_dec.scala 708:35] - node _T_1 = or(tlu.io.dec_tlu_i0_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[el2_dec.scala 709:98] + io.rv_trace_pkt.rv_i_address_ip <= _T @[el2_dec.scala 591:35] + node _T_1 = or(tlu.io.dec_tlu_i0_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[el2_dec.scala 592:98] node _T_2 = cat(tlu.io.dec_tlu_int_valid_wb1, _T_1) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_valid_ip <= _T_2 @[el2_dec.scala 709:33] + io.rv_trace_pkt.rv_i_valid_ip <= _T_2 @[el2_dec.scala 592:33] node _T_3 = cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_exception_ip <= _T_3 @[el2_dec.scala 710:37] - node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[el2_dec.scala 711:65] - io.rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[el2_dec.scala 711:34] + io.rv_trace_pkt.rv_i_exception_ip <= _T_3 @[el2_dec.scala 593:37] + node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[el2_dec.scala 594:65] + io.rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[el2_dec.scala 594:34] node _T_5 = cat(tlu.io.dec_tlu_int_valid_wb1, UInt<1>("h00")) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_interrupt_ip <= _T_5 @[el2_dec.scala 712:37] - io.rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[el2_dec.scala 713:32] - io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[el2_dec.scala 717:21] + io.rv_trace_pkt.rv_i_interrupt_ip <= _T_5 @[el2_dec.scala 595:37] + io.rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[el2_dec.scala 596:32] + io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[el2_dec.scala 600:21] extmodule gated_latch_755 : output Q : Clock @@ -109559,7 +109492,7 @@ circuit el2_swerv_wrapper : input reset : AsyncReset output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, trace_rv_i_insn_ip : UInt<32>, trace_rv_i_address_ip : UInt<32>, trace_rv_i_valid_ip : UInt<2>, trace_rv_i_exception_ip : UInt<2>, trace_rv_i_ecause_ip : UInt<5>, trace_rv_i_interrupt_ip : UInt<2>, trace_rv_i_tval_ip : UInt<32>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rlast : UInt<1>, ifu_axi_awvalid : UInt<1>, flip ifu_axi_awready : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, flip ifu_axi_wready : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, flip ifu_axi_bvalid : UInt<1>, ifu_axi_bready : UInt<1>, flip ifu_axi_bresp : UInt<2>, flip ifu_axi_bid : UInt<3>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_axi_rlast : UInt<1>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, flip sb_axi_bid : UInt<1>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rid : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip sb_axi_rlast : UInt<1>, flip dma_axi_awvalid : UInt<1>, dma_axi_awready : UInt<1>, flip dma_axi_awid : UInt<1>, flip dma_axi_awaddr : UInt<32>, flip dma_axi_awsize : UInt<3>, flip dma_axi_awprot : UInt<3>, flip dma_axi_awlen : UInt<8>, flip dma_axi_awburst : UInt<2>, flip dma_axi_wvalid : UInt<1>, dma_axi_wready : UInt<1>, flip dma_axi_wdata : UInt<64>, flip dma_axi_wstrb : UInt<8>, flip dma_axi_wlast : UInt<1>, dma_axi_bvalid : UInt<1>, flip dma_axi_bready : UInt<1>, dma_axi_bresp : UInt<2>, dma_axi_bid : UInt<1>, flip dma_axi_arvalid : UInt<1>, dma_axi_arready : UInt<1>, flip dma_axi_arid : UInt<1>, flip dma_axi_araddr : UInt<32>, flip dma_axi_arsize : UInt<3>, flip dma_axi_arprot : UInt<3>, flip dma_axi_arlen : UInt<8>, flip dma_axi_arburst : UInt<2>, dma_axi_rvalid : UInt<1>, flip dma_axi_rready : UInt<1>, dma_axi_rid : UInt<1>, dma_axi_rdata : UInt<64>, dma_axi_rresp : UInt<2>, dma_axi_rlast : UInt<1>, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, flip scan_mode : UInt<1>} - inst mem of el2_mem @[SweRV_Wrapper.scala 345:19] + inst mem of el2_mem @[el2_swerv_wrapper.scala 345:19] mem.iccm_rd_data is invalid mem.ic_debug_rd_data is invalid mem.ic_tag_perr is invalid @@ -109605,7 +109538,7 @@ circuit el2_swerv_wrapper : mem.dccm_clk_override is invalid mem.rst_l is invalid mem.clk is invalid - inst dmi_wrapper of dmi_wrapper @[SweRV_Wrapper.scala 346:27] + inst dmi_wrapper of dmi_wrapper @[el2_swerv_wrapper.scala 346:27] dmi_wrapper.dmi_hard_reset is invalid dmi_wrapper.reg_wr_en is invalid dmi_wrapper.reg_en is invalid @@ -109621,274 +109554,274 @@ circuit el2_swerv_wrapper : dmi_wrapper.tms is invalid dmi_wrapper.tck is invalid dmi_wrapper.trst_n is invalid - inst swerv of el2_swerv @[SweRV_Wrapper.scala 347:21] + inst swerv of el2_swerv @[el2_swerv_wrapper.scala 347:21] swerv.clock <= clock swerv.reset <= reset - dmi_wrapper.trst_n <= io.jtag_trst_n @[SweRV_Wrapper.scala 348:25] - dmi_wrapper.tck <= io.jtag_tck @[SweRV_Wrapper.scala 349:22] - dmi_wrapper.tms <= io.jtag_tms @[SweRV_Wrapper.scala 350:22] - dmi_wrapper.tdi <= io.jtag_tdi @[SweRV_Wrapper.scala 351:22] - dmi_wrapper.core_clk <= clock @[SweRV_Wrapper.scala 352:27] - dmi_wrapper.jtag_id <= io.jtag_id @[SweRV_Wrapper.scala 353:26] - dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[SweRV_Wrapper.scala 354:26] - dmi_wrapper.core_rst_n <= io.dbg_rst_l @[SweRV_Wrapper.scala 357:29] - swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[SweRV_Wrapper.scala 358:26] - swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[SweRV_Wrapper.scala 359:25] - swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[SweRV_Wrapper.scala 360:23] - swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[SweRV_Wrapper.scala 361:26] - swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[SweRV_Wrapper.scala 362:27] - io.jtag_tdo <= dmi_wrapper.tdo @[SweRV_Wrapper.scala 363:15] - mem.dccm_clk_override <= swerv.io.dccm_clk_override @[SweRV_Wrapper.scala 366:28] - mem.icm_clk_override <= swerv.io.icm_clk_override @[SweRV_Wrapper.scala 367:27] - mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[SweRV_Wrapper.scala 368:35] - mem.dccm_wren <= swerv.io.dccm_wren @[SweRV_Wrapper.scala 369:20] - mem.dccm_rden <= swerv.io.dccm_rden @[SweRV_Wrapper.scala 370:20] - mem.dccm_wr_addr_lo <= swerv.io.dccm_wr_addr_lo @[SweRV_Wrapper.scala 371:26] - mem.dccm_wr_addr_hi <= swerv.io.dccm_wr_addr_hi @[SweRV_Wrapper.scala 372:26] - mem.dccm_rd_addr_lo <= swerv.io.dccm_rd_addr_lo @[SweRV_Wrapper.scala 373:26] - mem.dccm_wr_data_lo <= swerv.io.dccm_wr_data_lo @[SweRV_Wrapper.scala 375:26] - mem.dccm_wr_data_hi <= swerv.io.dccm_wr_data_hi @[SweRV_Wrapper.scala 376:26] - swerv.io.dccm_rd_data_lo <= mem.dccm_rd_data_lo @[SweRV_Wrapper.scala 377:28] - mem.dccm_rd_addr_hi <= swerv.io.dccm_rd_addr_hi @[SweRV_Wrapper.scala 378:26] - mem.iccm_rw_addr <= swerv.io.iccm_rw_addr @[SweRV_Wrapper.scala 379:23] - mem.iccm_buf_correct_ecc <= swerv.io.iccm_buf_correct_ecc @[SweRV_Wrapper.scala 380:31] - mem.iccm_correction_state <= swerv.io.iccm_correction_state @[SweRV_Wrapper.scala 381:32] - mem.iccm_wren <= swerv.io.iccm_wren @[SweRV_Wrapper.scala 382:20] - mem.iccm_rden <= swerv.io.iccm_rden @[SweRV_Wrapper.scala 383:20] - mem.iccm_wr_size <= swerv.io.iccm_wr_size @[SweRV_Wrapper.scala 384:23] - mem.iccm_wr_data <= swerv.io.iccm_wr_data @[SweRV_Wrapper.scala 385:23] - mem.ic_rw_addr <= swerv.io.ic_rw_addr @[SweRV_Wrapper.scala 388:21] - mem.ic_tag_valid <= swerv.io.ic_tag_valid @[SweRV_Wrapper.scala 389:23] - mem.ic_wr_en <= swerv.io.ic_wr_en @[SweRV_Wrapper.scala 390:19] - mem.ic_rd_en <= swerv.io.ic_rd_en @[SweRV_Wrapper.scala 391:19] - mem.ic_premux_data <= swerv.io.ic_premux_data @[SweRV_Wrapper.scala 392:25] - mem.ic_sel_premux_data <= swerv.io.ic_sel_premux_data @[SweRV_Wrapper.scala 393:29] - mem.ic_wr_data[0] <= swerv.io.ic_wr_data[0] @[SweRV_Wrapper.scala 394:21] - mem.ic_wr_data[1] <= swerv.io.ic_wr_data[1] @[SweRV_Wrapper.scala 394:21] - mem.ic_debug_wr_data <= swerv.io.ic_debug_wr_data @[SweRV_Wrapper.scala 395:27] - mem.ic_debug_addr <= swerv.io.ic_debug_addr @[SweRV_Wrapper.scala 397:24] - mem.ic_debug_rd_en <= swerv.io.ic_debug_rd_en @[SweRV_Wrapper.scala 398:25] - mem.ic_debug_wr_en <= swerv.io.ic_debug_wr_en @[SweRV_Wrapper.scala 399:25] - mem.ic_debug_tag_array <= swerv.io.ic_debug_tag_array @[SweRV_Wrapper.scala 400:29] - mem.ic_debug_way <= swerv.io.ic_debug_way @[SweRV_Wrapper.scala 401:23] - mem.rst_l <= reset @[SweRV_Wrapper.scala 402:16] - mem.clk <= clock @[SweRV_Wrapper.scala 403:14] - mem.scan_mode <= io.scan_mode @[SweRV_Wrapper.scala 404:20] - swerv.io.dbg_rst_l <= io.dbg_rst_l @[SweRV_Wrapper.scala 406:22] - swerv.io.iccm_rd_data_ecc <= mem.iccm_rd_data_ecc @[SweRV_Wrapper.scala 407:29] - swerv.io.dccm_rd_data_hi <= mem.dccm_rd_data_hi @[SweRV_Wrapper.scala 408:28] - swerv.io.ic_rd_data <= mem.ic_rd_data @[SweRV_Wrapper.scala 409:23] - swerv.io.ictag_debug_rd_data <= mem.ictag_debug_rd_data @[SweRV_Wrapper.scala 410:32] - swerv.io.ic_eccerr <= mem.ic_eccerr @[SweRV_Wrapper.scala 411:22] - swerv.io.ic_parerr <= mem.ic_parerr @[SweRV_Wrapper.scala 412:22] - swerv.io.ic_rd_hit <= mem.ic_rd_hit @[SweRV_Wrapper.scala 413:22] - swerv.io.ic_tag_perr <= mem.ic_tag_perr @[SweRV_Wrapper.scala 414:24] - swerv.io.ic_debug_rd_data <= mem.ic_debug_rd_data @[SweRV_Wrapper.scala 415:29] - swerv.io.iccm_rd_data <= mem.iccm_rd_data @[SweRV_Wrapper.scala 416:25] - swerv.io.sb_hready <= UInt<1>("h00") @[SweRV_Wrapper.scala 417:22] - swerv.io.hrdata <= UInt<1>("h00") @[SweRV_Wrapper.scala 418:19] - swerv.io.sb_hresp <= UInt<1>("h00") @[SweRV_Wrapper.scala 419:21] - swerv.io.lsu_hrdata <= UInt<1>("h00") @[SweRV_Wrapper.scala 420:23] - swerv.io.lsu_hresp <= UInt<1>("h00") @[SweRV_Wrapper.scala 421:22] - swerv.io.lsu_hready <= UInt<1>("h00") @[SweRV_Wrapper.scala 422:23] - swerv.io.hready <= UInt<1>("h00") @[SweRV_Wrapper.scala 423:19] - swerv.io.hresp <= UInt<1>("h00") @[SweRV_Wrapper.scala 424:18] - swerv.io.sb_hrdata <= UInt<1>("h00") @[SweRV_Wrapper.scala 425:22] - swerv.io.scan_mode <= io.scan_mode @[SweRV_Wrapper.scala 426:22] - swerv.io.dbg_rst_l <= io.dbg_rst_l @[SweRV_Wrapper.scala 428:22] - swerv.io.rst_vec <= io.rst_vec @[SweRV_Wrapper.scala 429:20] - swerv.io.nmi_int <= io.nmi_int @[SweRV_Wrapper.scala 430:20] - swerv.io.nmi_vec <= io.nmi_vec @[SweRV_Wrapper.scala 431:20] - swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[SweRV_Wrapper.scala 434:27] - swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[SweRV_Wrapper.scala 435:26] - swerv.io.core_id <= io.core_id @[SweRV_Wrapper.scala 436:20] - swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[SweRV_Wrapper.scala 439:31] - swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[SweRV_Wrapper.scala 440:30] - swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[SweRV_Wrapper.scala 441:30] - swerv.io.lsu_axi_awready <= io.lsu_axi_awready @[SweRV_Wrapper.scala 445:28] - swerv.io.lsu_axi_wready <= io.lsu_axi_wready @[SweRV_Wrapper.scala 446:27] - swerv.io.lsu_axi_bvalid <= io.lsu_axi_bvalid @[SweRV_Wrapper.scala 448:27] - swerv.io.lsu_axi_bresp <= io.lsu_axi_bresp @[SweRV_Wrapper.scala 449:26] - swerv.io.lsu_axi_bid <= io.lsu_axi_bid @[SweRV_Wrapper.scala 450:24] - swerv.io.lsu_axi_arready <= io.lsu_axi_arready @[SweRV_Wrapper.scala 453:28] - swerv.io.lsu_axi_rvalid <= io.lsu_axi_rvalid @[SweRV_Wrapper.scala 454:27] - swerv.io.lsu_axi_rid <= io.lsu_axi_rid @[SweRV_Wrapper.scala 455:24] - swerv.io.lsu_axi_rdata <= io.lsu_axi_rdata @[SweRV_Wrapper.scala 456:26] - swerv.io.lsu_axi_rresp <= io.lsu_axi_rresp @[SweRV_Wrapper.scala 457:26] - swerv.io.lsu_axi_rlast <= io.lsu_axi_rlast @[SweRV_Wrapper.scala 458:26] - swerv.io.ifu_axi_awready <= io.ifu_axi_awready @[SweRV_Wrapper.scala 462:28] - swerv.io.ifu_axi_wready <= io.ifu_axi_wready @[SweRV_Wrapper.scala 463:27] - swerv.io.ifu_axi_bvalid <= io.ifu_axi_bvalid @[SweRV_Wrapper.scala 464:27] - swerv.io.ifu_axi_bresp <= io.ifu_axi_bresp @[SweRV_Wrapper.scala 465:26] - swerv.io.ifu_axi_bid <= io.ifu_axi_bid @[SweRV_Wrapper.scala 466:24] - swerv.io.ifu_axi_arready <= io.ifu_axi_arready @[SweRV_Wrapper.scala 469:28] - swerv.io.ifu_axi_rvalid <= io.ifu_axi_rvalid @[SweRV_Wrapper.scala 470:27] - swerv.io.ifu_axi_rid <= io.ifu_axi_rid @[SweRV_Wrapper.scala 471:24] - swerv.io.ifu_axi_rdata <= io.ifu_axi_rdata @[SweRV_Wrapper.scala 472:26] - swerv.io.ifu_axi_rresp <= io.ifu_axi_rresp @[SweRV_Wrapper.scala 473:26] - swerv.io.ifu_axi_rlast <= io.ifu_axi_rlast @[SweRV_Wrapper.scala 474:26] - swerv.io.sb_axi_awready <= io.sb_axi_awready @[SweRV_Wrapper.scala 478:27] - swerv.io.sb_axi_wready <= io.sb_axi_wready @[SweRV_Wrapper.scala 479:26] - swerv.io.sb_axi_bvalid <= io.sb_axi_bvalid @[SweRV_Wrapper.scala 481:26] - swerv.io.sb_axi_bresp <= io.sb_axi_bresp @[SweRV_Wrapper.scala 482:25] - swerv.io.sb_axi_bid <= io.sb_axi_bid @[SweRV_Wrapper.scala 483:23] - swerv.io.sb_axi_arready <= io.sb_axi_arready @[SweRV_Wrapper.scala 486:27] - swerv.io.sb_axi_rvalid <= io.sb_axi_rvalid @[SweRV_Wrapper.scala 487:26] - swerv.io.sb_axi_rid <= io.sb_axi_rid @[SweRV_Wrapper.scala 488:23] - swerv.io.sb_axi_rdata <= io.sb_axi_rdata @[SweRV_Wrapper.scala 489:25] - swerv.io.sb_axi_rresp <= io.sb_axi_rresp @[SweRV_Wrapper.scala 490:25] - swerv.io.sb_axi_rlast <= io.sb_axi_rlast @[SweRV_Wrapper.scala 491:25] - swerv.io.dma_axi_awvalid <= io.dma_axi_awvalid @[SweRV_Wrapper.scala 495:28] - swerv.io.dma_axi_awid <= io.dma_axi_awid @[SweRV_Wrapper.scala 496:25] - swerv.io.dma_axi_awaddr <= io.dma_axi_awaddr @[SweRV_Wrapper.scala 497:27] - swerv.io.dma_axi_awsize <= io.dma_axi_awsize @[SweRV_Wrapper.scala 498:27] - swerv.io.dma_axi_awprot <= io.dma_axi_awprot @[SweRV_Wrapper.scala 499:27] - swerv.io.dma_axi_awlen <= io.dma_axi_awlen @[SweRV_Wrapper.scala 500:26] - swerv.io.dma_axi_awburst <= io.dma_axi_awburst @[SweRV_Wrapper.scala 501:28] - swerv.io.dma_axi_wvalid <= io.dma_axi_wvalid @[SweRV_Wrapper.scala 503:27] - swerv.io.dma_axi_wdata <= io.dma_axi_wdata @[SweRV_Wrapper.scala 504:26] - swerv.io.dma_axi_wstrb <= io.dma_axi_wstrb @[SweRV_Wrapper.scala 505:26] - swerv.io.dma_axi_wlast <= io.dma_axi_wlast @[SweRV_Wrapper.scala 506:26] - swerv.io.dma_axi_bready <= io.dma_axi_bready @[SweRV_Wrapper.scala 507:27] - swerv.io.dma_axi_arvalid <= io.dma_axi_arvalid @[SweRV_Wrapper.scala 510:28] - swerv.io.dma_axi_arid <= io.dma_axi_arid @[SweRV_Wrapper.scala 511:25] - swerv.io.dma_axi_araddr <= io.dma_axi_araddr @[SweRV_Wrapper.scala 512:27] - swerv.io.dma_axi_arsize <= io.dma_axi_arsize @[SweRV_Wrapper.scala 513:27] - swerv.io.dma_axi_arprot <= io.dma_axi_arprot @[SweRV_Wrapper.scala 514:27] - swerv.io.dma_axi_arlen <= io.dma_axi_arlen @[SweRV_Wrapper.scala 515:26] - swerv.io.dma_axi_arburst <= io.dma_axi_arburst @[SweRV_Wrapper.scala 516:28] - swerv.io.dma_axi_rready <= io.dma_axi_rready @[SweRV_Wrapper.scala 517:27] - swerv.io.dma_hsel <= io.dma_hsel @[SweRV_Wrapper.scala 520:21] - swerv.io.dma_haddr <= io.dma_haddr @[SweRV_Wrapper.scala 521:22] - swerv.io.dma_hburst <= io.dma_hburst @[SweRV_Wrapper.scala 522:23] - swerv.io.dma_hmastlock <= io.dma_hmastlock @[SweRV_Wrapper.scala 523:26] - swerv.io.dma_hprot <= io.dma_hprot @[SweRV_Wrapper.scala 524:22] - swerv.io.dma_hsize <= io.dma_hsize @[SweRV_Wrapper.scala 525:22] - swerv.io.dma_htrans <= io.dma_htrans @[SweRV_Wrapper.scala 526:23] - swerv.io.dma_hwrite <= io.dma_hwrite @[SweRV_Wrapper.scala 527:23] - swerv.io.dma_hwdata <= io.dma_hwdata @[SweRV_Wrapper.scala 528:23] - swerv.io.dma_hreadyin <= io.dma_hreadyin @[SweRV_Wrapper.scala 529:25] - swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[SweRV_Wrapper.scala 547:27] - swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[SweRV_Wrapper.scala 548:27] - swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[SweRV_Wrapper.scala 549:27] - swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[SweRV_Wrapper.scala 550:27] - swerv.io.timer_int <= io.timer_int @[SweRV_Wrapper.scala 552:22] - swerv.io.soft_int <= io.soft_int @[SweRV_Wrapper.scala 553:21] - swerv.io.extintsrc_req <= io.extintsrc_req @[SweRV_Wrapper.scala 554:26] - io.trace_rv_i_insn_ip <= swerv.io.trace_rv_i_insn_ip @[SweRV_Wrapper.scala 558:25] - io.trace_rv_i_address_ip <= swerv.io.trace_rv_i_address_ip @[SweRV_Wrapper.scala 559:28] - io.trace_rv_i_valid_ip <= swerv.io.trace_rv_i_valid_ip @[SweRV_Wrapper.scala 560:26] - io.trace_rv_i_exception_ip <= swerv.io.trace_rv_i_exception_ip @[SweRV_Wrapper.scala 561:30] - io.trace_rv_i_ecause_ip <= swerv.io.trace_rv_i_ecause_ip @[SweRV_Wrapper.scala 562:27] - io.trace_rv_i_interrupt_ip <= swerv.io.trace_rv_i_interrupt_ip @[SweRV_Wrapper.scala 563:30] - io.trace_rv_i_tval_ip <= swerv.io.trace_rv_i_tval_ip @[SweRV_Wrapper.scala 564:25] - io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[SweRV_Wrapper.scala 567:21] - io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[SweRV_Wrapper.scala 568:24] - io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[SweRV_Wrapper.scala 569:20] - io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[SweRV_Wrapper.scala 570:26] - io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[SweRV_Wrapper.scala 572:25] - io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[SweRV_Wrapper.scala 573:24] - io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[SweRV_Wrapper.scala 574:25] - io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[SweRV_Wrapper.scala 576:23] - io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[SweRV_Wrapper.scala 577:23] - io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[SweRV_Wrapper.scala 578:23] - io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[SweRV_Wrapper.scala 579:23] - io.lsu_axi_awvalid <= swerv.io.lsu_axi_awvalid @[SweRV_Wrapper.scala 584:22] - io.lsu_axi_awid <= swerv.io.lsu_axi_awid @[SweRV_Wrapper.scala 585:19] - io.lsu_axi_awaddr <= swerv.io.lsu_axi_awaddr @[SweRV_Wrapper.scala 586:21] - io.lsu_axi_awregion <= swerv.io.lsu_axi_awregion @[SweRV_Wrapper.scala 587:23] - io.lsu_axi_awlen <= swerv.io.lsu_axi_awlen @[SweRV_Wrapper.scala 588:20] - io.lsu_axi_awsize <= swerv.io.lsu_axi_awsize @[SweRV_Wrapper.scala 589:21] - io.lsu_axi_awburst <= swerv.io.lsu_axi_awburst @[SweRV_Wrapper.scala 590:22] - io.lsu_axi_awlock <= swerv.io.lsu_axi_awlock @[SweRV_Wrapper.scala 591:21] - io.lsu_axi_awcache <= swerv.io.lsu_axi_awcache @[SweRV_Wrapper.scala 592:22] - io.lsu_axi_awprot <= swerv.io.lsu_axi_awprot @[SweRV_Wrapper.scala 593:21] - io.lsu_axi_awqos <= swerv.io.lsu_axi_awqos @[SweRV_Wrapper.scala 594:20] - io.lsu_axi_wvalid <= swerv.io.lsu_axi_wvalid @[SweRV_Wrapper.scala 596:21] - io.lsu_axi_wdata <= swerv.io.lsu_axi_wdata @[SweRV_Wrapper.scala 597:20] - io.lsu_axi_wstrb <= swerv.io.lsu_axi_wstrb @[SweRV_Wrapper.scala 598:20] - io.lsu_axi_wlast <= swerv.io.lsu_axi_wlast @[SweRV_Wrapper.scala 599:20] - io.lsu_axi_bready <= swerv.io.lsu_axi_bready @[SweRV_Wrapper.scala 600:21] - io.lsu_axi_arvalid <= swerv.io.lsu_axi_arvalid @[SweRV_Wrapper.scala 603:22] - io.lsu_axi_arid <= swerv.io.lsu_axi_arid @[SweRV_Wrapper.scala 604:19] - io.lsu_axi_araddr <= swerv.io.lsu_axi_araddr @[SweRV_Wrapper.scala 605:21] - io.lsu_axi_arregion <= swerv.io.lsu_axi_arregion @[SweRV_Wrapper.scala 606:23] - io.lsu_axi_arlen <= swerv.io.lsu_axi_arlen @[SweRV_Wrapper.scala 607:20] - io.lsu_axi_arsize <= swerv.io.lsu_axi_arsize @[SweRV_Wrapper.scala 608:21] - io.lsu_axi_arburst <= swerv.io.lsu_axi_arburst @[SweRV_Wrapper.scala 609:22] - io.lsu_axi_arlock <= swerv.io.lsu_axi_arlock @[SweRV_Wrapper.scala 610:21] - io.lsu_axi_arcache <= swerv.io.lsu_axi_arcache @[SweRV_Wrapper.scala 611:22] - io.lsu_axi_arprot <= swerv.io.lsu_axi_arprot @[SweRV_Wrapper.scala 612:21] - io.lsu_axi_arqos <= swerv.io.lsu_axi_arqos @[SweRV_Wrapper.scala 613:20] - io.lsu_axi_rready <= swerv.io.lsu_axi_rready @[SweRV_Wrapper.scala 614:21] - io.ifu_axi_awvalid <= swerv.io.ifu_axi_awvalid @[SweRV_Wrapper.scala 616:22] - io.ifu_axi_awid <= swerv.io.ifu_axi_awid @[SweRV_Wrapper.scala 617:19] - io.ifu_axi_awaddr <= swerv.io.ifu_axi_awaddr @[SweRV_Wrapper.scala 618:21] - io.ifu_axi_awregion <= swerv.io.ifu_axi_awregion @[SweRV_Wrapper.scala 619:23] - io.ifu_axi_awlen <= swerv.io.ifu_axi_awlen @[SweRV_Wrapper.scala 620:20] - io.ifu_axi_awsize <= swerv.io.ifu_axi_awsize @[SweRV_Wrapper.scala 621:21] - io.ifu_axi_awburst <= swerv.io.ifu_axi_awburst @[SweRV_Wrapper.scala 622:22] - io.ifu_axi_awlock <= swerv.io.ifu_axi_awlock @[SweRV_Wrapper.scala 623:21] - io.ifu_axi_awcache <= swerv.io.ifu_axi_awcache @[SweRV_Wrapper.scala 624:22] - io.ifu_axi_awprot <= swerv.io.ifu_axi_awprot @[SweRV_Wrapper.scala 625:21] - io.ifu_axi_awqos <= swerv.io.ifu_axi_awqos @[SweRV_Wrapper.scala 626:20] - io.ifu_axi_wvalid <= swerv.io.ifu_axi_wvalid @[SweRV_Wrapper.scala 627:21] - io.ifu_axi_wdata <= swerv.io.ifu_axi_wdata @[SweRV_Wrapper.scala 628:20] - io.ifu_axi_wstrb <= swerv.io.ifu_axi_wstrb @[SweRV_Wrapper.scala 629:20] - io.ifu_axi_wlast <= swerv.io.ifu_axi_wlast @[SweRV_Wrapper.scala 630:20] - io.ifu_axi_bready <= swerv.io.ifu_axi_bready @[SweRV_Wrapper.scala 632:21] - io.ifu_axi_arvalid <= swerv.io.ifu_axi_arvalid @[SweRV_Wrapper.scala 635:22] - io.ifu_axi_arid <= swerv.io.ifu_axi_arid @[SweRV_Wrapper.scala 636:19] - io.ifu_axi_araddr <= swerv.io.ifu_axi_araddr @[SweRV_Wrapper.scala 637:21] - io.ifu_axi_arregion <= swerv.io.ifu_axi_arregion @[SweRV_Wrapper.scala 638:23] - io.ifu_axi_arlen <= swerv.io.ifu_axi_arlen @[SweRV_Wrapper.scala 639:20] - io.ifu_axi_arsize <= swerv.io.ifu_axi_arsize @[SweRV_Wrapper.scala 640:21] - io.ifu_axi_arburst <= swerv.io.ifu_axi_arburst @[SweRV_Wrapper.scala 641:22] - io.ifu_axi_arlock <= swerv.io.ifu_axi_arlock @[SweRV_Wrapper.scala 642:21] - io.ifu_axi_arcache <= swerv.io.ifu_axi_arcache @[SweRV_Wrapper.scala 643:22] - io.ifu_axi_arprot <= swerv.io.ifu_axi_arprot @[SweRV_Wrapper.scala 644:21] - io.ifu_axi_arqos <= swerv.io.ifu_axi_arqos @[SweRV_Wrapper.scala 645:20] - io.ifu_axi_rready <= swerv.io.ifu_axi_rready @[SweRV_Wrapper.scala 646:21] - io.sb_axi_awvalid <= swerv.io.sb_axi_awvalid @[SweRV_Wrapper.scala 649:21] - io.sb_axi_awid <= swerv.io.sb_axi_awid @[SweRV_Wrapper.scala 650:18] - io.sb_axi_awaddr <= swerv.io.sb_axi_awaddr @[SweRV_Wrapper.scala 651:20] - io.sb_axi_awregion <= swerv.io.sb_axi_awregion @[SweRV_Wrapper.scala 652:22] - io.sb_axi_awlen <= swerv.io.sb_axi_awlen @[SweRV_Wrapper.scala 653:19] - io.sb_axi_awsize <= swerv.io.sb_axi_awsize @[SweRV_Wrapper.scala 654:20] - io.sb_axi_awburst <= swerv.io.sb_axi_awburst @[SweRV_Wrapper.scala 655:21] - io.sb_axi_awlock <= swerv.io.sb_axi_awlock @[SweRV_Wrapper.scala 656:20] - io.sb_axi_awcache <= swerv.io.sb_axi_awcache @[SweRV_Wrapper.scala 657:21] - io.sb_axi_awprot <= swerv.io.sb_axi_awprot @[SweRV_Wrapper.scala 658:20] - io.sb_axi_awqos <= swerv.io.sb_axi_awqos @[SweRV_Wrapper.scala 659:19] - io.sb_axi_wvalid <= swerv.io.sb_axi_wvalid @[SweRV_Wrapper.scala 661:19] - io.sb_axi_wdata <= swerv.io.sb_axi_wdata @[SweRV_Wrapper.scala 662:19] - io.sb_axi_wstrb <= swerv.io.sb_axi_wstrb @[SweRV_Wrapper.scala 663:19] - io.sb_axi_wlast <= swerv.io.sb_axi_wlast @[SweRV_Wrapper.scala 664:19] - io.sb_axi_bready <= swerv.io.sb_axi_bready @[SweRV_Wrapper.scala 665:20] - io.sb_axi_arvalid <= swerv.io.sb_axi_arvalid @[SweRV_Wrapper.scala 668:21] - io.sb_axi_arid <= swerv.io.sb_axi_arid @[SweRV_Wrapper.scala 669:18] - io.sb_axi_araddr <= swerv.io.sb_axi_araddr @[SweRV_Wrapper.scala 670:20] - io.sb_axi_arregion <= swerv.io.sb_axi_arregion @[SweRV_Wrapper.scala 671:22] - io.sb_axi_arlen <= swerv.io.sb_axi_arlen @[SweRV_Wrapper.scala 672:19] - io.sb_axi_arsize <= swerv.io.sb_axi_arsize @[SweRV_Wrapper.scala 673:20] - io.sb_axi_arburst <= swerv.io.sb_axi_arburst @[SweRV_Wrapper.scala 674:21] - io.sb_axi_arlock <= swerv.io.sb_axi_arlock @[SweRV_Wrapper.scala 675:20] - io.sb_axi_arcache <= swerv.io.sb_axi_arcache @[SweRV_Wrapper.scala 676:21] - io.sb_axi_arprot <= swerv.io.sb_axi_arprot @[SweRV_Wrapper.scala 677:20] - io.sb_axi_arqos <= swerv.io.sb_axi_arqos @[SweRV_Wrapper.scala 678:19] - io.sb_axi_rready <= swerv.io.sb_axi_rready @[SweRV_Wrapper.scala 679:20] - io.dma_axi_awready <= swerv.io.dma_axi_awready @[SweRV_Wrapper.scala 682:22] - io.dma_axi_wready <= swerv.io.dma_axi_wready @[SweRV_Wrapper.scala 683:21] - io.dma_axi_bvalid <= swerv.io.dma_axi_bvalid @[SweRV_Wrapper.scala 685:21] - io.dma_axi_bresp <= swerv.io.dma_axi_bresp @[SweRV_Wrapper.scala 686:20] - io.dma_axi_bid <= swerv.io.dma_axi_bid @[SweRV_Wrapper.scala 687:18] - io.dma_axi_arready <= swerv.io.dma_axi_arready @[SweRV_Wrapper.scala 690:22] - io.dma_axi_rvalid <= swerv.io.dma_axi_rvalid @[SweRV_Wrapper.scala 691:21] - io.dma_axi_rid <= swerv.io.dma_axi_rid @[SweRV_Wrapper.scala 692:18] - io.dma_axi_rdata <= swerv.io.dma_axi_rdata @[SweRV_Wrapper.scala 693:20] - io.dma_axi_rresp <= swerv.io.dma_axi_rresp @[SweRV_Wrapper.scala 694:20] - io.dma_axi_rlast <= swerv.io.dma_axi_rlast @[SweRV_Wrapper.scala 695:20] - io.dma_hrdata <= swerv.io.dma_hrdata @[SweRV_Wrapper.scala 698:17] - io.dma_hreadyout <= swerv.io.dma_hreadyout @[SweRV_Wrapper.scala 699:20] - io.dma_hresp <= swerv.io.dma_hresp @[SweRV_Wrapper.scala 700:16] + dmi_wrapper.trst_n <= io.jtag_trst_n @[el2_swerv_wrapper.scala 348:25] + dmi_wrapper.tck <= io.jtag_tck @[el2_swerv_wrapper.scala 349:22] + dmi_wrapper.tms <= io.jtag_tms @[el2_swerv_wrapper.scala 350:22] + dmi_wrapper.tdi <= io.jtag_tdi @[el2_swerv_wrapper.scala 351:22] + dmi_wrapper.core_clk <= clock @[el2_swerv_wrapper.scala 352:27] + dmi_wrapper.jtag_id <= io.jtag_id @[el2_swerv_wrapper.scala 353:26] + dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[el2_swerv_wrapper.scala 354:26] + dmi_wrapper.core_rst_n <= io.dbg_rst_l @[el2_swerv_wrapper.scala 357:29] + swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[el2_swerv_wrapper.scala 358:26] + swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[el2_swerv_wrapper.scala 359:25] + swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[el2_swerv_wrapper.scala 360:23] + swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[el2_swerv_wrapper.scala 361:26] + swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[el2_swerv_wrapper.scala 362:27] + io.jtag_tdo <= dmi_wrapper.tdo @[el2_swerv_wrapper.scala 363:15] + mem.dccm_clk_override <= swerv.io.dccm_clk_override @[el2_swerv_wrapper.scala 366:28] + mem.icm_clk_override <= swerv.io.icm_clk_override @[el2_swerv_wrapper.scala 367:27] + mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[el2_swerv_wrapper.scala 368:35] + mem.dccm_wren <= swerv.io.dccm_wren @[el2_swerv_wrapper.scala 369:20] + mem.dccm_rden <= swerv.io.dccm_rden @[el2_swerv_wrapper.scala 370:20] + mem.dccm_wr_addr_lo <= swerv.io.dccm_wr_addr_lo @[el2_swerv_wrapper.scala 371:26] + mem.dccm_wr_addr_hi <= swerv.io.dccm_wr_addr_hi @[el2_swerv_wrapper.scala 372:26] + mem.dccm_rd_addr_lo <= swerv.io.dccm_rd_addr_lo @[el2_swerv_wrapper.scala 373:26] + mem.dccm_wr_data_lo <= swerv.io.dccm_wr_data_lo @[el2_swerv_wrapper.scala 375:26] + mem.dccm_wr_data_hi <= swerv.io.dccm_wr_data_hi @[el2_swerv_wrapper.scala 376:26] + swerv.io.dccm_rd_data_lo <= mem.dccm_rd_data_lo @[el2_swerv_wrapper.scala 377:28] + mem.dccm_rd_addr_hi <= swerv.io.dccm_rd_addr_hi @[el2_swerv_wrapper.scala 378:26] + mem.iccm_rw_addr <= swerv.io.iccm_rw_addr @[el2_swerv_wrapper.scala 379:23] + mem.iccm_buf_correct_ecc <= swerv.io.iccm_buf_correct_ecc @[el2_swerv_wrapper.scala 380:31] + mem.iccm_correction_state <= swerv.io.iccm_correction_state @[el2_swerv_wrapper.scala 381:32] + mem.iccm_wren <= swerv.io.iccm_wren @[el2_swerv_wrapper.scala 382:20] + mem.iccm_rden <= swerv.io.iccm_rden @[el2_swerv_wrapper.scala 383:20] + mem.iccm_wr_size <= swerv.io.iccm_wr_size @[el2_swerv_wrapper.scala 384:23] + mem.iccm_wr_data <= swerv.io.iccm_wr_data @[el2_swerv_wrapper.scala 385:23] + mem.ic_rw_addr <= swerv.io.ic_rw_addr @[el2_swerv_wrapper.scala 388:21] + mem.ic_tag_valid <= swerv.io.ic_tag_valid @[el2_swerv_wrapper.scala 389:23] + mem.ic_wr_en <= swerv.io.ic_wr_en @[el2_swerv_wrapper.scala 390:19] + mem.ic_rd_en <= swerv.io.ic_rd_en @[el2_swerv_wrapper.scala 391:19] + mem.ic_premux_data <= swerv.io.ic_premux_data @[el2_swerv_wrapper.scala 392:25] + mem.ic_sel_premux_data <= swerv.io.ic_sel_premux_data @[el2_swerv_wrapper.scala 393:29] + mem.ic_wr_data[0] <= swerv.io.ic_wr_data[0] @[el2_swerv_wrapper.scala 394:21] + mem.ic_wr_data[1] <= swerv.io.ic_wr_data[1] @[el2_swerv_wrapper.scala 394:21] + mem.ic_debug_wr_data <= swerv.io.ic_debug_wr_data @[el2_swerv_wrapper.scala 395:27] + mem.ic_debug_addr <= swerv.io.ic_debug_addr @[el2_swerv_wrapper.scala 397:24] + mem.ic_debug_rd_en <= swerv.io.ic_debug_rd_en @[el2_swerv_wrapper.scala 398:25] + mem.ic_debug_wr_en <= swerv.io.ic_debug_wr_en @[el2_swerv_wrapper.scala 399:25] + mem.ic_debug_tag_array <= swerv.io.ic_debug_tag_array @[el2_swerv_wrapper.scala 400:29] + mem.ic_debug_way <= swerv.io.ic_debug_way @[el2_swerv_wrapper.scala 401:23] + mem.rst_l <= reset @[el2_swerv_wrapper.scala 402:16] + mem.clk <= clock @[el2_swerv_wrapper.scala 403:14] + mem.scan_mode <= io.scan_mode @[el2_swerv_wrapper.scala 404:20] + swerv.io.dbg_rst_l <= io.dbg_rst_l @[el2_swerv_wrapper.scala 406:22] + swerv.io.iccm_rd_data_ecc <= mem.iccm_rd_data_ecc @[el2_swerv_wrapper.scala 407:29] + swerv.io.dccm_rd_data_hi <= mem.dccm_rd_data_hi @[el2_swerv_wrapper.scala 408:28] + swerv.io.ic_rd_data <= mem.ic_rd_data @[el2_swerv_wrapper.scala 409:23] + swerv.io.ictag_debug_rd_data <= mem.ictag_debug_rd_data @[el2_swerv_wrapper.scala 410:32] + swerv.io.ic_eccerr <= mem.ic_eccerr @[el2_swerv_wrapper.scala 411:22] + swerv.io.ic_parerr <= mem.ic_parerr @[el2_swerv_wrapper.scala 412:22] + swerv.io.ic_rd_hit <= mem.ic_rd_hit @[el2_swerv_wrapper.scala 413:22] + swerv.io.ic_tag_perr <= mem.ic_tag_perr @[el2_swerv_wrapper.scala 414:24] + swerv.io.ic_debug_rd_data <= mem.ic_debug_rd_data @[el2_swerv_wrapper.scala 415:29] + swerv.io.iccm_rd_data <= mem.iccm_rd_data @[el2_swerv_wrapper.scala 416:25] + swerv.io.sb_hready <= UInt<1>("h00") @[el2_swerv_wrapper.scala 417:22] + swerv.io.hrdata <= UInt<1>("h00") @[el2_swerv_wrapper.scala 418:19] + swerv.io.sb_hresp <= UInt<1>("h00") @[el2_swerv_wrapper.scala 419:21] + swerv.io.lsu_hrdata <= UInt<1>("h00") @[el2_swerv_wrapper.scala 420:23] + swerv.io.lsu_hresp <= UInt<1>("h00") @[el2_swerv_wrapper.scala 421:22] + swerv.io.lsu_hready <= UInt<1>("h00") @[el2_swerv_wrapper.scala 422:23] + swerv.io.hready <= UInt<1>("h00") @[el2_swerv_wrapper.scala 423:19] + swerv.io.hresp <= UInt<1>("h00") @[el2_swerv_wrapper.scala 424:18] + swerv.io.sb_hrdata <= UInt<1>("h00") @[el2_swerv_wrapper.scala 425:22] + swerv.io.scan_mode <= io.scan_mode @[el2_swerv_wrapper.scala 426:22] + swerv.io.dbg_rst_l <= io.dbg_rst_l @[el2_swerv_wrapper.scala 428:22] + swerv.io.rst_vec <= io.rst_vec @[el2_swerv_wrapper.scala 429:20] + swerv.io.nmi_int <= io.nmi_int @[el2_swerv_wrapper.scala 430:20] + swerv.io.nmi_vec <= io.nmi_vec @[el2_swerv_wrapper.scala 431:20] + swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[el2_swerv_wrapper.scala 434:27] + swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[el2_swerv_wrapper.scala 435:26] + swerv.io.core_id <= io.core_id @[el2_swerv_wrapper.scala 436:20] + swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[el2_swerv_wrapper.scala 439:31] + swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[el2_swerv_wrapper.scala 440:30] + swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_swerv_wrapper.scala 441:30] + swerv.io.lsu_axi_awready <= io.lsu_axi_awready @[el2_swerv_wrapper.scala 445:28] + swerv.io.lsu_axi_wready <= io.lsu_axi_wready @[el2_swerv_wrapper.scala 446:27] + swerv.io.lsu_axi_bvalid <= io.lsu_axi_bvalid @[el2_swerv_wrapper.scala 448:27] + swerv.io.lsu_axi_bresp <= io.lsu_axi_bresp @[el2_swerv_wrapper.scala 449:26] + swerv.io.lsu_axi_bid <= io.lsu_axi_bid @[el2_swerv_wrapper.scala 450:24] + swerv.io.lsu_axi_arready <= io.lsu_axi_arready @[el2_swerv_wrapper.scala 453:28] + swerv.io.lsu_axi_rvalid <= io.lsu_axi_rvalid @[el2_swerv_wrapper.scala 454:27] + swerv.io.lsu_axi_rid <= io.lsu_axi_rid @[el2_swerv_wrapper.scala 455:24] + swerv.io.lsu_axi_rdata <= io.lsu_axi_rdata @[el2_swerv_wrapper.scala 456:26] + swerv.io.lsu_axi_rresp <= io.lsu_axi_rresp @[el2_swerv_wrapper.scala 457:26] + swerv.io.lsu_axi_rlast <= io.lsu_axi_rlast @[el2_swerv_wrapper.scala 458:26] + swerv.io.ifu_axi_awready <= io.ifu_axi_awready @[el2_swerv_wrapper.scala 462:28] + swerv.io.ifu_axi_wready <= io.ifu_axi_wready @[el2_swerv_wrapper.scala 463:27] + swerv.io.ifu_axi_bvalid <= io.ifu_axi_bvalid @[el2_swerv_wrapper.scala 464:27] + swerv.io.ifu_axi_bresp <= io.ifu_axi_bresp @[el2_swerv_wrapper.scala 465:26] + swerv.io.ifu_axi_bid <= io.ifu_axi_bid @[el2_swerv_wrapper.scala 466:24] + swerv.io.ifu_axi_arready <= io.ifu_axi_arready @[el2_swerv_wrapper.scala 469:28] + swerv.io.ifu_axi_rvalid <= io.ifu_axi_rvalid @[el2_swerv_wrapper.scala 470:27] + swerv.io.ifu_axi_rid <= io.ifu_axi_rid @[el2_swerv_wrapper.scala 471:24] + swerv.io.ifu_axi_rdata <= io.ifu_axi_rdata @[el2_swerv_wrapper.scala 472:26] + swerv.io.ifu_axi_rresp <= io.ifu_axi_rresp @[el2_swerv_wrapper.scala 473:26] + swerv.io.ifu_axi_rlast <= io.ifu_axi_rlast @[el2_swerv_wrapper.scala 474:26] + swerv.io.sb_axi_awready <= io.sb_axi_awready @[el2_swerv_wrapper.scala 478:27] + swerv.io.sb_axi_wready <= io.sb_axi_wready @[el2_swerv_wrapper.scala 479:26] + swerv.io.sb_axi_bvalid <= io.sb_axi_bvalid @[el2_swerv_wrapper.scala 481:26] + swerv.io.sb_axi_bresp <= io.sb_axi_bresp @[el2_swerv_wrapper.scala 482:25] + swerv.io.sb_axi_bid <= io.sb_axi_bid @[el2_swerv_wrapper.scala 483:23] + swerv.io.sb_axi_arready <= io.sb_axi_arready @[el2_swerv_wrapper.scala 486:27] + swerv.io.sb_axi_rvalid <= io.sb_axi_rvalid @[el2_swerv_wrapper.scala 487:26] + swerv.io.sb_axi_rid <= io.sb_axi_rid @[el2_swerv_wrapper.scala 488:23] + swerv.io.sb_axi_rdata <= io.sb_axi_rdata @[el2_swerv_wrapper.scala 489:25] + swerv.io.sb_axi_rresp <= io.sb_axi_rresp @[el2_swerv_wrapper.scala 490:25] + swerv.io.sb_axi_rlast <= io.sb_axi_rlast @[el2_swerv_wrapper.scala 491:25] + swerv.io.dma_axi_awvalid <= io.dma_axi_awvalid @[el2_swerv_wrapper.scala 495:28] + swerv.io.dma_axi_awid <= io.dma_axi_awid @[el2_swerv_wrapper.scala 496:25] + swerv.io.dma_axi_awaddr <= io.dma_axi_awaddr @[el2_swerv_wrapper.scala 497:27] + swerv.io.dma_axi_awsize <= io.dma_axi_awsize @[el2_swerv_wrapper.scala 498:27] + swerv.io.dma_axi_awprot <= io.dma_axi_awprot @[el2_swerv_wrapper.scala 499:27] + swerv.io.dma_axi_awlen <= io.dma_axi_awlen @[el2_swerv_wrapper.scala 500:26] + swerv.io.dma_axi_awburst <= io.dma_axi_awburst @[el2_swerv_wrapper.scala 501:28] + swerv.io.dma_axi_wvalid <= io.dma_axi_wvalid @[el2_swerv_wrapper.scala 503:27] + swerv.io.dma_axi_wdata <= io.dma_axi_wdata @[el2_swerv_wrapper.scala 504:26] + swerv.io.dma_axi_wstrb <= io.dma_axi_wstrb @[el2_swerv_wrapper.scala 505:26] + swerv.io.dma_axi_wlast <= io.dma_axi_wlast @[el2_swerv_wrapper.scala 506:26] + swerv.io.dma_axi_bready <= io.dma_axi_bready @[el2_swerv_wrapper.scala 507:27] + swerv.io.dma_axi_arvalid <= io.dma_axi_arvalid @[el2_swerv_wrapper.scala 510:28] + swerv.io.dma_axi_arid <= io.dma_axi_arid @[el2_swerv_wrapper.scala 511:25] + swerv.io.dma_axi_araddr <= io.dma_axi_araddr @[el2_swerv_wrapper.scala 512:27] + swerv.io.dma_axi_arsize <= io.dma_axi_arsize @[el2_swerv_wrapper.scala 513:27] + swerv.io.dma_axi_arprot <= io.dma_axi_arprot @[el2_swerv_wrapper.scala 514:27] + swerv.io.dma_axi_arlen <= io.dma_axi_arlen @[el2_swerv_wrapper.scala 515:26] + swerv.io.dma_axi_arburst <= io.dma_axi_arburst @[el2_swerv_wrapper.scala 516:28] + swerv.io.dma_axi_rready <= io.dma_axi_rready @[el2_swerv_wrapper.scala 517:27] + swerv.io.dma_hsel <= io.dma_hsel @[el2_swerv_wrapper.scala 520:21] + swerv.io.dma_haddr <= io.dma_haddr @[el2_swerv_wrapper.scala 521:22] + swerv.io.dma_hburst <= io.dma_hburst @[el2_swerv_wrapper.scala 522:23] + swerv.io.dma_hmastlock <= io.dma_hmastlock @[el2_swerv_wrapper.scala 523:26] + swerv.io.dma_hprot <= io.dma_hprot @[el2_swerv_wrapper.scala 524:22] + swerv.io.dma_hsize <= io.dma_hsize @[el2_swerv_wrapper.scala 525:22] + swerv.io.dma_htrans <= io.dma_htrans @[el2_swerv_wrapper.scala 526:23] + swerv.io.dma_hwrite <= io.dma_hwrite @[el2_swerv_wrapper.scala 527:23] + swerv.io.dma_hwdata <= io.dma_hwdata @[el2_swerv_wrapper.scala 528:23] + swerv.io.dma_hreadyin <= io.dma_hreadyin @[el2_swerv_wrapper.scala 529:25] + swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[el2_swerv_wrapper.scala 547:27] + swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_swerv_wrapper.scala 548:27] + swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[el2_swerv_wrapper.scala 549:27] + swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[el2_swerv_wrapper.scala 550:27] + swerv.io.timer_int <= io.timer_int @[el2_swerv_wrapper.scala 552:22] + swerv.io.soft_int <= io.soft_int @[el2_swerv_wrapper.scala 553:21] + swerv.io.extintsrc_req <= io.extintsrc_req @[el2_swerv_wrapper.scala 554:26] + io.trace_rv_i_insn_ip <= swerv.io.trace_rv_i_insn_ip @[el2_swerv_wrapper.scala 558:25] + io.trace_rv_i_address_ip <= swerv.io.trace_rv_i_address_ip @[el2_swerv_wrapper.scala 559:28] + io.trace_rv_i_valid_ip <= swerv.io.trace_rv_i_valid_ip @[el2_swerv_wrapper.scala 560:26] + io.trace_rv_i_exception_ip <= swerv.io.trace_rv_i_exception_ip @[el2_swerv_wrapper.scala 561:30] + io.trace_rv_i_ecause_ip <= swerv.io.trace_rv_i_ecause_ip @[el2_swerv_wrapper.scala 562:27] + io.trace_rv_i_interrupt_ip <= swerv.io.trace_rv_i_interrupt_ip @[el2_swerv_wrapper.scala 563:30] + io.trace_rv_i_tval_ip <= swerv.io.trace_rv_i_tval_ip @[el2_swerv_wrapper.scala 564:25] + io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[el2_swerv_wrapper.scala 567:21] + io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[el2_swerv_wrapper.scala 568:24] + io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[el2_swerv_wrapper.scala 569:20] + io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[el2_swerv_wrapper.scala 570:26] + io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[el2_swerv_wrapper.scala 572:25] + io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[el2_swerv_wrapper.scala 573:24] + io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[el2_swerv_wrapper.scala 574:25] + io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[el2_swerv_wrapper.scala 576:23] + io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[el2_swerv_wrapper.scala 577:23] + io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[el2_swerv_wrapper.scala 578:23] + io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[el2_swerv_wrapper.scala 579:23] + io.lsu_axi_awvalid <= swerv.io.lsu_axi_awvalid @[el2_swerv_wrapper.scala 584:22] + io.lsu_axi_awid <= swerv.io.lsu_axi_awid @[el2_swerv_wrapper.scala 585:19] + io.lsu_axi_awaddr <= swerv.io.lsu_axi_awaddr @[el2_swerv_wrapper.scala 586:21] + io.lsu_axi_awregion <= swerv.io.lsu_axi_awregion @[el2_swerv_wrapper.scala 587:23] + io.lsu_axi_awlen <= swerv.io.lsu_axi_awlen @[el2_swerv_wrapper.scala 588:20] + io.lsu_axi_awsize <= swerv.io.lsu_axi_awsize @[el2_swerv_wrapper.scala 589:21] + io.lsu_axi_awburst <= swerv.io.lsu_axi_awburst @[el2_swerv_wrapper.scala 590:22] + io.lsu_axi_awlock <= swerv.io.lsu_axi_awlock @[el2_swerv_wrapper.scala 591:21] + io.lsu_axi_awcache <= swerv.io.lsu_axi_awcache @[el2_swerv_wrapper.scala 592:22] + io.lsu_axi_awprot <= swerv.io.lsu_axi_awprot @[el2_swerv_wrapper.scala 593:21] + io.lsu_axi_awqos <= swerv.io.lsu_axi_awqos @[el2_swerv_wrapper.scala 594:20] + io.lsu_axi_wvalid <= swerv.io.lsu_axi_wvalid @[el2_swerv_wrapper.scala 596:21] + io.lsu_axi_wdata <= swerv.io.lsu_axi_wdata @[el2_swerv_wrapper.scala 597:20] + io.lsu_axi_wstrb <= swerv.io.lsu_axi_wstrb @[el2_swerv_wrapper.scala 598:20] + io.lsu_axi_wlast <= swerv.io.lsu_axi_wlast @[el2_swerv_wrapper.scala 599:20] + io.lsu_axi_bready <= swerv.io.lsu_axi_bready @[el2_swerv_wrapper.scala 600:21] + io.lsu_axi_arvalid <= swerv.io.lsu_axi_arvalid @[el2_swerv_wrapper.scala 603:22] + io.lsu_axi_arid <= swerv.io.lsu_axi_arid @[el2_swerv_wrapper.scala 604:19] + io.lsu_axi_araddr <= swerv.io.lsu_axi_araddr @[el2_swerv_wrapper.scala 605:21] + io.lsu_axi_arregion <= swerv.io.lsu_axi_arregion @[el2_swerv_wrapper.scala 606:23] + io.lsu_axi_arlen <= swerv.io.lsu_axi_arlen @[el2_swerv_wrapper.scala 607:20] + io.lsu_axi_arsize <= swerv.io.lsu_axi_arsize @[el2_swerv_wrapper.scala 608:21] + io.lsu_axi_arburst <= swerv.io.lsu_axi_arburst @[el2_swerv_wrapper.scala 609:22] + io.lsu_axi_arlock <= swerv.io.lsu_axi_arlock @[el2_swerv_wrapper.scala 610:21] + io.lsu_axi_arcache <= swerv.io.lsu_axi_arcache @[el2_swerv_wrapper.scala 611:22] + io.lsu_axi_arprot <= swerv.io.lsu_axi_arprot @[el2_swerv_wrapper.scala 612:21] + io.lsu_axi_arqos <= swerv.io.lsu_axi_arqos @[el2_swerv_wrapper.scala 613:20] + io.lsu_axi_rready <= swerv.io.lsu_axi_rready @[el2_swerv_wrapper.scala 614:21] + io.ifu_axi_awvalid <= swerv.io.ifu_axi_awvalid @[el2_swerv_wrapper.scala 616:22] + io.ifu_axi_awid <= swerv.io.ifu_axi_awid @[el2_swerv_wrapper.scala 617:19] + io.ifu_axi_awaddr <= swerv.io.ifu_axi_awaddr @[el2_swerv_wrapper.scala 618:21] + io.ifu_axi_awregion <= swerv.io.ifu_axi_awregion @[el2_swerv_wrapper.scala 619:23] + io.ifu_axi_awlen <= swerv.io.ifu_axi_awlen @[el2_swerv_wrapper.scala 620:20] + io.ifu_axi_awsize <= swerv.io.ifu_axi_awsize @[el2_swerv_wrapper.scala 621:21] + io.ifu_axi_awburst <= swerv.io.ifu_axi_awburst @[el2_swerv_wrapper.scala 622:22] + io.ifu_axi_awlock <= swerv.io.ifu_axi_awlock @[el2_swerv_wrapper.scala 623:21] + io.ifu_axi_awcache <= swerv.io.ifu_axi_awcache @[el2_swerv_wrapper.scala 624:22] + io.ifu_axi_awprot <= swerv.io.ifu_axi_awprot @[el2_swerv_wrapper.scala 625:21] + io.ifu_axi_awqos <= swerv.io.ifu_axi_awqos @[el2_swerv_wrapper.scala 626:20] + io.ifu_axi_wvalid <= swerv.io.ifu_axi_wvalid @[el2_swerv_wrapper.scala 627:21] + io.ifu_axi_wdata <= swerv.io.ifu_axi_wdata @[el2_swerv_wrapper.scala 628:20] + io.ifu_axi_wstrb <= swerv.io.ifu_axi_wstrb @[el2_swerv_wrapper.scala 629:20] + io.ifu_axi_wlast <= swerv.io.ifu_axi_wlast @[el2_swerv_wrapper.scala 630:20] + io.ifu_axi_bready <= swerv.io.ifu_axi_bready @[el2_swerv_wrapper.scala 632:21] + io.ifu_axi_arvalid <= swerv.io.ifu_axi_arvalid @[el2_swerv_wrapper.scala 635:22] + io.ifu_axi_arid <= swerv.io.ifu_axi_arid @[el2_swerv_wrapper.scala 636:19] + io.ifu_axi_araddr <= swerv.io.ifu_axi_araddr @[el2_swerv_wrapper.scala 637:21] + io.ifu_axi_arregion <= swerv.io.ifu_axi_arregion @[el2_swerv_wrapper.scala 638:23] + io.ifu_axi_arlen <= swerv.io.ifu_axi_arlen @[el2_swerv_wrapper.scala 639:20] + io.ifu_axi_arsize <= swerv.io.ifu_axi_arsize @[el2_swerv_wrapper.scala 640:21] + io.ifu_axi_arburst <= swerv.io.ifu_axi_arburst @[el2_swerv_wrapper.scala 641:22] + io.ifu_axi_arlock <= swerv.io.ifu_axi_arlock @[el2_swerv_wrapper.scala 642:21] + io.ifu_axi_arcache <= swerv.io.ifu_axi_arcache @[el2_swerv_wrapper.scala 643:22] + io.ifu_axi_arprot <= swerv.io.ifu_axi_arprot @[el2_swerv_wrapper.scala 644:21] + io.ifu_axi_arqos <= swerv.io.ifu_axi_arqos @[el2_swerv_wrapper.scala 645:20] + io.ifu_axi_rready <= swerv.io.ifu_axi_rready @[el2_swerv_wrapper.scala 646:21] + io.sb_axi_awvalid <= swerv.io.sb_axi_awvalid @[el2_swerv_wrapper.scala 649:21] + io.sb_axi_awid <= swerv.io.sb_axi_awid @[el2_swerv_wrapper.scala 650:18] + io.sb_axi_awaddr <= swerv.io.sb_axi_awaddr @[el2_swerv_wrapper.scala 651:20] + io.sb_axi_awregion <= swerv.io.sb_axi_awregion @[el2_swerv_wrapper.scala 652:22] + io.sb_axi_awlen <= swerv.io.sb_axi_awlen @[el2_swerv_wrapper.scala 653:19] + io.sb_axi_awsize <= swerv.io.sb_axi_awsize @[el2_swerv_wrapper.scala 654:20] + io.sb_axi_awburst <= swerv.io.sb_axi_awburst @[el2_swerv_wrapper.scala 655:21] + io.sb_axi_awlock <= swerv.io.sb_axi_awlock @[el2_swerv_wrapper.scala 656:20] + io.sb_axi_awcache <= swerv.io.sb_axi_awcache @[el2_swerv_wrapper.scala 657:21] + io.sb_axi_awprot <= swerv.io.sb_axi_awprot @[el2_swerv_wrapper.scala 658:20] + io.sb_axi_awqos <= swerv.io.sb_axi_awqos @[el2_swerv_wrapper.scala 659:19] + io.sb_axi_wvalid <= swerv.io.sb_axi_wvalid @[el2_swerv_wrapper.scala 661:19] + io.sb_axi_wdata <= swerv.io.sb_axi_wdata @[el2_swerv_wrapper.scala 662:19] + io.sb_axi_wstrb <= swerv.io.sb_axi_wstrb @[el2_swerv_wrapper.scala 663:19] + io.sb_axi_wlast <= swerv.io.sb_axi_wlast @[el2_swerv_wrapper.scala 664:19] + io.sb_axi_bready <= swerv.io.sb_axi_bready @[el2_swerv_wrapper.scala 665:20] + io.sb_axi_arvalid <= swerv.io.sb_axi_arvalid @[el2_swerv_wrapper.scala 668:21] + io.sb_axi_arid <= swerv.io.sb_axi_arid @[el2_swerv_wrapper.scala 669:18] + io.sb_axi_araddr <= swerv.io.sb_axi_araddr @[el2_swerv_wrapper.scala 670:20] + io.sb_axi_arregion <= swerv.io.sb_axi_arregion @[el2_swerv_wrapper.scala 671:22] + io.sb_axi_arlen <= swerv.io.sb_axi_arlen @[el2_swerv_wrapper.scala 672:19] + io.sb_axi_arsize <= swerv.io.sb_axi_arsize @[el2_swerv_wrapper.scala 673:20] + io.sb_axi_arburst <= swerv.io.sb_axi_arburst @[el2_swerv_wrapper.scala 674:21] + io.sb_axi_arlock <= swerv.io.sb_axi_arlock @[el2_swerv_wrapper.scala 675:20] + io.sb_axi_arcache <= swerv.io.sb_axi_arcache @[el2_swerv_wrapper.scala 676:21] + io.sb_axi_arprot <= swerv.io.sb_axi_arprot @[el2_swerv_wrapper.scala 677:20] + io.sb_axi_arqos <= swerv.io.sb_axi_arqos @[el2_swerv_wrapper.scala 678:19] + io.sb_axi_rready <= swerv.io.sb_axi_rready @[el2_swerv_wrapper.scala 679:20] + io.dma_axi_awready <= swerv.io.dma_axi_awready @[el2_swerv_wrapper.scala 682:22] + io.dma_axi_wready <= swerv.io.dma_axi_wready @[el2_swerv_wrapper.scala 683:21] + io.dma_axi_bvalid <= swerv.io.dma_axi_bvalid @[el2_swerv_wrapper.scala 685:21] + io.dma_axi_bresp <= swerv.io.dma_axi_bresp @[el2_swerv_wrapper.scala 686:20] + io.dma_axi_bid <= swerv.io.dma_axi_bid @[el2_swerv_wrapper.scala 687:18] + io.dma_axi_arready <= swerv.io.dma_axi_arready @[el2_swerv_wrapper.scala 690:22] + io.dma_axi_rvalid <= swerv.io.dma_axi_rvalid @[el2_swerv_wrapper.scala 691:21] + io.dma_axi_rid <= swerv.io.dma_axi_rid @[el2_swerv_wrapper.scala 692:18] + io.dma_axi_rdata <= swerv.io.dma_axi_rdata @[el2_swerv_wrapper.scala 693:20] + io.dma_axi_rresp <= swerv.io.dma_axi_rresp @[el2_swerv_wrapper.scala 694:20] + io.dma_axi_rlast <= swerv.io.dma_axi_rlast @[el2_swerv_wrapper.scala 695:20] + io.dma_hrdata <= swerv.io.dma_hrdata @[el2_swerv_wrapper.scala 698:17] + io.dma_hreadyout <= swerv.io.dma_hreadyout @[el2_swerv_wrapper.scala 699:20] + io.dma_hresp <= swerv.io.dma_hresp @[el2_swerv_wrapper.scala 700:16] diff --git a/el2_swerv_wrapper.v b/el2_swerv_wrapper.v index cc23c29f..28da1375 100644 --- a/el2_swerv_wrapper.v +++ b/el2_swerv_wrapper.v @@ -11826,6 +11826,7 @@ module el2_ifu_bp_ctl( input io_dec_tlu_bpred_disable, input io_exu_mp_pkt_bits_misp, input io_exu_mp_pkt_bits_ataken, + input io_exu_mp_pkt_bits_boffset, input io_exu_mp_pkt_bits_pc4, input [1:0] io_exu_mp_pkt_bits_hist, input [11:0] io_exu_mp_pkt_bits_toffset, @@ -21041,7 +21042,7 @@ module el2_ifu_bp_ctl( wire _T_531 = io_exu_mp_pkt_bits_pcall | io_exu_mp_pkt_bits_pja; // @[el2_ifu_bp_ctl.scala 396:89] wire _T_532 = io_exu_mp_pkt_bits_pret | io_exu_mp_pkt_bits_pja; // @[el2_ifu_bp_ctl.scala 396:113] wire [2:0] _T_534 = {_T_531,_T_532,btb_valid}; // @[Cat.scala 29:58] - wire [18:0] _T_537 = {io_exu_mp_btag,io_exu_mp_pkt_bits_toffset,io_exu_mp_pkt_bits_pc4,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_537 = {io_exu_mp_btag,io_exu_mp_pkt_bits_toffset,io_exu_mp_pkt_bits_pc4,io_exu_mp_pkt_bits_boffset}; // @[Cat.scala 29:58] wire exu_mp_valid_write = exu_mp_valid & io_exu_mp_pkt_bits_ataken; // @[el2_ifu_bp_ctl.scala 397:41] wire _T_539 = _T_175 & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 400:39] wire _T_541 = _T_539 & _T_530; // @[el2_ifu_bp_ctl.scala 400:60] @@ -21053,6 +21054,7 @@ module el2_ifu_bp_ctl( wire _T_547 = io_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98] wire btb_wr_en_way1 = _T_546 | _T_547; // @[el2_ifu_bp_ctl.scala 401:80] wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_i0_br_index_r : io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 404:24] + wire middle_of_bank = io_exu_mp_pkt_bits_pc4 ^ io_exu_mp_pkt_bits_boffset; // @[el2_ifu_bp_ctl.scala 405:35] wire _T_549 = ~io_exu_mp_pkt_bits_pcall; // @[el2_ifu_bp_ctl.scala 408:43] wire _T_550 = exu_mp_valid & _T_549; // @[el2_ifu_bp_ctl.scala 408:41] wire _T_551 = ~io_exu_mp_pkt_bits_pret; // @[el2_ifu_bp_ctl.scala 408:58] @@ -21060,8 +21062,8 @@ module el2_ifu_bp_ctl( wire _T_553 = ~io_exu_mp_pkt_bits_pja; // @[el2_ifu_bp_ctl.scala 408:72] wire _T_554 = _T_552 & _T_553; // @[el2_ifu_bp_ctl.scala 408:70] wire [1:0] _T_556 = _T_554 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_557 = ~io_exu_mp_pkt_bits_pc4; // @[el2_ifu_bp_ctl.scala 408:106] - wire [1:0] _T_558 = {io_exu_mp_pkt_bits_pc4,_T_557}; // @[Cat.scala 29:58] + wire _T_557 = ~middle_of_bank; // @[el2_ifu_bp_ctl.scala 408:106] + wire [1:0] _T_558 = {middle_of_bank,_T_557}; // @[Cat.scala 29:58] wire [1:0] bht_wr_en0 = _T_556 & _T_558; // @[el2_ifu_bp_ctl.scala 408:84] wire [1:0] _T_560 = io_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire _T_561 = ~io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu_bp_ctl.scala 409:75] @@ -43150,6 +43152,7 @@ module el2_ifu_aln_ctl( output io_ifu_i0_dbecc, output [31:0] io_ifu_i0_instr, output [30:0] io_ifu_i0_pc, + output io_ifu_i0_pc4, output io_ifu_fb_consume1, output io_ifu_fb_consume2, output [7:0] io_ifu_i0_bp_index, @@ -43704,6 +43707,7 @@ module el2_ifu_aln_ctl( assign io_ifu_i0_dbecc = _T_690 | _T_691; // @[el2_ifu_aln_ctl.scala 51:19 el2_ifu_aln_ctl.scala 362:19] assign io_ifu_i0_instr = _T_696 | _T_697; // @[el2_ifu_aln_ctl.scala 52:19 el2_ifu_aln_ctl.scala 368:19] assign io_ifu_i0_pc = f0pc; // @[el2_ifu_aln_ctl.scala 53:16 el2_ifu_aln_ctl.scala 340:16] + assign io_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 54:17 el2_ifu_aln_ctl.scala 344:17] assign io_ifu_fb_consume1 = _T_312 & _T_1; // @[el2_ifu_aln_ctl.scala 55:22 el2_ifu_aln_ctl.scala 258:22] assign io_ifu_fb_consume2 = _T_315 & _T_1; // @[el2_ifu_aln_ctl.scala 56:22 el2_ifu_aln_ctl.scala 259:22] assign io_ifu_i0_bp_index = _T_738 ? firstpc_hash : secondpc_hash; // @[el2_ifu_aln_ctl.scala 57:22 el2_ifu_aln_ctl.scala 400:22] @@ -44441,6 +44445,7 @@ module el2_ifu( output io_iccm_dma_sb_error, output [31:0] io_ifu_i0_instr, output [30:0] io_ifu_i0_pc, + output io_ifu_i0_pc4, output io_ifu_miss_state_idle, output io_i0_brp_valid, output [11:0] io_i0_brp_bits_toffset, @@ -44455,6 +44460,7 @@ module el2_ifu( output [4:0] io_ifu_i0_bp_btag, input io_exu_mp_pkt_bits_misp, input io_exu_mp_pkt_bits_ataken, + input io_exu_mp_pkt_bits_boffset, input io_exu_mp_pkt_bits_pc4, input [1:0] io_exu_mp_pkt_bits_hist, input [11:0] io_exu_mp_pkt_bits_toffset, @@ -44602,6 +44608,7 @@ module el2_ifu( wire bp_ctl_ch_io_dec_tlu_bpred_disable; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_exu_mp_pkt_bits_misp; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_exu_mp_pkt_bits_ataken; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_exu_mp_pkt_bits_boffset; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_exu_mp_pkt_bits_pc4; // @[el2_ifu.scala 147:25] wire [1:0] bp_ctl_ch_io_exu_mp_pkt_bits_hist; // @[el2_ifu.scala 147:25] wire [11:0] bp_ctl_ch_io_exu_mp_pkt_bits_toffset; // @[el2_ifu.scala 147:25] @@ -44655,6 +44662,7 @@ module el2_ifu( wire aln_ctl_ch_io_ifu_i0_dbecc; // @[el2_ifu.scala 148:26] wire [31:0] aln_ctl_ch_io_ifu_i0_instr; // @[el2_ifu.scala 148:26] wire [30:0] aln_ctl_ch_io_ifu_i0_pc; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_ifu_i0_pc4; // @[el2_ifu.scala 148:26] wire aln_ctl_ch_io_ifu_fb_consume1; // @[el2_ifu.scala 148:26] wire aln_ctl_ch_io_ifu_fb_consume2; // @[el2_ifu.scala 148:26] wire [7:0] aln_ctl_ch_io_ifu_i0_bp_index; // @[el2_ifu.scala 148:26] @@ -44818,6 +44826,7 @@ module el2_ifu( .io_dec_tlu_bpred_disable(bp_ctl_ch_io_dec_tlu_bpred_disable), .io_exu_mp_pkt_bits_misp(bp_ctl_ch_io_exu_mp_pkt_bits_misp), .io_exu_mp_pkt_bits_ataken(bp_ctl_ch_io_exu_mp_pkt_bits_ataken), + .io_exu_mp_pkt_bits_boffset(bp_ctl_ch_io_exu_mp_pkt_bits_boffset), .io_exu_mp_pkt_bits_pc4(bp_ctl_ch_io_exu_mp_pkt_bits_pc4), .io_exu_mp_pkt_bits_hist(bp_ctl_ch_io_exu_mp_pkt_bits_hist), .io_exu_mp_pkt_bits_toffset(bp_ctl_ch_io_exu_mp_pkt_bits_toffset), @@ -44873,6 +44882,7 @@ module el2_ifu( .io_ifu_i0_dbecc(aln_ctl_ch_io_ifu_i0_dbecc), .io_ifu_i0_instr(aln_ctl_ch_io_ifu_i0_instr), .io_ifu_i0_pc(aln_ctl_ch_io_ifu_i0_pc), + .io_ifu_i0_pc4(aln_ctl_ch_io_ifu_i0_pc4), .io_ifu_fb_consume1(aln_ctl_ch_io_ifu_fb_consume1), .io_ifu_fb_consume2(aln_ctl_ch_io_ifu_fb_consume2), .io_ifu_i0_bp_index(aln_ctl_ch_io_ifu_i0_bp_index), @@ -44965,6 +44975,7 @@ module el2_ifu( assign io_iccm_dma_sb_error = mem_ctl_ch_io_iccm_dma_sb_error; // @[el2_ifu.scala 325:24] assign io_ifu_i0_instr = aln_ctl_ch_io_ifu_i0_instr; // @[el2_ifu.scala 326:19] assign io_ifu_i0_pc = aln_ctl_ch_io_ifu_i0_pc; // @[el2_ifu.scala 327:16] + assign io_ifu_i0_pc4 = aln_ctl_ch_io_ifu_i0_pc4; // @[el2_ifu.scala 328:17] assign io_ifu_miss_state_idle = mem_ctl_ch_io_ifu_miss_state_idle; // @[el2_ifu.scala 329:26] assign io_i0_brp_valid = aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 331:13] assign io_i0_brp_bits_toffset = aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 331:13] @@ -45046,6 +45057,7 @@ module el2_ifu( assign bp_ctl_ch_io_dec_tlu_bpred_disable = io_dec_tlu_bpred_disable; // @[el2_ifu.scala 203:38] assign bp_ctl_ch_io_exu_mp_pkt_bits_misp = io_exu_mp_pkt_bits_misp; // @[el2_ifu.scala 204:27] assign bp_ctl_ch_io_exu_mp_pkt_bits_ataken = io_exu_mp_pkt_bits_ataken; // @[el2_ifu.scala 204:27] + assign bp_ctl_ch_io_exu_mp_pkt_bits_boffset = io_exu_mp_pkt_bits_boffset; // @[el2_ifu.scala 204:27] assign bp_ctl_ch_io_exu_mp_pkt_bits_pc4 = io_exu_mp_pkt_bits_pc4; // @[el2_ifu.scala 204:27] assign bp_ctl_ch_io_exu_mp_pkt_bits_hist = io_exu_mp_pkt_bits_hist; // @[el2_ifu.scala 204:27] assign bp_ctl_ch_io_exu_mp_pkt_bits_toffset = io_exu_mp_pkt_bits_toffset; // @[el2_ifu.scala 204:27] @@ -45116,6 +45128,7 @@ module el2_dec_ib_ctl( input [7:0] io_ifu_i0_bp_index, input [7:0] io_ifu_i0_bp_fghr, input [4:0] io_ifu_i0_bp_btag, + input io_ifu_i0_pc4, input io_ifu_i0_valid, input io_ifu_i0_icaf, input [1:0] io_ifu_i0_icaf_type, @@ -45127,6 +45140,7 @@ module el2_dec_ib_ctl( output [1:0] io_dec_i0_icaf_type_d, output [31:0] io_dec_i0_instr_d, output [30:0] io_dec_i0_pc_d, + output io_dec_i0_pc4_d, output io_dec_i0_brp_valid, output [11:0] io_dec_i0_brp_bits_toffset, output [1:0] io_dec_i0_brp_bits_hist, @@ -45173,6 +45187,7 @@ module el2_dec_ib_ctl( assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 48:31] assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 92:22] assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 46:31] + assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 47:31] assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 49:31] assign io_dec_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec_ib_ctl.scala 49:31] assign io_dec_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec_ib_ctl.scala 49:31] @@ -45199,6 +45214,7 @@ module el2_dec_dec_ctl( output io_out_rd, output io_out_shimm5, output io_out_imm20, + output io_out_pc, output io_out_load, output io_out_store, output io_out_lsu, @@ -45847,6 +45863,7 @@ module el2_dec_dec_ctl( assign io_out_rd = _T_170 | io_ins[4]; // @[el2_dec_dec_ctl.scala 82:13] assign io_out_shimm5 = _T_183 & _T_18; // @[el2_dec_dec_ctl.scala 83:17] assign io_out_imm20 = _T_187 | _T_190; // @[el2_dec_dec_ctl.scala 84:16] + assign io_out_pc = _T_198 | _T_187; // @[el2_dec_dec_ctl.scala 85:13] assign io_out_load = _T_209 & _T_18; // @[el2_dec_dec_ctl.scala 86:15] assign io_out_store = _T_121 & _T_98; // @[el2_dec_dec_ctl.scala 87:16] assign io_out_lsu = _T_224 & _T_18; // @[el2_dec_dec_ctl.scala 88:14] @@ -45950,6 +45967,7 @@ module el2_dec_decode_ctl( input [31:0] io_lsu_result_m, input [31:0] io_lsu_result_corr_r, input io_exu_flush_final, + input [30:0] io_exu_i0_pc_x, input [31:0] io_dec_i0_instr_d, input io_dec_ib0_valid_d, input [31:0] io_exu_i0_result_x, @@ -45988,6 +46006,7 @@ module el2_dec_decode_ctl( output [4:0] io_dec_i0_waddr_r, output io_dec_i0_wen_r, output [31:0] io_dec_i0_wdata_r, + output io_dec_i0_select_pc_d, output [1:0] io_dec_i0_rs1_bypass_en_d, output [1:0] io_dec_i0_rs2_bypass_en_d, output io_lsu_p_valid, @@ -46151,65 +46170,63 @@ module el2_dec_decode_ctl( reg [31:0] _RAND_87; reg [31:0] _RAND_88; reg [31:0] _RAND_89; + reg [31:0] _RAND_90; `endif // RANDOMIZE_REG_INIT - wire data_gated_cgc_io_l1clk; // @[el2_dec_decode_ctl.scala 222:29] - wire data_gated_cgc_io_clk; // @[el2_dec_decode_ctl.scala 222:29] - wire data_gated_cgc_io_en; // @[el2_dec_decode_ctl.scala 222:29] - wire data_gated_cgc_io_scan_mode; // @[el2_dec_decode_ctl.scala 222:29] - wire [31:0] i0_dec_io_ins; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 396:22] - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire [31:0] i0_dec_io_ins; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 392:22] wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] @@ -46222,10 +46239,10 @@ module el2_dec_decode_ctl( wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 518:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 518:23] wire rvclkhdr_5_io_clk; // @[el2_lib.scala 518:23] wire rvclkhdr_5_io_en; // @[el2_lib.scala 518:23] @@ -46242,10 +46259,10 @@ module el2_dec_decode_ctl( wire rvclkhdr_8_io_clk; // @[el2_lib.scala 518:23] wire rvclkhdr_8_io_en; // @[el2_lib.scala 518:23] wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 518:23] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 518:23] wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] @@ -46282,554 +46299,559 @@ module el2_dec_decode_ctl( wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23] wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23] - reg tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 503:29] + wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23] + reg tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 499:55] wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 211:51] - reg tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 504:29] + reg tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 500:55] wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 212:32] wire _T_3 = _T_1 | _T_2; // @[el2_dec_decode_ctl.scala 211:73] wire _T_4 = io_dec_tlu_flush_extint ^ io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 213:32] wire _T_5 = _T_3 | _T_4; // @[el2_dec_decode_ctl.scala 212:56] - reg leak1_i1_stall; // @[el2_dec_decode_ctl.scala 404:56] - wire _T_279 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 403:73] - wire _T_280 = leak1_i1_stall & _T_279; // @[el2_dec_decode_ctl.scala 403:71] - wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_280; // @[el2_dec_decode_ctl.scala 403:53] + reg leak1_i1_stall; // @[el2_dec_decode_ctl.scala 400:56] + wire _T_280 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 399:73] + wire _T_281 = leak1_i1_stall & _T_280; // @[el2_dec_decode_ctl.scala 399:71] + wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_281; // @[el2_dec_decode_ctl.scala 399:53] wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[el2_dec_decode_ctl.scala 214:32] wire _T_7 = _T_5 | _T_6; // @[el2_dec_decode_ctl.scala 213:56] - wire _T_283 = io_dec_i0_decode_d & leak1_i1_stall; // @[el2_dec_decode_ctl.scala 406:45] - reg leak1_i0_stall; // @[el2_dec_decode_ctl.scala 407:56] - wire _T_285 = leak1_i0_stall & _T_279; // @[el2_dec_decode_ctl.scala 406:81] - wire leak1_i0_stall_in = _T_283 | _T_285; // @[el2_dec_decode_ctl.scala 406:63] + wire _T_284 = io_dec_i0_decode_d & leak1_i1_stall; // @[el2_dec_decode_ctl.scala 402:45] + reg leak1_i0_stall; // @[el2_dec_decode_ctl.scala 403:56] + wire _T_286 = leak1_i0_stall & _T_280; // @[el2_dec_decode_ctl.scala 402:81] + wire leak1_i0_stall_in = _T_284 | _T_286; // @[el2_dec_decode_ctl.scala 402:63] wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[el2_dec_decode_ctl.scala 215:32] wire _T_9 = _T_7 | _T_8; // @[el2_dec_decode_ctl.scala 214:56] - reg pause_stall; // @[el2_dec_decode_ctl.scala 501:50] - wire _T_412 = io_dec_tlu_wr_pause_r | pause_stall; // @[el2_dec_decode_ctl.scala 500:44] - wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[el2_dec_decode_ctl.scala 499:49] - wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[el2_dec_decode_ctl.scala 499:47] + reg pause_stall; // @[el2_dec_decode_ctl.scala 497:50] + wire _T_412 = io_dec_tlu_wr_pause_r | pause_stall; // @[el2_dec_decode_ctl.scala 496:44] + wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[el2_dec_decode_ctl.scala 495:49] + wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[el2_dec_decode_ctl.scala 495:47] reg [31:0] write_csr_data; // @[el2_lib.scala 514:16] - wire _T_410 = write_csr_data == 32'h0; // @[el2_dec_decode_ctl.scala 499:109] - wire _T_411 = pause_stall & _T_410; // @[el2_dec_decode_ctl.scala 499:91] - wire clear_pause = _T_409 | _T_411; // @[el2_dec_decode_ctl.scala 499:76] - wire _T_413 = ~clear_pause; // @[el2_dec_decode_ctl.scala 500:61] - wire pause_state_in = _T_412 & _T_413; // @[el2_dec_decode_ctl.scala 500:59] + wire _T_410 = write_csr_data == 32'h0; // @[el2_dec_decode_ctl.scala 495:109] + wire _T_411 = pause_stall & _T_410; // @[el2_dec_decode_ctl.scala 495:91] + wire clear_pause = _T_409 | _T_411; // @[el2_dec_decode_ctl.scala 495:76] + wire _T_413 = ~clear_pause; // @[el2_dec_decode_ctl.scala 496:61] + wire pause_state_in = _T_412 & _T_413; // @[el2_dec_decode_ctl.scala 496:59] wire _T_10 = pause_state_in ^ pause_stall; // @[el2_dec_decode_ctl.scala 216:32] wire _T_11 = _T_9 | _T_10; // @[el2_dec_decode_ctl.scala 215:56] - wire _T_17 = ~leak1_i1_stall; // @[el2_dec_decode_ctl.scala 230:62] - wire i0_brp_valid = io_dec_i0_brp_valid & _T_17; // @[el2_dec_decode_ctl.scala 230:60] - wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire [20:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] - wire _T_298 = i0_pcall_imm[20:13] == 8'hff; // @[el2_dec_decode_ctl.scala 412:79] - wire _T_300 = i0_pcall_imm[20:13] == 8'h0; // @[el2_dec_decode_ctl.scala 412:112] - wire i0_pcall_12b_offset = i0_pcall_imm[12] ? _T_298 : _T_300; // @[el2_dec_decode_ctl.scala 412:33] - wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 413:47] - wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[el2_dec_decode_ctl.scala 626:16] - wire _T_302 = i0r_rd == 5'h1; // @[el2_dec_decode_ctl.scala 413:76] - wire _T_303 = i0r_rd == 5'h5; // @[el2_dec_decode_ctl.scala 413:98] - wire _T_304 = _T_302 | _T_303; // @[el2_dec_decode_ctl.scala 413:89] - wire i0_pcall_case = _T_301 & _T_304; // @[el2_dec_decode_ctl.scala 413:65] - wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 415:38] - wire _T_19 = i0_dp_raw_condbr | i0_pcall_raw; // @[el2_dec_decode_ctl.scala 241:75] - wire _T_309 = ~_T_304; // @[el2_dec_decode_ctl.scala 414:67] - wire i0_pja_case = _T_301 & _T_309; // @[el2_dec_decode_ctl.scala 414:65] - wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 417:38] - wire _T_20 = _T_19 | i0_pja_raw; // @[el2_dec_decode_ctl.scala 241:90] - wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 421:37] - wire _T_326 = i0r_rd == 5'h0; // @[el2_dec_decode_ctl.scala 421:65] - wire _T_327 = _T_325 & _T_326; // @[el2_dec_decode_ctl.scala 421:55] - wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 624:16] - wire _T_328 = i0r_rs1 == 5'h1; // @[el2_dec_decode_ctl.scala 421:89] - wire _T_329 = i0r_rs1 == 5'h5; // @[el2_dec_decode_ctl.scala 421:111] - wire _T_330 = _T_328 | _T_329; // @[el2_dec_decode_ctl.scala 421:101] - wire i0_pret_case = _T_327 & _T_330; // @[el2_dec_decode_ctl.scala 421:79] - wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 422:32] - wire _T_21 = _T_20 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 241:103] - wire _T_22 = ~_T_21; // @[el2_dec_decode_ctl.scala 241:56] - wire i0_notbr_error = i0_brp_valid & _T_22; // @[el2_dec_decode_ctl.scala 241:54] - wire _T_30 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 246:62] - wire _T_24 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[el2_dec_decode_ctl.scala 244:47] - wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 419:41] + wire _T_18 = ~leak1_i1_stall; // @[el2_dec_decode_ctl.scala 226:62] + wire i0_brp_valid = io_dec_i0_brp_valid & _T_18; // @[el2_dec_decode_ctl.scala 226:60] + wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire [19:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21]}; // @[Cat.scala 29:58] + wire _T_298 = i0_pcall_imm[19:12] == 8'hff; // @[el2_dec_decode_ctl.scala 408:79] + wire _T_300 = i0_pcall_imm[19:12] == 8'h0; // @[el2_dec_decode_ctl.scala 408:112] + wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_298 : _T_300; // @[el2_dec_decode_ctl.scala 408:33] + wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 409:47] + wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[el2_dec_decode_ctl.scala 622:16] + wire _T_302 = i0r_rd == 5'h1; // @[el2_dec_decode_ctl.scala 409:76] + wire _T_303 = i0r_rd == 5'h5; // @[el2_dec_decode_ctl.scala 409:98] + wire _T_304 = _T_302 | _T_303; // @[el2_dec_decode_ctl.scala 409:89] + wire i0_pcall_case = _T_301 & _T_304; // @[el2_dec_decode_ctl.scala 409:65] + wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 411:38] + wire _T_20 = i0_dp_raw_condbr | i0_pcall_raw; // @[el2_dec_decode_ctl.scala 237:75] + wire _T_309 = ~_T_304; // @[el2_dec_decode_ctl.scala 410:67] + wire i0_pja_case = _T_301 & _T_309; // @[el2_dec_decode_ctl.scala 410:65] + wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 413:38] + wire _T_21 = _T_20 | i0_pja_raw; // @[el2_dec_decode_ctl.scala 237:90] + wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 417:37] + wire _T_326 = i0r_rd == 5'h0; // @[el2_dec_decode_ctl.scala 417:65] + wire _T_327 = _T_325 & _T_326; // @[el2_dec_decode_ctl.scala 417:55] + wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 620:16] + wire _T_328 = i0r_rs1 == 5'h1; // @[el2_dec_decode_ctl.scala 417:89] + wire _T_329 = i0r_rs1 == 5'h5; // @[el2_dec_decode_ctl.scala 417:111] + wire _T_330 = _T_328 | _T_329; // @[el2_dec_decode_ctl.scala 417:101] + wire i0_pret_case = _T_327 & _T_330; // @[el2_dec_decode_ctl.scala 417:79] + wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 418:32] + wire _T_22 = _T_21 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 237:103] + wire _T_23 = ~_T_22; // @[el2_dec_decode_ctl.scala 237:56] + wire i0_notbr_error = i0_brp_valid & _T_23; // @[el2_dec_decode_ctl.scala 237:54] + wire _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:62] + wire _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[el2_dec_decode_ctl.scala 240:47] + wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 415:41] wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] - wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[12:1] : _T_323; // @[el2_dec_decode_ctl.scala 419:26] - wire _T_25 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 244:106] - wire _T_26 = _T_24 & _T_25; // @[el2_dec_decode_ctl.scala 244:76] - wire _T_27 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 244:126] - wire i0_br_toffset_error = _T_26 & _T_27; // @[el2_dec_decode_ctl.scala 244:124] - wire _T_31 = _T_30 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 246:79] - wire _T_28 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[el2_dec_decode_ctl.scala 245:47] - wire i0_ret_error = _T_28 & _T_27; // @[el2_dec_decode_ctl.scala 245:72] - wire i0_br_error = _T_31 | i0_ret_error; // @[el2_dec_decode_ctl.scala 246:101] - wire _T_38 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[el2_dec_decode_ctl.scala 251:47] - wire i0_br_error_all = _T_38 & _T_17; // @[el2_dec_decode_ctl.scala 251:84] - wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 260:36] - wire _T_40 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 264:25] - wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_postsync = _T_40 | i0_dp_raw_postsync; // @[el2_dec_decode_ctl.scala 264:50] - wire _T_439 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[el2_dec_decode_ctl.scala 530:36] - wire debug_fence_i = io_dec_debug_fence_d & io_dbg_cmd_wrdata[0]; // @[el2_dec_decode_ctl.scala 522:48] - wire _T_440 = _T_439 | debug_fence_i; // @[el2_dec_decode_ctl.scala 530:60] - wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_csr_write = _T_40 ? 1'h0 : i0_dp_raw_csr_write; // @[el2_dec_decode_ctl.scala 264:50] - wire _T_343 = ~io_dec_debug_fence_d; // @[el2_dec_decode_ctl.scala 461:42] - wire i0_csr_write = i0_dp_csr_write & _T_343; // @[el2_dec_decode_ctl.scala 461:40] - wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_csr_read = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 264:50] - wire _T_347 = ~i0_dp_csr_read; // @[el2_dec_decode_ctl.scala 466:41] - wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 466:39] - wire _T_442 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[el2_dec_decode_ctl.scala 530:112] - wire _T_443 = i0_csr_write_only_d & _T_442; // @[el2_dec_decode_ctl.scala 530:99] - wire i0_postsync = _T_440 | _T_443; // @[el2_dec_decode_ctl.scala 530:76] - wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_legal = _T_40 | i0_dp_raw_legal; // @[el2_dec_decode_ctl.scala 264:50] - wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 532:34] - wire _T_444 = ~any_csr_d; // @[el2_dec_decode_ctl.scala 534:40] - wire _T_445 = _T_444 | io_dec_csr_legal_d; // @[el2_dec_decode_ctl.scala 534:51] - wire i0_legal = i0_dp_legal & _T_445; // @[el2_dec_decode_ctl.scala 534:37] - wire _T_504 = ~i0_legal; // @[el2_dec_decode_ctl.scala 574:56] - wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 574:54] - wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 574:39] - reg postsync_stall; // @[el2_dec_decode_ctl.scala 572:53] + wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 415:26] + wire _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:106] + wire _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:76] + wire _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:126] + wire i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:124] + wire _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:79] + wire _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[el2_dec_decode_ctl.scala 241:47] + wire i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:72] + wire i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:101] + wire _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[el2_dec_decode_ctl.scala 247:47] + wire i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:84] + wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 256:36] + wire _T_41 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 260:25] + wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_postsync = _T_41 | i0_dp_raw_postsync; // @[el2_dec_decode_ctl.scala 260:50] + wire _T_439 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[el2_dec_decode_ctl.scala 526:36] + wire debug_fence_i = io_dec_debug_fence_d & io_dbg_cmd_wrdata[0]; // @[el2_dec_decode_ctl.scala 518:48] + wire _T_440 = _T_439 | debug_fence_i; // @[el2_dec_decode_ctl.scala 526:60] + wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_csr_write = _T_41 ? 1'h0 : i0_dp_raw_csr_write; // @[el2_dec_decode_ctl.scala 260:50] + wire _T_343 = ~io_dec_debug_fence_d; // @[el2_dec_decode_ctl.scala 457:42] + wire i0_csr_write = i0_dp_csr_write & _T_343; // @[el2_dec_decode_ctl.scala 457:40] + wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_csr_read = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 260:50] + wire _T_347 = ~i0_dp_csr_read; // @[el2_dec_decode_ctl.scala 462:41] + wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 462:39] + wire _T_442 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[el2_dec_decode_ctl.scala 526:112] + wire _T_443 = i0_csr_write_only_d & _T_442; // @[el2_dec_decode_ctl.scala 526:99] + wire i0_postsync = _T_440 | _T_443; // @[el2_dec_decode_ctl.scala 526:76] + wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_legal = _T_41 | i0_dp_raw_legal; // @[el2_dec_decode_ctl.scala 260:50] + wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 528:34] + wire _T_444 = ~any_csr_d; // @[el2_dec_decode_ctl.scala 530:40] + wire _T_445 = _T_444 | io_dec_csr_legal_d; // @[el2_dec_decode_ctl.scala 530:51] + wire i0_legal = i0_dp_legal & _T_445; // @[el2_dec_decode_ctl.scala 530:37] + wire _T_504 = ~i0_legal; // @[el2_dec_decode_ctl.scala 570:56] + wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 570:54] + wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 570:39] + reg postsync_stall; // @[el2_dec_decode_ctl.scala 568:53] reg x_d_valid; // @[el2_lib.scala 524:16] - wire _T_507 = postsync_stall & x_d_valid; // @[el2_dec_decode_ctl.scala 574:88] - wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 574:69] + wire _T_507 = postsync_stall & x_d_valid; // @[el2_dec_decode_ctl.scala 570:88] + wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 570:69] wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] - reg flush_final_r; // @[el2_dec_decode_ctl.scala 620:52] + reg flush_final_r; // @[el2_dec_decode_ctl.scala 616:52] wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[el2_dec_decode_ctl.scala 218:32] wire _T_15 = _T_13 | _T_14; // @[el2_dec_decode_ctl.scala 217:56] - wire shift_illegal = io_dec_i0_decode_d & _T_504; // @[el2_dec_decode_ctl.scala 538:47] - reg illegal_lockout; // @[el2_dec_decode_ctl.scala 542:54] - wire _T_466 = shift_illegal | illegal_lockout; // @[el2_dec_decode_ctl.scala 541:40] - wire _T_467 = ~flush_final_r; // @[el2_dec_decode_ctl.scala 541:61] - wire illegal_lockout_in = _T_466 & _T_467; // @[el2_dec_decode_ctl.scala 541:59] + wire shift_illegal = io_dec_i0_decode_d & _T_504; // @[el2_dec_decode_ctl.scala 534:47] + reg illegal_lockout; // @[el2_dec_decode_ctl.scala 538:54] + wire _T_466 = shift_illegal | illegal_lockout; // @[el2_dec_decode_ctl.scala 537:40] + wire _T_467 = ~flush_final_r; // @[el2_dec_decode_ctl.scala 537:61] + wire illegal_lockout_in = _T_466 & _T_467; // @[el2_dec_decode_ctl.scala 537:59] wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32] - wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 648:46] - wire _T_32 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 247:72] - wire _T_35 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 248:94] - wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_pm_alu = _T_40 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_fence_i = _T_40 ? 1'h0 : i0_dp_raw_fence_i; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_fence = _T_40 ? 1'h0 : i0_dp_raw_fence; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_div = i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_div = _T_40 ? 1'h0 : i0_dp_raw_div; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_low = i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_mul = _T_40 ? 1'h0 : i0_dp_raw_mul; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_mret = _T_40 ? 1'h0 : i0_dp_raw_mret; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_ecall = _T_40 ? 1'h0 : i0_dp_raw_ecall; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_ebreak = _T_40 ? 1'h0 : i0_dp_raw_ebreak; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_presync = _T_40 ? 1'h0 : i0_dp_raw_presync; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_csr_imm = _T_40 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_csr_set = _T_40 ? 1'h0 : i0_dp_raw_csr_set; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_csr_clr = _T_40 ? 1'h0 : i0_dp_raw_csr_clr; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_word = i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_word = _T_40 ? 1'h0 : i0_dp_raw_word; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_half = i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_half = _T_40 ? 1'h0 : i0_dp_raw_half; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_by = i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_by = _T_40 ? 1'h0 : i0_dp_raw_by; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_jal = _T_40 ? 1'h0 : i0_dp_raw_jal; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_condbr = _T_40 ? 1'h0 : i0_dp_raw_condbr; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_land = i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_add = i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_lsu = _T_40 ? 1'h0 : i0_dp_raw_lsu; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_store = i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_store = _T_40 ? 1'h0 : i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_load = i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_load = _T_40 ? 1'h0 : i0_dp_raw_load; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_imm20 = _T_40 ? 1'h0 : i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_shimm5 = _T_40 ? 1'h0 : i0_dp_raw_shimm5; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_rd = _T_40 ? 1'h0 : i0_dp_raw_rd; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_imm12 = _T_40 ? 1'h0 : i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_rs2 = _T_40 | i0_dp_raw_rs2; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_rs1 = _T_40 | i0_dp_raw_rs1; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_alu = _T_40 | i0_dp_raw_alu; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 416:38] - wire _T_43 = i0_dp_condbr | i0_pcall; // @[el2_dec_decode_ctl.scala 278:38] - wire i0_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 418:38] - wire _T_44 = _T_43 | i0_pja; // @[el2_dec_decode_ctl.scala 278:49] - wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 423:32] - wire i0_predict_br = _T_44 | i0_pret; // @[el2_dec_decode_ctl.scala 278:58] - wire _T_46 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 280:55] - wire _T_47 = ~_T_46; // @[el2_dec_decode_ctl.scala 280:26] - wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 282:20] - wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 315:63] - reg [2:0] cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 351:47] - wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 326:67] - wire _T_93 = _GEN_123 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 326:67] - wire _T_94 = cam_data_reset & _T_93; // @[el2_dec_decode_ctl.scala 326:45] - reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 351:47] - wire cam_data_reset_val_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 326:88] - wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 330:39] - wire _T_50 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 307:78] - reg [2:0] cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_119 = _GEN_123 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 326:67] - wire _T_120 = cam_data_reset & _T_119; // @[el2_dec_decode_ctl.scala 326:45] - reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 351:47] - wire cam_data_reset_val_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 326:88] - wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 330:39] - wire _T_53 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 307:78] - wire _T_56 = cam_0_valid & _T_53; // @[el2_dec_decode_ctl.scala 307:126] - wire [1:0] _T_58 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 307:158] - reg [2:0] cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_145 = _GEN_123 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 326:67] - wire _T_146 = cam_data_reset & _T_145; // @[el2_dec_decode_ctl.scala 326:45] - reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 351:47] - wire cam_data_reset_val_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 326:88] - wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 330:39] - wire _T_59 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 307:78] - wire _T_62 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 307:126] - wire _T_65 = _T_62 & _T_59; // @[el2_dec_decode_ctl.scala 307:126] - wire [2:0] _T_67 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 307:158] - reg [2:0] cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_171 = _GEN_123 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 326:67] - wire _T_172 = cam_data_reset & _T_171; // @[el2_dec_decode_ctl.scala 326:45] - reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 351:47] - wire cam_data_reset_val_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 326:88] - wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 330:39] - wire _T_68 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 307:78] - wire _T_74 = _T_62 & cam_2_valid; // @[el2_dec_decode_ctl.scala 307:126] - wire _T_77 = _T_74 & _T_68; // @[el2_dec_decode_ctl.scala 307:126] - wire [3:0] _T_79 = {io_lsu_nonblock_load_valid_m, 3'h0}; // @[el2_dec_decode_ctl.scala 307:158] - wire _T_80 = _T_50 & io_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] - wire [1:0] _T_81 = _T_56 ? _T_58 : 2'h0; // @[Mux.scala 27:72] - wire [2:0] _T_82 = _T_65 ? _T_67 : 3'h0; // @[Mux.scala 27:72] - wire [3:0] _T_83 = _T_77 ? _T_79 : 4'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_127 = {{1'd0}, _T_80}; // @[Mux.scala 27:72] - wire [1:0] _T_84 = _GEN_127 | _T_81; // @[Mux.scala 27:72] - wire [2:0] _GEN_128 = {{1'd0}, _T_84}; // @[Mux.scala 27:72] - wire [2:0] _T_85 = _GEN_128 | _T_82; // @[Mux.scala 27:72] - wire [3:0] _GEN_129 = {{1'd0}, _T_85}; // @[Mux.scala 27:72] - wire [3:0] cam_wen = _GEN_129 | _T_83; // @[Mux.scala 27:72] + wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 644:46] + wire _T_33 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 243:72] + wire _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:94] + wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_fence_i = _T_41 ? 1'h0 : i0_dp_raw_fence_i; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_fence = _T_41 ? 1'h0 : i0_dp_raw_fence; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_div = i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_div = _T_41 ? 1'h0 : i0_dp_raw_div; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_low = i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_mul = _T_41 ? 1'h0 : i0_dp_raw_mul; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_mret = _T_41 ? 1'h0 : i0_dp_raw_mret; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_ecall = _T_41 ? 1'h0 : i0_dp_raw_ecall; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_ebreak = _T_41 ? 1'h0 : i0_dp_raw_ebreak; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_presync = _T_41 ? 1'h0 : i0_dp_raw_presync; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_csr_set = _T_41 ? 1'h0 : i0_dp_raw_csr_set; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_csr_clr = _T_41 ? 1'h0 : i0_dp_raw_csr_clr; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_word = i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_word = _T_41 ? 1'h0 : i0_dp_raw_word; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_half = i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_half = _T_41 ? 1'h0 : i0_dp_raw_half; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_by = i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_by = _T_41 ? 1'h0 : i0_dp_raw_by; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_jal = _T_41 ? 1'h0 : i0_dp_raw_jal; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_condbr = _T_41 ? 1'h0 : i0_dp_raw_condbr; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_land = i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_add = i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_lsu = _T_41 ? 1'h0 : i0_dp_raw_lsu; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_store = i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_store = _T_41 ? 1'h0 : i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_load = i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_load = _T_41 ? 1'h0 : i0_dp_raw_load; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_imm20 = _T_41 ? 1'h0 : i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_shimm5 = _T_41 ? 1'h0 : i0_dp_raw_shimm5; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_rd = _T_41 ? 1'h0 : i0_dp_raw_rd; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_imm12 = _T_41 ? 1'h0 : i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_rs2 = _T_41 | i0_dp_raw_rs2; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_rs1 = _T_41 | i0_dp_raw_rs1; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_alu = _T_41 | i0_dp_raw_alu; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 412:38] + wire _T_44 = i0_dp_condbr | i0_pcall; // @[el2_dec_decode_ctl.scala 274:38] + wire i0_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 414:38] + wire _T_45 = _T_44 | i0_pja; // @[el2_dec_decode_ctl.scala 274:49] + wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 419:32] + wire i0_predict_br = _T_45 | i0_pret; // @[el2_dec_decode_ctl.scala 274:58] + wire _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:55] + wire _T_48 = ~_T_47; // @[el2_dec_decode_ctl.scala 276:26] + wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 278:20] + wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 311:63] + reg [2:0] cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_95 = cam_data_reset & _T_94; // @[el2_dec_decode_ctl.scala 322:45] + reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 347:47] + wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 326:39] + wire _T_51 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 303:78] + reg [2:0] cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_121 = cam_data_reset & _T_120; // @[el2_dec_decode_ctl.scala 322:45] + reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 347:47] + wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 326:39] + wire _T_54 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 303:78] + wire _T_57 = cam_0_valid & _T_54; // @[el2_dec_decode_ctl.scala 303:126] + wire [1:0] _T_59 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 303:158] + reg [2:0] cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_147 = cam_data_reset & _T_146; // @[el2_dec_decode_ctl.scala 322:45] + reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 347:47] + wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 326:39] + wire _T_60 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 303:78] + wire _T_63 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 303:126] + wire _T_66 = _T_63 & _T_60; // @[el2_dec_decode_ctl.scala 303:126] + wire [2:0] _T_68 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 303:158] + reg [2:0] cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_173 = cam_data_reset & _T_172; // @[el2_dec_decode_ctl.scala 322:45] + reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 347:47] + wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 326:39] + wire _T_69 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 303:78] + wire _T_75 = _T_63 & cam_2_valid; // @[el2_dec_decode_ctl.scala 303:126] + wire _T_78 = _T_75 & _T_69; // @[el2_dec_decode_ctl.scala 303:126] + wire [3:0] _T_80 = {io_lsu_nonblock_load_valid_m, 3'h0}; // @[el2_dec_decode_ctl.scala 303:158] + wire _T_81 = _T_51 & io_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] + wire [1:0] _T_82 = _T_57 ? _T_59 : 2'h0; // @[Mux.scala 27:72] + wire [2:0] _T_83 = _T_66 ? _T_68 : 3'h0; // @[Mux.scala 27:72] + wire [3:0] _T_84 = _T_78 ? _T_80 : 4'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_127 = {{1'd0}, _T_81}; // @[Mux.scala 27:72] + wire [1:0] _T_85 = _GEN_127 | _T_82; // @[Mux.scala 27:72] + wire [2:0] _GEN_128 = {{1'd0}, _T_85}; // @[Mux.scala 27:72] + wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72] + wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72] + wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] reg x_d_bits_i0load; // @[el2_lib.scala 524:16] reg [4:0] x_d_bits_i0rd; // @[el2_lib.scala 524:16] - wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 318:31] - reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 656:72] + wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] + reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 652:72] wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] - wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 659:49] - wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 659:53] + wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 655:49] + wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 655:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] reg r_d_bits_i0load; // @[el2_lib.scala 524:16] - wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 323:56] - wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 325:66] - wire _T_90 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 325:66] - wire _T_91 = io_lsu_nonblock_load_inv_r & _T_90; // @[el2_dec_decode_ctl.scala 325:45] - wire cam_inv_reset_val_0 = _T_91 & cam_0_valid; // @[el2_dec_decode_ctl.scala 325:87] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 319:56] + wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45] + wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:87] reg r_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 691:51] - wire r_d_in_bits_i0v = r_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 691:49] - wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 699:47] - wire i0_wen_r = r_d_in_bits_i0v & _T_754; // @[el2_dec_decode_ctl.scala 699:45] + wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:51] + wire r_d_in_bits_i0v = r_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:49] + wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:47] + wire i0_wen_r = r_d_in_bits_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:45] reg [4:0] r_d_bits_i0rd; // @[el2_lib.scala 524:16] - reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_102 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 338:85] - wire _T_103 = i0_wen_r & _T_102; // @[el2_dec_decode_ctl.scala 338:64] - reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_105 = _T_103 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 338:105] - wire _T_106 = cam_inv_reset_val_0 | _T_105; // @[el2_dec_decode_ctl.scala 338:44] - wire _GEN_52 = _T_106 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_55 = _T_106 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 333:28] - wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 333:28] - wire _T_109 = nonblock_load_valid_m_delay & _T_90; // @[el2_dec_decode_ctl.scala 343:44] - wire _T_111 = _T_109 & cam_0_valid; // @[el2_dec_decode_ctl.scala 343:100] - wire nonblock_load_write_0 = _T_93 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 352:71] - wire _T_116 = _GEN_130 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 325:66] - wire _T_117 = io_lsu_nonblock_load_inv_r & _T_116; // @[el2_dec_decode_ctl.scala 325:45] - wire cam_inv_reset_val_1 = _T_117 & cam_1_valid; // @[el2_dec_decode_ctl.scala 325:87] - reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_128 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 338:85] - wire _T_129 = i0_wen_r & _T_128; // @[el2_dec_decode_ctl.scala 338:64] - reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_131 = _T_129 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 338:105] - wire _T_132 = cam_inv_reset_val_1 | _T_131; // @[el2_dec_decode_ctl.scala 338:44] - wire _GEN_63 = _T_132 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_66 = _T_132 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 333:28] - wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 333:28] - wire _T_135 = nonblock_load_valid_m_delay & _T_116; // @[el2_dec_decode_ctl.scala 343:44] - wire _T_137 = _T_135 & cam_1_valid; // @[el2_dec_decode_ctl.scala 343:100] - wire nonblock_load_write_1 = _T_119 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 352:71] - wire _T_142 = _GEN_130 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 325:66] - wire _T_143 = io_lsu_nonblock_load_inv_r & _T_142; // @[el2_dec_decode_ctl.scala 325:45] - wire cam_inv_reset_val_2 = _T_143 & cam_2_valid; // @[el2_dec_decode_ctl.scala 325:87] - reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_154 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 338:85] - wire _T_155 = i0_wen_r & _T_154; // @[el2_dec_decode_ctl.scala 338:64] - reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_157 = _T_155 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 338:105] - wire _T_158 = cam_inv_reset_val_2 | _T_157; // @[el2_dec_decode_ctl.scala 338:44] - wire _GEN_74 = _T_158 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_77 = _T_158 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 333:28] - wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 333:28] - wire _T_161 = nonblock_load_valid_m_delay & _T_142; // @[el2_dec_decode_ctl.scala 343:44] - wire _T_163 = _T_161 & cam_2_valid; // @[el2_dec_decode_ctl.scala 343:100] - wire nonblock_load_write_2 = _T_145 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 352:71] - wire _T_168 = _GEN_130 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 325:66] - wire _T_169 = io_lsu_nonblock_load_inv_r & _T_168; // @[el2_dec_decode_ctl.scala 325:45] - wire cam_inv_reset_val_3 = _T_169 & cam_3_valid; // @[el2_dec_decode_ctl.scala 325:87] - reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_180 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 338:85] - wire _T_181 = i0_wen_r & _T_180; // @[el2_dec_decode_ctl.scala 338:64] - reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_183 = _T_181 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 338:105] - wire _T_184 = cam_inv_reset_val_3 | _T_183; // @[el2_dec_decode_ctl.scala 338:44] - wire _GEN_85 = _T_184 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_88 = _T_184 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 333:28] - wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 333:28] - wire _T_187 = nonblock_load_valid_m_delay & _T_168; // @[el2_dec_decode_ctl.scala 343:44] - wire _T_189 = _T_187 & cam_3_valid; // @[el2_dec_decode_ctl.scala 343:100] - wire nonblock_load_write_3 = _T_171 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 352:71] - wire _T_194 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 357:49] - wire nonblock_load_cancel = _T_194 & i0_wen_r; // @[el2_dec_decode_ctl.scala 357:81] - wire _T_195 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 358:95] - wire _T_196 = _T_195 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 358:95] - wire _T_197 = _T_196 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 358:95] - wire _T_199 = io_lsu_nonblock_load_data_valid & _T_197; // @[el2_dec_decode_ctl.scala 358:64] - wire _T_200 = ~nonblock_load_cancel; // @[el2_dec_decode_ctl.scala 358:109] - wire _T_202 = nonblock_load_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:54] - wire _T_203 = _T_202 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 359:66] - wire _T_204 = _T_203 & io_dec_i0_rs1_en_d; // @[el2_dec_decode_ctl.scala 359:97] - wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 625:16] - wire _T_205 = nonblock_load_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:137] - wire _T_206 = _T_205 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 359:149] - wire _T_207 = _T_206 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 359:180] - wire i0_nonblock_boundary_stall = _T_204 | _T_207; // @[el2_dec_decode_ctl.scala 359:118] - wire [4:0] _T_209 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_210 = _T_209 & cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 363:88] - wire _T_211 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 363:126] - wire _T_212 = cam_raw_0_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:159] - wire _T_213 = _T_211 & _T_212; // @[el2_dec_decode_ctl.scala 363:141] - wire _T_214 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 363:192] - wire _T_215 = cam_raw_0_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:225] - wire _T_216 = _T_214 & _T_215; // @[el2_dec_decode_ctl.scala 363:207] - wire [4:0] _T_218 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_219 = _T_218 & cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 363:88] - wire _T_220 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 363:126] - wire _T_221 = cam_raw_1_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:159] - wire _T_222 = _T_220 & _T_221; // @[el2_dec_decode_ctl.scala 363:141] - wire _T_223 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 363:192] - wire _T_224 = cam_raw_1_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:225] - wire _T_225 = _T_223 & _T_224; // @[el2_dec_decode_ctl.scala 363:207] - wire [4:0] _T_227 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_228 = _T_227 & cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 363:88] - wire _T_229 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 363:126] - wire _T_230 = cam_raw_2_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:159] - wire _T_231 = _T_229 & _T_230; // @[el2_dec_decode_ctl.scala 363:141] - wire _T_232 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 363:192] - wire _T_233 = cam_raw_2_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:225] - wire _T_234 = _T_232 & _T_233; // @[el2_dec_decode_ctl.scala 363:207] - wire [4:0] _T_236 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_237 = _T_236 & cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 363:88] - wire _T_238 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 363:126] - wire _T_239 = cam_raw_3_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:159] - wire _T_240 = _T_238 & _T_239; // @[el2_dec_decode_ctl.scala 363:141] - wire _T_241 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 363:192] - wire _T_242 = cam_raw_3_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:225] - wire _T_243 = _T_241 & _T_242; // @[el2_dec_decode_ctl.scala 363:207] - wire [4:0] _T_244 = _T_210 | _T_219; // @[el2_dec_decode_ctl.scala 364:69] - wire [4:0] _T_245 = _T_244 | _T_228; // @[el2_dec_decode_ctl.scala 364:69] - wire _T_246 = _T_213 | _T_222; // @[el2_dec_decode_ctl.scala 364:102] - wire _T_247 = _T_246 | _T_231; // @[el2_dec_decode_ctl.scala 364:102] - wire ld_stall_1 = _T_247 | _T_240; // @[el2_dec_decode_ctl.scala 364:102] - wire _T_248 = _T_216 | _T_225; // @[el2_dec_decode_ctl.scala 364:134] - wire _T_249 = _T_248 | _T_234; // @[el2_dec_decode_ctl.scala 364:134] - wire ld_stall_2 = _T_249 | _T_243; // @[el2_dec_decode_ctl.scala 364:134] - wire _T_250 = ld_stall_1 | ld_stall_2; // @[el2_dec_decode_ctl.scala 366:38] - wire i0_nonblock_load_stall = _T_250 | i0_nonblock_boundary_stall; // @[el2_dec_decode_ctl.scala 366:51] - wire _T_252 = ~i0_predict_br; // @[el2_dec_decode_ctl.scala 375:34] - wire [3:0] _T_254 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 459:36] - wire _T_255 = csr_read & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 387:16] - wire _T_257 = ~csr_read; // @[el2_dec_decode_ctl.scala 388:6] - wire _T_258 = _T_257 & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 388:16] - wire _T_260 = ~io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 389:18] - wire _T_261 = csr_read & _T_260; // @[el2_dec_decode_ctl.scala 389:16] - wire [3:0] _T_263 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] - wire [3:0] _T_264 = i0_dp_load ? 4'h2 : _T_263; // @[Mux.scala 98:16] - wire [3:0] _T_265 = i0_dp_store ? 4'h3 : _T_264; // @[Mux.scala 98:16] - wire [3:0] _T_266 = i0_dp_pm_alu ? 4'h4 : _T_265; // @[Mux.scala 98:16] - wire [3:0] _T_267 = _T_261 ? 4'h5 : _T_266; // @[Mux.scala 98:16] - wire [3:0] _T_268 = _T_258 ? 4'h6 : _T_267; // @[Mux.scala 98:16] - wire [3:0] _T_269 = _T_255 ? 4'h7 : _T_268; // @[Mux.scala 98:16] - wire [3:0] _T_270 = i0_dp_ebreak ? 4'h8 : _T_269; // @[Mux.scala 98:16] - wire [3:0] _T_271 = i0_dp_ecall ? 4'h9 : _T_270; // @[Mux.scala 98:16] - wire [3:0] _T_272 = i0_dp_fence ? 4'ha : _T_271; // @[Mux.scala 98:16] - wire [3:0] _T_273 = i0_dp_fence_i ? 4'hb : _T_272; // @[Mux.scala 98:16] - wire [3:0] _T_274 = i0_dp_mret ? 4'hc : _T_273; // @[Mux.scala 98:16] - wire [3:0] _T_275 = i0_dp_condbr ? 4'hd : _T_274; // @[Mux.scala 98:16] - wire [3:0] _T_276 = i0_dp_jal ? 4'he : _T_275; // @[Mux.scala 98:16] - reg lsu_idle; // @[el2_dec_decode_ctl.scala 400:45] - wire _T_333 = ~i0_pcall_case; // @[el2_dec_decode_ctl.scala 424:35] - wire _T_334 = i0_dp_jal & _T_333; // @[el2_dec_decode_ctl.scala 424:32] - wire _T_335 = ~i0_pja_case; // @[el2_dec_decode_ctl.scala 424:52] - wire _T_336 = _T_334 & _T_335; // @[el2_dec_decode_ctl.scala 424:50] - wire _T_337 = ~i0_pret_case; // @[el2_dec_decode_ctl.scala 424:67] - reg _T_339; // @[el2_dec_decode_ctl.scala 436:58] - wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 578:40] - wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 792:43] + reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64] + reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44] + wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28] + wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28] + wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44] + wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:100] + wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:71] + wire _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45] + wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:87] + reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64] + reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44] + wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28] + wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28] + wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44] + wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:100] + wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:71] + wire _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45] + wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:87] + reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64] + reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44] + wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28] + wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28] + wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44] + wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:100] + wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:71] + wire _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45] + wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:87] + reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64] + reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44] + wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28] + wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28] + wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44] + wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:100] + wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:71] + wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:49] + wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:81] + wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95] + wire _T_197 = _T_196 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 354:95] + wire _T_198 = _T_197 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 354:95] + wire _T_200 = io_lsu_nonblock_load_data_valid & _T_198; // @[el2_dec_decode_ctl.scala 354:64] + wire _T_201 = ~nonblock_load_cancel; // @[el2_dec_decode_ctl.scala 354:109] + wire _T_203 = nonblock_load_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 355:54] + wire _T_204 = _T_203 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 355:66] + wire _T_205 = _T_204 & io_dec_i0_rs1_en_d; // @[el2_dec_decode_ctl.scala 355:97] + wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 621:16] + wire _T_206 = nonblock_load_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 355:137] + wire _T_207 = _T_206 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 355:149] + wire _T_208 = _T_207 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 355:180] + wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[el2_dec_decode_ctl.scala 355:118] + wire [4:0] _T_210 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:126] + wire _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] + wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:141] + wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:192] + wire _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] + wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_219 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:126] + wire _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] + wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:141] + wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:192] + wire _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] + wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_228 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:126] + wire _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] + wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:141] + wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:192] + wire _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] + wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_237 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:126] + wire _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] + wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:141] + wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:192] + wire _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] + wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_245 = _T_211 | _T_220; // @[el2_dec_decode_ctl.scala 360:69] + wire [4:0] _T_246 = _T_245 | _T_229; // @[el2_dec_decode_ctl.scala 360:69] + wire _T_247 = _T_214 | _T_223; // @[el2_dec_decode_ctl.scala 360:102] + wire _T_248 = _T_247 | _T_232; // @[el2_dec_decode_ctl.scala 360:102] + wire ld_stall_1 = _T_248 | _T_241; // @[el2_dec_decode_ctl.scala 360:102] + wire _T_249 = _T_217 | _T_226; // @[el2_dec_decode_ctl.scala 360:134] + wire _T_250 = _T_249 | _T_235; // @[el2_dec_decode_ctl.scala 360:134] + wire ld_stall_2 = _T_250 | _T_244; // @[el2_dec_decode_ctl.scala 360:134] + wire _T_251 = ld_stall_1 | ld_stall_2; // @[el2_dec_decode_ctl.scala 362:38] + wire i0_nonblock_load_stall = _T_251 | i0_nonblock_boundary_stall; // @[el2_dec_decode_ctl.scala 362:51] + wire _T_253 = ~i0_predict_br; // @[el2_dec_decode_ctl.scala 371:34] + wire [3:0] _T_255 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 455:36] + wire _T_256 = csr_read & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 383:16] + wire _T_258 = ~csr_read; // @[el2_dec_decode_ctl.scala 384:6] + wire _T_259 = _T_258 & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 384:16] + wire _T_261 = ~io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 385:18] + wire _T_262 = csr_read & _T_261; // @[el2_dec_decode_ctl.scala 385:16] + wire [3:0] _T_264 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] + wire [3:0] _T_265 = i0_dp_load ? 4'h2 : _T_264; // @[Mux.scala 98:16] + wire [3:0] _T_266 = i0_dp_store ? 4'h3 : _T_265; // @[Mux.scala 98:16] + wire [3:0] _T_267 = i0_dp_pm_alu ? 4'h4 : _T_266; // @[Mux.scala 98:16] + wire [3:0] _T_268 = _T_262 ? 4'h5 : _T_267; // @[Mux.scala 98:16] + wire [3:0] _T_269 = _T_259 ? 4'h6 : _T_268; // @[Mux.scala 98:16] + wire [3:0] _T_270 = _T_256 ? 4'h7 : _T_269; // @[Mux.scala 98:16] + wire [3:0] _T_271 = i0_dp_ebreak ? 4'h8 : _T_270; // @[Mux.scala 98:16] + wire [3:0] _T_272 = i0_dp_ecall ? 4'h9 : _T_271; // @[Mux.scala 98:16] + wire [3:0] _T_273 = i0_dp_fence ? 4'ha : _T_272; // @[Mux.scala 98:16] + wire [3:0] _T_274 = i0_dp_fence_i ? 4'hb : _T_273; // @[Mux.scala 98:16] + wire [3:0] _T_275 = i0_dp_mret ? 4'hc : _T_274; // @[Mux.scala 98:16] + wire [3:0] _T_276 = i0_dp_condbr ? 4'hd : _T_275; // @[Mux.scala 98:16] + wire [3:0] _T_277 = i0_dp_jal ? 4'he : _T_276; // @[Mux.scala 98:16] + reg lsu_idle; // @[el2_dec_decode_ctl.scala 396:45] + wire _T_333 = ~i0_pcall_case; // @[el2_dec_decode_ctl.scala 420:35] + wire _T_334 = i0_dp_jal & _T_333; // @[el2_dec_decode_ctl.scala 420:32] + wire _T_335 = ~i0_pja_case; // @[el2_dec_decode_ctl.scala 420:52] + wire _T_336 = _T_334 & _T_335; // @[el2_dec_decode_ctl.scala 420:50] + wire _T_337 = ~i0_pret_case; // @[el2_dec_decode_ctl.scala 420:67] + reg _T_339; // @[el2_dec_decode_ctl.scala 432:58] + wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 574:40] + wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 788:43] reg x_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_876 = io_dec_i0_rs1_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 772:48] - wire _T_877 = x_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 772:80] - wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 772:63] - wire _T_878 = io_dec_i0_rs1_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 773:48] - wire _T_879 = r_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 773:80] - wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 773:63] - wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 779:63] - wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 779:24] - wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 792:58] + wire _T_876 = io_dec_i0_rs1_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 768:48] + wire _T_877 = x_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:80] + wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:63] + wire _T_878 = io_dec_i0_rs1_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 769:48] + wire _T_879 = r_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:80] + wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:63] + wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 775:63] + wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 775:24] + wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 788:58] reg i0_x_c_load; // @[Reg.scala 15:16] reg i0_r_c_load; // @[Reg.scala 15:16] - wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 778:61] - wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 778:24] - wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 792:78] - wire _T_880 = io_dec_i0_rs2_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 775:48] - wire _T_881 = x_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 775:80] - wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 775:63] - wire _T_882 = io_dec_i0_rs2_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 776:48] - wire _T_883 = r_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 776:80] - wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 776:63] - wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 781:63] - wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 781:24] - wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 793:43] - wire _T_896_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 780:61] - wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 780:24] - wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 793:63] - wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 467:42] + wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 774:61] + wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 774:24] + wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 788:78] + wire _T_880 = io_dec_i0_rs2_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 771:48] + wire _T_881 = x_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:80] + wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:63] + wire _T_882 = io_dec_i0_rs2_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 772:48] + wire _T_883 = r_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:80] + wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:63] + wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 777:63] + wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 777:24] + wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 789:43] + wire _T_896_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 776:61] + wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 776:24] + wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 789:63] + wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 463:42] reg r_d_bits_csrwen; // @[el2_lib.scala 524:16] reg r_d_valid; // @[el2_lib.scala 524:16] - wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[el2_dec_decode_ctl.scala 475:39] + wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[el2_dec_decode_ctl.scala 471:39] reg [11:0] r_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 478:50] - wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 478:85] - wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 478:64] - wire _T_358 = _T_357 & r_d_bits_csrwen; // @[el2_dec_decode_ctl.scala 478:100] - wire _T_359 = _T_358 & r_d_valid; // @[el2_dec_decode_ctl.scala 478:118] - wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 478:132] - reg csr_read_x; // @[el2_dec_decode_ctl.scala 480:52] - reg csr_clr_x; // @[el2_dec_decode_ctl.scala 481:51] - reg csr_set_x; // @[el2_dec_decode_ctl.scala 482:51] - reg csr_write_x; // @[el2_dec_decode_ctl.scala 483:53] - reg csr_imm_x; // @[el2_dec_decode_ctl.scala 484:51] - wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[el2_dec_decode_ctl.scala 661:50] + wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:50] + wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:85] + wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:64] + wire _T_358 = _T_357 & r_d_bits_csrwen; // @[el2_dec_decode_ctl.scala 474:100] + wire _T_359 = _T_358 & r_d_valid; // @[el2_dec_decode_ctl.scala 474:118] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:132] + reg csr_read_x; // @[el2_dec_decode_ctl.scala 476:52] + reg csr_clr_x; // @[el2_dec_decode_ctl.scala 477:51] + reg csr_set_x; // @[el2_dec_decode_ctl.scala 478:51] + reg csr_write_x; // @[el2_dec_decode_ctl.scala 479:53] + reg csr_imm_x; // @[el2_dec_decode_ctl.scala 480:51] + wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[el2_dec_decode_ctl.scala 657:50] reg [4:0] csrimm_x; // @[el2_lib.scala 514:16] reg [31:0] csr_rddata_x; // @[el2_lib.scala 514:16] wire [31:0] _T_394 = {27'h0,csrimm_x}; // @[Cat.scala 29:58] - wire _T_396 = ~csr_imm_x; // @[el2_dec_decode_ctl.scala 492:5] + wire _T_396 = ~csr_imm_x; // @[el2_dec_decode_ctl.scala 488:5] wire [31:0] _T_397 = csr_imm_x ? _T_394 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_398 = _T_396 ? io_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] csr_mask_x = _T_397 | _T_398; // @[Mux.scala 27:72] - wire [31:0] _T_400 = ~csr_mask_x; // @[el2_dec_decode_ctl.scala 495:38] - wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[el2_dec_decode_ctl.scala 495:35] - wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[el2_dec_decode_ctl.scala 496:35] + wire [31:0] _T_400 = ~csr_mask_x; // @[el2_dec_decode_ctl.scala 491:38] + wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[el2_dec_decode_ctl.scala 491:35] + wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[el2_dec_decode_ctl.scala 492:35] wire [31:0] _T_403 = csr_clr_x ? _T_401 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_404 = csr_set_x ? _T_402 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_405 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_406 = _T_403 | _T_404; // @[Mux.scala 27:72] wire [31:0] write_csr_data_x = _T_406 | _T_405; // @[Mux.scala 27:72] - wire _T_418 = ~tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 506:44] - wire _T_419 = ~tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 506:64] - wire _T_420 = _T_418 & _T_419; // @[el2_dec_decode_ctl.scala 506:61] - wire [31:0] _T_423 = write_csr_data - 32'h1; // @[el2_dec_decode_ctl.scala 509:59] - wire _T_425 = csr_clr_x | csr_set_x; // @[el2_dec_decode_ctl.scala 511:34] - wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 511:46] - wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 511:61] - wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 511:75] + wire _T_418 = ~tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 502:44] + wire _T_419 = ~tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 502:64] + wire _T_420 = _T_418 & _T_419; // @[el2_dec_decode_ctl.scala 502:61] + wire [31:0] _T_423 = write_csr_data - 32'h1; // @[el2_dec_decode_ctl.scala 505:59] + wire _T_425 = csr_clr_x | csr_set_x; // @[el2_dec_decode_ctl.scala 507:34] + wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 507:46] + wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 507:61] + wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 507:75] reg r_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_764 = r_d_bits_i0v & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 714:42] + wire _T_764 = r_d_bits_i0v & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 710:42] reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16] - wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 714:27] + wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 710:27] reg x_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_432 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[el2_dec_decode_ctl.scala 520:43] + wire _T_432 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:43] reg wbd_bits_csrwonly; // @[el2_lib.scala 524:16] - wire prior_csr_write = _T_432 | wbd_bits_csrwonly; // @[el2_dec_decode_ctl.scala 520:63] - wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 523:48] - wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 524:40] - wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 527:34] - wire _T_437 = _T_436 | debug_fence_i; // @[el2_dec_decode_ctl.scala 527:57] - wire _T_438 = _T_437 | debug_fence_raw; // @[el2_dec_decode_ctl.scala 527:73] - wire i0_presync = _T_438 | io_dec_tlu_pipelining_disable; // @[el2_dec_decode_ctl.scala 527:91] + wire prior_csr_write = _T_432 | wbd_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:63] + wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 519:48] + wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 520:40] + wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 523:34] + wire _T_437 = _T_436 | debug_fence_i; // @[el2_dec_decode_ctl.scala 523:57] + wire _T_438 = _T_437 | debug_fence_raw; // @[el2_dec_decode_ctl.scala 523:73] + wire i0_presync = _T_438 | io_dec_tlu_pipelining_disable; // @[el2_dec_decode_ctl.scala 523:91] wire [31:0] _T_462 = {16'h0,io_ifu_i0_cinst}; // @[Cat.scala 29:58] - wire _T_464 = ~illegal_lockout; // @[el2_dec_decode_ctl.scala 539:44] + wire _T_464 = ~illegal_lockout; // @[el2_dec_decode_ctl.scala 535:44] reg [31:0] _T_465; // @[el2_lib.scala 514:16] - wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[el2_dec_decode_ctl.scala 543:42] - wire _T_470 = i0_dp_csr_read & prior_csr_write; // @[el2_dec_decode_ctl.scala 545:40] - wire _T_471 = _T_470 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 545:59] - wire _T_472 = _T_471 | pause_stall; // @[el2_dec_decode_ctl.scala 545:81] - wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 545:95] - wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 546:20] - wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 546:45] - wire prior_inflight = x_d_valid | r_d_valid; // @[el2_dec_decode_ctl.scala 568:41] - wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[el2_dec_decode_ctl.scala 569:31] - wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 571:37] - wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 546:62] - wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 547:19] - wire _T_478 = ~lsu_idle; // @[el2_dec_decode_ctl.scala 547:36] - wire _T_479 = _T_477 & _T_478; // @[el2_dec_decode_ctl.scala 547:34] - wire _T_480 = _T_476 | _T_479; // @[el2_dec_decode_ctl.scala 546:79] - wire _T_481 = _T_480 | i0_nonblock_load_stall; // @[el2_dec_decode_ctl.scala 547:47] - wire _T_822 = io_dec_i0_rs1_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 742:49] - wire _T_823 = io_div_waddr_wb == i0r_rs1; // @[el2_dec_decode_ctl.scala 742:88] - wire _T_824 = _T_822 & _T_823; // @[el2_dec_decode_ctl.scala 742:69] - wire _T_825 = io_dec_i0_rs2_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 743:25] - wire _T_826 = io_div_waddr_wb == i0r_rs2; // @[el2_dec_decode_ctl.scala 743:64] - wire _T_827 = _T_825 & _T_826; // @[el2_dec_decode_ctl.scala 743:45] - wire i0_nonblock_div_stall = _T_824 | _T_827; // @[el2_dec_decode_ctl.scala 742:102] - wire _T_483 = _T_481 | i0_nonblock_div_stall; // @[el2_dec_decode_ctl.scala 548:21] - wire i0_block_raw_d = _T_483 | i0_div_prior_div_stall; // @[el2_dec_decode_ctl.scala 548:45] - wire _T_484 = io_lsu_store_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 550:65] - wire i0_store_stall_d = i0_dp_store & _T_484; // @[el2_dec_decode_ctl.scala 550:39] - wire _T_485 = io_lsu_load_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 551:63] - wire i0_load_stall_d = i0_dp_load & _T_485; // @[el2_dec_decode_ctl.scala 551:38] - wire _T_486 = i0_block_raw_d | i0_store_stall_d; // @[el2_dec_decode_ctl.scala 552:38] - wire i0_block_d = _T_486 | i0_load_stall_d; // @[el2_dec_decode_ctl.scala 552:57] - wire _T_487 = ~i0_block_d; // @[el2_dec_decode_ctl.scala 556:46] - wire _T_488 = io_dec_ib0_valid_d & _T_487; // @[el2_dec_decode_ctl.scala 556:44] - wire _T_490 = _T_488 & _T_279; // @[el2_dec_decode_ctl.scala 556:61] - wire _T_493 = ~i0_block_raw_d; // @[el2_dec_decode_ctl.scala 557:46] - wire _T_494 = io_dec_ib0_valid_d & _T_493; // @[el2_dec_decode_ctl.scala 557:44] - wire _T_496 = _T_494 & _T_279; // @[el2_dec_decode_ctl.scala 557:61] - wire i0_exudecode_d = _T_496 & _T_467; // @[el2_dec_decode_ctl.scala 557:89] - wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[el2_dec_decode_ctl.scala 558:46] - wire _T_498 = ~io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 562:51] - wire _T_517 = i0_dp_fence_i | debug_fence_i; // @[el2_dec_decode_ctl.scala 590:44] + wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[el2_dec_decode_ctl.scala 539:42] + wire _T_470 = i0_dp_csr_read & prior_csr_write; // @[el2_dec_decode_ctl.scala 541:40] + wire _T_471 = _T_470 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 541:59] + wire _T_472 = _T_471 | pause_stall; // @[el2_dec_decode_ctl.scala 541:81] + wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 541:95] + wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 542:20] + wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 542:45] + wire prior_inflight = x_d_valid | r_d_valid; // @[el2_dec_decode_ctl.scala 564:41] + wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] + wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 567:37] + wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 542:62] + wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 543:19] + wire _T_478 = ~lsu_idle; // @[el2_dec_decode_ctl.scala 543:36] + wire _T_479 = _T_477 & _T_478; // @[el2_dec_decode_ctl.scala 543:34] + wire _T_480 = _T_476 | _T_479; // @[el2_dec_decode_ctl.scala 542:79] + wire _T_481 = _T_480 | i0_nonblock_load_stall; // @[el2_dec_decode_ctl.scala 543:47] + wire _T_822 = io_dec_i0_rs1_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 738:49] + wire _T_823 = io_div_waddr_wb == i0r_rs1; // @[el2_dec_decode_ctl.scala 738:88] + wire _T_824 = _T_822 & _T_823; // @[el2_dec_decode_ctl.scala 738:69] + wire _T_825 = io_dec_i0_rs2_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 739:25] + wire _T_826 = io_div_waddr_wb == i0r_rs2; // @[el2_dec_decode_ctl.scala 739:64] + wire _T_827 = _T_825 & _T_826; // @[el2_dec_decode_ctl.scala 739:45] + wire i0_nonblock_div_stall = _T_824 | _T_827; // @[el2_dec_decode_ctl.scala 738:102] + wire _T_483 = _T_481 | i0_nonblock_div_stall; // @[el2_dec_decode_ctl.scala 544:21] + wire i0_block_raw_d = _T_483 | i0_div_prior_div_stall; // @[el2_dec_decode_ctl.scala 544:45] + wire _T_484 = io_lsu_store_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 546:65] + wire i0_store_stall_d = i0_dp_store & _T_484; // @[el2_dec_decode_ctl.scala 546:39] + wire _T_485 = io_lsu_load_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 547:63] + wire i0_load_stall_d = i0_dp_load & _T_485; // @[el2_dec_decode_ctl.scala 547:38] + wire _T_486 = i0_block_raw_d | i0_store_stall_d; // @[el2_dec_decode_ctl.scala 548:38] + wire i0_block_d = _T_486 | i0_load_stall_d; // @[el2_dec_decode_ctl.scala 548:57] + wire _T_487 = ~i0_block_d; // @[el2_dec_decode_ctl.scala 552:46] + wire _T_488 = io_dec_ib0_valid_d & _T_487; // @[el2_dec_decode_ctl.scala 552:44] + wire _T_490 = _T_488 & _T_280; // @[el2_dec_decode_ctl.scala 552:61] + wire _T_493 = ~i0_block_raw_d; // @[el2_dec_decode_ctl.scala 553:46] + wire _T_494 = io_dec_ib0_valid_d & _T_493; // @[el2_dec_decode_ctl.scala 553:44] + wire _T_496 = _T_494 & _T_280; // @[el2_dec_decode_ctl.scala 553:61] + wire i0_exudecode_d = _T_496 & _T_467; // @[el2_dec_decode_ctl.scala 553:89] + wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[el2_dec_decode_ctl.scala 554:46] + wire _T_498 = ~io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 558:51] + wire _T_517 = i0_dp_fence_i | debug_fence_i; // @[el2_dec_decode_ctl.scala 586:44] wire [3:0] _T_522 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58] - wire _T_704 = |i0_pipe_en[3:2]; // @[el2_dec_decode_ctl.scala 658:49] - wire i0_x_ctl_en = _T_704 | io_clk_override; // @[el2_dec_decode_ctl.scala 658:53] + wire _T_704 = |i0_pipe_en[3:2]; // @[el2_dec_decode_ctl.scala 654:49] + wire i0_x_ctl_en = _T_704 | io_clk_override; // @[el2_dec_decode_ctl.scala 654:53] reg x_t_legal; // @[el2_lib.scala 524:16] reg x_t_icaf; // @[el2_lib.scala 524:16] reg x_t_icaf_f1; // @[el2_lib.scala 524:16] @@ -46839,7 +46861,7 @@ module el2_dec_decode_ctl( reg [3:0] x_t_pmu_i0_itype; // @[el2_lib.scala 524:16] reg x_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] wire [3:0] _T_530 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] - wire [3:0] _T_531 = ~_T_530; // @[el2_dec_decode_ctl.scala 603:39] + wire [3:0] _T_531 = ~_T_530; // @[el2_dec_decode_ctl.scala 599:39] reg r_t_legal; // @[el2_lib.scala 524:16] reg r_t_icaf; // @[el2_lib.scala 524:16] reg r_t_icaf_f1; // @[el2_lib.scala 524:16] @@ -46848,22 +46870,22 @@ module el2_dec_decode_ctl( reg [3:0] r_t_i0trigger; // @[el2_lib.scala 524:16] reg [3:0] r_t_pmu_i0_itype; // @[el2_lib.scala 524:16] reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] - reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 606:36] - reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 607:37] + reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 602:36] + reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 603:37] reg r_d_bits_i0store; // @[el2_lib.scala 524:16] - wire _T_536 = r_d_bits_i0load | r_d_bits_i0store; // @[el2_dec_decode_ctl.scala 611:61] + wire _T_536 = r_d_bits_i0load | r_d_bits_i0store; // @[el2_dec_decode_ctl.scala 607:61] wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] - wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 611:82] - wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 611:105] + wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:82] + wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:105] reg r_d_bits_i0div; // @[el2_lib.scala 524:16] - wire _T_545 = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 617:58] - wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 628:49] - wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 629:49] - wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 630:48] - wire i0_rd_en_d = i0_dp_rd & _T_560; // @[el2_dec_decode_ctl.scala 630:37] - wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 634:38] - wire _T_561 = ~i0_dp_jal; // @[el2_dec_decode_ctl.scala 635:27] - wire i0_uiimm20 = _T_561 & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 635:38] + wire _T_545 = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 613:58] + wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 624:49] + wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 625:49] + wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 626:48] + wire i0_rd_en_d = i0_dp_rd & _T_560; // @[el2_dec_decode_ctl.scala 626:37] + wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 630:38] + wire _T_561 = ~i0_dp_jal; // @[el2_dec_decode_ctl.scala 631:27] + wire i0_uiimm20 = _T_561 & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 631:38] wire [31:0] _T_563 = i0_dp_csr_read ? io_dec_csr_rddata_d : 32'h0; // @[Mux.scala 27:72] wire [9:0] _T_577 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] wire [18:0] _T_586 = {_T_577,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] @@ -46878,55 +46900,55 @@ module el2_dec_decode_ctl( wire [31:0] _T_652 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] wire [31:0] _T_687 = i0_uiimm20 ? _T_652 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_691 = _T_690 | _T_687; // @[Mux.scala 27:72] - wire _T_653 = i0_csr_write_only_d & i0_dp_csr_imm; // @[el2_dec_decode_ctl.scala 646:26] + wire _T_653 = i0_csr_write_only_d & i0_dp_csr_imm; // @[el2_dec_decode_ctl.scala 642:26] wire [31:0] _T_683 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] wire [31:0] _T_688 = _T_653 ? _T_683 : 32'h0; // @[Mux.scala 27:72] wire [31:0] i0_immed_d = _T_691 | _T_688; // @[Mux.scala 27:72] wire [31:0] _T_564 = _T_347 ? i0_immed_d : 32'h0; // @[Mux.scala 27:72] - wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 650:44] - wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 651:44] - wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 652:44] + wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 646:44] + wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 647:44] + wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 648:44] reg i0_x_c_mul; // @[Reg.scala 15:16] reg i0_x_c_alu; // @[Reg.scala 15:16] reg i0_r_c_mul; // @[Reg.scala 15:16] reg i0_r_c_alu; // @[Reg.scala 15:16] - wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 660:49] - wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 662:50] + wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 656:49] + wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 658:50] reg x_d_bits_i0store; // @[el2_lib.scala 524:16] reg x_d_bits_i0div; // @[el2_lib.scala 524:16] reg x_d_bits_csrwen; // @[el2_lib.scala 524:16] reg [11:0] x_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_733 = x_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 684:47] - wire _T_737 = x_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 685:33] - wire _T_756 = ~r_d_bits_i0div; // @[el2_dec_decode_ctl.scala 700:49] - wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 700:47] - wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 700:70] - wire _T_761 = x_d_bits_i0v & x_d_bits_i0load; // @[el2_dec_decode_ctl.scala 709:47] - wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 715:52] + wire _T_733 = x_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:47] + wire _T_737 = x_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 681:33] + wire _T_756 = ~r_d_bits_i0div; // @[el2_dec_decode_ctl.scala 696:49] + wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 696:47] + wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:70] + wire _T_761 = x_d_bits_i0v & x_d_bits_i0load; // @[el2_dec_decode_ctl.scala 705:47] + wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 711:52] wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16] - wire _T_799 = x_d_bits_i0div & x_d_valid; // @[el2_dec_decode_ctl.scala 723:45] - wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 723:58] - wire _T_802 = x_d_bits_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 725:77] - wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 725:60] - wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 726:33] - wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 725:94] - wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 727:33] - wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 727:60] - wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 726:62] - wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 731:51] - wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 732:26] - wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 732:24] - wire _T_813 = r_d_bits_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 732:56] - wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 732:39] - wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 732:77] - wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 731:65] - wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 735:55] - wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 737:62] - wire _T_818 = io_dec_div_active & _T_817; // @[el2_dec_decode_ctl.scala 737:60] - wire _T_819 = ~nonblock_div_cancel; // @[el2_dec_decode_ctl.scala 737:81] - wire _T_820 = _T_818 & _T_819; // @[el2_dec_decode_ctl.scala 737:79] - reg _T_821; // @[el2_dec_decode_ctl.scala 739:54] + wire _T_799 = x_d_bits_i0div & x_d_valid; // @[el2_dec_decode_ctl.scala 719:45] + wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:58] + wire _T_802 = x_d_bits_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:77] + wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:60] + wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:33] + wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:94] + wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:33] + wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:60] + wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:62] + wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 727:51] + wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 728:26] + wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 728:24] + wire _T_813 = r_d_bits_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:56] + wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 728:39] + wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:77] + wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 727:65] + wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 731:55] + wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 733:62] + wire _T_818 = io_dec_div_active & _T_817; // @[el2_dec_decode_ctl.scala 733:60] + wire _T_819 = ~nonblock_div_cancel; // @[el2_dec_decode_ctl.scala 733:81] + wire _T_820 = _T_818 & _T_819; // @[el2_dec_decode_ctl.scala 733:79] + reg _T_821; // @[el2_dec_decode_ctl.scala 735:54] reg [4:0] _T_830; // @[Reg.scala 27:20] reg [31:0] i0_inst_x; // @[el2_lib.scala 514:16] reg [31:0] i0_inst_r; // @[el2_lib.scala 514:16] @@ -46934,86 +46956,92 @@ module el2_dec_decode_ctl( reg [31:0] _T_837; // @[el2_lib.scala 514:16] reg [30:0] i0_pc_wb; // @[el2_lib.scala 514:16] reg [30:0] _T_840; // @[el2_lib.scala 514:16] + reg [30:0] dec_i0_pc_r; // @[el2_lib.scala 514:16] + wire [31:0] _T_842 = {io_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_843 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_846 = {{1'd0}, _T_843[12:1]}; // @[el2_lib.scala 208:31] - wire [18:0] _T_852 = 19'h0 - 19'h1; // @[el2_lib.scala 210:27] + wire [12:0] _T_846 = _T_842[12:1] + _T_843[12:1]; // @[el2_lib.scala 208:31] + wire [18:0] _T_849 = _T_842[31:13] + 19'h1; // @[el2_lib.scala 209:27] + wire [18:0] _T_852 = _T_842[31:13] - 19'h1; // @[el2_lib.scala 210:27] wire _T_855 = ~_T_846[12]; // @[el2_lib.scala 212:28] + wire _T_856 = _T_843[12] ^ _T_855; // @[el2_lib.scala 212:26] wire _T_859 = ~_T_843[12]; // @[el2_lib.scala 213:20] wire _T_861 = _T_859 & _T_846[12]; // @[el2_lib.scala 213:26] wire _T_865 = _T_843[12] & _T_855; // @[el2_lib.scala 214:26] - wire [18:0] _T_868 = _T_861 ? 19'h1 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_867 = _T_856 ? _T_842[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_868 = _T_861 ? _T_849 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_869 = _T_865 ? _T_852 : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_871 = _T_868 | _T_869; // @[Mux.scala 27:72] + wire [18:0] _T_870 = _T_867 | _T_868; // @[Mux.scala 27:72] + wire [18:0] _T_871 = _T_870 | _T_869; // @[Mux.scala 27:72] wire [31:0] temp_pred_correct_npc_x = {_T_871,_T_846[11:0],1'h0}; // @[Cat.scala 29:58] - wire _T_887_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 778:61] - wire _T_887_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 778:61] - wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_887_mul; // @[el2_dec_decode_ctl.scala 778:24] - wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_887_alu; // @[el2_dec_decode_ctl.scala 778:24] - wire _T_896_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 780:61] - wire _T_896_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 780:61] - wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_896_mul; // @[el2_dec_decode_ctl.scala 780:24] - wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_896_alu; // @[el2_dec_decode_ctl.scala 780:24] - wire _T_909 = io_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 798:62] - wire _T_910 = io_dec_nonblock_load_waddr == i0r_rs1; // @[el2_dec_decode_ctl.scala 798:119] - wire i0_rs1_nonblock_load_bypass_en_d = _T_909 & _T_910; // @[el2_dec_decode_ctl.scala 798:89] - wire _T_911 = io_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 800:62] - wire _T_912 = io_dec_nonblock_load_waddr == i0r_rs2; // @[el2_dec_decode_ctl.scala 800:119] - wire i0_rs2_nonblock_load_bypass_en_d = _T_911 & _T_912; // @[el2_dec_decode_ctl.scala 800:89] - wire _T_914 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[el2_dec_decode_ctl.scala 803:66] - wire _T_915 = i0_rs1_depth_d[0] & _T_914; // @[el2_dec_decode_ctl.scala 803:45] - wire _T_917 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 803:108] - wire _T_920 = _T_914 | i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 803:196] - wire _T_921 = i0_rs1_depth_d[1] & _T_920; // @[el2_dec_decode_ctl.scala 803:153] + wire _T_887_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 774:61] + wire _T_887_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 774:61] + wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_887_mul; // @[el2_dec_decode_ctl.scala 774:24] + wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_887_alu; // @[el2_dec_decode_ctl.scala 774:24] + wire _T_896_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 776:61] + wire _T_896_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 776:61] + wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_896_mul; // @[el2_dec_decode_ctl.scala 776:24] + wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_896_alu; // @[el2_dec_decode_ctl.scala 776:24] + wire _T_909 = io_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 794:62] + wire _T_910 = io_dec_nonblock_load_waddr == i0r_rs1; // @[el2_dec_decode_ctl.scala 794:119] + wire i0_rs1_nonblock_load_bypass_en_d = _T_909 & _T_910; // @[el2_dec_decode_ctl.scala 794:89] + wire _T_911 = io_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 796:62] + wire _T_912 = io_dec_nonblock_load_waddr == i0r_rs2; // @[el2_dec_decode_ctl.scala 796:119] + wire i0_rs2_nonblock_load_bypass_en_d = _T_911 & _T_912; // @[el2_dec_decode_ctl.scala 796:89] + wire _T_914 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[el2_dec_decode_ctl.scala 799:66] + wire _T_915 = i0_rs1_depth_d[0] & _T_914; // @[el2_dec_decode_ctl.scala 799:45] + wire _T_917 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 799:108] + wire _T_920 = _T_914 | i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 799:196] + wire _T_921 = i0_rs1_depth_d[1] & _T_920; // @[el2_dec_decode_ctl.scala 799:153] wire [2:0] i0_rs1bypass = {_T_915,_T_917,_T_921}; // @[Cat.scala 29:58] - wire _T_925 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[el2_dec_decode_ctl.scala 805:67] - wire _T_926 = i0_rs2_depth_d[0] & _T_925; // @[el2_dec_decode_ctl.scala 805:45] - wire _T_928 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 805:109] - wire _T_931 = _T_925 | i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 805:196] - wire _T_932 = i0_rs2_depth_d[1] & _T_931; // @[el2_dec_decode_ctl.scala 805:153] + wire _T_925 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[el2_dec_decode_ctl.scala 801:67] + wire _T_926 = i0_rs2_depth_d[0] & _T_925; // @[el2_dec_decode_ctl.scala 801:45] + wire _T_928 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 801:109] + wire _T_931 = _T_925 | i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 801:196] + wire _T_932 = i0_rs2_depth_d[1] & _T_931; // @[el2_dec_decode_ctl.scala 801:153] wire [2:0] i0_rs2bypass = {_T_926,_T_928,_T_932}; // @[Cat.scala 29:58] - wire _T_938 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 807:75] - wire _T_940 = ~i0_rs1bypass[2]; // @[el2_dec_decode_ctl.scala 807:96] - wire _T_941 = _T_940 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 807:113] - wire _T_942 = _T_938 | _T_941; // @[el2_dec_decode_ctl.scala 807:93] - wire _T_947 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 808:75] - wire _T_949 = ~i0_rs2bypass[2]; // @[el2_dec_decode_ctl.scala 808:96] - wire _T_950 = _T_949 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 808:113] - wire _T_951 = _T_947 | _T_950; // @[el2_dec_decode_ctl.scala 808:93] - wire _T_958 = ~i0_rs1bypass[1]; // @[el2_dec_decode_ctl.scala 813:6] - wire _T_960 = ~i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 813:25] - wire _T_961 = _T_958 & _T_960; // @[el2_dec_decode_ctl.scala 813:23] - wire _T_962 = _T_961 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 813:42] + wire _T_938 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 803:75] + wire _T_940 = ~i0_rs1bypass[2]; // @[el2_dec_decode_ctl.scala 803:96] + wire _T_941 = _T_940 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 803:113] + wire _T_942 = _T_938 | _T_941; // @[el2_dec_decode_ctl.scala 803:93] + wire _T_947 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 804:75] + wire _T_949 = ~i0_rs2bypass[2]; // @[el2_dec_decode_ctl.scala 804:96] + wire _T_950 = _T_949 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 804:113] + wire _T_951 = _T_947 | _T_950; // @[el2_dec_decode_ctl.scala 804:93] + wire _T_958 = ~i0_rs1bypass[1]; // @[el2_dec_decode_ctl.scala 810:6] + wire _T_960 = ~i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 810:25] + wire _T_961 = _T_958 & _T_960; // @[el2_dec_decode_ctl.scala 810:23] + wire _T_962 = _T_961 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 810:42] wire [31:0] _T_964 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_965 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_966 = _T_962 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_967 = _T_964 | _T_965; // @[Mux.scala 27:72] - wire _T_975 = ~i0_rs2bypass[1]; // @[el2_dec_decode_ctl.scala 818:6] - wire _T_977 = ~i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 818:25] - wire _T_978 = _T_975 & _T_977; // @[el2_dec_decode_ctl.scala 818:23] - wire _T_979 = _T_978 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 818:42] + wire _T_975 = ~i0_rs2bypass[1]; // @[el2_dec_decode_ctl.scala 815:6] + wire _T_977 = ~i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 815:25] + wire _T_978 = _T_975 & _T_977; // @[el2_dec_decode_ctl.scala 815:23] + wire _T_979 = _T_978 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 815:42] wire [31:0] _T_981 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_982 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_983 = _T_979 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_984 = _T_981 | _T_982; // @[Mux.scala 27:72] - wire _T_987 = i0_dp_raw_load | i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 820:68] - wire _T_988 = io_dec_ib0_valid_d & _T_987; // @[el2_dec_decode_ctl.scala 820:50] - wire _T_989 = ~io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 820:89] - wire _T_990 = _T_988 & _T_989; // @[el2_dec_decode_ctl.scala 820:87] - wire _T_992 = _T_990 & _T_493; // @[el2_dec_decode_ctl.scala 820:112] - wire _T_994 = ~io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 822:6] - wire _T_995 = _T_994 & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 822:27] - wire _T_996 = _T_995 & i0_dp_load; // @[el2_dec_decode_ctl.scala 822:39] - wire _T_1001 = _T_995 & i0_dp_store; // @[el2_dec_decode_ctl.scala 823:39] + wire _T_987 = i0_dp_raw_load | i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 817:68] + wire _T_988 = io_dec_ib0_valid_d & _T_987; // @[el2_dec_decode_ctl.scala 817:50] + wire _T_989 = ~io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 817:89] + wire _T_990 = _T_988 & _T_989; // @[el2_dec_decode_ctl.scala 817:87] + wire _T_992 = _T_990 & _T_493; // @[el2_dec_decode_ctl.scala 817:112] + wire _T_994 = ~io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 819:6] + wire _T_995 = _T_994 & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 819:27] + wire _T_996 = _T_995 & i0_dp_load; // @[el2_dec_decode_ctl.scala 819:39] + wire _T_1001 = _T_995 & i0_dp_store; // @[el2_dec_decode_ctl.scala 820:39] wire [11:0] _T_1005 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] wire [11:0] _T_1006 = _T_996 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_1007 = _T_1001 ? _T_1005 : 12'h0; // @[Mux.scala 27:72] - rvclkhdr data_gated_cgc ( // @[el2_dec_decode_ctl.scala 222:29] - .io_l1clk(data_gated_cgc_io_l1clk), - .io_clk(data_gated_cgc_io_clk), - .io_en(data_gated_cgc_io_en), - .io_scan_mode(data_gated_cgc_io_scan_mode) + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) ); - el2_dec_dec_ctl i0_dec ( // @[el2_dec_decode_ctl.scala 396:22] + el2_dec_dec_ctl i0_dec ( // @[el2_dec_decode_ctl.scala 392:22] .io_ins(i0_dec_io_ins), .io_out_alu(i0_dec_io_out_alu), .io_out_rs1(i0_dec_io_out_rs1), @@ -47022,6 +47050,7 @@ module el2_dec_decode_ctl( .io_out_rd(i0_dec_io_out_rd), .io_out_shimm5(i0_dec_io_out_shimm5), .io_out_imm20(i0_dec_io_out_imm20), + .io_out_pc(i0_dec_io_out_pc), .io_out_load(i0_dec_io_out_load), .io_out_store(i0_dec_io_out_store), .io_out_lsu(i0_dec_io_out_lsu), @@ -47065,12 +47094,6 @@ module el2_dec_decode_ctl( .io_out_pm_alu(i0_dec_io_out_pm_alu), .io_out_legal(i0_dec_io_out_legal) ); - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), @@ -47089,7 +47112,7 @@ module el2_dec_decode_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 518:23] + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), @@ -47119,7 +47142,7 @@ module el2_dec_decode_ctl( .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 518:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), @@ -47179,130 +47202,134 @@ module el2_dec_decode_ctl( .io_en(rvclkhdr_18_io_en), .io_scan_mode(rvclkhdr_18_io_scan_mode) ); - assign io_dec_extint_stall = _T_339; // @[el2_dec_decode_ctl.scala 436:23] - assign io_dec_i0_inst_wb1 = _T_837; // @[el2_dec_decode_ctl.scala 757:22] - assign io_dec_i0_pc_wb1 = _T_840; // @[el2_dec_decode_ctl.scala 760:20] - assign io_dec_i0_rs1_en_d = i0_dp_rs1 & _T_556; // @[el2_dec_decode_ctl.scala 628:24] - assign io_dec_i0_rs2_en_d = i0_dp_rs2 & _T_558; // @[el2_dec_decode_ctl.scala 629:24] - assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 631:19] - assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 632:19] - assign io_dec_i0_immed_d = _T_563 | _T_564; // @[el2_dec_decode_ctl.scala 637:21] - assign io_dec_i0_br_immed_d = _T_768 ? i0_br_offset : _T_781; // @[el2_dec_decode_ctl.scala 715:24] - assign io_i0_ap_land = _T_40 ? 1'h0 : i0_dp_raw_land; // @[el2_dec_decode_ctl.scala 289:20] - assign io_i0_ap_lor = _T_40 | i0_dp_raw_lor; // @[el2_dec_decode_ctl.scala 290:20] - assign io_i0_ap_lxor = _T_40 ? 1'h0 : i0_dp_raw_lxor; // @[el2_dec_decode_ctl.scala 291:20] - assign io_i0_ap_sll = _T_40 ? 1'h0 : i0_dp_raw_sll; // @[el2_dec_decode_ctl.scala 292:20] - assign io_i0_ap_srl = _T_40 ? 1'h0 : i0_dp_raw_srl; // @[el2_dec_decode_ctl.scala 293:20] - assign io_i0_ap_sra = _T_40 ? 1'h0 : i0_dp_raw_sra; // @[el2_dec_decode_ctl.scala 294:20] - assign io_i0_ap_beq = _T_40 ? 1'h0 : i0_dp_raw_beq; // @[el2_dec_decode_ctl.scala 297:20] - assign io_i0_ap_bne = _T_40 ? 1'h0 : i0_dp_raw_bne; // @[el2_dec_decode_ctl.scala 298:20] - assign io_i0_ap_blt = _T_40 ? 1'h0 : i0_dp_raw_blt; // @[el2_dec_decode_ctl.scala 299:20] - assign io_i0_ap_bge = _T_40 ? 1'h0 : i0_dp_raw_bge; // @[el2_dec_decode_ctl.scala 300:20] - assign io_i0_ap_add = _T_40 ? 1'h0 : i0_dp_raw_add; // @[el2_dec_decode_ctl.scala 287:20] - assign io_i0_ap_sub = _T_40 ? 1'h0 : i0_dp_raw_sub; // @[el2_dec_decode_ctl.scala 288:20] - assign io_i0_ap_slt = _T_40 ? 1'h0 : i0_dp_raw_slt; // @[el2_dec_decode_ctl.scala 295:20] - assign io_i0_ap_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 296:20] - assign io_i0_ap_jal = _T_336 & _T_337; // @[el2_dec_decode_ctl.scala 303:22] - assign io_i0_ap_predict_t = _T_46 & i0_predict_br; // @[el2_dec_decode_ctl.scala 285:26] - assign io_i0_ap_predict_nt = _T_47 & i0_predict_br; // @[el2_dec_decode_ctl.scala 284:26] - assign io_i0_ap_csr_write = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 301:22] - assign io_i0_ap_csr_imm = _T_40 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 302:22] - assign io_dec_i0_decode_d = _T_490 & _T_467; // @[el2_dec_decode_ctl.scala 556:22 el2_dec_decode_ctl.scala 622:22] - assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 576:26] - assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 810:31] - assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 815:31] - assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[el2_dec_decode_ctl.scala 698:27] - assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 700:32] - assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 701:26] - assign io_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_942}; // @[el2_dec_decode_ctl.scala 807:34] - assign io_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_951}; // @[el2_dec_decode_ctl.scala 808:34] - assign io_lsu_p_valid = io_dec_extint_stall | lsu_decode_d; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 443:24 el2_dec_decode_ctl.scala 445:35] - assign io_lsu_p_bits_fast_int = io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 442:29] - assign io_lsu_p_bits_by = io_dec_extint_stall ? 1'h0 : i0_dp_by; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 448:40] - assign io_lsu_p_bits_half = io_dec_extint_stall ? 1'h0 : i0_dp_half; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 449:40] - assign io_lsu_p_bits_word = io_dec_extint_stall | i0_dp_word; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 441:29 el2_dec_decode_ctl.scala 450:40] - assign io_lsu_p_bits_load = io_dec_extint_stall | i0_dp_load; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 440:29 el2_dec_decode_ctl.scala 446:40] - assign io_lsu_p_bits_store = io_dec_extint_stall ? 1'h0 : i0_dp_store; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 447:40] - assign io_lsu_p_bits_unsign = io_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 454:40] - assign io_lsu_p_bits_store_data_bypass_d = io_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 452:40] - assign io_lsu_p_bits_load_ldst_bypass_d = io_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 451:40] - assign io_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 431:21] - assign io_mul_p_bits_rs1_sign = _T_40 ? 1'h0 : i0_dp_raw_rs1_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 432:26] - assign io_mul_p_bits_rs2_sign = _T_40 ? 1'h0 : i0_dp_raw_rs2_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 433:26] - assign io_mul_p_bits_low = _T_40 ? 1'h0 : i0_dp_raw_low; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 434:26] - assign io_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 427:21] - assign io_div_p_bits_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 428:26] - assign io_div_p_bits_rem = _T_40 ? 1'h0 : i0_dp_raw_rem; // @[el2_dec_decode_ctl.scala 429:26] - assign io_div_waddr_wb = _T_830; // @[el2_dec_decode_ctl.scala 745:19] - assign io_dec_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 734:29] - assign io_dec_lsu_valid_raw_d = _T_992 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 820:26] - assign io_dec_lsu_offset_d = _T_1006 | _T_1007; // @[el2_dec_decode_ctl.scala 821:23] - assign io_dec_csr_ren_d = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 458:21] - assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[el2_dec_decode_ctl.scala 467:24] - assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 533:24] - assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 470:24] - assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 475:20] - assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[el2_dec_decode_ctl.scala 471:23] - assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 518:24] - assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 478:27] - assign io_dec_tlu_i0_valid_r = r_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 582:29] - assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 616:39 el2_dec_decode_ctl.scala 617:39] - assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_i0_pc_r = 31'h0; // @[el2_dec_decode_ctl.scala 763:27] - assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 540:23] - assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 768:25] - assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 240:38] - assign io_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 238:43] - assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[el2_dec_decode_ctl.scala 239:43] - assign io_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[12:1] : _T_323; // @[el2_dec_decode_ctl.scala 252:49] - assign io_dec_i0_predict_p_d_bits_br_error = _T_32 & _T_17; // @[el2_dec_decode_ctl.scala 247:56] - assign io_dec_i0_predict_p_d_bits_br_start_error = _T_35 & _T_17; // @[el2_dec_decode_ctl.scala 248:56] - assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[el2_dec_decode_ctl.scala 237:43] - assign io_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 234:43] - assign io_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 236:43] - assign io_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 235:43] - assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[el2_dec_decode_ctl.scala 254:56] - assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 253:32] - assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 249:32] - assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 250:32] - assign io_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[el2_dec_decode_ctl.scala 666:27] - assign io_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[el2_dec_decode_ctl.scala 667:27] - assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 561:28] - assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_498; // @[el2_dec_decode_ctl.scala 562:27] - assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 564:29] - assign io_dec_pmu_postsync_stall = postsync_stall; // @[el2_dec_decode_ctl.scala 563:29] - assign io_dec_nonblock_load_wen = _T_199 & _T_200; // @[el2_dec_decode_ctl.scala 358:28] - assign io_dec_nonblock_load_waddr = _T_245 | _T_237; // @[el2_dec_decode_ctl.scala 355:29 el2_dec_decode_ctl.scala 365:29] - assign io_dec_pause_state = pause_stall; // @[el2_dec_decode_ctl.scala 502:22] - assign io_dec_pause_state_cg = pause_stall & _T_420; // @[el2_dec_decode_ctl.scala 506:25] - assign io_dec_div_active = _T_821; // @[el2_dec_decode_ctl.scala 739:21] - assign data_gated_cgc_io_clk = clock; // @[el2_dec_decode_ctl.scala 225:31] - assign data_gated_cgc_io_en = _T_15 | _T_16; // @[el2_dec_decode_ctl.scala 223:31] - assign data_gated_cgc_io_scan_mode = io_scan_mode; // @[el2_dec_decode_ctl.scala 224:31] - assign i0_dec_io_ins = io_dec_i0_instr_d; // @[el2_dec_decode_ctl.scala 397:16] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_19_io_l1clk), + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en), + .io_scan_mode(rvclkhdr_19_io_scan_mode) + ); + assign io_dec_extint_stall = _T_339; // @[el2_dec_decode_ctl.scala 432:23] + assign io_dec_i0_inst_wb1 = _T_837; // @[el2_dec_decode_ctl.scala 753:22] + assign io_dec_i0_pc_wb1 = _T_840; // @[el2_dec_decode_ctl.scala 756:20] + assign io_dec_i0_rs1_en_d = i0_dp_rs1 & _T_556; // @[el2_dec_decode_ctl.scala 624:24] + assign io_dec_i0_rs2_en_d = i0_dp_rs2 & _T_558; // @[el2_dec_decode_ctl.scala 625:24] + assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 627:19] + assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 628:19] + assign io_dec_i0_immed_d = _T_563 | _T_564; // @[el2_dec_decode_ctl.scala 633:21] + assign io_dec_i0_br_immed_d = _T_768 ? i0_br_offset : _T_781; // @[el2_dec_decode_ctl.scala 711:24] + assign io_i0_ap_land = _T_41 ? 1'h0 : i0_dp_raw_land; // @[el2_dec_decode_ctl.scala 285:20] + assign io_i0_ap_lor = _T_41 | i0_dp_raw_lor; // @[el2_dec_decode_ctl.scala 286:20] + assign io_i0_ap_lxor = _T_41 ? 1'h0 : i0_dp_raw_lxor; // @[el2_dec_decode_ctl.scala 287:20] + assign io_i0_ap_sll = _T_41 ? 1'h0 : i0_dp_raw_sll; // @[el2_dec_decode_ctl.scala 288:20] + assign io_i0_ap_srl = _T_41 ? 1'h0 : i0_dp_raw_srl; // @[el2_dec_decode_ctl.scala 289:20] + assign io_i0_ap_sra = _T_41 ? 1'h0 : i0_dp_raw_sra; // @[el2_dec_decode_ctl.scala 290:20] + assign io_i0_ap_beq = _T_41 ? 1'h0 : i0_dp_raw_beq; // @[el2_dec_decode_ctl.scala 293:20] + assign io_i0_ap_bne = _T_41 ? 1'h0 : i0_dp_raw_bne; // @[el2_dec_decode_ctl.scala 294:20] + assign io_i0_ap_blt = _T_41 ? 1'h0 : i0_dp_raw_blt; // @[el2_dec_decode_ctl.scala 295:20] + assign io_i0_ap_bge = _T_41 ? 1'h0 : i0_dp_raw_bge; // @[el2_dec_decode_ctl.scala 296:20] + assign io_i0_ap_add = _T_41 ? 1'h0 : i0_dp_raw_add; // @[el2_dec_decode_ctl.scala 283:20] + assign io_i0_ap_sub = _T_41 ? 1'h0 : i0_dp_raw_sub; // @[el2_dec_decode_ctl.scala 284:20] + assign io_i0_ap_slt = _T_41 ? 1'h0 : i0_dp_raw_slt; // @[el2_dec_decode_ctl.scala 291:20] + assign io_i0_ap_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 292:20] + assign io_i0_ap_jal = _T_336 & _T_337; // @[el2_dec_decode_ctl.scala 299:22] + assign io_i0_ap_predict_t = _T_47 & i0_predict_br; // @[el2_dec_decode_ctl.scala 281:26] + assign io_i0_ap_predict_nt = _T_48 & i0_predict_br; // @[el2_dec_decode_ctl.scala 280:26] + assign io_i0_ap_csr_write = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 297:22] + assign io_i0_ap_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 298:22] + assign io_dec_i0_decode_d = _T_490 & _T_467; // @[el2_dec_decode_ctl.scala 552:22 el2_dec_decode_ctl.scala 618:22] + assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 572:26] + assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 807:31] + assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 812:31] + assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[el2_dec_decode_ctl.scala 694:27] + assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 696:32] + assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 697:26] + assign io_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 271:25] + assign io_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_942}; // @[el2_dec_decode_ctl.scala 803:34] + assign io_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_951}; // @[el2_dec_decode_ctl.scala 804:34] + assign io_lsu_p_valid = io_dec_extint_stall | lsu_decode_d; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 439:24 el2_dec_decode_ctl.scala 441:35] + assign io_lsu_p_bits_fast_int = io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 438:29] + assign io_lsu_p_bits_by = io_dec_extint_stall ? 1'h0 : i0_dp_by; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 444:40] + assign io_lsu_p_bits_half = io_dec_extint_stall ? 1'h0 : i0_dp_half; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 445:40] + assign io_lsu_p_bits_word = io_dec_extint_stall | i0_dp_word; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 437:29 el2_dec_decode_ctl.scala 446:40] + assign io_lsu_p_bits_load = io_dec_extint_stall | i0_dp_load; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 436:29 el2_dec_decode_ctl.scala 442:40] + assign io_lsu_p_bits_store = io_dec_extint_stall ? 1'h0 : i0_dp_store; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 443:40] + assign io_lsu_p_bits_unsign = io_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 450:40] + assign io_lsu_p_bits_store_data_bypass_d = io_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 448:40] + assign io_lsu_p_bits_load_ldst_bypass_d = io_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 447:40] + assign io_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 427:21] + assign io_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 428:26] + assign io_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 429:26] + assign io_mul_p_bits_low = _T_41 ? 1'h0 : i0_dp_raw_low; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 430:26] + assign io_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 423:21] + assign io_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 424:26] + assign io_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[el2_dec_decode_ctl.scala 425:26] + assign io_div_waddr_wb = _T_830; // @[el2_dec_decode_ctl.scala 741:19] + assign io_dec_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 730:29] + assign io_dec_lsu_valid_raw_d = _T_992 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 817:26] + assign io_dec_lsu_offset_d = _T_1006 | _T_1007; // @[el2_dec_decode_ctl.scala 818:23] + assign io_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 454:21] + assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[el2_dec_decode_ctl.scala 463:24] + assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 529:24] + assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 466:24] + assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 471:20] + assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] + assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] + assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 474:27] + assign io_dec_tlu_i0_valid_r = r_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] + assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] + assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 759:27] + assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 536:23] + assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 764:25] + assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 236:38] + assign io_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 234:43] + assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[el2_dec_decode_ctl.scala 235:43] + assign io_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 248:49] + assign io_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[el2_dec_decode_ctl.scala 243:56] + assign io_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[el2_dec_decode_ctl.scala 244:56] + assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[el2_dec_decode_ctl.scala 233:43] + assign io_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 230:43] + assign io_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 232:43] + assign io_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 231:43] + assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[el2_dec_decode_ctl.scala 250:56] + assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 249:32] + assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 245:32] + assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 246:32] + assign io_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[el2_dec_decode_ctl.scala 662:27] + assign io_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[el2_dec_decode_ctl.scala 663:27] + assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 557:28] + assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_498; // @[el2_dec_decode_ctl.scala 558:27] + assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 560:29] + assign io_dec_pmu_postsync_stall = postsync_stall; // @[el2_dec_decode_ctl.scala 559:29] + assign io_dec_nonblock_load_wen = _T_200 & _T_201; // @[el2_dec_decode_ctl.scala 354:28] + assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[el2_dec_decode_ctl.scala 351:29 el2_dec_decode_ctl.scala 361:29] + assign io_dec_pause_state = pause_stall; // @[el2_dec_decode_ctl.scala 498:22] + assign io_dec_pause_state_cg = pause_stall & _T_420; // @[el2_dec_decode_ctl.scala 502:25] + assign io_dec_div_active = _T_821; // @[el2_dec_decode_ctl.scala 735:21] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = _T_15 | _T_16; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign i0_dec_io_ins = io_dec_i0_instr_d; // @[el2_dec_decode_ctl.scala 393:16] assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = _T_428 | pause_stall; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = shift_illegal & _T_464; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_en = _T_428 | pause_stall; // @[el2_lib.scala 511:17] assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_4_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = shift_illegal & _T_464; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 520:18] assign rvclkhdr_5_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] @@ -47310,41 +47337,44 @@ module el2_dec_decode_ctl( assign rvclkhdr_6_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_7_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_8_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 521:17] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_9_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_9_io_en = _T_710 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_10_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_10_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_11_io_en = i0_legal_decode_d & i0_dp_div; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_12_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_12_io_en = i0_legal_decode_d & i0_dp_div; // @[el2_lib.scala 511:17] assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_13_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_13_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_14_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_14_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_15_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_15_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_16_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_16_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_17_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_17_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_18_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_18_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_19_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -47560,6 +47590,8 @@ initial begin i0_pc_wb = _RAND_88[30:0]; _RAND_89 = {1{`RANDOM}}; _T_840 = _RAND_89[30:0]; + _RAND_90 = {1{`RANDOM}}; + dec_i0_pc_r = _RAND_90[30:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin tlu_wr_pause_r1 = 1'h0; @@ -47813,6 +47845,9 @@ initial begin if (reset) begin _T_840 = 31'h0; end + if (reset) begin + dec_i0_pc_r = 31'h0; + end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL @@ -47839,42 +47874,42 @@ end // initial i0_r_c_alu <= i0_x_c_alu; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin tlu_wr_pause_r1 <= 1'h0; end else begin tlu_wr_pause_r1 <= io_dec_tlu_wr_pause_r; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin tlu_wr_pause_r2 <= 1'h0; end else begin tlu_wr_pause_r2 <= tlu_wr_pause_r1; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin leak1_i1_stall <= 1'h0; end else begin - leak1_i1_stall <= io_dec_tlu_flush_leak_one_r | _T_280; + leak1_i1_stall <= io_dec_tlu_flush_leak_one_r | _T_281; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin leak1_i0_stall <= 1'h0; end else begin - leak1_i0_stall <= _T_283 | _T_285; + leak1_i0_stall <= _T_284 | _T_286; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin pause_stall <= 1'h0; end else begin pause_stall <= _T_412 & _T_413; end end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin write_csr_data <= 32'h0; end else if (pause_stall) begin @@ -47885,28 +47920,28 @@ end // initial write_csr_data <= write_csr_data_x; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin postsync_stall <= 1'h0; end else begin postsync_stall <= _T_506 | _T_507; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin x_d_valid <= 1'h0; end else begin x_d_valid <= io_dec_i0_decode_d; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin flush_final_r <= 1'h0; end else begin flush_final_r <= io_exu_flush_final; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin illegal_lockout <= 1'h0; end else begin @@ -47918,7 +47953,7 @@ end // initial cam_raw_0_bits_tag <= 3'h0; end else if (cam_wen[0]) begin cam_raw_0_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; - end else if (_T_106) begin + end else if (_T_107) begin cam_raw_0_bits_tag <= 3'h0; end end @@ -47936,7 +47971,7 @@ end // initial cam_raw_1_bits_tag <= 3'h0; end else if (cam_wen[1]) begin cam_raw_1_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; - end else if (_T_132) begin + end else if (_T_133) begin cam_raw_1_bits_tag <= 3'h0; end end @@ -47954,7 +47989,7 @@ end // initial cam_raw_2_bits_tag <= 3'h0; end else if (cam_wen[2]) begin cam_raw_2_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; - end else if (_T_158) begin + end else if (_T_159) begin cam_raw_2_bits_tag <= 3'h0; end end @@ -47972,7 +48007,7 @@ end // initial cam_raw_3_bits_tag <= 3'h0; end else if (cam_wen[3]) begin cam_raw_3_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; - end else if (_T_184) begin + end else if (_T_185) begin cam_raw_3_bits_tag <= 3'h0; end end @@ -47985,14 +48020,14 @@ end // initial cam_raw_3_valid <= _GEN_89; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin x_d_bits_i0load <= 1'h0; end else begin x_d_bits_i0load <= i0_dp_load & i0_legal_decode_d; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin x_d_bits_i0rd <= 5'h0; end else begin @@ -48013,21 +48048,21 @@ end // initial nonblock_load_valid_m_delay <= io_lsu_nonblock_load_valid_m; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin r_d_bits_i0load <= 1'h0; end else begin r_d_bits_i0load <= x_d_bits_i0load; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin r_d_bits_i0v <= 1'h0; end else begin - r_d_bits_i0v <= _T_733 & _T_279; + r_d_bits_i0v <= _T_733 & _T_280; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin r_d_bits_i0rd <= 5'h0; end else begin @@ -48043,7 +48078,7 @@ end // initial end else begin cam_raw_0_bits_rd <= 5'h0; end - end else if (_T_106) begin + end else if (_T_107) begin cam_raw_0_bits_rd <= 5'h0; end end @@ -48051,7 +48086,7 @@ end // initial if (reset) begin cam_raw_0_bits_wb <= 1'h0; end else begin - cam_raw_0_bits_wb <= _T_111 | _GEN_57; + cam_raw_0_bits_wb <= _T_112 | _GEN_57; end end always @(posedge io_free_clk or posedge reset) begin @@ -48063,7 +48098,7 @@ end // initial end else begin cam_raw_1_bits_rd <= 5'h0; end - end else if (_T_132) begin + end else if (_T_133) begin cam_raw_1_bits_rd <= 5'h0; end end @@ -48071,7 +48106,7 @@ end // initial if (reset) begin cam_raw_1_bits_wb <= 1'h0; end else begin - cam_raw_1_bits_wb <= _T_137 | _GEN_68; + cam_raw_1_bits_wb <= _T_138 | _GEN_68; end end always @(posedge io_free_clk or posedge reset) begin @@ -48083,7 +48118,7 @@ end // initial end else begin cam_raw_2_bits_rd <= 5'h0; end - end else if (_T_158) begin + end else if (_T_159) begin cam_raw_2_bits_rd <= 5'h0; end end @@ -48091,7 +48126,7 @@ end // initial if (reset) begin cam_raw_2_bits_wb <= 1'h0; end else begin - cam_raw_2_bits_wb <= _T_163 | _GEN_79; + cam_raw_2_bits_wb <= _T_164 | _GEN_79; end end always @(posedge io_free_clk or posedge reset) begin @@ -48103,7 +48138,7 @@ end // initial end else begin cam_raw_3_bits_rd <= 5'h0; end - end else if (_T_184) begin + end else if (_T_185) begin cam_raw_3_bits_rd <= 5'h0; end end @@ -48111,7 +48146,7 @@ end // initial if (reset) begin cam_raw_3_bits_wb <= 1'h0; end else begin - cam_raw_3_bits_wb <= _T_189 | _GEN_90; + cam_raw_3_bits_wb <= _T_190 | _GEN_90; end end always @(posedge io_active_clk or posedge reset) begin @@ -48121,35 +48156,35 @@ end // initial lsu_idle <= io_lsu_idle_any; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin _T_339 <= 1'h0; end else begin _T_339 <= io_dec_tlu_flush_extint; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin x_d_bits_i0v <= 1'h0; end else begin x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin r_d_bits_csrwen <= 1'h0; end else begin r_d_bits_csrwen <= x_d_bits_csrwen; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin r_d_valid <= 1'h0; end else begin - r_d_valid <= _T_737 & _T_279; + r_d_valid <= _T_737 & _T_280; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin r_d_bits_csrwaddr <= 12'h0; end else begin @@ -48187,34 +48222,34 @@ end // initial always @(posedge io_active_clk or posedge reset) begin if (reset) begin csr_imm_x <= 1'h0; - end else if (_T_40) begin + end else if (_T_41) begin csr_imm_x <= 1'h0; end else begin csr_imm_x <= i0_dp_raw_csr_imm; end end - always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin if (reset) begin csrimm_x <= 5'h0; end else begin csrimm_x <= io_dec_i0_instr_d[19:15]; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin csr_rddata_x <= 32'h0; end else begin csr_rddata_x <= io_dec_csr_rddata_d; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin r_d_bits_csrwonly <= 1'h0; end else begin r_d_bits_csrwonly <= x_d_bits_csrwonly; end end - always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin i0_result_r_raw <= 32'h0; end else if (_T_761) begin @@ -48223,21 +48258,21 @@ end // initial i0_result_r_raw <= io_exu_i0_result_x; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin x_d_bits_csrwonly <= 1'h0; end else begin x_d_bits_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; end end - always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin wbd_bits_csrwonly <= 1'h0; end else begin wbd_bits_csrwonly <= r_d_bits_csrwonly; end end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin if (reset) begin _T_465 <= 32'h0; end else if (io_dec_i0_pc4_d) begin @@ -48246,112 +48281,112 @@ end // initial _T_465 <= _T_462; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_legal <= 1'h0; end else begin x_t_legal <= io_dec_i0_decode_d & i0_legal; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_icaf <= 1'h0; end else begin x_t_icaf <= i0_icaf_d & i0_legal_decode_d; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_icaf_f1 <= 1'h0; end else begin x_t_icaf_f1 <= io_dec_i0_icaf_f1_d & i0_legal_decode_d; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_icaf_type <= 2'h0; end else begin x_t_icaf_type <= io_dec_i0_icaf_type_d; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_fence_i <= 1'h0; end else begin x_t_fence_i <= _T_517 & i0_legal_decode_d; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_i0trigger <= 4'h0; end else begin x_t_i0trigger <= io_dec_i0_trigger_match_d & _T_522; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_pmu_i0_itype <= 4'h0; end else begin - x_t_pmu_i0_itype <= _T_254 & _T_276; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - x_t_pmu_i0_br_unpred <= 1'h0; - end else begin - x_t_pmu_i0_br_unpred <= i0_dp_jal & _T_252; + x_t_pmu_i0_itype <= _T_255 & _T_277; end end always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + x_t_pmu_i0_br_unpred <= 1'h0; + end else begin + x_t_pmu_i0_br_unpred <= i0_dp_jal & _T_253; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_legal <= 1'h0; end else begin r_t_legal <= x_t_legal; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_icaf <= 1'h0; end else begin r_t_icaf <= x_t_icaf; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_icaf_f1 <= 1'h0; end else begin r_t_icaf_f1 <= x_t_icaf_f1; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_icaf_type <= 2'h0; end else begin r_t_icaf_type <= x_t_icaf_type; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_fence_i <= 1'h0; end else begin r_t_fence_i <= x_t_fence_i; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_i0trigger <= 4'h0; end else begin r_t_i0trigger <= x_t_i0trigger & _T_531; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_pmu_i0_itype <= 4'h0; end else begin r_t_pmu_i0_itype <= x_t_pmu_i0_itype; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_pmu_i0_br_unpred <= 1'h0; end else begin @@ -48372,55 +48407,55 @@ end // initial lsu_pmu_misaligned_r <= io_lsu_pmu_misaligned_m; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin r_d_bits_i0store <= 1'h0; end else begin r_d_bits_i0store <= x_d_bits_i0store; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin r_d_bits_i0div <= 1'h0; end else begin r_d_bits_i0div <= x_d_bits_i0div; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin x_d_bits_i0store <= 1'h0; end else begin x_d_bits_i0store <= i0_dp_store & i0_legal_decode_d; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin x_d_bits_i0div <= 1'h0; end else begin x_d_bits_i0div <= i0_dp_div & i0_legal_decode_d; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin x_d_bits_csrwen <= 1'h0; end else begin x_d_bits_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin x_d_bits_csrwaddr <= 12'h0; end else begin x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20]; end end - always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin if (reset) begin last_br_immed_x <= 12'h0; end else if (io_i0_ap_predict_nt) begin last_br_immed_x <= _T_781; end else if (_T_314) begin - last_br_immed_x <= i0_pcall_imm[12:1]; + last_br_immed_x <= i0_pcall_imm[11:0]; end else begin last_br_immed_x <= _T_323; end @@ -48439,7 +48474,7 @@ end // initial _T_830 <= i0r_rd; end end - always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin i0_inst_x <= 32'h0; end else if (io_dec_i0_pc4_d) begin @@ -48448,41 +48483,48 @@ end // initial i0_inst_x <= _T_462; end end - always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin if (reset) begin i0_inst_r <= 32'h0; end else begin i0_inst_r <= i0_inst_x; end end - always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin if (reset) begin i0_inst_wb <= 32'h0; end else begin i0_inst_wb <= i0_inst_r; end end - always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin if (reset) begin _T_837 <= 32'h0; end else begin _T_837 <= i0_inst_wb; end end - always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin i0_pc_wb <= 31'h0; end else begin i0_pc_wb <= io_dec_tlu_i0_pc_r; end end - always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin _T_840 <= 31'h0; end else begin _T_840 <= i0_pc_wb; end end + always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin + if (reset) begin + dec_i0_pc_r <= 31'h0; + end else begin + dec_i0_pc_r <= io_exu_i0_pc_x; + end + end endmodule module el2_dec_gpr_ctl( input clock, @@ -50364,6 +50406,7 @@ module csr_tlu( input io_dma_pmu_any_write, input io_dma_pmu_any_read, input io_lsu_pmu_bus_busy, + input [30:0] io_dec_tlu_i0_pc_r, input io_dec_tlu_i0_valid_r, input io_dec_csr_any_unq_d, output io_dec_tlu_misc_clk_override, @@ -50594,8 +50637,8 @@ module csr_tlu( reg [31:0] _RAND_35; reg [31:0] _RAND_36; reg [31:0] _RAND_37; - reg [95:0] _RAND_38; - reg [31:0] _RAND_39; + reg [31:0] _RAND_38; + reg [95:0] _RAND_39; reg [31:0] _RAND_40; reg [31:0] _RAND_41; reg [31:0] _RAND_42; @@ -50629,6 +50672,7 @@ module csr_tlu( reg [31:0] _RAND_70; reg [31:0] _RAND_71; reg [31:0] _RAND_72; + reg [31:0] _RAND_73; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] @@ -50910,15 +50954,25 @@ module csr_tlu( wire [30:0] _T_159 = _T_158 | _T_156; // @[Mux.scala 27:72] wire _T_162 = sel_exu_npc_r | sel_flush_npc_r; // @[el2_dec_tlu_ctl.scala 1687:49] reg [30:0] _T_165; // @[el2_lib.scala 514:16] + wire pc0_valid_r = _T_140 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 1690:45] + wire _T_168 = ~pc0_valid_r; // @[el2_dec_tlu_ctl.scala 1694:5] + wire [30:0] _T_169 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + reg [30:0] pc_r_d1; // @[el2_lib.scala 514:16] + wire [30:0] _T_170 = _T_168 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] pc_r = _T_169 | _T_170; // @[Mux.scala 27:72] wire _T_174 = io_dec_csr_wraddr_r == 12'h341; // @[el2_dec_tlu_ctl.scala 1698:69] wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_174; // @[el2_dec_tlu_ctl.scala 1698:40] + wire _T_175 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 1701:30] + wire _T_176 = _T_175 | io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1701:51] wire _T_180 = wr_mepc_r & _T_15; // @[el2_dec_tlu_ctl.scala 1703:16] wire _T_183 = ~wr_mepc_r; // @[el2_dec_tlu_ctl.scala 1704:6] wire _T_185 = _T_183 & _T_15; // @[el2_dec_tlu_ctl.scala 1704:17] + wire [30:0] _T_187 = _T_176 ? pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_188 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_189 = _T_180 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_190 = _T_185 ? io_mepc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_192 = _T_188 | _T_189; // @[Mux.scala 27:72] + wire [30:0] _T_191 = _T_187 | _T_188; // @[Mux.scala 27:72] + wire [30:0] _T_192 = _T_191 | _T_189; // @[Mux.scala 27:72] reg [30:0] _T_194; // @[el2_dec_tlu_ctl.scala 1706:48] wire _T_196 = io_dec_csr_wraddr_r == 12'h342; // @[el2_dec_tlu_ctl.scala 1713:71] wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_196; // @[el2_dec_tlu_ctl.scala 1713:42] @@ -50992,6 +51046,9 @@ module csr_tlu( wire _T_285 = _T_283 & _T_284; // @[el2_dec_tlu_ctl.scala 1767:91] wire _T_286 = ~io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1767:116] wire mtval_clear_r = _T_285 & _T_286; // @[el2_dec_tlu_ctl.scala 1767:114] + wire [31:0] _T_288 = {pc_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_291 = pc_r + 31'h1; // @[el2_dec_tlu_ctl.scala 1772:84] + wire [31:0] _T_292 = {_T_291,1'h0}; // @[Cat.scala 29:58] wire _T_295 = ~io_interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 1775:19] wire _T_296 = wr_mtval_r & _T_295; // @[el2_dec_tlu_ctl.scala 1775:17] wire _T_299 = ~wr_mtval_r; // @[el2_dec_tlu_ctl.scala 1776:21] @@ -51001,13 +51058,15 @@ module csr_tlu( wire _T_305 = ~mtval_clear_r; // @[el2_dec_tlu_ctl.scala 1776:81] wire _T_306 = _T_304 & _T_305; // @[el2_dec_tlu_ctl.scala 1776:79] wire _T_308 = _T_306 & _T_284; // @[el2_dec_tlu_ctl.scala 1776:96] - wire [31:0] _T_311 = mtval_capture_pc_plus2_r ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_310 = mtval_capture_pc_r ? _T_288 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_311 = mtval_capture_pc_plus2_r ? _T_292 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_312 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_313 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_314 = _T_296 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] reg [31:0] mtval; // @[el2_dec_tlu_ctl.scala 1778:47] wire [31:0] _T_315 = _T_308 ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_317 = _T_311 | _T_312; // @[Mux.scala 27:72] + wire [31:0] _T_316 = _T_310 | _T_311; // @[Mux.scala 27:72] + wire [31:0] _T_317 = _T_316 | _T_312; // @[Mux.scala 27:72] wire [31:0] _T_318 = _T_317 | _T_313; // @[Mux.scala 27:72] wire [31:0] _T_319 = _T_318 | _T_314; // @[Mux.scala 27:72] wire _T_323 = io_dec_csr_wraddr_r == 12'h7f8; // @[el2_dec_tlu_ctl.scala 1793:69] @@ -51177,7 +51236,9 @@ module csr_tlu( wire _T_710 = _T_709 & wr_dpc_r; // @[el2_dec_tlu_ctl.scala 2143:41] wire _T_715 = _T_707 & dpc_capture_npc; // @[el2_dec_tlu_ctl.scala 2145:22] wire [30:0] _T_717 = _T_710 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_718 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_719 = _T_715 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_720 = _T_717 | _T_718; // @[Mux.scala 27:72] wire _T_722 = wr_dpc_r | io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 2147:37] reg [30:0] _T_725; // @[el2_lib.scala 514:16] wire [2:0] _T_729 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] @@ -52741,113 +52802,115 @@ initial begin _RAND_18 = {1{`RANDOM}}; _T_165 = _RAND_18[30:0]; _RAND_19 = {1{`RANDOM}}; - _T_194 = _RAND_19[30:0]; + pc_r_d1 = _RAND_19[30:0]; _RAND_20 = {1{`RANDOM}}; - mcause = _RAND_20[31:0]; + _T_194 = _RAND_20[30:0]; _RAND_21 = {1{`RANDOM}}; - mscause = _RAND_21[3:0]; + mcause = _RAND_21[31:0]; _RAND_22 = {1{`RANDOM}}; - mtval = _RAND_22[31:0]; + mscause = _RAND_22[3:0]; _RAND_23 = {1{`RANDOM}}; - mcgc = _RAND_23[8:0]; + mtval = _RAND_23[31:0]; _RAND_24 = {1{`RANDOM}}; - mfdc_int = _RAND_24[14:0]; + mcgc = _RAND_24[8:0]; _RAND_25 = {1{`RANDOM}}; - mrac = _RAND_25[31:0]; + mfdc_int = _RAND_25[14:0]; _RAND_26 = {1{`RANDOM}}; - mdseac = _RAND_26[31:0]; + mrac = _RAND_26[31:0]; _RAND_27 = {1{`RANDOM}}; - mfdht = _RAND_27[5:0]; + mdseac = _RAND_27[31:0]; _RAND_28 = {1{`RANDOM}}; - mfdhs = _RAND_28[1:0]; + mfdht = _RAND_28[5:0]; _RAND_29 = {1{`RANDOM}}; - force_halt_ctr_f = _RAND_29[31:0]; + mfdhs = _RAND_29[1:0]; _RAND_30 = {1{`RANDOM}}; - meivt = _RAND_30[21:0]; + force_halt_ctr_f = _RAND_30[31:0]; _RAND_31 = {1{`RANDOM}}; - meihap = _RAND_31[7:0]; + meivt = _RAND_31[21:0]; _RAND_32 = {1{`RANDOM}}; - meicurpl = _RAND_32[3:0]; + meihap = _RAND_32[7:0]; _RAND_33 = {1{`RANDOM}}; - meicidpl = _RAND_33[3:0]; + meicurpl = _RAND_33[3:0]; _RAND_34 = {1{`RANDOM}}; - meipt = _RAND_34[3:0]; + meicidpl = _RAND_34[3:0]; _RAND_35 = {1{`RANDOM}}; - _T_700 = _RAND_35[15:0]; + meipt = _RAND_35[3:0]; _RAND_36 = {1{`RANDOM}}; - _T_725 = _RAND_36[30:0]; + _T_700 = _RAND_36[15:0]; _RAND_37 = {1{`RANDOM}}; - dicawics = _RAND_37[16:0]; - _RAND_38 = {3{`RANDOM}}; - dicad0 = _RAND_38[70:0]; - _RAND_39 = {1{`RANDOM}}; - dicad0h = _RAND_39[31:0]; + _T_725 = _RAND_37[30:0]; + _RAND_38 = {1{`RANDOM}}; + dicawics = _RAND_38[16:0]; + _RAND_39 = {3{`RANDOM}}; + dicad0 = _RAND_39[70:0]; _RAND_40 = {1{`RANDOM}}; - _T_757 = _RAND_40[31:0]; + dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - icache_rd_valid_f = _RAND_41[0:0]; + _T_757 = _RAND_41[31:0]; _RAND_42 = {1{`RANDOM}}; - icache_wr_valid_f = _RAND_42[0:0]; + icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - mtsel = _RAND_43[1:0]; + icache_wr_valid_f = _RAND_43[0:0]; _RAND_44 = {1{`RANDOM}}; - _T_871 = _RAND_44[9:0]; + mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_872 = _RAND_45[9:0]; + _T_871 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_873 = _RAND_46[9:0]; + _T_872 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_874 = _RAND_47[9:0]; + _T_873 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - mtdata2_t_0 = _RAND_48[31:0]; + _T_874 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; - mtdata2_t_1 = _RAND_49[31:0]; + mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; - mtdata2_t_2 = _RAND_50[31:0]; + mtdata2_t_1 = _RAND_50[31:0]; _RAND_51 = {1{`RANDOM}}; - mtdata2_t_3 = _RAND_51[31:0]; + mtdata2_t_2 = _RAND_51[31:0]; _RAND_52 = {1{`RANDOM}}; - mhpme3 = _RAND_52[9:0]; + mtdata2_t_3 = _RAND_52[31:0]; _RAND_53 = {1{`RANDOM}}; - mhpme4 = _RAND_53[9:0]; + mhpme3 = _RAND_53[9:0]; _RAND_54 = {1{`RANDOM}}; - mhpme5 = _RAND_54[9:0]; + mhpme4 = _RAND_54[9:0]; _RAND_55 = {1{`RANDOM}}; - mhpme6 = _RAND_55[9:0]; + mhpme5 = _RAND_55[9:0]; _RAND_56 = {1{`RANDOM}}; - mhpmc_inc_r_d1_0 = _RAND_56[0:0]; + mhpme6 = _RAND_56[9:0]; _RAND_57 = {1{`RANDOM}}; - mhpmc_inc_r_d1_1 = _RAND_57[0:0]; + mhpmc_inc_r_d1_0 = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - mhpmc_inc_r_d1_2 = _RAND_58[0:0]; + mhpmc_inc_r_d1_1 = _RAND_58[0:0]; _RAND_59 = {1{`RANDOM}}; - mhpmc_inc_r_d1_3 = _RAND_59[0:0]; + mhpmc_inc_r_d1_2 = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; - perfcnt_halted_d1 = _RAND_60[0:0]; + mhpmc_inc_r_d1_3 = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - mhpmc3h = _RAND_61[31:0]; + perfcnt_halted_d1 = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - mhpmc3 = _RAND_62[31:0]; + mhpmc3h = _RAND_62[31:0]; _RAND_63 = {1{`RANDOM}}; - mhpmc4h = _RAND_63[31:0]; + mhpmc3 = _RAND_63[31:0]; _RAND_64 = {1{`RANDOM}}; - mhpmc4 = _RAND_64[31:0]; + mhpmc4h = _RAND_64[31:0]; _RAND_65 = {1{`RANDOM}}; - mhpmc5h = _RAND_65[31:0]; + mhpmc4 = _RAND_65[31:0]; _RAND_66 = {1{`RANDOM}}; - mhpmc5 = _RAND_66[31:0]; + mhpmc5h = _RAND_66[31:0]; _RAND_67 = {1{`RANDOM}}; - mhpmc6h = _RAND_67[31:0]; + mhpmc5 = _RAND_67[31:0]; _RAND_68 = {1{`RANDOM}}; - mhpmc6 = _RAND_68[31:0]; + mhpmc6h = _RAND_68[31:0]; _RAND_69 = {1{`RANDOM}}; - _T_2325 = _RAND_69[0:0]; + mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2330 = _RAND_70[0:0]; + _T_2325 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2331 = _RAND_71[4:0]; + _T_2330 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2332 = _RAND_72[0:0]; + _T_2331 = _RAND_72[4:0]; + _RAND_73 = {1{`RANDOM}}; + _T_2332 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -52906,6 +52969,9 @@ initial begin if (reset) begin _T_165 = 31'h0; end + if (reset) begin + pc_r_d1 = 31'h0; + end if (reset) begin _T_194 = 31'h0; end @@ -53223,6 +53289,13 @@ end // initial _T_165 <= io_npc_r; end end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + pc_r_d1 <= 31'h0; + end else begin + pc_r_d1 <= _T_169 | _T_170; + end + end always @(posedge io_e4e5_int_clk or posedge reset) begin if (reset) begin _T_194 <= 31'h0; @@ -53360,7 +53433,7 @@ end // initial if (reset) begin _T_725 <= 31'h0; end else begin - _T_725 <= _T_717 | _T_719; + _T_725 <= _T_720 | _T_719; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin @@ -54162,6 +54235,7 @@ module el2_dec_tlu_ctl( input io_dec_csr_stall_int_ff, input io_dec_tlu_i0_valid_r, input [30:0] io_exu_npc_r, + input [30:0] io_dec_tlu_i0_pc_r, input io_dec_tlu_packet_r_legal, input io_dec_tlu_packet_r_icaf, input io_dec_tlu_packet_r_icaf_f1, @@ -54489,6 +54563,7 @@ module el2_dec_tlu_ctl( wire csr_io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_dec_tlu_misc_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] @@ -55371,6 +55446,10 @@ module el2_dec_tlu_ctl( wire _T_800 = _T_799 | take_halt; // @[el2_dec_tlu_ctl.scala 866:73] wire _T_801 = _T_800 | take_reset; // @[el2_dec_tlu_ctl.scala 866:85] wire _T_807 = _T_529 & sel_npc_r; // @[el2_dec_tlu_ctl.scala 870:21] + wire _T_810 = _T_529 & rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 871:21] + wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 871:39] + wire _T_813 = ~sel_npc_r; // @[el2_dec_tlu_ctl.scala 871:80] + wire _T_814 = _T_812 & _T_813; // @[el2_dec_tlu_ctl.scala 871:69] wire _T_816 = ~take_ext_int; // @[el2_dec_tlu_ctl.scala 872:44] wire _T_817 = interrupt_valid_r & _T_816; // @[el2_dec_tlu_ctl.scala 872:30] wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 873:28] @@ -55383,6 +55462,7 @@ module el2_dec_tlu_ctl( wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 337:41 el2_dec_tlu_ctl.scala 1075:31] wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 340:41 el2_dec_tlu_ctl.scala 1078:31] @@ -55392,7 +55472,8 @@ module el2_dec_tlu_ctl( wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 338:41 el2_dec_tlu_ctl.scala 1076:31] wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] - wire [30:0] _T_848 = _T_846 | _T_841; // @[Mux.scala 27:72] + wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] + wire [30:0] _T_848 = _T_847 | _T_841; // @[Mux.scala 27:72] wire [30:0] _T_849 = _T_848 | _T_842; // @[Mux.scala 27:72] wire [30:0] _T_850 = _T_849 | _T_843; // @[Mux.scala 27:72] wire [30:0] _T_851 = _T_850 | _T_844; // @[Mux.scala 27:72] @@ -55570,6 +55651,7 @@ module el2_dec_tlu_ctl( .io_dma_pmu_any_write(csr_io_dma_pmu_any_write), .io_dma_pmu_any_read(csr_io_dma_pmu_any_read), .io_lsu_pmu_bus_busy(csr_io_lsu_pmu_bus_busy), + .io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r), .io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r), .io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d), .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), @@ -55993,6 +56075,7 @@ module el2_dec_tlu_ctl( assign csr_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 927:44] assign csr_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 928:44] assign csr_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 929:44] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 930:44] assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 931:44] assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 933:44] assign csr_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 934:44] @@ -57704,16 +57787,16 @@ module el2_dec( output io_dec_extint_stall, output io_dec_i0_decode_d, output io_dec_pause_state_cg, - input [31:0] io_rst_vec, + input [30:0] io_rst_vec, input io_nmi_int, - input [31:0] io_nmi_vec, + input [30:0] io_nmi_vec, input io_i_cpu_halt_req, input io_i_cpu_run_req, output io_o_cpu_halt_status, output io_o_cpu_halt_ack, output io_o_cpu_run_ack, output io_o_debug_mode_status, - input [31:0] io_core_id, + input [27:0] io_core_id, input io_mpc_debug_halt_req, input io_mpc_debug_run_req, input io_mpc_reset_run_req, @@ -57741,7 +57824,7 @@ module el2_dec( input io_dma_pmu_dccm_write, input io_dma_pmu_any_read, input io_dma_pmu_any_write, - input [31:0] io_lsu_fir_addr, + input [30:0] io_lsu_fir_addr, input [1:0] io_lsu_fir_error, input io_ifu_pmu_instr_aligned, input io_ifu_pmu_fetch_stall, @@ -57771,7 +57854,7 @@ module el2_dec( input [30:0] io_i0_brp_bits_prett, input io_i0_brp_bits_way, input io_i0_brp_bits_ret, - input [8:0] io_ifu_i0_bp_index, + input [7:0] io_ifu_i0_bp_index, input [7:0] io_ifu_i0_bp_fghr, input [4:0] io_ifu_i0_bp_btag, input io_lsu_error_pkt_r_valid, @@ -57795,11 +57878,13 @@ module el2_dec( input io_dma_iccm_stall_any, input io_iccm_dma_sb_error, input io_exu_flush_final, - input [31:0] io_exu_npc_r, + input [30:0] io_exu_npc_r, input [31:0] io_exu_i0_result_x, input io_ifu_i0_valid, input [31:0] io_ifu_i0_instr, - input [31:0] io_ifu_i0_pc, + input [30:0] io_ifu_i0_pc, + input io_ifu_i0_pc4, + input [30:0] io_exu_i0_pc_x, input io_mexintpend, input io_timer_int, input io_soft_int, @@ -57808,7 +57893,7 @@ module el2_dec( input io_mhwakeup, output [3:0] io_dec_tlu_meicurpl, output [3:0] io_dec_tlu_meipt, - input [69:0] io_ifu_ic_debug_rd_data, + input [70:0] io_ifu_ic_debug_rd_data, input io_ifu_ic_debug_rd_data_valid, output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, @@ -57824,7 +57909,7 @@ module el2_dec( output io_dec_tlu_mpc_halted_only, output io_dec_tlu_flush_leak_one_r, output io_dec_tlu_flush_err_r, - output [31:0] io_dec_tlu_meihap, + output [29:0] io_dec_tlu_meihap, output io_dec_debug_wdata_rs1_d, output [31:0] io_dec_dbg_rddata, output io_dec_dbg_cmd_done, @@ -57862,7 +57947,7 @@ module el2_dec( output [31:0] io_gpr_i0_rs1_d, output [31:0] io_gpr_i0_rs2_d, output [31:0] io_dec_i0_immed_d, - output [12:0] io_dec_i0_br_immed_d, + output [11:0] io_dec_i0_br_immed_d, output io_i0_ap_land, output io_i0_ap_lor, output io_i0_ap_lxor, @@ -57883,6 +57968,8 @@ module el2_dec( output io_i0_ap_csr_write, output io_i0_ap_csr_imm, output io_dec_i0_alu_decode_d, + output io_dec_i0_select_pc_d, + output [30:0] io_dec_i0_pc_d, output [1:0] io_dec_i0_rs1_bypass_en_d, output [1:0] io_dec_i0_rs2_bypass_en_d, output [31:0] io_dec_i0_rs1_bypass_data_d, @@ -57908,10 +57995,10 @@ module el2_dec( output [11:0] io_dec_lsu_offset_d, output io_dec_csr_ren_d, output io_dec_tlu_flush_lower_r, - output [31:0] io_dec_tlu_flush_path_r, + output [30:0] io_dec_tlu_flush_path_r, output io_dec_tlu_i0_kill_writeb_r, output io_dec_tlu_fence_i_r, - output [31:0] io_pred_correct_npc_x, + output [30:0] io_pred_correct_npc_x, output io_dec_tlu_br0_r_pkt_valid, output [1:0] io_dec_tlu_br0_r_pkt_bits_hist, output io_dec_tlu_br0_r_pkt_bits_br_error, @@ -57934,7 +58021,7 @@ module el2_dec( output io_dec_i0_predict_p_d_bits_pja, output io_dec_i0_predict_p_d_bits_way, output [7:0] io_i0_predict_fghr_d, - output [8:0] io_i0_predict_index_d, + output [7:0] io_i0_predict_index_d, output [4:0] io_i0_predict_btag_d, output io_dec_lsu_valid_raw_d, output [31:0] io_dec_tlu_mrac_ff, @@ -57962,451 +58049,456 @@ module el2_dec( output io_dec_tlu_i0_commit_cmt, input io_scan_mode ); - wire instbuff_io_dbg_cmd_valid; // @[el2_dec.scala 353:24] - wire instbuff_io_dbg_cmd_write; // @[el2_dec.scala 353:24] - wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 353:24] - wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 353:24] - wire instbuff_io_i0_brp_valid; // @[el2_dec.scala 353:24] - wire [11:0] instbuff_io_i0_brp_bits_toffset; // @[el2_dec.scala 353:24] - wire [1:0] instbuff_io_i0_brp_bits_hist; // @[el2_dec.scala 353:24] - wire instbuff_io_i0_brp_bits_br_error; // @[el2_dec.scala 353:24] - wire instbuff_io_i0_brp_bits_br_start_error; // @[el2_dec.scala 353:24] - wire [30:0] instbuff_io_i0_brp_bits_prett; // @[el2_dec.scala 353:24] - wire instbuff_io_i0_brp_bits_way; // @[el2_dec.scala 353:24] - wire instbuff_io_i0_brp_bits_ret; // @[el2_dec.scala 353:24] - wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 353:24] - wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 353:24] - wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 353:24] - wire instbuff_io_ifu_i0_valid; // @[el2_dec.scala 353:24] - wire instbuff_io_ifu_i0_icaf; // @[el2_dec.scala 353:24] - wire [1:0] instbuff_io_ifu_i0_icaf_type; // @[el2_dec.scala 353:24] - wire instbuff_io_ifu_i0_icaf_f1; // @[el2_dec.scala 353:24] - wire instbuff_io_ifu_i0_dbecc; // @[el2_dec.scala 353:24] - wire [31:0] instbuff_io_ifu_i0_instr; // @[el2_dec.scala 353:24] - wire [30:0] instbuff_io_ifu_i0_pc; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 353:24] - wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 353:24] - wire [31:0] instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 353:24] - wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 353:24] - wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 353:24] - wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 353:24] - wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 353:24] - wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 353:24] - wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 353:24] - wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 353:24] - wire decode_clock; // @[el2_dec.scala 354:22] - wire decode_reset; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_flush_extint; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_force_halt; // @[el2_dec.scala 354:22] - wire decode_io_dec_extint_stall; // @[el2_dec.scala 354:22] - wire [15:0] decode_io_ifu_i0_cinst; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_inst_wb1; // @[el2_dec.scala 354:22] - wire [30:0] decode_io_dec_i0_pc_wb1; // @[el2_dec.scala 354:22] - wire decode_io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 354:22] - wire decode_io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 354:22] - wire decode_io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 354:22] - wire decode_io_lsu_nonblock_load_data_error; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_lsu_nonblock_load_data; // @[el2_dec.scala 354:22] - wire [3:0] decode_io_dec_i0_trigger_match_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 354:22] - wire [3:0] decode_io_lsu_trigger_match_m; // @[el2_dec.scala 354:22] - wire decode_io_lsu_pmu_misaligned_m; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_debug_stall; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_debug_fence_d; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dbg_cmd_wrdata; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_icaf_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_brp_valid; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 354:22] - wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_brp_bits_way; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 354:22] - wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 354:22] - wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 354:22] - wire decode_io_lsu_idle_any; // @[el2_dec.scala 354:22] - wire decode_io_lsu_load_stall_any; // @[el2_dec.scala 354:22] - wire decode_io_lsu_store_stall_any; // @[el2_dec.scala 354:22] - wire decode_io_dma_dccm_stall_any; // @[el2_dec.scala 354:22] - wire decode_io_exu_div_wren; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_presync_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_postsync_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_pc4_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_csr_rddata_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_legal_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_exu_csr_rs1_x; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_lsu_result_m; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_lsu_result_corr_r; // @[el2_dec.scala 354:22] - wire decode_io_exu_flush_final; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_instr_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_ib0_valid_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_exu_i0_result_x; // @[el2_dec.scala 354:22] - wire decode_io_free_clk; // @[el2_dec.scala 354:22] - wire decode_io_active_clk; // @[el2_dec.scala 354:22] - wire decode_io_clk_override; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_dec_i0_rs1_d; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_dec_i0_rs2_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_immed_d; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_i0_br_immed_d; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_land; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_lor; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_lxor; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_sll; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_srl; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_sra; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_beq; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_bne; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_blt; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_bge; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_add; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_sub; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_slt; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_unsign; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_jal; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_predict_t; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_predict_nt; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_csr_write; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_csr_imm; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_decode_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_dec_i0_waddr_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_wen_r; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_wdata_r; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_valid; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_fast_int; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_by; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_half; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_word; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_load; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_store; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_unsign; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_store_data_bypass_d; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_dec.scala 354:22] - wire decode_io_mul_p_valid; // @[el2_dec.scala 354:22] - wire decode_io_mul_p_bits_rs1_sign; // @[el2_dec.scala 354:22] - wire decode_io_mul_p_bits_rs2_sign; // @[el2_dec.scala 354:22] - wire decode_io_mul_p_bits_low; // @[el2_dec.scala 354:22] - wire decode_io_div_p_valid; // @[el2_dec.scala 354:22] - wire decode_io_div_p_bits_unsign; // @[el2_dec.scala 354:22] - wire decode_io_div_p_bits_rem; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_div_waddr_wb; // @[el2_dec.scala 354:22] - wire decode_io_dec_div_cancel; // @[el2_dec.scala 354:22] - wire decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_lsu_offset_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_ren_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_wen_r; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 354:22] - wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 354:22] - wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 354:22] - wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_illegal_inst; // @[el2_dec.scala 354:22] - wire [30:0] decode_io_pred_correct_npc_x; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_pc4; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_i0_predict_p_d_bits_hist; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_i0_predict_p_d_bits_toffset; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_br_error; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_dec.scala 354:22] - wire [30:0] decode_io_dec_i0_predict_p_d_bits_prett; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_pcall; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_pret; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_pja; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_way; // @[el2_dec.scala 354:22] - wire [7:0] decode_io_i0_predict_fghr_d; // @[el2_dec.scala 354:22] - wire [7:0] decode_io_i0_predict_index_d; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_i0_predict_btag_d; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_data_en; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_ctl_en; // @[el2_dec.scala 354:22] - wire decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 354:22] - wire decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 354:22] - wire decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 354:22] - wire decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 354:22] - wire decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 354:22] - wire decode_io_dec_pause_state; // @[el2_dec.scala 354:22] - wire decode_io_dec_pause_state_cg; // @[el2_dec.scala 354:22] - wire decode_io_dec_div_active; // @[el2_dec.scala 354:22] - wire decode_io_scan_mode; // @[el2_dec.scala 354:22] - wire gpr_clock; // @[el2_dec.scala 355:19] - wire gpr_reset; // @[el2_dec.scala 355:19] - wire [4:0] gpr_io_raddr0; // @[el2_dec.scala 355:19] - wire [4:0] gpr_io_raddr1; // @[el2_dec.scala 355:19] - wire gpr_io_wen0; // @[el2_dec.scala 355:19] - wire [4:0] gpr_io_waddr0; // @[el2_dec.scala 355:19] - wire [31:0] gpr_io_wd0; // @[el2_dec.scala 355:19] - wire gpr_io_wen1; // @[el2_dec.scala 355:19] - wire [4:0] gpr_io_waddr1; // @[el2_dec.scala 355:19] - wire [31:0] gpr_io_wd1; // @[el2_dec.scala 355:19] - wire gpr_io_wen2; // @[el2_dec.scala 355:19] - wire [4:0] gpr_io_waddr2; // @[el2_dec.scala 355:19] - wire [31:0] gpr_io_wd2; // @[el2_dec.scala 355:19] - wire [31:0] gpr_io_rd0; // @[el2_dec.scala 355:19] - wire [31:0] gpr_io_rd1; // @[el2_dec.scala 355:19] - wire gpr_io_scan_mode; // @[el2_dec.scala 355:19] - wire tlu_clock; // @[el2_dec.scala 356:19] - wire tlu_reset; // @[el2_dec.scala 356:19] - wire tlu_io_active_clk; // @[el2_dec.scala 356:19] - wire tlu_io_free_clk; // @[el2_dec.scala 356:19] - wire tlu_io_scan_mode; // @[el2_dec.scala 356:19] - wire [30:0] tlu_io_rst_vec; // @[el2_dec.scala 356:19] - wire tlu_io_nmi_int; // @[el2_dec.scala 356:19] - wire [30:0] tlu_io_nmi_vec; // @[el2_dec.scala 356:19] - wire tlu_io_i_cpu_halt_req; // @[el2_dec.scala 356:19] - wire tlu_io_i_cpu_run_req; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_fastint_stall_any; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_instr_aligned; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_fetch_stall; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_ic_miss; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_ic_hit; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_bus_error; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_bus_busy; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_bus_trxn; // @[el2_dec.scala 356:19] - wire tlu_io_dec_pmu_instr_decoded; // @[el2_dec.scala 356:19] - wire tlu_io_dec_pmu_decode_stall; // @[el2_dec.scala 356:19] - wire tlu_io_dec_pmu_presync_stall; // @[el2_dec.scala 356:19] - wire tlu_io_dec_pmu_postsync_stall; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_store_stall_any; // @[el2_dec.scala 356:19] - wire tlu_io_dma_dccm_stall_any; // @[el2_dec.scala 356:19] - wire tlu_io_dma_iccm_stall_any; // @[el2_dec.scala 356:19] - wire tlu_io_exu_pmu_i0_br_misp; // @[el2_dec.scala 356:19] - wire tlu_io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 356:19] - wire tlu_io_exu_pmu_i0_pc4; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_bus_trxn; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_bus_error; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_bus_busy; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_load_external_m; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_store_external_m; // @[el2_dec.scala 356:19] - wire tlu_io_dma_pmu_dccm_read; // @[el2_dec.scala 356:19] - wire tlu_io_dma_pmu_dccm_write; // @[el2_dec.scala 356:19] - wire tlu_io_dma_pmu_any_read; // @[el2_dec.scala 356:19] - wire tlu_io_dma_pmu_any_write; // @[el2_dec.scala 356:19] - wire [30:0] tlu_io_lsu_fir_addr; // @[el2_dec.scala 356:19] - wire [1:0] tlu_io_lsu_fir_error; // @[el2_dec.scala 356:19] - wire tlu_io_iccm_dma_sb_error; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_valid; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_single_ecc_error_incr; // @[el2_dec.scala 356:19] - wire tlu_io_dec_pause_state; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_imprecise_error_store_any; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_imprecise_error_load_any; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 356:19] - wire tlu_io_dec_csr_wen_unq_d; // @[el2_dec.scala 356:19] - wire tlu_io_dec_csr_any_unq_d; // @[el2_dec.scala 356:19] - wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[el2_dec.scala 356:19] - wire tlu_io_dec_csr_wen_r; // @[el2_dec.scala 356:19] - wire [11:0] tlu_io_dec_csr_wraddr_r; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_dec_csr_wrdata_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_csr_stall_int_ff; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 356:19] - wire [30:0] tlu_io_exu_npc_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 356:19] - wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 356:19] - wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 356:19] - wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_dec_illegal_inst; // @[el2_dec.scala 356:19] - wire tlu_io_dec_i0_decode_d; // @[el2_dec.scala 356:19] - wire [1:0] tlu_io_exu_i0_br_hist_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_error_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_start_error_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_valid_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_mp_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_middle_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_way_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 356:19] - wire tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 356:19] - wire [29:0] tlu_io_dec_tlu_meihap; // @[el2_dec.scala 356:19] - wire tlu_io_dbg_halt_req; // @[el2_dec.scala 356:19] - wire tlu_io_dbg_resume_req; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_miss_state_idle; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_idle_any; // @[el2_dec.scala 356:19] - wire tlu_io_dec_div_active; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_ic_error_start; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 356:19] - wire [70:0] tlu_io_ifu_ic_debug_rd_data; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 356:19] - wire [70:0] tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 356:19] - wire [16:0] tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 356:19] - wire [7:0] tlu_io_pic_claimid; // @[el2_dec.scala 356:19] - wire [3:0] tlu_io_pic_pl; // @[el2_dec.scala 356:19] - wire tlu_io_mhwakeup; // @[el2_dec.scala 356:19] - wire tlu_io_mexintpend; // @[el2_dec.scala 356:19] - wire tlu_io_timer_int; // @[el2_dec.scala 356:19] - wire tlu_io_soft_int; // @[el2_dec.scala 356:19] - wire tlu_io_o_cpu_halt_status; // @[el2_dec.scala 356:19] - wire tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 356:19] - wire tlu_io_o_cpu_run_ack; // @[el2_dec.scala 356:19] - wire tlu_io_o_debug_mode_status; // @[el2_dec.scala 356:19] - wire [27:0] tlu_io_core_id; // @[el2_dec.scala 356:19] - wire tlu_io_mpc_debug_halt_req; // @[el2_dec.scala 356:19] - wire tlu_io_mpc_debug_run_req; // @[el2_dec.scala 356:19] - wire tlu_io_mpc_reset_run_req; // @[el2_dec.scala 356:19] - wire tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 356:19] - wire tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 356:19] - wire tlu_io_debug_brkpt_status; // @[el2_dec.scala 356:19] - wire [3:0] tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 356:19] - wire [3:0] tlu_io_dec_tlu_meipt; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 356:19] - wire tlu_io_dec_csr_legal_d; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 356:19] - wire [1:0] tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 356:19] - wire [30:0] tlu_io_dec_tlu_flush_path_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_valid_wb1; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_int_valid_wb1; // @[el2_dec.scala 356:19] - wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 356:19] - wire [2:0] tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 356:19] - wire dec_trigger_io_trigger_pkt_any_0_select; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_0_m; // @[el2_dec.scala 357:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_1_select; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_1_m; // @[el2_dec.scala 357:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_2_select; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_2_m; // @[el2_dec.scala 357:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_3_select; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_3_m; // @[el2_dec.scala 357:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 357:27] - wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[el2_dec.scala 357:27] - wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 357:27] - wire _T_1 = tlu_io_dec_tlu_i0_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec.scala 709:98] - el2_dec_ib_ctl instbuff ( // @[el2_dec.scala 353:24] + wire instbuff_io_dbg_cmd_valid; // @[el2_dec.scala 285:24] + wire instbuff_io_dbg_cmd_write; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 285:24] + wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_valid; // @[el2_dec.scala 285:24] + wire [11:0] instbuff_io_i0_brp_bits_toffset; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_i0_brp_bits_hist; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_bits_br_error; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_i0_brp_bits_prett; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_bits_way; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_bits_ret; // @[el2_dec.scala 285:24] + wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 285:24] + wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 285:24] + wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 285:24] + wire instbuff_io_ifu_i0_pc4; // @[el2_dec.scala 285:24] + wire instbuff_io_ifu_i0_valid; // @[el2_dec.scala 285:24] + wire instbuff_io_ifu_i0_icaf; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_ifu_i0_icaf_type; // @[el2_dec.scala 285:24] + wire instbuff_io_ifu_i0_icaf_f1; // @[el2_dec.scala 285:24] + wire instbuff_io_ifu_i0_dbecc; // @[el2_dec.scala 285:24] + wire [31:0] instbuff_io_ifu_i0_instr; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_ifu_i0_pc; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 285:24] + wire [31:0] instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 285:24] + wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 285:24] + wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 285:24] + wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 285:24] + wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 285:24] + wire decode_clock; // @[el2_dec.scala 286:22] + wire decode_reset; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_flush_extint; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_force_halt; // @[el2_dec.scala 286:22] + wire decode_io_dec_extint_stall; // @[el2_dec.scala 286:22] + wire [15:0] decode_io_ifu_i0_cinst; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_inst_wb1; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_dec_i0_pc_wb1; // @[el2_dec.scala 286:22] + wire decode_io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 286:22] + wire decode_io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 286:22] + wire decode_io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 286:22] + wire decode_io_lsu_nonblock_load_data_error; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_lsu_nonblock_load_data; // @[el2_dec.scala 286:22] + wire [3:0] decode_io_dec_i0_trigger_match_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 286:22] + wire [3:0] decode_io_lsu_trigger_match_m; // @[el2_dec.scala 286:22] + wire decode_io_lsu_pmu_misaligned_m; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_debug_stall; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_debug_fence_d; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dbg_cmd_wrdata; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_icaf_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_valid; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_bits_way; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 286:22] + wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 286:22] + wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 286:22] + wire decode_io_lsu_idle_any; // @[el2_dec.scala 286:22] + wire decode_io_lsu_load_stall_any; // @[el2_dec.scala 286:22] + wire decode_io_lsu_store_stall_any; // @[el2_dec.scala 286:22] + wire decode_io_dma_dccm_stall_any; // @[el2_dec.scala 286:22] + wire decode_io_exu_div_wren; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_presync_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_postsync_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_pc4_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_csr_rddata_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_legal_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_exu_csr_rs1_x; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_lsu_result_m; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_lsu_result_corr_r; // @[el2_dec.scala 286:22] + wire decode_io_exu_flush_final; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_exu_i0_pc_x; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_instr_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_ib0_valid_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_exu_i0_result_x; // @[el2_dec.scala 286:22] + wire decode_io_free_clk; // @[el2_dec.scala 286:22] + wire decode_io_active_clk; // @[el2_dec.scala 286:22] + wire decode_io_clk_override; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_dec_i0_rs1_d; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_dec_i0_rs2_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_immed_d; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_i0_br_immed_d; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_land; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_lor; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_lxor; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_sll; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_srl; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_sra; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_beq; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_bne; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_blt; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_bge; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_add; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_sub; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_slt; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_unsign; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_jal; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_predict_t; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_predict_nt; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_csr_write; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_csr_imm; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_decode_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_dec_i0_waddr_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_wen_r; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_wdata_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_select_pc_d; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_valid; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_fast_int; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_by; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_half; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_word; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_load; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_store; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_unsign; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_store_data_bypass_d; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_dec.scala 286:22] + wire decode_io_mul_p_valid; // @[el2_dec.scala 286:22] + wire decode_io_mul_p_bits_rs1_sign; // @[el2_dec.scala 286:22] + wire decode_io_mul_p_bits_rs2_sign; // @[el2_dec.scala 286:22] + wire decode_io_mul_p_bits_low; // @[el2_dec.scala 286:22] + wire decode_io_div_p_valid; // @[el2_dec.scala 286:22] + wire decode_io_div_p_bits_unsign; // @[el2_dec.scala 286:22] + wire decode_io_div_p_bits_rem; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_div_waddr_wb; // @[el2_dec.scala 286:22] + wire decode_io_dec_div_cancel; // @[el2_dec.scala 286:22] + wire decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_lsu_offset_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_ren_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_wen_r; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 286:22] + wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 286:22] + wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_illegal_inst; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_pred_correct_npc_x; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_pc4; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_predict_p_d_bits_hist; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_i0_predict_p_d_bits_toffset; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_br_error; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_dec_i0_predict_p_d_bits_prett; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_pcall; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_pret; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_pja; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_way; // @[el2_dec.scala 286:22] + wire [7:0] decode_io_i0_predict_fghr_d; // @[el2_dec.scala 286:22] + wire [7:0] decode_io_i0_predict_index_d; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_i0_predict_btag_d; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_data_en; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_ctl_en; // @[el2_dec.scala 286:22] + wire decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 286:22] + wire decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 286:22] + wire decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 286:22] + wire decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 286:22] + wire decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 286:22] + wire decode_io_dec_pause_state; // @[el2_dec.scala 286:22] + wire decode_io_dec_pause_state_cg; // @[el2_dec.scala 286:22] + wire decode_io_dec_div_active; // @[el2_dec.scala 286:22] + wire decode_io_scan_mode; // @[el2_dec.scala 286:22] + wire gpr_clock; // @[el2_dec.scala 287:19] + wire gpr_reset; // @[el2_dec.scala 287:19] + wire [4:0] gpr_io_raddr0; // @[el2_dec.scala 287:19] + wire [4:0] gpr_io_raddr1; // @[el2_dec.scala 287:19] + wire gpr_io_wen0; // @[el2_dec.scala 287:19] + wire [4:0] gpr_io_waddr0; // @[el2_dec.scala 287:19] + wire [31:0] gpr_io_wd0; // @[el2_dec.scala 287:19] + wire gpr_io_wen1; // @[el2_dec.scala 287:19] + wire [4:0] gpr_io_waddr1; // @[el2_dec.scala 287:19] + wire [31:0] gpr_io_wd1; // @[el2_dec.scala 287:19] + wire gpr_io_wen2; // @[el2_dec.scala 287:19] + wire [4:0] gpr_io_waddr2; // @[el2_dec.scala 287:19] + wire [31:0] gpr_io_wd2; // @[el2_dec.scala 287:19] + wire [31:0] gpr_io_rd0; // @[el2_dec.scala 287:19] + wire [31:0] gpr_io_rd1; // @[el2_dec.scala 287:19] + wire gpr_io_scan_mode; // @[el2_dec.scala 287:19] + wire tlu_clock; // @[el2_dec.scala 288:19] + wire tlu_reset; // @[el2_dec.scala 288:19] + wire tlu_io_active_clk; // @[el2_dec.scala 288:19] + wire tlu_io_free_clk; // @[el2_dec.scala 288:19] + wire tlu_io_scan_mode; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_rst_vec; // @[el2_dec.scala 288:19] + wire tlu_io_nmi_int; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_nmi_vec; // @[el2_dec.scala 288:19] + wire tlu_io_i_cpu_halt_req; // @[el2_dec.scala 288:19] + wire tlu_io_i_cpu_run_req; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_fastint_stall_any; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_instr_aligned; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_fetch_stall; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_ic_miss; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_ic_hit; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_bus_error; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_bus_busy; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_bus_trxn; // @[el2_dec.scala 288:19] + wire tlu_io_dec_pmu_instr_decoded; // @[el2_dec.scala 288:19] + wire tlu_io_dec_pmu_decode_stall; // @[el2_dec.scala 288:19] + wire tlu_io_dec_pmu_presync_stall; // @[el2_dec.scala 288:19] + wire tlu_io_dec_pmu_postsync_stall; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_store_stall_any; // @[el2_dec.scala 288:19] + wire tlu_io_dma_dccm_stall_any; // @[el2_dec.scala 288:19] + wire tlu_io_dma_iccm_stall_any; // @[el2_dec.scala 288:19] + wire tlu_io_exu_pmu_i0_br_misp; // @[el2_dec.scala 288:19] + wire tlu_io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 288:19] + wire tlu_io_exu_pmu_i0_pc4; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_bus_trxn; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_bus_error; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_bus_busy; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_load_external_m; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_store_external_m; // @[el2_dec.scala 288:19] + wire tlu_io_dma_pmu_dccm_read; // @[el2_dec.scala 288:19] + wire tlu_io_dma_pmu_dccm_write; // @[el2_dec.scala 288:19] + wire tlu_io_dma_pmu_any_read; // @[el2_dec.scala 288:19] + wire tlu_io_dma_pmu_any_write; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_lsu_fir_addr; // @[el2_dec.scala 288:19] + wire [1:0] tlu_io_lsu_fir_error; // @[el2_dec.scala 288:19] + wire tlu_io_iccm_dma_sb_error; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_error_pkt_r_valid; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_single_ecc_error_incr; // @[el2_dec.scala 288:19] + wire tlu_io_dec_pause_state; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_imprecise_error_store_any; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_imprecise_error_load_any; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 288:19] + wire tlu_io_dec_csr_wen_unq_d; // @[el2_dec.scala 288:19] + wire tlu_io_dec_csr_any_unq_d; // @[el2_dec.scala 288:19] + wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[el2_dec.scala 288:19] + wire tlu_io_dec_csr_wen_r; // @[el2_dec.scala 288:19] + wire [11:0] tlu_io_dec_csr_wraddr_r; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_dec_csr_wrdata_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_csr_stall_int_ff; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_exu_npc_r; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 288:19] + wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_dec_illegal_inst; // @[el2_dec.scala 288:19] + wire tlu_io_dec_i0_decode_d; // @[el2_dec.scala 288:19] + wire [1:0] tlu_io_exu_i0_br_hist_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_error_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_start_error_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_valid_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_mp_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_middle_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_way_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 288:19] + wire tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 288:19] + wire [29:0] tlu_io_dec_tlu_meihap; // @[el2_dec.scala 288:19] + wire tlu_io_dbg_halt_req; // @[el2_dec.scala 288:19] + wire tlu_io_dbg_resume_req; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_miss_state_idle; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_idle_any; // @[el2_dec.scala 288:19] + wire tlu_io_dec_div_active; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_ic_error_start; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 288:19] + wire [70:0] tlu_io_ifu_ic_debug_rd_data; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 288:19] + wire [70:0] tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 288:19] + wire [16:0] tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 288:19] + wire [7:0] tlu_io_pic_claimid; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_pic_pl; // @[el2_dec.scala 288:19] + wire tlu_io_mhwakeup; // @[el2_dec.scala 288:19] + wire tlu_io_mexintpend; // @[el2_dec.scala 288:19] + wire tlu_io_timer_int; // @[el2_dec.scala 288:19] + wire tlu_io_soft_int; // @[el2_dec.scala 288:19] + wire tlu_io_o_cpu_halt_status; // @[el2_dec.scala 288:19] + wire tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 288:19] + wire tlu_io_o_cpu_run_ack; // @[el2_dec.scala 288:19] + wire tlu_io_o_debug_mode_status; // @[el2_dec.scala 288:19] + wire [27:0] tlu_io_core_id; // @[el2_dec.scala 288:19] + wire tlu_io_mpc_debug_halt_req; // @[el2_dec.scala 288:19] + wire tlu_io_mpc_debug_run_req; // @[el2_dec.scala 288:19] + wire tlu_io_mpc_reset_run_req; // @[el2_dec.scala 288:19] + wire tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 288:19] + wire tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 288:19] + wire tlu_io_debug_brkpt_status; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_dec_tlu_meipt; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 288:19] + wire tlu_io_dec_csr_legal_d; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 288:19] + wire [1:0] tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_dec_tlu_flush_path_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_valid_wb1; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_int_valid_wb1; // @[el2_dec.scala 288:19] + wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 288:19] + wire [2:0] tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 288:19] + wire dec_trigger_io_trigger_pkt_any_0_select; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_0_m; // @[el2_dec.scala 289:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_1_select; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_1_m; // @[el2_dec.scala 289:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_2_select; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_2_m; // @[el2_dec.scala 289:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_3_select; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_3_m; // @[el2_dec.scala 289:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 289:27] + wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[el2_dec.scala 289:27] + wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 289:27] + wire _T_1 = tlu_io_dec_tlu_i0_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec.scala 592:98] + el2_dec_ib_ctl instbuff ( // @[el2_dec.scala 285:24] .io_dbg_cmd_valid(instbuff_io_dbg_cmd_valid), .io_dbg_cmd_write(instbuff_io_dbg_cmd_write), .io_dbg_cmd_type(instbuff_io_dbg_cmd_type), @@ -58422,6 +58514,7 @@ module el2_dec( .io_ifu_i0_bp_index(instbuff_io_ifu_i0_bp_index), .io_ifu_i0_bp_fghr(instbuff_io_ifu_i0_bp_fghr), .io_ifu_i0_bp_btag(instbuff_io_ifu_i0_bp_btag), + .io_ifu_i0_pc4(instbuff_io_ifu_i0_pc4), .io_ifu_i0_valid(instbuff_io_ifu_i0_valid), .io_ifu_i0_icaf(instbuff_io_ifu_i0_icaf), .io_ifu_i0_icaf_type(instbuff_io_ifu_i0_icaf_type), @@ -58433,6 +58526,7 @@ module el2_dec( .io_dec_i0_icaf_type_d(instbuff_io_dec_i0_icaf_type_d), .io_dec_i0_instr_d(instbuff_io_dec_i0_instr_d), .io_dec_i0_pc_d(instbuff_io_dec_i0_pc_d), + .io_dec_i0_pc4_d(instbuff_io_dec_i0_pc4_d), .io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid), .io_dec_i0_brp_bits_toffset(instbuff_io_dec_i0_brp_bits_toffset), .io_dec_i0_brp_bits_hist(instbuff_io_dec_i0_brp_bits_hist), @@ -58450,7 +58544,7 @@ module el2_dec( .io_dec_debug_wdata_rs1_d(instbuff_io_dec_debug_wdata_rs1_d), .io_dec_debug_fence_d(instbuff_io_dec_debug_fence_d) ); - el2_dec_decode_ctl decode ( // @[el2_dec.scala 354:22] + el2_dec_decode_ctl decode ( // @[el2_dec.scala 286:22] .clock(decode_clock), .reset(decode_reset), .io_dec_tlu_flush_extint(decode_io_dec_tlu_flush_extint), @@ -58510,6 +58604,7 @@ module el2_dec( .io_lsu_result_m(decode_io_lsu_result_m), .io_lsu_result_corr_r(decode_io_lsu_result_corr_r), .io_exu_flush_final(decode_io_exu_flush_final), + .io_exu_i0_pc_x(decode_io_exu_i0_pc_x), .io_dec_i0_instr_d(decode_io_dec_i0_instr_d), .io_dec_ib0_valid_d(decode_io_dec_ib0_valid_d), .io_exu_i0_result_x(decode_io_exu_i0_result_x), @@ -58548,6 +58643,7 @@ module el2_dec( .io_dec_i0_waddr_r(decode_io_dec_i0_waddr_r), .io_dec_i0_wen_r(decode_io_dec_i0_wen_r), .io_dec_i0_wdata_r(decode_io_dec_i0_wdata_r), + .io_dec_i0_select_pc_d(decode_io_dec_i0_select_pc_d), .io_dec_i0_rs1_bypass_en_d(decode_io_dec_i0_rs1_bypass_en_d), .io_dec_i0_rs2_bypass_en_d(decode_io_dec_i0_rs2_bypass_en_d), .io_lsu_p_valid(decode_io_lsu_p_valid), @@ -58620,7 +58716,7 @@ module el2_dec( .io_dec_div_active(decode_io_dec_div_active), .io_scan_mode(decode_io_scan_mode) ); - el2_dec_gpr_ctl gpr ( // @[el2_dec.scala 355:19] + el2_dec_gpr_ctl gpr ( // @[el2_dec.scala 287:19] .clock(gpr_clock), .reset(gpr_reset), .io_raddr0(gpr_io_raddr0), @@ -58638,7 +58734,7 @@ module el2_dec( .io_rd1(gpr_io_rd1), .io_scan_mode(gpr_io_scan_mode) ); - el2_dec_tlu_ctl tlu ( // @[el2_dec.scala 356:19] + el2_dec_tlu_ctl tlu ( // @[el2_dec.scala 288:19] .clock(tlu_clock), .reset(tlu_reset), .io_active_clk(tlu_io_active_clk), @@ -58700,6 +58796,7 @@ module el2_dec( .io_dec_csr_stall_int_ff(tlu_io_dec_csr_stall_int_ff), .io_dec_tlu_i0_valid_r(tlu_io_dec_tlu_i0_valid_r), .io_exu_npc_r(tlu_io_exu_npc_r), + .io_dec_tlu_i0_pc_r(tlu_io_dec_tlu_i0_pc_r), .io_dec_tlu_packet_r_legal(tlu_io_dec_tlu_packet_r_legal), .io_dec_tlu_packet_r_icaf(tlu_io_dec_tlu_packet_r_icaf), .io_dec_tlu_packet_r_icaf_f1(tlu_io_dec_tlu_packet_r_icaf_f1), @@ -58835,7 +58932,7 @@ module el2_dec( .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override) ); - el2_dec_trigger dec_trigger ( // @[el2_dec.scala 357:27] + el2_dec_trigger dec_trigger ( // @[el2_dec.scala 289:27] .io_trigger_pkt_any_0_select(dec_trigger_io_trigger_pkt_any_0_select), .io_trigger_pkt_any_0_match_(dec_trigger_io_trigger_pkt_any_0_match_), .io_trigger_pkt_any_0_execute(dec_trigger_io_trigger_pkt_any_0_execute), @@ -58859,376 +58956,381 @@ module el2_dec( .io_dec_i0_pc_d(dec_trigger_io_dec_i0_pc_d), .io_dec_i0_trigger_match_d(dec_trigger_io_dec_i0_trigger_match_d) ); - assign io_dec_extint_stall = decode_io_dec_extint_stall; // @[el2_dec.scala 469:40] - assign io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 479:40] - assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[el2_dec.scala 522:40] - assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[el2_dec.scala 655:29] - assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 656:29] - assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[el2_dec.scala 657:29] - assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[el2_dec.scala 658:29] - assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 659:29] - assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 660:29] - assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[el2_dec.scala 661:29] - assign io_dec_tlu_meicurpl = tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 662:29] - assign io_dec_tlu_meipt = tlu_io_dec_tlu_meipt; // @[el2_dec.scala 663:29] - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 654:29] - assign io_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 654:29] - assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 654:29] - assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 654:29] - assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 643:28] - assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 644:28] - assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 645:28] - assign io_dec_tlu_flush_noredir_r = tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 647:34] - assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 648:34] - assign io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 649:34] - assign io_dec_tlu_flush_err_r = tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 650:34] - assign io_dec_tlu_meihap = {{2'd0}, tlu_io_dec_tlu_meihap}; // @[el2_dec.scala 652:29] - assign io_dec_debug_wdata_rs1_d = instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 393:38] - assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 717:21] - assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 641:28] - assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 642:28] - assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 653:29] - assign io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 679:29] - assign io_dec_i0_rs1_en_d = decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 472:40] - assign io_dec_i0_rs2_en_d = decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 473:40] - assign io_gpr_i0_rs1_d = gpr_io_rd0; // @[el2_dec.scala 545:19] - assign io_gpr_i0_rs2_d = gpr_io_rd1; // @[el2_dec.scala 546:19] - assign io_dec_i0_immed_d = decode_io_dec_i0_immed_d; // @[el2_dec.scala 476:40] - assign io_dec_i0_br_immed_d = {{1'd0}, decode_io_dec_i0_br_immed_d}; // @[el2_dec.scala 477:40] - assign io_i0_ap_land = decode_io_i0_ap_land; // @[el2_dec.scala 478:40] - assign io_i0_ap_lor = decode_io_i0_ap_lor; // @[el2_dec.scala 478:40] - assign io_i0_ap_lxor = decode_io_i0_ap_lxor; // @[el2_dec.scala 478:40] - assign io_i0_ap_sll = decode_io_i0_ap_sll; // @[el2_dec.scala 478:40] - assign io_i0_ap_srl = decode_io_i0_ap_srl; // @[el2_dec.scala 478:40] - assign io_i0_ap_sra = decode_io_i0_ap_sra; // @[el2_dec.scala 478:40] - assign io_i0_ap_beq = decode_io_i0_ap_beq; // @[el2_dec.scala 478:40] - assign io_i0_ap_bne = decode_io_i0_ap_bne; // @[el2_dec.scala 478:40] - assign io_i0_ap_blt = decode_io_i0_ap_blt; // @[el2_dec.scala 478:40] - assign io_i0_ap_bge = decode_io_i0_ap_bge; // @[el2_dec.scala 478:40] - assign io_i0_ap_add = decode_io_i0_ap_add; // @[el2_dec.scala 478:40] - assign io_i0_ap_sub = decode_io_i0_ap_sub; // @[el2_dec.scala 478:40] - assign io_i0_ap_slt = decode_io_i0_ap_slt; // @[el2_dec.scala 478:40] - assign io_i0_ap_unsign = decode_io_i0_ap_unsign; // @[el2_dec.scala 478:40] - assign io_i0_ap_jal = decode_io_i0_ap_jal; // @[el2_dec.scala 478:40] - assign io_i0_ap_predict_t = decode_io_i0_ap_predict_t; // @[el2_dec.scala 478:40] - assign io_i0_ap_predict_nt = decode_io_i0_ap_predict_nt; // @[el2_dec.scala 478:40] - assign io_i0_ap_csr_write = decode_io_i0_ap_csr_write; // @[el2_dec.scala 478:40] - assign io_i0_ap_csr_imm = decode_io_i0_ap_csr_imm; // @[el2_dec.scala 478:40] - assign io_dec_i0_alu_decode_d = decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 480:40] - assign io_dec_i0_rs1_bypass_en_d = decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 487:40] - assign io_dec_i0_rs2_bypass_en_d = decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 488:40] - assign io_dec_i0_rs1_bypass_data_d = decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 481:40] - assign io_dec_i0_rs2_bypass_data_d = decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 482:40] - assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_dec.scala 489:40] - assign io_mul_p_valid = decode_io_mul_p_valid; // @[el2_dec.scala 490:40] - assign io_mul_p_bits_rs1_sign = decode_io_mul_p_bits_rs1_sign; // @[el2_dec.scala 490:40] - assign io_mul_p_bits_rs2_sign = decode_io_mul_p_bits_rs2_sign; // @[el2_dec.scala 490:40] - assign io_mul_p_bits_low = decode_io_mul_p_bits_low; // @[el2_dec.scala 490:40] - assign io_div_p_valid = decode_io_div_p_valid; // @[el2_dec.scala 491:40] - assign io_div_p_bits_unsign = decode_io_div_p_bits_unsign; // @[el2_dec.scala 491:40] - assign io_div_p_bits_rem = decode_io_div_p_bits_rem; // @[el2_dec.scala 491:40] - assign io_dec_div_cancel = decode_io_dec_div_cancel; // @[el2_dec.scala 493:40] - assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[el2_dec.scala 495:40] - assign io_dec_csr_ren_d = decode_io_dec_csr_ren_d; // @[el2_dec.scala 496:40] - assign io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 671:34] - assign io_dec_tlu_flush_path_r = {{1'd0}, tlu_io_dec_tlu_flush_path_r}; // @[el2_dec.scala 672:34] - assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 670:34] - assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 673:34] - assign io_pred_correct_npc_x = {{1'd0}, decode_io_pred_correct_npc_x}; // @[el2_dec.scala 508:40] - assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 666:42] - assign io_dec_tlu_br0_r_pkt_bits_hist = tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 666:42] - assign io_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 666:42] - assign io_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 666:42] - assign io_dec_tlu_br0_r_pkt_bits_way = tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 666:42] - assign io_dec_tlu_br0_r_pkt_bits_middle = tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 666:42] - assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 680:29] - assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 681:29] - assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 682:29] - assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 683:29] - assign io_dec_i0_predict_p_d_valid = decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_pc4 = decode_io_dec_i0_predict_p_d_bits_pc4; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_hist = decode_io_dec_i0_predict_p_d_bits_hist; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_toffset = decode_io_dec_i0_predict_p_d_bits_toffset; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_br_error = decode_io_dec_i0_predict_p_d_bits_br_error; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_br_start_error = decode_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_prett = decode_io_dec_i0_predict_p_d_bits_prett; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_pcall = decode_io_dec_i0_predict_p_d_bits_pcall; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_pret = decode_io_dec_i0_predict_p_d_bits_pret; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_pja = decode_io_dec_i0_predict_p_d_bits_pja; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_way = decode_io_dec_i0_predict_p_d_bits_way; // @[el2_dec.scala 509:40] - assign io_i0_predict_fghr_d = decode_io_i0_predict_fghr_d; // @[el2_dec.scala 510:40] - assign io_i0_predict_index_d = {{1'd0}, decode_io_i0_predict_index_d}; // @[el2_dec.scala 511:40] - assign io_i0_predict_btag_d = decode_io_i0_predict_btag_d; // @[el2_dec.scala 512:40] - assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 494:40] - assign io_dec_tlu_mrac_ff = tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 678:29] - assign io_dec_data_en = decode_io_dec_data_en; // @[el2_dec.scala 513:40] - assign io_dec_ctl_en = decode_io_dec_ctl_en; // @[el2_dec.scala 514:40] - assign io_rv_trace_pkt_rv_i_valid_ip = {tlu_io_dec_tlu_int_valid_wb1,_T_1}; // @[el2_dec.scala 709:33] - assign io_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb1; // @[el2_dec.scala 707:32] - assign io_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb1,1'h0}; // @[el2_dec.scala 708:35] - assign io_rv_trace_pkt_rv_i_exception_ip = {tlu_io_dec_tlu_int_valid_wb1,tlu_io_dec_tlu_i0_exc_valid_wb1}; // @[el2_dec.scala 710:37] - assign io_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[el2_dec.scala 711:34] - assign io_rv_trace_pkt_rv_i_interrupt_ip = {tlu_io_dec_tlu_int_valid_wb1,1'h0}; // @[el2_dec.scala 712:37] - assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[el2_dec.scala 713:32] - assign io_dec_tlu_external_ldfwd_disable = tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 689:43] - assign io_dec_tlu_sideeffect_posted_disable = tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 690:43] - assign io_dec_tlu_core_ecc_disable = tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 691:43] - assign io_dec_tlu_bpred_disable = tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 692:43] - assign io_dec_tlu_wb_coalescing_disable = tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 693:43] - assign io_dec_tlu_dma_qos_prty = tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 695:35] - assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 696:35] - assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 699:36] - assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 701:36] - assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 702:36] - assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 703:36] - assign io_dec_tlu_i0_commit_cmt = tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 669:34] - assign instbuff_io_dbg_cmd_valid = io_dbg_cmd_valid; // @[el2_dec.scala 364:45] - assign instbuff_io_dbg_cmd_write = io_dbg_cmd_write; // @[el2_dec.scala 365:45] - assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 366:45] - assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 367:45] - assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec.scala 368:55] - assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index[7:0]; // @[el2_dec.scala 369:35] - assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 370:35] - assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 371:35] - assign instbuff_io_ifu_i0_valid = io_ifu_i0_valid; // @[el2_dec.scala 373:35] - assign instbuff_io_ifu_i0_icaf = io_ifu_i0_icaf; // @[el2_dec.scala 374:35] - assign instbuff_io_ifu_i0_icaf_type = io_ifu_i0_icaf_type; // @[el2_dec.scala 375:35] - assign instbuff_io_ifu_i0_icaf_f1 = io_ifu_i0_icaf_f1; // @[el2_dec.scala 376:35] - assign instbuff_io_ifu_i0_dbecc = io_ifu_i0_dbecc; // @[el2_dec.scala 377:35] - assign instbuff_io_ifu_i0_instr = io_ifu_i0_instr; // @[el2_dec.scala 378:35] - assign instbuff_io_ifu_i0_pc = io_ifu_i0_pc[30:0]; // @[el2_dec.scala 379:35] + assign io_dec_extint_stall = decode_io_dec_extint_stall; // @[el2_dec.scala 389:40] + assign io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 397:40] + assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[el2_dec.scala 418:40] + assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[el2_dec.scala 548:29] + assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 549:29] + assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[el2_dec.scala 550:29] + assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[el2_dec.scala 551:29] + assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 552:29] + assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 553:29] + assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[el2_dec.scala 554:29] + assign io_dec_tlu_meicurpl = tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 555:29] + assign io_dec_tlu_meipt = tlu_io_dec_tlu_meipt; // @[el2_dec.scala 556:29] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 547:29] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 547:29] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 547:29] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 547:29] + assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 538:28] + assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 539:28] + assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 540:28] + assign io_dec_tlu_flush_noredir_r = tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 541:34] + assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 542:34] + assign io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 543:34] + assign io_dec_tlu_flush_err_r = tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 544:34] + assign io_dec_tlu_meihap = tlu_io_dec_tlu_meihap; // @[el2_dec.scala 545:29] + assign io_dec_debug_wdata_rs1_d = instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 314:38] + assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 600:21] + assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 536:28] + assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 537:28] + assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 546:29] + assign io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 564:29] + assign io_dec_i0_rs1_en_d = decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 392:40] + assign io_dec_i0_rs2_en_d = decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 393:40] + assign io_gpr_i0_rs1_d = gpr_io_rd0; // @[el2_dec.scala 440:19] + assign io_gpr_i0_rs2_d = gpr_io_rd1; // @[el2_dec.scala 441:19] + assign io_dec_i0_immed_d = decode_io_dec_i0_immed_d; // @[el2_dec.scala 394:40] + assign io_dec_i0_br_immed_d = decode_io_dec_i0_br_immed_d; // @[el2_dec.scala 395:40] + assign io_i0_ap_land = decode_io_i0_ap_land; // @[el2_dec.scala 396:40] + assign io_i0_ap_lor = decode_io_i0_ap_lor; // @[el2_dec.scala 396:40] + assign io_i0_ap_lxor = decode_io_i0_ap_lxor; // @[el2_dec.scala 396:40] + assign io_i0_ap_sll = decode_io_i0_ap_sll; // @[el2_dec.scala 396:40] + assign io_i0_ap_srl = decode_io_i0_ap_srl; // @[el2_dec.scala 396:40] + assign io_i0_ap_sra = decode_io_i0_ap_sra; // @[el2_dec.scala 396:40] + assign io_i0_ap_beq = decode_io_i0_ap_beq; // @[el2_dec.scala 396:40] + assign io_i0_ap_bne = decode_io_i0_ap_bne; // @[el2_dec.scala 396:40] + assign io_i0_ap_blt = decode_io_i0_ap_blt; // @[el2_dec.scala 396:40] + assign io_i0_ap_bge = decode_io_i0_ap_bge; // @[el2_dec.scala 396:40] + assign io_i0_ap_add = decode_io_i0_ap_add; // @[el2_dec.scala 396:40] + assign io_i0_ap_sub = decode_io_i0_ap_sub; // @[el2_dec.scala 396:40] + assign io_i0_ap_slt = decode_io_i0_ap_slt; // @[el2_dec.scala 396:40] + assign io_i0_ap_unsign = decode_io_i0_ap_unsign; // @[el2_dec.scala 396:40] + assign io_i0_ap_jal = decode_io_i0_ap_jal; // @[el2_dec.scala 396:40] + assign io_i0_ap_predict_t = decode_io_i0_ap_predict_t; // @[el2_dec.scala 396:40] + assign io_i0_ap_predict_nt = decode_io_i0_ap_predict_nt; // @[el2_dec.scala 396:40] + assign io_i0_ap_csr_write = decode_io_i0_ap_csr_write; // @[el2_dec.scala 396:40] + assign io_i0_ap_csr_imm = decode_io_i0_ap_csr_imm; // @[el2_dec.scala 396:40] + assign io_dec_i0_alu_decode_d = decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 398:40] + assign io_dec_i0_select_pc_d = decode_io_dec_i0_select_pc_d; // @[el2_dec.scala 401:40] + assign io_dec_i0_pc_d = instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 291:18] + assign io_dec_i0_rs1_bypass_en_d = decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 402:40] + assign io_dec_i0_rs2_bypass_en_d = decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 403:40] + assign io_dec_i0_rs1_bypass_data_d = decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 399:40] + assign io_dec_i0_rs2_bypass_data_d = decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 400:40] + assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_dec.scala 404:40] + assign io_mul_p_valid = decode_io_mul_p_valid; // @[el2_dec.scala 405:40] + assign io_mul_p_bits_rs1_sign = decode_io_mul_p_bits_rs1_sign; // @[el2_dec.scala 405:40] + assign io_mul_p_bits_rs2_sign = decode_io_mul_p_bits_rs2_sign; // @[el2_dec.scala 405:40] + assign io_mul_p_bits_low = decode_io_mul_p_bits_low; // @[el2_dec.scala 405:40] + assign io_div_p_valid = decode_io_div_p_valid; // @[el2_dec.scala 406:40] + assign io_div_p_bits_unsign = decode_io_div_p_bits_unsign; // @[el2_dec.scala 406:40] + assign io_div_p_bits_rem = decode_io_div_p_bits_rem; // @[el2_dec.scala 406:40] + assign io_dec_div_cancel = decode_io_dec_div_cancel; // @[el2_dec.scala 407:40] + assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[el2_dec.scala 409:40] + assign io_dec_csr_ren_d = decode_io_dec_csr_ren_d; // @[el2_dec.scala 410:40] + assign io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 560:34] + assign io_dec_tlu_flush_path_r = tlu_io_dec_tlu_flush_path_r; // @[el2_dec.scala 561:34] + assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 559:34] + assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 562:34] + assign io_pred_correct_npc_x = decode_io_pred_correct_npc_x; // @[el2_dec.scala 411:40] + assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_bits_hist = tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_bits_way = tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_bits_middle = tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 557:42] + assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 565:29] + assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 566:29] + assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 567:29] + assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 568:29] + assign io_dec_i0_predict_p_d_valid = decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_pc4 = decode_io_dec_i0_predict_p_d_bits_pc4; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_hist = decode_io_dec_i0_predict_p_d_bits_hist; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_toffset = decode_io_dec_i0_predict_p_d_bits_toffset; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_br_error = decode_io_dec_i0_predict_p_d_bits_br_error; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_br_start_error = decode_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_prett = decode_io_dec_i0_predict_p_d_bits_prett; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_pcall = decode_io_dec_i0_predict_p_d_bits_pcall; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_pret = decode_io_dec_i0_predict_p_d_bits_pret; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_pja = decode_io_dec_i0_predict_p_d_bits_pja; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_way = decode_io_dec_i0_predict_p_d_bits_way; // @[el2_dec.scala 412:40] + assign io_i0_predict_fghr_d = decode_io_i0_predict_fghr_d; // @[el2_dec.scala 413:40] + assign io_i0_predict_index_d = decode_io_i0_predict_index_d; // @[el2_dec.scala 414:40] + assign io_i0_predict_btag_d = decode_io_i0_predict_btag_d; // @[el2_dec.scala 415:40] + assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 408:40] + assign io_dec_tlu_mrac_ff = tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 563:29] + assign io_dec_data_en = decode_io_dec_data_en; // @[el2_dec.scala 416:40] + assign io_dec_ctl_en = decode_io_dec_ctl_en; // @[el2_dec.scala 417:40] + assign io_rv_trace_pkt_rv_i_valid_ip = {tlu_io_dec_tlu_int_valid_wb1,_T_1}; // @[el2_dec.scala 592:33] + assign io_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb1; // @[el2_dec.scala 590:32] + assign io_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb1,1'h0}; // @[el2_dec.scala 591:35] + assign io_rv_trace_pkt_rv_i_exception_ip = {tlu_io_dec_tlu_int_valid_wb1,tlu_io_dec_tlu_i0_exc_valid_wb1}; // @[el2_dec.scala 593:37] + assign io_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[el2_dec.scala 594:34] + assign io_rv_trace_pkt_rv_i_interrupt_ip = {tlu_io_dec_tlu_int_valid_wb1,1'h0}; // @[el2_dec.scala 595:37] + assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[el2_dec.scala 596:32] + assign io_dec_tlu_external_ldfwd_disable = tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 574:43] + assign io_dec_tlu_sideeffect_posted_disable = tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 575:43] + assign io_dec_tlu_core_ecc_disable = tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 576:43] + assign io_dec_tlu_bpred_disable = tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 577:43] + assign io_dec_tlu_wb_coalescing_disable = tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 578:43] + assign io_dec_tlu_dma_qos_prty = tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 579:35] + assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 580:35] + assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 582:36] + assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 584:36] + assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 585:36] + assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 586:36] + assign io_dec_tlu_i0_commit_cmt = tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 558:34] + assign instbuff_io_dbg_cmd_valid = io_dbg_cmd_valid; // @[el2_dec.scala 297:45] + assign instbuff_io_dbg_cmd_write = io_dbg_cmd_write; // @[el2_dec.scala 298:45] + assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 299:45] + assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 300:45] + assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec.scala 301:55] + assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec.scala 302:35] + assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 303:35] + assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 304:35] + assign instbuff_io_ifu_i0_pc4 = io_ifu_i0_pc4; // @[el2_dec.scala 305:35] + assign instbuff_io_ifu_i0_valid = io_ifu_i0_valid; // @[el2_dec.scala 306:35] + assign instbuff_io_ifu_i0_icaf = io_ifu_i0_icaf; // @[el2_dec.scala 307:35] + assign instbuff_io_ifu_i0_icaf_type = io_ifu_i0_icaf_type; // @[el2_dec.scala 308:35] + assign instbuff_io_ifu_i0_icaf_f1 = io_ifu_i0_icaf_f1; // @[el2_dec.scala 309:35] + assign instbuff_io_ifu_i0_dbecc = io_ifu_i0_dbecc; // @[el2_dec.scala 310:35] + assign instbuff_io_ifu_i0_instr = io_ifu_i0_instr; // @[el2_dec.scala 311:35] + assign instbuff_io_ifu_i0_pc = io_ifu_i0_pc; // @[el2_dec.scala 312:35] assign decode_clock = clock; assign decode_reset = reset; - assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 410:48 el2_dec.scala 651:37] - assign decode_io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 411:48] - assign decode_io_ifu_i0_cinst = io_ifu_i0_cinst; // @[el2_dec.scala 412:48] - assign decode_io_lsu_nonblock_load_valid_m = io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 413:48] - assign decode_io_lsu_nonblock_load_tag_m = io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 414:48] - assign decode_io_lsu_nonblock_load_inv_r = io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 415:48] - assign decode_io_lsu_nonblock_load_inv_tag_r = io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 416:48] - assign decode_io_lsu_nonblock_load_data_valid = io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 417:48] - assign decode_io_lsu_nonblock_load_data_error = io_lsu_nonblock_load_data_error; // @[el2_dec.scala 418:48] - assign decode_io_lsu_nonblock_load_data_tag = io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 419:48] - assign decode_io_lsu_nonblock_load_data = io_lsu_nonblock_load_data; // @[el2_dec.scala 420:48] - assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 421:48] - assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 422:48 el2_dec.scala 674:35] - assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 423:48] - assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[el2_dec.scala 424:48] - assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 425:48] - assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 426:48 el2_dec.scala 646:36] - assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 427:48] - assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 394:38 el2_dec.scala 428:48] - assign decode_io_dbg_cmd_wrdata = io_dbg_cmd_wrdata; // @[el2_dec.scala 429:48] - assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 390:38 el2_dec.scala 430:48] - assign decode_io_dec_i0_icaf_f1_d = instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 391:38 el2_dec.scala 431:48] - assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 382:38 el2_dec.scala 432:48] - assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 392:38 el2_dec.scala 433:48] - assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 387:38 el2_dec.scala 435:48] - assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 388:38 el2_dec.scala 436:48] - assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 389:38 el2_dec.scala 437:48] - assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 439:48] - assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[el2_dec.scala 440:48] - assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 441:48] - assign decode_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 442:48] - assign decode_io_exu_div_wren = io_exu_div_wren; // @[el2_dec.scala 443:48] - assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 444:48 el2_dec.scala 667:42] - assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 445:48 el2_dec.scala 668:42] - assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 446:48] - assign decode_io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 447:48] - assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 448:48 el2_dec.scala 675:35] - assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 449:48 el2_dec.scala 676:35] - assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 450:48 el2_dec.scala 677:35] - assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc_d[0]; // @[el2_dec.scala 385:38 el2_dec.scala 451:48] - assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 452:48 el2_dec.scala 664:33] - assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[el2_dec.scala 453:48 el2_dec.scala 665:33] - assign decode_io_exu_csr_rs1_x = io_exu_csr_rs1_x; // @[el2_dec.scala 454:48] - assign decode_io_lsu_result_m = io_lsu_result_m; // @[el2_dec.scala 455:48] - assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[el2_dec.scala 456:48] - assign decode_io_exu_flush_final = io_exu_flush_final; // @[el2_dec.scala 457:48] - assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 383:38 el2_dec.scala 459:48] - assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 381:38 el2_dec.scala 460:48] - assign decode_io_exu_i0_result_x = io_exu_i0_result_x; // @[el2_dec.scala 461:48] - assign decode_io_free_clk = io_free_clk; // @[el2_dec.scala 463:48] - assign decode_io_active_clk = io_active_clk; // @[el2_dec.scala 464:48] - assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 465:48] - assign decode_io_scan_mode = io_scan_mode; // @[el2_dec.scala 467:48] + assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 330:48] + assign decode_io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 331:48] + assign decode_io_ifu_i0_cinst = io_ifu_i0_cinst; // @[el2_dec.scala 332:48] + assign decode_io_lsu_nonblock_load_valid_m = io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 333:48] + assign decode_io_lsu_nonblock_load_tag_m = io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 334:48] + assign decode_io_lsu_nonblock_load_inv_r = io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 335:48] + assign decode_io_lsu_nonblock_load_inv_tag_r = io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 336:48] + assign decode_io_lsu_nonblock_load_data_valid = io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 337:48] + assign decode_io_lsu_nonblock_load_data_error = io_lsu_nonblock_load_data_error; // @[el2_dec.scala 338:48] + assign decode_io_lsu_nonblock_load_data_tag = io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 339:48] + assign decode_io_lsu_nonblock_load_data = io_lsu_nonblock_load_data; // @[el2_dec.scala 340:48] + assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 341:48] + assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 342:48] + assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 343:48] + assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[el2_dec.scala 344:48] + assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 345:48] + assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 346:48] + assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 347:48] + assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 348:48] + assign decode_io_dbg_cmd_wrdata = io_dbg_cmd_wrdata; // @[el2_dec.scala 349:48] + assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 350:48] + assign decode_io_dec_i0_icaf_f1_d = instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 351:48] + assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 352:48] + assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:48] + assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 355:48] + assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 356:48] + assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 357:48] + assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 359:48] + assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[el2_dec.scala 360:48] + assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 361:48] + assign decode_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 362:48] + assign decode_io_exu_div_wren = io_exu_div_wren; // @[el2_dec.scala 363:48] + assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 364:48] + assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 365:48] + assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 366:48] + assign decode_io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 367:48] + assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 368:48] + assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 369:48] + assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 370:48] + assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 371:48] + assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 372:48] + assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[el2_dec.scala 373:48] + assign decode_io_exu_csr_rs1_x = io_exu_csr_rs1_x; // @[el2_dec.scala 374:48] + assign decode_io_lsu_result_m = io_lsu_result_m; // @[el2_dec.scala 375:48] + assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[el2_dec.scala 376:48] + assign decode_io_exu_flush_final = io_exu_flush_final; // @[el2_dec.scala 377:48] + assign decode_io_exu_i0_pc_x = io_exu_i0_pc_x; // @[el2_dec.scala 378:48] + assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 379:48] + assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 380:48] + assign decode_io_exu_i0_result_x = io_exu_i0_result_x; // @[el2_dec.scala 381:48] + assign decode_io_free_clk = io_free_clk; // @[el2_dec.scala 383:48] + assign decode_io_active_clk = io_active_clk; // @[el2_dec.scala 384:48] + assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 385:48] + assign decode_io_scan_mode = io_scan_mode; // @[el2_dec.scala 387:48] assign gpr_clock = clock; assign gpr_reset = reset; - assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[el2_dec.scala 474:40 el2_dec.scala 530:23] - assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[el2_dec.scala 475:40 el2_dec.scala 531:23] - assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[el2_dec.scala 484:40 el2_dec.scala 532:23] - assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[el2_dec.scala 483:40 el2_dec.scala 533:23] - assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 485:40 el2_dec.scala 534:23] - assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 535:23] - assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 536:23] - assign gpr_io_wd1 = io_lsu_nonblock_load_data; // @[el2_dec.scala 537:23] - assign gpr_io_wen2 = io_exu_div_wren; // @[el2_dec.scala 538:23] - assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[el2_dec.scala 492:40 el2_dec.scala 539:23] - assign gpr_io_wd2 = io_exu_div_result; // @[el2_dec.scala 540:23] - assign gpr_io_scan_mode = io_scan_mode; // @[el2_dec.scala 543:23] + assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[el2_dec.scala 425:23] + assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[el2_dec.scala 426:23] + assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[el2_dec.scala 427:23] + assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[el2_dec.scala 428:23] + assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 429:23] + assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 430:23] + assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 431:23] + assign gpr_io_wd1 = io_lsu_nonblock_load_data; // @[el2_dec.scala 432:23] + assign gpr_io_wen2 = io_exu_div_wren; // @[el2_dec.scala 433:23] + assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[el2_dec.scala 434:23] + assign gpr_io_wd2 = io_exu_div_result; // @[el2_dec.scala 435:23] + assign gpr_io_scan_mode = io_scan_mode; // @[el2_dec.scala 438:23] assign tlu_clock = clock; assign tlu_reset = reset; - assign tlu_io_active_clk = io_active_clk; // @[el2_dec.scala 555:45] - assign tlu_io_free_clk = io_free_clk; // @[el2_dec.scala 556:45] - assign tlu_io_scan_mode = io_scan_mode; // @[el2_dec.scala 558:45] - assign tlu_io_rst_vec = io_rst_vec[30:0]; // @[el2_dec.scala 559:45] - assign tlu_io_nmi_int = io_nmi_int; // @[el2_dec.scala 560:45] - assign tlu_io_nmi_vec = io_nmi_vec[30:0]; // @[el2_dec.scala 561:45] - assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_dec.scala 562:45] - assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_dec.scala 563:45] - assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[el2_dec.scala 564:45] - assign tlu_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[el2_dec.scala 565:45] - assign tlu_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[el2_dec.scala 566:45] - assign tlu_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[el2_dec.scala 567:45] - assign tlu_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[el2_dec.scala 568:45] - assign tlu_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[el2_dec.scala 569:45] - assign tlu_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec.scala 570:45] - assign tlu_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[el2_dec.scala 571:45] - assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 572:45] - assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 573:45] - assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 574:45] - assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 515:40 el2_dec.scala 516:40 el2_dec.scala 517:40 el2_dec.scala 518:40 el2_dec.scala 519:40 el2_dec.scala 520:40 el2_dec.scala 521:40 el2_dec.scala 575:45] - assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 576:45] - assign tlu_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 577:45] - assign tlu_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_dec.scala 578:45] - assign tlu_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[el2_dec.scala 579:45] - assign tlu_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 580:45] - assign tlu_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[el2_dec.scala 581:45] - assign tlu_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[el2_dec.scala 582:45] - assign tlu_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 583:45] - assign tlu_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[el2_dec.scala 584:45] - assign tlu_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec.scala 585:45] - assign tlu_io_lsu_pmu_load_external_m = io_lsu_pmu_load_external_m; // @[el2_dec.scala 586:45] - assign tlu_io_lsu_pmu_store_external_m = io_lsu_pmu_store_external_m; // @[el2_dec.scala 587:45] - assign tlu_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[el2_dec.scala 588:45] - assign tlu_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[el2_dec.scala 589:45] - assign tlu_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec.scala 590:45] - assign tlu_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec.scala 591:45] - assign tlu_io_lsu_fir_addr = io_lsu_fir_addr[30:0]; // @[el2_dec.scala 592:45] - assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[el2_dec.scala 593:45] - assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[el2_dec.scala 594:45] - assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[el2_dec.scala 596:45] - assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[el2_dec.scala 597:45] - assign tlu_io_lsu_imprecise_error_store_any = io_lsu_imprecise_error_store_any; // @[el2_dec.scala 598:45] - assign tlu_io_lsu_imprecise_error_load_any = io_lsu_imprecise_error_load_any; // @[el2_dec.scala 599:45] - assign tlu_io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 600:45] - assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 497:40 el2_dec.scala 601:45] - assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 498:40 el2_dec.scala 602:45] - assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 499:40 el2_dec.scala 603:45] - assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[el2_dec.scala 500:40 el2_dec.scala 604:45] - assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 501:40 el2_dec.scala 605:45] - assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 502:40 el2_dec.scala 606:45] - assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 503:40 el2_dec.scala 607:45] - assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 504:40 el2_dec.scala 608:45] - assign tlu_io_exu_npc_r = io_exu_npc_r[30:0]; // @[el2_dec.scala 609:45] - assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_icaf_f1 = decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[el2_dec.scala 507:40 el2_dec.scala 612:45] - assign tlu_io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 613:45] - assign tlu_io_exu_i0_br_hist_r = io_exu_i0_br_hist_r; // @[el2_dec.scala 614:45] - assign tlu_io_exu_i0_br_error_r = io_exu_i0_br_error_r; // @[el2_dec.scala 615:45] - assign tlu_io_exu_i0_br_start_error_r = io_exu_i0_br_start_error_r; // @[el2_dec.scala 616:45] - assign tlu_io_exu_i0_br_valid_r = io_exu_i0_br_valid_r; // @[el2_dec.scala 617:45] - assign tlu_io_exu_i0_br_mp_r = io_exu_i0_br_mp_r; // @[el2_dec.scala 618:45] - assign tlu_io_exu_i0_br_middle_r = io_exu_i0_br_middle_r; // @[el2_dec.scala 619:45] - assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[el2_dec.scala 620:45] - assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[el2_dec.scala 621:45] - assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[el2_dec.scala 622:45] - assign tlu_io_ifu_miss_state_idle = io_ifu_miss_state_idle; // @[el2_dec.scala 623:45] - assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 624:45] - assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[el2_dec.scala 523:40 el2_dec.scala 625:45] - assign tlu_io_ifu_ic_error_start = io_ifu_ic_error_start; // @[el2_dec.scala 626:45] - assign tlu_io_ifu_iccm_rd_ecc_single_err = io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 627:45] - assign tlu_io_ifu_ic_debug_rd_data = {{1'd0}, io_ifu_ic_debug_rd_data}; // @[el2_dec.scala 628:45] - assign tlu_io_ifu_ic_debug_rd_data_valid = io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 629:45] - assign tlu_io_pic_claimid = io_pic_claimid; // @[el2_dec.scala 630:45] - assign tlu_io_pic_pl = io_pic_pl; // @[el2_dec.scala 631:45] - assign tlu_io_mhwakeup = io_mhwakeup; // @[el2_dec.scala 632:45] - assign tlu_io_mexintpend = io_mexintpend; // @[el2_dec.scala 633:45] - assign tlu_io_timer_int = io_timer_int; // @[el2_dec.scala 634:45] - assign tlu_io_soft_int = io_soft_int; // @[el2_dec.scala 635:45] - assign tlu_io_core_id = io_core_id[27:0]; // @[el2_dec.scala 636:45] - assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_dec.scala 637:45] - assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_dec.scala 638:45] - assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec.scala 639:45] - assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 401:34] - assign dec_trigger_io_dec_i0_pc_d = instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 400:30] + assign tlu_io_active_clk = io_active_clk; // @[el2_dec.scala 450:45] + assign tlu_io_free_clk = io_free_clk; // @[el2_dec.scala 451:45] + assign tlu_io_scan_mode = io_scan_mode; // @[el2_dec.scala 453:45] + assign tlu_io_rst_vec = io_rst_vec; // @[el2_dec.scala 454:45] + assign tlu_io_nmi_int = io_nmi_int; // @[el2_dec.scala 455:45] + assign tlu_io_nmi_vec = io_nmi_vec; // @[el2_dec.scala 456:45] + assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_dec.scala 457:45] + assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_dec.scala 458:45] + assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[el2_dec.scala 459:45] + assign tlu_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[el2_dec.scala 460:45] + assign tlu_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[el2_dec.scala 461:45] + assign tlu_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[el2_dec.scala 462:45] + assign tlu_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[el2_dec.scala 463:45] + assign tlu_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[el2_dec.scala 464:45] + assign tlu_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec.scala 465:45] + assign tlu_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[el2_dec.scala 466:45] + assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 467:45] + assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 468:45] + assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 469:45] + assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 470:45] + assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 471:45] + assign tlu_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 472:45] + assign tlu_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_dec.scala 473:45] + assign tlu_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[el2_dec.scala 474:45] + assign tlu_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 475:45] + assign tlu_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[el2_dec.scala 476:45] + assign tlu_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[el2_dec.scala 477:45] + assign tlu_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 478:45] + assign tlu_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[el2_dec.scala 479:45] + assign tlu_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec.scala 480:45] + assign tlu_io_lsu_pmu_load_external_m = io_lsu_pmu_load_external_m; // @[el2_dec.scala 481:45] + assign tlu_io_lsu_pmu_store_external_m = io_lsu_pmu_store_external_m; // @[el2_dec.scala 482:45] + assign tlu_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[el2_dec.scala 483:45] + assign tlu_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[el2_dec.scala 484:45] + assign tlu_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec.scala 485:45] + assign tlu_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec.scala 486:45] + assign tlu_io_lsu_fir_addr = io_lsu_fir_addr; // @[el2_dec.scala 487:45] + assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[el2_dec.scala 488:45] + assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[el2_dec.scala 489:45] + assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[el2_dec.scala 491:45] + assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[el2_dec.scala 492:45] + assign tlu_io_lsu_imprecise_error_store_any = io_lsu_imprecise_error_store_any; // @[el2_dec.scala 493:45] + assign tlu_io_lsu_imprecise_error_load_any = io_lsu_imprecise_error_load_any; // @[el2_dec.scala 494:45] + assign tlu_io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 495:45] + assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 496:45] + assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 497:45] + assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 498:45] + assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[el2_dec.scala 499:45] + assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 500:45] + assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 501:45] + assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 502:45] + assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 503:45] + assign tlu_io_exu_npc_r = io_exu_npc_r; // @[el2_dec.scala 504:45] + assign tlu_io_dec_tlu_i0_pc_r = decode_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 505:45] + assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_icaf_f1 = decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 506:45] + assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[el2_dec.scala 507:45] + assign tlu_io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 508:45] + assign tlu_io_exu_i0_br_hist_r = io_exu_i0_br_hist_r; // @[el2_dec.scala 509:45] + assign tlu_io_exu_i0_br_error_r = io_exu_i0_br_error_r; // @[el2_dec.scala 510:45] + assign tlu_io_exu_i0_br_start_error_r = io_exu_i0_br_start_error_r; // @[el2_dec.scala 511:45] + assign tlu_io_exu_i0_br_valid_r = io_exu_i0_br_valid_r; // @[el2_dec.scala 512:45] + assign tlu_io_exu_i0_br_mp_r = io_exu_i0_br_mp_r; // @[el2_dec.scala 513:45] + assign tlu_io_exu_i0_br_middle_r = io_exu_i0_br_middle_r; // @[el2_dec.scala 514:45] + assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[el2_dec.scala 515:45] + assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[el2_dec.scala 516:45] + assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[el2_dec.scala 517:45] + assign tlu_io_ifu_miss_state_idle = io_ifu_miss_state_idle; // @[el2_dec.scala 518:45] + assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 519:45] + assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[el2_dec.scala 520:45] + assign tlu_io_ifu_ic_error_start = io_ifu_ic_error_start; // @[el2_dec.scala 521:45] + assign tlu_io_ifu_iccm_rd_ecc_single_err = io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 522:45] + assign tlu_io_ifu_ic_debug_rd_data = io_ifu_ic_debug_rd_data; // @[el2_dec.scala 523:45] + assign tlu_io_ifu_ic_debug_rd_data_valid = io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 524:45] + assign tlu_io_pic_claimid = io_pic_claimid; // @[el2_dec.scala 525:45] + assign tlu_io_pic_pl = io_pic_pl; // @[el2_dec.scala 526:45] + assign tlu_io_mhwakeup = io_mhwakeup; // @[el2_dec.scala 527:45] + assign tlu_io_mexintpend = io_mexintpend; // @[el2_dec.scala 528:45] + assign tlu_io_timer_int = io_timer_int; // @[el2_dec.scala 529:45] + assign tlu_io_soft_int = io_soft_int; // @[el2_dec.scala 530:45] + assign tlu_io_core_id = io_core_id; // @[el2_dec.scala 531:45] + assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_dec.scala 532:45] + assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_dec.scala 533:45] + assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec.scala 534:45] + assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 321:34] + assign dec_trigger_io_dec_i0_pc_d = instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 320:30] endmodule module rvclkhdr_757( output io_l1clk, @@ -60194,7 +60296,9 @@ module el2_exu_alu_ctl( input io_csr_ren_in, input [31:0] io_a_in, input [31:0] io_b_in, + input [30:0] io_pc_in, input io_pp_in_valid, + input io_pp_in_bits_boffset, input io_pp_in_bits_pc4, input [1:0] io_pp_in_bits_hist, input [11:0] io_pp_in_bits_toffset, @@ -60210,10 +60314,12 @@ module el2_exu_alu_ctl( output io_flush_upper_out, output io_flush_final_out, output [30:0] io_flush_path_out, + output [30:0] io_pc_ff, output io_pred_correct_out, output io_predict_p_out_valid, output io_predict_p_out_bits_misp, output io_predict_p_out_bits_ataken, + output io_predict_p_out_bits_boffset, output io_predict_p_out_bits_pc4, output [1:0] io_predict_p_out_bits_hist, output [11:0] io_predict_p_out_bits_toffset, @@ -60226,6 +60332,7 @@ module el2_exu_alu_ctl( ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; + reg [31:0] _RAND_1; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] @@ -60235,6 +60342,7 @@ module el2_exu_alu_ctl( wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + reg [30:0] _T_1; // @[el2_lib.scala 514:16] reg [31:0] _T_3; // @[el2_lib.scala 514:16] wire [31:0] _T_5 = ~io_b_in; // @[el2_exu_alu_ctl.scala 39:37] wire [31:0] bm = io_ap_sub ? _T_5 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17] @@ -60312,16 +60420,21 @@ module el2_exu_alu_ctl( wire _T_214 = _T_213 | io_pp_in_bits_pja; // @[el2_exu_alu_ctl.scala 79:63] wire sel_pc = _T_214 | io_pp_in_bits_pret; // @[el2_exu_alu_ctl.scala 79:83] wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40] + wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_221 = {{1'd0}, _T_218[12:1]}; // @[el2_lib.scala 208:31] - wire [18:0] _T_227 = 19'h0 - 19'h1; // @[el2_lib.scala 210:27] + wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 208:31] + wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 209:27] + wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27] wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28] + wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26] wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:20] wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:26] wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:26] - wire [18:0] _T_243 = _T_236 ? 19'h1 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_246 = _T_243 | _T_244; // @[Mux.scala 27:72] + wire [18:0] _T_245 = _T_242 | _T_243; // @[Mux.scala 27:72] + wire [18:0] _T_246 = _T_245 | _T_244; // @[Mux.scala 27:72] wire [31:0] pcout = {_T_246,_T_221[11:0],1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_250 = $signed(_T_77) | $signed(_T_73); // @[el2_exu_alu_ctl.scala 88:24] wire [31:0] _T_251 = {31'h0,slt_one}; // @[Cat.scala 29:58] @@ -60387,10 +60500,12 @@ module el2_exu_alu_ctl( assign io_flush_upper_out = _T_301 & _T_302; // @[el2_exu_alu_ctl.scala 116:26] assign io_flush_final_out = _T_301 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 118:26] assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22] + assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12] assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26] assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:35] assign io_predict_p_out_bits_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:35] + assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:35] assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[el2_exu_alu_ctl.scala 125:30] @@ -60442,8 +60557,13 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - _T_3 = _RAND_0[31:0]; + _T_1 = _RAND_0[30:0]; + _RAND_1 = {1{`RANDOM}}; + _T_3 = _RAND_1[31:0]; `endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_1 = 31'h0; + end if (reset) begin _T_3 = 32'h0; end @@ -60453,6 +60573,13 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_1 <= 31'h0; + end else begin + _T_1 <= io_pc_in; + end + end always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin if (reset) begin _T_3 <= 32'h0; @@ -61485,6 +61612,8 @@ module el2_exu( input [31:0] io_dec_i0_rs2_bypass_data_d, input [11:0] io_dec_i0_br_immed_d, input io_dec_i0_alu_decode_d, + input io_dec_i0_select_pc_d, + input [30:0] io_dec_i0_pc_d, input [1:0] io_dec_i0_rs1_bypass_en_d, input [1:0] io_dec_i0_rs2_bypass_en_d, input io_dec_csr_ren_d, @@ -61506,6 +61635,7 @@ module el2_exu( output io_exu_flush_final, output [30:0] io_exu_flush_path_final, output [31:0] io_exu_i0_result_x, + output [30:0] io_exu_i0_pc_x, output [31:0] io_exu_csr_rs1_x, output [30:0] io_exu_npc_r, output [1:0] io_exu_i0_br_hist_r, @@ -61519,6 +61649,7 @@ module el2_exu( output io_exu_i0_br_way_r, output io_exu_mp_pkt_bits_misp, output io_exu_mp_pkt_bits_ataken, + output io_exu_mp_pkt_bits_boffset, output io_exu_mp_pkt_bits_pc4, output [1:0] io_exu_mp_pkt_bits_hist, output [11:0] io_exu_mp_pkt_bits_toffset, @@ -61573,6 +61704,8 @@ module el2_exu( reg [31:0] _RAND_33; reg [31:0] _RAND_34; reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] @@ -61675,7 +61808,9 @@ module el2_exu( wire i_alu_io_csr_ren_in; // @[el2_exu.scala 187:19] wire [31:0] i_alu_io_a_in; // @[el2_exu.scala 187:19] wire [31:0] i_alu_io_b_in; // @[el2_exu.scala 187:19] + wire [30:0] i_alu_io_pc_in; // @[el2_exu.scala 187:19] wire i_alu_io_pp_in_valid; // @[el2_exu.scala 187:19] + wire i_alu_io_pp_in_bits_boffset; // @[el2_exu.scala 187:19] wire i_alu_io_pp_in_bits_pc4; // @[el2_exu.scala 187:19] wire [1:0] i_alu_io_pp_in_bits_hist; // @[el2_exu.scala 187:19] wire [11:0] i_alu_io_pp_in_bits_toffset; // @[el2_exu.scala 187:19] @@ -61691,10 +61826,12 @@ module el2_exu( wire i_alu_io_flush_upper_out; // @[el2_exu.scala 187:19] wire i_alu_io_flush_final_out; // @[el2_exu.scala 187:19] wire [30:0] i_alu_io_flush_path_out; // @[el2_exu.scala 187:19] + wire [30:0] i_alu_io_pc_ff; // @[el2_exu.scala 187:19] wire i_alu_io_pred_correct_out; // @[el2_exu.scala 187:19] wire i_alu_io_predict_p_out_valid; // @[el2_exu.scala 187:19] wire i_alu_io_predict_p_out_bits_misp; // @[el2_exu.scala 187:19] wire i_alu_io_predict_p_out_bits_ataken; // @[el2_exu.scala 187:19] + wire i_alu_io_predict_p_out_bits_boffset; // @[el2_exu.scala 187:19] wire i_alu_io_predict_p_out_bits_pc4; // @[el2_exu.scala 187:19] wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[el2_exu.scala 187:19] wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[el2_exu.scala 187:19] @@ -61731,6 +61868,7 @@ module el2_exu( reg i0_predict_p_x_valid; // @[el2_lib.scala 524:16] reg i0_predict_p_x_bits_misp; // @[el2_lib.scala 524:16] reg i0_predict_p_x_bits_ataken; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_bits_boffset; // @[el2_lib.scala 524:16] reg i0_predict_p_x_bits_pc4; // @[el2_lib.scala 524:16] reg [1:0] i0_predict_p_x_bits_hist; // @[el2_lib.scala 524:16] reg [11:0] i0_predict_p_x_bits_toffset; // @[el2_lib.scala 524:16] @@ -61750,6 +61888,7 @@ module el2_exu( reg i0_pp_r_valid; // @[el2_lib.scala 524:16] reg i0_pp_r_bits_misp; // @[el2_lib.scala 524:16] reg i0_pp_r_bits_ataken; // @[el2_lib.scala 524:16] + reg i0_pp_r_bits_boffset; // @[el2_lib.scala 524:16] reg i0_pp_r_bits_pc4; // @[el2_lib.scala 524:16] reg [1:0] i0_pp_r_bits_hist; // @[el2_lib.scala 524:16] reg i0_pp_r_bits_br_error; // @[el2_lib.scala 524:16] @@ -61791,14 +61930,18 @@ module el2_exu( wire [31:0] _T_60 = io_dec_i0_rs2_bypass_en_d[1] ? io_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] i0_rs2_bypass_data_d = _T_59 | _T_60; // @[Mux.scala 27:72] wire _T_63 = ~i0_rs1_bypass_en_d; // @[el2_exu.scala 150:6] + wire _T_64 = _T_63 & io_dec_i0_select_pc_d; // @[el2_exu.scala 150:26] + wire [31:0] _T_66 = {io_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58] wire _T_68 = _T_63 & io_dec_debug_wdata_rs1_d; // @[el2_exu.scala 151:26] wire _T_71 = ~io_dec_debug_wdata_rs1_d; // @[el2_exu.scala 152:28] wire _T_72 = _T_63 & _T_71; // @[el2_exu.scala 152:26] wire _T_73 = _T_72 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 152:54] wire [31:0] _T_75 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_76 = _T_64 ? _T_66 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_77 = _T_68 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_78 = _T_73 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_80 = _T_75 | _T_77; // @[Mux.scala 27:72] + wire [31:0] _T_79 = _T_75 | _T_76; // @[Mux.scala 27:72] + wire [31:0] _T_80 = _T_79 | _T_77; // @[Mux.scala 27:72] wire [31:0] i0_rs1_d = _T_80 | _T_78; // @[Mux.scala 27:72] wire _T_82 = ~i0_rs2_bypass_en_d; // @[el2_exu.scala 156:6] wire _T_83 = _T_82 & io_dec_i0_rs2_en_d; // @[el2_exu.scala 156:26] @@ -61968,7 +62111,9 @@ module el2_exu( .io_csr_ren_in(i_alu_io_csr_ren_in), .io_a_in(i_alu_io_a_in), .io_b_in(i_alu_io_b_in), + .io_pc_in(i_alu_io_pc_in), .io_pp_in_valid(i_alu_io_pp_in_valid), + .io_pp_in_bits_boffset(i_alu_io_pp_in_bits_boffset), .io_pp_in_bits_pc4(i_alu_io_pp_in_bits_pc4), .io_pp_in_bits_hist(i_alu_io_pp_in_bits_hist), .io_pp_in_bits_toffset(i_alu_io_pp_in_bits_toffset), @@ -61984,10 +62129,12 @@ module el2_exu( .io_flush_upper_out(i_alu_io_flush_upper_out), .io_flush_final_out(i_alu_io_flush_final_out), .io_flush_path_out(i_alu_io_flush_path_out), + .io_pc_ff(i_alu_io_pc_ff), .io_pred_correct_out(i_alu_io_pred_correct_out), .io_predict_p_out_valid(i_alu_io_predict_p_out_valid), .io_predict_p_out_bits_misp(i_alu_io_predict_p_out_bits_misp), .io_predict_p_out_bits_ataken(i_alu_io_predict_p_out_bits_ataken), + .io_predict_p_out_bits_boffset(i_alu_io_predict_p_out_bits_boffset), .io_predict_p_out_bits_pc4(i_alu_io_predict_p_out_bits_pc4), .io_predict_p_out_bits_hist(i_alu_io_predict_p_out_bits_hist), .io_predict_p_out_bits_toffset(i_alu_io_predict_p_out_bits_toffset), @@ -62028,6 +62175,7 @@ module el2_exu( assign io_exu_flush_final = i_alu_io_flush_final_out; // @[el2_exu.scala 202:33] assign io_exu_flush_path_final = io_dec_tlu_flush_lower_r ? io_dec_tlu_flush_path_r : i0_flush_path_d; // @[el2_exu.scala 277:50] assign io_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[el2_exu.scala 224:42] + assign io_exu_i0_pc_x = i_alu_io_pc_ff; // @[el2_exu.scala 206:41] assign io_exu_csr_rs1_x = _T_3; // @[el2_exu.scala 107:41] assign io_exu_npc_r = _T_188[30:0]; // @[el2_exu.scala 278:50] assign io_exu_i0_br_hist_r = i0_pp_r_bits_hist; // @[el2_exu.scala 251:50] @@ -62036,11 +62184,12 @@ module el2_exu( assign io_exu_i0_br_index_r = predpipe_r[12:5]; // @[el2_exu.scala 256:42] assign io_exu_i0_br_valid_r = i0_pp_r_valid; // @[el2_exu.scala 248:36] assign io_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[el2_exu.scala 249:36] - assign io_exu_i0_br_middle_r = i0_pp_r_bits_pc4; // @[el2_exu.scala 253:36] + assign io_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[el2_exu.scala 253:36] assign io_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[el2_exu.scala 255:50] assign io_exu_i0_br_way_r = i0_pp_r_bits_way; // @[el2_exu.scala 250:36] assign io_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[el2_exu.scala 264:41] assign io_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[el2_exu.scala 268:41] + assign io_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[el2_exu.scala 269:41] assign io_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[el2_exu.scala 270:41] assign io_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[el2_exu.scala 271:58] assign io_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[el2_exu.scala 272:50] @@ -62140,7 +62289,9 @@ module el2_exu( assign i_alu_io_csr_ren_in = io_dec_csr_ren_d; // @[el2_exu.scala 199:33] assign i_alu_io_a_in = _T_80 | _T_78; // @[el2_exu.scala 194:33] assign i_alu_io_b_in = i0_rs2_d; // @[el2_exu.scala 195:33] + assign i_alu_io_pc_in = io_dec_i0_pc_d; // @[el2_exu.scala 196:41] assign i_alu_io_pp_in_valid = io_dec_i0_predict_p_d_valid; // @[el2_exu.scala 190:41] + assign i_alu_io_pp_in_bits_boffset = io_dec_i0_pc_d[0]; // @[el2_exu.scala 190:41] assign i_alu_io_pp_in_bits_pc4 = io_dec_i0_predict_p_d_bits_pc4; // @[el2_exu.scala 190:41] assign i_alu_io_pp_in_bits_hist = io_dec_i0_predict_p_d_bits_hist; // @[el2_exu.scala 190:41] assign i_alu_io_pp_in_bits_toffset = io_dec_i0_predict_p_d_bits_toffset; // @[el2_exu.scala 190:41] @@ -62216,67 +62367,71 @@ initial begin _RAND_4 = {1{`RANDOM}}; i0_predict_p_x_bits_ataken = _RAND_4[0:0]; _RAND_5 = {1{`RANDOM}}; - i0_predict_p_x_bits_pc4 = _RAND_5[0:0]; + i0_predict_p_x_bits_boffset = _RAND_5[0:0]; _RAND_6 = {1{`RANDOM}}; - i0_predict_p_x_bits_hist = _RAND_6[1:0]; + i0_predict_p_x_bits_pc4 = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - i0_predict_p_x_bits_toffset = _RAND_7[11:0]; + i0_predict_p_x_bits_hist = _RAND_7[1:0]; _RAND_8 = {1{`RANDOM}}; - i0_predict_p_x_bits_br_error = _RAND_8[0:0]; + i0_predict_p_x_bits_toffset = _RAND_8[11:0]; _RAND_9 = {1{`RANDOM}}; - i0_predict_p_x_bits_br_start_error = _RAND_9[0:0]; + i0_predict_p_x_bits_br_error = _RAND_9[0:0]; _RAND_10 = {1{`RANDOM}}; - i0_predict_p_x_bits_pcall = _RAND_10[0:0]; + i0_predict_p_x_bits_br_start_error = _RAND_10[0:0]; _RAND_11 = {1{`RANDOM}}; - i0_predict_p_x_bits_pret = _RAND_11[0:0]; + i0_predict_p_x_bits_pcall = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - i0_predict_p_x_bits_pja = _RAND_12[0:0]; + i0_predict_p_x_bits_pret = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - i0_predict_p_x_bits_way = _RAND_13[0:0]; + i0_predict_p_x_bits_pja = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - predpipe_x = _RAND_14[20:0]; + i0_predict_p_x_bits_way = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; - predpipe_r = _RAND_15[20:0]; + predpipe_x = _RAND_15[20:0]; _RAND_16 = {1{`RANDOM}}; - ghr_x = _RAND_16[7:0]; + predpipe_r = _RAND_16[20:0]; _RAND_17 = {1{`RANDOM}}; - i0_pred_correct_upper_x = _RAND_17[0:0]; + ghr_x = _RAND_17[7:0]; _RAND_18 = {1{`RANDOM}}; - i0_flush_upper_x = _RAND_18[0:0]; + i0_pred_correct_upper_x = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - i0_taken_x = _RAND_19[0:0]; + i0_flush_upper_x = _RAND_19[0:0]; _RAND_20 = {1{`RANDOM}}; - i0_valid_x = _RAND_20[0:0]; + i0_taken_x = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - i0_pp_r_valid = _RAND_21[0:0]; + i0_valid_x = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - i0_pp_r_bits_misp = _RAND_22[0:0]; + i0_pp_r_valid = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - i0_pp_r_bits_ataken = _RAND_23[0:0]; + i0_pp_r_bits_misp = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - i0_pp_r_bits_pc4 = _RAND_24[0:0]; + i0_pp_r_bits_ataken = _RAND_24[0:0]; _RAND_25 = {1{`RANDOM}}; - i0_pp_r_bits_hist = _RAND_25[1:0]; + i0_pp_r_bits_boffset = _RAND_25[0:0]; _RAND_26 = {1{`RANDOM}}; - i0_pp_r_bits_br_error = _RAND_26[0:0]; + i0_pp_r_bits_pc4 = _RAND_26[0:0]; _RAND_27 = {1{`RANDOM}}; - i0_pp_r_bits_br_start_error = _RAND_27[0:0]; + i0_pp_r_bits_hist = _RAND_27[1:0]; _RAND_28 = {1{`RANDOM}}; - i0_pp_r_bits_way = _RAND_28[0:0]; + i0_pp_r_bits_br_error = _RAND_28[0:0]; _RAND_29 = {1{`RANDOM}}; - pred_temp1 = _RAND_29[5:0]; + i0_pp_r_bits_br_start_error = _RAND_29[0:0]; _RAND_30 = {1{`RANDOM}}; - i0_pred_correct_upper_r = _RAND_30[0:0]; + i0_pp_r_bits_way = _RAND_30[0:0]; _RAND_31 = {1{`RANDOM}}; - i0_flush_path_upper_r = _RAND_31[30:0]; + pred_temp1 = _RAND_31[5:0]; _RAND_32 = {1{`RANDOM}}; - pred_temp2 = _RAND_32[24:0]; + i0_pred_correct_upper_r = _RAND_32[0:0]; _RAND_33 = {1{`RANDOM}}; - ghr_d = _RAND_33[7:0]; + i0_flush_path_upper_r = _RAND_33[30:0]; _RAND_34 = {1{`RANDOM}}; - mul_valid_x = _RAND_34[0:0]; + pred_temp2 = _RAND_34[24:0]; _RAND_35 = {1{`RANDOM}}; - flush_lower_ff = _RAND_35[0:0]; + ghr_d = _RAND_35[7:0]; + _RAND_36 = {1{`RANDOM}}; + mul_valid_x = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + flush_lower_ff = _RAND_37[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin i0_flush_path_x = 31'h0; @@ -62293,6 +62448,9 @@ initial begin if (reset) begin i0_predict_p_x_bits_ataken = 1'h0; end + if (reset) begin + i0_predict_p_x_bits_boffset = 1'h0; + end if (reset) begin i0_predict_p_x_bits_pc4 = 1'h0; end @@ -62350,6 +62508,9 @@ initial begin if (reset) begin i0_pp_r_bits_ataken = 1'h0; end + if (reset) begin + i0_pp_r_bits_boffset = 1'h0; + end if (reset) begin i0_pp_r_bits_pc4 = 1'h0; end @@ -62429,6 +62590,13 @@ end // initial i0_predict_p_x_bits_ataken <= i_alu_io_predict_p_out_bits_ataken; end end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_bits_boffset <= 1'h0; + end else begin + i0_predict_p_x_bits_boffset <= i_alu_io_predict_p_out_bits_boffset; + end + end always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin i0_predict_p_x_bits_pc4 <= 1'h0; @@ -62562,6 +62730,13 @@ end // initial i0_pp_r_bits_ataken <= i0_predict_p_x_bits_ataken; end end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_bits_boffset <= 1'h0; + end else begin + i0_pp_r_bits_boffset <= i0_predict_p_x_bits_boffset; + end + end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin i0_pp_r_bits_pc4 <= 1'h0; @@ -80220,6 +80395,7 @@ module el2_swerv( wire ifu_io_iccm_dma_sb_error; // @[el2_swerv.scala 321:19] wire [31:0] ifu_io_ifu_i0_instr; // @[el2_swerv.scala 321:19] wire [30:0] ifu_io_ifu_i0_pc; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_i0_pc4; // @[el2_swerv.scala 321:19] wire ifu_io_ifu_miss_state_idle; // @[el2_swerv.scala 321:19] wire ifu_io_i0_brp_valid; // @[el2_swerv.scala 321:19] wire [11:0] ifu_io_i0_brp_bits_toffset; // @[el2_swerv.scala 321:19] @@ -80234,6 +80410,7 @@ module el2_swerv( wire [4:0] ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 321:19] wire ifu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 321:19] wire ifu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 321:19] + wire ifu_io_exu_mp_pkt_bits_boffset; // @[el2_swerv.scala 321:19] wire ifu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 321:19] wire [1:0] ifu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 321:19] wire [11:0] ifu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 321:19] @@ -80271,16 +80448,16 @@ module el2_swerv( wire dec_io_dec_extint_stall; // @[el2_swerv.scala 322:19] wire dec_io_dec_i0_decode_d; // @[el2_swerv.scala 322:19] wire dec_io_dec_pause_state_cg; // @[el2_swerv.scala 322:19] - wire [31:0] dec_io_rst_vec; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_rst_vec; // @[el2_swerv.scala 322:19] wire dec_io_nmi_int; // @[el2_swerv.scala 322:19] - wire [31:0] dec_io_nmi_vec; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_nmi_vec; // @[el2_swerv.scala 322:19] wire dec_io_i_cpu_halt_req; // @[el2_swerv.scala 322:19] wire dec_io_i_cpu_run_req; // @[el2_swerv.scala 322:19] wire dec_io_o_cpu_halt_status; // @[el2_swerv.scala 322:19] wire dec_io_o_cpu_halt_ack; // @[el2_swerv.scala 322:19] wire dec_io_o_cpu_run_ack; // @[el2_swerv.scala 322:19] wire dec_io_o_debug_mode_status; // @[el2_swerv.scala 322:19] - wire [31:0] dec_io_core_id; // @[el2_swerv.scala 322:19] + wire [27:0] dec_io_core_id; // @[el2_swerv.scala 322:19] wire dec_io_mpc_debug_halt_req; // @[el2_swerv.scala 322:19] wire dec_io_mpc_debug_run_req; // @[el2_swerv.scala 322:19] wire dec_io_mpc_reset_run_req; // @[el2_swerv.scala 322:19] @@ -80308,7 +80485,7 @@ module el2_swerv( wire dec_io_dma_pmu_dccm_write; // @[el2_swerv.scala 322:19] wire dec_io_dma_pmu_any_read; // @[el2_swerv.scala 322:19] wire dec_io_dma_pmu_any_write; // @[el2_swerv.scala 322:19] - wire [31:0] dec_io_lsu_fir_addr; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_lsu_fir_addr; // @[el2_swerv.scala 322:19] wire [1:0] dec_io_lsu_fir_error; // @[el2_swerv.scala 322:19] wire dec_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 322:19] wire dec_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 322:19] @@ -80338,7 +80515,7 @@ module el2_swerv( wire [30:0] dec_io_i0_brp_bits_prett; // @[el2_swerv.scala 322:19] wire dec_io_i0_brp_bits_way; // @[el2_swerv.scala 322:19] wire dec_io_i0_brp_bits_ret; // @[el2_swerv.scala 322:19] - wire [8:0] dec_io_ifu_i0_bp_index; // @[el2_swerv.scala 322:19] + wire [7:0] dec_io_ifu_i0_bp_index; // @[el2_swerv.scala 322:19] wire [7:0] dec_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 322:19] wire [4:0] dec_io_ifu_i0_bp_btag; // @[el2_swerv.scala 322:19] wire dec_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 322:19] @@ -80362,11 +80539,13 @@ module el2_swerv( wire dec_io_dma_iccm_stall_any; // @[el2_swerv.scala 322:19] wire dec_io_iccm_dma_sb_error; // @[el2_swerv.scala 322:19] wire dec_io_exu_flush_final; // @[el2_swerv.scala 322:19] - wire [31:0] dec_io_exu_npc_r; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_exu_npc_r; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_exu_i0_result_x; // @[el2_swerv.scala 322:19] wire dec_io_ifu_i0_valid; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_ifu_i0_instr; // @[el2_swerv.scala 322:19] - wire [31:0] dec_io_ifu_i0_pc; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_ifu_i0_pc; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_i0_pc4; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_exu_i0_pc_x; // @[el2_swerv.scala 322:19] wire dec_io_mexintpend; // @[el2_swerv.scala 322:19] wire dec_io_timer_int; // @[el2_swerv.scala 322:19] wire dec_io_soft_int; // @[el2_swerv.scala 322:19] @@ -80375,7 +80554,7 @@ module el2_swerv( wire dec_io_mhwakeup; // @[el2_swerv.scala 322:19] wire [3:0] dec_io_dec_tlu_meicurpl; // @[el2_swerv.scala 322:19] wire [3:0] dec_io_dec_tlu_meipt; // @[el2_swerv.scala 322:19] - wire [69:0] dec_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 322:19] + wire [70:0] dec_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 322:19] wire dec_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 322:19] wire [70:0] dec_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_swerv.scala 322:19] wire [16:0] dec_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_swerv.scala 322:19] @@ -80391,7 +80570,7 @@ module el2_swerv( wire dec_io_dec_tlu_mpc_halted_only; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_flush_leak_one_r; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_flush_err_r; // @[el2_swerv.scala 322:19] - wire [31:0] dec_io_dec_tlu_meihap; // @[el2_swerv.scala 322:19] + wire [29:0] dec_io_dec_tlu_meihap; // @[el2_swerv.scala 322:19] wire dec_io_dec_debug_wdata_rs1_d; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_dec_dbg_rddata; // @[el2_swerv.scala 322:19] wire dec_io_dec_dbg_cmd_done; // @[el2_swerv.scala 322:19] @@ -80429,7 +80608,7 @@ module el2_swerv( wire [31:0] dec_io_gpr_i0_rs1_d; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_gpr_i0_rs2_d; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_dec_i0_immed_d; // @[el2_swerv.scala 322:19] - wire [12:0] dec_io_dec_i0_br_immed_d; // @[el2_swerv.scala 322:19] + wire [11:0] dec_io_dec_i0_br_immed_d; // @[el2_swerv.scala 322:19] wire dec_io_i0_ap_land; // @[el2_swerv.scala 322:19] wire dec_io_i0_ap_lor; // @[el2_swerv.scala 322:19] wire dec_io_i0_ap_lxor; // @[el2_swerv.scala 322:19] @@ -80450,6 +80629,8 @@ module el2_swerv( wire dec_io_i0_ap_csr_write; // @[el2_swerv.scala 322:19] wire dec_io_i0_ap_csr_imm; // @[el2_swerv.scala 322:19] wire dec_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_select_pc_d; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_dec_i0_pc_d; // @[el2_swerv.scala 322:19] wire [1:0] dec_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 322:19] wire [1:0] dec_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 322:19] @@ -80475,10 +80656,10 @@ module el2_swerv( wire [11:0] dec_io_dec_lsu_offset_d; // @[el2_swerv.scala 322:19] wire dec_io_dec_csr_ren_d; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 322:19] - wire [31:0] dec_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_i0_kill_writeb_r; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_fence_i_r; // @[el2_swerv.scala 322:19] - wire [31:0] dec_io_pred_correct_npc_x; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_pred_correct_npc_x; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 322:19] wire [1:0] dec_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_swerv.scala 322:19] @@ -80501,7 +80682,7 @@ module el2_swerv( wire dec_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 322:19] wire dec_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 322:19] wire [7:0] dec_io_i0_predict_fghr_d; // @[el2_swerv.scala 322:19] - wire [8:0] dec_io_i0_predict_index_d; // @[el2_swerv.scala 322:19] + wire [7:0] dec_io_i0_predict_index_d; // @[el2_swerv.scala 322:19] wire [4:0] dec_io_i0_predict_btag_d; // @[el2_swerv.scala 322:19] wire dec_io_dec_lsu_valid_raw_d; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 322:19] @@ -80626,6 +80807,8 @@ module el2_swerv( wire [31:0] exu_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 324:19] wire [11:0] exu_io_dec_i0_br_immed_d; // @[el2_swerv.scala 324:19] wire exu_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_select_pc_d; // @[el2_swerv.scala 324:19] + wire [30:0] exu_io_dec_i0_pc_d; // @[el2_swerv.scala 324:19] wire [1:0] exu_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 324:19] wire [1:0] exu_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 324:19] wire exu_io_dec_csr_ren_d; // @[el2_swerv.scala 324:19] @@ -80647,6 +80830,7 @@ module el2_swerv( wire exu_io_exu_flush_final; // @[el2_swerv.scala 324:19] wire [30:0] exu_io_exu_flush_path_final; // @[el2_swerv.scala 324:19] wire [31:0] exu_io_exu_i0_result_x; // @[el2_swerv.scala 324:19] + wire [30:0] exu_io_exu_i0_pc_x; // @[el2_swerv.scala 324:19] wire [31:0] exu_io_exu_csr_rs1_x; // @[el2_swerv.scala 324:19] wire [30:0] exu_io_exu_npc_r; // @[el2_swerv.scala 324:19] wire [1:0] exu_io_exu_i0_br_hist_r; // @[el2_swerv.scala 324:19] @@ -80660,6 +80844,7 @@ module el2_swerv( wire exu_io_exu_i0_br_way_r; // @[el2_swerv.scala 324:19] wire exu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 324:19] wire exu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 324:19] + wire exu_io_exu_mp_pkt_bits_boffset; // @[el2_swerv.scala 324:19] wire exu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 324:19] wire [1:0] exu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 324:19] wire [11:0] exu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 324:19] @@ -80989,6 +81174,7 @@ module el2_swerv( .io_iccm_dma_sb_error(ifu_io_iccm_dma_sb_error), .io_ifu_i0_instr(ifu_io_ifu_i0_instr), .io_ifu_i0_pc(ifu_io_ifu_i0_pc), + .io_ifu_i0_pc4(ifu_io_ifu_i0_pc4), .io_ifu_miss_state_idle(ifu_io_ifu_miss_state_idle), .io_i0_brp_valid(ifu_io_i0_brp_valid), .io_i0_brp_bits_toffset(ifu_io_i0_brp_bits_toffset), @@ -81003,6 +81189,7 @@ module el2_swerv( .io_ifu_i0_bp_btag(ifu_io_ifu_i0_bp_btag), .io_exu_mp_pkt_bits_misp(ifu_io_exu_mp_pkt_bits_misp), .io_exu_mp_pkt_bits_ataken(ifu_io_exu_mp_pkt_bits_ataken), + .io_exu_mp_pkt_bits_boffset(ifu_io_exu_mp_pkt_bits_boffset), .io_exu_mp_pkt_bits_pc4(ifu_io_exu_mp_pkt_bits_pc4), .io_exu_mp_pkt_bits_hist(ifu_io_exu_mp_pkt_bits_hist), .io_exu_mp_pkt_bits_toffset(ifu_io_exu_mp_pkt_bits_toffset), @@ -81138,6 +81325,8 @@ module el2_swerv( .io_ifu_i0_valid(dec_io_ifu_i0_valid), .io_ifu_i0_instr(dec_io_ifu_i0_instr), .io_ifu_i0_pc(dec_io_ifu_i0_pc), + .io_ifu_i0_pc4(dec_io_ifu_i0_pc4), + .io_exu_i0_pc_x(dec_io_exu_i0_pc_x), .io_mexintpend(dec_io_mexintpend), .io_timer_int(dec_io_timer_int), .io_soft_int(dec_io_soft_int), @@ -81221,6 +81410,8 @@ module el2_swerv( .io_i0_ap_csr_write(dec_io_i0_ap_csr_write), .io_i0_ap_csr_imm(dec_io_i0_ap_csr_imm), .io_dec_i0_alu_decode_d(dec_io_dec_i0_alu_decode_d), + .io_dec_i0_select_pc_d(dec_io_dec_i0_select_pc_d), + .io_dec_i0_pc_d(dec_io_dec_i0_pc_d), .io_dec_i0_rs1_bypass_en_d(dec_io_dec_i0_rs1_bypass_en_d), .io_dec_i0_rs2_bypass_en_d(dec_io_dec_i0_rs2_bypass_en_d), .io_dec_i0_rs1_bypass_data_d(dec_io_dec_i0_rs1_bypass_data_d), @@ -81401,6 +81592,8 @@ module el2_swerv( .io_dec_i0_rs2_bypass_data_d(exu_io_dec_i0_rs2_bypass_data_d), .io_dec_i0_br_immed_d(exu_io_dec_i0_br_immed_d), .io_dec_i0_alu_decode_d(exu_io_dec_i0_alu_decode_d), + .io_dec_i0_select_pc_d(exu_io_dec_i0_select_pc_d), + .io_dec_i0_pc_d(exu_io_dec_i0_pc_d), .io_dec_i0_rs1_bypass_en_d(exu_io_dec_i0_rs1_bypass_en_d), .io_dec_i0_rs2_bypass_en_d(exu_io_dec_i0_rs2_bypass_en_d), .io_dec_csr_ren_d(exu_io_dec_csr_ren_d), @@ -81422,6 +81615,7 @@ module el2_swerv( .io_exu_flush_final(exu_io_exu_flush_final), .io_exu_flush_path_final(exu_io_exu_flush_path_final), .io_exu_i0_result_x(exu_io_exu_i0_result_x), + .io_exu_i0_pc_x(exu_io_exu_i0_pc_x), .io_exu_csr_rs1_x(exu_io_exu_csr_rs1_x), .io_exu_npc_r(exu_io_exu_npc_r), .io_exu_i0_br_hist_r(exu_io_exu_i0_br_hist_r), @@ -81435,6 +81629,7 @@ module el2_swerv( .io_exu_i0_br_way_r(exu_io_exu_i0_br_way_r), .io_exu_mp_pkt_bits_misp(exu_io_exu_mp_pkt_bits_misp), .io_exu_mp_pkt_bits_ataken(exu_io_exu_mp_pkt_bits_ataken), + .io_exu_mp_pkt_bits_boffset(exu_io_exu_mp_pkt_bits_boffset), .io_exu_mp_pkt_bits_pc4(exu_io_exu_mp_pkt_bits_pc4), .io_exu_mp_pkt_bits_hist(exu_io_exu_mp_pkt_bits_hist), .io_exu_mp_pkt_bits_toffset(exu_io_exu_mp_pkt_bits_toffset), @@ -81817,6 +82012,7 @@ module el2_swerv( assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[el2_swerv.scala 348:27] assign ifu_io_exu_mp_pkt_bits_misp = exu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 382:21] assign ifu_io_exu_mp_pkt_bits_ataken = exu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_pkt_bits_boffset = exu_io_exu_mp_pkt_bits_boffset; // @[el2_swerv.scala 382:21] assign ifu_io_exu_mp_pkt_bits_pc4 = exu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 382:21] assign ifu_io_exu_mp_pkt_bits_hist = exu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 382:21] assign ifu_io_exu_mp_pkt_bits_toffset = exu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 382:21] @@ -81847,12 +82043,12 @@ module el2_swerv( assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 395:19] assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[el2_swerv.scala 396:21] assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[el2_swerv.scala 397:32] - assign dec_io_rst_vec = {{1'd0}, io_rst_vec}; // @[el2_swerv.scala 398:18] + assign dec_io_rst_vec = io_rst_vec; // @[el2_swerv.scala 398:18] assign dec_io_nmi_int = io_nmi_int; // @[el2_swerv.scala 399:18] - assign dec_io_nmi_vec = {{1'd0}, io_nmi_vec}; // @[el2_swerv.scala 400:18] + assign dec_io_nmi_vec = io_nmi_vec; // @[el2_swerv.scala 400:18] assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_swerv.scala 401:25] assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_swerv.scala 402:24] - assign dec_io_core_id = {{4'd0}, io_core_id}; // @[el2_swerv.scala 403:18] + assign dec_io_core_id = io_core_id; // @[el2_swerv.scala 403:18] assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_swerv.scala 404:29] assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_swerv.scala 405:28] assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_swerv.scala 406:28] @@ -81877,7 +82073,7 @@ module el2_swerv( assign dec_io_dma_pmu_dccm_write = dma_ctrl_io_dma_pmu_dccm_write; // @[el2_swerv.scala 426:29] assign dec_io_dma_pmu_any_read = dma_ctrl_io_dma_pmu_any_read; // @[el2_swerv.scala 427:27] assign dec_io_dma_pmu_any_write = dma_ctrl_io_dma_pmu_any_write; // @[el2_swerv.scala 428:28] - assign dec_io_lsu_fir_addr = {{1'd0}, lsu_io_lsu_fir_addr}; // @[el2_swerv.scala 429:23] + assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[el2_swerv.scala 429:23] assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[el2_swerv.scala 430:24] assign dec_io_ifu_pmu_instr_aligned = ifu_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 431:32] assign dec_io_ifu_pmu_fetch_stall = ifu_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 432:30] @@ -81907,7 +82103,7 @@ module el2_swerv( assign dec_io_i0_brp_bits_prett = ifu_io_i0_brp_bits_prett; // @[el2_swerv.scala 451:17] assign dec_io_i0_brp_bits_way = ifu_io_i0_brp_bits_way; // @[el2_swerv.scala 451:17] assign dec_io_i0_brp_bits_ret = ifu_io_i0_brp_bits_ret; // @[el2_swerv.scala 451:17] - assign dec_io_ifu_i0_bp_index = {{1'd0}, ifu_io_ifu_i0_bp_index}; // @[el2_swerv.scala 452:26] + assign dec_io_ifu_i0_bp_index = ifu_io_ifu_i0_bp_index; // @[el2_swerv.scala 452:26] assign dec_io_ifu_i0_bp_fghr = ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 453:25] assign dec_io_ifu_i0_bp_btag = ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 454:25] assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 455:26] @@ -81931,18 +82127,20 @@ module el2_swerv( assign dec_io_dma_iccm_stall_any = dma_ctrl_io_dma_iccm_stall_any; // @[el2_swerv.scala 468:29] assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[el2_swerv.scala 469:28] assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[el2_swerv.scala 470:26] - assign dec_io_exu_npc_r = {{1'd0}, exu_io_exu_npc_r}; // @[el2_swerv.scala 471:20] + assign dec_io_exu_npc_r = exu_io_exu_npc_r; // @[el2_swerv.scala 471:20] assign dec_io_exu_i0_result_x = exu_io_exu_i0_result_x; // @[el2_swerv.scala 472:26] assign dec_io_ifu_i0_valid = ifu_io_ifu_i0_valid; // @[el2_swerv.scala 473:23] assign dec_io_ifu_i0_instr = ifu_io_ifu_i0_instr; // @[el2_swerv.scala 474:23] - assign dec_io_ifu_i0_pc = {{1'd0}, ifu_io_ifu_i0_pc}; // @[el2_swerv.scala 475:20] + assign dec_io_ifu_i0_pc = ifu_io_ifu_i0_pc; // @[el2_swerv.scala 475:20] + assign dec_io_ifu_i0_pc4 = ifu_io_ifu_i0_pc4; // @[el2_swerv.scala 476:21] + assign dec_io_exu_i0_pc_x = exu_io_exu_i0_pc_x; // @[el2_swerv.scala 477:22] assign dec_io_mexintpend = pic_ctrl_inst_io_mexintpend; // @[el2_swerv.scala 478:21] assign dec_io_timer_int = io_timer_int; // @[el2_swerv.scala 496:20] assign dec_io_soft_int = io_soft_int; // @[el2_swerv.scala 479:19] assign dec_io_pic_claimid = pic_ctrl_inst_io_claimid; // @[el2_swerv.scala 480:22] assign dec_io_pic_pl = pic_ctrl_inst_io_pl; // @[el2_swerv.scala 481:17] assign dec_io_mhwakeup = pic_ctrl_inst_io_mhwakeup; // @[el2_swerv.scala 482:19] - assign dec_io_ifu_ic_debug_rd_data = ifu_io_ifu_ic_debug_rd_data[69:0]; // @[el2_swerv.scala 483:31] + assign dec_io_ifu_ic_debug_rd_data = ifu_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 483:31] assign dec_io_ifu_ic_debug_rd_data_valid = ifu_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 484:37] assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[el2_swerv.scala 485:23] assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[el2_swerv.scala 486:25] @@ -82020,7 +82218,7 @@ module el2_swerv( assign exu_io_dec_i0_predict_p_d_bits_pja = dec_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 507:29] assign exu_io_dec_i0_predict_p_d_bits_way = dec_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 507:29] assign exu_io_i0_predict_fghr_d = dec_io_i0_predict_fghr_d; // @[el2_swerv.scala 508:28] - assign exu_io_i0_predict_index_d = dec_io_i0_predict_index_d[7:0]; // @[el2_swerv.scala 509:29] + assign exu_io_i0_predict_index_d = dec_io_i0_predict_index_d; // @[el2_swerv.scala 509:29] assign exu_io_i0_predict_btag_d = dec_io_i0_predict_btag_d; // @[el2_swerv.scala 510:28] assign exu_io_dec_i0_rs1_en_d = dec_io_dec_i0_rs1_en_d; // @[el2_swerv.scala 511:26] assign exu_io_dec_i0_rs2_en_d = dec_io_dec_i0_rs2_en_d; // @[el2_swerv.scala 512:26] @@ -82029,8 +82227,10 @@ module el2_swerv( assign exu_io_dec_i0_immed_d = dec_io_dec_i0_immed_d; // @[el2_swerv.scala 515:25] assign exu_io_dec_i0_rs1_bypass_data_d = dec_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 516:35] assign exu_io_dec_i0_rs2_bypass_data_d = dec_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 517:35] - assign exu_io_dec_i0_br_immed_d = dec_io_dec_i0_br_immed_d[11:0]; // @[el2_swerv.scala 518:28] + assign exu_io_dec_i0_br_immed_d = dec_io_dec_i0_br_immed_d; // @[el2_swerv.scala 518:28] assign exu_io_dec_i0_alu_decode_d = dec_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 519:30] + assign exu_io_dec_i0_select_pc_d = dec_io_dec_i0_select_pc_d; // @[el2_swerv.scala 520:29] + assign exu_io_dec_i0_pc_d = dec_io_dec_i0_pc_d; // @[el2_swerv.scala 521:22] assign exu_io_dec_i0_rs1_bypass_en_d = dec_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 522:33] assign exu_io_dec_i0_rs2_bypass_en_d = dec_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 523:33] assign exu_io_dec_csr_ren_d = dec_io_dec_csr_ren_d; // @[el2_swerv.scala 524:24] @@ -82042,11 +82242,11 @@ module el2_swerv( assign exu_io_div_p_bits_unsign = dec_io_div_p_bits_unsign; // @[el2_swerv.scala 526:16] assign exu_io_div_p_bits_rem = dec_io_div_p_bits_rem; // @[el2_swerv.scala 526:16] assign exu_io_dec_div_cancel = dec_io_dec_div_cancel; // @[el2_swerv.scala 527:25] - assign exu_io_pred_correct_npc_x = dec_io_pred_correct_npc_x[30:0]; // @[el2_swerv.scala 528:29] + assign exu_io_pred_correct_npc_x = dec_io_pred_correct_npc_x; // @[el2_swerv.scala 528:29] assign exu_io_dec_tlu_flush_lower_r = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 529:32] - assign exu_io_dec_tlu_flush_path_r = dec_io_dec_tlu_flush_path_r[30:0]; // @[el2_swerv.scala 530:31] + assign exu_io_dec_tlu_flush_path_r = dec_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 530:31] assign exu_io_dec_extint_stall = dec_io_dec_extint_stall; // @[el2_swerv.scala 531:27] - assign exu_io_dec_tlu_meihap = dec_io_dec_tlu_meihap[29:0]; // @[el2_swerv.scala 532:25] + assign exu_io_dec_tlu_meihap = dec_io_dec_tlu_meihap; // @[el2_swerv.scala 532:25] assign lsu_clock = clock; assign lsu_reset = io_core_rst_l; // @[el2_swerv.scala 536:13] assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[el2_swerv.scala 537:23] diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index 4ec29fe7..bde2aec4 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1 +1,3 @@ -/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v \ No newline at end of file +/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v +/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv +/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv \ No newline at end of file diff --git a/src/main/scala/SweRV_Wrapper.scala b/src/main/scala/el2_swerv_wrapper.scala similarity index 100% rename from src/main/scala/SweRV_Wrapper.scala rename to src/main/scala/el2_swerv_wrapper.scala diff --git a/src/main/scala/lib/el2_lib.scala b/src/main/scala/lib/el2_lib.scala index 2947b278..5fee1753 100644 --- a/src/main/scala/lib/el2_lib.scala +++ b/src/main/scala/lib/el2_lib.scala @@ -1,7 +1,7 @@ package lib import chisel3._ import chisel3.util._ -import el2_mem.waleed.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int} +import el2_mem.quasar.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int} trait param { val BHT_ADDR_HI = 9 val BHT_ADDR_LO = 2 diff --git a/target/scala-2.12/classes/SWERV_Wrp$.class b/target/scala-2.12/classes/SWERV_Wrp$.class index 7daf8efc2ea1ed4c8ba49609ff488d8e94e5e480..8b271e1afac806ec1848072b308c0641f1734a25 100644 GIT binary patch delta 23 ecmbO%H(hRmBae7$j!}GZd1_HveECMtQ+xnmrU;w> delta 19 acmbO(H(73iBZqKsd1_EteE3G+Q+xnGIR>@> diff --git a/target/scala-2.12/classes/SWERV_Wrp$delayedInit$body.class b/target/scala-2.12/classes/SWERV_Wrp$delayedInit$body.class index c2e96f74f4fac3f0a86362b059b9e0f210875ca0..a9e716602e09b9fed026c2db64e56a675af99616 100644 GIT binary patch delta 23 ecmcb_dX05LAdh%zj!}GZd1_HveEG)6N+tkk0tl-B delta 19 acmcb{dWm&HAct^pd1_EteE7!LN+tkCB?iR+ diff --git a/target/scala-2.12/classes/SWERV_Wrp.class b/target/scala-2.12/classes/SWERV_Wrp.class index 8b0b9c1d1e26c43cc9857f45ee78375b21b0a4bf..935632a0bb71785761a2e2f76509d6f07c748f7b 100644 GIT binary patch delta 23 ecmeBWo5(i7kViZ<$0)wIJhiASzI>zQ6(#^$W(Yn2 delta 19 acmbQp*2^}*kV81QJT)jRK76C?6(#^XDF#>o diff --git a/target/scala-2.12/classes/el2_swerv_wrapper$$anon$1.class b/target/scala-2.12/classes/el2_swerv_wrapper$$anon$1.class index cf5c149c845824938847a9b17d1f98fe6bb13b5b..94343a6e6e27e3991cf31a18fb0899cda6e7d291 100644 GIT binary patch delta 25 gcmZpE&e;B(ae_UMcxsMOd~tbdQCWQXMt7TH0D^7_;{X5v delta 21 ccmZpF&e;5%ae_UEaBz8QP*{BUMsJ&909-u>{Qv*} diff --git a/target/scala-2.12/classes/el2_swerv_wrapper.class b/target/scala-2.12/classes/el2_swerv_wrapper.class index eda21eab1079923dc7fea5e06b26d700bfe6955a..b58e85fb2add40d5bf251659beeb00f32504d705 100644 GIT binary patch delta 37 scmeC`5a{a=m{7(eo|