diff --git a/dbg.fir b/dbg.fir index 6a3a7890..c9834437 100644 --- a/dbg.fir +++ b/dbg.fir @@ -301,448 +301,431 @@ circuit dbg : node _T_27 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 105:61] node _T_28 = and(sbcs_wren, _T_27) @[dbg.scala 105:43] node sbcs_sbbusyerror_din = not(_T_28) @[dbg.scala 105:31] - node _T_29 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 106:54] - node _T_30 = asAsyncReset(_T_29) @[dbg.scala 106:81] - reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_30, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_29 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 106:80] + reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_29, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sbbusyerror_wren : @[Reg.scala 28:19] temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_31 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 110:54] - node _T_32 = asAsyncReset(_T_31) @[dbg.scala 110:81] - reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_32, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_30 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 110:80] + reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_30, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sbbusy_wren : @[Reg.scala 28:19] temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_33 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 114:54] - node _T_34 = asAsyncReset(_T_33) @[dbg.scala 114:81] - node _T_35 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 115:31] - reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_34, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_31 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 114:80] + node _T_32 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 115:31] + reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_31, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_wren : @[Reg.scala 28:19] - temp_sbcs_20 <= _T_35 @[Reg.scala 28:23] + temp_sbcs_20 <= _T_32 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_36 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 118:57] - node _T_37 = asAsyncReset(_T_36) @[dbg.scala 118:84] - node _T_38 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 119:31] - reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_37, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_33 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 118:83] + node _T_34 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 119:31] + reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_33, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_wren : @[Reg.scala 28:19] - temp_sbcs_19_15 <= _T_38 @[Reg.scala 28:23] + temp_sbcs_19_15 <= _T_34 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_39 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 122:57] - node _T_40 = asAsyncReset(_T_39) @[dbg.scala 122:84] - node _T_41 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 123:31] - reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_40, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_35 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 122:57] + node _T_36 = asAsyncReset(_T_35) @[dbg.scala 122:84] + node _T_37 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 123:31] + reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_36, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sberror_wren : @[Reg.scala 28:19] - temp_sbcs_14_12 <= _T_41 @[Reg.scala 28:23] + temp_sbcs_14_12 <= _T_37 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_42 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58] - node _T_43 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58] - node _T_44 = cat(_T_43, _T_42) @[Cat.scala 29:58] - node _T_45 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58] - node _T_46 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58] - node _T_47 = cat(_T_46, temp_sbcs_22) @[Cat.scala 29:58] - node _T_48 = cat(_T_47, _T_45) @[Cat.scala 29:58] - node _T_49 = cat(_T_48, _T_44) @[Cat.scala 29:58] - sbcs_reg <= _T_49 @[dbg.scala 125:12] - node _T_50 = bits(sbcs_reg, 19, 17) @[dbg.scala 127:33] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[dbg.scala 127:42] - node _T_52 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 127:72] - node _T_53 = and(_T_51, _T_52) @[dbg.scala 127:56] - node _T_54 = bits(sbcs_reg, 19, 17) @[dbg.scala 128:14] - node _T_55 = eq(_T_54, UInt<2>("h02")) @[dbg.scala 128:23] - node _T_56 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 128:53] - node _T_57 = orr(_T_56) @[dbg.scala 128:60] - node _T_58 = and(_T_55, _T_57) @[dbg.scala 128:37] - node _T_59 = or(_T_53, _T_58) @[dbg.scala 127:76] - node _T_60 = bits(sbcs_reg, 19, 17) @[dbg.scala 129:14] - node _T_61 = eq(_T_60, UInt<2>("h03")) @[dbg.scala 129:23] - node _T_62 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 129:53] - node _T_63 = orr(_T_62) @[dbg.scala 129:60] - node _T_64 = and(_T_61, _T_63) @[dbg.scala 129:37] - node sbcs_unaligned = or(_T_59, _T_64) @[dbg.scala 128:64] + node _T_38 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58] + node _T_39 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58] + node _T_40 = cat(_T_39, _T_38) @[Cat.scala 29:58] + node _T_41 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58] + node _T_42 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, temp_sbcs_22) @[Cat.scala 29:58] + node _T_44 = cat(_T_43, _T_41) @[Cat.scala 29:58] + node _T_45 = cat(_T_44, _T_40) @[Cat.scala 29:58] + sbcs_reg <= _T_45 @[dbg.scala 125:12] + node _T_46 = bits(sbcs_reg, 19, 17) @[dbg.scala 127:33] + node _T_47 = eq(_T_46, UInt<3>("h01")) @[dbg.scala 127:42] + node _T_48 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 127:77] + node _T_49 = and(_T_47, _T_48) @[dbg.scala 127:61] + node _T_50 = bits(sbcs_reg, 19, 17) @[dbg.scala 128:14] + node _T_51 = eq(_T_50, UInt<3>("h02")) @[dbg.scala 128:23] + node _T_52 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 128:58] + node _T_53 = orr(_T_52) @[dbg.scala 128:65] + node _T_54 = and(_T_51, _T_53) @[dbg.scala 128:42] + node _T_55 = or(_T_49, _T_54) @[dbg.scala 127:81] + node _T_56 = bits(sbcs_reg, 19, 17) @[dbg.scala 129:14] + node _T_57 = eq(_T_56, UInt<3>("h03")) @[dbg.scala 129:23] + node _T_58 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 129:58] + node _T_59 = orr(_T_58) @[dbg.scala 129:65] + node _T_60 = and(_T_57, _T_59) @[dbg.scala 129:42] + node sbcs_unaligned = or(_T_55, _T_60) @[dbg.scala 128:69] node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 131:35] - node _T_65 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:42] - node _T_66 = eq(_T_65, UInt<1>("h00")) @[dbg.scala 132:51] - node _T_67 = bits(_T_66, 0, 0) @[Bitwise.scala 72:15] - node _T_68 = mux(_T_67, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_69 = and(_T_68, UInt<1>("h01")) @[dbg.scala 132:64] - node _T_70 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:95] - node _T_71 = eq(_T_70, UInt<1>("h01")) @[dbg.scala 132:104] - node _T_72 = bits(_T_71, 0, 0) @[Bitwise.scala 72:15] - node _T_73 = mux(_T_72, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_74 = and(_T_73, UInt<2>("h02")) @[dbg.scala 132:117] - node _T_75 = or(_T_69, _T_74) @[dbg.scala 132:76] - node _T_76 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:22] - node _T_77 = eq(_T_76, UInt<2>("h02")) @[dbg.scala 133:31] - node _T_78 = bits(_T_77, 0, 0) @[Bitwise.scala 72:15] - node _T_79 = mux(_T_78, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_80 = and(_T_79, UInt<3>("h04")) @[dbg.scala 133:44] - node _T_81 = or(_T_75, _T_80) @[dbg.scala 132:129] - node _T_82 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:75] - node _T_83 = eq(_T_82, UInt<2>("h03")) @[dbg.scala 133:84] - node _T_84 = bits(_T_83, 0, 0) @[Bitwise.scala 72:15] - node _T_85 = mux(_T_84, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_86 = and(_T_85, UInt<4>("h08")) @[dbg.scala 133:97] - node sbaddress0_incr = or(_T_81, _T_86) @[dbg.scala 133:56] - node _T_87 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 135:41] - node _T_88 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 135:79] - node sbdata0_reg_wren0 = and(_T_87, _T_88) @[dbg.scala 135:60] - node _T_89 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 136:37] - node _T_90 = and(_T_89, sb_state_en) @[dbg.scala 136:60] - node _T_91 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 136:76] - node sbdata0_reg_wren1 = and(_T_90, _T_91) @[dbg.scala 136:74] + node _T_61 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:42] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[dbg.scala 132:51] + node _T_63 = bits(_T_62, 0, 0) @[Bitwise.scala 72:15] + node _T_64 = mux(_T_63, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_65 = and(_T_64, UInt<4>("h01")) @[dbg.scala 132:64] + node _T_66 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:100] + node _T_67 = eq(_T_66, UInt<1>("h01")) @[dbg.scala 132:109] + node _T_68 = bits(_T_67, 0, 0) @[Bitwise.scala 72:15] + node _T_69 = mux(_T_68, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_70 = and(_T_69, UInt<4>("h02")) @[dbg.scala 132:122] + node _T_71 = or(_T_65, _T_70) @[dbg.scala 132:81] + node _T_72 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:22] + node _T_73 = eq(_T_72, UInt<2>("h02")) @[dbg.scala 133:31] + node _T_74 = bits(_T_73, 0, 0) @[Bitwise.scala 72:15] + node _T_75 = mux(_T_74, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_76 = and(_T_75, UInt<4>("h04")) @[dbg.scala 133:44] + node _T_77 = or(_T_71, _T_76) @[dbg.scala 132:139] + node _T_78 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:80] + node _T_79 = eq(_T_78, UInt<2>("h03")) @[dbg.scala 133:89] + node _T_80 = bits(_T_79, 0, 0) @[Bitwise.scala 72:15] + node _T_81 = mux(_T_80, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_82 = and(_T_81, UInt<4>("h08")) @[dbg.scala 133:102] + node sbaddress0_incr = or(_T_77, _T_82) @[dbg.scala 133:61] + node _T_83 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 135:41] + node _T_84 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 135:79] + node sbdata0_reg_wren0 = and(_T_83, _T_84) @[dbg.scala 135:60] + node _T_85 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 136:37] + node _T_86 = and(_T_85, sb_state_en) @[dbg.scala 136:60] + node _T_87 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 136:76] + node sbdata0_reg_wren1 = and(_T_86, _T_87) @[dbg.scala 136:74] node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 137:44] - node _T_92 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 138:41] - node _T_93 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 138:79] - node sbdata1_reg_wren0 = and(_T_92, _T_93) @[dbg.scala 138:60] - node _T_94 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 139:37] - node _T_95 = and(_T_94, sb_state_en) @[dbg.scala 139:60] - node _T_96 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 139:76] - node sbdata1_reg_wren1 = and(_T_95, _T_96) @[dbg.scala 139:74] + node _T_88 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 138:41] + node _T_89 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 138:79] + node sbdata1_reg_wren0 = and(_T_88, _T_89) @[dbg.scala 138:60] + node _T_90 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 139:37] + node _T_91 = and(_T_90, sb_state_en) @[dbg.scala 139:60] + node _T_92 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 139:76] + node sbdata1_reg_wren1 = and(_T_91, _T_92) @[dbg.scala 139:74] node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 140:44] - node _T_97 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_98 = mux(_T_97, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_99 = and(_T_98, io.dmi_reg_wdata) @[dbg.scala 141:49] - node _T_100 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_93 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_94 = mux(_T_93, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_95 = and(_T_94, io.dmi_reg_wdata) @[dbg.scala 141:49] + node _T_96 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_97 = mux(_T_96, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_98 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 142:47] + node _T_99 = and(_T_97, _T_98) @[dbg.scala 142:33] + node sbdata0_din = or(_T_95, _T_99) @[dbg.scala 141:68] + node _T_100 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15] node _T_101 = mux(_T_100, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_102 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 142:47] - node _T_103 = and(_T_101, _T_102) @[dbg.scala 142:33] - node sbdata0_din = or(_T_99, _T_103) @[dbg.scala 141:68] - node _T_104 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_105 = mux(_T_104, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_106 = and(_T_105, io.dmi_reg_wdata) @[dbg.scala 144:49] - node _T_107 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15] - node _T_108 = mux(_T_107, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_109 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 145:47] - node _T_110 = and(_T_108, _T_109) @[dbg.scala 145:33] - node sbdata1_din = or(_T_106, _T_110) @[dbg.scala 144:68] - node _T_111 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 147:32] - node _T_112 = asAsyncReset(_T_111) @[dbg.scala 147:59] + node _T_102 = and(_T_101, io.dmi_reg_wdata) @[dbg.scala 144:49] + node _T_103 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_104 = mux(_T_103, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_105 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 145:47] + node _T_106 = and(_T_104, _T_105) @[dbg.scala 145:33] + node sbdata1_din = or(_T_102, _T_106) @[dbg.scala 144:68] + node _T_107 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 147:58] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 352:23] rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= _T_112 + rvclkhdr_2.reset <= _T_107 rvclkhdr_2.io.clk <= clock @[lib.scala 354:18] rvclkhdr_2.io.en <= sbdata0_reg_wren @[lib.scala 355:17] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (_T_112, UInt<1>("h00"))) @[lib.scala 358:16] + reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (_T_107, UInt<1>("h00"))) @[lib.scala 358:16] sbdata0_reg <= sbdata0_din @[lib.scala 358:16] - node _T_113 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 151:32] - node _T_114 = asAsyncReset(_T_113) @[dbg.scala 151:59] + node _T_108 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 151:58] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 352:23] rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= _T_114 + rvclkhdr_3.reset <= _T_108 rvclkhdr_3.io.clk <= clock @[lib.scala 354:18] rvclkhdr_3.io.en <= sbdata1_reg_wren @[lib.scala 355:17] rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (_T_114, UInt<1>("h00"))) @[lib.scala 358:16] + reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (_T_108, UInt<1>("h00"))) @[lib.scala 358:16] sbdata1_reg <= sbdata1_din @[lib.scala 358:16] - node _T_115 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 155:44] - node _T_116 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 155:82] - node sbaddress0_reg_wren0 = and(_T_115, _T_116) @[dbg.scala 155:63] + node _T_109 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 155:44] + node _T_110 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 155:82] + node sbaddress0_reg_wren0 = and(_T_109, _T_110) @[dbg.scala 155:63] node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 156:50] - node _T_117 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_118 = mux(_T_117, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_119 = and(_T_118, io.dmi_reg_wdata) @[dbg.scala 157:59] - node _T_120 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] - node _T_121 = mux(_T_120, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_122 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58] - node _T_123 = add(sbaddress0_reg, _T_122) @[dbg.scala 158:54] - node _T_124 = tail(_T_123, 1) @[dbg.scala 158:54] - node _T_125 = and(_T_121, _T_124) @[dbg.scala 158:36] - node sbaddress0_reg_din = or(_T_119, _T_125) @[dbg.scala 157:78] - node _T_126 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 159:32] - node _T_127 = asAsyncReset(_T_126) @[dbg.scala 159:59] + node _T_111 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_113 = and(_T_112, io.dmi_reg_wdata) @[dbg.scala 157:59] + node _T_114 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_115 = mux(_T_114, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_116 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58] + node _T_117 = add(sbaddress0_reg, _T_116) @[dbg.scala 158:54] + node _T_118 = tail(_T_117, 1) @[dbg.scala 158:54] + node _T_119 = and(_T_115, _T_118) @[dbg.scala 158:36] + node sbaddress0_reg_din = or(_T_113, _T_119) @[dbg.scala 157:78] + node _T_120 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 159:58] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 352:23] rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= _T_127 + rvclkhdr_4.reset <= _T_120 rvclkhdr_4.io.clk <= clock @[lib.scala 354:18] rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 355:17] rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_128 : UInt, rvclkhdr_4.io.l1clk with : (reset => (_T_127, UInt<1>("h00"))) @[lib.scala 358:16] - _T_128 <= sbaddress0_reg_din @[lib.scala 358:16] - sbaddress0_reg <= _T_128 @[dbg.scala 159:18] - node _T_129 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 163:43] - node _T_130 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 163:81] - node _T_131 = and(_T_129, _T_130) @[dbg.scala 163:62] - node _T_132 = bits(sbcs_reg, 20, 20) @[dbg.scala 163:104] - node sbreadonaddr_access = and(_T_131, _T_132) @[dbg.scala 163:94] - node _T_133 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 164:45] - node _T_134 = and(io.dmi_reg_en, _T_133) @[dbg.scala 164:43] - node _T_135 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 164:82] - node _T_136 = and(_T_134, _T_135) @[dbg.scala 164:63] - node _T_137 = bits(sbcs_reg, 15, 15) @[dbg.scala 164:105] - node sbreadondata_access = and(_T_136, _T_137) @[dbg.scala 164:95] - node _T_138 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 165:40] - node _T_139 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 165:78] - node sbdata0wr_access = and(_T_138, _T_139) @[dbg.scala 165:59] - node _T_140 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 166:41] - node _T_141 = and(_T_140, io.dmi_reg_en) @[dbg.scala 166:54] - node dmcontrol_wren = and(_T_141, io.dmi_reg_wr_en) @[dbg.scala 166:70] - node _T_142 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 167:50] - node _T_143 = asAsyncReset(_T_142) @[dbg.scala 167:77] - node _T_144 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 169:27] - node _T_145 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 169:53] - node _T_146 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 169:75] - node _T_147 = cat(_T_144, _T_145) @[Cat.scala 29:58] - node _T_148 = cat(_T_147, _T_146) @[Cat.scala 29:58] - reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (_T_143, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_121 : UInt, rvclkhdr_4.io.l1clk with : (reset => (_T_120, UInt<1>("h00"))) @[lib.scala 358:16] + _T_121 <= sbaddress0_reg_din @[lib.scala 358:16] + sbaddress0_reg <= _T_121 @[dbg.scala 159:18] + node _T_122 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 163:43] + node _T_123 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 163:81] + node _T_124 = and(_T_122, _T_123) @[dbg.scala 163:62] + node _T_125 = bits(sbcs_reg, 20, 20) @[dbg.scala 163:104] + node sbreadonaddr_access = and(_T_124, _T_125) @[dbg.scala 163:94] + node _T_126 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 164:45] + node _T_127 = and(io.dmi_reg_en, _T_126) @[dbg.scala 164:43] + node _T_128 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 164:82] + node _T_129 = and(_T_127, _T_128) @[dbg.scala 164:63] + node _T_130 = bits(sbcs_reg, 15, 15) @[dbg.scala 164:105] + node sbreadondata_access = and(_T_129, _T_130) @[dbg.scala 164:95] + node _T_131 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 165:40] + node _T_132 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 165:78] + node sbdata0wr_access = and(_T_131, _T_132) @[dbg.scala 165:59] + node _T_133 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 166:41] + node _T_134 = and(_T_133, io.dmi_reg_en) @[dbg.scala 166:54] + node dmcontrol_wren = and(_T_134, io.dmi_reg_wr_en) @[dbg.scala 166:70] + node _T_135 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 167:76] + node _T_136 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 169:27] + node _T_137 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 169:53] + node _T_138 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 169:75] + node _T_139 = cat(_T_136, _T_137) @[Cat.scala 29:58] + node _T_140 = cat(_T_139, _T_138) @[Cat.scala 29:58] + reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (_T_135, UInt<1>("h00"))) @[Reg.scala 27:20] when dmcontrol_wren : @[Reg.scala 28:19] - dm_temp <= _T_148 @[Reg.scala 28:23] + dm_temp <= _T_140 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_149 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 173:76] - node _T_150 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 174:31] - reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_149, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_141 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 173:76] + node _T_142 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 174:31] + reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_141, UInt<1>("h00"))) @[Reg.scala 27:20] when dmcontrol_wren : @[Reg.scala 28:19] - dm_temp_0 <= _T_150 @[Reg.scala 28:23] + dm_temp_0 <= _T_142 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_151 = bits(dm_temp, 3, 2) @[dbg.scala 177:25] - node _T_152 = bits(dm_temp, 1, 1) @[dbg.scala 177:45] - node _T_153 = bits(dm_temp, 0, 0) @[dbg.scala 177:68] - node _T_154 = cat(UInt<26>("h00"), _T_153) @[Cat.scala 29:58] - node _T_155 = cat(_T_154, dm_temp_0) @[Cat.scala 29:58] - node _T_156 = cat(_T_151, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_157 = cat(_T_156, _T_152) @[Cat.scala 29:58] - node temp = cat(_T_157, _T_155) @[Cat.scala 29:58] + node _T_143 = bits(dm_temp, 3, 2) @[dbg.scala 177:25] + node _T_144 = bits(dm_temp, 1, 1) @[dbg.scala 177:45] + node _T_145 = bits(dm_temp, 0, 0) @[dbg.scala 177:68] + node _T_146 = cat(UInt<26>("h00"), _T_145) @[Cat.scala 29:58] + node _T_147 = cat(_T_146, dm_temp_0) @[Cat.scala 29:58] + node _T_148 = cat(_T_143, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_149 = cat(_T_148, _T_144) @[Cat.scala 29:58] + node temp = cat(_T_149, _T_147) @[Cat.scala 29:58] dmcontrol_reg <= temp @[dbg.scala 178:17] - node _T_158 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 180:59] - node _T_159 = asAsyncReset(_T_158) @[dbg.scala 180:86] - reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_159, UInt<1>("h00"))) @[dbg.scala 181:12] + node _T_150 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 180:85] + reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_150, UInt<1>("h00"))) @[dbg.scala 181:12] dmcontrol_wren_Q <= dmcontrol_wren @[dbg.scala 181:12] - node _T_160 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15] - node _T_161 = mux(_T_160, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_162 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15] - node _T_163 = mux(_T_162, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_164 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15] - node _T_165 = mux(_T_164, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_166 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15] - node _T_167 = mux(_T_166, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_168 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15] - node _T_169 = mux(_T_168, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_170 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58] - node _T_171 = cat(_T_167, _T_169) @[Cat.scala 29:58] - node _T_172 = cat(_T_171, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_173 = cat(_T_172, _T_170) @[Cat.scala 29:58] - node _T_174 = cat(UInt<2>("h00"), _T_165) @[Cat.scala 29:58] - node _T_175 = cat(UInt<12>("h00"), _T_161) @[Cat.scala 29:58] - node _T_176 = cat(_T_175, _T_163) @[Cat.scala 29:58] - node _T_177 = cat(_T_176, _T_174) @[Cat.scala 29:58] - node _T_178 = cat(_T_177, _T_173) @[Cat.scala 29:58] - dmstatus_reg <= _T_178 @[dbg.scala 184:16] - node _T_179 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 186:44] - node _T_180 = and(_T_179, io.dec_tlu_resume_ack) @[dbg.scala 186:66] - node _T_181 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 186:127] - node _T_182 = eq(_T_181, UInt<1>("h00")) @[dbg.scala 186:113] - node _T_183 = and(dmstatus_resumeack, _T_182) @[dbg.scala 186:111] - node dmstatus_resumeack_wren = or(_T_180, _T_183) @[dbg.scala 186:90] - node _T_184 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 187:43] - node dmstatus_resumeack_din = and(_T_184, io.dec_tlu_resume_ack) @[dbg.scala 187:65] - node _T_185 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 188:50] - node _T_186 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 188:81] - node _T_187 = and(_T_185, _T_186) @[dbg.scala 188:63] - node _T_188 = and(_T_187, io.dmi_reg_en) @[dbg.scala 188:85] - node dmstatus_havereset_wren = and(_T_188, io.dmi_reg_wr_en) @[dbg.scala 188:101] - node _T_189 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 189:49] - node _T_190 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 189:80] - node _T_191 = and(_T_189, _T_190) @[dbg.scala 189:62] - node _T_192 = and(_T_191, io.dmi_reg_en) @[dbg.scala 189:85] - node dmstatus_havereset_rst = and(_T_192, io.dmi_reg_wr_en) @[dbg.scala 189:101] + node _T_151 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15] + node _T_152 = mux(_T_151, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_153 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15] + node _T_154 = mux(_T_153, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_155 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15] + node _T_156 = mux(_T_155, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_157 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15] + node _T_158 = mux(_T_157, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_159 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15] + node _T_160 = mux(_T_159, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_161 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58] + node _T_162 = cat(_T_158, _T_160) @[Cat.scala 29:58] + node _T_163 = cat(_T_162, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_164 = cat(_T_163, _T_161) @[Cat.scala 29:58] + node _T_165 = cat(UInt<2>("h00"), _T_156) @[Cat.scala 29:58] + node _T_166 = cat(UInt<12>("h00"), _T_152) @[Cat.scala 29:58] + node _T_167 = cat(_T_166, _T_154) @[Cat.scala 29:58] + node _T_168 = cat(_T_167, _T_165) @[Cat.scala 29:58] + node _T_169 = cat(_T_168, _T_164) @[Cat.scala 29:58] + dmstatus_reg <= _T_169 @[dbg.scala 184:16] + node _T_170 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 186:44] + node _T_171 = and(_T_170, io.dec_tlu_resume_ack) @[dbg.scala 186:66] + node _T_172 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 186:127] + node _T_173 = eq(_T_172, UInt<1>("h00")) @[dbg.scala 186:113] + node _T_174 = and(dmstatus_resumeack, _T_173) @[dbg.scala 186:111] + node dmstatus_resumeack_wren = or(_T_171, _T_174) @[dbg.scala 186:90] + node _T_175 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 187:43] + node dmstatus_resumeack_din = and(_T_175, io.dec_tlu_resume_ack) @[dbg.scala 187:65] + node _T_176 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 188:50] + node _T_177 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 188:81] + node _T_178 = and(_T_176, _T_177) @[dbg.scala 188:63] + node _T_179 = and(_T_178, io.dmi_reg_en) @[dbg.scala 188:85] + node dmstatus_havereset_wren = and(_T_179, io.dmi_reg_wr_en) @[dbg.scala 188:101] + node _T_180 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 189:49] + node _T_181 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 189:80] + node _T_182 = and(_T_180, _T_181) @[dbg.scala 189:62] + node _T_183 = and(_T_182, io.dmi_reg_en) @[dbg.scala 189:85] + node dmstatus_havereset_rst = and(_T_183, io.dmi_reg_wr_en) @[dbg.scala 189:101] node temp_rst = asUInt(reset) @[dbg.scala 190:30] - node _T_193 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 191:37] - node _T_194 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 191:43] - node _T_195 = or(_T_193, _T_194) @[dbg.scala 191:41] - node _T_196 = bits(_T_195, 0, 0) @[dbg.scala 191:62] - dmstatus_unavail <= _T_196 @[dbg.scala 191:20] - node _T_197 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 192:42] - node _T_198 = not(_T_197) @[dbg.scala 192:23] - dmstatus_running <= _T_198 @[dbg.scala 192:20] - node _T_199 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 193:58] - node _T_200 = asAsyncReset(_T_199) @[dbg.scala 193:85] - reg _T_201 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_200, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_184 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 191:37] + node _T_185 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 191:43] + node _T_186 = or(_T_184, _T_185) @[dbg.scala 191:41] + node _T_187 = bits(_T_186, 0, 0) @[dbg.scala 191:62] + dmstatus_unavail <= _T_187 @[dbg.scala 191:20] + node _T_188 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 192:42] + node _T_189 = not(_T_188) @[dbg.scala 192:23] + dmstatus_running <= _T_189 @[dbg.scala 192:20] + node _T_190 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 193:84] + reg _T_191 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_190, UInt<1>("h00"))) @[Reg.scala 27:20] when dmstatus_resumeack_wren : @[Reg.scala 28:19] - _T_201 <= dmstatus_resumeack_din @[Reg.scala 28:23] + _T_191 <= dmstatus_resumeack_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - dmstatus_resumeack <= _T_201 @[dbg.scala 193:22] - node _T_202 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 197:55] - node _T_203 = asAsyncReset(_T_202) @[dbg.scala 197:82] - node _T_204 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 198:37] - node _T_205 = and(io.dec_tlu_dbg_halted, _T_204) @[dbg.scala 198:35] - reg _T_206 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_203, UInt<1>("h00"))) @[dbg.scala 198:12] - _T_206 <= _T_205 @[dbg.scala 198:12] - dmstatus_halted <= _T_206 @[dbg.scala 197:19] - node _T_207 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 201:58] - node _T_208 = asAsyncReset(_T_207) @[dbg.scala 201:85] - node _T_209 = not(dmstatus_havereset_rst) @[dbg.scala 202:15] - reg _T_210 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_208, UInt<1>("h00"))) @[Reg.scala 27:20] - when dmstatus_havereset_wren : @[Reg.scala 28:19] - _T_210 <= _T_209 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - dmstatus_havereset <= _T_210 @[dbg.scala 201:22] + dmstatus_resumeack <= _T_191 @[dbg.scala 193:22] + node _T_192 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 197:81] + node _T_193 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 198:37] + node _T_194 = and(io.dec_tlu_dbg_halted, _T_193) @[dbg.scala 198:35] + reg _T_195 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_192, UInt<1>("h00"))) @[dbg.scala 198:12] + _T_195 <= _T_194 @[dbg.scala 198:12] + dmstatus_halted <= _T_195 @[dbg.scala 197:19] + node _T_196 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 201:84] + node _T_197 = mux(dmstatus_havereset_wren, UInt<1>("h01"), dmstatus_havereset) @[dbg.scala 202:16] + node _T_198 = eq(dmstatus_havereset_rst, UInt<1>("h00")) @[dbg.scala 202:72] + node _T_199 = and(_T_197, _T_198) @[dbg.scala 202:70] + reg _T_200 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_196, UInt<1>("h00"))) @[dbg.scala 202:12] + _T_200 <= _T_199 @[dbg.scala 202:12] + dmstatus_havereset <= _T_200 @[dbg.scala 201:22] node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58] wire abstractcs_reg : UInt<32> abstractcs_reg <= UInt<32>("h02") - node _T_211 = bits(abstractcs_reg, 12, 12) @[dbg.scala 208:45] - node _T_212 = and(_T_211, io.dmi_reg_en) @[dbg.scala 208:50] - node _T_213 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 208:106] - node _T_214 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 208:138] - node _T_215 = or(_T_213, _T_214) @[dbg.scala 208:119] - node _T_216 = and(io.dmi_reg_wr_en, _T_215) @[dbg.scala 208:86] - node _T_217 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 208:171] - node _T_218 = or(_T_216, _T_217) @[dbg.scala 208:152] - node abstractcs_error_sel0 = and(_T_212, _T_218) @[dbg.scala 208:66] - node _T_219 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 209:45] - node _T_220 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 209:83] - node _T_221 = and(_T_219, _T_220) @[dbg.scala 209:64] - node _T_222 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:117] - node _T_223 = eq(_T_222, UInt<1>("h00")) @[dbg.scala 209:126] - node _T_224 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:154] - node _T_225 = eq(_T_224, UInt<2>("h02")) @[dbg.scala 209:163] - node _T_226 = or(_T_223, _T_225) @[dbg.scala 209:135] - node _T_227 = eq(_T_226, UInt<1>("h00")) @[dbg.scala 209:98] - node abstractcs_error_sel1 = and(_T_221, _T_227) @[dbg.scala 209:96] + node _T_201 = bits(abstractcs_reg, 12, 12) @[dbg.scala 208:45] + node _T_202 = and(_T_201, io.dmi_reg_en) @[dbg.scala 208:50] + node _T_203 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 208:106] + node _T_204 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 208:138] + node _T_205 = or(_T_203, _T_204) @[dbg.scala 208:119] + node _T_206 = and(io.dmi_reg_wr_en, _T_205) @[dbg.scala 208:86] + node _T_207 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 208:171] + node _T_208 = or(_T_206, _T_207) @[dbg.scala 208:152] + node abstractcs_error_sel0 = and(_T_202, _T_208) @[dbg.scala 208:66] + node _T_209 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 209:45] + node _T_210 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 209:83] + node _T_211 = and(_T_209, _T_210) @[dbg.scala 209:64] + node _T_212 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:117] + node _T_213 = eq(_T_212, UInt<1>("h00")) @[dbg.scala 209:126] + node _T_214 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:154] + node _T_215 = eq(_T_214, UInt<2>("h02")) @[dbg.scala 209:163] + node _T_216 = or(_T_213, _T_215) @[dbg.scala 209:135] + node _T_217 = eq(_T_216, UInt<1>("h00")) @[dbg.scala 209:98] + node abstractcs_error_sel1 = and(_T_211, _T_217) @[dbg.scala 209:96] node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 210:52] - node _T_228 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 211:45] - node _T_229 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 211:83] - node _T_230 = and(_T_228, _T_229) @[dbg.scala 211:64] - node _T_231 = bits(dmstatus_reg, 9, 9) @[dbg.scala 211:111] - node _T_232 = eq(_T_231, UInt<1>("h00")) @[dbg.scala 211:98] - node abstractcs_error_sel3 = and(_T_230, _T_232) @[dbg.scala 211:96] - node _T_233 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 212:48] - node _T_234 = and(_T_233, io.dmi_reg_en) @[dbg.scala 212:61] - node _T_235 = and(_T_234, io.dmi_reg_wr_en) @[dbg.scala 212:77] - node _T_236 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 213:23] - node _T_237 = neq(_T_236, UInt<2>("h02")) @[dbg.scala 213:32] - node _T_238 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 213:66] - node _T_239 = eq(_T_238, UInt<2>("h02")) @[dbg.scala 213:75] - node _T_240 = bits(data1_reg, 1, 0) @[dbg.scala 213:99] - node _T_241 = orr(_T_240) @[dbg.scala 213:106] - node _T_242 = and(_T_239, _T_241) @[dbg.scala 213:87] - node _T_243 = or(_T_237, _T_242) @[dbg.scala 213:46] - node abstractcs_error_sel4 = and(_T_235, _T_243) @[dbg.scala 212:96] - node _T_244 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 215:48] - node _T_245 = and(_T_244, io.dmi_reg_en) @[dbg.scala 215:61] - node abstractcs_error_sel5 = and(_T_245, io.dmi_reg_wr_en) @[dbg.scala 215:77] - node _T_246 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 216:54] - node _T_247 = or(_T_246, abstractcs_error_sel2) @[dbg.scala 216:78] - node _T_248 = or(_T_247, abstractcs_error_sel3) @[dbg.scala 216:102] - node _T_249 = or(_T_248, abstractcs_error_sel4) @[dbg.scala 216:126] - node abstractcs_error_selor = or(_T_249, abstractcs_error_sel5) @[dbg.scala 216:150] - node _T_250 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15] - node _T_251 = mux(_T_250, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_252 = and(_T_251, UInt<1>("h01")) @[dbg.scala 217:62] - node _T_253 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15] - node _T_254 = mux(_T_253, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_255 = and(_T_254, UInt<2>("h02")) @[dbg.scala 218:37] - node _T_256 = or(_T_252, _T_255) @[dbg.scala 217:74] - node _T_257 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15] - node _T_258 = mux(_T_257, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_259 = and(_T_258, UInt<2>("h03")) @[dbg.scala 219:37] - node _T_260 = or(_T_256, _T_259) @[dbg.scala 218:49] - node _T_261 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15] - node _T_262 = mux(_T_261, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_263 = and(_T_262, UInt<3>("h04")) @[dbg.scala 220:37] - node _T_264 = or(_T_260, _T_263) @[dbg.scala 219:49] - node _T_265 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15] - node _T_266 = mux(_T_265, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_267 = and(_T_266, UInt<3>("h07")) @[dbg.scala 221:37] - node _T_268 = or(_T_264, _T_267) @[dbg.scala 220:49] - node _T_269 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15] - node _T_270 = mux(_T_269, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_271 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 222:57] - node _T_272 = not(_T_271) @[dbg.scala 222:40] - node _T_273 = and(_T_270, _T_272) @[dbg.scala 222:37] - node _T_274 = bits(abstractcs_reg, 10, 8) @[dbg.scala 222:91] - node _T_275 = and(_T_273, _T_274) @[dbg.scala 222:75] - node _T_276 = or(_T_268, _T_275) @[dbg.scala 221:49] - node _T_277 = not(abstractcs_error_selor) @[dbg.scala 223:15] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_280 = bits(abstractcs_reg, 10, 8) @[dbg.scala 223:66] - node _T_281 = and(_T_279, _T_280) @[dbg.scala 223:50] - node abstractcs_error_din = or(_T_276, _T_281) @[dbg.scala 222:100] - node _T_282 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 225:54] - node _T_283 = asAsyncReset(_T_282) @[dbg.scala 225:81] - reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_283, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_218 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 211:45] + node _T_219 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 211:83] + node _T_220 = and(_T_218, _T_219) @[dbg.scala 211:64] + node _T_221 = bits(dmstatus_reg, 9, 9) @[dbg.scala 211:111] + node _T_222 = eq(_T_221, UInt<1>("h00")) @[dbg.scala 211:98] + node abstractcs_error_sel3 = and(_T_220, _T_222) @[dbg.scala 211:96] + node _T_223 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 212:48] + node _T_224 = and(_T_223, io.dmi_reg_en) @[dbg.scala 212:61] + node _T_225 = and(_T_224, io.dmi_reg_wr_en) @[dbg.scala 212:77] + node _T_226 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 213:23] + node _T_227 = neq(_T_226, UInt<3>("h02")) @[dbg.scala 213:32] + node _T_228 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 213:71] + node _T_229 = eq(_T_228, UInt<2>("h02")) @[dbg.scala 213:80] + node _T_230 = bits(data1_reg, 1, 0) @[dbg.scala 213:104] + node _T_231 = orr(_T_230) @[dbg.scala 213:111] + node _T_232 = and(_T_229, _T_231) @[dbg.scala 213:92] + node _T_233 = or(_T_227, _T_232) @[dbg.scala 213:51] + node abstractcs_error_sel4 = and(_T_225, _T_233) @[dbg.scala 212:96] + node _T_234 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 215:48] + node _T_235 = and(_T_234, io.dmi_reg_en) @[dbg.scala 215:61] + node abstractcs_error_sel5 = and(_T_235, io.dmi_reg_wr_en) @[dbg.scala 215:77] + node _T_236 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 216:54] + node _T_237 = or(_T_236, abstractcs_error_sel2) @[dbg.scala 216:78] + node _T_238 = or(_T_237, abstractcs_error_sel3) @[dbg.scala 216:102] + node _T_239 = or(_T_238, abstractcs_error_sel4) @[dbg.scala 216:126] + node abstractcs_error_selor = or(_T_239, abstractcs_error_sel5) @[dbg.scala 216:150] + node _T_240 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15] + node _T_241 = mux(_T_240, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_242 = and(_T_241, UInt<3>("h01")) @[dbg.scala 217:62] + node _T_243 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15] + node _T_244 = mux(_T_243, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_245 = and(_T_244, UInt<3>("h02")) @[dbg.scala 218:37] + node _T_246 = or(_T_242, _T_245) @[dbg.scala 217:79] + node _T_247 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15] + node _T_248 = mux(_T_247, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_249 = and(_T_248, UInt<3>("h03")) @[dbg.scala 219:37] + node _T_250 = or(_T_246, _T_249) @[dbg.scala 218:54] + node _T_251 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15] + node _T_252 = mux(_T_251, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_253 = and(_T_252, UInt<3>("h04")) @[dbg.scala 220:37] + node _T_254 = or(_T_250, _T_253) @[dbg.scala 219:54] + node _T_255 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15] + node _T_256 = mux(_T_255, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_257 = and(_T_256, UInt<3>("h07")) @[dbg.scala 221:37] + node _T_258 = or(_T_254, _T_257) @[dbg.scala 220:54] + node _T_259 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15] + node _T_260 = mux(_T_259, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_261 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 222:57] + node _T_262 = not(_T_261) @[dbg.scala 222:40] + node _T_263 = and(_T_260, _T_262) @[dbg.scala 222:37] + node _T_264 = bits(abstractcs_reg, 10, 8) @[dbg.scala 222:91] + node _T_265 = and(_T_263, _T_264) @[dbg.scala 222:75] + node _T_266 = or(_T_258, _T_265) @[dbg.scala 221:54] + node _T_267 = not(abstractcs_error_selor) @[dbg.scala 223:15] + node _T_268 = bits(_T_267, 0, 0) @[Bitwise.scala 72:15] + node _T_269 = mux(_T_268, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_270 = bits(abstractcs_reg, 10, 8) @[dbg.scala 223:66] + node _T_271 = and(_T_269, _T_270) @[dbg.scala 223:50] + node abstractcs_error_din = or(_T_266, _T_271) @[dbg.scala 222:100] + node _T_272 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 225:80] + reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_272, UInt<1>("h00"))) @[Reg.scala 27:20] when abstractcs_busy_wren : @[Reg.scala 28:19] abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_284 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 229:56] - node _T_285 = asAsyncReset(_T_284) @[dbg.scala 229:83] - node _T_286 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 230:33] - reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_285, UInt<1>("h00"))) @[dbg.scala 230:12] - abs_temp_10_8 <= _T_286 @[dbg.scala 230:12] - node _T_287 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58] - node _T_288 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58] - node _T_289 = cat(_T_288, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_290 = cat(_T_289, _T_287) @[Cat.scala 29:58] - abstractcs_reg <= _T_290 @[dbg.scala 233:18] - node _T_291 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 235:39] - node _T_292 = and(_T_291, io.dmi_reg_en) @[dbg.scala 235:52] - node _T_293 = and(_T_292, io.dmi_reg_wr_en) @[dbg.scala 235:68] - node _T_294 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 235:100] - node command_wren = and(_T_293, _T_294) @[dbg.scala 235:87] - node _T_295 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 236:41] - node _T_296 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 236:77] - node _T_297 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 236:113] - node _T_298 = cat(UInt<3>("h00"), _T_297) @[Cat.scala 29:58] - node _T_299 = cat(_T_295, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_300 = cat(_T_299, _T_296) @[Cat.scala 29:58] - node command_din = cat(_T_300, _T_298) @[Cat.scala 29:58] - node _T_301 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 237:32] - node _T_302 = asAsyncReset(_T_301) @[dbg.scala 237:59] + node _T_273 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 229:82] + node _T_274 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 230:33] + reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_273, UInt<1>("h00"))) @[dbg.scala 230:12] + abs_temp_10_8 <= _T_274 @[dbg.scala 230:12] + node _T_275 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58] + node _T_276 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58] + node _T_277 = cat(_T_276, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_278 = cat(_T_277, _T_275) @[Cat.scala 29:58] + abstractcs_reg <= _T_278 @[dbg.scala 233:18] + node _T_279 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 235:39] + node _T_280 = and(_T_279, io.dmi_reg_en) @[dbg.scala 235:52] + node _T_281 = and(_T_280, io.dmi_reg_wr_en) @[dbg.scala 235:68] + node _T_282 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 235:100] + node command_wren = and(_T_281, _T_282) @[dbg.scala 235:87] + node _T_283 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 236:41] + node _T_284 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 236:77] + node _T_285 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 236:113] + node _T_286 = cat(UInt<3>("h00"), _T_285) @[Cat.scala 29:58] + node _T_287 = cat(_T_283, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_288 = cat(_T_287, _T_284) @[Cat.scala 29:58] + node command_din = cat(_T_288, _T_286) @[Cat.scala 29:58] + node _T_289 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 237:58] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 352:23] rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= _T_302 + rvclkhdr_5.reset <= _T_289 rvclkhdr_5.io.clk <= clock @[lib.scala 354:18] rvclkhdr_5.io.en <= command_wren @[lib.scala 355:17] rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_302, UInt<1>("h00"))) @[lib.scala 358:16] + reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_289, UInt<1>("h00"))) @[lib.scala 358:16] command_reg <= command_din @[lib.scala 358:16] - node _T_303 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39] - node _T_304 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77] - node _T_305 = and(_T_303, _T_304) @[dbg.scala 241:58] - node _T_306 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 241:102] - node data0_reg_wren0 = and(_T_305, _T_306) @[dbg.scala 241:89] - node _T_307 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 242:59] - node _T_308 = and(io.core_dbg_cmd_done, _T_307) @[dbg.scala 242:46] - node _T_309 = bits(command_reg, 16, 16) @[dbg.scala 242:95] - node _T_310 = eq(_T_309, UInt<1>("h00")) @[dbg.scala 242:83] - node data0_reg_wren1 = and(_T_308, _T_310) @[dbg.scala 242:81] + node _T_290 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39] + node _T_291 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77] + node _T_292 = and(_T_290, _T_291) @[dbg.scala 241:58] + node _T_293 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 241:102] + node data0_reg_wren0 = and(_T_292, _T_293) @[dbg.scala 241:89] + node _T_294 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 242:59] + node _T_295 = and(io.core_dbg_cmd_done, _T_294) @[dbg.scala 242:46] + node _T_296 = bits(command_reg, 16, 16) @[dbg.scala 242:95] + node _T_297 = eq(_T_296, UInt<1>("h00")) @[dbg.scala 242:83] + node data0_reg_wren1 = and(_T_295, _T_297) @[dbg.scala 242:81] node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 244:40] - node _T_311 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_312 = mux(_T_311, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_313 = and(_T_312, io.dmi_reg_wdata) @[dbg.scala 245:45] - node _T_314 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] - node _T_315 = mux(_T_314, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_316 = and(_T_315, io.core_dbg_rddata) @[dbg.scala 245:92] - node data0_din = or(_T_313, _T_316) @[dbg.scala 245:64] - node _T_317 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 246:30] - node _T_318 = asAsyncReset(_T_317) @[dbg.scala 246:57] + node _T_298 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_300 = and(_T_299, io.dmi_reg_wdata) @[dbg.scala 245:45] + node _T_301 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_302 = mux(_T_301, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_303 = and(_T_302, io.core_dbg_rddata) @[dbg.scala 245:92] + node data0_din = or(_T_300, _T_303) @[dbg.scala 245:64] + node _T_304 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 246:56] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 352:23] rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= _T_318 + rvclkhdr_6.reset <= _T_304 rvclkhdr_6.io.clk <= clock @[lib.scala 354:18] rvclkhdr_6.io.en <= data0_reg_wren @[lib.scala 355:17] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (_T_318, UInt<1>("h00"))) @[lib.scala 358:16] + reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (_T_304, UInt<1>("h00"))) @[lib.scala 358:16] data0_reg <= data0_din @[lib.scala 358:16] - node _T_319 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39] - node _T_320 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77] - node _T_321 = and(_T_319, _T_320) @[dbg.scala 250:58] - node _T_322 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 250:102] - node data1_reg_wren = and(_T_321, _T_322) @[dbg.scala 250:89] - node _T_323 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15] - node _T_324 = mux(_T_323, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node data1_din = and(_T_324, io.dmi_reg_wdata) @[dbg.scala 251:44] - node _T_325 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 252:27] - node _T_326 = asAsyncReset(_T_325) @[dbg.scala 252:54] + node _T_305 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39] + node _T_306 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77] + node _T_307 = and(_T_305, _T_306) @[dbg.scala 250:58] + node _T_308 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 250:102] + node data1_reg_wren = and(_T_307, _T_308) @[dbg.scala 250:89] + node _T_309 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15] + node _T_310 = mux(_T_309, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node data1_din = and(_T_310, io.dmi_reg_wdata) @[dbg.scala 251:44] + node _T_311 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 252:53] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 352:23] rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= _T_326 + rvclkhdr_7.reset <= _T_311 rvclkhdr_7.io.clk <= clock @[lib.scala 354:18] rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 355:17] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_327 : UInt, rvclkhdr_7.io.l1clk with : (reset => (_T_326, UInt<1>("h00"))) @[lib.scala 358:16] - _T_327 <= data1_din @[lib.scala 358:16] - data1_reg <= _T_327 @[dbg.scala 252:13] + reg _T_312 : UInt, rvclkhdr_7.io.l1clk with : (reset => (_T_311, UInt<1>("h00"))) @[lib.scala 358:16] + _T_312 <= data1_din @[lib.scala 358:16] + data1_reg <= _T_312 @[dbg.scala 252:13] wire dbg_nxtstate : UInt<3> dbg_nxtstate <= UInt<3>("h00") dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 257:16] @@ -751,275 +734,273 @@ circuit dbg : abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 260:23] io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 261:19] io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 262:21] - node _T_328 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30] - when _T_328 : @[Conditional.scala 40:58] - node _T_329 = bits(dmstatus_reg, 9, 9) @[dbg.scala 265:39] - node _T_330 = or(_T_329, io.dec_tlu_mpc_halted_only) @[dbg.scala 265:43] - node _T_331 = mux(_T_330, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 265:26] - dbg_nxtstate <= _T_331 @[dbg.scala 265:20] - node _T_332 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 266:38] - node _T_333 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 266:45] - node _T_334 = and(_T_332, _T_333) @[dbg.scala 266:43] - node _T_335 = bits(dmstatus_reg, 9, 9) @[dbg.scala 266:83] - node _T_336 = or(_T_334, _T_335) @[dbg.scala 266:69] - node _T_337 = or(_T_336, io.dec_tlu_mpc_halted_only) @[dbg.scala 266:87] - node _T_338 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 266:133] - node _T_339 = eq(_T_338, UInt<1>("h00")) @[dbg.scala 266:119] - node _T_340 = and(_T_337, _T_339) @[dbg.scala 266:117] - dbg_state_en <= _T_340 @[dbg.scala 266:20] - node _T_341 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 267:40] - node _T_342 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 267:61] - node _T_343 = eq(_T_342, UInt<1>("h00")) @[dbg.scala 267:47] - node _T_344 = and(_T_341, _T_343) @[dbg.scala 267:45] - node _T_345 = bits(_T_344, 0, 0) @[dbg.scala 267:72] - io.dbg_halt_req <= _T_345 @[dbg.scala 267:23] + node _T_313 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30] + when _T_313 : @[Conditional.scala 40:58] + node _T_314 = bits(dmstatus_reg, 9, 9) @[dbg.scala 265:39] + node _T_315 = or(_T_314, io.dec_tlu_mpc_halted_only) @[dbg.scala 265:43] + node _T_316 = mux(_T_315, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 265:26] + dbg_nxtstate <= _T_316 @[dbg.scala 265:20] + node _T_317 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 266:38] + node _T_318 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 266:45] + node _T_319 = and(_T_317, _T_318) @[dbg.scala 266:43] + node _T_320 = bits(dmstatus_reg, 9, 9) @[dbg.scala 266:83] + node _T_321 = or(_T_319, _T_320) @[dbg.scala 266:69] + node _T_322 = or(_T_321, io.dec_tlu_mpc_halted_only) @[dbg.scala 266:87] + node _T_323 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 266:133] + node _T_324 = eq(_T_323, UInt<1>("h00")) @[dbg.scala 266:119] + node _T_325 = and(_T_322, _T_324) @[dbg.scala 266:117] + dbg_state_en <= _T_325 @[dbg.scala 266:20] + node _T_326 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 267:40] + node _T_327 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 267:61] + node _T_328 = eq(_T_327, UInt<1>("h00")) @[dbg.scala 267:47] + node _T_329 = and(_T_326, _T_328) @[dbg.scala 267:45] + node _T_330 = bits(_T_329, 0, 0) @[dbg.scala 267:72] + io.dbg_halt_req <= _T_330 @[dbg.scala 267:23] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_346 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30] - when _T_346 : @[Conditional.scala 39:67] - node _T_347 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 270:40] - node _T_348 = mux(_T_347, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 270:26] - dbg_nxtstate <= _T_348 @[dbg.scala 270:20] - node _T_349 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:35] - node _T_350 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:54] - node _T_351 = or(_T_349, _T_350) @[dbg.scala 271:39] - dbg_state_en <= _T_351 @[dbg.scala 271:20] - node _T_352 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:59] - node _T_353 = and(dmcontrol_wren_Q, _T_352) @[dbg.scala 272:44] - node _T_354 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:81] - node _T_355 = not(_T_354) @[dbg.scala 272:67] - node _T_356 = and(_T_353, _T_355) @[dbg.scala 272:64] - node _T_357 = bits(_T_356, 0, 0) @[dbg.scala 272:102] - io.dbg_halt_req <= _T_357 @[dbg.scala 272:23] + node _T_331 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30] + when _T_331 : @[Conditional.scala 39:67] + node _T_332 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 270:40] + node _T_333 = mux(_T_332, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 270:26] + dbg_nxtstate <= _T_333 @[dbg.scala 270:20] + node _T_334 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:35] + node _T_335 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:54] + node _T_336 = or(_T_334, _T_335) @[dbg.scala 271:39] + dbg_state_en <= _T_336 @[dbg.scala 271:20] + node _T_337 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:59] + node _T_338 = and(dmcontrol_wren_Q, _T_337) @[dbg.scala 272:44] + node _T_339 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:81] + node _T_340 = not(_T_339) @[dbg.scala 272:67] + node _T_341 = and(_T_338, _T_340) @[dbg.scala 272:64] + node _T_342 = bits(_T_341, 0, 0) @[dbg.scala 272:102] + io.dbg_halt_req <= _T_342 @[dbg.scala 272:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_358 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30] - when _T_358 : @[Conditional.scala 39:67] - node _T_359 = bits(dmstatus_reg, 9, 9) @[dbg.scala 275:39] - node _T_360 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:59] - node _T_361 = eq(_T_360, UInt<1>("h00")) @[dbg.scala 275:45] - node _T_362 = and(_T_359, _T_361) @[dbg.scala 275:43] - node _T_363 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 276:26] - node _T_364 = bits(dmcontrol_reg, 3, 3) @[dbg.scala 276:47] - node _T_365 = eq(_T_364, UInt<1>("h00")) @[dbg.scala 276:33] - node _T_366 = and(_T_363, _T_365) @[dbg.scala 276:31] - node _T_367 = mux(_T_366, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 276:12] - node _T_368 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:26] - node _T_369 = mux(_T_368, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 277:12] - node _T_370 = mux(_T_362, _T_367, _T_369) @[dbg.scala 275:26] - dbg_nxtstate <= _T_370 @[dbg.scala 275:20] - node _T_371 = bits(dmstatus_reg, 9, 9) @[dbg.scala 278:35] - node _T_372 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 278:54] - node _T_373 = and(_T_371, _T_372) @[dbg.scala 278:39] - node _T_374 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 278:75] - node _T_375 = eq(_T_374, UInt<1>("h00")) @[dbg.scala 278:61] - node _T_376 = and(_T_373, _T_375) @[dbg.scala 278:59] - node _T_377 = and(_T_376, dmcontrol_wren_Q) @[dbg.scala 278:80] - node _T_378 = or(_T_377, command_wren) @[dbg.scala 278:99] - node _T_379 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 279:22] - node _T_380 = or(_T_378, _T_379) @[dbg.scala 278:114] - node _T_381 = bits(dmstatus_reg, 9, 9) @[dbg.scala 279:42] - node _T_382 = or(_T_381, io.dec_tlu_mpc_halted_only) @[dbg.scala 279:46] - node _T_383 = eq(_T_382, UInt<1>("h00")) @[dbg.scala 279:28] - node _T_384 = or(_T_380, _T_383) @[dbg.scala 279:26] - dbg_state_en <= _T_384 @[dbg.scala 278:20] - node _T_385 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 280:60] - node _T_386 = and(dbg_state_en, _T_385) @[dbg.scala 280:44] - abstractcs_busy_wren <= _T_386 @[dbg.scala 280:28] + node _T_343 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30] + when _T_343 : @[Conditional.scala 39:67] + node _T_344 = bits(dmstatus_reg, 9, 9) @[dbg.scala 275:39] + node _T_345 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:59] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dbg.scala 275:45] + node _T_347 = and(_T_344, _T_346) @[dbg.scala 275:43] + node _T_348 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 276:26] + node _T_349 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 276:47] + node _T_350 = eq(_T_349, UInt<1>("h00")) @[dbg.scala 276:33] + node _T_351 = and(_T_348, _T_350) @[dbg.scala 276:31] + node _T_352 = mux(_T_351, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 276:12] + node _T_353 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:26] + node _T_354 = mux(_T_353, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 277:12] + node _T_355 = mux(_T_347, _T_352, _T_354) @[dbg.scala 275:26] + dbg_nxtstate <= _T_355 @[dbg.scala 275:20] + node _T_356 = bits(dmstatus_reg, 9, 9) @[dbg.scala 278:35] + node _T_357 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 278:54] + node _T_358 = and(_T_356, _T_357) @[dbg.scala 278:39] + node _T_359 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 278:75] + node _T_360 = eq(_T_359, UInt<1>("h00")) @[dbg.scala 278:61] + node _T_361 = and(_T_358, _T_360) @[dbg.scala 278:59] + node _T_362 = and(_T_361, dmcontrol_wren_Q) @[dbg.scala 278:80] + node _T_363 = or(_T_362, command_wren) @[dbg.scala 278:99] + node _T_364 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 279:22] + node _T_365 = or(_T_363, _T_364) @[dbg.scala 278:114] + node _T_366 = bits(dmstatus_reg, 9, 9) @[dbg.scala 279:42] + node _T_367 = or(_T_366, io.dec_tlu_mpc_halted_only) @[dbg.scala 279:46] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dbg.scala 279:28] + node _T_369 = or(_T_365, _T_368) @[dbg.scala 279:26] + dbg_state_en <= _T_369 @[dbg.scala 278:20] + node _T_370 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 280:60] + node _T_371 = and(dbg_state_en, _T_370) @[dbg.scala 280:44] + abstractcs_busy_wren <= _T_371 @[dbg.scala 280:28] abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 281:27] - node _T_387 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 282:58] - node _T_388 = and(dbg_state_en, _T_387) @[dbg.scala 282:42] - node _T_389 = bits(_T_388, 0, 0) @[dbg.scala 282:87] - io.dbg_resume_req <= _T_389 @[dbg.scala 282:25] - node _T_390 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:59] - node _T_391 = and(dmcontrol_wren_Q, _T_390) @[dbg.scala 283:44] - node _T_392 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 283:81] - node _T_393 = not(_T_392) @[dbg.scala 283:67] - node _T_394 = and(_T_391, _T_393) @[dbg.scala 283:64] - node _T_395 = bits(_T_394, 0, 0) @[dbg.scala 283:102] - io.dbg_halt_req <= _T_395 @[dbg.scala 283:23] + node _T_372 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 282:58] + node _T_373 = and(dbg_state_en, _T_372) @[dbg.scala 282:42] + node _T_374 = bits(_T_373, 0, 0) @[dbg.scala 282:87] + io.dbg_resume_req <= _T_374 @[dbg.scala 282:25] + node _T_375 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:59] + node _T_376 = and(dmcontrol_wren_Q, _T_375) @[dbg.scala 283:44] + node _T_377 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 283:81] + node _T_378 = not(_T_377) @[dbg.scala 283:67] + node _T_379 = and(_T_376, _T_378) @[dbg.scala 283:64] + node _T_380 = bits(_T_379, 0, 0) @[dbg.scala 283:102] + io.dbg_halt_req <= _T_380 @[dbg.scala 283:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_396 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30] - when _T_396 : @[Conditional.scala 39:67] - node _T_397 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 286:40] - node _T_398 = bits(abstractcs_reg, 10, 8) @[dbg.scala 286:77] - node _T_399 = orr(_T_398) @[dbg.scala 286:85] - node _T_400 = mux(_T_399, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 286:62] - node _T_401 = mux(_T_397, UInt<3>("h00"), _T_400) @[dbg.scala 286:26] - dbg_nxtstate <= _T_401 @[dbg.scala 286:20] - node _T_402 = bits(abstractcs_reg, 10, 8) @[dbg.scala 287:71] - node _T_403 = orr(_T_402) @[dbg.scala 287:79] - node _T_404 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_403) @[dbg.scala 287:55] - node _T_405 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 287:98] - node _T_406 = or(_T_404, _T_405) @[dbg.scala 287:83] - dbg_state_en <= _T_406 @[dbg.scala 287:20] - node _T_407 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59] - node _T_408 = and(dmcontrol_wren_Q, _T_407) @[dbg.scala 288:44] - node _T_409 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81] - node _T_410 = not(_T_409) @[dbg.scala 288:67] - node _T_411 = and(_T_408, _T_410) @[dbg.scala 288:64] - node _T_412 = bits(_T_411, 0, 0) @[dbg.scala 288:102] - io.dbg_halt_req <= _T_412 @[dbg.scala 288:23] + node _T_381 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30] + when _T_381 : @[Conditional.scala 39:67] + node _T_382 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 286:40] + node _T_383 = bits(abstractcs_reg, 10, 8) @[dbg.scala 286:77] + node _T_384 = orr(_T_383) @[dbg.scala 286:85] + node _T_385 = mux(_T_384, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 286:62] + node _T_386 = mux(_T_382, UInt<3>("h00"), _T_385) @[dbg.scala 286:26] + dbg_nxtstate <= _T_386 @[dbg.scala 286:20] + node _T_387 = bits(abstractcs_reg, 10, 8) @[dbg.scala 287:71] + node _T_388 = orr(_T_387) @[dbg.scala 287:79] + node _T_389 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_388) @[dbg.scala 287:55] + node _T_390 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 287:98] + node _T_391 = or(_T_389, _T_390) @[dbg.scala 287:83] + dbg_state_en <= _T_391 @[dbg.scala 287:20] + node _T_392 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59] + node _T_393 = and(dmcontrol_wren_Q, _T_392) @[dbg.scala 288:44] + node _T_394 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81] + node _T_395 = not(_T_394) @[dbg.scala 288:67] + node _T_396 = and(_T_393, _T_395) @[dbg.scala 288:64] + node _T_397 = bits(_T_396, 0, 0) @[dbg.scala 288:102] + io.dbg_halt_req <= _T_397 @[dbg.scala 288:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_413 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30] - when _T_413 : @[Conditional.scala 39:67] - node _T_414 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40] - node _T_415 = mux(_T_414, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 291:26] - dbg_nxtstate <= _T_415 @[dbg.scala 291:20] - node _T_416 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:59] - node _T_417 = or(io.core_dbg_cmd_done, _T_416) @[dbg.scala 292:44] - dbg_state_en <= _T_417 @[dbg.scala 292:20] - node _T_418 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59] - node _T_419 = and(dmcontrol_wren_Q, _T_418) @[dbg.scala 293:44] - node _T_420 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81] - node _T_421 = not(_T_420) @[dbg.scala 293:67] - node _T_422 = and(_T_419, _T_421) @[dbg.scala 293:64] - node _T_423 = bits(_T_422, 0, 0) @[dbg.scala 293:102] - io.dbg_halt_req <= _T_423 @[dbg.scala 293:23] + node _T_398 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30] + when _T_398 : @[Conditional.scala 39:67] + node _T_399 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40] + node _T_400 = mux(_T_399, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 291:26] + dbg_nxtstate <= _T_400 @[dbg.scala 291:20] + node _T_401 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:59] + node _T_402 = or(io.core_dbg_cmd_done, _T_401) @[dbg.scala 292:44] + dbg_state_en <= _T_402 @[dbg.scala 292:20] + node _T_403 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59] + node _T_404 = and(dmcontrol_wren_Q, _T_403) @[dbg.scala 293:44] + node _T_405 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81] + node _T_406 = not(_T_405) @[dbg.scala 293:67] + node _T_407 = and(_T_404, _T_406) @[dbg.scala 293:64] + node _T_408 = bits(_T_407, 0, 0) @[dbg.scala 293:102] + io.dbg_halt_req <= _T_408 @[dbg.scala 293:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_424 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30] - when _T_424 : @[Conditional.scala 39:67] - node _T_425 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40] - node _T_426 = mux(_T_425, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 296:26] - dbg_nxtstate <= _T_426 @[dbg.scala 296:20] + node _T_409 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30] + when _T_409 : @[Conditional.scala 39:67] + node _T_410 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40] + node _T_411 = mux(_T_410, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 296:26] + dbg_nxtstate <= _T_411 @[dbg.scala 296:20] dbg_state_en <= UInt<1>("h01") @[dbg.scala 297:20] abstractcs_busy_wren <= dbg_state_en @[dbg.scala 298:28] abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 299:27] - node _T_427 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 300:59] - node _T_428 = and(dmcontrol_wren_Q, _T_427) @[dbg.scala 300:44] - node _T_429 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 300:81] - node _T_430 = not(_T_429) @[dbg.scala 300:67] - node _T_431 = and(_T_428, _T_430) @[dbg.scala 300:64] - node _T_432 = bits(_T_431, 0, 0) @[dbg.scala 300:102] - io.dbg_halt_req <= _T_432 @[dbg.scala 300:23] + node _T_412 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 300:59] + node _T_413 = and(dmcontrol_wren_Q, _T_412) @[dbg.scala 300:44] + node _T_414 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 300:81] + node _T_415 = not(_T_414) @[dbg.scala 300:67] + node _T_416 = and(_T_413, _T_415) @[dbg.scala 300:64] + node _T_417 = bits(_T_416, 0, 0) @[dbg.scala 300:102] + io.dbg_halt_req <= _T_417 @[dbg.scala 300:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_433 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30] - when _T_433 : @[Conditional.scala 39:67] + node _T_418 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30] + when _T_418 : @[Conditional.scala 39:67] dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 303:20] - node _T_434 = bits(dmstatus_reg, 17, 17) @[dbg.scala 304:35] - node _T_435 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 304:55] - node _T_436 = or(_T_434, _T_435) @[dbg.scala 304:40] - dbg_state_en <= _T_436 @[dbg.scala 304:20] - node _T_437 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59] - node _T_438 = and(dmcontrol_wren_Q, _T_437) @[dbg.scala 305:44] - node _T_439 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81] - node _T_440 = not(_T_439) @[dbg.scala 305:67] - node _T_441 = and(_T_438, _T_440) @[dbg.scala 305:64] - node _T_442 = bits(_T_441, 0, 0) @[dbg.scala 305:102] - io.dbg_halt_req <= _T_442 @[dbg.scala 305:23] + node _T_419 = bits(dmstatus_reg, 17, 17) @[dbg.scala 304:35] + node _T_420 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 304:55] + node _T_421 = or(_T_419, _T_420) @[dbg.scala 304:40] + dbg_state_en <= _T_421 @[dbg.scala 304:20] + node _T_422 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59] + node _T_423 = and(dmcontrol_wren_Q, _T_422) @[dbg.scala 305:44] + node _T_424 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81] + node _T_425 = not(_T_424) @[dbg.scala 305:67] + node _T_426 = and(_T_423, _T_425) @[dbg.scala 305:64] + node _T_427 = bits(_T_426, 0, 0) @[dbg.scala 305:102] + io.dbg_halt_req <= _T_427 @[dbg.scala 305:23] skip @[Conditional.scala 39:67] - node _T_443 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 308:52] - node _T_444 = bits(_T_443, 0, 0) @[Bitwise.scala 72:15] - node _T_445 = mux(_T_444, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_446 = and(_T_445, data0_reg) @[dbg.scala 308:71] - node _T_447 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 308:110] + node _T_428 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 308:52] + node _T_429 = bits(_T_428, 0, 0) @[Bitwise.scala 72:15] + node _T_430 = mux(_T_429, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_431 = and(_T_430, data0_reg) @[dbg.scala 308:71] + node _T_432 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 308:110] + node _T_433 = bits(_T_432, 0, 0) @[Bitwise.scala 72:15] + node _T_434 = mux(_T_433, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_435 = and(_T_434, data1_reg) @[dbg.scala 308:122] + node _T_436 = or(_T_431, _T_435) @[dbg.scala 308:83] + node _T_437 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 309:30] + node _T_438 = bits(_T_437, 0, 0) @[Bitwise.scala 72:15] + node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_440 = and(_T_439, dmcontrol_reg) @[dbg.scala 309:43] + node _T_441 = or(_T_436, _T_440) @[dbg.scala 308:134] + node _T_442 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 309:86] + node _T_443 = bits(_T_442, 0, 0) @[Bitwise.scala 72:15] + node _T_444 = mux(_T_443, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_445 = and(_T_444, dmstatus_reg) @[dbg.scala 309:99] + node _T_446 = or(_T_441, _T_445) @[dbg.scala 309:59] + node _T_447 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 310:30] node _T_448 = bits(_T_447, 0, 0) @[Bitwise.scala 72:15] node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_450 = and(_T_449, data1_reg) @[dbg.scala 308:122] - node _T_451 = or(_T_446, _T_450) @[dbg.scala 308:83] - node _T_452 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 309:30] + node _T_450 = and(_T_449, abstractcs_reg) @[dbg.scala 310:43] + node _T_451 = or(_T_446, _T_450) @[dbg.scala 309:114] + node _T_452 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 310:87] node _T_453 = bits(_T_452, 0, 0) @[Bitwise.scala 72:15] node _T_454 = mux(_T_453, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_455 = and(_T_454, dmcontrol_reg) @[dbg.scala 309:43] - node _T_456 = or(_T_451, _T_455) @[dbg.scala 308:134] - node _T_457 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 309:86] + node _T_455 = and(_T_454, command_reg) @[dbg.scala 310:100] + node _T_456 = or(_T_451, _T_455) @[dbg.scala 310:60] + node _T_457 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 311:30] node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_460 = and(_T_459, dmstatus_reg) @[dbg.scala 309:99] - node _T_461 = or(_T_456, _T_460) @[dbg.scala 309:59] - node _T_462 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 310:30] + node _T_460 = and(_T_459, haltsum0_reg) @[dbg.scala 311:43] + node _T_461 = or(_T_456, _T_460) @[dbg.scala 310:114] + node _T_462 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 311:85] node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15] node _T_464 = mux(_T_463, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_465 = and(_T_464, abstractcs_reg) @[dbg.scala 310:43] - node _T_466 = or(_T_461, _T_465) @[dbg.scala 309:114] - node _T_467 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 310:87] + node _T_465 = and(_T_464, sbcs_reg) @[dbg.scala 311:98] + node _T_466 = or(_T_461, _T_465) @[dbg.scala 311:58] + node _T_467 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 312:30] node _T_468 = bits(_T_467, 0, 0) @[Bitwise.scala 72:15] node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_470 = and(_T_469, command_reg) @[dbg.scala 310:100] - node _T_471 = or(_T_466, _T_470) @[dbg.scala 310:60] - node _T_472 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 311:30] + node _T_470 = and(_T_469, sbaddress0_reg) @[dbg.scala 312:43] + node _T_471 = or(_T_466, _T_470) @[dbg.scala 311:109] + node _T_472 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 312:87] node _T_473 = bits(_T_472, 0, 0) @[Bitwise.scala 72:15] node _T_474 = mux(_T_473, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_475 = and(_T_474, haltsum0_reg) @[dbg.scala 311:43] - node _T_476 = or(_T_471, _T_475) @[dbg.scala 310:114] - node _T_477 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 311:85] + node _T_475 = and(_T_474, sbdata0_reg) @[dbg.scala 312:100] + node _T_476 = or(_T_471, _T_475) @[dbg.scala 312:60] + node _T_477 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 313:30] node _T_478 = bits(_T_477, 0, 0) @[Bitwise.scala 72:15] node _T_479 = mux(_T_478, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_480 = and(_T_479, sbcs_reg) @[dbg.scala 311:98] - node _T_481 = or(_T_476, _T_480) @[dbg.scala 311:58] - node _T_482 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 312:30] - node _T_483 = bits(_T_482, 0, 0) @[Bitwise.scala 72:15] - node _T_484 = mux(_T_483, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_485 = and(_T_484, sbaddress0_reg) @[dbg.scala 312:43] - node _T_486 = or(_T_481, _T_485) @[dbg.scala 311:109] - node _T_487 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 312:87] - node _T_488 = bits(_T_487, 0, 0) @[Bitwise.scala 72:15] - node _T_489 = mux(_T_488, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_490 = and(_T_489, sbdata0_reg) @[dbg.scala 312:100] - node _T_491 = or(_T_486, _T_490) @[dbg.scala 312:60] - node _T_492 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 313:30] - node _T_493 = bits(_T_492, 0, 0) @[Bitwise.scala 72:15] - node _T_494 = mux(_T_493, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_495 = and(_T_494, sbdata1_reg) @[dbg.scala 313:43] - node dmi_reg_rdata_din = or(_T_491, _T_495) @[dbg.scala 312:114] - node _T_496 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 315:49] - node _T_497 = and(_T_496, temp_rst) @[dbg.scala 315:63] - node _T_498 = asAsyncReset(_T_497) @[dbg.scala 315:87] - reg _T_499 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_498, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_480 = and(_T_479, sbdata1_reg) @[dbg.scala 313:43] + node dmi_reg_rdata_din = or(_T_476, _T_480) @[dbg.scala 312:114] + node _T_481 = and(dbg_dm_rst_l, temp_rst) @[dbg.scala 315:62] + node _T_482 = asAsyncReset(_T_481) @[dbg.scala 315:86] + reg _T_483 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_482, UInt<1>("h00"))) @[Reg.scala 27:20] when dbg_state_en : @[Reg.scala 28:19] - _T_499 <= dbg_nxtstate @[Reg.scala 28:23] + _T_483 <= dbg_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - dbg_state <= _T_499 @[dbg.scala 315:13] - node _T_500 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 320:56] - node _T_501 = asAsyncReset(_T_500) @[dbg.scala 320:83] - reg _T_502 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_501, UInt<1>("h00"))) @[Reg.scala 27:20] + dbg_state <= _T_483 @[dbg.scala 315:13] + node _T_484 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 320:82] + reg _T_485 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_484, UInt<1>("h00"))) @[Reg.scala 27:20] when io.dmi_reg_en : @[Reg.scala 28:19] - _T_502 <= dmi_reg_rdata_din @[Reg.scala 28:23] + _T_485 <= dmi_reg_rdata_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.dmi_reg_rdata <= _T_502 @[dbg.scala 320:20] - node _T_503 = bits(command_reg, 31, 24) @[dbg.scala 324:53] - node _T_504 = eq(_T_503, UInt<2>("h02")) @[dbg.scala 324:62] - node _T_505 = bits(data1_reg, 31, 2) @[dbg.scala 324:88] - node _T_506 = cat(_T_505, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_507 = bits(command_reg, 11, 0) @[dbg.scala 324:133] - node _T_508 = cat(UInt<20>("h00"), _T_507) @[Cat.scala 29:58] - node _T_509 = mux(_T_504, _T_506, _T_508) @[dbg.scala 324:40] - io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_509 @[dbg.scala 324:34] - node _T_510 = bits(data0_reg, 31, 0) @[dbg.scala 325:50] - io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_510 @[dbg.scala 325:38] - node _T_511 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 326:50] - node _T_512 = bits(abstractcs_reg, 10, 8) @[dbg.scala 326:91] - node _T_513 = orr(_T_512) @[dbg.scala 326:99] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[dbg.scala 326:75] - node _T_515 = and(_T_511, _T_514) @[dbg.scala 326:73] - node _T_516 = and(_T_515, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 326:104] - node _T_517 = bits(_T_516, 0, 0) @[dbg.scala 326:141] - io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_517 @[dbg.scala 326:35] - node _T_518 = bits(command_reg, 16, 16) @[dbg.scala 327:49] - node _T_519 = bits(_T_518, 0, 0) @[dbg.scala 327:60] - io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_519 @[dbg.scala 327:35] - node _T_520 = bits(command_reg, 31, 24) @[dbg.scala 328:53] - node _T_521 = eq(_T_520, UInt<2>("h02")) @[dbg.scala 328:62] - node _T_522 = bits(command_reg, 15, 12) @[dbg.scala 328:108] - node _T_523 = eq(_T_522, UInt<1>("h00")) @[dbg.scala 328:117] - node _T_524 = cat(UInt<1>("h00"), _T_523) @[Cat.scala 29:58] - node _T_525 = mux(_T_521, UInt<2>("h02"), _T_524) @[dbg.scala 328:40] - io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_525 @[dbg.scala 328:34] - node _T_526 = bits(command_reg, 21, 20) @[dbg.scala 329:33] - io.dbg_cmd_size <= _T_526 @[dbg.scala 329:19] - node _T_527 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 330:47] - node _T_528 = bits(abstractcs_reg, 10, 8) @[dbg.scala 330:88] - node _T_529 = orr(_T_528) @[dbg.scala 330:96] - node _T_530 = eq(_T_529, UInt<1>("h00")) @[dbg.scala 330:72] - node _T_531 = and(_T_527, _T_530) @[dbg.scala 330:70] - node _T_532 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 330:114] - node _T_533 = or(_T_531, _T_532) @[dbg.scala 330:101] - node _T_534 = bits(_T_533, 0, 0) @[dbg.scala 330:143] - io.dbg_dma_io.dbg_dma_bubble <= _T_534 @[dbg.scala 330:32] + io.dmi_reg_rdata <= _T_485 @[dbg.scala 320:20] + node _T_486 = bits(command_reg, 31, 24) @[dbg.scala 324:53] + node _T_487 = eq(_T_486, UInt<2>("h02")) @[dbg.scala 324:62] + node _T_488 = bits(data1_reg, 31, 2) @[dbg.scala 324:88] + node _T_489 = cat(_T_488, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_490 = bits(command_reg, 11, 0) @[dbg.scala 324:138] + node _T_491 = cat(UInt<20>("h00"), _T_490) @[Cat.scala 29:58] + node _T_492 = mux(_T_487, _T_489, _T_491) @[dbg.scala 324:40] + io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_492 @[dbg.scala 324:34] + node _T_493 = bits(data0_reg, 31, 0) @[dbg.scala 325:50] + io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_493 @[dbg.scala 325:38] + node _T_494 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 326:50] + node _T_495 = bits(abstractcs_reg, 10, 8) @[dbg.scala 326:91] + node _T_496 = orr(_T_495) @[dbg.scala 326:99] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[dbg.scala 326:75] + node _T_498 = and(_T_494, _T_497) @[dbg.scala 326:73] + node _T_499 = and(_T_498, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 326:104] + node _T_500 = bits(_T_499, 0, 0) @[dbg.scala 326:141] + io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_500 @[dbg.scala 326:35] + node _T_501 = bits(command_reg, 16, 16) @[dbg.scala 327:49] + node _T_502 = bits(_T_501, 0, 0) @[dbg.scala 327:60] + io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_502 @[dbg.scala 327:35] + node _T_503 = bits(command_reg, 31, 24) @[dbg.scala 328:53] + node _T_504 = eq(_T_503, UInt<2>("h02")) @[dbg.scala 328:62] + node _T_505 = bits(command_reg, 15, 12) @[dbg.scala 328:113] + node _T_506 = eq(_T_505, UInt<1>("h00")) @[dbg.scala 328:122] + node _T_507 = cat(UInt<1>("h00"), _T_506) @[Cat.scala 29:58] + node _T_508 = mux(_T_504, UInt<2>("h02"), _T_507) @[dbg.scala 328:40] + io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_508 @[dbg.scala 328:34] + node _T_509 = bits(command_reg, 21, 20) @[dbg.scala 329:33] + io.dbg_cmd_size <= _T_509 @[dbg.scala 329:19] + node _T_510 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 330:47] + node _T_511 = bits(abstractcs_reg, 10, 8) @[dbg.scala 330:88] + node _T_512 = orr(_T_511) @[dbg.scala 330:96] + node _T_513 = eq(_T_512, UInt<1>("h00")) @[dbg.scala 330:72] + node _T_514 = and(_T_510, _T_513) @[dbg.scala 330:70] + node _T_515 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 330:114] + node _T_516 = or(_T_514, _T_515) @[dbg.scala 330:101] + node _T_517 = bits(_T_516, 0, 0) @[dbg.scala 330:143] + io.dbg_dma_io.dbg_dma_bubble <= _T_517 @[dbg.scala 330:32] wire sb_nxtstate : UInt<4> sb_nxtstate <= UInt<4>("h00") sb_nxtstate <= UInt<4>("h00") @[dbg.scala 333:15] @@ -1028,288 +1009,287 @@ circuit dbg : sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 337:21] sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 338:20] sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 339:24] - node _T_535 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30] - when _T_535 : @[Conditional.scala 40:58] - node _T_536 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 342:25] - sb_nxtstate <= _T_536 @[dbg.scala 342:19] - node _T_537 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 343:39] - node _T_538 = or(_T_537, sbreadonaddr_access) @[dbg.scala 343:61] - sb_state_en <= _T_538 @[dbg.scala 343:19] + node _T_518 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30] + when _T_518 : @[Conditional.scala 40:58] + node _T_519 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 342:25] + sb_nxtstate <= _T_519 @[dbg.scala 342:19] + node _T_520 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 343:39] + node _T_521 = or(_T_520, sbreadonaddr_access) @[dbg.scala 343:61] + sb_state_en <= _T_521 @[dbg.scala 343:19] sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 344:24] sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 345:23] - node _T_539 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 346:56] - node _T_540 = orr(_T_539) @[dbg.scala 346:65] - node _T_541 = and(sbcs_wren, _T_540) @[dbg.scala 346:38] - sbcs_sberror_wren <= _T_541 @[dbg.scala 346:25] - node _T_542 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 347:44] - node _T_543 = eq(_T_542, UInt<1>("h00")) @[dbg.scala 347:27] - node _T_544 = bits(sbcs_reg, 14, 12) @[dbg.scala 347:63] - node _T_545 = and(_T_543, _T_544) @[dbg.scala 347:53] - sbcs_sberror_din <= _T_545 @[dbg.scala 347:24] + node _T_522 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 346:56] + node _T_523 = orr(_T_522) @[dbg.scala 346:65] + node _T_524 = and(sbcs_wren, _T_523) @[dbg.scala 346:38] + sbcs_sberror_wren <= _T_524 @[dbg.scala 346:25] + node _T_525 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 347:44] + node _T_526 = not(_T_525) @[dbg.scala 347:27] + node _T_527 = bits(sbcs_reg, 14, 12) @[dbg.scala 347:63] + node _T_528 = and(_T_526, _T_527) @[dbg.scala 347:53] + sbcs_sberror_din <= _T_528 @[dbg.scala 347:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_546 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30] - when _T_546 : @[Conditional.scala 39:67] - node _T_547 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 350:41] - node _T_548 = mux(_T_547, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 350:25] - sb_nxtstate <= _T_548 @[dbg.scala 350:19] - node _T_549 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 351:40] - node _T_550 = or(_T_549, sbcs_illegal_size) @[dbg.scala 351:57] - sb_state_en <= _T_550 @[dbg.scala 351:19] - node _T_551 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 352:43] - sbcs_sberror_wren <= _T_551 @[dbg.scala 352:25] - node _T_552 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[dbg.scala 353:30] - sbcs_sberror_din <= _T_552 @[dbg.scala 353:24] + node _T_529 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30] + when _T_529 : @[Conditional.scala 39:67] + node _T_530 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 350:41] + node _T_531 = mux(_T_530, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 350:25] + sb_nxtstate <= _T_531 @[dbg.scala 350:19] + node _T_532 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 351:40] + node _T_533 = or(_T_532, sbcs_illegal_size) @[dbg.scala 351:57] + sb_state_en <= _T_533 @[dbg.scala 351:19] + node _T_534 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 352:43] + sbcs_sberror_wren <= _T_534 @[dbg.scala 352:25] + node _T_535 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 353:30] + sbcs_sberror_din <= _T_535 @[dbg.scala 353:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_553 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30] - when _T_553 : @[Conditional.scala 39:67] - node _T_554 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 356:41] - node _T_555 = mux(_T_554, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 356:25] - sb_nxtstate <= _T_555 @[dbg.scala 356:19] - node _T_556 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 357:40] - node _T_557 = or(_T_556, sbcs_illegal_size) @[dbg.scala 357:57] - sb_state_en <= _T_557 @[dbg.scala 357:19] - node _T_558 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 358:43] - sbcs_sberror_wren <= _T_558 @[dbg.scala 358:25] - node _T_559 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[dbg.scala 359:30] - sbcs_sberror_din <= _T_559 @[dbg.scala 359:24] + node _T_536 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30] + when _T_536 : @[Conditional.scala 39:67] + node _T_537 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 356:41] + node _T_538 = mux(_T_537, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 356:25] + sb_nxtstate <= _T_538 @[dbg.scala 356:19] + node _T_539 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 357:40] + node _T_540 = or(_T_539, sbcs_illegal_size) @[dbg.scala 357:57] + sb_state_en <= _T_540 @[dbg.scala 357:19] + node _T_541 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 358:43] + sbcs_sberror_wren <= _T_541 @[dbg.scala 358:25] + node _T_542 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 359:30] + sbcs_sberror_din <= _T_542 @[dbg.scala 359:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_560 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30] - when _T_560 : @[Conditional.scala 39:67] + node _T_543 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30] + when _T_543 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h07") @[dbg.scala 362:19] - node _T_561 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 363:38] - sb_state_en <= _T_561 @[dbg.scala 363:19] + node _T_544 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 363:38] + sb_state_en <= _T_544 @[dbg.scala 363:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_562 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30] - when _T_562 : @[Conditional.scala 39:67] - node _T_563 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 366:48] - node _T_564 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 366:95] - node _T_565 = mux(_T_563, UInt<4>("h08"), _T_564) @[dbg.scala 366:25] - sb_nxtstate <= _T_565 @[dbg.scala 366:19] - node _T_566 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 367:45] - node _T_567 = and(_T_566, io.dbg_bus_clk_en) @[dbg.scala 367:70] - sb_state_en <= _T_567 @[dbg.scala 367:19] + node _T_545 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30] + when _T_545 : @[Conditional.scala 39:67] + node _T_546 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 366:48] + node _T_547 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 366:95] + node _T_548 = mux(_T_546, UInt<4>("h08"), _T_547) @[dbg.scala 366:25] + sb_nxtstate <= _T_548 @[dbg.scala 366:19] + node _T_549 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 367:45] + node _T_550 = and(_T_549, io.dbg_bus_clk_en) @[dbg.scala 367:70] + sb_state_en <= _T_550 @[dbg.scala 367:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_568 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30] - when _T_568 : @[Conditional.scala 39:67] + node _T_551 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30] + when _T_551 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h08") @[dbg.scala 370:19] - node _T_569 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 371:44] - sb_state_en <= _T_569 @[dbg.scala 371:19] + node _T_552 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 371:44] + sb_state_en <= _T_552 @[dbg.scala 371:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_570 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30] - when _T_570 : @[Conditional.scala 39:67] + node _T_553 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30] + when _T_553 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h08") @[dbg.scala 374:19] - node _T_571 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 375:44] - sb_state_en <= _T_571 @[dbg.scala 375:19] + node _T_554 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 375:44] + sb_state_en <= _T_554 @[dbg.scala 375:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_572 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30] - when _T_572 : @[Conditional.scala 39:67] + node _T_555 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30] + when _T_555 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h09") @[dbg.scala 378:19] - node _T_573 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 379:38] - sb_state_en <= _T_573 @[dbg.scala 379:19] - node _T_574 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 380:40] - sbcs_sberror_wren <= _T_574 @[dbg.scala 380:25] - sbcs_sberror_din <= UInt<2>("h02") @[dbg.scala 381:24] + node _T_556 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 379:38] + sb_state_en <= _T_556 @[dbg.scala 379:19] + node _T_557 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 380:40] + sbcs_sberror_wren <= _T_557 @[dbg.scala 380:25] + sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 381:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_575 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30] - when _T_575 : @[Conditional.scala 39:67] + node _T_558 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30] + when _T_558 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h09") @[dbg.scala 384:19] - node _T_576 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 385:39] - sb_state_en <= _T_576 @[dbg.scala 385:19] - node _T_577 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 386:40] - sbcs_sberror_wren <= _T_577 @[dbg.scala 386:25] - sbcs_sberror_din <= UInt<2>("h02") @[dbg.scala 387:24] + node _T_559 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 385:39] + sb_state_en <= _T_559 @[dbg.scala 385:19] + node _T_560 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 386:40] + sbcs_sberror_wren <= _T_560 @[dbg.scala 386:25] + sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 387:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_578 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30] - when _T_578 : @[Conditional.scala 39:67] + node _T_561 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30] + when _T_561 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h00") @[dbg.scala 390:19] sb_state_en <= UInt<1>("h01") @[dbg.scala 391:19] sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 392:24] sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 393:23] - node _T_579 = bits(sbcs_reg, 16, 16) @[dbg.scala 394:39] - sbaddress0_reg_wren1 <= _T_579 @[dbg.scala 394:28] + node _T_562 = bits(sbcs_reg, 16, 16) @[dbg.scala 394:39] + sbaddress0_reg_wren1 <= _T_562 @[dbg.scala 394:28] skip @[Conditional.scala 39:67] - node _T_580 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 397:47] - node _T_581 = asAsyncReset(_T_580) @[dbg.scala 397:74] - reg _T_582 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_581, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_563 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 397:73] + reg _T_564 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_563, UInt<1>("h00"))) @[Reg.scala 27:20] when sb_state_en : @[Reg.scala 28:19] - _T_582 <= sb_nxtstate @[Reg.scala 28:23] + _T_564 <= sb_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - sb_state <= _T_582 @[dbg.scala 397:12] - node _T_583 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 401:41] - sb_bus_cmd_read <= _T_583 @[dbg.scala 401:19] - node _T_584 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 402:47] - sb_bus_cmd_write_addr <= _T_584 @[dbg.scala 402:25] - node _T_585 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 403:46] - sb_bus_cmd_write_data <= _T_585 @[dbg.scala 403:25] - node _T_586 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 404:40] - sb_bus_rsp_read <= _T_586 @[dbg.scala 404:19] - node _T_587 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 405:41] - sb_bus_rsp_write <= _T_587 @[dbg.scala 405:20] - node _T_588 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 406:62] - node _T_589 = orr(_T_588) @[dbg.scala 406:69] - node _T_590 = and(sb_bus_rsp_read, _T_589) @[dbg.scala 406:39] - node _T_591 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 406:115] - node _T_592 = orr(_T_591) @[dbg.scala 406:122] - node _T_593 = and(sb_bus_rsp_write, _T_592) @[dbg.scala 406:92] - node _T_594 = or(_T_590, _T_593) @[dbg.scala 406:73] - sb_bus_rsp_error <= _T_594 @[dbg.scala 406:20] - node _T_595 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 407:36] - node _T_596 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 407:71] - node _T_597 = or(_T_595, _T_596) @[dbg.scala 407:59] - node _T_598 = bits(_T_597, 0, 0) @[dbg.scala 407:106] - io.sb_axi.aw.valid <= _T_598 @[dbg.scala 407:22] + sb_state <= _T_564 @[dbg.scala 397:12] + node _T_565 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 401:41] + sb_bus_cmd_read <= _T_565 @[dbg.scala 401:19] + node _T_566 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 402:47] + sb_bus_cmd_write_addr <= _T_566 @[dbg.scala 402:25] + node _T_567 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 403:46] + sb_bus_cmd_write_data <= _T_567 @[dbg.scala 403:25] + node _T_568 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 404:40] + sb_bus_rsp_read <= _T_568 @[dbg.scala 404:19] + node _T_569 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 405:41] + sb_bus_rsp_write <= _T_569 @[dbg.scala 405:20] + node _T_570 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 406:62] + node _T_571 = orr(_T_570) @[dbg.scala 406:69] + node _T_572 = and(sb_bus_rsp_read, _T_571) @[dbg.scala 406:39] + node _T_573 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 406:115] + node _T_574 = orr(_T_573) @[dbg.scala 406:122] + node _T_575 = and(sb_bus_rsp_write, _T_574) @[dbg.scala 406:92] + node _T_576 = or(_T_572, _T_575) @[dbg.scala 406:73] + sb_bus_rsp_error <= _T_576 @[dbg.scala 406:20] + node _T_577 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 407:36] + node _T_578 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 407:71] + node _T_579 = or(_T_577, _T_578) @[dbg.scala 407:59] + node _T_580 = bits(_T_579, 0, 0) @[dbg.scala 407:106] + io.sb_axi.aw.valid <= _T_580 @[dbg.scala 407:22] io.sb_axi.aw.bits.addr <= sbaddress0_reg @[dbg.scala 408:26] io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 409:24] - node _T_599 = bits(sbcs_reg, 19, 17) @[dbg.scala 410:37] - io.sb_axi.aw.bits.size <= _T_599 @[dbg.scala 410:26] + node _T_581 = bits(sbcs_reg, 19, 17) @[dbg.scala 410:37] + io.sb_axi.aw.bits.size <= _T_581 @[dbg.scala 410:26] io.sb_axi.aw.bits.prot <= UInt<1>("h00") @[dbg.scala 411:26] io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 412:27] - node _T_600 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 413:45] - io.sb_axi.aw.bits.region <= _T_600 @[dbg.scala 413:28] + node _T_582 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 413:45] + io.sb_axi.aw.bits.region <= _T_582 @[dbg.scala 413:28] io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 414:25] - io.sb_axi.aw.bits.burst <= UInt<1>("h01") @[dbg.scala 415:27] + io.sb_axi.aw.bits.burst <= UInt<2>("h01") @[dbg.scala 415:27] io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 416:25] io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 417:26] - node _T_601 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 418:35] - node _T_602 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 418:70] - node _T_603 = or(_T_601, _T_602) @[dbg.scala 418:58] - node _T_604 = bits(_T_603, 0, 0) @[dbg.scala 418:105] - io.sb_axi.w.valid <= _T_604 @[dbg.scala 418:21] - node _T_605 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:46] - node _T_606 = eq(_T_605, UInt<1>("h00")) @[dbg.scala 419:55] + node _T_583 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 418:35] + node _T_584 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 418:70] + node _T_585 = or(_T_583, _T_584) @[dbg.scala 418:58] + node _T_586 = bits(_T_585, 0, 0) @[dbg.scala 418:105] + io.sb_axi.w.valid <= _T_586 @[dbg.scala 418:21] + node _T_587 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:46] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[dbg.scala 419:55] + node _T_589 = bits(_T_588, 0, 0) @[Bitwise.scala 72:15] + node _T_590 = mux(_T_589, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_591 = bits(sbdata0_reg, 7, 0) @[dbg.scala 419:87] + node _T_592 = cat(_T_591, _T_591) @[Cat.scala 29:58] + node _T_593 = cat(_T_592, _T_592) @[Cat.scala 29:58] + node _T_594 = cat(_T_593, _T_593) @[Cat.scala 29:58] + node _T_595 = and(_T_590, _T_594) @[dbg.scala 419:65] + node _T_596 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:116] + node _T_597 = eq(_T_596, UInt<1>("h01")) @[dbg.scala 419:125] + node _T_598 = bits(_T_597, 0, 0) @[Bitwise.scala 72:15] + node _T_599 = mux(_T_598, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_600 = bits(sbdata0_reg, 15, 0) @[dbg.scala 419:159] + node _T_601 = cat(_T_600, _T_600) @[Cat.scala 29:58] + node _T_602 = cat(_T_601, _T_601) @[Cat.scala 29:58] + node _T_603 = and(_T_599, _T_602) @[dbg.scala 419:138] + node _T_604 = or(_T_595, _T_603) @[dbg.scala 419:96] + node _T_605 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:23] + node _T_606 = eq(_T_605, UInt<2>("h02")) @[dbg.scala 420:32] node _T_607 = bits(_T_606, 0, 0) @[Bitwise.scala 72:15] node _T_608 = mux(_T_607, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_609 = bits(sbdata0_reg, 7, 0) @[dbg.scala 419:87] + node _T_609 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:67] node _T_610 = cat(_T_609, _T_609) @[Cat.scala 29:58] - node _T_611 = cat(_T_610, _T_610) @[Cat.scala 29:58] - node _T_612 = cat(_T_611, _T_611) @[Cat.scala 29:58] - node _T_613 = and(_T_608, _T_612) @[dbg.scala 419:65] - node _T_614 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:116] - node _T_615 = eq(_T_614, UInt<1>("h01")) @[dbg.scala 419:125] - node _T_616 = bits(_T_615, 0, 0) @[Bitwise.scala 72:15] - node _T_617 = mux(_T_616, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_618 = bits(sbdata0_reg, 15, 0) @[dbg.scala 419:159] - node _T_619 = cat(_T_618, _T_618) @[Cat.scala 29:58] - node _T_620 = cat(_T_619, _T_619) @[Cat.scala 29:58] - node _T_621 = and(_T_617, _T_620) @[dbg.scala 419:138] - node _T_622 = or(_T_613, _T_621) @[dbg.scala 419:96] - node _T_623 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:23] - node _T_624 = eq(_T_623, UInt<2>("h02")) @[dbg.scala 420:32] - node _T_625 = bits(_T_624, 0, 0) @[Bitwise.scala 72:15] - node _T_626 = mux(_T_625, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_627 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:67] - node _T_628 = cat(_T_627, _T_627) @[Cat.scala 29:58] - node _T_629 = and(_T_626, _T_628) @[dbg.scala 420:45] - node _T_630 = or(_T_622, _T_629) @[dbg.scala 419:168] - node _T_631 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:97] - node _T_632 = eq(_T_631, UInt<2>("h03")) @[dbg.scala 420:106] - node _T_633 = bits(_T_632, 0, 0) @[Bitwise.scala 72:15] - node _T_634 = mux(_T_633, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_635 = bits(sbdata1_reg, 31, 0) @[dbg.scala 420:136] - node _T_636 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:156] - node _T_637 = cat(_T_635, _T_636) @[Cat.scala 29:58] - node _T_638 = and(_T_634, _T_637) @[dbg.scala 420:119] - node _T_639 = or(_T_630, _T_638) @[dbg.scala 420:77] - io.sb_axi.w.bits.data <= _T_639 @[dbg.scala 419:25] - node _T_640 = bits(sbcs_reg, 19, 17) @[dbg.scala 422:45] - node _T_641 = eq(_T_640, UInt<1>("h00")) @[dbg.scala 422:54] - node _T_642 = bits(_T_641, 0, 0) @[Bitwise.scala 72:15] - node _T_643 = mux(_T_642, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_644 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 422:99] - node _T_645 = dshl(UInt<8>("h01"), _T_644) @[dbg.scala 422:82] - node _T_646 = and(_T_643, _T_645) @[dbg.scala 422:67] - node _T_647 = bits(sbcs_reg, 19, 17) @[dbg.scala 423:22] - node _T_648 = eq(_T_647, UInt<1>("h01")) @[dbg.scala 423:31] + node _T_611 = and(_T_608, _T_610) @[dbg.scala 420:45] + node _T_612 = or(_T_604, _T_611) @[dbg.scala 419:168] + node _T_613 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:97] + node _T_614 = eq(_T_613, UInt<2>("h03")) @[dbg.scala 420:106] + node _T_615 = bits(_T_614, 0, 0) @[Bitwise.scala 72:15] + node _T_616 = mux(_T_615, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_617 = bits(sbdata1_reg, 31, 0) @[dbg.scala 420:136] + node _T_618 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:156] + node _T_619 = cat(_T_617, _T_618) @[Cat.scala 29:58] + node _T_620 = and(_T_616, _T_619) @[dbg.scala 420:119] + node _T_621 = or(_T_612, _T_620) @[dbg.scala 420:77] + io.sb_axi.w.bits.data <= _T_621 @[dbg.scala 419:25] + node _T_622 = bits(sbcs_reg, 19, 17) @[dbg.scala 422:45] + node _T_623 = eq(_T_622, UInt<1>("h00")) @[dbg.scala 422:54] + node _T_624 = bits(_T_623, 0, 0) @[Bitwise.scala 72:15] + node _T_625 = mux(_T_624, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_626 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 422:99] + node _T_627 = dshl(UInt<8>("h01"), _T_626) @[dbg.scala 422:82] + node _T_628 = and(_T_625, _T_627) @[dbg.scala 422:67] + node _T_629 = bits(sbcs_reg, 19, 17) @[dbg.scala 423:22] + node _T_630 = eq(_T_629, UInt<1>("h01")) @[dbg.scala 423:31] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 423:80] + node _T_634 = cat(_T_633, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_635 = dshl(UInt<8>("h03"), _T_634) @[dbg.scala 423:59] + node _T_636 = and(_T_632, _T_635) @[dbg.scala 423:44] + node _T_637 = or(_T_628, _T_636) @[dbg.scala 422:107] + node _T_638 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:22] + node _T_639 = eq(_T_638, UInt<2>("h02")) @[dbg.scala 424:31] + node _T_640 = bits(_T_639, 0, 0) @[Bitwise.scala 72:15] + node _T_641 = mux(_T_640, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_642 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 424:80] + node _T_643 = cat(_T_642, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_644 = dshl(UInt<8>("h0f"), _T_643) @[dbg.scala 424:59] + node _T_645 = and(_T_641, _T_644) @[dbg.scala 424:44] + node _T_646 = or(_T_637, _T_645) @[dbg.scala 423:97] + node _T_647 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:22] + node _T_648 = eq(_T_647, UInt<2>("h03")) @[dbg.scala 425:31] node _T_649 = bits(_T_648, 0, 0) @[Bitwise.scala 72:15] node _T_650 = mux(_T_649, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_651 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 423:80] - node _T_652 = cat(_T_651, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_653 = dshl(UInt<8>("h03"), _T_652) @[dbg.scala 423:59] - node _T_654 = and(_T_650, _T_653) @[dbg.scala 423:44] - node _T_655 = or(_T_646, _T_654) @[dbg.scala 422:107] - node _T_656 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:22] - node _T_657 = eq(_T_656, UInt<2>("h02")) @[dbg.scala 424:31] - node _T_658 = bits(_T_657, 0, 0) @[Bitwise.scala 72:15] - node _T_659 = mux(_T_658, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_660 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 424:80] - node _T_661 = cat(_T_660, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_662 = dshl(UInt<8>("h0f"), _T_661) @[dbg.scala 424:59] - node _T_663 = and(_T_659, _T_662) @[dbg.scala 424:44] - node _T_664 = or(_T_655, _T_663) @[dbg.scala 423:97] - node _T_665 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:22] - node _T_666 = eq(_T_665, UInt<2>("h03")) @[dbg.scala 425:31] - node _T_667 = bits(_T_666, 0, 0) @[Bitwise.scala 72:15] - node _T_668 = mux(_T_667, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_669 = and(_T_668, UInt<8>("h0ff")) @[dbg.scala 425:44] - node _T_670 = or(_T_664, _T_669) @[dbg.scala 424:95] - io.sb_axi.w.bits.strb <= _T_670 @[dbg.scala 422:25] + node _T_651 = and(_T_650, UInt<8>("h0ff")) @[dbg.scala 425:44] + node _T_652 = or(_T_646, _T_651) @[dbg.scala 424:100] + io.sb_axi.w.bits.strb <= _T_652 @[dbg.scala 422:25] io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 427:25] - node _T_671 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 428:35] - node _T_672 = bits(_T_671, 0, 0) @[dbg.scala 428:64] - io.sb_axi.ar.valid <= _T_672 @[dbg.scala 428:22] + node _T_653 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 428:35] + node _T_654 = bits(_T_653, 0, 0) @[dbg.scala 428:64] + io.sb_axi.ar.valid <= _T_654 @[dbg.scala 428:22] io.sb_axi.ar.bits.addr <= sbaddress0_reg @[dbg.scala 429:26] io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 430:24] - node _T_673 = bits(sbcs_reg, 19, 17) @[dbg.scala 431:37] - io.sb_axi.ar.bits.size <= _T_673 @[dbg.scala 431:26] + node _T_655 = bits(sbcs_reg, 19, 17) @[dbg.scala 431:37] + io.sb_axi.ar.bits.size <= _T_655 @[dbg.scala 431:26] io.sb_axi.ar.bits.prot <= UInt<1>("h00") @[dbg.scala 432:26] io.sb_axi.ar.bits.cache <= UInt<1>("h00") @[dbg.scala 433:27] - node _T_674 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 434:45] - io.sb_axi.ar.bits.region <= _T_674 @[dbg.scala 434:28] + node _T_656 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 434:45] + io.sb_axi.ar.bits.region <= _T_656 @[dbg.scala 434:28] io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 435:25] - io.sb_axi.ar.bits.burst <= UInt<1>("h01") @[dbg.scala 436:27] + io.sb_axi.ar.bits.burst <= UInt<2>("h01") @[dbg.scala 436:27] io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 437:25] io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 438:26] io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 439:21] io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 440:21] - node _T_675 = bits(sbcs_reg, 19, 17) @[dbg.scala 441:37] - node _T_676 = eq(_T_675, UInt<1>("h00")) @[dbg.scala 441:46] - node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] - node _T_678 = mux(_T_677, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_679 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 441:84] - node _T_680 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 441:115] - node _T_681 = mul(UInt<4>("h08"), _T_680) @[dbg.scala 441:99] - node _T_682 = dshr(_T_679, _T_681) @[dbg.scala 441:92] - node _T_683 = and(_T_682, UInt<64>("h0ff")) @[dbg.scala 441:123] - node _T_684 = and(_T_678, _T_683) @[dbg.scala 441:59] - node _T_685 = bits(sbcs_reg, 19, 17) @[dbg.scala 442:23] - node _T_686 = eq(_T_685, UInt<1>("h01")) @[dbg.scala 442:32] - node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] - node _T_688 = mux(_T_687, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_689 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 442:70] - node _T_690 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 442:102] - node _T_691 = mul(UInt<5>("h010"), _T_690) @[dbg.scala 442:86] - node _T_692 = dshr(_T_689, _T_691) @[dbg.scala 442:78] - node _T_693 = and(_T_692, UInt<64>("h0ffff")) @[dbg.scala 442:110] - node _T_694 = and(_T_688, _T_693) @[dbg.scala 442:45] - node _T_695 = or(_T_684, _T_694) @[dbg.scala 441:140] - node _T_696 = bits(sbcs_reg, 19, 17) @[dbg.scala 443:23] - node _T_697 = eq(_T_696, UInt<2>("h02")) @[dbg.scala 443:32] - node _T_698 = bits(_T_697, 0, 0) @[Bitwise.scala 72:15] - node _T_699 = mux(_T_698, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_700 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 443:70] - node _T_701 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 443:102] - node _T_702 = mul(UInt<6>("h020"), _T_701) @[dbg.scala 443:86] - node _T_703 = dshr(_T_700, _T_702) @[dbg.scala 443:78] - node _T_704 = and(_T_703, UInt<64>("h0ffffffff")) @[dbg.scala 443:107] - node _T_705 = and(_T_699, _T_704) @[dbg.scala 443:45] - node _T_706 = or(_T_695, _T_705) @[dbg.scala 442:129] - node _T_707 = bits(sbcs_reg, 19, 17) @[dbg.scala 444:23] - node _T_708 = eq(_T_707, UInt<2>("h03")) @[dbg.scala 444:32] - node _T_709 = bits(_T_708, 0, 0) @[Bitwise.scala 72:15] - node _T_710 = mux(_T_709, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_711 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 444:68] - node _T_712 = and(_T_710, _T_711) @[dbg.scala 444:45] - node _T_713 = or(_T_706, _T_712) @[dbg.scala 443:131] - sb_bus_rdata <= _T_713 @[dbg.scala 441:16] + node _T_657 = bits(sbcs_reg, 19, 17) @[dbg.scala 441:37] + node _T_658 = eq(_T_657, UInt<1>("h00")) @[dbg.scala 441:46] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 441:84] + node _T_662 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 441:115] + node _T_663 = mul(UInt<4>("h08"), _T_662) @[dbg.scala 441:99] + node _T_664 = dshr(_T_661, _T_663) @[dbg.scala 441:92] + node _T_665 = and(_T_664, UInt<64>("h0ff")) @[dbg.scala 441:123] + node _T_666 = and(_T_660, _T_665) @[dbg.scala 441:59] + node _T_667 = bits(sbcs_reg, 19, 17) @[dbg.scala 442:23] + node _T_668 = eq(_T_667, UInt<1>("h01")) @[dbg.scala 442:32] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 442:70] + node _T_672 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 442:102] + node _T_673 = mul(UInt<5>("h010"), _T_672) @[dbg.scala 442:86] + node _T_674 = dshr(_T_671, _T_673) @[dbg.scala 442:78] + node _T_675 = and(_T_674, UInt<64>("h0ffff")) @[dbg.scala 442:110] + node _T_676 = and(_T_670, _T_675) @[dbg.scala 442:45] + node _T_677 = or(_T_666, _T_676) @[dbg.scala 441:140] + node _T_678 = bits(sbcs_reg, 19, 17) @[dbg.scala 443:23] + node _T_679 = eq(_T_678, UInt<2>("h02")) @[dbg.scala 443:32] + node _T_680 = bits(_T_679, 0, 0) @[Bitwise.scala 72:15] + node _T_681 = mux(_T_680, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_682 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 443:70] + node _T_683 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 443:102] + node _T_684 = mul(UInt<6>("h020"), _T_683) @[dbg.scala 443:86] + node _T_685 = dshr(_T_682, _T_684) @[dbg.scala 443:78] + node _T_686 = and(_T_685, UInt<64>("h0ffffffff")) @[dbg.scala 443:107] + node _T_687 = and(_T_681, _T_686) @[dbg.scala 443:45] + node _T_688 = or(_T_677, _T_687) @[dbg.scala 442:129] + node _T_689 = bits(sbcs_reg, 19, 17) @[dbg.scala 444:23] + node _T_690 = eq(_T_689, UInt<2>("h03")) @[dbg.scala 444:32] + node _T_691 = bits(_T_690, 0, 0) @[Bitwise.scala 72:15] + node _T_692 = mux(_T_691, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_693 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 444:68] + node _T_694 = and(_T_692, _T_693) @[dbg.scala 444:45] + node _T_695 = or(_T_688, _T_694) @[dbg.scala 443:131] + sb_bus_rdata <= _T_695 @[dbg.scala 441:16] io.dbg_dma.dbg_ib.dbg_cmd_addr <= io.dbg_dec.dbg_ib.dbg_cmd_addr @[dbg.scala 447:39] io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[dbg.scala 448:39] io.dbg_dma.dbg_ib.dbg_cmd_valid <= io.dbg_dec.dbg_ib.dbg_cmd_valid @[dbg.scala 449:39] diff --git a/dbg.v b/dbg.v index 6a4fd9a3..bcfa40f7 100644 --- a/dbg.v +++ b/dbg.v @@ -177,52 +177,52 @@ module dbg( wire _T_26 = _T_20 & _T_25; // @[dbg.scala 102:118] wire sbcs_sbbusyerror_wren = _T_18 | _T_26; // @[dbg.scala 102:66] wire sbcs_sbbusyerror_din = ~_T_18; // @[dbg.scala 105:31] - wire _T_29 = ~dbg_dm_rst_l; // @[dbg.scala 106:54] - wire _T_30 = ~dbg_dm_rst_l; // @[dbg.scala 106:81] + wire _T_29 = io_dbg_rst_l & _T_9; // @[dbg.scala 106:80] reg temp_sbcs_22; // @[Reg.scala 27:20] reg temp_sbcs_21; // @[Reg.scala 27:20] reg temp_sbcs_20; // @[Reg.scala 27:20] reg [4:0] temp_sbcs_19_15; // @[Reg.scala 27:20] + wire _T_36 = ~dbg_dm_rst_l; // @[dbg.scala 122:84] reg [2:0] temp_sbcs_14_12; // @[Reg.scala 27:20] - wire [19:0] _T_44 = {temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58] - wire [11:0] _T_48 = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20}; // @[Cat.scala 29:58] - wire _T_51 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 127:42] - wire _T_53 = _T_51 & sbaddress0_reg[0]; // @[dbg.scala 127:56] - wire _T_55 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 128:23] - wire _T_57 = |sbaddress0_reg[1:0]; // @[dbg.scala 128:60] - wire _T_58 = _T_55 & _T_57; // @[dbg.scala 128:37] - wire _T_59 = _T_53 | _T_58; // @[dbg.scala 127:76] - wire _T_61 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 129:23] - wire _T_63 = |sbaddress0_reg[2:0]; // @[dbg.scala 129:60] - wire _T_64 = _T_61 & _T_63; // @[dbg.scala 129:37] - wire sbcs_unaligned = _T_59 | _T_64; // @[dbg.scala 128:64] + wire [19:0] _T_40 = {temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58] + wire [11:0] _T_44 = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20}; // @[Cat.scala 29:58] + wire _T_47 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 127:42] + wire _T_49 = _T_47 & sbaddress0_reg[0]; // @[dbg.scala 127:61] + wire _T_51 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 128:23] + wire _T_53 = |sbaddress0_reg[1:0]; // @[dbg.scala 128:65] + wire _T_54 = _T_51 & _T_53; // @[dbg.scala 128:42] + wire _T_55 = _T_49 | _T_54; // @[dbg.scala 127:81] + wire _T_57 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 129:23] + wire _T_59 = |sbaddress0_reg[2:0]; // @[dbg.scala 129:65] + wire _T_60 = _T_57 & _T_59; // @[dbg.scala 129:42] + wire sbcs_unaligned = _T_55 | _T_60; // @[dbg.scala 128:69] wire sbcs_illegal_size = sbcs_reg[19]; // @[dbg.scala 131:35] - wire _T_66 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 132:51] - wire [3:0] _T_68 = _T_66 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_69 = _T_68 & 4'h1; // @[dbg.scala 132:64] - wire [3:0] _T_73 = _T_51 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_74 = _T_73 & 4'h2; // @[dbg.scala 132:117] - wire [3:0] _T_75 = _T_69 | _T_74; // @[dbg.scala 132:76] - wire [3:0] _T_79 = _T_55 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_80 = _T_79 & 4'h4; // @[dbg.scala 133:44] - wire [3:0] _T_81 = _T_75 | _T_80; // @[dbg.scala 132:129] - wire [3:0] _T_85 = _T_61 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_86 = _T_85 & 4'h8; // @[dbg.scala 133:97] - wire [3:0] sbaddress0_incr = _T_81 | _T_86; // @[dbg.scala 133:56] - wire _T_87 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 135:41] - wire sbdata0_reg_wren0 = _T_87 & _T_22; // @[dbg.scala 135:60] - wire _T_89 = sb_state == 4'h7; // @[dbg.scala 136:37] - wire _T_90 = _T_89 & sb_state_en; // @[dbg.scala 136:60] - wire _T_91 = ~sbcs_sberror_wren; // @[dbg.scala 136:76] - wire sbdata0_reg_wren1 = _T_90 & _T_91; // @[dbg.scala 136:74] - wire sbdata1_reg_wren0 = _T_87 & _T_24; // @[dbg.scala 138:60] - wire [31:0] _T_98 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_99 = _T_98 & io_dmi_reg_wdata; // @[dbg.scala 141:49] - wire [31:0] _T_101 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_103 = _T_101 & sb_bus_rdata[31:0]; // @[dbg.scala 142:33] - wire [31:0] _T_105 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_106 = _T_105 & io_dmi_reg_wdata; // @[dbg.scala 144:49] - wire [31:0] _T_110 = _T_101 & sb_bus_rdata[63:32]; // @[dbg.scala 145:33] + wire _T_62 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 132:51] + wire [3:0] _T_64 = _T_62 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_65 = _T_64 & 4'h1; // @[dbg.scala 132:64] + wire [3:0] _T_69 = _T_47 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_70 = _T_69 & 4'h2; // @[dbg.scala 132:122] + wire [3:0] _T_71 = _T_65 | _T_70; // @[dbg.scala 132:81] + wire [3:0] _T_75 = _T_51 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_76 = _T_75 & 4'h4; // @[dbg.scala 133:44] + wire [3:0] _T_77 = _T_71 | _T_76; // @[dbg.scala 132:139] + wire [3:0] _T_81 = _T_57 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_82 = _T_81 & 4'h8; // @[dbg.scala 133:102] + wire [3:0] sbaddress0_incr = _T_77 | _T_82; // @[dbg.scala 133:61] + wire _T_83 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 135:41] + wire sbdata0_reg_wren0 = _T_83 & _T_22; // @[dbg.scala 135:60] + wire _T_85 = sb_state == 4'h7; // @[dbg.scala 136:37] + wire _T_86 = _T_85 & sb_state_en; // @[dbg.scala 136:60] + wire _T_87 = ~sbcs_sberror_wren; // @[dbg.scala 136:76] + wire sbdata0_reg_wren1 = _T_86 & _T_87; // @[dbg.scala 136:74] + wire sbdata1_reg_wren0 = _T_83 & _T_24; // @[dbg.scala 138:60] + wire [31:0] _T_94 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_95 = _T_94 & io_dmi_reg_wdata; // @[dbg.scala 141:49] + wire [31:0] _T_97 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_99 = _T_97 & sb_bus_rdata[31:0]; // @[dbg.scala 142:33] + wire [31:0] _T_101 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_102 = _T_101 & io_dmi_reg_wdata; // @[dbg.scala 144:49] + wire [31:0] _T_106 = _T_97 & sb_bus_rdata[63:32]; // @[dbg.scala 145:33] wire rvclkhdr_2_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_2_io_clk; // @[lib.scala 352:23] wire rvclkhdr_2_io_en; // @[lib.scala 352:23] @@ -233,385 +233,383 @@ module dbg( wire rvclkhdr_3_io_en; // @[lib.scala 352:23] wire rvclkhdr_3_io_scan_mode; // @[lib.scala 352:23] reg [31:0] sbdata1_reg; // @[lib.scala 358:16] - wire sbaddress0_reg_wren0 = _T_87 & _T_21; // @[dbg.scala 155:63] - wire [31:0] _T_118 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_119 = _T_118 & io_dmi_reg_wdata; // @[dbg.scala 157:59] - wire [31:0] _T_121 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_122 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58] - wire [31:0] _T_124 = sbaddress0_reg + _T_122; // @[dbg.scala 158:54] - wire [31:0] _T_125 = _T_121 & _T_124; // @[dbg.scala 158:36] + wire sbaddress0_reg_wren0 = _T_83 & _T_21; // @[dbg.scala 155:63] + wire [31:0] _T_112 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_113 = _T_112 & io_dmi_reg_wdata; // @[dbg.scala 157:59] + wire [31:0] _T_115 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_116 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58] + wire [31:0] _T_118 = sbaddress0_reg + _T_116; // @[dbg.scala 158:54] + wire [31:0] _T_119 = _T_115 & _T_118; // @[dbg.scala 158:36] wire rvclkhdr_4_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_4_io_clk; // @[lib.scala 352:23] wire rvclkhdr_4_io_en; // @[lib.scala 352:23] wire rvclkhdr_4_io_scan_mode; // @[lib.scala 352:23] - reg [31:0] _T_128; // @[lib.scala 358:16] + reg [31:0] _T_121; // @[lib.scala 358:16] wire sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 163:94] - wire _T_133 = ~io_dmi_reg_wr_en; // @[dbg.scala 164:45] - wire _T_134 = io_dmi_reg_en & _T_133; // @[dbg.scala 164:43] - wire _T_136 = _T_134 & _T_22; // @[dbg.scala 164:63] - wire sbreadondata_access = _T_136 & sbcs_reg[15]; // @[dbg.scala 164:95] - wire _T_140 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 166:41] - wire _T_141 = _T_140 & io_dmi_reg_en; // @[dbg.scala 166:54] - wire dmcontrol_wren = _T_141 & io_dmi_reg_wr_en; // @[dbg.scala 166:70] - wire [3:0] _T_148 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58] + wire _T_126 = ~io_dmi_reg_wr_en; // @[dbg.scala 164:45] + wire _T_127 = io_dmi_reg_en & _T_126; // @[dbg.scala 164:43] + wire _T_129 = _T_127 & _T_22; // @[dbg.scala 164:63] + wire sbreadondata_access = _T_129 & sbcs_reg[15]; // @[dbg.scala 164:95] + wire _T_133 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 166:41] + wire _T_134 = _T_133 & io_dmi_reg_en; // @[dbg.scala 166:54] + wire dmcontrol_wren = _T_134 & io_dmi_reg_wr_en; // @[dbg.scala 166:70] + wire [3:0] _T_140 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58] reg [3:0] dm_temp; // @[Reg.scala 27:20] reg dm_temp_0; // @[Reg.scala 27:20] - wire [27:0] _T_155 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58] - wire [3:0] _T_157 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58] + wire [27:0] _T_147 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58] + wire [3:0] _T_149 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58] reg dmcontrol_wren_Q; // @[dbg.scala 181:12] - wire [1:0] _T_161 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_163 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_165 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_167 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_169 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [11:0] _T_173 = {_T_167,_T_169,1'h1,7'h2}; // @[Cat.scala 29:58] - wire [19:0] _T_177 = {12'h0,_T_161,_T_163,2'h0,_T_165}; // @[Cat.scala 29:58] - wire _T_179 = dbg_state == 3'h6; // @[dbg.scala 186:44] - wire _T_180 = _T_179 & io_dec_tlu_resume_ack; // @[dbg.scala 186:66] - wire _T_182 = ~dmcontrol_reg[30]; // @[dbg.scala 186:113] - wire _T_183 = dmstatus_resumeack & _T_182; // @[dbg.scala 186:111] - wire dmstatus_resumeack_wren = _T_180 | _T_183; // @[dbg.scala 186:90] - wire _T_187 = _T_140 & io_dmi_reg_wdata[1]; // @[dbg.scala 188:63] - wire _T_188 = _T_187 & io_dmi_reg_en; // @[dbg.scala 188:85] - wire dmstatus_havereset_wren = _T_188 & io_dmi_reg_wr_en; // @[dbg.scala 188:101] - wire _T_191 = _T_140 & io_dmi_reg_wdata[28]; // @[dbg.scala 189:62] - wire _T_192 = _T_191 & io_dmi_reg_en; // @[dbg.scala 189:85] - wire dmstatus_havereset_rst = _T_192 & io_dmi_reg_wr_en; // @[dbg.scala 189:101] - wire _T_194 = ~reset; // @[dbg.scala 191:43] - wire _T_197 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 192:42] - reg _T_201; // @[Reg.scala 27:20] - wire _T_204 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 198:37] - reg _T_206; // @[dbg.scala 198:12] - wire _T_209 = ~dmstatus_havereset_rst; // @[dbg.scala 202:15] - reg _T_210; // @[Reg.scala 27:20] + wire [1:0] _T_152 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_154 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_156 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_158 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_160 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [11:0] _T_164 = {_T_158,_T_160,1'h1,7'h2}; // @[Cat.scala 29:58] + wire [19:0] _T_168 = {12'h0,_T_152,_T_154,2'h0,_T_156}; // @[Cat.scala 29:58] + wire _T_170 = dbg_state == 3'h6; // @[dbg.scala 186:44] + wire _T_171 = _T_170 & io_dec_tlu_resume_ack; // @[dbg.scala 186:66] + wire _T_173 = ~dmcontrol_reg[30]; // @[dbg.scala 186:113] + wire _T_174 = dmstatus_resumeack & _T_173; // @[dbg.scala 186:111] + wire dmstatus_resumeack_wren = _T_171 | _T_174; // @[dbg.scala 186:90] + wire _T_178 = _T_133 & io_dmi_reg_wdata[1]; // @[dbg.scala 188:63] + wire _T_179 = _T_178 & io_dmi_reg_en; // @[dbg.scala 188:85] + wire dmstatus_havereset_wren = _T_179 & io_dmi_reg_wr_en; // @[dbg.scala 188:101] + wire _T_182 = _T_133 & io_dmi_reg_wdata[28]; // @[dbg.scala 189:62] + wire _T_183 = _T_182 & io_dmi_reg_en; // @[dbg.scala 189:85] + wire dmstatus_havereset_rst = _T_183 & io_dmi_reg_wr_en; // @[dbg.scala 189:101] + wire _T_185 = ~reset; // @[dbg.scala 191:43] + wire _T_188 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 192:42] + reg _T_191; // @[Reg.scala 27:20] + wire _T_193 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 198:37] + reg _T_195; // @[dbg.scala 198:12] + wire _T_197 = dmstatus_havereset_wren | dmstatus_havereset; // @[dbg.scala 202:16] + wire _T_198 = ~dmstatus_havereset_rst; // @[dbg.scala 202:72] + reg _T_200; // @[dbg.scala 202:12] wire [31:0] haltsum0_reg = {31'h0,dmstatus_halted}; // @[Cat.scala 29:58] wire [31:0] abstractcs_reg; - wire _T_212 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 208:50] - wire _T_213 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 208:106] - wire _T_214 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 208:138] - wire _T_215 = _T_213 | _T_214; // @[dbg.scala 208:119] - wire _T_216 = io_dmi_reg_wr_en & _T_215; // @[dbg.scala 208:86] - wire _T_217 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 208:171] - wire _T_218 = _T_216 | _T_217; // @[dbg.scala 208:152] - wire abstractcs_error_sel0 = _T_212 & _T_218; // @[dbg.scala 208:66] - wire _T_221 = _T_87 & _T_214; // @[dbg.scala 209:64] - wire _T_223 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 209:126] - wire _T_225 = io_dmi_reg_wdata[31:24] == 8'h2; // @[dbg.scala 209:163] - wire _T_226 = _T_223 | _T_225; // @[dbg.scala 209:135] - wire _T_227 = ~_T_226; // @[dbg.scala 209:98] - wire abstractcs_error_sel1 = _T_221 & _T_227; // @[dbg.scala 209:96] + wire _T_202 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 208:50] + wire _T_203 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 208:106] + wire _T_204 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 208:138] + wire _T_205 = _T_203 | _T_204; // @[dbg.scala 208:119] + wire _T_206 = io_dmi_reg_wr_en & _T_205; // @[dbg.scala 208:86] + wire _T_207 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 208:171] + wire _T_208 = _T_206 | _T_207; // @[dbg.scala 208:152] + wire abstractcs_error_sel0 = _T_202 & _T_208; // @[dbg.scala 208:66] + wire _T_211 = _T_83 & _T_204; // @[dbg.scala 209:64] + wire _T_213 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 209:126] + wire _T_215 = io_dmi_reg_wdata[31:24] == 8'h2; // @[dbg.scala 209:163] + wire _T_216 = _T_213 | _T_215; // @[dbg.scala 209:135] + wire _T_217 = ~_T_216; // @[dbg.scala 209:98] + wire abstractcs_error_sel1 = _T_211 & _T_217; // @[dbg.scala 209:96] wire abstractcs_error_sel2 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[dbg.scala 210:52] - wire _T_232 = ~dmstatus_reg[9]; // @[dbg.scala 211:98] - wire abstractcs_error_sel3 = _T_221 & _T_232; // @[dbg.scala 211:96] - wire _T_234 = _T_214 & io_dmi_reg_en; // @[dbg.scala 212:61] - wire _T_235 = _T_234 & io_dmi_reg_wr_en; // @[dbg.scala 212:77] - wire _T_237 = io_dmi_reg_wdata[22:20] != 3'h2; // @[dbg.scala 213:32] - wire _T_241 = |data1_reg[1:0]; // @[dbg.scala 213:106] - wire _T_242 = _T_225 & _T_241; // @[dbg.scala 213:87] - wire _T_243 = _T_237 | _T_242; // @[dbg.scala 213:46] - wire abstractcs_error_sel4 = _T_235 & _T_243; // @[dbg.scala 212:96] - wire _T_245 = _T_213 & io_dmi_reg_en; // @[dbg.scala 215:61] - wire abstractcs_error_sel5 = _T_245 & io_dmi_reg_wr_en; // @[dbg.scala 215:77] - wire _T_246 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[dbg.scala 216:54] - wire _T_247 = _T_246 | abstractcs_error_sel2; // @[dbg.scala 216:78] - wire _T_248 = _T_247 | abstractcs_error_sel3; // @[dbg.scala 216:102] - wire _T_249 = _T_248 | abstractcs_error_sel4; // @[dbg.scala 216:126] - wire abstractcs_error_selor = _T_249 | abstractcs_error_sel5; // @[dbg.scala 216:150] - wire [2:0] _T_251 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_252 = _T_251 & 3'h1; // @[dbg.scala 217:62] - wire [2:0] _T_254 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_255 = _T_254 & 3'h2; // @[dbg.scala 218:37] - wire [2:0] _T_256 = _T_252 | _T_255; // @[dbg.scala 217:74] - wire [2:0] _T_258 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_259 = _T_258 & 3'h3; // @[dbg.scala 219:37] - wire [2:0] _T_260 = _T_256 | _T_259; // @[dbg.scala 218:49] - wire [2:0] _T_262 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_263 = _T_262 & 3'h4; // @[dbg.scala 220:37] - wire [2:0] _T_264 = _T_260 | _T_263; // @[dbg.scala 219:49] - wire [2:0] _T_266 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_268 = _T_264 | _T_266; // @[dbg.scala 220:49] - wire [2:0] _T_270 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_272 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 222:40] - wire [2:0] _T_273 = _T_270 & _T_272; // @[dbg.scala 222:37] - wire [2:0] _T_275 = _T_273 & abstractcs_reg[10:8]; // @[dbg.scala 222:75] - wire [2:0] _T_276 = _T_268 | _T_275; // @[dbg.scala 221:49] - wire _T_277 = ~abstractcs_error_selor; // @[dbg.scala 223:15] - wire [2:0] _T_279 = _T_277 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_281 = _T_279 & abstractcs_reg[10:8]; // @[dbg.scala 223:50] + wire _T_222 = ~dmstatus_reg[9]; // @[dbg.scala 211:98] + wire abstractcs_error_sel3 = _T_211 & _T_222; // @[dbg.scala 211:96] + wire _T_224 = _T_204 & io_dmi_reg_en; // @[dbg.scala 212:61] + wire _T_225 = _T_224 & io_dmi_reg_wr_en; // @[dbg.scala 212:77] + wire _T_227 = io_dmi_reg_wdata[22:20] != 3'h2; // @[dbg.scala 213:32] + wire _T_231 = |data1_reg[1:0]; // @[dbg.scala 213:111] + wire _T_232 = _T_215 & _T_231; // @[dbg.scala 213:92] + wire _T_233 = _T_227 | _T_232; // @[dbg.scala 213:51] + wire abstractcs_error_sel4 = _T_225 & _T_233; // @[dbg.scala 212:96] + wire _T_235 = _T_203 & io_dmi_reg_en; // @[dbg.scala 215:61] + wire abstractcs_error_sel5 = _T_235 & io_dmi_reg_wr_en; // @[dbg.scala 215:77] + wire _T_236 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[dbg.scala 216:54] + wire _T_237 = _T_236 | abstractcs_error_sel2; // @[dbg.scala 216:78] + wire _T_238 = _T_237 | abstractcs_error_sel3; // @[dbg.scala 216:102] + wire _T_239 = _T_238 | abstractcs_error_sel4; // @[dbg.scala 216:126] + wire abstractcs_error_selor = _T_239 | abstractcs_error_sel5; // @[dbg.scala 216:150] + wire [2:0] _T_241 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_242 = _T_241 & 3'h1; // @[dbg.scala 217:62] + wire [2:0] _T_244 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_245 = _T_244 & 3'h2; // @[dbg.scala 218:37] + wire [2:0] _T_246 = _T_242 | _T_245; // @[dbg.scala 217:79] + wire [2:0] _T_248 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_249 = _T_248 & 3'h3; // @[dbg.scala 219:37] + wire [2:0] _T_250 = _T_246 | _T_249; // @[dbg.scala 218:54] + wire [2:0] _T_252 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_253 = _T_252 & 3'h4; // @[dbg.scala 220:37] + wire [2:0] _T_254 = _T_250 | _T_253; // @[dbg.scala 219:54] + wire [2:0] _T_256 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_258 = _T_254 | _T_256; // @[dbg.scala 220:54] + wire [2:0] _T_260 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_262 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 222:40] + wire [2:0] _T_263 = _T_260 & _T_262; // @[dbg.scala 222:37] + wire [2:0] _T_265 = _T_263 & abstractcs_reg[10:8]; // @[dbg.scala 222:75] + wire [2:0] _T_266 = _T_258 | _T_265; // @[dbg.scala 221:54] + wire _T_267 = ~abstractcs_error_selor; // @[dbg.scala 223:15] + wire [2:0] _T_269 = _T_267 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_271 = _T_269 & abstractcs_reg[10:8]; // @[dbg.scala 223:50] reg abs_temp_12; // @[Reg.scala 27:20] reg [2:0] abs_temp_10_8; // @[dbg.scala 230:12] - wire [10:0] _T_287 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58] - wire [20:0] _T_289 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58] - wire _T_294 = dbg_state == 3'h2; // @[dbg.scala 235:100] - wire command_wren = _T_235 & _T_294; // @[dbg.scala 235:87] - wire [19:0] _T_298 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] - wire [11:0] _T_300 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58] + wire [10:0] _T_275 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58] + wire [20:0] _T_277 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58] + wire _T_282 = dbg_state == 3'h2; // @[dbg.scala 235:100] + wire command_wren = _T_225 & _T_282; // @[dbg.scala 235:87] + wire [19:0] _T_286 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] + wire [11:0] _T_288 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58] wire rvclkhdr_5_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_5_io_clk; // @[lib.scala 352:23] wire rvclkhdr_5_io_en; // @[lib.scala 352:23] wire rvclkhdr_5_io_scan_mode; // @[lib.scala 352:23] reg [31:0] command_reg; // @[lib.scala 358:16] - wire _T_305 = _T_87 & _T_217; // @[dbg.scala 241:58] - wire data0_reg_wren0 = _T_305 & _T_294; // @[dbg.scala 241:89] - wire _T_307 = dbg_state == 3'h4; // @[dbg.scala 242:59] - wire _T_308 = io_core_dbg_cmd_done & _T_307; // @[dbg.scala 242:46] - wire _T_310 = ~command_reg[16]; // @[dbg.scala 242:83] - wire data0_reg_wren1 = _T_308 & _T_310; // @[dbg.scala 242:81] - wire [31:0] _T_312 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_313 = _T_312 & io_dmi_reg_wdata; // @[dbg.scala 245:45] - wire [31:0] _T_315 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_316 = _T_315 & io_core_dbg_rddata; // @[dbg.scala 245:92] + wire _T_292 = _T_83 & _T_207; // @[dbg.scala 241:58] + wire data0_reg_wren0 = _T_292 & _T_282; // @[dbg.scala 241:89] + wire _T_294 = dbg_state == 3'h4; // @[dbg.scala 242:59] + wire _T_295 = io_core_dbg_cmd_done & _T_294; // @[dbg.scala 242:46] + wire _T_297 = ~command_reg[16]; // @[dbg.scala 242:83] + wire data0_reg_wren1 = _T_295 & _T_297; // @[dbg.scala 242:81] + wire [31:0] _T_299 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_300 = _T_299 & io_dmi_reg_wdata; // @[dbg.scala 245:45] + wire [31:0] _T_302 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_303 = _T_302 & io_core_dbg_rddata; // @[dbg.scala 245:92] wire rvclkhdr_6_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_6_io_clk; // @[lib.scala 352:23] wire rvclkhdr_6_io_en; // @[lib.scala 352:23] wire rvclkhdr_6_io_scan_mode; // @[lib.scala 352:23] reg [31:0] data0_reg; // @[lib.scala 358:16] - wire _T_320 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 250:77] - wire _T_321 = _T_87 & _T_320; // @[dbg.scala 250:58] - wire data1_reg_wren = _T_321 & _T_294; // @[dbg.scala 250:89] - wire [31:0] _T_324 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire _T_306 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 250:77] + wire _T_307 = _T_83 & _T_306; // @[dbg.scala 250:58] + wire data1_reg_wren = _T_307 & _T_282; // @[dbg.scala 250:89] + wire [31:0] _T_310 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire rvclkhdr_7_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_7_io_clk; // @[lib.scala 352:23] wire rvclkhdr_7_io_en; // @[lib.scala 352:23] wire rvclkhdr_7_io_scan_mode; // @[lib.scala 352:23] - reg [31:0] _T_327; // @[lib.scala 358:16] + reg [31:0] _T_312; // @[lib.scala 358:16] wire [2:0] dbg_nxtstate; - wire _T_328 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] - wire _T_330 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 265:43] - wire [2:0] _T_331 = _T_330 ? 3'h2 : 3'h1; // @[dbg.scala 265:26] - wire _T_333 = ~io_dec_tlu_debug_mode; // @[dbg.scala 266:45] - wire _T_334 = dmcontrol_reg[31] & _T_333; // @[dbg.scala 266:43] - wire _T_336 = _T_334 | dmstatus_reg[9]; // @[dbg.scala 266:69] - wire _T_337 = _T_336 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 266:87] - wire _T_340 = _T_337 & _T_11; // @[dbg.scala 266:117] - wire _T_344 = dmcontrol_reg[31] & _T_11; // @[dbg.scala 267:45] - wire _T_346 = 3'h1 == dbg_state; // @[Conditional.scala 37:30] - wire [2:0] _T_348 = dmcontrol_reg[1] ? 3'h0 : 3'h2; // @[dbg.scala 270:26] - wire _T_351 = dmstatus_reg[9] | dmcontrol_reg[1]; // @[dbg.scala 271:39] - wire _T_353 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[dbg.scala 272:44] - wire _T_356 = _T_353 & _T_11; // @[dbg.scala 272:64] - wire _T_358 = 3'h2 == dbg_state; // @[Conditional.scala 37:30] - wire _T_362 = dmstatus_reg[9] & _T_11; // @[dbg.scala 275:43] - wire _T_365 = ~dmcontrol_reg[3]; // @[dbg.scala 276:33] - wire _T_366 = dmcontrol_reg[30] & _T_365; // @[dbg.scala 276:31] - wire [2:0] _T_367 = _T_366 ? 3'h6 : 3'h3; // @[dbg.scala 276:12] - wire [2:0] _T_369 = dmcontrol_reg[31] ? 3'h1 : 3'h0; // @[dbg.scala 277:12] - wire [2:0] _T_370 = _T_362 ? _T_367 : _T_369; // @[dbg.scala 275:26] - wire _T_373 = dmstatus_reg[9] & dmcontrol_reg[30]; // @[dbg.scala 278:39] - wire _T_375 = ~dmcontrol_reg[31]; // @[dbg.scala 278:61] - wire _T_376 = _T_373 & _T_375; // @[dbg.scala 278:59] - wire _T_377 = _T_376 & dmcontrol_wren_Q; // @[dbg.scala 278:80] - wire _T_378 = _T_377 | command_wren; // @[dbg.scala 278:99] - wire _T_380 = _T_378 | dmcontrol_reg[1]; // @[dbg.scala 278:114] - wire _T_383 = ~_T_330; // @[dbg.scala 279:28] - wire _T_384 = _T_380 | _T_383; // @[dbg.scala 279:26] - wire _T_385 = dbg_nxtstate == 3'h3; // @[dbg.scala 280:60] - wire _T_386 = dbg_state_en & _T_385; // @[dbg.scala 280:44] - wire _T_387 = dbg_nxtstate == 3'h6; // @[dbg.scala 282:58] - wire _T_388 = dbg_state_en & _T_387; // @[dbg.scala 282:42] - wire _T_396 = 3'h3 == dbg_state; // @[Conditional.scala 37:30] - wire _T_399 = |abstractcs_reg[10:8]; // @[dbg.scala 286:85] - wire [2:0] _T_400 = _T_399 ? 3'h5 : 3'h4; // @[dbg.scala 286:62] - wire [2:0] _T_401 = dmcontrol_reg[1] ? 3'h0 : _T_400; // @[dbg.scala 286:26] - wire _T_404 = io_dbg_dec_dbg_ib_dbg_cmd_valid | _T_399; // @[dbg.scala 287:55] - wire _T_406 = _T_404 | dmcontrol_reg[1]; // @[dbg.scala 287:83] - wire _T_413 = 3'h4 == dbg_state; // @[Conditional.scala 37:30] - wire [2:0] _T_415 = dmcontrol_reg[1] ? 3'h0 : 3'h5; // @[dbg.scala 291:26] - wire _T_417 = io_core_dbg_cmd_done | dmcontrol_reg[1]; // @[dbg.scala 292:44] - wire _T_424 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] - wire _T_433 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] - wire _T_436 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 304:40] - wire _GEN_11 = _T_433 & _T_436; // @[Conditional.scala 39:67] - wire _GEN_12 = _T_433 & _T_356; // @[Conditional.scala 39:67] - wire [2:0] _GEN_13 = _T_424 ? _T_348 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_14 = _T_424 | _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_15 = _T_424 & dbg_state_en; // @[Conditional.scala 39:67] - wire _GEN_17 = _T_424 ? _T_356 : _GEN_12; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_413 ? _T_415 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_413 ? _T_417 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_413 ? _T_356 : _GEN_17; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_413 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_396 ? _T_401 : _GEN_18; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_396 ? _T_406 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_25 = _T_396 ? _T_356 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_396 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_28 = _T_358 ? _T_370 : _GEN_23; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_358 ? _T_384 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_358 ? _T_386 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_358 & _T_388; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_358 ? _T_356 : _GEN_25; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_346 ? _T_348 : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_346 ? _T_351 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_346 ? _T_356 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_37 = _T_346 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_346 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire [31:0] _T_445 = _T_217 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_446 = _T_445 & data0_reg; // @[dbg.scala 308:71] - wire [31:0] _T_449 = _T_320 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_450 = _T_449 & data1_reg; // @[dbg.scala 308:122] - wire [31:0] _T_451 = _T_446 | _T_450; // @[dbg.scala 308:83] - wire [31:0] _T_454 = _T_140 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_455 = _T_454 & dmcontrol_reg; // @[dbg.scala 309:43] - wire [31:0] _T_456 = _T_451 | _T_455; // @[dbg.scala 308:134] - wire _T_457 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 309:86] + wire _T_313 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] + wire _T_315 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 265:43] + wire [2:0] _T_316 = _T_315 ? 3'h2 : 3'h1; // @[dbg.scala 265:26] + wire _T_318 = ~io_dec_tlu_debug_mode; // @[dbg.scala 266:45] + wire _T_319 = dmcontrol_reg[31] & _T_318; // @[dbg.scala 266:43] + wire _T_321 = _T_319 | dmstatus_reg[9]; // @[dbg.scala 266:69] + wire _T_322 = _T_321 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 266:87] + wire _T_325 = _T_322 & _T_11; // @[dbg.scala 266:117] + wire _T_329 = dmcontrol_reg[31] & _T_11; // @[dbg.scala 267:45] + wire _T_331 = 3'h1 == dbg_state; // @[Conditional.scala 37:30] + wire [2:0] _T_333 = dmcontrol_reg[1] ? 3'h0 : 3'h2; // @[dbg.scala 270:26] + wire _T_336 = dmstatus_reg[9] | dmcontrol_reg[1]; // @[dbg.scala 271:39] + wire _T_338 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[dbg.scala 272:44] + wire _T_341 = _T_338 & _T_11; // @[dbg.scala 272:64] + wire _T_343 = 3'h2 == dbg_state; // @[Conditional.scala 37:30] + wire _T_347 = dmstatus_reg[9] & _T_11; // @[dbg.scala 275:43] + wire _T_350 = ~dmcontrol_reg[31]; // @[dbg.scala 276:33] + wire _T_351 = dmcontrol_reg[30] & _T_350; // @[dbg.scala 276:31] + wire [2:0] _T_352 = _T_351 ? 3'h6 : 3'h3; // @[dbg.scala 276:12] + wire [2:0] _T_354 = dmcontrol_reg[31] ? 3'h1 : 3'h0; // @[dbg.scala 277:12] + wire [2:0] _T_355 = _T_347 ? _T_352 : _T_354; // @[dbg.scala 275:26] + wire _T_358 = dmstatus_reg[9] & dmcontrol_reg[30]; // @[dbg.scala 278:39] + wire _T_361 = _T_358 & _T_350; // @[dbg.scala 278:59] + wire _T_362 = _T_361 & dmcontrol_wren_Q; // @[dbg.scala 278:80] + wire _T_363 = _T_362 | command_wren; // @[dbg.scala 278:99] + wire _T_365 = _T_363 | dmcontrol_reg[1]; // @[dbg.scala 278:114] + wire _T_368 = ~_T_315; // @[dbg.scala 279:28] + wire _T_369 = _T_365 | _T_368; // @[dbg.scala 279:26] + wire _T_370 = dbg_nxtstate == 3'h3; // @[dbg.scala 280:60] + wire _T_371 = dbg_state_en & _T_370; // @[dbg.scala 280:44] + wire _T_372 = dbg_nxtstate == 3'h6; // @[dbg.scala 282:58] + wire _T_373 = dbg_state_en & _T_372; // @[dbg.scala 282:42] + wire _T_381 = 3'h3 == dbg_state; // @[Conditional.scala 37:30] + wire _T_384 = |abstractcs_reg[10:8]; // @[dbg.scala 286:85] + wire [2:0] _T_385 = _T_384 ? 3'h5 : 3'h4; // @[dbg.scala 286:62] + wire [2:0] _T_386 = dmcontrol_reg[1] ? 3'h0 : _T_385; // @[dbg.scala 286:26] + wire _T_389 = io_dbg_dec_dbg_ib_dbg_cmd_valid | _T_384; // @[dbg.scala 287:55] + wire _T_391 = _T_389 | dmcontrol_reg[1]; // @[dbg.scala 287:83] + wire _T_398 = 3'h4 == dbg_state; // @[Conditional.scala 37:30] + wire [2:0] _T_400 = dmcontrol_reg[1] ? 3'h0 : 3'h5; // @[dbg.scala 291:26] + wire _T_402 = io_core_dbg_cmd_done | dmcontrol_reg[1]; // @[dbg.scala 292:44] + wire _T_409 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] + wire _T_418 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] + wire _T_421 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 304:40] + wire _GEN_10 = _T_418 & _T_421; // @[Conditional.scala 39:67] + wire _GEN_11 = _T_418 & _T_341; // @[Conditional.scala 39:67] + wire [2:0] _GEN_12 = _T_409 ? _T_333 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_13 = _T_409 | _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_14 = _T_409 & dbg_state_en; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_409 ? _T_341 : _GEN_11; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_398 ? _T_400 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_18 = _T_398 ? _T_402 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_398 ? _T_341 : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_398 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire [2:0] _GEN_22 = _T_381 ? _T_386 : _GEN_17; // @[Conditional.scala 39:67] + wire _GEN_23 = _T_381 ? _T_391 : _GEN_18; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_381 ? _T_341 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_25 = _T_381 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] + wire [2:0] _GEN_27 = _T_343 ? _T_355 : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_343 ? _T_369 : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_343 ? _T_371 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_343 & _T_373; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_343 ? _T_341 : _GEN_24; // @[Conditional.scala 39:67] + wire [2:0] _GEN_33 = _T_331 ? _T_333 : _GEN_27; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_331 ? _T_336 : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_331 ? _T_341 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_331 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_331 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] + wire [31:0] _T_430 = _T_207 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_431 = _T_430 & data0_reg; // @[dbg.scala 308:71] + wire [31:0] _T_434 = _T_306 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_435 = _T_434 & data1_reg; // @[dbg.scala 308:122] + wire [31:0] _T_436 = _T_431 | _T_435; // @[dbg.scala 308:83] + wire [31:0] _T_439 = _T_133 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_440 = _T_439 & dmcontrol_reg; // @[dbg.scala 309:43] + wire [31:0] _T_441 = _T_436 | _T_440; // @[dbg.scala 308:134] + wire _T_442 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 309:86] + wire [31:0] _T_444 = _T_442 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_445 = _T_444 & dmstatus_reg; // @[dbg.scala 309:99] + wire [31:0] _T_446 = _T_441 | _T_445; // @[dbg.scala 309:59] + wire [31:0] _T_449 = _T_203 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & abstractcs_reg; // @[dbg.scala 310:43] + wire [31:0] _T_451 = _T_446 | _T_450; // @[dbg.scala 309:114] + wire [31:0] _T_454 = _T_204 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_455 = _T_454 & command_reg; // @[dbg.scala 310:100] + wire [31:0] _T_456 = _T_451 | _T_455; // @[dbg.scala 310:60] + wire _T_457 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 311:30] wire [31:0] _T_459 = _T_457 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_460 = _T_459 & dmstatus_reg; // @[dbg.scala 309:99] - wire [31:0] _T_461 = _T_456 | _T_460; // @[dbg.scala 309:59] - wire [31:0] _T_464 = _T_213 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_465 = _T_464 & abstractcs_reg; // @[dbg.scala 310:43] - wire [31:0] _T_466 = _T_461 | _T_465; // @[dbg.scala 309:114] - wire [31:0] _T_469 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_470 = _T_469 & command_reg; // @[dbg.scala 310:100] - wire [31:0] _T_471 = _T_466 | _T_470; // @[dbg.scala 310:60] - wire _T_472 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 311:30] - wire [31:0] _T_474 = _T_472 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_475 = _T_474 & haltsum0_reg; // @[dbg.scala 311:43] - wire [31:0] _T_476 = _T_471 | _T_475; // @[dbg.scala 310:114] - wire [31:0] _T_479 = _T_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_480 = _T_479 & sbcs_reg; // @[dbg.scala 311:98] - wire [31:0] _T_481 = _T_476 | _T_480; // @[dbg.scala 311:58] - wire [31:0] _T_484 = _T_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_485 = _T_484 & sbaddress0_reg; // @[dbg.scala 312:43] - wire [31:0] _T_486 = _T_481 | _T_485; // @[dbg.scala 311:109] - wire [31:0] _T_489 = _T_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_490 = _T_489 & sbdata0_reg; // @[dbg.scala 312:100] - wire [31:0] _T_491 = _T_486 | _T_490; // @[dbg.scala 312:60] - wire [31:0] _T_494 = _T_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_495 = _T_494 & sbdata1_reg; // @[dbg.scala 313:43] - wire [31:0] dmi_reg_rdata_din = _T_491 | _T_495; // @[dbg.scala 312:114] - wire _T_498 = _T_29 & reset; // @[dbg.scala 315:87] - reg [2:0] _T_499; // @[Reg.scala 27:20] - reg [31:0] _T_502; // @[Reg.scala 27:20] - wire _T_504 = command_reg[31:24] == 8'h2; // @[dbg.scala 324:62] - wire [30:0] _T_506 = {data1_reg[31:2],1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_508 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58] - wire _T_511 = dbg_state == 3'h3; // @[dbg.scala 326:50] - wire _T_514 = ~_T_399; // @[dbg.scala 326:75] - wire _T_515 = _T_511 & _T_514; // @[dbg.scala 326:73] - wire _T_523 = command_reg[15:12] == 4'h0; // @[dbg.scala 328:117] - wire [1:0] _T_524 = {1'h0,_T_523}; // @[Cat.scala 29:58] - wire _T_535 = 4'h0 == sb_state; // @[Conditional.scala 37:30] - wire _T_537 = sbdata0_reg_wren0 | sbreadondata_access; // @[dbg.scala 343:39] - wire _T_538 = _T_537 | sbreadonaddr_access; // @[dbg.scala 343:61] - wire _T_540 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 346:65] - wire _T_541 = sbcs_wren & _T_540; // @[dbg.scala 346:38] - wire _T_543 = io_dmi_reg_wdata[14:12] == 3'h0; // @[dbg.scala 347:27] - wire [2:0] _GEN_116 = {{2'd0}, _T_543}; // @[dbg.scala 347:53] - wire [2:0] _T_545 = _GEN_116 & sbcs_reg[14:12]; // @[dbg.scala 347:53] - wire _T_546 = 4'h1 == sb_state; // @[Conditional.scala 37:30] - wire _T_547 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 350:41] - wire _T_549 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 351:40] - wire _T_550 = _T_549 | sbcs_illegal_size; // @[dbg.scala 351:57] - wire _T_553 = 4'h2 == sb_state; // @[Conditional.scala 37:30] - wire _T_560 = 4'h3 == sb_state; // @[Conditional.scala 37:30] - wire _T_561 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 363:38] - wire _T_562 = 4'h4 == sb_state; // @[Conditional.scala 37:30] - wire _T_563 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 366:48] - wire _T_566 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 367:45] - wire _T_567 = _T_566 & io_dbg_bus_clk_en; // @[dbg.scala 367:70] - wire _T_568 = 4'h5 == sb_state; // @[Conditional.scala 37:30] - wire _T_569 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 371:44] - wire _T_570 = 4'h6 == sb_state; // @[Conditional.scala 37:30] - wire _T_571 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 375:44] - wire _T_572 = 4'h7 == sb_state; // @[Conditional.scala 37:30] - wire _T_573 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 379:38] - wire _T_574 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 380:40] - wire _T_575 = 4'h8 == sb_state; // @[Conditional.scala 37:30] - wire _T_576 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39] - wire _T_578 = 4'h9 == sb_state; // @[Conditional.scala 37:30] - wire _GEN_51 = _T_578 & sbcs_reg[16]; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_575 ? _T_576 : _T_578; // @[Conditional.scala 39:67] - wire _GEN_54 = _T_575 & _T_574; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_575 ? 1'h0 : _T_578; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_575 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_572 ? _T_573 : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_572 ? _T_574 : _GEN_54; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_572 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_572 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_570 ? _T_571 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_68 = _T_570 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_570 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_570 ? 1'h0 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_568 ? _T_569 : _GEN_67; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_568 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67] - wire _GEN_77 = _T_568 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_568 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_562 ? _T_567 : _GEN_74; // @[Conditional.scala 39:67] - wire _GEN_82 = _T_562 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_562 ? 1'h0 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_562 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_560 ? _T_561 : _GEN_81; // @[Conditional.scala 39:67] - wire _GEN_89 = _T_560 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_560 ? 1'h0 : _GEN_84; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_560 ? 1'h0 : _GEN_86; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_553 ? _T_550 : _GEN_88; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_553 ? _T_547 : _GEN_89; // @[Conditional.scala 39:67] - wire _GEN_98 = _T_553 ? 1'h0 : _GEN_91; // @[Conditional.scala 39:67] - wire _GEN_100 = _T_553 ? 1'h0 : _GEN_93; // @[Conditional.scala 39:67] - wire _GEN_102 = _T_546 ? _T_550 : _GEN_95; // @[Conditional.scala 39:67] - wire _GEN_103 = _T_546 ? _T_547 : _GEN_96; // @[Conditional.scala 39:67] - wire _GEN_105 = _T_546 ? 1'h0 : _GEN_98; // @[Conditional.scala 39:67] - wire _GEN_107 = _T_546 ? 1'h0 : _GEN_100; // @[Conditional.scala 39:67] - reg [3:0] _T_582; // @[Reg.scala 27:20] - wire _T_589 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69] - wire _T_590 = sb_bus_rsp_read & _T_589; // @[dbg.scala 406:39] - wire _T_592 = |io_sb_axi_b_bits_resp; // @[dbg.scala 406:122] - wire _T_593 = sb_bus_rsp_write & _T_592; // @[dbg.scala 406:92] - wire _T_595 = sb_state == 4'h4; // @[dbg.scala 407:36] - wire _T_596 = sb_state == 4'h5; // @[dbg.scala 407:71] - wire _T_602 = sb_state == 4'h6; // @[dbg.scala 418:70] - wire [63:0] _T_608 = _T_66 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_612 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58] - wire [63:0] _T_613 = _T_608 & _T_612; // @[dbg.scala 419:65] - wire [63:0] _T_617 = _T_51 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_620 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58] - wire [63:0] _T_621 = _T_617 & _T_620; // @[dbg.scala 419:138] - wire [63:0] _T_622 = _T_613 | _T_621; // @[dbg.scala 419:96] - wire [63:0] _T_626 = _T_55 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_628 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58] - wire [63:0] _T_629 = _T_626 & _T_628; // @[dbg.scala 420:45] - wire [63:0] _T_630 = _T_622 | _T_629; // @[dbg.scala 419:168] - wire [63:0] _T_634 = _T_61 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_637 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] - wire [63:0] _T_638 = _T_634 & _T_637; // @[dbg.scala 420:119] - wire [7:0] _T_643 = _T_66 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [14:0] _T_645 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82] - wire [14:0] _GEN_117 = {{7'd0}, _T_643}; // @[dbg.scala 422:67] - wire [14:0] _T_646 = _GEN_117 & _T_645; // @[dbg.scala 422:67] - wire [7:0] _T_650 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_652 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] - wire [14:0] _T_653 = 15'h3 << _T_652; // @[dbg.scala 423:59] - wire [14:0] _GEN_118 = {{7'd0}, _T_650}; // @[dbg.scala 423:44] - wire [14:0] _T_654 = _GEN_118 & _T_653; // @[dbg.scala 423:44] - wire [14:0] _T_655 = _T_646 | _T_654; // @[dbg.scala 422:107] - wire [7:0] _T_659 = _T_55 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_661 = {sbaddress0_reg[2],1'h0}; // @[Cat.scala 29:58] - wire [10:0] _T_662 = 11'hf << _T_661; // @[dbg.scala 424:59] - wire [10:0] _GEN_119 = {{3'd0}, _T_659}; // @[dbg.scala 424:44] - wire [10:0] _T_663 = _GEN_119 & _T_662; // @[dbg.scala 424:44] - wire [14:0] _GEN_120 = {{4'd0}, _T_663}; // @[dbg.scala 423:97] - wire [14:0] _T_664 = _T_655 | _GEN_120; // @[dbg.scala 423:97] - wire [7:0] _T_668 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [14:0] _GEN_121 = {{7'd0}, _T_668}; // @[dbg.scala 424:95] - wire [14:0] _T_670 = _T_664 | _GEN_121; // @[dbg.scala 424:95] - wire [3:0] _GEN_122 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99] - wire [6:0] _T_681 = 4'h8 * _GEN_122; // @[dbg.scala 441:99] - wire [63:0] _T_682 = io_sb_axi_r_bits_data >> _T_681; // @[dbg.scala 441:92] - wire [63:0] _T_683 = _T_682 & 64'hff; // @[dbg.scala 441:123] - wire [63:0] _T_684 = _T_608 & _T_683; // @[dbg.scala 441:59] - wire [4:0] _GEN_123 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86] - wire [6:0] _T_691 = 5'h10 * _GEN_123; // @[dbg.scala 442:86] - wire [63:0] _T_692 = io_sb_axi_r_bits_data >> _T_691; // @[dbg.scala 442:78] - wire [63:0] _T_693 = _T_692 & 64'hffff; // @[dbg.scala 442:110] - wire [63:0] _T_694 = _T_617 & _T_693; // @[dbg.scala 442:45] - wire [63:0] _T_695 = _T_684 | _T_694; // @[dbg.scala 441:140] - wire [5:0] _GEN_124 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86] - wire [6:0] _T_702 = 6'h20 * _GEN_124; // @[dbg.scala 443:86] - wire [63:0] _T_703 = io_sb_axi_r_bits_data >> _T_702; // @[dbg.scala 443:78] - wire [63:0] _T_704 = _T_703 & 64'hffffffff; // @[dbg.scala 443:107] - wire [63:0] _T_705 = _T_626 & _T_704; // @[dbg.scala 443:45] - wire [63:0] _T_706 = _T_695 | _T_705; // @[dbg.scala 442:129] - wire [63:0] _T_712 = _T_634 & io_sb_axi_r_bits_data; // @[dbg.scala 444:45] + wire [31:0] _T_460 = _T_459 & haltsum0_reg; // @[dbg.scala 311:43] + wire [31:0] _T_461 = _T_456 | _T_460; // @[dbg.scala 310:114] + wire [31:0] _T_464 = _T_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_465 = _T_464 & sbcs_reg; // @[dbg.scala 311:98] + wire [31:0] _T_466 = _T_461 | _T_465; // @[dbg.scala 311:58] + wire [31:0] _T_469 = _T_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_470 = _T_469 & sbaddress0_reg; // @[dbg.scala 312:43] + wire [31:0] _T_471 = _T_466 | _T_470; // @[dbg.scala 311:109] + wire [31:0] _T_474 = _T_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_475 = _T_474 & sbdata0_reg; // @[dbg.scala 312:100] + wire [31:0] _T_476 = _T_471 | _T_475; // @[dbg.scala 312:60] + wire [31:0] _T_479 = _T_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_480 = _T_479 & sbdata1_reg; // @[dbg.scala 313:43] + wire [31:0] dmi_reg_rdata_din = _T_476 | _T_480; // @[dbg.scala 312:114] + wire _T_482 = dbg_dm_rst_l & reset; // @[dbg.scala 315:86] + reg [2:0] _T_483; // @[Reg.scala 27:20] + reg [31:0] _T_485; // @[Reg.scala 27:20] + wire _T_487 = command_reg[31:24] == 8'h2; // @[dbg.scala 324:62] + wire [31:0] _T_489 = {data1_reg[31:2],2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_491 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58] + wire _T_494 = dbg_state == 3'h3; // @[dbg.scala 326:50] + wire _T_497 = ~_T_384; // @[dbg.scala 326:75] + wire _T_498 = _T_494 & _T_497; // @[dbg.scala 326:73] + wire _T_506 = command_reg[15:12] == 4'h0; // @[dbg.scala 328:122] + wire [1:0] _T_507 = {1'h0,_T_506}; // @[Cat.scala 29:58] + wire _T_518 = 4'h0 == sb_state; // @[Conditional.scala 37:30] + wire _T_520 = sbdata0_reg_wren0 | sbreadondata_access; // @[dbg.scala 343:39] + wire _T_521 = _T_520 | sbreadonaddr_access; // @[dbg.scala 343:61] + wire _T_523 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 346:65] + wire _T_524 = sbcs_wren & _T_523; // @[dbg.scala 346:38] + wire [2:0] _T_526 = ~io_dmi_reg_wdata[14:12]; // @[dbg.scala 347:27] + wire [2:0] _T_528 = _T_526 & sbcs_reg[14:12]; // @[dbg.scala 347:53] + wire _T_529 = 4'h1 == sb_state; // @[Conditional.scala 37:30] + wire _T_530 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 350:41] + wire _T_532 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 351:40] + wire _T_533 = _T_532 | sbcs_illegal_size; // @[dbg.scala 351:57] + wire _T_536 = 4'h2 == sb_state; // @[Conditional.scala 37:30] + wire _T_543 = 4'h3 == sb_state; // @[Conditional.scala 37:30] + wire _T_544 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 363:38] + wire _T_545 = 4'h4 == sb_state; // @[Conditional.scala 37:30] + wire _T_546 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 366:48] + wire _T_549 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 367:45] + wire _T_550 = _T_549 & io_dbg_bus_clk_en; // @[dbg.scala 367:70] + wire _T_551 = 4'h5 == sb_state; // @[Conditional.scala 37:30] + wire _T_552 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 371:44] + wire _T_553 = 4'h6 == sb_state; // @[Conditional.scala 37:30] + wire _T_554 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 375:44] + wire _T_555 = 4'h7 == sb_state; // @[Conditional.scala 37:30] + wire _T_556 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 379:38] + wire _T_557 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 380:40] + wire _T_558 = 4'h8 == sb_state; // @[Conditional.scala 37:30] + wire _T_559 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39] + wire _T_561 = 4'h9 == sb_state; // @[Conditional.scala 37:30] + wire _GEN_50 = _T_561 & sbcs_reg[16]; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_558 ? _T_559 : _T_561; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_558 & _T_557; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_558 ? 1'h0 : _T_561; // @[Conditional.scala 39:67] + wire _GEN_57 = _T_558 ? 1'h0 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_555 ? _T_556 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_555 ? _T_557 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_555 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_555 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_553 ? _T_554 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_553 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_553 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_553 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_551 ? _T_552 : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_551 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_551 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_551 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_545 ? _T_550 : _GEN_73; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_545 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_545 ? 1'h0 : _GEN_76; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_545 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_543 ? _T_544 : _GEN_80; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_543 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire _GEN_90 = _T_543 ? 1'h0 : _GEN_83; // @[Conditional.scala 39:67] + wire _GEN_92 = _T_543 ? 1'h0 : _GEN_85; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_536 ? _T_533 : _GEN_87; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_536 ? _T_530 : _GEN_88; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_536 ? 1'h0 : _GEN_90; // @[Conditional.scala 39:67] + wire _GEN_99 = _T_536 ? 1'h0 : _GEN_92; // @[Conditional.scala 39:67] + wire _GEN_101 = _T_529 ? _T_533 : _GEN_94; // @[Conditional.scala 39:67] + wire _GEN_102 = _T_529 ? _T_530 : _GEN_95; // @[Conditional.scala 39:67] + wire _GEN_104 = _T_529 ? 1'h0 : _GEN_97; // @[Conditional.scala 39:67] + wire _GEN_106 = _T_529 ? 1'h0 : _GEN_99; // @[Conditional.scala 39:67] + reg [3:0] _T_564; // @[Reg.scala 27:20] + wire _T_571 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69] + wire _T_572 = sb_bus_rsp_read & _T_571; // @[dbg.scala 406:39] + wire _T_574 = |io_sb_axi_b_bits_resp; // @[dbg.scala 406:122] + wire _T_575 = sb_bus_rsp_write & _T_574; // @[dbg.scala 406:92] + wire _T_577 = sb_state == 4'h4; // @[dbg.scala 407:36] + wire _T_578 = sb_state == 4'h5; // @[dbg.scala 407:71] + wire _T_584 = sb_state == 4'h6; // @[dbg.scala 418:70] + wire [63:0] _T_590 = _T_62 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_594 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_595 = _T_590 & _T_594; // @[dbg.scala 419:65] + wire [63:0] _T_599 = _T_47 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_602 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_603 = _T_599 & _T_602; // @[dbg.scala 419:138] + wire [63:0] _T_604 = _T_595 | _T_603; // @[dbg.scala 419:96] + wire [63:0] _T_608 = _T_51 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_610 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_611 = _T_608 & _T_610; // @[dbg.scala 420:45] + wire [63:0] _T_612 = _T_604 | _T_611; // @[dbg.scala 419:168] + wire [63:0] _T_616 = _T_57 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_619 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_620 = _T_616 & _T_619; // @[dbg.scala 420:119] + wire [7:0] _T_625 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _T_627 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82] + wire [14:0] _GEN_115 = {{7'd0}, _T_625}; // @[dbg.scala 422:67] + wire [14:0] _T_628 = _GEN_115 & _T_627; // @[dbg.scala 422:67] + wire [7:0] _T_632 = _T_47 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_634 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_635 = 15'h3 << _T_634; // @[dbg.scala 423:59] + wire [14:0] _GEN_116 = {{7'd0}, _T_632}; // @[dbg.scala 423:44] + wire [14:0] _T_636 = _GEN_116 & _T_635; // @[dbg.scala 423:44] + wire [14:0] _T_637 = _T_628 | _T_636; // @[dbg.scala 422:107] + wire [7:0] _T_641 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_643 = {sbaddress0_reg[2],2'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_644 = 15'hf << _T_643; // @[dbg.scala 424:59] + wire [14:0] _GEN_117 = {{7'd0}, _T_641}; // @[dbg.scala 424:44] + wire [14:0] _T_645 = _GEN_117 & _T_644; // @[dbg.scala 424:44] + wire [14:0] _T_646 = _T_637 | _T_645; // @[dbg.scala 423:97] + wire [7:0] _T_650 = _T_57 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _GEN_118 = {{7'd0}, _T_650}; // @[dbg.scala 424:100] + wire [14:0] _T_652 = _T_646 | _GEN_118; // @[dbg.scala 424:100] + wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99] + wire [6:0] _T_663 = 4'h8 * _GEN_119; // @[dbg.scala 441:99] + wire [63:0] _T_664 = io_sb_axi_r_bits_data >> _T_663; // @[dbg.scala 441:92] + wire [63:0] _T_665 = _T_664 & 64'hff; // @[dbg.scala 441:123] + wire [63:0] _T_666 = _T_590 & _T_665; // @[dbg.scala 441:59] + wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86] + wire [6:0] _T_673 = 5'h10 * _GEN_120; // @[dbg.scala 442:86] + wire [63:0] _T_674 = io_sb_axi_r_bits_data >> _T_673; // @[dbg.scala 442:78] + wire [63:0] _T_675 = _T_674 & 64'hffff; // @[dbg.scala 442:110] + wire [63:0] _T_676 = _T_599 & _T_675; // @[dbg.scala 442:45] + wire [63:0] _T_677 = _T_666 | _T_676; // @[dbg.scala 441:140] + wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86] + wire [6:0] _T_684 = 6'h20 * _GEN_121; // @[dbg.scala 443:86] + wire [63:0] _T_685 = io_sb_axi_r_bits_data >> _T_684; // @[dbg.scala 443:78] + wire [63:0] _T_686 = _T_685 & 64'hffffffff; // @[dbg.scala 443:107] + wire [63:0] _T_687 = _T_608 & _T_686; // @[dbg.scala 443:45] + wire [63:0] _T_688 = _T_677 | _T_687; // @[dbg.scala 442:129] + wire [63:0] _T_694 = _T_616 & io_sb_axi_r_bits_data; // @[dbg.scala 444:45] rvclkhdr rvclkhdr ( // @[lib.scala 327:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -662,10 +660,10 @@ module dbg( ); assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 329:19] assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 100:21] - assign io_dbg_halt_req = _T_328 ? _T_344 : _GEN_36; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23] - assign io_dbg_resume_req = _T_328 ? 1'h0 : _GEN_39; // @[dbg.scala 262:21 dbg.scala 282:25] - assign io_dmi_reg_rdata = _T_502; // @[dbg.scala 320:20] - assign io_sb_axi_aw_valid = _T_595 | _T_596; // @[dbg.scala 407:22] + assign io_dbg_halt_req = _T_313 ? _T_329 : _GEN_35; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23] + assign io_dbg_resume_req = _T_313 ? 1'h0 : _GEN_38; // @[dbg.scala 262:21 dbg.scala 282:25] + assign io_dmi_reg_rdata = _T_485; // @[dbg.scala 320:20] + assign io_sb_axi_aw_valid = _T_577 | _T_578; // @[dbg.scala 407:22] assign io_sb_axi_aw_bits_id = 1'h0; // @[dbg.scala 409:24] assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 408:26] assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 413:28] @@ -676,9 +674,9 @@ module dbg( assign io_sb_axi_aw_bits_cache = 4'hf; // @[dbg.scala 412:27] assign io_sb_axi_aw_bits_prot = 3'h0; // @[dbg.scala 411:26] assign io_sb_axi_aw_bits_qos = 4'h0; // @[dbg.scala 416:25] - assign io_sb_axi_w_valid = _T_595 | _T_602; // @[dbg.scala 418:21] - assign io_sb_axi_w_bits_data = _T_630 | _T_638; // @[dbg.scala 419:25] - assign io_sb_axi_w_bits_strb = _T_670[7:0]; // @[dbg.scala 422:25] + assign io_sb_axi_w_valid = _T_577 | _T_584; // @[dbg.scala 418:21] + assign io_sb_axi_w_bits_data = _T_612 | _T_620; // @[dbg.scala 419:25] + assign io_sb_axi_w_bits_strb = _T_652[7:0]; // @[dbg.scala 422:25] assign io_sb_axi_w_bits_last = 1'h1; // @[dbg.scala 427:25] assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 439:21] assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 428:22] @@ -693,43 +691,43 @@ module dbg( assign io_sb_axi_ar_bits_prot = 3'h0; // @[dbg.scala 432:26] assign io_sb_axi_ar_bits_qos = 4'h0; // @[dbg.scala 437:25] assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 440:21] - assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_515 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 326:35] + assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_498 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 326:35] assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 327:35] - assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_504 ? 2'h2 : _T_524; // @[dbg.scala 328:34] - assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_504 ? {{1'd0}, _T_506} : _T_508; // @[dbg.scala 324:34] + assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_487 ? 2'h2 : _T_507; // @[dbg.scala 328:34] + assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_487 ? _T_489 : _T_491; // @[dbg.scala 324:34] assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 325:38] assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 449:39] assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 450:39] assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 451:39] assign io_dbg_dma_dbg_ib_dbg_cmd_addr = io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[dbg.scala 447:39] assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 448:39] - assign io_dbg_dma_io_dbg_dma_bubble = _T_515 | _T_307; // @[dbg.scala 330:32] - assign dbg_state = _T_499; // @[dbg.scala 315:13] - assign dbg_state_en = _T_328 ? _T_340 : _GEN_35; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20] - assign sb_state = _T_582; // @[dbg.scala 397:12] - assign sb_state_en = _T_535 ? _T_538 : _GEN_102; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19] - assign dmcontrol_reg = {_T_157,_T_155}; // @[dbg.scala 178:17] - assign sbaddress0_reg = _T_128; // @[dbg.scala 159:18] - assign sbcs_sbbusy_wren = _T_535 ? sb_state_en : _GEN_105; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24] - assign sbcs_sberror_wren = _T_535 ? _T_541 : _GEN_103; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25] - assign sb_bus_rdata = _T_706 | _T_712; // @[dbg.scala 441:16] - assign sbaddress0_reg_wren1 = _T_535 ? 1'h0 : _GEN_107; // @[dbg.scala 339:24 dbg.scala 394:28] - assign dmstatus_reg = {_T_177,_T_173}; // @[dbg.scala 184:16] - assign dmstatus_havereset = _T_210; // @[dbg.scala 201:22] - assign dmstatus_resumeack = _T_201; // @[dbg.scala 193:22] - assign dmstatus_unavail = dmcontrol_reg[1] | _T_194; // @[dbg.scala 191:20] - assign dmstatus_running = ~_T_197; // @[dbg.scala 192:20] - assign dmstatus_halted = _T_206; // @[dbg.scala 197:19] - assign abstractcs_busy_wren = _T_328 ? 1'h0 : _GEN_37; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28] + assign io_dbg_dma_io_dbg_dma_bubble = _T_498 | _T_294; // @[dbg.scala 330:32] + assign dbg_state = _T_483; // @[dbg.scala 315:13] + assign dbg_state_en = _T_313 ? _T_325 : _GEN_34; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20] + assign sb_state = _T_564; // @[dbg.scala 397:12] + assign sb_state_en = _T_518 ? _T_521 : _GEN_101; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19] + assign dmcontrol_reg = {_T_149,_T_147}; // @[dbg.scala 178:17] + assign sbaddress0_reg = _T_121; // @[dbg.scala 159:18] + assign sbcs_sbbusy_wren = _T_518 ? sb_state_en : _GEN_104; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24] + assign sbcs_sberror_wren = _T_518 ? _T_524 : _GEN_102; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25] + assign sb_bus_rdata = _T_688 | _T_694; // @[dbg.scala 441:16] + assign sbaddress0_reg_wren1 = _T_518 ? 1'h0 : _GEN_106; // @[dbg.scala 339:24 dbg.scala 394:28] + assign dmstatus_reg = {_T_168,_T_164}; // @[dbg.scala 184:16] + assign dmstatus_havereset = _T_200; // @[dbg.scala 201:22] + assign dmstatus_resumeack = _T_191; // @[dbg.scala 193:22] + assign dmstatus_unavail = dmcontrol_reg[1] | _T_185; // @[dbg.scala 191:20] + assign dmstatus_running = ~_T_188; // @[dbg.scala 192:20] + assign dmstatus_halted = _T_195; // @[dbg.scala 197:19] + assign abstractcs_busy_wren = _T_313 ? 1'h0 : _GEN_36; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28] assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 401:19] assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 402:25] assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 403:25] assign sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 404:19] - assign sb_bus_rsp_error = _T_590 | _T_593; // @[dbg.scala 406:20] + assign sb_bus_rsp_error = _T_572 | _T_575; // @[dbg.scala 406:20] assign sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 405:20] assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 336:19 dbg.scala 345:23 dbg.scala 393:23] - assign data1_reg = _T_327; // @[dbg.scala 252:13] - assign sbcs_reg = {_T_48,_T_44}; // @[dbg.scala 125:12] + assign data1_reg = _T_312; // @[dbg.scala 252:13] + assign sbcs_reg = {_T_44,_T_40}; // @[dbg.scala 125:12] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -745,17 +743,17 @@ module dbg( assign rvclkhdr_4_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 355:17] assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] - assign abstractcs_reg = {_T_289,_T_287}; // @[dbg.scala 233:18] + assign abstractcs_reg = {_T_277,_T_275}; // @[dbg.scala 233:18] assign rvclkhdr_5_io_clk = clock; // @[lib.scala 354:18] - assign rvclkhdr_5_io_en = _T_235 & _T_294; // @[lib.scala 355:17] + assign rvclkhdr_5_io_en = _T_225 & _T_282; // @[lib.scala 355:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_6_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[lib.scala 355:17] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_7_io_clk = clock; // @[lib.scala 354:18] - assign rvclkhdr_7_io_en = _T_321 & _T_294; // @[lib.scala 355:17] + assign rvclkhdr_7_io_en = _T_307 & _T_282; // @[lib.scala 355:17] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] - assign dbg_nxtstate = _T_328 ? _T_331 : _GEN_34; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20] + assign dbg_nxtstate = _T_313 ? _T_316 : _GEN_33; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -806,7 +804,7 @@ initial begin _RAND_6 = {1{`RANDOM}}; sbdata1_reg = _RAND_6[31:0]; _RAND_7 = {1{`RANDOM}}; - _T_128 = _RAND_7[31:0]; + _T_121 = _RAND_7[31:0]; _RAND_8 = {1{`RANDOM}}; dm_temp = _RAND_8[3:0]; _RAND_9 = {1{`RANDOM}}; @@ -814,11 +812,11 @@ initial begin _RAND_10 = {1{`RANDOM}}; dmcontrol_wren_Q = _RAND_10[0:0]; _RAND_11 = {1{`RANDOM}}; - _T_201 = _RAND_11[0:0]; + _T_191 = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - _T_206 = _RAND_12[0:0]; + _T_195 = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - _T_210 = _RAND_13[0:0]; + _T_200 = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; abs_temp_12 = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; @@ -828,79 +826,79 @@ initial begin _RAND_17 = {1{`RANDOM}}; data0_reg = _RAND_17[31:0]; _RAND_18 = {1{`RANDOM}}; - _T_327 = _RAND_18[31:0]; + _T_312 = _RAND_18[31:0]; _RAND_19 = {1{`RANDOM}}; - _T_499 = _RAND_19[2:0]; + _T_483 = _RAND_19[2:0]; _RAND_20 = {1{`RANDOM}}; - _T_502 = _RAND_20[31:0]; + _T_485 = _RAND_20[31:0]; _RAND_21 = {1{`RANDOM}}; - _T_582 = _RAND_21[3:0]; + _T_564 = _RAND_21[3:0]; `endif // RANDOMIZE_REG_INIT - if (_T_30) begin + if (_T_29) begin temp_sbcs_22 = 1'h0; end - if (_T_30) begin + if (_T_29) begin temp_sbcs_21 = 1'h0; end - if (_T_30) begin + if (_T_29) begin temp_sbcs_20 = 1'h0; end - if (_T_30) begin + if (_T_29) begin temp_sbcs_19_15 = 5'h0; end - if (_T_30) begin + if (_T_36) begin temp_sbcs_14_12 = 3'h0; end - if (_T_30) begin + if (_T_29) begin sbdata0_reg = 32'h0; end - if (_T_30) begin + if (_T_29) begin sbdata1_reg = 32'h0; end - if (_T_30) begin - _T_128 = 32'h0; + if (_T_29) begin + _T_121 = 32'h0; end - if (_T_30) begin + if (_T_29) begin dm_temp = 4'h0; end if (io_dbg_rst_l) begin dm_temp_0 = 1'h0; end - if (_T_30) begin + if (_T_29) begin dmcontrol_wren_Q = 1'h0; end - if (_T_30) begin - _T_201 = 1'h0; + if (_T_29) begin + _T_191 = 1'h0; end - if (_T_30) begin - _T_206 = 1'h0; + if (_T_29) begin + _T_195 = 1'h0; end - if (_T_30) begin - _T_210 = 1'h0; + if (_T_29) begin + _T_200 = 1'h0; end - if (_T_30) begin + if (_T_29) begin abs_temp_12 = 1'h0; end - if (_T_30) begin + if (_T_29) begin abs_temp_10_8 = 3'h0; end - if (_T_30) begin + if (_T_29) begin command_reg = 32'h0; end - if (_T_30) begin + if (_T_29) begin data0_reg = 32'h0; end - if (_T_30) begin - _T_327 = 32'h0; + if (_T_29) begin + _T_312 = 32'h0; end - if (_T_498) begin - _T_499 = 3'h0; + if (_T_482) begin + _T_483 = 3'h0; end - if (_T_30) begin - _T_502 = 32'h0; + if (_T_29) begin + _T_485 = 32'h0; end - if (_T_30) begin - _T_582 = 4'h0; + if (_T_29) begin + _T_564 = 4'h0; end `endif // RANDOMIZE end // initial @@ -908,95 +906,95 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin + if (_T_29) begin temp_sbcs_22 <= 1'h0; end else if (sbcs_sbbusyerror_wren) begin temp_sbcs_22 <= sbcs_sbbusyerror_din; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin + if (_T_29) begin temp_sbcs_21 <= 1'h0; end else if (sbcs_sbbusy_wren) begin temp_sbcs_21 <= sbcs_sbbusy_din; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin + if (_T_29) begin temp_sbcs_20 <= 1'h0; end else if (sbcs_wren) begin temp_sbcs_20 <= io_dmi_reg_wdata[20]; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin + if (_T_29) begin temp_sbcs_19_15 <= 5'h0; end else if (sbcs_wren) begin temp_sbcs_19_15 <= io_dmi_reg_wdata[19:15]; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_36) begin + if (_T_36) begin temp_sbcs_14_12 <= 3'h0; end else if (sbcs_sberror_wren) begin - if (_T_535) begin - temp_sbcs_14_12 <= _T_545; - end else if (_T_546) begin + if (_T_518) begin + temp_sbcs_14_12 <= _T_528; + end else if (_T_529) begin if (sbcs_unaligned) begin temp_sbcs_14_12 <= 3'h3; end else begin temp_sbcs_14_12 <= 3'h4; end + end else if (_T_536) begin + if (sbcs_unaligned) begin + temp_sbcs_14_12 <= 3'h3; + end else begin + temp_sbcs_14_12 <= 3'h4; + end + end else if (_T_543) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_545) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_551) begin + temp_sbcs_14_12 <= 3'h0; end else if (_T_553) begin - if (sbcs_unaligned) begin - temp_sbcs_14_12 <= 3'h3; - end else begin - temp_sbcs_14_12 <= 3'h4; - end - end else if (_T_560) begin temp_sbcs_14_12 <= 3'h0; - end else if (_T_562) begin - temp_sbcs_14_12 <= 3'h0; - end else if (_T_568) begin - temp_sbcs_14_12 <= 3'h0; - end else if (_T_570) begin - temp_sbcs_14_12 <= 3'h0; - end else if (_T_572) begin + end else if (_T_555) begin temp_sbcs_14_12 <= 3'h2; - end else if (_T_575) begin + end else if (_T_558) begin temp_sbcs_14_12 <= 3'h2; end else begin temp_sbcs_14_12 <= 3'h0; end end end - always @(posedge rvclkhdr_2_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_2_io_l1clk or posedge _T_29) begin + if (_T_29) begin sbdata0_reg <= 32'h0; end else begin - sbdata0_reg <= _T_99 | _T_103; + sbdata0_reg <= _T_95 | _T_99; end end - always @(posedge rvclkhdr_3_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_3_io_l1clk or posedge _T_29) begin + if (_T_29) begin sbdata1_reg <= 32'h0; end else begin - sbdata1_reg <= _T_106 | _T_110; + sbdata1_reg <= _T_102 | _T_106; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_128 <= 32'h0; + always @(posedge rvclkhdr_4_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_121 <= 32'h0; end else begin - _T_128 <= _T_119 | _T_125; + _T_121 <= _T_113 | _T_119; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin dm_temp <= 4'h0; end else if (dmcontrol_wren) begin - dm_temp <= _T_148; + dm_temp <= _T_140; end end always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin @@ -1006,177 +1004,177 @@ end // initial dm_temp_0 <= io_dmi_reg_wdata[0]; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin dmcontrol_wren_Q <= 1'h0; end else begin - dmcontrol_wren_Q <= _T_141 & io_dmi_reg_wr_en; + dmcontrol_wren_Q <= _T_134 & io_dmi_reg_wr_en; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_201 <= 1'h0; + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_191 <= 1'h0; end else if (dmstatus_resumeack_wren) begin - _T_201 <= _T_180; + _T_191 <= _T_171; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_206 <= 1'h0; + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_195 <= 1'h0; end else begin - _T_206 <= io_dec_tlu_dbg_halted & _T_204; + _T_195 <= io_dec_tlu_dbg_halted & _T_193; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_210 <= 1'h0; - end else if (dmstatus_havereset_wren) begin - _T_210 <= _T_209; + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_200 <= 1'h0; + end else begin + _T_200 <= _T_197 & _T_198; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin abs_temp_12 <= 1'h0; end else if (abstractcs_busy_wren) begin - if (_T_328) begin + if (_T_313) begin abs_temp_12 <= 1'h0; - end else if (_T_346) begin + end else if (_T_331) begin abs_temp_12 <= 1'h0; end else begin - abs_temp_12 <= _T_358; + abs_temp_12 <= _T_343; end end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin abs_temp_10_8 <= 3'h0; end else begin - abs_temp_10_8 <= _T_276 | _T_281; + abs_temp_10_8 <= _T_266 | _T_271; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge _T_29) begin + if (_T_29) begin command_reg <= 32'h0; end else begin - command_reg <= {_T_300,_T_298}; + command_reg <= {_T_288,_T_286}; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge _T_29) begin + if (_T_29) begin data0_reg <= 32'h0; end else begin - data0_reg <= _T_313 | _T_316; + data0_reg <= _T_300 | _T_303; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_327 <= 32'h0; + always @(posedge rvclkhdr_7_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_312 <= 32'h0; end else begin - _T_327 <= _T_324 & io_dmi_reg_wdata; + _T_312 <= _T_310 & io_dmi_reg_wdata; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_498) begin - if (_T_498) begin - _T_499 <= 3'h0; + always @(posedge rvclkhdr_io_l1clk or posedge _T_482) begin + if (_T_482) begin + _T_483 <= 3'h0; end else if (dbg_state_en) begin - if (_T_328) begin - if (_T_330) begin - _T_499 <= 3'h2; + if (_T_313) begin + if (_T_315) begin + _T_483 <= 3'h2; end else begin - _T_499 <= 3'h1; + _T_483 <= 3'h1; end - end else if (_T_346) begin + end else if (_T_331) begin if (dmcontrol_reg[1]) begin - _T_499 <= 3'h0; + _T_483 <= 3'h0; end else begin - _T_499 <= 3'h2; + _T_483 <= 3'h2; end - end else if (_T_358) begin - if (_T_362) begin - if (_T_366) begin - _T_499 <= 3'h6; + end else if (_T_343) begin + if (_T_347) begin + if (_T_351) begin + _T_483 <= 3'h6; end else begin - _T_499 <= 3'h3; + _T_483 <= 3'h3; end end else if (dmcontrol_reg[31]) begin - _T_499 <= 3'h1; + _T_483 <= 3'h1; end else begin - _T_499 <= 3'h0; + _T_483 <= 3'h0; end - end else if (_T_396) begin + end else if (_T_381) begin if (dmcontrol_reg[1]) begin - _T_499 <= 3'h0; - end else if (_T_399) begin - _T_499 <= 3'h5; + _T_483 <= 3'h0; + end else if (_T_384) begin + _T_483 <= 3'h5; end else begin - _T_499 <= 3'h4; + _T_483 <= 3'h4; end - end else if (_T_413) begin + end else if (_T_398) begin if (dmcontrol_reg[1]) begin - _T_499 <= 3'h0; + _T_483 <= 3'h0; end else begin - _T_499 <= 3'h5; + _T_483 <= 3'h5; end - end else if (_T_424) begin + end else if (_T_409) begin if (dmcontrol_reg[1]) begin - _T_499 <= 3'h0; + _T_483 <= 3'h0; end else begin - _T_499 <= 3'h2; + _T_483 <= 3'h2; end end else begin - _T_499 <= 3'h0; + _T_483 <= 3'h0; end end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_502 <= 32'h0; + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_485 <= 32'h0; end else if (io_dmi_reg_en) begin - _T_502 <= dmi_reg_rdata_din; + _T_485 <= dmi_reg_rdata_din; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_582 <= 4'h0; + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_564 <= 4'h0; end else if (sb_state_en) begin - if (_T_535) begin + if (_T_518) begin if (sbdata0_reg_wren0) begin - _T_582 <= 4'h2; + _T_564 <= 4'h2; end else begin - _T_582 <= 4'h1; + _T_564 <= 4'h1; end - end else if (_T_546) begin - if (_T_547) begin - _T_582 <= 4'h9; + end else if (_T_529) begin + if (_T_530) begin + _T_564 <= 4'h9; end else begin - _T_582 <= 4'h3; + _T_564 <= 4'h3; end - end else if (_T_553) begin - if (_T_547) begin - _T_582 <= 4'h9; + end else if (_T_536) begin + if (_T_530) begin + _T_564 <= 4'h9; end else begin - _T_582 <= 4'h4; + _T_564 <= 4'h4; end - end else if (_T_560) begin - _T_582 <= 4'h7; - end else if (_T_562) begin - if (_T_563) begin - _T_582 <= 4'h8; + end else if (_T_543) begin + _T_564 <= 4'h7; + end else if (_T_545) begin + if (_T_546) begin + _T_564 <= 4'h8; end else if (sb_bus_cmd_write_data) begin - _T_582 <= 4'h5; + _T_564 <= 4'h5; end else begin - _T_582 <= 4'h6; + _T_564 <= 4'h6; end - end else if (_T_568) begin - _T_582 <= 4'h8; - end else if (_T_570) begin - _T_582 <= 4'h8; - end else if (_T_572) begin - _T_582 <= 4'h9; - end else if (_T_575) begin - _T_582 <= 4'h9; + end else if (_T_551) begin + _T_564 <= 4'h8; + end else if (_T_553) begin + _T_564 <= 4'h8; + end else if (_T_555) begin + _T_564 <= 4'h9; + end else if (_T_558) begin + _T_564 <= 4'h9; end else begin - _T_582 <= 4'h0; + _T_564 <= 4'h0; end end end diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index 40eae7ce..d4456bc6 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1,3 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/gated_latch.v -/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv -/home/waleedbinehsan/Desktop/Quasar/mem.sv \ No newline at end of file +/home/waleedbinehsan/Desktop/Quasar/gated_latch.v \ No newline at end of file diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala index 80b5fbca..49d28481 100644 --- a/src/main/scala/dbg/dbg.scala +++ b/src/main/scala/dbg/dbg.scala @@ -103,19 +103,19 @@ class dbg extends Module with lib with RequireAsyncReset { ((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U))) val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt() - val temp_sbcs_22 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val temp_sbcs_22 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren) } // sbcs_sbbusyerror_reg - val temp_sbcs_21 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val temp_sbcs_21 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren) } // sbcs_sbbusy_reg - val temp_sbcs_20 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val temp_sbcs_20 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren) } // sbcs_sbreadonaddr_reg - val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren) } // sbcs_misc_reg @@ -124,13 +124,13 @@ class dbg extends Module with lib with RequireAsyncReset { } // sbcs_error_reg sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W)) - val sbcs_unaligned = (sbcs_reg(19, 17) === "b001".U) & sbaddress0_reg(0) | - (sbcs_reg(19, 17) === "b010".U) & sbaddress0_reg(1, 0).orR | - (sbcs_reg(19, 17) === "b011".U) & sbaddress0_reg(2, 0).orR + val sbcs_unaligned = (sbcs_reg(19, 17) === "b001".U(3.W)) & sbaddress0_reg(0) | + (sbcs_reg(19, 17) === "b010".U(3.W)) & sbaddress0_reg(1, 0).orR | + (sbcs_reg(19, 17) === "b011".U(3.W)) & sbaddress0_reg(2, 0).orR val sbcs_illegal_size = sbcs_reg(19) - val sbaddress0_incr = Fill(4, (sbcs_reg(19, 17) === "h0".U)) & "b0001".U | Fill(4, (sbcs_reg(19, 17) === "h1".U)) & "b0010".U | - Fill(4, (sbcs_reg(19, 17) === "h2".U)) & "b0100".U | Fill(4, (sbcs_reg(19, 17) === "h3".U)) & "b1000".U + val sbaddress0_incr = Fill(4, (sbcs_reg(19, 17) === "h0".U)) & "b0001".U(4.W) | Fill(4, (sbcs_reg(19, 17) === "h1".U)) & "b0010".U(4.W) | + Fill(4, (sbcs_reg(19, 17) === "h2".U)) & "b0100".U(4.W) | Fill(4, (sbcs_reg(19, 17) === "h3".U)) & "b1000".U(4.W) val sbdata0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) val sbdata0_reg_wren1 = (sb_state === sb_state_t.rsp_rd) & sb_state_en & !sbcs_sberror_wren @@ -144,11 +144,11 @@ class dbg extends Module with lib with RequireAsyncReset { val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata | Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32) - val sbdata0_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { + val sbdata0_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode) } // dbg_sbdata0_reg - val sbdata1_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { + val sbdata1_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode) } // dbg_sbdata1_reg @@ -156,7 +156,7 @@ class dbg extends Module with lib with RequireAsyncReset { val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1 val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata | Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr)) - sbaddress0_reg := withReset((!dbg_dm_rst_l).asAsyncReset()) { + sbaddress0_reg := withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode) } // dbg_sbaddress0_reg @@ -164,7 +164,7 @@ class dbg extends Module with lib with RequireAsyncReset { val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15) val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en - val dm_temp = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val dm_temp = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable( Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)), 0.U, dmcontrol_wren) @@ -177,7 +177,7 @@ class dbg extends Module with lib with RequireAsyncReset { val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0) dmcontrol_reg := temp - val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegNext(dmcontrol_wren, 0.U) } // dmcontrol_wrenff @@ -190,16 +190,16 @@ class dbg extends Module with lib with RequireAsyncReset { val temp_rst = reset.asBool() dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool() dmstatus_running := ~(dmstatus_unavail | dmstatus_halted) - dmstatus_resumeack := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + dmstatus_resumeack := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren) } // dmstatus_resumeack_reg - dmstatus_halted := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + dmstatus_halted := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U) } // dmstatus_halted_reg - dmstatus_havereset := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { - RegEnable(~dmstatus_havereset_rst, 0.U, dmstatus_havereset_wren) + dmstatus_havereset := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { + RegNext(Mux(dmstatus_havereset_wren, true.B, dmstatus_havereset) & !dmstatus_havereset_rst, false.B) } // dmstatus_havereset_reg val haltsum0_reg = Cat(0.U(31.W), dmstatus_halted) @@ -210,23 +210,23 @@ class dbg extends Module with lib with RequireAsyncReset { val abstractcs_error_sel2 = io.core_dbg_cmd_done & io.core_dbg_cmd_fail val abstractcs_error_sel3 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h17".U) & !dmstatus_reg(9); val abstractcs_error_sel4 = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & - ((io.dmi_reg_wdata(22, 20) =/= "b010".U) | ((io.dmi_reg_wdata(31, 24) === "h2".U) && data1_reg(1, 0).orR)) + ((io.dmi_reg_wdata(22, 20) =/= "b010".U(3.W)) | ((io.dmi_reg_wdata(31, 24) === "h2".U) && data1_reg(1, 0).orR)) val abstractcs_error_sel5 = (io.dmi_reg_addr === "h16".U) & io.dmi_reg_en & io.dmi_reg_wr_en val abstractcs_error_selor = abstractcs_error_sel0 | abstractcs_error_sel1 | abstractcs_error_sel2 | abstractcs_error_sel3 | abstractcs_error_sel4 | abstractcs_error_sel5 - val abstractcs_error_din = (Fill(3, abstractcs_error_sel0) & "b001".U) | - (Fill(3, abstractcs_error_sel1) & "b010".U) | - (Fill(3, abstractcs_error_sel2) & "b011".U) | - (Fill(3, abstractcs_error_sel3) & "b100".U) | - (Fill(3, abstractcs_error_sel4) & "b111".U) | + val abstractcs_error_din = (Fill(3, abstractcs_error_sel0) & "b001".U(3.W)) | + (Fill(3, abstractcs_error_sel1) & "b010".U(3.W)) | + (Fill(3, abstractcs_error_sel2) & "b011".U(3.W)) | + (Fill(3, abstractcs_error_sel3) & "b100".U(3.W)) | + (Fill(3, abstractcs_error_sel4) & "b111".U(3.W)) | (Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) | (Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8)) - val abs_temp_12 = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val abs_temp_12 = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren) } // dmabstractcs_busy_reg - val abs_temp_10_8 = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val abs_temp_10_8 = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegNext(abstractcs_error_din(2, 0), 0.U) } // dmabstractcs_error_reg @@ -234,7 +234,7 @@ class dbg extends Module with lib with RequireAsyncReset { val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted) val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0)) - val command_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { + val command_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(command_din, command_wren,clock,io.scan_mode) } // dmcommand_reg @@ -243,13 +243,13 @@ class dbg extends Module with lib with RequireAsyncReset { val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata - val data0_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { + val data0_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(data0_din,data0_reg_wren,clock,io.scan_mode) } // dbg_data0_reg val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted)) val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata - data1_reg := withReset((!dbg_dm_rst_l).asAsyncReset()) { + data1_reg := withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode) } // dbg_data1_reg @@ -273,7 +273,7 @@ class dbg extends Module with lib with RequireAsyncReset { } is(state_t.halted) { dbg_nxtstate := Mux(dmstatus_reg(9) & !dmcontrol_reg(1), - Mux(dmcontrol_reg(30) & !dmcontrol_reg(3), state_t.resuming, state_t.cmd_start), + Mux(dmcontrol_reg(30) & !dmcontrol_reg(31), state_t.resuming, state_t.cmd_start), Mux(dmcontrol_reg(31), state_t.halting, state_t.idle)) dbg_state_en := dmstatus_reg(9) & dmcontrol_reg(30) & !dmcontrol_reg(31) & dmcontrol_wren_Q | command_wren | dmcontrol_reg(1) | !(dmstatus_reg(9) | io.dec_tlu_mpc_halted_only) @@ -311,21 +311,21 @@ class dbg extends Module with lib with RequireAsyncReset { Fill(32, io.dmi_reg_addr === "h40".U) & haltsum0_reg | Fill(32, io.dmi_reg_addr === "h38".U) & sbcs_reg | Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg | Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg - 0 - dbg_state := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l & temp_rst).asAsyncReset()) { + + dbg_state := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l & temp_rst).asAsyncReset()) { RegEnable(dbg_nxtstate, 0.U, dbg_state_en) } // dbg_state_reg - io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en) } // dmi_rddata_reg - io.dbg_dec.dbg_ib.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), Cat(data1_reg(31, 2), "b00".U), Cat(0.U(20.W), command_reg(11, 0))) + io.dbg_dec.dbg_ib.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), Cat(data1_reg(31, 2), "b00".U(2.W)), Cat(0.U(20.W), command_reg(11, 0))) io.dbg_dec.dbg_dctl.dbg_cmd_wrdata := data0_reg(31, 0) io.dbg_dec.dbg_ib.dbg_cmd_valid := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) & io.dbg_dma_io.dma_dbg_ready).asBool() io.dbg_dec.dbg_ib.dbg_cmd_write := command_reg(16).asBool() - io.dbg_dec.dbg_ib.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U, Cat("b0".U, (command_reg(15, 12) === "b0".U))) + io.dbg_dec.dbg_ib.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U(2.W), Cat("b0".U, (command_reg(15, 12) === "b0".U))) io.dbg_cmd_size := command_reg(21, 20) io.dbg_dma_io.dbg_dma_bubble := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) | (dbg_state === state_t.cmd_wait)).asBool() @@ -344,19 +344,19 @@ class dbg extends Module with lib with RequireAsyncReset { sbcs_sbbusy_wren := sb_state_en sbcs_sbbusy_din := true.B sbcs_sberror_wren := sbcs_wren & io.dmi_reg_wdata(14, 12).orR - sbcs_sberror_din := !io.dmi_reg_wdata(14, 12) & sbcs_reg(14, 12) + sbcs_sberror_din := ~io.dmi_reg_wdata(14, 12) & sbcs_reg(14, 12) } is(sb_state_t.wait_rd) { sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_rd) sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size - sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U, "b100".U) + sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U(3.W), "b100".U(3.W)) } is(sb_state_t.wait_wr) { sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_wr) sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size; - sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U, "b100".U) + sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U(3.W), "b100".U) } is(sb_state_t.cmd_rd) { sb_nxtstate := sb_state_t.rsp_rd @@ -378,13 +378,13 @@ class dbg extends Module with lib with RequireAsyncReset { sb_nxtstate := sb_state_t.done sb_state_en := sb_bus_rsp_read & io.dbg_bus_clk_en sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error - sbcs_sberror_din := "b010".U + sbcs_sberror_din := "b010".U(3.W) } is(sb_state_t.rsp_wr) { sb_nxtstate := sb_state_t.done; sb_state_en := sb_bus_rsp_write & io.dbg_bus_clk_en sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error - sbcs_sberror_din := "b010".U + sbcs_sberror_din := "b010".U(3.W) } is(sb_state_t.done) { sb_nxtstate := sb_state_t.sbidle; @@ -394,7 +394,7 @@ class dbg extends Module with lib with RequireAsyncReset { sbaddress0_reg_wren1 := sbcs_reg(16) }} - sb_state := withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + sb_state := withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(sb_nxtstate, 0.U, sb_state_en) } // sb_state_reg @@ -412,7 +412,7 @@ class dbg extends Module with lib with RequireAsyncReset { io.sb_axi.aw.bits.cache := "b1111".U io.sb_axi.aw.bits.region := sbaddress0_reg(31, 28) io.sb_axi.aw.bits.len := 0.U - io.sb_axi.aw.bits.burst := "b01".U + io.sb_axi.aw.bits.burst := "b01".U(2.W) io.sb_axi.aw.bits.qos := 0.U io.sb_axi.aw.bits.lock := false.B io.sb_axi.w.valid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_data)).asBool() @@ -421,7 +421,7 @@ class dbg extends Module with lib with RequireAsyncReset { io.sb_axi.w.bits.strb := Fill(8, (sbcs_reg(19, 17) === "h0".U)) & ("h1".U(8.W) << sbaddress0_reg(2, 0)) | Fill(8, (sbcs_reg(19, 17) === "h1".U)) & ("h3".U(8.W) << Cat(sbaddress0_reg(2, 1), "b0".U)) | - Fill(8, (sbcs_reg(19, 17) === "h2".U)) & ("hf".U(8.W) << Cat(sbaddress0_reg(2), "b00".U)) | + Fill(8, (sbcs_reg(19, 17) === "h2".U)) & ("hf".U(8.W) << Cat(sbaddress0_reg(2), "b00".U(2.W))) | Fill(8, (sbcs_reg(19, 17) === "h3".U)) & "hff".U io.sb_axi.w.bits.last := true.B @@ -433,7 +433,7 @@ class dbg extends Module with lib with RequireAsyncReset { io.sb_axi.ar.bits.cache := 0.U io.sb_axi.ar.bits.region := sbaddress0_reg(31, 28) io.sb_axi.ar.bits.len := 0.U - io.sb_axi.ar.bits.burst := "b01".U + io.sb_axi.ar.bits.burst := "b01".U(2.W) io.sb_axi.ar.bits.qos := 0.U io.sb_axi.ar.bits.lock := false.B io.sb_axi.b.ready := true.B diff --git a/target/scala-2.12/classes/dbg/dbg.class b/target/scala-2.12/classes/dbg/dbg.class index 0c3e7c94..84070814 100644 Binary files a/target/scala-2.12/classes/dbg/dbg.class and b/target/scala-2.12/classes/dbg/dbg.class differ diff --git a/target/scala-2.12/classes/lsu/lsu_stbuf.class b/target/scala-2.12/classes/lsu/lsu_stbuf.class index ebe39301..711e787c 100644 Binary files a/target/scala-2.12/classes/lsu/lsu_stbuf.class and b/target/scala-2.12/classes/lsu/lsu_stbuf.class differ