From 9a7bf160bf7032204f2e966e39929daa387ad5ea Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Fri, 11 Dec 2020 12:55:39 +0500 Subject: [PATCH] dma added --- dbg.fir | 1650 ++++++++--------- dbg.v | 1196 ++++++------ firrtl_black_box_resource_files.f | 4 +- src/main/scala/dbg/dbg.scala | 88 +- target/scala-2.12/classes/dbg/dbg.class | Bin 275622 -> 275167 bytes target/scala-2.12/classes/lsu/lsu_stbuf.class | Bin 193604 -> 193604 bytes 6 files changed, 1457 insertions(+), 1481 deletions(-) diff --git a/dbg.fir b/dbg.fir index 6a3a7890..c9834437 100644 --- a/dbg.fir +++ b/dbg.fir @@ -301,448 +301,431 @@ circuit dbg : node _T_27 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 105:61] node _T_28 = and(sbcs_wren, _T_27) @[dbg.scala 105:43] node sbcs_sbbusyerror_din = not(_T_28) @[dbg.scala 105:31] - node _T_29 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 106:54] - node _T_30 = asAsyncReset(_T_29) @[dbg.scala 106:81] - reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_30, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_29 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 106:80] + reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_29, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sbbusyerror_wren : @[Reg.scala 28:19] temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_31 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 110:54] - node _T_32 = asAsyncReset(_T_31) @[dbg.scala 110:81] - reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_32, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_30 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 110:80] + reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_30, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sbbusy_wren : @[Reg.scala 28:19] temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_33 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 114:54] - node _T_34 = asAsyncReset(_T_33) @[dbg.scala 114:81] - node _T_35 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 115:31] - reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_34, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_31 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 114:80] + node _T_32 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 115:31] + reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_31, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_wren : @[Reg.scala 28:19] - temp_sbcs_20 <= _T_35 @[Reg.scala 28:23] + temp_sbcs_20 <= _T_32 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_36 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 118:57] - node _T_37 = asAsyncReset(_T_36) @[dbg.scala 118:84] - node _T_38 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 119:31] - reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_37, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_33 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 118:83] + node _T_34 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 119:31] + reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_33, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_wren : @[Reg.scala 28:19] - temp_sbcs_19_15 <= _T_38 @[Reg.scala 28:23] + temp_sbcs_19_15 <= _T_34 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_39 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 122:57] - node _T_40 = asAsyncReset(_T_39) @[dbg.scala 122:84] - node _T_41 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 123:31] - reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_40, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_35 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 122:57] + node _T_36 = asAsyncReset(_T_35) @[dbg.scala 122:84] + node _T_37 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 123:31] + reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_36, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sberror_wren : @[Reg.scala 28:19] - temp_sbcs_14_12 <= _T_41 @[Reg.scala 28:23] + temp_sbcs_14_12 <= _T_37 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_42 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58] - node _T_43 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58] - node _T_44 = cat(_T_43, _T_42) @[Cat.scala 29:58] - node _T_45 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58] - node _T_46 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58] - node _T_47 = cat(_T_46, temp_sbcs_22) @[Cat.scala 29:58] - node _T_48 = cat(_T_47, _T_45) @[Cat.scala 29:58] - node _T_49 = cat(_T_48, _T_44) @[Cat.scala 29:58] - sbcs_reg <= _T_49 @[dbg.scala 125:12] - node _T_50 = bits(sbcs_reg, 19, 17) @[dbg.scala 127:33] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[dbg.scala 127:42] - node _T_52 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 127:72] - node _T_53 = and(_T_51, _T_52) @[dbg.scala 127:56] - node _T_54 = bits(sbcs_reg, 19, 17) @[dbg.scala 128:14] - node _T_55 = eq(_T_54, UInt<2>("h02")) @[dbg.scala 128:23] - node _T_56 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 128:53] - node _T_57 = orr(_T_56) @[dbg.scala 128:60] - node _T_58 = and(_T_55, _T_57) @[dbg.scala 128:37] - node _T_59 = or(_T_53, _T_58) @[dbg.scala 127:76] - node _T_60 = bits(sbcs_reg, 19, 17) @[dbg.scala 129:14] - node _T_61 = eq(_T_60, UInt<2>("h03")) @[dbg.scala 129:23] - node _T_62 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 129:53] - node _T_63 = orr(_T_62) @[dbg.scala 129:60] - node _T_64 = and(_T_61, _T_63) @[dbg.scala 129:37] - node sbcs_unaligned = or(_T_59, _T_64) @[dbg.scala 128:64] + node _T_38 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58] + node _T_39 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58] + node _T_40 = cat(_T_39, _T_38) @[Cat.scala 29:58] + node _T_41 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58] + node _T_42 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, temp_sbcs_22) @[Cat.scala 29:58] + node _T_44 = cat(_T_43, _T_41) @[Cat.scala 29:58] + node _T_45 = cat(_T_44, _T_40) @[Cat.scala 29:58] + sbcs_reg <= _T_45 @[dbg.scala 125:12] + node _T_46 = bits(sbcs_reg, 19, 17) @[dbg.scala 127:33] + node _T_47 = eq(_T_46, UInt<3>("h01")) @[dbg.scala 127:42] + node _T_48 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 127:77] + node _T_49 = and(_T_47, _T_48) @[dbg.scala 127:61] + node _T_50 = bits(sbcs_reg, 19, 17) @[dbg.scala 128:14] + node _T_51 = eq(_T_50, UInt<3>("h02")) @[dbg.scala 128:23] + node _T_52 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 128:58] + node _T_53 = orr(_T_52) @[dbg.scala 128:65] + node _T_54 = and(_T_51, _T_53) @[dbg.scala 128:42] + node _T_55 = or(_T_49, _T_54) @[dbg.scala 127:81] + node _T_56 = bits(sbcs_reg, 19, 17) @[dbg.scala 129:14] + node _T_57 = eq(_T_56, UInt<3>("h03")) @[dbg.scala 129:23] + node _T_58 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 129:58] + node _T_59 = orr(_T_58) @[dbg.scala 129:65] + node _T_60 = and(_T_57, _T_59) @[dbg.scala 129:42] + node sbcs_unaligned = or(_T_55, _T_60) @[dbg.scala 128:69] node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 131:35] - node _T_65 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:42] - node _T_66 = eq(_T_65, UInt<1>("h00")) @[dbg.scala 132:51] - node _T_67 = bits(_T_66, 0, 0) @[Bitwise.scala 72:15] - node _T_68 = mux(_T_67, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_69 = and(_T_68, UInt<1>("h01")) @[dbg.scala 132:64] - node _T_70 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:95] - node _T_71 = eq(_T_70, UInt<1>("h01")) @[dbg.scala 132:104] - node _T_72 = bits(_T_71, 0, 0) @[Bitwise.scala 72:15] - node _T_73 = mux(_T_72, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_74 = and(_T_73, UInt<2>("h02")) @[dbg.scala 132:117] - node _T_75 = or(_T_69, _T_74) @[dbg.scala 132:76] - node _T_76 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:22] - node _T_77 = eq(_T_76, UInt<2>("h02")) @[dbg.scala 133:31] - node _T_78 = bits(_T_77, 0, 0) @[Bitwise.scala 72:15] - node _T_79 = mux(_T_78, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_80 = and(_T_79, UInt<3>("h04")) @[dbg.scala 133:44] - node _T_81 = or(_T_75, _T_80) @[dbg.scala 132:129] - node _T_82 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:75] - node _T_83 = eq(_T_82, UInt<2>("h03")) @[dbg.scala 133:84] - node _T_84 = bits(_T_83, 0, 0) @[Bitwise.scala 72:15] - node _T_85 = mux(_T_84, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_86 = and(_T_85, UInt<4>("h08")) @[dbg.scala 133:97] - node sbaddress0_incr = or(_T_81, _T_86) @[dbg.scala 133:56] - node _T_87 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 135:41] - node _T_88 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 135:79] - node sbdata0_reg_wren0 = and(_T_87, _T_88) @[dbg.scala 135:60] - node _T_89 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 136:37] - node _T_90 = and(_T_89, sb_state_en) @[dbg.scala 136:60] - node _T_91 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 136:76] - node sbdata0_reg_wren1 = and(_T_90, _T_91) @[dbg.scala 136:74] + node _T_61 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:42] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[dbg.scala 132:51] + node _T_63 = bits(_T_62, 0, 0) @[Bitwise.scala 72:15] + node _T_64 = mux(_T_63, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_65 = and(_T_64, UInt<4>("h01")) @[dbg.scala 132:64] + node _T_66 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:100] + node _T_67 = eq(_T_66, UInt<1>("h01")) @[dbg.scala 132:109] + node _T_68 = bits(_T_67, 0, 0) @[Bitwise.scala 72:15] + node _T_69 = mux(_T_68, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_70 = and(_T_69, UInt<4>("h02")) @[dbg.scala 132:122] + node _T_71 = or(_T_65, _T_70) @[dbg.scala 132:81] + node _T_72 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:22] + node _T_73 = eq(_T_72, UInt<2>("h02")) @[dbg.scala 133:31] + node _T_74 = bits(_T_73, 0, 0) @[Bitwise.scala 72:15] + node _T_75 = mux(_T_74, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_76 = and(_T_75, UInt<4>("h04")) @[dbg.scala 133:44] + node _T_77 = or(_T_71, _T_76) @[dbg.scala 132:139] + node _T_78 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:80] + node _T_79 = eq(_T_78, UInt<2>("h03")) @[dbg.scala 133:89] + node _T_80 = bits(_T_79, 0, 0) @[Bitwise.scala 72:15] + node _T_81 = mux(_T_80, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_82 = and(_T_81, UInt<4>("h08")) @[dbg.scala 133:102] + node sbaddress0_incr = or(_T_77, _T_82) @[dbg.scala 133:61] + node _T_83 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 135:41] + node _T_84 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 135:79] + node sbdata0_reg_wren0 = and(_T_83, _T_84) @[dbg.scala 135:60] + node _T_85 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 136:37] + node _T_86 = and(_T_85, sb_state_en) @[dbg.scala 136:60] + node _T_87 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 136:76] + node sbdata0_reg_wren1 = and(_T_86, _T_87) @[dbg.scala 136:74] node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 137:44] - node _T_92 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 138:41] - node _T_93 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 138:79] - node sbdata1_reg_wren0 = and(_T_92, _T_93) @[dbg.scala 138:60] - node _T_94 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 139:37] - node _T_95 = and(_T_94, sb_state_en) @[dbg.scala 139:60] - node _T_96 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 139:76] - node sbdata1_reg_wren1 = and(_T_95, _T_96) @[dbg.scala 139:74] + node _T_88 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 138:41] + node _T_89 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 138:79] + node sbdata1_reg_wren0 = and(_T_88, _T_89) @[dbg.scala 138:60] + node _T_90 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 139:37] + node _T_91 = and(_T_90, sb_state_en) @[dbg.scala 139:60] + node _T_92 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 139:76] + node sbdata1_reg_wren1 = and(_T_91, _T_92) @[dbg.scala 139:74] node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 140:44] - node _T_97 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_98 = mux(_T_97, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_99 = and(_T_98, io.dmi_reg_wdata) @[dbg.scala 141:49] - node _T_100 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_93 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_94 = mux(_T_93, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_95 = and(_T_94, io.dmi_reg_wdata) @[dbg.scala 141:49] + node _T_96 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_97 = mux(_T_96, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_98 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 142:47] + node _T_99 = and(_T_97, _T_98) @[dbg.scala 142:33] + node sbdata0_din = or(_T_95, _T_99) @[dbg.scala 141:68] + node _T_100 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15] node _T_101 = mux(_T_100, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_102 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 142:47] - node _T_103 = and(_T_101, _T_102) @[dbg.scala 142:33] - node sbdata0_din = or(_T_99, _T_103) @[dbg.scala 141:68] - node _T_104 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_105 = mux(_T_104, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_106 = and(_T_105, io.dmi_reg_wdata) @[dbg.scala 144:49] - node _T_107 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15] - node _T_108 = mux(_T_107, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_109 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 145:47] - node _T_110 = and(_T_108, _T_109) @[dbg.scala 145:33] - node sbdata1_din = or(_T_106, _T_110) @[dbg.scala 144:68] - node _T_111 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 147:32] - node _T_112 = asAsyncReset(_T_111) @[dbg.scala 147:59] + node _T_102 = and(_T_101, io.dmi_reg_wdata) @[dbg.scala 144:49] + node _T_103 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_104 = mux(_T_103, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_105 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 145:47] + node _T_106 = and(_T_104, _T_105) @[dbg.scala 145:33] + node sbdata1_din = or(_T_102, _T_106) @[dbg.scala 144:68] + node _T_107 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 147:58] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 352:23] rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= _T_112 + rvclkhdr_2.reset <= _T_107 rvclkhdr_2.io.clk <= clock @[lib.scala 354:18] rvclkhdr_2.io.en <= sbdata0_reg_wren @[lib.scala 355:17] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (_T_112, UInt<1>("h00"))) @[lib.scala 358:16] + reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (_T_107, UInt<1>("h00"))) @[lib.scala 358:16] sbdata0_reg <= sbdata0_din @[lib.scala 358:16] - node _T_113 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 151:32] - node _T_114 = asAsyncReset(_T_113) @[dbg.scala 151:59] + node _T_108 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 151:58] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 352:23] rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= _T_114 + rvclkhdr_3.reset <= _T_108 rvclkhdr_3.io.clk <= clock @[lib.scala 354:18] rvclkhdr_3.io.en <= sbdata1_reg_wren @[lib.scala 355:17] rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (_T_114, UInt<1>("h00"))) @[lib.scala 358:16] + reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (_T_108, UInt<1>("h00"))) @[lib.scala 358:16] sbdata1_reg <= sbdata1_din @[lib.scala 358:16] - node _T_115 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 155:44] - node _T_116 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 155:82] - node sbaddress0_reg_wren0 = and(_T_115, _T_116) @[dbg.scala 155:63] + node _T_109 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 155:44] + node _T_110 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 155:82] + node sbaddress0_reg_wren0 = and(_T_109, _T_110) @[dbg.scala 155:63] node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 156:50] - node _T_117 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_118 = mux(_T_117, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_119 = and(_T_118, io.dmi_reg_wdata) @[dbg.scala 157:59] - node _T_120 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] - node _T_121 = mux(_T_120, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_122 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58] - node _T_123 = add(sbaddress0_reg, _T_122) @[dbg.scala 158:54] - node _T_124 = tail(_T_123, 1) @[dbg.scala 158:54] - node _T_125 = and(_T_121, _T_124) @[dbg.scala 158:36] - node sbaddress0_reg_din = or(_T_119, _T_125) @[dbg.scala 157:78] - node _T_126 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 159:32] - node _T_127 = asAsyncReset(_T_126) @[dbg.scala 159:59] + node _T_111 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_113 = and(_T_112, io.dmi_reg_wdata) @[dbg.scala 157:59] + node _T_114 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_115 = mux(_T_114, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_116 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58] + node _T_117 = add(sbaddress0_reg, _T_116) @[dbg.scala 158:54] + node _T_118 = tail(_T_117, 1) @[dbg.scala 158:54] + node _T_119 = and(_T_115, _T_118) @[dbg.scala 158:36] + node sbaddress0_reg_din = or(_T_113, _T_119) @[dbg.scala 157:78] + node _T_120 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 159:58] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 352:23] rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= _T_127 + rvclkhdr_4.reset <= _T_120 rvclkhdr_4.io.clk <= clock @[lib.scala 354:18] rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 355:17] rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_128 : UInt, rvclkhdr_4.io.l1clk with : (reset => (_T_127, UInt<1>("h00"))) @[lib.scala 358:16] - _T_128 <= sbaddress0_reg_din @[lib.scala 358:16] - sbaddress0_reg <= _T_128 @[dbg.scala 159:18] - node _T_129 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 163:43] - node _T_130 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 163:81] - node _T_131 = and(_T_129, _T_130) @[dbg.scala 163:62] - node _T_132 = bits(sbcs_reg, 20, 20) @[dbg.scala 163:104] - node sbreadonaddr_access = and(_T_131, _T_132) @[dbg.scala 163:94] - node _T_133 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 164:45] - node _T_134 = and(io.dmi_reg_en, _T_133) @[dbg.scala 164:43] - node _T_135 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 164:82] - node _T_136 = and(_T_134, _T_135) @[dbg.scala 164:63] - node _T_137 = bits(sbcs_reg, 15, 15) @[dbg.scala 164:105] - node sbreadondata_access = and(_T_136, _T_137) @[dbg.scala 164:95] - node _T_138 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 165:40] - node _T_139 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 165:78] - node sbdata0wr_access = and(_T_138, _T_139) @[dbg.scala 165:59] - node _T_140 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 166:41] - node _T_141 = and(_T_140, io.dmi_reg_en) @[dbg.scala 166:54] - node dmcontrol_wren = and(_T_141, io.dmi_reg_wr_en) @[dbg.scala 166:70] - node _T_142 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 167:50] - node _T_143 = asAsyncReset(_T_142) @[dbg.scala 167:77] - node _T_144 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 169:27] - node _T_145 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 169:53] - node _T_146 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 169:75] - node _T_147 = cat(_T_144, _T_145) @[Cat.scala 29:58] - node _T_148 = cat(_T_147, _T_146) @[Cat.scala 29:58] - reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (_T_143, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_121 : UInt, rvclkhdr_4.io.l1clk with : (reset => (_T_120, UInt<1>("h00"))) @[lib.scala 358:16] + _T_121 <= sbaddress0_reg_din @[lib.scala 358:16] + sbaddress0_reg <= _T_121 @[dbg.scala 159:18] + node _T_122 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 163:43] + node _T_123 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 163:81] + node _T_124 = and(_T_122, _T_123) @[dbg.scala 163:62] + node _T_125 = bits(sbcs_reg, 20, 20) @[dbg.scala 163:104] + node sbreadonaddr_access = and(_T_124, _T_125) @[dbg.scala 163:94] + node _T_126 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 164:45] + node _T_127 = and(io.dmi_reg_en, _T_126) @[dbg.scala 164:43] + node _T_128 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 164:82] + node _T_129 = and(_T_127, _T_128) @[dbg.scala 164:63] + node _T_130 = bits(sbcs_reg, 15, 15) @[dbg.scala 164:105] + node sbreadondata_access = and(_T_129, _T_130) @[dbg.scala 164:95] + node _T_131 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 165:40] + node _T_132 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 165:78] + node sbdata0wr_access = and(_T_131, _T_132) @[dbg.scala 165:59] + node _T_133 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 166:41] + node _T_134 = and(_T_133, io.dmi_reg_en) @[dbg.scala 166:54] + node dmcontrol_wren = and(_T_134, io.dmi_reg_wr_en) @[dbg.scala 166:70] + node _T_135 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 167:76] + node _T_136 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 169:27] + node _T_137 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 169:53] + node _T_138 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 169:75] + node _T_139 = cat(_T_136, _T_137) @[Cat.scala 29:58] + node _T_140 = cat(_T_139, _T_138) @[Cat.scala 29:58] + reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (_T_135, UInt<1>("h00"))) @[Reg.scala 27:20] when dmcontrol_wren : @[Reg.scala 28:19] - dm_temp <= _T_148 @[Reg.scala 28:23] + dm_temp <= _T_140 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_149 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 173:76] - node _T_150 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 174:31] - reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_149, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_141 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 173:76] + node _T_142 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 174:31] + reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_141, UInt<1>("h00"))) @[Reg.scala 27:20] when dmcontrol_wren : @[Reg.scala 28:19] - dm_temp_0 <= _T_150 @[Reg.scala 28:23] + dm_temp_0 <= _T_142 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_151 = bits(dm_temp, 3, 2) @[dbg.scala 177:25] - node _T_152 = bits(dm_temp, 1, 1) @[dbg.scala 177:45] - node _T_153 = bits(dm_temp, 0, 0) @[dbg.scala 177:68] - node _T_154 = cat(UInt<26>("h00"), _T_153) @[Cat.scala 29:58] - node _T_155 = cat(_T_154, dm_temp_0) @[Cat.scala 29:58] - node _T_156 = cat(_T_151, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_157 = cat(_T_156, _T_152) @[Cat.scala 29:58] - node temp = cat(_T_157, _T_155) @[Cat.scala 29:58] + node _T_143 = bits(dm_temp, 3, 2) @[dbg.scala 177:25] + node _T_144 = bits(dm_temp, 1, 1) @[dbg.scala 177:45] + node _T_145 = bits(dm_temp, 0, 0) @[dbg.scala 177:68] + node _T_146 = cat(UInt<26>("h00"), _T_145) @[Cat.scala 29:58] + node _T_147 = cat(_T_146, dm_temp_0) @[Cat.scala 29:58] + node _T_148 = cat(_T_143, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_149 = cat(_T_148, _T_144) @[Cat.scala 29:58] + node temp = cat(_T_149, _T_147) @[Cat.scala 29:58] dmcontrol_reg <= temp @[dbg.scala 178:17] - node _T_158 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 180:59] - node _T_159 = asAsyncReset(_T_158) @[dbg.scala 180:86] - reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_159, UInt<1>("h00"))) @[dbg.scala 181:12] + node _T_150 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 180:85] + reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_150, UInt<1>("h00"))) @[dbg.scala 181:12] dmcontrol_wren_Q <= dmcontrol_wren @[dbg.scala 181:12] - node _T_160 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15] - node _T_161 = mux(_T_160, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_162 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15] - node _T_163 = mux(_T_162, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_164 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15] - node _T_165 = mux(_T_164, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_166 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15] - node _T_167 = mux(_T_166, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_168 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15] - node _T_169 = mux(_T_168, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_170 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58] - node _T_171 = cat(_T_167, _T_169) @[Cat.scala 29:58] - node _T_172 = cat(_T_171, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_173 = cat(_T_172, _T_170) @[Cat.scala 29:58] - node _T_174 = cat(UInt<2>("h00"), _T_165) @[Cat.scala 29:58] - node _T_175 = cat(UInt<12>("h00"), _T_161) @[Cat.scala 29:58] - node _T_176 = cat(_T_175, _T_163) @[Cat.scala 29:58] - node _T_177 = cat(_T_176, _T_174) @[Cat.scala 29:58] - node _T_178 = cat(_T_177, _T_173) @[Cat.scala 29:58] - dmstatus_reg <= _T_178 @[dbg.scala 184:16] - node _T_179 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 186:44] - node _T_180 = and(_T_179, io.dec_tlu_resume_ack) @[dbg.scala 186:66] - node _T_181 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 186:127] - node _T_182 = eq(_T_181, UInt<1>("h00")) @[dbg.scala 186:113] - node _T_183 = and(dmstatus_resumeack, _T_182) @[dbg.scala 186:111] - node dmstatus_resumeack_wren = or(_T_180, _T_183) @[dbg.scala 186:90] - node _T_184 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 187:43] - node dmstatus_resumeack_din = and(_T_184, io.dec_tlu_resume_ack) @[dbg.scala 187:65] - node _T_185 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 188:50] - node _T_186 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 188:81] - node _T_187 = and(_T_185, _T_186) @[dbg.scala 188:63] - node _T_188 = and(_T_187, io.dmi_reg_en) @[dbg.scala 188:85] - node dmstatus_havereset_wren = and(_T_188, io.dmi_reg_wr_en) @[dbg.scala 188:101] - node _T_189 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 189:49] - node _T_190 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 189:80] - node _T_191 = and(_T_189, _T_190) @[dbg.scala 189:62] - node _T_192 = and(_T_191, io.dmi_reg_en) @[dbg.scala 189:85] - node dmstatus_havereset_rst = and(_T_192, io.dmi_reg_wr_en) @[dbg.scala 189:101] + node _T_151 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15] + node _T_152 = mux(_T_151, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_153 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15] + node _T_154 = mux(_T_153, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_155 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15] + node _T_156 = mux(_T_155, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_157 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15] + node _T_158 = mux(_T_157, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_159 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15] + node _T_160 = mux(_T_159, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_161 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58] + node _T_162 = cat(_T_158, _T_160) @[Cat.scala 29:58] + node _T_163 = cat(_T_162, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_164 = cat(_T_163, _T_161) @[Cat.scala 29:58] + node _T_165 = cat(UInt<2>("h00"), _T_156) @[Cat.scala 29:58] + node _T_166 = cat(UInt<12>("h00"), _T_152) @[Cat.scala 29:58] + node _T_167 = cat(_T_166, _T_154) @[Cat.scala 29:58] + node _T_168 = cat(_T_167, _T_165) @[Cat.scala 29:58] + node _T_169 = cat(_T_168, _T_164) @[Cat.scala 29:58] + dmstatus_reg <= _T_169 @[dbg.scala 184:16] + node _T_170 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 186:44] + node _T_171 = and(_T_170, io.dec_tlu_resume_ack) @[dbg.scala 186:66] + node _T_172 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 186:127] + node _T_173 = eq(_T_172, UInt<1>("h00")) @[dbg.scala 186:113] + node _T_174 = and(dmstatus_resumeack, _T_173) @[dbg.scala 186:111] + node dmstatus_resumeack_wren = or(_T_171, _T_174) @[dbg.scala 186:90] + node _T_175 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 187:43] + node dmstatus_resumeack_din = and(_T_175, io.dec_tlu_resume_ack) @[dbg.scala 187:65] + node _T_176 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 188:50] + node _T_177 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 188:81] + node _T_178 = and(_T_176, _T_177) @[dbg.scala 188:63] + node _T_179 = and(_T_178, io.dmi_reg_en) @[dbg.scala 188:85] + node dmstatus_havereset_wren = and(_T_179, io.dmi_reg_wr_en) @[dbg.scala 188:101] + node _T_180 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 189:49] + node _T_181 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 189:80] + node _T_182 = and(_T_180, _T_181) @[dbg.scala 189:62] + node _T_183 = and(_T_182, io.dmi_reg_en) @[dbg.scala 189:85] + node dmstatus_havereset_rst = and(_T_183, io.dmi_reg_wr_en) @[dbg.scala 189:101] node temp_rst = asUInt(reset) @[dbg.scala 190:30] - node _T_193 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 191:37] - node _T_194 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 191:43] - node _T_195 = or(_T_193, _T_194) @[dbg.scala 191:41] - node _T_196 = bits(_T_195, 0, 0) @[dbg.scala 191:62] - dmstatus_unavail <= _T_196 @[dbg.scala 191:20] - node _T_197 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 192:42] - node _T_198 = not(_T_197) @[dbg.scala 192:23] - dmstatus_running <= _T_198 @[dbg.scala 192:20] - node _T_199 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 193:58] - node _T_200 = asAsyncReset(_T_199) @[dbg.scala 193:85] - reg _T_201 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_200, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_184 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 191:37] + node _T_185 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 191:43] + node _T_186 = or(_T_184, _T_185) @[dbg.scala 191:41] + node _T_187 = bits(_T_186, 0, 0) @[dbg.scala 191:62] + dmstatus_unavail <= _T_187 @[dbg.scala 191:20] + node _T_188 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 192:42] + node _T_189 = not(_T_188) @[dbg.scala 192:23] + dmstatus_running <= _T_189 @[dbg.scala 192:20] + node _T_190 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 193:84] + reg _T_191 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_190, UInt<1>("h00"))) @[Reg.scala 27:20] when dmstatus_resumeack_wren : @[Reg.scala 28:19] - _T_201 <= dmstatus_resumeack_din @[Reg.scala 28:23] + _T_191 <= dmstatus_resumeack_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - dmstatus_resumeack <= _T_201 @[dbg.scala 193:22] - node _T_202 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 197:55] - node _T_203 = asAsyncReset(_T_202) @[dbg.scala 197:82] - node _T_204 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 198:37] - node _T_205 = and(io.dec_tlu_dbg_halted, _T_204) @[dbg.scala 198:35] - reg _T_206 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_203, UInt<1>("h00"))) @[dbg.scala 198:12] - _T_206 <= _T_205 @[dbg.scala 198:12] - dmstatus_halted <= _T_206 @[dbg.scala 197:19] - node _T_207 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 201:58] - node _T_208 = asAsyncReset(_T_207) @[dbg.scala 201:85] - node _T_209 = not(dmstatus_havereset_rst) @[dbg.scala 202:15] - reg _T_210 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_208, UInt<1>("h00"))) @[Reg.scala 27:20] - when dmstatus_havereset_wren : @[Reg.scala 28:19] - _T_210 <= _T_209 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - dmstatus_havereset <= _T_210 @[dbg.scala 201:22] + dmstatus_resumeack <= _T_191 @[dbg.scala 193:22] + node _T_192 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 197:81] + node _T_193 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 198:37] + node _T_194 = and(io.dec_tlu_dbg_halted, _T_193) @[dbg.scala 198:35] + reg _T_195 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_192, UInt<1>("h00"))) @[dbg.scala 198:12] + _T_195 <= _T_194 @[dbg.scala 198:12] + dmstatus_halted <= _T_195 @[dbg.scala 197:19] + node _T_196 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 201:84] + node _T_197 = mux(dmstatus_havereset_wren, UInt<1>("h01"), dmstatus_havereset) @[dbg.scala 202:16] + node _T_198 = eq(dmstatus_havereset_rst, UInt<1>("h00")) @[dbg.scala 202:72] + node _T_199 = and(_T_197, _T_198) @[dbg.scala 202:70] + reg _T_200 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_196, UInt<1>("h00"))) @[dbg.scala 202:12] + _T_200 <= _T_199 @[dbg.scala 202:12] + dmstatus_havereset <= _T_200 @[dbg.scala 201:22] node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58] wire abstractcs_reg : UInt<32> abstractcs_reg <= UInt<32>("h02") - node _T_211 = bits(abstractcs_reg, 12, 12) @[dbg.scala 208:45] - node _T_212 = and(_T_211, io.dmi_reg_en) @[dbg.scala 208:50] - node _T_213 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 208:106] - node _T_214 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 208:138] - node _T_215 = or(_T_213, _T_214) @[dbg.scala 208:119] - node _T_216 = and(io.dmi_reg_wr_en, _T_215) @[dbg.scala 208:86] - node _T_217 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 208:171] - node _T_218 = or(_T_216, _T_217) @[dbg.scala 208:152] - node abstractcs_error_sel0 = and(_T_212, _T_218) @[dbg.scala 208:66] - node _T_219 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 209:45] - node _T_220 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 209:83] - node _T_221 = and(_T_219, _T_220) @[dbg.scala 209:64] - node _T_222 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:117] - node _T_223 = eq(_T_222, UInt<1>("h00")) @[dbg.scala 209:126] - node _T_224 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:154] - node _T_225 = eq(_T_224, UInt<2>("h02")) @[dbg.scala 209:163] - node _T_226 = or(_T_223, _T_225) @[dbg.scala 209:135] - node _T_227 = eq(_T_226, UInt<1>("h00")) @[dbg.scala 209:98] - node abstractcs_error_sel1 = and(_T_221, _T_227) @[dbg.scala 209:96] + node _T_201 = bits(abstractcs_reg, 12, 12) @[dbg.scala 208:45] + node _T_202 = and(_T_201, io.dmi_reg_en) @[dbg.scala 208:50] + node _T_203 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 208:106] + node _T_204 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 208:138] + node _T_205 = or(_T_203, _T_204) @[dbg.scala 208:119] + node _T_206 = and(io.dmi_reg_wr_en, _T_205) @[dbg.scala 208:86] + node _T_207 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 208:171] + node _T_208 = or(_T_206, _T_207) @[dbg.scala 208:152] + node abstractcs_error_sel0 = and(_T_202, _T_208) @[dbg.scala 208:66] + node _T_209 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 209:45] + node _T_210 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 209:83] + node _T_211 = and(_T_209, _T_210) @[dbg.scala 209:64] + node _T_212 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:117] + node _T_213 = eq(_T_212, UInt<1>("h00")) @[dbg.scala 209:126] + node _T_214 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:154] + node _T_215 = eq(_T_214, UInt<2>("h02")) @[dbg.scala 209:163] + node _T_216 = or(_T_213, _T_215) @[dbg.scala 209:135] + node _T_217 = eq(_T_216, UInt<1>("h00")) @[dbg.scala 209:98] + node abstractcs_error_sel1 = and(_T_211, _T_217) @[dbg.scala 209:96] node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 210:52] - node _T_228 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 211:45] - node _T_229 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 211:83] - node _T_230 = and(_T_228, _T_229) @[dbg.scala 211:64] - node _T_231 = bits(dmstatus_reg, 9, 9) @[dbg.scala 211:111] - node _T_232 = eq(_T_231, UInt<1>("h00")) @[dbg.scala 211:98] - node abstractcs_error_sel3 = and(_T_230, _T_232) @[dbg.scala 211:96] - node _T_233 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 212:48] - node _T_234 = and(_T_233, io.dmi_reg_en) @[dbg.scala 212:61] - node _T_235 = and(_T_234, io.dmi_reg_wr_en) @[dbg.scala 212:77] - node _T_236 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 213:23] - node _T_237 = neq(_T_236, UInt<2>("h02")) @[dbg.scala 213:32] - node _T_238 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 213:66] - node _T_239 = eq(_T_238, UInt<2>("h02")) @[dbg.scala 213:75] - node _T_240 = bits(data1_reg, 1, 0) @[dbg.scala 213:99] - node _T_241 = orr(_T_240) @[dbg.scala 213:106] - node _T_242 = and(_T_239, _T_241) @[dbg.scala 213:87] - node _T_243 = or(_T_237, _T_242) @[dbg.scala 213:46] - node abstractcs_error_sel4 = and(_T_235, _T_243) @[dbg.scala 212:96] - node _T_244 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 215:48] - node _T_245 = and(_T_244, io.dmi_reg_en) @[dbg.scala 215:61] - node abstractcs_error_sel5 = and(_T_245, io.dmi_reg_wr_en) @[dbg.scala 215:77] - node _T_246 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 216:54] - node _T_247 = or(_T_246, abstractcs_error_sel2) @[dbg.scala 216:78] - node _T_248 = or(_T_247, abstractcs_error_sel3) @[dbg.scala 216:102] - node _T_249 = or(_T_248, abstractcs_error_sel4) @[dbg.scala 216:126] - node abstractcs_error_selor = or(_T_249, abstractcs_error_sel5) @[dbg.scala 216:150] - node _T_250 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15] - node _T_251 = mux(_T_250, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_252 = and(_T_251, UInt<1>("h01")) @[dbg.scala 217:62] - node _T_253 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15] - node _T_254 = mux(_T_253, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_255 = and(_T_254, UInt<2>("h02")) @[dbg.scala 218:37] - node _T_256 = or(_T_252, _T_255) @[dbg.scala 217:74] - node _T_257 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15] - node _T_258 = mux(_T_257, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_259 = and(_T_258, UInt<2>("h03")) @[dbg.scala 219:37] - node _T_260 = or(_T_256, _T_259) @[dbg.scala 218:49] - node _T_261 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15] - node _T_262 = mux(_T_261, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_263 = and(_T_262, UInt<3>("h04")) @[dbg.scala 220:37] - node _T_264 = or(_T_260, _T_263) @[dbg.scala 219:49] - node _T_265 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15] - node _T_266 = mux(_T_265, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_267 = and(_T_266, UInt<3>("h07")) @[dbg.scala 221:37] - node _T_268 = or(_T_264, _T_267) @[dbg.scala 220:49] - node _T_269 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15] - node _T_270 = mux(_T_269, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_271 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 222:57] - node _T_272 = not(_T_271) @[dbg.scala 222:40] - node _T_273 = and(_T_270, _T_272) @[dbg.scala 222:37] - node _T_274 = bits(abstractcs_reg, 10, 8) @[dbg.scala 222:91] - node _T_275 = and(_T_273, _T_274) @[dbg.scala 222:75] - node _T_276 = or(_T_268, _T_275) @[dbg.scala 221:49] - node _T_277 = not(abstractcs_error_selor) @[dbg.scala 223:15] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_280 = bits(abstractcs_reg, 10, 8) @[dbg.scala 223:66] - node _T_281 = and(_T_279, _T_280) @[dbg.scala 223:50] - node abstractcs_error_din = or(_T_276, _T_281) @[dbg.scala 222:100] - node _T_282 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 225:54] - node _T_283 = asAsyncReset(_T_282) @[dbg.scala 225:81] - reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_283, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_218 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 211:45] + node _T_219 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 211:83] + node _T_220 = and(_T_218, _T_219) @[dbg.scala 211:64] + node _T_221 = bits(dmstatus_reg, 9, 9) @[dbg.scala 211:111] + node _T_222 = eq(_T_221, UInt<1>("h00")) @[dbg.scala 211:98] + node abstractcs_error_sel3 = and(_T_220, _T_222) @[dbg.scala 211:96] + node _T_223 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 212:48] + node _T_224 = and(_T_223, io.dmi_reg_en) @[dbg.scala 212:61] + node _T_225 = and(_T_224, io.dmi_reg_wr_en) @[dbg.scala 212:77] + node _T_226 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 213:23] + node _T_227 = neq(_T_226, UInt<3>("h02")) @[dbg.scala 213:32] + node _T_228 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 213:71] + node _T_229 = eq(_T_228, UInt<2>("h02")) @[dbg.scala 213:80] + node _T_230 = bits(data1_reg, 1, 0) @[dbg.scala 213:104] + node _T_231 = orr(_T_230) @[dbg.scala 213:111] + node _T_232 = and(_T_229, _T_231) @[dbg.scala 213:92] + node _T_233 = or(_T_227, _T_232) @[dbg.scala 213:51] + node abstractcs_error_sel4 = and(_T_225, _T_233) @[dbg.scala 212:96] + node _T_234 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 215:48] + node _T_235 = and(_T_234, io.dmi_reg_en) @[dbg.scala 215:61] + node abstractcs_error_sel5 = and(_T_235, io.dmi_reg_wr_en) @[dbg.scala 215:77] + node _T_236 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 216:54] + node _T_237 = or(_T_236, abstractcs_error_sel2) @[dbg.scala 216:78] + node _T_238 = or(_T_237, abstractcs_error_sel3) @[dbg.scala 216:102] + node _T_239 = or(_T_238, abstractcs_error_sel4) @[dbg.scala 216:126] + node abstractcs_error_selor = or(_T_239, abstractcs_error_sel5) @[dbg.scala 216:150] + node _T_240 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15] + node _T_241 = mux(_T_240, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_242 = and(_T_241, UInt<3>("h01")) @[dbg.scala 217:62] + node _T_243 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15] + node _T_244 = mux(_T_243, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_245 = and(_T_244, UInt<3>("h02")) @[dbg.scala 218:37] + node _T_246 = or(_T_242, _T_245) @[dbg.scala 217:79] + node _T_247 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15] + node _T_248 = mux(_T_247, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_249 = and(_T_248, UInt<3>("h03")) @[dbg.scala 219:37] + node _T_250 = or(_T_246, _T_249) @[dbg.scala 218:54] + node _T_251 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15] + node _T_252 = mux(_T_251, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_253 = and(_T_252, UInt<3>("h04")) @[dbg.scala 220:37] + node _T_254 = or(_T_250, _T_253) @[dbg.scala 219:54] + node _T_255 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15] + node _T_256 = mux(_T_255, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_257 = and(_T_256, UInt<3>("h07")) @[dbg.scala 221:37] + node _T_258 = or(_T_254, _T_257) @[dbg.scala 220:54] + node _T_259 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15] + node _T_260 = mux(_T_259, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_261 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 222:57] + node _T_262 = not(_T_261) @[dbg.scala 222:40] + node _T_263 = and(_T_260, _T_262) @[dbg.scala 222:37] + node _T_264 = bits(abstractcs_reg, 10, 8) @[dbg.scala 222:91] + node _T_265 = and(_T_263, _T_264) @[dbg.scala 222:75] + node _T_266 = or(_T_258, _T_265) @[dbg.scala 221:54] + node _T_267 = not(abstractcs_error_selor) @[dbg.scala 223:15] + node _T_268 = bits(_T_267, 0, 0) @[Bitwise.scala 72:15] + node _T_269 = mux(_T_268, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_270 = bits(abstractcs_reg, 10, 8) @[dbg.scala 223:66] + node _T_271 = and(_T_269, _T_270) @[dbg.scala 223:50] + node abstractcs_error_din = or(_T_266, _T_271) @[dbg.scala 222:100] + node _T_272 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 225:80] + reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_272, UInt<1>("h00"))) @[Reg.scala 27:20] when abstractcs_busy_wren : @[Reg.scala 28:19] abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_284 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 229:56] - node _T_285 = asAsyncReset(_T_284) @[dbg.scala 229:83] - node _T_286 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 230:33] - reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_285, UInt<1>("h00"))) @[dbg.scala 230:12] - abs_temp_10_8 <= _T_286 @[dbg.scala 230:12] - node _T_287 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58] - node _T_288 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58] - node _T_289 = cat(_T_288, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_290 = cat(_T_289, _T_287) @[Cat.scala 29:58] - abstractcs_reg <= _T_290 @[dbg.scala 233:18] - node _T_291 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 235:39] - node _T_292 = and(_T_291, io.dmi_reg_en) @[dbg.scala 235:52] - node _T_293 = and(_T_292, io.dmi_reg_wr_en) @[dbg.scala 235:68] - node _T_294 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 235:100] - node command_wren = and(_T_293, _T_294) @[dbg.scala 235:87] - node _T_295 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 236:41] - node _T_296 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 236:77] - node _T_297 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 236:113] - node _T_298 = cat(UInt<3>("h00"), _T_297) @[Cat.scala 29:58] - node _T_299 = cat(_T_295, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_300 = cat(_T_299, _T_296) @[Cat.scala 29:58] - node command_din = cat(_T_300, _T_298) @[Cat.scala 29:58] - node _T_301 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 237:32] - node _T_302 = asAsyncReset(_T_301) @[dbg.scala 237:59] + node _T_273 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 229:82] + node _T_274 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 230:33] + reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_273, UInt<1>("h00"))) @[dbg.scala 230:12] + abs_temp_10_8 <= _T_274 @[dbg.scala 230:12] + node _T_275 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58] + node _T_276 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58] + node _T_277 = cat(_T_276, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_278 = cat(_T_277, _T_275) @[Cat.scala 29:58] + abstractcs_reg <= _T_278 @[dbg.scala 233:18] + node _T_279 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 235:39] + node _T_280 = and(_T_279, io.dmi_reg_en) @[dbg.scala 235:52] + node _T_281 = and(_T_280, io.dmi_reg_wr_en) @[dbg.scala 235:68] + node _T_282 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 235:100] + node command_wren = and(_T_281, _T_282) @[dbg.scala 235:87] + node _T_283 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 236:41] + node _T_284 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 236:77] + node _T_285 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 236:113] + node _T_286 = cat(UInt<3>("h00"), _T_285) @[Cat.scala 29:58] + node _T_287 = cat(_T_283, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_288 = cat(_T_287, _T_284) @[Cat.scala 29:58] + node command_din = cat(_T_288, _T_286) @[Cat.scala 29:58] + node _T_289 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 237:58] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 352:23] rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= _T_302 + rvclkhdr_5.reset <= _T_289 rvclkhdr_5.io.clk <= clock @[lib.scala 354:18] rvclkhdr_5.io.en <= command_wren @[lib.scala 355:17] rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_302, UInt<1>("h00"))) @[lib.scala 358:16] + reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_289, UInt<1>("h00"))) @[lib.scala 358:16] command_reg <= command_din @[lib.scala 358:16] - node _T_303 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39] - node _T_304 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77] - node _T_305 = and(_T_303, _T_304) @[dbg.scala 241:58] - node _T_306 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 241:102] - node data0_reg_wren0 = and(_T_305, _T_306) @[dbg.scala 241:89] - node _T_307 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 242:59] - node _T_308 = and(io.core_dbg_cmd_done, _T_307) @[dbg.scala 242:46] - node _T_309 = bits(command_reg, 16, 16) @[dbg.scala 242:95] - node _T_310 = eq(_T_309, UInt<1>("h00")) @[dbg.scala 242:83] - node data0_reg_wren1 = and(_T_308, _T_310) @[dbg.scala 242:81] + node _T_290 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39] + node _T_291 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77] + node _T_292 = and(_T_290, _T_291) @[dbg.scala 241:58] + node _T_293 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 241:102] + node data0_reg_wren0 = and(_T_292, _T_293) @[dbg.scala 241:89] + node _T_294 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 242:59] + node _T_295 = and(io.core_dbg_cmd_done, _T_294) @[dbg.scala 242:46] + node _T_296 = bits(command_reg, 16, 16) @[dbg.scala 242:95] + node _T_297 = eq(_T_296, UInt<1>("h00")) @[dbg.scala 242:83] + node data0_reg_wren1 = and(_T_295, _T_297) @[dbg.scala 242:81] node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 244:40] - node _T_311 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_312 = mux(_T_311, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_313 = and(_T_312, io.dmi_reg_wdata) @[dbg.scala 245:45] - node _T_314 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] - node _T_315 = mux(_T_314, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_316 = and(_T_315, io.core_dbg_rddata) @[dbg.scala 245:92] - node data0_din = or(_T_313, _T_316) @[dbg.scala 245:64] - node _T_317 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 246:30] - node _T_318 = asAsyncReset(_T_317) @[dbg.scala 246:57] + node _T_298 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_300 = and(_T_299, io.dmi_reg_wdata) @[dbg.scala 245:45] + node _T_301 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_302 = mux(_T_301, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_303 = and(_T_302, io.core_dbg_rddata) @[dbg.scala 245:92] + node data0_din = or(_T_300, _T_303) @[dbg.scala 245:64] + node _T_304 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 246:56] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 352:23] rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= _T_318 + rvclkhdr_6.reset <= _T_304 rvclkhdr_6.io.clk <= clock @[lib.scala 354:18] rvclkhdr_6.io.en <= data0_reg_wren @[lib.scala 355:17] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (_T_318, UInt<1>("h00"))) @[lib.scala 358:16] + reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (_T_304, UInt<1>("h00"))) @[lib.scala 358:16] data0_reg <= data0_din @[lib.scala 358:16] - node _T_319 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39] - node _T_320 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77] - node _T_321 = and(_T_319, _T_320) @[dbg.scala 250:58] - node _T_322 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 250:102] - node data1_reg_wren = and(_T_321, _T_322) @[dbg.scala 250:89] - node _T_323 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15] - node _T_324 = mux(_T_323, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node data1_din = and(_T_324, io.dmi_reg_wdata) @[dbg.scala 251:44] - node _T_325 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 252:27] - node _T_326 = asAsyncReset(_T_325) @[dbg.scala 252:54] + node _T_305 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39] + node _T_306 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77] + node _T_307 = and(_T_305, _T_306) @[dbg.scala 250:58] + node _T_308 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 250:102] + node data1_reg_wren = and(_T_307, _T_308) @[dbg.scala 250:89] + node _T_309 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15] + node _T_310 = mux(_T_309, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node data1_din = and(_T_310, io.dmi_reg_wdata) @[dbg.scala 251:44] + node _T_311 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 252:53] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 352:23] rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= _T_326 + rvclkhdr_7.reset <= _T_311 rvclkhdr_7.io.clk <= clock @[lib.scala 354:18] rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 355:17] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_327 : UInt, rvclkhdr_7.io.l1clk with : (reset => (_T_326, UInt<1>("h00"))) @[lib.scala 358:16] - _T_327 <= data1_din @[lib.scala 358:16] - data1_reg <= _T_327 @[dbg.scala 252:13] + reg _T_312 : UInt, rvclkhdr_7.io.l1clk with : (reset => (_T_311, UInt<1>("h00"))) @[lib.scala 358:16] + _T_312 <= data1_din @[lib.scala 358:16] + data1_reg <= _T_312 @[dbg.scala 252:13] wire dbg_nxtstate : UInt<3> dbg_nxtstate <= UInt<3>("h00") dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 257:16] @@ -751,275 +734,273 @@ circuit dbg : abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 260:23] io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 261:19] io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 262:21] - node _T_328 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30] - when _T_328 : @[Conditional.scala 40:58] - node _T_329 = bits(dmstatus_reg, 9, 9) @[dbg.scala 265:39] - node _T_330 = or(_T_329, io.dec_tlu_mpc_halted_only) @[dbg.scala 265:43] - node _T_331 = mux(_T_330, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 265:26] - dbg_nxtstate <= _T_331 @[dbg.scala 265:20] - node _T_332 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 266:38] - node _T_333 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 266:45] - node _T_334 = and(_T_332, _T_333) @[dbg.scala 266:43] - node _T_335 = bits(dmstatus_reg, 9, 9) @[dbg.scala 266:83] - node _T_336 = or(_T_334, _T_335) @[dbg.scala 266:69] - node _T_337 = or(_T_336, io.dec_tlu_mpc_halted_only) @[dbg.scala 266:87] - node _T_338 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 266:133] - node _T_339 = eq(_T_338, UInt<1>("h00")) @[dbg.scala 266:119] - node _T_340 = and(_T_337, _T_339) @[dbg.scala 266:117] - dbg_state_en <= _T_340 @[dbg.scala 266:20] - node _T_341 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 267:40] - node _T_342 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 267:61] - node _T_343 = eq(_T_342, UInt<1>("h00")) @[dbg.scala 267:47] - node _T_344 = and(_T_341, _T_343) @[dbg.scala 267:45] - node _T_345 = bits(_T_344, 0, 0) @[dbg.scala 267:72] - io.dbg_halt_req <= _T_345 @[dbg.scala 267:23] + node _T_313 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30] + when _T_313 : @[Conditional.scala 40:58] + node _T_314 = bits(dmstatus_reg, 9, 9) @[dbg.scala 265:39] + node _T_315 = or(_T_314, io.dec_tlu_mpc_halted_only) @[dbg.scala 265:43] + node _T_316 = mux(_T_315, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 265:26] + dbg_nxtstate <= _T_316 @[dbg.scala 265:20] + node _T_317 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 266:38] + node _T_318 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 266:45] + node _T_319 = and(_T_317, _T_318) @[dbg.scala 266:43] + node _T_320 = bits(dmstatus_reg, 9, 9) @[dbg.scala 266:83] + node _T_321 = or(_T_319, _T_320) @[dbg.scala 266:69] + node _T_322 = or(_T_321, io.dec_tlu_mpc_halted_only) @[dbg.scala 266:87] + node _T_323 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 266:133] + node _T_324 = eq(_T_323, UInt<1>("h00")) @[dbg.scala 266:119] + node _T_325 = and(_T_322, _T_324) @[dbg.scala 266:117] + dbg_state_en <= _T_325 @[dbg.scala 266:20] + node _T_326 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 267:40] + node _T_327 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 267:61] + node _T_328 = eq(_T_327, UInt<1>("h00")) @[dbg.scala 267:47] + node _T_329 = and(_T_326, _T_328) @[dbg.scala 267:45] + node _T_330 = bits(_T_329, 0, 0) @[dbg.scala 267:72] + io.dbg_halt_req <= _T_330 @[dbg.scala 267:23] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_346 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30] - when _T_346 : @[Conditional.scala 39:67] - node _T_347 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 270:40] - node _T_348 = mux(_T_347, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 270:26] - dbg_nxtstate <= _T_348 @[dbg.scala 270:20] - node _T_349 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:35] - node _T_350 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:54] - node _T_351 = or(_T_349, _T_350) @[dbg.scala 271:39] - dbg_state_en <= _T_351 @[dbg.scala 271:20] - node _T_352 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:59] - node _T_353 = and(dmcontrol_wren_Q, _T_352) @[dbg.scala 272:44] - node _T_354 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:81] - node _T_355 = not(_T_354) @[dbg.scala 272:67] - node _T_356 = and(_T_353, _T_355) @[dbg.scala 272:64] - node _T_357 = bits(_T_356, 0, 0) @[dbg.scala 272:102] - io.dbg_halt_req <= _T_357 @[dbg.scala 272:23] + node _T_331 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30] + when _T_331 : @[Conditional.scala 39:67] + node _T_332 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 270:40] + node _T_333 = mux(_T_332, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 270:26] + dbg_nxtstate <= _T_333 @[dbg.scala 270:20] + node _T_334 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:35] + node _T_335 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:54] + node _T_336 = or(_T_334, _T_335) @[dbg.scala 271:39] + dbg_state_en <= _T_336 @[dbg.scala 271:20] + node _T_337 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:59] + node _T_338 = and(dmcontrol_wren_Q, _T_337) @[dbg.scala 272:44] + node _T_339 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:81] + node _T_340 = not(_T_339) @[dbg.scala 272:67] + node _T_341 = and(_T_338, _T_340) @[dbg.scala 272:64] + node _T_342 = bits(_T_341, 0, 0) @[dbg.scala 272:102] + io.dbg_halt_req <= _T_342 @[dbg.scala 272:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_358 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30] - when _T_358 : @[Conditional.scala 39:67] - node _T_359 = bits(dmstatus_reg, 9, 9) @[dbg.scala 275:39] - node _T_360 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:59] - node _T_361 = eq(_T_360, UInt<1>("h00")) @[dbg.scala 275:45] - node _T_362 = and(_T_359, _T_361) @[dbg.scala 275:43] - node _T_363 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 276:26] - node _T_364 = bits(dmcontrol_reg, 3, 3) @[dbg.scala 276:47] - node _T_365 = eq(_T_364, UInt<1>("h00")) @[dbg.scala 276:33] - node _T_366 = and(_T_363, _T_365) @[dbg.scala 276:31] - node _T_367 = mux(_T_366, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 276:12] - node _T_368 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:26] - node _T_369 = mux(_T_368, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 277:12] - node _T_370 = mux(_T_362, _T_367, _T_369) @[dbg.scala 275:26] - dbg_nxtstate <= _T_370 @[dbg.scala 275:20] - node _T_371 = bits(dmstatus_reg, 9, 9) @[dbg.scala 278:35] - node _T_372 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 278:54] - node _T_373 = and(_T_371, _T_372) @[dbg.scala 278:39] - node _T_374 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 278:75] - node _T_375 = eq(_T_374, UInt<1>("h00")) @[dbg.scala 278:61] - node _T_376 = and(_T_373, _T_375) @[dbg.scala 278:59] - node _T_377 = and(_T_376, dmcontrol_wren_Q) @[dbg.scala 278:80] - node _T_378 = or(_T_377, command_wren) @[dbg.scala 278:99] - node _T_379 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 279:22] - node _T_380 = or(_T_378, _T_379) @[dbg.scala 278:114] - node _T_381 = bits(dmstatus_reg, 9, 9) @[dbg.scala 279:42] - node _T_382 = or(_T_381, io.dec_tlu_mpc_halted_only) @[dbg.scala 279:46] - node _T_383 = eq(_T_382, UInt<1>("h00")) @[dbg.scala 279:28] - node _T_384 = or(_T_380, _T_383) @[dbg.scala 279:26] - dbg_state_en <= _T_384 @[dbg.scala 278:20] - node _T_385 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 280:60] - node _T_386 = and(dbg_state_en, _T_385) @[dbg.scala 280:44] - abstractcs_busy_wren <= _T_386 @[dbg.scala 280:28] + node _T_343 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30] + when _T_343 : @[Conditional.scala 39:67] + node _T_344 = bits(dmstatus_reg, 9, 9) @[dbg.scala 275:39] + node _T_345 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:59] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dbg.scala 275:45] + node _T_347 = and(_T_344, _T_346) @[dbg.scala 275:43] + node _T_348 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 276:26] + node _T_349 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 276:47] + node _T_350 = eq(_T_349, UInt<1>("h00")) @[dbg.scala 276:33] + node _T_351 = and(_T_348, _T_350) @[dbg.scala 276:31] + node _T_352 = mux(_T_351, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 276:12] + node _T_353 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:26] + node _T_354 = mux(_T_353, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 277:12] + node _T_355 = mux(_T_347, _T_352, _T_354) @[dbg.scala 275:26] + dbg_nxtstate <= _T_355 @[dbg.scala 275:20] + node _T_356 = bits(dmstatus_reg, 9, 9) @[dbg.scala 278:35] + node _T_357 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 278:54] + node _T_358 = and(_T_356, _T_357) @[dbg.scala 278:39] + node _T_359 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 278:75] + node _T_360 = eq(_T_359, UInt<1>("h00")) @[dbg.scala 278:61] + node _T_361 = and(_T_358, _T_360) @[dbg.scala 278:59] + node _T_362 = and(_T_361, dmcontrol_wren_Q) @[dbg.scala 278:80] + node _T_363 = or(_T_362, command_wren) @[dbg.scala 278:99] + node _T_364 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 279:22] + node _T_365 = or(_T_363, _T_364) @[dbg.scala 278:114] + node _T_366 = bits(dmstatus_reg, 9, 9) @[dbg.scala 279:42] + node _T_367 = or(_T_366, io.dec_tlu_mpc_halted_only) @[dbg.scala 279:46] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dbg.scala 279:28] + node _T_369 = or(_T_365, _T_368) @[dbg.scala 279:26] + dbg_state_en <= _T_369 @[dbg.scala 278:20] + node _T_370 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 280:60] + node _T_371 = and(dbg_state_en, _T_370) @[dbg.scala 280:44] + abstractcs_busy_wren <= _T_371 @[dbg.scala 280:28] abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 281:27] - node _T_387 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 282:58] - node _T_388 = and(dbg_state_en, _T_387) @[dbg.scala 282:42] - node _T_389 = bits(_T_388, 0, 0) @[dbg.scala 282:87] - io.dbg_resume_req <= _T_389 @[dbg.scala 282:25] - node _T_390 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:59] - node _T_391 = and(dmcontrol_wren_Q, _T_390) @[dbg.scala 283:44] - node _T_392 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 283:81] - node _T_393 = not(_T_392) @[dbg.scala 283:67] - node _T_394 = and(_T_391, _T_393) @[dbg.scala 283:64] - node _T_395 = bits(_T_394, 0, 0) @[dbg.scala 283:102] - io.dbg_halt_req <= _T_395 @[dbg.scala 283:23] + node _T_372 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 282:58] + node _T_373 = and(dbg_state_en, _T_372) @[dbg.scala 282:42] + node _T_374 = bits(_T_373, 0, 0) @[dbg.scala 282:87] + io.dbg_resume_req <= _T_374 @[dbg.scala 282:25] + node _T_375 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:59] + node _T_376 = and(dmcontrol_wren_Q, _T_375) @[dbg.scala 283:44] + node _T_377 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 283:81] + node _T_378 = not(_T_377) @[dbg.scala 283:67] + node _T_379 = and(_T_376, _T_378) @[dbg.scala 283:64] + node _T_380 = bits(_T_379, 0, 0) @[dbg.scala 283:102] + io.dbg_halt_req <= _T_380 @[dbg.scala 283:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_396 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30] - when _T_396 : @[Conditional.scala 39:67] - node _T_397 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 286:40] - node _T_398 = bits(abstractcs_reg, 10, 8) @[dbg.scala 286:77] - node _T_399 = orr(_T_398) @[dbg.scala 286:85] - node _T_400 = mux(_T_399, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 286:62] - node _T_401 = mux(_T_397, UInt<3>("h00"), _T_400) @[dbg.scala 286:26] - dbg_nxtstate <= _T_401 @[dbg.scala 286:20] - node _T_402 = bits(abstractcs_reg, 10, 8) @[dbg.scala 287:71] - node _T_403 = orr(_T_402) @[dbg.scala 287:79] - node _T_404 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_403) @[dbg.scala 287:55] - node _T_405 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 287:98] - node _T_406 = or(_T_404, _T_405) @[dbg.scala 287:83] - dbg_state_en <= _T_406 @[dbg.scala 287:20] - node _T_407 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59] - node _T_408 = and(dmcontrol_wren_Q, _T_407) @[dbg.scala 288:44] - node _T_409 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81] - node _T_410 = not(_T_409) @[dbg.scala 288:67] - node _T_411 = and(_T_408, _T_410) @[dbg.scala 288:64] - node _T_412 = bits(_T_411, 0, 0) @[dbg.scala 288:102] - io.dbg_halt_req <= _T_412 @[dbg.scala 288:23] + node _T_381 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30] + when _T_381 : @[Conditional.scala 39:67] + node _T_382 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 286:40] + node _T_383 = bits(abstractcs_reg, 10, 8) @[dbg.scala 286:77] + node _T_384 = orr(_T_383) @[dbg.scala 286:85] + node _T_385 = mux(_T_384, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 286:62] + node _T_386 = mux(_T_382, UInt<3>("h00"), _T_385) @[dbg.scala 286:26] + dbg_nxtstate <= _T_386 @[dbg.scala 286:20] + node _T_387 = bits(abstractcs_reg, 10, 8) @[dbg.scala 287:71] + node _T_388 = orr(_T_387) @[dbg.scala 287:79] + node _T_389 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_388) @[dbg.scala 287:55] + node _T_390 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 287:98] + node _T_391 = or(_T_389, _T_390) @[dbg.scala 287:83] + dbg_state_en <= _T_391 @[dbg.scala 287:20] + node _T_392 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59] + node _T_393 = and(dmcontrol_wren_Q, _T_392) @[dbg.scala 288:44] + node _T_394 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81] + node _T_395 = not(_T_394) @[dbg.scala 288:67] + node _T_396 = and(_T_393, _T_395) @[dbg.scala 288:64] + node _T_397 = bits(_T_396, 0, 0) @[dbg.scala 288:102] + io.dbg_halt_req <= _T_397 @[dbg.scala 288:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_413 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30] - when _T_413 : @[Conditional.scala 39:67] - node _T_414 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40] - node _T_415 = mux(_T_414, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 291:26] - dbg_nxtstate <= _T_415 @[dbg.scala 291:20] - node _T_416 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:59] - node _T_417 = or(io.core_dbg_cmd_done, _T_416) @[dbg.scala 292:44] - dbg_state_en <= _T_417 @[dbg.scala 292:20] - node _T_418 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59] - node _T_419 = and(dmcontrol_wren_Q, _T_418) @[dbg.scala 293:44] - node _T_420 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81] - node _T_421 = not(_T_420) @[dbg.scala 293:67] - node _T_422 = and(_T_419, _T_421) @[dbg.scala 293:64] - node _T_423 = bits(_T_422, 0, 0) @[dbg.scala 293:102] - io.dbg_halt_req <= _T_423 @[dbg.scala 293:23] + node _T_398 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30] + when _T_398 : @[Conditional.scala 39:67] + node _T_399 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40] + node _T_400 = mux(_T_399, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 291:26] + dbg_nxtstate <= _T_400 @[dbg.scala 291:20] + node _T_401 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:59] + node _T_402 = or(io.core_dbg_cmd_done, _T_401) @[dbg.scala 292:44] + dbg_state_en <= _T_402 @[dbg.scala 292:20] + node _T_403 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59] + node _T_404 = and(dmcontrol_wren_Q, _T_403) @[dbg.scala 293:44] + node _T_405 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81] + node _T_406 = not(_T_405) @[dbg.scala 293:67] + node _T_407 = and(_T_404, _T_406) @[dbg.scala 293:64] + node _T_408 = bits(_T_407, 0, 0) @[dbg.scala 293:102] + io.dbg_halt_req <= _T_408 @[dbg.scala 293:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_424 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30] - when _T_424 : @[Conditional.scala 39:67] - node _T_425 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40] - node _T_426 = mux(_T_425, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 296:26] - dbg_nxtstate <= _T_426 @[dbg.scala 296:20] + node _T_409 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30] + when _T_409 : @[Conditional.scala 39:67] + node _T_410 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40] + node _T_411 = mux(_T_410, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 296:26] + dbg_nxtstate <= _T_411 @[dbg.scala 296:20] dbg_state_en <= UInt<1>("h01") @[dbg.scala 297:20] abstractcs_busy_wren <= dbg_state_en @[dbg.scala 298:28] abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 299:27] - node _T_427 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 300:59] - node _T_428 = and(dmcontrol_wren_Q, _T_427) @[dbg.scala 300:44] - node _T_429 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 300:81] - node _T_430 = not(_T_429) @[dbg.scala 300:67] - node _T_431 = and(_T_428, _T_430) @[dbg.scala 300:64] - node _T_432 = bits(_T_431, 0, 0) @[dbg.scala 300:102] - io.dbg_halt_req <= _T_432 @[dbg.scala 300:23] + node _T_412 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 300:59] + node _T_413 = and(dmcontrol_wren_Q, _T_412) @[dbg.scala 300:44] + node _T_414 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 300:81] + node _T_415 = not(_T_414) @[dbg.scala 300:67] + node _T_416 = and(_T_413, _T_415) @[dbg.scala 300:64] + node _T_417 = bits(_T_416, 0, 0) @[dbg.scala 300:102] + io.dbg_halt_req <= _T_417 @[dbg.scala 300:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_433 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30] - when _T_433 : @[Conditional.scala 39:67] + node _T_418 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30] + when _T_418 : @[Conditional.scala 39:67] dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 303:20] - node _T_434 = bits(dmstatus_reg, 17, 17) @[dbg.scala 304:35] - node _T_435 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 304:55] - node _T_436 = or(_T_434, _T_435) @[dbg.scala 304:40] - dbg_state_en <= _T_436 @[dbg.scala 304:20] - node _T_437 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59] - node _T_438 = and(dmcontrol_wren_Q, _T_437) @[dbg.scala 305:44] - node _T_439 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81] - node _T_440 = not(_T_439) @[dbg.scala 305:67] - node _T_441 = and(_T_438, _T_440) @[dbg.scala 305:64] - node _T_442 = bits(_T_441, 0, 0) @[dbg.scala 305:102] - io.dbg_halt_req <= _T_442 @[dbg.scala 305:23] + node _T_419 = bits(dmstatus_reg, 17, 17) @[dbg.scala 304:35] + node _T_420 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 304:55] + node _T_421 = or(_T_419, _T_420) @[dbg.scala 304:40] + dbg_state_en <= _T_421 @[dbg.scala 304:20] + node _T_422 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59] + node _T_423 = and(dmcontrol_wren_Q, _T_422) @[dbg.scala 305:44] + node _T_424 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81] + node _T_425 = not(_T_424) @[dbg.scala 305:67] + node _T_426 = and(_T_423, _T_425) @[dbg.scala 305:64] + node _T_427 = bits(_T_426, 0, 0) @[dbg.scala 305:102] + io.dbg_halt_req <= _T_427 @[dbg.scala 305:23] skip @[Conditional.scala 39:67] - node _T_443 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 308:52] - node _T_444 = bits(_T_443, 0, 0) @[Bitwise.scala 72:15] - node _T_445 = mux(_T_444, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_446 = and(_T_445, data0_reg) @[dbg.scala 308:71] - node _T_447 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 308:110] + node _T_428 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 308:52] + node _T_429 = bits(_T_428, 0, 0) @[Bitwise.scala 72:15] + node _T_430 = mux(_T_429, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_431 = and(_T_430, data0_reg) @[dbg.scala 308:71] + node _T_432 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 308:110] + node _T_433 = bits(_T_432, 0, 0) @[Bitwise.scala 72:15] + node _T_434 = mux(_T_433, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_435 = and(_T_434, data1_reg) @[dbg.scala 308:122] + node _T_436 = or(_T_431, _T_435) @[dbg.scala 308:83] + node _T_437 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 309:30] + node _T_438 = bits(_T_437, 0, 0) @[Bitwise.scala 72:15] + node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_440 = and(_T_439, dmcontrol_reg) @[dbg.scala 309:43] + node _T_441 = or(_T_436, _T_440) @[dbg.scala 308:134] + node _T_442 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 309:86] + node _T_443 = bits(_T_442, 0, 0) @[Bitwise.scala 72:15] + node _T_444 = mux(_T_443, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_445 = and(_T_444, dmstatus_reg) @[dbg.scala 309:99] + node _T_446 = or(_T_441, _T_445) @[dbg.scala 309:59] + node _T_447 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 310:30] node _T_448 = bits(_T_447, 0, 0) @[Bitwise.scala 72:15] node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_450 = and(_T_449, data1_reg) @[dbg.scala 308:122] - node _T_451 = or(_T_446, _T_450) @[dbg.scala 308:83] - node _T_452 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 309:30] + node _T_450 = and(_T_449, abstractcs_reg) @[dbg.scala 310:43] + node _T_451 = or(_T_446, _T_450) @[dbg.scala 309:114] + node _T_452 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 310:87] node _T_453 = bits(_T_452, 0, 0) @[Bitwise.scala 72:15] node _T_454 = mux(_T_453, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_455 = and(_T_454, dmcontrol_reg) @[dbg.scala 309:43] - node _T_456 = or(_T_451, _T_455) @[dbg.scala 308:134] - node _T_457 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 309:86] + node _T_455 = and(_T_454, command_reg) @[dbg.scala 310:100] + node _T_456 = or(_T_451, _T_455) @[dbg.scala 310:60] + node _T_457 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 311:30] node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_460 = and(_T_459, dmstatus_reg) @[dbg.scala 309:99] - node _T_461 = or(_T_456, _T_460) @[dbg.scala 309:59] - node _T_462 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 310:30] + node _T_460 = and(_T_459, haltsum0_reg) @[dbg.scala 311:43] + node _T_461 = or(_T_456, _T_460) @[dbg.scala 310:114] + node _T_462 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 311:85] node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15] node _T_464 = mux(_T_463, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_465 = and(_T_464, abstractcs_reg) @[dbg.scala 310:43] - node _T_466 = or(_T_461, _T_465) @[dbg.scala 309:114] - node _T_467 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 310:87] + node _T_465 = and(_T_464, sbcs_reg) @[dbg.scala 311:98] + node _T_466 = or(_T_461, _T_465) @[dbg.scala 311:58] + node _T_467 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 312:30] node _T_468 = bits(_T_467, 0, 0) @[Bitwise.scala 72:15] node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_470 = and(_T_469, command_reg) @[dbg.scala 310:100] - node _T_471 = or(_T_466, _T_470) @[dbg.scala 310:60] - node _T_472 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 311:30] + node _T_470 = and(_T_469, sbaddress0_reg) @[dbg.scala 312:43] + node _T_471 = or(_T_466, _T_470) @[dbg.scala 311:109] + node _T_472 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 312:87] node _T_473 = bits(_T_472, 0, 0) @[Bitwise.scala 72:15] node _T_474 = mux(_T_473, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_475 = and(_T_474, haltsum0_reg) @[dbg.scala 311:43] - node _T_476 = or(_T_471, _T_475) @[dbg.scala 310:114] - node _T_477 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 311:85] + node _T_475 = and(_T_474, sbdata0_reg) @[dbg.scala 312:100] + node _T_476 = or(_T_471, _T_475) @[dbg.scala 312:60] + node _T_477 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 313:30] node _T_478 = bits(_T_477, 0, 0) @[Bitwise.scala 72:15] node _T_479 = mux(_T_478, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_480 = and(_T_479, sbcs_reg) @[dbg.scala 311:98] - node _T_481 = or(_T_476, _T_480) @[dbg.scala 311:58] - node _T_482 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 312:30] - node _T_483 = bits(_T_482, 0, 0) @[Bitwise.scala 72:15] - node _T_484 = mux(_T_483, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_485 = and(_T_484, sbaddress0_reg) @[dbg.scala 312:43] - node _T_486 = or(_T_481, _T_485) @[dbg.scala 311:109] - node _T_487 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 312:87] - node _T_488 = bits(_T_487, 0, 0) @[Bitwise.scala 72:15] - node _T_489 = mux(_T_488, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_490 = and(_T_489, sbdata0_reg) @[dbg.scala 312:100] - node _T_491 = or(_T_486, _T_490) @[dbg.scala 312:60] - node _T_492 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 313:30] - node _T_493 = bits(_T_492, 0, 0) @[Bitwise.scala 72:15] - node _T_494 = mux(_T_493, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_495 = and(_T_494, sbdata1_reg) @[dbg.scala 313:43] - node dmi_reg_rdata_din = or(_T_491, _T_495) @[dbg.scala 312:114] - node _T_496 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 315:49] - node _T_497 = and(_T_496, temp_rst) @[dbg.scala 315:63] - node _T_498 = asAsyncReset(_T_497) @[dbg.scala 315:87] - reg _T_499 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_498, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_480 = and(_T_479, sbdata1_reg) @[dbg.scala 313:43] + node dmi_reg_rdata_din = or(_T_476, _T_480) @[dbg.scala 312:114] + node _T_481 = and(dbg_dm_rst_l, temp_rst) @[dbg.scala 315:62] + node _T_482 = asAsyncReset(_T_481) @[dbg.scala 315:86] + reg _T_483 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_482, UInt<1>("h00"))) @[Reg.scala 27:20] when dbg_state_en : @[Reg.scala 28:19] - _T_499 <= dbg_nxtstate @[Reg.scala 28:23] + _T_483 <= dbg_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - dbg_state <= _T_499 @[dbg.scala 315:13] - node _T_500 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 320:56] - node _T_501 = asAsyncReset(_T_500) @[dbg.scala 320:83] - reg _T_502 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_501, UInt<1>("h00"))) @[Reg.scala 27:20] + dbg_state <= _T_483 @[dbg.scala 315:13] + node _T_484 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 320:82] + reg _T_485 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_484, UInt<1>("h00"))) @[Reg.scala 27:20] when io.dmi_reg_en : @[Reg.scala 28:19] - _T_502 <= dmi_reg_rdata_din @[Reg.scala 28:23] + _T_485 <= dmi_reg_rdata_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.dmi_reg_rdata <= _T_502 @[dbg.scala 320:20] - node _T_503 = bits(command_reg, 31, 24) @[dbg.scala 324:53] - node _T_504 = eq(_T_503, UInt<2>("h02")) @[dbg.scala 324:62] - node _T_505 = bits(data1_reg, 31, 2) @[dbg.scala 324:88] - node _T_506 = cat(_T_505, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_507 = bits(command_reg, 11, 0) @[dbg.scala 324:133] - node _T_508 = cat(UInt<20>("h00"), _T_507) @[Cat.scala 29:58] - node _T_509 = mux(_T_504, _T_506, _T_508) @[dbg.scala 324:40] - io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_509 @[dbg.scala 324:34] - node _T_510 = bits(data0_reg, 31, 0) @[dbg.scala 325:50] - io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_510 @[dbg.scala 325:38] - node _T_511 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 326:50] - node _T_512 = bits(abstractcs_reg, 10, 8) @[dbg.scala 326:91] - node _T_513 = orr(_T_512) @[dbg.scala 326:99] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[dbg.scala 326:75] - node _T_515 = and(_T_511, _T_514) @[dbg.scala 326:73] - node _T_516 = and(_T_515, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 326:104] - node _T_517 = bits(_T_516, 0, 0) @[dbg.scala 326:141] - io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_517 @[dbg.scala 326:35] - node _T_518 = bits(command_reg, 16, 16) @[dbg.scala 327:49] - node _T_519 = bits(_T_518, 0, 0) @[dbg.scala 327:60] - io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_519 @[dbg.scala 327:35] - node _T_520 = bits(command_reg, 31, 24) @[dbg.scala 328:53] - node _T_521 = eq(_T_520, UInt<2>("h02")) @[dbg.scala 328:62] - node _T_522 = bits(command_reg, 15, 12) @[dbg.scala 328:108] - node _T_523 = eq(_T_522, UInt<1>("h00")) @[dbg.scala 328:117] - node _T_524 = cat(UInt<1>("h00"), _T_523) @[Cat.scala 29:58] - node _T_525 = mux(_T_521, UInt<2>("h02"), _T_524) @[dbg.scala 328:40] - io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_525 @[dbg.scala 328:34] - node _T_526 = bits(command_reg, 21, 20) @[dbg.scala 329:33] - io.dbg_cmd_size <= _T_526 @[dbg.scala 329:19] - node _T_527 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 330:47] - node _T_528 = bits(abstractcs_reg, 10, 8) @[dbg.scala 330:88] - node _T_529 = orr(_T_528) @[dbg.scala 330:96] - node _T_530 = eq(_T_529, UInt<1>("h00")) @[dbg.scala 330:72] - node _T_531 = and(_T_527, _T_530) @[dbg.scala 330:70] - node _T_532 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 330:114] - node _T_533 = or(_T_531, _T_532) @[dbg.scala 330:101] - node _T_534 = bits(_T_533, 0, 0) @[dbg.scala 330:143] - io.dbg_dma_io.dbg_dma_bubble <= _T_534 @[dbg.scala 330:32] + io.dmi_reg_rdata <= _T_485 @[dbg.scala 320:20] + node _T_486 = bits(command_reg, 31, 24) @[dbg.scala 324:53] + node _T_487 = eq(_T_486, UInt<2>("h02")) @[dbg.scala 324:62] + node _T_488 = bits(data1_reg, 31, 2) @[dbg.scala 324:88] + node _T_489 = cat(_T_488, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_490 = bits(command_reg, 11, 0) @[dbg.scala 324:138] + node _T_491 = cat(UInt<20>("h00"), _T_490) @[Cat.scala 29:58] + node _T_492 = mux(_T_487, _T_489, _T_491) @[dbg.scala 324:40] + io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_492 @[dbg.scala 324:34] + node _T_493 = bits(data0_reg, 31, 0) @[dbg.scala 325:50] + io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_493 @[dbg.scala 325:38] + node _T_494 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 326:50] + node _T_495 = bits(abstractcs_reg, 10, 8) @[dbg.scala 326:91] + node _T_496 = orr(_T_495) @[dbg.scala 326:99] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[dbg.scala 326:75] + node _T_498 = and(_T_494, _T_497) @[dbg.scala 326:73] + node _T_499 = and(_T_498, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 326:104] + node _T_500 = bits(_T_499, 0, 0) @[dbg.scala 326:141] + io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_500 @[dbg.scala 326:35] + node _T_501 = bits(command_reg, 16, 16) @[dbg.scala 327:49] + node _T_502 = bits(_T_501, 0, 0) @[dbg.scala 327:60] + io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_502 @[dbg.scala 327:35] + node _T_503 = bits(command_reg, 31, 24) @[dbg.scala 328:53] + node _T_504 = eq(_T_503, UInt<2>("h02")) @[dbg.scala 328:62] + node _T_505 = bits(command_reg, 15, 12) @[dbg.scala 328:113] + node _T_506 = eq(_T_505, UInt<1>("h00")) @[dbg.scala 328:122] + node _T_507 = cat(UInt<1>("h00"), _T_506) @[Cat.scala 29:58] + node _T_508 = mux(_T_504, UInt<2>("h02"), _T_507) @[dbg.scala 328:40] + io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_508 @[dbg.scala 328:34] + node _T_509 = bits(command_reg, 21, 20) @[dbg.scala 329:33] + io.dbg_cmd_size <= _T_509 @[dbg.scala 329:19] + node _T_510 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 330:47] + node _T_511 = bits(abstractcs_reg, 10, 8) @[dbg.scala 330:88] + node _T_512 = orr(_T_511) @[dbg.scala 330:96] + node _T_513 = eq(_T_512, UInt<1>("h00")) @[dbg.scala 330:72] + node _T_514 = and(_T_510, _T_513) @[dbg.scala 330:70] + node _T_515 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 330:114] + node _T_516 = or(_T_514, _T_515) @[dbg.scala 330:101] + node _T_517 = bits(_T_516, 0, 0) @[dbg.scala 330:143] + io.dbg_dma_io.dbg_dma_bubble <= _T_517 @[dbg.scala 330:32] wire sb_nxtstate : UInt<4> sb_nxtstate <= UInt<4>("h00") sb_nxtstate <= UInt<4>("h00") @[dbg.scala 333:15] @@ -1028,288 +1009,287 @@ circuit dbg : sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 337:21] sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 338:20] sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 339:24] - node _T_535 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30] - when _T_535 : @[Conditional.scala 40:58] - node _T_536 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 342:25] - sb_nxtstate <= _T_536 @[dbg.scala 342:19] - node _T_537 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 343:39] - node _T_538 = or(_T_537, sbreadonaddr_access) @[dbg.scala 343:61] - sb_state_en <= _T_538 @[dbg.scala 343:19] + node _T_518 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30] + when _T_518 : @[Conditional.scala 40:58] + node _T_519 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 342:25] + sb_nxtstate <= _T_519 @[dbg.scala 342:19] + node _T_520 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 343:39] + node _T_521 = or(_T_520, sbreadonaddr_access) @[dbg.scala 343:61] + sb_state_en <= _T_521 @[dbg.scala 343:19] sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 344:24] sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 345:23] - node _T_539 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 346:56] - node _T_540 = orr(_T_539) @[dbg.scala 346:65] - node _T_541 = and(sbcs_wren, _T_540) @[dbg.scala 346:38] - sbcs_sberror_wren <= _T_541 @[dbg.scala 346:25] - node _T_542 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 347:44] - node _T_543 = eq(_T_542, UInt<1>("h00")) @[dbg.scala 347:27] - node _T_544 = bits(sbcs_reg, 14, 12) @[dbg.scala 347:63] - node _T_545 = and(_T_543, _T_544) @[dbg.scala 347:53] - sbcs_sberror_din <= _T_545 @[dbg.scala 347:24] + node _T_522 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 346:56] + node _T_523 = orr(_T_522) @[dbg.scala 346:65] + node _T_524 = and(sbcs_wren, _T_523) @[dbg.scala 346:38] + sbcs_sberror_wren <= _T_524 @[dbg.scala 346:25] + node _T_525 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 347:44] + node _T_526 = not(_T_525) @[dbg.scala 347:27] + node _T_527 = bits(sbcs_reg, 14, 12) @[dbg.scala 347:63] + node _T_528 = and(_T_526, _T_527) @[dbg.scala 347:53] + sbcs_sberror_din <= _T_528 @[dbg.scala 347:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_546 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30] - when _T_546 : @[Conditional.scala 39:67] - node _T_547 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 350:41] - node _T_548 = mux(_T_547, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 350:25] - sb_nxtstate <= _T_548 @[dbg.scala 350:19] - node _T_549 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 351:40] - node _T_550 = or(_T_549, sbcs_illegal_size) @[dbg.scala 351:57] - sb_state_en <= _T_550 @[dbg.scala 351:19] - node _T_551 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 352:43] - sbcs_sberror_wren <= _T_551 @[dbg.scala 352:25] - node _T_552 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[dbg.scala 353:30] - sbcs_sberror_din <= _T_552 @[dbg.scala 353:24] + node _T_529 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30] + when _T_529 : @[Conditional.scala 39:67] + node _T_530 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 350:41] + node _T_531 = mux(_T_530, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 350:25] + sb_nxtstate <= _T_531 @[dbg.scala 350:19] + node _T_532 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 351:40] + node _T_533 = or(_T_532, sbcs_illegal_size) @[dbg.scala 351:57] + sb_state_en <= _T_533 @[dbg.scala 351:19] + node _T_534 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 352:43] + sbcs_sberror_wren <= _T_534 @[dbg.scala 352:25] + node _T_535 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 353:30] + sbcs_sberror_din <= _T_535 @[dbg.scala 353:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_553 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30] - when _T_553 : @[Conditional.scala 39:67] - node _T_554 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 356:41] - node _T_555 = mux(_T_554, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 356:25] - sb_nxtstate <= _T_555 @[dbg.scala 356:19] - node _T_556 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 357:40] - node _T_557 = or(_T_556, sbcs_illegal_size) @[dbg.scala 357:57] - sb_state_en <= _T_557 @[dbg.scala 357:19] - node _T_558 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 358:43] - sbcs_sberror_wren <= _T_558 @[dbg.scala 358:25] - node _T_559 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[dbg.scala 359:30] - sbcs_sberror_din <= _T_559 @[dbg.scala 359:24] + node _T_536 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30] + when _T_536 : @[Conditional.scala 39:67] + node _T_537 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 356:41] + node _T_538 = mux(_T_537, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 356:25] + sb_nxtstate <= _T_538 @[dbg.scala 356:19] + node _T_539 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 357:40] + node _T_540 = or(_T_539, sbcs_illegal_size) @[dbg.scala 357:57] + sb_state_en <= _T_540 @[dbg.scala 357:19] + node _T_541 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 358:43] + sbcs_sberror_wren <= _T_541 @[dbg.scala 358:25] + node _T_542 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 359:30] + sbcs_sberror_din <= _T_542 @[dbg.scala 359:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_560 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30] - when _T_560 : @[Conditional.scala 39:67] + node _T_543 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30] + when _T_543 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h07") @[dbg.scala 362:19] - node _T_561 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 363:38] - sb_state_en <= _T_561 @[dbg.scala 363:19] + node _T_544 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 363:38] + sb_state_en <= _T_544 @[dbg.scala 363:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_562 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30] - when _T_562 : @[Conditional.scala 39:67] - node _T_563 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 366:48] - node _T_564 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 366:95] - node _T_565 = mux(_T_563, UInt<4>("h08"), _T_564) @[dbg.scala 366:25] - sb_nxtstate <= _T_565 @[dbg.scala 366:19] - node _T_566 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 367:45] - node _T_567 = and(_T_566, io.dbg_bus_clk_en) @[dbg.scala 367:70] - sb_state_en <= _T_567 @[dbg.scala 367:19] + node _T_545 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30] + when _T_545 : @[Conditional.scala 39:67] + node _T_546 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 366:48] + node _T_547 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 366:95] + node _T_548 = mux(_T_546, UInt<4>("h08"), _T_547) @[dbg.scala 366:25] + sb_nxtstate <= _T_548 @[dbg.scala 366:19] + node _T_549 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 367:45] + node _T_550 = and(_T_549, io.dbg_bus_clk_en) @[dbg.scala 367:70] + sb_state_en <= _T_550 @[dbg.scala 367:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_568 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30] - when _T_568 : @[Conditional.scala 39:67] + node _T_551 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30] + when _T_551 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h08") @[dbg.scala 370:19] - node _T_569 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 371:44] - sb_state_en <= _T_569 @[dbg.scala 371:19] + node _T_552 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 371:44] + sb_state_en <= _T_552 @[dbg.scala 371:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_570 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30] - when _T_570 : @[Conditional.scala 39:67] + node _T_553 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30] + when _T_553 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h08") @[dbg.scala 374:19] - node _T_571 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 375:44] - sb_state_en <= _T_571 @[dbg.scala 375:19] + node _T_554 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 375:44] + sb_state_en <= _T_554 @[dbg.scala 375:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_572 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30] - when _T_572 : @[Conditional.scala 39:67] + node _T_555 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30] + when _T_555 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h09") @[dbg.scala 378:19] - node _T_573 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 379:38] - sb_state_en <= _T_573 @[dbg.scala 379:19] - node _T_574 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 380:40] - sbcs_sberror_wren <= _T_574 @[dbg.scala 380:25] - sbcs_sberror_din <= UInt<2>("h02") @[dbg.scala 381:24] + node _T_556 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 379:38] + sb_state_en <= _T_556 @[dbg.scala 379:19] + node _T_557 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 380:40] + sbcs_sberror_wren <= _T_557 @[dbg.scala 380:25] + sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 381:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_575 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30] - when _T_575 : @[Conditional.scala 39:67] + node _T_558 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30] + when _T_558 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h09") @[dbg.scala 384:19] - node _T_576 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 385:39] - sb_state_en <= _T_576 @[dbg.scala 385:19] - node _T_577 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 386:40] - sbcs_sberror_wren <= _T_577 @[dbg.scala 386:25] - sbcs_sberror_din <= UInt<2>("h02") @[dbg.scala 387:24] + node _T_559 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 385:39] + sb_state_en <= _T_559 @[dbg.scala 385:19] + node _T_560 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 386:40] + sbcs_sberror_wren <= _T_560 @[dbg.scala 386:25] + sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 387:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_578 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30] - when _T_578 : @[Conditional.scala 39:67] + node _T_561 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30] + when _T_561 : @[Conditional.scala 39:67] sb_nxtstate <= UInt<4>("h00") @[dbg.scala 390:19] sb_state_en <= UInt<1>("h01") @[dbg.scala 391:19] sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 392:24] sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 393:23] - node _T_579 = bits(sbcs_reg, 16, 16) @[dbg.scala 394:39] - sbaddress0_reg_wren1 <= _T_579 @[dbg.scala 394:28] + node _T_562 = bits(sbcs_reg, 16, 16) @[dbg.scala 394:39] + sbaddress0_reg_wren1 <= _T_562 @[dbg.scala 394:28] skip @[Conditional.scala 39:67] - node _T_580 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 397:47] - node _T_581 = asAsyncReset(_T_580) @[dbg.scala 397:74] - reg _T_582 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_581, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_563 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 397:73] + reg _T_564 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_563, UInt<1>("h00"))) @[Reg.scala 27:20] when sb_state_en : @[Reg.scala 28:19] - _T_582 <= sb_nxtstate @[Reg.scala 28:23] + _T_564 <= sb_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - sb_state <= _T_582 @[dbg.scala 397:12] - node _T_583 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 401:41] - sb_bus_cmd_read <= _T_583 @[dbg.scala 401:19] - node _T_584 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 402:47] - sb_bus_cmd_write_addr <= _T_584 @[dbg.scala 402:25] - node _T_585 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 403:46] - sb_bus_cmd_write_data <= _T_585 @[dbg.scala 403:25] - node _T_586 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 404:40] - sb_bus_rsp_read <= _T_586 @[dbg.scala 404:19] - node _T_587 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 405:41] - sb_bus_rsp_write <= _T_587 @[dbg.scala 405:20] - node _T_588 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 406:62] - node _T_589 = orr(_T_588) @[dbg.scala 406:69] - node _T_590 = and(sb_bus_rsp_read, _T_589) @[dbg.scala 406:39] - node _T_591 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 406:115] - node _T_592 = orr(_T_591) @[dbg.scala 406:122] - node _T_593 = and(sb_bus_rsp_write, _T_592) @[dbg.scala 406:92] - node _T_594 = or(_T_590, _T_593) @[dbg.scala 406:73] - sb_bus_rsp_error <= _T_594 @[dbg.scala 406:20] - node _T_595 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 407:36] - node _T_596 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 407:71] - node _T_597 = or(_T_595, _T_596) @[dbg.scala 407:59] - node _T_598 = bits(_T_597, 0, 0) @[dbg.scala 407:106] - io.sb_axi.aw.valid <= _T_598 @[dbg.scala 407:22] + sb_state <= _T_564 @[dbg.scala 397:12] + node _T_565 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 401:41] + sb_bus_cmd_read <= _T_565 @[dbg.scala 401:19] + node _T_566 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 402:47] + sb_bus_cmd_write_addr <= _T_566 @[dbg.scala 402:25] + node _T_567 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 403:46] + sb_bus_cmd_write_data <= _T_567 @[dbg.scala 403:25] + node _T_568 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 404:40] + sb_bus_rsp_read <= _T_568 @[dbg.scala 404:19] + node _T_569 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 405:41] + sb_bus_rsp_write <= _T_569 @[dbg.scala 405:20] + node _T_570 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 406:62] + node _T_571 = orr(_T_570) @[dbg.scala 406:69] + node _T_572 = and(sb_bus_rsp_read, _T_571) @[dbg.scala 406:39] + node _T_573 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 406:115] + node _T_574 = orr(_T_573) @[dbg.scala 406:122] + node _T_575 = and(sb_bus_rsp_write, _T_574) @[dbg.scala 406:92] + node _T_576 = or(_T_572, _T_575) @[dbg.scala 406:73] + sb_bus_rsp_error <= _T_576 @[dbg.scala 406:20] + node _T_577 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 407:36] + node _T_578 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 407:71] + node _T_579 = or(_T_577, _T_578) @[dbg.scala 407:59] + node _T_580 = bits(_T_579, 0, 0) @[dbg.scala 407:106] + io.sb_axi.aw.valid <= _T_580 @[dbg.scala 407:22] io.sb_axi.aw.bits.addr <= sbaddress0_reg @[dbg.scala 408:26] io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 409:24] - node _T_599 = bits(sbcs_reg, 19, 17) @[dbg.scala 410:37] - io.sb_axi.aw.bits.size <= _T_599 @[dbg.scala 410:26] + node _T_581 = bits(sbcs_reg, 19, 17) @[dbg.scala 410:37] + io.sb_axi.aw.bits.size <= _T_581 @[dbg.scala 410:26] io.sb_axi.aw.bits.prot <= UInt<1>("h00") @[dbg.scala 411:26] io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 412:27] - node _T_600 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 413:45] - io.sb_axi.aw.bits.region <= _T_600 @[dbg.scala 413:28] + node _T_582 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 413:45] + io.sb_axi.aw.bits.region <= _T_582 @[dbg.scala 413:28] io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 414:25] - io.sb_axi.aw.bits.burst <= UInt<1>("h01") @[dbg.scala 415:27] + io.sb_axi.aw.bits.burst <= UInt<2>("h01") @[dbg.scala 415:27] io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 416:25] io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 417:26] - node _T_601 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 418:35] - node _T_602 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 418:70] - node _T_603 = or(_T_601, _T_602) @[dbg.scala 418:58] - node _T_604 = bits(_T_603, 0, 0) @[dbg.scala 418:105] - io.sb_axi.w.valid <= _T_604 @[dbg.scala 418:21] - node _T_605 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:46] - node _T_606 = eq(_T_605, UInt<1>("h00")) @[dbg.scala 419:55] + node _T_583 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 418:35] + node _T_584 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 418:70] + node _T_585 = or(_T_583, _T_584) @[dbg.scala 418:58] + node _T_586 = bits(_T_585, 0, 0) @[dbg.scala 418:105] + io.sb_axi.w.valid <= _T_586 @[dbg.scala 418:21] + node _T_587 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:46] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[dbg.scala 419:55] + node _T_589 = bits(_T_588, 0, 0) @[Bitwise.scala 72:15] + node _T_590 = mux(_T_589, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_591 = bits(sbdata0_reg, 7, 0) @[dbg.scala 419:87] + node _T_592 = cat(_T_591, _T_591) @[Cat.scala 29:58] + node _T_593 = cat(_T_592, _T_592) @[Cat.scala 29:58] + node _T_594 = cat(_T_593, _T_593) @[Cat.scala 29:58] + node _T_595 = and(_T_590, _T_594) @[dbg.scala 419:65] + node _T_596 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:116] + node _T_597 = eq(_T_596, UInt<1>("h01")) @[dbg.scala 419:125] + node _T_598 = bits(_T_597, 0, 0) @[Bitwise.scala 72:15] + node _T_599 = mux(_T_598, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_600 = bits(sbdata0_reg, 15, 0) @[dbg.scala 419:159] + node _T_601 = cat(_T_600, _T_600) @[Cat.scala 29:58] + node _T_602 = cat(_T_601, _T_601) @[Cat.scala 29:58] + node _T_603 = and(_T_599, _T_602) @[dbg.scala 419:138] + node _T_604 = or(_T_595, _T_603) @[dbg.scala 419:96] + node _T_605 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:23] + node _T_606 = eq(_T_605, UInt<2>("h02")) @[dbg.scala 420:32] node _T_607 = bits(_T_606, 0, 0) @[Bitwise.scala 72:15] node _T_608 = mux(_T_607, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_609 = bits(sbdata0_reg, 7, 0) @[dbg.scala 419:87] + node _T_609 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:67] node _T_610 = cat(_T_609, _T_609) @[Cat.scala 29:58] - node _T_611 = cat(_T_610, _T_610) @[Cat.scala 29:58] - node _T_612 = cat(_T_611, _T_611) @[Cat.scala 29:58] - node _T_613 = and(_T_608, _T_612) @[dbg.scala 419:65] - node _T_614 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:116] - node _T_615 = eq(_T_614, UInt<1>("h01")) @[dbg.scala 419:125] - node _T_616 = bits(_T_615, 0, 0) @[Bitwise.scala 72:15] - node _T_617 = mux(_T_616, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_618 = bits(sbdata0_reg, 15, 0) @[dbg.scala 419:159] - node _T_619 = cat(_T_618, _T_618) @[Cat.scala 29:58] - node _T_620 = cat(_T_619, _T_619) @[Cat.scala 29:58] - node _T_621 = and(_T_617, _T_620) @[dbg.scala 419:138] - node _T_622 = or(_T_613, _T_621) @[dbg.scala 419:96] - node _T_623 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:23] - node _T_624 = eq(_T_623, UInt<2>("h02")) @[dbg.scala 420:32] - node _T_625 = bits(_T_624, 0, 0) @[Bitwise.scala 72:15] - node _T_626 = mux(_T_625, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_627 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:67] - node _T_628 = cat(_T_627, _T_627) @[Cat.scala 29:58] - node _T_629 = and(_T_626, _T_628) @[dbg.scala 420:45] - node _T_630 = or(_T_622, _T_629) @[dbg.scala 419:168] - node _T_631 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:97] - node _T_632 = eq(_T_631, UInt<2>("h03")) @[dbg.scala 420:106] - node _T_633 = bits(_T_632, 0, 0) @[Bitwise.scala 72:15] - node _T_634 = mux(_T_633, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_635 = bits(sbdata1_reg, 31, 0) @[dbg.scala 420:136] - node _T_636 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:156] - node _T_637 = cat(_T_635, _T_636) @[Cat.scala 29:58] - node _T_638 = and(_T_634, _T_637) @[dbg.scala 420:119] - node _T_639 = or(_T_630, _T_638) @[dbg.scala 420:77] - io.sb_axi.w.bits.data <= _T_639 @[dbg.scala 419:25] - node _T_640 = bits(sbcs_reg, 19, 17) @[dbg.scala 422:45] - node _T_641 = eq(_T_640, UInt<1>("h00")) @[dbg.scala 422:54] - node _T_642 = bits(_T_641, 0, 0) @[Bitwise.scala 72:15] - node _T_643 = mux(_T_642, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_644 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 422:99] - node _T_645 = dshl(UInt<8>("h01"), _T_644) @[dbg.scala 422:82] - node _T_646 = and(_T_643, _T_645) @[dbg.scala 422:67] - node _T_647 = bits(sbcs_reg, 19, 17) @[dbg.scala 423:22] - node _T_648 = eq(_T_647, UInt<1>("h01")) @[dbg.scala 423:31] + node _T_611 = and(_T_608, _T_610) @[dbg.scala 420:45] + node _T_612 = or(_T_604, _T_611) @[dbg.scala 419:168] + node _T_613 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:97] + node _T_614 = eq(_T_613, UInt<2>("h03")) @[dbg.scala 420:106] + node _T_615 = bits(_T_614, 0, 0) @[Bitwise.scala 72:15] + node _T_616 = mux(_T_615, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_617 = bits(sbdata1_reg, 31, 0) @[dbg.scala 420:136] + node _T_618 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:156] + node _T_619 = cat(_T_617, _T_618) @[Cat.scala 29:58] + node _T_620 = and(_T_616, _T_619) @[dbg.scala 420:119] + node _T_621 = or(_T_612, _T_620) @[dbg.scala 420:77] + io.sb_axi.w.bits.data <= _T_621 @[dbg.scala 419:25] + node _T_622 = bits(sbcs_reg, 19, 17) @[dbg.scala 422:45] + node _T_623 = eq(_T_622, UInt<1>("h00")) @[dbg.scala 422:54] + node _T_624 = bits(_T_623, 0, 0) @[Bitwise.scala 72:15] + node _T_625 = mux(_T_624, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_626 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 422:99] + node _T_627 = dshl(UInt<8>("h01"), _T_626) @[dbg.scala 422:82] + node _T_628 = and(_T_625, _T_627) @[dbg.scala 422:67] + node _T_629 = bits(sbcs_reg, 19, 17) @[dbg.scala 423:22] + node _T_630 = eq(_T_629, UInt<1>("h01")) @[dbg.scala 423:31] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 423:80] + node _T_634 = cat(_T_633, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_635 = dshl(UInt<8>("h03"), _T_634) @[dbg.scala 423:59] + node _T_636 = and(_T_632, _T_635) @[dbg.scala 423:44] + node _T_637 = or(_T_628, _T_636) @[dbg.scala 422:107] + node _T_638 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:22] + node _T_639 = eq(_T_638, UInt<2>("h02")) @[dbg.scala 424:31] + node _T_640 = bits(_T_639, 0, 0) @[Bitwise.scala 72:15] + node _T_641 = mux(_T_640, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_642 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 424:80] + node _T_643 = cat(_T_642, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_644 = dshl(UInt<8>("h0f"), _T_643) @[dbg.scala 424:59] + node _T_645 = and(_T_641, _T_644) @[dbg.scala 424:44] + node _T_646 = or(_T_637, _T_645) @[dbg.scala 423:97] + node _T_647 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:22] + node _T_648 = eq(_T_647, UInt<2>("h03")) @[dbg.scala 425:31] node _T_649 = bits(_T_648, 0, 0) @[Bitwise.scala 72:15] node _T_650 = mux(_T_649, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_651 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 423:80] - node _T_652 = cat(_T_651, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_653 = dshl(UInt<8>("h03"), _T_652) @[dbg.scala 423:59] - node _T_654 = and(_T_650, _T_653) @[dbg.scala 423:44] - node _T_655 = or(_T_646, _T_654) @[dbg.scala 422:107] - node _T_656 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:22] - node _T_657 = eq(_T_656, UInt<2>("h02")) @[dbg.scala 424:31] - node _T_658 = bits(_T_657, 0, 0) @[Bitwise.scala 72:15] - node _T_659 = mux(_T_658, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_660 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 424:80] - node _T_661 = cat(_T_660, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_662 = dshl(UInt<8>("h0f"), _T_661) @[dbg.scala 424:59] - node _T_663 = and(_T_659, _T_662) @[dbg.scala 424:44] - node _T_664 = or(_T_655, _T_663) @[dbg.scala 423:97] - node _T_665 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:22] - node _T_666 = eq(_T_665, UInt<2>("h03")) @[dbg.scala 425:31] - node _T_667 = bits(_T_666, 0, 0) @[Bitwise.scala 72:15] - node _T_668 = mux(_T_667, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_669 = and(_T_668, UInt<8>("h0ff")) @[dbg.scala 425:44] - node _T_670 = or(_T_664, _T_669) @[dbg.scala 424:95] - io.sb_axi.w.bits.strb <= _T_670 @[dbg.scala 422:25] + node _T_651 = and(_T_650, UInt<8>("h0ff")) @[dbg.scala 425:44] + node _T_652 = or(_T_646, _T_651) @[dbg.scala 424:100] + io.sb_axi.w.bits.strb <= _T_652 @[dbg.scala 422:25] io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 427:25] - node _T_671 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 428:35] - node _T_672 = bits(_T_671, 0, 0) @[dbg.scala 428:64] - io.sb_axi.ar.valid <= _T_672 @[dbg.scala 428:22] + node _T_653 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 428:35] + node _T_654 = bits(_T_653, 0, 0) @[dbg.scala 428:64] + io.sb_axi.ar.valid <= _T_654 @[dbg.scala 428:22] io.sb_axi.ar.bits.addr <= sbaddress0_reg @[dbg.scala 429:26] io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 430:24] - node _T_673 = bits(sbcs_reg, 19, 17) @[dbg.scala 431:37] - io.sb_axi.ar.bits.size <= _T_673 @[dbg.scala 431:26] + node _T_655 = bits(sbcs_reg, 19, 17) @[dbg.scala 431:37] + io.sb_axi.ar.bits.size <= _T_655 @[dbg.scala 431:26] io.sb_axi.ar.bits.prot <= UInt<1>("h00") @[dbg.scala 432:26] io.sb_axi.ar.bits.cache <= UInt<1>("h00") @[dbg.scala 433:27] - node _T_674 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 434:45] - io.sb_axi.ar.bits.region <= _T_674 @[dbg.scala 434:28] + node _T_656 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 434:45] + io.sb_axi.ar.bits.region <= _T_656 @[dbg.scala 434:28] io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 435:25] - io.sb_axi.ar.bits.burst <= UInt<1>("h01") @[dbg.scala 436:27] + io.sb_axi.ar.bits.burst <= UInt<2>("h01") @[dbg.scala 436:27] io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 437:25] io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 438:26] io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 439:21] io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 440:21] - node _T_675 = bits(sbcs_reg, 19, 17) @[dbg.scala 441:37] - node _T_676 = eq(_T_675, UInt<1>("h00")) @[dbg.scala 441:46] - node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] - node _T_678 = mux(_T_677, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_679 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 441:84] - node _T_680 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 441:115] - node _T_681 = mul(UInt<4>("h08"), _T_680) @[dbg.scala 441:99] - node _T_682 = dshr(_T_679, _T_681) @[dbg.scala 441:92] - node _T_683 = and(_T_682, UInt<64>("h0ff")) @[dbg.scala 441:123] - node _T_684 = and(_T_678, _T_683) @[dbg.scala 441:59] - node _T_685 = bits(sbcs_reg, 19, 17) @[dbg.scala 442:23] - node _T_686 = eq(_T_685, UInt<1>("h01")) @[dbg.scala 442:32] - node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] - node _T_688 = mux(_T_687, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_689 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 442:70] - node _T_690 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 442:102] - node _T_691 = mul(UInt<5>("h010"), _T_690) @[dbg.scala 442:86] - node _T_692 = dshr(_T_689, _T_691) @[dbg.scala 442:78] - node _T_693 = and(_T_692, UInt<64>("h0ffff")) @[dbg.scala 442:110] - node _T_694 = and(_T_688, _T_693) @[dbg.scala 442:45] - node _T_695 = or(_T_684, _T_694) @[dbg.scala 441:140] - node _T_696 = bits(sbcs_reg, 19, 17) @[dbg.scala 443:23] - node _T_697 = eq(_T_696, UInt<2>("h02")) @[dbg.scala 443:32] - node _T_698 = bits(_T_697, 0, 0) @[Bitwise.scala 72:15] - node _T_699 = mux(_T_698, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_700 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 443:70] - node _T_701 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 443:102] - node _T_702 = mul(UInt<6>("h020"), _T_701) @[dbg.scala 443:86] - node _T_703 = dshr(_T_700, _T_702) @[dbg.scala 443:78] - node _T_704 = and(_T_703, UInt<64>("h0ffffffff")) @[dbg.scala 443:107] - node _T_705 = and(_T_699, _T_704) @[dbg.scala 443:45] - node _T_706 = or(_T_695, _T_705) @[dbg.scala 442:129] - node _T_707 = bits(sbcs_reg, 19, 17) @[dbg.scala 444:23] - node _T_708 = eq(_T_707, UInt<2>("h03")) @[dbg.scala 444:32] - node _T_709 = bits(_T_708, 0, 0) @[Bitwise.scala 72:15] - node _T_710 = mux(_T_709, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_711 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 444:68] - node _T_712 = and(_T_710, _T_711) @[dbg.scala 444:45] - node _T_713 = or(_T_706, _T_712) @[dbg.scala 443:131] - sb_bus_rdata <= _T_713 @[dbg.scala 441:16] + node _T_657 = bits(sbcs_reg, 19, 17) @[dbg.scala 441:37] + node _T_658 = eq(_T_657, UInt<1>("h00")) @[dbg.scala 441:46] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 441:84] + node _T_662 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 441:115] + node _T_663 = mul(UInt<4>("h08"), _T_662) @[dbg.scala 441:99] + node _T_664 = dshr(_T_661, _T_663) @[dbg.scala 441:92] + node _T_665 = and(_T_664, UInt<64>("h0ff")) @[dbg.scala 441:123] + node _T_666 = and(_T_660, _T_665) @[dbg.scala 441:59] + node _T_667 = bits(sbcs_reg, 19, 17) @[dbg.scala 442:23] + node _T_668 = eq(_T_667, UInt<1>("h01")) @[dbg.scala 442:32] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 442:70] + node _T_672 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 442:102] + node _T_673 = mul(UInt<5>("h010"), _T_672) @[dbg.scala 442:86] + node _T_674 = dshr(_T_671, _T_673) @[dbg.scala 442:78] + node _T_675 = and(_T_674, UInt<64>("h0ffff")) @[dbg.scala 442:110] + node _T_676 = and(_T_670, _T_675) @[dbg.scala 442:45] + node _T_677 = or(_T_666, _T_676) @[dbg.scala 441:140] + node _T_678 = bits(sbcs_reg, 19, 17) @[dbg.scala 443:23] + node _T_679 = eq(_T_678, UInt<2>("h02")) @[dbg.scala 443:32] + node _T_680 = bits(_T_679, 0, 0) @[Bitwise.scala 72:15] + node _T_681 = mux(_T_680, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_682 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 443:70] + node _T_683 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 443:102] + node _T_684 = mul(UInt<6>("h020"), _T_683) @[dbg.scala 443:86] + node _T_685 = dshr(_T_682, _T_684) @[dbg.scala 443:78] + node _T_686 = and(_T_685, UInt<64>("h0ffffffff")) @[dbg.scala 443:107] + node _T_687 = and(_T_681, _T_686) @[dbg.scala 443:45] + node _T_688 = or(_T_677, _T_687) @[dbg.scala 442:129] + node _T_689 = bits(sbcs_reg, 19, 17) @[dbg.scala 444:23] + node _T_690 = eq(_T_689, UInt<2>("h03")) @[dbg.scala 444:32] + node _T_691 = bits(_T_690, 0, 0) @[Bitwise.scala 72:15] + node _T_692 = mux(_T_691, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_693 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 444:68] + node _T_694 = and(_T_692, _T_693) @[dbg.scala 444:45] + node _T_695 = or(_T_688, _T_694) @[dbg.scala 443:131] + sb_bus_rdata <= _T_695 @[dbg.scala 441:16] io.dbg_dma.dbg_ib.dbg_cmd_addr <= io.dbg_dec.dbg_ib.dbg_cmd_addr @[dbg.scala 447:39] io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[dbg.scala 448:39] io.dbg_dma.dbg_ib.dbg_cmd_valid <= io.dbg_dec.dbg_ib.dbg_cmd_valid @[dbg.scala 449:39] diff --git a/dbg.v b/dbg.v index 6a4fd9a3..bcfa40f7 100644 --- a/dbg.v +++ b/dbg.v @@ -177,52 +177,52 @@ module dbg( wire _T_26 = _T_20 & _T_25; // @[dbg.scala 102:118] wire sbcs_sbbusyerror_wren = _T_18 | _T_26; // @[dbg.scala 102:66] wire sbcs_sbbusyerror_din = ~_T_18; // @[dbg.scala 105:31] - wire _T_29 = ~dbg_dm_rst_l; // @[dbg.scala 106:54] - wire _T_30 = ~dbg_dm_rst_l; // @[dbg.scala 106:81] + wire _T_29 = io_dbg_rst_l & _T_9; // @[dbg.scala 106:80] reg temp_sbcs_22; // @[Reg.scala 27:20] reg temp_sbcs_21; // @[Reg.scala 27:20] reg temp_sbcs_20; // @[Reg.scala 27:20] reg [4:0] temp_sbcs_19_15; // @[Reg.scala 27:20] + wire _T_36 = ~dbg_dm_rst_l; // @[dbg.scala 122:84] reg [2:0] temp_sbcs_14_12; // @[Reg.scala 27:20] - wire [19:0] _T_44 = {temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58] - wire [11:0] _T_48 = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20}; // @[Cat.scala 29:58] - wire _T_51 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 127:42] - wire _T_53 = _T_51 & sbaddress0_reg[0]; // @[dbg.scala 127:56] - wire _T_55 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 128:23] - wire _T_57 = |sbaddress0_reg[1:0]; // @[dbg.scala 128:60] - wire _T_58 = _T_55 & _T_57; // @[dbg.scala 128:37] - wire _T_59 = _T_53 | _T_58; // @[dbg.scala 127:76] - wire _T_61 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 129:23] - wire _T_63 = |sbaddress0_reg[2:0]; // @[dbg.scala 129:60] - wire _T_64 = _T_61 & _T_63; // @[dbg.scala 129:37] - wire sbcs_unaligned = _T_59 | _T_64; // @[dbg.scala 128:64] + wire [19:0] _T_40 = {temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58] + wire [11:0] _T_44 = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20}; // @[Cat.scala 29:58] + wire _T_47 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 127:42] + wire _T_49 = _T_47 & sbaddress0_reg[0]; // @[dbg.scala 127:61] + wire _T_51 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 128:23] + wire _T_53 = |sbaddress0_reg[1:0]; // @[dbg.scala 128:65] + wire _T_54 = _T_51 & _T_53; // @[dbg.scala 128:42] + wire _T_55 = _T_49 | _T_54; // @[dbg.scala 127:81] + wire _T_57 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 129:23] + wire _T_59 = |sbaddress0_reg[2:0]; // @[dbg.scala 129:65] + wire _T_60 = _T_57 & _T_59; // @[dbg.scala 129:42] + wire sbcs_unaligned = _T_55 | _T_60; // @[dbg.scala 128:69] wire sbcs_illegal_size = sbcs_reg[19]; // @[dbg.scala 131:35] - wire _T_66 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 132:51] - wire [3:0] _T_68 = _T_66 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_69 = _T_68 & 4'h1; // @[dbg.scala 132:64] - wire [3:0] _T_73 = _T_51 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_74 = _T_73 & 4'h2; // @[dbg.scala 132:117] - wire [3:0] _T_75 = _T_69 | _T_74; // @[dbg.scala 132:76] - wire [3:0] _T_79 = _T_55 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_80 = _T_79 & 4'h4; // @[dbg.scala 133:44] - wire [3:0] _T_81 = _T_75 | _T_80; // @[dbg.scala 132:129] - wire [3:0] _T_85 = _T_61 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_86 = _T_85 & 4'h8; // @[dbg.scala 133:97] - wire [3:0] sbaddress0_incr = _T_81 | _T_86; // @[dbg.scala 133:56] - wire _T_87 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 135:41] - wire sbdata0_reg_wren0 = _T_87 & _T_22; // @[dbg.scala 135:60] - wire _T_89 = sb_state == 4'h7; // @[dbg.scala 136:37] - wire _T_90 = _T_89 & sb_state_en; // @[dbg.scala 136:60] - wire _T_91 = ~sbcs_sberror_wren; // @[dbg.scala 136:76] - wire sbdata0_reg_wren1 = _T_90 & _T_91; // @[dbg.scala 136:74] - wire sbdata1_reg_wren0 = _T_87 & _T_24; // @[dbg.scala 138:60] - wire [31:0] _T_98 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_99 = _T_98 & io_dmi_reg_wdata; // @[dbg.scala 141:49] - wire [31:0] _T_101 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_103 = _T_101 & sb_bus_rdata[31:0]; // @[dbg.scala 142:33] - wire [31:0] _T_105 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_106 = _T_105 & io_dmi_reg_wdata; // @[dbg.scala 144:49] - wire [31:0] _T_110 = _T_101 & sb_bus_rdata[63:32]; // @[dbg.scala 145:33] + wire _T_62 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 132:51] + wire [3:0] _T_64 = _T_62 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_65 = _T_64 & 4'h1; // @[dbg.scala 132:64] + wire [3:0] _T_69 = _T_47 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_70 = _T_69 & 4'h2; // @[dbg.scala 132:122] + wire [3:0] _T_71 = _T_65 | _T_70; // @[dbg.scala 132:81] + wire [3:0] _T_75 = _T_51 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_76 = _T_75 & 4'h4; // @[dbg.scala 133:44] + wire [3:0] _T_77 = _T_71 | _T_76; // @[dbg.scala 132:139] + wire [3:0] _T_81 = _T_57 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_82 = _T_81 & 4'h8; // @[dbg.scala 133:102] + wire [3:0] sbaddress0_incr = _T_77 | _T_82; // @[dbg.scala 133:61] + wire _T_83 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 135:41] + wire sbdata0_reg_wren0 = _T_83 & _T_22; // @[dbg.scala 135:60] + wire _T_85 = sb_state == 4'h7; // @[dbg.scala 136:37] + wire _T_86 = _T_85 & sb_state_en; // @[dbg.scala 136:60] + wire _T_87 = ~sbcs_sberror_wren; // @[dbg.scala 136:76] + wire sbdata0_reg_wren1 = _T_86 & _T_87; // @[dbg.scala 136:74] + wire sbdata1_reg_wren0 = _T_83 & _T_24; // @[dbg.scala 138:60] + wire [31:0] _T_94 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_95 = _T_94 & io_dmi_reg_wdata; // @[dbg.scala 141:49] + wire [31:0] _T_97 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_99 = _T_97 & sb_bus_rdata[31:0]; // @[dbg.scala 142:33] + wire [31:0] _T_101 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_102 = _T_101 & io_dmi_reg_wdata; // @[dbg.scala 144:49] + wire [31:0] _T_106 = _T_97 & sb_bus_rdata[63:32]; // @[dbg.scala 145:33] wire rvclkhdr_2_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_2_io_clk; // @[lib.scala 352:23] wire rvclkhdr_2_io_en; // @[lib.scala 352:23] @@ -233,385 +233,383 @@ module dbg( wire rvclkhdr_3_io_en; // @[lib.scala 352:23] wire rvclkhdr_3_io_scan_mode; // @[lib.scala 352:23] reg [31:0] sbdata1_reg; // @[lib.scala 358:16] - wire sbaddress0_reg_wren0 = _T_87 & _T_21; // @[dbg.scala 155:63] - wire [31:0] _T_118 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_119 = _T_118 & io_dmi_reg_wdata; // @[dbg.scala 157:59] - wire [31:0] _T_121 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_122 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58] - wire [31:0] _T_124 = sbaddress0_reg + _T_122; // @[dbg.scala 158:54] - wire [31:0] _T_125 = _T_121 & _T_124; // @[dbg.scala 158:36] + wire sbaddress0_reg_wren0 = _T_83 & _T_21; // @[dbg.scala 155:63] + wire [31:0] _T_112 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_113 = _T_112 & io_dmi_reg_wdata; // @[dbg.scala 157:59] + wire [31:0] _T_115 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_116 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58] + wire [31:0] _T_118 = sbaddress0_reg + _T_116; // @[dbg.scala 158:54] + wire [31:0] _T_119 = _T_115 & _T_118; // @[dbg.scala 158:36] wire rvclkhdr_4_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_4_io_clk; // @[lib.scala 352:23] wire rvclkhdr_4_io_en; // @[lib.scala 352:23] wire rvclkhdr_4_io_scan_mode; // @[lib.scala 352:23] - reg [31:0] _T_128; // @[lib.scala 358:16] + reg [31:0] _T_121; // @[lib.scala 358:16] wire sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 163:94] - wire _T_133 = ~io_dmi_reg_wr_en; // @[dbg.scala 164:45] - wire _T_134 = io_dmi_reg_en & _T_133; // @[dbg.scala 164:43] - wire _T_136 = _T_134 & _T_22; // @[dbg.scala 164:63] - wire sbreadondata_access = _T_136 & sbcs_reg[15]; // @[dbg.scala 164:95] - wire _T_140 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 166:41] - wire _T_141 = _T_140 & io_dmi_reg_en; // @[dbg.scala 166:54] - wire dmcontrol_wren = _T_141 & io_dmi_reg_wr_en; // @[dbg.scala 166:70] - wire [3:0] _T_148 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58] + wire _T_126 = ~io_dmi_reg_wr_en; // @[dbg.scala 164:45] + wire _T_127 = io_dmi_reg_en & _T_126; // @[dbg.scala 164:43] + wire _T_129 = _T_127 & _T_22; // @[dbg.scala 164:63] + wire sbreadondata_access = _T_129 & sbcs_reg[15]; // @[dbg.scala 164:95] + wire _T_133 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 166:41] + wire _T_134 = _T_133 & io_dmi_reg_en; // @[dbg.scala 166:54] + wire dmcontrol_wren = _T_134 & io_dmi_reg_wr_en; // @[dbg.scala 166:70] + wire [3:0] _T_140 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58] reg [3:0] dm_temp; // @[Reg.scala 27:20] reg dm_temp_0; // @[Reg.scala 27:20] - wire [27:0] _T_155 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58] - wire [3:0] _T_157 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58] + wire [27:0] _T_147 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58] + wire [3:0] _T_149 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58] reg dmcontrol_wren_Q; // @[dbg.scala 181:12] - wire [1:0] _T_161 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_163 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_165 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_167 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_169 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [11:0] _T_173 = {_T_167,_T_169,1'h1,7'h2}; // @[Cat.scala 29:58] - wire [19:0] _T_177 = {12'h0,_T_161,_T_163,2'h0,_T_165}; // @[Cat.scala 29:58] - wire _T_179 = dbg_state == 3'h6; // @[dbg.scala 186:44] - wire _T_180 = _T_179 & io_dec_tlu_resume_ack; // @[dbg.scala 186:66] - wire _T_182 = ~dmcontrol_reg[30]; // @[dbg.scala 186:113] - wire _T_183 = dmstatus_resumeack & _T_182; // @[dbg.scala 186:111] - wire dmstatus_resumeack_wren = _T_180 | _T_183; // @[dbg.scala 186:90] - wire _T_187 = _T_140 & io_dmi_reg_wdata[1]; // @[dbg.scala 188:63] - wire _T_188 = _T_187 & io_dmi_reg_en; // @[dbg.scala 188:85] - wire dmstatus_havereset_wren = _T_188 & io_dmi_reg_wr_en; // @[dbg.scala 188:101] - wire _T_191 = _T_140 & io_dmi_reg_wdata[28]; // @[dbg.scala 189:62] - wire _T_192 = _T_191 & io_dmi_reg_en; // @[dbg.scala 189:85] - wire dmstatus_havereset_rst = _T_192 & io_dmi_reg_wr_en; // @[dbg.scala 189:101] - wire _T_194 = ~reset; // @[dbg.scala 191:43] - wire _T_197 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 192:42] - reg _T_201; // @[Reg.scala 27:20] - wire _T_204 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 198:37] - reg _T_206; // @[dbg.scala 198:12] - wire _T_209 = ~dmstatus_havereset_rst; // @[dbg.scala 202:15] - reg _T_210; // @[Reg.scala 27:20] + wire [1:0] _T_152 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_154 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_156 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_158 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_160 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [11:0] _T_164 = {_T_158,_T_160,1'h1,7'h2}; // @[Cat.scala 29:58] + wire [19:0] _T_168 = {12'h0,_T_152,_T_154,2'h0,_T_156}; // @[Cat.scala 29:58] + wire _T_170 = dbg_state == 3'h6; // @[dbg.scala 186:44] + wire _T_171 = _T_170 & io_dec_tlu_resume_ack; // @[dbg.scala 186:66] + wire _T_173 = ~dmcontrol_reg[30]; // @[dbg.scala 186:113] + wire _T_174 = dmstatus_resumeack & _T_173; // @[dbg.scala 186:111] + wire dmstatus_resumeack_wren = _T_171 | _T_174; // @[dbg.scala 186:90] + wire _T_178 = _T_133 & io_dmi_reg_wdata[1]; // @[dbg.scala 188:63] + wire _T_179 = _T_178 & io_dmi_reg_en; // @[dbg.scala 188:85] + wire dmstatus_havereset_wren = _T_179 & io_dmi_reg_wr_en; // @[dbg.scala 188:101] + wire _T_182 = _T_133 & io_dmi_reg_wdata[28]; // @[dbg.scala 189:62] + wire _T_183 = _T_182 & io_dmi_reg_en; // @[dbg.scala 189:85] + wire dmstatus_havereset_rst = _T_183 & io_dmi_reg_wr_en; // @[dbg.scala 189:101] + wire _T_185 = ~reset; // @[dbg.scala 191:43] + wire _T_188 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 192:42] + reg _T_191; // @[Reg.scala 27:20] + wire _T_193 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 198:37] + reg _T_195; // @[dbg.scala 198:12] + wire _T_197 = dmstatus_havereset_wren | dmstatus_havereset; // @[dbg.scala 202:16] + wire _T_198 = ~dmstatus_havereset_rst; // @[dbg.scala 202:72] + reg _T_200; // @[dbg.scala 202:12] wire [31:0] haltsum0_reg = {31'h0,dmstatus_halted}; // @[Cat.scala 29:58] wire [31:0] abstractcs_reg; - wire _T_212 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 208:50] - wire _T_213 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 208:106] - wire _T_214 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 208:138] - wire _T_215 = _T_213 | _T_214; // @[dbg.scala 208:119] - wire _T_216 = io_dmi_reg_wr_en & _T_215; // @[dbg.scala 208:86] - wire _T_217 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 208:171] - wire _T_218 = _T_216 | _T_217; // @[dbg.scala 208:152] - wire abstractcs_error_sel0 = _T_212 & _T_218; // @[dbg.scala 208:66] - wire _T_221 = _T_87 & _T_214; // @[dbg.scala 209:64] - wire _T_223 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 209:126] - wire _T_225 = io_dmi_reg_wdata[31:24] == 8'h2; // @[dbg.scala 209:163] - wire _T_226 = _T_223 | _T_225; // @[dbg.scala 209:135] - wire _T_227 = ~_T_226; // @[dbg.scala 209:98] - wire abstractcs_error_sel1 = _T_221 & _T_227; // @[dbg.scala 209:96] + wire _T_202 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 208:50] + wire _T_203 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 208:106] + wire _T_204 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 208:138] + wire _T_205 = _T_203 | _T_204; // @[dbg.scala 208:119] + wire _T_206 = io_dmi_reg_wr_en & _T_205; // @[dbg.scala 208:86] + wire _T_207 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 208:171] + wire _T_208 = _T_206 | _T_207; // @[dbg.scala 208:152] + wire abstractcs_error_sel0 = _T_202 & _T_208; // @[dbg.scala 208:66] + wire _T_211 = _T_83 & _T_204; // @[dbg.scala 209:64] + wire _T_213 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 209:126] + wire _T_215 = io_dmi_reg_wdata[31:24] == 8'h2; // @[dbg.scala 209:163] + wire _T_216 = _T_213 | _T_215; // @[dbg.scala 209:135] + wire _T_217 = ~_T_216; // @[dbg.scala 209:98] + wire abstractcs_error_sel1 = _T_211 & _T_217; // @[dbg.scala 209:96] wire abstractcs_error_sel2 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[dbg.scala 210:52] - wire _T_232 = ~dmstatus_reg[9]; // @[dbg.scala 211:98] - wire abstractcs_error_sel3 = _T_221 & _T_232; // @[dbg.scala 211:96] - wire _T_234 = _T_214 & io_dmi_reg_en; // @[dbg.scala 212:61] - wire _T_235 = _T_234 & io_dmi_reg_wr_en; // @[dbg.scala 212:77] - wire _T_237 = io_dmi_reg_wdata[22:20] != 3'h2; // @[dbg.scala 213:32] - wire _T_241 = |data1_reg[1:0]; // @[dbg.scala 213:106] - wire _T_242 = _T_225 & _T_241; // @[dbg.scala 213:87] - wire _T_243 = _T_237 | _T_242; // @[dbg.scala 213:46] - wire abstractcs_error_sel4 = _T_235 & _T_243; // @[dbg.scala 212:96] - wire _T_245 = _T_213 & io_dmi_reg_en; // @[dbg.scala 215:61] - wire abstractcs_error_sel5 = _T_245 & io_dmi_reg_wr_en; // @[dbg.scala 215:77] - wire _T_246 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[dbg.scala 216:54] - wire _T_247 = _T_246 | abstractcs_error_sel2; // @[dbg.scala 216:78] - wire _T_248 = _T_247 | abstractcs_error_sel3; // @[dbg.scala 216:102] - wire _T_249 = _T_248 | abstractcs_error_sel4; // @[dbg.scala 216:126] - wire abstractcs_error_selor = _T_249 | abstractcs_error_sel5; // @[dbg.scala 216:150] - wire [2:0] _T_251 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_252 = _T_251 & 3'h1; // @[dbg.scala 217:62] - wire [2:0] _T_254 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_255 = _T_254 & 3'h2; // @[dbg.scala 218:37] - wire [2:0] _T_256 = _T_252 | _T_255; // @[dbg.scala 217:74] - wire [2:0] _T_258 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_259 = _T_258 & 3'h3; // @[dbg.scala 219:37] - wire [2:0] _T_260 = _T_256 | _T_259; // @[dbg.scala 218:49] - wire [2:0] _T_262 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_263 = _T_262 & 3'h4; // @[dbg.scala 220:37] - wire [2:0] _T_264 = _T_260 | _T_263; // @[dbg.scala 219:49] - wire [2:0] _T_266 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_268 = _T_264 | _T_266; // @[dbg.scala 220:49] - wire [2:0] _T_270 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_272 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 222:40] - wire [2:0] _T_273 = _T_270 & _T_272; // @[dbg.scala 222:37] - wire [2:0] _T_275 = _T_273 & abstractcs_reg[10:8]; // @[dbg.scala 222:75] - wire [2:0] _T_276 = _T_268 | _T_275; // @[dbg.scala 221:49] - wire _T_277 = ~abstractcs_error_selor; // @[dbg.scala 223:15] - wire [2:0] _T_279 = _T_277 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_281 = _T_279 & abstractcs_reg[10:8]; // @[dbg.scala 223:50] + wire _T_222 = ~dmstatus_reg[9]; // @[dbg.scala 211:98] + wire abstractcs_error_sel3 = _T_211 & _T_222; // @[dbg.scala 211:96] + wire _T_224 = _T_204 & io_dmi_reg_en; // @[dbg.scala 212:61] + wire _T_225 = _T_224 & io_dmi_reg_wr_en; // @[dbg.scala 212:77] + wire _T_227 = io_dmi_reg_wdata[22:20] != 3'h2; // @[dbg.scala 213:32] + wire _T_231 = |data1_reg[1:0]; // @[dbg.scala 213:111] + wire _T_232 = _T_215 & _T_231; // @[dbg.scala 213:92] + wire _T_233 = _T_227 | _T_232; // @[dbg.scala 213:51] + wire abstractcs_error_sel4 = _T_225 & _T_233; // @[dbg.scala 212:96] + wire _T_235 = _T_203 & io_dmi_reg_en; // @[dbg.scala 215:61] + wire abstractcs_error_sel5 = _T_235 & io_dmi_reg_wr_en; // @[dbg.scala 215:77] + wire _T_236 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[dbg.scala 216:54] + wire _T_237 = _T_236 | abstractcs_error_sel2; // @[dbg.scala 216:78] + wire _T_238 = _T_237 | abstractcs_error_sel3; // @[dbg.scala 216:102] + wire _T_239 = _T_238 | abstractcs_error_sel4; // @[dbg.scala 216:126] + wire abstractcs_error_selor = _T_239 | abstractcs_error_sel5; // @[dbg.scala 216:150] + wire [2:0] _T_241 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_242 = _T_241 & 3'h1; // @[dbg.scala 217:62] + wire [2:0] _T_244 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_245 = _T_244 & 3'h2; // @[dbg.scala 218:37] + wire [2:0] _T_246 = _T_242 | _T_245; // @[dbg.scala 217:79] + wire [2:0] _T_248 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_249 = _T_248 & 3'h3; // @[dbg.scala 219:37] + wire [2:0] _T_250 = _T_246 | _T_249; // @[dbg.scala 218:54] + wire [2:0] _T_252 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_253 = _T_252 & 3'h4; // @[dbg.scala 220:37] + wire [2:0] _T_254 = _T_250 | _T_253; // @[dbg.scala 219:54] + wire [2:0] _T_256 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_258 = _T_254 | _T_256; // @[dbg.scala 220:54] + wire [2:0] _T_260 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_262 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 222:40] + wire [2:0] _T_263 = _T_260 & _T_262; // @[dbg.scala 222:37] + wire [2:0] _T_265 = _T_263 & abstractcs_reg[10:8]; // @[dbg.scala 222:75] + wire [2:0] _T_266 = _T_258 | _T_265; // @[dbg.scala 221:54] + wire _T_267 = ~abstractcs_error_selor; // @[dbg.scala 223:15] + wire [2:0] _T_269 = _T_267 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_271 = _T_269 & abstractcs_reg[10:8]; // @[dbg.scala 223:50] reg abs_temp_12; // @[Reg.scala 27:20] reg [2:0] abs_temp_10_8; // @[dbg.scala 230:12] - wire [10:0] _T_287 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58] - wire [20:0] _T_289 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58] - wire _T_294 = dbg_state == 3'h2; // @[dbg.scala 235:100] - wire command_wren = _T_235 & _T_294; // @[dbg.scala 235:87] - wire [19:0] _T_298 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] - wire [11:0] _T_300 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58] + wire [10:0] _T_275 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58] + wire [20:0] _T_277 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58] + wire _T_282 = dbg_state == 3'h2; // @[dbg.scala 235:100] + wire command_wren = _T_225 & _T_282; // @[dbg.scala 235:87] + wire [19:0] _T_286 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] + wire [11:0] _T_288 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58] wire rvclkhdr_5_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_5_io_clk; // @[lib.scala 352:23] wire rvclkhdr_5_io_en; // @[lib.scala 352:23] wire rvclkhdr_5_io_scan_mode; // @[lib.scala 352:23] reg [31:0] command_reg; // @[lib.scala 358:16] - wire _T_305 = _T_87 & _T_217; // @[dbg.scala 241:58] - wire data0_reg_wren0 = _T_305 & _T_294; // @[dbg.scala 241:89] - wire _T_307 = dbg_state == 3'h4; // @[dbg.scala 242:59] - wire _T_308 = io_core_dbg_cmd_done & _T_307; // @[dbg.scala 242:46] - wire _T_310 = ~command_reg[16]; // @[dbg.scala 242:83] - wire data0_reg_wren1 = _T_308 & _T_310; // @[dbg.scala 242:81] - wire [31:0] _T_312 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_313 = _T_312 & io_dmi_reg_wdata; // @[dbg.scala 245:45] - wire [31:0] _T_315 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_316 = _T_315 & io_core_dbg_rddata; // @[dbg.scala 245:92] + wire _T_292 = _T_83 & _T_207; // @[dbg.scala 241:58] + wire data0_reg_wren0 = _T_292 & _T_282; // @[dbg.scala 241:89] + wire _T_294 = dbg_state == 3'h4; // @[dbg.scala 242:59] + wire _T_295 = io_core_dbg_cmd_done & _T_294; // @[dbg.scala 242:46] + wire _T_297 = ~command_reg[16]; // @[dbg.scala 242:83] + wire data0_reg_wren1 = _T_295 & _T_297; // @[dbg.scala 242:81] + wire [31:0] _T_299 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_300 = _T_299 & io_dmi_reg_wdata; // @[dbg.scala 245:45] + wire [31:0] _T_302 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_303 = _T_302 & io_core_dbg_rddata; // @[dbg.scala 245:92] wire rvclkhdr_6_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_6_io_clk; // @[lib.scala 352:23] wire rvclkhdr_6_io_en; // @[lib.scala 352:23] wire rvclkhdr_6_io_scan_mode; // @[lib.scala 352:23] reg [31:0] data0_reg; // @[lib.scala 358:16] - wire _T_320 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 250:77] - wire _T_321 = _T_87 & _T_320; // @[dbg.scala 250:58] - wire data1_reg_wren = _T_321 & _T_294; // @[dbg.scala 250:89] - wire [31:0] _T_324 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire _T_306 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 250:77] + wire _T_307 = _T_83 & _T_306; // @[dbg.scala 250:58] + wire data1_reg_wren = _T_307 & _T_282; // @[dbg.scala 250:89] + wire [31:0] _T_310 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire rvclkhdr_7_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_7_io_clk; // @[lib.scala 352:23] wire rvclkhdr_7_io_en; // @[lib.scala 352:23] wire rvclkhdr_7_io_scan_mode; // @[lib.scala 352:23] - reg [31:0] _T_327; // @[lib.scala 358:16] + reg [31:0] _T_312; // @[lib.scala 358:16] wire [2:0] dbg_nxtstate; - wire _T_328 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] - wire _T_330 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 265:43] - wire [2:0] _T_331 = _T_330 ? 3'h2 : 3'h1; // @[dbg.scala 265:26] - wire _T_333 = ~io_dec_tlu_debug_mode; // @[dbg.scala 266:45] - wire _T_334 = dmcontrol_reg[31] & _T_333; // @[dbg.scala 266:43] - wire _T_336 = _T_334 | dmstatus_reg[9]; // @[dbg.scala 266:69] - wire _T_337 = _T_336 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 266:87] - wire _T_340 = _T_337 & _T_11; // @[dbg.scala 266:117] - wire _T_344 = dmcontrol_reg[31] & _T_11; // @[dbg.scala 267:45] - wire _T_346 = 3'h1 == dbg_state; // @[Conditional.scala 37:30] - wire [2:0] _T_348 = dmcontrol_reg[1] ? 3'h0 : 3'h2; // @[dbg.scala 270:26] - wire _T_351 = dmstatus_reg[9] | dmcontrol_reg[1]; // @[dbg.scala 271:39] - wire _T_353 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[dbg.scala 272:44] - wire _T_356 = _T_353 & _T_11; // @[dbg.scala 272:64] - wire _T_358 = 3'h2 == dbg_state; // @[Conditional.scala 37:30] - wire _T_362 = dmstatus_reg[9] & _T_11; // @[dbg.scala 275:43] - wire _T_365 = ~dmcontrol_reg[3]; // @[dbg.scala 276:33] - wire _T_366 = dmcontrol_reg[30] & _T_365; // @[dbg.scala 276:31] - wire [2:0] _T_367 = _T_366 ? 3'h6 : 3'h3; // @[dbg.scala 276:12] - wire [2:0] _T_369 = dmcontrol_reg[31] ? 3'h1 : 3'h0; // @[dbg.scala 277:12] - wire [2:0] _T_370 = _T_362 ? _T_367 : _T_369; // @[dbg.scala 275:26] - wire _T_373 = dmstatus_reg[9] & dmcontrol_reg[30]; // @[dbg.scala 278:39] - wire _T_375 = ~dmcontrol_reg[31]; // @[dbg.scala 278:61] - wire _T_376 = _T_373 & _T_375; // @[dbg.scala 278:59] - wire _T_377 = _T_376 & dmcontrol_wren_Q; // @[dbg.scala 278:80] - wire _T_378 = _T_377 | command_wren; // @[dbg.scala 278:99] - wire _T_380 = _T_378 | dmcontrol_reg[1]; // @[dbg.scala 278:114] - wire _T_383 = ~_T_330; // @[dbg.scala 279:28] - wire _T_384 = _T_380 | _T_383; // @[dbg.scala 279:26] - wire _T_385 = dbg_nxtstate == 3'h3; // @[dbg.scala 280:60] - wire _T_386 = dbg_state_en & _T_385; // @[dbg.scala 280:44] - wire _T_387 = dbg_nxtstate == 3'h6; // @[dbg.scala 282:58] - wire _T_388 = dbg_state_en & _T_387; // @[dbg.scala 282:42] - wire _T_396 = 3'h3 == dbg_state; // @[Conditional.scala 37:30] - wire _T_399 = |abstractcs_reg[10:8]; // @[dbg.scala 286:85] - wire [2:0] _T_400 = _T_399 ? 3'h5 : 3'h4; // @[dbg.scala 286:62] - wire [2:0] _T_401 = dmcontrol_reg[1] ? 3'h0 : _T_400; // @[dbg.scala 286:26] - wire _T_404 = io_dbg_dec_dbg_ib_dbg_cmd_valid | _T_399; // @[dbg.scala 287:55] - wire _T_406 = _T_404 | dmcontrol_reg[1]; // @[dbg.scala 287:83] - wire _T_413 = 3'h4 == dbg_state; // @[Conditional.scala 37:30] - wire [2:0] _T_415 = dmcontrol_reg[1] ? 3'h0 : 3'h5; // @[dbg.scala 291:26] - wire _T_417 = io_core_dbg_cmd_done | dmcontrol_reg[1]; // @[dbg.scala 292:44] - wire _T_424 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] - wire _T_433 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] - wire _T_436 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 304:40] - wire _GEN_11 = _T_433 & _T_436; // @[Conditional.scala 39:67] - wire _GEN_12 = _T_433 & _T_356; // @[Conditional.scala 39:67] - wire [2:0] _GEN_13 = _T_424 ? _T_348 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_14 = _T_424 | _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_15 = _T_424 & dbg_state_en; // @[Conditional.scala 39:67] - wire _GEN_17 = _T_424 ? _T_356 : _GEN_12; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_413 ? _T_415 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_413 ? _T_417 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_413 ? _T_356 : _GEN_17; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_413 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_396 ? _T_401 : _GEN_18; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_396 ? _T_406 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_25 = _T_396 ? _T_356 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_396 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_28 = _T_358 ? _T_370 : _GEN_23; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_358 ? _T_384 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_358 ? _T_386 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_358 & _T_388; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_358 ? _T_356 : _GEN_25; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_346 ? _T_348 : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_346 ? _T_351 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_346 ? _T_356 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_37 = _T_346 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_346 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire [31:0] _T_445 = _T_217 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_446 = _T_445 & data0_reg; // @[dbg.scala 308:71] - wire [31:0] _T_449 = _T_320 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_450 = _T_449 & data1_reg; // @[dbg.scala 308:122] - wire [31:0] _T_451 = _T_446 | _T_450; // @[dbg.scala 308:83] - wire [31:0] _T_454 = _T_140 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_455 = _T_454 & dmcontrol_reg; // @[dbg.scala 309:43] - wire [31:0] _T_456 = _T_451 | _T_455; // @[dbg.scala 308:134] - wire _T_457 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 309:86] + wire _T_313 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] + wire _T_315 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 265:43] + wire [2:0] _T_316 = _T_315 ? 3'h2 : 3'h1; // @[dbg.scala 265:26] + wire _T_318 = ~io_dec_tlu_debug_mode; // @[dbg.scala 266:45] + wire _T_319 = dmcontrol_reg[31] & _T_318; // @[dbg.scala 266:43] + wire _T_321 = _T_319 | dmstatus_reg[9]; // @[dbg.scala 266:69] + wire _T_322 = _T_321 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 266:87] + wire _T_325 = _T_322 & _T_11; // @[dbg.scala 266:117] + wire _T_329 = dmcontrol_reg[31] & _T_11; // @[dbg.scala 267:45] + wire _T_331 = 3'h1 == dbg_state; // @[Conditional.scala 37:30] + wire [2:0] _T_333 = dmcontrol_reg[1] ? 3'h0 : 3'h2; // @[dbg.scala 270:26] + wire _T_336 = dmstatus_reg[9] | dmcontrol_reg[1]; // @[dbg.scala 271:39] + wire _T_338 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[dbg.scala 272:44] + wire _T_341 = _T_338 & _T_11; // @[dbg.scala 272:64] + wire _T_343 = 3'h2 == dbg_state; // @[Conditional.scala 37:30] + wire _T_347 = dmstatus_reg[9] & _T_11; // @[dbg.scala 275:43] + wire _T_350 = ~dmcontrol_reg[31]; // @[dbg.scala 276:33] + wire _T_351 = dmcontrol_reg[30] & _T_350; // @[dbg.scala 276:31] + wire [2:0] _T_352 = _T_351 ? 3'h6 : 3'h3; // @[dbg.scala 276:12] + wire [2:0] _T_354 = dmcontrol_reg[31] ? 3'h1 : 3'h0; // @[dbg.scala 277:12] + wire [2:0] _T_355 = _T_347 ? _T_352 : _T_354; // @[dbg.scala 275:26] + wire _T_358 = dmstatus_reg[9] & dmcontrol_reg[30]; // @[dbg.scala 278:39] + wire _T_361 = _T_358 & _T_350; // @[dbg.scala 278:59] + wire _T_362 = _T_361 & dmcontrol_wren_Q; // @[dbg.scala 278:80] + wire _T_363 = _T_362 | command_wren; // @[dbg.scala 278:99] + wire _T_365 = _T_363 | dmcontrol_reg[1]; // @[dbg.scala 278:114] + wire _T_368 = ~_T_315; // @[dbg.scala 279:28] + wire _T_369 = _T_365 | _T_368; // @[dbg.scala 279:26] + wire _T_370 = dbg_nxtstate == 3'h3; // @[dbg.scala 280:60] + wire _T_371 = dbg_state_en & _T_370; // @[dbg.scala 280:44] + wire _T_372 = dbg_nxtstate == 3'h6; // @[dbg.scala 282:58] + wire _T_373 = dbg_state_en & _T_372; // @[dbg.scala 282:42] + wire _T_381 = 3'h3 == dbg_state; // @[Conditional.scala 37:30] + wire _T_384 = |abstractcs_reg[10:8]; // @[dbg.scala 286:85] + wire [2:0] _T_385 = _T_384 ? 3'h5 : 3'h4; // @[dbg.scala 286:62] + wire [2:0] _T_386 = dmcontrol_reg[1] ? 3'h0 : _T_385; // @[dbg.scala 286:26] + wire _T_389 = io_dbg_dec_dbg_ib_dbg_cmd_valid | _T_384; // @[dbg.scala 287:55] + wire _T_391 = _T_389 | dmcontrol_reg[1]; // @[dbg.scala 287:83] + wire _T_398 = 3'h4 == dbg_state; // @[Conditional.scala 37:30] + wire [2:0] _T_400 = dmcontrol_reg[1] ? 3'h0 : 3'h5; // @[dbg.scala 291:26] + wire _T_402 = io_core_dbg_cmd_done | dmcontrol_reg[1]; // @[dbg.scala 292:44] + wire _T_409 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] + wire _T_418 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] + wire _T_421 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 304:40] + wire _GEN_10 = _T_418 & _T_421; // @[Conditional.scala 39:67] + wire _GEN_11 = _T_418 & _T_341; // @[Conditional.scala 39:67] + wire [2:0] _GEN_12 = _T_409 ? _T_333 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_13 = _T_409 | _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_14 = _T_409 & dbg_state_en; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_409 ? _T_341 : _GEN_11; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_398 ? _T_400 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_18 = _T_398 ? _T_402 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_398 ? _T_341 : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_398 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire [2:0] _GEN_22 = _T_381 ? _T_386 : _GEN_17; // @[Conditional.scala 39:67] + wire _GEN_23 = _T_381 ? _T_391 : _GEN_18; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_381 ? _T_341 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_25 = _T_381 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] + wire [2:0] _GEN_27 = _T_343 ? _T_355 : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_343 ? _T_369 : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_343 ? _T_371 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_343 & _T_373; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_343 ? _T_341 : _GEN_24; // @[Conditional.scala 39:67] + wire [2:0] _GEN_33 = _T_331 ? _T_333 : _GEN_27; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_331 ? _T_336 : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_331 ? _T_341 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_331 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_331 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] + wire [31:0] _T_430 = _T_207 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_431 = _T_430 & data0_reg; // @[dbg.scala 308:71] + wire [31:0] _T_434 = _T_306 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_435 = _T_434 & data1_reg; // @[dbg.scala 308:122] + wire [31:0] _T_436 = _T_431 | _T_435; // @[dbg.scala 308:83] + wire [31:0] _T_439 = _T_133 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_440 = _T_439 & dmcontrol_reg; // @[dbg.scala 309:43] + wire [31:0] _T_441 = _T_436 | _T_440; // @[dbg.scala 308:134] + wire _T_442 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 309:86] + wire [31:0] _T_444 = _T_442 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_445 = _T_444 & dmstatus_reg; // @[dbg.scala 309:99] + wire [31:0] _T_446 = _T_441 | _T_445; // @[dbg.scala 309:59] + wire [31:0] _T_449 = _T_203 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & abstractcs_reg; // @[dbg.scala 310:43] + wire [31:0] _T_451 = _T_446 | _T_450; // @[dbg.scala 309:114] + wire [31:0] _T_454 = _T_204 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_455 = _T_454 & command_reg; // @[dbg.scala 310:100] + wire [31:0] _T_456 = _T_451 | _T_455; // @[dbg.scala 310:60] + wire _T_457 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 311:30] wire [31:0] _T_459 = _T_457 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_460 = _T_459 & dmstatus_reg; // @[dbg.scala 309:99] - wire [31:0] _T_461 = _T_456 | _T_460; // @[dbg.scala 309:59] - wire [31:0] _T_464 = _T_213 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_465 = _T_464 & abstractcs_reg; // @[dbg.scala 310:43] - wire [31:0] _T_466 = _T_461 | _T_465; // @[dbg.scala 309:114] - wire [31:0] _T_469 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_470 = _T_469 & command_reg; // @[dbg.scala 310:100] - wire [31:0] _T_471 = _T_466 | _T_470; // @[dbg.scala 310:60] - wire _T_472 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 311:30] - wire [31:0] _T_474 = _T_472 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_475 = _T_474 & haltsum0_reg; // @[dbg.scala 311:43] - wire [31:0] _T_476 = _T_471 | _T_475; // @[dbg.scala 310:114] - wire [31:0] _T_479 = _T_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_480 = _T_479 & sbcs_reg; // @[dbg.scala 311:98] - wire [31:0] _T_481 = _T_476 | _T_480; // @[dbg.scala 311:58] - wire [31:0] _T_484 = _T_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_485 = _T_484 & sbaddress0_reg; // @[dbg.scala 312:43] - wire [31:0] _T_486 = _T_481 | _T_485; // @[dbg.scala 311:109] - wire [31:0] _T_489 = _T_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_490 = _T_489 & sbdata0_reg; // @[dbg.scala 312:100] - wire [31:0] _T_491 = _T_486 | _T_490; // @[dbg.scala 312:60] - wire [31:0] _T_494 = _T_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_495 = _T_494 & sbdata1_reg; // @[dbg.scala 313:43] - wire [31:0] dmi_reg_rdata_din = _T_491 | _T_495; // @[dbg.scala 312:114] - wire _T_498 = _T_29 & reset; // @[dbg.scala 315:87] - reg [2:0] _T_499; // @[Reg.scala 27:20] - reg [31:0] _T_502; // @[Reg.scala 27:20] - wire _T_504 = command_reg[31:24] == 8'h2; // @[dbg.scala 324:62] - wire [30:0] _T_506 = {data1_reg[31:2],1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_508 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58] - wire _T_511 = dbg_state == 3'h3; // @[dbg.scala 326:50] - wire _T_514 = ~_T_399; // @[dbg.scala 326:75] - wire _T_515 = _T_511 & _T_514; // @[dbg.scala 326:73] - wire _T_523 = command_reg[15:12] == 4'h0; // @[dbg.scala 328:117] - wire [1:0] _T_524 = {1'h0,_T_523}; // @[Cat.scala 29:58] - wire _T_535 = 4'h0 == sb_state; // @[Conditional.scala 37:30] - wire _T_537 = sbdata0_reg_wren0 | sbreadondata_access; // @[dbg.scala 343:39] - wire _T_538 = _T_537 | sbreadonaddr_access; // @[dbg.scala 343:61] - wire _T_540 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 346:65] - wire _T_541 = sbcs_wren & _T_540; // @[dbg.scala 346:38] - wire _T_543 = io_dmi_reg_wdata[14:12] == 3'h0; // @[dbg.scala 347:27] - wire [2:0] _GEN_116 = {{2'd0}, _T_543}; // @[dbg.scala 347:53] - wire [2:0] _T_545 = _GEN_116 & sbcs_reg[14:12]; // @[dbg.scala 347:53] - wire _T_546 = 4'h1 == sb_state; // @[Conditional.scala 37:30] - wire _T_547 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 350:41] - wire _T_549 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 351:40] - wire _T_550 = _T_549 | sbcs_illegal_size; // @[dbg.scala 351:57] - wire _T_553 = 4'h2 == sb_state; // @[Conditional.scala 37:30] - wire _T_560 = 4'h3 == sb_state; // @[Conditional.scala 37:30] - wire _T_561 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 363:38] - wire _T_562 = 4'h4 == sb_state; // @[Conditional.scala 37:30] - wire _T_563 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 366:48] - wire _T_566 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 367:45] - wire _T_567 = _T_566 & io_dbg_bus_clk_en; // @[dbg.scala 367:70] - wire _T_568 = 4'h5 == sb_state; // @[Conditional.scala 37:30] - wire _T_569 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 371:44] - wire _T_570 = 4'h6 == sb_state; // @[Conditional.scala 37:30] - wire _T_571 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 375:44] - wire _T_572 = 4'h7 == sb_state; // @[Conditional.scala 37:30] - wire _T_573 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 379:38] - wire _T_574 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 380:40] - wire _T_575 = 4'h8 == sb_state; // @[Conditional.scala 37:30] - wire _T_576 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39] - wire _T_578 = 4'h9 == sb_state; // @[Conditional.scala 37:30] - wire _GEN_51 = _T_578 & sbcs_reg[16]; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_575 ? _T_576 : _T_578; // @[Conditional.scala 39:67] - wire _GEN_54 = _T_575 & _T_574; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_575 ? 1'h0 : _T_578; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_575 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_572 ? _T_573 : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_572 ? _T_574 : _GEN_54; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_572 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_572 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_570 ? _T_571 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_68 = _T_570 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_570 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_570 ? 1'h0 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_568 ? _T_569 : _GEN_67; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_568 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67] - wire _GEN_77 = _T_568 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_568 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_562 ? _T_567 : _GEN_74; // @[Conditional.scala 39:67] - wire _GEN_82 = _T_562 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_562 ? 1'h0 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_562 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_560 ? _T_561 : _GEN_81; // @[Conditional.scala 39:67] - wire _GEN_89 = _T_560 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_560 ? 1'h0 : _GEN_84; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_560 ? 1'h0 : _GEN_86; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_553 ? _T_550 : _GEN_88; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_553 ? _T_547 : _GEN_89; // @[Conditional.scala 39:67] - wire _GEN_98 = _T_553 ? 1'h0 : _GEN_91; // @[Conditional.scala 39:67] - wire _GEN_100 = _T_553 ? 1'h0 : _GEN_93; // @[Conditional.scala 39:67] - wire _GEN_102 = _T_546 ? _T_550 : _GEN_95; // @[Conditional.scala 39:67] - wire _GEN_103 = _T_546 ? _T_547 : _GEN_96; // @[Conditional.scala 39:67] - wire _GEN_105 = _T_546 ? 1'h0 : _GEN_98; // @[Conditional.scala 39:67] - wire _GEN_107 = _T_546 ? 1'h0 : _GEN_100; // @[Conditional.scala 39:67] - reg [3:0] _T_582; // @[Reg.scala 27:20] - wire _T_589 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69] - wire _T_590 = sb_bus_rsp_read & _T_589; // @[dbg.scala 406:39] - wire _T_592 = |io_sb_axi_b_bits_resp; // @[dbg.scala 406:122] - wire _T_593 = sb_bus_rsp_write & _T_592; // @[dbg.scala 406:92] - wire _T_595 = sb_state == 4'h4; // @[dbg.scala 407:36] - wire _T_596 = sb_state == 4'h5; // @[dbg.scala 407:71] - wire _T_602 = sb_state == 4'h6; // @[dbg.scala 418:70] - wire [63:0] _T_608 = _T_66 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_612 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58] - wire [63:0] _T_613 = _T_608 & _T_612; // @[dbg.scala 419:65] - wire [63:0] _T_617 = _T_51 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_620 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58] - wire [63:0] _T_621 = _T_617 & _T_620; // @[dbg.scala 419:138] - wire [63:0] _T_622 = _T_613 | _T_621; // @[dbg.scala 419:96] - wire [63:0] _T_626 = _T_55 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_628 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58] - wire [63:0] _T_629 = _T_626 & _T_628; // @[dbg.scala 420:45] - wire [63:0] _T_630 = _T_622 | _T_629; // @[dbg.scala 419:168] - wire [63:0] _T_634 = _T_61 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_637 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] - wire [63:0] _T_638 = _T_634 & _T_637; // @[dbg.scala 420:119] - wire [7:0] _T_643 = _T_66 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [14:0] _T_645 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82] - wire [14:0] _GEN_117 = {{7'd0}, _T_643}; // @[dbg.scala 422:67] - wire [14:0] _T_646 = _GEN_117 & _T_645; // @[dbg.scala 422:67] - wire [7:0] _T_650 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_652 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] - wire [14:0] _T_653 = 15'h3 << _T_652; // @[dbg.scala 423:59] - wire [14:0] _GEN_118 = {{7'd0}, _T_650}; // @[dbg.scala 423:44] - wire [14:0] _T_654 = _GEN_118 & _T_653; // @[dbg.scala 423:44] - wire [14:0] _T_655 = _T_646 | _T_654; // @[dbg.scala 422:107] - wire [7:0] _T_659 = _T_55 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_661 = {sbaddress0_reg[2],1'h0}; // @[Cat.scala 29:58] - wire [10:0] _T_662 = 11'hf << _T_661; // @[dbg.scala 424:59] - wire [10:0] _GEN_119 = {{3'd0}, _T_659}; // @[dbg.scala 424:44] - wire [10:0] _T_663 = _GEN_119 & _T_662; // @[dbg.scala 424:44] - wire [14:0] _GEN_120 = {{4'd0}, _T_663}; // @[dbg.scala 423:97] - wire [14:0] _T_664 = _T_655 | _GEN_120; // @[dbg.scala 423:97] - wire [7:0] _T_668 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [14:0] _GEN_121 = {{7'd0}, _T_668}; // @[dbg.scala 424:95] - wire [14:0] _T_670 = _T_664 | _GEN_121; // @[dbg.scala 424:95] - wire [3:0] _GEN_122 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99] - wire [6:0] _T_681 = 4'h8 * _GEN_122; // @[dbg.scala 441:99] - wire [63:0] _T_682 = io_sb_axi_r_bits_data >> _T_681; // @[dbg.scala 441:92] - wire [63:0] _T_683 = _T_682 & 64'hff; // @[dbg.scala 441:123] - wire [63:0] _T_684 = _T_608 & _T_683; // @[dbg.scala 441:59] - wire [4:0] _GEN_123 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86] - wire [6:0] _T_691 = 5'h10 * _GEN_123; // @[dbg.scala 442:86] - wire [63:0] _T_692 = io_sb_axi_r_bits_data >> _T_691; // @[dbg.scala 442:78] - wire [63:0] _T_693 = _T_692 & 64'hffff; // @[dbg.scala 442:110] - wire [63:0] _T_694 = _T_617 & _T_693; // @[dbg.scala 442:45] - wire [63:0] _T_695 = _T_684 | _T_694; // @[dbg.scala 441:140] - wire [5:0] _GEN_124 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86] - wire [6:0] _T_702 = 6'h20 * _GEN_124; // @[dbg.scala 443:86] - wire [63:0] _T_703 = io_sb_axi_r_bits_data >> _T_702; // @[dbg.scala 443:78] - wire [63:0] _T_704 = _T_703 & 64'hffffffff; // @[dbg.scala 443:107] - wire [63:0] _T_705 = _T_626 & _T_704; // @[dbg.scala 443:45] - wire [63:0] _T_706 = _T_695 | _T_705; // @[dbg.scala 442:129] - wire [63:0] _T_712 = _T_634 & io_sb_axi_r_bits_data; // @[dbg.scala 444:45] + wire [31:0] _T_460 = _T_459 & haltsum0_reg; // @[dbg.scala 311:43] + wire [31:0] _T_461 = _T_456 | _T_460; // @[dbg.scala 310:114] + wire [31:0] _T_464 = _T_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_465 = _T_464 & sbcs_reg; // @[dbg.scala 311:98] + wire [31:0] _T_466 = _T_461 | _T_465; // @[dbg.scala 311:58] + wire [31:0] _T_469 = _T_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_470 = _T_469 & sbaddress0_reg; // @[dbg.scala 312:43] + wire [31:0] _T_471 = _T_466 | _T_470; // @[dbg.scala 311:109] + wire [31:0] _T_474 = _T_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_475 = _T_474 & sbdata0_reg; // @[dbg.scala 312:100] + wire [31:0] _T_476 = _T_471 | _T_475; // @[dbg.scala 312:60] + wire [31:0] _T_479 = _T_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_480 = _T_479 & sbdata1_reg; // @[dbg.scala 313:43] + wire [31:0] dmi_reg_rdata_din = _T_476 | _T_480; // @[dbg.scala 312:114] + wire _T_482 = dbg_dm_rst_l & reset; // @[dbg.scala 315:86] + reg [2:0] _T_483; // @[Reg.scala 27:20] + reg [31:0] _T_485; // @[Reg.scala 27:20] + wire _T_487 = command_reg[31:24] == 8'h2; // @[dbg.scala 324:62] + wire [31:0] _T_489 = {data1_reg[31:2],2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_491 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58] + wire _T_494 = dbg_state == 3'h3; // @[dbg.scala 326:50] + wire _T_497 = ~_T_384; // @[dbg.scala 326:75] + wire _T_498 = _T_494 & _T_497; // @[dbg.scala 326:73] + wire _T_506 = command_reg[15:12] == 4'h0; // @[dbg.scala 328:122] + wire [1:0] _T_507 = {1'h0,_T_506}; // @[Cat.scala 29:58] + wire _T_518 = 4'h0 == sb_state; // @[Conditional.scala 37:30] + wire _T_520 = sbdata0_reg_wren0 | sbreadondata_access; // @[dbg.scala 343:39] + wire _T_521 = _T_520 | sbreadonaddr_access; // @[dbg.scala 343:61] + wire _T_523 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 346:65] + wire _T_524 = sbcs_wren & _T_523; // @[dbg.scala 346:38] + wire [2:0] _T_526 = ~io_dmi_reg_wdata[14:12]; // @[dbg.scala 347:27] + wire [2:0] _T_528 = _T_526 & sbcs_reg[14:12]; // @[dbg.scala 347:53] + wire _T_529 = 4'h1 == sb_state; // @[Conditional.scala 37:30] + wire _T_530 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 350:41] + wire _T_532 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 351:40] + wire _T_533 = _T_532 | sbcs_illegal_size; // @[dbg.scala 351:57] + wire _T_536 = 4'h2 == sb_state; // @[Conditional.scala 37:30] + wire _T_543 = 4'h3 == sb_state; // @[Conditional.scala 37:30] + wire _T_544 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 363:38] + wire _T_545 = 4'h4 == sb_state; // @[Conditional.scala 37:30] + wire _T_546 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 366:48] + wire _T_549 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 367:45] + wire _T_550 = _T_549 & io_dbg_bus_clk_en; // @[dbg.scala 367:70] + wire _T_551 = 4'h5 == sb_state; // @[Conditional.scala 37:30] + wire _T_552 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 371:44] + wire _T_553 = 4'h6 == sb_state; // @[Conditional.scala 37:30] + wire _T_554 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 375:44] + wire _T_555 = 4'h7 == sb_state; // @[Conditional.scala 37:30] + wire _T_556 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 379:38] + wire _T_557 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 380:40] + wire _T_558 = 4'h8 == sb_state; // @[Conditional.scala 37:30] + wire _T_559 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39] + wire _T_561 = 4'h9 == sb_state; // @[Conditional.scala 37:30] + wire _GEN_50 = _T_561 & sbcs_reg[16]; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_558 ? _T_559 : _T_561; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_558 & _T_557; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_558 ? 1'h0 : _T_561; // @[Conditional.scala 39:67] + wire _GEN_57 = _T_558 ? 1'h0 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_555 ? _T_556 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_555 ? _T_557 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_555 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_555 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_553 ? _T_554 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_553 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_553 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_553 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_551 ? _T_552 : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_551 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_551 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_551 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_545 ? _T_550 : _GEN_73; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_545 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_545 ? 1'h0 : _GEN_76; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_545 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_543 ? _T_544 : _GEN_80; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_543 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire _GEN_90 = _T_543 ? 1'h0 : _GEN_83; // @[Conditional.scala 39:67] + wire _GEN_92 = _T_543 ? 1'h0 : _GEN_85; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_536 ? _T_533 : _GEN_87; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_536 ? _T_530 : _GEN_88; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_536 ? 1'h0 : _GEN_90; // @[Conditional.scala 39:67] + wire _GEN_99 = _T_536 ? 1'h0 : _GEN_92; // @[Conditional.scala 39:67] + wire _GEN_101 = _T_529 ? _T_533 : _GEN_94; // @[Conditional.scala 39:67] + wire _GEN_102 = _T_529 ? _T_530 : _GEN_95; // @[Conditional.scala 39:67] + wire _GEN_104 = _T_529 ? 1'h0 : _GEN_97; // @[Conditional.scala 39:67] + wire _GEN_106 = _T_529 ? 1'h0 : _GEN_99; // @[Conditional.scala 39:67] + reg [3:0] _T_564; // @[Reg.scala 27:20] + wire _T_571 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69] + wire _T_572 = sb_bus_rsp_read & _T_571; // @[dbg.scala 406:39] + wire _T_574 = |io_sb_axi_b_bits_resp; // @[dbg.scala 406:122] + wire _T_575 = sb_bus_rsp_write & _T_574; // @[dbg.scala 406:92] + wire _T_577 = sb_state == 4'h4; // @[dbg.scala 407:36] + wire _T_578 = sb_state == 4'h5; // @[dbg.scala 407:71] + wire _T_584 = sb_state == 4'h6; // @[dbg.scala 418:70] + wire [63:0] _T_590 = _T_62 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_594 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_595 = _T_590 & _T_594; // @[dbg.scala 419:65] + wire [63:0] _T_599 = _T_47 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_602 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_603 = _T_599 & _T_602; // @[dbg.scala 419:138] + wire [63:0] _T_604 = _T_595 | _T_603; // @[dbg.scala 419:96] + wire [63:0] _T_608 = _T_51 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_610 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_611 = _T_608 & _T_610; // @[dbg.scala 420:45] + wire [63:0] _T_612 = _T_604 | _T_611; // @[dbg.scala 419:168] + wire [63:0] _T_616 = _T_57 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_619 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_620 = _T_616 & _T_619; // @[dbg.scala 420:119] + wire [7:0] _T_625 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _T_627 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82] + wire [14:0] _GEN_115 = {{7'd0}, _T_625}; // @[dbg.scala 422:67] + wire [14:0] _T_628 = _GEN_115 & _T_627; // @[dbg.scala 422:67] + wire [7:0] _T_632 = _T_47 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_634 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_635 = 15'h3 << _T_634; // @[dbg.scala 423:59] + wire [14:0] _GEN_116 = {{7'd0}, _T_632}; // @[dbg.scala 423:44] + wire [14:0] _T_636 = _GEN_116 & _T_635; // @[dbg.scala 423:44] + wire [14:0] _T_637 = _T_628 | _T_636; // @[dbg.scala 422:107] + wire [7:0] _T_641 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_643 = {sbaddress0_reg[2],2'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_644 = 15'hf << _T_643; // @[dbg.scala 424:59] + wire [14:0] _GEN_117 = {{7'd0}, _T_641}; // @[dbg.scala 424:44] + wire [14:0] _T_645 = _GEN_117 & _T_644; // @[dbg.scala 424:44] + wire [14:0] _T_646 = _T_637 | _T_645; // @[dbg.scala 423:97] + wire [7:0] _T_650 = _T_57 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _GEN_118 = {{7'd0}, _T_650}; // @[dbg.scala 424:100] + wire [14:0] _T_652 = _T_646 | _GEN_118; // @[dbg.scala 424:100] + wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99] + wire [6:0] _T_663 = 4'h8 * _GEN_119; // @[dbg.scala 441:99] + wire [63:0] _T_664 = io_sb_axi_r_bits_data >> _T_663; // @[dbg.scala 441:92] + wire [63:0] _T_665 = _T_664 & 64'hff; // @[dbg.scala 441:123] + wire [63:0] _T_666 = _T_590 & _T_665; // @[dbg.scala 441:59] + wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86] + wire [6:0] _T_673 = 5'h10 * _GEN_120; // @[dbg.scala 442:86] + wire [63:0] _T_674 = io_sb_axi_r_bits_data >> _T_673; // @[dbg.scala 442:78] + wire [63:0] _T_675 = _T_674 & 64'hffff; // @[dbg.scala 442:110] + wire [63:0] _T_676 = _T_599 & _T_675; // @[dbg.scala 442:45] + wire [63:0] _T_677 = _T_666 | _T_676; // @[dbg.scala 441:140] + wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86] + wire [6:0] _T_684 = 6'h20 * _GEN_121; // @[dbg.scala 443:86] + wire [63:0] _T_685 = io_sb_axi_r_bits_data >> _T_684; // @[dbg.scala 443:78] + wire [63:0] _T_686 = _T_685 & 64'hffffffff; // @[dbg.scala 443:107] + wire [63:0] _T_687 = _T_608 & _T_686; // @[dbg.scala 443:45] + wire [63:0] _T_688 = _T_677 | _T_687; // @[dbg.scala 442:129] + wire [63:0] _T_694 = _T_616 & io_sb_axi_r_bits_data; // @[dbg.scala 444:45] rvclkhdr rvclkhdr ( // @[lib.scala 327:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -662,10 +660,10 @@ module dbg( ); assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 329:19] assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 100:21] - assign io_dbg_halt_req = _T_328 ? _T_344 : _GEN_36; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23] - assign io_dbg_resume_req = _T_328 ? 1'h0 : _GEN_39; // @[dbg.scala 262:21 dbg.scala 282:25] - assign io_dmi_reg_rdata = _T_502; // @[dbg.scala 320:20] - assign io_sb_axi_aw_valid = _T_595 | _T_596; // @[dbg.scala 407:22] + assign io_dbg_halt_req = _T_313 ? _T_329 : _GEN_35; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23] + assign io_dbg_resume_req = _T_313 ? 1'h0 : _GEN_38; // @[dbg.scala 262:21 dbg.scala 282:25] + assign io_dmi_reg_rdata = _T_485; // @[dbg.scala 320:20] + assign io_sb_axi_aw_valid = _T_577 | _T_578; // @[dbg.scala 407:22] assign io_sb_axi_aw_bits_id = 1'h0; // @[dbg.scala 409:24] assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 408:26] assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 413:28] @@ -676,9 +674,9 @@ module dbg( assign io_sb_axi_aw_bits_cache = 4'hf; // @[dbg.scala 412:27] assign io_sb_axi_aw_bits_prot = 3'h0; // @[dbg.scala 411:26] assign io_sb_axi_aw_bits_qos = 4'h0; // @[dbg.scala 416:25] - assign io_sb_axi_w_valid = _T_595 | _T_602; // @[dbg.scala 418:21] - assign io_sb_axi_w_bits_data = _T_630 | _T_638; // @[dbg.scala 419:25] - assign io_sb_axi_w_bits_strb = _T_670[7:0]; // @[dbg.scala 422:25] + assign io_sb_axi_w_valid = _T_577 | _T_584; // @[dbg.scala 418:21] + assign io_sb_axi_w_bits_data = _T_612 | _T_620; // @[dbg.scala 419:25] + assign io_sb_axi_w_bits_strb = _T_652[7:0]; // @[dbg.scala 422:25] assign io_sb_axi_w_bits_last = 1'h1; // @[dbg.scala 427:25] assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 439:21] assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 428:22] @@ -693,43 +691,43 @@ module dbg( assign io_sb_axi_ar_bits_prot = 3'h0; // @[dbg.scala 432:26] assign io_sb_axi_ar_bits_qos = 4'h0; // @[dbg.scala 437:25] assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 440:21] - assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_515 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 326:35] + assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_498 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 326:35] assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 327:35] - assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_504 ? 2'h2 : _T_524; // @[dbg.scala 328:34] - assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_504 ? {{1'd0}, _T_506} : _T_508; // @[dbg.scala 324:34] + assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_487 ? 2'h2 : _T_507; // @[dbg.scala 328:34] + assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_487 ? _T_489 : _T_491; // @[dbg.scala 324:34] assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 325:38] assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 449:39] assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 450:39] assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 451:39] assign io_dbg_dma_dbg_ib_dbg_cmd_addr = io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[dbg.scala 447:39] assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 448:39] - assign io_dbg_dma_io_dbg_dma_bubble = _T_515 | _T_307; // @[dbg.scala 330:32] - assign dbg_state = _T_499; // @[dbg.scala 315:13] - assign dbg_state_en = _T_328 ? _T_340 : _GEN_35; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20] - assign sb_state = _T_582; // @[dbg.scala 397:12] - assign sb_state_en = _T_535 ? _T_538 : _GEN_102; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19] - assign dmcontrol_reg = {_T_157,_T_155}; // @[dbg.scala 178:17] - assign sbaddress0_reg = _T_128; // @[dbg.scala 159:18] - assign sbcs_sbbusy_wren = _T_535 ? sb_state_en : _GEN_105; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24] - assign sbcs_sberror_wren = _T_535 ? _T_541 : _GEN_103; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25] - assign sb_bus_rdata = _T_706 | _T_712; // @[dbg.scala 441:16] - assign sbaddress0_reg_wren1 = _T_535 ? 1'h0 : _GEN_107; // @[dbg.scala 339:24 dbg.scala 394:28] - assign dmstatus_reg = {_T_177,_T_173}; // @[dbg.scala 184:16] - assign dmstatus_havereset = _T_210; // @[dbg.scala 201:22] - assign dmstatus_resumeack = _T_201; // @[dbg.scala 193:22] - assign dmstatus_unavail = dmcontrol_reg[1] | _T_194; // @[dbg.scala 191:20] - assign dmstatus_running = ~_T_197; // @[dbg.scala 192:20] - assign dmstatus_halted = _T_206; // @[dbg.scala 197:19] - assign abstractcs_busy_wren = _T_328 ? 1'h0 : _GEN_37; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28] + assign io_dbg_dma_io_dbg_dma_bubble = _T_498 | _T_294; // @[dbg.scala 330:32] + assign dbg_state = _T_483; // @[dbg.scala 315:13] + assign dbg_state_en = _T_313 ? _T_325 : _GEN_34; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20] + assign sb_state = _T_564; // @[dbg.scala 397:12] + assign sb_state_en = _T_518 ? _T_521 : _GEN_101; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19] + assign dmcontrol_reg = {_T_149,_T_147}; // @[dbg.scala 178:17] + assign sbaddress0_reg = _T_121; // @[dbg.scala 159:18] + assign sbcs_sbbusy_wren = _T_518 ? sb_state_en : _GEN_104; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24] + assign sbcs_sberror_wren = _T_518 ? _T_524 : _GEN_102; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25] + assign sb_bus_rdata = _T_688 | _T_694; // @[dbg.scala 441:16] + assign sbaddress0_reg_wren1 = _T_518 ? 1'h0 : _GEN_106; // @[dbg.scala 339:24 dbg.scala 394:28] + assign dmstatus_reg = {_T_168,_T_164}; // @[dbg.scala 184:16] + assign dmstatus_havereset = _T_200; // @[dbg.scala 201:22] + assign dmstatus_resumeack = _T_191; // @[dbg.scala 193:22] + assign dmstatus_unavail = dmcontrol_reg[1] | _T_185; // @[dbg.scala 191:20] + assign dmstatus_running = ~_T_188; // @[dbg.scala 192:20] + assign dmstatus_halted = _T_195; // @[dbg.scala 197:19] + assign abstractcs_busy_wren = _T_313 ? 1'h0 : _GEN_36; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28] assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 401:19] assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 402:25] assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 403:25] assign sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 404:19] - assign sb_bus_rsp_error = _T_590 | _T_593; // @[dbg.scala 406:20] + assign sb_bus_rsp_error = _T_572 | _T_575; // @[dbg.scala 406:20] assign sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 405:20] assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 336:19 dbg.scala 345:23 dbg.scala 393:23] - assign data1_reg = _T_327; // @[dbg.scala 252:13] - assign sbcs_reg = {_T_48,_T_44}; // @[dbg.scala 125:12] + assign data1_reg = _T_312; // @[dbg.scala 252:13] + assign sbcs_reg = {_T_44,_T_40}; // @[dbg.scala 125:12] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -745,17 +743,17 @@ module dbg( assign rvclkhdr_4_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 355:17] assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] - assign abstractcs_reg = {_T_289,_T_287}; // @[dbg.scala 233:18] + assign abstractcs_reg = {_T_277,_T_275}; // @[dbg.scala 233:18] assign rvclkhdr_5_io_clk = clock; // @[lib.scala 354:18] - assign rvclkhdr_5_io_en = _T_235 & _T_294; // @[lib.scala 355:17] + assign rvclkhdr_5_io_en = _T_225 & _T_282; // @[lib.scala 355:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_6_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[lib.scala 355:17] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_7_io_clk = clock; // @[lib.scala 354:18] - assign rvclkhdr_7_io_en = _T_321 & _T_294; // @[lib.scala 355:17] + assign rvclkhdr_7_io_en = _T_307 & _T_282; // @[lib.scala 355:17] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] - assign dbg_nxtstate = _T_328 ? _T_331 : _GEN_34; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20] + assign dbg_nxtstate = _T_313 ? _T_316 : _GEN_33; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -806,7 +804,7 @@ initial begin _RAND_6 = {1{`RANDOM}}; sbdata1_reg = _RAND_6[31:0]; _RAND_7 = {1{`RANDOM}}; - _T_128 = _RAND_7[31:0]; + _T_121 = _RAND_7[31:0]; _RAND_8 = {1{`RANDOM}}; dm_temp = _RAND_8[3:0]; _RAND_9 = {1{`RANDOM}}; @@ -814,11 +812,11 @@ initial begin _RAND_10 = {1{`RANDOM}}; dmcontrol_wren_Q = _RAND_10[0:0]; _RAND_11 = {1{`RANDOM}}; - _T_201 = _RAND_11[0:0]; + _T_191 = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - _T_206 = _RAND_12[0:0]; + _T_195 = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - _T_210 = _RAND_13[0:0]; + _T_200 = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; abs_temp_12 = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; @@ -828,79 +826,79 @@ initial begin _RAND_17 = {1{`RANDOM}}; data0_reg = _RAND_17[31:0]; _RAND_18 = {1{`RANDOM}}; - _T_327 = _RAND_18[31:0]; + _T_312 = _RAND_18[31:0]; _RAND_19 = {1{`RANDOM}}; - _T_499 = _RAND_19[2:0]; + _T_483 = _RAND_19[2:0]; _RAND_20 = {1{`RANDOM}}; - _T_502 = _RAND_20[31:0]; + _T_485 = _RAND_20[31:0]; _RAND_21 = {1{`RANDOM}}; - _T_582 = _RAND_21[3:0]; + _T_564 = _RAND_21[3:0]; `endif // RANDOMIZE_REG_INIT - if (_T_30) begin + if (_T_29) begin temp_sbcs_22 = 1'h0; end - if (_T_30) begin + if (_T_29) begin temp_sbcs_21 = 1'h0; end - if (_T_30) begin + if (_T_29) begin temp_sbcs_20 = 1'h0; end - if (_T_30) begin + if (_T_29) begin temp_sbcs_19_15 = 5'h0; end - if (_T_30) begin + if (_T_36) begin temp_sbcs_14_12 = 3'h0; end - if (_T_30) begin + if (_T_29) begin sbdata0_reg = 32'h0; end - if (_T_30) begin + if (_T_29) begin sbdata1_reg = 32'h0; end - if (_T_30) begin - _T_128 = 32'h0; + if (_T_29) begin + _T_121 = 32'h0; end - if (_T_30) begin + if (_T_29) begin dm_temp = 4'h0; end if (io_dbg_rst_l) begin dm_temp_0 = 1'h0; end - if (_T_30) begin + if (_T_29) begin dmcontrol_wren_Q = 1'h0; end - if (_T_30) begin - _T_201 = 1'h0; + if (_T_29) begin + _T_191 = 1'h0; end - if (_T_30) begin - _T_206 = 1'h0; + if (_T_29) begin + _T_195 = 1'h0; end - if (_T_30) begin - _T_210 = 1'h0; + if (_T_29) begin + _T_200 = 1'h0; end - if (_T_30) begin + if (_T_29) begin abs_temp_12 = 1'h0; end - if (_T_30) begin + if (_T_29) begin abs_temp_10_8 = 3'h0; end - if (_T_30) begin + if (_T_29) begin command_reg = 32'h0; end - if (_T_30) begin + if (_T_29) begin data0_reg = 32'h0; end - if (_T_30) begin - _T_327 = 32'h0; + if (_T_29) begin + _T_312 = 32'h0; end - if (_T_498) begin - _T_499 = 3'h0; + if (_T_482) begin + _T_483 = 3'h0; end - if (_T_30) begin - _T_502 = 32'h0; + if (_T_29) begin + _T_485 = 32'h0; end - if (_T_30) begin - _T_582 = 4'h0; + if (_T_29) begin + _T_564 = 4'h0; end `endif // RANDOMIZE end // initial @@ -908,95 +906,95 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin + if (_T_29) begin temp_sbcs_22 <= 1'h0; end else if (sbcs_sbbusyerror_wren) begin temp_sbcs_22 <= sbcs_sbbusyerror_din; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin + if (_T_29) begin temp_sbcs_21 <= 1'h0; end else if (sbcs_sbbusy_wren) begin temp_sbcs_21 <= sbcs_sbbusy_din; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin + if (_T_29) begin temp_sbcs_20 <= 1'h0; end else if (sbcs_wren) begin temp_sbcs_20 <= io_dmi_reg_wdata[20]; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin + if (_T_29) begin temp_sbcs_19_15 <= 5'h0; end else if (sbcs_wren) begin temp_sbcs_19_15 <= io_dmi_reg_wdata[19:15]; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_36) begin + if (_T_36) begin temp_sbcs_14_12 <= 3'h0; end else if (sbcs_sberror_wren) begin - if (_T_535) begin - temp_sbcs_14_12 <= _T_545; - end else if (_T_546) begin + if (_T_518) begin + temp_sbcs_14_12 <= _T_528; + end else if (_T_529) begin if (sbcs_unaligned) begin temp_sbcs_14_12 <= 3'h3; end else begin temp_sbcs_14_12 <= 3'h4; end + end else if (_T_536) begin + if (sbcs_unaligned) begin + temp_sbcs_14_12 <= 3'h3; + end else begin + temp_sbcs_14_12 <= 3'h4; + end + end else if (_T_543) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_545) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_551) begin + temp_sbcs_14_12 <= 3'h0; end else if (_T_553) begin - if (sbcs_unaligned) begin - temp_sbcs_14_12 <= 3'h3; - end else begin - temp_sbcs_14_12 <= 3'h4; - end - end else if (_T_560) begin temp_sbcs_14_12 <= 3'h0; - end else if (_T_562) begin - temp_sbcs_14_12 <= 3'h0; - end else if (_T_568) begin - temp_sbcs_14_12 <= 3'h0; - end else if (_T_570) begin - temp_sbcs_14_12 <= 3'h0; - end else if (_T_572) begin + end else if (_T_555) begin temp_sbcs_14_12 <= 3'h2; - end else if (_T_575) begin + end else if (_T_558) begin temp_sbcs_14_12 <= 3'h2; end else begin temp_sbcs_14_12 <= 3'h0; end end end - always @(posedge rvclkhdr_2_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_2_io_l1clk or posedge _T_29) begin + if (_T_29) begin sbdata0_reg <= 32'h0; end else begin - sbdata0_reg <= _T_99 | _T_103; + sbdata0_reg <= _T_95 | _T_99; end end - always @(posedge rvclkhdr_3_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_3_io_l1clk or posedge _T_29) begin + if (_T_29) begin sbdata1_reg <= 32'h0; end else begin - sbdata1_reg <= _T_106 | _T_110; + sbdata1_reg <= _T_102 | _T_106; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_128 <= 32'h0; + always @(posedge rvclkhdr_4_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_121 <= 32'h0; end else begin - _T_128 <= _T_119 | _T_125; + _T_121 <= _T_113 | _T_119; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin dm_temp <= 4'h0; end else if (dmcontrol_wren) begin - dm_temp <= _T_148; + dm_temp <= _T_140; end end always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin @@ -1006,177 +1004,177 @@ end // initial dm_temp_0 <= io_dmi_reg_wdata[0]; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin dmcontrol_wren_Q <= 1'h0; end else begin - dmcontrol_wren_Q <= _T_141 & io_dmi_reg_wr_en; + dmcontrol_wren_Q <= _T_134 & io_dmi_reg_wr_en; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_201 <= 1'h0; + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_191 <= 1'h0; end else if (dmstatus_resumeack_wren) begin - _T_201 <= _T_180; + _T_191 <= _T_171; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_206 <= 1'h0; + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_195 <= 1'h0; end else begin - _T_206 <= io_dec_tlu_dbg_halted & _T_204; + _T_195 <= io_dec_tlu_dbg_halted & _T_193; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_210 <= 1'h0; - end else if (dmstatus_havereset_wren) begin - _T_210 <= _T_209; + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_200 <= 1'h0; + end else begin + _T_200 <= _T_197 & _T_198; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin abs_temp_12 <= 1'h0; end else if (abstractcs_busy_wren) begin - if (_T_328) begin + if (_T_313) begin abs_temp_12 <= 1'h0; - end else if (_T_346) begin + end else if (_T_331) begin abs_temp_12 <= 1'h0; end else begin - abs_temp_12 <= _T_358; + abs_temp_12 <= _T_343; end end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin abs_temp_10_8 <= 3'h0; end else begin - abs_temp_10_8 <= _T_276 | _T_281; + abs_temp_10_8 <= _T_266 | _T_271; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge _T_29) begin + if (_T_29) begin command_reg <= 32'h0; end else begin - command_reg <= {_T_300,_T_298}; + command_reg <= {_T_288,_T_286}; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge _T_30) begin - if (_T_30) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge _T_29) begin + if (_T_29) begin data0_reg <= 32'h0; end else begin - data0_reg <= _T_313 | _T_316; + data0_reg <= _T_300 | _T_303; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_327 <= 32'h0; + always @(posedge rvclkhdr_7_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_312 <= 32'h0; end else begin - _T_327 <= _T_324 & io_dmi_reg_wdata; + _T_312 <= _T_310 & io_dmi_reg_wdata; end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_498) begin - if (_T_498) begin - _T_499 <= 3'h0; + always @(posedge rvclkhdr_io_l1clk or posedge _T_482) begin + if (_T_482) begin + _T_483 <= 3'h0; end else if (dbg_state_en) begin - if (_T_328) begin - if (_T_330) begin - _T_499 <= 3'h2; + if (_T_313) begin + if (_T_315) begin + _T_483 <= 3'h2; end else begin - _T_499 <= 3'h1; + _T_483 <= 3'h1; end - end else if (_T_346) begin + end else if (_T_331) begin if (dmcontrol_reg[1]) begin - _T_499 <= 3'h0; + _T_483 <= 3'h0; end else begin - _T_499 <= 3'h2; + _T_483 <= 3'h2; end - end else if (_T_358) begin - if (_T_362) begin - if (_T_366) begin - _T_499 <= 3'h6; + end else if (_T_343) begin + if (_T_347) begin + if (_T_351) begin + _T_483 <= 3'h6; end else begin - _T_499 <= 3'h3; + _T_483 <= 3'h3; end end else if (dmcontrol_reg[31]) begin - _T_499 <= 3'h1; + _T_483 <= 3'h1; end else begin - _T_499 <= 3'h0; + _T_483 <= 3'h0; end - end else if (_T_396) begin + end else if (_T_381) begin if (dmcontrol_reg[1]) begin - _T_499 <= 3'h0; - end else if (_T_399) begin - _T_499 <= 3'h5; + _T_483 <= 3'h0; + end else if (_T_384) begin + _T_483 <= 3'h5; end else begin - _T_499 <= 3'h4; + _T_483 <= 3'h4; end - end else if (_T_413) begin + end else if (_T_398) begin if (dmcontrol_reg[1]) begin - _T_499 <= 3'h0; + _T_483 <= 3'h0; end else begin - _T_499 <= 3'h5; + _T_483 <= 3'h5; end - end else if (_T_424) begin + end else if (_T_409) begin if (dmcontrol_reg[1]) begin - _T_499 <= 3'h0; + _T_483 <= 3'h0; end else begin - _T_499 <= 3'h2; + _T_483 <= 3'h2; end end else begin - _T_499 <= 3'h0; + _T_483 <= 3'h0; end end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_502 <= 32'h0; + always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_485 <= 32'h0; end else if (io_dmi_reg_en) begin - _T_502 <= dmi_reg_rdata_din; + _T_485 <= dmi_reg_rdata_din; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge _T_30) begin - if (_T_30) begin - _T_582 <= 4'h0; + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin + if (_T_29) begin + _T_564 <= 4'h0; end else if (sb_state_en) begin - if (_T_535) begin + if (_T_518) begin if (sbdata0_reg_wren0) begin - _T_582 <= 4'h2; + _T_564 <= 4'h2; end else begin - _T_582 <= 4'h1; + _T_564 <= 4'h1; end - end else if (_T_546) begin - if (_T_547) begin - _T_582 <= 4'h9; + end else if (_T_529) begin + if (_T_530) begin + _T_564 <= 4'h9; end else begin - _T_582 <= 4'h3; + _T_564 <= 4'h3; end - end else if (_T_553) begin - if (_T_547) begin - _T_582 <= 4'h9; + end else if (_T_536) begin + if (_T_530) begin + _T_564 <= 4'h9; end else begin - _T_582 <= 4'h4; + _T_564 <= 4'h4; end - end else if (_T_560) begin - _T_582 <= 4'h7; - end else if (_T_562) begin - if (_T_563) begin - _T_582 <= 4'h8; + end else if (_T_543) begin + _T_564 <= 4'h7; + end else if (_T_545) begin + if (_T_546) begin + _T_564 <= 4'h8; end else if (sb_bus_cmd_write_data) begin - _T_582 <= 4'h5; + _T_564 <= 4'h5; end else begin - _T_582 <= 4'h6; + _T_564 <= 4'h6; end - end else if (_T_568) begin - _T_582 <= 4'h8; - end else if (_T_570) begin - _T_582 <= 4'h8; - end else if (_T_572) begin - _T_582 <= 4'h9; - end else if (_T_575) begin - _T_582 <= 4'h9; + end else if (_T_551) begin + _T_564 <= 4'h8; + end else if (_T_553) begin + _T_564 <= 4'h8; + end else if (_T_555) begin + _T_564 <= 4'h9; + end else if (_T_558) begin + _T_564 <= 4'h9; end else begin - _T_582 <= 4'h0; + _T_564 <= 4'h0; end end end diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index 40eae7ce..d4456bc6 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1,3 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/gated_latch.v -/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv -/home/waleedbinehsan/Desktop/Quasar/mem.sv \ No newline at end of file +/home/waleedbinehsan/Desktop/Quasar/gated_latch.v \ No newline at end of file diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala index 80b5fbca..49d28481 100644 --- a/src/main/scala/dbg/dbg.scala +++ b/src/main/scala/dbg/dbg.scala @@ -103,19 +103,19 @@ class dbg extends Module with lib with RequireAsyncReset { ((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U))) val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt() - val temp_sbcs_22 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val temp_sbcs_22 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren) } // sbcs_sbbusyerror_reg - val temp_sbcs_21 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val temp_sbcs_21 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren) } // sbcs_sbbusy_reg - val temp_sbcs_20 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val temp_sbcs_20 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren) } // sbcs_sbreadonaddr_reg - val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren) } // sbcs_misc_reg @@ -124,13 +124,13 @@ class dbg extends Module with lib with RequireAsyncReset { } // sbcs_error_reg sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W)) - val sbcs_unaligned = (sbcs_reg(19, 17) === "b001".U) & sbaddress0_reg(0) | - (sbcs_reg(19, 17) === "b010".U) & sbaddress0_reg(1, 0).orR | - (sbcs_reg(19, 17) === "b011".U) & sbaddress0_reg(2, 0).orR + val sbcs_unaligned = (sbcs_reg(19, 17) === "b001".U(3.W)) & sbaddress0_reg(0) | + (sbcs_reg(19, 17) === "b010".U(3.W)) & sbaddress0_reg(1, 0).orR | + (sbcs_reg(19, 17) === "b011".U(3.W)) & sbaddress0_reg(2, 0).orR val sbcs_illegal_size = sbcs_reg(19) - val sbaddress0_incr = Fill(4, (sbcs_reg(19, 17) === "h0".U)) & "b0001".U | Fill(4, (sbcs_reg(19, 17) === "h1".U)) & "b0010".U | - Fill(4, (sbcs_reg(19, 17) === "h2".U)) & "b0100".U | Fill(4, (sbcs_reg(19, 17) === "h3".U)) & "b1000".U + val sbaddress0_incr = Fill(4, (sbcs_reg(19, 17) === "h0".U)) & "b0001".U(4.W) | Fill(4, (sbcs_reg(19, 17) === "h1".U)) & "b0010".U(4.W) | + Fill(4, (sbcs_reg(19, 17) === "h2".U)) & "b0100".U(4.W) | Fill(4, (sbcs_reg(19, 17) === "h3".U)) & "b1000".U(4.W) val sbdata0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) val sbdata0_reg_wren1 = (sb_state === sb_state_t.rsp_rd) & sb_state_en & !sbcs_sberror_wren @@ -144,11 +144,11 @@ class dbg extends Module with lib with RequireAsyncReset { val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata | Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32) - val sbdata0_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { + val sbdata0_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode) } // dbg_sbdata0_reg - val sbdata1_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { + val sbdata1_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode) } // dbg_sbdata1_reg @@ -156,7 +156,7 @@ class dbg extends Module with lib with RequireAsyncReset { val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1 val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata | Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr)) - sbaddress0_reg := withReset((!dbg_dm_rst_l).asAsyncReset()) { + sbaddress0_reg := withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode) } // dbg_sbaddress0_reg @@ -164,7 +164,7 @@ class dbg extends Module with lib with RequireAsyncReset { val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15) val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en - val dm_temp = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val dm_temp = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable( Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)), 0.U, dmcontrol_wren) @@ -177,7 +177,7 @@ class dbg extends Module with lib with RequireAsyncReset { val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0) dmcontrol_reg := temp - val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegNext(dmcontrol_wren, 0.U) } // dmcontrol_wrenff @@ -190,16 +190,16 @@ class dbg extends Module with lib with RequireAsyncReset { val temp_rst = reset.asBool() dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool() dmstatus_running := ~(dmstatus_unavail | dmstatus_halted) - dmstatus_resumeack := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + dmstatus_resumeack := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren) } // dmstatus_resumeack_reg - dmstatus_halted := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + dmstatus_halted := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U) } // dmstatus_halted_reg - dmstatus_havereset := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { - RegEnable(~dmstatus_havereset_rst, 0.U, dmstatus_havereset_wren) + dmstatus_havereset := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { + RegNext(Mux(dmstatus_havereset_wren, true.B, dmstatus_havereset) & !dmstatus_havereset_rst, false.B) } // dmstatus_havereset_reg val haltsum0_reg = Cat(0.U(31.W), dmstatus_halted) @@ -210,23 +210,23 @@ class dbg extends Module with lib with RequireAsyncReset { val abstractcs_error_sel2 = io.core_dbg_cmd_done & io.core_dbg_cmd_fail val abstractcs_error_sel3 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h17".U) & !dmstatus_reg(9); val abstractcs_error_sel4 = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & - ((io.dmi_reg_wdata(22, 20) =/= "b010".U) | ((io.dmi_reg_wdata(31, 24) === "h2".U) && data1_reg(1, 0).orR)) + ((io.dmi_reg_wdata(22, 20) =/= "b010".U(3.W)) | ((io.dmi_reg_wdata(31, 24) === "h2".U) && data1_reg(1, 0).orR)) val abstractcs_error_sel5 = (io.dmi_reg_addr === "h16".U) & io.dmi_reg_en & io.dmi_reg_wr_en val abstractcs_error_selor = abstractcs_error_sel0 | abstractcs_error_sel1 | abstractcs_error_sel2 | abstractcs_error_sel3 | abstractcs_error_sel4 | abstractcs_error_sel5 - val abstractcs_error_din = (Fill(3, abstractcs_error_sel0) & "b001".U) | - (Fill(3, abstractcs_error_sel1) & "b010".U) | - (Fill(3, abstractcs_error_sel2) & "b011".U) | - (Fill(3, abstractcs_error_sel3) & "b100".U) | - (Fill(3, abstractcs_error_sel4) & "b111".U) | + val abstractcs_error_din = (Fill(3, abstractcs_error_sel0) & "b001".U(3.W)) | + (Fill(3, abstractcs_error_sel1) & "b010".U(3.W)) | + (Fill(3, abstractcs_error_sel2) & "b011".U(3.W)) | + (Fill(3, abstractcs_error_sel3) & "b100".U(3.W)) | + (Fill(3, abstractcs_error_sel4) & "b111".U(3.W)) | (Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) | (Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8)) - val abs_temp_12 = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val abs_temp_12 = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren) } // dmabstractcs_busy_reg - val abs_temp_10_8 = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + val abs_temp_10_8 = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegNext(abstractcs_error_din(2, 0), 0.U) } // dmabstractcs_error_reg @@ -234,7 +234,7 @@ class dbg extends Module with lib with RequireAsyncReset { val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted) val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0)) - val command_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { + val command_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(command_din, command_wren,clock,io.scan_mode) } // dmcommand_reg @@ -243,13 +243,13 @@ class dbg extends Module with lib with RequireAsyncReset { val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata - val data0_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { + val data0_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(data0_din,data0_reg_wren,clock,io.scan_mode) } // dbg_data0_reg val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted)) val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata - data1_reg := withReset((!dbg_dm_rst_l).asAsyncReset()) { + data1_reg := withReset((dbg_dm_rst_l).asAsyncReset()) { rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode) } // dbg_data1_reg @@ -273,7 +273,7 @@ class dbg extends Module with lib with RequireAsyncReset { } is(state_t.halted) { dbg_nxtstate := Mux(dmstatus_reg(9) & !dmcontrol_reg(1), - Mux(dmcontrol_reg(30) & !dmcontrol_reg(3), state_t.resuming, state_t.cmd_start), + Mux(dmcontrol_reg(30) & !dmcontrol_reg(31), state_t.resuming, state_t.cmd_start), Mux(dmcontrol_reg(31), state_t.halting, state_t.idle)) dbg_state_en := dmstatus_reg(9) & dmcontrol_reg(30) & !dmcontrol_reg(31) & dmcontrol_wren_Q | command_wren | dmcontrol_reg(1) | !(dmstatus_reg(9) | io.dec_tlu_mpc_halted_only) @@ -311,21 +311,21 @@ class dbg extends Module with lib with RequireAsyncReset { Fill(32, io.dmi_reg_addr === "h40".U) & haltsum0_reg | Fill(32, io.dmi_reg_addr === "h38".U) & sbcs_reg | Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg | Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg - 0 - dbg_state := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l & temp_rst).asAsyncReset()) { + + dbg_state := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l & temp_rst).asAsyncReset()) { RegEnable(dbg_nxtstate, 0.U, dbg_state_en) } // dbg_state_reg - io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en) } // dmi_rddata_reg - io.dbg_dec.dbg_ib.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), Cat(data1_reg(31, 2), "b00".U), Cat(0.U(20.W), command_reg(11, 0))) + io.dbg_dec.dbg_ib.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), Cat(data1_reg(31, 2), "b00".U(2.W)), Cat(0.U(20.W), command_reg(11, 0))) io.dbg_dec.dbg_dctl.dbg_cmd_wrdata := data0_reg(31, 0) io.dbg_dec.dbg_ib.dbg_cmd_valid := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) & io.dbg_dma_io.dma_dbg_ready).asBool() io.dbg_dec.dbg_ib.dbg_cmd_write := command_reg(16).asBool() - io.dbg_dec.dbg_ib.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U, Cat("b0".U, (command_reg(15, 12) === "b0".U))) + io.dbg_dec.dbg_ib.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U(2.W), Cat("b0".U, (command_reg(15, 12) === "b0".U))) io.dbg_cmd_size := command_reg(21, 20) io.dbg_dma_io.dbg_dma_bubble := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) | (dbg_state === state_t.cmd_wait)).asBool() @@ -344,19 +344,19 @@ class dbg extends Module with lib with RequireAsyncReset { sbcs_sbbusy_wren := sb_state_en sbcs_sbbusy_din := true.B sbcs_sberror_wren := sbcs_wren & io.dmi_reg_wdata(14, 12).orR - sbcs_sberror_din := !io.dmi_reg_wdata(14, 12) & sbcs_reg(14, 12) + sbcs_sberror_din := ~io.dmi_reg_wdata(14, 12) & sbcs_reg(14, 12) } is(sb_state_t.wait_rd) { sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_rd) sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size - sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U, "b100".U) + sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U(3.W), "b100".U(3.W)) } is(sb_state_t.wait_wr) { sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_wr) sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size; - sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U, "b100".U) + sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U(3.W), "b100".U) } is(sb_state_t.cmd_rd) { sb_nxtstate := sb_state_t.rsp_rd @@ -378,13 +378,13 @@ class dbg extends Module with lib with RequireAsyncReset { sb_nxtstate := sb_state_t.done sb_state_en := sb_bus_rsp_read & io.dbg_bus_clk_en sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error - sbcs_sberror_din := "b010".U + sbcs_sberror_din := "b010".U(3.W) } is(sb_state_t.rsp_wr) { sb_nxtstate := sb_state_t.done; sb_state_en := sb_bus_rsp_write & io.dbg_bus_clk_en sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error - sbcs_sberror_din := "b010".U + sbcs_sberror_din := "b010".U(3.W) } is(sb_state_t.done) { sb_nxtstate := sb_state_t.sbidle; @@ -394,7 +394,7 @@ class dbg extends Module with lib with RequireAsyncReset { sbaddress0_reg_wren1 := sbcs_reg(16) }} - sb_state := withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { + sb_state := withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { RegEnable(sb_nxtstate, 0.U, sb_state_en) } // sb_state_reg @@ -412,7 +412,7 @@ class dbg extends Module with lib with RequireAsyncReset { io.sb_axi.aw.bits.cache := "b1111".U io.sb_axi.aw.bits.region := sbaddress0_reg(31, 28) io.sb_axi.aw.bits.len := 0.U - io.sb_axi.aw.bits.burst := "b01".U + io.sb_axi.aw.bits.burst := "b01".U(2.W) io.sb_axi.aw.bits.qos := 0.U io.sb_axi.aw.bits.lock := false.B io.sb_axi.w.valid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_data)).asBool() @@ -421,7 +421,7 @@ class dbg extends Module with lib with RequireAsyncReset { io.sb_axi.w.bits.strb := Fill(8, (sbcs_reg(19, 17) === "h0".U)) & ("h1".U(8.W) << sbaddress0_reg(2, 0)) | Fill(8, (sbcs_reg(19, 17) === "h1".U)) & ("h3".U(8.W) << Cat(sbaddress0_reg(2, 1), "b0".U)) | - Fill(8, (sbcs_reg(19, 17) === "h2".U)) & ("hf".U(8.W) << Cat(sbaddress0_reg(2), "b00".U)) | + Fill(8, (sbcs_reg(19, 17) === "h2".U)) & ("hf".U(8.W) << Cat(sbaddress0_reg(2), "b00".U(2.W))) | Fill(8, (sbcs_reg(19, 17) === "h3".U)) & "hff".U io.sb_axi.w.bits.last := true.B @@ -433,7 +433,7 @@ class dbg extends Module with lib with RequireAsyncReset { io.sb_axi.ar.bits.cache := 0.U io.sb_axi.ar.bits.region := sbaddress0_reg(31, 28) io.sb_axi.ar.bits.len := 0.U - io.sb_axi.ar.bits.burst := "b01".U + io.sb_axi.ar.bits.burst := "b01".U(2.W) io.sb_axi.ar.bits.qos := 0.U io.sb_axi.ar.bits.lock := false.B io.sb_axi.b.ready := true.B diff --git a/target/scala-2.12/classes/dbg/dbg.class b/target/scala-2.12/classes/dbg/dbg.class index 0c3e7c940dfdf7090179488e569679be343c846d..8407081442936cddc4d72d922e3ae172fa2cdc06 100644 GIT binary patch literal 275167 zcmce934C2e_5WR7@|H}}CM{{xra;}TiPV0dsA9oUy_$JG)tSMX|bXL zBBH1WDvKf_A|fKPiwZ7?%g+_ppMQVu3o7DY|%;E!y4LTZO-r z)IHXpiE1X~`};bp@E6tcbgj&i-s*$dAe_Geh zY?VaSaHgj}(=}SPi`cvRdI!^^W5b#Cx|Y{@YBV#Vmp_!R7p^>#Zb~+r)6C)>C3!LP z6=t$HnM@Zij5ieOoqEEIw-lOr#!f>oC~ivj6fZ1ph%&#g$jmb@(Ix*F_#KMhG7bDe z=AQunlv{q-kuQs>{7L?VBj2F-GXF~*`3^V#GKYW4osYpdsob)-EB}0l-=O$1{{-_T zez$y)BY(;*U*gD@C0zNJI`R!}{v3zj;pU&|@K3q<^BsO!fh+$-4!^<8U*_;T-27Dz z|CF0w>+s8jEC00)zroFKbod=^{&^1nl$+n=@XIXwq4wS6@NK&y{#J+Iq2y(|v@@UD z<&>MR?2!0nMT}p{?{(xG6kpom0ayNR{>2Xe6!VMYgy$0C8%@K=zhj!rpZS9h{}l7% zGXG&GpR(yLeV%am4Q~FW4!=Y3CH~8pFYD{#M-1D}%gS`8zL9)~-{9sa9DawJU*zyl zx%njyzszv(M@pHGepJ@r=Ff5X9g0u*BWF7KoN~+0cjU`VSN@9}euJC8%;9&q`KuiM zDL22?;g>~R`LA{O4T>*uHZmW2F6(gf&vW>v-25hoUzX?6|0ajup!j4Dk*&-py>+nJ!|!nOFLwB+-26_5U*__|ksjug9^C#s;`sA2%b!cV zDSuA#Zhsze{CSz%pGO>jUS|1osUPLfrG8v~JEHtK@!kGBV%Ytq%bcxx}yXk$mOPiEsIH$yffI_-=n5ar}9i<jUS|1o+3w1p%l38o^N8cm%iR7v;`sA2w?B_K{=BTi<^LnfpG*91 zey0n+^4qdrJr2LY&6obaDS0ffuwwDRoP5)qQBb4LsXY?a%ZBx2a*MgIph4uBMoIn| zJw{VvGT~0q;W~gFq$eVs*JshDvFO^l-!wDR=j6>dELOa`8$eh4kml^ zA`9ac73++$;+f+E`)dbVE}J{MJylnlm-lkU+1!eHHW-zOiXF>mtQ#v{8gHnoSlw*Q z$SW?sSfAFCIA^@SW8KKM%Vw;bc5(Fp;hF|qjrnV4L(eD8%`=k89qW#DPX4`KF?@RL|ZVA9WytUjkh1FJIwjlXU;D<-MeZ|UV%9- z`r2xec}CvC*%cdWk7Y_vZ))pUeR%WQ%JJ3%HJ4C1#}8ZOtmk^oUenpJ^Yo&s0}b&r z;)TUK=J5QuN{`9%s}3}txTw^6KF{?$k=a&sdegLn>kqe-&fGV2pn5P>vLf1KHszah zXBHOE*Nsc^ipa;_*8|Xr`au~<>TVa`V;4`jjS7x zcvfs4*uQS5qh~`!Q##M7cT2^-fsX32j=h9O;wl~JSPR^TT)6Tx7cHXas}FB$r1ViM z{g7Exv2WEy)g#-^JY8Bir*4FB%y)1UwXAI&Z#`6Z7#E|GHT~L zR3bK4mE{%WZI3H`kIkxx)D7;sY{ve91Jxrf`IWN^&3to3-kQZ_70r6yMe%fcUhU!L z&ena+deiKR;^O#*bWu@WylsAy-Za;o*U~#!R)3Qz2&aUg(ytlZbI3CZ->nbi=Xqx6GWT2z*aBl+r<t+*K=z%>(ta-Cf1Sg_(44v>sYNbZF7&_{wBFbCI-z^`mH? zBkc#*3~e_O$I*^f`o8Ac%Ke20+~qXSDlA{$(*k`iD61Xq+bZe{FRmRuKe1w6Rf_dr zv8kr3cjwI617+*Gf!Ez$Gn*6TTecsn>Fz5+J9Mlc9l2})#ufdHKz@0#aTe^4Li?;;SzZUb zX(fB@Y$=%;TS)Dy`r$<-WM^x}wgFG!#Wlvtfc(UPnz3f+$F`e8jmKsA&`)pT^rDp) zHy+NkM^3`7JE0#NXDi8-&P2axG!|I-ZY_@u?U(i$Td2n^93#C=3P*n2!o6r{UIXJs zJ)w{KfkV}!8(H6(U5!#7(DU3SZI(Wvw+c&+%RSt(XmnPEuV07*Ylf0}EypQ!o zz3T7@JIXF4(iisJZ(k4-gepC&4U-!A>Y0l z=)E^nx?;S)tiB)qB29X0+qz;O<^u!!N=Ks$^(gtJ9`vi8^NYIcSLGXKH|9CTvzta{ z6c;yCrI(rogs&W zX4k9qbymE>T*&@J_G3MNbR+Ch`H3B{FGrtBe=H|hZeA_ysdazbyvAdh%hoTcnzOFL z+~M(0@Xx0g56!N-j8i<91Xv_&uMEA5Yx|D$$_w&_KlIQ-LDJ67x~B6~soRX5=@I?ErqId)DBbbv-Tlr_j#8zjt(2;lVXW z4wY6$7baoPRNmbBfo*4s&4c?JFBvNp6|C27n~M(C9civTy|!xZc|FNIN?(&{fnOY& zS9W+;WBKAL>JN^;Ep0zoJCe*pe<&lr&Ep2<8T;GH%Z!C>GdGj{y8Lw%dcn9*N&UEn z#+?E91K8h88W-gJLfSWvD_y$mrwZ*f4r((Vh%4>eu7Y2{qZuWg+0qv-du zRJ`lu(ytcU`IfZOcq!a^S*b@yH_G{#tPk1^{lKZ;EPVs(%k~Gs<70HP@v#W@vbb#~ z{BzyNw)XOvOFzcaU_Qo6|9s%ItmnjhxW3@S57lH+jdEUbxVfl&-@u_p%0Gx-VYZbm zfxqc&!Mud*=6sB!D>2?v{|(|N^K{$pwjZkQ+*|}ZJ>=Ne(ALwKN7vGPW`<|JL-t92 zac%i{d-?j2R4v)E;qf3y?*b6&AAqqu)u$bME5U8yC!g+A?*=ELnZLl;+%V1DVYM_==S6=>JS zo<90ri1|`6`!|v+Hl+TTUsgfCm+(7>=WE7XZ@j{6h%X+Pw|=C#sB#^TYvTBP_k4!u ztEKLF$%;9RBdM+MTXX7b%nna__V@c6dpeqo8Q%HN^2M0{j-21VV)LptebyxT)h6?n zmb7&=j%D)8HxI!tt8rp4iVfFzafW)%{WZ_QlfOgG z1LZi1dFDKlbB}ZRr(E+yHNkGTZZ^|DPD}$TJJ(Po;=py*VQ-LJT!2u zuRpW>*l6F-;7Fx6+T5QW8Hs9zcrhBDE~-t_wHX14b?po*<*{_v(R6R7vT10jzcQ+o z=-M>jqo_6$Z&>AXU90pxtn3*c8lY#H^x*EH);_%YP4`E&S-Lhe=!veK9h5=K;HWF{ z99^4EiQQaRT`k16$iBYr(IZi9o~{*ndAhbBsI*<9!+nFjt^&`7mMEp~0aT%0a938Q z2ZshLYogi$U0Zlb`b4^_KRwusSKTLuj%KRbGNVU^y0@eUyZbXEm90ZVN5_suwS~YO zE*jMq>smg`>sqmTJ6<__qO1Stk?vtM$1=PKx1+%0h;;Y#WFW8-Z`FrS$cQHgdYL{l z0)c9ogNo{!(KiI`wpwaw8Y9ejgHEs8QzN74(G0X`Ki-2Tz(Zj_Ol1b$&#B?@JT}s4 zr7f^XDOuP(&^0tTIy}^$8qV}0CCPMal`{bG5A;hDVO69H2hd3pi3=0PbSROl8TAk|h>P?W|+Tic=XitU0tN z5^#%A)AtN#GAY<3HBTY(cgLk|SPYb9+fH-;P}fly2U&#kT#9!Oq=rXEQ&4kUmc$JY zb=WZ7jgQv$@g-m}ni)6-)4{XaS~R{ZO19vNq6QoJKfN>%(SU^8^ zmQeGuCHD3AV;@U@YNYQ{^bNFuZNYtmU1%*xk?N#DOG`v?6L>%boqOeMF{yQ5Qitax zb$C*%oSW1Ibj;1?j;StYKa=el)O7%OhO1hTQ{Aq_$CbH5l+1T%ko1sBcXgpR%M6%H zIBc#}=W$1{$Z-kW>`_<)wGR0prcwYDVHSF(U}wL{lt+1=3Y!3u6^z!M4CNn(3~ z2}ztMFip5LX)ux$)ZO7Lls=1Gy<4jE3>Sm#7Tcgug+M-9GmsDa3*^^L!e2cJAC_Gj zgl7nr>ULMIo?ifY*#fc`6gsi$)H-yeuAzYejBH9_1y+RqrxFNYanQGhEmTGNj z-$+9k?E6`7p<#Fwy#+cMKA}eA z0l6~{eW%qK*3}~@d%1zD-AXCt^Wp^sMVZ+YU79en9t=mzK ze719EvLm%&S1nfd>h-7O|2V&Fn|k; z0bHOA-~wj=7f1uRz#6~>+5j%_dg|4d+_lZGPvZIYNj$$kiRafR@%;KEo?oBD^Xrp% zz*n@Pxw$RXlx*LYYHHcN3oeZrlAgwN$L@`(eJvZPcQHq{f#Prm8=IRgkph{Bn+7H( zW1HM5I1lb4TqftyzK4MT1n04H5aZfr)6C~Rp?HgDOO zswE`>+jJFo>8!}jA}8fxP%kcaODN5`GuoBfmjtF6me|Im%jMaE#AS_H`ANMh&o@&g zmONIkyJ&Y4B$Ozc&8eW(WF_jMx6u@n^QAfp#c6F%?KJK1 zw@HTA_E9B^K{Z72R@BKg&P>@qP#p+ZdgB<^P*xt#IGwU`Debay&Wd%xiEWFQqRQf# zmKL9A*|Z1tt?b!~D0{Y|(w>W3+F{Q=Kkny|-|_Rv@A!Fj0X*_MemU|xejfQ9Kac#l zo9FoPiCpsI6S?HaCvt%^fD5DnT=L@+b09xHkxPEu%_ZMSe%#OV>yzaC`XruTpTzU) zlX!l863?$s;t{^q?a2+P-P==pc5O^u*t%yIutZyT?Wu*A!$bg-V>ebr*^L#Ic2h(# zveEV?$`SK!FT?io#NLGo5f2nHw%g@-i`%!S*xo552MQDywlt?|n>(6Y5h$!zU@0Vz-!2KR@abn>>i}t?(Msit>n1Ta+HM~x3o~Sb0a2vyV2v- zG$~H7RUax)G^-+^VyubXEo~cjrdl^{M*bTy43*Fq9K2dq$pLh{a*1nhE!Q^JFLiOO zk3Lu)lUeg*B~r~?;ucbq^y&I}SYcEji;NA9_6=mJu&6iIh3`bt{mtqA{#{sRiRu?% z6zm)t!taOS^f6s~lN&+Enx6Yd0IwCgIi7^OPaVsIKXk)aNiBfuh2Eq$C-kJgVOqY9 zmd;BbJJx>+tFNf^i`5Q^H|twUH2GsA($hECE%a^rIh0$guFdr&r!Q%Cjt%aHrYfU4 znkd?~eZ!vCjg|PI$6u6N7NuOM?}+Q$br>F&`S|zOIQ^K5=`f_CW9i}aKnBafq=^yP zUKhDqmD^e9d-Z*UY(Koc^OK7gxOEJP@!rfRH@vQ0;BFbOfWMKXC{cSVB$k9=voCe}^CNH1-o=@{gI@@7+@kaH5pl%Eo?M8^G zDjd|rP7miDhaC>4@S8Og(_tO%#CWO_gPNEaUfwN@sFDUXQ5yc=Esdy>1~pL{BZFHS zQ6&v(qBO<~w=|+k8q`E-T1#;?BBDwf)I{k9uQZ}c8q^GG67Ch27sXIo(w*r_jrNbF zXvLOSsAKvy=$x)XYaka>Rsk{~BN)ppE2Dv9T`Hs0&|p74V|b%4Hwas~fegqEt?wxw zaVr7HfCOl9PXffP1Rw(vpwT@E5VsP53`l@>_as2vN&qq-0X4m)k?u_ASg*3$+k6>8 z&dLa6Kt`|%PsxZ|2|xxUAd9gY6U$r2WBOgbEFfWJ0Wu&9Sc|7j#H|E@hExlya3`R+ zNeXqcG(5npkR(U4p~ zaXzD|b&Q6{fCR9N;;y0LjO<(V0td_Aa9p4A73|njZJ;gH!Z1AAb!>(n1r+SFnOetY zhzv*oGw_t)SV(Q4h19|f64vmY8I0*)^=05#42e!GvCd~P6jyCWWIzI#fE!|+V;w{W zB!CG>6QehPSog%6#hCtGUnY*l)CF2h9W239s$(SdD4XxLS#S!G`Xh)#~SJa zt)b3m4HUOD7ibN2K5L-3l_1a>>U`EfaVtTfHPoSrJ#}zepB_!D^lD%0Q(TomWIzI6 z>#ufNpU8j&Xih<`K7@C;!+kVg_`4V6YNzdq49LRQ_N$$?Co&*`ukBYmZBJxC0$X^ssK=W7w8^Bw6{&7I>3u6X0cesI*gfbW+C*oM+GZ>0n2?7mf4Q#;qK{8C< z!kF(X)Ug4%)Au=F=&tld%7DHq}0-wdKaV&<&fCN5^S>sp?kpT%{2Odp3 zCbA~bMArCBgyNQ_15IQN+T2ruV-ECaBBZrwVRr(Gs}hI|NZ@PywNB#`8IXV)-!$EhH0SSC9z1C@IA_EfmT6(S1(nJO%@U`?>r=^JuNZ@PfwN6VD8IZu&(rcZTCNdy_ zucg;IElp%V0$)q7by}Lpi3#d`ElqLN(nJO%@U?Wk)6zr+B=EI#z0=Y}1|;ycbiLEk zLW2(A zhQ*94z20PY`0-pt}b1ZLRkigf{4NglF8IZu&(hW{a6B&@e*U}A6OA|RWV3`T+ zS>zgCYpTJBTMJ5{gVLZ$y=lO((|`_2gI4vX0mDuMIw%bq)|&Ky*+Vza7-L z?11QiG_+Lc(E%|my%8Oh#%~9-RA{FOwgXxx^p@kY19})#j^7SwjnFP9*bZn_&|8kn z4(MS}Iet5!B|*EKU^}2iKyNuNJD`U_<@oJ@76$Edg6)8o0=?z9?0_Bym4l|9X0L$` zcgr_@<}`msF5{r}!hnouRnSv7F)YAD2c_{F2dxy^X@ZS|)&afcxQv4y29@JC4q6+u z%Lz6PS`GA;<1!9<7*vkmIB12?E+^PHXnD|Ej>|acVNf}KH;@S6&)4%+1gn+mN5da=4pg&qc#18b0P_UKg-eOD4Q5Bqa*84s->2Ib;69$GlG z(FPk2EfwZtXMFl(U(7t>FVkg6Bp6gC48vPnm(|d+Vo(~t)zHGCjWgJ4X#LPzj>~H3 zVL&;wgy=~_467WXgVMkdylGrkLQ9N6Y5Z0~D~onH!B#?RiQaNtRzeSh%0aVx)3|Jc z)*6G-_-%rg7;S99HbIMu-f~=aKo5h;@!J6{G}`3^+W{>tddqRy0X+;V$8QI;+-R2* zYzMT!=qZO7RvMxM%AqwzZyJ{!(8HiKemkIbN4uP0JD`(ddqRy0X+;V z$8QI;3~84WYzMUP=q<-(2lOzg9KRjVVx(P8upQ9yqqiKF9niy|a{P8cOOkdu!FE84 zke+ggVWlBDpd4C<^rmsy0X+;#>zmYvX<5= zdDGB9I%YoS%|Jd?g-UuN(AsLBQAmcJCeSEqt9?cx8FrdLqo}R+8HHrnX#$O+w%TVD zl3}L_G>Y14pHWDLohHyIYO8%lAsKd>K%=Ow_8Em_*l7ZdqPE&+6p~@52{ek@YM)U^ zhMfivqXS2G@-YCV*hp=if#6&`fQ_#)C4&9WHA`%f30D+ghk8JA5t$a5UZBMy#ql!$3YOxtxz+^{Rp>;NNuE!(xC5&&e6`)D82$dk{-d2 zuE{~F_BW1op~CJ&*@2bGMWi9pNCm^(Xa;?lz-8GZ7O=z|v(h}K9mB+Vf zCBr8&Cvau}zC`F7J%xSqbks+b)-6+1Y@GR$o-t7rHNB9t+JPSAdEP6JDe<$AU^lB~ z4>BJ<(K!sQWl*#Hp`IRj_DI5JLbii5Cqo}TF^t1xG790@OIjv$a{g#T_MBQY>v=CC za*nMdX};c={3M+|y5n!-Vv>}f#zm-^(GqSvXo;mxOS}j&5$TL{k@jI`&_Mr)(ttTU zg3%GxR~%IT2v@%kqww&Ff%M2x95FDE9_>Q+XbiO@Z)GO9&Isj&&PmM-)l-aG3m?T^wHLdONX)xWxBes)vpU5lt2se z1PIu%!-UCQ!M*cJTO6CmrT7-7p~5U6;F)hs)3wY0OIbNRIG|Kp2LaEhcN=8!`BZoE zbJ39u_N&u*HcBB}ZM5c&fYuDiGOReC0z~BXk!z``-XOc2qy7}FSCJRBTL~Pr$#vW& zZ??r5oD|Q}4@krlx`Qgq&JNZ6cYAzL#v=08$lIubH%i2g-%gR|!k3KJtS~^2Egof& zAK&)x$cLH)H9M;8!GkK}lQwm<$ohW=nTWh2ax2yHotVM-bM4Obq{sS4EAczTT(T73 zc+Z(s0tkeIU}=kpygPCS<@+8v8jOw)jo<*8W0(LApRgh@io4h--Y2xTX*b3-Bl3Qs z-K^b0)Cb_9tn*WF0uE-e6OT?2+S|2vkno2fVF_3EUwVql8XL{f*P}qbS419&JeYvo zLo!o7QN^Drb1T;i?N;rbl<9|Mri$&(R75_)*?kn9kI!VmrW+4JK8{6bw`uR9tUgYg za`@~vZ$_WwjPQBMd{nQJ{!*Ah;A6^Er96YcI>;tfnK_PG-V)E@HS3q|)wPSfy#M0- zo^qcz0hV>f4I`qt@m`_b&W-kYp}m`_F9_`proJS!_b~Mpq20;U(?WYMQ(qU_T}*vb zXzyd{+d{jWsqYBw{Y-sVX!kJnJ)wPosUHaKUZ#E|v=1`%6QSM5)X#+WA*P-Y+Wk!Z zQfLn_^{mhyWa>GgJ;c;+h4wI0zZcpgOg%5ON16JQ&_2x63qpI0slN*CBTW5WXdh+j zpF;bXr1CVOJ=F;yb8 z&oDJpXrE=ORA`@LYPQfm&(s{D{SQ;+Li++!XA13$Or0&XFEKS=XkTWkQfOacYLU>s z%G45}J%pb4W_Dv_D!a0h4w9`RtxRhOsy5#|1z~sXy0L~QE2~< zsdI$(U8c?x+W#?ifzZCkRFlxY&(sE?{eY=WLi-_8TZHx_rnU<0$4s>f?I%pN3+<;& zT`07lF||`@KWA#U(4Jvxuh4$M)PAA;lBoki`xR3Mh4w5{7YpszOdS^5b4+y#?Kezy z3+=Z|^$6{EOdS#0@0q$pXn$a;Uue%WH7K+{GIdO7e`0D_Xn$sERA?_SbwX%=Vd|vN z{>s#)Li-z2r-k-+rY;lOKbU%@(EiEPr7oObc3mDgl;nRdZ9;{ zdV|pOn0k}Y^O<_H(4$PTaRWVCo*B&t&Rep`XFjeL^o~>VBcmV(LMm&t~djp_eiB zsL7pfyL1pK;ypnaqoV-FQ`DzH4Lipb4> z09$yb@^~IPmn|zXtICr>l)2FYlTpXag-Lo(pJT}-0eQ-Kqx&$U>_uy`7p=`+v@Uy5rK)VIwI=&q*JdwT z&!Wp-M6c=)rhi9R={CEZm3FfeR{G6OSZO#rVWs2jgq4=F6IObDv4*Ato2s*GJrd2* zen~V-`z6sV?UzKev|kd<(tb%aOZz2JrPm<8#pe@RhZnL^&knM4S|_HXs#qjwSoR%t z_#%SNVR|e$DLDIJM3xI0cU|WtvQUs$^&g}7BKVwh=UxP#eH`73;N#=BSZGoW)1v%~ ziP)2rNgKgA(2?^B8gBXQMs?03iv^8W))9{_8(1c2`eez_5nwD8*htP{ku0<-z|1B& zLy{8&RYM(zSSyc~WU-*eS7P>wlPnozb8bm%=I~;2*3==$ak=y3c9DxVF9K4YX2~Ff zT&I<(>yXPAue){jB};~2m0eRF49TKFGew0!igH)ULJ9spA7pSUW9s!%Q6Y`a<1LFV z4KOB^mFpBvmJRARN|vi)wR@1UD?xc?CubMZl+riQQJybaFiFx0pDY;Ee^kMA*yW3s zYo7=DqS-mK+7J!8P7i(2qUo$qm+gdDFG+e$C#0=O*s`#Y?x;>CWt72kG>&=4yWnQF zy_swxE&;AC+83zH(N9e$jstZ1$odlTY{Ar?hGiGWqn2 zhD<*Fq9Kz{zi7zh(=Qq_`Sgp1{CIMUzUYsqiNYa2o+b*1{CJuutn?e`yj-@xm_vR% zP0Tsu$J0dNkRMMIg+qQkxrOQXK**0Lzi5{BOSxugza*Na{gP;w_DiB!+AoP_X}=^I zqSpy02D4u{Ghi-)<9+EMVHOB-X>|TCpQ+0-K`zab33q9h6b+ejfC%#YBt&kX4=HB3 zpn0B8&NYJ#8UjdK9cj#228~Tp$T{hl1%uq~gaeRSG)Q~SxyURNG?VZgm&{^8Ykk%! z%HbK=hbxC;au0`-73K_elc9D_WR~q2C3mR-rXA?>3>WXWs2XJBO(|gmx}Jy;ErCF?E;F&gZ9h3+)2t-6OOl^X?T| z6Z7s9S~FAk3vB~a4+?D~Qx6Mm6H|{0Z8KAk32h5g9~D{)Q;!R6D^njA+BT*>DYRCm zo)lUeQ%?!4ovF_XZ97w+7uto4>I*{K!PJ+8wv(x^2yGY3JuS4|OnsfU5;zLyja@?9 zqwOWFeM@NjnEGF#?dKH#PiP%X{h!bdF!g<*UBqSlP-q94`mxXsG4)fSUCh+ag_dIK z7eYJC)USk==3IU)v`(geBeX7l`a7X@Gw%;V%P{pvq4hBJXQA~n^%tQXVd`%}>tpI4 zLc4@>`Ipd+N-BzXkNr%ULK|QzPiTWOMKmh3A*SL&JH}57gm#>Hg+d!+SN>9 z+skX2I#+1du-y4VdmZzVLVG<^%|g4DpKcV|8<^TGv^O%Bma64DU1|h4^I^PXx+|YC${ztcLRQ1{#)qr zA?(RHr*E)t6z9XcwR?TDjI#&Br2|{gz;|Y!mor|X6mX*q^qexmOHI!9bw*r>pHvAbfxO<^e|4A z-*~bsBX3xZMqi7)uoe^^X`<2BVP6=ef!?TIrfU>K5|~MMD#7uw~B0O;h{G6i-^tyW-K? zqPOeXB1=2iSezNgC5crdLu12TnZCiEp{iYyZ0#FFf4L*3#R-!Ok~*xvg*Jtuzr8mR zeNXf*Yys>W;M;ELYJ)}Y1Ys(;JNo_vAl;J{q!yryM(@Q(Hx~R!ZrF`R@6)vkyK77$ zB{gz?Jo=&N187jHRu?+eTGyaCNy28&eZH3QJQRI6fxI5UoqZNOuV6Ha?S`@Lp_ID+ zVTbF}p~>5UD(&<~Z;q}Hmv~YX{YdnqiRi7-k6|e1UiAbzJ^If|R|CFi2g3H#yyIi( zex#cd;3DOno9M#&5O)KBDHw^!AU3m6~x_pM}@>$fNRv|(dh=}g|B&TvAJJc^G zqL)W8c{-1E@D((PT@TmAok$URJn{r}^siw?!D+vNIS42F77Fd6drw95fAhadQrN3A z%yq_z)wZ)E)kmY>)3uh#b^y!9vCYx9$KK~ux$Iurp|!(Lak^v4vaaim=F5&R}Mok{;uvzr&=7lm0>ImvYiS zA}Ky5lt~em*h$rOpX98IEtGQXYfg{CAz>TQ3|j*>Uv|O2$D@CX{zK?5=Mw%U^jAtM zrVITFrc9&`@T$>R9@=3X*S_q`^dyIe({MfKEC~>_Hfwhc;r`by8Z)W}#ztwluG)vx z$1>eA^?DJD#$s?tF*v=|PHU2zU9a4!D~ny3X`Y8Dbr(I;LN9GibmEsEtzj{*`4TXLcYo!c1G^iX9&UFcU?^&frv1b^V zskGyhlFDf8O!o}KVpEgE&W^{XtJH+$V!b*u&+CkF2n zMQN33+68~HQ;fI!|F;TV9b1!#em@42GUznEeCe@47==GiG;wa*bnVi~6z8=$Z|px-DqCRmBeAvws)r55ry0L!Gk`c(>dGNUR>6p2 zlksLwu@@Ka*geq^#{IkGT3;hwYplbaBR*x2m-6D$TM~I4i(otQHJszcLcgBv83zj) zbUY$AF9?@|z`R{vYD`(YiL=PyR~u*1EA+Q=7JZZjh7!&Kgx5mw6Y_daj7`gL=ETQ@ zeiJ7iro=EJPCQ}gfGy(pnElHM+pTZlys(`)$<(DZG=EI!Z|4kOuDVQTdRW9>!4~~W zN`g<~KLIt!9x zAiS-O$C1A7{)~vdpY?=2*Y_|WtbUzj^!It3nH-#K?fu97jz`Vd>e&6HyazB2I{q5J ztGfa1A+GtumOd!Sf7gvG5Rb+_Oe%hikl+WDK?h>8;y`#62TjK0+0xR;KF-Sf1Q5zY zz(&)l&IkIyM7n$Sy|5U13I(QNLpV$|ua$iK{I%{IF zFZ+JKs-Jej&YU0a9&*+d=EuHDzWnKgR)OUN{eG_2H-!EOQ{O@{bU>)oArS^01IjTF z1|90jF%Vw;V%6#uY<)j~474;fyi>$}#N+Ibp?uOa-P!lOfkpPebD_g%>0GW zA7d=Pf@Sp$cJ+^SXR7cWA>I8Gjs2SP#>GQ@oxI>=3rHSjgTIOWHW7O+_B+7yK8wcw zfY~^uB_Jo#{e9gc_DA&l*z+;$qJM%5eSs=z`C1|jI$xBl3}Tu+Ovrh6wa`Dw=`aQU zjHKc^rLlTC5eA(c$~l1Wd9td7NFLjOFcPf!ZW8xY}3Q7iN>vLp`wH0ZQY&KrbJ z66k%L)mYb)Z4^I4=wIPnW>GFyw;{rp2E)r+IZZiMTBVHRhJ@z8L5E+8E$l?umi}(`eVKKFl3&CRQFjH7eJ(7(a3 zF{l1EQ+4ET;07*_1L{tO3bh$@mZ?+?5eA)D$}teWDz3${H|KvImc5y}fIea;YmGNC zFwC0ryI?tlbtAJj3H|>uhAoiptgfkv#c?FXg3v|2eSO`dM=-5AE8dE(7;nS0Y9E$9 zTx%G%hwkYc9vYF{D!vPSKE9i9;?(e1d@t$5 z>di#>bOH^^>QZyjq9>Z`pwNH7)xDS!TfKw`Ut%)K;gMrfS6!UA8!uH@vpqupF=umx zvaz}s5x#8TQnqp$th{bx3M;QNYr=J$vmV9=tkg2&!}6dE5g%p#n8WYJ_$=b%%s(mg zpD}<-34qmCiSPobMgRTV2hQW~o-6X7eHbUo53rw{R4 zSQ&U3cL8T}>jZHqWUgar{)H@BON_rOp+(|Yo{Zy_dzJh&CK|s3rBu>lKm97??~mmZ zd>AX@cgEja5PwhnE>O|K_!c>Sx932XfRlb?qI+F7ThmRqL^S?k z&zLVu`R`4w7_`1Q{*grdu{b_to@M84y-uKMf&5h$e>|?uh(CeFd}_WK@lPO0tP<}D z;=6_ZN4AGgFzs$*^7vOPR=ai_&V+dmd4j{e`D%P!qAw)d&&mR z;b~!*%=@~CJQ8`7a{VUWVzTjkTNwHL^gFbmW5W(wIkO+iDUQ=*>V+q&|6RQEiT@v7 zjB@7R7e<^j|DiAhQ$NN+W9*&6DCX$TgfWw;XM|D4)GzU!`H{MHvG}vXIFnh=38R9k z-wI<9Q@k+6 z;vBxAYkM7K+hf6mR|8otNjv$j7m30|5$3^(X(HMiJ%ZLw6i>@fluXaR(bP08O8;Q0 zQ^IdCc4db9Fr&IuzOqZq!Uu@X3lVj>a%*~^vpe0E8BO=3yGDnGPel`D@DKRa=i=$w zRqpo?Dk%hx40Uh85jFjpk;>Mgp`&BR*1ML+)g;)(@g$UYK?g1|P5|lL0G*hdC{HBj zB<7*gnC_Ijek7}9#Z6;_a$T|-jkY;)c8R7Zu>OWqF0A(V**?E9osii5?#O!2g!~pH zU<8#SdIjr#5nwDXK_gU%=+(?x2G;Tt%_P>7%vuFjRf!fM))$yn3szl;mIs!0Q1;{m zraOn2T8G^LOf_OR08{5+Hvm)Tk$Klv#}b$e<rUnT1$qhUSTBp zX`e7QFm+TIo0-DoqnG7|u(N@w6yWSF{L7)O}8Ll{Syx>Fc~Ox-1n<4oNxj8UfU5eB~%N#Mnz zd4vq(K4I|Nj>P@K;I|S9Z1>s29`s=m{R^Xe6zD!&qQwavzp_YtRK#ZU!^iRPi4rYA zU1f|bi_JbKn0gZ1N0@p_#O85=&mzI+O0)t>(99acUY`w2VXx0drZ9$XVhUp@zaB|^ zT^Lt$ZN4dt*D-}Llo!Dh-x0=j%=@k|ZeZ$r!gw1~KM=;vO#Mh0?_laD!nlno{Hn&e zg*dK6B%XcP-^%hFnPc-qXg2b~JJ++rJuIEH-5m)KAsM7CBG=VC`mNV;lu>M%0 z6%y;5*twMB3t;_adj2gXS`oO$ySe0l2;)ws{w0j}NvZ%t1X^fqtiTk;J+MlH3US#4momuS<$ z(yr!8?7*fXrgjPA*PP`ZVf>b!{l!#r#MWj(gXNgu! zmhdlrm=UJIRIf1enCcT|jH#p8x5NP8S+C_vz_Y%AspG;dV7U=t7BMv@V%=QWI0`#i zqLrX9a|SQ_KN*N&`-6}(EA<^1dl5gXtv-~|id1!qteXYs?=3UfYF zuXD}cf7U1Uwr*XZB>>IFNXF>)O`hpt@-h$Vd1^5Yf){6*73vNUo&kP(J#dtFRMKed< zHy7NJD7dKr>(fon^kidyW*{>-YP}`hE_dQsvB{9qZ@6fx;MPRJ8w%bzJ@TN4ouFT2 zM#1gS>bq%DXkv|2ZkMPW=-OL3a!l81C(fOQ#|B6H1~OGN0b5tK)t*YJG=O|(!Fx-z znFV*DA?X~~3ns;Fr**y9o!D~7@$Q266Y6_J>~4m9FCc%gL_4G4E)jczS@(nWK#5jL ztnV}HVXz)4(Pk0rpUip;tdEpvv%!i-nT4^V0AoiPv5J`WNw7XuqRpW?%;F}ss@*hn zGSj^WzeS@3PoabFX>Zw08_*^Z0`|`qd@f$_nS##?b0OO)#+mE54}D3POPKc+VJ>It zX<@En>g&?k!hL*Gm^IA$wlG&S^&Mf>Glk6&=8@Iav4ZbmeHv6!9I)a`mX27Kua@<%xU|6Xp(Cj7SJ`H&cS#KOZNY!fBaNfsF#V z)+H^kr610uyH5#$Q86K=iDF^$%t_238MW#>j+0O`LYx7a*z=-Pm^?!gvt6~Ob0CG7 zBWo?@Qmrw;5%Yw}b0~3^FuNHJW`+_yA?O_I#MTHQ7I5*EB0g7Ip}-FZfgcX@$S}`k z7JfJg{BSsvSO=Je9}WUP9L^$EC$sRwLEwkO*~IE+)>^RYOSB4NUB;|Nu-2Do^NDo@ zv(5wS{1R;ev94xT6Ijh9S|zcrXVxaLHkW7%iFGrxwt}^-L|a6x+oXkvcCfaWXp6~0 zdb!p+(bQH;;u;kk{Ffda%=C{$1^SSY#$sT(Yk5a{f(_V>I(Do-)7`Qi7O_|CONc#U zKh}XfKU!Q;QE>nsmfsPGgQU`n#35n!GlGn052LiBJU82*O& z0fxUZrjBC87ZL+3F(}NF%s(c~mobGp=)*#cvc#A$FJu0=Fki*gDG`~)Pciyk$vljH zuVD(KU!)ToU|{nuRq*1Hc$K)EAYXyidP|LDx+${$sKCov9FskAObB{4E3Oh(3-cPz z^&0%Bu~JAw#^I(T$D-o(32`lnUCUx`6y}?lx^6-O>d{egy@;eK^BcrlgvqbT#oNfw zcMEY7Ke$<#{PJ61%!<$zJwn{dkKQTFn>hb>;nA_-p-~~;&5!O7=G*zvooJ%2G*0vt z;x2ynK5%FvRTC5M7v?)z>;w2=i&yyATqMK?S?)ez-p&v2N8jtu;K_shh8WDnCHKMMc5a#>&$)|u@Zc-DUCiA&LJSEI~ z`O#;E`5~r0KS6oiKwl7%LCWxp0*?Pdmi-FpXmq$!h^P6{*U0B!o{Hs?5&4f0-;h7l z#5bYmBRw(kZJ;~S0|H|Jzxxvy10wxts?_%g))&S1g~_kt#1Dn}F)r%IezV~w{b@q{ zj9T;KEcFaU(T1Pm=&vY>c6*AW&ruX@#glaLJBq$fm^@P#&r=kwz|(c{XNp4gJZBew zrRZbA!`Yd#QxNa$)|FsWXN70#j!T^KVSe7v?{i!g-uJQ;S3-!qgHGi88fJL=sG`K*Q3l zZSr*i5eD7O#xW2E-L%Fr5C+|+#xW2E-HygF5C+|W#xW2E-Dt)!5C&aL#xW2ET|dS# z5C&Z)#xW2ET@xl_L>P487sm(-UF*d$!a|pHag4CgWm_C0EOez7#|VqOJ&Rte5Mj`D zSNx2y(4|%!BP?`96~_n*T|OmaL>P3f6vqe)T^_|T!a`R;ag4Cgp}8C*EOeC<#|R5u z%)~LmLf0>GjIhvUN*p6BbY&992n$_+Bx6JvbhQ!32n$_c#4*A`*Aa1yu+XJL93w1r zg%HOG3tbe%F~UOE{&0-2(B(cHBP?`P561`#UBV+{L>P3{4#x-!U7W))!a~>MaE!3f zWj7onEOey}#|R5uP{T38Lf6o6jIhw9G8`i;baf2J2n$^VBV$Aubj1tD2n${0!ZE@^ z*RpVou+Zfz93w1rl?ulQ3tgDPF~UOEpKy$@&?P4vBP?`f3CBQ~@>=C6@6H1n#DPM^ zK_LztDh>*9AW?Bphy#m?gF+l=R2&rIz@y@z5CRafl9?CKH5FVaiUC& zYIa=WqYY>3xx`1i$5dS6qYYsyF7eUMBo&wVXm65=OMG;nt%^&0v_DD3B|h4Aqv8@D z?Hu7aQDzNoB2jUPkG7GhxWq>rEmU0MqdgZYF7eSe3Kf_5Xh(&LOMJ9VLd7LM+7+SV z5+7}AP;rTmb_8&oD6@t(2dKEjNAJT`T;iiw+$t{d(YtCDm-y(_v5HH4^rl$FB|dr$ ztl|_M42@-G^n`5M}vckOMEmusJO&O z1B8l8d^AL;xWq?;go;aiG)$}&e3C-k!Y3)jEqs!iQQ3|61N_1^!>?trQ=>lM#jEvN zH`C2xSYmTtnW~qS_IjnYxW%FyoFbw{SL)jJ0onhz-|Kqb`ts{y4`TJ)dC99c6LcO7j@ zAKOhYzVUXRKEZ1r8|cgoD^5u(zIg24i|al}LNTXv#V<1Ql z?~he7$pL(=LNl}o{_?dLPN6QLZ~3ugTSA}h%Mf4a%Mjn^%Mf4Z%Mjn@%Mf4Y%Mjn? z%Mf4X%Mjn>%Mf4W%Mjn=%Mf4V%Mjn<%Mf4U%Mjn;%Mf4T%Mjn-%Mf4S%Mjn+%Mf4R z%Mjn*%Mf4Q%Mjn)%Mf4P%Mjn(%Mf4O%Mjn&%Mf4N%Mjn%%Mf4M%Mjnx%Mf4G%Mjnw z%Mf4F%Mjnv%Mf4E%Mjnu%Mf4D%Mjnt%Mf4C%Mjns%Mf4B%Mjnr%Mf4A%Mjnq%Mf49 z%Mjnp%Mf48%Mjno%Mf47%Mjnn%Mf46%Mjnm%Mf45%Mjnl%Mf44%Mjnk%Mf43%Mjnj z%Mf42%Mjni%Mf41%Mjnh%Mf40%Mjng%Mf3~%Mjnf%Mf3}%Mjne%Mf3|%Mjnd%Mf3{ z%Mjnc%Mf3`%Mjnb%Mf3_%Mjna%Mf3^%MjnZ%Mf3@%MjnY%Mf3?%MjnX%Mf3>%MjnW z%Mf3=%MjnV%Mf3<%MjnU%Mf3;%MjnT%Mf3-%MjnS%Mf3+%MjnR%Mce_XnN7LpbhON z^n;tVTR=C_4Hh!Qr4us5jS&b-=tcz@zFUQNsPH{1yic-8R^cNmd{l)WR^ekR#Qg}e9=IJrhPWF+hPW9) zhPW3&hPV|$hPV?!hM!d7r&Rc)3O}vFr&RbE6@FHQpHt!IRro(D{DKOsqk49{#u34sqi-{{H+Rqr^4T> z@DD0{UWI>D;h$9aXBEDn!oR5SuPVg-1hPK3oj``Tn?Q!RnLviPmw-aLl|Y8LlR$=s z3QZM8RG6p2d=*Aj7*kYDM}@dwK-LGh3&;?63&;>R3&;@n3dj(*3dj(53dnH23KyubQiTguxJZSIRk%cj zOI5f`h09gALWL_;xJrdpDy&vvjS6d3Sf|3(DqN$&wJNMv;W`yIsIZYj<35}auwFk$ zGm74TTAjv>fL`3Ld`#b}X|2nbJ*>C2t$0eyTXEn0`mSX&^gYWT);k{7QxEH1ZOfOf zcv$b*s3I0SYfsrWDk;2h=ee)bTJ-c!85GsL@|VdO)4DL7fT%g)LZ93hFiwsF&HGPKSZQZm?`YC^a@_>514eHu3 zP;bZ{)SLcuP}kX@-W&!BuXnSxshphWa~@6IV1s%~7%042o>EYM_JDeu4eG`)PXtB2c%7ats9bDHk9$D9!v=M07%05F&lc3Xaxio~;Q@8K4eH%tpzg>X zR8E@mf_je)>dr7w@68_6`*P7#fk#t!+o0Yb1`6ANvu(bdKu!06`hX4U-Y`%f%pO!u z%{R*f>OLFPhr&SJpFOAtb7{Ug9#9Y2pdJnbh20`k+I(|8pdPhBeK-sh_NinG>Z7@6 z>MReakJ+Fe4+Hf?_Mmby^s_ynK5m2hL>Q<~W)JGgTr^eb0rhDc)Kg)gK9fDDoHVu2 z1M0IjsLzFg`ur4wTHyipKQ^c@gn|0v6oabqfclaR>dRrEaFRf_z3=HRNY(f2BF3p$nfcl;d z>ic1!elW$LG9FMrv_btS4AhUO7}QY@sGr!Nei{bqXHyJn$OG!cEhL3x)K ze`$mIRT!verx=uXdGXgasOQ2!{bq_mz0A{mzqLXAE({blsZOa&c$Ej#A8b(1hk?R= z*=#}OGR$aRKlLXY)StsZVe4+TpmJIY@`Cz{4eGC9ps$^-mkrzd}IK zi4xg@%BlGdyKTzQEl`FL2FlDHR8E@mf{NIn^1?vnXAdf;MYFU=Q&AgKEDTh9ia~XH zKqYKY1!15>)}V}{TnxR-18SNLYI+!`;;cdGIW?abREZ60Mi{7>S%Wf4bJ0|{M^m$G zP_x58;cMM2U4k(;7f_x_o>6XtnimG@%&bA_Ir%9ssIzQPXNQ5R$QqQf;6K+?r44Ff z7^p>AgUan4a*xNR7Tchfgn?R`J*b?T&kJgq4QhE9s1;d*%FWPwJ(^l+gIW~^s_G>L zRc(W+2?JI8l7gzUL9Gr0wI*v&xfyz&r}@^}pz6awt;-%%PKN#(52ywkRAU&Z?6;NV z=BK=%&apwA8wTpUtTmNe@AHB>-v)I-7^q~{pmG~#uJJTqlMSjl4Ah3KLFLwbUQiot zP@BR)ZO$H4PO}6rs4X_AmM~CTvj&x$OSsn4eA{eLtzn?rrWn+lJfPZbP}{>m;iRc7 zCwaLU`Yj$%J8V!p!$9rI8dPqE?gh2m2DK*))ZXktjJ1FPC+6 z?H!)xJ79ylC=3+N&Bzv1PGjG@J)jQRpe_yrg#$XW1eKdjc|jevL8Ze$b!HDLC!6wu z>asy~hk?S;Z&_+8Ha#(G?TDoV@v_uZZc`U8sD2yN zK$xZmvj&x0^S#H@d_y*TTJB%E_ia=CP?8ZBRFbfx0)-V+Au&a6S@rYSF|_u8QD3Ip}N z>_O$!`@Ep+UDig}E^9h$IZKb8+YbjXD0`Q+5w^>kj(dIyLD{>kjj&zTbmDZDpmH>tzK}Jj++2be)E8|~UkU^DoRuqtjIbQ##CeLD~D!jj;Xbbn8KupmMV*FDQFIx)HV?oi1R=5>##;{TrU< z`>t(M{}*Oc-+M_xecuN4gD_A(%oW^Wd{**PS+??mLp62_r4eEt3P=9$zLH*SR z^|vrke}73q{lfr=mTH=n6lpiDgk6y4>MW$(+)(7m8c8&o6=6s{G@ z7F13%PcNu^8&ot5R4i*ydQLyFe(!0%xD6^12C5)?P&w`3_@f7uut61ufhx)xlsP?@ z-+f+C#WtvtFia6TR<@9ZPo(I&~HmHg)Q1i0~mD9-*`5sUUY*3Y9 zpm4R-RN9oj+5>8l4Qg>1s3k8csHHZjWnrL}Pcf)99!;&VL9Gk}wdy4WRb_*!4g*y) z#h})DG*xSZstW_P`XvRm#s;-E3{?FTgR1vvYMl+LAq-UGOA2be4eFdQQ0GoDsC6Dq zoo9nOKMd3bFDa;`4XP;&RPz*rYVc@kgAHn97^qEIgEF_|F!R(e@PKNuL2V5KwJmE< zdQJxzZSa6s6T+qq9yYi0?`Oy|;kEgn#v zwoP?~*;IG-pmMUQtsYPr8&ppisNU>B_2r_e>pY+?u|XXT1J(bMf*PfJV|JHkNWmhvez^mlqd-D!h*Zy2b%rWn+1 z9#HSILERk&>its;>RldC_t>C55C-brDF$`B2h;~`Q1^v_`p^`E@_a^a-fx3?APm%l zQw+-Ud8TQfk8XyYk8WmvKDwFHfc$<>^V#R4n_=gpo7ta_o*SrpJfJ>eH{VCYn(t#% z+Rz$uLl#nqp8N^fcd-HmFaBfqH6+LEYy8W$)ZK z!*=eQ+3(!X&CoyO0cG#pH^X-Bo7wN&&kfZ59#HnqeKTz5zM1{b{oFu3-~nat+&9B^ z?wi@~+|LcvgC0=!&V4g%=f0W!&i&j#J>&sp@7y=TcJ7L+nf=cF+(3QU1IpgHZ~i#Uqi4T! zKQ~a1c|h4a_sy`K`)2k#_j3c~ImE%VckY{EJNM1(ckbr~%5w^UY46-O!*=eQ+3(yp zf0N6*nI}BW_gj0G@VhXZ`hC{3gxp?2dO`ic2K9Uxs6S>6DmP7i+@q;K*`WR$2I_^Z zLFJ|?FQ~uRp#B;L>Tg+t%1u+B@M!AqHmHAuf%<3GpmNic7u3HjP!TNzR7B4jRBoF3 zq+3%F!v5;-n5w54FOPZ^2eKK9EoVV=JNC{oOY`E@PUL-3lSRgVZG851B$QhARwG6lsw=mNU z&(URbS3DXi4^B>3HA6%tCyFl7rZS_E+1grUMOQV)4X~$!F&!n$i=3%SaKl>=oWBQN z(Y46Sh@6E?DkBS3CXKilny!YggBamO&1!!TQe^PFgyo2lkdd^EDfZJ3*3m|LVC+9oMsXSOA@+a+vw zm(Y$9w#yQB1*>ImZ~+rdOcr377_x=c?wbVkMZtMaREsnSsh0h2&@he2ep$l7$RS+X zPVVGF-1#0s7+W^CeC4B&OmGp)SjO&bu}Dg}gjnP-DC&x_NE(HiszYBat5j%0a5_Y$ z;~`b8XOgO25?t=Ys`c9K;i+1$UA3c;eq~cm)t0Y7)kcDgm{_#|RYWW@NZONC8`9RH zYUBt|r2!N+h`%9OrP0WkDsWVb;y+wvzYGPIMauHZ@*j=7BDmNsENN@BC~`vED{Z+b zG9G!QEVd|el8U7qBd0)7I~7GP1(heMmx0Qcpvv-*e0pRYe<$&G3V)a4?`0C;tAZ`` z)xp3fTIl7Z56eO?mswsFd5yB4gTO*)5?tp;BX11Ob~Q`c^-V-xtJIu`PywXoMC2M! zRNqA8b)X{3madkC7e|m}I)tY~Y&rzUp57E(x9fvJWL38tB5w&cpqqj-ooGN-&0==V zVq7!JfL!%J9d3@?GNCgrUor2|$ZgpcNF9&dAazU2VyRnNo$>8f!RUlmheW~eirgMB zskk$Ey!DLQNc`Sl&EFl2IUCJuZwr`3JQ%qrI7bg2XBMH|98jqTBll)ksSif(QyOW8 zLP@35mpvG{|1+2{Jra4CNCIOPy^;Ra^nwYq5=J#$nYkW$B=TrLhL3TEA47(Z{hJv+ z9(f`l!%uLAPa?xl{F@nmI`WjVK4;do{GrG_A3_zgn04vrYBvH9&*DC#yabrkIX@fu zoa#wV)^i_<+?##Yn09)y)NcR(>|F(JJCu8JnA^D0ia*mMvvoZ2IA^Dmy@_HfpH)G@tLh>KR$Qy;^ z8^*|+gyg@Bkv9v;H;s|Eh{%DGG4cmOvcEC%Rv|gi7ZjAhqkX+Chd5@4>*cf@Qkc^FyKNgaU86)o#l1msP ze%>x82Nufay4V*qe5~GW8`B(a=bC}aUr?3G4cr^xsEaNNg=tOG4dBe zasy-JQ$lhhW8~99auZ|ZGeUAxW8^P|dQDfv^gyf;d$k&AA$BmJH z6_SS;BmX8Ok1$65T}U2fjQod?JjNLLx{y5182N^fJi!?GPa%1dG4fwRa;7oz-$L>f zW8|Ac@>D})2?@#5jFBZFdAc#OpOE~FF|xmqJkuCCKuCVp7&%Z#e$E&yFh&j)k{1~x=M$2b7$ZA` zW90lo^4rG9;X?9CW8?xt@+xEGfnN<$W?{p3&zOR zgyc)c$km19pNx@f2+3EBk!uRcKN};*3(41vk!uObzZoOf7LxxkMotitZx|v6{wdza zwC~^VV+#CBEONgOBL5bPJm7=Kn_`g%|Gmf{Bo=wd2a%FkQJm-T*n^@#|A4J;4BER=R zWUyG|1s_C)h(%uVL1d^{h1;rx&@~fSY$^ZL^ctN z?CgWcM6t-OK8S287TMhgkX=0HRd=UAtSmY!hM0OO5%=AHIC$Y#WK8Wlr7CF@ikzK?hr}-eV zt61c8A4GN&i+sihk=?~2XZj$rhgjsZK8Q>gi+s)pkr`ru|jv9#|VRU;WD9a-q+`>ul98x2h3D zUR}$7RAFt<%W86CAvr#Xyqs1|UZ5s75t3^Qb6%(>Ckn|4!kphwlbZ_3b%Z%DQj?nr z$#sR~C2De#kX%n#>}6_lvXER~NM4~PHy4r{2#fu;n%qK2ZYa!orJCGQNNyy|d6k-+ zA|y8!=Db=>ZY3l)5t83mlUobPi9&L=n%qW6ZYm_NQ^&JPR8DMIpYHMygZ+)7CP zNKNh}B)1ll_o~UAh2%Cu@;)`Wi;&z_7?S(dnerJCGNNbV}M^H*x}Kq0xCko=9BJV;3HE+l`eCJzykdkD$jsmV_W$>~D!4{GvA zAvr@xzNjXT6_R@jP4%OiJXuKYB_v-~lcxyDy@kcTswPhrlKTjA{zXlmCM5S2l7Cf` zpB9q)3CX{!$>`3WJ}p(ZaDl7|V&xxTTtL`WVkBo|QUyi`aYAyil)HF=qkJW@z5q9(5t zl1B;2Mb%{2$IjLB=g~rPuCEHZKDDhTj}a;?LY=egOTlXLSRpw|O?G|JS4|!#B$rZ? zU0>c+lgA6mWz^&?LTyhFlFO>e9|*}4h1xE!Chr%LCke?hYVxN-@?>GL2QRFjVi$xjK%wbbNeLh>}B zofFjL(?asoLUOLpP@WZ%rwhsT)j6LNlAXdjH&l}^2+7X~b8f6AUlfvO2+4_R@+Bd8 zrm)z})Z{Bd@+=`aSxvqwBtI)8w@{OR5t3&M>ztw{UlWp_6Ovo2$-fH8&kKv)R!zPx zB+n7%++Iz-AtcWgk~^r#5)zVM5R%oO_>^i1$@7HdPU@TmYk-bM0U>hdT$Aq{S>r>X zTwmpAgsREi1mqs7oRR3G!TAH;4_NCa_k|BnlFu_n#dJ>D;rbk2zL-s@O6Qn$a0hzN8~zrMUK33o4g9(HS*dVc|E<{m?M9{6?B`Ypc1lxa}|}HZs&rJMc+h4ksr91 zEYCoaEIV()M@Bu@01lSrxy%U$j7 zXnhCp_5Dz*zTu91OpQnB)p+lJRO3-xjXzduyw6?Z0iqgzqSW|ts4?-+Bv*|;4fJO! zG)}KV2e=9y^q7#J^NwSDElE_8&y|v_21AkW!p1{j9EQLD!QV0XI|+Xt$2%o3#F=gK znH>2m_^2l;h{~XHit|(?&Qnft7Pa#P%BZ3&XUXyzS^k#yqPdDr%YhetO?6rTyyzRZ zPUA&2Ij>oh@1X`4R5iJDdus9`SCb!=n*5|!lgpYlxeB%TMOBkuZ%<8L=W6nsQj_2H zYVwDtCVrhzKJqnYsVw;U8u@RigWIPpNKk&-m_<4wys;35Ryc}jw`UODivqXES)Kif zAga91CG?dUCcp6F~xrVmn4^le^5Sa;qIFL$(Z%#8}gK&^nYydB{ zrJmGnmY^JqEyohVhOs4|Cyf1(9h%S*5KMj1a5M_e8__=WsS;dEQP53PLNmDhY0G>A z!s;eUMFH;i+uMfA9A@#PhG=|UwiJf{AzFdj8p03qfTrK`=Za!E7p@_Kb`7DlU0Dvt z6;c>_i#ihdHg^dWWN}bOvZ3OZFzQI7kj0W8umIEtMOeZC^GBZoRsgUdv>uhT6a);u zhAov9Gy;|)9*0BXuG3Of!`qlQ=axBmf#;qXIZ&@Wj zeqd!O@68W#hky|ctadQsMFT5KtVg^w8Ad+jo9DY}b(F@Ug1~&F17f1Sk}&EaQ5GAW zA3CBnqtjB2Pgzh5EQLtA%ksNF2>ctWx^p*^3nnRZH-S!j_IvwW;J%Ng~! z|6|5IcZ#%->Tyq`^8Pfh8-NNrioO3UM!eAbJ1OF)xJQMZUBTRi9TkS5ZyhByt1dIc zLZ#~8s;i!B%JVH#w$7recU8)!8Yf!1LyglR{+My1rKd)i-r{lMkF?ZewgKZrOE2o) zFiy1eb~l-#aiXP*qF0kgHES{yYVx?MCc|z|P5$C) zGF++22)&w&w2X2!FM$o9d9lLU#&=MIF|PJyoWsflzGQWj)AWAJc+wHLX33U`8WrY+ z#cB)7Tw{4E$1sMPcDH`fu#inBS&YKx;aat~y>W)dSQ*n zN8gey3{BNeuPW;(?UZbv1Ns`FoibiAx{WjXOSHB!mg(%_6)ZEe2Me~iW)Ek!Sr+7W z47;Pec7EU(syf>p^>mW6%CtKwX{Y3>Y}a!p=w_8!lw^14bltBj%CS2NL)M;%fX8J6 zP+im#wU(Vys8m9Vg7a6>&(g25)9*9Cvwq(wL#0*7LM9}hwI}s*LI7DyurzQDfo{TF zi5(n?2TWwNL!a9d6s@aief|cYMhS8~yWJO0Lo8QNhowkkL zpn-#lmE}#^Hr9duY7uE0r6?GVEe0$=3W4F+62SbWUjbVRSdjE3OnsIC7U=g4V9Nos z_uKLT+uEOe$AMrAGyUGVlsIITkHgKi8J!Fg?>M+_8hH^pS zX$e&gOg@LsSUb1F=X2E5c4IEa^XYXOnTm7f;|fV5*WH<{5_TpuXjkVBT!*8M!Gbv) zaoQ=@<_d9#qn&nguEq{W6YZ4i*uZr-x@o7}#HVbiopLRovY&R!&5FJq>c&8lsz?o` zCQ8s3f;B{`2^aKD`Pd3Y)1-V-oaFF~J0N+GWebTdsWQaY2PC$L&Ktbooe z#KIN3fX;G?C7w1aJLqvY>p}(Sq(yxH!a@dFp89fQse-!orMb+Y$CYee1@p{{Y4gJM zvfxI4;aqc~(dHG(v(4izTF7vtS4hue$?#4!4lU%+Ua_=rwlAbN(%@`gNG}XX8CJ7) zDCB6X-E4dasnhw?y|q*CA@$>igoPc2w3Dl<_k?yzB3RWl6n4N3OpRM@+?3>FVK2fD zbPGEwY75I`>tEPWTstLag~EC+yGLn`3vvDm-Jhi+{E-<83>jc5#KmV3M_ujQKV{2V zM6ZwY4x5Y6>Uc(mBzLl`5^nh{$8spga#$%PrZ)nZbjpJN|1{=Dw43%;V+UKfqK*WE z)hMcGWo{^3)S)w1@eYNHIxuAIsmL4Ltmv55tVnCfQA{t;IPWf|XO7%Mj$(#~9K{R| zIf@w`aujnI9dZMnu%cAko8PE7ApgR;0lKH>q zY7EG_FWgC)MMn}` z7Di_@5nOBO?%kEur;E9pddrX7EI;O0uI5;N6R9E6k)&BnUJa3sHkv6x4NPq!9r4;J zVI4+g#7IXk?c`h|5~;ToO?VF!e3MN(6VLhd>Upv1JO1oAMZaqoWHQP0~>r2;0BrI&vyf=2G z2nkD(e)Xg%+7dx)0#bu4*XazbB(y{~NK53`0a~3uNlWC{2wI}QNJ~VT6H%-4x2M(d zC#%8G>iD_)?%b_TX+y0J3|-E%QBhiNIK++MOLP9KigBxG>w@cUq$;k;7B zScy}|iiEC9Rw-DC5xT4w%*BYZtXGJ%_)>Xr{)f;?DF*GAV$n4zPFdayh9C&0LGT9z zK?n%~=pjVAW2~Wy!@ud;Sn5~H%s{+SC`G3>%s47+d@!!BIKunSi)=E7BSyYMII zBs$HxFgh)EVb@)sN~jd9Kz}4v@whG|53+_)*WCxMo8RrawM1=oxN>h_wbf({x7Fl% z;Z_r=F3r-lk4v=G#9BZRzXrC|k!`D>TEc+)&x7$a;VhP)zLt+()9T{-*CUJduOVx4Z~QRoCUr!|V0G(vsWVLY zx=3G3U1_kA>0Uhu*4iXkp|>t>O(4N4{SCv?I)DX87hqUg7cg@7`M4;6>v;m$?@`yV zRJshxbq8<*_}PectR9YsG<9srq=BADkMKl=cj2gq;c)N4g`7Lwl|X4O2o%?h&)R^^ zFI~4+SJx@sQCp`@iZ`TlMRUioHJ64m^zIUR+m?*n0p)5lp&}!~tu0{;4L^c%tgUmb z?Q^VjE#BHOH|kY#Pe+7yHMnVYPqkl5Xb#M7mMH#AA3R#3>CfPyWO0HnLga@XBuMIk zoKm_JEoDfl)B_+EzMdp+I0_pPV}?B(%2$pU+W$Y_jMyaa8=`YPc+h*P}VC#?OMZhWAI zU$BZAY^=K-%w+~&h>%bvR39}`A{0hhx@l>nBTut3$^kO7E z!oZppk*+O5eam2o;jkXUY1L!GToo9qw0?|dBwYiaz&#CzX?0? z!Z?G&<2!i|F&KjnLAxZ^ALW_3*I*iNg7DdDp5E0&IW=TY3DiM*T7ZFnoDQF~DW{-j%W15Vq1{5^P zn1V)encX457Cs$PRQN!`O>Dl23}*qK;zJ}(s*=A znxJ%k#8A&EhI-x|>JCw;&oN}E$(-&yhI)Z9)O-Vm%G8^rdsUmsWu|GUEMtbs`p1Tv z@?RKgG8ifo43!0ja=mQN(+R(*80sZGL%pmRsu)BRc?RsP5>X2jCwq$19W|6-Nn#q8 zifDM6Al1{H9!M(J3l_KsyQJyrwqtz|rT9YcD+TKWPJ zzd~10xRi#_l(VqPMPBr<&blaOy>$iry$yfw#=vVf%D`(jtncMm*KU(%WCzWMgd=jS z>s^~6-3o9tX77|(x49|+`^Ga?+h_1 zLGD5&<+dCv?8#C~Z|W!kV=xbACzbw&hvU*7kQ`B-8R{-iC7RLwrXHfJ5{rxwlN?b@ zjxOR7mdMpU*-?s54YgmUnYuZ>fxr|BQmC#b#Jpou23y$SHx$t zl1=T(Cb!a31lg=&iCi|V9A$FVeYIxl)`HaUYo=}^&}+74>b8Q^>oilhqnnm_^=!~g z-Cm%~O`54w=_AFw>@Aw9I|xd$RWo%OZN7Nf+ci@^EJ(dmGj&HnNp@?d?j+FnN1CZS z3sUdZOx;CLl6`Dy>b%O5loIe=)ww{3?9as$v=rS0&D{Yb#O{Lj>|hKt8WFv+#=TIu z$JOL|dnZS_qZ&k$_-2H4AD2+)NkOum>v=A5UeDmU7ti+#7ti?z@SuzxG|OnAb5hR} zebxh7dso?w&LHp+9f8?Fhp0Le+z-xK4{AL)M;`vS#xeEI(0jBWN@_hs=lcsdiuS@i zXMhYHOS!dR#a8m9pY;f~GEe&1u+8(NAE$*3$HTf>I09O*9tFpO$E&T!iGwBBv7Kgc z65E*!f^o1ngBk-QJ`C?8fvS9i^D)UC*r6nU zjZtE6oi$PGIkMM~dC7*Ox8C+~crXPj8ivDY_UCaJlYM@iU&;Oqm%YwTVP@Yva2$&jUOa)%Sm=RbM7u67`b8`^{3L?C(BSX6k%+m^v zzIyE(c*kj?UV85|p%^Yk3;i=L#uU0ZF0QEfH3!^J_pB;9`suhlc_SN>Q0I9PasB$~ zYzemRqdG2uOVHw8!zGyFM&Jmcj{E8DlW-X=5=T;jzu`zmU=)s0>hE%~KXSQPe>!E; zb+MATBo%%Gmt=&O!lhKg{}Kq-+4Ibry1$;IySlW}xHK)rOF*+i_0qY<6U^5&Vyf^ z3lG%0{lgY^px(oQ%yX)afsPj1wc3;&^i|9nn$&UKu}V$QY}4n~&{$#_F_$ zG_xAs%q~KsTMORn23-ogW{u2by`yw!*c|XcF1(u!VDj=!I61ukOy93&i%;zw2!^Yj z+BpbLby7RaaH^NunOL+zYG+3fkiu<^Aj}9`_RNyg;GbmrPfc9^Wbyus@`g3fy1)eP zH8`^&3SgBeoZaW=m_%nF;)aR7S|{Ar)RmD^0k|=)G~AQ)9ub4C)0V^zfhOrZ_rgAJ z38m86EkybQRW-uUWJjoGu(;}xd!5)@55h03$tPm~TT%d16Ovy0DLQWF3#8QPyV++~ zAf;X}=q)X%N9Un@Ho%u_x58=Eo>t0&X2dNK{FhZsk1BA6ZY zqdOA3Dh)$ZboaYv2VI8NB?V$Mw{D-*DVIBhTC01@F!ZF}#Ol)=TU#3B?On0w4S%-C zPwMXh)huowO;2|hw}Ys-k7}|kN^u|7FYZ`v5$wwpKsP%6y+_LqQ*|D9c2}%Z?ut#- z>yDL*b!!Or@5u|$vKSa~@!VfX&VlW6H?|$Z&YQoSoote1B zHFl51^i|TfKG=KP%$^X3y>F9tjoot%uZeV>rw^HtElH{Kh&arpejyEyYc-}X8_7@W zt>8fK!!GxPp{I3o0TmtOWv6Jn0We?hb=(>jGpZQ0Ye?~VKwdJ327`6N}d075WV)@75?+I4-GxD(f z-=xcQL=mTf{)}3;8m>ldF&tN8Y*8IoXKms2t(kfYDQi8_2THj^#^CwSAbI(K9bAV>oQ3N!66@l+tc_vq zG1tOS7<$FgUb}hbI+s^;Hrrd`vtnXBRni-bCS=$QR(tJwV$W>|=yzk)wxpN{EI~mwub#rnHuea8st1&2TfX z-l#T`a1u?o1Sc`+l5w(<4u*$bpI@xEVU>O5C|aDiC7R>rH1B1&Ig@t_+(Kmu!O(QE z;nriZZtFqkweSjcwuS?>^~+geu|sF;Fj&IjvP4VVlGbtsZpqX#1*a$)hWnZj5v_15 zn(l4fib>ZRxAvxE%eh2%Pa2ij2DhOSSK>B|#J0F?-uhjl*F12ZzC^DT1TExuX`vl% zN6WGbw`0oE9=GSqVq2YiKDShFsO!2-m5NiT^!ITpBfSIeAlBVdod(rCZA!ywRAM$x zVap7)4lDXwa7U(u zop2{{30LNo(ROb}MPO$He7VE6GboUCxz#$`-|4`TTl|GDFS%BHcQUt5!_aEI7Gyju z4l})EQKgr3trqX(#<{EY#%CajEG+N#_Ndu%QF3bhq;0MQyp7}qsv7-_A}+lZ)< z_IY(z95NZlclN;feI58;7)XaCX(G( z2kDi?eRYUl(KU4U>U;nrfi9rCM zfC);uOwbqirBcu0zKqm6_VBDd&Go?RyBkNZ>UU*rCa^Z|H)BKe<7y znTRA~KUn~q?rre408$|v+WD(M!1bXYsr5ziN7ly*uku0GS-I_gr~2t0xo z*@j0jMIMPqs)`&eEb`mh1>xp;pM{|pwUesKtg|%<`n)(-pEnARqU8?7qnL7!#-mjR zAA`rxbPha*NjDac^`>KWdr;4LT^bvQ$5Dy-@i<1}csyREF@cc}>TJ%ja0)x9ccj?i(6_*RB{pYt3%hn6Y^&tXb67tdu%rD{5l=)HQGG@Zis z>WI!%h-{Lx$MKuwjySYe^Z7flNA$e<8#Zo_=)5A&UWres{g4qqU_YFP|5tbU{|op9 zs^=>B1xC;F@H|D&bYdzRZ5_?q|L5cRRC+Z$pOO9|eo^eLNAvdom+(teVh#KfBk^VY zvX(?W|Ie0df)?x$S@znjmXGPJA;VroJG^JlJBd1`x1LT?*W**`Y(FBY*;i1ZV-B6J zouqEW$qqyFw7VZznyN)^jKbbrdps;A(umO62pfiu>rFPvT~H#bwp)~b$e+-gIdj_) zj_d7DA=}AFrgc1->hAD7X*kmpdKUL&TF;ZI-V3zQ7lt!EX(ZDI?o93Oz0u0zF0*Ah z44pEZ=@&*aZ3LOp0mv)(6&h|$@heQYy^3E|nupg^9|Az9b+)E+@8*M)+F!=A)?^*~ zw9aSg?9KR;(b^F}-fyk`Z~>H}t0seQ&`;}qT8H!DQ%01W%$EC%BcEm|EX)%WVd#wB zr)4%#!{x5z8J$&jzLID3X7XGmPdl_X-CAIqL4x;|7JpyttWK9pR%h%f-diqpwS=70 zxl2riwDk(9PwdXGxrDQ8F0y-*hP^$xU!&~gVDGQMEgX9Xa-&AMo8nNOQV`uv`Cha! zVgX)2qv>J1fQhEp@M}smxjI|H;QNB!V~MW8=0d!XO7DahGSXkiuZz3J3%XMk8vSqJ zH>kue_zgzloA^yFi8>p}pp$jq6q(NY{RKTI;^x~I^uEUfQ>%uq8=J5oy$CO&#qNd| zF~wet7b|McHSNBrvj9sQEtiXkeItM>YYARLbM1kbFu5+pOPO3%U zuI+D$uF>TR3>%hU0i+*Z!IbeW{Fc{&XkFgMZ_{)G@Y_tfcknyjbga`{(F+FGJZU9f zNhJ=#D;bIJ;&&D8xI#^^Xm&-%D*OV*6&;O`*_FuQujoCJ$vONLht6JiaQJ2}9k0Tx zXiXo%tC*U;hu`z+PALg@6XdGi?hdXbSM|CaGI}1uy{89V)!RM8&F8P`ttoKpI#+d; z^vO=aWHOS6?Y#CUSWo#yXNX~e0dWg5AST;+?aJQP)p#}4=Wx85(dQbxhV>lp=>MAD znu}+rpxw2%6{7Zi{63XF62H$#UyIjjN!R(TC)XQa(_3?a-Z(`R(!c7w3YvDJW4$5W z+U0K9IGa{rJkDk+kb`qrcY}(q!|Q0eiFh58ZarS_O~)GQdfp+u0dJrZC*uu_#Ep0( ztGW^4_N?6N;MWa@^!0xc($@`#^z}SKx~<0@EsuLf;G6I!TI(nACZ^V#@n*KxUU$5q zw?SiVw%i_EJx0AO%Kb(nxdRNx zT;C$}rju0LPv~1vV6mHhVNsam$EAWhfR>K5OXgGgtKT?Azd@*$6+joUJjDlD;Iv!t z7OHF~-ohyR1N?!iQ=(M{&=sW{1;YDYj%js~L?Y-O$mm9p7KfvV{@8x;8 zBs;|1qISULZhF~qjeTE7k4u7jw&U%zQv30Crcyib4%QbT0&{n&Qgyx2rt85i#fc%Y z_FF*g&A@}%CmkTQ_9xe1W3;P%htluFJ89_;;+;(Cci~;C(&uhJAd4Z|volh98dcsk zAs`rhE)Y_tYKtZ-52Sa3((lH*Y3UE)-Aw5}#2@md7wjOBYH06v$f3_ULLALy8e<^D zYL|)ab)@QH=qc@_Oz}U$AJO6;!5=Zj--Gw?#kU{L)p$c`bl$GxQa;(0=XIYN4xLZR za>cKqHw0ozzZdVNr9Y1MGNu0*f2=Bf?t9WwO#{k@xv97GH4Q7jhC}ZQw_exThxgIa zpTzr^(tmAt4kb6Q-Pbgz`vdp@E&bQ{08{$U@MnDKbHBkSOp4drDCP2d^124E=fvyX z9OHB!uQ$qJbbk;Zq@_QH4>G0y9DlAVeeP#~q*{6F9v(trN?*&c?&BRg&uufMKZFm_ z(x1nNn9?7{hgGG|{R{$>K5xJOo-e&ozprJ`?~mXkwDcG75vKJ2!~f$;FL=aLs-3s) z?U&fn*EX#CTDpFpEk8`hE8dM$ut|&E6DQTtyQRQxvxSt}%|0EGUV$+Ryz<36A_WRR zA|?IiQGArD@n?LLQR6Xu%%esa(s_%^Dy3mwD~!1|kx31??QgD;;BkDM7T^zjoGHKw ze1aB0`JAl%Px>}{m`d}vHKjzIkvUnq72ehamd-;;Fu8|E0PJy&NcI^3;B?aL%jqJq zYi}CK(*8HJw(vvQ#Gd9|KH?Wz3$P2Vp3QAgOFO$XB_--b_quKBx9E^@E43-f&+4btz^8(KZYwc)mbE$4|sM%Lb9@;P|p;@ zmF+2fie_uar{#!{}y;8}c@ma70h%arRY{1tDh;KJY_`~sMiq_=0AT>yiWI&W9-mM=+AzOV7u zw0szU&6MvO{Ee!7#Wfn1P*YgT(G2Y9-pT|`TSf`Q~7l`_iEOmHLBGts-&2W!Q}OOumnXeW8jj!NzZ** z4lc<{@!Xe5a7kWU=f3O?m$ki@BjK{1_i_weHu7Hfh0CVi%VBWY+WlcIDs^wxji1xGy~%tX=Q*{rSclL&FX2lx&%XE) zljo24M>fv^o)Z3qf1;@e;h&h)m+@s)YOaLO>ori`k9s_>{tSopF4^H=;U zo99SR34g=C(bS{yZ%pdn@$ahCTnXpub!c84&dp_I`URGRKky$k&$0LqCeQ2mI-BQs zPYG|}8#MJqe1l2-C;n5Fnk(T8#{BRFu6cpx$T|!DTzdQq|3&kijQ?Wt{Tu(y<_mg! za$E3IIlPHkQucdo21?cT&UX}O=lHx75Rb|(?y~quu=jpU}7Vq~c=cz3x_kcP|P)CW@em42V z)!z>gKeqm^cEtTgvF>auHec^mzcBZ4b4KzUotp#PpkTh#n6LMkk$22KU-i%z zwBDc#f2c2XtT6F>p8Vo;5dcVlN*CY@b8~{{LI0Dav@tKTA1-i>M?rERumh>&7s)S9 zau6UvLdmbVJ9>DgM3Mgz*KyN%E6A5YhD_xzAip^I7C#XmSDfNhFU&^FdzuXgS^| zzqoQZ0C5P*kt5LLYh17Aksk&!!l?Z9NFhWh10yY zl3!e21pp}^%xj0BF0TvgQV?Vmr1E!>U!43xfD{tS|A@-xZ%@C$c^w&SlXjsn$S6$Z z?Cz9i>WU5kzbrHiULwpr3+{y_vZv3Aa}ePikh26Izu3q+D-pCQwezD%;N17|*i*+74^3gy2A@pb#wDBV;}up0`?aKZ`9bH=@?y-S8c7D90 zJ7#5_@Ex6vffnzm@*UyKyCjsTBrWYX;o-{u6L=Vsn3xv{%vo>Lmw zrK#la$uCZF89>SiCBw}Ny2Q@Tyx$ehyrV%zG?jmm{Nm)71*EJ{{v}aYwaVDcdzG-B zZQ?UtBrL15#dCj?032z9*Fb5Xg9l%D+l}aq?pTfvFO_DL+_Q5qDYWXMz0H z!Z~6r$cUx#uaRGz{5U}3gz|qC&AZp=cKJ%&tP#$;D?nZqXgPi-zqoQ#1f-&{9DfMv z`92qy9)GL^GAdE|H^?teeq}%^3+4X_^239*=iO_CI;{fos?fatCcn76ssd6~nAc4~ zU9yFBsRlBt5&0ox6|ov8zd9h*Me;-ZsC>Q+%i(;^(}vXm88xVUvieqolV1~%nyh?S zn}zl4T&?3e;Vd>D*zr^{S$&J=B-a9@7AqN6tVNR7t0mh;YR+;u=!P~iu4ojxL1%94 z-W*KVCu&29Yt!10wZ7V1Z4v-UP}K%v^QoK=tD^xomE557?kqZcfpIRKisv5WZg3b~ z|K6Z891h{`;%(4*@j^&GqOxGpd&3X!H=Wt%uB8o*aoWQPEfY{+v-a>huEqQpbicG(+1{w5R)<^0vQV;J?YB{p*2^ z>rwlY<;{AW{p$l#-;n(`%+G#2Elk>E*!-LFHh*DV^Ka6dqH*Tm zWZ3*0;d5jE#{8S}HostAve}^d8-R%$Q1g=&*9M&V8v@eMkoh<3ysMdy;mwBiwFy36 zrlT)qe6@jlAj~uVX#{0&MC(OXdKz){Y79tYS}$hnt-CpF0{_;8^2p4o3CBwWBvH*% z%CVK+1ZKDFkag^)z-db5k(p9cPF^!WnlbX+TTN+Sn*{%sM0sS+lEm?n0ZCT#lyYnn zmZLdvnp1gXrqY~~*8-3hj6C<=Q(BIe@NX?CkIXKV4o~IgNp^n1y_ReBf%4b$@Sjg6TzosXGoin zjF8^4Gqh4@!_X$Ov+%oxw-(+3=l>NxU-$>vS)_cC+C}QhPP`m%z?CZn3S!Abs&Simxf2EjuIZ5yc}S;an{uF(L`hQzPa@yd*m#QzQFC_LrSe zTcbXUIt1tQQNKsskewxKmuyk8mFz4PS*miWYH&^})u~ihIPWZVxYSYES$ak3jitB1 z`C#dlMw^;j9D4;LCkj985JE$H&f$1--|99{Y9dx3V*?a$KXh zL^!`2w>1vxRRL89t5868R-RIMZsqxKK2rJH%HPBJuPUKc!enQau2mkXGE{a}4Xqkk zwG^B`ta`NS2{`{)^=36c*;%b&wRY7yz9oz>e{?_Is0?5xqd#_$@W;QUOD zS8FVU^Vu3#Yh06^HLW#^)&x7&>{|1YnjklRaQyiANpRj9ejh4fwHq{ zlcpV-c9fmXDm1I#tdZHF;(7dvM;Bd?fjp>}+1BdAa5> zva>~SixMrOWM|7UEuAfA!g*)Q!!3`>&XgBZR;0WmJ6k>6s(-6Nva@x8*3qrY!}(C_ zZ(5(1oo$|L^JbeRva@ZQwi#`~ZtX(aMYIDux7*k5i*{#ZXZz{xUv9rZcBUq!c1i_* z=@8hVPzNkK(^As9r)9u-f7*y(0xuuJEsI?wO? zvh3_qwo81M1liejao6mw>t$!RLfy)BgL0?;n0_+@(q$CSsE|<^&a*S#$XE>L4>As9 zd@ehCR_)oOXEQiw^nASMa5x|Cd9LSova^?8ukc=l;5@R|v|dg)FYcAy3*`1L-n&9? zkkk8c?{mE&U7yeToa+PUzF+jc()SnH*{^25mi=18d0xM_`@JhW`$zPz)*s@l|HS@t z`a?U=|I7Z@`u{FF2Mic6VF1MMfIS0F4fs-a4y-<~`M?x7&mFj8An0@8FN3Uuf@SAm zG`Qg4BC>O6#?TQ%N6XIP$-}!32fYkmK77mYZL)L3!y^Wd7y{?_M(iH3M|O^MjEo*x z9?mb0Tsac#IP&*VA)_3!b5y5MkB)i_&R>qYHVX0|-Eef;=uU8cXY}^byJY8>;4vk~ zl!5ajV=~7)3Fi;ToE&pnc8;ApcEwmI&-j7kCyoa{oj7pf#EEd8JYe#K$x!~xhM8%Z zASZKl=FH65aNd)7Dii9Hg|Z4}6@hcxtiD+T;QVyff~?o!d@Soy)@9i_#W5v%3Y2q7 z#*`6LM#K5VDJ!SECp(dU=(9)~H(ly*GjI;_li`1P29jjic@qUH*DieSO|%3BxRZF3 z$sFcS|NV?CL+WG{#H3~!YMf=IAd8B{GDZKU6mL1Q38*Yx>)+V|bV9)zQdmiPX#xo! z#me%xvg}etRTQctla-rSy48foO9Vq{RYTm}$vNgWl`7*VZdZJplxz=pW??m2A6P0iWs?JvbPUX)8 zIW%Q;?~oQ)P29;cu-e#->fb?auo}73FY^U8+S^lXr6&nQ(4>7psz0=iOdT)DP zb-4!(z#8FREk6?mQZ>}=9<>5%iF>&Yj5Saz)Z-qu25XUfy&lY1DB~VC32T=7p)PE| z3`f201M9FBx?k$UTB$kebDvm=wbcDoC)Qf6P`~@gTCBzHw|X(1)PVcUWUSfl$GWir zHv$d153R>q@P4fyYsKd1k^9t&tR?T~Ix^PuAB%?E$JS&mdcW6`u_|oBdh9;8Dr?yX zp{}fTBheENfOT05KPdI3OUK>^aMIB52gJ~z_2d&zbqS52zQgp70>+fc1t+XyOCx4Xj5z=z3ti zA`?x1z`cU?3{w{~+^+)iyt6^Fpe)lt5bGqSK4wsTFr&>UO&6gmVco>kiOWrhPS_r& z6?)3_7R6gwk1_S)^%$ZTrh$3dbQ#WNShq2C!@G^T!D)`1ruXFX9@c|Q{p9u_l^01e znqhj8(2H14GIb>OB%&jwJ4-{eOjpu$CDxrxJ!!j>s)2$n8naEW()B9VvrJv-dsc4m zdfxP|JiUwcFjHT7dzjkGW}>;Kml^Uh*3(R#8S^xvGk%YRl#b?^4rkcmSf?}fX58tB z-k8zAx{BbQ^{&eYvMb339tcJ;kEdfD{8f9!p%2b%i(=N_o?LjQi~RnrUql^3#} zXzK9ac_PuFYa9qK)~4^)_HT+_Gad3@J0$CrrXK&jQxZKg6=>; zUGn3|H%;&K**jSeHTCJchpN5wU9{Nr(p%!Ctf!hfy)~Zd_0}8o122!FrKY#uGH+!) z*3|2*^H`!+3-wd*T9`e(E?Wx2|M0COL{H?tmX>iNI(Xth_L zMemtj{hxX@>)EER|69){y7mk|q$IS)bnXA#wORKz_5I(wx3>XzeU>>5tu?*;ws<+~ z>88$akEauz^Lr)GdX!^2{B3i1*6B^X-#(`&diRWEP$XJ!y8LZ*dDiVs-QQlfC%Wes zUN)NEf7`vEjQ~^sw?6{ZQE&-uHlyHZGfeKdNjxqA zHgS?rF>P|^!^C3~*T+1vWN*ZLXhzIk6EVa}o~SYHa`!|Hv5Pu#a?l<#a_*|gVWY>i z&D|9}q6o@HADa<$*F_K;MW%i3z9F$jxab$gFM%G;&S!{Hfwz|8cOB`XJn-O-`M;IGrroHa|C=*B8VKdV1iAZCk&9vFQ z5pCj#`=1$c_e{jGQD@ri-ibOvF*EY+smSw0pKD9sXmrA~-#uqP&W6&n=nK<^ z_oNLuJE9@zv}wnC){dMlB`f;UwB|M2$6XVF(? zbmr2KT4VRZHQ5*G8p+N_- z2h+ayoqatvCL?3hzPU%5L_hcXpPy%_9E~oTA$-r9Q_CGaj}@6VzV|~`%f{@)cQE?V zjOP0`nu!N^BHFa`{TtE5&P)e=*$nCXI;7dKHf?=>hc&S^-(g=hqx-&(ZZ^VAd*A;N zuIj*lF+==;2yr&dO`AU$VV=7~|J9842PWFth&S#2;6%Ktga6$O`3EZG*|0Zl|6qlE z?hgOD8T}7j^s_C1Y5xbW1yBtD{xq9_2eJuZn*q}Y9?WJyJs=p0{x(~K2evg}TLjY& z9^4i|-72h-U^gY))PJxw@}Sq>wR^{I`hpn;@HJHT18eZu8a%W1v*h|pq}f22jfCuM zNqyp`L_c(52Fn9Iob<#4={#J1(Mk$32NR}GFztfZH&P{w=^LhRFupW2=6CpQmE-Crk`l|3GXZ8B!}rMrmyJu3hyteQhw84On=G4 zUwEHMmkO9ZWBQB%pW*!`RVrlqjp;WA{YLFOMNHo@edize4(~rVrJ|<)nEvw*{fG0R zfK;it=|iRu{RhY3Vod)s{p%L{m)ghT zOdm6S>_6}^-p|HK6-_@g{p>&TGv3!yrOKwSnZEWP`Wo+V=~7kG-%Nk|kNu7Jxm2mT z>2s#f-3Fgi`&~`b?@YhDO@7DwUMs1V>3gQ{-A3Qz{cpRJVEUiwf4ABHJU)06*-ihu z1G*>rf6)KnJ1JT8|G77%JyKn>6@1`5;!Z_`=e13y51Osgo$^6=U6iXegd;SFKTGw^ z2GMK~@8B@O(s!=5Qsv5?tQbV(0G#kb{*f0{O^fZp9FPe?xoopO)H;`zb z)Yxnw%?9!gH;|r2()B{iSSiu;Nz*6q0-yBwC0Y13ebVf_?{w$w$sax)Ko@>c6RDZm zRGLlYUD8x~noCbNo^1N2>6>?vZ+iTbbmyjTn%%jlJH1=ZOt;>`Y&y-R^Db*TJhV|7{hPjOcK_;b_inpph5_x(rqyg(@A9VA)4Y0y1077CHGTFT@L7-Fl3{`A zv*xhiZW{(@mB)QkAapiD0Ut_L5JF{9Ayf`Mgc_q%)C6UsMD#Xliq4>BQW2CSwL{6$ zB-C75iCReCqLzLIP>NqG)XHxhYVEfIwedTO+WH5gcK+2+d;gv&)&E)4!G8-%^S^)| z4#22mKoaT{FamWBScJL+97J6Mt*BdIW7Iux97+%R7-h(xp`I2y>Sbw$dRv>IJ~ltp z*WMHL3+{*dha5otLd&3mq1Vx%e3j7Pe0AVl9}USj3=PdU3C>yQiG1tOuzWk={2>~d z?*$Hu%WSz0cf0KIGjhJ31Km4a#$>y6m}I&&i@^n6dr~$;ag6V3sgr_3JgF~ z3k*b07QBL{7J3~$S!f@cT6h_nR%9i58V^R(@f*llbQyZ4SYI@w*ehsevFm77@t$aA z@mXkg@k{8r5@~35i7Ygy#9B1B#5OqZMDt5rLoY^1XnsThdL`0^UX5&s7DO&YuSHcw z3!>7|!l=3E^{Ch3ydEtoRRk?A{U%ycW;t3K{VrM-{S8_keHqR_qm^Y_p?Ax6hI2Qx zx?DB1rd%poTW&haF82bQUqtK6XQ7P`eSkK_B%{r-`_PsOZO{i5rl74A+oEk1_n_^S zB($Sa2%MwQ?n*t-hm{7wIScKrvDe-;uW8zjg??6|Yl|@&Rs-s_$2BB-o9ni1IPodwEpNI1c=z8-%(2W*d z(Vs15qrY0b3g@*FYH>!AT1t{%%W{%`%T`iA%VAPr%Pmq+iY&<~5t1dPf)tWcSIVE# zQYw+sMJkmtP%4))TB?}xH2nJvsaDENsd{UxRHO9*IPZ~aw0TOZ*|w-uqiv#8vz?z5 z-)Vzns@-9hRI9@#sZLrcscu?DI5(3TrY({hrLBVVM^a+P zbg5~_|4Gd{PnMFpL`lhAUz3`5b4V?^ZG1v}kZmY0;yB(&9&tN{fd0NsEUz zlok!`BrP2}Pg?re8`84JKb4j~{=2k%SVd{suujs7VSh`@hnJU@4sR&EJ^Xd)oe{02 zl_Qo*?~b%ct47Y2-Wz#YT0N?*v}V*X>HX2Qq_v|LOW9)rq?|E*q;+FHkk*eaB5fF3 zT-q@1inMXUhth@#SENmoc1s&4U6wXaz9wzTjFL8F){?enZj-iUB}?10K9hD#=_Ku( z@+B%8`W!+b9i+6tIVdQkqPzq71x`lALn@)_ND69zEFqNv3kZrs5g}Co^ADO0SXID+ zg2tkfA=Lm23_1r`b-*k^2LP)9m@Ll&tR`SKc`{(}fLZ0=0ILO9uzVJ<+JM3)V0M-<+!nS>YH3O`uEgP^Tz_5KXV99_Lw+{lWIbg+t zD*@I5u!vv`SWCc41e0_rfJFt9bgcl33_b-|Yrskce*{)(x=A_*1~T16HYMO~85pR<&ppVCjHWDMs?m0IYg3 zl5bDIsuj-$tQTN4i!TJMH()g)A_40ISgi;vV0{6Lk4OTnA7BX)RRHS`SnY_H02=^U z-H0iG4Fs%CWPiX00aib<9bkh2s~2?$utxxE7_|kkM*(XPbpx;=fHjUf2iQ=+8kKAX z*kgbtmW&7Nalo3Css`8-fHf;s0w2*8p`9R+M8U@b~*2W%8z z%}Z|qY&2jgrI!IV2C$Z;iSLdDtaWMPyW;?BRVE&=@qo20QxdQVfVC;J6R?SZwJ)<0 zut|Wmi!KS+WWYK^+X2f2EH!!l#CR$O%}F7~(_E0MJ41J*D0Gr;Bm);BH@u(^N@h^q+L3xM^H zBfc>Yut9OeH|7I2utEXAUIgrsxW55=39!MH=L7aKU_&Zr0`>}Ek5>L3uvYk@zv@BwgRwm)xH4iEx;yL`w+0V0h>_0 zA7JkQHo1CRz*Yh_sm3V4-UTeHMo++20hU=~Az<$T_GFFefUO2>N{wrPtpV(*8fO4| zAF!!4Nt?44u&3c|SS3TU0h?Bn)GY@vXH8PKb%0Hep9I)?z-Gh`1Z)Ff&%~2 z9e~YCAbIQr?1co9$1cELOdxse25f#ElE;UDy>yx^n(PJabHJ81c^|MtfGtU^4cKA8mM4}5>i?Q2Kcu?U9bQ=#1rMSvYng?2Yo0_;!+445Ba|Lfonm_J}g(lP)G0PI*= z3%~*aJDPSDupq!rr0oMt2JCppF@RYB`=VoSz^s6s?06Y48(^n9o&d}a*s0DC`=P;r zec1_OKQsieGo4=sEEKS>IzI_mKETd)NdU|N*f(9u02T(=*Im~GmLIThyS@onIAG_x zfh|J|0QOxsuw`gLz|LooJPHB!LpsT$Fks(jR0gaFU>7rr0)_#*kg*uBqJaIFF$=I_ zfL+S?9I)bmUC!7HSP8&>>e&pi2*9rPtPEHrU{`t$2P_J(UwZZctR!GR_xuj9Qh@#1 z^K-yT19q)fA;8K2_Iob`STtb2^>PAM7O?BRh67d(us?c{x|Ij)&t9Z%4*_)@bRRIg?R~4{ofCct@7qIGpS^7N>SPj7B{xt!s37D;aQNZE>v-Y0{SS`SU z`;P^zHemMtzXO&4SZMz*0ILI7$biX!)dkEkpbud60LwSvOTg*_mVdx5z#0G+HZTRS zhJY0qSQ)TJfQ1iy2e8I~6&g4juqJ>N925*#B49-ZUIwfwV1)-40jwEdMF;%}SQ21( z=xD%_0V_VV8(_@=D>gg>uoi$t3{M2CC153nZv!j^u&CjS0c!5=6DYY$l2k->na0v0{;J-|8uR(|AMz|sIKH_8Fn!+^z% z`~|R%fIT$oF~B+j7B{K`V4VSr9Yyrl1+a>vi2k|)R$+7}z`6led30UCx&u~e^e(`9 z09JMMa=_97t1_kxU>Sf_A7cTmCt%gaJPBAYz-o>e09bFpYK%DzSRcS@joATMU%=wW z5p zlazS~V2v|LnTG<_D04Poj{%mLIUKOZ0c(;;{NM?|nq?9{7zS9=tRjF72P`@BPryb1 zmXtLBu#teZ$Vvfh6kyG>UI%P6U@2Ko0yYM)mRXkp8w*(Ltiynf1FY2)Vx#eZwVgt2 zGy$+SQ$_h;p|fC} zC>%-fA3}1>#?ToEy$3%L3JRSA$1cc@LXiW7AuA*+2n$M9R0Pf#&c)zd9L^DNj)Zeb zIG2KR8OjfX<)`wn_=Hg`3PN#^K}9%Mf^!u(SB0$SLOMTW4SfO5cED}$XCDToo`;Zs zDfE!k3`tT0TO_i;G2B+bR?t?+Rs{YExUupAEKYz`7GTu{*kl1VO@O^Dz%~l7Z366L z0d`e@{VKq&+ioa2xZ%=)y=Crn_BH~nw*VU>z|{2(vcF+p41Y_g?jsSoeouA1R&~8z zb-h`2y-jt!i@63{+b;{srPc?OBe*=nBiC`N>&mL@>ZxQc9MAdb&>NcP+h+UNcGdQ)?Yh0Cy^X!MeT;n?==(kU zTKjtYX8Sh#F8gKsufgSmkJsc$ysMki*O5@H!D1OAd7{^(4!qI9 z9Hx*%e{x6N)F4&VL3UhAcwce;caqwha6Ut!@K0LiX7e} zht=e;h8*4}hqdI8O%6Hau#Ozolfwpb*hmhW$YC=%Y$1ma$YCovY$J#59%jxK0i?$l*_N z_=_C=CWo7FkPtaYo&UR6{>b<{vj+<;oBjXJ1{dZ>>E zXoyB=j3#J`Vl=~zXpR=Fc7cO9gyW8l#WCe1Oep$1%f?A3EObGMa<#MuJ+aEMb<$lJq8xxbu@U_( z43sutJqBYCHmB9tG!|!Br=qk?=v2Nmi|@pDv-p0zn3cPP|8N;s5=9vTa>yg19EwmL z6>t@<#xcFP2#c`< zOR)^gu>vcx3ahaOYq1XNu>l)#CpKX-wqPsDunpU>13R$`yRip*u@C!k00(ghhj9c) zaSX?CA`vUa%8Bxmv(Pj2%EI16?q!_AdAx=<@HQ^uLwt-+6XB5b8NR@m_zK_PJN$s3 z@C$xRgyYg5_zVBw60RijIg~>MT!YGqa8jy@8mNW3Xn^!%Tb3_IbF@O+M7US#fX*mE z5A;Sq48#zO!01G{UmA z_#|}|bQN?JzQ(us9zWt|{0hBQYs3BV8i~=EXs0kyxW4>}O=3zNjV6D|n(jC$?+>WUzO~jV5RaQ9_>7QGc{SU9F BV37a- literal 275622 zcmcd!34C2e)xXP2-jYe$q#!Gaqi zf+z~IDT;`QiUB@6*t`d+!x$%Ls1l$?|Vd`&Y5%1%>3ufnKSd| z&Yk)EzaIIxrfJKIZql`AcV}-E{-T<$YqPoz_Kjrv>#F(&M>E5N>Hey=OmDjD_@<%m zvHna{Ga=vK*I9+XsFtT|<(B-`%;B-V;Y@Pm_+Z!8%t&T5szr4zj(nGmbfx>#x;DE_ z5>>;Qp8ibNXw^1iZ|mzFOplHYXIAT4Ugz=A%!oeop?tk?>A`eUve}$u7H=uZi&oQ2f?O;14qY z2>8d{^23gNc}(R`@<$x`2E~{8U+TzrxcQem{NwI?48}?2md9QB=R5oc#h3Xfm@o0W z<%=Bo<8Jv9N4`Aa%D>E!Z*cRcJNynef40Lv?&i;N_~iwz{O39R1~-3^!|!nOmpT07 zZho!9FBh)-S33L#H^0&0cewfIIsD^pev`v5x9o@7cdf&>?TYvt9DawAm+jKdd}^2D zZoaZZ;+GdOeks4xk#A6ZX@`4U`Mdf19sY6V7smrQ9R6`P zzt-WGM_l=@bodR5FL5?9A9^nDaP!Y|_{ZJ+CWl|1=hFXLhu@(1WDk)I%qP8dxcTi4 z|F}D!txi7W`7ZoB9r*?~e~-iOaP#*&{NrwZr^7FI`Qbe$SNTZ3^5?|2{JG>Se@=Y2KaV*6yxj8VQeOFUnZNSqlHX+erE<4F zk2wCk-0jaJjz2HA{JCs*<@#p1ke;#rCdAZx4M;w1%-r@595#`S%emB3< zg9uiuApO~9yvF2-idXaFU&K|)dh#s(~`!S7w?-_c`%l57;Bo!i?@{PMR|F%&PXO#99kTYcWgp^+VeN{CYzF|C*pea z+)UZ>sqK5~1~)cV9$b(#E>0OnQ$ZzhWBne9T-oC7Il^>QD!jmvYKGv+%_H zsy)@2mf0ufO`2ZU*_XejVov%zqdgIA#XNS*Y$-q5zOU{8=U<;WzvM*kvgvsR=26kN zsV13cIy<(Wm{+x@A$~@@ zuz1UKo*!4~F(f+zj@xtQc6^@>!wU*61DrVOoIe%qj)qupa zWZl5-RYM&;Ybu)3c}~4sD|QWZRF8G+Bs>yV*+9oi;NIuLm7lq29z9=vU}Gbtk6P)6 z%$kZ_%Py)O**N<|S>g1$5yCOY!BNz@vh8TwzPf|w?=L;JWcn)7M~Tu$-?C)X&UdIp ztg9-|E6Cd%SNa~CS`n!m+;;ht-2;27M_ThMrxlv{=90V>^UEum^}LJX>GZ7H1I?Xn zyPEZ;X%)rA@ipn9qP+N~IZb-g40Bd%?_hcTk=C-dWU^wCxjddOE=;XBux^g%g}n~+ z&e>A2Wj(iBGCkRtMD{qXu4moO;)>#UJTI@SxO}c@nro3?+5rFZv(e9iZ%Tsk#V;!X zziad5XYX1@xMx`WbEhOt#qX%TI7Rst#PiI8((-x8Z)e`Dxt?@&Djn=A8KHDjb`9;T z?(SH2V&|rr$al5#yh7&7b`L$r=R0~XTvxmIX#dP}dNLc@)-5HR8(ry|8@rnuPwX6= zS=VFEg}>TUJ=&LFxqGRePxiQS(*ByUjYcAAkUh0S&-?4p&SHx<9+{#yH+HG##*|H^ zNBd{3?(8dzOi4R@N|)?JyYy~Fd+w?3*=HoS7<=lwQ;n4ihGy0u$dsKk74;lkci!l_ z&HGjjoWEho(ZW`JQg1@6E1cfg)7u^yC3`W?Enl#-ye^X|o4IPzCbBP--_qE%uKmQy z&E>U6dV5YB*}SiA2>o`!Ku6<&-URx~zH<)@ZCKJ<)T)>CCT7+T?QZPaxS{k|`@ZU9 znX=KTNh^Iv-ALxV(qsLz8wsDp+p=@!v9?*{7sM9A@5E8=+QzQtl1liG#?ka;(jH}g z^OFUmE%}w}Htnk$?QObL_75t5Sz$5!Kz}{y^^$hkZ;TnCY zsjr&8+L-Ui5TdcGwI-H+qZgX-@MVIOOx@;MbZvdkD`4J zw(ngrwAn};Mmt*R`e`i6yJ5Qmp@q zwKZM6TT7=6l&|gvUUz$yHYaAT-@LD;yRQiC(6M@S}yvj3_>KdCzaf3$1UUVSo+r)}uh8!w-+Zt$Wy#TT%IhXy3?8kckXbbF7`H3yCFGrtBe=H|hZdNVqscrYBS&fG>m#HGNfu zxy9q3;Ga*-ADUKo@xJ_pXh-yq_R{&Vk4u%GLc77=L{|4))C50A&o`8mR(RtP=x1!> z%E+;PiDydb{G>M?ZPg3=%KD?^|EQg!oAe@29RBIdElYM4k-eaPOE%3q(6u9>oBQhq z)36uvr(Ky#%jOsPx2b*h8tgM=GUQaTQ(${2K;TMNy zl^@vFICFj#^#{k_mbLG#9ZBY)Ka`W-=5Yh_jNO}NmK$?7m98WEb@}Tk^n!7rlKOEC zjXMMI2e7|V8W-gJLfSWvD_y$mrTU)wn0N73)6 zs(9CB(ytcU`IfZNcq!a^S*k}zTjYF9)(7o|e&Ez^s=kKxW&4BR@iBU;@v#W@GJjJk z{BzyN#`c*pmwt?e!F-ID{`tTOS{s)XO-uJSjx}#xvT6vwQwGXPF^{Pm<9=LhEOqcW^P&CKBbZ;h>(SS|X9?Q1 zv8RuI7h=9t%>Iq!iVdkh=9gE{?dZSN9`EKjh#G>&DdQybB3|>6#4b(i7lS_o*EaijPuairRo7;K-yKh1)?Aug zy6(Jw{LWjIVSlX`dE(?>3s3A?wzp=emFKOFyz;NMJnRSlwL7)4f9fX8 zJ276Mf5iObObzDczHuso_8BKvJ6=v;elSkXIJ203U%SR9BT;O)#)~u5bMCKs4xaoi zavmthQOq-Ek(_&+%Rla#Cn`UYl<6_<(L9IK%W(&K;`!IA<9+-)Q_a8Zc!k+wuP4l# zMEF>rQ|xtw4RSnGeg)&w`Os+J(BMd=H`?5v9vO*hg?KRHcQuvygXeyJE*j6qr-iJy{-b!f|e+y?*UYyUT{}d zrU!=xD{G?K*}69O;`EVpReyT07q7aH3|*3`+LReRIMls9J=oo!8L4a=8oFfcP*j@> z%;BO@ZN9GMv%IbqtGDBo!$-RMFFDvfjOJK`7vXjkcpQ=Lo}LT@mg24Y@DUmDi2U7gX&V*;W!bjV+&|QH35Tuo%q@9D?cKS#2#E-xVcWa7EDtCOOfXhE&Z8FK2nG206eukrynW zA3IB^dD#;C`unkur9U;&cPaV?+Q7EpzQHcE7NkgZ(x9a!qPTH9AcD@la<-V%x-Y52 zbCNndsa4KR>H<3E=5xnX7qg$q_6+Je06fK2Ey$^ESK{N!+#yQlJ2XgoNTs{F(3@oj z%q1K)*Q)bTN3h6o3Eb>aSOc{V`5>lJ02E;sdZy(-NIJDe*QVOt(C)zsZdt$+3E4?v zdxCLEoF_0%xHM@nk`&b4;VYCri(I{1s`LyOgY6dEpiqTCK3X%75Bm$`*PVjD{1kjx zc3BXfAy}&0UAcOG0pw*1$X-zB#Hv%P(2=@^1_m&)DTNhSQMNQICKWNsYu`|TkAun= zd1a{4W#^IEDOzSG1>F{}9F!E4US#mts2Z?}y9fHnUGeykVrXzXjzr;_*ZCsofsNIc?6sy}9#Z>^WPV8|OS49k-`@Q@e(S;ZgKf=w$ea z8jT0!&N%d)HfLB@kB|&L}9j$F^QpxpAFqG}6YeF%0x1z^Qwj-(bR3ew{L?>V}_(BG2OAfCAF({4fQVO$Tmk9_>3A2taTiTU*w(Zf>_AZA-4%YSXeSb4C(}0$;dhQ!>@GW3A;3 z5**)_YDI??R)j2`%8;_#Qs~kcnAaw^ZAZu5-m-P;jtjS^wzjNk-P+QO9#PoZoNQj- zlBy*o0o!C1cj>Ii%_1k|VNfqFc1tMDxii|9+LZ*RDVA7E(&h4OLE^H;to)>2mFFu} zi6xKK>n_^e1PLXIW^*cNHCc&z=xsE`wGaAMoyrKqxa zrlrLvTG#G?eJgvmBFdhvsI=$e)^^yl&yV|gy{#j$e-aj-N+<$Il}_ z?&djud_0%@_;@b)@$p>X4B!H30GIsu_#DWOkLQvfcXP>ik{|c;{Q4w0zdniQ*C+A( z`XruTpTzU)lX!%$ZF6!>YWwEYj%_We3)^;V1D0spwjH(ba+nB!a_q*6D7&$u(r$_< zMmE~sL^)#K?Pb_rp4i(kA>x5T#J>8h8zv&gvRcj@^Tl+rD{wvW*-!T8^@?67*Iu)?T578x5H?HkBcVNq|a3*U*P`Onx6Yd0IwCgIi7^uj~~i}KXk)aNiBe@h2Eq$C-kJgW>UV6 zmd;BbI@Et0tFNf^>1v0>>-6;{n*6a5>FFEn7Wzj09LlXt*Jk*V)0Z?`#|F1UQ4@S8Og(_tO%#CWO_gBqV0UfwN@sFDUXUK;-2Esdy>1~pz9BZFHS zQ6&v(yfnrPw=|+k8q|1cT1#;?BBDwf)OhIzuQZ}c8q^eO67Ch27sXIo(w*r_jrNbF zXvLOSsAKxo=$x)XYaka>Rsk{~BN)q6E2Du!T`Hs0&|p74V|b%4Hwas~fegqEt?wxw zaVr7HfCOl9PXffP1Rw(vpwT@E5VsP53`l@>_as2vN&qq-0X4m)k?u_ASg*3$+kF{9 z&dLa6Kt`|%PsxZ|2|xxUAd9gY6U$qNWBT2`EFfWJ0Wu&9Sc|7j#H|E@hExlya3`R+ zN|QLgE3L`0Rw%^Q}???W7jQKp&r`&@eImqrT!CqanF~ z;(SI^>lh7@0SRCk#a%Xg<*KK>(~rE3MklTGqsM* z5E+mFX5cBov5?w83#o+}B&^{(GZ@pq>dU~f7!n;{Vx7-oD6ZO$$bbYe0XM`t$2y1% zNB|R%CPr@nvF?dCi!uFszDyj8sSC82I#`0IRL4l@Q9!9aBdK$YgvfvdXmU>pjy2Q; zT0@=B8YpgQF3=k4eAYm5D?y+&)cLG|;#Pt{Yp6pLd+Ok{K0O*=>E*uGr?@JC$bbaC z)?ey>U)wKt+MdXO1irRk z?zBCT0SSC!jaP zrJms{)iICdf#$ISHh{PC{NsS$7sd>1?r;Mq31u)uj>oaWXD}4E5(FB|3fO@2gJhVz zg)zrhsADlC9Z;yxVpcd7Lu5b#pT(?jEQZK{1U`#d;aCij0SSB-v%;|$A_Ee@4m_H6 zOk_o%iLCIM2*oW;2b#zVw7I7Q#~kRLRkigf{E1i}mG9ZDkrB^yFO=Lg< zUrVoaTAIj!1iqGD>9jPF;}g{TTAJdjrHKqk;A`o6r=^JuNZ@PfdZ(p{3`pQ>>3XN7 zi3~{KYw3EYrHKqk;A`o6r=^JuNZ@PfdZ(p{3`pQ>>3XN7i3~{KYw3EYrHKqk;A`o6 zr=^J;pJ0`*r75mjn#h0zzLs9)v^0?c34ATR%4umL0}}XJdX>}CL1U?H`zgCYpTJBTMJ5{gVLZ$y=lO((|`_2gI4vX0mDuMIw%bq)|&Ky*+Vza7-L z?11QiG_+Lc(E%|my%8Oh#%~9-RA{FOwgXxx^p@kY19})#j^7SwjnFP9*bZn_&|8kn z4(MS}Iet5!B|*EKU^}2iKyNuNJD`U_<@oJ@76$Edg6)8o0=?z9?0_Bym4l|9WUqk^ zcgr_@<|KbcF5{r}!hnouRnSv7F)YAD2c_{F2dxy^X@ZS|)&afcxQv4y29@JC4q6+u z%Lz6PS`GA;<1!9<7*vkmIB12?E+^PHXnD|Ej>|acVNf}KH;@S6&)4%+1gn+mN5da=4pg&qc#18b0P_UKg-eOD4Q5BPI&84s->2Ib;69$GlG z(FPk2EfwZtXMFltU(7t{FVkg6Bp6gC48vPnm(|d+Vo(~t)zHGCjWgJ4X#LPzj>~H3 zVL&;wgy=~_467WXgVMkdylGrkLQ9N6Y5Z0~D~onH!B#?RiQaNtRzeSh%0aVx)3|Jc z)*6G-_-%rg7;S99HbIMu-f~=aKo5h;@!J6{G}`3^+W{>tddqRy0X+;V$8QI;+-R2* zYzMT!=qZO7RvMxM%AqwzZyJ{!(8HiKemkIbN4uP0JD`(ddqRy0X+;V z$8QI;3~84WYzMUP=q<-(2lOzg9KRjVVx(P8upQ9yqqiKF9niy|a{P8cOOkdu!FE84 zke+ggVWlBDpd4C<^rmsy0X+;#>zmYvX<5= zdDGB9I%fXPn}K|)3YGMDptaRLqmT?cO`uWKR{M-XGVC;gMp0YsGYZMD(*zntZMDxR zB*RV8KBJHfJ58Wb)K>e9LNe?$fkshV?K29=u+sz@MQyduC?vy96KE8*)jp$; z3_A@TMh7n0%EthdVI#G527+_(05-nHlnC}e*DSC_#$8c>9qIweMPyQBa)B0$6w?RH zxDEk!+=kyIbVma6jtplG;hXm}7qr@m&hGoNbJQ56YW75={+Iu3$hZh)FO?nk&mL~0{-lm>lIbdGkWM)4K!!So1z zbe$TcYJcNU7b@&dlpR=^TtpfojZ`o!uGpPNs%NOb8!tM?@hU~+JWg`HDpr2l&tQv4 z+>S%EiAC|%o2*vv!C_UcB|hDsN~Nlj`IJ8$jA0@RRj!p8s=MM;Z4;WUh_psFQ04J$ zTFLN{%n_U!fG-jHMvr6PJRS8BrFF{`6&q*1q^FD*MNKc{thS&Bd7k&mV@muiB-qZX z*@4W5k8}=0YZ=rmf2gNNo;{MVnUL+^%*oJ)j|}55nT$es)`He?ot!_~kUggs&3fKx zM9#5wB+b_wlb@v1M|b>fTuhSk)3^vVGg`up2Q9JCX^GPy6OqnH7ik}61`YI&C=Hmy zBN!b~eZ@ib4|4VUFbWSJ8Ay*@f+Ge7(xYAI9*v=Ph)GTQiW8ATk;7D9Xbo%QgFSt{W5a2DOp@w7s%w`x_29Em?3`UA zj?D{bsjz20B2>Cb`q1~>%ld}3G zZOY-Z+q@ZliZjCJC38@{O8QG-27!+$Q2l z)P+KOhN-PW`vp_mh4xFPb_(rROzjrhubJ8-wBInbS7^^NwO?qzW$J*?e#ca&(0 zB&O~Z`edf=5_&OHcMH9QsrLze3RCw8y_BhYg?sRx8Um8l1XK8>k|gJg#OVCqq!&t&T3LZ8LdCxt$nsZR<0Or{mwM_k5=ygmzEA-_|{Z8mBnEHdzS2FdS(CeA{v(Q&D z^%tQxF!h4a8=3mM8n@&T0M5uI&l%%0$as{HgWIWu+BUP$JQ`|(gtpozma*X6QwTZ- znX%m2A#!vm21}iJ3Moe-5IvoEcG@ahLZMY8A%7L+Ou(-T2--)gG4@a~rvi(Es)*eD z2e5@_Dv#%(bJ?;Iv#NY5h%z@i#Vw26=y10z#OTboti-I`0-GLsaWofbYMz7RxWI}a z4YM51lVh3rVKVBNxiCrZ>2oZ(ARtdUZ*(7Kl)Y$8_M)}fi`Hc?s#KLtwN_-G>&om! z>sfTsY4oZNVfs&mm2R`kS!p*rVWr>fgq4P~6IMFTPFQIyc=d z_DiB!+AoP_X}=_zrTvmgI7RmCDf!?N$F z!_x>lhv~84DZ$wXBeGo3xa&GEk%fZ1s{a_p)8KQ?ojVOa`#8GO;N#=BSm=}*rbYSF ziP)2rQ#OKgpd;rMG~Dvpjq03777H4$tRo&<*RV{`^vRN;BfwZHu#ud@B3WozfSH}* z3`tH9R1I|;Vy!${lEs1=Uy0c#PO@Z>&ABD5nZxPitf@ng<8tT6?IIU#P6JY&X2~Ff zT&I<(>yXRS*WEh%k|jg1%C0F7hGfy8nW91CBFG4*<>sE|hI@s`CF z1{jmd%5@4S%LeruCCgQ@+C9kFm7qMcld}tHO6eQuD9_UtOp_(MS}dhJj>A;L4%tZ*}1LyltRiFWDf~8XXM0~oFY%D58n`WO7xEHof6pT zMmhUfR&JtG7UkGwpp&o+Hha;K$*245Q(83$nSA<1 zLnfbo(U8ffUo>R$=@$)|eELO0emuEFPy6F(yl}{mr}4reKc2=5EByvKFPAMa=8zvx z<8u!A@ibmI6FPf$OQm$FrFNtPpza*Na{gP;w_DiB!+AoQQ z=ylwQ!R!}i2h2rqye}Oj%mP6!jn4n&Gj&-e$fa2_;V#XRq9Icb5J7&QgvjmlA;l~g zG|%(Nxn{6ILjXyuBaJ!Bps`5`IVT;nV36A#cK|Yr25HYZ7nx;(W)hy`l36Tht-6VS zYr;7c`qY@bXGODI30|LDJ1W#wWkRddmgDVt{*Bo2;Cd`KTnKH2wvry+;(f@wIJJ6h z6+L{L&>C3m?Lup0-t9tL&AdB=b`Dc_3hi8edY917W9n|9ozG9-C$tNgcaPAL%)3`; zP0YJbXw6JLAhb11Jt(vmrXCjBTBc44Z5>mO2yH!6j|#1osgDb715=+A+D4{6CA2oC z9v9jsrk)U5J5x^zZ8KA!7uto4>M5aZVd_gl+sf2egtm?4o)+46roK*F2^@v<#x9}l z&~}p6z9qC>OnpaayE(=G39W;v?+a}YQ$G~iMO?;@g|?Tep9*asQ$H8lex`mQv=mdn z650W#ej~Ir=ki;jbu#sPp>^@oKMJjzd4CdGhNFFNkSW8s#s{F zOidBm7^gTxXh)cuDzu|al?&|{Q!|8ioKwsa+NDgLDYTa{RUxz!Or0&X%b1!gw97f| ze4)LZsf9v&1wUOZv{y2vk4fv9)iw8}RG$-$IY~ zVNcFEeS>|YI3M1+F32kvSozRw%$W(a| zWY5@OrE{TNZ7uC6!cKQN5oYW@TpGhZ&7xFHnh{i^Z17N8-`p=qT>4#KxR)685E; z>iSNoZD#aH0x7VIRo@|^$Ena6QS2+&lmAvK{)A_j?i%d1b@rEeW4>*(@*xhWk6xZY zeO`{nuxdf7ibh{~3KiE>!gx1x;a9*dGj-)Dq^qex7CWtJ9bw*z>pHvAbfxO{^e|4A zZ#mYLkvFVHqp!nWSPKe|G|}ia*cS#Vd4fA{<#MuA=hsKCjlLlfeSP$eLSKzD_Mw_L zp=BH~zLy{xy&m?*hy3eWgZp@Rb#a0F9DBubA33jBBKnr-jR}1)dXqwy9vi`S*Qs#Y zPLa0ht`^Z-qPHfZS4ZFK(sNVa=twkr8+L>8rt%AiGuY7w6U1J>NopUN;z`SSXFPg) z^bTE{XK4o;i!;NxB(Z8_Xl%GE(>K^NRJBc#ZGD62FL%bYIAL-@Qit`o(xx!%y}?)aA2OmnTt!T7?K`=d$ zh`uU{$5CX`7Lme@(vb)V#{i!GFL>}yVs!XaTB(G*()HeYtZf5f9NM*k`F%eaJp3;h+6 zis?dsHB%;12YA(JED!B)6xY6N&GaOPhtqI9=PU>iv^HyZ4dMRRE*dkc2F6BdxUSlT z)Q2+NGWBW^i^gJbNHI9Q()8gkQZWjD|wLlC@Hf92!&(2xqv2z4xqAqu4VH z%v9R(Nl9fiHrqYJu-Mcjv9sc_Gh-FH*6--RI}`B6{_7rZ%_L%HCr~hUntM&M7V~LV zCg#bl$SUeGVs3xum@V8SYI^QA1V<1Dbz_l=yz zZlT}ES>Q*7LB|Ag79hN;!EdMQIdKZVW;k(L=(liUd~#*bd4ZgGoX!@4Q(m&Wp{T}As;A&dJ6^-2p+%&x#p$;!%H*;^gB@w$Rb`{wV z#!I#z5C)wD$uSTHo$<&q5C)yz$T1LJGsWXbUw1z`>$|zlu!s5{26Q)8BDf0g^SB>5 zoY*S-uiJ{px!Cg9J)}W=!^3qZ_W#zos)9ZkyN?uqKb3Y1DF;IxD+h#EInY*2p7<<{ z`opZClRzks<{C{8kBZnM%>5|k`2p%pvKrVC{z29vzT*+(#50Ha|A|zk8a_T1`!rSV zaa69eCKh|b_p4I<;0pe!&kwf`IluPj#Gb^j{n+OcS_OXO>kn|Xuvz`XOnnK((6OCT zheQ~3I48$I7r_;P?!7cSTn+3g=QvxmaC~2wxhEpEq(EtcZ?Cry8FDDLEi@rtD!VJ_|n(c$jjyG*ZRSjK^ok z&%&@o#)2E_MSKo21n+E%H{31abD1{}i~U^40xaG#wFnEkOkoE24Til;=-+0l8q4Jj z5O!_Q*`!h-L>P1eDaSzgDz*~K*qkfOzmqBaLXJo~kDtqMuo9Wy1)C#;7ceU+^#9|M zn<3p43R>rK zd|Y&B@w+iTiugh1_X+(O27tMcL5HQX5Qq4lk*zYs-3sB08b8EPTAuhjB8Wk_hI>) znr}+{0VJVcu4jiX%J1sy9zBR9`7`4WQ9U1qli!7Dp$bf>%T2&OzD{%JWK ziQ_Z47g!pf!M(`TlfuxL!VAd;&fzIxn9Tcu%+VhSqm-$i2&0@S zOfbxYb*p0WXM{1ES-%uU1yjEk#yqB;6~;oQekY72O#MM7ZHUF66Gj!Y{w!HtvG`wv zQOm3sB&$0X|GO|&Fbmh5O}8xiXy52TS*PS+w|w(e8IAu-*Jj%FA1^=yWI~I_|DC{l z&RudfGJ*G;yQLlySOudW^XU=i91UID=_uPalX0v3S*|WS`K}g;XaY-QKTO0$v^NTG zU?d7AX zlkOTF8a^IPOo8LVPg569*RFKGQcy`DaB!%5Jx-hH&x};I4Gmo~c4)P0rCZIMT^vtB zd98EcYT-DL&SlPtGZJNqL}_9wDm@L2=K9&MRtVRQ4az0PYBbuq#PkwPPhcX111qfd z_t`$b{2Z6q{Tj%6WrX}@C13=zMfBCI`?CO}q6CdFLqxA)RwY<-OEi;Mk27llSPM(E z2(g}G))KImmS}lkX?tZ)PGE+#k0}h2`fmJ08pVgr7V)-1FPQnC=c0F{%!OSVLP)hVka&nR&6Y?RkCQ7mDo#Z-vA_Xqw=h=8E}7UP z41Ud**ei_ln1_i@H}|On*pd)7*H+(Ri1ZX!&GVu664F%#tok zAkWK1^cS4xE0E_aOSC8q!nlx;ULlNaOkF9AolIfLWRPolwJH=;99-`13e8V zhx*4xMB+O6<2vys5&Z*~aXreop+t*O8GAYHO~Obq1*hG~)LVs-Vd^$v9AxSp!nlN~ zcM4;WsdowEFjMaq#wb(o5eC2INW7QKlnmqj!r-?Ti4O>a-!ddVh^;W}M(-EVzcIQG z0o{WoTAa}FD~QC0MQj>B{0JUCQlcfOzl?EZ@s{lfQy5Q=GWD2<&Ef=~MuNvnv;s=d z#2Wi7_7O4lIqV~1>I>LM#MBqDkBF%+3xi*LB)%$)tGHfY6UH@6eM1<$yq)-#Fy6#G zjD$BZ^?$;+iK*`k<5s4AD2&^f`mr!>XX>Zu62o+UqDcHa+Cgso8Q1$IX-UzJeu>Mk_6@g{Ei;Ml6Fz#aN zMPa;`sej6bS{Y0HTNw99Rslv3v|W9yz!U~A%oJddGY&3~6-0%>YZ?V{VLZg*1;RMV zRG~0F%G4xbe4MFbVLZmv6k$Bh)EUC~98*(;@f1_#!uT>%!22{)vxLFFBn!?I2LF;Q zs1OGKvMV@S7(ZY+Y~|S^EudgNe)dooz*_+N69o(9f^ESfVf>h7mk8r$Of3_}FPMVw zeT7tV0etT(nS$?q6;trNuVxAdYh1xpBewl8b&mX13IAJgo-lsR`CUM(`B*r6RY4Q2 zE!~fuK`h)NVryjU6s((+U$DMJn?w!P%B+oGwUua-!P2hc>R?CD>zLXijNfwR+l284 zrgjM9PfYC+#$TA~5XRq_x=0xRU}~R;wQ&(C6mg(LD<+%xH$UtWromK3n0ZX~3Nyx3 zA2ud2fJ?A3i7SDG?Ng&!UlW*Jj26DCgx z3oawmS`jOFxiDw)vsa4Pe$L|6$l{6;Z3<;^CO>?wFy}D!I@hdD4q@Bix4RBD4`Exy zvC(J&Hk}mkM5rCBVwKT?YthHlNH00$+zZ|qFL*=2b+Gtt8H@pEF9m+ow?Rxz)ysoeC-av$?=I0w3+_Tg(m|~koD#R4*7fFg ze9Ixny9?e+sNW}IcQWLA0QmzY+8G6RiP*!;x(}@TOSCd#eUn)ag7r{|HkDY7)ovO(mg(MspU%;O$I;byw6|hj zQ?86;oDi@-QSjM#!DkAd6y{vEQ~X+c6ZfH~gt>ruUlQhGroJM~WlTLS-7Xx-*M(Wb ztZxc)IaA*jW<66_>NO88uZ|Ub4;vUc-yaCGkstm@nCCL}6JcJ!)X%UvljWWfW;64C ziEWz9`?ZKq=Favkl-D%e{2or6_m- zS;l@-@HZgDOfgpQqA=T87NbmzmWI2#M*A_-LPu~f9upUu`?t`rv`ok5O!hyG3fL-N zqAb_tx@k>I5NniK=YVx?iFP)zjx*~5u#zQO zC9$qx)*7%{O0>Dex`tWn!D=nh<`L^n(n3TVSer_;`D7uzTx zrhg2BS;T8QmpM?!29_ysY|^DD+B6&1VTVfl4~ zpiPycLtG@xenzlQPPAler})_cVGi*#yx}m?M}_F-LNNRd^8*ZjV@%-rWyZG6A!0D8~X~lbm z`3@F)KYrLCylh$i~fL3v{onz z3;4MZCeQKW47$&XpAi8o zV}yn7MB*4>p&O25j0l77F5(zrp&N=gMp)>+A&wCix>bl{goW-1;uv9}n}9e*Sm<6K zju95Ry@z9jh3?|v7-6AXc4UkQgYMGd7-6BCaX3a;=>8jy5f-}5hGT?WtV}yn7hT#}tp_^W0j0l77aN!tXp_^JbMp)?H6^;=Wx?P21goW-( z;TU0|8&Nn$Sm=Heju95R#e`#oh3+Kb7zk6|n;hlscR+(UP^dU4#DPP_K_Lz#Dh>*9 zU{P^Uhy#s^gF+m5R2&rIK&0ZJ5CP+XFdHl!;-@j!S&Bu}(dg_-L1$ zic5U7@lC}gKHA8n;u0TiWm0j8k2W)@xWq@>nN(cjqa8ddF7eSO6pj;R*3fJK6)ds;u0UdT32z2k6wAJxWq^AvsGN;qqo*7F7eUZXBC(D=*_Z< zOMK+NIZl*WL#|xKB|dWIDlYMnJ6Cauj~u#+OMK+gRb1jDr>^1>AGviEm-xuBtGL8R zu3g0?KJw`tC(5iL_pag+A31mxm-xuVtGL8RPF}?&K63LaF7c6nS8<7tT)m1*eB|s^ zT;d~lui_FP`FV~LW!8|(S8<7toW6=neB}03T;e0gui_FPxqcOw_{jOIxWq^9U&SRp z8UR#W;-euz#U(!S{TwICtf65*#U(x(2vl6+qoF{>B|aJqR9xbt;XuVDJ{k~IT;ii4 zLB%CL8WdDq;-g_f#U(x(4>(SgSwlmEic5SnIH$ z_-Nozafy$H4i%U9Xz);RiI0X46(@Xrmlcg4l0w|VCn>}&e3C-k!Y3)jEqszf+`=a* z#4UW1Lfpb9Da0*&l0w|VC#flw-FQvFuW>W{vKHGM>H}WKS}%Ju-7JPBHs?jEdWC7P zS6b^N5_UU_@UG+ucj#6Hk$6bWK;Ukc6uF-clPv+UHjNT zXJ%M&O4{&AWB*Rv=Rp#RIhiYdVR|?{kijpF5iI|-Vi99letDKbG{K+j;l(O)E#Jzk zr91mZ`jAO-aByf;ekKXQ$=F#jir;?eL!2jAleVG6bn9S0u+VM*tddC%;A<6{p+)eQ zuf=f8bP0W|k0sj@`YvCF_yk{u_yAvq`21dm`1oFi`1D?e`0!qa`0QSW_~>4S_~c%O z_~2fK_}pHG_}E^C_|#s8_|RU4_{?60_{d&{_{3g@_`qI<_`F_*__$t%__SVz_^@7v z_^e)r_^4in_@rKj_@G{f_?%vb_?TXX_>^9T_-I~+_+(y&_+Va!_*`Cw_*hQ_&8pM_%vRI_%L3E_$*$A_$Xe6_#|G2_#j?} z_#9q__!wS>_!M4-_z+%(_zYf#_y}Hx_yk^t_yAsp`21al`1oCh`1D1R_~c!N_~2cJ_}pEF_}E>B_|#p7_|RR3_{?2~_{d#`_{3d?_`qF;_`F?)__$q$ z__SSy_^@4u_^e%q_^4fm_@rHi_@G^e_?%sa_?TUW_>^6S_>f(O_>5hK_=sJG_=H`C z_<&u8_?7}Xt$sr+^W45bQ4`sAw%3M zAwygVfv|+GOpxKbRCuQf->t&CRQMhh-mSv-s_=a(e7_3sQQ-$vc&`dSsKWbHc)toC zP~nGE_@D|OQsKiY{ICj7s_-K!d_;w~072FR*B{6bmmkOwS0Bg_7azzF*B;0ammbLQ zQ!4zl3LjVDXH@uv3O}pDCsp`46@FfYUr^ywD*U1fzof!1tMDr-{Hh9{R^iuF_;nS2 zLxtZ|;kQ)yZ54h;h2K>nE-;Yw!Sw|)#N`Dt#MK2d#Ki?N#I*%7#H9r?{D}&Gs=}YC z@aHOgMuopn;V)JAD;54)g}+hZvnu?p3V)}<->dKsD*U4gpHtzVRQP8VKCi;RsPL~U zd_jeOQ{mrLhzkg0eQ^DN3~~8@3~}{<3~})Qg>>zJ3~}jz3=I{UDvYQwPlfp^jH)oE z!ng_(DlAZ;P+_48i&QvCg_BiStilo%PEld03eQksnF^<>aGDCsRXAORxIjSG2iFJ4 z5SItY5LXAt5Elo?5Z4CC5SIqXaE=PkR$-+I=c;g?3g@eEfeII@aFGfZt8j@5m#T1? z3aeCDt-=}=)~c{hh09gALWL_;Sg*oWDr`_;BZbC&I09g`evW1oy&knXff)h4xLx{) zzCqL47B6~O-?VAT6I$Mq`ySA@Et;b5Sp2Zw@vxqHSnt}jc+rxF_1;}e?n45z=vw?+ zpy~hAN}_r)st*>u0gQYNW}}T1y%GPOg`D%W1^Pj~58MK6j()Lz34AR|)6doWHLd76 z(0RIkt~ME<@DgQ0K^^sgI%I=790m$6aIyt8nv14x@PHb#K^+MLg&k273hHJLsAD#$ z<6)q%Cu>4M-R=SPG8@#1Fi_YYmMy594E?y($b8cBs9C zpsuh%y(SFQl@ko=UQhGA)&_M|7^v4}59*p+T*4C`P_MT^T^k1K4cUXb?!O21CL7e7 z!$9HnZnid+lk@zYM^iW0pxzP&3a^$Y6x3fmpl-53-5drAFSREW)IU9-ZnZ(ZH4GG9 zr)LW)7n{=K9#FU0pxzz^3NP=o1@+Dx3|&unK;2=3dRG{zJF^Fslcv0&-fe@rD-6_o zvIq6vTr^eS(bW5FQ11@|g$=>kHeXJlCVN1Azy@`17^n|s4=ShTo9Y2|pAG8%Fi;O< z59+~Ons2%X)I&C?hr>W&x5$Jx-wY3^lQyW2gn`07m25#hnv15+^nm)94eH}zpgxg3 zsGJP_EDxwp+Mpf_1NEuwK|P*}rYb$4K4XJ=A`H}Lvj>%vrsjG;J!ymbTo|a&PcWz@ z9#CJfK|K`)>WdQ$s>TEAOE#!4hk?R@0@?Pyr*pBXqzBa3Y*1eh1BD%8*@DXDcb~q; z1L~VLsBeXV!alVL1$B`J)OT!9-wgwW-E!H2`hG6Wm-2x6feq@1VW56A!Jsl8P(QXo z{Ui+3PbV1EB_2>evqAkl4Ae6d3~I;&>K8VsUxtDD)dYj`E-(Jt2KAdTP|r>LH#)l6!yzz3o4gkM)Ufqzu2Ju z8U_kmce4eR(^8NZ)Zc7Se-8tNUBuaf`ezOv-KVL4*`WR%0*cO=$QD#i&3C|UQ-*GV zGK?@#X7-?R(v%le#0HfY1}Z;$P&qA{r9GO8+Mr@#pyCq@s?!51VS_3N10}KsWfbLN z=v^LAlWb6v!$1{h4NA|c`MjV?Y*16eK$T_<$|%c4Q{5g-O|?Ny3j>9(b+dE{#*AD* zc_w+rOdHg!Fi^9z2BqiZr@Wxfv_YK}2C5=!P{!H+y{0N{P;XC(i^D)I$r@B{hTiMZ)KVMNvM^9pFDa;M8&pjgsM?nlRGkfK zc^Ie_S%b>W(EB{ix6%ex9|mew_Mmby^w)YoHQ1mU!$4)ftt2-; zsoZ*>7u5MSs0+eCC9?*V+c0yrr}>&}P|abW)?^JTx90PLYOz7B4Fk0hW9buq$W)CVSL-&H(WrNxs1`5YmWZQhXtfOnUd75vJ4eFvWP&hXu zTTnTTeed#s+Gm5>9|j5sbYuxCH=FW;I$(oJhk@$M9#l>?1Ry?59M+dE9BDNd+O-Q{UMd+)Fjws)A$ zbIcM{ZZ_owW$zs}!uAf+(UMt$%FU*{pzOWFM%dnAI><6xP&uu6e!$aw_TFJ5Z0|6g zZka8p*W|K3^@s=5m3HrYZCLNSYJx$1)C1~uHmIw^KwXnPsGMBFqaIN9-eDtb?=T%d znq~9l_G`uq>W#Lht_#!Do3aO$(diK&>%&0ZkTs~>T!I(WTWnA_hJm^%dr&#q z)W?KsJp{Jy*GPMIrTm-D0`Q+5w^>k zj$O{uqv!U+!3)aXWo?A*vZjNdUqVp!E^8xfmo=R|oh7K;4E?JfL;sL%QxAsO)I(W= z%FWQdpdPkCeK-u%$?QSpWawT{AF)9_5(es{S%b=LnDK&o)CTpjFi; zP>*E~DwnO_+S49G|C9~t(_x?<&l;5RL@qxZyr4d7gL*Oy)aSAWm77cWnnzQgw?Ta& z4AfIugUZb%ctL&92KA*dP+!g-R8B6z3+gL2sIP{BdU}FEecjW1_I`9DY(F|(IxwNb zj2D!>AKeJsk52a=WCQ`Z) za6IsY8u|}B&G#D{)U#ora8hxWpmMXR-*`a%&Ia}SFi^OhBuh}a*_0R5A8k<2g@O80 z)}V5;DKDr$+n}Bg1NE1zLFMK=pY=4~Uu{q?gn|0oOA6}mHmDcFK>gz-1@%uG)W5<& z{X2V5Ijv9q(cOHeW`Q#G5KwfNPnNweH$(S=GHp`6x2c+)S@s@izgV=3Xi6i*r1k%fm-&Gf~vAXRfmD9nP5;WJ({YuLDhwUTK)YJ&$< z#s<|B2C6rEP<^>*>P;R{7u%pN2?N#tl7bqrK@En18k%5GZ}w>FkPYf^7^vZw6x4_f zYBUVg*aU;R-lM4_HmIXvppLzyppM(1E)4_qvIz!tgGW;*Y*3elfx7%91@&?p)GNY3 zy>fy!$4g- z!JuyPXzC3%s5gdz!d=VRPF->ukUbXxnD(jPX4t9UbgA=%g1W_{Df`rKGwjrFx=?yT zLEY*Bb(7tEH-|OfEfWmN^U1Gys}1U{VW8eN!Jyve(bR1=sJDlKddCEVy3GUXb{o_? z!$93J!Jyvm0rf5$)SY3Va7+1w8u~jtpzg9ky(bLR-4hJzb`Plc+MwPS2I~D24CRLZBX}xfx3T!L3utSHy^M;eJBjngA)wO^LeIepO0>aosVv2 ze?GdI(}4VbPxIO5qnlypqnp{EkDeQ-dpw{%YB%4bVa@lk32r{mhpgtuZBU;G1NF%X z2IaYL#(c~M^{FsWpPpb)AM`Ze<2IL+nf=cF+(3QU1IpgHZ-(vM zH?!ZlpBt!?9#HnqeKTz5zM1{b{oFu(!~@FSxo`e7%%f+&b3Zpwk9a`YJNM17o%?3? zJNI(~iIn2G9yudYrj`L)a0@ft@Elz#y@xQOvp8&E~WB7>woS+yZ;6{>a}XjEwcg$?3wNLFby zGNuX~)uQ+hSJ^K@f#s3%yz=~$k(UP-yPhR&jTS|YXgj4X7e$UnULlJuiX5Y2DaXih zP}ELEkxN14N$O>w@+GM9d?cS7If}ny_&bijOY!$I3GkJ{7W$fCVB;UiV^saskWOWo4yjBm3FMklm7Bnp0KYPtTKBsz;ll6>;BKKyW zHKv`OEVVlVTlfFjyAJp$iY`8zws)7ph0uoHdvAfzTOgEBLhmi~BE3s59-ts7R#52{ zP%uF{sHlJlh}Z#9(ND2~6e+^@X0FZbz1^%HQun9Xz5O%)H#2YEdsB9H_n@iPB`Z<# zA#>zaDEY8C@@kZP)Es#YN$SpP=M&=E%oUas_kbPf>CubL7uZ zausvr&rx!`Ir0}Mxw<*>mngZ0Ir3L1xt2Nd*C@G;Ir0gVT+bZ&BuZ{zj(iFwH!?^5 z1|>H(M?Q^`lgyF7Maj*~k-tO9EzFU>N69VCkD7n8m@;Q_| z&>Z();N`BTHIT9s5Z;l*= zl2@1`N2BBy&5>hJ@=9~$OelG^IkFQauQf-GMak>Uku#&@SIm*)Q1WZ$$XQVGMswt> zDESR@UcoC76qF-N8-d8;{cPL#ae961+C-f51U8zt{HN6v$i_nIT; zMal1&Bj-cO`^=H^qvZF^kqe;Y{pQF8QSw1^nALZky1`C||wBXN;G1tBsD7kM@ak`RC>BL3;8HC7K zT;#%!o zTx56>@WIkMEY!D*z<09jN5Lo~h znKcNJ1#ywtgAiE=7fFKktJ}E zMS>7n5*Jx42$7|5ktKoRBgvd&`$m&6etc;7S5roJpxX4;Th^&f>tP_ODcwA(?AVgNfMK%aRWOZC* zqaZ{k;369bA+iQ8GARg=HF1&6f)H5?7ug~Rk+pG=ErSqQ2N&5o2$6MhktsoltcQzi z7lg?AxX2Dch-`q1>=cB^hPcQsL5OUGi|iJJ$V6OZk03-g#zpoDLSz$MWS<~JCgCDe zgAmyi7ui1ukO9F z1R=6FE^=8ABKzPXpAJG~UtHv~L5NJnMLr*d$bPuU6+wvXkBfXU2$2JDkt>4`IS?1Q zItY=2aFJ_+5IGnZxjqPyLvWF=1R-)LF7mY?L=MA6ZVW=?a9rdYL5O?^7r8kIkt1-C zX+ek_iHqD4gve32$gM$$9F2?I9)!p-xX7JBh#ZTH+#Q6-ak$96L5LiWi+m>tkrQx{ z`+^WT5f}M>5F#hxBKHR&axyORU=Sjw;35wNA@X5dMYza6gAlnG z7kM!Vk&ojdF9#uV2`=(V5F(f2BCq{>k)%?@6Q0-M`aeAIX2de>D}#$+-$fu*BG{{I z7r={dMe;LRa($E>AHiNut0h0LB{x9H)zO?+Xvqyxasrz3i&}Cclw1SNd8L+|h>~lf zlAEGr{vL1f1>EgWax;|tjyC7^D7iUG-lrvZK*=po^7~qHN0gk5 zlJ{%LoltU1lzdQ2?u?RKp)PqyOYVY_TchN|T5?yE+y*5d)snlRsckKJ0;;gQ+ML~A3f7V*qU8Kqvipm^TJj{6Tu@7Pe|c9+o{W+UYsouNZBIeT zMYZHzDEVPj+r_oyLnwJFN-n7-e}s~!p~Wt(B_Bb_(@}C+E%_))o`I6fYsnv@Q5SJ&RP;t>K)jC0WZ!a*-36l>;6Pu zGzq;^ZkF)DJeFlCmSt*M*tT1i<=eVh!YB1umStI% z{nEnr-kL0(RPC=0@O%|75!A)LF_?RkI;>>6`p_nIOlZ0~K3$yzS5wl}X?xTe+Qu3z z*jR3LAp63z=L>o2K&KPL&(sq?TM|DP7e72B@$-D*KO=Vjt((-b*DIWjdPSU-xhU!y87B4btAx=)Hl=B zxA^6@baj_h&^_LQD#QlHl~Z+jj0-*%eUs!QAz)srx_~IE>beOZ8TDQRI9OGe3SVd( z#p}jCDVvi-sC(77!Kzh~TYZOA=FQL#Q|G(B`hGziyuJhE`o5=E-#BL`p~mBkYP|nH zs_{6f#s_>gKIp0O0IbFz`f5A^YRv4jvAf0}g@+0inq*X=!%~HgdYe$5^G*_Mtua=T zk9{S10~(5b7d9Ro;}iJ%6#hPkzpvoWYj`J+hB&oHJ(aG03m^3)SxI41%x64hnei0! z8H?6+Pw@ zQ<S^VQ^cqniAoTa)upiwl~XT)I6qc|oelWnWGHGOEcHZ%slvl1%Jt%t}$P^G)gv zsDsC*Yy>Gk4`%tCdHuc+OV&Gc>Blqh?v>#?)ft^andIa$EKJ%$%J{-$WI`AX69Of4 z2i`!*Bv;Xwyep+s7?YV0PQ$rW_~x`AHiAa@#fHgJn;A*nV~a?)Inr&>q8r;XdEGda zL_!G71J0C6Mw4-H-bN0Rk9^LxhD6*Xd32pClt<=k;8r(D3JLSXZ+{F|CCuhc4c_>I zYReA)gSP@T8Qc%@fY9&#b9=EGfa{3hT|*3yE9>C6UWp|yb3M7DoD#ytX*NLdi#fWdSULyhRGwvH}KQ!&ZtSLBN*7Yj6bbI&C?1tW5~J zv1Ef$+?Bdce}e_xb#CxE7<8SsTwE{Eb=q=!91QC^ZFzk4?Eqaj>qyFMvK1_uZi9Z& zJJ9hA2x3W^GYTxyGZ3&9K}J4lybSI!ZW&C!MSc0n11no`e}0fVI1DzhdRq{W4XkXX zyyBH znnQd8t5PI^)bhD8_@?my%a)HjVs6P_y-q0lb*RdcLSHHl$KK-#Xa2%$s+!NHs&kvF z1%8#leXS(;S`F@NpmD6-YkC`oJmj&nL_T1#)fQECz?n&3RrUO;0t;z?TgU;yLK3lp zH1rijV}MW|ufc=(Cb;--1@Wi>Ci%qA^bE{8x&5h`I53MPKR65M)>IWnWOYdZHFK zRI|0ytw{%{NheKBy4;?cT$XCm)mM{lMm6cKTa%tplir$|^u0Yb`CF<r_}4R!U#kxJ|an z>9(o-D8_FnLQZ|wYzX#V&x4d%Af>n0djx7TAO03P^NEFUIE(6w<2CY(DIYV_yC@E4 z8GUhL?*b_eY7bK}t?C`l6n)7f1;8SdZ(#QEB4FVm-vjm%V78Et09y$d z%xy#ehxOX4ym2*Dg}4d}EFsT>)p+8n>@YEgw#H-NT2DL_8a>8zB#e=q!W#)Su|1R1 zV7MD-@R^)d^-WIl@k~aY#yFpGW|9iYJ=fEjtVcT&?zFE2IY z<0%a!r*9;mCBFyg0rk`9>y^;DUnP5$1$nJz&h_s~fd7PWw zSyo@zII;fOow@Z>O0AIH$Ygi>qH#9KUZMB1HGw}iVSy0?_>APAIh-~1bKfVHGlx+Z z=N~oa;MMUC3|a1MRVB{$e!A^Iy6vE^l$0;U3+a4I?uT@yN4%HzS7WPKxSY-elhw#+ z)XLIGIH%KKs^T9B=X6rY+FOxlrAg6Yy-AVYh$EMgqe<4C%cwa5M;y6Kk2rFf9&zL{ zJ>tmaG&|zRbOAQ;Ky28`K-wl6Xbwx~#SQN3uHv;Ja_d3F0b;2{! zN2VPxA8_ADTzXUK7%=T%Q-Pc09dv@>n`PB0E>v20@H`%fWcC?`a3o}`qVo-3hM?1gk+(wyMqB+ zmXV`tUQ^Qt#{1mqaN0x{%w;`K(?3$p>ujf+()JaPQ78HFw9Kll&*CEqDGRep zJ9(vO>FM2lq5iwTP;Wc4$95*&_EWm;H%txroQ-vhDXSr$v!!lIP=ipLe9n0Nl&}n= zX~cZa-ulU~S$`PCYGg*0-*kM-|IgxEe$(+Szv=jv-*kM- zZ#ur^Hy7XXYvWspQV`};m0>xhen{((w!XMl3vT`>m38A9+;`@+c`b~D*%z`Jc~pjZ6WIX$s$omJ%~gXSR`WM1dBQsy-_EWEe1o> z33(hW6w(B-7)6@`q3L(&MokYvAFAHN*vOCUM#k&+tHM&b zM8CT75B;i$>7o@eDq7&Up@?a}Dq`BNikSARBBuSSh&jJ165v;45m`ZAg5}D>N+qSL z5M%*d|_!NNviC7)8n>sKH(!giJU6?qK&>KgMar7HN>$}A@Hle-F_AF zIObP3ynYq(xo0u3pPpY8H|tkZMZYR;+OLXB_RIYW#`e+3m2kVWoOPltU(*Mj?N}KkT(x!c-v}s={ZQ55#oAZ^@ zT3=DfRmHAE`Fw=0>P1OD;#<|r#v;B_9E`sNc}*!v4k@L`MWwWFbuWrU*zMd2u8`bz z2Xg}GA+Y@^_DG+>zvSN98B)z{@NE6ZXGP^CEAy|?#EPa}KEqWSX|18W(YQ+*NR>D8 zG=IP^FBOspe2)o7|05HwVA_N${4*1-VA_N$m^R@GrcJnlX%nts&V(xjn(&9@D{@jY zVR8~TVfRg+a-<+EK)(~Lo5^Fk)sR?iclvJaYj&Cpl6IQRM|YYi zHF=iqomALP6ML*r{3h7g#x~y8;5%yUaiVzdWX7HqwK2By*1ge6A=yX~QrxGUQf%{W zaY;Gi&TY6=2RpZ6&J6zx8-|p6K1~$|O=aVn$_kpw?$#8kfoUp-*U3ZIc}9z0luWnh z+?(tL((Q%$v6$%3?fKe^!HTahJhXSl!JNpuN(14+UIPAd!(S;;U?$r9dzJruE^ZL0ge_z=;I&%nRWB<;c0nm1%og`aksgA86yYsGW^AKg9d0+F4pGW0m-bRlq%)v{yh!y;v2x7=$&s z3SA7g{Msr(J5+LN)YHXTN4L`Q48DuOreE7mU!}W9?F(;k4^c`f2@34sQ+`pdDK~r$ z$9D25wR9a$ylK5HVBC2VZhVP1%VFy0b4=K|2fcB7(pBj|K8MwOW*Tb+^*Vd_r zv$}ri{L!F?R5Xtt+XFPz)95ClUs}&VhjPbEsK}T&d!l;`&3`xX{`RlL^>XIbFS0a+ z?xnS1g)D)Y%xa(Q^2dBu>)I|@BU^~z3l5oKvj|bT6PMCMDWddLMk(%>(&Pv0S`Aj1 z#Jh~g!3vwYyA0)P%;K8;Ba7>6*5Z;y3+QXQgXt?ZtJdOLnY6gne`Il~<}5B%Dw?jv z^)qL2{erT%{-!Oi|1Gz;zF={wU~&Dx;`;jrDa_(p`z)@Fk;SEWEl#n)<{viRTEt@< z8=bWGh5JF0y1heS;rbg%NuO2Lmez-2A`i$;3bK*Nj;xm!uahbsi*6g{yv4f zrh`2}stkfLuloT;=92Y5L0!0l%7ROFbt{N0!d$YOPeGr%}kn^CJwM{Q+#4vxmM2?M;DUrk#11q*ZSd22^0U(UuPwE&4i~ zAtoApxHD0|D*h4FaH(j#!EeHryI85g;Sm|VJ6&jl4;_ug@b!N@W(*=~K`M6ABt-Fy^!Q6*Nl9>=t>%Nbm^%bE(WDM*2Kr zl#xe_Hl?7kQklI9>LpmvSQ82wXHG%mq|9!Sg2sY^{Ex9R1&#A5XuOevCioOI#~o9Z z2wzOCuiC@HNj&kAp{G4nE6N^GuU8=53xiLi5Zs z(LB?QCf|OAPM0#%ZJrtCnrDW|=9&3lG|x0>p6Sp$GoX3gFR$}e z3%rLtyLZ~>J&*dlXO5&X-aNtZH4{Cbo=T(>VmY0Wsq=8x_!NSYokX2&idkg5Bmn#Gnp3gj5j4Kv8Z}y z13tj^EOfEdr_v&x_oik8Rj*k%8}j=+LQ0Uk!k6-mbo*wm4@r6>XC4@&csXx!=`VUY zZtVfdnLpjWCEdO~-M-6PiA278)Jt?%Vx<{kV`qLLM>lb`NR-Og#92^I4YgmZn>vZ# z4iE|jsn?6C)$y!0bpvYCRI6lA-76wdDpWJx?a0}@CZ=|06R5Q2NH!ZqqLfVwXW@Xl zzoDBt8A-iaH+4%yuW7oeTOp~p=%#MXw;;>v*{Ykm4Wi8Lx~Wt6Bf7Heow}*pA|=_a zo4OqjU$X4Ix~bbEso&8}-2o}dKHbzE5q-a}o4ON{dcSV!&PYiPimAErMg+J>7i})! zB8LKaNTleBguBCLh~1EQcC@502HB%C27#XGZFk7^_fF0p&Pw1-_*$b~*cb~54IcYr zo3rLiQZss>&a)K$KDrbxKTQW&x7979jn6;5kLTI<>+M7pw=ILfAqE1|B93u&CU~BL zvmexZ3XVNYZ!aO#yQk5k^6b9KAwIW%RHEoF!%Gd&)1ak1TCh_)du-2snA(NM_8ipV zeQZzCLQiLVLoFN!E!f%37kF0MevBDdLL`mk862mPLIzPZ%AY~H{qwYl&qeB&oElA| zIrVEAEl^`mwdUP#6AYAo_1&?+d|=`70y0Jo5A@G z_=H#*%dKh&x)HeGSK$f~E{tdWCKHAhDvpb$GXhL#nKh%F{X6o^`ifR+^QU{|wD4ls_BI z<}N?n=z`~yVQToJcBS5#%6n@(8rk-70UU!(;D;RR_yjquBeaDyGpVpI1w zGIZ!DAPN+sg?K5h&_Y5f3e&=xQd~nyVemwUT#APJmMO-qe$KJ_35BOgz_>7qN^Wz&ODxkJ`S_gpd!5XNnayliMwu1z zXZC|mW+TmJHZr5kiup79pH60Djqd-6Y8-12K)D)A`7`@jC$ouWGn<%EX65{u{Q`j# z-eqwEx;=Qc8k=qVXA%&6oi_eHHh|d+H{s;;|1*E5nxjHWr*JT?N-3RS+1ODfrIQM$ z_>@lY`Y1>Bluk~tx-oH%8W0K?TlGv+95vyeRQ^x3-T!3s|BLUfYTmVrDbjm)9sy5< zm8>|Yu(QxPmCus!;K|?R6X&QK5RRrAbt%w4IO>aov#CZeW)L$2FG#8E#?C_hVY@QOU~0U=0f@KB=oWDKMlYUKl|ZFT&sZtG-4)(ZLM)k{p;F|RKutHTl@yAb z(56NF0r8_TcwwMMXBpVL$4Qd3P7+II8BOo@r8}B&H*SFu4Jx-mzmWQOls$!PiRCpw z-@JTg2O-bEw6ivjdtV8Offsx#Z*acNI=QUXgg+h_pbt4=$NXfThHs{_8GuQG%B z=s(@=sZR&2SOyCvzWQ{+h`sa+Db;7TQPka?7IB^p@VX}yqs7?Z&e4Sy69#w1X>s@9 z&b_rK(v~~eQ`@h^RUxxBG$~sc1xU^T6mi4zNZ>Ms!9B=vl zw4BiLV826Eq{Y`h0grUXrQ0sty_s!;%zaURubBx zGOaAOg?~7)&}f;4^W7!kJGRa6M}978n*Q{nSO-$-zh#O~&L*?@(o{CbRl~5XmYL3KSw>mS^k)^}4qNdwp10m?8ZWe7 zHCoLdj<{i0r`377xwN{FE`cWa(~0f$tdZ-uJFFVC2AB8ZGo;BF)Z;MY;ZOrlEr6cx5V(FhVS_2-JraF9HFyHG1wP-C~n}xKNP@CGc zwpbg#M?P=RQs9wp$G0zXdjV{cXESK;967h|W*n3`%=1Qb$73nJiLF?bPo|vHZHLNZNMcyM;izd8`6fN zJ>b^8(qQSxCRz7Nr@=cj+)Dw%=RRV|N~ggzMp$EDDZA@8G5Af4TfdEHBVNnpw2@HD zM4IT=8`nl-+L)(%fi@P>HKFhhX3uaJ2B&`SSY@>FR(v-qS(R~1B+(?E_e(TM$h#?R zs%Z&iV7$t7oLOZUXZUP6lU&1r`udexVwKSrXlMziyCs^@X1tcGXfvUf&1rL=hT(P~ zcti`@f~Q+UTL|frX|g|^SkBdkyX?5cmb4|8xQ@0IB(|chGS=^Eqd+2A`f7uKz~Xpj zw-#E{*1Rk))7C;++R!#~SsbqhP6gK(4YXm30=i3~DO~ynnj%PVOWWeQTVoJliDI&CLNY){+kNi^C+o~CAjeu=HeZ__9sm zXa`=Gw`d2UE*)t{ye_X94BmN0JNy~tfc+uxJrKvPh;Y$3-!Rzl&j-NL@-lqS$-Sn$ zOMD2NykQh;M#A#5(DUZ>^}O!&=v~ry{0*aVBuHXQ*L(cEbefuz-Jl2XZC@w0$r&qk zVmi(Frja*D&H1LmUI(t__xxIhr)6y;CZJCks<5jA z{7TSOxQ_{{@+A6@CsI9EAMq=j=jsT*;_LaII|cB7tY?#-BP{FA6U%aVH6hKW$r5UOe+JX)hu3-n2KaupLG(UUN^n z`p`aH;@7l~Ah9p)t0ys4-x#3VE$D87RGP}Ao}{UQ)PA&|Pf2|35o>~-M#};2Cg@N5 zbLrpE{(|%YbbwF#a;NmMrkw^aD3#k_X9fdkXoG=tAkY0;ZBQ86!11HlFYeNR2y?6B=TMTS76rUUyW4234)%vRei3uo zZRGG$@Y!uNv>GSNG?>tMH($k)-P-r8IN&t{tU`_>qO?5*H>BVxbYa4=$LO|RJzp=f zCm`PgIz9AWqZgJ+%GqmRFuaHU!`(v*Q{BD%rjK{33(sgkwefM^KBG6>NX6J^FxBD3 zxDZf`ecA^~93SWuW4~!_?9WIWe+3j{zeXGK2qvFz6anq+TP!)^A0niw#r?aFJwu7W zZOgIbqre9h)RN$O@TN@h?HlBX;dqkIBZktUJOEs!Lxlh^j1I#Cz!9Tf${p5+)8Sm= zbvj&-_z-=_FOlawf{x(nZqN}zx{-9GJDs<$j3j~cqa)5i`dxuLP>-UcnDodHI!cf} znvT{;4@0EGy$A#GqOTrtj?+&mdG!&4!LMfmHinMjMUJ3jgd&fnV>Ly#p+$a0zaY}= z^++svNc8y2qBV1x``iLOWMO|)*zUYd$#xc{baV!JZ(7g7Z95b5vjg)I>@Lplb4vuAD z2Nm5dF`v%o`p8S?3;I|<7i6rDPmJCj;dZ-)bRn0XpDq-nKT03P+wT*DZM2@w;4%6b zmspTKCP-XF7wJjVe;$pg(ODs$m3lblvkNY$Ldws=Ea>tV6218MIWWYA-9XGhO z;@OM7gf8J_DN2_JWm!s>3T4p*%;N^D7y41^xX~9XpzR`y%NqxeJN3U1A>YS7ZZrmw zHVz&)c)5S1_)0j?x5+O#kWVtO`pRyre}X>2^<0KNA?W!@`lL_Kd@_uUu|CV#>X*@F zTzWaWOpyK*eG0eH&oZ|9r|HvNVg>rNAn_UcjGjazt4~v_f)*kx!Cw_IwtQ~17CsJA z$IGb=ZZNXc)#cO%-xOe};jM}OdrO}?4LWp|x|WnWmOQE7>5NNLtFc?bus1of5-ecC z5CYi<98111T4rE(dzpYL9s!tpe`z!`m+sAeVYJhQZM$Px#e1_tcDR0JI;$^@mTtUR zRrh8U_D_L;o5 z=(JI=lm=p_4OW}ks!e25|LvWcdfA;Z+S)2*cgA3p%Ck%MXIGoqlDrlZC$7b)o{cM! zt=L^8-|iOiu1`3Gsy6KQk?$Ul)B79;dXwiTYzxTq^m*=~ZRzuZhc2hfeIDxWj*&t6 zS)+$b-Gk5-bOo2*o~{t2zd&EWJI}L*Qy3mmUZgK_i5=;Sg2b2TOL`IwHtfawZq(@3{#qipEVdpvD@x--8W`onS3Q($&1~Yt`v&BimvjhIbb^ei@~xm4}@+L!EFN` zIfGnR)73oJu5`7K>l(U7$W=4G{>9)1x4K`t-z(l}gl-e^TT9pS{JPV%LVoM$Iw3!& zbW`{jgIjcvoo~-pnpz+HGhmzHuLk3Kd7I&{2KR)yZ}w)s>E348&^=OJPuKI>^rh>C z+Pq9(_L~~7^(*uho~|E#MM(E5ebt{%4Atk1+y+b%^!OTmjY}LrUlSy5pc{O8bUP)o z>~_we{p2N(b4IJqI<9ff=n-7WHO@IZ=|^{PjYPMOH`0x~ri184p{B3X*ZsQlIjQ(P zBy!%MJ>`0yH=4mfJtK!m?_~nX`j5a!Ul4?p249kvdWQ1`9T5u@P1vkp82mjXTFM23 z0gep@*G<{rnr(rO9OfNxy+PmL`W#8$5cIi;ZW1lWKNz@Zv})tsXBqjBSNdkUnM)r{ zHw)6=q;Kj;@2YPD(pcc4(W(uM1)5{de@Xv7Ub^i3mkh>~-1*1*oj=)am}xYPS9Kyy z6RMg{(?!DsSKUIl@N|>u79rhR^eulnu}QCH?EG8lRxa^jx>b<4jcyZ_JSHx3THrAL zs%huH`Y)XSs%huHnt}7T@*1wKx7W0`)9t+0Gw61q);s79vDSXWy=Jr(WkZ_U2ArZe z(qUXTdLO#vveykpncQaPxNSzb@p#=C4fgK6@%V`Mz8U{gtM?|ULIU4vrM88^p!@5T z{x5ncnk_l}O**gyFTV6DRtb?(!M#pf6Fwl2Q-x~ZTF1Xisg)JRm)5++2U%d=JLyi| zEc572p;>m(U0(CHEkp7Pmu`K!KMJ{Vua-;upDqL>%U+#d*E&j{XaJk)oc@i#n`!Bb` ze);8@=6_~dxc89P2U!+7JN0ZqgE;#jdk4*<@wAV66-(A8QBnQ z{g4o3AhrHS_x{sIsDBUNN{yqAhTzX_zjZ(#^=Wv(awoue)6{F1@a_M8q9Q}$4 z#ebi^&x?PIzAqI21Nwnn{K(@0VIGQa@P;N&@nNT;-+ZbVEFnt|IDu&Wr*UjT>G#w9 zy!4;Z{X*#v&;y#%2i_@Hs+v$f%#8h|uWDNPRh&lOJocN;L3)sv{tJ3gDE)`@Lrv)e zC%sU5qnD_-4S$GSdV^&S$#kk3J>4hh{t!LHOaB!;B$WOm`jMveCju=eK4aZS3U9EA zRpL$SzN$&xAEt+S=}*(cLg|mtBXa2j-vY%7(@x*D+;-1ir{TApc%xgllJ4V;#zTVc zkJ6*O^xx5=Lg_!IA8Se<_*9lsEo0roV?jdctC`k)ymP3&VuaEkqsMsZ&(LE+=|7>L zXi6XWtOt}nW4jl3*#W_<-B&Yd_s8jRUizQtaiR2|(oZ#|4}6eUsh+X!BhQMuuWnlR z)eP-EO>H0Afsa_w9cW4oqm|yrHG2vnwf;*1ZQ?B=NU7gkeDwM|jA!7@LH^MzP~_1o z>tjEopK+C+qn`;X|D1mARXGg*@QT$nyK1V`HR$hoQ7;A*wXU?$&^^BVf_}k^dYOJ9 z6!lB`B`>P)v&E5D`8O3{(l6i4RT^gSDiXML6}aUDSOz;XVL=2Q%ZM!Q%oi@&Rzqh; zU2o-g4BY$hU|by+dEFhu{R?68l5rMs$=JJn59$^vF0v^NW65lT97W;&*xAr%@j?1H zPDAlsr#5)MHW~db?hmBYzl|?{Of1pp zK9M*_1(`{@?dsWLaf+Ve8i}N*1dV({zu_8*iry0yogO8cIBD{)!by`1!pWGpsNCLB9ed_E&ik2IsI}n!nWR0pN)vs*}yy%o2HtkRYs zCCT7b212|@LKY={q(AZ;^V1)N9RElECwfOA-wL!8ESeg;YXJ`yO*0DoKHWDp+Djwu z@SqCng@k{sO z8G8W|A2Mp*iW#dcG;%1(louN8;$cI^sFskSJi1+|d5dAX9n1sVvqI`$=r5Yo(uckl8{EhhzTC7}YgYCiJkMY0 zuRPB_^j9Iz-{@~*p8dQf{GI;JQxBlO3#tF0e`r!mC4AgS^ZrlIJg)s%jGcd@Dd8MF z$MYOS&k1>+r{~2yhk8r+C;gMB9!~!hQeU7KG^wQ$E-}1`=X0VZ0VSNob$F3pGu#)_xEH5_tWfd?cSs}dAT2SCTA(faDBTii%WkmHttq>~?NMo<{iM-2f1JXOB7dzsPuZ(wfZ;q;d|1~($4;e*kunWSeCm1Rbooc&|^ zWtzv{Al8E}LZQB)To;SjFG&|+fP`su0k-gXdel-_hpF$=@>Al6HryjukQ@%|a4z{t z_Dhl+0Z0TY`DxFP0A9Y}lmE2T#q;Sj$X7vz%H==Heo69efY?y^%b{Jg@4Ho=G1%-W zjF+E5>uHC)?7SQ=uwPO+9Dq2`a;!w^`7A0w5@bYj`K#G4Nq!U{QKjiNDjK9j^Bi7fzoZ;u0Et0!*vM=E){Mj_sg>sqwoeF}d|vv5m$yYTL0*}7 zIo@Euq;fa`aiZmT6Vc>ysn_$$j|CaATz)$HCCSeWNM=+%yzl`uxm}~l6{sfTKuR3X zVJG_~<&XuCENBjUkQ%&z)*vg$$jarv&3;MpvjLI~l@DDXfh^6#+QulOh^-}mz)MKP4Y*^mjWgx zOcxaDOSvxgvtN=fasrZ5qYH?P2h*cqDBsvw7Yi~g4F+s{%>lyjcnEus&!q)YDI1ct}~<7sLyoODi(a5fmZoWWWQFi z8-@ORdFxDTb)9Lgu661MMFXv_&seKSEM0F(t6#WBt)dFoo376~qix^*=(YxpZh0Vr z<>AroEA~r@Zg~O8i$=GT;92lMkCJW=^F_~BB>CQvYCe#WkIVmt{gUM82PD5J-@RJt z8L3J;N?tV_sfv1g)nLP+%|DiW6`f@lfD#qprTv!ul1f_;kb;`h!dUYA^r$n^Ec-QS z#O|Hb6asc3F8N3HOOjj|kiw|s|AC%8!%d%_H=wiZA|Rs(m;W>SCCM)eNKsV&Su84V zG&jrMh}N?hEGQe6I@?3X0JG$5r>`4_M`_9nxQ-q)U+&^dM)$g2!5$0hblDo0sB z%A)1CjMQ_p(APucSC6G~x%fHEfN%AWLQW=vUO}KnHa-~a_=8arcKt>fNKboyIR*~da1*EDd zA68#s#X2A+Zb4_P@xYGflG(~#yd=3AAk{?4uqKU3eoHIaF+z7nyVcO4S(9QT&aDRX zU_Jr#tVL9Z5?AN7VXKAJrP?F_lAx&#c;u|~Xw_Lqnl^4V`1lwf3c{F{PrCyLv|F8K zSGczt41J>=VlT4QslUP<9nDl0#rkac;rq(CqoyoilK#+5nw)Gk7~;6c&gj%`TgLNR zWbC{xqj{~TQENcM)!>cF7W-;Qjan0snx-0co55O&DjgB>J)NMx34oHo<%^>#6`_{L{k_GyfqQ9=OJ>&LA2Kn1fwtp>X z<66A^*-~jOsr_pMQrlGfZ_lv(Vfg23f6;xm8#KT4D5J97bn|b|xcRdhHve{~!E{V& z{_Uole_Mv1)52FNcVyiB$ZTYX$>y&EO<{kCagR$8LU`SKPkC)~p)=rxBOO=3k8@d5M4|3i3RgP5HWiWB9kmoX6%>jU`?aK$>WI zzH;nA%aH_}BrcE5e3B%2O#x{t$n)$z<>hDw|JIE2*u18h#A^;nb1lzTj=fSjyko5v zz-htdv3X1jNnSD_$+A4Qx008mCHz}U&SUeAmJ+WOAg#1KUpd}J%h4J*t+_ll&uA^l zYXe9djXZeKJ1<8H{96j=vH3%a#A^#kTP@F5j(4PTJn{y4IedEfqVOfEE22z9&4@a1 zo*c0-ViBB=MtmD_Ms=w()FtYZaQ;rcpk7v8w!F4-wu*3WVe4+|1?LZKCv4xSE_;%_ zv%Q<@a@ZX?9eLo~&oRz15zbp2A2<%GuE-&gQzECSuBcp5rK8Hhc}UchD0aO+>dUAT zsw=u>bkFEMsw<{kOx>6Usw+oSjyyT?!?|*fMmd_mc}|XHIi68nIU{mr&zTd>Wpmca zSs%{RaxTufRCVQ!%AF@Sq|bdbk26o4>dLz_??-u$!ud?zOL?!Tu6*(Nn&fMyy7GtT z&z7I6t^&^%c(uSrIKNZilLDWqu7X($7A;r;&esY>70RT#3Kc3;xllZuR}^}^&}P+D zcy{3@3qK9#*9z|{ycf5eOh}oy zGTGqVv&@Jxqv3qA%#?8@`t{9NVND!&fr-zwj%5~8}QjIA=aic57>B~@dqW>H=7 zvGE1ti@>>heADL*lJLav0;3DBMiYZKl|*si*2W~!OLW+6Bat@&`x>2Tg%^GMBOs;kcRy3uu=s;j~B z1{)h}g7fu;(GB6cVRFMB4STDuM&XUJHG+0&G^x>oMvuYyY@_RqZmO=tt%(N`55f6# z;`zjjs;hCO#tj=cR$WcFcCZs;g;w)AySmfb+?wzc&TF zH7nn&UNg{J^PZPu!;l-4P|Q&Lq|+e~fqw}pDPJ=FGO+taG6 z-TZdXwF5h7pVYo{`);bM!;TJzIvi159s742-*J-a>U6PlL}$C|>O7?Ll+IxHT^{c8 zSeM6DSJ!M^i*+pt=k%`ccZG6yFWJ3D_u6oNuKR1%)f1|qk z)a}!{Pg^(->oc{_3^;$==g&TuR99bT-vWIL!+BQUC;C1G=S_Xz>HD7QN-dfip9=L( zZJU~!Isncerk+RzIsIn!d!iqt>p!jk6aC>lV8MVF2dskg4+E|ZxS_fRCJyW}usfVT z8u;D7A5_<%vV$57N`&*GL8}L?Q(c2|3@$UcJe(r=NVUL zW}2BYLtJLl|jvn#@R z(Cn$RLGQC)n!RQAHaMT3qt1cy&nY>l&Yb$Hi-g83B+8^ml(sj+myi$@{#O?eMO9rl zNx1LYjW4}PR+BJK5`QvP!b17KpHfvw-GoF4sYQks7g^1TO~VqI*uVLTw~javsz}%S zcd-B+NtBKhQIb)baKg^neeO^6o7 zn@#VwBT$Z8Kch(&lNot4Ys^h-3(58mcwX*JqW)u^PbY0jj(?b?nC-veipJT5;y6uq`Qg3koO} z@>a>?VU7g{Ux=7O3g4o#isikPG6T!}87X=T%Pf}rR?8Lq$^Ho`ev3;jmi)hv?F-KN zNXh@8=wk8zEBQhLkR($2KdOaTlm9Xgp*G4mQuaTrjaZ}qIv>Hz%Kyhz603DP@)8;h z%&+2YsGV5D+m)YCOJydhe4A=1*7SDf>8|YzK2ZLdRK1P06>EIE^A&2Xq>*a3xz=LM z??m20h)TEvRTry&r}7t^970*mJER3s6L+!qK7c!D&)OSLF!@@_7p;Lgc+u_{G%-tFZS4K#_gy34gHYW7|z ztEk+qQ>vFa*JAjhjhHhv@UA? zUMzbU)3^O5-;1*JX2=QB`5tTlu@Uao@(XUDR3csP(N+*!;$E(U&>Ex#>3$ElhS(za zdOd`(P|th3NyKKkAL=4H%xKd4K4=}Wh3=R7h^>@F`raq4B(~K3R41{uT9AJCQEQ1U zcE8n2=%fbRXH6zH+x=KK(c#9BLHA+ni7j}))=zB3Br@baZAGyq@8>!Str_|k8FnAH zrr4tQdp(6#g-uuw-RG?;w(NsYSFv^Tk&zET>xwP>pwyQy9s3`^X-7ssAPp@x_JdUC zzz3LKCSxCHywIb1yEFIyN#B}8A&f1YjEmP7pCDEKLJ?Wd1 zCP2X!jYXDK8CsQSS(dJhEi2Hv9=EJ3L+cVP%+goJ7N)hbnPjPDWu~l5v@}a+<}8ir zOx`1*^dL`K24~vfM5D9xX5Q$S-h|QrQ9IERpHZJr0ByYx8$&hdxb~TL$^B4N^2pOOOBF zD48CGapDV>Nd{$-qFGwH49+Z>F6D9LOO|y8ZJnZpTKWv$LbX=9fvmEu^p;quXsMP? zZ;hq;t@RrJz{^mw#87R&T%<8}&G3$v#eR9klVA3it>-;3=})>$Te zOHEibV@tQU){G5Jc^`S%GUZ!t%Az@2`n~n$%=GJ9LdZv6wM_UwF=5e+Egk_^elXlg@i@`ztaiJ1ybkd^Wf1w?^1OS> z^Ss{Y-qQCH`O<2?d#?SYHdJPludOz`C)-eJM>33@wA%5WZAYms6+8LHYRh}NExql@ z_9|L!d2fwUS=(veV5g1V{zg;nEYmW^L^{h%mTa~ZMF0L>(Q*8g%0`;%cbvY zmloaHYU}&ktyx>k9rk(4yYGAN7Cqc*@B81wH68c`%f%lE7Z=^!YV!xf%>z61OP04k zFy1bDyw&axj>l^{_`fWdf1q4mbbG7qA1t>I?C`Hz-v7XPzZe0m_J8mqfMx)2-3kE@ zWC#$$fMo*@W*E>82!@jzRy25Eqk$L^EIW8`BZ4+6Y*b)3CEV11ur>0a*WbN+C(^P7 z%MajdsGbMb;ITD$X6;YK{gp^7Kv+RSbv5HQaZ}+RIgg0(oTu7?8LGY z9XpY2Ws>5wY{jw_16z^pB}K_>*^6Z_8Q6<#GwqZtmd#i;W5Q-+yGc>9S$1RDjY+%F z+D;D3b}ZZZ2eu>I&rKz#Wj~hv{6qVZY$z;6$!*z?WkdhMhGaWBs^qoo$g-nNH$_GQ`EEw(SMjg_`+%(Ainz{X@do1~Pr?98&W|H#f{TT4;O zTefD|+J9(kvc0uaDq8kt+1r0?Z?es$D3vXnvuy4**qqkxs#Fu@xXEjzS=;++bLEMHAvJg?NX z0;3fe?_gkLM(GWXmMvPr@lFQEzyL`OD)p@ZX$8nT93Z_x()~iqQc6S1CM}!13vAMB zmu%tNvPrA+zSEtzH-Gqa0AKha4U|MHR9d0(E(w+1aOv&Fn^?AK+2&njn_l~5-MM9( zR(J00PVbhp(5*MMLZ=lv@3PS84WHiby}4zhmW|$pHtMxg*3DZsYIXB>OZToV2Xy!D zuYEO8lC4l`h0?n;lzPLdx7%-J*{Wr$cd@N{?Ui-^maSUdzqZ@G+pdLSKpQKxTA}qW z53Szt>KzWWwQSb1*?Yidy>`on1(wZP!-BhQ7@$`k&rN}tM+pf#pj0G;6eZb6F;arm zCn=->nNAv#S4bmriX055UpV(C z!!qq7!!sR)^Cx7avmzPgtPSUSWUO-q8RvWj&Kti zPM*!TgFKh-Jb6BUYqC85_vHBkv1CPohsX;BCc}9tSy}J`SylL9vbxADvZknutS$O8 zSy%KDoUf4AilvYZ#d^TGH+iFYb+V~=C-P?Ttt74ZJ~)3s-YT()Y%BR2*vbTH}@^<;4<$$A9pvNqdE{92%;b}VtmJr&ugE7gZRE3BG34`Ff0L87Zjdi(*CAil zo(AWa$yc?{k}vCIC12NRPrj-%jhv{n7k-~5C+ig@C+f8#r|L(Nll7~S)AgSs-_~CR z=e6Wa1C{*HAP&yi$WINHk+Ti2kzW!UlV1~8lHU?H!g&)p*CZP`pH!G!Na{>3Hf=~Q zHGP3xZu%;mHg6w;!QqO@qFgtQo}gtl0$gtgeBgeNOX zL~=7lP42DOl1C`f${l9ww5lV4McCGSwmCVvS3enhF3d{n92s)bUe)oG=2 z>nNp4>jO&FHr5L z6s1Oo$Ca8Lmcuz+soSxZQmw^JN>RS>fBFB?CMk+cYR%H(!H>f)cr}NY0pHZ zdCw6_i=IoAmOZyBt$LnPTK5W9+VrZTr1a{dwCy!gY1eDI(yiAbrBAOF%D`S5l%c(L zDkFM*sEq0Ll`^5%&&t$ZSCrYk?MmC;(aOT!4=IoKo($)u%Hlp%mB;&ht}N+0QCXUr zTX`aNm-1x)@yfCRvy`U>oK&73SX+5!;CsrmgNiE84VtGsKiH`(AN-KAV(`bx3qvX@ zFAjNJd1>f!W#!PXm6gL^QC2-PMOpdKI%U;}AC#3NZYXO;)>PJvYOJgsJz7~adbzT0 z%mHQXmUvT;Ib<@E^*ls6{)qHLNt zTG>4D6XnfGRh6_!Pb%q?E-70kw^H7k{Iarj@&;w=!!wm_(>f|!r_EHh&*-3Rn=wP# zF>|i6edZ=*>¥?pbY=J+r=4_Rj9DygmD8<()YrNzs_c2#Id1vua zRi6Z`GGGpM8emlbv#XZ@s|r|@dK$2Jz#?rG0jmaBj4d}{)d7pP^#UvbFsH2TMVA8eok8qmk19O9U);u>4Uh zT{FP)MV$bwIba2&-UqA&UItWJT?02=~W{Q`Rd8wyyxf+YYO23W&_aexg6tU;knfIS3Q zV!jbTA39mPJ+oHW{!sMIHfc3Sg~^{0-Q{fVD01BVbbj zODWnCuxWs`FIpY2>43E>mJ6^MfORYu4%ke?y#8RV)YC(|`@FxD2po0DGw7bikekYBLQ0p*tp8C1GWmV ziItxLY&BpLs)PWx2C&JMe*tVQV3Vr209yyx!&OEDwjQu4RkHy0GGNoH+yLwqz^29* z0qj-4X2fR#>@~oq$F~4%17Ne_;{n?U*v$BqfV~dbocM)+y#d(lcos`G0X8q5#gff{ z&8^1j_9kF1cvDe<=rq6{sa^)Kbifu=&kooYz~)z<57=9PJz9MXU|RuOSp5WG+W=cs z{e8f;1NK+~i$gmAdpv=~p`Cy&PS_6EF2I&1tOjg1U`uKi0&EXpPu7eEY%gF>)SM33 z+kib)b1-1<0Jf~=F~Hsh?3tQ70ow=I({-JIy$9HHb*=*TK48x_*aX-IfGuzE9ANta zd%ht{cL1;#8nAQ+0b9|qH((zE_EN*u0bAMVF~E)hwx-bp zz>Wg8y3tL*J_c-Eqn`jf2H4ufLx6n(*vpAq06PxY`oxQXeG1sCiKhVj46s)kHwNr; zz&13l0N59Rz1E}xU|$0EdXrp$eFfOYB&LI}0o#QJVChZY1ne|mX-%0gd<)oHO_?uz2iTTo%on}~Y+Ezt3uge^+B^ZU9{}6Yyf9!t z0=B&ci=F=iY*z~wJAVRfXEKWiKLfTWnZ<*%fbCBH1F&BJdpr3{zMP9|P~UuF#e-nE?B)du_m+fc?D2w=GY`@PR4z;Xk2zRx#+}o35T1*kZuA~kCtSDgDQ`-Pm46tjdtjxs$yOGMu zTmrDa`#nXXVoIuSE2Q5HQY5AnU^n|StTbRD{U?)BFgB^IC<9gjRu-_Z0rLPW2UzHU z8-SGuEMma7fK>o2d|-FLDgtI3SRb%TfT;t20IV`#j)4aNs{)vPP$FPe0gD<`60mr{ zA_uJltQuf3gBAc*9kA%Z!cr;+O0E-=b90$AR$-vE{bSe|iR0c#3a{&95yYX(@p@eaV616FX{Z-BJ`tibrb zfF%P~czhGUS^`#R{JVg)0<7rxb%3=7tjL7sfVBav_=NI+r2tlJ!mEI_1+3(RMS!&f zti;49z}f>=dcq%obpWi?#HE0B1gz}D@ql##tjxpjGH0N$mma3RuNS z34nD2tiq&pz`6rgdD1h0^#H8WjPN)l-hvx z1uS7oLBLW0t3EXjuzrBmeE2e8{Q;{nonZq2t38cj0|BcwGc#a=0INIW5@3S?t26Uw zz=i-;f96Mk4F#;;tb%|I1FYe!2*8E|)?n61z#alDaaMc4MgZ1m*2{p61gy!dM*$lJ zSmRk&0UHfi(^)408v|I`~oXf$v0-P&C){jHF5Mqy60_RA;9q<=93QE0{ zkkEppgpx=UrH%voX*fnZVjP(qPDf_=i}7Fu5v(YJl|-H43=F%V!Jr&bMFk$aE~&XLtGTYIxvr|YPS9M})?C-uTqkO-n+n%Z=BQ+` z%rSFGF|gu-j-rl|jLdqd==$n?l< zk-H+_j{Gh1LR8VHl2K)&Dn?a}N{Ff*RX-{*s%cbm%oDIWGF%}c8*NGI0L9jj9h$R4 zJ2|cko%hBvG zfgNVC!+dsF%!HO=hnnorogMnaKiF2WLpnQr3J3LL_y_ezcKDDT-ere*>@brZ`m;li zur~>LDeNUeR5y?683yHnPL(?C=IVY+{Ga z?C>T#q_IOfJ8WTxx7cATJ8WZz?d-6F9d@$AE_T?>4tv;PFFU-=4)3tTyX>%!9o}Py z_u1hCcG%Aj2iV~tJAB9vhuGmGb~wxqN7!LmSYASovR@yw!!dUFgdL8v!>8=<89RK= z4qvdtm+bHrJABO!C)nX6JDg&NZ`k29JABIy-?790*x`G2IKvJ1B})OP7@p*pcaa8DQcq*>Y^U%qX8P?GBiSCT#hTy1WnNl&2c4Kpe0(NHQJyp z+Mzu=gDF-I-5YwVWAvRInMVR3jCdrJco*+Eyi4F}T6adrArPIg3j6o*~l z5GrxZv5B}{IUQ4rKFPAl(s2vDP^w%btwn#Vc5JhQpU^6zM%)$_9BQ{_dhGJ`4 zjjdywEbCE}zT5SvTAsx>P zU@g{RJvLw?HeoZiU@LCLHf+ZZ?8GkY#vbg&KJ3Q<9K>xngi0L75gf(sIELeiSSuDM zs?Nwl|1cm6`xCk6aUL(?0$#-%cn9y{1ALSSmD0!f6rbU9e2K5|ExyN(_&E`dNx$NE z{E5HuUm~AF6;wkF6eq$-sU8}lF`A$`TA~fwqXeB3;V!8gdZHBlFc5<=1j8{J;}YQ> zX(Faz2Ffu9^RWm^upBEB;XY{%)?*X4Vmo$WFAm@kjwHgvlFubyxXVJ%g$@eWd(gro zcnnYAsYEy}J%h72hZpb?Ucu|Q2oubkV0cn8#=J4+O)zhQc@xZ=VBQ4tCYU$Dya@(( z8O|upGXD#H!yoty|0ZHUL{(HzglD0@pug}k(ofS_cnk01eSC<*C#kETtDvj!1-`;J z_zpkdC+H=tgNA~Jf`)P#@+iV3sEInLp9mWzPgAZLTA(dDpcA^FJ9?o{B5aZRV-U(P z6eBPSV=)1faa|&8lRQm1PgBm*l$(bISd0oR!wRfUgq@Nb%oW-#eDT7i3Jd!z97H9K z;&>wLk?z1L+>8715FW+j@I>T{HfK<=L2Q`CY2N$i;`tC?jAui<5MK`QHEB=Wo5kbt zL>9N(6&%4>Cr_3ZN)>TQ7R%$TES`#Klkh;=lEgFd=@6fDfz$R8BfX+WVKlDxDjzG2 z!8lB_Q1FlMtT( diff --git a/target/scala-2.12/classes/lsu/lsu_stbuf.class b/target/scala-2.12/classes/lsu/lsu_stbuf.class index ebe39301508e22e6c31dce14969dc86c93822d44..711e787c6a400d9cd0682997596158f78de652c2 100644 GIT binary patch delta 37 tcmX@|g8Rq|?hP4SjKY&Mx$+pfHs9cq5MwlK{;1IYQGs#$M+K(f%K#H44mJP) delta 37 tcmX@|g8Rq|?hP4SjK-5Qx$+pLHs9cq5MwlM{;1IYQGs#$M+K(f%K#Vg4rl-X