diff --git a/design/src/main/scala/ifu/ifu_mem_ctl.scala b/design/src/main/scala/ifu/ifu_mem_ctl.scala index 98bbd025..00d82472 100644 --- a/design/src/main/scala/ifu/ifu_mem_ctl.scala +++ b/design/src/main/scala/ifu/ifu_mem_ctl.scala @@ -113,8 +113,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C, Mux((ic_byp_hit_f & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C, Mux((bus_ifu_wr_en_ff & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C, - Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C, - Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C)))))))) + Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C, + Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C)))))))) miss_state_en := io.dec_mem_ctrl.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff) } is (crit_wrd_rdy_C){ // Critical word hit but not complete, its going to be available in next cycle @@ -159,7 +159,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { miss_pending := miss_state =/= idle_C val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f) val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) & - !((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f | + !((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f | (miss_pending & (miss_nxtstate === crit_wrd_rdy_C)) val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f @@ -200,12 +200,12 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff, - Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new, - Mux(miss_pending.asBool, way_status_mb_ff, way_status))) + Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new, + Mux(miss_pending.asBool, way_status_mb_ff, way_status))) val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any.reverse.reduce(Cat(_,_))), - Mux(miss_pending.asBool, tagv_mb_ff, io.ic.tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags))) + Mux(miss_pending.asBool, tagv_mb_ff, io.ic.tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags))) val scnd_miss_req_q = WireInit(Bool(), false.B) val reset_ic_ff = WireInit(Bool(), false.B) val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff) @@ -237,7 +237,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val reset_tag_valid_for_miss = WireInit(Bool(), false.B) val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)), - !sel_mb_addr -> io.ifc_fetch_addr_bf)) + !sel_mb_addr -> io.ifc_fetch_addr_bf)) val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B) val sel_mb_status_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q) | reset_tag_valid_for_miss val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f) @@ -286,9 +286,9 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val final_data_out1 = VecInit(io.ic.rd_data, ic_byp_data_only_new, io.ic.rd_data, ic_byp_data_only_new) val final_data_out2 = VecInit(1.U, io.iccm.rd_data, 1.U, 1.U) val ic_final_data = if(ICCM_ICACHE) Fill(64, sel_byp_data | sel_iccm_data | sel_ic_data) & io.ic.rd_data else - if (ICCM_ONLY) (Fill(64, sel_byp_data) & ic_byp_data_only_new) | (Fill(64, sel_iccm_data) & io.iccm.rd_data) else + if (ICCM_ONLY) (Fill(64, sel_byp_data) & ic_byp_data_only_new) | (Fill(64, sel_iccm_data) & io.iccm.rd_data) else if (ICACHE_ONLY) Fill(64, sel_byp_data | sel_ic_data) & io.ic.rd_data else - if (NO_ICCM_NO_ICACHE) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U + if (NO_ICCM_NO_ICACHE) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U val ic_premux_data_temp = if(ICCM_ICACHE) (Fill(64,sel_iccm_data) & io.iccm.rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new) else if(ICACHE_ONLY) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U val ic_sel_premux_data_temp = if(ICCM_ICACHE) sel_iccm_data | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U @@ -313,8 +313,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val ic_miss_buff_data = Wire(Vec(2*ICACHE_NUM_BEATS, UInt(32.W))) for(i<- 0 until ICACHE_NUM_BEATS){ val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode)) - ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)} - ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}} + ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)} + ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}} val ic_miss_buff_data_valid = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U) val ic_miss_buff_data_valid_in = (0 until ICACHE_NUM_BEATS).map(i=>write_fill_data(i)|(ic_miss_buff_data_valid(i)&(!ic_act_miss_f))) ic_miss_buff_data_valid := withClock(io.free_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)} @@ -329,16 +329,16 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val bypass_index_5_3_inc = bypass_index(bypass_index.getWidth-1,2) + 1.U val bypass_valid_value_check = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(bypass_index.getWidth-1,2)===i.U).asBool->ic_miss_buff_data_valid_in(i))) val bypass_data_ready_in = (bypass_valid_value_check & !bypass_index(1) & !bypass_index(0)) | - (bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) | - (bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) | - (bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) | - (bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U)) + (bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) | + (bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) | + (bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) | + (bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U)) val ic_crit_wd_rdy_new_ff = WireInit(Bool(), 0.U) val ic_crit_wd_rdy_new_in = (bypass_data_ready_in & crit_wd_byp_ok_ff & uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) | - ( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) | - (ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final) + ( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) | + (ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final) ic_crit_wd_rdy_new_ff := withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)} val byp_fetch_index = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,0) val byp_fetch_index_0 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 0.U) @@ -348,12 +348,12 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val byp_fetch_index_inc_1 = Cat(byp_fetch_index_inc, 1.U) val ic_miss_buff_data_error_bypass = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_error(i))) val ic_miss_buff_data_error_bypass_inc = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_error(i))) - ifu_byp_data_err_new := (!ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) | - (!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) | - (!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) | - ( ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) | - (ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & (ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)) | - ic_miss_buff_data_error(byp_fetch_index_inc(ICACHE_BEAT_ADDR_HI-3,0)))) + ifu_byp_data_err_new := (!ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) | + (!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) | + (!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) | + ( ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) | + (ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & (ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)) | + ic_miss_buff_data_error(byp_fetch_index_inc(ICACHE_BEAT_ADDR_HI-3,0)))) val ic_byp_data_only_pre_new = Mux(!ifu_fetch_addr_int_f(1).asBool, Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_0===i.U).asBool->ic_miss_buff_data(i)(31,0)))), Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_1===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))))) @@ -458,8 +458,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { } err_stop_state := withClock(io.free_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)} bus_ifu_bus_clk_en := io.ifu_bus_clk_en - val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode) - val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_mem_ctrl.dec_tlu_force_halt , io.scan_mode) + val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode) + val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_mem_ctrl.dec_tlu_force_halt , io.scan_mode) val bus_ifu_bus_clk_en_ff = withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)} scnd_miss_req_q := withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)} val scnd_miss_req_ff2 = withClock(io.free_clk){RegNext(scnd_miss_req, 0.U)} @@ -535,8 +535,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { last_data_recieved_ff := withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)} // Request Address Count val bus_new_rd_addr_count = Mux(!miss_pending, imb_ff(ICACHE_BEAT_ADDR_HI-1, 2), - Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2), - Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count))) + Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2), + Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count))) bus_rd_addr_count := withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)} // Command beat Count val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt @@ -630,115 +630,110 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { ((miss_state===miss_wait_C) & !miss_state_en) | ((miss_state===crit_wrd_rdy_C) & !miss_state_en) | ((miss_state===crit_byp_ok_C) & miss_state_en & (miss_nxtstate===miss_wait_C)) )) | - (io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf) + (io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf) val bus_ic_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) io.ic.wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes) io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff))) reset_all_tags := withClock(io.active_clk){RegNext(io.dec_mem_ctrl.dec_tlu_fence_i_wb, false.B)} - // I$ status and P-LRU - val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss - val ifu_status_wr_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), - ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) - val ifu_status_wr_addr_ff = withClock(io.free_clk) { - RegNext(ifu_status_wr_addr_w_debug, 0.U) - } - val way_status_wr_en = WireInit(Bool(), false.B) - val way_status_wr_en_w_debug = way_status_wr_en | (io.ic.debug_wr_en & io.ic.debug_tag_array) - val way_status_wr_en_ff = withClock(io.free_clk) { - RegNext(way_status_wr_en_w_debug, false.B) - } - val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) - val way_status_new_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array, - if (ICACHE_STATUS_BITS == 1) io.ic.debug_wr_data(4) else io.ic.debug_wr_data(6, 4), way_status_new) - val way_status_new_ff = withClock(io.free_clk) { - RegNext(way_status_new_w_debug, 0.U) - } - val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U) - val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode)) - val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W))) - for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8) - way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)} + // I$ status and P-LRU + val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss + val ifu_status_wr_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), + ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) + val ifu_status_wr_addr_ff = withClock(io.free_clk) { + RegNext(ifu_status_wr_addr_w_debug, 0.U) + } + val way_status_wr_en = WireInit(Bool(), false.B) + val way_status_wr_en_w_debug = way_status_wr_en | (io.ic.debug_wr_en & io.ic.debug_tag_array) + val way_status_wr_en_ff = withClock(io.free_clk) { + RegNext(way_status_wr_en_w_debug, false.B) + } + val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) + val way_status_new_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array, + if (ICACHE_STATUS_BITS == 1) io.ic.debug_wr_data(4) else io.ic.debug_wr_data(6, 4), way_status_new) + val way_status_new_ff = withClock(io.free_clk) { + RegNext(way_status_new_w_debug, 0.U) + } + val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U) + val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode)) + val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W))) + for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8) + way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)} val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_)) - // io.test_way_status_out := test_way_status_out + // io.test_way_status_out := test_way_status_out val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_)) //io.test_way_status_clken := test_way_status_clken way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i))) - val ifu_ic_rw_int_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, - io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) - ifu_ic_rw_int_addr_ff := withClock(io.free_clk) { - RegNext(ifu_ic_rw_int_addr_w_debug, 0.U) - } - val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) - val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) - val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en - val ifu_tag_wren_ff = withClock(io.free_clk) { - RegNext(ifu_tag_wren_w_debug, 0.U) - } - val ic_valid_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array, io.ic.debug_wr_data(0), ic_valid) - val ic_valid_ff = withClock(io.free_clk) { - RegNext(ic_valid_w_debug, false.B) - } - val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j => - if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags - else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) | - ((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) | - reset_all_tags).reverse.reduce(Cat(_, _))) - val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode))) - val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool()))) - // io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)), - // (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_))) + val ifu_ic_rw_int_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, + io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) + ifu_ic_rw_int_addr_ff := withClock(io.free_clk) { + RegNext(ifu_ic_rw_int_addr_w_debug, 0.U) + } + val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en + val ifu_tag_wren_ff = withClock(io.free_clk) { + RegNext(ifu_tag_wren_w_debug, 0.U) + } + val ic_valid_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array, io.ic.debug_wr_data(0), ic_valid) + val ic_valid_ff = withClock(io.free_clk) { + RegNext(ic_valid_w_debug, false.B) + } + val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j => + if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags + else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) | + ((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) | + reset_all_tags).reverse.reduce(Cat(_, _))) + val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode))) + val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool()))) + // io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)), + // (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_))) - for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32) - ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B, - ((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)} + for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32) + ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B, + ((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)} - val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j => - Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_)) + val ic_tag_valid_unq = if(ICACHE_ENABLE)(0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j => + Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_)) + else 0.U(ICACHE_NUM_WAYS.W) + // Making sudo LRU + val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) + if (ICACHE_NUM_WAYS == 4) { + replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | + (!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) + replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | + (!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) + replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | + (!tagv_mb_ff(1) & tagv_mb_ff(0)) + replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0) - // Making sudo LRU - val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) - if (ICACHE_NUM_WAYS == 4) { - replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | - (!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) - replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | - (!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) - replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | - (!tagv_mb_ff(1) & tagv_mb_ff(0)) - replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0) + way_status_hit_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status(2), 3.U), + io.ic.rd_hit(1) -> Cat(way_status(2), 1.U(2.W)), + io.ic.rd_hit(2) -> Cat(1.U, way_status(1), 0.U), + io.ic.rd_hit(3) -> Cat(0.U, way_status(1), 0.U))) - way_status_hit_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status(2), 3.U), - io.ic.rd_hit(1) -> Cat(way_status(2), 1.U(2.W)), - io.ic.rd_hit(2) -> Cat(1.U, way_status(1), 0.U), - io.ic.rd_hit(3) -> Cat(0.U, way_status(1), 0.U))) - - way_status_rep_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U), - io.ic.rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)), - io.ic.rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U), - io.ic.rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U))) - } - else { - replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0) - replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0) - way_status_hit_new := io.ic.rd_hit(0) - way_status_rep_new := replace_way_mb_any(0) - } - way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new) - way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f - val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending) - - val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat) - val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss) - ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _)) + way_status_rep_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U), + io.ic.rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)), + io.ic.rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U), + io.ic.rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U))) + } + else { + replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0) + replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0) + way_status_hit_new := io.ic.rd_hit(0) + way_status_rep_new := replace_way_mb_any(0) + } + way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new) + way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f + val bus_wren = if(ICACHE_ENABLE)(0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending) + else (0 until ICACHE_NUM_WAYS).map(i => 0.U) + val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat) + val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss) + ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _)) bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_)) if(!ICACHE_ENABLE){ - for(i<- 0 until ICACHE_NUM_WAYS){ - - bus_wren(i) := 0.U - } - ic_tag_valid_unq := 0.U way_status := 0.U - replace_way_mb_any := 0.U + replace_way_mb_any := (0 until ICACHE_NUM_WAYS).map(i =>0.U) way_status_hit_new := 0.U way_status_rep_new := 0.U way_status_new := 0.U @@ -770,16 +765,17 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegNext(ic_debug_rd_en_ff, 0.U)} // Memory protection each access enable with its Mask val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) | - (INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) | - (INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) | - (INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U))) | - (INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U))) | - (INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U))) | - (INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) | - (INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) | - (INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U))) + (INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) | + (INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) | + (INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U))) | + (INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U))) | + (INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U))) | + (INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) | + (INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) | + (INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U))) val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)} -} \ No newline at end of file +} + diff --git a/design/target/scala-2.12/classes/ifu/ifu_mem_ctl.class b/design/target/scala-2.12/classes/ifu/ifu_mem_ctl.class index 69675195..347cf37d 100644 Binary files a/design/target/scala-2.12/classes/ifu/ifu_mem_ctl.class and b/design/target/scala-2.12/classes/ifu/ifu_mem_ctl.class differ diff --git a/design/target/scala-2.12/quasar_2.12-3.3.0.jar b/design/target/scala-2.12/quasar_2.12-3.3.0.jar index 5290f90d..9feb5aed 100644 Binary files a/design/target/scala-2.12/quasar_2.12-3.3.0.jar and b/design/target/scala-2.12/quasar_2.12-3.3.0.jar differ diff --git a/design/target/streams/compile/_global/_global/compileSourceFileInputs/previous b/design/target/streams/compile/_global/_global/compileSourceFileInputs/previous index 259b554e..153b65f2 100644 --- a/design/target/streams/compile/_global/_global/compileSourceFileInputs/previous +++ b/design/target/streams/compile/_global/_global/compileSourceFileInputs/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/mem.scala","e9418660ac1519eea2058bbd87d585d5d47343f0"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar.scala","a6e350adebfb964e096f83b6f340cd22ecc2218d"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dma_ctrl.scala","2594f33928c43ca21ecae10a21afad6532b8b538"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar_wrapper.scala","d622bea24629292ee875d0cdff1791fc918192c2"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/pic_ctrl.scala","2c0bf6d2f4c554108b67ebc3e19c57369eb40e17"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_ifc_ctl.scala","58feaf508d092ed1910a9d0dfcf34bdd11f3049b"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_aln_ctl.scala","c37fe97894075254205a512d25d660b5f15788c0"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_bp_ctl.scala","474eec82140152f20417b6c1e4404d409f7f4a9b"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala","9f207697371dc1f28e50e429fe84ae24b9de4fc3"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_compress_ctl.scala","3e2056149b7e8a89ba0809ff0082c71e3601820a"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu.scala","bd1d2820b1ce1701dffc6deea3a4718a54cdccd7"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_intf.scala","7774491efcdfee647906ae17875a8ca9a4e637f1"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_trigger.scala","e7f2ac077dddb18205983382b69216c94df83e9f"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu.scala","e58a2fe2fee2677843009cccb6161c940037f996"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_ecc.scala","b711e9f06be192b7ec6b1b2288692a94cdd80466"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_stbuf.scala","06b7b5e9d73d155d45733fecf2a25e1491c42ef8"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_dccm_ctl.scala","5168463f9c0e776c36750656998fc360fd269ab2"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_lsc_ctl.scala","191bf9cc863939ecf0cab24cdceca1b9b64223d4"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_buffer.scala","39c80c21490c75b51eb65d08abc5a5d65729021f"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_addrcheck.scala","3c84af93ccb882d99b74852439d20c3b189dd518"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_clkdomain.scala","d7ca34e7d329d7eef0e2506c7a07d6911f2226bf"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu.scala","e1fc1e1167146d3e1fe7798fb3598384848ea521"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_mul_ctl.scala","fd528764c26575f995645a109d8b55799591874c"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_div_ctl.scala","dc91c0c780fed1ff374122dea516b6252fca923f"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_alu_ctl.scala","369f3ac01e07eb8a2ec97049e878647a148eefef"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dbg/dbg.scala","000ac44e7f30f2beb5febc19c7916edd24afffc5"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/param.scala","b9357c4b290ddf5f9ad4f6948e2ae098feaf53a7"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/axi4_to_ahb.scala","a0f8764410367a2ea344a3e90ed394351e14ab00"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/lib.scala","cba1371cade8c2d7e697a800be2387a7e5519d54"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/ahb_to_axi4.scala","c19d86c71a650a13cd42769f6ada9cd370ffdb7e"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dmi/dmi_wrapper.scala","619171c0b49373f3aaf18f92aa659d8c05acbdfa"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/include/bundle.scala","3e759c46cae7c883f50d10a62c53eb3c5864cfbb"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_trigger.scala","cb83a19d8b65a41e5dc8a61e2b4198c362c2d912"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_decode_ctl.scala","cb54784303a8451eea6df9648ea012ad0f2b317e"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec.scala","b84f82ee6dd9d53f53025e38f2f447da16e91caa"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_ib_ctl.scala","76e2bf13097343ace8beed76c0d1bf730db133ed"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_dec_ctl.scala","e1f606df5c404d0d829d3a680836da2d31e9197e"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_tlu_ctl.scala","339c13fe7403c4900a13674ef96642d373f0a2c7"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_gpr_ctl.scala","ef85566d41d8ca0d3781ab005c86097221e11c28"]],"lastModifiedTimes":[]}}] \ No newline at end of file +["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/mem.scala","e9418660ac1519eea2058bbd87d585d5d47343f0"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar.scala","a6e350adebfb964e096f83b6f340cd22ecc2218d"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dma_ctrl.scala","2594f33928c43ca21ecae10a21afad6532b8b538"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar_wrapper.scala","d622bea24629292ee875d0cdff1791fc918192c2"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/pic_ctrl.scala","2c0bf6d2f4c554108b67ebc3e19c57369eb40e17"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_ifc_ctl.scala","58feaf508d092ed1910a9d0dfcf34bdd11f3049b"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_aln_ctl.scala","c37fe97894075254205a512d25d660b5f15788c0"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_bp_ctl.scala","474eec82140152f20417b6c1e4404d409f7f4a9b"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala","50dba4385c5cbbed2cdf7fef4f7bbeccf6c76d2e"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_compress_ctl.scala","3e2056149b7e8a89ba0809ff0082c71e3601820a"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu.scala","bd1d2820b1ce1701dffc6deea3a4718a54cdccd7"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_intf.scala","7774491efcdfee647906ae17875a8ca9a4e637f1"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_trigger.scala","e7f2ac077dddb18205983382b69216c94df83e9f"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu.scala","e58a2fe2fee2677843009cccb6161c940037f996"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_ecc.scala","b711e9f06be192b7ec6b1b2288692a94cdd80466"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_stbuf.scala","06b7b5e9d73d155d45733fecf2a25e1491c42ef8"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_dccm_ctl.scala","5168463f9c0e776c36750656998fc360fd269ab2"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_lsc_ctl.scala","191bf9cc863939ecf0cab24cdceca1b9b64223d4"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_buffer.scala","39c80c21490c75b51eb65d08abc5a5d65729021f"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_addrcheck.scala","3c84af93ccb882d99b74852439d20c3b189dd518"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_clkdomain.scala","d7ca34e7d329d7eef0e2506c7a07d6911f2226bf"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu.scala","e1fc1e1167146d3e1fe7798fb3598384848ea521"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_mul_ctl.scala","fd528764c26575f995645a109d8b55799591874c"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_div_ctl.scala","dc91c0c780fed1ff374122dea516b6252fca923f"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_alu_ctl.scala","369f3ac01e07eb8a2ec97049e878647a148eefef"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dbg/dbg.scala","000ac44e7f30f2beb5febc19c7916edd24afffc5"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/param.scala","b9357c4b290ddf5f9ad4f6948e2ae098feaf53a7"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/axi4_to_ahb.scala","a0f8764410367a2ea344a3e90ed394351e14ab00"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/lib.scala","cba1371cade8c2d7e697a800be2387a7e5519d54"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/ahb_to_axi4.scala","c19d86c71a650a13cd42769f6ada9cd370ffdb7e"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dmi/dmi_wrapper.scala","619171c0b49373f3aaf18f92aa659d8c05acbdfa"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/include/bundle.scala","3e759c46cae7c883f50d10a62c53eb3c5864cfbb"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_trigger.scala","cb83a19d8b65a41e5dc8a61e2b4198c362c2d912"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_decode_ctl.scala","cb54784303a8451eea6df9648ea012ad0f2b317e"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec.scala","b84f82ee6dd9d53f53025e38f2f447da16e91caa"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_ib_ctl.scala","76e2bf13097343ace8beed76c0d1bf730db133ed"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_dec_ctl.scala","e1f606df5c404d0d829d3a680836da2d31e9197e"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_tlu_ctl.scala","339c13fe7403c4900a13674ef96642d373f0a2c7"],["/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_gpr_ctl.scala","ef85566d41d8ca0d3781ab005c86097221e11c28"]],"lastModifiedTimes":[]}}] \ No newline at end of file diff --git a/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip b/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip index f6a79a39..51a5a5fc 100644 Binary files a/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip and b/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip differ diff --git a/design/target/streams/compile/compileIncremental/_global/streams/export b/design/target/streams/compile/compileIncremental/_global/streams/export index fa24aad1..95c087c4 100644 --- a/design/target/streams/compile/compileIncremental/_global/streams/export +++ b/design/target/streams/compile/compileIncremental/_global/streams/export @@ -1 +1 @@ -scalac -bootclasspath /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/mem.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dma_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/pic_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_ifc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_aln_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_bp_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_compress_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_intf.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_trigger.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_ecc.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_stbuf.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_dccm_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_lsc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_buffer.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_addrcheck.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_clkdomain.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_mul_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_div_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_alu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dbg/dbg.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/param.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/axi4_to_ahb.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/lib.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/ahb_to_axi4.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dmi/dmi_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/include/bundle.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_trigger.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_decode_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_ib_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_dec_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_tlu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_gpr_ctl.scala +scalac -bootclasspath /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala diff --git a/design/target/streams/compile/compileIncremental/_global/streams/out b/design/target/streams/compile/compileIncremental/_global/streams/out index 7ef19cc0..2803a200 100644 --- a/design/target/streams/compile/compileIncremental/_global/streams/out +++ b/design/target/streams/compile/compileIncremental/_global/streams/out @@ -1 +1,36 @@ -[debug] No changes +[debug]  +[debug] Initial source changes:  +[debug]  removed:Set() +[debug]  added: Set() +[debug]  modified: Set(/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala) +[debug] Invalidated products: Set() +[debug] External API changes: API Changes: Set() +[debug] Modified binary dependencies: Set() +[debug] Initial directly invalidated classes: Set(ifu.ifu_mem_ctl, ifu.mem_ctl_io) +[debug]  +[debug] Sources indirectly invalidated by: +[debug]  product: Set() +[debug]  binary dep: Set() +[debug]  external source: Set() +[debug] All initially invalidated classes: Set(ifu.ifu_mem_ctl, ifu.mem_ctl_io) +[debug] All initially invalidated sources:Set(/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala) +[debug] Initial set of included nodes: ifu.ifu_mem_ctl, ifu.mem_ctl_io +[info] Compiling 1 Scala source to /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes ... +[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 +[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 +[debug] [zinc] Running cached compiler 284ab752 for Scala compiler version 2.12.10 +[debug] [zinc] The Scala compiler is invoked with: +[debug]  -Xsource:2.11 +[debug]  -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar +[debug]  -bootclasspath +[debug]  /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar +[debug]  -classpath +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar +[debug] Scala compilation took 17.036715456 s +[debug] Done compiling. +[debug] New invalidations: +[debug]  Set() +[debug] Initial set of included nodes:  +[debug] Previously invalidated, but (transitively) depend on new invalidations: +[debug]  Set() +[debug] No classes were invalidated. diff --git a/design/target/streams/compile/copyResources/_global/streams/copy-resources b/design/target/streams/compile/copyResources/_global/streams/copy-resources index 1439309b..a4a6a198 100644 --- a/design/target/streams/compile/copyResources/_global/streams/copy-resources +++ b/design/target/streams/compile/copyResources/_global/streams/copy-resources @@ -1 +1 @@ -[[{"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/rvjtag_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/gated_latch.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_mod.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_mod.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/beh_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_lib.sv"]},{"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/rvjtag_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/gated_latch.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/beh_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_mod.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_mod.sv"]}],{"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv","lastModified":1609765194000},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv","lastModified":1609765194000},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv","lastModified":1609765194000},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv","lastModified":1609765194000},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv","lastModified":1609765194000},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv","lastModified":1609765194000},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv","lastModified":1609765194000},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv","lastModified":1609765194000},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_mod.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_mod.sv","lastModified":1609765194000},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv","lastModified":1609765194000},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv","lastModified":1609765194000}}] \ No newline at end of file +[[{"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/rvjtag_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/gated_latch.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_mod.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_mod.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/beh_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_lib.sv"]},{"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/rvjtag_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/gated_latch.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/beh_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_mod.sv":["file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_mod.sv"]}],{"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv","lastModified":1609919539535},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv","lastModified":1609919539599},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv","lastModified":1609919539599},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv","lastModified":1609919539599},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv","lastModified":1609919539531},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv","lastModified":1609919539535},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv","lastModified":1609919539531},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv","lastModified":1609919539531},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_mod.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_mod.sv","lastModified":1609919539599},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv","lastModified":1609919539531},"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv","lastModified":1609919539599}}] \ No newline at end of file diff --git a/design/target/streams/compile/packageBin/_global/streams/inputs b/design/target/streams/compile/packageBin/_global/streams/inputs index eb22e84e..6ef253e5 100644 --- a/design/target/streams/compile/packageBin/_global/streams/inputs +++ b/design/target/streams/compile/packageBin/_global/streams/inputs @@ -1 +1 @@ --157721800 \ No newline at end of file +447944643 \ No newline at end of file diff --git a/design/target/streams/compile/packageBin/_global/streams/out b/design/target/streams/compile/packageBin/_global/streams/out index d13369b7..cac1ad1f 100644 --- a/design/target/streams/compile/packageBin/_global/streams/out +++ b/design/target/streams/compile/packageBin/_global/streams/out @@ -1 +1,423 @@ -[debug] Jar uptodate: /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/quasar_2.12-3.3.0.jar +[debug] Packaging /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/quasar_2.12-3.3.0.jar ... +[debug] Input file mappings: +[debug]  pic_ctrl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/pic_ctrl$$anon$1.class +[debug]  ifu +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu +[debug]  ifu/ifu_aln_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class +[debug]  ifu/ifu_aln_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_aln_ctl.class +[debug]  ifu/ifu_compress_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_compress_ctl$$anon$1.class +[debug]  ifu/ifu_ifc_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_ifc_ctl$$anon$1.class +[debug]  ifu/mem_ctl_io.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/mem_ctl_io.class +[debug]  ifu/ifu_mem_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_mem_ctl.class +[debug]  ifu/ifu$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu$$anon$1.class +[debug]  ifu/ifu_ifc_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_ifc_ctl.class +[debug]  ifu/ifu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu.class +[debug]  ifu/ifu_bp_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_bp_ctl$$anon$1.class +[debug]  ifu/ifu_compress_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_compress_ctl.class +[debug]  ifu/ifu_bp_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_bp_ctl.class +[debug]  quasar_wrapper.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/quasar_wrapper.class +[debug]  quasar_bundle$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/quasar_bundle$$anon$1.class +[debug]  vsrc +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc +[debug]  vsrc/ifu_iccm_mem.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv +[debug]  vsrc/dmi_wrapper.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv +[debug]  vsrc/dmi_jtag_to_core_sync.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv +[debug]  vsrc/beh_lib.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/beh_lib.sv +[debug]  vsrc/lsu_dccm_mem.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv +[debug]  vsrc/gated_latch.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/gated_latch.sv +[debug]  vsrc/rvjtag_tap.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/rvjtag_tap.sv +[debug]  vsrc/mem.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem.sv +[debug]  vsrc/mem_lib.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_lib.sv +[debug]  vsrc/mem_mod.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_mod.sv +[debug]  vsrc/ifu_ic_mem.sv +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv +[debug]  lsu +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu +[debug]  lsu/lsu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu.class +[debug]  lsu/lsu_dccm_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class +[debug]  lsu/lsu_trigger.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_trigger.class +[debug]  lsu/lsu_lsc_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class +[debug]  lsu/lsu_ecc.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_ecc.class +[debug]  lsu/lsu_bus_buffer.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_bus_buffer.class +[debug]  lsu/lsu_stbuf$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class +[debug]  lsu/lsu_clkdomain$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class +[debug]  lsu/lsu_lsc_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class +[debug]  lsu/lsu_bus_buffer$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class +[debug]  lsu/lsu_clkdomain.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_clkdomain.class +[debug]  lsu/lsu_stbuf.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_stbuf.class +[debug]  lsu/lsu_ecc$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class +[debug]  lsu/lsu_trigger$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_trigger$$anon$1.class +[debug]  lsu/lsu_addrcheck.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_addrcheck.class +[debug]  lsu/lsu_dccm_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class +[debug]  lsu/lsu_addrcheck$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class +[debug]  lsu/lsu_bus_intf$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class +[debug]  lsu/lsu_bus_intf.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_bus_intf.class +[debug]  lsu/lsu$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu$$anon$1.class +[debug]  pic_ctrl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/pic_ctrl.class +[debug]  wrapper$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/wrapper$.class +[debug]  quasar.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/quasar.class +[debug]  .vscode +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/.vscode +[debug]  .vscode/settings.json +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/.vscode/settings.json +[debug]  wrapper$delayedInit$body.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/wrapper$delayedInit$body.class +[debug]  wrapper.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/wrapper.class +[debug]  exu +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu +[debug]  exu/exu$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu$$anon$1.class +[debug]  exu/exu_div_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu_div_ctl$$anon$1.class +[debug]  exu/exu_alu_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu_alu_ctl$$anon$1.class +[debug]  exu/exu_alu_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu_alu_ctl.class +[debug]  exu/exu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu.class +[debug]  exu/exu_mul_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu_mul_ctl.class +[debug]  exu/exu_mul_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu_mul_ctl$$anon$1.class +[debug]  exu/exu_div_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu_div_ctl.class +[debug]  dbg +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg +[debug]  dbg/state_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/state_t.class +[debug]  dbg/sb_state_t$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/sb_state_t$.class +[debug]  dbg/sb_state_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/sb_state_t.class +[debug]  dbg/dbg$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/dbg$$anon$1.class +[debug]  dbg/dbg_dma.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/dbg_dma.class +[debug]  dbg/dbg.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/dbg.class +[debug]  dbg/state_t$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/state_t$.class +[debug]  lib +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib +[debug]  lib/lib$rvdffe$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvdffe$.class +[debug]  lib/lib$rvclkhdr.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvclkhdr.class +[debug]  lib/lib$rvecc_encode.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvecc_encode.class +[debug]  lib/lib$gated_latch$$anon$4.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class +[debug]  lib/axi4_to_ahb_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class +[debug]  lib/lib.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib.class +[debug]  lib/axi4_to_ahb$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/axi4_to_ahb$.class +[debug]  lib/lib$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$$anon$1.class +[debug]  lib/lib$rvecc_encode_64.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class +[debug]  lib/ahb_to_axi4.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/ahb_to_axi4.class +[debug]  lib/lib$rvecc_encode_64$$anon$3.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class +[debug]  lib/ahb_to_axi4$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class +[debug]  lib/lib$rvsyncss$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvsyncss$.class +[debug]  lib/lib$gated_latch.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$gated_latch.class +[debug]  lib/ahb_to_axi4$$anon$1$$anon$2.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1$$anon$2.class +[debug]  lib/lib$rvclkhdr$$anon$5.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class +[debug]  lib/lib$rvecc_encode$$anon$2.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class +[debug]  lib/axi4_to_ahb.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/axi4_to_ahb.class +[debug]  lib/param.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/param.class +[debug]  lib/lib$rvclkhdr$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvclkhdr$.class +[debug]  quasar_wrapper$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/quasar_wrapper$$anon$1.class +[debug]  dmi +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dmi +[debug]  dmi/dmi_wrapper_module.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dmi/dmi_wrapper_module.class +[debug]  dmi/dmi_wrapper_module$$anon$2.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dmi/dmi_wrapper_module$$anon$2.class +[debug]  dmi/dmi_wrapper.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dmi/dmi_wrapper.class +[debug]  dmi/dmi_wrapper$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dmi/dmi_wrapper$$anon$1.class +[debug]  dma_ctrl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dma_ctrl.class +[debug]  mem +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/mem +[debug]  mem/Mem_bundle.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/mem/Mem_bundle.class +[debug]  mem/blackbox_mem.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/mem/blackbox_mem.class +[debug]  mem/quasar.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/mem/quasar.class +[debug]  mem/mem_lsu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/mem/mem_lsu.class +[debug]  mem/quasar$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/mem/quasar$.class +[debug]  mem/quasar$mem.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/mem/quasar$mem.class +[debug]  quasar_bundle.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/quasar_bundle.class +[debug]  dma_ctrl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dma_ctrl$$anon$1.class +[debug]  include +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include +[debug]  include/dctl_dma.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dctl_dma.class +[debug]  include/exu_ifu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/exu_ifu.class +[debug]  include/trace_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/trace_pkt_t.class +[debug]  include/lsu_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_pkt_t.class +[debug]  include/div_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/div_pkt_t.class +[debug]  include/write_resp.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/write_resp.class +[debug]  include/lsu_error_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_error_pkt_t.class +[debug]  include/read_addr.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/read_addr.class +[debug]  include/ahb_out_dma.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ahb_out_dma.class +[debug]  include/dest_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dest_pkt_t.class +[debug]  include/dbg_ib.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dbg_ib.class +[debug]  include/reg_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/reg_pkt_t.class +[debug]  include/tlu_exu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/tlu_exu.class +[debug]  include/inst_pkt_t$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/inst_pkt_t$.class +[debug]  include/tlu_dma.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/tlu_dma.class +[debug]  include/write_addr$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/write_addr$.class +[debug]  include/axi_channels.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/axi_channels.class +[debug]  include/ahb_out.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ahb_out.class +[debug]  include/ic_mem.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ic_mem.class +[debug]  include/write_addr.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/write_addr.class +[debug]  include/iccm_mem.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/iccm_mem.class +[debug]  include/aln_dec.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/aln_dec.class +[debug]  include/tlu_busbuff.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/tlu_busbuff.class +[debug]  include/trap_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/trap_pkt_t.class +[debug]  include/dma_lsc_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dma_lsc_ctl.class +[debug]  include/mul_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/mul_pkt_t.class +[debug]  include/ib_exu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ib_exu.class +[debug]  include/ccm_ext_in_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class +[debug]  include/dbg_dctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dbg_dctl.class +[debug]  include/dec_div.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_div.class +[debug]  include/dec_exu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_exu.class +[debug]  include/decode_exu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/decode_exu.class +[debug]  include/dec_dma.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_dma.class +[debug]  include/ic_data_ext_in_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class +[debug]  include/dec_ifc.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_ifc.class +[debug]  include/ifu_dec.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ifu_dec.class +[debug]  include/ahb_channel.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ahb_channel.class +[debug]  include/lsu_pic.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_pic.class +[debug]  include/dctl_busbuff.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dctl_busbuff.class +[debug]  include/dec_aln.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_aln.class +[debug]  include/dma_ifc.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dma_ifc.class +[debug]  include/dccm_ext_in_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class +[debug]  include/ifu_dma.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ifu_dma.class +[debug]  include/br_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/br_pkt_t.class +[debug]  include/lsu_tlu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_tlu.class +[debug]  include/dec_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_pkt_t.class +[debug]  include/aln_ib.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/aln_ib.class +[debug]  include/read_data$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/read_data$.class +[debug]  include/cache_debug_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/cache_debug_pkt_t.class +[debug]  include/load_cam_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/load_cam_pkt_t.class +[debug]  include/dec_mem_ctrl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_mem_ctrl.class +[debug]  include/ahb_in.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ahb_in.class +[debug]  include/axi_channels$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/axi_channels$.class +[debug]  include/ic_tag_ext_in_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class +[debug]  include/gpr_exu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/gpr_exu.class +[debug]  include/inst_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/inst_pkt_t.class +[debug]  include/dec_bp.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_bp.class +[debug]  include/dec_pic.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_pic.class +[debug]  include/lsu_exu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_exu.class +[debug]  include/lsu_dma.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_dma.class +[debug]  include/class_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/class_pkt_t.class +[debug]  include/dma_mem_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dma_mem_ctl.class +[debug]  include/dec_dbg.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_dbg.class +[debug]  include/dma_dccm_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dma_dccm_ctl.class +[debug]  include/predict_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/predict_pkt_t.class +[debug]  include/br_tlu_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/br_tlu_pkt_t.class +[debug]  include/exu_bp.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/exu_bp.class +[debug]  include/dec_tlu_csr_pkt.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class +[debug]  include/trigger_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/trigger_pkt_t.class +[debug]  include/dec_alu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_alu.class +[debug]  include/lsu_dec.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_dec.class +[debug]  include/read_data.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/read_data.class +[debug]  include/write_data.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/write_data.class +[debug]  include/alu_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/alu_pkt_t.class +[debug]  include/rets_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/rets_pkt_t.class +[debug]  include/read_addr$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/read_addr$.class +[debug]  dec +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec +[debug]  dec/dec_trigger$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_trigger$$anon$1.class +[debug]  dec/dec_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_IO.class +[debug]  dec/CSR_VAL.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/CSR_VAL.class +[debug]  dec/dec_ib_ctl_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_ib_ctl_IO.class +[debug]  dec/dec_tlu_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_tlu_ctl.class +[debug]  dec/dec_timer_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_timer_ctl.class +[debug]  dec/dec_dec_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_dec_ctl$$anon$1.class +[debug]  dec/dec_gpr_ctl_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_gpr_ctl_IO.class +[debug]  dec/dec_ib_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_ib_ctl.class +[debug]  dec/CSR_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/CSR_IO.class +[debug]  dec/dec_decode_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class +[debug]  dec/dec_decode_csr_read.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_decode_csr_read.class +[debug]  dec/dec.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec.class +[debug]  dec/dec_decode_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_decode_ctl.class +[debug]  dec/dec_trigger.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_trigger.class +[debug]  dec/csr_tlu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/csr_tlu.class +[debug]  dec/dec_dec_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_dec_ctl.class +[debug]  dec/dec_gpr_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_gpr_ctl.class +[debug]  dec/CSRs.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/CSRs.class +[debug]  dec/dec_decode_csr_read_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class +[debug]  dec/dec_tlu_ctl_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class +[debug]  dec/dec_timer_ctl_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class +[debug] Done packaging. diff --git a/verif/LEC/config.py b/verif/LEC/config.py new file mode 100644 index 00000000..4a8077e8 --- /dev/null +++ b/verif/LEC/config.py @@ -0,0 +1,39 @@ +import re +infile= open("./configs/snapshots/default/param.vh",'r') +params = [] +lines = infile.readlines() +for line in lines: + patern_1=re.match(r'(.*):(.*)' , line ) + if ((patern_1)): + lesson_group2=patern_1.group(1) + splittedl = lesson_group2.split() + split_data='' + for x in splittedl: + split_data=split_data+" "+x + lesson_group3=patern_1.group(2) + splittedl2 = lesson_group3.split() + split_data2='' + for x in splittedl2: + split_data2=split_data2+" "+x + else: + continue + params.append(split_data+" = " + split_data2) + +#writing to a file +filename2 = "./verif/LEC/LEC_RTL/Golden_RTL/parameter.sv" +#w+ tells python we are opening the file to write into it +outfile = open(filename2, 'w+') +outfile.write("#(parameter"+"\n") +outfile.write("\t"+" AWIDTH = 7,"+"\n") +outfile.write("\t"+" TAG = 1'h1,"+"\n") +for x in params: + if ("DCCM_INDEX_BITS") in x: + y="// " + "DCCM_INDEX_BITS = 4'hC ," + outfile.write("\t"+str(y)+"\n") + else: + outfile.write("\t"+str(x)+"\n") +outfile.write(")"+"\n") +outfile.close() #Close file +print("Done...!") + +