Bus-buffer testing start
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@ -6256,7 +6256,7 @@ circuit el2_lsu_bus_buffer :
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node _T_4778 = mux(obuf_sideeffect, obuf_addr, _T_4777) @[el2_lsu_bus_buffer.scala 592:27]
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node _T_4778 = mux(obuf_sideeffect, obuf_addr, _T_4777) @[el2_lsu_bus_buffer.scala 592:27]
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io.lsu_axi_awaddr <= _T_4778 @[el2_lsu_bus_buffer.scala 592:21]
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io.lsu_axi_awaddr <= _T_4778 @[el2_lsu_bus_buffer.scala 592:21]
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node _T_4779 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58]
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node _T_4779 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58]
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node _T_4780 = mux(obuf_sideeffect, _T_4779, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 593:27]
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node _T_4780 = mux(obuf_sideeffect, _T_4779, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 593:27]
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io.lsu_axi_awsize <= _T_4780 @[el2_lsu_bus_buffer.scala 593:21]
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io.lsu_axi_awsize <= _T_4780 @[el2_lsu_bus_buffer.scala 593:21]
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io.lsu_axi_awprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 594:21]
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io.lsu_axi_awprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 594:21]
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node _T_4781 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 595:28]
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node _T_4781 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 595:28]
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@ -2602,7 +2602,7 @@ module el2_lsu_bus_buffer(
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assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4777; // @[el2_lsu_bus_buffer.scala 592:21]
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assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4777; // @[el2_lsu_bus_buffer.scala 592:21]
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assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 596:23]
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assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 596:23]
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assign io_lsu_axi_awlen = 8'h0; // @[el2_lsu_bus_buffer.scala 597:20]
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assign io_lsu_axi_awlen = 8'h0; // @[el2_lsu_bus_buffer.scala 597:20]
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assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4779 : 3'h2; // @[el2_lsu_bus_buffer.scala 593:21]
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assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4779 : 3'h3; // @[el2_lsu_bus_buffer.scala 593:21]
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assign io_lsu_axi_awburst = 2'h1; // @[el2_lsu_bus_buffer.scala 598:22]
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assign io_lsu_axi_awburst = 2'h1; // @[el2_lsu_bus_buffer.scala 598:22]
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assign io_lsu_axi_awlock = 1'h0; // @[el2_lsu_bus_buffer.scala 600:21]
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assign io_lsu_axi_awlock = 1'h0; // @[el2_lsu_bus_buffer.scala 600:21]
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assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 595:22]
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assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 595:22]
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@ -590,7 +590,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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io.lsu_axi_awvalid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending
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io.lsu_axi_awvalid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending
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io.lsu_axi_awid := obuf_tag0
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io.lsu_axi_awid := obuf_tag0
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io.lsu_axi_awaddr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W)))
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io.lsu_axi_awaddr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W)))
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io.lsu_axi_awsize := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 2.U(3.W))
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io.lsu_axi_awsize := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W))
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io.lsu_axi_awprot := 0.U
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io.lsu_axi_awprot := 0.U
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io.lsu_axi_awcache := Mux(obuf_sideeffect, 0.U, 15.U)
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io.lsu_axi_awcache := Mux(obuf_sideeffect, 0.U, 15.U)
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io.lsu_axi_awregion := obuf_addr(31,28)
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io.lsu_axi_awregion := obuf_addr(31,28)
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