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Hard-coded values

This commit is contained in:
waleed-lm 2020-10-09 16:28:54 +05:00
parent 44969ef6b6
commit 9c61c63e9e
4 changed files with 17 additions and 13 deletions
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8
el2_ifu_iccm_mem.fir
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@ -528,16 +528,16 @@ circuit el2_ifu_iccm_mem :
node _T_389 = or(_T_388, _T_386) @[Mux.scala 27:72] node _T_389 = or(_T_388, _T_386) @[Mux.scala 27:72]
wire _T_390 : UInt<32> @[Mux.scala 27:72] wire _T_390 : UInt<32> @[Mux.scala 27:72]
_T_390 <= _T_389 @[Mux.scala 27:72] _T_390 <= _T_389 @[Mux.scala 27:72]
node _T_391 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59] node _T_391 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77] node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_393 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106] node _T_393 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_394 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59] node _T_394 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
node _T_395 = eq(_T_394, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77] node _T_395 = eq(_T_394, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_396 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106] node _T_396 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_397 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59] node _T_397 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
node _T_398 = eq(_T_397, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77] node _T_398 = eq(_T_397, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_399 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106] node _T_399 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_400 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59] node _T_400 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
node _T_401 = eq(_T_400, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77] node _T_401 = eq(_T_400, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_402 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106] node _T_402 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_403 = mux(_T_392, _T_393, UInt<1>("h00")) @[Mux.scala 27:72] node _T_403 = mux(_T_392, _T_393, UInt<1>("h00")) @[Mux.scala 27:72]

20
el2_ifu_iccm_mem.v
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@ -250,10 +250,10 @@ module el2_ifu_iccm_mem(
wire [31:0] _T_387 = _T_383 | _T_384; // @[Mux.scala 27:72] wire [31:0] _T_387 = _T_383 | _T_384; // @[Mux.scala 27:72]
wire [31:0] _T_388 = _T_387 | _T_385; // @[Mux.scala 27:72] wire [31:0] _T_388 = _T_387 | _T_385; // @[Mux.scala 27:72]
wire [31:0] _T_389 = _T_388 | _T_386; // @[Mux.scala 27:72] wire [31:0] _T_389 = _T_388 | _T_386; // @[Mux.scala 27:72]
wire _T_392 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 106:77] wire _T_392 = iccm_rd_addr_lo_q[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 106:77]
wire _T_395 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 106:77] wire _T_395 = iccm_rd_addr_lo_q[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 106:77]
wire _T_398 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 106:77] wire _T_398 = iccm_rd_addr_lo_q[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 106:77]
wire _T_401 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 106:77] wire _T_401 = iccm_rd_addr_lo_q[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 106:77]
wire [31:0] _T_403 = _T_392 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_403 = _T_392 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_404 = _T_395 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_404 = _T_395 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_405 = _T_398 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_405 = _T_398 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
@ -270,10 +270,14 @@ module el2_ifu_iccm_mem(
wire [38:0] _T_425 = _T_421 | _T_422; // @[Mux.scala 27:72] wire [38:0] _T_425 = _T_421 | _T_422; // @[Mux.scala 27:72]
wire [38:0] _T_426 = _T_425 | _T_423; // @[Mux.scala 27:72] wire [38:0] _T_426 = _T_425 | _T_423; // @[Mux.scala 27:72]
wire [38:0] _T_427 = _T_426 | _T_424; // @[Mux.scala 27:72] wire [38:0] _T_427 = _T_426 | _T_424; // @[Mux.scala 27:72]
wire [38:0] _T_437 = _T_392 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] wire _T_430 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 110:79]
wire [38:0] _T_438 = _T_395 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] wire _T_432 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 110:79]
wire [38:0] _T_439 = _T_398 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] wire _T_434 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 110:79]
wire [38:0] _T_440 = _T_401 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] wire _T_436 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 110:79]
wire [38:0] _T_437 = _T_430 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_438 = _T_432 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_439 = _T_434 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_440 = _T_436 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_441 = _T_437 | _T_438; // @[Mux.scala 27:72] wire [38:0] _T_441 = _T_437 | _T_438; // @[Mux.scala 27:72]
wire [38:0] _T_442 = _T_441 | _T_439; // @[Mux.scala 27:72] wire [38:0] _T_442 = _T_441 | _T_439; // @[Mux.scala 27:72]
wire [38:0] _T_443 = _T_442 | _T_440; // @[Mux.scala 27:72] wire [38:0] _T_443 = _T_442 | _T_440; // @[Mux.scala 27:72]

2
src/main/scala/ifu/el2_ifu_iccm_mem.scala
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@ -103,7 +103,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U) val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U)
val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i)(31,0))), val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i)(31,0))),
Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-2,0)===i.U)->iccm_bank_dout_fn(i)(31,0)))) Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(i)(31,0))))
io.iccm_rd_data := Mux(iccm_rd_addr_lo_q(0).asBool(),Cat(Fill(16,0.U),iccm_rd_data_pre(63,16)) ,iccm_rd_data_pre) io.iccm_rd_data := Mux(iccm_rd_addr_lo_q(0).asBool(),Cat(Fill(16,0.U),iccm_rd_data_pre(63,16)) ,iccm_rd_data_pre)
io.iccm_rd_data_ecc :=Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i))), io.iccm_rd_data_ecc :=Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i))),

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target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class
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