IMC DONE
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@ -114,6 +114,13 @@
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
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]
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]
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},
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_test",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_wdata"
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]
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},
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_rd_en",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_rd_en",
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22227
el2_ifu_mem_ctl.fir
22227
el2_ifu_mem_ctl.fir
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8714
el2_ifu_mem_ctl.v
8714
el2_ifu_mem_ctl.v
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@ -126,6 +126,7 @@ class mem_ctl_bundle extends Bundle with el2_lib{
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val iccm_buf_correct_ecc = Output(Bool())
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val iccm_buf_correct_ecc = Output(Bool())
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val iccm_correction_state = Output(Bool())
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val iccm_correction_state = Output(Bool())
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val scan_mode = Input(Bool())
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val scan_mode = Input(Bool())
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val test = Output(UInt())
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}
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}
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class el2_ifu_mem_ctl extends Module with el2_lib {
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class el2_ifu_mem_ctl extends Module with el2_lib {
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val io = IO(new mem_ctl_bundle)
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val io = IO(new mem_ctl_bundle)
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@ -632,6 +633,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
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io.iccm_rden := (ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write) | (io.ifc_iccm_access_bf & io.ifc_fetch_req_bf)
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io.iccm_rden := (ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write) | (io.ifc_iccm_access_bf & io.ifc_fetch_req_bf)
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val iccm_dma_rden = ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write
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val iccm_dma_rden = ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write
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io.iccm_wr_size := Fill(3, io.dma_iccm_req) & io.dma_mem_sz
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io.iccm_wr_size := Fill(3, io.dma_iccm_req) & io.dma_mem_sz
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io.test := rvecc_encode(io.dma_mem_wdata(31,0))
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val dma_mem_ecc = Cat(rvecc_encode(io.dma_mem_wdata(63,32)), rvecc_encode(io.dma_mem_wdata(31,0)))
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val dma_mem_ecc = Cat(rvecc_encode(io.dma_mem_wdata(63,32)), rvecc_encode(io.dma_mem_wdata(31,0)))
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val iccm_ecc_corr_data_ff = WireInit(UInt(39.W), 0.U)
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val iccm_ecc_corr_data_ff = WireInit(UInt(39.W), 0.U)
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io.iccm_wr_data := Mux(iccm_correct_ecc & !(ifc_dma_access_q_ok & io.dma_iccm_req), Fill(2,iccm_ecc_corr_data_ff),
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io.iccm_wr_data := Mux(iccm_correct_ecc & !(ifc_dma_access_q_ok & io.dma_iccm_req), Fill(2,iccm_ecc_corr_data_ff),
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