Master updated with one object

firrtl_black_box_resource_files.f

@@ -1,3 +1,3 @@
-/home/abdulhameed.akram/Videos/Quasar/gated_latch.v
+/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v
-/home/abdulhameed.akram/Videos/Quasar/dmi_wrapper.sv
+/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
-/home/abdulhameed.akram/Videos/Quasar/mem.sv
+/home/laraibkhan/Desktop/SweRV-Chislified/mem.sv

gated_latch.v

@@ -1,10 +1,10 @@
 module gated_latch
   (
-   input wire SE, EN, CK,
+   input logic SE, EN, CK,
    output Q
    );
-   reg  en_ff;
+   logic  en_ff;
-   wire  enable;
+   logic  enable;
    assign      enable = EN | SE;
   always @(CK, enable) begin
       if(!CK)

src/main/scala/dbg/dbg.scala

@@ -456,6 +456,3 @@ class dbg extends Module with lib with RequireAsyncReset {
   io.dbg_dma.dbg_ib.dbg_cmd_type      := io.dbg_dec.dbg_ib.dbg_cmd_type
 }
 
-object dbg_main extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
-}

src/main/scala/dec/dec.scala

@@ -298,6 +298,4 @@ class dec extends Module with param with RequireAsyncReset{
   io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
 }
 
-object dec_main extends App {
+
-  println((new chisel3.stage.ChiselStage).emitVerilog(new dec()))
-}

src/main/scala/dma_ctrl.scala

@@ -496,6 +496,4 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
   io.ifu_dma.dma_mem_ctl.dma_mem_tag := io.lsu_dma.dma_mem_tag
 }
 
-object dma extends App {
+
-  println((new chisel3.stage.ChiselStage).emitVerilog(new dma_ctrl()))
-}

src/main/scala/exu/exu.scala

@@ -233,6 +233,3 @@ class exu extends Module with lib with RequireAsyncReset{
   io.dec_exu.tlu_exu.exu_npc_r			:= Mux(i0_pred_correct_upper_r===1.U,  pred_correct_npc_r, i0_flush_path_upper_r)
 }
 
-object exu_main extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new exu()))
-}

src/main/scala/ifu/ifu.scala

@@ -118,6 +118,4 @@ class ifu extends Module with lib with RequireAsyncReset {
   io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error
 }
 
-object ifu_main extends App {
+
-  println((new chisel3.stage.ChiselStage).emitVerilog(new ifu()))
-}

src/main/scala/lsu/lsu.scala

@@ -319,6 +319,3 @@ class lsu extends Module with RequireAsyncReset with param with lib {
   withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)}
 
 }
-object lsu_top extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
-}

src/main/scala/lsu/lsu_bus_buffer.scala

@@ -618,6 +618,3 @@ class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
 }
 
-object bus_buffer extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer()))
-}

src/main/scala/pic_ctrl.scala

@@ -406,6 +406,3 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
 
 }
 
-object pic_gen extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl()))
-}

src/main/scala/quasar.scala

@@ -285,6 +285,3 @@ class quasar extends Module with RequireAsyncReset with lib {
     }
 
 }
-object QUASAR extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
-}

target/scala-2.12/classes/vsrc/gated_latch.v

@@ -1,10 +1,10 @@
 module gated_latch
   (
-   input wire SE, EN, CK,
+   input logic SE, EN, CK,
    output Q
    );
-   reg  en_ff;
+   logic  en_ff;
-   wire  enable;
+   logic  enable;
    assign      enable = EN | SE;
   always @(CK, enable) begin
       if(!CK)

target/scala-2.12/classes/vsrc/mem_mod.sv

@@ -1,5 +1,5 @@
 module el2_btb_tag_hash #(
-`include "el2_param.vh"
+`include "param.vh"
  ) (
                        input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc,
                        output logic [pt.BTB_BTAG_SIZE-1:0] hash
@@ -11,7 +11,7 @@ module el2_btb_tag_hash #(
 endmodule
 
 module el2_btb_tag_hash_fold  #(
-`include "el2_param.vh"
+`include "param.vh"
  )(
                        input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc,
                        output logic [pt.BTB_BTAG_SIZE-1:0] hash
@@ -24,7 +24,7 @@ module el2_btb_tag_hash_fold  #(
 endmodule
 
 module el2_btb_addr_hash  #(
-`include "el2_param.vh"
+`include "param.vh"
  )(
                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
@@ -44,7 +44,7 @@ end
 endmodule
 
 module el2_btb_ghr_hash  #(
-`include "el2_param.vh"
+`include "param.vh"
  )(
                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,