diff --git a/exu.fir b/exu.fir index f6f772b2..6b64e9aa 100644 --- a/exu.fir +++ b/exu.fir @@ -44560,26 +44560,26 @@ circuit exu : io.exu_bp.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[exu.scala 51:39] io.exu_bp.exu_mp_pkt.valid <= UInt<1>("h00") @[exu.scala 52:53] i0_pp_r.bits.toffset <= UInt<1>("h00") @[exu.scala 53:39] - node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 54:69] - node _T = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 55:69] - node x_data_en_q1 = and(_T, io.dec_exu.dec_alu.dec_csr_ren_d) @[exu.scala 55:73] - node _T_1 = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69] - node x_data_en_q2 = and(_T_1, io.dec_exu.decode_exu.dec_i0_branch_d) @[exu.scala 56:73] - node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 57:69] - node _T_2 = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 58:69] - node r_data_en_q2 = and(_T_2, i0_branch_x) @[exu.scala 58:73] - node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 59:68] - node r_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 0, 0) @[exu.scala 60:68] + node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 55:69] + node _T = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69] + node x_data_en_q1 = and(_T, io.dec_exu.dec_alu.dec_csr_ren_d) @[exu.scala 56:73] + node _T_1 = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 57:69] + node x_data_en_q2 = and(_T_1, io.dec_exu.decode_exu.dec_i0_branch_d) @[exu.scala 57:73] + node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 58:69] + node _T_2 = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 59:69] + node r_data_en_q2 = and(_T_2, i0_branch_x) @[exu.scala 59:73] + node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 60:68] + node r_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 0, 0) @[exu.scala 61:68] node _T_3 = cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d) @[Cat.scala 29:58] node predpipe_d = cat(_T_3, io.dec_exu.decode_exu.i0_predict_btag_d) @[Cat.scala 29:58] - node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 63:68] + node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 64:68] wire _T_5 : UInt<31> @[lib.scala 648:38] _T_5 <= UInt<1>("h00") @[lib.scala 648:38] reg i0_flush_path_x : UInt, clock with : (reset => (reset, _T_5)) @[Reg.scala 27:20] when _T_4 : @[Reg.scala 28:19] i0_flush_path_x <= i0_flush_path_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 64:116] + node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 65:116] node _T_7 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] wire _T_8 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] _T_8.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] @@ -44613,21 +44613,21 @@ circuit exu : _T_9.bits.misp <= i0_predict_p_d.bits.misp @[Reg.scala 28:23] _T_9.valid <= i0_predict_p_d.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - i0_predict_p_x.bits.prett <= _T_9.bits.prett @[exu.scala 64:55] - i0_predict_p_x.bits.pret <= _T_9.bits.pret @[exu.scala 64:55] - i0_predict_p_x.bits.way <= _T_9.bits.way @[exu.scala 64:55] - i0_predict_p_x.bits.pja <= _T_9.bits.pja @[exu.scala 64:55] - i0_predict_p_x.bits.pcall <= _T_9.bits.pcall @[exu.scala 64:55] - i0_predict_p_x.bits.br_start_error <= _T_9.bits.br_start_error @[exu.scala 64:55] - i0_predict_p_x.bits.br_error <= _T_9.bits.br_error @[exu.scala 64:55] - i0_predict_p_x.bits.toffset <= _T_9.bits.toffset @[exu.scala 64:55] - i0_predict_p_x.bits.hist <= _T_9.bits.hist @[exu.scala 64:55] - i0_predict_p_x.bits.pc4 <= _T_9.bits.pc4 @[exu.scala 64:55] - i0_predict_p_x.bits.boffset <= _T_9.bits.boffset @[exu.scala 64:55] - i0_predict_p_x.bits.ataken <= _T_9.bits.ataken @[exu.scala 64:55] - i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 64:55] - i0_predict_p_x.valid <= _T_9.valid @[exu.scala 64:55] - node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 65:79] + i0_predict_p_x.bits.prett <= _T_9.bits.prett @[exu.scala 65:55] + i0_predict_p_x.bits.pret <= _T_9.bits.pret @[exu.scala 65:55] + i0_predict_p_x.bits.way <= _T_9.bits.way @[exu.scala 65:55] + i0_predict_p_x.bits.pja <= _T_9.bits.pja @[exu.scala 65:55] + i0_predict_p_x.bits.pcall <= _T_9.bits.pcall @[exu.scala 65:55] + i0_predict_p_x.bits.br_start_error <= _T_9.bits.br_start_error @[exu.scala 65:55] + i0_predict_p_x.bits.br_error <= _T_9.bits.br_error @[exu.scala 65:55] + i0_predict_p_x.bits.toffset <= _T_9.bits.toffset @[exu.scala 65:55] + i0_predict_p_x.bits.hist <= _T_9.bits.hist @[exu.scala 65:55] + i0_predict_p_x.bits.pc4 <= _T_9.bits.pc4 @[exu.scala 65:55] + i0_predict_p_x.bits.boffset <= _T_9.bits.boffset @[exu.scala 65:55] + i0_predict_p_x.bits.ataken <= _T_9.bits.ataken @[exu.scala 65:55] + i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 65:55] + i0_predict_p_x.valid <= _T_9.valid @[exu.scala 65:55] + node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 66:79] inst rvclkhdr of rvclkhdr @[lib.scala 404:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -44638,7 +44638,7 @@ circuit exu : when _T_10 : @[Reg.scala 28:19] predpipe_x <= predpipe_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 66:88] + node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 67:88] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -44649,7 +44649,7 @@ circuit exu : when _T_11 : @[Reg.scala 28:19] predpipe_r <= predpipe_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 67:86] + node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 68:86] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -44660,7 +44660,7 @@ circuit exu : when _T_12 : @[Reg.scala 28:19] ghr_x <= ghr_x_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 68:75] + node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 69:75] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -44671,7 +44671,7 @@ circuit exu : when _T_13 : @[Reg.scala 28:19] i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 69:66] + node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 70:66] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -44682,7 +44682,7 @@ circuit exu : when _T_14 : @[Reg.scala 28:19] i0_flush_upper_x <= i0_flush_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 70:84] + node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -44693,7 +44693,7 @@ circuit exu : when _T_15 : @[Reg.scala 28:19] i0_taken_x <= i0_taken_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] + node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 72:84] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -44704,7 +44704,7 @@ circuit exu : when _T_16 : @[Reg.scala 28:19] i0_valid_x <= i0_valid_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 72:93] + node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 73:93] node _T_18 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] wire _T_19 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] _T_19.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] @@ -44738,44 +44738,44 @@ circuit exu : _T_20.bits.misp <= i0_predict_p_x.bits.misp @[Reg.scala 28:23] _T_20.valid <= i0_predict_p_x.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - i0_pp_r.bits.prett <= _T_20.bits.prett @[exu.scala 72:31] - i0_pp_r.bits.pret <= _T_20.bits.pret @[exu.scala 72:31] - i0_pp_r.bits.way <= _T_20.bits.way @[exu.scala 72:31] - i0_pp_r.bits.pja <= _T_20.bits.pja @[exu.scala 72:31] - i0_pp_r.bits.pcall <= _T_20.bits.pcall @[exu.scala 72:31] - i0_pp_r.bits.br_start_error <= _T_20.bits.br_start_error @[exu.scala 72:31] - i0_pp_r.bits.br_error <= _T_20.bits.br_error @[exu.scala 72:31] - i0_pp_r.bits.toffset <= _T_20.bits.toffset @[exu.scala 72:31] - i0_pp_r.bits.hist <= _T_20.bits.hist @[exu.scala 72:31] - i0_pp_r.bits.pc4 <= _T_20.bits.pc4 @[exu.scala 72:31] - i0_pp_r.bits.boffset <= _T_20.bits.boffset @[exu.scala 72:31] - i0_pp_r.bits.ataken <= _T_20.bits.ataken @[exu.scala 72:31] - i0_pp_r.bits.misp <= _T_20.bits.misp @[exu.scala 72:31] - i0_pp_r.valid <= _T_20.valid @[exu.scala 72:31] - node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 73:94] - node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 73:111] + i0_pp_r.bits.prett <= _T_20.bits.prett @[exu.scala 73:31] + i0_pp_r.bits.pret <= _T_20.bits.pret @[exu.scala 73:31] + i0_pp_r.bits.way <= _T_20.bits.way @[exu.scala 73:31] + i0_pp_r.bits.pja <= _T_20.bits.pja @[exu.scala 73:31] + i0_pp_r.bits.pcall <= _T_20.bits.pcall @[exu.scala 73:31] + i0_pp_r.bits.br_start_error <= _T_20.bits.br_start_error @[exu.scala 73:31] + i0_pp_r.bits.br_error <= _T_20.bits.br_error @[exu.scala 73:31] + i0_pp_r.bits.toffset <= _T_20.bits.toffset @[exu.scala 73:31] + i0_pp_r.bits.hist <= _T_20.bits.hist @[exu.scala 73:31] + i0_pp_r.bits.pc4 <= _T_20.bits.pc4 @[exu.scala 73:31] + i0_pp_r.bits.boffset <= _T_20.bits.boffset @[exu.scala 73:31] + i0_pp_r.bits.ataken <= _T_20.bits.ataken @[exu.scala 73:31] + i0_pp_r.bits.misp <= _T_20.bits.misp @[exu.scala 73:31] + i0_pp_r.valid <= _T_20.valid @[exu.scala 73:31] + node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 74:94] + node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 74:111] wire _T_23 : UInt<6> @[lib.scala 648:38] _T_23 <= UInt<1>("h00") @[lib.scala 648:38] reg pred_temp1 : UInt, clock with : (reset => (reset, _T_23)) @[Reg.scala 27:20] when _T_22 : @[Reg.scala 28:19] pred_temp1 <= _T_21 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 74:109] + node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 75:109] wire _T_25 : UInt @[lib.scala 588:35] _T_25 <= UInt<1>("h00") @[lib.scala 588:35] reg i0_pred_correct_upper_r : UInt, clock with : (reset => (reset, _T_25)) @[Reg.scala 27:20] when _T_24 : @[Reg.scala 28:19] i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 75:73] + node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 76:73] wire _T_27 : UInt @[lib.scala 648:38] _T_27 <= UInt<1>("h00") @[lib.scala 648:38] reg i0_flush_path_upper_r : UInt, clock with : (reset => (reset, _T_27)) @[Reg.scala 27:20] when _T_26 : @[Reg.scala 28:19] i0_flush_path_upper_r <= i0_flush_path_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 76:106] - node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 76:124] + node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 77:106] + node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 77:124] wire _T_30 : UInt<25> @[lib.scala 648:38] _T_30 <= UInt<1>("h00") @[lib.scala 648:38] reg pred_temp2 : UInt, clock with : (reset => (reset, _T_30)) @[Reg.scala 27:20] @@ -44783,7 +44783,7 @@ circuit exu : pred_temp2 <= _T_28 @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_31 = cat(pred_temp2, pred_temp1) @[Cat.scala 29:58] - pred_correct_npc_r <= _T_31 @[exu.scala 77:45] + pred_correct_npc_r <= _T_31 @[exu.scala 78:45] wire _T_32 : UInt _T_32 <= UInt<1>("h00") node _T_33 = xor(ghr_d_ns, _T_32) @[lib.scala 448:21] @@ -44793,7 +44793,7 @@ circuit exu : _T_35 <= ghr_d_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_32 <= _T_35 @[lib.scala 451:16] - ghr_d <= _T_32 @[exu.scala 78:43] + ghr_d <= _T_32 @[exu.scala 79:43] wire _T_36 : UInt<1> _T_36 <= UInt<1>("h00") node _T_37 = xor(io.dec_exu.decode_exu.mul_p.valid, _T_36) @[lib.scala 470:21] @@ -44803,7 +44803,7 @@ circuit exu : _T_39 <= io.dec_exu.decode_exu.mul_p.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_36 <= _T_39 @[lib.scala 473:16] - mul_valid_x <= _T_36 @[exu.scala 79:39] + mul_valid_x <= _T_36 @[exu.scala 80:39] wire _T_40 : UInt _T_40 <= UInt<1>("h00") node _T_41 = xor(io.dec_exu.decode_exu.dec_i0_branch_d, _T_40) @[lib.scala 448:21] @@ -44813,29 +44813,29 @@ circuit exu : _T_43 <= io.dec_exu.decode_exu.dec_i0_branch_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_40 <= _T_43 @[lib.scala 451:16] - i0_branch_x <= _T_40 @[exu.scala 80:39] - node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 82:80] - node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 82:130] - node _T_46 = or(_T_44, _T_45) @[exu.scala 82:84] - node _T_47 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 82:180] - node _T_48 = or(_T_46, _T_47) @[exu.scala 82:134] - node _T_49 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 82:230] - node i0_rs1_bypass_en_d = or(_T_48, _T_49) @[exu.scala 82:184] - node _T_50 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 83:80] - node _T_51 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 83:130] - node _T_52 = or(_T_50, _T_51) @[exu.scala 83:84] - node _T_53 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 83:180] - node _T_54 = or(_T_52, _T_53) @[exu.scala 83:134] - node _T_55 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 83:230] - node i0_rs2_bypass_en_d = or(_T_54, _T_55) @[exu.scala 83:184] - node _T_56 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 86:49] - node _T_57 = bits(_T_56, 0, 0) @[exu.scala 86:53] - node _T_58 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 87:49] - node _T_59 = bits(_T_58, 0, 0) @[exu.scala 87:53] - node _T_60 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 88:49] - node _T_61 = bits(_T_60, 0, 0) @[exu.scala 88:53] - node _T_62 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 89:49] - node _T_63 = bits(_T_62, 0, 0) @[exu.scala 89:53] + i0_branch_x <= _T_40 @[exu.scala 81:39] + node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 83:80] + node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 83:130] + node _T_46 = or(_T_44, _T_45) @[exu.scala 83:84] + node _T_47 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 83:180] + node _T_48 = or(_T_46, _T_47) @[exu.scala 83:134] + node _T_49 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 83:230] + node i0_rs1_bypass_en_d = or(_T_48, _T_49) @[exu.scala 83:184] + node _T_50 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 84:80] + node _T_51 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 84:130] + node _T_52 = or(_T_50, _T_51) @[exu.scala 84:84] + node _T_53 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 84:180] + node _T_54 = or(_T_52, _T_53) @[exu.scala 84:134] + node _T_55 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 84:230] + node i0_rs2_bypass_en_d = or(_T_54, _T_55) @[exu.scala 84:184] + node _T_56 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 87:49] + node _T_57 = bits(_T_56, 0, 0) @[exu.scala 87:53] + node _T_58 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 88:49] + node _T_59 = bits(_T_58, 0, 0) @[exu.scala 88:53] + node _T_60 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 89:49] + node _T_61 = bits(_T_60, 0, 0) @[exu.scala 89:53] + node _T_62 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 90:49] + node _T_63 = bits(_T_62, 0, 0) @[exu.scala 90:53] node _T_64 = mux(_T_57, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_65 = mux(_T_59, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_66 = mux(_T_61, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44845,14 +44845,14 @@ circuit exu : node _T_70 = or(_T_69, _T_67) @[Mux.scala 27:72] wire i0_rs1_bypass_data_d : UInt<32> @[Mux.scala 27:72] i0_rs1_bypass_data_d <= _T_70 @[Mux.scala 27:72] - node _T_71 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 92:49] - node _T_72 = bits(_T_71, 0, 0) @[exu.scala 92:53] - node _T_73 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 93:49] - node _T_74 = bits(_T_73, 0, 0) @[exu.scala 93:53] - node _T_75 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 94:49] - node _T_76 = bits(_T_75, 0, 0) @[exu.scala 94:53] - node _T_77 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 95:49] - node _T_78 = bits(_T_77, 0, 0) @[exu.scala 95:53] + node _T_71 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 93:49] + node _T_72 = bits(_T_71, 0, 0) @[exu.scala 93:53] + node _T_73 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 94:49] + node _T_74 = bits(_T_73, 0, 0) @[exu.scala 94:53] + node _T_75 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 95:49] + node _T_76 = bits(_T_75, 0, 0) @[exu.scala 95:53] + node _T_77 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 96:49] + node _T_78 = bits(_T_77, 0, 0) @[exu.scala 96:53] node _T_79 = mux(_T_72, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_80 = mux(_T_74, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_81 = mux(_T_76, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44862,19 +44862,19 @@ circuit exu : node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72] wire i0_rs2_bypass_data_d : UInt<32> @[Mux.scala 27:72] i0_rs2_bypass_data_d <= _T_85 @[Mux.scala 27:72] - node _T_86 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 99:24] - node _T_87 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 100:6] - node _T_88 = and(_T_87, io.dec_exu.decode_exu.dec_i0_select_pc_d) @[exu.scala 100:26] - node _T_89 = bits(_T_88, 0, 0) @[exu.scala 100:71] + node _T_86 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 100:24] + node _T_87 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 101:6] + node _T_88 = and(_T_87, io.dec_exu.decode_exu.dec_i0_select_pc_d) @[exu.scala 101:26] + node _T_89 = bits(_T_88, 0, 0) @[exu.scala 101:71] node _T_90 = cat(io.dec_exu.ib_exu.dec_i0_pc_d, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_91 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 101:6] - node _T_92 = and(_T_91, io.dec_exu.ib_exu.dec_debug_wdata_rs1_d) @[exu.scala 101:26] - node _T_93 = bits(_T_92, 0, 0) @[exu.scala 101:70] - node _T_94 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 102:6] - node _T_95 = eq(io.dec_exu.ib_exu.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[exu.scala 102:28] - node _T_96 = and(_T_94, _T_95) @[exu.scala 102:26] - node _T_97 = and(_T_96, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 102:69] - node _T_98 = bits(_T_97, 0, 0) @[exu.scala 102:110] + node _T_91 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 102:6] + node _T_92 = and(_T_91, io.dec_exu.ib_exu.dec_debug_wdata_rs1_d) @[exu.scala 102:26] + node _T_93 = bits(_T_92, 0, 0) @[exu.scala 102:70] + node _T_94 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 103:6] + node _T_95 = eq(io.dec_exu.ib_exu.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[exu.scala 103:28] + node _T_96 = and(_T_94, _T_95) @[exu.scala 103:26] + node _T_97 = and(_T_96, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 103:69] + node _T_98 = bits(_T_97, 0, 0) @[exu.scala 103:110] node _T_99 = mux(_T_86, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_100 = mux(_T_89, _T_90, UInt<1>("h00")) @[Mux.scala 27:72] node _T_101 = mux(_T_93, io.dbg_cmd_wrdata, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44884,7 +44884,7 @@ circuit exu : node _T_105 = or(_T_104, _T_102) @[Mux.scala 27:72] wire i0_rs1_d : UInt<32> @[Mux.scala 27:72] i0_rs1_d <= _T_105 @[Mux.scala 27:72] - node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 104:88] + node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 105:88] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -44895,13 +44895,13 @@ circuit exu : when _T_106 : @[Reg.scala 28:19] _T_107 <= i0_rs1_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_107 @[exu.scala 104:57] - node _T_108 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 107:6] - node _T_109 = and(_T_108, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 107:26] - node _T_110 = bits(_T_109, 0, 0) @[exu.scala 107:67] - node _T_111 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 108:6] - node _T_112 = bits(_T_111, 0, 0) @[exu.scala 108:27] - node _T_113 = bits(i0_rs2_bypass_en_d, 0, 0) @[exu.scala 109:26] + io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_107 @[exu.scala 105:57] + node _T_108 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 108:6] + node _T_109 = and(_T_108, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 108:26] + node _T_110 = bits(_T_109, 0, 0) @[exu.scala 108:67] + node _T_111 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 109:6] + node _T_112 = bits(_T_111, 0, 0) @[exu.scala 109:27] + node _T_113 = bits(i0_rs2_bypass_en_d, 0, 0) @[exu.scala 110:26] node _T_114 = mux(_T_110, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_115 = mux(_T_112, io.dec_exu.decode_exu.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_116 = mux(_T_113, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44909,18 +44909,18 @@ circuit exu : node _T_118 = or(_T_117, _T_116) @[Mux.scala 27:72] wire i0_rs2_d : UInt<32> @[Mux.scala 27:72] i0_rs2_d <= _T_118 @[Mux.scala 27:72] - node _T_119 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 114:6] - node _T_120 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 114:28] - node _T_121 = and(_T_119, _T_120) @[exu.scala 114:26] - node _T_122 = and(_T_121, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 114:68] - node _T_123 = and(_T_122, io.dec_qual_lsu_d) @[exu.scala 114:108] - node _T_124 = bits(_T_123, 0, 0) @[exu.scala 114:129] - node _T_125 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 115:27] - node _T_126 = and(i0_rs1_bypass_en_d, _T_125) @[exu.scala 115:25] - node _T_127 = and(_T_126, io.dec_qual_lsu_d) @[exu.scala 115:67] - node _T_128 = bits(_T_127, 0, 0) @[exu.scala 115:88] - node _T_129 = and(io.dec_exu.decode_exu.dec_extint_stall, io.dec_qual_lsu_d) @[exu.scala 116:45] - node _T_130 = bits(_T_129, 0, 0) @[exu.scala 116:66] + node _T_119 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 115:6] + node _T_120 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 115:28] + node _T_121 = and(_T_119, _T_120) @[exu.scala 115:26] + node _T_122 = and(_T_121, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 115:68] + node _T_123 = and(_T_122, io.dec_qual_lsu_d) @[exu.scala 115:108] + node _T_124 = bits(_T_123, 0, 0) @[exu.scala 115:129] + node _T_125 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 116:27] + node _T_126 = and(i0_rs1_bypass_en_d, _T_125) @[exu.scala 116:25] + node _T_127 = and(_T_126, io.dec_qual_lsu_d) @[exu.scala 116:67] + node _T_128 = bits(_T_127, 0, 0) @[exu.scala 116:88] + node _T_129 = and(io.dec_exu.decode_exu.dec_extint_stall, io.dec_qual_lsu_d) @[exu.scala 117:45] + node _T_130 = bits(_T_129, 0, 0) @[exu.scala 117:66] node _T_131 = cat(io.dec_exu.tlu_exu.dec_tlu_meihap, UInt<2>("h00")) @[Cat.scala 29:58] node _T_132 = mux(_T_124, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_133 = mux(_T_128, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44929,370 +44929,304 @@ circuit exu : node _T_136 = or(_T_135, _T_134) @[Mux.scala 27:72] wire _T_137 : UInt<32> @[Mux.scala 27:72] _T_137 <= _T_136 @[Mux.scala 27:72] - io.lsu_exu.exu_lsu_rs1_d <= _T_137 @[exu.scala 113:27] - node _T_138 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 120:6] - node _T_139 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 120:28] - node _T_140 = and(_T_138, _T_139) @[exu.scala 120:26] - node _T_141 = and(_T_140, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 120:68] - node _T_142 = and(_T_141, io.dec_qual_lsu_d) @[exu.scala 120:108] - node _T_143 = bits(_T_142, 0, 0) @[exu.scala 120:129] - node _T_144 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 121:27] - node _T_145 = and(i0_rs2_bypass_en_d, _T_144) @[exu.scala 121:25] - node _T_146 = and(_T_145, io.dec_qual_lsu_d) @[exu.scala 121:67] - node _T_147 = bits(_T_146, 0, 0) @[exu.scala 121:88] + io.lsu_exu.exu_lsu_rs1_d <= _T_137 @[exu.scala 114:27] + node _T_138 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 121:6] + node _T_139 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 121:28] + node _T_140 = and(_T_138, _T_139) @[exu.scala 121:26] + node _T_141 = and(_T_140, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 121:68] + node _T_142 = and(_T_141, io.dec_qual_lsu_d) @[exu.scala 121:108] + node _T_143 = bits(_T_142, 0, 0) @[exu.scala 121:129] + node _T_144 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 122:27] + node _T_145 = and(i0_rs2_bypass_en_d, _T_144) @[exu.scala 122:25] + node _T_146 = and(_T_145, io.dec_qual_lsu_d) @[exu.scala 122:67] + node _T_147 = bits(_T_146, 0, 0) @[exu.scala 122:88] node _T_148 = mux(_T_143, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_149 = mux(_T_147, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_150 = or(_T_148, _T_149) @[Mux.scala 27:72] wire _T_151 : UInt<32> @[Mux.scala 27:72] _T_151 <= _T_150 @[Mux.scala 27:72] - io.lsu_exu.exu_lsu_rs2_d <= _T_151 @[exu.scala 119:27] - node _T_152 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 125:6] - node _T_153 = and(_T_152, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 125:26] - node _T_154 = bits(_T_153, 0, 0) @[exu.scala 125:67] - node _T_155 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 126:26] + io.lsu_exu.exu_lsu_rs2_d <= _T_151 @[exu.scala 120:27] + node _T_152 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 126:6] + node _T_153 = and(_T_152, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 126:26] + node _T_154 = bits(_T_153, 0, 0) @[exu.scala 126:67] + node _T_155 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 127:26] node _T_156 = mux(_T_154, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_157 = mux(_T_155, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_158 = or(_T_156, _T_157) @[Mux.scala 27:72] wire muldiv_rs1_d : UInt<32> @[Mux.scala 27:72] muldiv_rs1_d <= _T_158 @[Mux.scala 27:72] - inst i_alu of exu_alu_ctl @[exu.scala 129:19] + inst i_alu of exu_alu_ctl @[exu.scala 130:19] i_alu.clock <= clock i_alu.reset <= reset - io.dec_exu.dec_alu.exu_i0_pc_x <= i_alu.io.dec_alu.exu_i0_pc_x @[exu.scala 130:20] - i_alu.io.dec_alu.dec_i0_br_immed_d <= io.dec_exu.dec_alu.dec_i0_br_immed_d @[exu.scala 130:20] - i_alu.io.dec_alu.dec_csr_rddata_d <= io.dec_exu.dec_alu.dec_csr_rddata_d @[exu.scala 130:20] - i_alu.io.dec_alu.dec_csr_ren_d <= io.dec_exu.dec_alu.dec_csr_ren_d @[exu.scala 130:20] - i_alu.io.dec_alu.dec_i0_alu_decode_d <= io.dec_exu.dec_alu.dec_i0_alu_decode_d @[exu.scala 130:20] - i_alu.io.scan_mode <= io.scan_mode @[exu.scala 131:35] - i_alu.io.enable <= x_data_en @[exu.scala 132:45] - i_alu.io.pp_in.bits.prett <= i0_predict_newp_d.bits.prett @[exu.scala 133:45] - i_alu.io.pp_in.bits.pret <= i0_predict_newp_d.bits.pret @[exu.scala 133:45] - i_alu.io.pp_in.bits.way <= i0_predict_newp_d.bits.way @[exu.scala 133:45] - i_alu.io.pp_in.bits.pja <= i0_predict_newp_d.bits.pja @[exu.scala 133:45] - i_alu.io.pp_in.bits.pcall <= i0_predict_newp_d.bits.pcall @[exu.scala 133:45] - i_alu.io.pp_in.bits.br_start_error <= i0_predict_newp_d.bits.br_start_error @[exu.scala 133:45] - i_alu.io.pp_in.bits.br_error <= i0_predict_newp_d.bits.br_error @[exu.scala 133:45] - i_alu.io.pp_in.bits.toffset <= i0_predict_newp_d.bits.toffset @[exu.scala 133:45] - i_alu.io.pp_in.bits.hist <= i0_predict_newp_d.bits.hist @[exu.scala 133:45] - i_alu.io.pp_in.bits.pc4 <= i0_predict_newp_d.bits.pc4 @[exu.scala 133:45] - i_alu.io.pp_in.bits.boffset <= i0_predict_newp_d.bits.boffset @[exu.scala 133:45] - i_alu.io.pp_in.bits.ataken <= i0_predict_newp_d.bits.ataken @[exu.scala 133:45] - i_alu.io.pp_in.bits.misp <= i0_predict_newp_d.bits.misp @[exu.scala 133:45] - i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[exu.scala 133:45] - i_alu.io.flush_upper_x <= i0_flush_upper_x @[exu.scala 134:33] - i_alu.io.dec_tlu_flush_lower_r <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[exu.scala 135:41] - node _T_159 = asSInt(i0_rs1_d) @[exu.scala 136:50] - i_alu.io.a_in <= _T_159 @[exu.scala 136:39] - i_alu.io.b_in <= i0_rs2_d @[exu.scala 137:39] - i_alu.io.dec_i0_pc_d <= io.dec_exu.ib_exu.dec_i0_pc_d @[exu.scala 138:33] - i_alu.io.i0_ap.csr_imm <= io.dec_exu.decode_exu.i0_ap.csr_imm @[exu.scala 139:51] - i_alu.io.i0_ap.csr_write <= io.dec_exu.decode_exu.i0_ap.csr_write @[exu.scala 139:51] - i_alu.io.i0_ap.predict_nt <= io.dec_exu.decode_exu.i0_ap.predict_nt @[exu.scala 139:51] - i_alu.io.i0_ap.predict_t <= io.dec_exu.decode_exu.i0_ap.predict_t @[exu.scala 139:51] - i_alu.io.i0_ap.jal <= io.dec_exu.decode_exu.i0_ap.jal @[exu.scala 139:51] - i_alu.io.i0_ap.unsign <= io.dec_exu.decode_exu.i0_ap.unsign @[exu.scala 139:51] - i_alu.io.i0_ap.slt <= io.dec_exu.decode_exu.i0_ap.slt @[exu.scala 139:51] - i_alu.io.i0_ap.sub <= io.dec_exu.decode_exu.i0_ap.sub @[exu.scala 139:51] - i_alu.io.i0_ap.add <= io.dec_exu.decode_exu.i0_ap.add @[exu.scala 139:51] - i_alu.io.i0_ap.bge <= io.dec_exu.decode_exu.i0_ap.bge @[exu.scala 139:51] - i_alu.io.i0_ap.blt <= io.dec_exu.decode_exu.i0_ap.blt @[exu.scala 139:51] - i_alu.io.i0_ap.bne <= io.dec_exu.decode_exu.i0_ap.bne @[exu.scala 139:51] - i_alu.io.i0_ap.beq <= io.dec_exu.decode_exu.i0_ap.beq @[exu.scala 139:51] - i_alu.io.i0_ap.sra <= io.dec_exu.decode_exu.i0_ap.sra @[exu.scala 139:51] - i_alu.io.i0_ap.srl <= io.dec_exu.decode_exu.i0_ap.srl @[exu.scala 139:51] - i_alu.io.i0_ap.sll <= io.dec_exu.decode_exu.i0_ap.sll @[exu.scala 139:51] - i_alu.io.i0_ap.lxor <= io.dec_exu.decode_exu.i0_ap.lxor @[exu.scala 139:51] - i_alu.io.i0_ap.lor <= io.dec_exu.decode_exu.i0_ap.lor @[exu.scala 139:51] - i_alu.io.i0_ap.land <= io.dec_exu.decode_exu.i0_ap.land @[exu.scala 139:51] - i_alu.io.i0_ap.zba <= io.dec_exu.decode_exu.i0_ap.zba @[exu.scala 139:51] - i_alu.io.i0_ap.sh3add <= io.dec_exu.decode_exu.i0_ap.sh3add @[exu.scala 139:51] - i_alu.io.i0_ap.sh2add <= io.dec_exu.decode_exu.i0_ap.sh2add @[exu.scala 139:51] - i_alu.io.i0_ap.sh1add <= io.dec_exu.decode_exu.i0_ap.sh1add @[exu.scala 139:51] - i_alu.io.i0_ap.sbext <= io.dec_exu.decode_exu.i0_ap.sbext @[exu.scala 139:51] - i_alu.io.i0_ap.sbinv <= io.dec_exu.decode_exu.i0_ap.sbinv @[exu.scala 139:51] - i_alu.io.i0_ap.sbclr <= io.dec_exu.decode_exu.i0_ap.sbclr @[exu.scala 139:51] - i_alu.io.i0_ap.sbset <= io.dec_exu.decode_exu.i0_ap.sbset @[exu.scala 139:51] - i_alu.io.i0_ap.zbb <= io.dec_exu.decode_exu.i0_ap.zbb @[exu.scala 139:51] - i_alu.io.i0_ap.gorc <= io.dec_exu.decode_exu.i0_ap.gorc @[exu.scala 139:51] - i_alu.io.i0_ap.grev <= io.dec_exu.decode_exu.i0_ap.grev @[exu.scala 139:51] - i_alu.io.i0_ap.ror <= io.dec_exu.decode_exu.i0_ap.ror @[exu.scala 139:51] - i_alu.io.i0_ap.rol <= io.dec_exu.decode_exu.i0_ap.rol @[exu.scala 139:51] - i_alu.io.i0_ap.packh <= io.dec_exu.decode_exu.i0_ap.packh @[exu.scala 139:51] - i_alu.io.i0_ap.packu <= io.dec_exu.decode_exu.i0_ap.packu @[exu.scala 139:51] - i_alu.io.i0_ap.pack <= io.dec_exu.decode_exu.i0_ap.pack @[exu.scala 139:51] - i_alu.io.i0_ap.max <= io.dec_exu.decode_exu.i0_ap.max @[exu.scala 139:51] - i_alu.io.i0_ap.min <= io.dec_exu.decode_exu.i0_ap.min @[exu.scala 139:51] - i_alu.io.i0_ap.sro <= io.dec_exu.decode_exu.i0_ap.sro @[exu.scala 139:51] - i_alu.io.i0_ap.slo <= io.dec_exu.decode_exu.i0_ap.slo @[exu.scala 139:51] - i_alu.io.i0_ap.sext_h <= io.dec_exu.decode_exu.i0_ap.sext_h @[exu.scala 139:51] - i_alu.io.i0_ap.sext_b <= io.dec_exu.decode_exu.i0_ap.sext_b @[exu.scala 139:51] - i_alu.io.i0_ap.pcnt <= io.dec_exu.decode_exu.i0_ap.pcnt @[exu.scala 139:51] - i_alu.io.i0_ap.ctz <= io.dec_exu.decode_exu.i0_ap.ctz @[exu.scala 139:51] - i_alu.io.i0_ap.clz <= io.dec_exu.decode_exu.i0_ap.clz @[exu.scala 139:51] - i0_flush_upper_d <= i_alu.io.flush_upper_out @[exu.scala 141:35] - i0_flush_path_d <= i_alu.io.flush_path_out @[exu.scala 142:45] - io.exu_flush_final <= i_alu.io.flush_final_out @[exu.scala 143:27] - i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[exu.scala 144:45] - i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[exu.scala 144:45] - i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[exu.scala 144:45] - i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[exu.scala 144:45] - i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[exu.scala 144:45] - i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[exu.scala 144:45] - i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[exu.scala 144:45] - i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[exu.scala 144:45] - i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[exu.scala 144:45] - i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[exu.scala 144:45] - i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[exu.scala 144:45] - i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[exu.scala 144:45] - i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 144:45] - i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 144:45] - i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 145:27] - inst i_mul of exu_mul_ctl @[exu.scala 147:21] + io.dec_exu.dec_alu.exu_i0_pc_x <= i_alu.io.dec_alu.exu_i0_pc_x @[exu.scala 131:20] + i_alu.io.dec_alu.dec_i0_br_immed_d <= io.dec_exu.dec_alu.dec_i0_br_immed_d @[exu.scala 131:20] + i_alu.io.dec_alu.dec_csr_rddata_d <= io.dec_exu.dec_alu.dec_csr_rddata_d @[exu.scala 131:20] + i_alu.io.dec_alu.dec_csr_ren_d <= io.dec_exu.dec_alu.dec_csr_ren_d @[exu.scala 131:20] + i_alu.io.dec_alu.dec_i0_alu_decode_d <= io.dec_exu.dec_alu.dec_i0_alu_decode_d @[exu.scala 131:20] + i_alu.io.scan_mode <= io.scan_mode @[exu.scala 132:35] + i_alu.io.enable <= x_data_en @[exu.scala 133:45] + i_alu.io.pp_in.bits.prett <= i0_predict_newp_d.bits.prett @[exu.scala 134:45] + i_alu.io.pp_in.bits.pret <= i0_predict_newp_d.bits.pret @[exu.scala 134:45] + i_alu.io.pp_in.bits.way <= i0_predict_newp_d.bits.way @[exu.scala 134:45] + i_alu.io.pp_in.bits.pja <= i0_predict_newp_d.bits.pja @[exu.scala 134:45] + i_alu.io.pp_in.bits.pcall <= i0_predict_newp_d.bits.pcall @[exu.scala 134:45] + i_alu.io.pp_in.bits.br_start_error <= i0_predict_newp_d.bits.br_start_error @[exu.scala 134:45] + i_alu.io.pp_in.bits.br_error <= i0_predict_newp_d.bits.br_error @[exu.scala 134:45] + i_alu.io.pp_in.bits.toffset <= i0_predict_newp_d.bits.toffset @[exu.scala 134:45] + i_alu.io.pp_in.bits.hist <= i0_predict_newp_d.bits.hist @[exu.scala 134:45] + i_alu.io.pp_in.bits.pc4 <= i0_predict_newp_d.bits.pc4 @[exu.scala 134:45] + i_alu.io.pp_in.bits.boffset <= i0_predict_newp_d.bits.boffset @[exu.scala 134:45] + i_alu.io.pp_in.bits.ataken <= i0_predict_newp_d.bits.ataken @[exu.scala 134:45] + i_alu.io.pp_in.bits.misp <= i0_predict_newp_d.bits.misp @[exu.scala 134:45] + i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[exu.scala 134:45] + i_alu.io.flush_upper_x <= i0_flush_upper_x @[exu.scala 135:33] + i_alu.io.dec_tlu_flush_lower_r <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[exu.scala 136:41] + node _T_159 = asSInt(i0_rs1_d) @[exu.scala 137:50] + i_alu.io.a_in <= _T_159 @[exu.scala 137:39] + i_alu.io.b_in <= i0_rs2_d @[exu.scala 138:39] + i_alu.io.dec_i0_pc_d <= io.dec_exu.ib_exu.dec_i0_pc_d @[exu.scala 139:33] + i_alu.io.i0_ap.csr_imm <= io.dec_exu.decode_exu.i0_ap.csr_imm @[exu.scala 140:51] + i_alu.io.i0_ap.csr_write <= io.dec_exu.decode_exu.i0_ap.csr_write @[exu.scala 140:51] + i_alu.io.i0_ap.predict_nt <= io.dec_exu.decode_exu.i0_ap.predict_nt @[exu.scala 140:51] + i_alu.io.i0_ap.predict_t <= io.dec_exu.decode_exu.i0_ap.predict_t @[exu.scala 140:51] + i_alu.io.i0_ap.jal <= io.dec_exu.decode_exu.i0_ap.jal @[exu.scala 140:51] + i_alu.io.i0_ap.unsign <= io.dec_exu.decode_exu.i0_ap.unsign @[exu.scala 140:51] + i_alu.io.i0_ap.slt <= io.dec_exu.decode_exu.i0_ap.slt @[exu.scala 140:51] + i_alu.io.i0_ap.sub <= io.dec_exu.decode_exu.i0_ap.sub @[exu.scala 140:51] + i_alu.io.i0_ap.add <= io.dec_exu.decode_exu.i0_ap.add @[exu.scala 140:51] + i_alu.io.i0_ap.bge <= io.dec_exu.decode_exu.i0_ap.bge @[exu.scala 140:51] + i_alu.io.i0_ap.blt <= io.dec_exu.decode_exu.i0_ap.blt @[exu.scala 140:51] + i_alu.io.i0_ap.bne <= io.dec_exu.decode_exu.i0_ap.bne @[exu.scala 140:51] + i_alu.io.i0_ap.beq <= io.dec_exu.decode_exu.i0_ap.beq @[exu.scala 140:51] + i_alu.io.i0_ap.sra <= io.dec_exu.decode_exu.i0_ap.sra @[exu.scala 140:51] + i_alu.io.i0_ap.srl <= io.dec_exu.decode_exu.i0_ap.srl @[exu.scala 140:51] + i_alu.io.i0_ap.sll <= io.dec_exu.decode_exu.i0_ap.sll @[exu.scala 140:51] + i_alu.io.i0_ap.lxor <= io.dec_exu.decode_exu.i0_ap.lxor @[exu.scala 140:51] + i_alu.io.i0_ap.lor <= io.dec_exu.decode_exu.i0_ap.lor @[exu.scala 140:51] + i_alu.io.i0_ap.land <= io.dec_exu.decode_exu.i0_ap.land @[exu.scala 140:51] + i_alu.io.i0_ap.zba <= io.dec_exu.decode_exu.i0_ap.zba @[exu.scala 140:51] + i_alu.io.i0_ap.sh3add <= io.dec_exu.decode_exu.i0_ap.sh3add @[exu.scala 140:51] + i_alu.io.i0_ap.sh2add <= io.dec_exu.decode_exu.i0_ap.sh2add @[exu.scala 140:51] + i_alu.io.i0_ap.sh1add <= io.dec_exu.decode_exu.i0_ap.sh1add @[exu.scala 140:51] + i_alu.io.i0_ap.sbext <= io.dec_exu.decode_exu.i0_ap.sbext @[exu.scala 140:51] + i_alu.io.i0_ap.sbinv <= io.dec_exu.decode_exu.i0_ap.sbinv @[exu.scala 140:51] + i_alu.io.i0_ap.sbclr <= io.dec_exu.decode_exu.i0_ap.sbclr @[exu.scala 140:51] + i_alu.io.i0_ap.sbset <= io.dec_exu.decode_exu.i0_ap.sbset @[exu.scala 140:51] + i_alu.io.i0_ap.zbb <= io.dec_exu.decode_exu.i0_ap.zbb @[exu.scala 140:51] + i_alu.io.i0_ap.gorc <= io.dec_exu.decode_exu.i0_ap.gorc @[exu.scala 140:51] + i_alu.io.i0_ap.grev <= io.dec_exu.decode_exu.i0_ap.grev @[exu.scala 140:51] + i_alu.io.i0_ap.ror <= io.dec_exu.decode_exu.i0_ap.ror @[exu.scala 140:51] + i_alu.io.i0_ap.rol <= io.dec_exu.decode_exu.i0_ap.rol @[exu.scala 140:51] + i_alu.io.i0_ap.packh <= io.dec_exu.decode_exu.i0_ap.packh @[exu.scala 140:51] + i_alu.io.i0_ap.packu <= io.dec_exu.decode_exu.i0_ap.packu @[exu.scala 140:51] + i_alu.io.i0_ap.pack <= io.dec_exu.decode_exu.i0_ap.pack @[exu.scala 140:51] + i_alu.io.i0_ap.max <= io.dec_exu.decode_exu.i0_ap.max @[exu.scala 140:51] + i_alu.io.i0_ap.min <= io.dec_exu.decode_exu.i0_ap.min @[exu.scala 140:51] + i_alu.io.i0_ap.sro <= io.dec_exu.decode_exu.i0_ap.sro @[exu.scala 140:51] + i_alu.io.i0_ap.slo <= io.dec_exu.decode_exu.i0_ap.slo @[exu.scala 140:51] + i_alu.io.i0_ap.sext_h <= io.dec_exu.decode_exu.i0_ap.sext_h @[exu.scala 140:51] + i_alu.io.i0_ap.sext_b <= io.dec_exu.decode_exu.i0_ap.sext_b @[exu.scala 140:51] + i_alu.io.i0_ap.pcnt <= io.dec_exu.decode_exu.i0_ap.pcnt @[exu.scala 140:51] + i_alu.io.i0_ap.ctz <= io.dec_exu.decode_exu.i0_ap.ctz @[exu.scala 140:51] + i_alu.io.i0_ap.clz <= io.dec_exu.decode_exu.i0_ap.clz @[exu.scala 140:51] + i0_flush_upper_d <= i_alu.io.flush_upper_out @[exu.scala 142:35] + i0_flush_path_d <= i_alu.io.flush_path_out @[exu.scala 143:45] + io.exu_flush_final <= i_alu.io.flush_final_out @[exu.scala 144:27] + i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[exu.scala 145:45] + i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[exu.scala 145:45] + i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[exu.scala 145:45] + i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[exu.scala 145:45] + i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[exu.scala 145:45] + i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[exu.scala 145:45] + i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[exu.scala 145:45] + i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[exu.scala 145:45] + i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[exu.scala 145:45] + i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[exu.scala 145:45] + i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[exu.scala 145:45] + i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[exu.scala 145:45] + i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 145:45] + i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 145:45] + i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 146:27] + inst i_mul of exu_mul_ctl @[exu.scala 148:21] i_mul.clock <= clock i_mul.reset <= reset - i_mul.io.scan_mode <= io.scan_mode @[exu.scala 148:25] - node _T_160 = cat(io.dec_exu.decode_exu.mul_p.bits.crc32c_w, io.dec_exu.decode_exu.mul_p.bits.bfp) @[exu.scala 149:139] - node _T_161 = cat(io.dec_exu.decode_exu.mul_p.bits.crc32c_b, io.dec_exu.decode_exu.mul_p.bits.crc32c_h) @[exu.scala 149:139] - node _T_162 = cat(_T_161, _T_160) @[exu.scala 149:139] - node _T_163 = cat(io.dec_exu.decode_exu.mul_p.bits.crc32_h, io.dec_exu.decode_exu.mul_p.bits.crc32_w) @[exu.scala 149:139] - node _T_164 = cat(io.dec_exu.decode_exu.mul_p.bits.shfl, io.dec_exu.decode_exu.mul_p.bits.unshfl) @[exu.scala 149:139] - node _T_165 = cat(_T_164, io.dec_exu.decode_exu.mul_p.bits.crc32_b) @[exu.scala 149:139] - node _T_166 = cat(_T_165, _T_163) @[exu.scala 149:139] - node _T_167 = cat(_T_166, _T_162) @[exu.scala 149:139] - node _T_168 = cat(io.dec_exu.decode_exu.mul_p.bits.grev, io.dec_exu.decode_exu.mul_p.bits.gorc) @[exu.scala 149:139] - node _T_169 = cat(io.dec_exu.decode_exu.mul_p.bits.clmul, io.dec_exu.decode_exu.mul_p.bits.clmulh) @[exu.scala 149:139] - node _T_170 = cat(_T_169, io.dec_exu.decode_exu.mul_p.bits.clmulr) @[exu.scala 149:139] - node _T_171 = cat(_T_170, _T_168) @[exu.scala 149:139] - node _T_172 = cat(io.dec_exu.decode_exu.mul_p.bits.bext, io.dec_exu.decode_exu.mul_p.bits.bdep) @[exu.scala 149:139] - node _T_173 = cat(io.dec_exu.decode_exu.mul_p.bits.rs1_sign, io.dec_exu.decode_exu.mul_p.bits.rs2_sign) @[exu.scala 149:139] - node _T_174 = cat(_T_173, io.dec_exu.decode_exu.mul_p.bits.low) @[exu.scala 149:139] - node _T_175 = cat(_T_174, _T_172) @[exu.scala 149:139] - node _T_176 = cat(_T_175, _T_171) @[exu.scala 149:139] - node _T_177 = cat(_T_176, _T_167) @[exu.scala 149:139] - node _T_178 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] - node _T_179 = mux(_T_178, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_180 = and(_T_177, _T_179) @[exu.scala 149:146] - wire _T_181 : UInt<19>[1] @[exu.scala 149:92] - _T_181[0] <= _T_180 @[exu.scala 149:92] - wire _T_182 : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[exu.scala 149:242] - wire _T_183 : UInt<20> - _T_183 <= _T_181[0] - node _T_184 = bits(_T_183, 0, 0) @[exu.scala 149:242] - _T_182.bits.bfp <= _T_184 @[exu.scala 149:242] - node _T_185 = bits(_T_183, 1, 1) @[exu.scala 149:242] - _T_182.bits.crc32c_w <= _T_185 @[exu.scala 149:242] - node _T_186 = bits(_T_183, 2, 2) @[exu.scala 149:242] - _T_182.bits.crc32c_h <= _T_186 @[exu.scala 149:242] - node _T_187 = bits(_T_183, 3, 3) @[exu.scala 149:242] - _T_182.bits.crc32c_b <= _T_187 @[exu.scala 149:242] - node _T_188 = bits(_T_183, 4, 4) @[exu.scala 149:242] - _T_182.bits.crc32_w <= _T_188 @[exu.scala 149:242] - node _T_189 = bits(_T_183, 5, 5) @[exu.scala 149:242] - _T_182.bits.crc32_h <= _T_189 @[exu.scala 149:242] - node _T_190 = bits(_T_183, 6, 6) @[exu.scala 149:242] - _T_182.bits.crc32_b <= _T_190 @[exu.scala 149:242] - node _T_191 = bits(_T_183, 7, 7) @[exu.scala 149:242] - _T_182.bits.unshfl <= _T_191 @[exu.scala 149:242] - node _T_192 = bits(_T_183, 8, 8) @[exu.scala 149:242] - _T_182.bits.shfl <= _T_192 @[exu.scala 149:242] - node _T_193 = bits(_T_183, 9, 9) @[exu.scala 149:242] - _T_182.bits.gorc <= _T_193 @[exu.scala 149:242] - node _T_194 = bits(_T_183, 10, 10) @[exu.scala 149:242] - _T_182.bits.grev <= _T_194 @[exu.scala 149:242] - node _T_195 = bits(_T_183, 11, 11) @[exu.scala 149:242] - _T_182.bits.clmulr <= _T_195 @[exu.scala 149:242] - node _T_196 = bits(_T_183, 12, 12) @[exu.scala 149:242] - _T_182.bits.clmulh <= _T_196 @[exu.scala 149:242] - node _T_197 = bits(_T_183, 13, 13) @[exu.scala 149:242] - _T_182.bits.clmul <= _T_197 @[exu.scala 149:242] - node _T_198 = bits(_T_183, 14, 14) @[exu.scala 149:242] - _T_182.bits.bdep <= _T_198 @[exu.scala 149:242] - node _T_199 = bits(_T_183, 15, 15) @[exu.scala 149:242] - _T_182.bits.bext <= _T_199 @[exu.scala 149:242] - node _T_200 = bits(_T_183, 16, 16) @[exu.scala 149:242] - _T_182.bits.low <= _T_200 @[exu.scala 149:242] - node _T_201 = bits(_T_183, 17, 17) @[exu.scala 149:242] - _T_182.bits.rs2_sign <= _T_201 @[exu.scala 149:242] - node _T_202 = bits(_T_183, 18, 18) @[exu.scala 149:242] - _T_182.bits.rs1_sign <= _T_202 @[exu.scala 149:242] - node _T_203 = bits(_T_183, 19, 19) @[exu.scala 149:242] - _T_182.valid <= _T_203 @[exu.scala 149:242] - i_mul.io.mul_p.bits.bfp <= _T_182.bits.bfp @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32c_w <= _T_182.bits.crc32c_w @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32c_h <= _T_182.bits.crc32c_h @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32c_b <= _T_182.bits.crc32c_b @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32_w <= _T_182.bits.crc32_w @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32_h <= _T_182.bits.crc32_h @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32_b <= _T_182.bits.crc32_b @[exu.scala 149:25] - i_mul.io.mul_p.bits.unshfl <= _T_182.bits.unshfl @[exu.scala 149:25] - i_mul.io.mul_p.bits.shfl <= _T_182.bits.shfl @[exu.scala 149:25] - i_mul.io.mul_p.bits.gorc <= _T_182.bits.gorc @[exu.scala 149:25] - i_mul.io.mul_p.bits.grev <= _T_182.bits.grev @[exu.scala 149:25] - i_mul.io.mul_p.bits.clmulr <= _T_182.bits.clmulr @[exu.scala 149:25] - i_mul.io.mul_p.bits.clmulh <= _T_182.bits.clmulh @[exu.scala 149:25] - i_mul.io.mul_p.bits.clmul <= _T_182.bits.clmul @[exu.scala 149:25] - i_mul.io.mul_p.bits.bdep <= _T_182.bits.bdep @[exu.scala 149:25] - i_mul.io.mul_p.bits.bext <= _T_182.bits.bext @[exu.scala 149:25] - i_mul.io.mul_p.bits.low <= _T_182.bits.low @[exu.scala 149:25] - i_mul.io.mul_p.bits.rs2_sign <= _T_182.bits.rs2_sign @[exu.scala 149:25] - i_mul.io.mul_p.bits.rs1_sign <= _T_182.bits.rs1_sign @[exu.scala 149:25] - i_mul.io.mul_p.valid <= _T_182.valid @[exu.scala 149:25] - node _T_204 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] - node _T_205 = mux(_T_204, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_206 = and(muldiv_rs1_d, _T_205) @[exu.scala 150:57] - i_mul.io.rs1_in <= _T_206 @[exu.scala 150:41] - node _T_207 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] - node _T_208 = mux(_T_207, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_209 = and(i0_rs2_d, _T_208) @[exu.scala 151:54] - i_mul.io.rs2_in <= _T_209 @[exu.scala 151:41] - inst i_div of exu_div_ctl @[exu.scala 154:21] + i_mul.io.scan_mode <= io.scan_mode @[exu.scala 149:25] + i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 150:18] + i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 150:18] + i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 150:18] + i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 150:18] + i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 150:18] + i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 150:18] + i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 150:18] + i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 150:18] + i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 150:18] + i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 150:18] + i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 150:18] + i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 150:18] + i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 150:18] + i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 150:18] + node _T_160 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] + node _T_161 = mux(_T_160, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_162 = and(muldiv_rs1_d, _T_161) @[exu.scala 152:57] + i_mul.io.rs1_in <= _T_162 @[exu.scala 152:41] + node _T_163 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] + node _T_164 = mux(_T_163, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_165 = and(i0_rs2_d, _T_164) @[exu.scala 153:54] + i_mul.io.rs2_in <= _T_165 @[exu.scala 153:41] + inst i_div of exu_div_ctl @[exu.scala 156:21] i_div.clock <= clock i_div.reset <= reset - i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 155:20] - i_div.io.dec_div.div_p.bits.rem <= io.dec_exu.dec_div.div_p.bits.rem @[exu.scala 155:20] - i_div.io.dec_div.div_p.bits.unsign <= io.dec_exu.dec_div.div_p.bits.unsign @[exu.scala 155:20] - i_div.io.dec_div.div_p.valid <= io.dec_exu.dec_div.div_p.valid @[exu.scala 155:20] - i_div.io.scan_mode <= io.scan_mode @[exu.scala 156:25] - i_div.io.dividend <= muldiv_rs1_d @[exu.scala 157:33] - i_div.io.divisor <= i0_rs2_d @[exu.scala 158:33] - io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 159:41] - io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 160:33] - node _T_210 = bits(mul_valid_x, 0, 0) @[exu.scala 162:76] - node _T_211 = mux(_T_210, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 162:63] - io.dec_exu.decode_exu.exu_i0_result_x <= _T_211 @[exu.scala 162:57] - i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 163:47] - i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 163:47] - i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 163:47] - i0_predict_newp_d.bits.pja <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[exu.scala 163:47] - i0_predict_newp_d.bits.pcall <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[exu.scala 163:47] - i0_predict_newp_d.bits.br_start_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[exu.scala 163:47] - i0_predict_newp_d.bits.br_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[exu.scala 163:47] - i0_predict_newp_d.bits.toffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[exu.scala 163:47] - i0_predict_newp_d.bits.hist <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[exu.scala 163:47] - i0_predict_newp_d.bits.pc4 <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[exu.scala 163:47] - i0_predict_newp_d.bits.boffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[exu.scala 163:47] - i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 163:47] - i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 163:47] - i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 163:47] - node _T_212 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 164:80] - i0_predict_newp_d.bits.boffset <= _T_212 @[exu.scala 164:47] - io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 166:47] - io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 167:47] - io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 168:47] - node _T_213 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 171:54] - node _T_214 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 171:97] - node _T_215 = and(_T_213, _T_214) @[exu.scala 171:95] - i0_valid_d <= _T_215 @[exu.scala 171:28] - node _T_216 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 172:59] - i0_taken_d <= _T_216 @[exu.scala 172:28] - node _T_217 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 178:8] - node _T_218 = and(_T_217, i0_valid_d) @[exu.scala 178:50] - node _T_219 = bits(_T_218, 0, 0) @[exu.scala 178:64] - node _T_220 = bits(ghr_d, 6, 0) @[exu.scala 178:85] - node _T_221 = cat(_T_220, i0_taken_d) @[Cat.scala 29:58] - node _T_222 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 179:8] - node _T_223 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 179:52] - node _T_224 = and(_T_222, _T_223) @[exu.scala 179:50] - node _T_225 = bits(_T_224, 0, 0) @[exu.scala 179:65] - node _T_226 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 180:50] - node _T_227 = mux(_T_219, _T_221, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_228 = mux(_T_225, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_229 = mux(_T_226, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_230 = or(_T_227, _T_228) @[Mux.scala 27:72] - node _T_231 = or(_T_230, _T_229) @[Mux.scala 27:72] - wire _T_232 : UInt @[Mux.scala 27:72] - _T_232 <= _T_231 @[Mux.scala 27:72] - ghr_d_ns <= _T_232 @[exu.scala 177:14] - node _T_233 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 184:32] - node _T_234 = bits(ghr_x, 6, 0) @[exu.scala 184:50] - node _T_235 = cat(_T_234, i0_taken_x) @[Cat.scala 29:58] - node _T_236 = mux(_T_233, _T_235, ghr_x) @[exu.scala 184:20] - ghr_x_ns <= _T_236 @[exu.scala 184:14] - io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 186:43] - io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 187:43] - io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 188:43] - node _T_237 = bits(i0_pp_r.valid, 0, 0) @[Bitwise.scala 72:15] - node _T_238 = mux(_T_237, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_239 = and(_T_238, i0_pp_r.bits.hist) @[exu.scala 189:69] - io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_239 @[exu.scala 189:43] - io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 190:43] - node _T_240 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 191:63] - io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_240 @[exu.scala 191:43] - io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 192:48] - node _T_241 = bits(predpipe_r, 20, 13) @[exu.scala 193:56] - io.exu_bp.exu_i0_br_fghr_r <= _T_241 @[exu.scala 193:43] - node _T_242 = bits(predpipe_r, 12, 5) @[exu.scala 194:56] - io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_242 @[exu.scala 194:43] - io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 195:43] - node _T_243 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 196:67] - wire _T_244 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 196:104] - _T_244.bits.prett <= UInt<31>("h00") @[exu.scala 196:104] - _T_244.bits.pret <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.way <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.pja <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.pcall <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.br_start_error <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.br_error <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.toffset <= UInt<12>("h00") @[exu.scala 196:104] - _T_244.bits.hist <= UInt<2>("h00") @[exu.scala 196:104] - _T_244.bits.pc4 <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.boffset <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.ataken <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.misp <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.valid <= UInt<1>("h00") @[exu.scala 196:104] - node _T_245 = mux(_T_243, i0_predict_p_x, _T_244) @[exu.scala 196:49] - final_predict_mp.bits.prett <= _T_245.bits.prett @[exu.scala 196:43] - final_predict_mp.bits.pret <= _T_245.bits.pret @[exu.scala 196:43] - final_predict_mp.bits.way <= _T_245.bits.way @[exu.scala 196:43] - final_predict_mp.bits.pja <= _T_245.bits.pja @[exu.scala 196:43] - final_predict_mp.bits.pcall <= _T_245.bits.pcall @[exu.scala 196:43] - final_predict_mp.bits.br_start_error <= _T_245.bits.br_start_error @[exu.scala 196:43] - final_predict_mp.bits.br_error <= _T_245.bits.br_error @[exu.scala 196:43] - final_predict_mp.bits.toffset <= _T_245.bits.toffset @[exu.scala 196:43] - final_predict_mp.bits.hist <= _T_245.bits.hist @[exu.scala 196:43] - final_predict_mp.bits.pc4 <= _T_245.bits.pc4 @[exu.scala 196:43] - final_predict_mp.bits.boffset <= _T_245.bits.boffset @[exu.scala 196:43] - final_predict_mp.bits.ataken <= _T_245.bits.ataken @[exu.scala 196:43] - final_predict_mp.bits.misp <= _T_245.bits.misp @[exu.scala 196:43] - final_predict_mp.valid <= _T_245.valid @[exu.scala 196:43] - node _T_246 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 197:66] - node final_predpipe_mp = mux(_T_246, predpipe_x, UInt<1>("h00")) @[exu.scala 197:48] - node _T_247 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:67] - node _T_248 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 199:120] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[exu.scala 199:77] - node _T_250 = and(_T_247, _T_249) @[exu.scala 199:75] - node after_flush_eghr = mux(_T_250, ghr_d, ghr_x) @[exu.scala 199:48] - io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 201:39] - io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 202:39] - io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 203:39] - io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 204:39] - io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 205:39] - io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 206:39] - io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 207:39] - io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 208:39] - io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 209:39] - node _T_251 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 210:68] - io.exu_bp.exu_mp_pkt.bits.hist <= _T_251 @[exu.scala 210:39] - node _T_252 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 211:71] - io.exu_bp.exu_mp_pkt.bits.toffset <= _T_252 @[exu.scala 211:39] - io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 212:39] - node _T_253 = bits(final_predpipe_mp, 12, 5) @[exu.scala 213:59] - io.exu_bp.exu_mp_index <= _T_253 @[exu.scala 213:39] - node _T_254 = bits(final_predpipe_mp, 4, 0) @[exu.scala 214:59] - io.exu_bp.exu_mp_btag <= _T_254 @[exu.scala 214:39] - node _T_255 = bits(final_predpipe_mp, 20, 13) @[exu.scala 215:59] - io.exu_bp.exu_mp_eghr <= _T_255 @[exu.scala 215:39] - node _T_256 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 237:46] - node _T_257 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 238:6] - node _T_258 = and(_T_257, i0_flush_upper_d) @[exu.scala 238:48] - node _T_259 = bits(_T_258, 0, 0) @[exu.scala 238:68] - node _T_260 = mux(_T_256, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_261 = mux(_T_259, i0_flush_path_d, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_262 = or(_T_260, _T_261) @[Mux.scala 27:72] - wire _T_263 : UInt<31> @[Mux.scala 27:72] - _T_263 <= _T_262 @[Mux.scala 27:72] - io.exu_flush_path_final <= _T_263 @[exu.scala 236:33] - node _T_264 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 240:79] - node _T_265 = mux(_T_264, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 240:55] - io.dec_exu.tlu_exu.exu_npc_r <= _T_265 @[exu.scala 240:49] + i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 157:20] + i_div.io.dec_div.div_p.bits.rem <= io.dec_exu.dec_div.div_p.bits.rem @[exu.scala 157:20] + i_div.io.dec_div.div_p.bits.unsign <= io.dec_exu.dec_div.div_p.bits.unsign @[exu.scala 157:20] + i_div.io.dec_div.div_p.valid <= io.dec_exu.dec_div.div_p.valid @[exu.scala 157:20] + i_div.io.scan_mode <= io.scan_mode @[exu.scala 158:25] + i_div.io.dividend <= muldiv_rs1_d @[exu.scala 159:33] + i_div.io.divisor <= i0_rs2_d @[exu.scala 160:33] + io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 161:41] + io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 162:33] + node _T_166 = bits(mul_valid_x, 0, 0) @[exu.scala 164:76] + node _T_167 = mux(_T_166, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 164:63] + io.dec_exu.decode_exu.exu_i0_result_x <= _T_167 @[exu.scala 164:57] + i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 165:47] + i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 165:47] + i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 165:47] + i0_predict_newp_d.bits.pja <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[exu.scala 165:47] + i0_predict_newp_d.bits.pcall <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[exu.scala 165:47] + i0_predict_newp_d.bits.br_start_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[exu.scala 165:47] + i0_predict_newp_d.bits.br_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[exu.scala 165:47] + i0_predict_newp_d.bits.toffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[exu.scala 165:47] + i0_predict_newp_d.bits.hist <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[exu.scala 165:47] + i0_predict_newp_d.bits.pc4 <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[exu.scala 165:47] + i0_predict_newp_d.bits.boffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[exu.scala 165:47] + i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 165:47] + i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 165:47] + i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 165:47] + node _T_168 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 166:80] + i0_predict_newp_d.bits.boffset <= _T_168 @[exu.scala 166:47] + io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 168:47] + io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 169:47] + io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 170:47] + node _T_169 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 173:54] + node _T_170 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 173:97] + node _T_171 = and(_T_169, _T_170) @[exu.scala 173:95] + i0_valid_d <= _T_171 @[exu.scala 173:28] + node _T_172 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 174:59] + i0_taken_d <= _T_172 @[exu.scala 174:28] + node _T_173 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 180:8] + node _T_174 = and(_T_173, i0_valid_d) @[exu.scala 180:50] + node _T_175 = bits(_T_174, 0, 0) @[exu.scala 180:64] + node _T_176 = bits(ghr_d, 6, 0) @[exu.scala 180:85] + node _T_177 = cat(_T_176, i0_taken_d) @[Cat.scala 29:58] + node _T_178 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 181:8] + node _T_179 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 181:52] + node _T_180 = and(_T_178, _T_179) @[exu.scala 181:50] + node _T_181 = bits(_T_180, 0, 0) @[exu.scala 181:65] + node _T_182 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 182:50] + node _T_183 = mux(_T_175, _T_177, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_184 = mux(_T_181, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_185 = mux(_T_182, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_186 = or(_T_183, _T_184) @[Mux.scala 27:72] + node _T_187 = or(_T_186, _T_185) @[Mux.scala 27:72] + wire _T_188 : UInt @[Mux.scala 27:72] + _T_188 <= _T_187 @[Mux.scala 27:72] + ghr_d_ns <= _T_188 @[exu.scala 179:14] + node _T_189 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 186:32] + node _T_190 = bits(ghr_x, 6, 0) @[exu.scala 186:50] + node _T_191 = cat(_T_190, i0_taken_x) @[Cat.scala 29:58] + node _T_192 = mux(_T_189, _T_191, ghr_x) @[exu.scala 186:20] + ghr_x_ns <= _T_192 @[exu.scala 186:14] + io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 188:43] + io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 189:43] + io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 190:43] + node _T_193 = bits(i0_pp_r.valid, 0, 0) @[Bitwise.scala 72:15] + node _T_194 = mux(_T_193, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_195 = and(_T_194, i0_pp_r.bits.hist) @[exu.scala 191:69] + io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_195 @[exu.scala 191:43] + io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 192:43] + node _T_196 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 193:63] + io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_196 @[exu.scala 193:43] + io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 194:48] + node _T_197 = bits(predpipe_r, 20, 13) @[exu.scala 195:56] + io.exu_bp.exu_i0_br_fghr_r <= _T_197 @[exu.scala 195:43] + node _T_198 = bits(predpipe_r, 12, 5) @[exu.scala 196:56] + io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_198 @[exu.scala 196:43] + io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 197:43] + node _T_199 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 198:67] + wire _T_200 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 198:104] + _T_200.bits.prett <= UInt<31>("h00") @[exu.scala 198:104] + _T_200.bits.pret <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.way <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.pja <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.pcall <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.br_start_error <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.br_error <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.toffset <= UInt<12>("h00") @[exu.scala 198:104] + _T_200.bits.hist <= UInt<2>("h00") @[exu.scala 198:104] + _T_200.bits.pc4 <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.boffset <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.ataken <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.misp <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.valid <= UInt<1>("h00") @[exu.scala 198:104] + node _T_201 = mux(_T_199, i0_predict_p_x, _T_200) @[exu.scala 198:49] + final_predict_mp.bits.prett <= _T_201.bits.prett @[exu.scala 198:43] + final_predict_mp.bits.pret <= _T_201.bits.pret @[exu.scala 198:43] + final_predict_mp.bits.way <= _T_201.bits.way @[exu.scala 198:43] + final_predict_mp.bits.pja <= _T_201.bits.pja @[exu.scala 198:43] + final_predict_mp.bits.pcall <= _T_201.bits.pcall @[exu.scala 198:43] + final_predict_mp.bits.br_start_error <= _T_201.bits.br_start_error @[exu.scala 198:43] + final_predict_mp.bits.br_error <= _T_201.bits.br_error @[exu.scala 198:43] + final_predict_mp.bits.toffset <= _T_201.bits.toffset @[exu.scala 198:43] + final_predict_mp.bits.hist <= _T_201.bits.hist @[exu.scala 198:43] + final_predict_mp.bits.pc4 <= _T_201.bits.pc4 @[exu.scala 198:43] + final_predict_mp.bits.boffset <= _T_201.bits.boffset @[exu.scala 198:43] + final_predict_mp.bits.ataken <= _T_201.bits.ataken @[exu.scala 198:43] + final_predict_mp.bits.misp <= _T_201.bits.misp @[exu.scala 198:43] + final_predict_mp.valid <= _T_201.valid @[exu.scala 198:43] + node _T_202 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:66] + node final_predpipe_mp = mux(_T_202, predpipe_x, UInt<1>("h00")) @[exu.scala 199:48] + node _T_203 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 201:67] + node _T_204 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 201:120] + node _T_205 = eq(_T_204, UInt<1>("h00")) @[exu.scala 201:77] + node _T_206 = and(_T_203, _T_205) @[exu.scala 201:75] + node after_flush_eghr = mux(_T_206, ghr_d, ghr_x) @[exu.scala 201:48] + io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 203:39] + io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 204:39] + io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 205:39] + io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 206:39] + io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 207:39] + io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 208:39] + io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 209:39] + io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 210:39] + io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 211:39] + node _T_207 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 212:68] + io.exu_bp.exu_mp_pkt.bits.hist <= _T_207 @[exu.scala 212:39] + node _T_208 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 213:71] + io.exu_bp.exu_mp_pkt.bits.toffset <= _T_208 @[exu.scala 213:39] + io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 214:39] + node _T_209 = bits(final_predpipe_mp, 12, 5) @[exu.scala 215:59] + io.exu_bp.exu_mp_index <= _T_209 @[exu.scala 215:39] + node _T_210 = bits(final_predpipe_mp, 4, 0) @[exu.scala 216:59] + io.exu_bp.exu_mp_btag <= _T_210 @[exu.scala 216:39] + node _T_211 = bits(final_predpipe_mp, 20, 13) @[exu.scala 217:59] + io.exu_bp.exu_mp_eghr <= _T_211 @[exu.scala 217:39] + node _T_212 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 239:46] + node _T_213 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 240:6] + node _T_214 = and(_T_213, i0_flush_upper_d) @[exu.scala 240:48] + node _T_215 = bits(_T_214, 0, 0) @[exu.scala 240:68] + node _T_216 = mux(_T_212, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_217 = mux(_T_215, i0_flush_path_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72] + wire _T_219 : UInt<31> @[Mux.scala 27:72] + _T_219 <= _T_218 @[Mux.scala 27:72] + io.exu_flush_path_final <= _T_219 @[exu.scala 238:33] + node _T_220 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 242:79] + node _T_221 = mux(_T_220, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 242:55] + io.dec_exu.tlu_exu.exu_npc_r <= _T_221 @[exu.scala 242:49] diff --git a/exu.v b/exu.v index 6d709859..f8ec13ee 100644 --- a/exu.v +++ b/exu.v @@ -2160,117 +2160,117 @@ module exu( wire rvclkhdr_6_io_en; // @[lib.scala 404:23] wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] wire rvclkhdr_7_io_en; // @[lib.scala 404:23] - wire i_alu_clock; // @[exu.scala 129:19] - wire i_alu_reset; // @[exu.scala 129:19] - wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 129:19] - wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 129:19] - wire [31:0] i_alu_io_dec_alu_dec_csr_rddata_d; // @[exu.scala 129:19] - wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 129:19] - wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 129:19] - wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 129:19] - wire i_alu_io_flush_upper_x; // @[exu.scala 129:19] - wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 129:19] - wire i_alu_io_enable; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_clz; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_ctz; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_pcnt; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sext_b; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sext_h; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_min; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_max; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_pack; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_packu; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_packh; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_rol; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_ror; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_grev; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_gorc; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_zbb; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sbset; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sbclr; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sbinv; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sbext; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_land; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_lor; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_lxor; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sll; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_srl; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sra; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_beq; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_bne; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_blt; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_bge; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_add; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sub; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_slt; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_unsign; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_jal; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_predict_t; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_csr_write; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 129:19] - wire [31:0] i_alu_io_a_in; // @[exu.scala 129:19] - wire [31:0] i_alu_io_b_in; // @[exu.scala 129:19] - wire i_alu_io_pp_in_valid; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 129:19] - wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 129:19] - wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_pja; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_way; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_pret; // @[exu.scala 129:19] - wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 129:19] - wire [31:0] i_alu_io_result_ff; // @[exu.scala 129:19] - wire i_alu_io_flush_upper_out; // @[exu.scala 129:19] - wire i_alu_io_flush_final_out; // @[exu.scala 129:19] - wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 129:19] - wire i_alu_io_pred_correct_out; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_valid; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 129:19] - wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 129:19] - wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 129:19] - wire i_mul_clock; // @[exu.scala 147:21] - wire i_mul_reset; // @[exu.scala 147:21] - wire i_mul_io_mul_p_valid; // @[exu.scala 147:21] - wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 147:21] - wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 147:21] - wire i_mul_io_mul_p_bits_low; // @[exu.scala 147:21] - wire [31:0] i_mul_io_rs1_in; // @[exu.scala 147:21] - wire [31:0] i_mul_io_rs2_in; // @[exu.scala 147:21] - wire [31:0] i_mul_io_result_x; // @[exu.scala 147:21] - wire i_div_clock; // @[exu.scala 154:21] - wire i_div_reset; // @[exu.scala 154:21] - wire [31:0] i_div_io_dividend; // @[exu.scala 154:21] - wire [31:0] i_div_io_divisor; // @[exu.scala 154:21] - wire [31:0] i_div_io_exu_div_result; // @[exu.scala 154:21] - wire i_div_io_exu_div_wren; // @[exu.scala 154:21] - wire i_div_io_dec_div_div_p_valid; // @[exu.scala 154:21] - wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 154:21] - wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 154:21] - wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 154:21] - wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 54:69] - wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 55:73] - wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 56:73] - wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 57:69] + wire i_alu_clock; // @[exu.scala 130:19] + wire i_alu_reset; // @[exu.scala 130:19] + wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:19] + wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 130:19] + wire [31:0] i_alu_io_dec_alu_dec_csr_rddata_d; // @[exu.scala 130:19] + wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:19] + wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:19] + wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 130:19] + wire i_alu_io_flush_upper_x; // @[exu.scala 130:19] + wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 130:19] + wire i_alu_io_enable; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_clz; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_ctz; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_pcnt; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sext_b; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sext_h; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_min; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_max; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_pack; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_packu; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_packh; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_rol; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_ror; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_grev; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_gorc; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_zbb; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sbset; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sbclr; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sbinv; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sbext; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_land; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_lor; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_lxor; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sll; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_srl; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sra; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_beq; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_bne; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_blt; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_bge; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_add; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sub; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_slt; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_unsign; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_jal; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_predict_t; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_csr_write; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 130:19] + wire [31:0] i_alu_io_a_in; // @[exu.scala 130:19] + wire [31:0] i_alu_io_b_in; // @[exu.scala 130:19] + wire i_alu_io_pp_in_valid; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 130:19] + wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 130:19] + wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_pja; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_way; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_pret; // @[exu.scala 130:19] + wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 130:19] + wire [31:0] i_alu_io_result_ff; // @[exu.scala 130:19] + wire i_alu_io_flush_upper_out; // @[exu.scala 130:19] + wire i_alu_io_flush_final_out; // @[exu.scala 130:19] + wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 130:19] + wire i_alu_io_pred_correct_out; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_valid; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 130:19] + wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 130:19] + wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 130:19] + wire i_mul_clock; // @[exu.scala 148:21] + wire i_mul_reset; // @[exu.scala 148:21] + wire i_mul_io_mul_p_valid; // @[exu.scala 148:21] + wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 148:21] + wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 148:21] + wire i_mul_io_mul_p_bits_low; // @[exu.scala 148:21] + wire [31:0] i_mul_io_rs1_in; // @[exu.scala 148:21] + wire [31:0] i_mul_io_rs2_in; // @[exu.scala 148:21] + wire [31:0] i_mul_io_result_x; // @[exu.scala 148:21] + wire i_div_clock; // @[exu.scala 156:21] + wire i_div_reset; // @[exu.scala 156:21] + wire [31:0] i_div_io_dividend; // @[exu.scala 156:21] + wire [31:0] i_div_io_divisor; // @[exu.scala 156:21] + wire [31:0] i_div_io_exu_div_result; // @[exu.scala 156:21] + wire i_div_io_exu_div_wren; // @[exu.scala 156:21] + wire i_div_io_dec_div_div_p_valid; // @[exu.scala 156:21] + wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 156:21] + wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 156:21] + wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 156:21] + wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 55:69] + wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 56:73] + wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 57:73] + wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 58:69] reg i0_branch_x; // @[Reg.scala 27:20] - wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 58:73] - wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 59:68] - wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 60:68] + wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 59:73] + wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 60:68] + wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 61:68] wire [20:0] predpipe_d = {io_dec_exu_decode_exu_i0_predict_fghr_d,io_dec_exu_decode_exu_i0_predict_index_d,io_dec_exu_decode_exu_i0_predict_btag_d}; // @[Cat.scala 29:58] reg [30:0] i0_flush_path_x; // @[Reg.scala 27:20] - wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 41:53 exu.scala 142:45] + wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 41:53 exu.scala 143:45] reg i0_predict_p_x_valid; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_misp; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_ataken; // @[Reg.scala 27:20] @@ -2284,33 +2284,33 @@ module exu( reg i0_predict_p_x_bits_pja; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_way; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_pret; // @[Reg.scala 27:20] - wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 42:53 exu.scala 144:45] - wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 42:53 exu.scala 144:45] - wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 42:53 exu.scala 144:45] + wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 42:53 exu.scala 145:45] + wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 42:53 exu.scala 145:45] + wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 42:53 exu.scala 145:45] reg [20:0] predpipe_x; // @[Reg.scala 27:20] reg [20:0] predpipe_r; // @[Reg.scala 27:20] reg [7:0] ghr_x; // @[Reg.scala 27:20] reg i0_valid_x; // @[Reg.scala 27:20] reg i0_taken_x; // @[Reg.scala 27:20] - wire [7:0] _T_235 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58] + wire [7:0] _T_191 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58] reg i0_pred_correct_upper_x; // @[Reg.scala 27:20] - wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 47:41 exu.scala 145:27] + wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 47:41 exu.scala 146:27] reg i0_flush_upper_x; // @[Reg.scala 27:20] - wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 48:45 exu.scala 141:35] - wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 172:59] - wire _T_213 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 171:54] - wire _T_214 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 171:97] - wire i0_valid_d = _T_213 & _T_214; // @[exu.scala 171:95] + wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 48:45 exu.scala 142:35] + wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 174:59] + wire _T_169 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 173:54] + wire _T_170 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 173:97] + wire i0_valid_d = _T_169 & _T_170; // @[exu.scala 173:95] reg i0_pp_r_valid; // @[Reg.scala 27:20] reg i0_pp_r_bits_misp; // @[Reg.scala 27:20] reg i0_pp_r_bits_ataken; // @[Reg.scala 27:20] @@ -2325,16 +2325,16 @@ module exu( reg [30:0] i0_flush_path_upper_r; // @[Reg.scala 27:20] reg [24:0] pred_temp2; // @[Reg.scala 27:20] wire [30:0] _T_31 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58] - wire _T_218 = _T_214 & i0_valid_d; // @[exu.scala 178:50] + wire _T_174 = _T_170 & i0_valid_d; // @[exu.scala 180:50] reg [7:0] ghr_d; // @[Reg.scala 27:20] - wire [7:0] _T_221 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58] - wire [7:0] _T_227 = _T_218 ? _T_221 : 8'h0; // @[Mux.scala 27:72] - wire _T_223 = ~i0_valid_d; // @[exu.scala 179:52] - wire _T_224 = _T_214 & _T_223; // @[exu.scala 179:50] - wire [7:0] _T_228 = _T_224 ? ghr_d : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_230 = _T_227 | _T_228; // @[Mux.scala 27:72] - wire [7:0] _T_229 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] - wire [7:0] ghr_d_ns = _T_230 | _T_229; // @[Mux.scala 27:72] + wire [7:0] _T_177 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58] + wire [7:0] _T_183 = _T_174 ? _T_177 : 8'h0; // @[Mux.scala 27:72] + wire _T_179 = ~i0_valid_d; // @[exu.scala 181:52] + wire _T_180 = _T_170 & _T_179; // @[exu.scala 181:50] + wire [7:0] _T_184 = _T_180 ? ghr_d : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_186 = _T_183 | _T_184; // @[Mux.scala 27:72] + wire [7:0] _T_185 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] + wire [7:0] ghr_d_ns = _T_186 | _T_185; // @[Mux.scala 27:72] wire [7:0] _T_33 = ghr_d_ns ^ ghr_d; // @[lib.scala 448:21] wire _T_34 = |_T_33; // @[lib.scala 448:29] reg mul_valid_x; // @[Reg.scala 27:20] @@ -2342,12 +2342,12 @@ module exu( wire _T_38 = |_T_37; // @[lib.scala 470:29] wire _T_41 = io_dec_exu_decode_exu_dec_i0_branch_d ^ i0_branch_x; // @[lib.scala 448:21] wire _T_42 = |_T_41; // @[lib.scala 448:29] - wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 82:84] - wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 82:134] - wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 82:184] - wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 83:84] - wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 83:134] - wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 83:184] + wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 83:84] + wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 83:134] + wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 83:184] + wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 84:84] + wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 84:134] + wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 84:184] wire [31:0] _T_64 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] ? io_dec_exu_decode_exu_dec_i0_result_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_65 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1] ? io_lsu_exu_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_66 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2] ? io_dec_exu_decode_exu_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] @@ -2362,13 +2362,13 @@ module exu( wire [31:0] _T_83 = _T_79 | _T_80; // @[Mux.scala 27:72] wire [31:0] _T_84 = _T_83 | _T_81; // @[Mux.scala 27:72] wire [31:0] i0_rs2_bypass_data_d = _T_84 | _T_82; // @[Mux.scala 27:72] - wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 100:6] - wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 100:26] + wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 101:6] + wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 101:26] wire [31:0] _T_90 = {io_dec_exu_ib_exu_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58] - wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 101:26] - wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:28] - wire _T_96 = _T_87 & _T_95; // @[exu.scala 102:26] - wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 102:69] + wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:26] + wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 103:28] + wire _T_96 = _T_87 & _T_95; // @[exu.scala 103:26] + wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 103:69] wire [31:0] _T_99 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_100 = _T_88 ? _T_90 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_101 = _T_92 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72] @@ -2377,51 +2377,45 @@ module exu( wire [31:0] _T_104 = _T_103 | _T_101; // @[Mux.scala 27:72] wire [31:0] i0_rs1_d = _T_104 | _T_102; // @[Mux.scala 27:72] reg [31:0] _T_107; // @[Reg.scala 27:20] - wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 107:6] - wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 107:26] + wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 108:6] + wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 108:26] wire [31:0] _T_114 = _T_109 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_115 = _T_108 ? io_dec_exu_decode_exu_dec_i0_immed_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_116 = i0_rs2_bypass_en_d ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_117 = _T_114 | _T_115; // @[Mux.scala 27:72] wire [31:0] _T_118 = _T_117 | _T_116; // @[Mux.scala 27:72] - wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 114:28] - wire _T_121 = _T_87 & _T_120; // @[exu.scala 114:26] - wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 114:68] - wire _T_123 = _T_122 & io_dec_qual_lsu_d; // @[exu.scala 114:108] - wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 115:25] - wire _T_127 = _T_126 & io_dec_qual_lsu_d; // @[exu.scala 115:67] - wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_qual_lsu_d; // @[exu.scala 116:45] + wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 115:28] + wire _T_121 = _T_87 & _T_120; // @[exu.scala 115:26] + wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 115:68] + wire _T_123 = _T_122 & io_dec_qual_lsu_d; // @[exu.scala 115:108] + wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 116:25] + wire _T_127 = _T_126 & io_dec_qual_lsu_d; // @[exu.scala 116:67] + wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_qual_lsu_d; // @[exu.scala 117:45] wire [31:0] _T_131 = {io_dec_exu_tlu_exu_dec_tlu_meihap,2'h0}; // @[Cat.scala 29:58] wire [31:0] _T_132 = _T_123 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_133 = _T_127 ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_134 = _T_129 ? _T_131 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_135 = _T_132 | _T_133; // @[Mux.scala 27:72] - wire _T_140 = _T_108 & _T_120; // @[exu.scala 120:26] - wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 120:68] - wire _T_142 = _T_141 & io_dec_qual_lsu_d; // @[exu.scala 120:108] - wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 121:25] - wire _T_146 = _T_145 & io_dec_qual_lsu_d; // @[exu.scala 121:67] + wire _T_140 = _T_108 & _T_120; // @[exu.scala 121:26] + wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 121:68] + wire _T_142 = _T_141 & io_dec_qual_lsu_d; // @[exu.scala 121:108] + wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 122:25] + wire _T_146 = _T_145 & io_dec_qual_lsu_d; // @[exu.scala 122:67] wire [31:0] _T_148 = _T_142 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_149 = _T_146 ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] - wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 125:26] + wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 126:26] wire [31:0] _T_156 = _T_153 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] muldiv_rs1_d = _T_156 | _T_99; // @[Mux.scala 27:72] - wire [9:0] _T_176 = {io_dec_exu_decode_exu_mul_p_bits_rs1_sign,io_dec_exu_decode_exu_mul_p_bits_rs2_sign,io_dec_exu_decode_exu_mul_p_bits_low,io_dec_exu_decode_exu_mul_p_bits_bext,io_dec_exu_decode_exu_mul_p_bits_bdep,io_dec_exu_decode_exu_mul_p_bits_clmul,io_dec_exu_decode_exu_mul_p_bits_clmulh,io_dec_exu_decode_exu_mul_p_bits_clmulr,io_dec_exu_decode_exu_mul_p_bits_grev,io_dec_exu_decode_exu_mul_p_bits_gorc}; // @[exu.scala 149:139] - wire [18:0] _T_177 = {_T_176,io_dec_exu_decode_exu_mul_p_bits_shfl,io_dec_exu_decode_exu_mul_p_bits_unshfl,io_dec_exu_decode_exu_mul_p_bits_crc32_b,io_dec_exu_decode_exu_mul_p_bits_crc32_h,io_dec_exu_decode_exu_mul_p_bits_crc32_w,io_dec_exu_decode_exu_mul_p_bits_crc32c_b,io_dec_exu_decode_exu_mul_p_bits_crc32c_h,io_dec_exu_decode_exu_mul_p_bits_crc32c_w,io_dec_exu_decode_exu_mul_p_bits_bfp}; // @[exu.scala 149:139] - wire [1:0] _T_179 = io_dec_exu_decode_exu_mul_p_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [18:0] _GEN_44 = {{17'd0}, _T_179}; // @[exu.scala 149:146] - wire [18:0] _T_180 = _T_177 & _GEN_44; // @[exu.scala 149:146] - wire [19:0] _T_183 = {{1'd0}, _T_180}; - wire [31:0] _T_205 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_161 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] i0_rs2_d = _T_118; // @[Mux.scala 27:72 Mux.scala 27:72] - wire [1:0] _T_238 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 197:48] - wire _T_250 = i0_flush_upper_x & _T_214; // @[exu.scala 199:75] - wire _T_258 = _T_214 & i0_flush_upper_d; // @[exu.scala 238:48] - wire [30:0] _T_260 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_261 = _T_258 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72] - wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 46:51 exu.scala 77:45] - wire [31:0] _T_265 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 240:55] + wire [1:0] _T_194 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 199:48] + wire _T_206 = i0_flush_upper_x & _T_170; // @[exu.scala 201:75] + wire _T_214 = _T_170 & i0_flush_upper_d; // @[exu.scala 240:48] + wire [30:0] _T_216 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_217 = _T_214 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72] + wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 46:51 exu.scala 78:45] + wire [31:0] _T_221 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 242:55] rvclkhdr rvclkhdr ( // @[lib.scala 404:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) @@ -2454,7 +2448,7 @@ module exu( .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en) ); - exu_alu_ctl i_alu ( // @[exu.scala 129:19] + exu_alu_ctl i_alu ( // @[exu.scala 130:19] .clock(i_alu_clock), .reset(i_alu_reset), .io_dec_alu_dec_i0_alu_decode_d(i_alu_io_dec_alu_dec_i0_alu_decode_d), @@ -2537,7 +2531,7 @@ module exu( .io_predict_p_out_bits_way(i_alu_io_predict_p_out_bits_way), .io_predict_p_out_bits_pret(i_alu_io_predict_p_out_bits_pret) ); - exu_mul_ctl i_mul ( // @[exu.scala 147:21] + exu_mul_ctl i_mul ( // @[exu.scala 148:21] .clock(i_mul_clock), .reset(i_mul_reset), .io_mul_p_valid(i_mul_io_mul_p_valid), @@ -2548,7 +2542,7 @@ module exu( .io_rs2_in(i_mul_io_rs2_in), .io_result_x(i_mul_io_result_x) ); - exu_div_ctl i_div ( // @[exu.scala 154:21] + exu_div_ctl i_div ( // @[exu.scala 156:21] .clock(i_div_clock), .reset(i_div_reset), .io_dividend(i_div_io_dividend), @@ -2560,47 +2554,47 @@ module exu( .io_dec_div_div_p_bits_rem(i_div_io_dec_div_div_p_bits_rem), .io_dec_div_dec_div_cancel(i_div_io_dec_div_dec_div_cancel) ); - assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:20] - assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 162:57] - assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 104:57] - assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_238 & i0_pp_r_bits_hist; // @[exu.scala 189:43] - assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 190:43] - assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 192:48] - assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 194:43] - assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 186:43] - assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 187:43] - assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 191:43] - assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 166:47] - assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 167:47] - assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 168:47] - assign io_dec_exu_tlu_exu_exu_npc_r = _T_265[30:0]; // @[exu.scala 240:49] - assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 195:43] - assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 193:43] - assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 188:43] - assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 52:53 exu.scala 201:39] - assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 203:39] - assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 207:39] - assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 208:39] - assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 209:39] - assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 210:39] - assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 211:39] + assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 131:20] + assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 164:57] + assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 105:57] + assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_194 & i0_pp_r_bits_hist; // @[exu.scala 191:43] + assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 192:43] + assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 194:48] + assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 196:43] + assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 188:43] + assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 189:43] + assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 193:43] + assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 168:47] + assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 169:47] + assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 170:47] + assign io_dec_exu_tlu_exu_exu_npc_r = _T_221[30:0]; // @[exu.scala 242:49] + assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 197:43] + assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 195:43] + assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 190:43] + assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 52:53 exu.scala 203:39] + assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 205:39] + assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 209:39] + assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 210:39] + assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 211:39] + assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 212:39] + assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 213:39] assign io_exu_bp_exu_mp_pkt_bits_br_error = 1'h0; // @[exu.scala 51:39] assign io_exu_bp_exu_mp_pkt_bits_br_start_error = 1'h0; // @[exu.scala 50:44] - assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 204:39] - assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 205:39] - assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 202:39] - assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 206:39] + assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 206:39] + assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 207:39] + assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 204:39] + assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 208:39] assign io_exu_bp_exu_mp_pkt_bits_prett = 31'h0; // @[exu.scala 49:57] - assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 215:39] - assign io_exu_bp_exu_mp_fghr = _T_250 ? ghr_d : ghr_x; // @[exu.scala 212:39] - assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 213:39] - assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 214:39] - assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 143:27] - assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 160:33] - assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 159:41] - assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 113:27] - assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 119:27] - assign io_exu_flush_path_final = _T_260 | _T_261; // @[exu.scala 236:33] + assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 217:39] + assign io_exu_bp_exu_mp_fghr = _T_206 ? ghr_d : ghr_x; // @[exu.scala 214:39] + assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 215:39] + assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 216:39] + assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 144:27] + assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 162:33] + assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 161:41] + assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 114:27] + assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 120:27] + assign io_exu_flush_path_final = _T_216 | _T_217; // @[exu.scala 238:33] assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_io_en = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[lib.scala 407:17] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] @@ -2619,82 +2613,82 @@ module exu( assign rvclkhdr_7_io_en = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[lib.scala 407:17] assign i_alu_clock = clock; assign i_alu_reset = reset; - assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:20] - assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 130:20] - assign i_alu_io_dec_alu_dec_csr_rddata_d = io_dec_exu_dec_alu_dec_csr_rddata_d; // @[exu.scala 130:20] - assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:20] - assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 138:33] - assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[exu.scala 134:33] - assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 135:41] - assign i_alu_io_enable = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 132:45] - assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 139:51] - assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 136:39] - assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 137:39] - assign i_alu_io_pp_in_valid = io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_boffset = io_dec_exu_ib_exu_dec_i0_pc_d[0]; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_pc4 = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_hist = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_toffset = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_br_error = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_br_start_error = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_pcall = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_pja = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_way = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_pret = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 133:45] + assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 131:20] + assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 131:20] + assign i_alu_io_dec_alu_dec_csr_rddata_d = io_dec_exu_dec_alu_dec_csr_rddata_d; // @[exu.scala 131:20] + assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 131:20] + assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 139:33] + assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[exu.scala 135:33] + assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 136:41] + assign i_alu_io_enable = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 133:45] + assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 140:51] + assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 137:39] + assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 138:39] + assign i_alu_io_pp_in_valid = io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_boffset = io_dec_exu_ib_exu_dec_i0_pc_d[0]; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_pc4 = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_hist = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_toffset = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_br_error = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_br_start_error = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_pcall = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_pja = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_way = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_pret = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 134:45] assign i_mul_clock = clock; assign i_mul_reset = reset; - assign i_mul_io_mul_p_valid = _T_183[19]; // @[exu.scala 149:25] - assign i_mul_io_mul_p_bits_rs1_sign = _T_183[18]; // @[exu.scala 149:25] - assign i_mul_io_mul_p_bits_rs2_sign = _T_183[17]; // @[exu.scala 149:25] - assign i_mul_io_mul_p_bits_low = _T_183[16]; // @[exu.scala 149:25] - assign i_mul_io_rs1_in = muldiv_rs1_d & _T_205; // @[exu.scala 150:41] - assign i_mul_io_rs2_in = i0_rs2_d & _T_205; // @[exu.scala 151:41] + assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 150:18] + assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 150:18] + assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 150:18] + assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 150:18] + assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 152:41] + assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 153:41] assign i_div_clock = clock; assign i_div_reset = reset; - assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 157:33] - assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 158:33] - assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 155:20] - assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 155:20] - assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 155:20] - assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 155:20] + assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 159:33] + assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 160:33] + assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 157:20] + assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 157:20] + assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 157:20] + assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 157:20] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -3051,7 +3045,7 @@ end // initial ghr_x <= 8'h0; end else if (x_ctl_en) begin if (i0_valid_x) begin - ghr_x <= _T_235; + ghr_x <= _T_191; end end end diff --git a/src/main/scala/exu/exu.scala b/src/main/scala/exu/exu.scala index b8ed7ea6..cbaea511 100644 --- a/src/main/scala/exu/exu.scala +++ b/src/main/scala/exu/exu.scala @@ -51,6 +51,7 @@ class exu extends Module with lib with RequireAsyncReset{ io.exu_bp.exu_mp_pkt.bits.br_error := 0.U io.exu_bp.exu_mp_pkt.valid := 0.U i0_pp_r.bits.toffset := 0.U + val x_data_en = io.dec_exu.decode_exu.dec_data_en(1) val x_data_en_q1 = io.dec_exu.decode_exu.dec_data_en(1) & io.dec_exu.dec_alu.dec_csr_ren_d val x_data_en_q2 = io.dec_exu.decode_exu.dec_data_en(1) & io.dec_exu.decode_exu.dec_i0_branch_d @@ -146,7 +147,8 @@ class exu extends Module with lib with RequireAsyncReset{ val i_mul = Module(new exu_mul_ctl()) i_mul.io.scan_mode := io.scan_mode - i_mul.io.mul_p := VecInit.tabulate(io.dec_exu.decode_exu.mul_p.getElements.size-1)(i=>io.dec_exu.decode_exu.mul_p.getElements(i).asUInt & Fill(io.dec_exu.decode_exu.mul_p.getElements.size,io.dec_exu.decode_exu.mul_p.valid)).asTypeOf(io.dec_exu.decode_exu.mul_p) //& io.dec_exu.decode_exu.mul_p.valid + i_mul.io.mul_p := io.dec_exu.decode_exu.mul_p + //i_mul.io.mul_p := VecInit.tabulate(io.dec_exu.decode_exu.mul_p.getElements.size-1)(i=>io.dec_exu.decode_exu.mul_p.getElements(i).asUInt & Fill(io.dec_exu.decode_exu.mul_p.getElements.size,io.dec_exu.decode_exu.mul_p.valid)).asTypeOf(io.dec_exu.decode_exu.mul_p) //& io.dec_exu.decode_exu.mul_p.valid i_mul.io.rs1_in := muldiv_rs1_d & Fill(32,io.dec_exu.decode_exu.mul_p.valid) i_mul.io.rs2_in := i0_rs2_d & Fill(32,io.dec_exu.decode_exu.mul_p.valid) val mul_result_x = i_mul.io.result_x diff --git a/target/scala-2.12/classes/exu/exu.class b/target/scala-2.12/classes/exu/exu.class index cd6ede21..0107f466 100644 Binary files a/target/scala-2.12/classes/exu/exu.class and b/target/scala-2.12/classes/exu/exu.class differ diff --git a/target/scala-2.12/classes/exu/exu_main$.class b/target/scala-2.12/classes/exu/exu_main$.class index e6a15875..01347c7c 100644 Binary files a/target/scala-2.12/classes/exu/exu_main$.class and b/target/scala-2.12/classes/exu/exu_main$.class differ diff --git a/target/scala-2.12/classes/exu/exu_main$delayedInit$body.class b/target/scala-2.12/classes/exu/exu_main$delayedInit$body.class index 0b9ee1bc..4e8b98ee 100644 Binary files a/target/scala-2.12/classes/exu/exu_main$delayedInit$body.class and b/target/scala-2.12/classes/exu/exu_main$delayedInit$body.class differ