From 9d2075de6476bd4cecadb8fb9bbeacaa28d0437c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Tue, 26 Jan 2021 16:06:50 +0500 Subject: [PATCH] Multiplier updated --- exu.fir | 874 ++++++++---------- exu.v | 580 ++++++------ src/main/scala/exu/exu.scala | 4 +- target/scala-2.12/classes/exu/exu.class | Bin 264491 -> 260714 bytes target/scala-2.12/classes/exu/exu_main$.class | Bin 3844 -> 3844 bytes .../exu/exu_main$delayedInit$body.class | Bin 730 -> 730 bytes 6 files changed, 694 insertions(+), 764 deletions(-) diff --git a/exu.fir b/exu.fir index f6f772b2..6b64e9aa 100644 --- a/exu.fir +++ b/exu.fir @@ -44560,26 +44560,26 @@ circuit exu : io.exu_bp.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[exu.scala 51:39] io.exu_bp.exu_mp_pkt.valid <= UInt<1>("h00") @[exu.scala 52:53] i0_pp_r.bits.toffset <= UInt<1>("h00") @[exu.scala 53:39] - node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 54:69] - node _T = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 55:69] - node x_data_en_q1 = and(_T, io.dec_exu.dec_alu.dec_csr_ren_d) @[exu.scala 55:73] - node _T_1 = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69] - node x_data_en_q2 = and(_T_1, io.dec_exu.decode_exu.dec_i0_branch_d) @[exu.scala 56:73] - node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 57:69] - node _T_2 = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 58:69] - node r_data_en_q2 = and(_T_2, i0_branch_x) @[exu.scala 58:73] - node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 59:68] - node r_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 0, 0) @[exu.scala 60:68] + node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 55:69] + node _T = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69] + node x_data_en_q1 = and(_T, io.dec_exu.dec_alu.dec_csr_ren_d) @[exu.scala 56:73] + node _T_1 = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 57:69] + node x_data_en_q2 = and(_T_1, io.dec_exu.decode_exu.dec_i0_branch_d) @[exu.scala 57:73] + node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 58:69] + node _T_2 = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 59:69] + node r_data_en_q2 = and(_T_2, i0_branch_x) @[exu.scala 59:73] + node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 60:68] + node r_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 0, 0) @[exu.scala 61:68] node _T_3 = cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d) @[Cat.scala 29:58] node predpipe_d = cat(_T_3, io.dec_exu.decode_exu.i0_predict_btag_d) @[Cat.scala 29:58] - node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 63:68] + node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 64:68] wire _T_5 : UInt<31> @[lib.scala 648:38] _T_5 <= UInt<1>("h00") @[lib.scala 648:38] reg i0_flush_path_x : UInt, clock with : (reset => (reset, _T_5)) @[Reg.scala 27:20] when _T_4 : @[Reg.scala 28:19] i0_flush_path_x <= i0_flush_path_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 64:116] + node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 65:116] node _T_7 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] wire _T_8 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] _T_8.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] @@ -44613,21 +44613,21 @@ circuit exu : _T_9.bits.misp <= i0_predict_p_d.bits.misp @[Reg.scala 28:23] _T_9.valid <= i0_predict_p_d.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - i0_predict_p_x.bits.prett <= _T_9.bits.prett @[exu.scala 64:55] - i0_predict_p_x.bits.pret <= _T_9.bits.pret @[exu.scala 64:55] - i0_predict_p_x.bits.way <= _T_9.bits.way @[exu.scala 64:55] - i0_predict_p_x.bits.pja <= _T_9.bits.pja @[exu.scala 64:55] - i0_predict_p_x.bits.pcall <= _T_9.bits.pcall @[exu.scala 64:55] - i0_predict_p_x.bits.br_start_error <= _T_9.bits.br_start_error @[exu.scala 64:55] - i0_predict_p_x.bits.br_error <= _T_9.bits.br_error @[exu.scala 64:55] - i0_predict_p_x.bits.toffset <= _T_9.bits.toffset @[exu.scala 64:55] - i0_predict_p_x.bits.hist <= _T_9.bits.hist @[exu.scala 64:55] - i0_predict_p_x.bits.pc4 <= _T_9.bits.pc4 @[exu.scala 64:55] - i0_predict_p_x.bits.boffset <= _T_9.bits.boffset @[exu.scala 64:55] - i0_predict_p_x.bits.ataken <= _T_9.bits.ataken @[exu.scala 64:55] - i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 64:55] - i0_predict_p_x.valid <= _T_9.valid @[exu.scala 64:55] - node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 65:79] + i0_predict_p_x.bits.prett <= _T_9.bits.prett @[exu.scala 65:55] + i0_predict_p_x.bits.pret <= _T_9.bits.pret @[exu.scala 65:55] + i0_predict_p_x.bits.way <= _T_9.bits.way @[exu.scala 65:55] + i0_predict_p_x.bits.pja <= _T_9.bits.pja @[exu.scala 65:55] + i0_predict_p_x.bits.pcall <= _T_9.bits.pcall @[exu.scala 65:55] + i0_predict_p_x.bits.br_start_error <= _T_9.bits.br_start_error @[exu.scala 65:55] + i0_predict_p_x.bits.br_error <= _T_9.bits.br_error @[exu.scala 65:55] + i0_predict_p_x.bits.toffset <= _T_9.bits.toffset @[exu.scala 65:55] + i0_predict_p_x.bits.hist <= _T_9.bits.hist @[exu.scala 65:55] + i0_predict_p_x.bits.pc4 <= _T_9.bits.pc4 @[exu.scala 65:55] + i0_predict_p_x.bits.boffset <= _T_9.bits.boffset @[exu.scala 65:55] + i0_predict_p_x.bits.ataken <= _T_9.bits.ataken @[exu.scala 65:55] + i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 65:55] + i0_predict_p_x.valid <= _T_9.valid @[exu.scala 65:55] + node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 66:79] inst rvclkhdr of rvclkhdr @[lib.scala 404:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -44638,7 +44638,7 @@ circuit exu : when _T_10 : @[Reg.scala 28:19] predpipe_x <= predpipe_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 66:88] + node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 67:88] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -44649,7 +44649,7 @@ circuit exu : when _T_11 : @[Reg.scala 28:19] predpipe_r <= predpipe_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 67:86] + node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 68:86] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -44660,7 +44660,7 @@ circuit exu : when _T_12 : @[Reg.scala 28:19] ghr_x <= ghr_x_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 68:75] + node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 69:75] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -44671,7 +44671,7 @@ circuit exu : when _T_13 : @[Reg.scala 28:19] i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 69:66] + node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 70:66] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -44682,7 +44682,7 @@ circuit exu : when _T_14 : @[Reg.scala 28:19] i0_flush_upper_x <= i0_flush_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 70:84] + node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -44693,7 +44693,7 @@ circuit exu : when _T_15 : @[Reg.scala 28:19] i0_taken_x <= i0_taken_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] + node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 72:84] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -44704,7 +44704,7 @@ circuit exu : when _T_16 : @[Reg.scala 28:19] i0_valid_x <= i0_valid_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 72:93] + node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 73:93] node _T_18 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] wire _T_19 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] _T_19.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] @@ -44738,44 +44738,44 @@ circuit exu : _T_20.bits.misp <= i0_predict_p_x.bits.misp @[Reg.scala 28:23] _T_20.valid <= i0_predict_p_x.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - i0_pp_r.bits.prett <= _T_20.bits.prett @[exu.scala 72:31] - i0_pp_r.bits.pret <= _T_20.bits.pret @[exu.scala 72:31] - i0_pp_r.bits.way <= _T_20.bits.way @[exu.scala 72:31] - i0_pp_r.bits.pja <= _T_20.bits.pja @[exu.scala 72:31] - i0_pp_r.bits.pcall <= _T_20.bits.pcall @[exu.scala 72:31] - i0_pp_r.bits.br_start_error <= _T_20.bits.br_start_error @[exu.scala 72:31] - i0_pp_r.bits.br_error <= _T_20.bits.br_error @[exu.scala 72:31] - i0_pp_r.bits.toffset <= _T_20.bits.toffset @[exu.scala 72:31] - i0_pp_r.bits.hist <= _T_20.bits.hist @[exu.scala 72:31] - i0_pp_r.bits.pc4 <= _T_20.bits.pc4 @[exu.scala 72:31] - i0_pp_r.bits.boffset <= _T_20.bits.boffset @[exu.scala 72:31] - i0_pp_r.bits.ataken <= _T_20.bits.ataken @[exu.scala 72:31] - i0_pp_r.bits.misp <= _T_20.bits.misp @[exu.scala 72:31] - i0_pp_r.valid <= _T_20.valid @[exu.scala 72:31] - node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 73:94] - node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 73:111] + i0_pp_r.bits.prett <= _T_20.bits.prett @[exu.scala 73:31] + i0_pp_r.bits.pret <= _T_20.bits.pret @[exu.scala 73:31] + i0_pp_r.bits.way <= _T_20.bits.way @[exu.scala 73:31] + i0_pp_r.bits.pja <= _T_20.bits.pja @[exu.scala 73:31] + i0_pp_r.bits.pcall <= _T_20.bits.pcall @[exu.scala 73:31] + i0_pp_r.bits.br_start_error <= _T_20.bits.br_start_error @[exu.scala 73:31] + i0_pp_r.bits.br_error <= _T_20.bits.br_error @[exu.scala 73:31] + i0_pp_r.bits.toffset <= _T_20.bits.toffset @[exu.scala 73:31] + i0_pp_r.bits.hist <= _T_20.bits.hist @[exu.scala 73:31] + i0_pp_r.bits.pc4 <= _T_20.bits.pc4 @[exu.scala 73:31] + i0_pp_r.bits.boffset <= _T_20.bits.boffset @[exu.scala 73:31] + i0_pp_r.bits.ataken <= _T_20.bits.ataken @[exu.scala 73:31] + i0_pp_r.bits.misp <= _T_20.bits.misp @[exu.scala 73:31] + i0_pp_r.valid <= _T_20.valid @[exu.scala 73:31] + node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 74:94] + node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 74:111] wire _T_23 : UInt<6> @[lib.scala 648:38] _T_23 <= UInt<1>("h00") @[lib.scala 648:38] reg pred_temp1 : UInt, clock with : (reset => (reset, _T_23)) @[Reg.scala 27:20] when _T_22 : @[Reg.scala 28:19] pred_temp1 <= _T_21 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 74:109] + node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 75:109] wire _T_25 : UInt @[lib.scala 588:35] _T_25 <= UInt<1>("h00") @[lib.scala 588:35] reg i0_pred_correct_upper_r : UInt, clock with : (reset => (reset, _T_25)) @[Reg.scala 27:20] when _T_24 : @[Reg.scala 28:19] i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 75:73] + node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 76:73] wire _T_27 : UInt @[lib.scala 648:38] _T_27 <= UInt<1>("h00") @[lib.scala 648:38] reg i0_flush_path_upper_r : UInt, clock with : (reset => (reset, _T_27)) @[Reg.scala 27:20] when _T_26 : @[Reg.scala 28:19] i0_flush_path_upper_r <= i0_flush_path_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 76:106] - node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 76:124] + node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 77:106] + node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 77:124] wire _T_30 : UInt<25> @[lib.scala 648:38] _T_30 <= UInt<1>("h00") @[lib.scala 648:38] reg pred_temp2 : UInt, clock with : (reset => (reset, _T_30)) @[Reg.scala 27:20] @@ -44783,7 +44783,7 @@ circuit exu : pred_temp2 <= _T_28 @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_31 = cat(pred_temp2, pred_temp1) @[Cat.scala 29:58] - pred_correct_npc_r <= _T_31 @[exu.scala 77:45] + pred_correct_npc_r <= _T_31 @[exu.scala 78:45] wire _T_32 : UInt _T_32 <= UInt<1>("h00") node _T_33 = xor(ghr_d_ns, _T_32) @[lib.scala 448:21] @@ -44793,7 +44793,7 @@ circuit exu : _T_35 <= ghr_d_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_32 <= _T_35 @[lib.scala 451:16] - ghr_d <= _T_32 @[exu.scala 78:43] + ghr_d <= _T_32 @[exu.scala 79:43] wire _T_36 : UInt<1> _T_36 <= UInt<1>("h00") node _T_37 = xor(io.dec_exu.decode_exu.mul_p.valid, _T_36) @[lib.scala 470:21] @@ -44803,7 +44803,7 @@ circuit exu : _T_39 <= io.dec_exu.decode_exu.mul_p.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_36 <= _T_39 @[lib.scala 473:16] - mul_valid_x <= _T_36 @[exu.scala 79:39] + mul_valid_x <= _T_36 @[exu.scala 80:39] wire _T_40 : UInt _T_40 <= UInt<1>("h00") node _T_41 = xor(io.dec_exu.decode_exu.dec_i0_branch_d, _T_40) @[lib.scala 448:21] @@ -44813,29 +44813,29 @@ circuit exu : _T_43 <= io.dec_exu.decode_exu.dec_i0_branch_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_40 <= _T_43 @[lib.scala 451:16] - i0_branch_x <= _T_40 @[exu.scala 80:39] - node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 82:80] - node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 82:130] - node _T_46 = or(_T_44, _T_45) @[exu.scala 82:84] - node _T_47 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 82:180] - node _T_48 = or(_T_46, _T_47) @[exu.scala 82:134] - node _T_49 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 82:230] - node i0_rs1_bypass_en_d = or(_T_48, _T_49) @[exu.scala 82:184] - node _T_50 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 83:80] - node _T_51 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 83:130] - node _T_52 = or(_T_50, _T_51) @[exu.scala 83:84] - node _T_53 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 83:180] - node _T_54 = or(_T_52, _T_53) @[exu.scala 83:134] - node _T_55 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 83:230] - node i0_rs2_bypass_en_d = or(_T_54, _T_55) @[exu.scala 83:184] - node _T_56 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 86:49] - node _T_57 = bits(_T_56, 0, 0) @[exu.scala 86:53] - node _T_58 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 87:49] - node _T_59 = bits(_T_58, 0, 0) @[exu.scala 87:53] - node _T_60 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 88:49] - node _T_61 = bits(_T_60, 0, 0) @[exu.scala 88:53] - node _T_62 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 89:49] - node _T_63 = bits(_T_62, 0, 0) @[exu.scala 89:53] + i0_branch_x <= _T_40 @[exu.scala 81:39] + node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 83:80] + node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 83:130] + node _T_46 = or(_T_44, _T_45) @[exu.scala 83:84] + node _T_47 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 83:180] + node _T_48 = or(_T_46, _T_47) @[exu.scala 83:134] + node _T_49 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 83:230] + node i0_rs1_bypass_en_d = or(_T_48, _T_49) @[exu.scala 83:184] + node _T_50 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 84:80] + node _T_51 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 84:130] + node _T_52 = or(_T_50, _T_51) @[exu.scala 84:84] + node _T_53 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 84:180] + node _T_54 = or(_T_52, _T_53) @[exu.scala 84:134] + node _T_55 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 84:230] + node i0_rs2_bypass_en_d = or(_T_54, _T_55) @[exu.scala 84:184] + node _T_56 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 87:49] + node _T_57 = bits(_T_56, 0, 0) @[exu.scala 87:53] + node _T_58 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 88:49] + node _T_59 = bits(_T_58, 0, 0) @[exu.scala 88:53] + node _T_60 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 89:49] + node _T_61 = bits(_T_60, 0, 0) @[exu.scala 89:53] + node _T_62 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 90:49] + node _T_63 = bits(_T_62, 0, 0) @[exu.scala 90:53] node _T_64 = mux(_T_57, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_65 = mux(_T_59, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_66 = mux(_T_61, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44845,14 +44845,14 @@ circuit exu : node _T_70 = or(_T_69, _T_67) @[Mux.scala 27:72] wire i0_rs1_bypass_data_d : UInt<32> @[Mux.scala 27:72] i0_rs1_bypass_data_d <= _T_70 @[Mux.scala 27:72] - node _T_71 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 92:49] - node _T_72 = bits(_T_71, 0, 0) @[exu.scala 92:53] - node _T_73 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 93:49] - node _T_74 = bits(_T_73, 0, 0) @[exu.scala 93:53] - node _T_75 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 94:49] - node _T_76 = bits(_T_75, 0, 0) @[exu.scala 94:53] - node _T_77 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 95:49] - node _T_78 = bits(_T_77, 0, 0) @[exu.scala 95:53] + node _T_71 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 93:49] + node _T_72 = bits(_T_71, 0, 0) @[exu.scala 93:53] + node _T_73 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 94:49] + node _T_74 = bits(_T_73, 0, 0) @[exu.scala 94:53] + node _T_75 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 95:49] + node _T_76 = bits(_T_75, 0, 0) @[exu.scala 95:53] + node _T_77 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 96:49] + node _T_78 = bits(_T_77, 0, 0) @[exu.scala 96:53] node _T_79 = mux(_T_72, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_80 = mux(_T_74, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_81 = mux(_T_76, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44862,19 +44862,19 @@ circuit exu : node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72] wire i0_rs2_bypass_data_d : UInt<32> @[Mux.scala 27:72] i0_rs2_bypass_data_d <= _T_85 @[Mux.scala 27:72] - node _T_86 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 99:24] - node _T_87 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 100:6] - node _T_88 = and(_T_87, io.dec_exu.decode_exu.dec_i0_select_pc_d) @[exu.scala 100:26] - node _T_89 = bits(_T_88, 0, 0) @[exu.scala 100:71] + node _T_86 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 100:24] + node _T_87 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 101:6] + node _T_88 = and(_T_87, io.dec_exu.decode_exu.dec_i0_select_pc_d) @[exu.scala 101:26] + node _T_89 = bits(_T_88, 0, 0) @[exu.scala 101:71] node _T_90 = cat(io.dec_exu.ib_exu.dec_i0_pc_d, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_91 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 101:6] - node _T_92 = and(_T_91, io.dec_exu.ib_exu.dec_debug_wdata_rs1_d) @[exu.scala 101:26] - node _T_93 = bits(_T_92, 0, 0) @[exu.scala 101:70] - node _T_94 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 102:6] - node _T_95 = eq(io.dec_exu.ib_exu.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[exu.scala 102:28] - node _T_96 = and(_T_94, _T_95) @[exu.scala 102:26] - node _T_97 = and(_T_96, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 102:69] - node _T_98 = bits(_T_97, 0, 0) @[exu.scala 102:110] + node _T_91 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 102:6] + node _T_92 = and(_T_91, io.dec_exu.ib_exu.dec_debug_wdata_rs1_d) @[exu.scala 102:26] + node _T_93 = bits(_T_92, 0, 0) @[exu.scala 102:70] + node _T_94 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 103:6] + node _T_95 = eq(io.dec_exu.ib_exu.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[exu.scala 103:28] + node _T_96 = and(_T_94, _T_95) @[exu.scala 103:26] + node _T_97 = and(_T_96, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 103:69] + node _T_98 = bits(_T_97, 0, 0) @[exu.scala 103:110] node _T_99 = mux(_T_86, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_100 = mux(_T_89, _T_90, UInt<1>("h00")) @[Mux.scala 27:72] node _T_101 = mux(_T_93, io.dbg_cmd_wrdata, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44884,7 +44884,7 @@ circuit exu : node _T_105 = or(_T_104, _T_102) @[Mux.scala 27:72] wire i0_rs1_d : UInt<32> @[Mux.scala 27:72] i0_rs1_d <= _T_105 @[Mux.scala 27:72] - node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 104:88] + node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 105:88] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -44895,13 +44895,13 @@ circuit exu : when _T_106 : @[Reg.scala 28:19] _T_107 <= i0_rs1_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_107 @[exu.scala 104:57] - node _T_108 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 107:6] - node _T_109 = and(_T_108, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 107:26] - node _T_110 = bits(_T_109, 0, 0) @[exu.scala 107:67] - node _T_111 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 108:6] - node _T_112 = bits(_T_111, 0, 0) @[exu.scala 108:27] - node _T_113 = bits(i0_rs2_bypass_en_d, 0, 0) @[exu.scala 109:26] + io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_107 @[exu.scala 105:57] + node _T_108 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 108:6] + node _T_109 = and(_T_108, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 108:26] + node _T_110 = bits(_T_109, 0, 0) @[exu.scala 108:67] + node _T_111 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 109:6] + node _T_112 = bits(_T_111, 0, 0) @[exu.scala 109:27] + node _T_113 = bits(i0_rs2_bypass_en_d, 0, 0) @[exu.scala 110:26] node _T_114 = mux(_T_110, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_115 = mux(_T_112, io.dec_exu.decode_exu.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_116 = mux(_T_113, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44909,18 +44909,18 @@ circuit exu : node _T_118 = or(_T_117, _T_116) @[Mux.scala 27:72] wire i0_rs2_d : UInt<32> @[Mux.scala 27:72] i0_rs2_d <= _T_118 @[Mux.scala 27:72] - node _T_119 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 114:6] - node _T_120 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 114:28] - node _T_121 = and(_T_119, _T_120) @[exu.scala 114:26] - node _T_122 = and(_T_121, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 114:68] - node _T_123 = and(_T_122, io.dec_qual_lsu_d) @[exu.scala 114:108] - node _T_124 = bits(_T_123, 0, 0) @[exu.scala 114:129] - node _T_125 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 115:27] - node _T_126 = and(i0_rs1_bypass_en_d, _T_125) @[exu.scala 115:25] - node _T_127 = and(_T_126, io.dec_qual_lsu_d) @[exu.scala 115:67] - node _T_128 = bits(_T_127, 0, 0) @[exu.scala 115:88] - node _T_129 = and(io.dec_exu.decode_exu.dec_extint_stall, io.dec_qual_lsu_d) @[exu.scala 116:45] - node _T_130 = bits(_T_129, 0, 0) @[exu.scala 116:66] + node _T_119 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 115:6] + node _T_120 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 115:28] + node _T_121 = and(_T_119, _T_120) @[exu.scala 115:26] + node _T_122 = and(_T_121, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 115:68] + node _T_123 = and(_T_122, io.dec_qual_lsu_d) @[exu.scala 115:108] + node _T_124 = bits(_T_123, 0, 0) @[exu.scala 115:129] + node _T_125 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 116:27] + node _T_126 = and(i0_rs1_bypass_en_d, _T_125) @[exu.scala 116:25] + node _T_127 = and(_T_126, io.dec_qual_lsu_d) @[exu.scala 116:67] + node _T_128 = bits(_T_127, 0, 0) @[exu.scala 116:88] + node _T_129 = and(io.dec_exu.decode_exu.dec_extint_stall, io.dec_qual_lsu_d) @[exu.scala 117:45] + node _T_130 = bits(_T_129, 0, 0) @[exu.scala 117:66] node _T_131 = cat(io.dec_exu.tlu_exu.dec_tlu_meihap, UInt<2>("h00")) @[Cat.scala 29:58] node _T_132 = mux(_T_124, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_133 = mux(_T_128, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44929,370 +44929,304 @@ circuit exu : node _T_136 = or(_T_135, _T_134) @[Mux.scala 27:72] wire _T_137 : UInt<32> @[Mux.scala 27:72] _T_137 <= _T_136 @[Mux.scala 27:72] - io.lsu_exu.exu_lsu_rs1_d <= _T_137 @[exu.scala 113:27] - node _T_138 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 120:6] - node _T_139 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 120:28] - node _T_140 = and(_T_138, _T_139) @[exu.scala 120:26] - node _T_141 = and(_T_140, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 120:68] - node _T_142 = and(_T_141, io.dec_qual_lsu_d) @[exu.scala 120:108] - node _T_143 = bits(_T_142, 0, 0) @[exu.scala 120:129] - node _T_144 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 121:27] - node _T_145 = and(i0_rs2_bypass_en_d, _T_144) @[exu.scala 121:25] - node _T_146 = and(_T_145, io.dec_qual_lsu_d) @[exu.scala 121:67] - node _T_147 = bits(_T_146, 0, 0) @[exu.scala 121:88] + io.lsu_exu.exu_lsu_rs1_d <= _T_137 @[exu.scala 114:27] + node _T_138 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 121:6] + node _T_139 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 121:28] + node _T_140 = and(_T_138, _T_139) @[exu.scala 121:26] + node _T_141 = and(_T_140, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 121:68] + node _T_142 = and(_T_141, io.dec_qual_lsu_d) @[exu.scala 121:108] + node _T_143 = bits(_T_142, 0, 0) @[exu.scala 121:129] + node _T_144 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 122:27] + node _T_145 = and(i0_rs2_bypass_en_d, _T_144) @[exu.scala 122:25] + node _T_146 = and(_T_145, io.dec_qual_lsu_d) @[exu.scala 122:67] + node _T_147 = bits(_T_146, 0, 0) @[exu.scala 122:88] node _T_148 = mux(_T_143, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_149 = mux(_T_147, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_150 = or(_T_148, _T_149) @[Mux.scala 27:72] wire _T_151 : UInt<32> @[Mux.scala 27:72] _T_151 <= _T_150 @[Mux.scala 27:72] - io.lsu_exu.exu_lsu_rs2_d <= _T_151 @[exu.scala 119:27] - node _T_152 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 125:6] - node _T_153 = and(_T_152, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 125:26] - node _T_154 = bits(_T_153, 0, 0) @[exu.scala 125:67] - node _T_155 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 126:26] + io.lsu_exu.exu_lsu_rs2_d <= _T_151 @[exu.scala 120:27] + node _T_152 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 126:6] + node _T_153 = and(_T_152, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 126:26] + node _T_154 = bits(_T_153, 0, 0) @[exu.scala 126:67] + node _T_155 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 127:26] node _T_156 = mux(_T_154, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_157 = mux(_T_155, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_158 = or(_T_156, _T_157) @[Mux.scala 27:72] wire muldiv_rs1_d : UInt<32> @[Mux.scala 27:72] muldiv_rs1_d <= _T_158 @[Mux.scala 27:72] - inst i_alu of exu_alu_ctl @[exu.scala 129:19] + inst i_alu of exu_alu_ctl @[exu.scala 130:19] i_alu.clock <= clock i_alu.reset <= reset - io.dec_exu.dec_alu.exu_i0_pc_x <= i_alu.io.dec_alu.exu_i0_pc_x @[exu.scala 130:20] - i_alu.io.dec_alu.dec_i0_br_immed_d <= io.dec_exu.dec_alu.dec_i0_br_immed_d @[exu.scala 130:20] - i_alu.io.dec_alu.dec_csr_rddata_d <= io.dec_exu.dec_alu.dec_csr_rddata_d @[exu.scala 130:20] - i_alu.io.dec_alu.dec_csr_ren_d <= io.dec_exu.dec_alu.dec_csr_ren_d @[exu.scala 130:20] - i_alu.io.dec_alu.dec_i0_alu_decode_d <= io.dec_exu.dec_alu.dec_i0_alu_decode_d @[exu.scala 130:20] - i_alu.io.scan_mode <= io.scan_mode @[exu.scala 131:35] - i_alu.io.enable <= x_data_en @[exu.scala 132:45] - i_alu.io.pp_in.bits.prett <= i0_predict_newp_d.bits.prett @[exu.scala 133:45] - i_alu.io.pp_in.bits.pret <= i0_predict_newp_d.bits.pret @[exu.scala 133:45] - i_alu.io.pp_in.bits.way <= i0_predict_newp_d.bits.way @[exu.scala 133:45] - i_alu.io.pp_in.bits.pja <= i0_predict_newp_d.bits.pja @[exu.scala 133:45] - i_alu.io.pp_in.bits.pcall <= i0_predict_newp_d.bits.pcall @[exu.scala 133:45] - i_alu.io.pp_in.bits.br_start_error <= i0_predict_newp_d.bits.br_start_error @[exu.scala 133:45] - i_alu.io.pp_in.bits.br_error <= i0_predict_newp_d.bits.br_error @[exu.scala 133:45] - i_alu.io.pp_in.bits.toffset <= i0_predict_newp_d.bits.toffset @[exu.scala 133:45] - i_alu.io.pp_in.bits.hist <= i0_predict_newp_d.bits.hist @[exu.scala 133:45] - i_alu.io.pp_in.bits.pc4 <= i0_predict_newp_d.bits.pc4 @[exu.scala 133:45] - i_alu.io.pp_in.bits.boffset <= i0_predict_newp_d.bits.boffset @[exu.scala 133:45] - i_alu.io.pp_in.bits.ataken <= i0_predict_newp_d.bits.ataken @[exu.scala 133:45] - i_alu.io.pp_in.bits.misp <= i0_predict_newp_d.bits.misp @[exu.scala 133:45] - i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[exu.scala 133:45] - i_alu.io.flush_upper_x <= i0_flush_upper_x @[exu.scala 134:33] - i_alu.io.dec_tlu_flush_lower_r <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[exu.scala 135:41] - node _T_159 = asSInt(i0_rs1_d) @[exu.scala 136:50] - i_alu.io.a_in <= _T_159 @[exu.scala 136:39] - i_alu.io.b_in <= i0_rs2_d @[exu.scala 137:39] - i_alu.io.dec_i0_pc_d <= io.dec_exu.ib_exu.dec_i0_pc_d @[exu.scala 138:33] - i_alu.io.i0_ap.csr_imm <= io.dec_exu.decode_exu.i0_ap.csr_imm @[exu.scala 139:51] - i_alu.io.i0_ap.csr_write <= io.dec_exu.decode_exu.i0_ap.csr_write @[exu.scala 139:51] - i_alu.io.i0_ap.predict_nt <= io.dec_exu.decode_exu.i0_ap.predict_nt @[exu.scala 139:51] - i_alu.io.i0_ap.predict_t <= io.dec_exu.decode_exu.i0_ap.predict_t @[exu.scala 139:51] - i_alu.io.i0_ap.jal <= io.dec_exu.decode_exu.i0_ap.jal @[exu.scala 139:51] - i_alu.io.i0_ap.unsign <= io.dec_exu.decode_exu.i0_ap.unsign @[exu.scala 139:51] - i_alu.io.i0_ap.slt <= io.dec_exu.decode_exu.i0_ap.slt @[exu.scala 139:51] - i_alu.io.i0_ap.sub <= io.dec_exu.decode_exu.i0_ap.sub @[exu.scala 139:51] - i_alu.io.i0_ap.add <= io.dec_exu.decode_exu.i0_ap.add @[exu.scala 139:51] - i_alu.io.i0_ap.bge <= io.dec_exu.decode_exu.i0_ap.bge @[exu.scala 139:51] - i_alu.io.i0_ap.blt <= io.dec_exu.decode_exu.i0_ap.blt @[exu.scala 139:51] - i_alu.io.i0_ap.bne <= io.dec_exu.decode_exu.i0_ap.bne @[exu.scala 139:51] - i_alu.io.i0_ap.beq <= io.dec_exu.decode_exu.i0_ap.beq @[exu.scala 139:51] - i_alu.io.i0_ap.sra <= io.dec_exu.decode_exu.i0_ap.sra @[exu.scala 139:51] - i_alu.io.i0_ap.srl <= io.dec_exu.decode_exu.i0_ap.srl @[exu.scala 139:51] - i_alu.io.i0_ap.sll <= io.dec_exu.decode_exu.i0_ap.sll @[exu.scala 139:51] - i_alu.io.i0_ap.lxor <= io.dec_exu.decode_exu.i0_ap.lxor @[exu.scala 139:51] - i_alu.io.i0_ap.lor <= io.dec_exu.decode_exu.i0_ap.lor @[exu.scala 139:51] - i_alu.io.i0_ap.land <= io.dec_exu.decode_exu.i0_ap.land @[exu.scala 139:51] - i_alu.io.i0_ap.zba <= io.dec_exu.decode_exu.i0_ap.zba @[exu.scala 139:51] - i_alu.io.i0_ap.sh3add <= io.dec_exu.decode_exu.i0_ap.sh3add @[exu.scala 139:51] - i_alu.io.i0_ap.sh2add <= io.dec_exu.decode_exu.i0_ap.sh2add @[exu.scala 139:51] - i_alu.io.i0_ap.sh1add <= io.dec_exu.decode_exu.i0_ap.sh1add @[exu.scala 139:51] - i_alu.io.i0_ap.sbext <= io.dec_exu.decode_exu.i0_ap.sbext @[exu.scala 139:51] - i_alu.io.i0_ap.sbinv <= io.dec_exu.decode_exu.i0_ap.sbinv @[exu.scala 139:51] - i_alu.io.i0_ap.sbclr <= io.dec_exu.decode_exu.i0_ap.sbclr @[exu.scala 139:51] - i_alu.io.i0_ap.sbset <= io.dec_exu.decode_exu.i0_ap.sbset @[exu.scala 139:51] - i_alu.io.i0_ap.zbb <= io.dec_exu.decode_exu.i0_ap.zbb @[exu.scala 139:51] - i_alu.io.i0_ap.gorc <= io.dec_exu.decode_exu.i0_ap.gorc @[exu.scala 139:51] - i_alu.io.i0_ap.grev <= io.dec_exu.decode_exu.i0_ap.grev @[exu.scala 139:51] - i_alu.io.i0_ap.ror <= io.dec_exu.decode_exu.i0_ap.ror @[exu.scala 139:51] - i_alu.io.i0_ap.rol <= io.dec_exu.decode_exu.i0_ap.rol @[exu.scala 139:51] - i_alu.io.i0_ap.packh <= io.dec_exu.decode_exu.i0_ap.packh @[exu.scala 139:51] - i_alu.io.i0_ap.packu <= io.dec_exu.decode_exu.i0_ap.packu @[exu.scala 139:51] - i_alu.io.i0_ap.pack <= io.dec_exu.decode_exu.i0_ap.pack @[exu.scala 139:51] - i_alu.io.i0_ap.max <= io.dec_exu.decode_exu.i0_ap.max @[exu.scala 139:51] - i_alu.io.i0_ap.min <= io.dec_exu.decode_exu.i0_ap.min @[exu.scala 139:51] - i_alu.io.i0_ap.sro <= io.dec_exu.decode_exu.i0_ap.sro @[exu.scala 139:51] - i_alu.io.i0_ap.slo <= io.dec_exu.decode_exu.i0_ap.slo @[exu.scala 139:51] - i_alu.io.i0_ap.sext_h <= io.dec_exu.decode_exu.i0_ap.sext_h @[exu.scala 139:51] - i_alu.io.i0_ap.sext_b <= io.dec_exu.decode_exu.i0_ap.sext_b @[exu.scala 139:51] - i_alu.io.i0_ap.pcnt <= io.dec_exu.decode_exu.i0_ap.pcnt @[exu.scala 139:51] - i_alu.io.i0_ap.ctz <= io.dec_exu.decode_exu.i0_ap.ctz @[exu.scala 139:51] - i_alu.io.i0_ap.clz <= io.dec_exu.decode_exu.i0_ap.clz @[exu.scala 139:51] - i0_flush_upper_d <= i_alu.io.flush_upper_out @[exu.scala 141:35] - i0_flush_path_d <= i_alu.io.flush_path_out @[exu.scala 142:45] - io.exu_flush_final <= i_alu.io.flush_final_out @[exu.scala 143:27] - i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[exu.scala 144:45] - i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[exu.scala 144:45] - i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[exu.scala 144:45] - i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[exu.scala 144:45] - i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[exu.scala 144:45] - i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[exu.scala 144:45] - i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[exu.scala 144:45] - i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[exu.scala 144:45] - i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[exu.scala 144:45] - i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[exu.scala 144:45] - i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[exu.scala 144:45] - i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[exu.scala 144:45] - i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 144:45] - i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 144:45] - i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 145:27] - inst i_mul of exu_mul_ctl @[exu.scala 147:21] + io.dec_exu.dec_alu.exu_i0_pc_x <= i_alu.io.dec_alu.exu_i0_pc_x @[exu.scala 131:20] + i_alu.io.dec_alu.dec_i0_br_immed_d <= io.dec_exu.dec_alu.dec_i0_br_immed_d @[exu.scala 131:20] + i_alu.io.dec_alu.dec_csr_rddata_d <= io.dec_exu.dec_alu.dec_csr_rddata_d @[exu.scala 131:20] + i_alu.io.dec_alu.dec_csr_ren_d <= io.dec_exu.dec_alu.dec_csr_ren_d @[exu.scala 131:20] + i_alu.io.dec_alu.dec_i0_alu_decode_d <= io.dec_exu.dec_alu.dec_i0_alu_decode_d @[exu.scala 131:20] + i_alu.io.scan_mode <= io.scan_mode @[exu.scala 132:35] + i_alu.io.enable <= x_data_en @[exu.scala 133:45] + i_alu.io.pp_in.bits.prett <= i0_predict_newp_d.bits.prett @[exu.scala 134:45] + i_alu.io.pp_in.bits.pret <= i0_predict_newp_d.bits.pret @[exu.scala 134:45] + i_alu.io.pp_in.bits.way <= i0_predict_newp_d.bits.way @[exu.scala 134:45] + i_alu.io.pp_in.bits.pja <= i0_predict_newp_d.bits.pja @[exu.scala 134:45] + i_alu.io.pp_in.bits.pcall <= i0_predict_newp_d.bits.pcall @[exu.scala 134:45] + i_alu.io.pp_in.bits.br_start_error <= i0_predict_newp_d.bits.br_start_error @[exu.scala 134:45] + i_alu.io.pp_in.bits.br_error <= i0_predict_newp_d.bits.br_error @[exu.scala 134:45] + i_alu.io.pp_in.bits.toffset <= i0_predict_newp_d.bits.toffset @[exu.scala 134:45] + i_alu.io.pp_in.bits.hist <= i0_predict_newp_d.bits.hist @[exu.scala 134:45] + i_alu.io.pp_in.bits.pc4 <= i0_predict_newp_d.bits.pc4 @[exu.scala 134:45] + i_alu.io.pp_in.bits.boffset <= i0_predict_newp_d.bits.boffset @[exu.scala 134:45] + i_alu.io.pp_in.bits.ataken <= i0_predict_newp_d.bits.ataken @[exu.scala 134:45] + i_alu.io.pp_in.bits.misp <= i0_predict_newp_d.bits.misp @[exu.scala 134:45] + i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[exu.scala 134:45] + i_alu.io.flush_upper_x <= i0_flush_upper_x @[exu.scala 135:33] + i_alu.io.dec_tlu_flush_lower_r <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[exu.scala 136:41] + node _T_159 = asSInt(i0_rs1_d) @[exu.scala 137:50] + i_alu.io.a_in <= _T_159 @[exu.scala 137:39] + i_alu.io.b_in <= i0_rs2_d @[exu.scala 138:39] + i_alu.io.dec_i0_pc_d <= io.dec_exu.ib_exu.dec_i0_pc_d @[exu.scala 139:33] + i_alu.io.i0_ap.csr_imm <= io.dec_exu.decode_exu.i0_ap.csr_imm @[exu.scala 140:51] + i_alu.io.i0_ap.csr_write <= io.dec_exu.decode_exu.i0_ap.csr_write @[exu.scala 140:51] + i_alu.io.i0_ap.predict_nt <= io.dec_exu.decode_exu.i0_ap.predict_nt @[exu.scala 140:51] + i_alu.io.i0_ap.predict_t <= io.dec_exu.decode_exu.i0_ap.predict_t @[exu.scala 140:51] + i_alu.io.i0_ap.jal <= io.dec_exu.decode_exu.i0_ap.jal @[exu.scala 140:51] + i_alu.io.i0_ap.unsign <= io.dec_exu.decode_exu.i0_ap.unsign @[exu.scala 140:51] + i_alu.io.i0_ap.slt <= io.dec_exu.decode_exu.i0_ap.slt @[exu.scala 140:51] + i_alu.io.i0_ap.sub <= io.dec_exu.decode_exu.i0_ap.sub @[exu.scala 140:51] + i_alu.io.i0_ap.add <= io.dec_exu.decode_exu.i0_ap.add @[exu.scala 140:51] + i_alu.io.i0_ap.bge <= io.dec_exu.decode_exu.i0_ap.bge @[exu.scala 140:51] + i_alu.io.i0_ap.blt <= io.dec_exu.decode_exu.i0_ap.blt @[exu.scala 140:51] + i_alu.io.i0_ap.bne <= io.dec_exu.decode_exu.i0_ap.bne @[exu.scala 140:51] + i_alu.io.i0_ap.beq <= io.dec_exu.decode_exu.i0_ap.beq @[exu.scala 140:51] + i_alu.io.i0_ap.sra <= io.dec_exu.decode_exu.i0_ap.sra @[exu.scala 140:51] + i_alu.io.i0_ap.srl <= io.dec_exu.decode_exu.i0_ap.srl @[exu.scala 140:51] + i_alu.io.i0_ap.sll <= io.dec_exu.decode_exu.i0_ap.sll @[exu.scala 140:51] + i_alu.io.i0_ap.lxor <= io.dec_exu.decode_exu.i0_ap.lxor @[exu.scala 140:51] + i_alu.io.i0_ap.lor <= io.dec_exu.decode_exu.i0_ap.lor @[exu.scala 140:51] + i_alu.io.i0_ap.land <= io.dec_exu.decode_exu.i0_ap.land @[exu.scala 140:51] + i_alu.io.i0_ap.zba <= io.dec_exu.decode_exu.i0_ap.zba @[exu.scala 140:51] + i_alu.io.i0_ap.sh3add <= io.dec_exu.decode_exu.i0_ap.sh3add @[exu.scala 140:51] + i_alu.io.i0_ap.sh2add <= io.dec_exu.decode_exu.i0_ap.sh2add @[exu.scala 140:51] + i_alu.io.i0_ap.sh1add <= io.dec_exu.decode_exu.i0_ap.sh1add @[exu.scala 140:51] + i_alu.io.i0_ap.sbext <= io.dec_exu.decode_exu.i0_ap.sbext @[exu.scala 140:51] + i_alu.io.i0_ap.sbinv <= io.dec_exu.decode_exu.i0_ap.sbinv @[exu.scala 140:51] + i_alu.io.i0_ap.sbclr <= io.dec_exu.decode_exu.i0_ap.sbclr @[exu.scala 140:51] + i_alu.io.i0_ap.sbset <= io.dec_exu.decode_exu.i0_ap.sbset @[exu.scala 140:51] + i_alu.io.i0_ap.zbb <= io.dec_exu.decode_exu.i0_ap.zbb @[exu.scala 140:51] + i_alu.io.i0_ap.gorc <= io.dec_exu.decode_exu.i0_ap.gorc @[exu.scala 140:51] + i_alu.io.i0_ap.grev <= io.dec_exu.decode_exu.i0_ap.grev @[exu.scala 140:51] + i_alu.io.i0_ap.ror <= io.dec_exu.decode_exu.i0_ap.ror @[exu.scala 140:51] + i_alu.io.i0_ap.rol <= io.dec_exu.decode_exu.i0_ap.rol @[exu.scala 140:51] + i_alu.io.i0_ap.packh <= io.dec_exu.decode_exu.i0_ap.packh @[exu.scala 140:51] + i_alu.io.i0_ap.packu <= io.dec_exu.decode_exu.i0_ap.packu @[exu.scala 140:51] + i_alu.io.i0_ap.pack <= io.dec_exu.decode_exu.i0_ap.pack @[exu.scala 140:51] + i_alu.io.i0_ap.max <= io.dec_exu.decode_exu.i0_ap.max @[exu.scala 140:51] + i_alu.io.i0_ap.min <= io.dec_exu.decode_exu.i0_ap.min @[exu.scala 140:51] + i_alu.io.i0_ap.sro <= io.dec_exu.decode_exu.i0_ap.sro @[exu.scala 140:51] + i_alu.io.i0_ap.slo <= io.dec_exu.decode_exu.i0_ap.slo @[exu.scala 140:51] + i_alu.io.i0_ap.sext_h <= io.dec_exu.decode_exu.i0_ap.sext_h @[exu.scala 140:51] + i_alu.io.i0_ap.sext_b <= io.dec_exu.decode_exu.i0_ap.sext_b @[exu.scala 140:51] + i_alu.io.i0_ap.pcnt <= io.dec_exu.decode_exu.i0_ap.pcnt @[exu.scala 140:51] + i_alu.io.i0_ap.ctz <= io.dec_exu.decode_exu.i0_ap.ctz @[exu.scala 140:51] + i_alu.io.i0_ap.clz <= io.dec_exu.decode_exu.i0_ap.clz @[exu.scala 140:51] + i0_flush_upper_d <= i_alu.io.flush_upper_out @[exu.scala 142:35] + i0_flush_path_d <= i_alu.io.flush_path_out @[exu.scala 143:45] + io.exu_flush_final <= i_alu.io.flush_final_out @[exu.scala 144:27] + i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[exu.scala 145:45] + i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[exu.scala 145:45] + i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[exu.scala 145:45] + i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[exu.scala 145:45] + i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[exu.scala 145:45] + i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[exu.scala 145:45] + i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[exu.scala 145:45] + i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[exu.scala 145:45] + i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[exu.scala 145:45] + i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[exu.scala 145:45] + i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[exu.scala 145:45] + i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[exu.scala 145:45] + i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 145:45] + i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 145:45] + i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 146:27] + inst i_mul of exu_mul_ctl @[exu.scala 148:21] i_mul.clock <= clock i_mul.reset <= reset - i_mul.io.scan_mode <= io.scan_mode @[exu.scala 148:25] - node _T_160 = cat(io.dec_exu.decode_exu.mul_p.bits.crc32c_w, io.dec_exu.decode_exu.mul_p.bits.bfp) @[exu.scala 149:139] - node _T_161 = cat(io.dec_exu.decode_exu.mul_p.bits.crc32c_b, io.dec_exu.decode_exu.mul_p.bits.crc32c_h) @[exu.scala 149:139] - node _T_162 = cat(_T_161, _T_160) @[exu.scala 149:139] - node _T_163 = cat(io.dec_exu.decode_exu.mul_p.bits.crc32_h, io.dec_exu.decode_exu.mul_p.bits.crc32_w) @[exu.scala 149:139] - node _T_164 = cat(io.dec_exu.decode_exu.mul_p.bits.shfl, io.dec_exu.decode_exu.mul_p.bits.unshfl) @[exu.scala 149:139] - node _T_165 = cat(_T_164, io.dec_exu.decode_exu.mul_p.bits.crc32_b) @[exu.scala 149:139] - node _T_166 = cat(_T_165, _T_163) @[exu.scala 149:139] - node _T_167 = cat(_T_166, _T_162) @[exu.scala 149:139] - node _T_168 = cat(io.dec_exu.decode_exu.mul_p.bits.grev, io.dec_exu.decode_exu.mul_p.bits.gorc) @[exu.scala 149:139] - node _T_169 = cat(io.dec_exu.decode_exu.mul_p.bits.clmul, io.dec_exu.decode_exu.mul_p.bits.clmulh) @[exu.scala 149:139] - node _T_170 = cat(_T_169, io.dec_exu.decode_exu.mul_p.bits.clmulr) @[exu.scala 149:139] - node _T_171 = cat(_T_170, _T_168) @[exu.scala 149:139] - node _T_172 = cat(io.dec_exu.decode_exu.mul_p.bits.bext, io.dec_exu.decode_exu.mul_p.bits.bdep) @[exu.scala 149:139] - node _T_173 = cat(io.dec_exu.decode_exu.mul_p.bits.rs1_sign, io.dec_exu.decode_exu.mul_p.bits.rs2_sign) @[exu.scala 149:139] - node _T_174 = cat(_T_173, io.dec_exu.decode_exu.mul_p.bits.low) @[exu.scala 149:139] - node _T_175 = cat(_T_174, _T_172) @[exu.scala 149:139] - node _T_176 = cat(_T_175, _T_171) @[exu.scala 149:139] - node _T_177 = cat(_T_176, _T_167) @[exu.scala 149:139] - node _T_178 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] - node _T_179 = mux(_T_178, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_180 = and(_T_177, _T_179) @[exu.scala 149:146] - wire _T_181 : UInt<19>[1] @[exu.scala 149:92] - _T_181[0] <= _T_180 @[exu.scala 149:92] - wire _T_182 : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[exu.scala 149:242] - wire _T_183 : UInt<20> - _T_183 <= _T_181[0] - node _T_184 = bits(_T_183, 0, 0) @[exu.scala 149:242] - _T_182.bits.bfp <= _T_184 @[exu.scala 149:242] - node _T_185 = bits(_T_183, 1, 1) @[exu.scala 149:242] - _T_182.bits.crc32c_w <= _T_185 @[exu.scala 149:242] - node _T_186 = bits(_T_183, 2, 2) @[exu.scala 149:242] - _T_182.bits.crc32c_h <= _T_186 @[exu.scala 149:242] - node _T_187 = bits(_T_183, 3, 3) @[exu.scala 149:242] - _T_182.bits.crc32c_b <= _T_187 @[exu.scala 149:242] - node _T_188 = bits(_T_183, 4, 4) @[exu.scala 149:242] - _T_182.bits.crc32_w <= _T_188 @[exu.scala 149:242] - node _T_189 = bits(_T_183, 5, 5) @[exu.scala 149:242] - _T_182.bits.crc32_h <= _T_189 @[exu.scala 149:242] - node _T_190 = bits(_T_183, 6, 6) @[exu.scala 149:242] - _T_182.bits.crc32_b <= _T_190 @[exu.scala 149:242] - node _T_191 = bits(_T_183, 7, 7) @[exu.scala 149:242] - _T_182.bits.unshfl <= _T_191 @[exu.scala 149:242] - node _T_192 = bits(_T_183, 8, 8) @[exu.scala 149:242] - _T_182.bits.shfl <= _T_192 @[exu.scala 149:242] - node _T_193 = bits(_T_183, 9, 9) @[exu.scala 149:242] - _T_182.bits.gorc <= _T_193 @[exu.scala 149:242] - node _T_194 = bits(_T_183, 10, 10) @[exu.scala 149:242] - _T_182.bits.grev <= _T_194 @[exu.scala 149:242] - node _T_195 = bits(_T_183, 11, 11) @[exu.scala 149:242] - _T_182.bits.clmulr <= _T_195 @[exu.scala 149:242] - node _T_196 = bits(_T_183, 12, 12) @[exu.scala 149:242] - _T_182.bits.clmulh <= _T_196 @[exu.scala 149:242] - node _T_197 = bits(_T_183, 13, 13) @[exu.scala 149:242] - _T_182.bits.clmul <= _T_197 @[exu.scala 149:242] - node _T_198 = bits(_T_183, 14, 14) @[exu.scala 149:242] - _T_182.bits.bdep <= _T_198 @[exu.scala 149:242] - node _T_199 = bits(_T_183, 15, 15) @[exu.scala 149:242] - _T_182.bits.bext <= _T_199 @[exu.scala 149:242] - node _T_200 = bits(_T_183, 16, 16) @[exu.scala 149:242] - _T_182.bits.low <= _T_200 @[exu.scala 149:242] - node _T_201 = bits(_T_183, 17, 17) @[exu.scala 149:242] - _T_182.bits.rs2_sign <= _T_201 @[exu.scala 149:242] - node _T_202 = bits(_T_183, 18, 18) @[exu.scala 149:242] - _T_182.bits.rs1_sign <= _T_202 @[exu.scala 149:242] - node _T_203 = bits(_T_183, 19, 19) @[exu.scala 149:242] - _T_182.valid <= _T_203 @[exu.scala 149:242] - i_mul.io.mul_p.bits.bfp <= _T_182.bits.bfp @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32c_w <= _T_182.bits.crc32c_w @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32c_h <= _T_182.bits.crc32c_h @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32c_b <= _T_182.bits.crc32c_b @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32_w <= _T_182.bits.crc32_w @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32_h <= _T_182.bits.crc32_h @[exu.scala 149:25] - i_mul.io.mul_p.bits.crc32_b <= _T_182.bits.crc32_b @[exu.scala 149:25] - i_mul.io.mul_p.bits.unshfl <= _T_182.bits.unshfl @[exu.scala 149:25] - i_mul.io.mul_p.bits.shfl <= _T_182.bits.shfl @[exu.scala 149:25] - i_mul.io.mul_p.bits.gorc <= _T_182.bits.gorc @[exu.scala 149:25] - i_mul.io.mul_p.bits.grev <= _T_182.bits.grev @[exu.scala 149:25] - i_mul.io.mul_p.bits.clmulr <= _T_182.bits.clmulr @[exu.scala 149:25] - i_mul.io.mul_p.bits.clmulh <= _T_182.bits.clmulh @[exu.scala 149:25] - i_mul.io.mul_p.bits.clmul <= _T_182.bits.clmul @[exu.scala 149:25] - i_mul.io.mul_p.bits.bdep <= _T_182.bits.bdep @[exu.scala 149:25] - i_mul.io.mul_p.bits.bext <= _T_182.bits.bext @[exu.scala 149:25] - i_mul.io.mul_p.bits.low <= _T_182.bits.low @[exu.scala 149:25] - i_mul.io.mul_p.bits.rs2_sign <= _T_182.bits.rs2_sign @[exu.scala 149:25] - i_mul.io.mul_p.bits.rs1_sign <= _T_182.bits.rs1_sign @[exu.scala 149:25] - i_mul.io.mul_p.valid <= _T_182.valid @[exu.scala 149:25] - node _T_204 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] - node _T_205 = mux(_T_204, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_206 = and(muldiv_rs1_d, _T_205) @[exu.scala 150:57] - i_mul.io.rs1_in <= _T_206 @[exu.scala 150:41] - node _T_207 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] - node _T_208 = mux(_T_207, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_209 = and(i0_rs2_d, _T_208) @[exu.scala 151:54] - i_mul.io.rs2_in <= _T_209 @[exu.scala 151:41] - inst i_div of exu_div_ctl @[exu.scala 154:21] + i_mul.io.scan_mode <= io.scan_mode @[exu.scala 149:25] + i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 150:18] + i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 150:18] + i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 150:18] + i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 150:18] + i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 150:18] + i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 150:18] + i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 150:18] + i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 150:18] + i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 150:18] + i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 150:18] + i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 150:18] + i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 150:18] + i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 150:18] + i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 150:18] + i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 150:18] + node _T_160 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] + node _T_161 = mux(_T_160, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_162 = and(muldiv_rs1_d, _T_161) @[exu.scala 152:57] + i_mul.io.rs1_in <= _T_162 @[exu.scala 152:41] + node _T_163 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] + node _T_164 = mux(_T_163, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_165 = and(i0_rs2_d, _T_164) @[exu.scala 153:54] + i_mul.io.rs2_in <= _T_165 @[exu.scala 153:41] + inst i_div of exu_div_ctl @[exu.scala 156:21] i_div.clock <= clock i_div.reset <= reset - i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 155:20] - i_div.io.dec_div.div_p.bits.rem <= io.dec_exu.dec_div.div_p.bits.rem @[exu.scala 155:20] - i_div.io.dec_div.div_p.bits.unsign <= io.dec_exu.dec_div.div_p.bits.unsign @[exu.scala 155:20] - i_div.io.dec_div.div_p.valid <= io.dec_exu.dec_div.div_p.valid @[exu.scala 155:20] - i_div.io.scan_mode <= io.scan_mode @[exu.scala 156:25] - i_div.io.dividend <= muldiv_rs1_d @[exu.scala 157:33] - i_div.io.divisor <= i0_rs2_d @[exu.scala 158:33] - io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 159:41] - io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 160:33] - node _T_210 = bits(mul_valid_x, 0, 0) @[exu.scala 162:76] - node _T_211 = mux(_T_210, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 162:63] - io.dec_exu.decode_exu.exu_i0_result_x <= _T_211 @[exu.scala 162:57] - i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 163:47] - i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 163:47] - i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 163:47] - i0_predict_newp_d.bits.pja <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[exu.scala 163:47] - i0_predict_newp_d.bits.pcall <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[exu.scala 163:47] - i0_predict_newp_d.bits.br_start_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[exu.scala 163:47] - i0_predict_newp_d.bits.br_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[exu.scala 163:47] - i0_predict_newp_d.bits.toffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[exu.scala 163:47] - i0_predict_newp_d.bits.hist <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[exu.scala 163:47] - i0_predict_newp_d.bits.pc4 <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[exu.scala 163:47] - i0_predict_newp_d.bits.boffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[exu.scala 163:47] - i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 163:47] - i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 163:47] - i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 163:47] - node _T_212 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 164:80] - i0_predict_newp_d.bits.boffset <= _T_212 @[exu.scala 164:47] - io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 166:47] - io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 167:47] - io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 168:47] - node _T_213 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 171:54] - node _T_214 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 171:97] - node _T_215 = and(_T_213, _T_214) @[exu.scala 171:95] - i0_valid_d <= _T_215 @[exu.scala 171:28] - node _T_216 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 172:59] - i0_taken_d <= _T_216 @[exu.scala 172:28] - node _T_217 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 178:8] - node _T_218 = and(_T_217, i0_valid_d) @[exu.scala 178:50] - node _T_219 = bits(_T_218, 0, 0) @[exu.scala 178:64] - node _T_220 = bits(ghr_d, 6, 0) @[exu.scala 178:85] - node _T_221 = cat(_T_220, i0_taken_d) @[Cat.scala 29:58] - node _T_222 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 179:8] - node _T_223 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 179:52] - node _T_224 = and(_T_222, _T_223) @[exu.scala 179:50] - node _T_225 = bits(_T_224, 0, 0) @[exu.scala 179:65] - node _T_226 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 180:50] - node _T_227 = mux(_T_219, _T_221, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_228 = mux(_T_225, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_229 = mux(_T_226, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_230 = or(_T_227, _T_228) @[Mux.scala 27:72] - node _T_231 = or(_T_230, _T_229) @[Mux.scala 27:72] - wire _T_232 : UInt @[Mux.scala 27:72] - _T_232 <= _T_231 @[Mux.scala 27:72] - ghr_d_ns <= _T_232 @[exu.scala 177:14] - node _T_233 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 184:32] - node _T_234 = bits(ghr_x, 6, 0) @[exu.scala 184:50] - node _T_235 = cat(_T_234, i0_taken_x) @[Cat.scala 29:58] - node _T_236 = mux(_T_233, _T_235, ghr_x) @[exu.scala 184:20] - ghr_x_ns <= _T_236 @[exu.scala 184:14] - io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 186:43] - io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 187:43] - io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 188:43] - node _T_237 = bits(i0_pp_r.valid, 0, 0) @[Bitwise.scala 72:15] - node _T_238 = mux(_T_237, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_239 = and(_T_238, i0_pp_r.bits.hist) @[exu.scala 189:69] - io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_239 @[exu.scala 189:43] - io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 190:43] - node _T_240 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 191:63] - io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_240 @[exu.scala 191:43] - io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 192:48] - node _T_241 = bits(predpipe_r, 20, 13) @[exu.scala 193:56] - io.exu_bp.exu_i0_br_fghr_r <= _T_241 @[exu.scala 193:43] - node _T_242 = bits(predpipe_r, 12, 5) @[exu.scala 194:56] - io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_242 @[exu.scala 194:43] - io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 195:43] - node _T_243 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 196:67] - wire _T_244 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 196:104] - _T_244.bits.prett <= UInt<31>("h00") @[exu.scala 196:104] - _T_244.bits.pret <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.way <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.pja <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.pcall <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.br_start_error <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.br_error <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.toffset <= UInt<12>("h00") @[exu.scala 196:104] - _T_244.bits.hist <= UInt<2>("h00") @[exu.scala 196:104] - _T_244.bits.pc4 <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.boffset <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.ataken <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.bits.misp <= UInt<1>("h00") @[exu.scala 196:104] - _T_244.valid <= UInt<1>("h00") @[exu.scala 196:104] - node _T_245 = mux(_T_243, i0_predict_p_x, _T_244) @[exu.scala 196:49] - final_predict_mp.bits.prett <= _T_245.bits.prett @[exu.scala 196:43] - final_predict_mp.bits.pret <= _T_245.bits.pret @[exu.scala 196:43] - final_predict_mp.bits.way <= _T_245.bits.way @[exu.scala 196:43] - final_predict_mp.bits.pja <= _T_245.bits.pja @[exu.scala 196:43] - final_predict_mp.bits.pcall <= _T_245.bits.pcall @[exu.scala 196:43] - final_predict_mp.bits.br_start_error <= _T_245.bits.br_start_error @[exu.scala 196:43] - final_predict_mp.bits.br_error <= _T_245.bits.br_error @[exu.scala 196:43] - final_predict_mp.bits.toffset <= _T_245.bits.toffset @[exu.scala 196:43] - final_predict_mp.bits.hist <= _T_245.bits.hist @[exu.scala 196:43] - final_predict_mp.bits.pc4 <= _T_245.bits.pc4 @[exu.scala 196:43] - final_predict_mp.bits.boffset <= _T_245.bits.boffset @[exu.scala 196:43] - final_predict_mp.bits.ataken <= _T_245.bits.ataken @[exu.scala 196:43] - final_predict_mp.bits.misp <= _T_245.bits.misp @[exu.scala 196:43] - final_predict_mp.valid <= _T_245.valid @[exu.scala 196:43] - node _T_246 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 197:66] - node final_predpipe_mp = mux(_T_246, predpipe_x, UInt<1>("h00")) @[exu.scala 197:48] - node _T_247 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:67] - node _T_248 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 199:120] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[exu.scala 199:77] - node _T_250 = and(_T_247, _T_249) @[exu.scala 199:75] - node after_flush_eghr = mux(_T_250, ghr_d, ghr_x) @[exu.scala 199:48] - io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 201:39] - io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 202:39] - io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 203:39] - io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 204:39] - io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 205:39] - io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 206:39] - io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 207:39] - io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 208:39] - io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 209:39] - node _T_251 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 210:68] - io.exu_bp.exu_mp_pkt.bits.hist <= _T_251 @[exu.scala 210:39] - node _T_252 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 211:71] - io.exu_bp.exu_mp_pkt.bits.toffset <= _T_252 @[exu.scala 211:39] - io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 212:39] - node _T_253 = bits(final_predpipe_mp, 12, 5) @[exu.scala 213:59] - io.exu_bp.exu_mp_index <= _T_253 @[exu.scala 213:39] - node _T_254 = bits(final_predpipe_mp, 4, 0) @[exu.scala 214:59] - io.exu_bp.exu_mp_btag <= _T_254 @[exu.scala 214:39] - node _T_255 = bits(final_predpipe_mp, 20, 13) @[exu.scala 215:59] - io.exu_bp.exu_mp_eghr <= _T_255 @[exu.scala 215:39] - node _T_256 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 237:46] - node _T_257 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 238:6] - node _T_258 = and(_T_257, i0_flush_upper_d) @[exu.scala 238:48] - node _T_259 = bits(_T_258, 0, 0) @[exu.scala 238:68] - node _T_260 = mux(_T_256, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_261 = mux(_T_259, i0_flush_path_d, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_262 = or(_T_260, _T_261) @[Mux.scala 27:72] - wire _T_263 : UInt<31> @[Mux.scala 27:72] - _T_263 <= _T_262 @[Mux.scala 27:72] - io.exu_flush_path_final <= _T_263 @[exu.scala 236:33] - node _T_264 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 240:79] - node _T_265 = mux(_T_264, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 240:55] - io.dec_exu.tlu_exu.exu_npc_r <= _T_265 @[exu.scala 240:49] + i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 157:20] + i_div.io.dec_div.div_p.bits.rem <= io.dec_exu.dec_div.div_p.bits.rem @[exu.scala 157:20] + i_div.io.dec_div.div_p.bits.unsign <= io.dec_exu.dec_div.div_p.bits.unsign @[exu.scala 157:20] + i_div.io.dec_div.div_p.valid <= io.dec_exu.dec_div.div_p.valid @[exu.scala 157:20] + i_div.io.scan_mode <= io.scan_mode @[exu.scala 158:25] + i_div.io.dividend <= muldiv_rs1_d @[exu.scala 159:33] + i_div.io.divisor <= i0_rs2_d @[exu.scala 160:33] + io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 161:41] + io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 162:33] + node _T_166 = bits(mul_valid_x, 0, 0) @[exu.scala 164:76] + node _T_167 = mux(_T_166, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 164:63] + io.dec_exu.decode_exu.exu_i0_result_x <= _T_167 @[exu.scala 164:57] + i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 165:47] + i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 165:47] + i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 165:47] + i0_predict_newp_d.bits.pja <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[exu.scala 165:47] + i0_predict_newp_d.bits.pcall <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[exu.scala 165:47] + i0_predict_newp_d.bits.br_start_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[exu.scala 165:47] + i0_predict_newp_d.bits.br_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[exu.scala 165:47] + i0_predict_newp_d.bits.toffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[exu.scala 165:47] + i0_predict_newp_d.bits.hist <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[exu.scala 165:47] + i0_predict_newp_d.bits.pc4 <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[exu.scala 165:47] + i0_predict_newp_d.bits.boffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[exu.scala 165:47] + i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 165:47] + i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 165:47] + i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 165:47] + node _T_168 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 166:80] + i0_predict_newp_d.bits.boffset <= _T_168 @[exu.scala 166:47] + io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 168:47] + io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 169:47] + io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 170:47] + node _T_169 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 173:54] + node _T_170 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 173:97] + node _T_171 = and(_T_169, _T_170) @[exu.scala 173:95] + i0_valid_d <= _T_171 @[exu.scala 173:28] + node _T_172 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 174:59] + i0_taken_d <= _T_172 @[exu.scala 174:28] + node _T_173 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 180:8] + node _T_174 = and(_T_173, i0_valid_d) @[exu.scala 180:50] + node _T_175 = bits(_T_174, 0, 0) @[exu.scala 180:64] + node _T_176 = bits(ghr_d, 6, 0) @[exu.scala 180:85] + node _T_177 = cat(_T_176, i0_taken_d) @[Cat.scala 29:58] + node _T_178 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 181:8] + node _T_179 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 181:52] + node _T_180 = and(_T_178, _T_179) @[exu.scala 181:50] + node _T_181 = bits(_T_180, 0, 0) @[exu.scala 181:65] + node _T_182 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 182:50] + node _T_183 = mux(_T_175, _T_177, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_184 = mux(_T_181, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_185 = mux(_T_182, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_186 = or(_T_183, _T_184) @[Mux.scala 27:72] + node _T_187 = or(_T_186, _T_185) @[Mux.scala 27:72] + wire _T_188 : UInt @[Mux.scala 27:72] + _T_188 <= _T_187 @[Mux.scala 27:72] + ghr_d_ns <= _T_188 @[exu.scala 179:14] + node _T_189 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 186:32] + node _T_190 = bits(ghr_x, 6, 0) @[exu.scala 186:50] + node _T_191 = cat(_T_190, i0_taken_x) @[Cat.scala 29:58] + node _T_192 = mux(_T_189, _T_191, ghr_x) @[exu.scala 186:20] + ghr_x_ns <= _T_192 @[exu.scala 186:14] + io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 188:43] + io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 189:43] + io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 190:43] + node _T_193 = bits(i0_pp_r.valid, 0, 0) @[Bitwise.scala 72:15] + node _T_194 = mux(_T_193, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_195 = and(_T_194, i0_pp_r.bits.hist) @[exu.scala 191:69] + io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_195 @[exu.scala 191:43] + io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 192:43] + node _T_196 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 193:63] + io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_196 @[exu.scala 193:43] + io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 194:48] + node _T_197 = bits(predpipe_r, 20, 13) @[exu.scala 195:56] + io.exu_bp.exu_i0_br_fghr_r <= _T_197 @[exu.scala 195:43] + node _T_198 = bits(predpipe_r, 12, 5) @[exu.scala 196:56] + io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_198 @[exu.scala 196:43] + io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 197:43] + node _T_199 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 198:67] + wire _T_200 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 198:104] + _T_200.bits.prett <= UInt<31>("h00") @[exu.scala 198:104] + _T_200.bits.pret <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.way <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.pja <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.pcall <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.br_start_error <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.br_error <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.toffset <= UInt<12>("h00") @[exu.scala 198:104] + _T_200.bits.hist <= UInt<2>("h00") @[exu.scala 198:104] + _T_200.bits.pc4 <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.boffset <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.ataken <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.bits.misp <= UInt<1>("h00") @[exu.scala 198:104] + _T_200.valid <= UInt<1>("h00") @[exu.scala 198:104] + node _T_201 = mux(_T_199, i0_predict_p_x, _T_200) @[exu.scala 198:49] + final_predict_mp.bits.prett <= _T_201.bits.prett @[exu.scala 198:43] + final_predict_mp.bits.pret <= _T_201.bits.pret @[exu.scala 198:43] + final_predict_mp.bits.way <= _T_201.bits.way @[exu.scala 198:43] + final_predict_mp.bits.pja <= _T_201.bits.pja @[exu.scala 198:43] + final_predict_mp.bits.pcall <= _T_201.bits.pcall @[exu.scala 198:43] + final_predict_mp.bits.br_start_error <= _T_201.bits.br_start_error @[exu.scala 198:43] + final_predict_mp.bits.br_error <= _T_201.bits.br_error @[exu.scala 198:43] + final_predict_mp.bits.toffset <= _T_201.bits.toffset @[exu.scala 198:43] + final_predict_mp.bits.hist <= _T_201.bits.hist @[exu.scala 198:43] + final_predict_mp.bits.pc4 <= _T_201.bits.pc4 @[exu.scala 198:43] + final_predict_mp.bits.boffset <= _T_201.bits.boffset @[exu.scala 198:43] + final_predict_mp.bits.ataken <= _T_201.bits.ataken @[exu.scala 198:43] + final_predict_mp.bits.misp <= _T_201.bits.misp @[exu.scala 198:43] + final_predict_mp.valid <= _T_201.valid @[exu.scala 198:43] + node _T_202 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:66] + node final_predpipe_mp = mux(_T_202, predpipe_x, UInt<1>("h00")) @[exu.scala 199:48] + node _T_203 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 201:67] + node _T_204 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 201:120] + node _T_205 = eq(_T_204, UInt<1>("h00")) @[exu.scala 201:77] + node _T_206 = and(_T_203, _T_205) @[exu.scala 201:75] + node after_flush_eghr = mux(_T_206, ghr_d, ghr_x) @[exu.scala 201:48] + io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 203:39] + io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 204:39] + io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 205:39] + io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 206:39] + io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 207:39] + io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 208:39] + io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 209:39] + io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 210:39] + io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 211:39] + node _T_207 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 212:68] + io.exu_bp.exu_mp_pkt.bits.hist <= _T_207 @[exu.scala 212:39] + node _T_208 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 213:71] + io.exu_bp.exu_mp_pkt.bits.toffset <= _T_208 @[exu.scala 213:39] + io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 214:39] + node _T_209 = bits(final_predpipe_mp, 12, 5) @[exu.scala 215:59] + io.exu_bp.exu_mp_index <= _T_209 @[exu.scala 215:39] + node _T_210 = bits(final_predpipe_mp, 4, 0) @[exu.scala 216:59] + io.exu_bp.exu_mp_btag <= _T_210 @[exu.scala 216:39] + node _T_211 = bits(final_predpipe_mp, 20, 13) @[exu.scala 217:59] + io.exu_bp.exu_mp_eghr <= _T_211 @[exu.scala 217:39] + node _T_212 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 239:46] + node _T_213 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 240:6] + node _T_214 = and(_T_213, i0_flush_upper_d) @[exu.scala 240:48] + node _T_215 = bits(_T_214, 0, 0) @[exu.scala 240:68] + node _T_216 = mux(_T_212, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_217 = mux(_T_215, i0_flush_path_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72] + wire _T_219 : UInt<31> @[Mux.scala 27:72] + _T_219 <= _T_218 @[Mux.scala 27:72] + io.exu_flush_path_final <= _T_219 @[exu.scala 238:33] + node _T_220 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 242:79] + node _T_221 = mux(_T_220, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 242:55] + io.dec_exu.tlu_exu.exu_npc_r <= _T_221 @[exu.scala 242:49] diff --git a/exu.v b/exu.v index 6d709859..f8ec13ee 100644 --- a/exu.v +++ b/exu.v @@ -2160,117 +2160,117 @@ module exu( wire rvclkhdr_6_io_en; // @[lib.scala 404:23] wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] wire rvclkhdr_7_io_en; // @[lib.scala 404:23] - wire i_alu_clock; // @[exu.scala 129:19] - wire i_alu_reset; // @[exu.scala 129:19] - wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 129:19] - wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 129:19] - wire [31:0] i_alu_io_dec_alu_dec_csr_rddata_d; // @[exu.scala 129:19] - wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 129:19] - wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 129:19] - wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 129:19] - wire i_alu_io_flush_upper_x; // @[exu.scala 129:19] - wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 129:19] - wire i_alu_io_enable; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_clz; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_ctz; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_pcnt; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sext_b; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sext_h; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_min; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_max; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_pack; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_packu; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_packh; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_rol; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_ror; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_grev; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_gorc; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_zbb; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sbset; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sbclr; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sbinv; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sbext; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_land; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_lor; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_lxor; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sll; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_srl; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sra; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_beq; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_bne; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_blt; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_bge; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_add; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_sub; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_slt; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_unsign; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_jal; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_predict_t; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_csr_write; // @[exu.scala 129:19] - wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 129:19] - wire [31:0] i_alu_io_a_in; // @[exu.scala 129:19] - wire [31:0] i_alu_io_b_in; // @[exu.scala 129:19] - wire i_alu_io_pp_in_valid; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 129:19] - wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 129:19] - wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_pja; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_way; // @[exu.scala 129:19] - wire i_alu_io_pp_in_bits_pret; // @[exu.scala 129:19] - wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 129:19] - wire [31:0] i_alu_io_result_ff; // @[exu.scala 129:19] - wire i_alu_io_flush_upper_out; // @[exu.scala 129:19] - wire i_alu_io_flush_final_out; // @[exu.scala 129:19] - wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 129:19] - wire i_alu_io_pred_correct_out; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_valid; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 129:19] - wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 129:19] - wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 129:19] - wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 129:19] - wire i_mul_clock; // @[exu.scala 147:21] - wire i_mul_reset; // @[exu.scala 147:21] - wire i_mul_io_mul_p_valid; // @[exu.scala 147:21] - wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 147:21] - wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 147:21] - wire i_mul_io_mul_p_bits_low; // @[exu.scala 147:21] - wire [31:0] i_mul_io_rs1_in; // @[exu.scala 147:21] - wire [31:0] i_mul_io_rs2_in; // @[exu.scala 147:21] - wire [31:0] i_mul_io_result_x; // @[exu.scala 147:21] - wire i_div_clock; // @[exu.scala 154:21] - wire i_div_reset; // @[exu.scala 154:21] - wire [31:0] i_div_io_dividend; // @[exu.scala 154:21] - wire [31:0] i_div_io_divisor; // @[exu.scala 154:21] - wire [31:0] i_div_io_exu_div_result; // @[exu.scala 154:21] - wire i_div_io_exu_div_wren; // @[exu.scala 154:21] - wire i_div_io_dec_div_div_p_valid; // @[exu.scala 154:21] - wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 154:21] - wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 154:21] - wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 154:21] - wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 54:69] - wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 55:73] - wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 56:73] - wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 57:69] + wire i_alu_clock; // @[exu.scala 130:19] + wire i_alu_reset; // @[exu.scala 130:19] + wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:19] + wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 130:19] + wire [31:0] i_alu_io_dec_alu_dec_csr_rddata_d; // @[exu.scala 130:19] + wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:19] + wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:19] + wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 130:19] + wire i_alu_io_flush_upper_x; // @[exu.scala 130:19] + wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 130:19] + wire i_alu_io_enable; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_clz; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_ctz; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_pcnt; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sext_b; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sext_h; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_min; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_max; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_pack; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_packu; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_packh; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_rol; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_ror; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_grev; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_gorc; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_zbb; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sbset; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sbclr; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sbinv; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sbext; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_land; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_lor; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_lxor; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sll; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_srl; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sra; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_beq; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_bne; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_blt; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_bge; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_add; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_sub; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_slt; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_unsign; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_jal; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_predict_t; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_csr_write; // @[exu.scala 130:19] + wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 130:19] + wire [31:0] i_alu_io_a_in; // @[exu.scala 130:19] + wire [31:0] i_alu_io_b_in; // @[exu.scala 130:19] + wire i_alu_io_pp_in_valid; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 130:19] + wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 130:19] + wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_pja; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_way; // @[exu.scala 130:19] + wire i_alu_io_pp_in_bits_pret; // @[exu.scala 130:19] + wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 130:19] + wire [31:0] i_alu_io_result_ff; // @[exu.scala 130:19] + wire i_alu_io_flush_upper_out; // @[exu.scala 130:19] + wire i_alu_io_flush_final_out; // @[exu.scala 130:19] + wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 130:19] + wire i_alu_io_pred_correct_out; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_valid; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 130:19] + wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 130:19] + wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 130:19] + wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 130:19] + wire i_mul_clock; // @[exu.scala 148:21] + wire i_mul_reset; // @[exu.scala 148:21] + wire i_mul_io_mul_p_valid; // @[exu.scala 148:21] + wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 148:21] + wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 148:21] + wire i_mul_io_mul_p_bits_low; // @[exu.scala 148:21] + wire [31:0] i_mul_io_rs1_in; // @[exu.scala 148:21] + wire [31:0] i_mul_io_rs2_in; // @[exu.scala 148:21] + wire [31:0] i_mul_io_result_x; // @[exu.scala 148:21] + wire i_div_clock; // @[exu.scala 156:21] + wire i_div_reset; // @[exu.scala 156:21] + wire [31:0] i_div_io_dividend; // @[exu.scala 156:21] + wire [31:0] i_div_io_divisor; // @[exu.scala 156:21] + wire [31:0] i_div_io_exu_div_result; // @[exu.scala 156:21] + wire i_div_io_exu_div_wren; // @[exu.scala 156:21] + wire i_div_io_dec_div_div_p_valid; // @[exu.scala 156:21] + wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 156:21] + wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 156:21] + wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 156:21] + wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 55:69] + wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 56:73] + wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 57:73] + wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 58:69] reg i0_branch_x; // @[Reg.scala 27:20] - wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 58:73] - wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 59:68] - wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 60:68] + wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 59:73] + wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 60:68] + wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 61:68] wire [20:0] predpipe_d = {io_dec_exu_decode_exu_i0_predict_fghr_d,io_dec_exu_decode_exu_i0_predict_index_d,io_dec_exu_decode_exu_i0_predict_btag_d}; // @[Cat.scala 29:58] reg [30:0] i0_flush_path_x; // @[Reg.scala 27:20] - wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 41:53 exu.scala 142:45] + wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 41:53 exu.scala 143:45] reg i0_predict_p_x_valid; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_misp; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_ataken; // @[Reg.scala 27:20] @@ -2284,33 +2284,33 @@ module exu( reg i0_predict_p_x_bits_pja; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_way; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_pret; // @[Reg.scala 27:20] - wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 42:53 exu.scala 144:45] - wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 42:53 exu.scala 144:45] - wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 42:53 exu.scala 144:45] - wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 42:53 exu.scala 144:45] + wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 42:53 exu.scala 145:45] + wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 42:53 exu.scala 145:45] + wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 42:53 exu.scala 145:45] reg [20:0] predpipe_x; // @[Reg.scala 27:20] reg [20:0] predpipe_r; // @[Reg.scala 27:20] reg [7:0] ghr_x; // @[Reg.scala 27:20] reg i0_valid_x; // @[Reg.scala 27:20] reg i0_taken_x; // @[Reg.scala 27:20] - wire [7:0] _T_235 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58] + wire [7:0] _T_191 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58] reg i0_pred_correct_upper_x; // @[Reg.scala 27:20] - wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 47:41 exu.scala 145:27] + wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 47:41 exu.scala 146:27] reg i0_flush_upper_x; // @[Reg.scala 27:20] - wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 48:45 exu.scala 141:35] - wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 172:59] - wire _T_213 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 171:54] - wire _T_214 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 171:97] - wire i0_valid_d = _T_213 & _T_214; // @[exu.scala 171:95] + wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 48:45 exu.scala 142:35] + wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 174:59] + wire _T_169 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 173:54] + wire _T_170 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 173:97] + wire i0_valid_d = _T_169 & _T_170; // @[exu.scala 173:95] reg i0_pp_r_valid; // @[Reg.scala 27:20] reg i0_pp_r_bits_misp; // @[Reg.scala 27:20] reg i0_pp_r_bits_ataken; // @[Reg.scala 27:20] @@ -2325,16 +2325,16 @@ module exu( reg [30:0] i0_flush_path_upper_r; // @[Reg.scala 27:20] reg [24:0] pred_temp2; // @[Reg.scala 27:20] wire [30:0] _T_31 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58] - wire _T_218 = _T_214 & i0_valid_d; // @[exu.scala 178:50] + wire _T_174 = _T_170 & i0_valid_d; // @[exu.scala 180:50] reg [7:0] ghr_d; // @[Reg.scala 27:20] - wire [7:0] _T_221 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58] - wire [7:0] _T_227 = _T_218 ? _T_221 : 8'h0; // @[Mux.scala 27:72] - wire _T_223 = ~i0_valid_d; // @[exu.scala 179:52] - wire _T_224 = _T_214 & _T_223; // @[exu.scala 179:50] - wire [7:0] _T_228 = _T_224 ? ghr_d : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_230 = _T_227 | _T_228; // @[Mux.scala 27:72] - wire [7:0] _T_229 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] - wire [7:0] ghr_d_ns = _T_230 | _T_229; // @[Mux.scala 27:72] + wire [7:0] _T_177 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58] + wire [7:0] _T_183 = _T_174 ? _T_177 : 8'h0; // @[Mux.scala 27:72] + wire _T_179 = ~i0_valid_d; // @[exu.scala 181:52] + wire _T_180 = _T_170 & _T_179; // @[exu.scala 181:50] + wire [7:0] _T_184 = _T_180 ? ghr_d : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_186 = _T_183 | _T_184; // @[Mux.scala 27:72] + wire [7:0] _T_185 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] + wire [7:0] ghr_d_ns = _T_186 | _T_185; // @[Mux.scala 27:72] wire [7:0] _T_33 = ghr_d_ns ^ ghr_d; // @[lib.scala 448:21] wire _T_34 = |_T_33; // @[lib.scala 448:29] reg mul_valid_x; // @[Reg.scala 27:20] @@ -2342,12 +2342,12 @@ module exu( wire _T_38 = |_T_37; // @[lib.scala 470:29] wire _T_41 = io_dec_exu_decode_exu_dec_i0_branch_d ^ i0_branch_x; // @[lib.scala 448:21] wire _T_42 = |_T_41; // @[lib.scala 448:29] - wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 82:84] - wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 82:134] - wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 82:184] - wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 83:84] - wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 83:134] - wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 83:184] + wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 83:84] + wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 83:134] + wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 83:184] + wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 84:84] + wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 84:134] + wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 84:184] wire [31:0] _T_64 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] ? io_dec_exu_decode_exu_dec_i0_result_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_65 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1] ? io_lsu_exu_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_66 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2] ? io_dec_exu_decode_exu_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] @@ -2362,13 +2362,13 @@ module exu( wire [31:0] _T_83 = _T_79 | _T_80; // @[Mux.scala 27:72] wire [31:0] _T_84 = _T_83 | _T_81; // @[Mux.scala 27:72] wire [31:0] i0_rs2_bypass_data_d = _T_84 | _T_82; // @[Mux.scala 27:72] - wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 100:6] - wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 100:26] + wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 101:6] + wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 101:26] wire [31:0] _T_90 = {io_dec_exu_ib_exu_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58] - wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 101:26] - wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:28] - wire _T_96 = _T_87 & _T_95; // @[exu.scala 102:26] - wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 102:69] + wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:26] + wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 103:28] + wire _T_96 = _T_87 & _T_95; // @[exu.scala 103:26] + wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 103:69] wire [31:0] _T_99 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_100 = _T_88 ? _T_90 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_101 = _T_92 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72] @@ -2377,51 +2377,45 @@ module exu( wire [31:0] _T_104 = _T_103 | _T_101; // @[Mux.scala 27:72] wire [31:0] i0_rs1_d = _T_104 | _T_102; // @[Mux.scala 27:72] reg [31:0] _T_107; // @[Reg.scala 27:20] - wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 107:6] - wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 107:26] + wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 108:6] + wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 108:26] wire [31:0] _T_114 = _T_109 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_115 = _T_108 ? io_dec_exu_decode_exu_dec_i0_immed_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_116 = i0_rs2_bypass_en_d ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_117 = _T_114 | _T_115; // @[Mux.scala 27:72] wire [31:0] _T_118 = _T_117 | _T_116; // @[Mux.scala 27:72] - wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 114:28] - wire _T_121 = _T_87 & _T_120; // @[exu.scala 114:26] - wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 114:68] - wire _T_123 = _T_122 & io_dec_qual_lsu_d; // @[exu.scala 114:108] - wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 115:25] - wire _T_127 = _T_126 & io_dec_qual_lsu_d; // @[exu.scala 115:67] - wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_qual_lsu_d; // @[exu.scala 116:45] + wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 115:28] + wire _T_121 = _T_87 & _T_120; // @[exu.scala 115:26] + wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 115:68] + wire _T_123 = _T_122 & io_dec_qual_lsu_d; // @[exu.scala 115:108] + wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 116:25] + wire _T_127 = _T_126 & io_dec_qual_lsu_d; // @[exu.scala 116:67] + wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_qual_lsu_d; // @[exu.scala 117:45] wire [31:0] _T_131 = {io_dec_exu_tlu_exu_dec_tlu_meihap,2'h0}; // @[Cat.scala 29:58] wire [31:0] _T_132 = _T_123 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_133 = _T_127 ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_134 = _T_129 ? _T_131 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_135 = _T_132 | _T_133; // @[Mux.scala 27:72] - wire _T_140 = _T_108 & _T_120; // @[exu.scala 120:26] - wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 120:68] - wire _T_142 = _T_141 & io_dec_qual_lsu_d; // @[exu.scala 120:108] - wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 121:25] - wire _T_146 = _T_145 & io_dec_qual_lsu_d; // @[exu.scala 121:67] + wire _T_140 = _T_108 & _T_120; // @[exu.scala 121:26] + wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 121:68] + wire _T_142 = _T_141 & io_dec_qual_lsu_d; // @[exu.scala 121:108] + wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 122:25] + wire _T_146 = _T_145 & io_dec_qual_lsu_d; // @[exu.scala 122:67] wire [31:0] _T_148 = _T_142 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_149 = _T_146 ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] - wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 125:26] + wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 126:26] wire [31:0] _T_156 = _T_153 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] muldiv_rs1_d = _T_156 | _T_99; // @[Mux.scala 27:72] - wire [9:0] _T_176 = {io_dec_exu_decode_exu_mul_p_bits_rs1_sign,io_dec_exu_decode_exu_mul_p_bits_rs2_sign,io_dec_exu_decode_exu_mul_p_bits_low,io_dec_exu_decode_exu_mul_p_bits_bext,io_dec_exu_decode_exu_mul_p_bits_bdep,io_dec_exu_decode_exu_mul_p_bits_clmul,io_dec_exu_decode_exu_mul_p_bits_clmulh,io_dec_exu_decode_exu_mul_p_bits_clmulr,io_dec_exu_decode_exu_mul_p_bits_grev,io_dec_exu_decode_exu_mul_p_bits_gorc}; // @[exu.scala 149:139] - wire [18:0] _T_177 = {_T_176,io_dec_exu_decode_exu_mul_p_bits_shfl,io_dec_exu_decode_exu_mul_p_bits_unshfl,io_dec_exu_decode_exu_mul_p_bits_crc32_b,io_dec_exu_decode_exu_mul_p_bits_crc32_h,io_dec_exu_decode_exu_mul_p_bits_crc32_w,io_dec_exu_decode_exu_mul_p_bits_crc32c_b,io_dec_exu_decode_exu_mul_p_bits_crc32c_h,io_dec_exu_decode_exu_mul_p_bits_crc32c_w,io_dec_exu_decode_exu_mul_p_bits_bfp}; // @[exu.scala 149:139] - wire [1:0] _T_179 = io_dec_exu_decode_exu_mul_p_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [18:0] _GEN_44 = {{17'd0}, _T_179}; // @[exu.scala 149:146] - wire [18:0] _T_180 = _T_177 & _GEN_44; // @[exu.scala 149:146] - wire [19:0] _T_183 = {{1'd0}, _T_180}; - wire [31:0] _T_205 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_161 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] i0_rs2_d = _T_118; // @[Mux.scala 27:72 Mux.scala 27:72] - wire [1:0] _T_238 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 197:48] - wire _T_250 = i0_flush_upper_x & _T_214; // @[exu.scala 199:75] - wire _T_258 = _T_214 & i0_flush_upper_d; // @[exu.scala 238:48] - wire [30:0] _T_260 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_261 = _T_258 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72] - wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 46:51 exu.scala 77:45] - wire [31:0] _T_265 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 240:55] + wire [1:0] _T_194 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 199:48] + wire _T_206 = i0_flush_upper_x & _T_170; // @[exu.scala 201:75] + wire _T_214 = _T_170 & i0_flush_upper_d; // @[exu.scala 240:48] + wire [30:0] _T_216 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_217 = _T_214 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72] + wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 46:51 exu.scala 78:45] + wire [31:0] _T_221 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 242:55] rvclkhdr rvclkhdr ( // @[lib.scala 404:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) @@ -2454,7 +2448,7 @@ module exu( .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en) ); - exu_alu_ctl i_alu ( // @[exu.scala 129:19] + exu_alu_ctl i_alu ( // @[exu.scala 130:19] .clock(i_alu_clock), .reset(i_alu_reset), .io_dec_alu_dec_i0_alu_decode_d(i_alu_io_dec_alu_dec_i0_alu_decode_d), @@ -2537,7 +2531,7 @@ module exu( .io_predict_p_out_bits_way(i_alu_io_predict_p_out_bits_way), .io_predict_p_out_bits_pret(i_alu_io_predict_p_out_bits_pret) ); - exu_mul_ctl i_mul ( // @[exu.scala 147:21] + exu_mul_ctl i_mul ( // @[exu.scala 148:21] .clock(i_mul_clock), .reset(i_mul_reset), .io_mul_p_valid(i_mul_io_mul_p_valid), @@ -2548,7 +2542,7 @@ module exu( .io_rs2_in(i_mul_io_rs2_in), .io_result_x(i_mul_io_result_x) ); - exu_div_ctl i_div ( // @[exu.scala 154:21] + exu_div_ctl i_div ( // @[exu.scala 156:21] .clock(i_div_clock), .reset(i_div_reset), .io_dividend(i_div_io_dividend), @@ -2560,47 +2554,47 @@ module exu( .io_dec_div_div_p_bits_rem(i_div_io_dec_div_div_p_bits_rem), .io_dec_div_dec_div_cancel(i_div_io_dec_div_dec_div_cancel) ); - assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:20] - assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 162:57] - assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 104:57] - assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_238 & i0_pp_r_bits_hist; // @[exu.scala 189:43] - assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 190:43] - assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 192:48] - assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 194:43] - assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 186:43] - assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 187:43] - assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 191:43] - assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 166:47] - assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 167:47] - assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 168:47] - assign io_dec_exu_tlu_exu_exu_npc_r = _T_265[30:0]; // @[exu.scala 240:49] - assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 195:43] - assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 193:43] - assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 188:43] - assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 52:53 exu.scala 201:39] - assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 203:39] - assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 207:39] - assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 208:39] - assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 209:39] - assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 210:39] - assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 211:39] + assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 131:20] + assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 164:57] + assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 105:57] + assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_194 & i0_pp_r_bits_hist; // @[exu.scala 191:43] + assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 192:43] + assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 194:48] + assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 196:43] + assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 188:43] + assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 189:43] + assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 193:43] + assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 168:47] + assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 169:47] + assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 170:47] + assign io_dec_exu_tlu_exu_exu_npc_r = _T_221[30:0]; // @[exu.scala 242:49] + assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 197:43] + assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 195:43] + assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 190:43] + assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 52:53 exu.scala 203:39] + assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 205:39] + assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 209:39] + assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 210:39] + assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 211:39] + assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 212:39] + assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 213:39] assign io_exu_bp_exu_mp_pkt_bits_br_error = 1'h0; // @[exu.scala 51:39] assign io_exu_bp_exu_mp_pkt_bits_br_start_error = 1'h0; // @[exu.scala 50:44] - assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 204:39] - assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 205:39] - assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 202:39] - assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 206:39] + assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 206:39] + assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 207:39] + assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 204:39] + assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 208:39] assign io_exu_bp_exu_mp_pkt_bits_prett = 31'h0; // @[exu.scala 49:57] - assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 215:39] - assign io_exu_bp_exu_mp_fghr = _T_250 ? ghr_d : ghr_x; // @[exu.scala 212:39] - assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 213:39] - assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 214:39] - assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 143:27] - assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 160:33] - assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 159:41] - assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 113:27] - assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 119:27] - assign io_exu_flush_path_final = _T_260 | _T_261; // @[exu.scala 236:33] + assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 217:39] + assign io_exu_bp_exu_mp_fghr = _T_206 ? ghr_d : ghr_x; // @[exu.scala 214:39] + assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 215:39] + assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 216:39] + assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 144:27] + assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 162:33] + assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 161:41] + assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 114:27] + assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 120:27] + assign io_exu_flush_path_final = _T_216 | _T_217; // @[exu.scala 238:33] assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_io_en = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[lib.scala 407:17] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] @@ -2619,82 +2613,82 @@ module exu( assign rvclkhdr_7_io_en = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[lib.scala 407:17] assign i_alu_clock = clock; assign i_alu_reset = reset; - assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:20] - assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 130:20] - assign i_alu_io_dec_alu_dec_csr_rddata_d = io_dec_exu_dec_alu_dec_csr_rddata_d; // @[exu.scala 130:20] - assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:20] - assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 138:33] - assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[exu.scala 134:33] - assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 135:41] - assign i_alu_io_enable = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 132:45] - assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 139:51] - assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 139:51] - assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 136:39] - assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 137:39] - assign i_alu_io_pp_in_valid = io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_boffset = io_dec_exu_ib_exu_dec_i0_pc_d[0]; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_pc4 = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_hist = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_toffset = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_br_error = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_br_start_error = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_pcall = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_pja = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_way = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_pret = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[exu.scala 133:45] - assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 133:45] + assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 131:20] + assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 131:20] + assign i_alu_io_dec_alu_dec_csr_rddata_d = io_dec_exu_dec_alu_dec_csr_rddata_d; // @[exu.scala 131:20] + assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 131:20] + assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 139:33] + assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[exu.scala 135:33] + assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 136:41] + assign i_alu_io_enable = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 133:45] + assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 140:51] + assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 140:51] + assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 137:39] + assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 138:39] + assign i_alu_io_pp_in_valid = io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_boffset = io_dec_exu_ib_exu_dec_i0_pc_d[0]; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_pc4 = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_hist = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_toffset = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_br_error = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_br_start_error = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_pcall = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_pja = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_way = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_pret = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[exu.scala 134:45] + assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 134:45] assign i_mul_clock = clock; assign i_mul_reset = reset; - assign i_mul_io_mul_p_valid = _T_183[19]; // @[exu.scala 149:25] - assign i_mul_io_mul_p_bits_rs1_sign = _T_183[18]; // @[exu.scala 149:25] - assign i_mul_io_mul_p_bits_rs2_sign = _T_183[17]; // @[exu.scala 149:25] - assign i_mul_io_mul_p_bits_low = _T_183[16]; // @[exu.scala 149:25] - assign i_mul_io_rs1_in = muldiv_rs1_d & _T_205; // @[exu.scala 150:41] - assign i_mul_io_rs2_in = i0_rs2_d & _T_205; // @[exu.scala 151:41] + assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 150:18] + assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 150:18] + assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 150:18] + assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 150:18] + assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 152:41] + assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 153:41] assign i_div_clock = clock; assign i_div_reset = reset; - assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 157:33] - assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 158:33] - assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 155:20] - assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 155:20] - assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 155:20] - assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 155:20] + assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 159:33] + assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 160:33] + assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 157:20] + assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 157:20] + assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 157:20] + assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 157:20] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -3051,7 +3045,7 @@ end // initial ghr_x <= 8'h0; end else if (x_ctl_en) begin if (i0_valid_x) begin - ghr_x <= _T_235; + ghr_x <= _T_191; end end end diff --git a/src/main/scala/exu/exu.scala b/src/main/scala/exu/exu.scala index b8ed7ea6..cbaea511 100644 --- a/src/main/scala/exu/exu.scala +++ b/src/main/scala/exu/exu.scala @@ -51,6 +51,7 @@ class exu extends Module with lib with RequireAsyncReset{ io.exu_bp.exu_mp_pkt.bits.br_error := 0.U io.exu_bp.exu_mp_pkt.valid := 0.U i0_pp_r.bits.toffset := 0.U + val x_data_en = io.dec_exu.decode_exu.dec_data_en(1) val x_data_en_q1 = io.dec_exu.decode_exu.dec_data_en(1) & io.dec_exu.dec_alu.dec_csr_ren_d val x_data_en_q2 = io.dec_exu.decode_exu.dec_data_en(1) & io.dec_exu.decode_exu.dec_i0_branch_d @@ -146,7 +147,8 @@ class exu extends Module with lib with RequireAsyncReset{ val i_mul = Module(new exu_mul_ctl()) i_mul.io.scan_mode := io.scan_mode - i_mul.io.mul_p := VecInit.tabulate(io.dec_exu.decode_exu.mul_p.getElements.size-1)(i=>io.dec_exu.decode_exu.mul_p.getElements(i).asUInt & Fill(io.dec_exu.decode_exu.mul_p.getElements.size,io.dec_exu.decode_exu.mul_p.valid)).asTypeOf(io.dec_exu.decode_exu.mul_p) //& io.dec_exu.decode_exu.mul_p.valid + i_mul.io.mul_p := io.dec_exu.decode_exu.mul_p + //i_mul.io.mul_p := VecInit.tabulate(io.dec_exu.decode_exu.mul_p.getElements.size-1)(i=>io.dec_exu.decode_exu.mul_p.getElements(i).asUInt & Fill(io.dec_exu.decode_exu.mul_p.getElements.size,io.dec_exu.decode_exu.mul_p.valid)).asTypeOf(io.dec_exu.decode_exu.mul_p) //& io.dec_exu.decode_exu.mul_p.valid i_mul.io.rs1_in := muldiv_rs1_d & Fill(32,io.dec_exu.decode_exu.mul_p.valid) i_mul.io.rs2_in := i0_rs2_d & Fill(32,io.dec_exu.decode_exu.mul_p.valid) val mul_result_x = i_mul.io.result_x diff --git a/target/scala-2.12/classes/exu/exu.class b/target/scala-2.12/classes/exu/exu.class index cd6ede211d4c14d6bfe3e84ee11a23f8905f0f2a..0107f46616ad1295b356b099ce3c09c6e5db6d0e 100644 GIT binary patch literal 260714 zcmcd!2YejG)!%m7y}OZYxmQ3&Hf|tGaxa)uu`OFJvgB@aK1nC}Y&EO6fH8y~2niv9 z5CTa^qa+X@KnOJn5JHELo)AJp2h0@JFH)6AT~o*G?}R<$|1)zYfHMJZj4>d}l^ z8PP_lh53b(RBcpIqHu3SEz*WZ7if?_UF6S%{8E$WXLQIPrjh)JNr}S3kvxA|4DyRb z{%(-3qx>x<im<)0?< zD*%7pcrHISA8>AV$rnz@+S%@wr+hBI)0JO1F>9yUm0#z|-{s0LJT5EWCh~c^Q9f^< zE?0ix@mV~*uKYSz{sEDH8nl1m30yuJfqETs<=46Lzk5#BP*I`k6rdZz@nEQ^j`Gov zZi##VT2!cI<(XTa^11v_SAL=H0MhM%Lpybpj}_L(xa}KR`x9LGb*}sqT=|6*xZF;$ zE5FW_Kh>3An3uIb)0JQ6%Ae)RFQglQ+n?>quXE+kcjXsaS^JA!`E{=R(_Hz5(X4!x zE5FW_ze41rUkYPfp0{(YE5FW_zs_Z+FrKyF;L5La5 z-%R;>3;MSJ^9vWCf4kiBL$dO{LVh304<&gE zXK7qN$V%1ibDDg`!L z;iMT`7q(>bN)uDZ&)=OnW74Felu>9#s@0+@b+^7@@92}a&*@xSaAs@4>E#DA!*-8u zAG@%trg}QaB7=#Q`hI!C5nnH?Sx2a>Xa?>cJDZ@p|q$ddO$C#LA{ zio|ezUSX=Tp|qoZ;o^Cj3G@3_H5QLqIbl&tdK{Z~@>X^9j=Z+fYqrm>N-iwkoPYeH z$=mWKoYXmCcv&J+SlF>WuIt+hD~eJ~n>)6&uyDDq0-w-^E^JvnrFYZG+sivMXT(a2 zw#_dpDvVAmN)^P+NVS|RJ;^9E;*af2^k+XF0 z&s4o~WuhoGR$Ct}t;nZ1Y z+i?q9c1)@(EM1ov6EP-7i;Bi;6AMS|Z{J+jQFD0F)FE3-`zqo3Ugvs|Hl%dI=FZLK z2ls3&EG&g+(2tKzo2KiUl~;XYN}Jca=kN@3)^X78qvN98Cy!8k(}w0PnKZVjQq|9nrnIf)%}bZf9FxC&R(tElL(5K9&AQ2>PK?YL zK5f}aQ|dQP%hR+`6-9-6>l16oN24_>bxoU)H?6dDOKE%M6v%H#td8W@qzg`03yN0G zsE%%!To+%nYVyosg<9dns*^g$EZMnZ4J&LMH>YQ59LKlM{Izd&&;Al#HFXyXJ7^7`1BNzAcB# zp&oP6OB;>hiOM;pOSiJ+r;IP(S(CS=uweD9{gq|4%iG747wIRX-Ljs_g%iwbGO`Q|x>`dhq zLtKK~0+d_OvuarFy!_K=?Oi&I?VU7!?9SB6nafY!R@S!^@aEU37PMF1kR7vnpnpL5 zy-Qa@yHtU_iV>Uhx6WzK9M%u8q&gJk*6t`z*B2BYU^`|VOhnYilgH0*+;UjAac?Zx zp$>!le>B92gL_*A*oz>JLv!0FEbLhY`n3}lG%sDrN_A|%!{hg_ffVZ9Qm~_JXIhKx zJyGC;XjmoV7J^@+*p76+ zZeFxEHEP5GHm*<`o&tZ3UDUXARPX47z69io$Fy%Q?@UBeYS)TZf; zyu2DqXvtaW%JmHTpZPnRR>tbQyf(Z@$8yP@KCSQo!~6B{jMjo0H6L(}&Og0$=c^5i00LKK#ugT_D?8xSiOn{%pE!dqJ1@%efVY{0p z;}^6n9cBzqp&vbQu|zAvI371|U+bhpc_m{PW%zxdqkoJs1v|=j?#uy+;OP4xHYUM*IHah%E9z6tzuknU4)|HFMb66<$5 z-e0Jnhw+fT-+4U`Ei2hNZ*NnC>bZ3N%uNM5#un*2?E57frvk^65;Y&}@HpSO{L~Rs zOSZ!OBjO9C97vO^;EEVojYb>e>OUW_xZ{RW1wF;Bb7H{KJ@pU=;s9GPxa=rQpA;B zGorV4%aXm7YbG4Pc&*W53Cd?qKE>yWql=dL?9+XK{lrM{>y*xk<91fJ7-QOZi1>#4 zaR#>cj)mn*W3^VvmW930&nz$5GAo^kB(Oj2X(#AU>;Pd0yLHh=AEluy;2a@@Rh z{nkTMI(LkP`zPb&p`DAi&1&4Tapt5%Y8*V_s*4KOM2yI$l_#Yt@i`WU=NR4>EJbq0 zaJ8zmeb3?Ho7;CRYR^FbU*zR6es?dOJ9EV;d76Fz#?6I##ggIqg)F$k`!4UY@JSHS8!}L@4<#sTs=L2t(s#K ztg4LZ!5OWRb=~RabW3rfySsCLqNk^`2_#nlKKE5qSqXk}i2&e^RC}hQwXzc?-VXE@ zx2KxAJBv$IWmc^n<<68GNtUc}D?r$%yIWFCIFY7hI>E7yUPT|qBIL7m>#M8Q)vT+o zuh|ON)f#Yg>#pwPfn-My1iYhww-<=>Yt8&x1jU-6NiwsNy{SFv4rJo(eQn8oskTgW z@&H{T1}}kJV|S{fX%}891g;BOCDYWK>`3qLLgf)oX??w!wvvr#2Fg5HlD)V#)6vw{ z*PJe~jdbnlP4+H2737D2>6W&>o?XeVRPQb{T;M8~EdeiM)P^lx>gi=R3Ho3Q`$snKOOrko}bQlPA_mn0Z4|c($1!|0S zqs%gI<_NDOZ*>eUp6$rm*_Mz72_nnTFoPg&&g|nQ0vpLBQ*C_^vbCbOM;4nKeTQUs zx~H$L7o!?PLDwyc_k$2c(jy9GxJ9u@63wqlG$fL%t5+v$Yu3PBSsFOP!Mn$5NVO(6b#_C=hji}~9a%e{>WAk`ZMF*)mp}#NL?0=W z6PG}4X!kz5^Rxv=xD49YK(df`$J9UDq9a|R&a(_;hq*g>TX>XLSUdtidbp>fx5Y>M z#Km&}H24%-x#ek|T$Ywj;>lB}Wb) zrALs%OCSfW4#xT8)E0ENx_u2K;}t6!l8LIS^~n|R7|3$9YXLpKwtjtLOR}nZT?0J4 z3NUB+3J^}zuSjCYWoOW%#6p(Hctt~n+px`%VdUI~^HI8@A+bEUY;A27xWM7b+6d(F zQdzQQO;z<~4nTt#vr^>W|!a(>;yVhKS(#fF;Ns$^nC1>B$w zaD&D~#^##Y(BKY}T$5<1*$CGmt3J7IeFHY$vc!hk1_*I}k0&ZCtLy7|+rR*-Ummn- zzdYy;`{lvNs$U);>6bT0k_RKMesc5RMsee-UX!S(tp@~~ zD#-=3l3c*+sl)0-{VIQZVxGS}G0)$gnCEX#%=5P==K0$b^Zf0Jd4R8=spCL~m)RPHw8H!n=!dxDP}Q8K|zTv_;}viChCA#<^u~4YEP^2$e}T z)@&dk0D^3+uU=lWc8v|GK2f#aq4}tg3~?L+e16sHM6zPTGP^T~5nrFIfg6_D3`RVb z!DZ`{a7)8TU|FKR0dCxe>hn_^uf|w8m zw`D76yKI=a=yjUNB)eEgCUR=mB?R5fYdM)kD9EoV9Cep|*Ct>MPe& zC2OJmvjWti*+}Xe5)IH(QPpiN?1@Fq?PkNQY{hNIVJXFPXLw^Ds$^$i z4WW3O&0398Cci(RIv`-T8*x-aUU|4idLqiXv@6QV6tx8@I}y)CMZ^=$BR*EMYy-r% zh-aG-@ocj^o(pT%Ks@{Uaep56JN`WEcl>$fl058p{Bqdu`17#e@#kSb?#|2h^0h$NO8re!PD!_T%nc>^rd^_viWB6XpEviFy9^#5{j{VxGS} zG0)$gn1}dk*Cwix4QrDd>Z_CMYB$sa7PGc~LmBjPFc1JL8#gv1;>Koq+!P>(F}kJ# zE#lj+C&TIGF}ofHMD(EGT!X9UEnKrUN%4*;cA$V_T}@@Ota3|bEin1WR3rc`4((uo z&v|Z*UxKbUxoPeCD(E%1o_%X@IqDv`T*KOiL@jpQ;5jtm@OCQ{tgnUvUjy9nVwe;~ z*y0|F3!0iDCOB$|hMLvY>yx$B%fWs%Jcfp@-ankVP9iJ9~S2yHj1Na=9Bp zz$~TvMH0-yWRyF{qu6k;D;<2%4PU6*02eW}LER8j>(z}z@>FnhB-Pc`c2HG{q0&dI z9Vl;6w+>Sjb(^XfFn`m`)E(*?w063xjQ6SIgxvbRjs|F{VpH7-5w&`4)rQ*YVp!?s zFUlMk{dkaoi( zEBn6AFPbXM8AMytz2tFKInC`J(eC|Cy4%wiGfeGJJ7a3Q3ceni?&yKlbcv>>bWcyF zu`R7CbKUlRs)1I!)t(r%Krh5(su|j0x!Vv`)K&8jVtJpsA6o||Q5dx4uFmGlRMW0B zg#9GHQ~E_W+#x3EfcUs0myeydujN5?Og77l*Hq7z-M{dhaU%p)6b@AXyB(fDZfRhJ zG*JDe;o0Pt23AM|)n6K(T4r;)DG9M?sh4_H@fx)WQ2kZm;pQ#~SRoBme`$E^xut;> z(m?f>p6`_gR!9TYUwVO88dxC>)NphN-4k}_ISU?W?)U)S621pgq5vV`Q2^dn08*j= zZuBSsZz}*PQ2kK3ASDXmMUMjTwgQk61#n~( z`pJ$YOcA9m^>&{=T(w-uzGF86sF zd0Rp1>2jZ^k+&73o-X%!8hKkm>gjTyr;)c6q@FJKc^Y|JLF(yppQn+x6{Man_jww5 zTS4mS**;GrFBFjM@9Eh-Pa|(DNIgB<=V|0^1*xZJ`#g=jtswREY@er*w-uzGp6&BA z^0tE1)3be^M&4GCdV03c)5zNjQcutJc^Y|JLF(z*K2IZWD@Z*($LDF}g#wcOJv|59 zX}0zB@v)6I*4s(pMO$0y_BlScBX286-9E?XcI0gZsoUrH+>X4hAa(m3pWBhQ6{K#T z<8wRmwu02{b9`<`-d2#heU8uV$lD51x6kpp9eG

h`%lw<9kUknHdFx!_Ls;|O_M zLF(zbK2IZWD@Z*(*XL>EZ3U^P=lVR2ysaSh^jx2(k+&73o}TOTH1f8B)YEgpodwN} zt;weL=H&iv{4v|oV4Bs_a#`=AxTL9l-k+QGK9UjzpZDixy^myng?T>jBQNTOq(s5z z{drmMBPmhvd4FEk`$$R@eBPgz^*)jk1)ullWxbE2M8W6%d0FoxDN*owe_q!6NJ5ebtZ3U^P7x+Alyih>0zo!@YJdM1qAocVDpQn+x z6{MbC;PW){wu02t3w)kN-d2!$dI7kTPrkqcAWQqQx5@CLtu1x?0-xKFw-uyrU*K~) z^0tE1?F)QvN8VPDx_troHZR?gg84y9yWLlxYzUy(2+6bzI649=>M|Xcb~p4Mo+%o* z7PaSSfR?FaM9`W&S^##y((dz{0U5^(&@wX+3?s4Q>V;KVWUj4qKdj2@wzTj1&4H|A z4rrM<2o-NlAj8oCTBZZhVx)LG{LrrrmmF=NW!exeMkCjL+OG|l9BrUw+7LQ%tUj!2 zgGGwaY5&M?1SA|IK+B9kIC(1#8IBInG98Gh2o##?vb10N)!~|>4zx@iV#-@2WH>tV zfGfqI607N2S}g5%J`?=92s)%C#g;-44RHruXJ4Blbe77a6Q?9SMPh~x6KP42I6;|*i(H`()rb4_T~UaFGJT9f zcfX4hm`<7Uh{GvMD6@>0Io_}D3N#dyl?h?vEz=cKIK3&;ff%vub+DFxqThlmoN&HV zW&vV@KYL-ttff!&8*oJt&VR}b_@fA?J)NeKM-fhRdaLS+BD^Ro2cpBP;|d*|2$ksY z=}xFvra9fwZ0S$|j|IGJBSl(f0pi0%3q76PmJYvgc@4NC31>=W1|V1%_CvTLd4G2r z;_)=U6<2KG^r_4Wgp9XjS3Kbis!Rvt$u5~<#L{6koY#&k#&BX)W(NYttK*6)oLiOY z^lNHYAmQ|?OvfKcIIHToM;=HxkLtzd3M9NJE5{#5IJfGQBM&5;LiLn`8MY46l5%iD z)vM!*7Q86a0rz`#T(N-@t}-2eY~VbrgH0YAIJ4?4#}x;7QC5yW4sf>BDMua$IKS#G z#}x;7QC5yW4sg!ZDMua$ILqoS#}x;7QC5yW4shnxDMua$IKk>E2QzFPq$TCx469ei z6$f}xrsIzToON}|k;ehfvwF*M#Q|QFmE(^CoO^Z3k;ehfwtCBP#Q|QFmE(^CoPl-9 zk;ehfxq8cS#Q|QFmE(^CoQHMFk;ehfyn4%V#Q|QFl!G&_9v#fE%RySE-f~=VfEQ)u_~QVlWu0>5aex!C-f~=VfEQ)u_~QU4XPt87ae&jY-f~=VfEQ)u z_~QWQV4ZU0ae%X~-f~=VfEQ)u_~QU)Vx4m2ae#BLo^mk5) zM;-?_QR^+o6$f}xRt~y4JA=T#sHABG{U3g7t_Z;?UWqlFz4ai#3>!7lG97<};N-5O zBaaZA&h?h#iV(agE5{!pIK}If1GL$`XFcvYs4Ami390?PbapR7crUVq2(0`po$846 z+qDqZ=1SC=p&D9Tu?!ui?0R8`L@3_=Koo4p;mhnYSa92xPQf?7#?+c=@aYCDAXS*_ z0u-D-)&5p+5r{A&X2j!4p25IcpDhXd1Z3gy53#d|#5cq-M;L6Ll(p#~m#Hyhs8NWe z4TD*LR8L!HM=L>v57ABH{RmewW0Wx(b;f{bce)D}t{y+N=19eeuf}1;s1iY8FgG;| zE?A8j6OH4rB-ke**4UkCZcQg!@dN4+Q){-m8o>UNUGGf+d@Hr9G1&|2aKQyxB`9~I ztK9zT%$RIU!NN`gFM+3wmbOe6EGFee*`J!H4rG!|yHXt;>9!tlaRg<+@`+x{QfX$) zG)_kQr$DG9#4I-Wg=A`fKrn&l6@!8%WDDxAz>G4Z97}+n&csiLD-*Ra>*g$dX3YzaADP1KP1!wDuBifq@wdjD-jl8j&^jg1_LC<6WtqT|t2^LP_gtf}6&z1Vx1i zc&^Tj(~JZb3`_nC-8Pafoo&sqI<;S3F*B-31s4AEVqw{Hw*Xs!;tmg@H6#kR53d$( zkU-U%>AQcAa=+xERt7>{2NR-P+Za@LPPS#ehP+(%9ubvaXVhWk*W)tWed&Gh6+Nt6 z&-5OIb=FOLaLx#~D8OQ)l+S7SVA?MVHQhv}HbaDYuJaodzTS4JKo%%$qo&yo#=G~y zHW1CtX{cFVXG;t3qhZevkqNRp$vAWxuz?5c7}1&*2v3+=)348<)%`rO${?OjJ&MR; zr;T{e>E-zM@A#z|eGq1Gl7CBLpqs%HZam^BZzeGftjO`RPrnby8;{Bbeax?ffHWb0Ac*4eaYkz?8Q zfOhgEo(j6=LjrdZY(W5jyL(_TFbpTooU_Q)Y}d7{he+6 zp5P-AJCmL#@bf8Vv_TvU_0A+ocX5QLY~{rWLS9DY~i;w!SQ3yKNJHQ!S}RnGm8Ol9wBNvTd7 zNUq`iuHik9hjqthFneI9m*#Y{(;!rB@Nb>OzY>!{#rYb58J{+;MCV<_Z^CTzCvo-y z`&GwFkOMyXEcxUbN1VWM@sK?ON8IlQ5oI~%a_9qOhMDns;|o~9FLK1$o*YI|{3AGf zSS@MC8c$A%Sj(DtquimEof(vAapOI|_k}8DBNNhPAu_#yozjuO?18{a^?xA0)ZeL7%I9|WW-ryr>;a_e!R@jR}; z(RxpB62|rsd-DO>L_`1psI6J3UR{U#aG)^bTgIK(3U|TQ0bUSx+rlgNm?K<)o8}&B z#P8UR2)m+)MofOljo7~xjoRvE4g4_<-m?pa#@jVmjpv8Jj0cT}u=QZ|3$>nuqF?Lv zzXGlIFty$zM^uNo3u^p+>hnPTF;f2_AK~=w@9b%UeFNdmtb3o$fY6iFtv$t*OO#8a zie@~+l*^R$NIi!?6^l)XU}+D$x%A(Eh$$aeK7qnN1_@iZxb2LCSXN(e8b6(ddv7B% zero(I268{=Mrm6jzfpU$BBorfd=icRnj00_Zllcj4Vin159q|^MKs%x1?lW*#FQ(P zPocrzgGhECB(KFkki}Pdb3w@P4UnMeJ@vNpix)BF)5?`-^Ut<>XvZY4(Z7<>zwu@V zW!eh~+~&7xZ<556tCY{6*?-!;6<54=-z2;L;v)pKOPeO)i=W#~*((V6YUQ(N`MfY(;tWa5XUI4N1yHYoAxXfY$PP^oVRv9V0`? z+)&#bbnX&!e6J^_d{Ma`&5f|lVYb)YC^9$NHV3z(#2n-zx-ThTMswqBbC~TlH<8R8 z$737tlfp{B)s~;SJTO2zGI5L-C43Y zy%%23r+T(HTQqH>s%-P-eTWkmXnkToSoTh6gb3&GHZtXFyl0BcWXcUhox+qGiJHZf zn}{l7%FRU0X3E!zn#+`L5H+7Ew-B|EDYp`}m?_^R>QtuOM$~Ccxt*vArrbeP6;r-N z)H0^rNz@9a+(pz%rrb?bEmOWt)EcJTL)1E^e21v@Ou3h+2BzFc6x8j0qBb+-0iw1t zKjb?BT=_97b2buCZ zQQu|CKZ*K2Q{Euz5vIIJ)DM{QFQR_Plz$WT1XJE3>M5rDhp1PL&i>cFyDr4$&qGmI722pdFI+LjROg)*Xg-kt#sKrbz zA?j47&LZkGrj`;_!PGLMs+d|%)H0^dCTay!=Mc4$sdI^{W$HYl)-ZKGQR|qxfT;CM zT}V^|Qx_4nk*SM`+RW4?L~Uj2sYGpO>QbUkXX1A@-M5n@r%G({ zF|2zVxbUK-;YG{BipqCEXxng>MeBwW7VR5O zShR3BVbR9ngheZd6Bg}!G)LoBceBEI4@E=9FN%hYUla`)zbG0qeo-`J{Gw>c_(f6C zuCjiMc6PP5eWgY{K^EuuVC5oeHcL?>jo!X;a>$1Ux8D|W~wG1>FV z-W<24iezNNCtC(LPb4X+ld{|FlF%uVFgwETyQCnihS*59jBm|O;pFlbaNWKp+fs}Qfwo%viz(=pUy=yQ@24Lm4Cf`z*L}epI zfq;wBtrDUU{P(;p;Dlkk>v=;3IGvuiBsNVFOv03F|6-Dr-8Vv(s$%vinCAjN1eswOnT><)fO*j%ov1(6#UKQH#c1mR+$E5WOhr z4V?gAqp%%e0k@;r)0t4pd5vFXBM{Ez@BkYLiv$1zXU`Kn(IU8D&i;h@SHZG-|gtPrMnUQ)>$OJ!? zT$^Q+DQUmx-$OgRXu#mpy=yei8UzeJ{h|SbPrqou;L|S}F!=O~1`Iy^q5&^YZqcK@ zJoOh2czNnC9PskgUs$xSwDWSs0$~n#dFpRD;N_{maKOt`f8l_aC$})Z4+OkC`9(v< zFIo*5zbG0qeo-`J{Gw>c_(jo>@r$AX?b>gzb?O(6lZ-`RV|3htodjfE8t$A((-Ev}2{$K$Z z9g%=6sL?|O-#(5awJcPL>q1G1 zxsIchC|-)nU}cQG4iMHzr@P@G#FF5HC7H5XSp!QyOj!Cc%%v{Qmt@LXWgT9g%#=F* zqGmB=Gf`zs*+SH8rfek&mI1oI z^zs}bS>h@&d*R53NHS%cvK;{}WXkDeelb&$ly@pqb`o_OQ&L1#Fr|^GDyB4%#xkZf z6SaaVX`sUbN!-;0&sk*3#mYxf^5eMN zC>xUev%y77f8S7GxuE$;Z)C5Bb@1KIpuE;B#>=0EMQV#P9hu%!z3X>3GV?0)GcjeE zc{LQDJ!7C@7n}i$A3~VsH8Ewfd38*w#6MH<&l3D|8vdDqe@?+arTAwd{+W$`=Apfz z{Ji0ozK&vkHYF}`w2vaTo6IzC1O%|?%Dl1IHdWrSNFzhEz8kYf*imDa}ucHqATXdqMl&Kf+e_f0oRcfg7iQ*<%%T|NzW}{DP!QZd;V~_4Mp1uQLwlV0bNFzg29El2)uReND{_4* z%UNdr()<+~`n9Ei^eO$S68Lm6O;}rNfCwx-obNtpr2iqO;*1pc*(E}VnJ=5ai<`eS zVc~6oT|PaYO!E)0CeOGT0saxz}^gX2z8595Q8cWf!n~YlB3zv+1K5a&UCbN zmeg|+PLEETR-vW9YTnWAW*2c(gG)WltE>?*YnV0C^SuR+Yo~dRTtp3&mi>;z-;+27 z=r#fLqhsd(tTC2S520jN0IOzN<1J-_rEIj6O_s9RQnpwMe4sqsmdOrhicRZ8h$6?d z>k9YY7zr=_n~xS>Sf0xPRP-CfT=C|GSJ?39BNeo?}%CWU0O$0Ez4Fvqd@& zZV1$BYgx>^%UTXyirttvT50SuE%?SKhID&Z5{@Ki)+%#;%vx#HLQmG1>4jYa+~Ys; zzO}|$8?$Cv>)?AE@JTOdtv9EEH!KK-$$|G;EgbFz=X}B4HrCpJcN;8ZRyQzfGw3U0 ztS#`EDsJk8FZ=m>Equdf`{~08P8 zvr<$YSSEKq2{l7QgOIq~LYG^adJ$dDKuhq0#F@3nti`s0Z;_na0!PiJ)e*Bgp;%=n zG%&;mtQj|Z>2qRc^^ieWJa-8h+y_0S?J4-o4UZKttpngH@y#3X^!nfug3ldM4%~f) zb!N;uXdQw$?|!UHyza&)Ghy9XieGF=Ahl00nGA$Sm zTg{!YnJYhltq=!2#n*zFh3hiBI3F>U@-ns?R z-D)Wrrhbkv-EJwcEcNrmz;f}e00-`;yDeo8Q?I9N7-Hj{g0D?H!0#i-_gf0AWBm%r zJY*^D@FHbL6@OM#rg|ahVRSs)sfv@&1OJhz^|19QQ*R&}kAVT)yjbiw+k%@OKnp!i z#XZ5)n@R2|yc4r>aN=M3017@sg3mJb77~2kYp@Y_ngF>MNbbh~O!9;&hX~fF=(n6Ev17+PKe;>-1;p{PC!L~`W?(6K(qt(3iSAR z^Y&nPtIE1;X#w{192g7V%_%%ELU)ioE_J`gGIe-DKM>);!m@v!Xm>W!vSYhgLx;) zgHH$U;)tVpOudIF7+f1TWMI)4hV-;(oEZhi5LC=pm9A_{iwU_SL6f2P){nqD`kc)U z!tMD!bxRZqUl<*V&+Hw{c-MFju?&aVDITfOkubAG)M$JJyvEe~s3zl7r6vnEsHJ7C znnhwaYIFijqC_WJN*Bz6QHdwO3>s1Jy~Bf4Y_X-l6jnWDp9B+Y{5FbCW9s)vV1}i1 z!$cklz_$*MQ1&cKfeEiPWtTJcG0L7}DZMaXN!jq7!xNOf&{AMhYzt*CVd~SAz0^|R ztEP4;625VGj=u*u4%!{C!}|diT?sa=v!kovLm2nYCj-9O zsTr-yqpQJ9(KRp&NhskPieC_-^_BwDdpObp2XA2NuPJ*IGrnouhI#O!0$*x%k^p=^ z@e&EZE5Sjg{*IUwQ~y8|yc(PVQ>P@|0<(%l?Sk1yqIScKFi~wRVniZXLhpGRhQqE=Szlb`YssAAg29cx02m|*LZ#>wQ>gj=JHazvB7eiA4 z%#Skl|48^!F*IsSb+hPYeB=`SI8)!HtCurPAqoa+XEIGE=1O-7W!@4#LnU0zv^)~N zhG|ivu4Nh{>hqQYBWdpo?CQP)r7Mcf==J?xVCf1D7NTE{M!yvO3P{iZ+WW`^<*(tC zhx8g(zcCuUA$k)$*-3=93^Jo%$1`I+Lvna%ckWO0^mI1yxsvEDQKcq&E7OJ${@Y+M zloesoJNWQB`YomnBZ0fJqda&*!uAhIXx?vA)7%5!R2R2rI{JEwTf5UKczY{`9ckc% zUKl*^!9n(gQ;hFjub|Ewth)w_SoGfLeKCM|Khs7Mf(My4hA5b*bOy`fJT)^412Tq; zK-bQqj{v&p!_h~XHj(rmW7-KsJq{M|g%-wJLLR!EC#g11G3`W>dWLCJh=N(gQE0rQ zv!fB8!pXMI6zr)2??x>8BP!+v{<1Ff6byX&WiL;6G<2u-rMr7@WCgC=68%XGTnU4; zvHgT=@O>C(*P}2+Im7;7*cB?afNO|FZ{c9}moW&iUs=joOq)iP`3=)%67^fAl@Rqi zrj-%(3e)Bg^(xcm6ZIO?77_JlrkzUEUo8c`NK)X=!!+(-MeT1k+rkzg|%rBXE2vEN`5}6Q3EwNUNqg}2z5*N+b zZs82ffL*_KrMg(G4QdtJ6KiMMMN~$or{>(Nd#UE#OuK|+dYN_^QTv#7IZ+3g_9>#y zVA@qg9b(#Ni8{=*Yl%9CX;ibhaXcq-xx+7t#x9Iq z%*-3i^U&d!49SaKI@CN*R}{s>KPm(fb)EI;?o6sJa|Z7-W0%91rP&7%O{|vGrrH~u zQ>)Xxsg_hzZ)f*GGj;{EPpS=%tGDx12u0^f~ znwV~P<#-euU?0y#()aFuAS)rH>R~bz9Q*0mm9f~TVpl<>#Z(eiby;5re@CB%kC51B zhbe088oqCv|FYAh10F@E4|GBMwx>HF;!7%0J!x_hysKUwyEX344sDUa=b~+*jJf$16{iTVy_t5)EPyv*iA4I8~a-9W~SXtGT&et&4R>k zg$wXDrqK&;>~^NzMIzsVg%14XGIkf!?xnnM!)gHPC%(h9hbZqprqO#(>;a~Imu`fI znD!W5{hkYGeGU9%5qsF4g+TVhorOS);N(YRKY%_W2E&x62*l$|d!DE#nMN;7v8S0v zFDtQUaUQ6nsjaU$U4m;0U}_$I@`ydpwBL{t3`uY=mwqxZ?fA>sPq3f*Dbrpi*`Hg= z`AmD2m|roCUIbzfPChBFT(O5h7d#1fld4FK$H_VIizWgJE=xamGi-!Sy zjip=wYZvIk-|&a{Pcz*hjn|oO67>etV?_On=`$S#sKoZf;b$*{GFFj|TBg&mDZU0` z&Z`NX8Eieu;_FDa4o0qa7S6-~f(EA304u%`n%||})ij&M@f{q>+yWbWaef;qZD%@- zx8kQm{D?Z^-3}!Fm;;sGiIUgFQ%rBB3N|slm8dlA;lO|GkGC?zG%O6~4AW@{6W_yh z8l}YBnNFjWI84`dgFTRgDWrWw!4G^4e{D$brT+uw4+rdVniq)o#rHv17>CK2KEePq z5GojnV#)I)NIE??I2JfPAeE)#*xg>NR(+`pmj5h2S zK`^#Ibr7X6{;ieqi@_C;!{V19KP`SK(+`o>Wia;3LV$hJ@ohN%2{I1j4Fj`S{0h?h z6w}Wpy(>M?`45Gth%*cT{c5J4OLFiC=W!{ZXPRNCfr8hP;B^pN=#M@K)i2<$9~0tV zWcmf9`z4q#$YOK-Vu=R6LI%Fd^ovOvp1H1?@ZTmt>?Q=hG7dZQ;NTBp0e0r8qd2;i z>6en~ZJx@|&lRA12Nm%xrhlB|?m|<*ev(+&sHc%Xp5yo8PmDONk3*uhEi8UNEEs^g zJOGC2h(ElyyE3prV|$kse~9UyCKK>%9-3-_mtt|KU>bf>vEmOi{WEm^QKnx*)MHG) zj;P0({zamm#9ySFaI_wO8tXYN{tVNnyKi@j#qrG%uDrnXuhEsCF#RT?e#Z1~ z5cLbDf0L+RG5rprUSv9rL*g$n{T|AD87hh{ff&RVX7S&n^_B5gn0_Bgyb5=ikl+o; z;;)g&pP2q2iTovN1b^{i@xPJ8-*Iu(mJ*KiGQ~N!hEuHZpb!D}hB`Y!-xj zS10^#*W1_KA=b6=U!1Zp4ED5|J+yYZ;lQ2a9HGMNy;=%8+PXxJx)gE| z+*)|PHt4Bkf`(Kr7c`_Q*yS>4e~zFbRp$yCQWeG}Ahc2_o;V;hJXDi7AT&H9 zlQ_hJr(bdo35_3miO7)9@We{GhFJLFl>8cE!P6w^8e+kdA&EmQc+4Ylhy@RGBo49Q z(Tv0)7Cdy3IK+YnC~^)74NpTP4zb{=hQuKjJg<;A#Db>|5{FpuJVD|ROSz2&2@TH! zq-%%;Pxm7ZvEUhg#32?uk&kmoXn58hafk&^(IXDA;8}UZAr?IOjyS}E=i3p7Sn#wu z;t&g-Nk<%F!4u|)Lo9fX9C3&RPle+g5*nWOMjT?nQ{9L|EOv5DT6eMjT?nJ+z5K zEO^crafk&^?II4b;MrWnAr?Goi#WuB=V=j#SnzZ#&LN@UxmUy?7ChaGIK+ZyRS}0+ z@I)%&5DT6!MI2(mQ>2JPEO;gqafk&^ej*OB;5kmjAr?HLiE~J3cn%YBhy_noA`Y?O z*-6A97CZ@wIK+bI9TA6E@bn_$5DT7BL>ywl6NiXHEO=rNafk)a0^%GJ8lLz=9Ad%q zdx%3UcuEg(hy_nsCl0aTsp-Ta7CaK2IK+bIofC&x@Gx`Y5DP!K9Qz3*^wL>?!9hvJm3*LP{0Es!2<<6U=ln~zym75b9~qt z6OWW$irul`IX>)=1<&zemn?XW4?AVSb9~q>3!dY{j#=;=A9l@x=lHO57Cgs?-Lv31 zKJ1r?M@lcno>}l5A9m7$=lHOj7Cgs?9kt*&KJ2Om&+%brEqIO(yKBL7eArqeAsmhp5w#LTksqocHe^M_^{s=JjaJ!xZpWH?8F7n z@nJVEc#aSIZ{m^COR*~#JjaKfx!^fI?9K(x@nMH9c#aRdbis3c*r^Mi(WO93OW6g6H_K z`xiXNhYtY3bA0#+5Io0+eLwL?>81D>5Io0+4+6n+eE293JjaI*1Hp5A_&5+e$A=FD z!E=20NDw^7hYtn8bA0$%5Io0+&jaF-(o6BtAb5@s9}a@&`0(){c#aPr5Q69U@DU++ zjt?Iag6H_~F(G)44<8hQ=lJkZA$X1tpAp0(rI+I4Lhu|PJ}?B&@!=yw@IVdO=FG+M zw+=J^JFcnD?1Bz6|2~)^x5xN=&4rl{Z_A)h)BWPaAT$3Vm@9&nUp?Z7kTm_=QLHNS zBtK}_KbNGNNlf-y0ADy!5#4-+o-sS^nes-yfzJ`A@*RU45ptBL#0-@H%N!!VDX< zcs+iOv^v$*fIlcfbK{p5Yx>$7)7>IxSS@@S*0vE2*+B`BIg~2C4mUJS!(>GdyyMrv zIcwegbAU9kG5T-=rm?~5SorV;TXtinCj&+j9UYy${Btu99162yy*<6K{E}=!){uHA zF;&yi23T zr}7j&P30+kn95W5ES0D5Q7TX2J5oi>e+p<#*#UOpYf_#M-;#Rr;fqoa58st~c=)>1 z!^1bG+zxzU%2W8hl&A11DNo@;Ql7$Rq&$U>NO=mMkn$8hAmu51KFU-0c$BB`=_pU( z!%?2XXQMoYk4AY4pN#SpJ{aXGd@jmU_*j&u@Tn+I;X_fL!e^p9g^xse3ZIDb6h08; zDSRHvQ}{TPr|@YgPvOH*p2BCLJcZ9cc?utY@)SPud@U4gGlvJMr@rw$SG(?0gUD zFx(cNr#Fc7Mv>km(wjy4b&-BUq_>FlR*`;Fq_>Imc9Gs8(r=0MPLbXv(z`|aZIRw1 z((j1$UXk7>()&gFfJh${=|dv@u1LQp((jA(VUa!}(nm%51Cc%^(jSWSagjbD(kDgw zlt`Zz=`$jIR;15~^m&o~NTe@_^v5FoiAaAc(w~X+=OX=uNPj8PUy1bBB7IS$zY*z6 zBK@sMUl!@_MEZM?z9P~;i1byF{!yf_iS$n*{j*5_BGSK#^lu{lyGZ{b($_`$Pm#VM z(ltirldo@yf1MQVsN zBGNpOnj*DC8Wm|wq;Zilk>-oEK%_%NI#i^EA{{2u;UXO&(vcz^CDPF%9V61QA{{5v z@gkid(upEHPNc_+^aPO>iFA@kPZVjfNGFSQibziq=~R(U6X|r3&JgKLk)ABlQ$$)K z(pe%c6=|7B%SAd{q;o_%SETbqI$xv1zCDK|X|=KA~SEhLrqT~uC~s&TitWFy7z9iZ}p7nGw)UpZkl-;DCqgmz~8u{zN-u~)p}Ds zC;wT<$WtJUmD2p@;O_}wIigHe&rr{V+_*AHJ*1um&txb~U8^2el>Fy`j;QKdWhj7x z1x14js>}oGTnE&7L7>hbWKiWEP!~9$E(`*7(IA7G?E!VM1L~tepe_jy>SMXY)I1NU z%N$T24+8axK?XJ71L|@I)F*>LU2#l7eaZp#=^#*74l<|(o|d}G0ri<6P*)#QP@i=` zT@wWAbAt?Op{J#;bwFJg1nTpH3~G@F)E693Ukn0u{UC!{>;d&92h^8?Kz(J9K`rrs z`l;&K;0Px3f6fHDyW19)ZGrKZwG;bB`0A)fRtwu*xMY zsGQta;c2P+9Z(Mhfr524g9@tB1L`3M)OUkG!BU<<1y$t%^?e7_!$F{6_0XV#s`h|- z)B*K_AW*Q7X;48e^MLxH1M2Z0P_U+IP(dyCfO^sa^;8fjSl%_LpjLQ5J>!6SHV71~ zG#gY1xo?L zg375!_k#MR1L{{npkP(vpn_WEX{i?-P`?QR1q&nx6;!PU)NdV7F9(5wwVGi;pYVW!N5GYvJ8x~Yf?(>5BhXd;MAW*QYKv+;YwN#y_rQUEry%_`wHaG|iDyNq6g8H`u z>a8G9u-8IZP&u_!y{D!A>wtPY2o!v0b__xN&jIyL5GdG6;uwN@&jIy*04Utm;@E-G zR2!701%ZOyH3k(_gFB`)!vPfu0tLHx979m11Ih{l1sjSSLr^gXR6Gb2JEoxW9Z&^9 zpoR=Gs7;=j8tQ;53<5Rmn1UMafEp15YUCh;+U#kmQ4XllL7>Kj2BnS5WhT!HYP*OU%K=py z1gb1FsN7=83#!}!H9H8@oY0_hi>aiirRF-I<^_S8e@sCwa6l~#0<~z6LGARk)M5wJ zk|0p0h6a^eOnE^qbwHgK1S%04RBkbq_Ow)m1FA9zRMjyBRqcRU76fYfAcJc0wA2a* zR80`5m7zgtwYiL^yr5P)pwyIg@dIwZP5U35u6x2os z)TSU%n+F+G#^b&%4ydg`ptgkvmD8k|7u0qK)Q%ufr-uiX(;%LW9b!rM#fdbwHgL1nT_IpgxS2 zy1)T-VGyW`LW9b!M?c_k-^C87j|PFdBs8epTI!$&)TIunj|G9c?3jZ3xC81FL7*-V z4Jx-l_qNn09Z**Uf%;TvP#=c-KJ9?IG6>XFgAD2nPfUHr0d;i{sLzH5m7Dv#pssO1 zeJ%*pwV^@f=Dx$8mb%UX_4y!BUpS_qzUY9uJ_yv8LW9!2lFNANJWoq~)dBUjAW%1i z29=xpyr6D$K;0As>gMpEa(Wp(-_ugg%6%K-(BHBeLI&xzt98f9tYHSfH!DTgF&Dk3J>ag zxq!OZ1Ik&Ct_7_}$8Ebq##C-yf)~`IPD}kDsHGkY4N7}FmzMgdr=^~7Ks^}*>Z$Oc zp2-E&B_2@EI-s5l0tH)|hjgFzLN1^#^?-6#S!+S7tZ{eskf3slDK98zm9-YM${II% z4+%>9RW2>{F;7eV+Hv2DLGJraXi&Melo!-X4yfM-fqFSKDDC&TwA5vumU_hj^@ku( zu$z8Z_q~=2sE>O_DQBIh9<ADkf8JtxwO>Po|YQvxNlUD``~Pokf3sVAbUZLaX^g?0yQo) zD1AaME%jMXOHFh@9Tx=Z_|TwoYbh_N6C6-QL7*mu2BjD0(o)xWT57TbYDy5Olfr|V zmJ6usJfNJ_i+a%NMLbAnPy^iy%2~ar2d!SjGkd~<%4ve*^PZM+Rxj#7s~7S3pkoNC z+=;2#K`}KaG$?&uE;025PfN{rKrILYwJH$^nxUV6|eH#WD)Ym+qoHcoR(3(6vv20LV>P8PJXHA|S zv?dP^LmO03H+eugYx4AEsxJuCzCi}{fCtom2h@QePzS?<%4r9j2R)#i zjcfHYgFqb$4=Sgj%R?SeXE`l(I0)3)gAD4s9#H2vpgs}=>fAvF^*s-$^Bhp;2Z4fv zDF?Mn_`V0!g$}5TfmK*4Fbg9_?d52&v=puQRe3J&TWR8Y@(K;7Vgx-ke8oEbc*pq}@Dy4eBs^&n8+ z7-UdC@_@R<0d;E-sBaE3s24n-ZgW809t7%+K?e0>4=88#q8_w*5zm(%)R_8-2h`n8 zOMN@2rS2JIP(Ss6`i=wY-XKu-4Kk>oc|hIofO;SZ)PsWz>gOI%4>_Q|8wBcmgAD2y z9#GCYPd#XzC!Sh9sDb{H2h^iZOZ_0Ir5+n(P`~wn`k@2r@gPu73^J&fJ)oX+Ks^-% z>ghoS^*ax!XB<$^27!8RkU{<41IpQVSP$BFSpNX~4(IeX^NI(Qvm#axS`n)c_KMg) zctANTV)dXEv3mFwvAM0_c+~^S*>_kE+ILw00Q(N-#3@30=U@38&>_8rdYwf!$1 zP|n(6J!tK)9)9g`ZpWJa)dR}ecUTYFcUTX<@38)QE=vIZ?g8~r=k9wW=pf z{~J>6Q6wR>LDs-CFI91#ATUG0WPvfHpUD~b7{ld&WF{N@CPx?}`Q~Tk97^{?9>5pqExXi(|ls9IT+~o2Bm|P(@xoQ9=YmL?Y zTs{NBwq9kivB5L9>^sA@DEp@c1AOTc5psRTSY+_^C}KnWXp30vjO zvO``#f9LT6>^=v~0_f9^0J>3bvwySjfZ)xNbc2S_Fp|84CZie7Ud3K^9UR>XU9MtH zA3x#bdyF=D5z|S==`bv#McmGo(FzoHwU)693e!bgr+Jm~br2j1B17RKR;~RARog2s zw|~{}xO4J{r)nKe)w+!y5mVW!&6o*QJ40SX|El2$=~#qi;2G&uwS92vxo%gf7Ygfx zfBSfq&NL2*0(%t`{!^5K=}_QUV{Bw>-aW>J@?uwzq|>4W##zQiyx0QcuyHXjw!k~zWAlu&0MKFhcQ*Vx2mXBo{+-JKepDWzm&t+kkI+l7 zJ?sd*gq!@h@d*(>+W`xriBX;JF+L+VJDa4O`o@e;ie`=(SO7M2%(wz5tZ&Tt6i|kU zrOSEYg$Ae$1>vC}HWUOfp01YH?Q?Pvq3U+6ah*JXu9q9_A3%1^ET?7`)yxhcS3RH( zUoyVj?`E7abK*V5jbRJK8;>HkMKmSdmiEo~6}w=#3GEva3cks>864{$YuzdzEqNYZ zp!`i3lhNtV{lb1Eg#F!e?ES-@M;Ex9ZU78}0^@eL0VwQ0X@|XfyA$?zK!@XmJ%$5@ z{_XG&nia%`8h7x}__nlm_lB$8ea8KwcIPM-{HG{G?VEaJ-bnKv<9qV@ttVM0%rRcc zHvkiEaI7DI74<{NbXy~Ex~&mD)Q`(O0F=pnH__yQFR7{V0I%)$rL}!DTy1|KRen62 z@)Pn~@M(Dig}DWlOC+PJJB?@M7CnKP9aSlpNh)=x@qD;S{m6Jh+!~c|XW_jybo!mf zPacDD^|y^*Ac2LD0^{|*NK@&OJ0!+2d{@C`EfZ!q}A2Q>JW@gIr7x5?l;VDRk^Xz*R* zz5WIx3O5+hr{5V-KA6FX5s63)nq)8r2F(v>Fdl*M=3TTa4kHC*un-Iud_aT4BEuyH zN0PxYU~uFIG&nXgPGWEZ89W{gPWXTZPlyyr44y~^r+~o|KcK;rB2&flHT&8(<1XXb z+u;uGKc~>IgHqQjmja-tP&zV=_r?(wGGX`;nI5s-gI`tflMl2lXY8> zlS6e|$_-NGl5om5N|j5)Da*zZcSg#?Dc>wDc}_UxuS=EZg;V~9RCz%-~Dc>not_i1nmsELGIOV&g z%B#aE%f_&GM%IQ?zDHVeT{z|MNR{iuDc>tq-VjdtKB@AiaLV^fmA8aben6_cEu8X$ zQso`tlpm5RC&MX!SE`%}r~Eysa#J{E*-OWrk#soahovRAhEsk-s+ml*q{;`wDL*Y$J~N#1 zGg9TV!YMy1RX#hM@^ez?vT({jlPZ5Aobu15%AX9U{0ph_r@|@!QmTAqIOShSl|K_s`PWkA&xTWeQL6m8 zaLT`tDqj~)`6a3H7s4t3R;qk`IOUh6%3ltr{5z@gSHmg)UaEXUIOSKQ$~T2m{)1Hc z>*17Nl`7v7PWg{gleod-;dpPAkNtM49PWjJL<-5Wu|3#|&?QqI}l`4NHobunK z%J+p+{<~E9fpE(IkSaeEPWg4I^7q0i|5K{`a5&{Rq{@$mQ+`vb{8%{Ue@T@e52yTZ zsq&NIl;4snKOIi_KT_pq!zuq)s{DL7<+r8EFN9P6KdJIh!YThxs{FHX%I`>(e-Tdk zU8(Y~!YRKeRemv?^7~TdmqID4id6aKaLTGw`S;A zD*q*%a-LNAZ{d_psq#OmER4gJVdJeemLc!GUYrqoN}R5Sr4Z?OsX6Sr#xJ$Y=%=FAytlsQywW*j)zko zB~{K3r#xD!JS3d*7^!k$IOVZY<>BF!$4Qk(hEpCdRUREqd4g1VY&hkKQswdCl#i1t zPYkDgyj1!4aLOl0m5ahD7fF>*45vIvsysQI@`+OAlfo$%OO>aEQ=TkUo)J!Yid6aJ zaLOl1l}o}YPn9Z{hEtv>38!2wRo)X$d6`tXJ)H7#sd8sHf046V#o2(vy$&2JBmk+??#d4E112Fkfxye-nFnNjG++=D1Ca;v6Y#M;ctK=rr12Fj+xyjZ6n7mqUGBW^^pOu^3GXRs<$W68nz~txT zCOZdU@>;pcy#p|Lo!n&408D;fZnAFxCchvzxqkpAzbH3(Z~!K+|Nr)`1F)&83*WS9 zUq%ZlWnCzZd8|i&Iidi)Fq$yL2{G2 z0i@M}$A0*#Ymwe3!$*t;=YkiR1rY^bO2g$e8 zC13YJ@@;j=H++zMM_tnDgXDH~$<01U?ogL}(+A0&>XO@hkldv%`L+*|yVWJP`yjbT zU2>-nlJBZZ?)E`)ue#*BK1jZ&F8Q7hlJBca?(;!%pSt9JA0$6emptHuW-}oT;sk-F1K1hD1F8Q4g zl84kKkNY6`xw_;JK1d!`mptKvp0jk@G7 zK1d!>m;BWS$#2yqfAc}|sJi4OA0)q1m;BQQ$z$r0mwk{tt}gkv50c-jOJ4Co@&|Rv zt3F8ns45w#^Fi{2x}?7kk|)(A1ALG?r7kJ?AbDC{(&&Ta8Ffjs50YoqC4+sC{7GH1 zs1K6o)FnfFko;L)GSmmj^Xif%e31M_U9yx9k{8q^xet=Rs!NvjLGq%yWH}!se^ZyN z;DhAv>XMawki4WW8SaDRAL^1-eUSW9U9!3llK)eetl@*?Wp&A#K1lwhE?L_L$-mVl zqkNG3M_n?;2gxhyl5svr{;MvT;Dh8gWU>#EI(5lZA0++MCF}bj>8~!? z&<9Dqx@2P?Bm>kXoBALbs4m&u2T4g?vZW7_26f3aA0&XPk!kSwAu*}(_NqUw^Je2}!LOLp-=GDKann-7x3)Fr$7AQ`GI+0zHf z;_8z3`XE_CUGhF3BulDG_Vq!sl)7YpA0$hwOAhowlB-J&_Cd0Yy5vwFB+IHx4);Ma zOkHxM50d57B}e-pSzcXotPheE)FsFJAX!mea^m$%vP{YTare$|5ZfflpK*Wfhtn&* z>jGa((N?OG_gVR3=W6r;`T2LwR(o%o6yeo-+gN*vz6(wH-7%Y_n%-INpxU{%cbz+` zc6ReEajpUDq}n;gJIkF_JI8s~xr=INH{U(y>ULMv&WYYx?j|MWeV2`xB&l9>wteY= zl#ER4q3S_>FGSF}r>X}Hz341>&`VXM@qZJ!S5?H#H|;5ALGYxvsz~$y=E;4k0d?~Q zeF{$y&_1f2)4cEio%^bGcJn=cu9o{r87k|(jdzv@sCLfsuJb@ux7&Hwd625*9Pc_0 zR<+#GyUs&YEqC^=^H9~!UA^l(Ox5jsyz4w%wQ~>eI*(B8+{?SpBUL-Q`R+s4^cR69@guJd%&&eOf? zJVUkfOz%3+lxC?MZsvH`dA6$Mx!!f2Bh6E>yuiE8b5$)ri@fM;Y3zSh zdgPkUxzb}^b;jky<0_q>@S-y-ra!FzBCm5_d{ZfX(P72NE*ZPyrPlYSc@)^ zo24aI{pU4zuVR5UcW-|kCnI`RiiKfc+gIrYGyi{BDT(c$rLiV!WvNGhM6qq z)+D})kW9vt$(OAGVK>ZV6}KkwWrbuikxZ_%287=jlNK(mavTmT$`ux0QoT)D-DR`% z8r5i>@GYb>vG*FsAxzkN9rj-Dy7yx2y}@zV5%%7Qz29)%`&p)wp3ED(Uu-A~)y-k7 zQ;*1v($-w*oz2qD$Su-)_}Pb_55XSHl@3{@@W{wq=`g}lzKd?N^i{6(ZK!ngP3cE} zwnI8;m8#kPoGYEiZfE-d&h-ME@1^gxMfyEdx+L$qMY?R2BII2+O8;&&=r$SxY1dqX zG1m~BYp`rH6zdXd2(?tQByTp9w0V?k;Gu>xHdBT$t5nmA{*_((mvi>7?M44^OH-x& z^3MKI%KrLmoUdYOsO((9**PY^&Q)DIS9Erc%dc}a*UpukofGowT-{P#>2_sj=R{}c z>e~!8x@@7>ye3L@Tw`1}uQygi zOJ(nCGcw9jLuoqE**Pu0&e5)ZCpkN}#_D|{qh_w5-WEfHn*MJa8s!?AtzyQ^TDgW+ z+jkh!@h{hqnQO@2VW^R7$Uz49=NdZY8oJtZCq}VSdyrn6+Ol4++73N)ik@RsDvI}A zs~BskB@9+pObOrtvSwc%AczL?KvmHJ*NVm|7Kcq#;*u;nh)aT~fg4;zhh8feugIbi zSWKhrF&caA-U%+o5v0Qus1zed-9+febEDvaiJNR5Ox$6Zm}|H{*DzDR(JgX$0#-4I7+GtetZNp*&Q!w2_AjmWuP@E|zBc3#L*$ zjv&PE#d#3E7mDmk>;q7lNTVvam?or_&FiWX(Lag zKZBjmDR$0wH!E)%F8VX<{)g;xC0p6owNHp8P#cV6@%*OFJ z*=!>oCzy@r@h)Z?JIxM3VvK?{DikOflq8Bmk!H!SRvDWLNtououGkAj0#A^gY|aw| zC+qUMPABb!B9SM`ySC(s!mdd?$+oNKLXl>vfT?mV6jZ%Yf|7Z%tenP^1?3c;VpFys z<&7Bz@feqG>EU+vjcpOZY#|ismf>!9me-?rNJtN1^W5#NJSL>_RN3?PJXP?#9&u>Y=Jf?n8}J5BPxZOR zuA#WN z#*r!s+1CB>EYEkuyg6?!`#qXB7yNF)TR8pBHIB18(AH8D;jmx#kpmNK4nV0TZz(HH z;w=TGR=kzV>`lov!0T)3WR_)cK9PovG@d5gn99=x8|ge<^mc~b+boxhUtC2vylu@} z%Sy9&Ye6Z4XDGcjtWj|_+kIhj1~!x9-UZH1=I~6xKpWmhbkz~qY!_EiV-L%9wk>Zf z%gp6%1(__KrS#LdKrFNEEm`hjiR*M(H=Ae6x)1SeLAM=m=c+4S4YdzpGd&0kOR~L( z_L0pUiRQo-d^w^hv&F@5FqM?uuWci5W*gCyJwyY9e4-Xg~xdZ!G(^zqpJ&I zwLuV0x)nA&u5@;b+dYkoLXE=xl5u&Z5J}#N<1QC6=Skj4@TxQK?BdlDamsV@pYkre zi>$kpcM){E@~*DB;*{rjJ>@z1PkA@qP4?h9-c9h}9)6Fj2jY~&123l>d*(ak-FbJ} zh39#9!G#{YhpP+Xltb9dDaW3kr~HMy!jD^I6XYr1Xnc92@l|Av^tN$L7ypgM_1Kmd zNKf8VcJ+1MQ*gBx@8#mEV(E9X#JEj4MRInM?<2aomv<)DxJmZmUVg9aLoUBp@S!*F z?c&3mxyH9~pFr^bK7OCvb34CJ=-G$&ap}20%(l+ndf(YA@B8w;vJX3XU%`idyr1lY zarX}6?p)(u+4TUy_5QrS-0gkdU+6Y~4{&u|Ow%sjy57Yr*9Y=}vJW5dfr1Z%_#hV_ z4#?gI3f>RqgXNwd^T9&TA$*8S&jn(JclFl$u3mXRln<4CILLcJ_}?xA1+(@jt>{CjNl_&Mye>3-Mt-Ycdte|l8=;qIL=23 zK8)hHDKFj>GhVwuM)T2f&mZ_`q30Mr#--;Hae?&k*83h_c|Vqqm3=tD#|l1-dpl93{{2iGmN4_#_t}u3aFL`DD50 zPkge_a|*|asbb2Ohzq2bx8C>i%KQ5{UM_(5KlA$qAExrDV&K&m$a&`inc``I7%vE? zB7H2S-5(Zg)!ukfS;H0m`&t6s_BURV4;9n+G%n$z-I~G%;vLQyfF(y?dNSw`dM0dj)^=ibNC$DgS1@(D+o`(VUw}iR%+hh?U(ce=fR>-59&*#hb zi}Cq_{RMo1U>`4Ino1~SJ-mu3CS8BaFt?7%NhiDTAb(JHp%i~maN!~Tkl=!;Y_6%I z+TqS5JZ3RfmRrad%5vd+p&<7#e^`*C5mm#bEbiHxa2MMo-o+m1;pVw;7kd$3B%7(l z7YSw_;g8tNvc< z(H@G7@seUk54mJ3GE4bV*?vd9RIvXnf7ZpmSY$?fdOdT!Jgn#VbFyq_{+uAYj4!jv zVhM&R{2byoZ%kdp9Yfd*w|hF1{(1hqY`q(QUaQ>3 z3fISad_7M%Lt4#O%l7;7)q?$3`KyArrh&PpVTgB zdX2v(n;*en6U?vSYh?3zm1DG{as;?PxJ=Bya;)WRWn*LcTEW;lzD^jcYno2?T_c{1^XNL1{eF{!EIvxmE(2(x-2`9zb?pbBST*~Qh3Yp>Z71I; ztE}Za1(jWVmrW(iZf!T;E$_FU?-usk!}r+s8;<=Pre<5h1ydXBrrzc6$`Tv-yMn}C zzSk*%m&Q&wWafykO`04s@A3C!nN9pXLFRq_zD*`t_Slr`ka<8|W*^@t%WUEM1ep)` z2jaj@TOBfUEtS*;wV&^oW!~cZ1(^@|hoTG)QU~|}dB1n~0b#$7_(!(=kp zn$y#dHkt4Ece2b;{+%Fmj2}~xStKqEl0p2B^W$>=WBj<#|9k$uv%lTc5Bvvt*YEic z!mdB^ADz28V)lr5G@|69XCQ4JpWr8CnIHKHLFObsX_KJ^?T~p?^casC<{G2yGN_}^CCHrSr&YXpO!Ni=myeB9!hceh@WqxA?pF><__|Qjxx5m-&MGZ{E9Y}fzoeYu zXJl7?I96#sW&oS~RPD@k_GdKz>Ou{0IL-;b}{!r+@N4?lSY*D7{v-za##!z!eUdnE?N_cR>9GYt`p7J;U zTee=3|1DVmhyNp6H=k}R-meV5BJB4s|5u2SxtwEao^w6xuvxpxugWSF_*I8W z(LE_TwukGOP07AU!0N#2c$As@YvI z;txi-Qw`cubTWZ4IXgMV^P)>CqV~hQ8GD;$rJA&*PznMQV%T-5T6nhtym7-`%p=1GLu_-yK)q#y>96yZ{#Iv0hmJGK`ksdKO*Tqkg zvIo6KQoYQWQ*qPG;q?layVkj;T&i)1K?uAHkv*?ZTMEyMfhnf++}y~a`LZR-S!d~x zX2ON5{1!EH(>(D|2!zVw&1p*^UK~tuL0o<*N_dVZgst@WAdkb3m7*WElL3sY1msJ| zrd!gM!gNV62%F<2PMp7*({U~`%I<%rL;Mw0@lp^dC5yMEErob#Fr{6@+lk^G9OA20 z#W@7HEZ&K>6yjyTlyMR7DvEb^h`;J8Zfrm&FY+UY^30coR$19jPuf!02?G-**fA{4 zHTM=%Z>@*phC#lmi#aFv%|wXqPk*3#4MG7yfo zYvsFH!Yw!>J&})q*mAZ*Ud~p4V-;kl`_Y!d>55<~3Qk`WmUWg?Z(LdD;tCe_fL!yS zB_XNsXr$wgpYr7-dD7@WQc3o12yH36s|=>H;N3ML-DEMi_s#;-4a5o9=stTbGrIY4sFA;bwaXv&wI!R|77-<=wC{k5YM6%u!yCh!dsNZjM{3c=r(d@91HO# zJ~Q4xa!rzK_2j6SB<4xZBq1%Oak`JB9%ALea;xjGIg6q%21o9 z*~;=zN3`B@ePUder4yeTvg{1nQpiSvfr{cdHCwFq&g0bEs^WAmR8tmzfVLFkwZPP} ziOX+(G0zv3A9A?;j;b=9Fx8foAEqsZavd;rT-<&XS1a`9K^$V~Vo5Z$Se&Kp9^U;b z)bj1BPSLqnld?{@y#ACt4x`;0m#Lam7 ziSz8DsW{-B@~2I>Ny`@Nt!9eSO%6b>bUNpcx2p4%m#L~qD1(Vsou`LjpWpJdofmi@`4ErmZRU{b^Y z;r$kJR8#SXRJqfew58}&4@^DRK{$f)uB#K~ZF03WZB?(fdp*1!VWu~$(1&E;iju0d z?Kk@)10ig$Wq{jxGQYFK5G@9AuZIT$sj@~phOk#00$noTl^wbeayNwcJiL-C522EC z2%<;t$qDUdQPG7_sCkF|o&-)F>gVgozI{-dT$mXzATk%ERTp{6n}$2qCU5=*CC8%E^GHbvK_vh4e`rI2j~rkRVZ?Ueo@n|R(Y4ig_L zOvrbSkpy&w+FUmA0c|Nvv;fmW)kLOf!g)A8plX7yL|e)xKBO&$iB@1*shap$H1V-x z6d$RYNP|q8Y~mnoDNLk;Nmn&-NHlTCVd7&|6RjcBS~hW*wiG5Zz+|YIFa`-Gj6n_) zpQxJ1gbb1cx2C?NErp3TVA`meFyji2aw+d}&SB!9stLMqZ!4Slnzj@svcP1in!t?> zr-`Nx6Q8P@$c9X|Y~l!QDNM8j(@xa{P8FOcoR{;TshVgHnf9`YqqL2NH*_~swrEsSsn2u`h7{&_j7{*%63V%NL^tiM0jNx-t zf9M7Z4sXb#?`ccnPiHWl1%J#ZKs0bn>0wpDF4(7wEO?5x6oOsBbQJ~9g2180Ot(YM z^^s4E6ek~Fc(_?0g!&6rPr5<8o9xLs+ERFO514yIPkym^BAwSOufD(Z&Vw&iJ?IY6 z?y?8J(w4%59$v}0? z#0$*!lOD%jM_u=l4`p;$tfxG_KWIxazFuH@3F9+ls>pt4DTl*z-sQ1;wnH~u??u;p zW!eAHmO{2SnBIb{`F9oBW1_6%e&>DYdY>%&7i}qI>F!$}QTBw2>~U4uzUbOlmi>pe z6texm^b=*zs>pt?D%&4j`^&Qb(w0JY0GI)y>@O;^Kd8zMMAv~N8^mZ!Av*}nAe*fH zp#}4!D#|~K=ctbG4o2_6va%m-DU^qR8RDY6L`C_8s`60u9x5yAX-lC@_p*k$D6dpe zKB;;EHypi(%gTYYrBJ5ZMI&64H>oI}QuTQxdXJQq4YZ|D9t8$h`HGts(^QmCt16F1 z@6ocdiMABVW5A4YQJ$@$d`4AyEP9WXm4j$Yp*#-EI2Yw*D#~Y7mB*v^cv-m!Z7Gx| zfSF)Z&bv@nk^M=0P05jR6VY{|ENh`Hh3q6SlSJA1DzfKPWhbNSWLcJ8-kGeBodRZx zO_p9qbliwmK6NKo$NRDC{jyAP+EU0&1v6C{PP*7}US9rUspI~_h2F!IciKMMh+?n;~nIr7eZVOfWN*8cIhmczC8Tr~(c;@#3&9c(`T~ zA50Hn7d)M1*#cnr!PBkR^WxmnV=3~a%))qP$z!cVTZ*yH1~XeZ)}Si#)pt-eB#+*9 zBS0L^MGv2OC0~8_kIW5HJg{|9{y;4c*WHdo?nU{Yf#cROeL!wdP5lc@z9$eGRQt`K z7(cd(`Qs1r69c(H3HXw~o%&RLx;|5~>L1iUqkj(VQT;Fai;^`UE}&UJOSIO2y#f0q zYhcB|n80|n69VT4K7{uBz~2J@kgQUQ)LLqTb_IU6NLE8pLq$V4+Es=v_!wcUv6wO3 zSPkuTLAsz~K_$>m z2$~-RdqKYhvtWP88r&~}i(aw>T8xs_vfi@8vRkr-bO{+0GE}k_W5q&>6-S#^tZT9Ek~K6Sv}7np`*!F@ zp$8>vajAIe;$_heEHl8Gf-m28c6 zYsvj3Ka#AavP#`sst?*%O1)X?Ey-FsvUFjU`!XjaYuOHE`;{Gtc2U_E%DyC7!$QNVgjGj7F>FEDLbO-P z6)6`YS<5AsYgG>R%WW(7VY!ddUM%llK2WljA6I^E`2}bqny_MghZl`WFB@|4O8D?ftvYPcmlRI-M* z3GW%+8?7~bZ#c$Xr9qXpRobE5S>@9zpG(%NIaT{s#e7u#y;?vugJi9CZ?#d?#-cr5 z?P9e{lC^qL^|b04XmhK-SN#LDzefZ_V84hl5pyEuN!A*=8pUd0-fKkFXjG#q+VwSd z)WEz&)`@Hw*#zy<$Tg9e*P3N()~X4AYmTZpt0wZL=7n0iT6)P^t4^(kwXk2Ub+xwF z+9g?Qzfk-2+M6V6o$xyGbrR8Di7FC>ctur>svDJzc5u{`D9mrv<54T3R-ru{bt>wt zWQ{HtT_-vQZJ+3|(G$?V7X4QAcC?>G{}_Ervc`nP)Q*WpyD(;14B{7aDCR`WX|(^u z2FD_9vCU&U#&$tFG+5-tk z6OK#Px-IH1efL!8qqq{pWtPts?mKb8Ir+7s!2rC*V( zty{J3-ntjs*IMsrjeN`~k`bO!4eiK`2QuJqCd(|5SsLvlnJ;I;&&=bQe`H>ktZfFj zncij=+MnC{wGEK0Z4b2lzAgOAs*;tQRS)gttVgmQNBe2ksVwAOc8%-?*^SXo&we8N zX|!Kw|B`)CvbKwFm(~vJrrpEsUTU`z?df(`+9SU0o3!uL9`oJ)+4iru--Py$9CJ<) z$(oay(>tdx+7&r(=Ai!M{M3PU@RzI|vO4tbFaYi14y!w?k*po3cYLBF?8x7hq1(Ao zH|MH8llkG>G9>9FK9U^~lnjlovNWd80`K}agUjEPf1k)qDu1`{bCpSM z|L!mMJ0^S3n+3U15tTgcBdWD!MLej9iuvtlix+$xF1vXzv*aTzihHxK((PhisEZc7 z-T#_l6!+4QXzaiA5r@^AmHZFZM2r8mpJ;UvEBzm>ik7dZuV}qDD{~#zMGvmGzvx9@ z7IvLph@SYO;YhsQ^7^U6%KPAu=#;NIM%fQ6Y&aGs8D>ktTk%gPdl|th`sk(T>5b6x zRhes%g(BTQUt}kvCx^;%IJ` zzWWi?x=AAvM|Cr8xF1=an>aFYbT`|M`w^mU$S2<9&CU9ulX^P2z7@9Ik2Llcj8vS{ zTV>Dvh~sb3h{aLgN}KLR{w%9|3r8-F{#M&{f8bBL#Ssvra64@0a{`f#v!k0|=qL!T zKlb8xyX@PqYUsokXHu`TdbcSMVusvKA3U7tzsMTg#^8tny4`*_f`s$$Fy%$XGS=ue z2T2T6LGZ;9tZT0w8?hz@AXs9+3W`52b?FV(tbhbc3|2w%$wQW{XDtd)@WcQXG`|9= zoUuAWQNuB@F>6)8!Y78XAo}KS4$celC=TLD&XN2LtGeq6<-o-%i0x!=!y|8EdJV0KJ#8D znaFYqNub4G7bc%w0zQd#EJOhpgI?JDb_x7K*13=cUJQO=^j%rdyB5Oei!)GI{dZXg z6WKk5bRxvbD9mGUnUG1WMsC9+gR>U+6WS$*lJsFlXYt-6`YoGV{M zc&Cla(_GrtV;wf&4x3AHKJUb_d74xE`W$oz&Z#)Bck1{&&8_|TIphwVTXBBx|85$yryQ`a|8aLw4v2Yhw~gCVF4(WXC){PZAm+o}ICf7tVXqI9?!uf9^WttD zzo*==pFd2wOLIfakGnYro^r%qKc?QrIU?rC-5v)|xnip)AF%0nd9H~0qQ&B5-iJTA zef{0`;Y;_knOfS&?}fF$|5b~J?Y+T4a$cyX4@!>hvxnxe*;@KI-b!sxAuT4(x0icL zBb?>fs?a3%fR;v%G!hSFT3no|L~+UgM5qIsr{$6&m&AP1Vx!C_ij7w#YCKz@rPVcQ zC8m}ZpKDXg>-3t$9@5fFHNC_X(_*BaVicqNkBlwY!&;8H%`tnP**?9w2YW<|mB(1w z<3%5sr^U+sx}-SKkL`WwE}ybFojsg<>FK9X)PE3Q!d)`(RS9{hdrak??1=S9z!~l z*5dcy)-=V=wzlzkd2ZfmYem+6vsPO#%qGJj5lU&B5(i zBDO;a^OGdEpC^SUN)NJkv^8?u)`)$b*j~%2z;~lq@aoRi;oYOd(7uO%h zm1!gPiMFJ!36E>IZujr>De<<`y#ee~ZN3Wpd{MqQ=d1xcq|I5Om^0BK8AU+FPx5isV%uewdCx}&VEzaEe}$`b+RLh= zgf?eKv?W+5m!P-|wK*)D%aG>KUtWL5)wW~}(Rmj$r?n+}M=e=#*=lopXD!>jrE9wn zF_WFumhK(5bnVO6{(9&+ZI18AIkwL;T?}b+eCL&EnqOPF&bv5DVdu4_e8(%(>*A(TsJZZy^zwA|2gL&yy}&2Z*NgwCYphn62M`C-oyIt|tG zL%T$`Uz&)ma3{m|U2TjdrL}In>zK3grqNaB6)e(sJlJa>$-XbcL?vkap@!`EWfy{_+R%50@Xn?Vu~KRio>Q;`K!S zPV8fU`AW;9>syU?VoqGom~2(a_6eP@=qhSeNvlfNd3>{HpS?0^xujJldrn+$D^{mR zb(OX1q*W&$s}p6Sy+UdEq*bWvtxRG+6J6OEmrKS~l3}(KyaWGq5=*0B@C9r-v#yF( zxU|A`0}7W|ytJIsikDb~eA)I~z}Q(`HLZYY1?&bDFtLbfd8HLGUkaCNU(bb1*FzVf z6*8@m-M~U-FJ`s}UD9=tT7GHyb%XOunPXYHT3U{2Id&6rOqpkyx;k2(X?b>&@=Td) z^K{W#u4%b;6LU?OZ&|unE#I_!yUF>c%(=O`crE9&oVx`%r_8%7U0p5jw7k1Td8f?1 z*}5bx_q5!*g}JB9zgfBzE&sIqyT$pZ%)tmY8W;QY(_$^wyIYJtsE*KEzwvQ^900-dd{ z8QV_FSS@1GPuxXuriD9*WIIKv6jV!GK-a&JXY63%VaH+3vDJVv$??#|q z>!p=Ntt|SO)Xb;6)4Sw9M2pv%qAgYjzIM zvQx{>0+pSv89GSIP%T3XT!t#MG*dT3%Tg^%3uKnMX6i64Q?*Pju$k(bts}H-)v~of zXRB+*j?yw#%h&>+v94J=M$1|)YYRozx@PV;EpxTZEi{?yn!OXW?A5ZjP-U+&gVS}B zv<%iVxX@*=GK(X%2ljlNL5k!xc(S1Y;&zUWdq+Y7Ijv0CA^m$&O}J=RX2{wR9nw)i%Zi*KTCrdE8l;#(++ zuULS!tknvzSmv&0+ou}qv9qf;Zi}$(4EQ_UY^?}uMYzxuVS6E_FKzjotqJ~^G5?R) zZ&(s$R+5=mRTjiz&^BWg**$27vr6n)wCh=Ab_DG&EL<1HOu8smMb`!G5LQ+9B-+)i zn(i~SCs}nr3p4qJvk1R*wB1<^zj~ZkeQ@qEJgZ*nG8mjYIqp!i>#jEGBX*2Sbbw3wBuO=QyFG5)n<)M@1gyiH8#J^ zOy*szNl-Or3QA^8gPudXfi(**&P>78S@U4%1}|eRiuf^8krJ$Bk%?#@Vy%i?K>IIC zD|(WdivGmXE#EMchAcA_@eFOq+JsJEZ9^}!tm3O!c8PY( zRH74WUn-HAN~NR2fhOkkQ5o|(aUpBE;B{r#cJvO0sduFQL zncZJ|5Sv;jhfS-qjG5}Z&SuuZSnK@GW<~X8v!f2MInl-01JT{s-00g1td07y z+(swZ8;!28t&I<{x0=*sZ#S98-f8kZ+un3M+tKt8+u3XY+tut{w!3*pwx{_?_HK*8 zY;Vgt%+xZLz1Q*;wA;#?epwt+jrS_Sz+v0)@XJ->jU=%&N22&hxzP6 z$6oAw#|i9WrzGU+CyW)1*UiyqvcRCaL5a*ypTfd|l2{hg>7QeUpk#1*{Q_1#CQAfGaAs0oM{-F)0aLD{vvw7I10cic8DErGpDK zgoA4huB0ItTn4xjhHc<7!Id_=46Y5hQpRfF+JY-%w1CS3$Bm1@WrGVdP6gKvTv_9O zaP7gBH(J5vfGcPG2V4hm6^$psbp%(zv>se1aFtCjAEM5XGe@xX2)iOD}LWg8jkW3$9ks&)|B4s~J2A z+ z9t1ZTT#L|c;HH3UUc4;0`@yv;9sq7CxR%AIftv;{z4$skgu_0@tr%P_xJSX=Q#u0N zW8k`#-U;q;a6L-D25vF9?tBQiC&2aM9l<>bt|z|$?kRA+`Pbl{26t~68ru?Zeag_- zo&k4XnRVcng6mi2X>iYi>s#goxaYtPDDyG6W#Iak9SH7uaD&RW2loQFfn{F;_ae9< zWfy{54sLK*b#O0%8x|GDGT6u;Hr z#+0M@y$Wu0xsSoU25wxrH^Hp|H@18rxV7LWl)C_K9k}u37l2z2Zc_O%;5LApSbh(< z*TGFGzYg3+aFZ*v0`~^EsTE?uZ31_HMamZ|xak!sUvj}stN0?g&ERHMd=T6ga5E}J zfqN6&>`ENmR&cW_Z3MRs+yj-K1@{)XIh8Ho-Uc_X(qG`-0XMhuBjC1!TTpotxEVbP7 z+@n=K2e%L0;wsz0eE{z9sSN#KUpM!g$`X+FP!95>AHogG2 zygJ$V65NXs^T2%tZbif>a9@LasRq@$Z@{gLpjvkX+{-nZg8LTSD>Z6^I|^=94XP#I zfqS(E)skc2R!24gcO2ZB$XejO2lrYe)utc7t&61E^dq>nHEG^XfZI@$=Itc7^);#P zo&vYACe_{3;9jq#2X_YCrkdx$odx$sEwb?wxZGM~;~Y3^tzF=L2Dhcw8gS>qZLYlu z+%Mp^)?Nng0=PHp;0PG>E4a7nR04Mq+_osn``^I5Q-|{YcW`e=U*L8}odx$dxV=$_!2JX6-RKx_SHQg=T^8KG z;NFX#0PZTd52AasO2G`=zUb}D5Ud0DVf1Qne&F^;p91F(?xW~~;Pl`Q#6*J&0QX5u z8E}E%K90fq2$sNo8iVx_YyfvK<}^4XxI;0Yf-`~pEEa1a*bMG)4Aw$$5V+4{yMPM@ z_hoETa7Dm<5jz81QE*?!4hCld_f;&`esBo5Be7Wf!NtIR6K4b$3hrp^Z{Ui9`!+5M zTnTW;;!?ns1ovGW)?08XaNoyay#<#BcRUWq{a_C6$2c7KgUf*XA>I#MS#T%g&VdU9 zcOpIwTsd&3@LQ%HV!VXb3JG-1&qW z;HrT8IiWwes^BgpWP_^)?w5oO;HrbWnD7j^2ynk990yke-0und!9{}mt!`IvHNpK+ zw;8xv;4amD5L|6=|EoI|Tpe(KCQ@9Y!2MO1;t~z+a^hTYG2s4590@KK+~0{UV;I1ZB2bT!WFUgFviX@h$(vL9SaaK%#AgKGsYBsBtD8o1)ALEzHC zg{Hm)t~I!lsdK?)fGbgtfy)F}I`v0zZNQbP*BxA2aAoQ>2A2hn*Q2pzgA1!iV`~Sl zY<-GLdvN9JQ(SVum8*XQTnBI!>+b;95nP1^lfZQXSGhqCaGk+bYDnYl0~l>jth`qoLsL0avy0@8G(Fi)j2MxE|oDH)##7C%DKaQQ&%ktI^~YaQA|%)#M>? zy}{LN>Id#VaCMrT1lI>#?WRwG>kBTr>11&Iz(qAB8~wq>HYFPaz{ND12W}v^_+~@E z4FVU}>;$;M;OaKp2W|+sgy!SG4F#9fyeqh2;1XK|f*TGlrTJNKBfurMNCh_%T)h?* zz>NZz+NvbD(cl`j{0rO|a1GPSfEx?0NvnUsjRV&>Z6vty;F_g%05<_#)3ih2CW32` zwgucIaLvTw3}SaMQqLq#p-29bD_yy}-=? z*QRwda5KSWw%!eH7Pzd|tH8|$*EXXXxH;h3WthM{04_U&=4~#xoD7<`dEnY-mIgN; zT*r)mz%2mRA(Q6lL2#WjX^tKO*D3QdxP{=lW_}CqVQ^jA%mTLv+&yjjgL?#Ax3&S` z9tGE<%^7fyf$QG#4QaP|JIm44Z}msubn|X(HE2t7^f>nG)t2UHG4|`3RS(<~;Cg3O z1otGkd$S$~_Y}B3S>wSy4eq|Iv*4D1>zDNrxM#ri&29{CDYyaIRlz+Au7CE^;GP3F zD0>RHW#9&8Uj+9&xFOkx!My-(aJvj}FM=D^E*ji&a6{Xz1oslS5$zU$TLEr(ds>4p zgB#V3*5FETBinZcw+h^t_6@+j0&aBsP2g688`u76aIb1DJKowI&c$n-U7EC+?1Rbz-<6Gxr0Br*TGHAIR$PbxcfT{0QUyC=^Zk_Z2~u~ z!y0f_a5FnR0xlQajE)q8&ERHtq!?@gH;b`OJ@f(kK*lVl;GMy{m@fDL?uUgk9sXxb zirgB!pRo<{UE{#uPtiVuKNevY7Q&3!DuEkkMphavM_U$c7~1mk{vo)HR+)w4FI8C} zs|LXcv^CJyL|Y4O9kfwsW6;K;jYpe+7MJ5J32h46RJ8TcHbC15ZDX`e(KbWd0&PpQ zX{vX@j&-C#{j@>7*z1Uof^( z|0-jv2wovrP4FtgYXDtyf))fV30e`P5u_8eCddG=H3Vx3))A~H*Z|Nqp{>_xs~K%= zBzS{h6M>Z=mtZr&7J#lPZM{jbm0%meTLfJii@XaHaf0s3ft3}dsU8cbhYUxMi?=_@mRD}4i|&%hl&eSO+$Mle}Fg|Xha zx2BKO*JP|Cdaw=zqX^m)bS3CPFp*$5L0^I~1ijFg^`Wf^1fvPM5!aL8UV{6Hn=EB8 zHjTEX5=^0Ar_)v^g0Tc$2*wf2lu&TzNeda9Bh6!aNpE1RtyG2JaTZWLAc6%%2B0`j zBA84th2VaIsRYvi5+^7_P?jK!pd3MYf(ir`0fEyAW)RFIm_;xfAeE%8IkZ)pwjLmu zOE8aMKEVQl2MHbmNTq0NA;H50iwGVec$DBVg2xFK6FfoiB*9YzPZKO5c!ppp!LtO< z5iBEkp5O(77YUXVyhN~q;AMi91gi*MAy`fDD#2?6YY5g7tRq-Yuz}!pf{g@k5Nsl_ z0;CcI#p%~vg3Sb52;L;vO0bP!2fw9>Mzr`v^WD z*iY~w!2yDg2tFqGgy0~-rv#r793uFf;4r}#1YZ(-MesGjHv~rrz9l$H@EyT1g5w0= z6Z}B%Bf$xRlLV&-P7|CVI7{#o!8wAT3C$&V6A_XKT?C73`knP4gbh1ib*=10T#lLxbq zwjKfKo~EtG37#ZaLhvlX^90KYRuQ~Pu$Ev0Kwm~*mg#%YNy69qZ*=;j`Y&|))A}pXxu;=?~K%KA;{&^hFsPLZzx7!2p7R OC|bd|1Y!OGjQt<<#9R*m literal 264491 zcmcd!2YejG)!%m7y}OYt$-RPX*|;K0axa*ZEZef>D!G^QNjk}At69Ybj3I=C&`IwE zLINZ}LJy&nPy!(dgg`?0LMkDUkX~u|-kUeOx4RmxmkaU_ta)$ty*K}v_jY!6Zg%F$ zckX#WQIt6aC8}bkkMxznKT}avWqi}VOi#M4vMkflo9^yNwUyPSTT@L(*LF7dwWUo( z2l=*4V;TH2m58d0w&gda5B6oc(}|v=9Zj3kJ?UOkF;yiBc2DnVO0}g_WkMY%%DU4n zZRw`ovU<#}&$M==di%Q5i&Z7kc(ga&qYgQir$(2iRc-EmwS4)(l9aAS^=L+|j%dTw zqWq$Xsy3n|QFJh(mS{tx3pL1}F7jtWe!0o>GdkoKYa~BxVxp*MIM1IJgZxsFzaQi` zQvP-m@~67;i$-vHobh+}2 zPRZiwb>(k# zKue0WtUPneQ$Ck3bmbT64j|nQIJC2o^0C7DD7SqhYk!<8f1@k^R9Aix1unN!>dN2f z%Ae}WFUrf>pXtiq=*pk%$}gfDfZLzr%HQb9U*O6wva=ebb_8VOJ8(sO^T=_*TE5FN?ztNSy*OgzCpOtT> ze7yzzTY&jR3(>z_Zuucu`CcJ^2;~b&-U9iD&T}giWfcqxTs?0hC=`=IZ9;1~xTT>e zu~RkHG|pV0CSrN&++Cx}p`Y8`*jtj?wRlJ*F>c$$#KL%_cGt*+c1ln3jM9BmtJOYz z{Aly^or_wwuUlP`*t0|%l3?@Ocb4y4Gd-Fp)3vkuV&xn6kE=YieMAFZFNz#I26mRk z^`op@-8HvqXnr(Wa;j!*pEAtUs}j0CBvX{y6EXCm3#XPurnfY0sXMJ~M@etbqH(9q z*s-W3lUJUYI(EVS%vlpBmZXd#Gg70LELZpIn-7khwQFwY`hv4t3-(kV%@pq+**g$LPL2;N%V+bQj2;$yYreyYE_A$ z`uw6)bwhba{h}rFGvgNYt!XSBwR+s*mh>1lf7T9l8c~Q|yT?Ia&6)tL7JEeE)tX-9znX_W$B|8_C zloUm$m81${W+dIcUNx!@EGk`j`j|*uKRbG~x;zolBIgvBR4;0-UUY0r$GFOt8PRAo z64AB1NdC~qL}F5BtfVBfYe9R_v}o<*6sy*TMvBT;t5)rZaffG)S$YWMGbq0yvbnx0 zk(f3-8XY|)VeH>s(7biXj>=dxvU_MzTyx~X&h{z7&c-^`gm^eoH+tcSNaP$H{4-Ur zUY#gOjn+0r%QxmH7w@g9T3#|SHAb5qHEW9!iMjgHY3A%bvs<@s8E18jnzJ9;b8B@X zF^|`?WE|9UY43Vf-!gPjsZ~{-SfnTEiMT&p2*Zd>QJ%A*Ii z6cv?2H0YBP|`)vA7OG^OpRY+klv=BWH#v)fy@99uCQ4`%f zd1HLtn#nVZi?pKg%TMbZwRG?9b*!jy%-o)3jmKI##@qRo+5BS4k8}A-EuYd7eOj&A zI%;v_))Bpj*$$P}SDm$@Z2P>H-Nz@HlM{Iz2P%%Wl#QOhzxH_bD0TV#L)(v6LOtfD zmo*wg6V-Fem+fFHPaj*kw>EEkQNh~ThpQ{(UqTRX?k-J8lQg}4N{ zg($bMXH9Y4{QNz$4=yWa2Pcjly*IUb=E_++EBclJ-uznCg7(TAvU_$9^baV1aM@~T zm*rruYS^~?9dnyA$MqvDsTQK#`rVc3`hwCUZ1?P=iHO=bYwUu??Z+p1b&TTJJS8SZSld> zh+#+Am?CXx3j8&CapSTPy(1I)QjjYh)xNE=GZ9ItU85=+GkM3htlc%cyD5_K@@g!h zC1XXRBb~nq$E^Jv= zYz$4IA3brgR4c(a9y9+?>%?PuWuq5o_^NCgaO^a&1MxG%8nU|* z?rWx&4(L}XCy|ZonG+TsT!VHK{r!1RiH4lmu;H4wP5$?5`DLQzhvW7;FwaT=7Sv`=X+P4F>Gqt4!D0r zd_lZ!#CTm>F>?X*p9iZqEkB&qW7&A5{#C^BBD-DpW=6D`5C^Ugs@VL_-LtVj8=1oUeD%0d&@Y{p${V);`uk4wbAs}xdh=O1;!3X@)?2rI z>A~uC>`!}ISDXcL8L{h=&0n3(U%wXRQyWj8Fh5X|QhW7CpV5?Ni5U495jCcP(yTR#3X? zbk*Q;c>nI)(hTu$k2}}W0*st_8N4nZFO_|>6&i1ZMTY7z0Z>F=Or_{?y(bbMHP=8KWu%-aLRJ=1EFRQyrZhrRAnFUR5UVPaR5?wWT^* zVaDW8=Ye$D+H~)}&gNCAj^?&>Pib9e=YhU1Q#l0+4Hh+(5>?3~c~vPAlPsm(hnm_B z>}&3Z<|u{v6o-Yj%!)L(v?N=)T2ml&nySRR4>=hC+as0+k?Amp!$s0yvCwllgV$%N zip8%3=RpEiGij8V&5;P!FVe=1RN5lQs!Fk^n64%+Gf!1wydci|?R0fvQ44K5$g0XP zkDVU7)=N}{aZ4fxV#+JnWJ@knm3)#ESsrYiPGeVbY&P$~hErTUJ%Fu-V-u{ZjOxJ| zt+EZ>>E?7xX`;Kk^Khc4r?UwpR{=ivRa03FesYNb;Eq&#rlYmG6DHn{^p>`#nz}nn z%T;A|ogL-QlpINxt#d0t*r&T&QcXCKre!+8v5sCUPK&qV39brLpF|wm_dampu&Bh&vQA2dEjgjjv{C0kX*Z zg2_6cw_0zyy$dQefK4cMxMP!hi<%7bInE@iLrsf8sJo{;*?6=I9xYH~tQ%!kcr%B2 zC3&l3Xz^@E*3PzsG)NFxfrc3badYMnFA>;CCYfsMgOIHgy*;wn+~_+byVE^=ZM_)P zAPTx}QM@07D3TsgD8ns^MUrU#@bw^QnG#zSL#AP;m)VKu+|LGC6Sxv0g$H$ zL%P(KEb>aGOF^c9+l0rLEmZ6kf-4{ett6g~wwSv$#U)1$A8iB3;Uz~7AEg7x;U$oR zRtMw!acT>?Tiw0}lJTll4avmv<(rbL;4zTp>ed5#er?mH#P;O!nhg!`@G8KZm8(EF zQNJpQ9haR!j}i-6BI8vJRc^yJM~0De8_q}Rs)oeMPu7MZkC!Tvwdx2x#+h6!b!N6qUl+Ul{ zSX}fvO=OZ?tRoXSb?cJ#JF?Bfy$C>|rG^Lz%!2BnUq#OPb#+i%yI%Fx>y{_$p#8G~ z)S=l(>KhUb&{I*>Z7uAHMa}JI!>nw@ZO36QHiYdIfU+S`y@qFaV;`zyXJ8GXc$>{y zjZ!ARKcG4wV7D7_R6|~QxJG&+%DJ>F%E=V91t~ib&qYPV6U`$&R=Z*|#J7lNn-TGB zvpk-QYS%$L`}%Qz9`-x_JnVP;d6kkp?05Wf*zfrBu;20LVL$H9%l6~_bFm-qpNsu? z|6IT+$pxg6TSRUr_Ubxd@{y@Z09qW{!2qB0+#0_G zU2$^j`c2EB*Wh~gt-l+ev*l~mB(1gR=tx&M31_pc$aL0>bQWRl}dnhhw zYKoZPs3jU|*Vb%G*43;8`!(4*!`V}kc5d_`Ce4Mzsu5LRxhJni3#JbuI$sJWb7N&LFSD~YJv(SQWc7>PS z;ANqC-NMkM#kjPI=Ko45fq0oU)%AYHXG<4PbLH5pp-3JE=K2ww^%*wREhJv_3RQq` zD$OHx_jUAU+S6tAz1@9Huz)JnR-I~VtA}|{Qw3zv#?H>(p5E?Mm#SRpMi4Md>3)#} zvoIOu&haQV9PLU6Uv$G4sy4vIOl?p%$JBat%aA-3+#E@Db+sK;l~SnmiE0PR+tnS# zilXjR6$9pPnwh#=U5D28sLEKMI!?%K>g#BLmMS&Xy%14r*Dv2(S5pcr-TXzlWucTt zwJEBm)Mn6WPB$fCI>1s};PKX#>Q1$%VX_U|poe>Er^}z@VW#d=Gl*$FJhQSd?EIps z!lXg8HQh@tSCuo}{t*q|-=w=ieL=(24z)9;wyWUm!gNOuET>B}HKlucGL3C%Rhj3u z?^6x5+O77)pb2^*C{xYQ5G&n=sG_c#zZ=Vk)Wg_1FpI*VE%$XcSErixr6KMo`n}RG zyx|rxNe9Ho3|v0;-oBOx)lu0jFJ4nUS9Sx#gT{>zSW!4o{cm@81i7Vw71BWUmxhN^ z9)wl0vCC3F`|$lD51$5;3q zkG!oQb$o@-@yOc>QpZ>L9FM%MAa#6&&+*9H3R1^c_#BVCtsr%Lh0pQG+X_<0SNI%{ zysaR0e1*^P$lD51$5(Q`Mj?dG`+X_-o&+&O0d0Rp1={Y`6BX286Jw3fdOIn+XlqN|KG)}VizjX?;~$3NWDMb z=Y8aD1*!Mv`@E05tswRO0&u7M9zk9xAlcv33w)kN-d2!$dI7kz0Owo|_QB#D?1h^x z?JQrZS?{B`q*R~x7i7JUq(s5z{RLU?BPmhvd4ECH`$$R@eBNJ>^*)jk1)uj9WWA51 zM8W6%1zGPSDN*owe?iv!NcLA)=<`1E!kI`)6nx%anDsuA5(RLlJH8fXJ&mM9!RP6P zSx+M=QSffV}O?FfPcL@km2Y6Ez)-eaP%pAmww;>?I(E(bf17TyNcso4f*M>`uHqbI{ z2pgl3Yd`PThD(k%&@yd^p*U6_R@}h?O6a{`^cw*Q$A~=Q%KZ_C8MY46l7h=2s3K5k zs>{-T?JE+mIqLG@D~Fi!v@>QnI`V)k$Dk4`{aRWq?e~5YuAoC%8EOckA?~2-?CZ6( zKl=^2!meB%cI6O01+LYw+|EDzc3km>3Nk@T65_5Tnt^Y>ea>d9 zC#pyQ;XI@#RQMF8=ns*W=|I$ZbzC8dQ`ukQ>G3P=Pl9| zjyQ)Y(}Cdf>bN2gr!i$Z5J-8rXczij{S?2xE8=igQ>G8`<1Nz_TsW~Q(}7TdGAnqQ z@Y#b`-xX6h&neS~81d@30tlx%WjYWImc6dm(#!l7T!DjgpAri=t;rwUumaf9{Y{Nm z?G6WNnE`(k;S{K&Bab4S^z>8}GaMax=-|AkSH~4Pcu|H8>SIC0GR^6ZW=n@3+r1WC zfrPW9G7AtNCR*s}?6!1RLgqE#iX@yhl^K9wVc2)!3hTq&X^6)^JV215rq-8q(K*AYT zM@Jq=IH&3@#}!C;QC5yWkZ_*WDMubiIJ4?4#}ztwQC1EFgjdHEEjaTk(*gH;bzHH5 zldm!ze{A5Kt5Y9&Y~U=bw;Wd-;6+(E{y4yySEn3#9N+}2ryR_%b&!^ngVU{E9akLS zMVXF24sZ(ADMua$IO*yw#}x;7QC5yW4sh<(DMua$INRzi#}x;7QC5yW4sZt6DMua$ zIOpmu#}x;7QC5yW4sagUDMua$IP>Z)#}x;7QBn@hxO#Lj!!8GDnT|gWa6;D6k;ef} z!FtPa#Q|QFmE(^CoR)RUk;ef}#Cpqd#Q|QFmE(^CoSb#ak;ef}$9l_g#Q|QFmE(^C zoT7Egk;ef}%6iLj#Q|QFmE(^CoTzomk;eg_s&&7%V}`ARw4@xIiS=N^3`a*E2RIq) z)p5lEUX+#Nj{}^bb;^;)0Zz$!%W=g4UX+#Nj{}^hb;^;)0Zz<%%W=g4UX+#Nj{}^n zb;^;)0Zz|)%W=g4UX+#Nj{}^tb;^;)0nW^N%E1g<2Wd$;I8W=~fHn>GdeSD3gU`o z41sCBUfA&wAlo0jg6%kbXlvmXN&@CeYPa*dys|4KP=B865m9}9AU6|TGpn6T&Bj1amIKoZ34^!qFfgOWSbV2u6eL;aPLP_gtf}6&z1Vx1ic&^TjI%6#s3?EGt zxosp{I@_9IwQaw=Qf6!`Z!|z^}WQ z(FSo)=&KPlTCb$h2EA^~xWc#+TlvG#%1)b5vGAaDa$K#-Z>n??e2vr51PjHXU7GQh zhse%mLJ)qE?$=K_;_zD}7hjciT~JI&uKAtJghr5 zgV_T+*EFZ0UlR>N)dv4=l=xR-GN?FT12E%i;~I3{7x_(?ZT=+A#$dndcnNaACtoI? zT<3@rI4&NtXW)qY-5{bY$6OA5fXpy6zG~cv6}*Wf&i3RmisB#j*~4l{JJxy{3w!o8 zfzjfV4-5%(J5NNOt zd(40mfPiHYOsi$aH;lW{?l*Zb;=UuWM-c*2l|2KsMQ%L~G@i#5I9l)NO~TkdVsEBE zo1zE+0JSv>)vN1p?+p}YJZL=GoCcQi>>#R-Fgm+ey!L43bfu2sPP#xa1 zsqy=%&jMLO-T%?I%pRSh*ysXvR;Oa+$ITssF>D zip8c%up9{9T>9^)#FWdGD^U0sAYluaww-kp%j)Y*hmuZ&;EK<+o(C~dRk zH)?Ob#FQ(Q52MlFaib#JZIl_Wk-6XV0iD>4iDnzJAe}v$nDPb+~&7xZ~DZP zPbi;6vv1qJ6<54=|I6)06h1;gyR-=uzWBM_l)Zw0Kc##cEJqC9Rk|*DOh@v_v%IB2N zqp4z?p`wkae71&>t>HX+xEdJqh9u>pwX2jbptaFFdPKIjj$_H(INKa_?h0@Zwphd<2_Sk0aLCgY7tXzAZiIyzCzR)O!+ENXENnR zqNEawk!M z?=GUYG36UX?O@8?MD1eAH;LNAlzWKU%anVGYGlfNL^U(zexh2K@&Hl$nDQV|`e2b_qrhJ>IZl*j!R4-E=CF&4U9wX`qQywSkET(*isAEidf~ez6d6KB} znDSks&S%O~L|wp??-BJurhK2M4>9EjL|x33r-{0hDbEmfIa7W})RjzmmZ*;~QF@?)Yt!<3&8^*N@zK-5)C`6*FXGv!61zQ~mSBkD^``595yG36zq zZeYsKiTWy2enHetO!*~IUt`Lzh`NO-zb5K7ru>GeJDBn^QFk%rw?y5|lvjwlhbg}! z>OQ8tO4I{Pd5x%tnDTp~zQvS35cLRCUMK1?ru>np?=a<0L_NurKNIy7Q~pBK_nGon zqMl~T--!AlQ~plWkC^fgqMm2UKZ*JYQ~pKNPnq&>qW+I5{~_unro2JaFPQQsQNLo! zTSWbaDQ^??Tc*52)bE(`U!q=PszTHsn5q)>N2Y2-{h6scQGaEsLDb)w8X@YROwA+e z-%K@$dV{GJQExFdO4K_{jd3bZVQQQxjj4<%gQ@vMh>9__kSGR6gOQ;3?*)KiI?38%Xdbvjcg5;dEtlZdK--Q9_r!_>({&132mq82dq zG@=$Ubt+Lym^zK9GnhJ^s56;5gQzN|&LnC%Q)dyif~ltywTh`_M6G7(Y@+IzT29nD zrdANOfvJ^5ZDQ&iq8gYwm#8gFok!F*rp_m72U8aiwTr0>iQ2=|MMUjo>SCfAnYx51 z*bZeWQ7ue8gQ$H>T}IS?rk+Vu8&eZRbuhJxs4k{f6V=VsMW+NBI+1ZYl%9})YU|t$J8}MozK)dqAn26&@S9YCHoZRJ5JJWl=Q^n588o*>eiFc z6nyN-gtA*qlHlY41hZROlH8;KIoxQ7q)r(?Dk~vH51ST=4L8Y5pip2H(UQN4d{p9Z z3lMZR*Q7!N#j+KcA*&)-^KZo&Y?N=*hC6hI60@s35JYYb_wx*44Y&CWA%?quh7z-_ zNnH=^l5II@sCl*!r2O(pG2phpk2jweD6kBv~4)cqIJUwi}npCELu36uxR6O!lISK z35#|P<;G8XTNlx}ib?ux>Lb6`fzoG64@MU)(Jpn#v zW6~4gqm39zXuuZ6Uv^I<;tWy-bV7D(U$P~8+|n+-V#i++lRdBO&3dY8_$I?7CUd?JbM_u4NmyC9Qf09Jl$@-2c%R5nr+2)HQSDj^!df6vPT zP8i0!o;Os0)9HCjV$&qSBuu&XV(?#*N_z?Hmjz)hV`STIWB zUe6>byMIK%xb5)?%XM~!KB2kns5YPlUHeF%uxQ*h+7&wi(TkGa&=RV(Vld~9>H&pBFz`D>9?oEiFlCDz zuswW_umRC$V{brUCwj^`8+4P41}rKYm(otc+0L8HNIfWIf}cvR&A-W%v|se^2_9ZF zVDRbQ1si7#0tTOc(SX6HUo>Fw=@$(ceELNL2A_V>fR`t?=m}q*`U?lVJoOh2czNnC zEZSGvdAVYNFbBLm^|u`G^3-2A;N_{maKOuxTNvL50$!f{q9NlKt%i(W6b%`_C>k<; zQ8Z-yqG-tYMbUtE?YDP4^$QauV-eWs9k-Mx0a=%ZJHgZL>LerU(rlUFF3pz0M<#zj z$ohR0!fv0ot0y_xIL{~N8o|mQ0Vpjtw97?s-pwvTnEER`?_;YrX6a`6MG7 zNq9ESCo$PvpS_=cupwug{a{S)$KgPQWgm3|q0a8j&;2RumLyyF6Ed0ey*vApoa{;L zZ1_(iGLO5?0T{R?vd04qjLCay0LjTl*8al;NK$soi8BU*1z>bU0RhIrO<3N? zlw(A_pDE|i)ekV`I8hfe6FD$_G*M<4n1bBtPku#9dAB+(@Q;NVy0lKZDDSvLVSo8(hqcxWQn# zp!s=kWN(6X@ZHUzyxyFRm#>CJYD+R5ncg$J>vy*>^NZ%SF=d7MB`7|7WJ1F}IMWtC zgfPwPV#;LmOEIMy|4hX{OYzT{_-6+GIUWC$5bd8c`oR|A^Lqam8kG`|@$??K@L$2=T0i=tzuI-fTBmzcsD;Zpki zQO&5zjBG{ivmt8XOy{N)o_pPp>V_jbYK}Ce`7zk0`4ALkcLda9nC7=&1sh25qcO;D zS(D;m5c3i9(U|#d^D(Bbg=0&=3EzPVX2s~J7t?$aTtnxksLDe3xf|jv8214oBFlZ2 zhsa{)Q|9+#>Urk(1+r9M53Gg5MVZ+m9j`8C=F{dgG4o;bhu{P@kJ})dCa#1P z%j|)t9?K;JUs#|V7G6ym&eQ(O;{pZY`0;yYctK4V7(`{ zc3ZkV4d1)adQbXTs;RTB4Guj8kCfG?4?UQ(Dar0&K6^MQt#&Y<;$TVMt71v~K18h15r#YJ@ER`K1mi37|JS4_^J!<~J{G+N& zu?;v6pPtUX?xu96qouQ~o|ABlG2A$RwiMWJY^2+z;>?#?T%!j!-rr*8U(CNlV`tjw z0CqeZXNp@P$l?Dq{}lsB{|*JI7SNgI8}J>h4S#?`-%ax^RVi_vd;>`F7I`OXzHP!D zZ+Td)re6FuA=^I}+1!~-_0YEk8?wvd2lfM2 zI{TG`*P`otX?nU_re(#<*DUavH&j<-+S*D@3zqL@KULx}%r9U|Sou+lS+IQSef&nZ z3gP>;p3GTkW)&NELEKqGnR)?Tf`z#eewZ?|Mw;6oo-J5IwcR)^1_s8sq7yNh7OcB9 zq0*%(T#r8B=M?W%15B_^iCN<dTT@6T4!y9<;BKb2&NvE7ZbG^mLU_h6&4i}wH==3)Ggb`pH+1p zN%x2ozD#Q;v`J&q@`?xp0=;UR>Oyd3%uRa z)-tQnYC?@>cr@5;wKdZX=ZaZyELipfMxMtVxi4z9S}?8{>G-}2;vvjPB@4E&xwqi?nXFHg0=-irV?%fAty>V7g z4CJ9B#oeot!2ba(f*l?e^&kaakwjJ1xaN?G=XlM82icIqzG?bcZ_sM6V< zj)@1HQy0flzb9nKo|)noiaI9-EqvTk>MdonrEIa3t(LOQQnp*l4j6vfO`089fUhnD z2RleyS9rr-6tzBNT?`WTu*KPO^gwSCI^IiT)@9fam1dj8cWY%Wg2C<96)`Y)rKRk& zls%RL!M4{@QkK$aDNUBrY$<7`UPw=X&qD8HmkKvD913PyFnW(6-QJb#I?&6kFTkkD zy2^r4yV01zVUhcFOx)C8w64X+2aK~L0KONrt~2KXZ0mYenH(4|b#Qhd93u!3GurwJ zM$A_sVm34DCeT+#SvNzsS_-4D&JI4!1fP`J?fc$%7dqCjTesko=2oU&N{wrSf9T}-`#gzko+EeMIr_t52gnfejBe821QiLb1t^W@Q5j3eM?++QHw!K^1h!hF$!@wtTq4?4MUqiY+H z|2e$r#oBtx`X08%_bmlh@_vfYJj2w_67?*-U)Ujo5aE4uG1G3co`b=+^}KHc4;M`f zM&$V@+0+ADQNtDr&CL2K3^%M7tQS4^tM{Yz_o_k@te;`azho(}Ao(h)#xI$A4N<=a zz=#dDZ-(6zI-2$&x|gZ3e~WsjT1tkgUn1$(ECtpwUr)^IFpmO);LAT*$^oW+m9qaz z?<@Ge%suyaGWHKkfyK`^lgz&@1-5D^vO}5QzSXH-=qTQV26jT+$>-g~+fnN+>m8=v z!fiwqFn~KNbXax?F=0__%H#2`QJCW?YwOvRY3E#KRT){QYu%Gi$@ZtREJWGMOxD@Y6 zqYGJNLgW-|Rd|RbDQ_uLA0WibnEEhL33!0v!-++!Arh?1qRW{v#u$r=FnI0CwzQau z9SE8Xy|;b@-qGi5HcIV@UUhqP6--k_Yw^i>D~m)UF~kBhq#YEgFhiOlY6Eo1(GsRU zLN%#ZmD()apq7@kY8HvpsGDK-ED8geE|~tL5@BNX08u-c`ZyK4+frcOv!1f|!i*~2 zM(`ELlOzB`i*A^~C4p9^evh&#67m(M>Q}yPr^A#MECAqDw3V=7f8wPM0(FWy-#i8TT6Zq0>KN zDMw%ungl-1)ZdZ7CoSbDQ-4p)XPEj&qCRISXTh8~Nq+&RlZmdP!r z7%9Rcu7@8ADDNvw{R%+)53LVku(Qh#I4JzfEOnsZEdzq#X1tYT&;)#!2$2T7BO7-->lNz6O z4+3C_kcXJ2lQ53baL%JK)y<-h@R3CHQKse5)yJ6@CF%)FIh$#W7}z-=TSA4mgzr-c zKVaGr5`Knh#Y8>JwBbZOXDP@0ZxUdr zAS2MVv*??EF8W6FEv8K&y?2;4jZ-lgiQ!KPIEEDRM_7!;VKJR)Gf67Kv@)Vhhz~U0 z(b>_6&)#HPX9~8^fuTN&MR_qX7>mL5yUbHC-07FSGTqV8ojR26?!oaCxN>_8EWH$i zG27^V!nOFmg+HdmVB|JKQiv_!8d%X=9+)kPMPG;&Tgo|1tDwpZXWCq%Mlx*yQKOl* zn5eN#JABDL`|}kA#p;3qI>21Scag*P#{{rWmm-AC~z z>}X}N>3mETo58fzq&o|`dvQbeq;Zy>pZ>yPWjvl@vzbOedBk82FfY@HzZQT7Oi0*X zr@X~1HYWzR|8p^zjdNa#>6#f^z_b^^UTk4(5xkq?Y{RJ75~gh+2rzHP58i1`H}|B~z>`c;1Fs+_stC_Zqs2X@&U_EvcyUKM_fG+QmVymeVYnZl&q}D=@)Y=6v zo>&Xq;=!(k$b@RFk8QwezzmZU*y5rYgP{XM24j@~;zJ?U5QC@xxlBt@Au!{Wj}gt^ z*gy>8c_#tc1wTas1-{t>KfRK__A;%R^cvx3Ov-C!S}Wz@G?mleR)}itBWoF^?I$T1 zfM#)3V8gW&t`4TPlL*W@^YhsNdZxV{H=Sa!Zn6Wzi{pf<&r;3<@7ixx&7C+W)z`GI z)QrKzQg+TfdjWgC*jdro(b(DW<0@G>hi`3U8{yIKjOP4Pz|IBdCOJ0-#?E6}7vVl% zG$!v)sLd~cVxn)vKESjdlDQCORj`q0t2LZ@XlrA!i=Zvd7h@MQ?GTAw%Cw_IUCy-Q zL|w_W_Yw6Grd>eP$C!2@QJ-Mi#YBCIX_pZNKi-;nL{z^J5}6P}pNoASL+C132#Jek z>}uf$%z*vf_NBU5?2AyL*fp_hnRX?W@nuh?xkIm~O5eb=kCMz+nf3{yZerS}iTWDT zK1b9oO#1>+w=wODMBTx(FB5ea({3Q@ZcBjy-w@kbYdf3!+F*J#b}zirIKC0N+}HO< zWB0`#VCL=S6&S}44ati=TxedQD~e*`9~I(

QDcP7=AIg7f>$KV^{?6Ze{B`vE< zwKq1W)~0(?Evcs7&hDdT41QTHNVWC4@>J!6?%7?T3Ih8&n^(bBg>C7c(z?#h1ASeK zUC%NxgYC-kC^o>3t&62E+WkOQLp0UHJR3On$=G*eu_t0rL8ZS({RdTbMPCR1d2=>@ zdi;v$w@Fv{#5LTG4Ro|mU2Fn||v7NTIdlV1ug=nNNF>}N2eXTBDDiD|c!%rBTmlN_;M;je19GL7D6 zV=!iUfJ9z_1uXpCG4?9czD;?*hgBZbA-vAC?@->Km`1NPvA-}4XXPO5VOa4rUHu1i zV|FCg*TS!6F&JLZPld?7x04KL5nTG8*c! zu32P1GjOd4%<;k`a~y^zuW+R}3{P;6o_;cmnfB{=6gs4MjA^ftEVGmgnD!@PhA@rB z`SBvA{fF{~GVL9rhBKW8)$x%`wrZ%!aWZ2o*0mNrU<1^y3m`G)cv&!D{ZOh28djh1pDv!Q-b#@t+Je!5sOFg88}tB~lz z4*Y=@Vxy9jcDtTd_%MYZa?N;>=`<>hr@Z4OA+eb0bK*_#u!}b{okp$k7N(y;CigL& zMy>JvOkY8HZA@Q7R0q>H5Y@%>dZN0SPQ$x+FVksc7eD0c72s_Rf)mCf1y1N-77xs` zqVc0~7=>I&jRgzEaG(G!aIUJHm3>e5zAbx4CtmJ!9Uk+w)oY~dR-=5(2 zl=e(d7mHsBDzR(gABGt_%J?YR_!!e^R2lyS4CcI=@cIOs^RoD-NcYn)*tfGjOWL1f zI*m5tFs|WeW{GmUn&zm`YzKyKteDGvEQA+*x}Ssl==ZkSy#nj0HQ+< zi~kV$%i_;6{X?Yn9Q62E({PdiP9Vg8OvYh`#K0^T|0(Ic$n;A{59U8y(D`q7sQ7bI z`~}l5Cpnn$;BiS+Y|k{q5Df)?LxL|uY@t8;AXH!B>r~>uWBP|l_cfSf$zpT;h=>OM zKn7lC`o~BbW;>c2geq2F~t_YErI zO{RZ_yOo4T`e4xWL^l%MWp;I#PM()bMex>bQ7K$%3DS^lRyQoaxsQmCy9A5H*D9HxX5YzX&(s+YB3umAZ@#WBS+W+6cVW_NN#d zMOQ{M{WiKXmg#pAHJ<5r6LkvH?AGN!*kRD$U=am}ikPJ=WCPfQx5v6W1xIbsG+%-@j)JTZSy6g)9$ zCYZq!lcsXnMyAu?i`6roCRy2Lrqe_y+sgF+lJ0h9XhiLVE)@GSe2;S--wIXP4ONL< z!}c&ELZW-&F3rxv^k&+c(~LF35;bc)YhnhC<`|4fqS&rD-40e-$;v)h0u7X+vHeUr zN)-Isme-c(lwS;xT7G)MY2s4Mcyk`R}^2)$N(z7bYUedFLu^!e7D|i@8 zffROi!cULAecc^m(GvgBEc*&1MqSRs*6APv7aGCbS3eVs9cD)mD*VK$&VjhbHD-{i zFwo;Pq$-33ry*5gV8>}l)dhlvR9z@&NHsiCIFBz@146^of{6n{!*hU%146@Ne2D`> z!?Spa146?Sb%_H)!((xY141i@;)w%7!y{^m146@NW{E>Acz`VDkkIgGSmF>1p7cr_ zV!<<9i9;-SIxBIA1C4{JQI~T#Db@t5{FpuLziB1<%tY4zb{=n8YC#Jnxb?#DXVTat;X% z&#NR3vEb>G#32?uW0E+;f+t22hgk3|Na7F+p7KZ>V!^W1VSnzBx;t&g-07e{Q z!SlR`Lo9e|7jcLM&)^~svEb=ioI^sxGqi|9EO;Uoafk&^v?30%;JH=AAr?G^ia5lA zXH5}@Sn%X1;tJO zfJX2@0S|Zt4;1i#Nbo=b510fG6!3sb@Ejj@#>69~mt%J*b1<&ze7cO{?4?A(eb9~s13!dY{{+oED^m6RV1<&zeXD)b- z54&^0b9~sL3!dY{E?w{(A9m`3=lHN&7d*#@9lPK;KJ3~B&+%cOPCQb2Id<=Y=lHOL z7d*#@UA*8qKJ4TL&+%b5FL;g*J9@!$eAv|sp5w#LUho_rcK3qk_^_WR9x1&XyL`cO zeAwv=p5w!AU+^3scKm|p_^|62JjaKfzu-AO?EVGM@!;3@EjjL76i}n;q!oa zr1WxpGzgyK!-s?5IX-+m2%h7^2ZZ1`K72$7p5w!Zgy1@F#4LbcXq?q^e6fgG0JGYlPm`hISAVl0!p!^3`{C820A6B?`;X{h zLI>8d^@v}2()3#nEX|wmp0*V~y4b%3rJG4i_J#l-G!X*(I{^}1o-M+J?{bunO3c64 zKL&YzDx%+*Jcz~h>@P!VLqS2TAirS9ki3FIm=kE@KWw?6vx4G+c(D>G7z(d>^_kX= z6ufl7E1yvf(_r9`di?BUZK|sQe=P%Vzz+!Nb$#uP>28rzTn8UDwrzp4qEJF)7E;AG z;J&ovzLD;34(<% zb=BL`3yVp~CS(n%hZ0k@9c_RGSNX&0X`Tb{l@di$4EUF)Sg;#-F@BW|KmHZt=hr-i zkFR+O-&yk%zOv>id}Ga1_`;f}@O?E;;p=Li!nf5th0mcCwO}~Vnz9@0!bj0OA3llp zxx* z3I|H?6i$NRDIDMcX)&H|z|-qRdV@&6BGRvl^hS~1B+{Ej`ZbY$U8J{&^j4AHCeqtQ zdWT5w6zN?e{f0>I7U?%ddXGr&73qB&o73q&e`kY9g7wL~h`V*19Akv?T z^hJ^WpGbcu(w9W~bCLc+q`wsDuSEK5k^V-cFN^fIB7H@qzZ2=JB7IGyzZdBrMEbf& z|0vQwiS*AR{fkKdD$>7+^zS15he-b^(tnBc-y;2wNZ%0Yn<9Nnq;HG#9g+T*QamXD z;~Ac@lxiZ?MQVsNBGNpOnj*DC8Wm|wq;Zilk>-oEK%_%NS}4*Ykrs<|s7Qy2bht=I zh;*b#M~QT_NXLkDtVqX+bi7C>i1ZYZo+{E3kxmrpB$1Yibh1dNi1aj(P8I1ikxm!s z43W+h=`4|+F48iQ&K7C8NGn8IDbhJ2oh#CLBAqYN1tMK2(nTU&EYc++T`JNuM7m6* zXNoi-(khWwi*&h2Yec$2q$@?bN~EGapkTGjF*~O-~=Hw$8XqJ#d$L@GiA)?TqO&?^2I$op}o==mjI; zZ(LE|R*Frv-c-*k7zG)53WTxp@q*Ft_f)VPQKqVAsb@oOT$!jIQ_q2CGL)vSSC1=7 z!5E+;s=8h&1W>S+>Lh|X-vRahAW*QZ>m-8ufCK7-L7-rTSy)gP<>J0_kNYlmKwT09 z>e4|5Rp9}3nFH$bAW&BfGN?)qs4E>%9}WTqA1V&2`{sB+ebfQ<%4-YD*E@7Sr z)F&KJp9})^sX+!c-vjE?4yexrf%@!81@$=x)aQdhT{Xy{7I<3f3l6BOgFsz#QbB#u z0d;KG7l9#A(ppuQ3W>Z^kcYOx2@jSi@rft_4Oc7w+u3dqiguoyV(voEK|jJKt};efh32ox+y z4h!nuT*gz&Jnp;C0d;>6C|GDSsG!dDfO^mY^-vHfSo0GWR8AvLFQ{)hpuQah3YH&* z1(lQg5}uZN)B*Ka5GYvjG^n7eJfObgfO;Yb6s)ltR8Z9(P~UYxJrx8BmURs(sO26| z-*-U$AP5w!BpXyvH6BpUIG}zQ1PT_l4JxP=9#B7WKs^@(3f9*RDyWqnP(OA+{Uit! zEcF{yP^&zke(HdFF$ff_It&Xcr_R$0>Sqq9mx4gS0?4qSa(W=wdRpoi4ya!Sfr7P| zVL|28qkBR9+5z>OAW*O@bWlO9_O#S*9Z;_Xfr1sPg9>Vm2h^($sMmr(!D894pmK_- zIuEEnIG|n+0tM@K!-C2wro5p3K)n?N3ijOy3o56U@`8HD z0rlSiP`Cw1SWr2&)FyXJX{rrM(}F<3SCJ z#e+b>rZ0mEs@@Y*`3|UpAW%b2DyTvSR8bHp*yrXXw$xAu)UY5>!%r%x5e}%4L7+wr zGN>({m>TVX8WRL+>`4VR&H*((2-Ji@2DR1GQl~heP7MN85*m~?DVLc%FQ`%n)Z`#g z@U``z-hJCVEp?g$YHAQD*g@$ef|~Atnh^vFHf$PHP}@B%HOm2YdJw3x(4caQDKDtm z4yf`VP_PHoptjU5PfJxgpymXDntM_~&2vD_4+6DdkU{PCwA4Ze)S@6zi$jCTEvCGn zmN=l627x*wG^pHG1?};))G`OunL(fuClyqc1FAX*)bc?FmGrb!jRR^$5U7=*LFE=x zUQnwXP_;pzR)+?aTTC^3T5630sxAoBU@w33f?DT*S|0>z!yva*+S5`S9Z;KsK-Gr^ zrESh-Jmm$o#R0W72-LRFpmK|;7EeoUcR=k30=4s`g4*SP+8qRH&q)Q9bU^J50+kwM zQ2RXYYji+01%YY~4=SfgGcTyL1F9tmRBL!pIZc`!@U+xE2UI2q)c%tS>VN~PEeKTm zAcJc2v{Z)!sxt^wS7=bVJ&+H2Kpk{Ibq9g!2@NW@&a>MCs@DP47X%7+Wg67C884{A z4yYqRpkRZjkf5})b9wf8K^=2Iof8D=cxX`Xh5OERK%Ex^>V1O@s>c&k=R2U@9|Y=x z(4ca2pBK~z98ez&0(D_%P`SCU*V9rTazI@a1nT0@pmJ*|FQ`i#P?rXQx-2xP_oAgP zcR*bc1nSDrpmOWc4}0AAVF%PlfWBx_#~e@}4+8axlM3pS4yaEBf%Kz%thsNCFlj;E!rb3k1m1nP#93hFBksILZrx-m2;?dDv@Q|EhH>T3?DuLps; zB{Znq+~);#s{`t`AW*l52bI&y==(h_<*eM-f>!S1Hr`?TsrLYsvvOYxTDgy#iH8KG z7f>JcfO^aU^>`4d?}P{S zWGv4M zu>>JOX}`&(r7rQb)XR?hejDVzS3-lzt);x6e&>LCH3-yep+RYX$fcz&^|aLM4yZo{ zf%;Q;P=Cn<)MXw}&e~xuXzef_LlHKn{+SD?%RQj}<+RklgIel8;X%Eb3#cnRpx$yo zy&VMVozS3k<$ngHJ1b)KpcS!rPDn`i>5*JOUFmKqJpJ5E_(zYA){kgeTBT98eR3Kurn_DmV9e zK{@L@^`Ld0c&biF_vuq}X{k?oT56ipQqzN4YDQ>KxwVuR)JzA|tRPTu)==1%nw?8a zeah2Po#wC};Je9<+K94{HhwDyL`P z=R7U7#Btx!AorbdQb9SZ7xkdki+F@p$d=NpbBU?Xds=F_(^54-Ewv&%s8zXuy2=Bp z)&aFT2-KSJpw{LB>I)uF>l{$)gFtOKsh~DGpf&}8st*q;r!{$3ds@m_lcxu*$-|S^ z!Up<#0LodDrw6Uc!$aUgg37J){Gz9&b~*0b9pt_}gAD3g4=86%o*uL&56_1i)Ry{^ z2b8lWPY+s?hey>7DyZu`pqw>%deE9YJOyu1L0#_w<*domgVyBX;d+A#>IM%eXHA|S zv?dP^?;BK5H+n#IICo!X(B0Q{Qb8SbKy?R!>KSBEH+fphS(B#+t;xfa5(m|Nw|PK0 zYx4AdGKca3blTf_lgU>LU)Qj|PE)gHOYP$|=wv_JI1h z1L_k&px{W=u%L1Z^ly1UeaZp#=^#*Wers4zIknWcJ)l18fcjhzC^$tnEU27X$_wf$ z2hMjS=H-bRjJ;aieDj}J1a=RBakcVv%^_E#QI&Wcz)Xhp0Zeno6HHx zE_|Tp1nOlEs8=0OuLXhn{UC$-tp}8|@30=U@38(Z_8rctrC#xXa`qk8gZ3TP-^ISe zIf43}2b8mRSPxn|tcPDatmgDG`l<(%v+uATwC}L~F7_SH3Dj#IP|m)?deFYZdiZ^Z z^|x|aEb#{qsJETF@13B#@4th5_r2~0Whgc%Lk$3BXeSkv?tn6aKt%=_)E_-9<*c$c zf>v1@;a6Gb_U!w!2UOH)so20Rr5bUA!O_BaP-Ph$A&EyzMyB6w6ygDtn(MsD7`F|g zC}0#B#gMATP-B=FOD}>`C-L0Lyy;`_Hb&nh)gD0-LK|caJm*vuXH)`H2qwoEWBZw$ zakp`b9FWXpgWu$-2Aqe@tLQ;F`R3eFPBBgsCTrjbPCVYzoIZBu-3C9nvwyqcIh`Ql z)ZC<+^Sr5W*0aXjAgW;-7*lyW%rZ{zU&6S%jXCm$=wAY!xr*L0joHTBYzbvh!fal` zJY&AJgvIY!2}_Knq6AOFC*%e6_ay>%!h=9p8P&q1J6u=EEqcP0jw?5oLyXlLtNY=C z7+Wv5(jV6vaG8T^4R6d1a+CG{gUJTD$*uo`$!*5=elDK@VVjiO>>pHk06YcNPIuVu zfS}sR+hOkjC8Wcaka9|BbeE8V5*m34E%Ii`$P4K2JYIm^=YUy=hy4S9?vUH;-z+>J z_`QZF(K~lDgobf|m(Xc+!Fj&e%Wi<0`&uy4yG+FJd~$I30#%bc@^BGJ1f* zuGTW}xO!d0^+8^xd>sS}L8K5aV%3fgP_=X9<@T={9&t||_f+jHr)tNIb45&Lt2SdM zRPBTEBKlYDJW+&YyboKCSM7YI6{?1(7ekfKgTmei|IX)Cy3qKLD6m&C;XgR#csdj~ z+87-fop-nK5qYtzNYZK10^=g%qr7GX#>K|Rc(Db>C0Hz4G%f`S{ZwFF22_Momjji@ zL5N?4aQgG0d%w6X#W7RYi2n$v#4fv0J-V`b@-a`^?oKps*hfVgD^T_Wohd zqYJRp4S-=#VB8Nk0EPYM?XXwxal-xqsF@S?7!DZv_rpJERuC&R9^j$zZE5Wu3s<|x zjqixsou^pvpQ04nH}&wm;pW}O_vH24M6ynpW4w}Y04ChvSU&(O>W7f&wnpG|TO)j^ zAD4RqD3kkcyvYM!Qd8pzUfb_WYx_*N+Wt_g{9HKY=jFHH3-SgEa|$s!}eKRO$}nXW=UKlJRqKYgEIXh4)tB^gE1SJ`UsRZx}BliD2}Ck@#0p;{&{! z6pBDljo%utNDRJ82LAvCUwxMbUpM|JG5BXP_%|^4=XYuF@5VnQ2LD9{-vEREdY1;@ zG~SXJe1{v1s9^A&cV{r7MWCs9f8}yYBtizQ>32jT@6up25|bEYWN-)=Wbe{oVWdc6 za3~oZ0S1S@OM@dLqa+5$kiqd_aLl_jI3aS1#9#>-ECqul@6zDp$P|gesbp{l7@Ybp z4bF_rk{B!_gB4(~>|GkHjLZ?w*X(QGj601NZ-sle|GRO&4oY3GTmpcGqjY30?~NlW zWWw+xGB0Akvt~_?z0>$vc+=Sl2QsN#C+oH%3qy5V%Jov^#o?51kSZ??r~DPE^0IKs zUzI8+!YSV{0*t{&Tz_iOO%7|obq?1%IAbrenP5zZaC#9 zrONLMr~F;1^83RnKP6TEKse>^NtG`Qr!0G+z9Vu`IOQKmOTHwW^3zh~%fcx?BUQd4 zoU&{l;Eu?L!zn*2E%~G2lz${u{&+a$=cLM?45$3ORQc24lz%K${%knqpGcKIA5QrN zsqz=XDgRWed`&pz7p2PAhEx7Osq&Y@DgR8We0@0Om!!&H38(yXsq&5Clz$;rzB!!o zFQv*~52ySqsq(Gilz%N%zCE1sZ=}k1hEsl7s{D;`%D0r&D^lfq!zuqxs(gPq z(U!obn%~%1?w-{*zSsyWy1oELHwq zIOV@cm46UU`L9ytXTmA}O{)BCIOV@fm7fcz{12(}kHabdQ>y$zIOTsym0t{}{BNo9 z&%!DHN2>huaLR8;m46vd`Awt8Qsw+`%0*J; zA>ovZrOHL&l!r={hlW!gCRH9DPI4 z|F?G?fKe1(crLkQuO#6@LYY8lp(hYhAR+WlsDV&LKoAfqf(TNiN)bU+RBQ+;7VHR^ z(4-uosHlkbS5fR@L+lOZ|K42gZuXcvP8Ws1{=fIl@@3!m-psryySI1OCOqR*rE$CP zjMJ3H9l|qipfv6jo^eB^aejEl=}P0S;Tbnl8g~!RI74aNGd$x=rE#zDjI)%+h2a@z zD~mY+*q1TD4>=1CmSBl5Gq~E>%mmGaz}LTC#%y z$z^KEP6i~eS4-v_ki0=H+0}sLjcUp61|*lOC3_l>yh$zD%Yfv~YRN(alDDWO`x=m3 zp_c4#K=M|#yVQ~+4M?t1 zOI~6?afk6Lo00m;2;$sz-i&!{Cg8IXKd zExE;jB0m(Pil5ZK1d{Zs? zwgJhv)RONSko=!o@;w8RZ>uE_8<2cQE%~7V$#>O~9~+Q7q?Y{DfaH5>$i|1==^g=K=N0$WU>Lt-_(*-4M_g3maJ|-@(;CSiUG;vYROs#B>z-P)-fRYms+x(0m&0; z$<%)?sWG)=0|Sy4wPd;h$q2P%h5^Y)wPcn7Nvm42u>r{_wPcO~$!N7?Qv;HkTC$k| zNt;@-g#k&sTC$Y^NrzgpjR8rgTC$x1$r!a{2LqC^YROIpB;(YQ`35A*s3p4^kaVdf zyBm;R#QukHy~ME zEjht}WDT|CikgTbeoMJ$-mRfSE0m<5G$>|0p>!>BKG9X!3Eji18WIeUy z90QW|)spiJNT#YK=NphrQ%f%V=aQ_u=KZ>R|1XF=rHSvjKl#h)b-#6ipQY%jH7fb8 zeAzgYz99e9#=TUZZPT*D`fM93)abX+^uHbRl$H~o=e|ngrr{a)QyK^PmAJqL>#sC! z5uWD(O5;}H84pw%2l?%}z_2e+8n+A2^B}E#$#2=nNzy3{W6zHsXdRGgLzEHZham#v zp~?ulhG8s4aFJ4^``;58rW6VCOMALrkRlnb6zTQ%BDq-Eph141PZtRqbcE8lZx|84 zc%;%e$nW?CdLE?>P>lNv!t*>@X?$UL#+NF?9ul7M7^UZn!ZRML^gKK~<8eyQBf>Kt zuQVPNp7CYMut$eyJV9wZCOqSbO5<_i8DFk64)WWFf$2F(X*@AJ&sQjoCxvG`S!p~u zJmV=!<1526zEWu%5F`1+ru+ntlgpTyfO@9R~xHSyXz$5Vr_L;#<-lgTVZ@}7{;uu z^&{)YCB`H1OQrNfht=v2?6w=f^M;?zD^q_P>o~CfChdVD>xZd(*0Si-Jv-N9Gh$^G zSY@2+`6<0v7I~ai&{#x!OJmS_ zM=slu%ZH1s$4;BeUxT{DkMohsy5#baBI_@w&E<)pF7fkyM-B$rPVMJ1dzmz9FL z#Lozl%M5b4t|%($w7IMi)FpmskX+`G%O{JXs-HHO^@6&@PZ5&KY;w82D5~yhbJ-}U zOZ-?Nxy&J#8;YXRPmfC%*Eaf=!)juN#ZUfj(~1Ue(l*f?ZIOP3bRN#$>|4U5v$x{x zZGmUsjI*ECwtH?9L}(>HdHY-aV(s4UX~o*U&D!&6k=wQX#oB?j%-*9xvG&@|UD_M? zuULD#SbMKn`?%5;?MMXMrG2?U`*xf5-M|Fx`*^k@o-N&^{Zy>|woCg1f7oDS#rPU# z{L>a)Y;$a|l_3{-R(u;PoY>;I)#t^T7saC#ezw>WElgNN^JrmJo<~bo8rM#;vhiYD zrGU6@3LY1J0y7dnSDlEJ$jvTgGuSMYce5wiMwFg~YA%aDft4!~OO-{__Ar3EgQo32 z!G^LZFX{cm3H;W#j*Qf7$(k)joZo1aaFZ=9Fr)57ldLHjAQ8DaEWvUOV*@PpJsGgcmR^6e ztubCXc;$g@Rcvcpq@~xdUuT5OwAY@1$en^}^cuIjF) zNP?1_w9QGd&GoplB^PNqVc6FQw4djR;Mzq9caAJZ`|fo#&ukE^kFaZ8@KZtFWqKahP1lA*tXo;TXkJoddr(U zmfGPWt&`u9dfQd?q~@yUYOJ@u+3z>sZ>{iKKhW|Pzu&GQEmK`>^gdVkExU)bObhgR ztKYI`NXrJU26~^j`7L|-Ek!F;JE@f#2Db6-9%~vAg?j6gGcw&(Pw)B;zj5DF88-@y z`%b@cf12*QrHaY^u2kP#Z>OaR>yT|V{wucKTWot^mu*?G?IC19WU=khV%rnm+{w_5 z)D5IZix`%iryBV5oSt<^p}6T}#Y|V4R9T_uS+JnFg-1!EVwqBiK7F!imTqu(M8$dr z(H&fqL~Yy_PudkvgiOLuawV7;=% zo*IcO346K-xjL^dLeAjTrI2gz8X{!du3ffWI5(--o?UFuNwDYogB=4t53lBUwZsd0 zx)55s2A?Vfxq7W#lY^aJOx45nQVLHIv9{(ZQmi$3O@FMeSTrF{t;K7JQ`_=d(y6t1 zZO^ItrPJP_*xsqw-o?9Ywsz$pl#&gy-Lu(2<+|h56R%!UJGXK53?6lFoa|}kI=qeu zrw^|qg;ST;^+#T8@1I~F;BVe>-drHJ7vOcFf+6-CicU9R{}-OK#h_`UQ7ODd?$fDi@m;`$+EJwK((Ac*(xS=XR9e?L^t_=m59v zU0uU*+klI`jeQK4H#ZG=!+_e3^}C%UyB#0kwu7r}IBwHUt%Y{HxPgY-@mIXp+4 zI+y22r{?lp p&iq5X8=&F+@3e4V^f|~NCLiuXmR8r34c|zHD7s;#(7z`MY|CC&Td9 z8x$Sg#Wn0y0mvQQ#WgE4cR!CQz(m-7}7+%rt7~|$0QC*pinkJB-p*S|VYcS2{b3>wUxP{)kh7&=kyCAW8zHok zw~>U}^0t9F<*MR}mJ+3#YfP|6i|v6~)y*|C_{o7;)eUz$gPpB!gm%20h7%uMt_Zat_{8LI*zUZ$aPTzmE;;DId&r^s8nz%HRNr-aPu^3=?BG2mnF3y*kJIj! zr`g`Ff?#b~Y&#(4?_Ru@(A~p(NxHpx??7GoYN&TSyE=rhG$eb6T5q2f5ft)55y5l3 zP>P@r?-Lk7l&l-io(eO9c(y3$nRZVIeR*FI!VA2w6hc4VFE9jowm~C&7F5`FKp*Vp zpl8~jO|b7TnFVmaxkfD622=xdbDusFx zzbGJ7-O%sn$_Scry5#I9?jx%2<=JZ#+rJVq4CBK@4Bzl!QVhfS@PHVO72AKreF7=^ zi}}UE@@IarWI2M52(Wa^+15YY==+Bi{YXAi#PBO0Da9~~j}kH1f8S;Qz1aSz2t7&) z{StnOFgw97k<3Q((Sf1MX*wX>&fzf5X)hm%4txmDzd+vRW-I}#Ec ziT<6@qEifz34DU^Ql3wcyiDX118S<9C@&1RrWb}))64ngB8H0maw&#Md{RIRCl8P- z_!Yu3iC-aEPUe#XEMJia$l!3J9~@TnQ}`4SLuEciis4FrrPNP~0Wy_O6=qfVRLN`_ zpB5OpJV1to8~Tv2LZ8m3ix{f$=~4_c_zZmviUD#Jze-rv;8#hOGxc z`k`S(Ka0;2G1TOi-dDXbB$q@c34Bf1ki1wGN;8>^M~X81flPehT$ z=Sfjq&99cCaO4y_nnB!isa5i(84B;apNeLmyhF>GpJMwEJ z^~HQ~hzgE!RSp`rqm$GUqe8XBVNttl`L)7-KEGD-zl1N5{NtTDM>m~ph<7pNq#NbB zENGx2=|l)i`BD)=5580i;W~bu6oR97v7^6oxs&dRFA;Lf_%b1P0beG`UC*zVLx4U=j&I@HZ`|6S}G_zl9%#ry`z&5is<;l_LO+sJTngkSep5hw$LM6koHoXahjD^za%tKSO@1@KS%ff--z@qO0kb~RSKR|zJ2!!zCwg_IbR`#bSuAA3W>5{a=`o~hcrIK z@bS+1S1OZos(*>OZi8bcGHiCqJs-zB@!Uq2 z%ahEc5btN&j)-cl;;V%04Sba(yPB^SvNQyfb#aahnm4xU@`>?mUeGiB)7IVmZsC17 zzgzNt55GsMlyBPdU)ee8h}iGt_X_Kq`Mr|$8ooxdru>w<REN=O#XE0splS96rC+(0P<_`=1EBV8c|3~;EQnZe{ ziyil)T>^JVQ6&$T1@4dnuHwAQ#^s{NrQ5~0yY(o4RJebTKPtI@j6Wvam&_aw`(}=) z;ET(&Q_mca^T&m=NBQHDvnTiyQe6YnbXvGG$FvahYe|}}G#gcVkmrM_L=9qr!nPU^*B>WfgO_Kl3e6z3Z=@GYXooA?%~##{N;fEJgRuUVmTTizqj3eiCR#bz7d zCPLW4w@D#9&7YP+P%bvo+&nu(NZ##?xP%Ruj1nAM{o9%AJy*<*om(9T8S|?n^IZu+ z7ahmzyR@PN#~U6Ut*A&_jy=&^#g6~wZRguX&EDbLrJC*FJ3Q(1Ha2VXMR8udWF9tgdD$m zsy|dt#Ko@6;E8zL=Wwz7j-lV-L4Hs;{EHuy9KOn5m22pj?UT7yE%O?GjbxmRzb47N z&R>^h&`@viH^g}n{0-^6H~E`#L(%OPpTi~Uo_UMEC4{W}ElKEq{C`5o8STyNxB1)R zJR5&oI`19+j^q%_htuhExKw`p9S!AqYt=KJ-sSHKwOIbHq;`lODye3IGtNJE+>Ct3 zQ&b+y_xO9l(#7ACEZ^tvmsrXpY?(a5Z1k>qWv|R(eptwq<%cDi5BLWPnd{}DK{9Cn z5BZ0}K9PSY*?+`8^4oh|eat@=rStzM9`6HX`2n8x81j^$q_bpRH?}H0> z+@&4%wZsZ_OZ>op5NB~UGQN-S2YpmPy8og(2f5j8T`zD4vZ6z zmjrw;@K$m6D#$fdbzh{n22SCgKKq6LA{_VNzetXM<-f|2(hU-Cq`&dsgh2uSO)~hM z|9Y36!;r_w@5Z-(9KP2zR`SFr)6P$(qDeZRuSQ?P12>(;^{ulpCcz0gp9ZM(p331+Ve!_QNnZ0=y zwwGI&)K1QkzV2BWxFr%EVPk=fMW|guM>@R-FcF@bd&e;>BEd!qi%aQ9XJG|n^;`Jd z-*r+RQ-vWG1%oIdHkOWbV$ootJ!0OB_6e>ETnN4O(O{$r!SQsY6SRS`$%4{SzB*7) zyBFcvVPO|)6X-~%<^bc6)x04%@du|cx}1)5MloPw{6@a|+#QgVSf1cM7H7u_r7P%2 zrxXV!&aYIGLoh0XKa>$hQ|L%%A&W;yKQ|U;jR2EEGq2zm9)nVP> z#O+S|dU>*2e+bB)mzZVIMox5b3X3t`J!GEaAUpLA=VnSK?0&n5RosW zBVFW)U=sC_I~V&j?{lTYd&$~EtFGhAl23>^m(o-U@p2F-C&ZW0kxslknDUaic(+V? z)F__aAM#lvUmW+#ad`GCa9siN6@=>>=t$?fBAAM@>${7cH(_$~e!|VU!YBTqQk+A8 z3-R0NNGF~ICMiJtPFZ}FPkgOXyb=T|3Gut>NGDzyOyvOaHL~~vKJkYF#qIR4dQ0(C zr0ASvXeA3jYw1YmrwW)Vk{^7&&H0F&dXI)$LBxG$^g&gqR23c`qa&S%YGA5K9>isi z-b2vmoQvhR@8a2`uAxDPfwY=EDsH$*cM0v2JPjf~`RQC$lC#wjSalKf6Lh2tx(1jU zQqU(g%VVx);e_&7Kqwg4PZm2j+!5al5k2C&DXD+QOLSTaB1jR@Jw->l=xTzgDMfcu zlWuU?f=1`)1lLpL4%iUl0#Sa`Jf3ZEwGOK5f7hHIBDM{P8lfBG8(e*Zn=VE;zUP!D z1-w}Y4W@RecG>v1+GV3FJ7~!I#M~IF1*P``;@L*=X>avR zUUJjP{-FLnIFSx@P_;Uu+MDS}SM9oB>V~TJQz61Dxu@pbs(9nhH^r=X#i1qS5j9M# zYfk!jGM;jvPf^Pmwb@lIXv;ZwiAO7(TNO#NIaHu>k~nw!lLTXGtKK=?>QXncezDvf zSS``i_0XL4L{smjBVAM12ZQMY9|!X+@fdl|eV%EV`&w&j;6v>~HWj9+LiTw&(#fWQ zNehsDQJ(Gn>(n--cmoJD5aKV>kxslJn1({!^BH*OL0S2AU)WD8mD6FJE|lM-Bb{<1 zFpUDjejC>U}!W1(gXVGa#rBr7&zy z`)a&HDV_y^EFu0e9qGig!DI)BeGHXau4~(ZX{+yA$B*iM+vl1VwC%AMX6_F&peV}ibQ1s~Ch!S}8BSIOt)HwtX{ z-VxEX9bno)$kN4p2c2w3FdYMAJzM(MJ>n(*@C~FFbS}gVZX`h`$aE4e=+eKF&P8W1 zos}+D$S(ZL@qVR?e8}Vr7j#b`U+1C=m@X<8G36u|G39)kpGAi1!2@VR(d>7plOdI}eG zA=*>tq5w>R$^~7)`D)?xUu7Rqy66R&Ucv=kiT2XD=nbZ~(gkj8_+2dZ)#4SUi$cg0 z3Kw+USg3Q+2TUKO3v3nqF8r7C2bC`RLZ+{9K^K30buRjW>8EsYNOp0^s=FY2HN;~f z(hB{mGMxT!*U$i{}C`7fA8M&`!LyuS;K73J$_KgM=V$tq17@F9dU;EJ*ucEG^Dou)GWyAvQ+3 z&Bq%dZWc&Q{f07qUMys3yLYipb_AFa zl5C8$Mf26^eOcCbzjGu^M+({2bfl9V1!j~io2rQRuu}FCm|h}eX$NzOPIfey(XwnK zh3p4P*-K%1sgR{j!KFIcF<{2XvW*q8A1YVrA@(Do$NR;aJQ2*q0ASFiafR}y%9!armMerZE%;aHlqZ9k9H6{Uq5PRr zc?ztj2xVI5r|6Wg1aoD8@{0=P&y~tkVLeqS)ABx5r#ubJv;gJL6v{`G%F|&zT`1G4 zK3%6g1I!Ge?7dJ{$bKQer{qhyt6+MSkfoLUDxK_1Ff(P@g9_O%m9n#7I!nmXiabjv zI~&Ywk1V~9=(`cEe=tx?V{>ro93evs=^UNRTrhL>&54U0>B8k3SHqweF21MvuqU4f zp?SgyEw1x)POb)Xwcbh0P;rY?e`k0;&YLeZXhNT_(^vpzfnGx&=+O|5J;vZphkd+U zt)n5XndE2Z0R|*W6KAQSGBTp)87e zHtKoJ9bGLtBRU)9wCHQ2uS5A!^bgTLYi=!1>#FrYdB0YKuef&G%Gj#eQc$k7ZN|4@ zyX|G|DfZeZ=h~OsZ$Y`q{+xY3$|LsQ?8h~?W2NIU$2!gJ?BpEa9E5U`bG~zt=8mz% zl#MBea$3x_G4L1jZ7hq8)ZDS7VyDK=K>1$m(b(@acU+&ik#VC@?vFbZcUW_mnOJ6C znFT0UmU*lUbj$qYigwvGw`-kimurvajvp95CVsr;F3ZZsmrX>OU-p8sgEeMY*#6WA)Lmsg+XGQW0 zr9F|hGi|r#Zg5Y7^$niV+znG2W;e`1`Dc1uI@&9}R(g~4rYOgz&rC=Err(@?fBIUK zZ>E2q{-x$_l-#IcqYRWI8ck_54dtVao^G@gnLlMkXW2D(R`aaxSp_I(W-ZG? z`(~}p+MI>)l65reM0SMc&TgFDF*_gSuIz)^ucJJY{aZH1OXJkW%^SBu*{|^>jmMze z(fB~)S2cH&#!Wgl!TC)_HJRE3WU#W$@tEoeHj>1dRzn{LD{Vt3QmnjUHTmFCV% z&dbbejIwv$C3*0lcURu}JhX4Ke$B=|hf*zsYM&vtyb5uY`K2P*nkMdaGsJ=GM-M3TU3;Pa5 zd41pe`aX#AhkmwxPR-pfr(d^zJvDd#l>WK>;YWOa>UXEfUtNah6kRvgo;Y+;ZV*E5@ zRSX0q2W3>pPI1t{K2ARbqJ6E!G5kkA2XcbdWz`HuDMxxbv_eJu2&-`#qLm{)U3y~S zKpV3h@nb8yw73W@&MKPtK34NI1uX}DIyE&-JFKxhLd1;7OO}8dtoCV)T#o*9>pB!Q zudhxlGF`^%{|hydYx8gE2d`1uzf>c+R{y4t z;5BRbFV;-1-M{T8cnur<%Qcj1`Cs@7UenC~pr&$d|0{pNYn=Tb)mX0ef9W$=&F^AO z{==Hfwg0dE24DDd|Kk>rTj5OjKE(#27j{RUI}8-)fBB-H2&6j;XUf0#ssqse=lo!1{+6ipfeqZuaU5cP1avjtY)pxa3jeLbvDG}Ypj#69b2=u zXF+4h4R*G~6EH7rWbMzAhLRiWY>FvFmaStQ&!WbY8}Mw4E1IS=*3dtx(VEzXbw10Q zPj14qF*fl_#%M-ry+N$YS=f4V3!bg<`H~TL8^vuqPcn8pOPf<}(z7{6IXMR~+=3JD zEK>Am%!WS5Df}5Uc!_SWniw6tu3~!lfl%@8+}QeUj;{ zPbq0=xv@)A%mEEPgY_##4K6o&X^T6c;g_)irL5uQ#xISr>nHRJN@45EJy2TX4;Tj1 z*@dOFBjnB~&2oSYOKhc`nv1RG)gs=a_S_Pvw3+SL+w5Z@ug1xO22`<^DaF>lmt! zz2oXh8LF>6<9RTfc#ikA+~4OzT|@P`cYIGe5Bgm0_w%K`q59steosD6 z`d;q;^Qq3Ea=<(OuRM=(K+c2nt=^$>!F&BZ?L5l`IUml)x`)aM@BA?1Jj@9>FV5Hc zhsq7_{$b{Mnj3O{oX>3#Do4EY$L#YsN8~&?-`gQnu6X8?7uekMJXhp=G23E~=gXgh zzW-kGMCmMcwV5{Jd3*2k?Phy;K7SBHc@ZRi_S0AV&=VXB*#a|td>_~FrjXet{*SPP zN~5p6-~Tg%Ei%){mqzkJX10qzm8e}#y%Flm7Mr=G%OyFV%(l_z6SYlPQ`A(p#7wJ` z(n?M(vwcoZt+3N;2D{EoFJ*ekDQ32jI>o4sPQ5aAWY?QH7Bt7adFJ`{<{|7xv#mn5 zmAAd>QNy&}_Hx^Dw+zyp7#%=HlPVMQ=WOcFiN$oo4&}?e_Dw zA?>8i_WOHdn%d4Yw()&=>Q5S%ywf?A-DT$HKgvxxKg~A$XZaakj`m=y%^dy5IV$I= z*^d7_PfwMr_-P-!^*@E(W9F)%T$S_HY)fPLN^R+&Z_8Ef0X$F0HD+tfgf*P7a?+aZ zX*_99HQDYGlkHS?znQzIC3ofgHQV&`zAI+xGM(b9j^URQ8CO)2BVB<-9iA_w?s=$lUgQNa0HMn3>!EN^X1e z+xza%6J|UAYwhf9YkHT+Z0CPxE}=FKIj8tOu`-oCY3BOBn(K1Dn{EB?=6iTK--B&1 zbN*k?c{%UR_Wt+t{#3c|eYfi=Gxz_K+?Vs;Z1evn|EbM`-t_Xmdsb`?fd6a&$b-Oa z_y2AXoN6)HRq}4!W^*k3r(;1L4`$o{x8otaG4Tc4YL1Ejd`!sW!fgNleq2!dhxtjX zr_JGUMuvwxM9e-oGeg9)goOG&DSD#xAlqS%kux?%yyL|4UQSiE%j}CY+85sbp!a*s zzBqI97WD(YA~fwwarM`N?KX$T86O(n;o+UG_L_ZiR`iLtUufDg`{c||TPICldF)wp zsGK!J#XDR)(^yOPoY^;LRo?{m&kJV%oOS&Z*hep#eRNj#k-nd*vX{+%I&1sM+gG%W zGyCc6*~U@71ipM%rmfj4=8!t6c>?3n%minRT9iEiIE!k)0P(5dcsytlHem!@FYsrv3EbcF~WJk;)drl2m zdDxnLdu|O|&(JNo4{&Uz>e=PWG|4pXp-A?BjE9nx_8sOxGnB zM|te1Ih4=Yq3j*b-g{QZ%)UOS``X*zG<}qoJoP!f zqG(Tto2j-KeAW)nT25rYnj`wj+!&t(__HPTl%brrXiYFVsiPMA4SGEGum(6V9Xgt>k4&K17z-Dquz zHm3@6s*rY6{$-@S#b)M)nHy4W(DdQYk2V&EnIC3;1muT4N9tO{uf{3P@h(MXdH!xo zyjxQ_j7Ty8=vCH}2RU5m@i6*E^t6;B$_#6=1dql-&Ye~W~pdSIp&n}H>Mo#wBy+w7g&64|1gidxkOj*W*(W_Y08Ix`ic}E65k~r=9su@?6V_e_9{U?Bw}rqK7Os%-PADoeZpX-YoRaP-Z@vGn6+cjFj>$ zwcJwEoTbcJ>NLz!l#$+<%FHQqrZO@^$+ix<;n{AbZvKK%n<6lQT+ zYMT?7If0#~2~3{E%)BxuF?k{~dK`KpV_#b8niH8hk)6hgOrFfl+%hLKqZ3%5edr0z zGQ?8foY2e(?KDql-bu~#kW3d#nweu}j{OTcrq8niOG7iy%sl&-@=Tv=-7SsGTr+d+ zU(7XqzAd(7n)znt+rOM|`kX7UWSco>=G=dfbNaly#?r*hJ2UV8qrB7SUV$ao%sn&r z{=?kU=idTLo|%7U{{6@Kr_aIpmgZ&-nmKp|a!{X#buBH;JT&w04CSFW7wH30W*(Yv z%u+s_sh9Wr3M?;M+L}}18S92K)%|CcUt6+hfA3SoW2>J@v+liEbYyS(wr#IR8o>(`k`!m%Fr`C&~)j28m6O}nPz65HJM2n>d(%8md<8& zn%Q|)WoKZ9b}=*5%+RwgLj$w4o0+9%mY$Va8kng)%uF>i^{ma*z-%orv(?PjvpQP? zGq$&xv1Z1e^%)zOwSCO2HM6!;xNY8E#IG=Ja?PlA0O%pMHw#Vi{p(rJ0pyMOFr8<|s2W&CEP&GBYqc zN1NGcX6IRzoq-uT#>`MNL(jSl4b0MUW|o>+dRAtsK2y6}E;BRL%+#|sQvp?z^t8YX04gEr6OwsGxtg}bIr^xHJKZjz0=I>HM6%=Wp7{x z&oDFC%-~X&!TK!jVwq`Xv6;oCGK=+@T;F`y?=&cS>~Dn{AbZvKK(=6e}WCLTy0Li=Hy!{CSOWv?*wdStvLaEr#K^J$T`%|ALXcm zPQv@eB%EVeU{1p3BwT7HVR<4pGuNDm<*DwU9vhl#LmCH06m&B7?1&Fr7MYW=IT@F# z$=Ev~(~rsg!5)jN$XMjd><0`BCo9h!tQL!587SMcYV1Ok6IgY27s_?420MiETb5#} z%p8_1OGXU!nYqHL})a4r>#ZVO_*Bt^Z?LQ4Lsj)J)bm z>JjFMTF071Ys?Xy#B!paM|p_lYD<|zTg{qkKQo8T&hl*6qr8_jv;D>#_88XOJ_6-b z*20m*9F7L8m17^uH&|=ucII&IW^H0>Ge=BQ);4Ap$|qU7*hJ=tt;5>KLN|6b>kt>g z9C77X$GGVzuVbC!j-mXEbuRN6bCmgt<-6Wx4%boEC4LTb#NWiamQ7=hvaMLR1hi*D zE7m<>8takp8|#_4mKBui%^c}$R>NAyp2#jtZpa2Ff5C=SS<8l29mgD1=dj^bm$Qqj9%Lh`eac2wf0m6($zzU` z&TMqbcPM{mV`|#i*qYz7akUn*@wE;xN3HkRgjz@0<+W4Uq&lCoE9(BrCfAQ=m)Eb$ zrq&MAQcEi=o(QrMR*AR7W_#?YIeK?z+{t{cz zD3L8}G>9!~w1!=ik-!#bEMV7W>}N|do3o{vk26Q+26kQMJ1CE^Wm)O$`m8J24Ot(u z8?)=O<=GRMBYQHtIs0Lho7gRlYp@kf(%7v{-ekAs%w>+8h3xhmXyoi-cjo-W9J!Hf zW$qMqSMHB&Rnrb^b<lfzI^0Y{wnr-{*Ua1F8$g5 zE?e1)U6a{MUFWiwyMD|LbnD1o>Gm)?*gb~5+I=N^tw$<*y~j-UM$c&WX3xd!t%Azz z-Ga94P{C;SUcpZGey{TEaIf*~gI;^thrKJYk9tpGANM}MJ}IonJ}sQjJ}Z2WecmUB z9qF^2ebMI#`?7B<_I2O+?3;dR>}dZ;_I3YC>{x%~U>s+xOlQkA*6u7i<|Ej6)9Rcnka1CO=1NShvMzQaLdjwp1 z+-Pu*g3FBS4el{;8F7cfJq|8A?s;%efXgbg0NgroP0Cyb?n!Ws%TV3cgUc;Lb=v?g z$7Kh%5nNuGAHY2YuBmGexFT@PU5|q+2G=ZpJh)BZTE_PWw;5cEvWeiffNLH97r3q9 zT9q9PZX39^Wjld;8eE$M4sJWR_6d>Tc7SV_a1h*1a2*r2f!hVHLt-UxZg8CwqrmM3 z*C}xhxIN&yBwh+`FSz_f%E@QIbxWk2d=^~Sa`nOO1J|QmBDm+kbuV{0xaYwYlp6%@ z1#msfk?nqPy~~m9i{N^d?+WfEaDB=*2KO?!!tyVJI{>a<`OV;70oS*}2yh3%4XDrq z+^gXFS9luSYv3-Z@F2L?!40g~65Jc$F05D=+?(JARdj=U3*3;3kAnLjxWRlJxVOPw z#QTAJ2i#D84BWfmhVys89RfEjiR$(qxDiQIxA(zaob&{^!{A0G-45;pa3hmG1@|Gi z(MboueFW~3N|%EB7~Ggjh2TB`cWI^jzvU;;JyZTc`~)%H{d2GQ~MnScSZ66aNmNvGImWzWfGmZZ*o6-@(nPb}zU;z+GK!DY)a{=2cGz_b0do)j7Doz|F6|0o)02i>lwn zs>d>L3v0NTE!F~VarNK9MS#1e#*N@2!7ZsV1DqAywJ8bUqQG5O<4WR(lG#1aNoO9ttiI+#R)l0#^>)U9}H`D-UjE zoo?VNfLmRs3Al>jR@Hd{90zw#ou|MhfxEjd`KSbLO&#)48Qi^f7lTU%cYobU;HrST zuO8;Q*s9tx>a_z`9o$3p8i1<-Zf!lxC9x^s9;t`9B(^5FhwHZmR}0)@ z_0z!B2KQ)v%uTU%z&%kPb5m?xaF3^=-(u^5domUM7F!?Ox>U@&v8muTq+;HUO#`<+ z%?hpoxTjK&f@=tFV;cEL2Una%J{o~5O4|)C1Kj4c$G~NR+tlDGa9QBCHdqZV8{C$L zIp7+Dd%9tDa81B%OGno`j_BZfqORnb#Sf0J<})yTpMuDHL3)zEx3J+rh#h*?uACf z!L~UIo_!+-sRM7J7nvGlRxL0k}6Z2ZHMb?thu>!1V_AR^~i# zh2Y-F91E@wxVJMg_G9~kJCupBAKMSyyIFQ{{lUGT`2)BC;NHtB05=fa2U&UGE&z8p zi^kg^a35vSc)JkXhgn$nV+Vu#Bn#_)>=1AtXGee=3huM4ufbge?$hjiaKpeI$<6{d z9Ng#GuYNU+MK;#`*pcAA&c?bQI||%ajaz}c1l-Za^}vk=_f6w5;4TGs ztZ^T3W59je_*HOY!F}KOX>jAfebDwf z;4TOEYm@iDO#=5zPEBxEfcrfs4%}pLzvZj}HwE1Boa?|{3GR>FYT%}V`zzN0ZW_2h zb33z`*y*+u3(L)9wXlOIU?*~K2X_^?h}@ajRm@}s7EA66;AVld<~{*#Hn_;96~N5_ z7oGbDxVhk>nvMoH51g%OH*i;j)0!58n-9*>^iFUKz}cIA1#Tg@n5GB7EduAvYYgrh zaB+DY++uLCd1Js`3(l3-1KbjDW%8Z^w-j92yxYND2QI$ZW#E>9OKjE~-1XoRn(YU7 z1Gw_d)`7bbT)E~Q!7T?@v3Y%PH-W3r{626ugG*|D4Y*st;gSm63UHO1e**4SaFtq6 z-EIR{r3KaPc5ulps9o*=SFHuL%bnn=wwwcQCAba@KL+vTNiLIfa}%md2su|_38FFxEH|{cBg)O z30%MK)Ne0?>)U-BxC7t@biW(iE8zO~pguYX?t&iFN3Vh#*yAp6uYtR;$6Ro)gB#Sd zHn=yy4e99s_a?Z(Js$%17PyOgUI*@f;D&bYr|pS}Vtp*F^6!YA8)L^&>jLVdw{hO^ z0_vl8aNe+j!{FWpH=EJ#CH@^3`;64X8vG;4>j)0p` zm=Ep?aFYrffcp~M<%Ki`zXCV8kjCKG;I1hA6Wll8t}Ofz+);2-`t%3)Ex2iYnt?k8 zZfc+P;JyPlqt6O(--Dap*9Ptfa5MXS4em#9SM?nV?k8}w`?dr3Gq_oO9|ZRcxVe3o zfcq8PoPJJlzk$2D@3-K72RE-@PjG*LThK2H+;MR8`%@eI32sq;YJ!PfOG8JVS%7!S@QD&gbM464UG0Gg2 zxhV5cHbdD0WlNN;QMN(Z4rP0k9Z_~dna{eiZphQ$RmBuvY+(^gw2j&g7F#{-4vV%~yTzhCt!=kZ-&wRZ){hx`&|1vcT7riN z9wvB%;8B3313^cEP6V9^@(H>SbS3BpV2=?zPVfZ5I)WzwmbP@Xo{rkn(FTHz1WyqZ z5fl?_BG?SDw4onQySPJ&$oZi3wedkFRtJVWp-!9IfL2%aZ+fnYzu ziv%wbyi9O_;1z;{1g{djM({ep5^Fog-k_s53Em?3AHmxM?-0C8aERbNg7*my6MR7M zA;8jxpf&yTBZ7|!J|Xy&;4^~H3BD#cLhuE_mjquCd_!=Q;9G)Y1m6*SPw)f5j|4vv z{7mo*!LJ0r5&TZ@2f=ZIKMDRKI03LQ0t-O|K_r2dAc`QGKqIgb*a;j2PJ$SMSb{i$ zG6XJyc!IJ72?U7*L3M%}1SteH32G74Ca6PD zm!KX&eS%biG=c^M4GGc-8Ud_r(Y2Ng`e!CV7C|;aV}d3GIRv=`O#!SI9pw?UB4|d? zoS+3kO8{F2ur{}1kF`K+%&gU{)tR+{wIQ?iv36nB0oH-cnomas1lL#>Gd5gn&#X zf|>NsxpdT@U<$!Nf-4EG)^1>Iv33Vz3$Bn1!%PhY7^8Us7p|fpgut=K^h?XI)Y^c*Av`8a3esgK}XB!s3slVL~t{~ zEd(nFZY8*l;C6tPLPvKH+)1#K;4Xqy1gi<|Cb);-UV=3Q_YvGr@BqPs1ZxQ%B6yhK z5rRhv9wT_1;0c0t1WyvIC)hx+k>DwUB7$OqO$3_>wh(M3*hcU)!FGZj1Um_K5x4@L+~uYK7tnso+Egk;01#H1TPW1OmKkU6@r5VuM)gQ@H)X81aA_& zMesj@w+Y@Mc$eT1!FvSn6C5V^fZ#)dj|e^{_=Mn7g3ky(Cpbdz1;LjDUlDvw@D0IH zf^P|q5qwARJ;4tIKN9>z@H4?L1iupeM({hq9|Xq<{v`N|-~>Qp1Qvn_f=B`@K@>qW zfkt2>uoE~4oCGlhu>^4hWe8jZ@dRZF5(p9r$`O<&s6bGWfD-yM^g!A5L`xZIl)AN@id6X5RAn?E!{0Wm}Mm(Vk1E@ z!4`rY1bYacBY2766@oVi-T_!v)6rpqj|e^|_>$mTf*%QfBlrst8A)IRSnj2xSOOP8 z0zpNBN(5C1a1p{HYZIgrGz3`gr=u)_T!Lld4!Ip6U-!-LvS_0LW0EvO9`$gSWa*Y!16d9-9~UH!774# z2<{_zkl>&Bb`ZD;_7dzPc!7YrBJvf0Wg{KEM(`%V+XROQ zs8b@TQzAblI709h!BK#PIyv$?0_vm4UkH9DI03Lm5JVA(-kOIa3uT0b0kfC92mKo$zfLIGJQAPWU#p@1wRAd1C8u~@DlpnxnCkmXN6 z1S6pIiHIh!6T}ddAt(#5Tt`Rc2q=*vD3Kzn5L73iM2e_KkVcSBkO{EdKu3)UD5WAO zr6O7qv>|9u(21Z6L3e@zfaNASDkPu`i=gC+7(y_NU1Y-!s6HEkHR?yKE1e9SB zlw1+B3FZ+{gGEsFBbE>>Be)S@xt)$~Cb*U04uZP~?j~46@BqO>1dkFt39#0-)?wB$ zv~l>%`nkpWrS)Tr^+)SZ7VED#in2#JEK#v^_s7iEHE2_37sveH4 z`>f9~EA4l!w84!^i)vtrYDA}0iK=ReszIl0vp&tNw3D{}VLfiKo}j-*L`7PnqUo=9 zT30gbL)M3xbp>r*?kBj2q8dd<)9Globq=$BV?AoIen%D)tP`2_3F|s$Eh5qPt%ohv ikLV9?l0}jg*Ky-$`Wi(rn&47QWO3DSl@uAp*#80BNnSkw diff --git a/target/scala-2.12/classes/exu/exu_main$.class b/target/scala-2.12/classes/exu/exu_main$.class index e6a158752781c1529bba0d635f010e600713a2c6..01347c7c9f0c609b3e4c5ae384845c446e6a413f 100644 GIT binary patch delta 106 zcmZpXYmwV&yC;L7m~t&yC?L7m~#