Aligner

el2_ifu_bp_ctl.anno.json

@@ -102,6 +102,13 @@
       "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test",
+    "sources":[
+      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_ret_f",

el2_ifu_ifc_ctl.v

@@ -54,7 +54,7 @@ module el2_ifu_ifc_ctl(
   wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
-  wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
+  wire [29:0] address_upper = {io_ifc_fetch_addr_f[30:1]} + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
   wire  _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
   wire  _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
   wire  fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]

src/main/scala/ifu/el2_ifu_bp_ctl.scala

@@ -38,6 +38,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
     val ifu_bp_pc4_f = Output(UInt(2.W))
     val ifu_bp_valid_f = Output(UInt(2.W))
     val ifu_bp_poffset_f = Output(UInt(12.W))
+    val test = Output(UInt())
   })
 
   val TAG_START = 16+BTB_BTAG_SIZE
@@ -388,12 +389,13 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
 
   val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
   for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
-    bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j)&bht_bank_clken(i)(k))
+    bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j))
   }
 
   bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i)))
   bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
   bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
+  io.test := bht_rd_addr_f
 }
 
 object ifu_bp extends App {

src/main/scala/include/el2_bundle.scala

@@ -55,7 +55,7 @@ class el2_br_pkt_t extends Bundle {
   val br_error       = UInt(1.W)
   val br_start_error = UInt(1.W)
   val bank           = UInt(1.W)
-  val prett          = UInt(32.W)     // predicted ret target //[31:1] in swerv
+  val prett          = UInt(31.W)     // predicted ret target //[31:1] in swerv
   val way            = UInt(1.W)
   val ret            = UInt(1.W)
 }