diff --git a/exu.anno.json b/exu.anno.json index 3f5451bd..ad79e866 100644 --- a/exu.anno.json +++ b/exu.anno.json @@ -11,7 +11,7 @@ "sink":"~exu|exu>io_lsu_exu_exu_lsu_rs2_d", "sources":[ "~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs2_d", - "~exu|exu>io_dec_qual_lsu_d", + "~exu|exu>io_dec_exu_decode_exu_dec_qual_lsu_d", "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs2_en_d", "~exu|exu>io_lsu_exu_lsu_nonblock_load_data", "~exu|exu>io_dec_exu_decode_exu_dec_extint_stall", @@ -66,22 +66,6 @@ "~exu|exu>io_dec_exu_tlu_exu_exu_i0_br_index_r" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~exu|exu>io_lsu_exu_exu_lsu_rs1_d", - "sources":[ - "~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs1_d", - "~exu|exu>io_dec_exu_tlu_exu_dec_tlu_meihap", - "~exu|exu>io_dec_exu_decode_exu_dec_extint_stall", - "~exu|exu>io_dec_qual_lsu_d", - "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_en_d", - "~exu|exu>io_lsu_exu_lsu_nonblock_load_data", - "~exu|exu>io_dec_exu_decode_exu_exu_i0_result_x", - "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d", - "~exu|exu>io_dec_exu_decode_exu_dec_i0_result_r", - "~exu|exu>io_lsu_exu_lsu_result_m" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~exu|exu>io_exu_flush_final", @@ -132,6 +116,22 @@ "~exu|exu>io_dec_exu_dec_div_dec_div_cancel" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~exu|exu>io_lsu_exu_exu_lsu_rs1_d", + "sources":[ + "~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs1_d", + "~exu|exu>io_dec_exu_tlu_exu_dec_tlu_meihap", + "~exu|exu>io_dec_exu_decode_exu_dec_extint_stall", + "~exu|exu>io_dec_exu_decode_exu_dec_qual_lsu_d", + "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_en_d", + "~exu|exu>io_lsu_exu_lsu_nonblock_load_data", + "~exu|exu>io_dec_exu_decode_exu_exu_i0_result_x", + "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d", + "~exu|exu>io_dec_exu_decode_exu_dec_i0_result_r", + "~exu|exu>io_lsu_exu_lsu_result_m" + ] + }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" diff --git a/exu.fir b/exu.fir index 4a9386ef..402ba9a9 100644 --- a/exu.fir +++ b/exu.fir @@ -219,7 +219,7 @@ circuit exu : module exu_alu_ctl : input clock : Clock input reset : AsyncReset - output io : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_i0_pc_d : UInt<31>, flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip enable : UInt<1>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}} + output io : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip csr_rddata_in : UInt<32>, flip dec_i0_pc_d : UInt<31>, flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip enable : UInt<1>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}} wire ap_clz : UInt<1> ap_clz <= UInt<1>("h00") @@ -429,7 +429,7 @@ circuit exu : node _T_92 = and(io.i0_ap.unsign, _T_91) @[exu_alu_ctl.scala 154:82] node lt = or(_T_90, _T_92) @[exu_alu_ctl.scala 154:61] node ge = eq(lt, UInt<1>("h00")) @[exu_alu_ctl.scala 155:29] - node _T_93 = asSInt(io.dec_alu.dec_csr_rddata_d) @[exu_alu_ctl.scala 159:73] + node _T_93 = asSInt(io.csr_rddata_in) @[exu_alu_ctl.scala 159:62] node _T_94 = eq(ap_zbb, UInt<1>("h00")) @[exu_alu_ctl.scala 160:22] node _T_95 = and(io.i0_ap.land, _T_94) @[exu_alu_ctl.scala 160:20] node _T_96 = bits(_T_95, 0, 0) @[exu_alu_ctl.scala 160:31] @@ -44537,49 +44537,49 @@ circuit exu : module exu : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}, exu_flush_final : UInt<1>, exu_div_result : UInt<32>, exu_div_wren : UInt<1>, flip dbg_cmd_wrdata : UInt<32>, flip lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>, lsu_nonblock_load_data : UInt<32>}, exu_flush_path_final : UInt<31>, flip dec_qual_lsu_d : UInt<1>} + output io : {flip scan_mode : UInt<1>, dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_qual_lsu_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}, exu_flush_final : UInt<1>, exu_div_result : UInt<32>, exu_div_wren : UInt<1>, flip dbg_cmd_wrdata : UInt<32>, flip dec_csr_rddata_d : UInt<32>, flip lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>, lsu_nonblock_load_data : UInt<32>}, exu_flush_path_final : UInt<31>} - wire ghr_x_ns : UInt<8> @[exu.scala 33:57] - wire ghr_d_ns : UInt<8> @[exu.scala 34:57] - wire ghr_d : UInt<8> @[exu.scala 35:67] - wire i0_taken_d : UInt<1> @[exu.scala 36:63] - wire mul_valid_x : UInt<1> @[exu.scala 37:63] - wire i0_valid_d : UInt<1> @[exu.scala 38:63] - wire i0_branch_x : UInt<1> @[exu.scala 39:39] - wire i0_predict_newp_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 40:51] - wire i0_flush_path_d : UInt<31> @[exu.scala 41:53] - wire i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 42:53] - wire i0_pp_r : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 43:65] - wire i0_predict_p_x : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 44:53] - wire final_predict_mp : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 45:45] - wire pred_correct_npc_r : UInt<32> @[exu.scala 46:51] - wire i0_pred_correct_upper_d : UInt<1> @[exu.scala 47:41] - wire i0_flush_upper_d : UInt<1> @[exu.scala 48:45] - io.exu_bp.exu_mp_pkt.bits.prett <= UInt<1>("h00") @[exu.scala 49:57] - io.exu_bp.exu_mp_pkt.bits.br_start_error <= UInt<1>("h00") @[exu.scala 50:44] - io.exu_bp.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[exu.scala 51:39] - io.exu_bp.exu_mp_pkt.valid <= UInt<1>("h00") @[exu.scala 52:53] - i0_pp_r.bits.toffset <= UInt<1>("h00") @[exu.scala 53:39] - node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 55:69] - node _T = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69] - node x_data_en_q1 = and(_T, io.dec_exu.dec_alu.dec_csr_ren_d) @[exu.scala 56:73] - node _T_1 = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 57:69] - node x_data_en_q2 = and(_T_1, io.dec_exu.decode_exu.dec_i0_branch_d) @[exu.scala 57:73] - node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 58:69] - node _T_2 = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 59:69] - node r_data_en_q2 = and(_T_2, i0_branch_x) @[exu.scala 59:73] - node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 60:68] - node r_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 0, 0) @[exu.scala 61:68] + wire ghr_x_ns : UInt<8> @[exu.scala 32:57] + wire ghr_d_ns : UInt<8> @[exu.scala 33:57] + wire ghr_d : UInt<8> @[exu.scala 34:67] + wire i0_taken_d : UInt<1> @[exu.scala 35:63] + wire mul_valid_x : UInt<1> @[exu.scala 36:63] + wire i0_valid_d : UInt<1> @[exu.scala 37:63] + wire i0_branch_x : UInt<1> @[exu.scala 38:39] + wire i0_predict_newp_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 39:51] + wire i0_flush_path_d : UInt<31> @[exu.scala 40:53] + wire i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 41:53] + wire i0_pp_r : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 42:65] + wire i0_predict_p_x : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 43:53] + wire final_predict_mp : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 44:45] + wire pred_correct_npc_r : UInt<32> @[exu.scala 45:51] + wire i0_pred_correct_upper_d : UInt<1> @[exu.scala 46:41] + wire i0_flush_upper_d : UInt<1> @[exu.scala 47:45] + io.exu_bp.exu_mp_pkt.bits.prett <= UInt<1>("h00") @[exu.scala 48:57] + io.exu_bp.exu_mp_pkt.bits.br_start_error <= UInt<1>("h00") @[exu.scala 49:44] + io.exu_bp.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[exu.scala 50:39] + io.exu_bp.exu_mp_pkt.valid <= UInt<1>("h00") @[exu.scala 51:53] + i0_pp_r.bits.toffset <= UInt<1>("h00") @[exu.scala 52:39] + node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 54:69] + node _T = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 55:69] + node x_data_en_q1 = and(_T, io.dec_exu.dec_alu.dec_csr_ren_d) @[exu.scala 55:73] + node _T_1 = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69] + node x_data_en_q2 = and(_T_1, io.dec_exu.decode_exu.dec_i0_branch_d) @[exu.scala 56:73] + node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 57:69] + node _T_2 = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 58:69] + node r_data_en_q2 = and(_T_2, i0_branch_x) @[exu.scala 58:73] + node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 59:68] + node r_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 0, 0) @[exu.scala 60:68] node _T_3 = cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d) @[Cat.scala 29:58] node predpipe_d = cat(_T_3, io.dec_exu.decode_exu.i0_predict_btag_d) @[Cat.scala 29:58] - node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 64:68] + node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 63:68] wire _T_5 : UInt<31> @[lib.scala 648:38] _T_5 <= UInt<1>("h00") @[lib.scala 648:38] reg i0_flush_path_x : UInt, clock with : (reset => (reset, _T_5)) @[Reg.scala 27:20] when _T_4 : @[Reg.scala 28:19] i0_flush_path_x <= i0_flush_path_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 65:116] + node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 64:116] node _T_7 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] wire _T_8 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] _T_8.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] @@ -44613,21 +44613,21 @@ circuit exu : _T_9.bits.misp <= i0_predict_p_d.bits.misp @[Reg.scala 28:23] _T_9.valid <= i0_predict_p_d.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - i0_predict_p_x.bits.prett <= _T_9.bits.prett @[exu.scala 65:55] - i0_predict_p_x.bits.pret <= _T_9.bits.pret @[exu.scala 65:55] - i0_predict_p_x.bits.way <= _T_9.bits.way @[exu.scala 65:55] - i0_predict_p_x.bits.pja <= _T_9.bits.pja @[exu.scala 65:55] - i0_predict_p_x.bits.pcall <= _T_9.bits.pcall @[exu.scala 65:55] - i0_predict_p_x.bits.br_start_error <= _T_9.bits.br_start_error @[exu.scala 65:55] - i0_predict_p_x.bits.br_error <= _T_9.bits.br_error @[exu.scala 65:55] - i0_predict_p_x.bits.toffset <= _T_9.bits.toffset @[exu.scala 65:55] - i0_predict_p_x.bits.hist <= _T_9.bits.hist @[exu.scala 65:55] - i0_predict_p_x.bits.pc4 <= _T_9.bits.pc4 @[exu.scala 65:55] - i0_predict_p_x.bits.boffset <= _T_9.bits.boffset @[exu.scala 65:55] - i0_predict_p_x.bits.ataken <= _T_9.bits.ataken @[exu.scala 65:55] - i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 65:55] - i0_predict_p_x.valid <= _T_9.valid @[exu.scala 65:55] - node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 66:79] + i0_predict_p_x.bits.prett <= _T_9.bits.prett @[exu.scala 64:55] + i0_predict_p_x.bits.pret <= _T_9.bits.pret @[exu.scala 64:55] + i0_predict_p_x.bits.way <= _T_9.bits.way @[exu.scala 64:55] + i0_predict_p_x.bits.pja <= _T_9.bits.pja @[exu.scala 64:55] + i0_predict_p_x.bits.pcall <= _T_9.bits.pcall @[exu.scala 64:55] + i0_predict_p_x.bits.br_start_error <= _T_9.bits.br_start_error @[exu.scala 64:55] + i0_predict_p_x.bits.br_error <= _T_9.bits.br_error @[exu.scala 64:55] + i0_predict_p_x.bits.toffset <= _T_9.bits.toffset @[exu.scala 64:55] + i0_predict_p_x.bits.hist <= _T_9.bits.hist @[exu.scala 64:55] + i0_predict_p_x.bits.pc4 <= _T_9.bits.pc4 @[exu.scala 64:55] + i0_predict_p_x.bits.boffset <= _T_9.bits.boffset @[exu.scala 64:55] + i0_predict_p_x.bits.ataken <= _T_9.bits.ataken @[exu.scala 64:55] + i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 64:55] + i0_predict_p_x.valid <= _T_9.valid @[exu.scala 64:55] + node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 65:79] inst rvclkhdr of rvclkhdr @[lib.scala 404:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -44638,7 +44638,7 @@ circuit exu : when _T_10 : @[Reg.scala 28:19] predpipe_x <= predpipe_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 67:88] + node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 66:88] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -44649,7 +44649,7 @@ circuit exu : when _T_11 : @[Reg.scala 28:19] predpipe_r <= predpipe_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 68:86] + node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 67:86] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -44660,7 +44660,7 @@ circuit exu : when _T_12 : @[Reg.scala 28:19] ghr_x <= ghr_x_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 69:75] + node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 68:75] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -44671,7 +44671,7 @@ circuit exu : when _T_13 : @[Reg.scala 28:19] i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 70:66] + node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 69:66] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -44682,7 +44682,7 @@ circuit exu : when _T_14 : @[Reg.scala 28:19] i0_flush_upper_x <= i0_flush_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] + node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 70:84] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -44693,7 +44693,7 @@ circuit exu : when _T_15 : @[Reg.scala 28:19] i0_taken_x <= i0_taken_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 72:84] + node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -44704,7 +44704,7 @@ circuit exu : when _T_16 : @[Reg.scala 28:19] i0_valid_x <= i0_valid_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 73:93] + node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 72:93] node _T_18 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] wire _T_19 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] _T_19.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] @@ -44738,44 +44738,44 @@ circuit exu : _T_20.bits.misp <= i0_predict_p_x.bits.misp @[Reg.scala 28:23] _T_20.valid <= i0_predict_p_x.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - i0_pp_r.bits.prett <= _T_20.bits.prett @[exu.scala 73:31] - i0_pp_r.bits.pret <= _T_20.bits.pret @[exu.scala 73:31] - i0_pp_r.bits.way <= _T_20.bits.way @[exu.scala 73:31] - i0_pp_r.bits.pja <= _T_20.bits.pja @[exu.scala 73:31] - i0_pp_r.bits.pcall <= _T_20.bits.pcall @[exu.scala 73:31] - i0_pp_r.bits.br_start_error <= _T_20.bits.br_start_error @[exu.scala 73:31] - i0_pp_r.bits.br_error <= _T_20.bits.br_error @[exu.scala 73:31] - i0_pp_r.bits.toffset <= _T_20.bits.toffset @[exu.scala 73:31] - i0_pp_r.bits.hist <= _T_20.bits.hist @[exu.scala 73:31] - i0_pp_r.bits.pc4 <= _T_20.bits.pc4 @[exu.scala 73:31] - i0_pp_r.bits.boffset <= _T_20.bits.boffset @[exu.scala 73:31] - i0_pp_r.bits.ataken <= _T_20.bits.ataken @[exu.scala 73:31] - i0_pp_r.bits.misp <= _T_20.bits.misp @[exu.scala 73:31] - i0_pp_r.valid <= _T_20.valid @[exu.scala 73:31] - node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 74:94] - node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 74:111] + i0_pp_r.bits.prett <= _T_20.bits.prett @[exu.scala 72:31] + i0_pp_r.bits.pret <= _T_20.bits.pret @[exu.scala 72:31] + i0_pp_r.bits.way <= _T_20.bits.way @[exu.scala 72:31] + i0_pp_r.bits.pja <= _T_20.bits.pja @[exu.scala 72:31] + i0_pp_r.bits.pcall <= _T_20.bits.pcall @[exu.scala 72:31] + i0_pp_r.bits.br_start_error <= _T_20.bits.br_start_error @[exu.scala 72:31] + i0_pp_r.bits.br_error <= _T_20.bits.br_error @[exu.scala 72:31] + i0_pp_r.bits.toffset <= _T_20.bits.toffset @[exu.scala 72:31] + i0_pp_r.bits.hist <= _T_20.bits.hist @[exu.scala 72:31] + i0_pp_r.bits.pc4 <= _T_20.bits.pc4 @[exu.scala 72:31] + i0_pp_r.bits.boffset <= _T_20.bits.boffset @[exu.scala 72:31] + i0_pp_r.bits.ataken <= _T_20.bits.ataken @[exu.scala 72:31] + i0_pp_r.bits.misp <= _T_20.bits.misp @[exu.scala 72:31] + i0_pp_r.valid <= _T_20.valid @[exu.scala 72:31] + node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 73:94] + node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 73:111] wire _T_23 : UInt<6> @[lib.scala 648:38] _T_23 <= UInt<1>("h00") @[lib.scala 648:38] reg pred_temp1 : UInt, clock with : (reset => (reset, _T_23)) @[Reg.scala 27:20] when _T_22 : @[Reg.scala 28:19] pred_temp1 <= _T_21 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 75:109] + node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 74:109] wire _T_25 : UInt @[lib.scala 588:35] _T_25 <= UInt<1>("h00") @[lib.scala 588:35] reg i0_pred_correct_upper_r : UInt, clock with : (reset => (reset, _T_25)) @[Reg.scala 27:20] when _T_24 : @[Reg.scala 28:19] i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 76:73] + node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 75:73] wire _T_27 : UInt @[lib.scala 648:38] _T_27 <= UInt<1>("h00") @[lib.scala 648:38] reg i0_flush_path_upper_r : UInt, clock with : (reset => (reset, _T_27)) @[Reg.scala 27:20] when _T_26 : @[Reg.scala 28:19] i0_flush_path_upper_r <= i0_flush_path_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 77:106] - node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 77:124] + node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 76:106] + node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 76:124] wire _T_30 : UInt<25> @[lib.scala 648:38] _T_30 <= UInt<1>("h00") @[lib.scala 648:38] reg pred_temp2 : UInt, clock with : (reset => (reset, _T_30)) @[Reg.scala 27:20] @@ -44783,7 +44783,7 @@ circuit exu : pred_temp2 <= _T_28 @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_31 = cat(pred_temp2, pred_temp1) @[Cat.scala 29:58] - pred_correct_npc_r <= _T_31 @[exu.scala 78:45] + pred_correct_npc_r <= _T_31 @[exu.scala 77:45] wire _T_32 : UInt _T_32 <= UInt<1>("h00") node _T_33 = xor(ghr_d_ns, _T_32) @[lib.scala 448:21] @@ -44793,7 +44793,7 @@ circuit exu : _T_35 <= ghr_d_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_32 <= _T_35 @[lib.scala 451:16] - ghr_d <= _T_32 @[exu.scala 79:43] + ghr_d <= _T_32 @[exu.scala 78:43] wire _T_36 : UInt<1> _T_36 <= UInt<1>("h00") node _T_37 = xor(io.dec_exu.decode_exu.mul_p.valid, _T_36) @[lib.scala 470:21] @@ -44803,7 +44803,7 @@ circuit exu : _T_39 <= io.dec_exu.decode_exu.mul_p.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_36 <= _T_39 @[lib.scala 473:16] - mul_valid_x <= _T_36 @[exu.scala 80:39] + mul_valid_x <= _T_36 @[exu.scala 79:39] wire _T_40 : UInt _T_40 <= UInt<1>("h00") node _T_41 = xor(io.dec_exu.decode_exu.dec_i0_branch_d, _T_40) @[lib.scala 448:21] @@ -44813,29 +44813,29 @@ circuit exu : _T_43 <= io.dec_exu.decode_exu.dec_i0_branch_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_40 <= _T_43 @[lib.scala 451:16] - i0_branch_x <= _T_40 @[exu.scala 81:39] - node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 83:80] - node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 83:130] - node _T_46 = or(_T_44, _T_45) @[exu.scala 83:84] - node _T_47 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 83:180] - node _T_48 = or(_T_46, _T_47) @[exu.scala 83:134] - node _T_49 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 83:230] - node i0_rs1_bypass_en_d = or(_T_48, _T_49) @[exu.scala 83:184] - node _T_50 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 84:80] - node _T_51 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 84:130] - node _T_52 = or(_T_50, _T_51) @[exu.scala 84:84] - node _T_53 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 84:180] - node _T_54 = or(_T_52, _T_53) @[exu.scala 84:134] - node _T_55 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 84:230] - node i0_rs2_bypass_en_d = or(_T_54, _T_55) @[exu.scala 84:184] - node _T_56 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 87:49] - node _T_57 = bits(_T_56, 0, 0) @[exu.scala 87:53] - node _T_58 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 88:49] - node _T_59 = bits(_T_58, 0, 0) @[exu.scala 88:53] - node _T_60 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 89:49] - node _T_61 = bits(_T_60, 0, 0) @[exu.scala 89:53] - node _T_62 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 90:49] - node _T_63 = bits(_T_62, 0, 0) @[exu.scala 90:53] + i0_branch_x <= _T_40 @[exu.scala 80:39] + node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 82:80] + node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 82:130] + node _T_46 = or(_T_44, _T_45) @[exu.scala 82:84] + node _T_47 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 82:180] + node _T_48 = or(_T_46, _T_47) @[exu.scala 82:134] + node _T_49 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 82:230] + node i0_rs1_bypass_en_d = or(_T_48, _T_49) @[exu.scala 82:184] + node _T_50 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 83:80] + node _T_51 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 83:130] + node _T_52 = or(_T_50, _T_51) @[exu.scala 83:84] + node _T_53 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 83:180] + node _T_54 = or(_T_52, _T_53) @[exu.scala 83:134] + node _T_55 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 83:230] + node i0_rs2_bypass_en_d = or(_T_54, _T_55) @[exu.scala 83:184] + node _T_56 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 86:49] + node _T_57 = bits(_T_56, 0, 0) @[exu.scala 86:53] + node _T_58 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 87:49] + node _T_59 = bits(_T_58, 0, 0) @[exu.scala 87:53] + node _T_60 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 88:49] + node _T_61 = bits(_T_60, 0, 0) @[exu.scala 88:53] + node _T_62 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 89:49] + node _T_63 = bits(_T_62, 0, 0) @[exu.scala 89:53] node _T_64 = mux(_T_57, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_65 = mux(_T_59, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_66 = mux(_T_61, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44845,14 +44845,14 @@ circuit exu : node _T_70 = or(_T_69, _T_67) @[Mux.scala 27:72] wire i0_rs1_bypass_data_d : UInt<32> @[Mux.scala 27:72] i0_rs1_bypass_data_d <= _T_70 @[Mux.scala 27:72] - node _T_71 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 93:49] - node _T_72 = bits(_T_71, 0, 0) @[exu.scala 93:53] - node _T_73 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 94:49] - node _T_74 = bits(_T_73, 0, 0) @[exu.scala 94:53] - node _T_75 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 95:49] - node _T_76 = bits(_T_75, 0, 0) @[exu.scala 95:53] - node _T_77 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 96:49] - node _T_78 = bits(_T_77, 0, 0) @[exu.scala 96:53] + node _T_71 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 92:49] + node _T_72 = bits(_T_71, 0, 0) @[exu.scala 92:53] + node _T_73 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 93:49] + node _T_74 = bits(_T_73, 0, 0) @[exu.scala 93:53] + node _T_75 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 94:49] + node _T_76 = bits(_T_75, 0, 0) @[exu.scala 94:53] + node _T_77 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 95:49] + node _T_78 = bits(_T_77, 0, 0) @[exu.scala 95:53] node _T_79 = mux(_T_72, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_80 = mux(_T_74, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_81 = mux(_T_76, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44862,19 +44862,19 @@ circuit exu : node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72] wire i0_rs2_bypass_data_d : UInt<32> @[Mux.scala 27:72] i0_rs2_bypass_data_d <= _T_85 @[Mux.scala 27:72] - node _T_86 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 100:24] - node _T_87 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 101:6] - node _T_88 = and(_T_87, io.dec_exu.decode_exu.dec_i0_select_pc_d) @[exu.scala 101:26] - node _T_89 = bits(_T_88, 0, 0) @[exu.scala 101:71] + node _T_86 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 99:24] + node _T_87 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 100:6] + node _T_88 = and(_T_87, io.dec_exu.decode_exu.dec_i0_select_pc_d) @[exu.scala 100:26] + node _T_89 = bits(_T_88, 0, 0) @[exu.scala 100:71] node _T_90 = cat(io.dec_exu.ib_exu.dec_i0_pc_d, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_91 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 102:6] - node _T_92 = and(_T_91, io.dec_exu.ib_exu.dec_debug_wdata_rs1_d) @[exu.scala 102:26] - node _T_93 = bits(_T_92, 0, 0) @[exu.scala 102:70] - node _T_94 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 103:6] - node _T_95 = eq(io.dec_exu.ib_exu.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[exu.scala 103:28] - node _T_96 = and(_T_94, _T_95) @[exu.scala 103:26] - node _T_97 = and(_T_96, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 103:69] - node _T_98 = bits(_T_97, 0, 0) @[exu.scala 103:110] + node _T_91 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 101:6] + node _T_92 = and(_T_91, io.dec_exu.ib_exu.dec_debug_wdata_rs1_d) @[exu.scala 101:26] + node _T_93 = bits(_T_92, 0, 0) @[exu.scala 101:70] + node _T_94 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 102:6] + node _T_95 = eq(io.dec_exu.ib_exu.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[exu.scala 102:28] + node _T_96 = and(_T_94, _T_95) @[exu.scala 102:26] + node _T_97 = and(_T_96, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 102:69] + node _T_98 = bits(_T_97, 0, 0) @[exu.scala 102:110] node _T_99 = mux(_T_86, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_100 = mux(_T_89, _T_90, UInt<1>("h00")) @[Mux.scala 27:72] node _T_101 = mux(_T_93, io.dbg_cmd_wrdata, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44884,7 +44884,7 @@ circuit exu : node _T_105 = or(_T_104, _T_102) @[Mux.scala 27:72] wire i0_rs1_d : UInt<32> @[Mux.scala 27:72] i0_rs1_d <= _T_105 @[Mux.scala 27:72] - node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 105:88] + node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 104:88] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -44895,13 +44895,13 @@ circuit exu : when _T_106 : @[Reg.scala 28:19] _T_107 <= i0_rs1_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_107 @[exu.scala 105:57] - node _T_108 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 108:6] - node _T_109 = and(_T_108, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 108:26] - node _T_110 = bits(_T_109, 0, 0) @[exu.scala 108:67] - node _T_111 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 109:6] - node _T_112 = bits(_T_111, 0, 0) @[exu.scala 109:27] - node _T_113 = bits(i0_rs2_bypass_en_d, 0, 0) @[exu.scala 110:26] + io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_107 @[exu.scala 104:57] + node _T_108 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 107:6] + node _T_109 = and(_T_108, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 107:26] + node _T_110 = bits(_T_109, 0, 0) @[exu.scala 107:67] + node _T_111 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 108:6] + node _T_112 = bits(_T_111, 0, 0) @[exu.scala 108:27] + node _T_113 = bits(i0_rs2_bypass_en_d, 0, 0) @[exu.scala 109:26] node _T_114 = mux(_T_110, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_115 = mux(_T_112, io.dec_exu.decode_exu.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_116 = mux(_T_113, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44909,18 +44909,18 @@ circuit exu : node _T_118 = or(_T_117, _T_116) @[Mux.scala 27:72] wire i0_rs2_d : UInt<32> @[Mux.scala 27:72] i0_rs2_d <= _T_118 @[Mux.scala 27:72] - node _T_119 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 115:6] - node _T_120 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 115:28] - node _T_121 = and(_T_119, _T_120) @[exu.scala 115:26] - node _T_122 = and(_T_121, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 115:68] - node _T_123 = and(_T_122, io.dec_qual_lsu_d) @[exu.scala 115:108] - node _T_124 = bits(_T_123, 0, 0) @[exu.scala 115:129] - node _T_125 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 116:27] - node _T_126 = and(i0_rs1_bypass_en_d, _T_125) @[exu.scala 116:25] - node _T_127 = and(_T_126, io.dec_qual_lsu_d) @[exu.scala 116:67] - node _T_128 = bits(_T_127, 0, 0) @[exu.scala 116:88] - node _T_129 = and(io.dec_exu.decode_exu.dec_extint_stall, io.dec_qual_lsu_d) @[exu.scala 117:45] - node _T_130 = bits(_T_129, 0, 0) @[exu.scala 117:66] + node _T_119 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 114:6] + node _T_120 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 114:28] + node _T_121 = and(_T_119, _T_120) @[exu.scala 114:26] + node _T_122 = and(_T_121, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 114:68] + node _T_123 = and(_T_122, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 114:108] + node _T_124 = bits(_T_123, 0, 0) @[exu.scala 114:148] + node _T_125 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 115:27] + node _T_126 = and(i0_rs1_bypass_en_d, _T_125) @[exu.scala 115:25] + node _T_127 = and(_T_126, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 115:67] + node _T_128 = bits(_T_127, 0, 0) @[exu.scala 115:107] + node _T_129 = and(io.dec_exu.decode_exu.dec_extint_stall, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 116:45] + node _T_130 = bits(_T_129, 0, 0) @[exu.scala 116:85] node _T_131 = cat(io.dec_exu.tlu_exu.dec_tlu_meihap, UInt<2>("h00")) @[Cat.scala 29:58] node _T_132 = mux(_T_124, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_133 = mux(_T_128, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44929,40 +44929,39 @@ circuit exu : node _T_136 = or(_T_135, _T_134) @[Mux.scala 27:72] wire _T_137 : UInt<32> @[Mux.scala 27:72] _T_137 <= _T_136 @[Mux.scala 27:72] - io.lsu_exu.exu_lsu_rs1_d <= _T_137 @[exu.scala 114:27] - node _T_138 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 121:6] - node _T_139 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 121:28] - node _T_140 = and(_T_138, _T_139) @[exu.scala 121:26] - node _T_141 = and(_T_140, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 121:68] - node _T_142 = and(_T_141, io.dec_qual_lsu_d) @[exu.scala 121:108] - node _T_143 = bits(_T_142, 0, 0) @[exu.scala 121:129] - node _T_144 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 122:27] - node _T_145 = and(i0_rs2_bypass_en_d, _T_144) @[exu.scala 122:25] - node _T_146 = and(_T_145, io.dec_qual_lsu_d) @[exu.scala 122:67] - node _T_147 = bits(_T_146, 0, 0) @[exu.scala 122:88] + io.lsu_exu.exu_lsu_rs1_d <= _T_137 @[exu.scala 113:27] + node _T_138 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 120:6] + node _T_139 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 120:28] + node _T_140 = and(_T_138, _T_139) @[exu.scala 120:26] + node _T_141 = and(_T_140, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 120:68] + node _T_142 = and(_T_141, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 120:108] + node _T_143 = bits(_T_142, 0, 0) @[exu.scala 120:148] + node _T_144 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 121:27] + node _T_145 = and(i0_rs2_bypass_en_d, _T_144) @[exu.scala 121:25] + node _T_146 = and(_T_145, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 121:67] + node _T_147 = bits(_T_146, 0, 0) @[exu.scala 121:107] node _T_148 = mux(_T_143, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_149 = mux(_T_147, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_150 = or(_T_148, _T_149) @[Mux.scala 27:72] wire _T_151 : UInt<32> @[Mux.scala 27:72] _T_151 <= _T_150 @[Mux.scala 27:72] - io.lsu_exu.exu_lsu_rs2_d <= _T_151 @[exu.scala 120:27] - node _T_152 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 126:6] - node _T_153 = and(_T_152, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 126:26] - node _T_154 = bits(_T_153, 0, 0) @[exu.scala 126:67] - node _T_155 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 127:26] + io.lsu_exu.exu_lsu_rs2_d <= _T_151 @[exu.scala 119:27] + node _T_152 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 125:6] + node _T_153 = and(_T_152, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 125:26] + node _T_154 = bits(_T_153, 0, 0) @[exu.scala 125:67] + node _T_155 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 126:26] node _T_156 = mux(_T_154, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_157 = mux(_T_155, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_158 = or(_T_156, _T_157) @[Mux.scala 27:72] wire muldiv_rs1_d : UInt<32> @[Mux.scala 27:72] muldiv_rs1_d <= _T_158 @[Mux.scala 27:72] - inst i_alu of exu_alu_ctl @[exu.scala 130:19] + inst i_alu of exu_alu_ctl @[exu.scala 129:19] i_alu.clock <= clock i_alu.reset <= reset - io.dec_exu.dec_alu.exu_i0_pc_x <= i_alu.io.dec_alu.exu_i0_pc_x @[exu.scala 131:20] - i_alu.io.dec_alu.dec_i0_br_immed_d <= io.dec_exu.dec_alu.dec_i0_br_immed_d @[exu.scala 131:20] - i_alu.io.dec_alu.dec_csr_rddata_d <= io.dec_exu.dec_alu.dec_csr_rddata_d @[exu.scala 131:20] - i_alu.io.dec_alu.dec_csr_ren_d <= io.dec_exu.dec_alu.dec_csr_ren_d @[exu.scala 131:20] - i_alu.io.dec_alu.dec_i0_alu_decode_d <= io.dec_exu.dec_alu.dec_i0_alu_decode_d @[exu.scala 131:20] + io.dec_exu.dec_alu.exu_i0_pc_x <= i_alu.io.dec_alu.exu_i0_pc_x @[exu.scala 130:20] + i_alu.io.dec_alu.dec_i0_br_immed_d <= io.dec_exu.dec_alu.dec_i0_br_immed_d @[exu.scala 130:20] + i_alu.io.dec_alu.dec_csr_ren_d <= io.dec_exu.dec_alu.dec_csr_ren_d @[exu.scala 130:20] + i_alu.io.dec_alu.dec_i0_alu_decode_d <= io.dec_exu.dec_alu.dec_i0_alu_decode_d @[exu.scala 130:20] i_alu.io.scan_mode <= io.scan_mode @[exu.scala 132:35] i_alu.io.enable <= x_data_en @[exu.scala 133:45] i_alu.io.pp_in.bits.prett <= i0_predict_newp_d.bits.prett @[exu.scala 134:45] @@ -44980,155 +44979,156 @@ circuit exu : i_alu.io.pp_in.bits.misp <= i0_predict_newp_d.bits.misp @[exu.scala 134:45] i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[exu.scala 134:45] i_alu.io.flush_upper_x <= i0_flush_upper_x @[exu.scala 135:33] - i_alu.io.dec_tlu_flush_lower_r <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[exu.scala 136:41] - node _T_159 = asSInt(i0_rs1_d) @[exu.scala 137:50] - i_alu.io.a_in <= _T_159 @[exu.scala 137:39] - i_alu.io.b_in <= i0_rs2_d @[exu.scala 138:39] - i_alu.io.dec_i0_pc_d <= io.dec_exu.ib_exu.dec_i0_pc_d @[exu.scala 139:33] - i_alu.io.i0_ap.csr_imm <= io.dec_exu.decode_exu.i0_ap.csr_imm @[exu.scala 140:51] - i_alu.io.i0_ap.csr_write <= io.dec_exu.decode_exu.i0_ap.csr_write @[exu.scala 140:51] - i_alu.io.i0_ap.predict_nt <= io.dec_exu.decode_exu.i0_ap.predict_nt @[exu.scala 140:51] - i_alu.io.i0_ap.predict_t <= io.dec_exu.decode_exu.i0_ap.predict_t @[exu.scala 140:51] - i_alu.io.i0_ap.jal <= io.dec_exu.decode_exu.i0_ap.jal @[exu.scala 140:51] - i_alu.io.i0_ap.unsign <= io.dec_exu.decode_exu.i0_ap.unsign @[exu.scala 140:51] - i_alu.io.i0_ap.slt <= io.dec_exu.decode_exu.i0_ap.slt @[exu.scala 140:51] - i_alu.io.i0_ap.sub <= io.dec_exu.decode_exu.i0_ap.sub @[exu.scala 140:51] - i_alu.io.i0_ap.add <= io.dec_exu.decode_exu.i0_ap.add @[exu.scala 140:51] - i_alu.io.i0_ap.bge <= io.dec_exu.decode_exu.i0_ap.bge @[exu.scala 140:51] - i_alu.io.i0_ap.blt <= io.dec_exu.decode_exu.i0_ap.blt @[exu.scala 140:51] - i_alu.io.i0_ap.bne <= io.dec_exu.decode_exu.i0_ap.bne @[exu.scala 140:51] - i_alu.io.i0_ap.beq <= io.dec_exu.decode_exu.i0_ap.beq @[exu.scala 140:51] - i_alu.io.i0_ap.sra <= io.dec_exu.decode_exu.i0_ap.sra @[exu.scala 140:51] - i_alu.io.i0_ap.srl <= io.dec_exu.decode_exu.i0_ap.srl @[exu.scala 140:51] - i_alu.io.i0_ap.sll <= io.dec_exu.decode_exu.i0_ap.sll @[exu.scala 140:51] - i_alu.io.i0_ap.lxor <= io.dec_exu.decode_exu.i0_ap.lxor @[exu.scala 140:51] - i_alu.io.i0_ap.lor <= io.dec_exu.decode_exu.i0_ap.lor @[exu.scala 140:51] - i_alu.io.i0_ap.land <= io.dec_exu.decode_exu.i0_ap.land @[exu.scala 140:51] - i_alu.io.i0_ap.zba <= io.dec_exu.decode_exu.i0_ap.zba @[exu.scala 140:51] - i_alu.io.i0_ap.sh3add <= io.dec_exu.decode_exu.i0_ap.sh3add @[exu.scala 140:51] - i_alu.io.i0_ap.sh2add <= io.dec_exu.decode_exu.i0_ap.sh2add @[exu.scala 140:51] - i_alu.io.i0_ap.sh1add <= io.dec_exu.decode_exu.i0_ap.sh1add @[exu.scala 140:51] - i_alu.io.i0_ap.sbext <= io.dec_exu.decode_exu.i0_ap.sbext @[exu.scala 140:51] - i_alu.io.i0_ap.sbinv <= io.dec_exu.decode_exu.i0_ap.sbinv @[exu.scala 140:51] - i_alu.io.i0_ap.sbclr <= io.dec_exu.decode_exu.i0_ap.sbclr @[exu.scala 140:51] - i_alu.io.i0_ap.sbset <= io.dec_exu.decode_exu.i0_ap.sbset @[exu.scala 140:51] - i_alu.io.i0_ap.zbb <= io.dec_exu.decode_exu.i0_ap.zbb @[exu.scala 140:51] - i_alu.io.i0_ap.gorc <= io.dec_exu.decode_exu.i0_ap.gorc @[exu.scala 140:51] - i_alu.io.i0_ap.grev <= io.dec_exu.decode_exu.i0_ap.grev @[exu.scala 140:51] - i_alu.io.i0_ap.ror <= io.dec_exu.decode_exu.i0_ap.ror @[exu.scala 140:51] - i_alu.io.i0_ap.rol <= io.dec_exu.decode_exu.i0_ap.rol @[exu.scala 140:51] - i_alu.io.i0_ap.packh <= io.dec_exu.decode_exu.i0_ap.packh @[exu.scala 140:51] - i_alu.io.i0_ap.packu <= io.dec_exu.decode_exu.i0_ap.packu @[exu.scala 140:51] - i_alu.io.i0_ap.pack <= io.dec_exu.decode_exu.i0_ap.pack @[exu.scala 140:51] - i_alu.io.i0_ap.max <= io.dec_exu.decode_exu.i0_ap.max @[exu.scala 140:51] - i_alu.io.i0_ap.min <= io.dec_exu.decode_exu.i0_ap.min @[exu.scala 140:51] - i_alu.io.i0_ap.sro <= io.dec_exu.decode_exu.i0_ap.sro @[exu.scala 140:51] - i_alu.io.i0_ap.slo <= io.dec_exu.decode_exu.i0_ap.slo @[exu.scala 140:51] - i_alu.io.i0_ap.sext_h <= io.dec_exu.decode_exu.i0_ap.sext_h @[exu.scala 140:51] - i_alu.io.i0_ap.sext_b <= io.dec_exu.decode_exu.i0_ap.sext_b @[exu.scala 140:51] - i_alu.io.i0_ap.pcnt <= io.dec_exu.decode_exu.i0_ap.pcnt @[exu.scala 140:51] - i_alu.io.i0_ap.ctz <= io.dec_exu.decode_exu.i0_ap.ctz @[exu.scala 140:51] - i_alu.io.i0_ap.clz <= io.dec_exu.decode_exu.i0_ap.clz @[exu.scala 140:51] - i0_flush_upper_d <= i_alu.io.flush_upper_out @[exu.scala 142:35] - i0_flush_path_d <= i_alu.io.flush_path_out @[exu.scala 143:45] - io.exu_flush_final <= i_alu.io.flush_final_out @[exu.scala 144:27] - i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[exu.scala 145:45] - i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[exu.scala 145:45] - i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[exu.scala 145:45] - i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[exu.scala 145:45] - i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[exu.scala 145:45] - i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[exu.scala 145:45] - i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[exu.scala 145:45] - i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[exu.scala 145:45] - i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[exu.scala 145:45] - i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[exu.scala 145:45] - i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[exu.scala 145:45] - i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[exu.scala 145:45] - i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 145:45] - i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 145:45] - i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 146:27] - inst i_mul of exu_mul_ctl @[exu.scala 148:21] + i_alu.io.csr_rddata_in <= io.dec_csr_rddata_d @[exu.scala 136:33] + i_alu.io.dec_tlu_flush_lower_r <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[exu.scala 137:41] + node _T_159 = asSInt(i0_rs1_d) @[exu.scala 138:50] + i_alu.io.a_in <= _T_159 @[exu.scala 138:39] + i_alu.io.b_in <= i0_rs2_d @[exu.scala 139:39] + i_alu.io.dec_i0_pc_d <= io.dec_exu.ib_exu.dec_i0_pc_d @[exu.scala 140:33] + i_alu.io.i0_ap.csr_imm <= io.dec_exu.decode_exu.i0_ap.csr_imm @[exu.scala 141:51] + i_alu.io.i0_ap.csr_write <= io.dec_exu.decode_exu.i0_ap.csr_write @[exu.scala 141:51] + i_alu.io.i0_ap.predict_nt <= io.dec_exu.decode_exu.i0_ap.predict_nt @[exu.scala 141:51] + i_alu.io.i0_ap.predict_t <= io.dec_exu.decode_exu.i0_ap.predict_t @[exu.scala 141:51] + i_alu.io.i0_ap.jal <= io.dec_exu.decode_exu.i0_ap.jal @[exu.scala 141:51] + i_alu.io.i0_ap.unsign <= io.dec_exu.decode_exu.i0_ap.unsign @[exu.scala 141:51] + i_alu.io.i0_ap.slt <= io.dec_exu.decode_exu.i0_ap.slt @[exu.scala 141:51] + i_alu.io.i0_ap.sub <= io.dec_exu.decode_exu.i0_ap.sub @[exu.scala 141:51] + i_alu.io.i0_ap.add <= io.dec_exu.decode_exu.i0_ap.add @[exu.scala 141:51] + i_alu.io.i0_ap.bge <= io.dec_exu.decode_exu.i0_ap.bge @[exu.scala 141:51] + i_alu.io.i0_ap.blt <= io.dec_exu.decode_exu.i0_ap.blt @[exu.scala 141:51] + i_alu.io.i0_ap.bne <= io.dec_exu.decode_exu.i0_ap.bne @[exu.scala 141:51] + i_alu.io.i0_ap.beq <= io.dec_exu.decode_exu.i0_ap.beq @[exu.scala 141:51] + i_alu.io.i0_ap.sra <= io.dec_exu.decode_exu.i0_ap.sra @[exu.scala 141:51] + i_alu.io.i0_ap.srl <= io.dec_exu.decode_exu.i0_ap.srl @[exu.scala 141:51] + i_alu.io.i0_ap.sll <= io.dec_exu.decode_exu.i0_ap.sll @[exu.scala 141:51] + i_alu.io.i0_ap.lxor <= io.dec_exu.decode_exu.i0_ap.lxor @[exu.scala 141:51] + i_alu.io.i0_ap.lor <= io.dec_exu.decode_exu.i0_ap.lor @[exu.scala 141:51] + i_alu.io.i0_ap.land <= io.dec_exu.decode_exu.i0_ap.land @[exu.scala 141:51] + i_alu.io.i0_ap.zba <= io.dec_exu.decode_exu.i0_ap.zba @[exu.scala 141:51] + i_alu.io.i0_ap.sh3add <= io.dec_exu.decode_exu.i0_ap.sh3add @[exu.scala 141:51] + i_alu.io.i0_ap.sh2add <= io.dec_exu.decode_exu.i0_ap.sh2add @[exu.scala 141:51] + i_alu.io.i0_ap.sh1add <= io.dec_exu.decode_exu.i0_ap.sh1add @[exu.scala 141:51] + i_alu.io.i0_ap.sbext <= io.dec_exu.decode_exu.i0_ap.sbext @[exu.scala 141:51] + i_alu.io.i0_ap.sbinv <= io.dec_exu.decode_exu.i0_ap.sbinv @[exu.scala 141:51] + i_alu.io.i0_ap.sbclr <= io.dec_exu.decode_exu.i0_ap.sbclr @[exu.scala 141:51] + i_alu.io.i0_ap.sbset <= io.dec_exu.decode_exu.i0_ap.sbset @[exu.scala 141:51] + i_alu.io.i0_ap.zbb <= io.dec_exu.decode_exu.i0_ap.zbb @[exu.scala 141:51] + i_alu.io.i0_ap.gorc <= io.dec_exu.decode_exu.i0_ap.gorc @[exu.scala 141:51] + i_alu.io.i0_ap.grev <= io.dec_exu.decode_exu.i0_ap.grev @[exu.scala 141:51] + i_alu.io.i0_ap.ror <= io.dec_exu.decode_exu.i0_ap.ror @[exu.scala 141:51] + i_alu.io.i0_ap.rol <= io.dec_exu.decode_exu.i0_ap.rol @[exu.scala 141:51] + i_alu.io.i0_ap.packh <= io.dec_exu.decode_exu.i0_ap.packh @[exu.scala 141:51] + i_alu.io.i0_ap.packu <= io.dec_exu.decode_exu.i0_ap.packu @[exu.scala 141:51] + i_alu.io.i0_ap.pack <= io.dec_exu.decode_exu.i0_ap.pack @[exu.scala 141:51] + i_alu.io.i0_ap.max <= io.dec_exu.decode_exu.i0_ap.max @[exu.scala 141:51] + i_alu.io.i0_ap.min <= io.dec_exu.decode_exu.i0_ap.min @[exu.scala 141:51] + i_alu.io.i0_ap.sro <= io.dec_exu.decode_exu.i0_ap.sro @[exu.scala 141:51] + i_alu.io.i0_ap.slo <= io.dec_exu.decode_exu.i0_ap.slo @[exu.scala 141:51] + i_alu.io.i0_ap.sext_h <= io.dec_exu.decode_exu.i0_ap.sext_h @[exu.scala 141:51] + i_alu.io.i0_ap.sext_b <= io.dec_exu.decode_exu.i0_ap.sext_b @[exu.scala 141:51] + i_alu.io.i0_ap.pcnt <= io.dec_exu.decode_exu.i0_ap.pcnt @[exu.scala 141:51] + i_alu.io.i0_ap.ctz <= io.dec_exu.decode_exu.i0_ap.ctz @[exu.scala 141:51] + i_alu.io.i0_ap.clz <= io.dec_exu.decode_exu.i0_ap.clz @[exu.scala 141:51] + i0_flush_upper_d <= i_alu.io.flush_upper_out @[exu.scala 143:35] + i0_flush_path_d <= i_alu.io.flush_path_out @[exu.scala 144:45] + io.exu_flush_final <= i_alu.io.flush_final_out @[exu.scala 145:27] + i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[exu.scala 146:45] + i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[exu.scala 146:45] + i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[exu.scala 146:45] + i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[exu.scala 146:45] + i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[exu.scala 146:45] + i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[exu.scala 146:45] + i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[exu.scala 146:45] + i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[exu.scala 146:45] + i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[exu.scala 146:45] + i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[exu.scala 146:45] + i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[exu.scala 146:45] + i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[exu.scala 146:45] + i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 146:45] + i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 146:45] + i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 147:27] + inst i_mul of exu_mul_ctl @[exu.scala 149:21] i_mul.clock <= clock i_mul.reset <= reset - i_mul.io.scan_mode <= io.scan_mode @[exu.scala 149:25] - i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 150:23] - i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 150:23] - i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 150:23] - i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 150:23] - i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 150:23] - i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 150:23] - i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 150:23] - i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 150:23] - i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 150:23] - i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 150:23] - i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 150:23] - i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 150:23] - i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 150:23] - i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 150:23] + i_mul.io.scan_mode <= io.scan_mode @[exu.scala 150:25] + i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 151:23] + i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 151:23] + i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 151:23] + i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 151:23] + i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 151:23] + i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 151:23] + i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 151:23] + i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 151:23] + i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 151:23] + i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 151:23] + i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 151:23] + i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 151:23] + i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 151:23] + i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 151:23] node _T_160 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] node _T_161 = mux(_T_160, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_162 = and(muldiv_rs1_d, _T_161) @[exu.scala 152:57] - i_mul.io.rs1_in <= _T_162 @[exu.scala 152:41] + node _T_162 = and(muldiv_rs1_d, _T_161) @[exu.scala 153:57] + i_mul.io.rs1_in <= _T_162 @[exu.scala 153:41] node _T_163 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] node _T_164 = mux(_T_163, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_165 = and(i0_rs2_d, _T_164) @[exu.scala 153:54] - i_mul.io.rs2_in <= _T_165 @[exu.scala 153:41] - inst i_div of exu_div_ctl @[exu.scala 156:21] + node _T_165 = and(i0_rs2_d, _T_164) @[exu.scala 154:54] + i_mul.io.rs2_in <= _T_165 @[exu.scala 154:41] + inst i_div of exu_div_ctl @[exu.scala 157:21] i_div.clock <= clock i_div.reset <= reset - i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 157:20] - i_div.io.dec_div.div_p.bits.rem <= io.dec_exu.dec_div.div_p.bits.rem @[exu.scala 157:20] - i_div.io.dec_div.div_p.bits.unsign <= io.dec_exu.dec_div.div_p.bits.unsign @[exu.scala 157:20] - i_div.io.dec_div.div_p.valid <= io.dec_exu.dec_div.div_p.valid @[exu.scala 157:20] - i_div.io.scan_mode <= io.scan_mode @[exu.scala 158:25] - i_div.io.dividend <= muldiv_rs1_d @[exu.scala 159:33] - i_div.io.divisor <= i0_rs2_d @[exu.scala 160:33] - io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 161:41] - io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 162:33] - node _T_166 = bits(mul_valid_x, 0, 0) @[exu.scala 164:76] - node _T_167 = mux(_T_166, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 164:63] - io.dec_exu.decode_exu.exu_i0_result_x <= _T_167 @[exu.scala 164:57] - i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 165:47] - i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 165:47] - i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 165:47] - i0_predict_newp_d.bits.pja <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[exu.scala 165:47] - i0_predict_newp_d.bits.pcall <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[exu.scala 165:47] - i0_predict_newp_d.bits.br_start_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[exu.scala 165:47] - i0_predict_newp_d.bits.br_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[exu.scala 165:47] - i0_predict_newp_d.bits.toffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[exu.scala 165:47] - i0_predict_newp_d.bits.hist <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[exu.scala 165:47] - i0_predict_newp_d.bits.pc4 <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[exu.scala 165:47] - i0_predict_newp_d.bits.boffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[exu.scala 165:47] - i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 165:47] - i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 165:47] - i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 165:47] - node _T_168 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 166:80] - i0_predict_newp_d.bits.boffset <= _T_168 @[exu.scala 166:47] - io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 168:47] - io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 169:47] - io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 170:47] - node _T_169 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 173:54] - node _T_170 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 173:97] - node _T_171 = and(_T_169, _T_170) @[exu.scala 173:95] - i0_valid_d <= _T_171 @[exu.scala 173:28] - node _T_172 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 174:59] - i0_taken_d <= _T_172 @[exu.scala 174:28] - node _T_173 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 180:8] - node _T_174 = and(_T_173, i0_valid_d) @[exu.scala 180:50] - node _T_175 = bits(_T_174, 0, 0) @[exu.scala 180:64] - node _T_176 = bits(ghr_d, 6, 0) @[exu.scala 180:85] + i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 158:20] + i_div.io.dec_div.div_p.bits.rem <= io.dec_exu.dec_div.div_p.bits.rem @[exu.scala 158:20] + i_div.io.dec_div.div_p.bits.unsign <= io.dec_exu.dec_div.div_p.bits.unsign @[exu.scala 158:20] + i_div.io.dec_div.div_p.valid <= io.dec_exu.dec_div.div_p.valid @[exu.scala 158:20] + i_div.io.scan_mode <= io.scan_mode @[exu.scala 159:25] + i_div.io.dividend <= muldiv_rs1_d @[exu.scala 160:33] + i_div.io.divisor <= i0_rs2_d @[exu.scala 161:33] + io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 162:41] + io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 163:33] + node _T_166 = bits(mul_valid_x, 0, 0) @[exu.scala 165:76] + node _T_167 = mux(_T_166, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 165:63] + io.dec_exu.decode_exu.exu_i0_result_x <= _T_167 @[exu.scala 165:57] + i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 166:47] + i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 166:47] + i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 166:47] + i0_predict_newp_d.bits.pja <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[exu.scala 166:47] + i0_predict_newp_d.bits.pcall <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[exu.scala 166:47] + i0_predict_newp_d.bits.br_start_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[exu.scala 166:47] + i0_predict_newp_d.bits.br_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[exu.scala 166:47] + i0_predict_newp_d.bits.toffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[exu.scala 166:47] + i0_predict_newp_d.bits.hist <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[exu.scala 166:47] + i0_predict_newp_d.bits.pc4 <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[exu.scala 166:47] + i0_predict_newp_d.bits.boffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[exu.scala 166:47] + i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 166:47] + i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 166:47] + i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 166:47] + node _T_168 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 167:80] + i0_predict_newp_d.bits.boffset <= _T_168 @[exu.scala 167:47] + io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 169:47] + io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 170:47] + io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 171:47] + node _T_169 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 174:54] + node _T_170 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 174:97] + node _T_171 = and(_T_169, _T_170) @[exu.scala 174:95] + i0_valid_d <= _T_171 @[exu.scala 174:28] + node _T_172 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 175:59] + i0_taken_d <= _T_172 @[exu.scala 175:28] + node _T_173 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 181:8] + node _T_174 = and(_T_173, i0_valid_d) @[exu.scala 181:50] + node _T_175 = bits(_T_174, 0, 0) @[exu.scala 181:64] + node _T_176 = bits(ghr_d, 6, 0) @[exu.scala 181:85] node _T_177 = cat(_T_176, i0_taken_d) @[Cat.scala 29:58] - node _T_178 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 181:8] - node _T_179 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 181:52] - node _T_180 = and(_T_178, _T_179) @[exu.scala 181:50] - node _T_181 = bits(_T_180, 0, 0) @[exu.scala 181:65] - node _T_182 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 182:50] + node _T_178 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 182:8] + node _T_179 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 182:52] + node _T_180 = and(_T_178, _T_179) @[exu.scala 182:50] + node _T_181 = bits(_T_180, 0, 0) @[exu.scala 182:65] + node _T_182 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 183:50] node _T_183 = mux(_T_175, _T_177, UInt<1>("h00")) @[Mux.scala 27:72] node _T_184 = mux(_T_181, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_185 = mux(_T_182, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -45136,97 +45136,97 @@ circuit exu : node _T_187 = or(_T_186, _T_185) @[Mux.scala 27:72] wire _T_188 : UInt @[Mux.scala 27:72] _T_188 <= _T_187 @[Mux.scala 27:72] - ghr_d_ns <= _T_188 @[exu.scala 179:14] - node _T_189 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 186:32] - node _T_190 = bits(ghr_x, 6, 0) @[exu.scala 186:50] + ghr_d_ns <= _T_188 @[exu.scala 180:14] + node _T_189 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 187:32] + node _T_190 = bits(ghr_x, 6, 0) @[exu.scala 187:50] node _T_191 = cat(_T_190, i0_taken_x) @[Cat.scala 29:58] - node _T_192 = mux(_T_189, _T_191, ghr_x) @[exu.scala 186:20] - ghr_x_ns <= _T_192 @[exu.scala 186:14] - io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 188:43] - io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 189:43] - io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 190:43] + node _T_192 = mux(_T_189, _T_191, ghr_x) @[exu.scala 187:20] + ghr_x_ns <= _T_192 @[exu.scala 187:14] + io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 189:43] + io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 190:43] + io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 191:43] node _T_193 = bits(i0_pp_r.valid, 0, 0) @[Bitwise.scala 72:15] node _T_194 = mux(_T_193, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_195 = and(_T_194, i0_pp_r.bits.hist) @[exu.scala 191:69] - io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_195 @[exu.scala 191:43] - io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 192:43] - node _T_196 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 193:63] - io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_196 @[exu.scala 193:43] - io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 194:48] - node _T_197 = bits(predpipe_r, 20, 13) @[exu.scala 195:56] - io.exu_bp.exu_i0_br_fghr_r <= _T_197 @[exu.scala 195:43] - node _T_198 = bits(predpipe_r, 12, 5) @[exu.scala 196:56] - io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_198 @[exu.scala 196:43] - io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 197:43] - node _T_199 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 198:67] - wire _T_200 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 198:104] - _T_200.bits.prett <= UInt<31>("h00") @[exu.scala 198:104] - _T_200.bits.pret <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.way <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.pja <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.pcall <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.br_start_error <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.br_error <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.toffset <= UInt<12>("h00") @[exu.scala 198:104] - _T_200.bits.hist <= UInt<2>("h00") @[exu.scala 198:104] - _T_200.bits.pc4 <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.boffset <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.ataken <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.misp <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.valid <= UInt<1>("h00") @[exu.scala 198:104] - node _T_201 = mux(_T_199, i0_predict_p_x, _T_200) @[exu.scala 198:49] - final_predict_mp.bits.prett <= _T_201.bits.prett @[exu.scala 198:43] - final_predict_mp.bits.pret <= _T_201.bits.pret @[exu.scala 198:43] - final_predict_mp.bits.way <= _T_201.bits.way @[exu.scala 198:43] - final_predict_mp.bits.pja <= _T_201.bits.pja @[exu.scala 198:43] - final_predict_mp.bits.pcall <= _T_201.bits.pcall @[exu.scala 198:43] - final_predict_mp.bits.br_start_error <= _T_201.bits.br_start_error @[exu.scala 198:43] - final_predict_mp.bits.br_error <= _T_201.bits.br_error @[exu.scala 198:43] - final_predict_mp.bits.toffset <= _T_201.bits.toffset @[exu.scala 198:43] - final_predict_mp.bits.hist <= _T_201.bits.hist @[exu.scala 198:43] - final_predict_mp.bits.pc4 <= _T_201.bits.pc4 @[exu.scala 198:43] - final_predict_mp.bits.boffset <= _T_201.bits.boffset @[exu.scala 198:43] - final_predict_mp.bits.ataken <= _T_201.bits.ataken @[exu.scala 198:43] - final_predict_mp.bits.misp <= _T_201.bits.misp @[exu.scala 198:43] - final_predict_mp.valid <= _T_201.valid @[exu.scala 198:43] - node _T_202 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:66] - node final_predpipe_mp = mux(_T_202, predpipe_x, UInt<1>("h00")) @[exu.scala 199:48] - node _T_203 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 201:67] - node _T_204 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 201:120] - node _T_205 = eq(_T_204, UInt<1>("h00")) @[exu.scala 201:77] - node _T_206 = and(_T_203, _T_205) @[exu.scala 201:75] - node after_flush_eghr = mux(_T_206, ghr_d, ghr_x) @[exu.scala 201:48] - io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 203:39] - io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 204:39] - io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 205:39] - io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 206:39] - io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 207:39] - io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 208:39] - io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 209:39] - io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 210:39] - io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 211:39] - node _T_207 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 212:68] - io.exu_bp.exu_mp_pkt.bits.hist <= _T_207 @[exu.scala 212:39] - node _T_208 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 213:71] - io.exu_bp.exu_mp_pkt.bits.toffset <= _T_208 @[exu.scala 213:39] - io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 214:39] - node _T_209 = bits(final_predpipe_mp, 12, 5) @[exu.scala 215:59] - io.exu_bp.exu_mp_index <= _T_209 @[exu.scala 215:39] - node _T_210 = bits(final_predpipe_mp, 4, 0) @[exu.scala 216:59] - io.exu_bp.exu_mp_btag <= _T_210 @[exu.scala 216:39] - node _T_211 = bits(final_predpipe_mp, 20, 13) @[exu.scala 217:59] - io.exu_bp.exu_mp_eghr <= _T_211 @[exu.scala 217:39] - node _T_212 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 239:46] - node _T_213 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 240:6] - node _T_214 = and(_T_213, i0_flush_upper_d) @[exu.scala 240:48] - node _T_215 = bits(_T_214, 0, 0) @[exu.scala 240:68] + node _T_195 = and(_T_194, i0_pp_r.bits.hist) @[exu.scala 192:69] + io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_195 @[exu.scala 192:43] + io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 193:43] + node _T_196 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 194:63] + io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_196 @[exu.scala 194:43] + io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 195:48] + node _T_197 = bits(predpipe_r, 20, 13) @[exu.scala 196:56] + io.exu_bp.exu_i0_br_fghr_r <= _T_197 @[exu.scala 196:43] + node _T_198 = bits(predpipe_r, 12, 5) @[exu.scala 197:56] + io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_198 @[exu.scala 197:43] + io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 198:43] + node _T_199 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:67] + wire _T_200 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 199:104] + _T_200.bits.prett <= UInt<31>("h00") @[exu.scala 199:104] + _T_200.bits.pret <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.way <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.pja <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.pcall <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.br_start_error <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.br_error <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.toffset <= UInt<12>("h00") @[exu.scala 199:104] + _T_200.bits.hist <= UInt<2>("h00") @[exu.scala 199:104] + _T_200.bits.pc4 <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.boffset <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.ataken <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.misp <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.valid <= UInt<1>("h00") @[exu.scala 199:104] + node _T_201 = mux(_T_199, i0_predict_p_x, _T_200) @[exu.scala 199:49] + final_predict_mp.bits.prett <= _T_201.bits.prett @[exu.scala 199:43] + final_predict_mp.bits.pret <= _T_201.bits.pret @[exu.scala 199:43] + final_predict_mp.bits.way <= _T_201.bits.way @[exu.scala 199:43] + final_predict_mp.bits.pja <= _T_201.bits.pja @[exu.scala 199:43] + final_predict_mp.bits.pcall <= _T_201.bits.pcall @[exu.scala 199:43] + final_predict_mp.bits.br_start_error <= _T_201.bits.br_start_error @[exu.scala 199:43] + final_predict_mp.bits.br_error <= _T_201.bits.br_error @[exu.scala 199:43] + final_predict_mp.bits.toffset <= _T_201.bits.toffset @[exu.scala 199:43] + final_predict_mp.bits.hist <= _T_201.bits.hist @[exu.scala 199:43] + final_predict_mp.bits.pc4 <= _T_201.bits.pc4 @[exu.scala 199:43] + final_predict_mp.bits.boffset <= _T_201.bits.boffset @[exu.scala 199:43] + final_predict_mp.bits.ataken <= _T_201.bits.ataken @[exu.scala 199:43] + final_predict_mp.bits.misp <= _T_201.bits.misp @[exu.scala 199:43] + final_predict_mp.valid <= _T_201.valid @[exu.scala 199:43] + node _T_202 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 200:66] + node final_predpipe_mp = mux(_T_202, predpipe_x, UInt<1>("h00")) @[exu.scala 200:48] + node _T_203 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 202:67] + node _T_204 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 202:120] + node _T_205 = eq(_T_204, UInt<1>("h00")) @[exu.scala 202:77] + node _T_206 = and(_T_203, _T_205) @[exu.scala 202:75] + node after_flush_eghr = mux(_T_206, ghr_d, ghr_x) @[exu.scala 202:48] + io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 204:39] + io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 205:39] + io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 206:39] + io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 207:39] + io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 208:39] + io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 209:39] + io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 210:39] + io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 211:39] + io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 212:39] + node _T_207 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 213:68] + io.exu_bp.exu_mp_pkt.bits.hist <= _T_207 @[exu.scala 213:39] + node _T_208 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 214:71] + io.exu_bp.exu_mp_pkt.bits.toffset <= _T_208 @[exu.scala 214:39] + io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 215:39] + node _T_209 = bits(final_predpipe_mp, 12, 5) @[exu.scala 216:59] + io.exu_bp.exu_mp_index <= _T_209 @[exu.scala 216:39] + node _T_210 = bits(final_predpipe_mp, 4, 0) @[exu.scala 217:59] + io.exu_bp.exu_mp_btag <= _T_210 @[exu.scala 217:39] + node _T_211 = bits(final_predpipe_mp, 20, 13) @[exu.scala 218:59] + io.exu_bp.exu_mp_eghr <= _T_211 @[exu.scala 218:39] + node _T_212 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 240:46] + node _T_213 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 241:6] + node _T_214 = and(_T_213, i0_flush_upper_d) @[exu.scala 241:48] + node _T_215 = bits(_T_214, 0, 0) @[exu.scala 241:68] node _T_216 = mux(_T_212, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_217 = mux(_T_215, i0_flush_path_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72] wire _T_219 : UInt<31> @[Mux.scala 27:72] _T_219 <= _T_218 @[Mux.scala 27:72] - io.exu_flush_path_final <= _T_219 @[exu.scala 238:33] - node _T_220 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 242:79] - node _T_221 = mux(_T_220, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 242:55] - io.dec_exu.tlu_exu.exu_npc_r <= _T_221 @[exu.scala 242:49] + io.exu_flush_path_final <= _T_219 @[exu.scala 239:33] + node _T_220 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 243:79] + node _T_221 = mux(_T_220, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 243:55] + io.dec_exu.tlu_exu.exu_npc_r <= _T_221 @[exu.scala 243:49] diff --git a/exu.v b/exu.v index 4662915c..aef37fe1 100644 --- a/exu.v +++ b/exu.v @@ -21,9 +21,9 @@ module exu_alu_ctl( input reset, input io_dec_alu_dec_i0_alu_decode_d, input io_dec_alu_dec_csr_ren_d, - input [31:0] io_dec_alu_dec_csr_rddata_d, input [11:0] io_dec_alu_dec_i0_br_immed_d, output [30:0] io_dec_alu_exu_i0_pc_x, + input [31:0] io_csr_rddata_in, input [30:0] io_dec_i0_pc_d, input io_flush_upper_x, input io_dec_tlu_flush_lower_r, @@ -116,7 +116,7 @@ module exu_alu_ctl( reg [30:0] _T_14; // @[Reg.scala 27:20] wire _T_15 = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[exu_alu_ctl.scala 135:43] reg [31:0] _T_18; // @[Reg.scala 27:20] - wire [31:0] _T_153 = io_dec_alu_dec_csr_rddata_d; // @[Mux.scala 27:72] + wire [31:0] _T_153 = io_csr_rddata_in; // @[Mux.scala 27:72] wire [32:0] _T_151 = {{1{_T_153[31]}},_T_153}; // @[Mux.scala 27:72 Mux.scala 27:72] wire [32:0] _T_172 = io_dec_alu_dec_csr_ren_d ? $signed(_T_151) : $signed(33'sh0); // @[Mux.scala 27:72] wire _T_94 = ~io_i0_ap_zbb; // @[exu_alu_ctl.scala 160:22] @@ -1952,7 +1952,6 @@ module exu( input io_scan_mode, input io_dec_exu_dec_alu_dec_i0_alu_decode_d, input io_dec_exu_dec_alu_dec_csr_ren_d, - input [31:0] io_dec_exu_dec_alu_dec_csr_rddata_d, input [11:0] io_dec_exu_dec_alu_dec_i0_br_immed_d, output [30:0] io_dec_exu_dec_alu_exu_i0_pc_x, input io_dec_exu_dec_div_div_p_valid, @@ -2027,6 +2026,7 @@ module exu( input io_dec_exu_decode_exu_dec_i0_rs2_en_d, input [31:0] io_dec_exu_decode_exu_dec_i0_immed_d, input [31:0] io_dec_exu_decode_exu_dec_i0_result_r, + input io_dec_exu_decode_exu_dec_qual_lsu_d, input io_dec_exu_decode_exu_dec_i0_select_pc_d, input [3:0] io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d, input [3:0] io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d, @@ -2097,12 +2097,12 @@ module exu( output [31:0] io_exu_div_result, output io_exu_div_wren, input [31:0] io_dbg_cmd_wrdata, + input [31:0] io_dec_csr_rddata_d, output [31:0] io_lsu_exu_exu_lsu_rs1_d, output [31:0] io_lsu_exu_exu_lsu_rs2_d, input [31:0] io_lsu_exu_lsu_result_m, input [31:0] io_lsu_exu_lsu_nonblock_load_data, - output [30:0] io_exu_flush_path_final, - input io_dec_qual_lsu_d + output [30:0] io_exu_flush_path_final ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -2160,117 +2160,117 @@ module exu( wire rvclkhdr_6_io_en; // @[lib.scala 404:23] wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] wire rvclkhdr_7_io_en; // @[lib.scala 404:23] - wire i_alu_clock; // @[exu.scala 130:19] - wire i_alu_reset; // @[exu.scala 130:19] - wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:19] - wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 130:19] - wire [31:0] i_alu_io_dec_alu_dec_csr_rddata_d; // @[exu.scala 130:19] - wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:19] - wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:19] - wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 130:19] - wire i_alu_io_flush_upper_x; // @[exu.scala 130:19] - wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 130:19] - wire i_alu_io_enable; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_clz; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_ctz; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_pcnt; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sext_b; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sext_h; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_min; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_max; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_pack; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_packu; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_packh; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_rol; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_ror; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_grev; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_gorc; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_zbb; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sbset; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sbclr; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sbinv; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sbext; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_land; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_lor; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_lxor; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sll; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_srl; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sra; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_beq; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_bne; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_blt; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_bge; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_add; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sub; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_slt; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_unsign; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_jal; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_predict_t; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_csr_write; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 130:19] - wire [31:0] i_alu_io_a_in; // @[exu.scala 130:19] - wire [31:0] i_alu_io_b_in; // @[exu.scala 130:19] - wire i_alu_io_pp_in_valid; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 130:19] - wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 130:19] - wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_pja; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_way; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_pret; // @[exu.scala 130:19] - wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 130:19] - wire [31:0] i_alu_io_result_ff; // @[exu.scala 130:19] - wire i_alu_io_flush_upper_out; // @[exu.scala 130:19] - wire i_alu_io_flush_final_out; // @[exu.scala 130:19] - wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 130:19] - wire i_alu_io_pred_correct_out; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_valid; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 130:19] - wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 130:19] - wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 130:19] - wire i_mul_clock; // @[exu.scala 148:21] - wire i_mul_reset; // @[exu.scala 148:21] - wire i_mul_io_mul_p_valid; // @[exu.scala 148:21] - wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 148:21] - wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 148:21] - wire i_mul_io_mul_p_bits_low; // @[exu.scala 148:21] - wire [31:0] i_mul_io_rs1_in; // @[exu.scala 148:21] - wire [31:0] i_mul_io_rs2_in; // @[exu.scala 148:21] - wire [31:0] i_mul_io_result_x; // @[exu.scala 148:21] - wire i_div_clock; // @[exu.scala 156:21] - wire i_div_reset; // @[exu.scala 156:21] - wire [31:0] i_div_io_dividend; // @[exu.scala 156:21] - wire [31:0] i_div_io_divisor; // @[exu.scala 156:21] - wire [31:0] i_div_io_exu_div_result; // @[exu.scala 156:21] - wire i_div_io_exu_div_wren; // @[exu.scala 156:21] - wire i_div_io_dec_div_div_p_valid; // @[exu.scala 156:21] - wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 156:21] - wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 156:21] - wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 156:21] - wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 55:69] - wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 56:73] - wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 57:73] - wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 58:69] + wire i_alu_clock; // @[exu.scala 129:19] + wire i_alu_reset; // @[exu.scala 129:19] + wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 129:19] + wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 129:19] + wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 129:19] + wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 129:19] + wire [31:0] i_alu_io_csr_rddata_in; // @[exu.scala 129:19] + wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 129:19] + wire i_alu_io_flush_upper_x; // @[exu.scala 129:19] + wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 129:19] + wire i_alu_io_enable; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_clz; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_ctz; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_pcnt; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sext_b; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sext_h; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_min; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_max; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_pack; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_packu; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_packh; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_rol; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_ror; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_grev; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_gorc; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_zbb; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sbset; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sbclr; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sbinv; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sbext; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_land; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_lor; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_lxor; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sll; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_srl; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sra; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_beq; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_bne; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_blt; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_bge; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_add; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sub; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_slt; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_unsign; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_jal; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_predict_t; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_csr_write; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 129:19] + wire [31:0] i_alu_io_a_in; // @[exu.scala 129:19] + wire [31:0] i_alu_io_b_in; // @[exu.scala 129:19] + wire i_alu_io_pp_in_valid; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 129:19] + wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 129:19] + wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_pja; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_way; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_pret; // @[exu.scala 129:19] + wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 129:19] + wire [31:0] i_alu_io_result_ff; // @[exu.scala 129:19] + wire i_alu_io_flush_upper_out; // @[exu.scala 129:19] + wire i_alu_io_flush_final_out; // @[exu.scala 129:19] + wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 129:19] + wire i_alu_io_pred_correct_out; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_valid; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 129:19] + wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 129:19] + wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 129:19] + wire i_mul_clock; // @[exu.scala 149:21] + wire i_mul_reset; // @[exu.scala 149:21] + wire i_mul_io_mul_p_valid; // @[exu.scala 149:21] + wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 149:21] + wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 149:21] + wire i_mul_io_mul_p_bits_low; // @[exu.scala 149:21] + wire [31:0] i_mul_io_rs1_in; // @[exu.scala 149:21] + wire [31:0] i_mul_io_rs2_in; // @[exu.scala 149:21] + wire [31:0] i_mul_io_result_x; // @[exu.scala 149:21] + wire i_div_clock; // @[exu.scala 157:21] + wire i_div_reset; // @[exu.scala 157:21] + wire [31:0] i_div_io_dividend; // @[exu.scala 157:21] + wire [31:0] i_div_io_divisor; // @[exu.scala 157:21] + wire [31:0] i_div_io_exu_div_result; // @[exu.scala 157:21] + wire i_div_io_exu_div_wren; // @[exu.scala 157:21] + wire i_div_io_dec_div_div_p_valid; // @[exu.scala 157:21] + wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 157:21] + wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 157:21] + wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 157:21] + wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 54:69] + wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 55:73] + wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 56:73] + wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 57:69] reg i0_branch_x; // @[Reg.scala 27:20] - wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 59:73] - wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 60:68] - wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 61:68] + wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 58:73] + wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 59:68] + wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 60:68] wire [20:0] predpipe_d = {io_dec_exu_decode_exu_i0_predict_fghr_d,io_dec_exu_decode_exu_i0_predict_index_d,io_dec_exu_decode_exu_i0_predict_btag_d}; // @[Cat.scala 29:58] reg [30:0] i0_flush_path_x; // @[Reg.scala 27:20] - wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 41:53 exu.scala 143:45] + wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 40:53 exu.scala 144:45] reg i0_predict_p_x_valid; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_misp; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_ataken; // @[Reg.scala 27:20] @@ -2284,19 +2284,19 @@ module exu( reg i0_predict_p_x_bits_pja; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_way; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_pret; // @[Reg.scala 27:20] - wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 42:53 exu.scala 145:45] - wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 42:53 exu.scala 145:45] - wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 41:53 exu.scala 146:45] + wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 41:53 exu.scala 146:45] + wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 41:53 exu.scala 146:45] reg [20:0] predpipe_x; // @[Reg.scala 27:20] reg [20:0] predpipe_r; // @[Reg.scala 27:20] reg [7:0] ghr_x; // @[Reg.scala 27:20] @@ -2304,13 +2304,13 @@ module exu( reg i0_taken_x; // @[Reg.scala 27:20] wire [7:0] _T_191 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58] reg i0_pred_correct_upper_x; // @[Reg.scala 27:20] - wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 47:41 exu.scala 146:27] + wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 46:41 exu.scala 147:27] reg i0_flush_upper_x; // @[Reg.scala 27:20] - wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 48:45 exu.scala 142:35] - wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 174:59] - wire _T_169 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 173:54] - wire _T_170 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 173:97] - wire i0_valid_d = _T_169 & _T_170; // @[exu.scala 173:95] + wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 47:45 exu.scala 143:35] + wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 175:59] + wire _T_169 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 174:54] + wire _T_170 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 174:97] + wire i0_valid_d = _T_169 & _T_170; // @[exu.scala 174:95] reg i0_pp_r_valid; // @[Reg.scala 27:20] reg i0_pp_r_bits_misp; // @[Reg.scala 27:20] reg i0_pp_r_bits_ataken; // @[Reg.scala 27:20] @@ -2325,12 +2325,12 @@ module exu( reg [30:0] i0_flush_path_upper_r; // @[Reg.scala 27:20] reg [24:0] pred_temp2; // @[Reg.scala 27:20] wire [30:0] _T_31 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58] - wire _T_174 = _T_170 & i0_valid_d; // @[exu.scala 180:50] + wire _T_174 = _T_170 & i0_valid_d; // @[exu.scala 181:50] reg [7:0] ghr_d; // @[Reg.scala 27:20] wire [7:0] _T_177 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58] wire [7:0] _T_183 = _T_174 ? _T_177 : 8'h0; // @[Mux.scala 27:72] - wire _T_179 = ~i0_valid_d; // @[exu.scala 181:52] - wire _T_180 = _T_170 & _T_179; // @[exu.scala 181:50] + wire _T_179 = ~i0_valid_d; // @[exu.scala 182:52] + wire _T_180 = _T_170 & _T_179; // @[exu.scala 182:50] wire [7:0] _T_184 = _T_180 ? ghr_d : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_186 = _T_183 | _T_184; // @[Mux.scala 27:72] wire [7:0] _T_185 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] @@ -2342,12 +2342,12 @@ module exu( wire _T_38 = |_T_37; // @[lib.scala 470:29] wire _T_41 = io_dec_exu_decode_exu_dec_i0_branch_d ^ i0_branch_x; // @[lib.scala 448:21] wire _T_42 = |_T_41; // @[lib.scala 448:29] - wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 83:84] - wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 83:134] - wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 83:184] - wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 84:84] - wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 84:134] - wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 84:184] + wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 82:84] + wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 82:134] + wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 82:184] + wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 83:84] + wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 83:134] + wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 83:184] wire [31:0] _T_64 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] ? io_dec_exu_decode_exu_dec_i0_result_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_65 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1] ? io_lsu_exu_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_66 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2] ? io_dec_exu_decode_exu_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] @@ -2362,13 +2362,13 @@ module exu( wire [31:0] _T_83 = _T_79 | _T_80; // @[Mux.scala 27:72] wire [31:0] _T_84 = _T_83 | _T_81; // @[Mux.scala 27:72] wire [31:0] i0_rs2_bypass_data_d = _T_84 | _T_82; // @[Mux.scala 27:72] - wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 101:6] - wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 101:26] + wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 100:6] + wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 100:26] wire [31:0] _T_90 = {io_dec_exu_ib_exu_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58] - wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:26] - wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 103:28] - wire _T_96 = _T_87 & _T_95; // @[exu.scala 103:26] - wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 103:69] + wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 101:26] + wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:28] + wire _T_96 = _T_87 & _T_95; // @[exu.scala 102:26] + wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 102:69] wire [31:0] _T_99 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_100 = _T_88 ? _T_90 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_101 = _T_92 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72] @@ -2377,45 +2377,45 @@ module exu( wire [31:0] _T_104 = _T_103 | _T_101; // @[Mux.scala 27:72] wire [31:0] i0_rs1_d = _T_104 | _T_102; // @[Mux.scala 27:72] reg [31:0] _T_107; // @[Reg.scala 27:20] - wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 108:6] - wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 108:26] + wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 107:6] + wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 107:26] wire [31:0] _T_114 = _T_109 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_115 = _T_108 ? io_dec_exu_decode_exu_dec_i0_immed_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_116 = i0_rs2_bypass_en_d ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_117 = _T_114 | _T_115; // @[Mux.scala 27:72] wire [31:0] _T_118 = _T_117 | _T_116; // @[Mux.scala 27:72] - wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 115:28] - wire _T_121 = _T_87 & _T_120; // @[exu.scala 115:26] - wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 115:68] - wire _T_123 = _T_122 & io_dec_qual_lsu_d; // @[exu.scala 115:108] - wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 116:25] - wire _T_127 = _T_126 & io_dec_qual_lsu_d; // @[exu.scala 116:67] - wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_qual_lsu_d; // @[exu.scala 117:45] + wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 114:28] + wire _T_121 = _T_87 & _T_120; // @[exu.scala 114:26] + wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 114:68] + wire _T_123 = _T_122 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 114:108] + wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 115:25] + wire _T_127 = _T_126 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 115:67] + wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 116:45] wire [31:0] _T_131 = {io_dec_exu_tlu_exu_dec_tlu_meihap,2'h0}; // @[Cat.scala 29:58] wire [31:0] _T_132 = _T_123 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_133 = _T_127 ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_134 = _T_129 ? _T_131 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_135 = _T_132 | _T_133; // @[Mux.scala 27:72] - wire _T_140 = _T_108 & _T_120; // @[exu.scala 121:26] - wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 121:68] - wire _T_142 = _T_141 & io_dec_qual_lsu_d; // @[exu.scala 121:108] - wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 122:25] - wire _T_146 = _T_145 & io_dec_qual_lsu_d; // @[exu.scala 122:67] + wire _T_140 = _T_108 & _T_120; // @[exu.scala 120:26] + wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 120:68] + wire _T_142 = _T_141 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 120:108] + wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 121:25] + wire _T_146 = _T_145 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 121:67] wire [31:0] _T_148 = _T_142 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_149 = _T_146 ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] - wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 126:26] + wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 125:26] wire [31:0] _T_156 = _T_153 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] muldiv_rs1_d = _T_156 | _T_99; // @[Mux.scala 27:72] wire [31:0] _T_161 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] i0_rs2_d = _T_118; // @[Mux.scala 27:72 Mux.scala 27:72] wire [1:0] _T_194 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 199:48] - wire _T_206 = i0_flush_upper_x & _T_170; // @[exu.scala 201:75] - wire _T_214 = _T_170 & i0_flush_upper_d; // @[exu.scala 240:48] + wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 200:48] + wire _T_206 = i0_flush_upper_x & _T_170; // @[exu.scala 202:75] + wire _T_214 = _T_170 & i0_flush_upper_d; // @[exu.scala 241:48] wire [30:0] _T_216 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_217 = _T_214 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72] - wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 46:51 exu.scala 78:45] - wire [31:0] _T_221 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 242:55] + wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 45:51 exu.scala 77:45] + wire [31:0] _T_221 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 243:55] rvclkhdr rvclkhdr ( // @[lib.scala 404:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) @@ -2448,14 +2448,14 @@ module exu( .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en) ); - exu_alu_ctl i_alu ( // @[exu.scala 130:19] + exu_alu_ctl i_alu ( // @[exu.scala 129:19] .clock(i_alu_clock), .reset(i_alu_reset), .io_dec_alu_dec_i0_alu_decode_d(i_alu_io_dec_alu_dec_i0_alu_decode_d), .io_dec_alu_dec_csr_ren_d(i_alu_io_dec_alu_dec_csr_ren_d), - .io_dec_alu_dec_csr_rddata_d(i_alu_io_dec_alu_dec_csr_rddata_d), .io_dec_alu_dec_i0_br_immed_d(i_alu_io_dec_alu_dec_i0_br_immed_d), .io_dec_alu_exu_i0_pc_x(i_alu_io_dec_alu_exu_i0_pc_x), + .io_csr_rddata_in(i_alu_io_csr_rddata_in), .io_dec_i0_pc_d(i_alu_io_dec_i0_pc_d), .io_flush_upper_x(i_alu_io_flush_upper_x), .io_dec_tlu_flush_lower_r(i_alu_io_dec_tlu_flush_lower_r), @@ -2531,7 +2531,7 @@ module exu( .io_predict_p_out_bits_way(i_alu_io_predict_p_out_bits_way), .io_predict_p_out_bits_pret(i_alu_io_predict_p_out_bits_pret) ); - exu_mul_ctl i_mul ( // @[exu.scala 148:21] + exu_mul_ctl i_mul ( // @[exu.scala 149:21] .clock(i_mul_clock), .reset(i_mul_reset), .io_mul_p_valid(i_mul_io_mul_p_valid), @@ -2542,7 +2542,7 @@ module exu( .io_rs2_in(i_mul_io_rs2_in), .io_result_x(i_mul_io_result_x) ); - exu_div_ctl i_div ( // @[exu.scala 156:21] + exu_div_ctl i_div ( // @[exu.scala 157:21] .clock(i_div_clock), .reset(i_div_reset), .io_dividend(i_div_io_dividend), @@ -2554,47 +2554,47 @@ module exu( .io_dec_div_div_p_bits_rem(i_div_io_dec_div_div_p_bits_rem), .io_dec_div_dec_div_cancel(i_div_io_dec_div_dec_div_cancel) ); - assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 131:20] - assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 164:57] - assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 105:57] - assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_194 & i0_pp_r_bits_hist; // @[exu.scala 191:43] - assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 192:43] - assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 194:48] - assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 196:43] - assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 188:43] - assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 189:43] - assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 193:43] - assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 168:47] - assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 169:47] - assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 170:47] - assign io_dec_exu_tlu_exu_exu_npc_r = _T_221[30:0]; // @[exu.scala 242:49] - assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 197:43] - assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 195:43] - assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 190:43] - assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 52:53 exu.scala 203:39] - assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 205:39] - assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 209:39] - assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 210:39] - assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 211:39] - assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 212:39] - assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 213:39] - assign io_exu_bp_exu_mp_pkt_bits_br_error = 1'h0; // @[exu.scala 51:39] - assign io_exu_bp_exu_mp_pkt_bits_br_start_error = 1'h0; // @[exu.scala 50:44] - assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 206:39] - assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 207:39] - assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 204:39] - assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 208:39] - assign io_exu_bp_exu_mp_pkt_bits_prett = 31'h0; // @[exu.scala 49:57] - assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 217:39] - assign io_exu_bp_exu_mp_fghr = _T_206 ? ghr_d : ghr_x; // @[exu.scala 214:39] - assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 215:39] - assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 216:39] - assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 144:27] - assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 162:33] - assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 161:41] - assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 114:27] - assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 120:27] - assign io_exu_flush_path_final = _T_216 | _T_217; // @[exu.scala 238:33] + assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:20] + assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 165:57] + assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 104:57] + assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_194 & i0_pp_r_bits_hist; // @[exu.scala 192:43] + assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 193:43] + assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 195:48] + assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 197:43] + assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 189:43] + assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 190:43] + assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 194:43] + assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 169:47] + assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 170:47] + assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 171:47] + assign io_dec_exu_tlu_exu_exu_npc_r = _T_221[30:0]; // @[exu.scala 243:49] + assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 198:43] + assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 196:43] + assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 191:43] + assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 51:53 exu.scala 204:39] + assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 206:39] + assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 210:39] + assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 211:39] + assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 212:39] + assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 213:39] + assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 214:39] + assign io_exu_bp_exu_mp_pkt_bits_br_error = 1'h0; // @[exu.scala 50:39] + assign io_exu_bp_exu_mp_pkt_bits_br_start_error = 1'h0; // @[exu.scala 49:44] + assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 207:39] + assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 208:39] + assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 205:39] + assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 209:39] + assign io_exu_bp_exu_mp_pkt_bits_prett = 31'h0; // @[exu.scala 48:57] + assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 218:39] + assign io_exu_bp_exu_mp_fghr = _T_206 ? ghr_d : ghr_x; // @[exu.scala 215:39] + assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 216:39] + assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 217:39] + assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 145:27] + assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 163:33] + assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 162:41] + assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 113:27] + assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 119:27] + assign io_exu_flush_path_final = _T_216 | _T_217; // @[exu.scala 239:33] assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_io_en = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[lib.scala 407:17] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] @@ -2613,54 +2613,54 @@ module exu( assign rvclkhdr_7_io_en = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[lib.scala 407:17] assign i_alu_clock = clock; assign i_alu_reset = reset; - assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 131:20] - assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 131:20] - assign i_alu_io_dec_alu_dec_csr_rddata_d = io_dec_exu_dec_alu_dec_csr_rddata_d; // @[exu.scala 131:20] - assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 131:20] - assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 139:33] + assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:20] + assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 130:20] + assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:20] + assign i_alu_io_csr_rddata_in = io_dec_csr_rddata_d; // @[exu.scala 136:33] + assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 140:33] assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[exu.scala 135:33] - assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 136:41] + assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 137:41] assign i_alu_io_enable = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 133:45] - assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 140:51] - assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 137:39] - assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 138:39] + assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 141:51] + assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 138:39] + assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 139:39] assign i_alu_io_pp_in_valid = io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[exu.scala 134:45] assign i_alu_io_pp_in_bits_boffset = io_dec_exu_ib_exu_dec_i0_pc_d[0]; // @[exu.scala 134:45] assign i_alu_io_pp_in_bits_pc4 = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[exu.scala 134:45] @@ -2675,20 +2675,20 @@ module exu( assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 134:45] assign i_mul_clock = clock; assign i_mul_reset = reset; - assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 150:23] - assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 150:23] - assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 150:23] - assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 150:23] - assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 152:41] - assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 153:41] + assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 151:23] + assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 151:23] + assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 151:23] + assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 151:23] + assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 153:41] + assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 154:41] assign i_div_clock = clock; assign i_div_reset = reset; - assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 159:33] - assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 160:33] - assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 157:20] - assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 157:20] - assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 157:20] - assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 157:20] + assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 160:33] + assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 161:33] + assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 158:20] + assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 158:20] + assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 158:20] + assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 158:20] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif diff --git a/lsu.anno.json b/lsu.anno.json new file mode 100644 index 00000000..7e37459a --- /dev/null +++ b/lsu.anno.json @@ -0,0 +1,547 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn", + "sources":[ + "~lsu|lsu>io_axi_ar_ready", + "~lsu|lsu>io_axi_aw_ready", + "~lsu|lsu>io_axi_w_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_mken", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_single_ecc_error_incr", + "sources":[ + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dma_dccm_ready", + "sources":[ + "~lsu|lsu>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_trigger_match_m", + "sources":[ + "~lsu|lsu>io_trigger_pkt_any_0_store", + "~lsu|lsu>io_trigger_pkt_any_1_store", + "~lsu|lsu>io_trigger_pkt_any_3_m", + "~lsu|lsu>io_trigger_pkt_any_0_load", + "~lsu|lsu>io_trigger_pkt_any_0_select", + "~lsu|lsu>io_trigger_pkt_any_3_store", + "~lsu|lsu>io_trigger_pkt_any_2_store", + "~lsu|lsu>io_trigger_pkt_any_1_load", + "~lsu|lsu>io_trigger_pkt_any_1_select", + "~lsu|lsu>io_trigger_pkt_any_2_m", + "~lsu|lsu>io_trigger_pkt_any_3_load", + "~lsu|lsu>io_trigger_pkt_any_3_select", + "~lsu|lsu>io_trigger_pkt_any_2_load", + "~lsu|lsu>io_trigger_pkt_any_2_select", + "~lsu|lsu>io_trigger_pkt_any_0_m", + "~lsu|lsu>io_trigger_pkt_any_1_m", + "~lsu|lsu>io_trigger_pkt_any_0_tdata2", + "~lsu|lsu>io_trigger_pkt_any_0_match_pkt", + "~lsu|lsu>io_trigger_pkt_any_1_tdata2", + "~lsu|lsu>io_trigger_pkt_any_1_match_pkt", + "~lsu|lsu>io_trigger_pkt_any_3_tdata2", + "~lsu|lsu>io_trigger_pkt_any_3_match_pkt", + "~lsu|lsu>io_trigger_pkt_any_2_tdata2", + "~lsu|lsu>io_trigger_pkt_any_2_match_pkt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wren", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy", + "sources":[ + "~lsu|lsu>io_axi_ar_ready", + "~lsu|lsu>io_axi_aw_ready", + "~lsu|lsu>io_axi_w_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_data_hi", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_addr_lo", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_store_stall_any", + "sources":[ + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata", + "sources":[ + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_addr_hi", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_fastint_stall_any", + "sources":[ + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_exu_lsu_result_m", + "sources":[ + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_rd_addr_hi", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_data_lo", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned", + "sources":[ + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_wren", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error", + "sources":[ + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_rden", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r", + "sources":[ + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_load_stall_any", + "sources":[ + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_rden", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_rd_addr_lo", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_wr_data", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_wraddr", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "sources":[ + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_force_halt" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"lsu.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"lsu" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/lsu.fir b/lsu.fir new file mode 100644 index 00000000..31e690e4 --- /dev/null +++ b/lsu.fir @@ -0,0 +1,16090 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit lsu : + module lsu_addrcheck : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} + + node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 370:27] + node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 370:49] + wire start_addr_in_dccm_d : UInt<1> @[lib.scala 371:26] + node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 375:24] + node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 375:39] + start_addr_in_dccm_d <= _T_2 @[lib.scala 375:16] + node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 370:27] + node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 370:49] + wire end_addr_in_dccm_d : UInt<1> @[lib.scala 371:26] + node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 375:24] + node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 375:39] + end_addr_in_dccm_d <= _T_5 @[lib.scala 375:16] + wire addr_in_iccm : UInt<1> + addr_in_iccm <= UInt<1>("h00") + node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37] + node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45] + addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18] + node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89] + node _T_9 = bits(_T_8, 31, 28) @[lib.scala 370:27] + node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 370:49] + wire start_addr_in_pic_d : UInt<1> @[lib.scala 371:26] + node _T_10 = bits(_T_8, 31, 15) @[lib.scala 375:24] + node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 375:39] + start_addr_in_pic_d <= _T_11 @[lib.scala 375:16] + node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83] + node _T_13 = bits(_T_12, 31, 28) @[lib.scala 370:27] + node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 370:49] + wire end_addr_in_pic_d : UInt<1> @[lib.scala 371:26] + node _T_14 = bits(_T_12, 31, 15) @[lib.scala 375:24] + node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 375:39] + end_addr_in_pic_d <= _T_15 @[lib.scala 375:16] + node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60] + node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49] + node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55] + node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74] + node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109] + node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115] + node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91] + node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57] + io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32] + node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56] + io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32] + node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63] + node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33] + io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30] + node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51] + node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50] + node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50] + node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92] + node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62] + node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60] + node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137] + node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185] + node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158] + node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80] + node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56] + node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134] + node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138] + node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116] + node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90] + node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148] + node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58] + node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58] + node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58] + node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99] + node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33] + node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49] + node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56] + node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121] + node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88] + node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30] + node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49] + node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56] + node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121] + node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88] + node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30] + node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153] + node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49] + node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56] + node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121] + node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88] + node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30] + node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153] + node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49] + node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56] + node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121] + node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88] + node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30] + node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153] + node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49] + node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56] + node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121] + node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88] + node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30] + node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153] + node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49] + node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56] + node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121] + node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88] + node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30] + node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153] + node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49] + node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56] + node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121] + node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88] + node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30] + node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153] + node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49] + node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56] + node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121] + node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88] + node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30] + node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153] + node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48] + node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57] + node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122] + node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89] + node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31] + node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49] + node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58] + node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123] + node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90] + node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32] + node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154] + node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49] + node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58] + node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123] + node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90] + node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32] + node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155] + node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49] + node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58] + node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123] + node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90] + node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32] + node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155] + node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49] + node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58] + node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123] + node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90] + node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32] + node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155] + node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49] + node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58] + node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123] + node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90] + node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32] + node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155] + node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49] + node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58] + node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123] + node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90] + node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32] + node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155] + node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49] + node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58] + node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123] + node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90] + node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32] + node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155] + node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7] + node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104] + node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57] + node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70] + node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76] + node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92] + node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90] + node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51] + wire unmapped_access_fault_d : UInt<1> + unmapped_access_fault_d <= UInt<1>("h01") + wire mpu_access_fault_d : UInt<1> + mpu_access_fault_d <= UInt<1>("h01") + node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64] + node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62] + node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36] + node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34] + node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112] + node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29] + node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85] + node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29] + node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85] + unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29] + node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33] + node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64] + node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62] + mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29] + node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49] + node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70] + node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92] + node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118] + node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141] + node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139] + io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21] + node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60] + node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100] + node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144] + node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185] + node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164] + node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120] + node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80] + node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35] + node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53] + node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78] + node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61] + node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59] + node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57] + node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90] + node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57] + node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113] + node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136] + node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134] + io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25] + node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111] + node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80] + node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39] + node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50] + node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84] + node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113] + node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27] + io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21] + node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66] + node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64] + node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120] + node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118] + node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88] + node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142] + node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163] + io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31] + node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66] + node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36] + node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95] + node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116] + io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33] + reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60] + _T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60] + io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50] + + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_lsc_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} + + wire end_addr_pre_m : UInt<29> + end_addr_pre_m <= UInt<29>("h00") + wire end_addr_pre_r : UInt<29> + end_addr_pre_r <= UInt<29>("h00") + wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 93:29] + wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 94:29] + wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29] + wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 96:29] + wire _T : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 97:35] + _T.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + lsu_error_pkt_m.bits.addr <= _T.bits.addr @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.mscause <= _T.bits.mscause @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.exc_type <= _T.bits.exc_type @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.inst_type <= _T.bits.inst_type @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.single_ecc_error <= _T.bits.single_ecc_error @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.valid <= _T.valid @[lsu_lsc_ctl.scala 97:20] + node _T_1 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 99:52] + node lsu_rs1_d = mux(_T_1, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 99:28] + node _T_2 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 100:44] + node _T_3 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node lsu_offset_d = and(_T_2, _T_4) @[lsu_lsc_ctl.scala 100:51] + node _T_5 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 103:66] + node rs1_d = mux(_T_5, io.lsu_exu.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 103:28] + node _T_6 = bits(rs1_d, 11, 0) @[lib.scala 92:31] + node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58] + node _T_8 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60] + node _T_9 = cat(UInt<1>("h00"), _T_8) @[Cat.scala 29:58] + node _T_10 = add(_T_7, _T_9) @[lib.scala 92:39] + node _T_11 = tail(_T_10, 1) @[lib.scala 92:39] + node _T_12 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41] + node _T_13 = bits(_T_11, 12, 12) @[lib.scala 93:50] + node _T_14 = xor(_T_12, _T_13) @[lib.scala 93:46] + node _T_15 = not(_T_14) @[lib.scala 93:33] + node _T_16 = bits(_T_15, 0, 0) @[Bitwise.scala 72:15] + node _T_17 = mux(_T_16, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_18 = bits(rs1_d, 31, 12) @[lib.scala 93:63] + node _T_19 = and(_T_17, _T_18) @[lib.scala 93:58] + node _T_20 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25] + node _T_21 = not(_T_20) @[lib.scala 94:18] + node _T_22 = bits(_T_11, 12, 12) @[lib.scala 94:34] + node _T_23 = and(_T_21, _T_22) @[lib.scala 94:30] + node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15] + node _T_25 = mux(_T_24, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_26 = bits(rs1_d, 31, 12) @[lib.scala 94:47] + node _T_27 = add(_T_26, UInt<1>("h01")) @[lib.scala 94:54] + node _T_28 = tail(_T_27, 1) @[lib.scala 94:54] + node _T_29 = and(_T_25, _T_28) @[lib.scala 94:41] + node _T_30 = or(_T_19, _T_29) @[lib.scala 93:72] + node _T_31 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24] + node _T_32 = bits(_T_11, 12, 12) @[lib.scala 95:34] + node _T_33 = not(_T_32) @[lib.scala 95:31] + node _T_34 = and(_T_31, _T_33) @[lib.scala 95:29] + node _T_35 = bits(_T_34, 0, 0) @[Bitwise.scala 72:15] + node _T_36 = mux(_T_35, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_37 = bits(rs1_d, 31, 12) @[lib.scala 95:47] + node _T_38 = sub(_T_37, UInt<1>("h01")) @[lib.scala 95:54] + node _T_39 = tail(_T_38, 1) @[lib.scala 95:54] + node _T_40 = and(_T_36, _T_39) @[lib.scala 95:41] + node _T_41 = or(_T_30, _T_40) @[lib.scala 94:61] + node _T_42 = bits(_T_11, 11, 0) @[lib.scala 96:22] + node full_addr_d = cat(_T_41, _T_42) @[Cat.scala 29:58] + node _T_43 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_44 = mux(_T_43, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_45 = and(_T_44, UInt<3>("h01")) @[lsu_lsc_ctl.scala 108:58] + node _T_46 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_47 = mux(_T_46, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_48 = and(_T_47, UInt<3>("h03")) @[lsu_lsc_ctl.scala 109:40] + node _T_49 = or(_T_45, _T_48) @[lsu_lsc_ctl.scala 108:70] + node _T_50 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15] + node _T_51 = mux(_T_50, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_52 = and(_T_51, UInt<3>("h07")) @[lsu_lsc_ctl.scala 110:40] + node addr_offset_d = or(_T_49, _T_52) @[lsu_lsc_ctl.scala 109:52] + node _T_53 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 112:39] + node _T_54 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 112:52] + node _T_55 = cat(_T_53, _T_54) @[Cat.scala 29:58] + node _T_56 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_57 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 112:91] + node _T_58 = cat(_T_56, _T_57) @[Cat.scala 29:58] + node _T_59 = add(_T_55, _T_58) @[lsu_lsc_ctl.scala 112:60] + node end_addr_offset_d = tail(_T_59, 1) @[lsu_lsc_ctl.scala 112:60] + node _T_60 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 113:32] + node _T_61 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 113:70] + node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] + node _T_63 = mux(_T_62, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] + node _T_64 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 113:93] + node _T_65 = cat(_T_63, _T_64) @[Cat.scala 29:58] + node _T_66 = add(_T_60, _T_65) @[lsu_lsc_ctl.scala 113:39] + node full_end_addr_d = tail(_T_66, 1) @[lsu_lsc_ctl.scala 113:39] + io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 114:24] + inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 117:25] + addrcheck.clock <= clock + addrcheck.reset <= reset + addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 121:42] + addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 122:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 124:42] + node _T_67 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 125:50] + addrcheck.io.rs1_region_d <= _T_67 @[lsu_lsc_ctl.scala 125:42] + addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 126:42] + io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 127:42] + io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 128:42] + io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 129:42] + addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 136:42] + wire exc_mscause_r : UInt<4> + exc_mscause_r <= UInt<4>("h00") + wire fir_dccm_access_error_r : UInt<1> + fir_dccm_access_error_r <= UInt<1>("h00") + wire fir_nondccm_access_error_r : UInt<1> + fir_nondccm_access_error_r <= UInt<1>("h00") + wire access_fault_r : UInt<1> + access_fault_r <= UInt<1>("h00") + wire misaligned_fault_r : UInt<1> + misaligned_fault_r <= UInt<1>("h00") + wire lsu_fir_error_m : UInt<2> + lsu_fir_error_m <= UInt<2>("h00") + wire fir_dccm_access_error_m : UInt<1> + fir_dccm_access_error_m <= UInt<1>("h00") + wire fir_nondccm_access_error_m : UInt<1> + fir_nondccm_access_error_m <= UInt<1>("h00") + reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 148:75] + access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 148:75] + reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75] + misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 149:75] + reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75] + exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 150:75] + reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75] + _T_68 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 151:75] + fir_dccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 151:38] + reg _T_69 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75] + _T_69 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 152:75] + fir_nondccm_access_error_m <= _T_69 @[lsu_lsc_ctl.scala 152:38] + node _T_70 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 154:34] + io.lsu_exc_m <= _T_70 @[lsu_lsc_ctl.scala 154:16] + node _T_71 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 155:64] + node _T_72 = and(io.lsu_single_ecc_error_r, _T_71) @[lsu_lsc_ctl.scala 155:62] + node _T_73 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 155:111] + node _T_74 = and(_T_72, _T_73) @[lsu_lsc_ctl.scala 155:92] + node _T_75 = and(_T_74, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 155:136] + io.lsu_single_ecc_error_incr <= _T_75 @[lsu_lsc_ctl.scala 155:32] + node _T_76 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 177:46] + node _T_77 = or(_T_76, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 177:67] + node _T_78 = and(_T_77, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 177:96] + node _T_79 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:119] + node _T_80 = and(_T_78, _T_79) @[lsu_lsc_ctl.scala 177:117] + node _T_81 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:144] + node _T_82 = and(_T_80, _T_81) @[lsu_lsc_ctl.scala 177:142] + node _T_83 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:174] + node _T_84 = and(_T_82, _T_83) @[lsu_lsc_ctl.scala 177:172] + lsu_error_pkt_m.valid <= _T_84 @[lsu_lsc_ctl.scala 177:27] + node _T_85 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:75] + node _T_86 = and(io.lsu_single_ecc_error_m, _T_85) @[lsu_lsc_ctl.scala 178:73] + node _T_87 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:101] + node _T_88 = and(_T_86, _T_87) @[lsu_lsc_ctl.scala 178:99] + lsu_error_pkt_m.bits.single_ecc_error <= _T_88 @[lsu_lsc_ctl.scala 178:43] + lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 179:43] + node _T_89 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 180:46] + lsu_error_pkt_m.bits.exc_type <= _T_89 @[lsu_lsc_ctl.scala 180:43] + node _T_90 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:80] + node _T_91 = and(io.lsu_double_ecc_error_m, _T_90) @[lsu_lsc_ctl.scala 181:78] + node _T_92 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:102] + node _T_93 = and(_T_91, _T_92) @[lsu_lsc_ctl.scala 181:100] + node _T_94 = eq(_T_93, UInt<1>("h01")) @[lsu_lsc_ctl.scala 181:118] + node _T_95 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 181:149] + node _T_96 = mux(_T_94, UInt<4>("h01"), _T_95) @[lsu_lsc_ctl.scala 181:49] + lsu_error_pkt_m.bits.mscause <= _T_96 @[lsu_lsc_ctl.scala 181:43] + node _T_97 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 182:59] + lsu_error_pkt_m.bits.addr <= _T_97 @[lsu_lsc_ctl.scala 182:43] + node _T_98 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:72] + node _T_99 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:117] + node _T_100 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 183:166] + node _T_101 = bits(_T_100, 0, 0) @[lsu_lsc_ctl.scala 183:195] + node _T_102 = mux(_T_101, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 183:137] + node _T_103 = mux(_T_99, UInt<2>("h02"), _T_102) @[lsu_lsc_ctl.scala 183:92] + node _T_104 = mux(_T_98, UInt<2>("h03"), _T_103) @[lsu_lsc_ctl.scala 183:44] + lsu_fir_error_m <= _T_104 @[lsu_lsc_ctl.scala 183:38] + node _T_105 = or(lsu_error_pkt_m.valid, lsu_error_pkt_m.bits.single_ecc_error) @[lsu_lsc_ctl.scala 184:73] + node _T_106 = or(_T_105, io.clk_override) @[lsu_lsc_ctl.scala 184:113] + node _T_107 = bits(_T_106, 0, 0) @[lib.scala 8:44] + node _T_108 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr of rvclkhdr @[lib.scala 417:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 419:18] + rvclkhdr.io.en <= _T_107 @[lib.scala 420:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 421:24] + wire _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 423:50] + _T_109.bits.addr <= UInt<32>("h00") @[lib.scala 423:50] + _T_109.bits.mscause <= UInt<4>("h00") @[lib.scala 423:50] + _T_109.bits.exc_type <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.bits.inst_type <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.valid <= UInt<1>("h00") @[lib.scala 423:50] + reg _T_110 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, clock with : (reset => (reset, _T_109)) @[Reg.scala 27:20] + when _T_107 : @[Reg.scala 28:19] + _T_110.bits.addr <= lsu_error_pkt_m.bits.addr @[Reg.scala 28:23] + _T_110.bits.mscause <= lsu_error_pkt_m.bits.mscause @[Reg.scala 28:23] + _T_110.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[Reg.scala 28:23] + _T_110.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[Reg.scala 28:23] + _T_110.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[Reg.scala 28:23] + _T_110.valid <= lsu_error_pkt_m.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.lsu_error_pkt_r.bits.addr <= _T_110.bits.addr @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.mscause <= _T_110.bits.mscause @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.exc_type <= _T_110.bits.exc_type @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.inst_type <= _T_110.bits.inst_type @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.single_ecc_error <= _T_110.bits.single_ecc_error @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.valid <= _T_110.valid @[lsu_lsc_ctl.scala 184:24] + reg _T_111 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 185:83] + _T_111 <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 185:83] + io.lsu_error_pkt_r.bits.single_ecc_error <= _T_111 @[lsu_lsc_ctl.scala 185:46] + reg _T_112 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 186:67] + _T_112 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 186:67] + io.lsu_error_pkt_r.valid <= _T_112 @[lsu_lsc_ctl.scala 186:30] + reg _T_113 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:75] + _T_113 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 187:75] + io.lsu_fir_error <= _T_113 @[lsu_lsc_ctl.scala 187:38] + dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 189:27] + dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:26] + dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27] + dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22] + dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27] + dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27] + node _T_114 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30] + dma_pkt_d.bits.load <= _T_114 @[lsu_lsc_ctl.scala 195:27] + node _T_115 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56] + node _T_116 = eq(_T_115, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62] + dma_pkt_d.bits.by <= _T_116 @[lsu_lsc_ctl.scala 196:27] + node _T_117 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56] + node _T_118 = eq(_T_117, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62] + dma_pkt_d.bits.half <= _T_118 @[lsu_lsc_ctl.scala 197:27] + node _T_119 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56] + node _T_120 = eq(_T_119, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62] + dma_pkt_d.bits.word <= _T_120 @[lsu_lsc_ctl.scala 198:27] + node _T_121 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56] + node _T_122 = eq(_T_121, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62] + dma_pkt_d.bits.dword <= _T_122 @[lsu_lsc_ctl.scala 199:27] + dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39] + dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39] + dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39] + wire lsu_ld_datafn_r : UInt<32> + lsu_ld_datafn_r <= UInt<32>("h00") + wire lsu_ld_datafn_corr_r : UInt<32> + lsu_ld_datafn_corr_r <= UInt<32>("h00") + wire lsu_ld_datafn_m : UInt<32> + lsu_ld_datafn_m <= UInt<32>("h00") + node _T_123 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50] + node _T_124 = mux(_T_123, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26] + io.lsu_pkt_d.bits.store_data_bypass_m <= _T_124.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_124.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.store_data_bypass_d <= _T_124.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.dma <= _T_124.bits.dma @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.unsign <= _T_124.bits.unsign @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.store <= _T_124.bits.store @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.load <= _T_124.bits.load @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.dword <= _T_124.bits.dword @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.word <= _T_124.bits.word @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.half <= _T_124.bits.half @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.by <= _T_124.bits.by @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.stack <= _T_124.bits.stack @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.fast_int <= _T_124.bits.fast_int @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.valid <= _T_124.valid @[lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20] + node _T_125 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64] + node _T_126 = and(io.flush_m_up, _T_125) @[lsu_lsc_ctl.scala 212:61] + node _T_127 = eq(_T_126, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45] + node _T_128 = and(io.lsu_p.valid, _T_127) @[lsu_lsc_ctl.scala 212:43] + node _T_129 = or(_T_128, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90] + io.lsu_pkt_d.valid <= _T_129 @[lsu_lsc_ctl.scala 212:24] + node _T_130 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68] + node _T_131 = and(io.flush_m_up, _T_130) @[lsu_lsc_ctl.scala 213:65] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49] + node _T_133 = and(io.lsu_pkt_d.valid, _T_132) @[lsu_lsc_ctl.scala 213:47] + lsu_pkt_m_in.valid <= _T_133 @[lsu_lsc_ctl.scala 213:24] + node _T_134 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68] + node _T_135 = and(io.flush_m_up, _T_134) @[lsu_lsc_ctl.scala 214:65] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49] + node _T_137 = and(io.lsu_pkt_m.valid, _T_136) @[lsu_lsc_ctl.scala 214:47] + lsu_pkt_r_in.valid <= _T_137 @[lsu_lsc_ctl.scala 214:24] + wire _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + reg _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_138)) @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65] + _T_139.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65] + io.lsu_pkt_m.bits.store_data_bypass_m <= _T_139.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_139.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.store_data_bypass_d <= _T_139.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.dma <= _T_139.bits.dma @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.unsign <= _T_139.bits.unsign @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.store <= _T_139.bits.store @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.load <= _T_139.bits.load @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.dword <= _T_139.bits.dword @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.word <= _T_139.bits.word @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.half <= _T_139.bits.half @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.by <= _T_139.bits.by @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.stack <= _T_139.bits.stack @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.fast_int <= _T_139.bits.fast_int @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.valid <= _T_139.valid @[lsu_lsc_ctl.scala 216:28] + wire _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + reg _T_141 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_140)) @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65] + _T_141.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65] + io.lsu_pkt_r.bits.store_data_bypass_m <= _T_141.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_141.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.store_data_bypass_d <= _T_141.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.dma <= _T_141.bits.dma @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.unsign <= _T_141.bits.unsign @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.store <= _T_141.bits.store @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.load <= _T_141.bits.load @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.dword <= _T_141.bits.dword @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.word <= _T_141.bits.word @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.half <= _T_141.bits.half @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.by <= _T_141.bits.by @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.stack <= _T_141.bits.stack @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.fast_int <= _T_141.bits.fast_int @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.valid <= _T_141.valid @[lsu_lsc_ctl.scala 217:28] + reg _T_142 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65] + _T_142 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65] + io.lsu_pkt_m.valid <= _T_142 @[lsu_lsc_ctl.scala 218:28] + reg _T_143 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65] + _T_143 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65] + io.lsu_pkt_r.valid <= _T_143 @[lsu_lsc_ctl.scala 219:28] + node _T_144 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59] + node _T_145 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100] + node _T_146 = cat(_T_145, UInt<3>("h00")) @[Cat.scala 29:58] + node dma_mem_wdata_shifted = dshr(_T_144, _T_146) @[lsu_lsc_ctl.scala 221:66] + node _T_147 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63] + node _T_148 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91] + node _T_149 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122] + node store_data_d = mux(_T_147, _T_148, _T_149) @[lsu_lsc_ctl.scala 222:34] + node _T_150 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73] + node _T_151 = bits(io.lsu_exu.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:103] + node _T_152 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:122] + node store_data_m_in = mux(_T_150, _T_151, _T_152) @[lsu_lsc_ctl.scala 223:34] + node _T_153 = bits(io.lsu_addr_d, 2, 2) @[lsu_lsc_ctl.scala 224:62] + reg _T_154 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:48] + _T_154 <= _T_153 @[lsu_lsc_ctl.scala 224:48] + node _T_155 = bits(io.end_addr_d, 2, 2) @[lsu_lsc_ctl.scala 224:124] + reg _T_156 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:110] + _T_156 <= _T_155 @[lsu_lsc_ctl.scala 224:110] + node int = neq(_T_154, _T_156) @[lsu_lsc_ctl.scala 224:72] + node _T_157 = bits(io.lsu_addr_m, 2, 2) @[lsu_lsc_ctl.scala 225:62] + reg _T_158 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:48] + _T_158 <= _T_157 @[lsu_lsc_ctl.scala 225:48] + node _T_159 = bits(io.end_addr_m, 2, 2) @[lsu_lsc_ctl.scala 225:124] + reg _T_160 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:110] + _T_160 <= _T_159 @[lsu_lsc_ctl.scala 225:110] + node int1 = neq(_T_158, _T_160) @[lsu_lsc_ctl.scala 225:72] + reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:72] + store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 226:72] + reg _T_161 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62] + _T_161 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 227:62] + io.lsu_addr_m <= _T_161 @[lsu_lsc_ctl.scala 227:24] + reg _T_162 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:62] + _T_162 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 228:62] + io.lsu_addr_r <= _T_162 @[lsu_lsc_ctl.scala 228:24] + node _T_163 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:60] + node _T_164 = mux(int, end_addr_pre_m, _T_163) @[lsu_lsc_ctl.scala 229:27] + node _T_165 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:117] + reg _T_166 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:103] + _T_166 <= _T_165 @[lsu_lsc_ctl.scala 229:103] + node _T_167 = cat(_T_164, _T_166) @[Cat.scala 29:58] + io.end_addr_m <= _T_167 @[lsu_lsc_ctl.scala 229:17] + node _T_168 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:61] + node _T_169 = mux(int1, end_addr_pre_r, _T_168) @[lsu_lsc_ctl.scala 230:27] + node _T_170 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:118] + reg _T_171 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:104] + _T_171 <= _T_170 @[lsu_lsc_ctl.scala 230:104] + node _T_172 = cat(_T_169, _T_171) @[Cat.scala 29:58] + io.end_addr_r <= _T_172 @[lsu_lsc_ctl.scala 230:17] + node _T_173 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 231:41] + node _T_174 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 231:69] + node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 231:87] + node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_175 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_175 : @[Reg.scala 28:19] + _T_177 <= _T_173 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + end_addr_pre_m <= _T_177 @[lsu_lsc_ctl.scala 231:18] + node _T_178 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:41] + node _T_179 = and(io.lsu_pkt_m.valid, int) @[lsu_lsc_ctl.scala 232:69] + node _T_180 = or(_T_179, io.clk_override) @[lsu_lsc_ctl.scala 232:76] + node _T_181 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_180 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_182 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_180 : @[Reg.scala 28:19] + _T_182 <= _T_178 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + end_addr_pre_r <= _T_182 @[lsu_lsc_ctl.scala 232:18] + reg _T_183 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62] + _T_183 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 233:62] + io.addr_in_dccm_m <= _T_183 @[lsu_lsc_ctl.scala 233:24] + reg _T_184 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62] + _T_184 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 234:62] + io.addr_in_dccm_r <= _T_184 @[lsu_lsc_ctl.scala 234:24] + reg _T_185 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62] + _T_185 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 235:62] + io.addr_in_pic_m <= _T_185 @[lsu_lsc_ctl.scala 235:24] + reg _T_186 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62] + _T_186 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 236:62] + io.addr_in_pic_r <= _T_186 @[lsu_lsc_ctl.scala 236:24] + reg _T_187 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62] + _T_187 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 237:62] + io.addr_external_m <= _T_187 @[lsu_lsc_ctl.scala 237:24] + reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:66] + addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 238:66] + node _T_188 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 239:77] + node _T_189 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_188 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_188 : @[Reg.scala 28:19] + bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_190 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 242:52] + io.lsu_fir_addr <= _T_190 @[lsu_lsc_ctl.scala 242:28] + io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 244:28] + node _T_191 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 246:68] + node _T_192 = and(io.lsu_pkt_r.valid, _T_191) @[lsu_lsc_ctl.scala 246:41] + node _T_193 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:96] + node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 246:94] + node _T_195 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:110] + node _T_196 = and(_T_194, _T_195) @[lsu_lsc_ctl.scala 246:108] + io.lsu_commit_r <= _T_196 @[lsu_lsc_ctl.scala 246:19] + node _T_197 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 247:52] + node _T_198 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 247:69] + node _T_199 = bits(_T_198, 0, 0) @[Bitwise.scala 72:15] + node _T_200 = mux(_T_199, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_201 = or(_T_197, _T_200) @[lsu_lsc_ctl.scala 247:59] + node _T_202 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 247:133] + node _T_203 = mux(_T_202, io.lsu_exu.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 247:94] + node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 247:89] + io.store_data_m <= _T_204 @[lsu_lsc_ctl.scala 247:29] + node _T_205 = mux(io.addr_external_m, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 268:33] + lsu_ld_datafn_m <= _T_205 @[lsu_lsc_ctl.scala 268:27] + node _T_206 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 269:49] + node _T_207 = mux(_T_206, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 269:33] + lsu_ld_datafn_corr_r <= _T_207 @[lsu_lsc_ctl.scala 269:27] + node _T_208 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 270:74] + node _T_209 = bits(_T_208, 0, 0) @[Bitwise.scala 72:15] + node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_211 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 270:133] + node _T_212 = cat(UInt<24>("h00"), _T_211) @[Cat.scala 29:58] + node _T_213 = and(_T_210, _T_212) @[lsu_lsc_ctl.scala 270:102] + node _T_214 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 271:43] + node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15] + node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_217 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 271:102] + node _T_218 = cat(UInt<16>("h00"), _T_217) @[Cat.scala 29:58] + node _T_219 = and(_T_216, _T_218) @[lsu_lsc_ctl.scala 271:71] + node _T_220 = or(_T_213, _T_219) @[lsu_lsc_ctl.scala 270:141] + node _T_221 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17] + node _T_222 = and(_T_221, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 272:43] + node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15] + node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_225 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 272:102] + node _T_226 = bits(_T_225, 0, 0) @[Bitwise.scala 72:15] + node _T_227 = mux(_T_226, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_228 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 272:125] + node _T_229 = cat(_T_227, _T_228) @[Cat.scala 29:58] + node _T_230 = and(_T_224, _T_229) @[lsu_lsc_ctl.scala 272:71] + node _T_231 = or(_T_220, _T_230) @[lsu_lsc_ctl.scala 271:114] + node _T_232 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 273:17] + node _T_233 = and(_T_232, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 273:43] + node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15] + node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_236 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 273:101] + node _T_237 = bits(_T_236, 0, 0) @[Bitwise.scala 72:15] + node _T_238 = mux(_T_237, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_239 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 273:125] + node _T_240 = cat(_T_238, _T_239) @[Cat.scala 29:58] + node _T_241 = and(_T_235, _T_240) @[lsu_lsc_ctl.scala 273:71] + node _T_242 = or(_T_231, _T_241) @[lsu_lsc_ctl.scala 272:134] + node _T_243 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_244 = mux(_T_243, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_245 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 274:60] + node _T_246 = and(_T_244, _T_245) @[lsu_lsc_ctl.scala 274:43] + node _T_247 = or(_T_242, _T_246) @[lsu_lsc_ctl.scala 273:134] + io.lsu_exu.lsu_result_m <= _T_247 @[lsu_lsc_ctl.scala 270:35] + node _T_248 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 275:66] + node _T_249 = bits(_T_248, 0, 0) @[Bitwise.scala 72:15] + node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_251 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 275:130] + node _T_252 = cat(UInt<24>("h00"), _T_251) @[Cat.scala 29:58] + node _T_253 = and(_T_250, _T_252) @[lsu_lsc_ctl.scala 275:94] + node _T_254 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 276:43] + node _T_255 = bits(_T_254, 0, 0) @[Bitwise.scala 72:15] + node _T_256 = mux(_T_255, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_257 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 276:107] + node _T_258 = cat(UInt<16>("h00"), _T_257) @[Cat.scala 29:58] + node _T_259 = and(_T_256, _T_258) @[lsu_lsc_ctl.scala 276:71] + node _T_260 = or(_T_253, _T_259) @[lsu_lsc_ctl.scala 275:138] + node _T_261 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17] + node _T_262 = and(_T_261, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 277:43] + node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15] + node _T_264 = mux(_T_263, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 277:107] + node _T_266 = bits(_T_265, 0, 0) @[Bitwise.scala 72:15] + node _T_267 = mux(_T_266, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_268 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 277:135] + node _T_269 = cat(_T_267, _T_268) @[Cat.scala 29:58] + node _T_270 = and(_T_264, _T_269) @[lsu_lsc_ctl.scala 277:71] + node _T_271 = or(_T_260, _T_270) @[lsu_lsc_ctl.scala 276:119] + node _T_272 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 278:17] + node _T_273 = and(_T_272, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 278:43] + node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15] + node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 278:106] + node _T_277 = bits(_T_276, 0, 0) @[Bitwise.scala 72:15] + node _T_278 = mux(_T_277, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_279 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 278:135] + node _T_280 = cat(_T_278, _T_279) @[Cat.scala 29:58] + node _T_281 = and(_T_275, _T_280) @[lsu_lsc_ctl.scala 278:71] + node _T_282 = or(_T_271, _T_281) @[lsu_lsc_ctl.scala 277:144] + node _T_283 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_284 = mux(_T_283, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_285 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 279:65] + node _T_286 = and(_T_284, _T_285) @[lsu_lsc_ctl.scala 279:43] + node _T_287 = or(_T_282, _T_286) @[lsu_lsc_ctl.scala 278:144] + io.lsu_result_corr_r <= _T_287 @[lsu_lsc_ctl.scala 275:27] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_dccm_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, flip scan_mode : UInt<1>} + + node picm_rd_data_m = cat(io.lsu_pic.picm_rd_data, io.lsu_pic.picm_rd_data) @[Cat.scala 29:58] + node dccm_rdata_corr_r = cat(io.sec_data_hi_r, io.sec_data_lo_r) @[Cat.scala 29:58] + node dccm_rdata_corr_m = cat(io.sec_data_hi_m, io.sec_data_lo_m) @[Cat.scala 29:58] + node dccm_rdata_r = cat(io.dccm_rdata_hi_r, io.dccm_rdata_lo_r) @[Cat.scala 29:58] + node dccm_rdata_m = cat(io.dccm_rdata_hi_m, io.dccm_rdata_lo_m) @[Cat.scala 29:58] + wire lsu_rdata_r : UInt<64> + lsu_rdata_r <= UInt<1>("h00") + wire lsu_rdata_m : UInt<64> + lsu_rdata_m <= UInt<1>("h00") + wire lsu_rdata_corr_r : UInt<64> + lsu_rdata_corr_r <= UInt<1>("h00") + wire lsu_rdata_corr_m : UInt<64> + lsu_rdata_corr_m <= UInt<1>("h00") + wire stbuf_fwddata_r : UInt<64> + stbuf_fwddata_r <= UInt<1>("h00") + wire stbuf_fwdbyteen_r : UInt<64> + stbuf_fwdbyteen_r <= UInt<1>("h00") + wire picm_rd_data_r_32 : UInt<32> + picm_rd_data_r_32 <= UInt<1>("h00") + wire picm_rd_data_r : UInt<64> + picm_rd_data_r <= UInt<1>("h00") + wire lsu_ld_data_corr_m : UInt<64> + lsu_ld_data_corr_m <= UInt<1>("h00") + wire stbuf_fwddata_en : UInt<1> + stbuf_fwddata_en <= UInt<1>("h00") + wire lsu_double_ecc_error_r_ff : UInt<1> + lsu_double_ecc_error_r_ff <= UInt<1>("h00") + wire ld_single_ecc_error_hi_r_ff : UInt<1> + ld_single_ecc_error_hi_r_ff <= UInt<1>("h00") + wire ld_single_ecc_error_lo_r_ff : UInt<1> + ld_single_ecc_error_lo_r_ff <= UInt<1>("h00") + wire ld_sec_addr_hi_r_ff : UInt<16> + ld_sec_addr_hi_r_ff <= UInt<1>("h00") + wire ld_sec_addr_lo_r_ff : UInt<16> + ld_sec_addr_lo_r_ff <= UInt<1>("h00") + io.lsu_ld_data_m <= UInt<1>("h00") @[lsu_dccm_ctl.scala 121:20] + node _T = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.load) @[lsu_dccm_ctl.scala 145:63] + node _T_1 = and(_T, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 145:88] + io.dma_dccm_ctl.dccm_dma_rvalid <= _T_1 @[lsu_dccm_ctl.scala 145:41] + io.dma_dccm_ctl.dccm_dma_ecc_error <= io.lsu_double_ecc_error_m @[lsu_dccm_ctl.scala 146:41] + node _T_2 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44] + node _T_3 = bits(lsu_rdata_corr_m, 31, 0) @[lsu_dccm_ctl.scala 147:104] + node _T_4 = cat(_T_3, _T_3) @[Cat.scala 29:58] + node _T_5 = mux(_T_2, lsu_rdata_corr_m, _T_4) @[lsu_dccm_ctl.scala 147:47] + io.dma_dccm_ctl.dccm_dma_rdata <= _T_5 @[lsu_dccm_ctl.scala 147:41] + io.dma_dccm_ctl.dccm_dma_rtag <= io.dma_mem_tag_m @[lsu_dccm_ctl.scala 148:41] + io.dccm_rdata_lo_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 149:28] + io.dccm_rdata_hi_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 150:28] + io.dccm_data_ecc_hi_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 151:28] + io.dccm_data_ecc_lo_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 152:28] + io.lsu_ld_data_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 153:28] + node _T_6 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_7 = bits(_T_6, 0, 0) @[lsu_dccm_ctl.scala 155:134] + node _T_8 = bits(_T_7, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_9 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_10 = bits(_T_9, 7, 0) @[lsu_dccm_ctl.scala 155:196] + node _T_11 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_12 = bits(picm_rd_data_m, 7, 0) @[lsu_dccm_ctl.scala 155:253] + node _T_13 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_14 = mux(_T_13, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_15 = bits(dccm_rdata_corr_m, 7, 0) @[lsu_dccm_ctl.scala 155:313] + node _T_16 = and(_T_14, _T_15) @[lsu_dccm_ctl.scala 155:294] + node _T_17 = mux(_T_11, _T_12, _T_16) @[lsu_dccm_ctl.scala 155:214] + node _T_18 = mux(_T_8, _T_10, _T_17) @[lsu_dccm_ctl.scala 155:78] + node _T_19 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_20 = xor(UInt<8>("h0ff"), _T_19) @[Bitwise.scala 102:21] + node _T_21 = shr(_T_18, 4) @[Bitwise.scala 103:21] + node _T_22 = and(_T_21, _T_20) @[Bitwise.scala 103:31] + node _T_23 = bits(_T_18, 3, 0) @[Bitwise.scala 103:46] + node _T_24 = shl(_T_23, 4) @[Bitwise.scala 103:65] + node _T_25 = not(_T_20) @[Bitwise.scala 103:77] + node _T_26 = and(_T_24, _T_25) @[Bitwise.scala 103:75] + node _T_27 = or(_T_22, _T_26) @[Bitwise.scala 103:39] + node _T_28 = bits(_T_20, 5, 0) @[Bitwise.scala 102:28] + node _T_29 = shl(_T_28, 2) @[Bitwise.scala 102:47] + node _T_30 = xor(_T_20, _T_29) @[Bitwise.scala 102:21] + node _T_31 = shr(_T_27, 2) @[Bitwise.scala 103:21] + node _T_32 = and(_T_31, _T_30) @[Bitwise.scala 103:31] + node _T_33 = bits(_T_27, 5, 0) @[Bitwise.scala 103:46] + node _T_34 = shl(_T_33, 2) @[Bitwise.scala 103:65] + node _T_35 = not(_T_30) @[Bitwise.scala 103:77] + node _T_36 = and(_T_34, _T_35) @[Bitwise.scala 103:75] + node _T_37 = or(_T_32, _T_36) @[Bitwise.scala 103:39] + node _T_38 = bits(_T_30, 6, 0) @[Bitwise.scala 102:28] + node _T_39 = shl(_T_38, 1) @[Bitwise.scala 102:47] + node _T_40 = xor(_T_30, _T_39) @[Bitwise.scala 102:21] + node _T_41 = shr(_T_37, 1) @[Bitwise.scala 103:21] + node _T_42 = and(_T_41, _T_40) @[Bitwise.scala 103:31] + node _T_43 = bits(_T_37, 6, 0) @[Bitwise.scala 103:46] + node _T_44 = shl(_T_43, 1) @[Bitwise.scala 103:65] + node _T_45 = not(_T_40) @[Bitwise.scala 103:77] + node _T_46 = and(_T_44, _T_45) @[Bitwise.scala 103:75] + node _T_47 = or(_T_42, _T_46) @[Bitwise.scala 103:39] + node _T_48 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_49 = bits(_T_48, 1, 1) @[lsu_dccm_ctl.scala 155:134] + node _T_50 = bits(_T_49, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_51 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_52 = bits(_T_51, 15, 8) @[lsu_dccm_ctl.scala 155:196] + node _T_53 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_54 = bits(picm_rd_data_m, 15, 8) @[lsu_dccm_ctl.scala 155:253] + node _T_55 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_56 = mux(_T_55, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_57 = bits(dccm_rdata_corr_m, 15, 8) @[lsu_dccm_ctl.scala 155:313] + node _T_58 = and(_T_56, _T_57) @[lsu_dccm_ctl.scala 155:294] + node _T_59 = mux(_T_53, _T_54, _T_58) @[lsu_dccm_ctl.scala 155:214] + node _T_60 = mux(_T_50, _T_52, _T_59) @[lsu_dccm_ctl.scala 155:78] + node _T_61 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_62 = xor(UInt<8>("h0ff"), _T_61) @[Bitwise.scala 102:21] + node _T_63 = shr(_T_60, 4) @[Bitwise.scala 103:21] + node _T_64 = and(_T_63, _T_62) @[Bitwise.scala 103:31] + node _T_65 = bits(_T_60, 3, 0) @[Bitwise.scala 103:46] + node _T_66 = shl(_T_65, 4) @[Bitwise.scala 103:65] + node _T_67 = not(_T_62) @[Bitwise.scala 103:77] + node _T_68 = and(_T_66, _T_67) @[Bitwise.scala 103:75] + node _T_69 = or(_T_64, _T_68) @[Bitwise.scala 103:39] + node _T_70 = bits(_T_62, 5, 0) @[Bitwise.scala 102:28] + node _T_71 = shl(_T_70, 2) @[Bitwise.scala 102:47] + node _T_72 = xor(_T_62, _T_71) @[Bitwise.scala 102:21] + node _T_73 = shr(_T_69, 2) @[Bitwise.scala 103:21] + node _T_74 = and(_T_73, _T_72) @[Bitwise.scala 103:31] + node _T_75 = bits(_T_69, 5, 0) @[Bitwise.scala 103:46] + node _T_76 = shl(_T_75, 2) @[Bitwise.scala 103:65] + node _T_77 = not(_T_72) @[Bitwise.scala 103:77] + node _T_78 = and(_T_76, _T_77) @[Bitwise.scala 103:75] + node _T_79 = or(_T_74, _T_78) @[Bitwise.scala 103:39] + node _T_80 = bits(_T_72, 6, 0) @[Bitwise.scala 102:28] + node _T_81 = shl(_T_80, 1) @[Bitwise.scala 102:47] + node _T_82 = xor(_T_72, _T_81) @[Bitwise.scala 102:21] + node _T_83 = shr(_T_79, 1) @[Bitwise.scala 103:21] + node _T_84 = and(_T_83, _T_82) @[Bitwise.scala 103:31] + node _T_85 = bits(_T_79, 6, 0) @[Bitwise.scala 103:46] + node _T_86 = shl(_T_85, 1) @[Bitwise.scala 103:65] + node _T_87 = not(_T_82) @[Bitwise.scala 103:77] + node _T_88 = and(_T_86, _T_87) @[Bitwise.scala 103:75] + node _T_89 = or(_T_84, _T_88) @[Bitwise.scala 103:39] + node _T_90 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_91 = bits(_T_90, 2, 2) @[lsu_dccm_ctl.scala 155:134] + node _T_92 = bits(_T_91, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_93 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_94 = bits(_T_93, 23, 16) @[lsu_dccm_ctl.scala 155:196] + node _T_95 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_96 = bits(picm_rd_data_m, 23, 16) @[lsu_dccm_ctl.scala 155:253] + node _T_97 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_98 = mux(_T_97, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_99 = bits(dccm_rdata_corr_m, 23, 16) @[lsu_dccm_ctl.scala 155:313] + node _T_100 = and(_T_98, _T_99) @[lsu_dccm_ctl.scala 155:294] + node _T_101 = mux(_T_95, _T_96, _T_100) @[lsu_dccm_ctl.scala 155:214] + node _T_102 = mux(_T_92, _T_94, _T_101) @[lsu_dccm_ctl.scala 155:78] + node _T_103 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_104 = xor(UInt<8>("h0ff"), _T_103) @[Bitwise.scala 102:21] + node _T_105 = shr(_T_102, 4) @[Bitwise.scala 103:21] + node _T_106 = and(_T_105, _T_104) @[Bitwise.scala 103:31] + node _T_107 = bits(_T_102, 3, 0) @[Bitwise.scala 103:46] + node _T_108 = shl(_T_107, 4) @[Bitwise.scala 103:65] + node _T_109 = not(_T_104) @[Bitwise.scala 103:77] + node _T_110 = and(_T_108, _T_109) @[Bitwise.scala 103:75] + node _T_111 = or(_T_106, _T_110) @[Bitwise.scala 103:39] + node _T_112 = bits(_T_104, 5, 0) @[Bitwise.scala 102:28] + node _T_113 = shl(_T_112, 2) @[Bitwise.scala 102:47] + node _T_114 = xor(_T_104, _T_113) @[Bitwise.scala 102:21] + node _T_115 = shr(_T_111, 2) @[Bitwise.scala 103:21] + node _T_116 = and(_T_115, _T_114) @[Bitwise.scala 103:31] + node _T_117 = bits(_T_111, 5, 0) @[Bitwise.scala 103:46] + node _T_118 = shl(_T_117, 2) @[Bitwise.scala 103:65] + node _T_119 = not(_T_114) @[Bitwise.scala 103:77] + node _T_120 = and(_T_118, _T_119) @[Bitwise.scala 103:75] + node _T_121 = or(_T_116, _T_120) @[Bitwise.scala 103:39] + node _T_122 = bits(_T_114, 6, 0) @[Bitwise.scala 102:28] + node _T_123 = shl(_T_122, 1) @[Bitwise.scala 102:47] + node _T_124 = xor(_T_114, _T_123) @[Bitwise.scala 102:21] + node _T_125 = shr(_T_121, 1) @[Bitwise.scala 103:21] + node _T_126 = and(_T_125, _T_124) @[Bitwise.scala 103:31] + node _T_127 = bits(_T_121, 6, 0) @[Bitwise.scala 103:46] + node _T_128 = shl(_T_127, 1) @[Bitwise.scala 103:65] + node _T_129 = not(_T_124) @[Bitwise.scala 103:77] + node _T_130 = and(_T_128, _T_129) @[Bitwise.scala 103:75] + node _T_131 = or(_T_126, _T_130) @[Bitwise.scala 103:39] + node _T_132 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_133 = bits(_T_132, 3, 3) @[lsu_dccm_ctl.scala 155:134] + node _T_134 = bits(_T_133, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_135 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_136 = bits(_T_135, 31, 24) @[lsu_dccm_ctl.scala 155:196] + node _T_137 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_138 = bits(picm_rd_data_m, 31, 24) @[lsu_dccm_ctl.scala 155:253] + node _T_139 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_140 = mux(_T_139, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_141 = bits(dccm_rdata_corr_m, 31, 24) @[lsu_dccm_ctl.scala 155:313] + node _T_142 = and(_T_140, _T_141) @[lsu_dccm_ctl.scala 155:294] + node _T_143 = mux(_T_137, _T_138, _T_142) @[lsu_dccm_ctl.scala 155:214] + node _T_144 = mux(_T_134, _T_136, _T_143) @[lsu_dccm_ctl.scala 155:78] + node _T_145 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_146 = xor(UInt<8>("h0ff"), _T_145) @[Bitwise.scala 102:21] + node _T_147 = shr(_T_144, 4) @[Bitwise.scala 103:21] + node _T_148 = and(_T_147, _T_146) @[Bitwise.scala 103:31] + node _T_149 = bits(_T_144, 3, 0) @[Bitwise.scala 103:46] + node _T_150 = shl(_T_149, 4) @[Bitwise.scala 103:65] + node _T_151 = not(_T_146) @[Bitwise.scala 103:77] + node _T_152 = and(_T_150, _T_151) @[Bitwise.scala 103:75] + node _T_153 = or(_T_148, _T_152) @[Bitwise.scala 103:39] + node _T_154 = bits(_T_146, 5, 0) @[Bitwise.scala 102:28] + node _T_155 = shl(_T_154, 2) @[Bitwise.scala 102:47] + node _T_156 = xor(_T_146, _T_155) @[Bitwise.scala 102:21] + node _T_157 = shr(_T_153, 2) @[Bitwise.scala 103:21] + node _T_158 = and(_T_157, _T_156) @[Bitwise.scala 103:31] + node _T_159 = bits(_T_153, 5, 0) @[Bitwise.scala 103:46] + node _T_160 = shl(_T_159, 2) @[Bitwise.scala 103:65] + node _T_161 = not(_T_156) @[Bitwise.scala 103:77] + node _T_162 = and(_T_160, _T_161) @[Bitwise.scala 103:75] + node _T_163 = or(_T_158, _T_162) @[Bitwise.scala 103:39] + node _T_164 = bits(_T_156, 6, 0) @[Bitwise.scala 102:28] + node _T_165 = shl(_T_164, 1) @[Bitwise.scala 102:47] + node _T_166 = xor(_T_156, _T_165) @[Bitwise.scala 102:21] + node _T_167 = shr(_T_163, 1) @[Bitwise.scala 103:21] + node _T_168 = and(_T_167, _T_166) @[Bitwise.scala 103:31] + node _T_169 = bits(_T_163, 6, 0) @[Bitwise.scala 103:46] + node _T_170 = shl(_T_169, 1) @[Bitwise.scala 103:65] + node _T_171 = not(_T_166) @[Bitwise.scala 103:77] + node _T_172 = and(_T_170, _T_171) @[Bitwise.scala 103:75] + node _T_173 = or(_T_168, _T_172) @[Bitwise.scala 103:39] + node _T_174 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_175 = bits(_T_174, 4, 4) @[lsu_dccm_ctl.scala 155:134] + node _T_176 = bits(_T_175, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_177 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_178 = bits(_T_177, 39, 32) @[lsu_dccm_ctl.scala 155:196] + node _T_179 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_180 = bits(picm_rd_data_m, 39, 32) @[lsu_dccm_ctl.scala 155:253] + node _T_181 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_182 = mux(_T_181, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_183 = bits(dccm_rdata_corr_m, 39, 32) @[lsu_dccm_ctl.scala 155:313] + node _T_184 = and(_T_182, _T_183) @[lsu_dccm_ctl.scala 155:294] + node _T_185 = mux(_T_179, _T_180, _T_184) @[lsu_dccm_ctl.scala 155:214] + node _T_186 = mux(_T_176, _T_178, _T_185) @[lsu_dccm_ctl.scala 155:78] + node _T_187 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_188 = xor(UInt<8>("h0ff"), _T_187) @[Bitwise.scala 102:21] + node _T_189 = shr(_T_186, 4) @[Bitwise.scala 103:21] + node _T_190 = and(_T_189, _T_188) @[Bitwise.scala 103:31] + node _T_191 = bits(_T_186, 3, 0) @[Bitwise.scala 103:46] + node _T_192 = shl(_T_191, 4) @[Bitwise.scala 103:65] + node _T_193 = not(_T_188) @[Bitwise.scala 103:77] + node _T_194 = and(_T_192, _T_193) @[Bitwise.scala 103:75] + node _T_195 = or(_T_190, _T_194) @[Bitwise.scala 103:39] + node _T_196 = bits(_T_188, 5, 0) @[Bitwise.scala 102:28] + node _T_197 = shl(_T_196, 2) @[Bitwise.scala 102:47] + node _T_198 = xor(_T_188, _T_197) @[Bitwise.scala 102:21] + node _T_199 = shr(_T_195, 2) @[Bitwise.scala 103:21] + node _T_200 = and(_T_199, _T_198) @[Bitwise.scala 103:31] + node _T_201 = bits(_T_195, 5, 0) @[Bitwise.scala 103:46] + node _T_202 = shl(_T_201, 2) @[Bitwise.scala 103:65] + node _T_203 = not(_T_198) @[Bitwise.scala 103:77] + node _T_204 = and(_T_202, _T_203) @[Bitwise.scala 103:75] + node _T_205 = or(_T_200, _T_204) @[Bitwise.scala 103:39] + node _T_206 = bits(_T_198, 6, 0) @[Bitwise.scala 102:28] + node _T_207 = shl(_T_206, 1) @[Bitwise.scala 102:47] + node _T_208 = xor(_T_198, _T_207) @[Bitwise.scala 102:21] + node _T_209 = shr(_T_205, 1) @[Bitwise.scala 103:21] + node _T_210 = and(_T_209, _T_208) @[Bitwise.scala 103:31] + node _T_211 = bits(_T_205, 6, 0) @[Bitwise.scala 103:46] + node _T_212 = shl(_T_211, 1) @[Bitwise.scala 103:65] + node _T_213 = not(_T_208) @[Bitwise.scala 103:77] + node _T_214 = and(_T_212, _T_213) @[Bitwise.scala 103:75] + node _T_215 = or(_T_210, _T_214) @[Bitwise.scala 103:39] + node _T_216 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_217 = bits(_T_216, 5, 5) @[lsu_dccm_ctl.scala 155:134] + node _T_218 = bits(_T_217, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_219 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_220 = bits(_T_219, 47, 40) @[lsu_dccm_ctl.scala 155:196] + node _T_221 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_222 = bits(picm_rd_data_m, 47, 40) @[lsu_dccm_ctl.scala 155:253] + node _T_223 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_224 = mux(_T_223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_225 = bits(dccm_rdata_corr_m, 47, 40) @[lsu_dccm_ctl.scala 155:313] + node _T_226 = and(_T_224, _T_225) @[lsu_dccm_ctl.scala 155:294] + node _T_227 = mux(_T_221, _T_222, _T_226) @[lsu_dccm_ctl.scala 155:214] + node _T_228 = mux(_T_218, _T_220, _T_227) @[lsu_dccm_ctl.scala 155:78] + node _T_229 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_230 = xor(UInt<8>("h0ff"), _T_229) @[Bitwise.scala 102:21] + node _T_231 = shr(_T_228, 4) @[Bitwise.scala 103:21] + node _T_232 = and(_T_231, _T_230) @[Bitwise.scala 103:31] + node _T_233 = bits(_T_228, 3, 0) @[Bitwise.scala 103:46] + node _T_234 = shl(_T_233, 4) @[Bitwise.scala 103:65] + node _T_235 = not(_T_230) @[Bitwise.scala 103:77] + node _T_236 = and(_T_234, _T_235) @[Bitwise.scala 103:75] + node _T_237 = or(_T_232, _T_236) @[Bitwise.scala 103:39] + node _T_238 = bits(_T_230, 5, 0) @[Bitwise.scala 102:28] + node _T_239 = shl(_T_238, 2) @[Bitwise.scala 102:47] + node _T_240 = xor(_T_230, _T_239) @[Bitwise.scala 102:21] + node _T_241 = shr(_T_237, 2) @[Bitwise.scala 103:21] + node _T_242 = and(_T_241, _T_240) @[Bitwise.scala 103:31] + node _T_243 = bits(_T_237, 5, 0) @[Bitwise.scala 103:46] + node _T_244 = shl(_T_243, 2) @[Bitwise.scala 103:65] + node _T_245 = not(_T_240) @[Bitwise.scala 103:77] + node _T_246 = and(_T_244, _T_245) @[Bitwise.scala 103:75] + node _T_247 = or(_T_242, _T_246) @[Bitwise.scala 103:39] + node _T_248 = bits(_T_240, 6, 0) @[Bitwise.scala 102:28] + node _T_249 = shl(_T_248, 1) @[Bitwise.scala 102:47] + node _T_250 = xor(_T_240, _T_249) @[Bitwise.scala 102:21] + node _T_251 = shr(_T_247, 1) @[Bitwise.scala 103:21] + node _T_252 = and(_T_251, _T_250) @[Bitwise.scala 103:31] + node _T_253 = bits(_T_247, 6, 0) @[Bitwise.scala 103:46] + node _T_254 = shl(_T_253, 1) @[Bitwise.scala 103:65] + node _T_255 = not(_T_250) @[Bitwise.scala 103:77] + node _T_256 = and(_T_254, _T_255) @[Bitwise.scala 103:75] + node _T_257 = or(_T_252, _T_256) @[Bitwise.scala 103:39] + node _T_258 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_259 = bits(_T_258, 6, 6) @[lsu_dccm_ctl.scala 155:134] + node _T_260 = bits(_T_259, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_261 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_262 = bits(_T_261, 55, 48) @[lsu_dccm_ctl.scala 155:196] + node _T_263 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_264 = bits(picm_rd_data_m, 55, 48) @[lsu_dccm_ctl.scala 155:253] + node _T_265 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_266 = mux(_T_265, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_267 = bits(dccm_rdata_corr_m, 55, 48) @[lsu_dccm_ctl.scala 155:313] + node _T_268 = and(_T_266, _T_267) @[lsu_dccm_ctl.scala 155:294] + node _T_269 = mux(_T_263, _T_264, _T_268) @[lsu_dccm_ctl.scala 155:214] + node _T_270 = mux(_T_260, _T_262, _T_269) @[lsu_dccm_ctl.scala 155:78] + node _T_271 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_272 = xor(UInt<8>("h0ff"), _T_271) @[Bitwise.scala 102:21] + node _T_273 = shr(_T_270, 4) @[Bitwise.scala 103:21] + node _T_274 = and(_T_273, _T_272) @[Bitwise.scala 103:31] + node _T_275 = bits(_T_270, 3, 0) @[Bitwise.scala 103:46] + node _T_276 = shl(_T_275, 4) @[Bitwise.scala 103:65] + node _T_277 = not(_T_272) @[Bitwise.scala 103:77] + node _T_278 = and(_T_276, _T_277) @[Bitwise.scala 103:75] + node _T_279 = or(_T_274, _T_278) @[Bitwise.scala 103:39] + node _T_280 = bits(_T_272, 5, 0) @[Bitwise.scala 102:28] + node _T_281 = shl(_T_280, 2) @[Bitwise.scala 102:47] + node _T_282 = xor(_T_272, _T_281) @[Bitwise.scala 102:21] + node _T_283 = shr(_T_279, 2) @[Bitwise.scala 103:21] + node _T_284 = and(_T_283, _T_282) @[Bitwise.scala 103:31] + node _T_285 = bits(_T_279, 5, 0) @[Bitwise.scala 103:46] + node _T_286 = shl(_T_285, 2) @[Bitwise.scala 103:65] + node _T_287 = not(_T_282) @[Bitwise.scala 103:77] + node _T_288 = and(_T_286, _T_287) @[Bitwise.scala 103:75] + node _T_289 = or(_T_284, _T_288) @[Bitwise.scala 103:39] + node _T_290 = bits(_T_282, 6, 0) @[Bitwise.scala 102:28] + node _T_291 = shl(_T_290, 1) @[Bitwise.scala 102:47] + node _T_292 = xor(_T_282, _T_291) @[Bitwise.scala 102:21] + node _T_293 = shr(_T_289, 1) @[Bitwise.scala 103:21] + node _T_294 = and(_T_293, _T_292) @[Bitwise.scala 103:31] + node _T_295 = bits(_T_289, 6, 0) @[Bitwise.scala 103:46] + node _T_296 = shl(_T_295, 1) @[Bitwise.scala 103:65] + node _T_297 = not(_T_292) @[Bitwise.scala 103:77] + node _T_298 = and(_T_296, _T_297) @[Bitwise.scala 103:75] + node _T_299 = or(_T_294, _T_298) @[Bitwise.scala 103:39] + node _T_300 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_301 = bits(_T_300, 7, 7) @[lsu_dccm_ctl.scala 155:134] + node _T_302 = bits(_T_301, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_303 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_304 = bits(_T_303, 63, 56) @[lsu_dccm_ctl.scala 155:196] + node _T_305 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_306 = bits(picm_rd_data_m, 63, 56) @[lsu_dccm_ctl.scala 155:253] + node _T_307 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_308 = mux(_T_307, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_309 = bits(dccm_rdata_corr_m, 63, 56) @[lsu_dccm_ctl.scala 155:313] + node _T_310 = and(_T_308, _T_309) @[lsu_dccm_ctl.scala 155:294] + node _T_311 = mux(_T_305, _T_306, _T_310) @[lsu_dccm_ctl.scala 155:214] + node _T_312 = mux(_T_302, _T_304, _T_311) @[lsu_dccm_ctl.scala 155:78] + node _T_313 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_314 = xor(UInt<8>("h0ff"), _T_313) @[Bitwise.scala 102:21] + node _T_315 = shr(_T_312, 4) @[Bitwise.scala 103:21] + node _T_316 = and(_T_315, _T_314) @[Bitwise.scala 103:31] + node _T_317 = bits(_T_312, 3, 0) @[Bitwise.scala 103:46] + node _T_318 = shl(_T_317, 4) @[Bitwise.scala 103:65] + node _T_319 = not(_T_314) @[Bitwise.scala 103:77] + node _T_320 = and(_T_318, _T_319) @[Bitwise.scala 103:75] + node _T_321 = or(_T_316, _T_320) @[Bitwise.scala 103:39] + node _T_322 = bits(_T_314, 5, 0) @[Bitwise.scala 102:28] + node _T_323 = shl(_T_322, 2) @[Bitwise.scala 102:47] + node _T_324 = xor(_T_314, _T_323) @[Bitwise.scala 102:21] + node _T_325 = shr(_T_321, 2) @[Bitwise.scala 103:21] + node _T_326 = and(_T_325, _T_324) @[Bitwise.scala 103:31] + node _T_327 = bits(_T_321, 5, 0) @[Bitwise.scala 103:46] + node _T_328 = shl(_T_327, 2) @[Bitwise.scala 103:65] + node _T_329 = not(_T_324) @[Bitwise.scala 103:77] + node _T_330 = and(_T_328, _T_329) @[Bitwise.scala 103:75] + node _T_331 = or(_T_326, _T_330) @[Bitwise.scala 103:39] + node _T_332 = bits(_T_324, 6, 0) @[Bitwise.scala 102:28] + node _T_333 = shl(_T_332, 1) @[Bitwise.scala 102:47] + node _T_334 = xor(_T_324, _T_333) @[Bitwise.scala 102:21] + node _T_335 = shr(_T_331, 1) @[Bitwise.scala 103:21] + node _T_336 = and(_T_335, _T_334) @[Bitwise.scala 103:31] + node _T_337 = bits(_T_331, 6, 0) @[Bitwise.scala 103:46] + node _T_338 = shl(_T_337, 1) @[Bitwise.scala 103:65] + node _T_339 = not(_T_334) @[Bitwise.scala 103:77] + node _T_340 = and(_T_338, _T_339) @[Bitwise.scala 103:75] + node _T_341 = or(_T_336, _T_340) @[Bitwise.scala 103:39] + wire _T_342 : UInt<8>[8] @[lsu_dccm_ctl.scala 155:62] + _T_342[0] <= _T_47 @[lsu_dccm_ctl.scala 155:62] + _T_342[1] <= _T_89 @[lsu_dccm_ctl.scala 155:62] + _T_342[2] <= _T_131 @[lsu_dccm_ctl.scala 155:62] + _T_342[3] <= _T_173 @[lsu_dccm_ctl.scala 155:62] + _T_342[4] <= _T_215 @[lsu_dccm_ctl.scala 155:62] + _T_342[5] <= _T_257 @[lsu_dccm_ctl.scala 155:62] + _T_342[6] <= _T_299 @[lsu_dccm_ctl.scala 155:62] + _T_342[7] <= _T_341 @[lsu_dccm_ctl.scala 155:62] + node _T_343 = cat(_T_342[6], _T_342[7]) @[Cat.scala 29:58] + node _T_344 = cat(_T_342[4], _T_342[5]) @[Cat.scala 29:58] + node _T_345 = cat(_T_344, _T_343) @[Cat.scala 29:58] + node _T_346 = cat(_T_342[2], _T_342[3]) @[Cat.scala 29:58] + node _T_347 = cat(_T_342[0], _T_342[1]) @[Cat.scala 29:58] + node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] + node _T_349 = cat(_T_348, _T_345) @[Cat.scala 29:58] + node _T_350 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47] + node _T_351 = xor(UInt<64>("h0ffffffffffffffff"), _T_350) @[Bitwise.scala 102:21] + node _T_352 = shr(_T_349, 32) @[Bitwise.scala 103:21] + node _T_353 = and(_T_352, _T_351) @[Bitwise.scala 103:31] + node _T_354 = bits(_T_349, 31, 0) @[Bitwise.scala 103:46] + node _T_355 = shl(_T_354, 32) @[Bitwise.scala 103:65] + node _T_356 = not(_T_351) @[Bitwise.scala 103:77] + node _T_357 = and(_T_355, _T_356) @[Bitwise.scala 103:75] + node _T_358 = or(_T_353, _T_357) @[Bitwise.scala 103:39] + node _T_359 = bits(_T_351, 47, 0) @[Bitwise.scala 102:28] + node _T_360 = shl(_T_359, 16) @[Bitwise.scala 102:47] + node _T_361 = xor(_T_351, _T_360) @[Bitwise.scala 102:21] + node _T_362 = shr(_T_358, 16) @[Bitwise.scala 103:21] + node _T_363 = and(_T_362, _T_361) @[Bitwise.scala 103:31] + node _T_364 = bits(_T_358, 47, 0) @[Bitwise.scala 103:46] + node _T_365 = shl(_T_364, 16) @[Bitwise.scala 103:65] + node _T_366 = not(_T_361) @[Bitwise.scala 103:77] + node _T_367 = and(_T_365, _T_366) @[Bitwise.scala 103:75] + node _T_368 = or(_T_363, _T_367) @[Bitwise.scala 103:39] + node _T_369 = bits(_T_361, 55, 0) @[Bitwise.scala 102:28] + node _T_370 = shl(_T_369, 8) @[Bitwise.scala 102:47] + node _T_371 = xor(_T_361, _T_370) @[Bitwise.scala 102:21] + node _T_372 = shr(_T_368, 8) @[Bitwise.scala 103:21] + node _T_373 = and(_T_372, _T_371) @[Bitwise.scala 103:31] + node _T_374 = bits(_T_368, 55, 0) @[Bitwise.scala 103:46] + node _T_375 = shl(_T_374, 8) @[Bitwise.scala 103:65] + node _T_376 = not(_T_371) @[Bitwise.scala 103:77] + node _T_377 = and(_T_375, _T_376) @[Bitwise.scala 103:75] + node _T_378 = or(_T_373, _T_377) @[Bitwise.scala 103:39] + node _T_379 = bits(_T_371, 59, 0) @[Bitwise.scala 102:28] + node _T_380 = shl(_T_379, 4) @[Bitwise.scala 102:47] + node _T_381 = xor(_T_371, _T_380) @[Bitwise.scala 102:21] + node _T_382 = shr(_T_378, 4) @[Bitwise.scala 103:21] + node _T_383 = and(_T_382, _T_381) @[Bitwise.scala 103:31] + node _T_384 = bits(_T_378, 59, 0) @[Bitwise.scala 103:46] + node _T_385 = shl(_T_384, 4) @[Bitwise.scala 103:65] + node _T_386 = not(_T_381) @[Bitwise.scala 103:77] + node _T_387 = and(_T_385, _T_386) @[Bitwise.scala 103:75] + node _T_388 = or(_T_383, _T_387) @[Bitwise.scala 103:39] + node _T_389 = bits(_T_381, 61, 0) @[Bitwise.scala 102:28] + node _T_390 = shl(_T_389, 2) @[Bitwise.scala 102:47] + node _T_391 = xor(_T_381, _T_390) @[Bitwise.scala 102:21] + node _T_392 = shr(_T_388, 2) @[Bitwise.scala 103:21] + node _T_393 = and(_T_392, _T_391) @[Bitwise.scala 103:31] + node _T_394 = bits(_T_388, 61, 0) @[Bitwise.scala 103:46] + node _T_395 = shl(_T_394, 2) @[Bitwise.scala 103:65] + node _T_396 = not(_T_391) @[Bitwise.scala 103:77] + node _T_397 = and(_T_395, _T_396) @[Bitwise.scala 103:75] + node _T_398 = or(_T_393, _T_397) @[Bitwise.scala 103:39] + node _T_399 = bits(_T_391, 62, 0) @[Bitwise.scala 102:28] + node _T_400 = shl(_T_399, 1) @[Bitwise.scala 102:47] + node _T_401 = xor(_T_391, _T_400) @[Bitwise.scala 102:21] + node _T_402 = shr(_T_398, 1) @[Bitwise.scala 103:21] + node _T_403 = and(_T_402, _T_401) @[Bitwise.scala 103:31] + node _T_404 = bits(_T_398, 62, 0) @[Bitwise.scala 103:46] + node _T_405 = shl(_T_404, 1) @[Bitwise.scala 103:65] + node _T_406 = not(_T_401) @[Bitwise.scala 103:77] + node _T_407 = and(_T_405, _T_406) @[Bitwise.scala 103:75] + node _T_408 = or(_T_403, _T_407) @[Bitwise.scala 103:39] + lsu_rdata_corr_m <= _T_408 @[lsu_dccm_ctl.scala 155:28] + node _T_409 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_410 = bits(_T_409, 0, 0) @[lsu_dccm_ctl.scala 156:134] + node _T_411 = bits(_T_410, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_412 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_413 = bits(_T_412, 7, 0) @[lsu_dccm_ctl.scala 156:196] + node _T_414 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_415 = bits(picm_rd_data_m, 7, 0) @[lsu_dccm_ctl.scala 156:253] + node _T_416 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_417 = mux(_T_416, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_418 = bits(dccm_rdata_m, 7, 0) @[lsu_dccm_ctl.scala 156:308] + node _T_419 = and(_T_417, _T_418) @[lsu_dccm_ctl.scala 156:294] + node _T_420 = mux(_T_414, _T_415, _T_419) @[lsu_dccm_ctl.scala 156:214] + node _T_421 = mux(_T_411, _T_413, _T_420) @[lsu_dccm_ctl.scala 156:78] + node _T_422 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_423 = xor(UInt<8>("h0ff"), _T_422) @[Bitwise.scala 102:21] + node _T_424 = shr(_T_421, 4) @[Bitwise.scala 103:21] + node _T_425 = and(_T_424, _T_423) @[Bitwise.scala 103:31] + node _T_426 = bits(_T_421, 3, 0) @[Bitwise.scala 103:46] + node _T_427 = shl(_T_426, 4) @[Bitwise.scala 103:65] + node _T_428 = not(_T_423) @[Bitwise.scala 103:77] + node _T_429 = and(_T_427, _T_428) @[Bitwise.scala 103:75] + node _T_430 = or(_T_425, _T_429) @[Bitwise.scala 103:39] + node _T_431 = bits(_T_423, 5, 0) @[Bitwise.scala 102:28] + node _T_432 = shl(_T_431, 2) @[Bitwise.scala 102:47] + node _T_433 = xor(_T_423, _T_432) @[Bitwise.scala 102:21] + node _T_434 = shr(_T_430, 2) @[Bitwise.scala 103:21] + node _T_435 = and(_T_434, _T_433) @[Bitwise.scala 103:31] + node _T_436 = bits(_T_430, 5, 0) @[Bitwise.scala 103:46] + node _T_437 = shl(_T_436, 2) @[Bitwise.scala 103:65] + node _T_438 = not(_T_433) @[Bitwise.scala 103:77] + node _T_439 = and(_T_437, _T_438) @[Bitwise.scala 103:75] + node _T_440 = or(_T_435, _T_439) @[Bitwise.scala 103:39] + node _T_441 = bits(_T_433, 6, 0) @[Bitwise.scala 102:28] + node _T_442 = shl(_T_441, 1) @[Bitwise.scala 102:47] + node _T_443 = xor(_T_433, _T_442) @[Bitwise.scala 102:21] + node _T_444 = shr(_T_440, 1) @[Bitwise.scala 103:21] + node _T_445 = and(_T_444, _T_443) @[Bitwise.scala 103:31] + node _T_446 = bits(_T_440, 6, 0) @[Bitwise.scala 103:46] + node _T_447 = shl(_T_446, 1) @[Bitwise.scala 103:65] + node _T_448 = not(_T_443) @[Bitwise.scala 103:77] + node _T_449 = and(_T_447, _T_448) @[Bitwise.scala 103:75] + node _T_450 = or(_T_445, _T_449) @[Bitwise.scala 103:39] + node _T_451 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_452 = bits(_T_451, 1, 1) @[lsu_dccm_ctl.scala 156:134] + node _T_453 = bits(_T_452, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_454 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_455 = bits(_T_454, 15, 8) @[lsu_dccm_ctl.scala 156:196] + node _T_456 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_457 = bits(picm_rd_data_m, 15, 8) @[lsu_dccm_ctl.scala 156:253] + node _T_458 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_459 = mux(_T_458, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_460 = bits(dccm_rdata_m, 15, 8) @[lsu_dccm_ctl.scala 156:308] + node _T_461 = and(_T_459, _T_460) @[lsu_dccm_ctl.scala 156:294] + node _T_462 = mux(_T_456, _T_457, _T_461) @[lsu_dccm_ctl.scala 156:214] + node _T_463 = mux(_T_453, _T_455, _T_462) @[lsu_dccm_ctl.scala 156:78] + node _T_464 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_465 = xor(UInt<8>("h0ff"), _T_464) @[Bitwise.scala 102:21] + node _T_466 = shr(_T_463, 4) @[Bitwise.scala 103:21] + node _T_467 = and(_T_466, _T_465) @[Bitwise.scala 103:31] + node _T_468 = bits(_T_463, 3, 0) @[Bitwise.scala 103:46] + node _T_469 = shl(_T_468, 4) @[Bitwise.scala 103:65] + node _T_470 = not(_T_465) @[Bitwise.scala 103:77] + node _T_471 = and(_T_469, _T_470) @[Bitwise.scala 103:75] + node _T_472 = or(_T_467, _T_471) @[Bitwise.scala 103:39] + node _T_473 = bits(_T_465, 5, 0) @[Bitwise.scala 102:28] + node _T_474 = shl(_T_473, 2) @[Bitwise.scala 102:47] + node _T_475 = xor(_T_465, _T_474) @[Bitwise.scala 102:21] + node _T_476 = shr(_T_472, 2) @[Bitwise.scala 103:21] + node _T_477 = and(_T_476, _T_475) @[Bitwise.scala 103:31] + node _T_478 = bits(_T_472, 5, 0) @[Bitwise.scala 103:46] + node _T_479 = shl(_T_478, 2) @[Bitwise.scala 103:65] + node _T_480 = not(_T_475) @[Bitwise.scala 103:77] + node _T_481 = and(_T_479, _T_480) @[Bitwise.scala 103:75] + node _T_482 = or(_T_477, _T_481) @[Bitwise.scala 103:39] + node _T_483 = bits(_T_475, 6, 0) @[Bitwise.scala 102:28] + node _T_484 = shl(_T_483, 1) @[Bitwise.scala 102:47] + node _T_485 = xor(_T_475, _T_484) @[Bitwise.scala 102:21] + node _T_486 = shr(_T_482, 1) @[Bitwise.scala 103:21] + node _T_487 = and(_T_486, _T_485) @[Bitwise.scala 103:31] + node _T_488 = bits(_T_482, 6, 0) @[Bitwise.scala 103:46] + node _T_489 = shl(_T_488, 1) @[Bitwise.scala 103:65] + node _T_490 = not(_T_485) @[Bitwise.scala 103:77] + node _T_491 = and(_T_489, _T_490) @[Bitwise.scala 103:75] + node _T_492 = or(_T_487, _T_491) @[Bitwise.scala 103:39] + node _T_493 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_494 = bits(_T_493, 2, 2) @[lsu_dccm_ctl.scala 156:134] + node _T_495 = bits(_T_494, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_496 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_497 = bits(_T_496, 23, 16) @[lsu_dccm_ctl.scala 156:196] + node _T_498 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_499 = bits(picm_rd_data_m, 23, 16) @[lsu_dccm_ctl.scala 156:253] + node _T_500 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_501 = mux(_T_500, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_502 = bits(dccm_rdata_m, 23, 16) @[lsu_dccm_ctl.scala 156:308] + node _T_503 = and(_T_501, _T_502) @[lsu_dccm_ctl.scala 156:294] + node _T_504 = mux(_T_498, _T_499, _T_503) @[lsu_dccm_ctl.scala 156:214] + node _T_505 = mux(_T_495, _T_497, _T_504) @[lsu_dccm_ctl.scala 156:78] + node _T_506 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_507 = xor(UInt<8>("h0ff"), _T_506) @[Bitwise.scala 102:21] + node _T_508 = shr(_T_505, 4) @[Bitwise.scala 103:21] + node _T_509 = and(_T_508, _T_507) @[Bitwise.scala 103:31] + node _T_510 = bits(_T_505, 3, 0) @[Bitwise.scala 103:46] + node _T_511 = shl(_T_510, 4) @[Bitwise.scala 103:65] + node _T_512 = not(_T_507) @[Bitwise.scala 103:77] + node _T_513 = and(_T_511, _T_512) @[Bitwise.scala 103:75] + node _T_514 = or(_T_509, _T_513) @[Bitwise.scala 103:39] + node _T_515 = bits(_T_507, 5, 0) @[Bitwise.scala 102:28] + node _T_516 = shl(_T_515, 2) @[Bitwise.scala 102:47] + node _T_517 = xor(_T_507, _T_516) @[Bitwise.scala 102:21] + node _T_518 = shr(_T_514, 2) @[Bitwise.scala 103:21] + node _T_519 = and(_T_518, _T_517) @[Bitwise.scala 103:31] + node _T_520 = bits(_T_514, 5, 0) @[Bitwise.scala 103:46] + node _T_521 = shl(_T_520, 2) @[Bitwise.scala 103:65] + node _T_522 = not(_T_517) @[Bitwise.scala 103:77] + node _T_523 = and(_T_521, _T_522) @[Bitwise.scala 103:75] + node _T_524 = or(_T_519, _T_523) @[Bitwise.scala 103:39] + node _T_525 = bits(_T_517, 6, 0) @[Bitwise.scala 102:28] + node _T_526 = shl(_T_525, 1) @[Bitwise.scala 102:47] + node _T_527 = xor(_T_517, _T_526) @[Bitwise.scala 102:21] + node _T_528 = shr(_T_524, 1) @[Bitwise.scala 103:21] + node _T_529 = and(_T_528, _T_527) @[Bitwise.scala 103:31] + node _T_530 = bits(_T_524, 6, 0) @[Bitwise.scala 103:46] + node _T_531 = shl(_T_530, 1) @[Bitwise.scala 103:65] + node _T_532 = not(_T_527) @[Bitwise.scala 103:77] + node _T_533 = and(_T_531, _T_532) @[Bitwise.scala 103:75] + node _T_534 = or(_T_529, _T_533) @[Bitwise.scala 103:39] + node _T_535 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_536 = bits(_T_535, 3, 3) @[lsu_dccm_ctl.scala 156:134] + node _T_537 = bits(_T_536, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_538 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_539 = bits(_T_538, 31, 24) @[lsu_dccm_ctl.scala 156:196] + node _T_540 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_541 = bits(picm_rd_data_m, 31, 24) @[lsu_dccm_ctl.scala 156:253] + node _T_542 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_543 = mux(_T_542, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_544 = bits(dccm_rdata_m, 31, 24) @[lsu_dccm_ctl.scala 156:308] + node _T_545 = and(_T_543, _T_544) @[lsu_dccm_ctl.scala 156:294] + node _T_546 = mux(_T_540, _T_541, _T_545) @[lsu_dccm_ctl.scala 156:214] + node _T_547 = mux(_T_537, _T_539, _T_546) @[lsu_dccm_ctl.scala 156:78] + node _T_548 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_549 = xor(UInt<8>("h0ff"), _T_548) @[Bitwise.scala 102:21] + node _T_550 = shr(_T_547, 4) @[Bitwise.scala 103:21] + node _T_551 = and(_T_550, _T_549) @[Bitwise.scala 103:31] + node _T_552 = bits(_T_547, 3, 0) @[Bitwise.scala 103:46] + node _T_553 = shl(_T_552, 4) @[Bitwise.scala 103:65] + node _T_554 = not(_T_549) @[Bitwise.scala 103:77] + node _T_555 = and(_T_553, _T_554) @[Bitwise.scala 103:75] + node _T_556 = or(_T_551, _T_555) @[Bitwise.scala 103:39] + node _T_557 = bits(_T_549, 5, 0) @[Bitwise.scala 102:28] + node _T_558 = shl(_T_557, 2) @[Bitwise.scala 102:47] + node _T_559 = xor(_T_549, _T_558) @[Bitwise.scala 102:21] + node _T_560 = shr(_T_556, 2) @[Bitwise.scala 103:21] + node _T_561 = and(_T_560, _T_559) @[Bitwise.scala 103:31] + node _T_562 = bits(_T_556, 5, 0) @[Bitwise.scala 103:46] + node _T_563 = shl(_T_562, 2) @[Bitwise.scala 103:65] + node _T_564 = not(_T_559) @[Bitwise.scala 103:77] + node _T_565 = and(_T_563, _T_564) @[Bitwise.scala 103:75] + node _T_566 = or(_T_561, _T_565) @[Bitwise.scala 103:39] + node _T_567 = bits(_T_559, 6, 0) @[Bitwise.scala 102:28] + node _T_568 = shl(_T_567, 1) @[Bitwise.scala 102:47] + node _T_569 = xor(_T_559, _T_568) @[Bitwise.scala 102:21] + node _T_570 = shr(_T_566, 1) @[Bitwise.scala 103:21] + node _T_571 = and(_T_570, _T_569) @[Bitwise.scala 103:31] + node _T_572 = bits(_T_566, 6, 0) @[Bitwise.scala 103:46] + node _T_573 = shl(_T_572, 1) @[Bitwise.scala 103:65] + node _T_574 = not(_T_569) @[Bitwise.scala 103:77] + node _T_575 = and(_T_573, _T_574) @[Bitwise.scala 103:75] + node _T_576 = or(_T_571, _T_575) @[Bitwise.scala 103:39] + node _T_577 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_578 = bits(_T_577, 4, 4) @[lsu_dccm_ctl.scala 156:134] + node _T_579 = bits(_T_578, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_580 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_581 = bits(_T_580, 39, 32) @[lsu_dccm_ctl.scala 156:196] + node _T_582 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_583 = bits(picm_rd_data_m, 39, 32) @[lsu_dccm_ctl.scala 156:253] + node _T_584 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_585 = mux(_T_584, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_586 = bits(dccm_rdata_m, 39, 32) @[lsu_dccm_ctl.scala 156:308] + node _T_587 = and(_T_585, _T_586) @[lsu_dccm_ctl.scala 156:294] + node _T_588 = mux(_T_582, _T_583, _T_587) @[lsu_dccm_ctl.scala 156:214] + node _T_589 = mux(_T_579, _T_581, _T_588) @[lsu_dccm_ctl.scala 156:78] + node _T_590 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_591 = xor(UInt<8>("h0ff"), _T_590) @[Bitwise.scala 102:21] + node _T_592 = shr(_T_589, 4) @[Bitwise.scala 103:21] + node _T_593 = and(_T_592, _T_591) @[Bitwise.scala 103:31] + node _T_594 = bits(_T_589, 3, 0) @[Bitwise.scala 103:46] + node _T_595 = shl(_T_594, 4) @[Bitwise.scala 103:65] + node _T_596 = not(_T_591) @[Bitwise.scala 103:77] + node _T_597 = and(_T_595, _T_596) @[Bitwise.scala 103:75] + node _T_598 = or(_T_593, _T_597) @[Bitwise.scala 103:39] + node _T_599 = bits(_T_591, 5, 0) @[Bitwise.scala 102:28] + node _T_600 = shl(_T_599, 2) @[Bitwise.scala 102:47] + node _T_601 = xor(_T_591, _T_600) @[Bitwise.scala 102:21] + node _T_602 = shr(_T_598, 2) @[Bitwise.scala 103:21] + node _T_603 = and(_T_602, _T_601) @[Bitwise.scala 103:31] + node _T_604 = bits(_T_598, 5, 0) @[Bitwise.scala 103:46] + node _T_605 = shl(_T_604, 2) @[Bitwise.scala 103:65] + node _T_606 = not(_T_601) @[Bitwise.scala 103:77] + node _T_607 = and(_T_605, _T_606) @[Bitwise.scala 103:75] + node _T_608 = or(_T_603, _T_607) @[Bitwise.scala 103:39] + node _T_609 = bits(_T_601, 6, 0) @[Bitwise.scala 102:28] + node _T_610 = shl(_T_609, 1) @[Bitwise.scala 102:47] + node _T_611 = xor(_T_601, _T_610) @[Bitwise.scala 102:21] + node _T_612 = shr(_T_608, 1) @[Bitwise.scala 103:21] + node _T_613 = and(_T_612, _T_611) @[Bitwise.scala 103:31] + node _T_614 = bits(_T_608, 6, 0) @[Bitwise.scala 103:46] + node _T_615 = shl(_T_614, 1) @[Bitwise.scala 103:65] + node _T_616 = not(_T_611) @[Bitwise.scala 103:77] + node _T_617 = and(_T_615, _T_616) @[Bitwise.scala 103:75] + node _T_618 = or(_T_613, _T_617) @[Bitwise.scala 103:39] + node _T_619 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_620 = bits(_T_619, 5, 5) @[lsu_dccm_ctl.scala 156:134] + node _T_621 = bits(_T_620, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_622 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_623 = bits(_T_622, 47, 40) @[lsu_dccm_ctl.scala 156:196] + node _T_624 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_625 = bits(picm_rd_data_m, 47, 40) @[lsu_dccm_ctl.scala 156:253] + node _T_626 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(dccm_rdata_m, 47, 40) @[lsu_dccm_ctl.scala 156:308] + node _T_629 = and(_T_627, _T_628) @[lsu_dccm_ctl.scala 156:294] + node _T_630 = mux(_T_624, _T_625, _T_629) @[lsu_dccm_ctl.scala 156:214] + node _T_631 = mux(_T_621, _T_623, _T_630) @[lsu_dccm_ctl.scala 156:78] + node _T_632 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_633 = xor(UInt<8>("h0ff"), _T_632) @[Bitwise.scala 102:21] + node _T_634 = shr(_T_631, 4) @[Bitwise.scala 103:21] + node _T_635 = and(_T_634, _T_633) @[Bitwise.scala 103:31] + node _T_636 = bits(_T_631, 3, 0) @[Bitwise.scala 103:46] + node _T_637 = shl(_T_636, 4) @[Bitwise.scala 103:65] + node _T_638 = not(_T_633) @[Bitwise.scala 103:77] + node _T_639 = and(_T_637, _T_638) @[Bitwise.scala 103:75] + node _T_640 = or(_T_635, _T_639) @[Bitwise.scala 103:39] + node _T_641 = bits(_T_633, 5, 0) @[Bitwise.scala 102:28] + node _T_642 = shl(_T_641, 2) @[Bitwise.scala 102:47] + node _T_643 = xor(_T_633, _T_642) @[Bitwise.scala 102:21] + node _T_644 = shr(_T_640, 2) @[Bitwise.scala 103:21] + node _T_645 = and(_T_644, _T_643) @[Bitwise.scala 103:31] + node _T_646 = bits(_T_640, 5, 0) @[Bitwise.scala 103:46] + node _T_647 = shl(_T_646, 2) @[Bitwise.scala 103:65] + node _T_648 = not(_T_643) @[Bitwise.scala 103:77] + node _T_649 = and(_T_647, _T_648) @[Bitwise.scala 103:75] + node _T_650 = or(_T_645, _T_649) @[Bitwise.scala 103:39] + node _T_651 = bits(_T_643, 6, 0) @[Bitwise.scala 102:28] + node _T_652 = shl(_T_651, 1) @[Bitwise.scala 102:47] + node _T_653 = xor(_T_643, _T_652) @[Bitwise.scala 102:21] + node _T_654 = shr(_T_650, 1) @[Bitwise.scala 103:21] + node _T_655 = and(_T_654, _T_653) @[Bitwise.scala 103:31] + node _T_656 = bits(_T_650, 6, 0) @[Bitwise.scala 103:46] + node _T_657 = shl(_T_656, 1) @[Bitwise.scala 103:65] + node _T_658 = not(_T_653) @[Bitwise.scala 103:77] + node _T_659 = and(_T_657, _T_658) @[Bitwise.scala 103:75] + node _T_660 = or(_T_655, _T_659) @[Bitwise.scala 103:39] + node _T_661 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_662 = bits(_T_661, 6, 6) @[lsu_dccm_ctl.scala 156:134] + node _T_663 = bits(_T_662, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_664 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_665 = bits(_T_664, 55, 48) @[lsu_dccm_ctl.scala 156:196] + node _T_666 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_667 = bits(picm_rd_data_m, 55, 48) @[lsu_dccm_ctl.scala 156:253] + node _T_668 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_669 = mux(_T_668, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_670 = bits(dccm_rdata_m, 55, 48) @[lsu_dccm_ctl.scala 156:308] + node _T_671 = and(_T_669, _T_670) @[lsu_dccm_ctl.scala 156:294] + node _T_672 = mux(_T_666, _T_667, _T_671) @[lsu_dccm_ctl.scala 156:214] + node _T_673 = mux(_T_663, _T_665, _T_672) @[lsu_dccm_ctl.scala 156:78] + node _T_674 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_675 = xor(UInt<8>("h0ff"), _T_674) @[Bitwise.scala 102:21] + node _T_676 = shr(_T_673, 4) @[Bitwise.scala 103:21] + node _T_677 = and(_T_676, _T_675) @[Bitwise.scala 103:31] + node _T_678 = bits(_T_673, 3, 0) @[Bitwise.scala 103:46] + node _T_679 = shl(_T_678, 4) @[Bitwise.scala 103:65] + node _T_680 = not(_T_675) @[Bitwise.scala 103:77] + node _T_681 = and(_T_679, _T_680) @[Bitwise.scala 103:75] + node _T_682 = or(_T_677, _T_681) @[Bitwise.scala 103:39] + node _T_683 = bits(_T_675, 5, 0) @[Bitwise.scala 102:28] + node _T_684 = shl(_T_683, 2) @[Bitwise.scala 102:47] + node _T_685 = xor(_T_675, _T_684) @[Bitwise.scala 102:21] + node _T_686 = shr(_T_682, 2) @[Bitwise.scala 103:21] + node _T_687 = and(_T_686, _T_685) @[Bitwise.scala 103:31] + node _T_688 = bits(_T_682, 5, 0) @[Bitwise.scala 103:46] + node _T_689 = shl(_T_688, 2) @[Bitwise.scala 103:65] + node _T_690 = not(_T_685) @[Bitwise.scala 103:77] + node _T_691 = and(_T_689, _T_690) @[Bitwise.scala 103:75] + node _T_692 = or(_T_687, _T_691) @[Bitwise.scala 103:39] + node _T_693 = bits(_T_685, 6, 0) @[Bitwise.scala 102:28] + node _T_694 = shl(_T_693, 1) @[Bitwise.scala 102:47] + node _T_695 = xor(_T_685, _T_694) @[Bitwise.scala 102:21] + node _T_696 = shr(_T_692, 1) @[Bitwise.scala 103:21] + node _T_697 = and(_T_696, _T_695) @[Bitwise.scala 103:31] + node _T_698 = bits(_T_692, 6, 0) @[Bitwise.scala 103:46] + node _T_699 = shl(_T_698, 1) @[Bitwise.scala 103:65] + node _T_700 = not(_T_695) @[Bitwise.scala 103:77] + node _T_701 = and(_T_699, _T_700) @[Bitwise.scala 103:75] + node _T_702 = or(_T_697, _T_701) @[Bitwise.scala 103:39] + node _T_703 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_704 = bits(_T_703, 7, 7) @[lsu_dccm_ctl.scala 156:134] + node _T_705 = bits(_T_704, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_706 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_707 = bits(_T_706, 63, 56) @[lsu_dccm_ctl.scala 156:196] + node _T_708 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_709 = bits(picm_rd_data_m, 63, 56) @[lsu_dccm_ctl.scala 156:253] + node _T_710 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(dccm_rdata_m, 63, 56) @[lsu_dccm_ctl.scala 156:308] + node _T_713 = and(_T_711, _T_712) @[lsu_dccm_ctl.scala 156:294] + node _T_714 = mux(_T_708, _T_709, _T_713) @[lsu_dccm_ctl.scala 156:214] + node _T_715 = mux(_T_705, _T_707, _T_714) @[lsu_dccm_ctl.scala 156:78] + node _T_716 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_717 = xor(UInt<8>("h0ff"), _T_716) @[Bitwise.scala 102:21] + node _T_718 = shr(_T_715, 4) @[Bitwise.scala 103:21] + node _T_719 = and(_T_718, _T_717) @[Bitwise.scala 103:31] + node _T_720 = bits(_T_715, 3, 0) @[Bitwise.scala 103:46] + node _T_721 = shl(_T_720, 4) @[Bitwise.scala 103:65] + node _T_722 = not(_T_717) @[Bitwise.scala 103:77] + node _T_723 = and(_T_721, _T_722) @[Bitwise.scala 103:75] + node _T_724 = or(_T_719, _T_723) @[Bitwise.scala 103:39] + node _T_725 = bits(_T_717, 5, 0) @[Bitwise.scala 102:28] + node _T_726 = shl(_T_725, 2) @[Bitwise.scala 102:47] + node _T_727 = xor(_T_717, _T_726) @[Bitwise.scala 102:21] + node _T_728 = shr(_T_724, 2) @[Bitwise.scala 103:21] + node _T_729 = and(_T_728, _T_727) @[Bitwise.scala 103:31] + node _T_730 = bits(_T_724, 5, 0) @[Bitwise.scala 103:46] + node _T_731 = shl(_T_730, 2) @[Bitwise.scala 103:65] + node _T_732 = not(_T_727) @[Bitwise.scala 103:77] + node _T_733 = and(_T_731, _T_732) @[Bitwise.scala 103:75] + node _T_734 = or(_T_729, _T_733) @[Bitwise.scala 103:39] + node _T_735 = bits(_T_727, 6, 0) @[Bitwise.scala 102:28] + node _T_736 = shl(_T_735, 1) @[Bitwise.scala 102:47] + node _T_737 = xor(_T_727, _T_736) @[Bitwise.scala 102:21] + node _T_738 = shr(_T_734, 1) @[Bitwise.scala 103:21] + node _T_739 = and(_T_738, _T_737) @[Bitwise.scala 103:31] + node _T_740 = bits(_T_734, 6, 0) @[Bitwise.scala 103:46] + node _T_741 = shl(_T_740, 1) @[Bitwise.scala 103:65] + node _T_742 = not(_T_737) @[Bitwise.scala 103:77] + node _T_743 = and(_T_741, _T_742) @[Bitwise.scala 103:75] + node _T_744 = or(_T_739, _T_743) @[Bitwise.scala 103:39] + wire _T_745 : UInt<8>[8] @[lsu_dccm_ctl.scala 156:62] + _T_745[0] <= _T_450 @[lsu_dccm_ctl.scala 156:62] + _T_745[1] <= _T_492 @[lsu_dccm_ctl.scala 156:62] + _T_745[2] <= _T_534 @[lsu_dccm_ctl.scala 156:62] + _T_745[3] <= _T_576 @[lsu_dccm_ctl.scala 156:62] + _T_745[4] <= _T_618 @[lsu_dccm_ctl.scala 156:62] + _T_745[5] <= _T_660 @[lsu_dccm_ctl.scala 156:62] + _T_745[6] <= _T_702 @[lsu_dccm_ctl.scala 156:62] + _T_745[7] <= _T_744 @[lsu_dccm_ctl.scala 156:62] + node _T_746 = cat(_T_745[6], _T_745[7]) @[Cat.scala 29:58] + node _T_747 = cat(_T_745[4], _T_745[5]) @[Cat.scala 29:58] + node _T_748 = cat(_T_747, _T_746) @[Cat.scala 29:58] + node _T_749 = cat(_T_745[2], _T_745[3]) @[Cat.scala 29:58] + node _T_750 = cat(_T_745[0], _T_745[1]) @[Cat.scala 29:58] + node _T_751 = cat(_T_750, _T_749) @[Cat.scala 29:58] + node _T_752 = cat(_T_751, _T_748) @[Cat.scala 29:58] + node _T_753 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47] + node _T_754 = xor(UInt<64>("h0ffffffffffffffff"), _T_753) @[Bitwise.scala 102:21] + node _T_755 = shr(_T_752, 32) @[Bitwise.scala 103:21] + node _T_756 = and(_T_755, _T_754) @[Bitwise.scala 103:31] + node _T_757 = bits(_T_752, 31, 0) @[Bitwise.scala 103:46] + node _T_758 = shl(_T_757, 32) @[Bitwise.scala 103:65] + node _T_759 = not(_T_754) @[Bitwise.scala 103:77] + node _T_760 = and(_T_758, _T_759) @[Bitwise.scala 103:75] + node _T_761 = or(_T_756, _T_760) @[Bitwise.scala 103:39] + node _T_762 = bits(_T_754, 47, 0) @[Bitwise.scala 102:28] + node _T_763 = shl(_T_762, 16) @[Bitwise.scala 102:47] + node _T_764 = xor(_T_754, _T_763) @[Bitwise.scala 102:21] + node _T_765 = shr(_T_761, 16) @[Bitwise.scala 103:21] + node _T_766 = and(_T_765, _T_764) @[Bitwise.scala 103:31] + node _T_767 = bits(_T_761, 47, 0) @[Bitwise.scala 103:46] + node _T_768 = shl(_T_767, 16) @[Bitwise.scala 103:65] + node _T_769 = not(_T_764) @[Bitwise.scala 103:77] + node _T_770 = and(_T_768, _T_769) @[Bitwise.scala 103:75] + node _T_771 = or(_T_766, _T_770) @[Bitwise.scala 103:39] + node _T_772 = bits(_T_764, 55, 0) @[Bitwise.scala 102:28] + node _T_773 = shl(_T_772, 8) @[Bitwise.scala 102:47] + node _T_774 = xor(_T_764, _T_773) @[Bitwise.scala 102:21] + node _T_775 = shr(_T_771, 8) @[Bitwise.scala 103:21] + node _T_776 = and(_T_775, _T_774) @[Bitwise.scala 103:31] + node _T_777 = bits(_T_771, 55, 0) @[Bitwise.scala 103:46] + node _T_778 = shl(_T_777, 8) @[Bitwise.scala 103:65] + node _T_779 = not(_T_774) @[Bitwise.scala 103:77] + node _T_780 = and(_T_778, _T_779) @[Bitwise.scala 103:75] + node _T_781 = or(_T_776, _T_780) @[Bitwise.scala 103:39] + node _T_782 = bits(_T_774, 59, 0) @[Bitwise.scala 102:28] + node _T_783 = shl(_T_782, 4) @[Bitwise.scala 102:47] + node _T_784 = xor(_T_774, _T_783) @[Bitwise.scala 102:21] + node _T_785 = shr(_T_781, 4) @[Bitwise.scala 103:21] + node _T_786 = and(_T_785, _T_784) @[Bitwise.scala 103:31] + node _T_787 = bits(_T_781, 59, 0) @[Bitwise.scala 103:46] + node _T_788 = shl(_T_787, 4) @[Bitwise.scala 103:65] + node _T_789 = not(_T_784) @[Bitwise.scala 103:77] + node _T_790 = and(_T_788, _T_789) @[Bitwise.scala 103:75] + node _T_791 = or(_T_786, _T_790) @[Bitwise.scala 103:39] + node _T_792 = bits(_T_784, 61, 0) @[Bitwise.scala 102:28] + node _T_793 = shl(_T_792, 2) @[Bitwise.scala 102:47] + node _T_794 = xor(_T_784, _T_793) @[Bitwise.scala 102:21] + node _T_795 = shr(_T_791, 2) @[Bitwise.scala 103:21] + node _T_796 = and(_T_795, _T_794) @[Bitwise.scala 103:31] + node _T_797 = bits(_T_791, 61, 0) @[Bitwise.scala 103:46] + node _T_798 = shl(_T_797, 2) @[Bitwise.scala 103:65] + node _T_799 = not(_T_794) @[Bitwise.scala 103:77] + node _T_800 = and(_T_798, _T_799) @[Bitwise.scala 103:75] + node _T_801 = or(_T_796, _T_800) @[Bitwise.scala 103:39] + node _T_802 = bits(_T_794, 62, 0) @[Bitwise.scala 102:28] + node _T_803 = shl(_T_802, 1) @[Bitwise.scala 102:47] + node _T_804 = xor(_T_794, _T_803) @[Bitwise.scala 102:21] + node _T_805 = shr(_T_801, 1) @[Bitwise.scala 103:21] + node _T_806 = and(_T_805, _T_804) @[Bitwise.scala 103:31] + node _T_807 = bits(_T_801, 62, 0) @[Bitwise.scala 103:46] + node _T_808 = shl(_T_807, 1) @[Bitwise.scala 103:65] + node _T_809 = not(_T_804) @[Bitwise.scala 103:77] + node _T_810 = and(_T_808, _T_809) @[Bitwise.scala 103:75] + node _T_811 = or(_T_806, _T_810) @[Bitwise.scala 103:39] + lsu_rdata_m <= _T_811 @[lsu_dccm_ctl.scala 156:28] + node _T_812 = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.load) @[lsu_dccm_ctl.scala 157:78] + node _T_813 = or(io.addr_in_pic_m, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 157:123] + node _T_814 = and(_T_812, _T_813) @[lsu_dccm_ctl.scala 157:103] + node _T_815 = or(_T_814, io.clk_override) @[lsu_dccm_ctl.scala 157:145] + node _T_816 = bits(_T_815, 0, 0) @[lib.scala 8:44] + node _T_817 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr of rvclkhdr_4 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_816 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_818 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_816 : @[Reg.scala 28:19] + _T_818 <= lsu_ld_data_corr_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.lsu_ld_data_corr_r <= _T_818 @[lsu_dccm_ctl.scala 157:28] + node _T_819 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 158:63] + node _T_820 = mul(UInt<4>("h08"), _T_819) @[lsu_dccm_ctl.scala 158:49] + node _T_821 = dshr(lsu_rdata_m, _T_820) @[lsu_dccm_ctl.scala 158:43] + io.lsu_ld_data_m <= _T_821 @[lsu_dccm_ctl.scala 158:28] + node _T_822 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 159:68] + node _T_823 = mul(UInt<4>("h08"), _T_822) @[lsu_dccm_ctl.scala 159:54] + node _T_824 = dshr(lsu_rdata_corr_m, _T_823) @[lsu_dccm_ctl.scala 159:48] + lsu_ld_data_corr_m <= _T_824 @[lsu_dccm_ctl.scala 159:28] + node _T_825 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 163:44] + node _T_826 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 163:77] + node _T_827 = eq(_T_825, _T_826) @[lsu_dccm_ctl.scala 163:60] + node _T_828 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 163:117] + node _T_829 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 163:150] + node _T_830 = eq(_T_828, _T_829) @[lsu_dccm_ctl.scala 163:133] + node _T_831 = or(_T_827, _T_830) @[lsu_dccm_ctl.scala 163:101] + node _T_832 = and(_T_831, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 163:175] + node _T_833 = and(_T_832, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 163:196] + node _T_834 = and(_T_833, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 163:222] + node _T_835 = and(_T_834, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 163:246] + node _T_836 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 164:21] + node _T_837 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 164:54] + node _T_838 = eq(_T_836, _T_837) @[lsu_dccm_ctl.scala 164:37] + node _T_839 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 164:94] + node _T_840 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 164:127] + node _T_841 = eq(_T_839, _T_840) @[lsu_dccm_ctl.scala 164:110] + node _T_842 = or(_T_838, _T_841) @[lsu_dccm_ctl.scala 164:78] + node _T_843 = and(_T_842, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 164:152] + node _T_844 = and(_T_843, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 164:173] + node _T_845 = and(_T_844, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 164:199] + node _T_846 = and(_T_845, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 164:223] + node kill_ecc_corr_lo_r = or(_T_835, _T_846) @[lsu_dccm_ctl.scala 163:267] + node _T_847 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 166:44] + node _T_848 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 166:77] + node _T_849 = eq(_T_847, _T_848) @[lsu_dccm_ctl.scala 166:60] + node _T_850 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 166:117] + node _T_851 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 166:150] + node _T_852 = eq(_T_850, _T_851) @[lsu_dccm_ctl.scala 166:133] + node _T_853 = or(_T_849, _T_852) @[lsu_dccm_ctl.scala 166:101] + node _T_854 = and(_T_853, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 166:175] + node _T_855 = and(_T_854, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 166:196] + node _T_856 = and(_T_855, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 166:222] + node _T_857 = and(_T_856, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 166:246] + node _T_858 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 167:21] + node _T_859 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 167:54] + node _T_860 = eq(_T_858, _T_859) @[lsu_dccm_ctl.scala 167:37] + node _T_861 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 167:94] + node _T_862 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 167:127] + node _T_863 = eq(_T_861, _T_862) @[lsu_dccm_ctl.scala 167:110] + node _T_864 = or(_T_860, _T_863) @[lsu_dccm_ctl.scala 167:78] + node _T_865 = and(_T_864, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 167:152] + node _T_866 = and(_T_865, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 167:173] + node _T_867 = and(_T_866, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 167:199] + node _T_868 = and(_T_867, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 167:223] + node kill_ecc_corr_hi_r = or(_T_857, _T_868) @[lsu_dccm_ctl.scala 166:267] + node _T_869 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_lo_r) @[lsu_dccm_ctl.scala 169:60] + node _T_870 = eq(io.lsu_raw_fwd_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 169:89] + node ld_single_ecc_error_lo_r = and(_T_869, _T_870) @[lsu_dccm_ctl.scala 169:87] + node _T_871 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 170:60] + node _T_872 = eq(io.lsu_raw_fwd_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 170:89] + node ld_single_ecc_error_hi_r = and(_T_871, _T_872) @[lsu_dccm_ctl.scala 170:87] + node _T_873 = or(ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 171:63] + node _T_874 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 171:93] + node _T_875 = and(_T_873, _T_874) @[lsu_dccm_ctl.scala 171:91] + io.ld_single_ecc_error_r <= _T_875 @[lsu_dccm_ctl.scala 171:34] + node _T_876 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 172:81] + node _T_877 = and(ld_single_ecc_error_lo_r, _T_876) @[lsu_dccm_ctl.scala 172:62] + node _T_878 = eq(kill_ecc_corr_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 172:108] + node ld_single_ecc_error_lo_r_ns = and(_T_877, _T_878) @[lsu_dccm_ctl.scala 172:106] + node _T_879 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 173:81] + node _T_880 = and(ld_single_ecc_error_hi_r, _T_879) @[lsu_dccm_ctl.scala 173:62] + node _T_881 = eq(kill_ecc_corr_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 173:108] + node ld_single_ecc_error_hi_r_ns = and(_T_880, _T_881) @[lsu_dccm_ctl.scala 173:106] + node _T_882 = or(io.lsu_pkt_d.bits.word, io.lsu_pkt_d.bits.dword) @[lsu_dccm_ctl.scala 175:125] + node _T_883 = eq(_T_882, UInt<1>("h00")) @[lsu_dccm_ctl.scala 175:100] + node _T_884 = bits(io.lsu_addr_d, 1, 0) @[lsu_dccm_ctl.scala 175:168] + node _T_885 = neq(_T_884, UInt<2>("h00")) @[lsu_dccm_ctl.scala 175:174] + node _T_886 = or(_T_883, _T_885) @[lsu_dccm_ctl.scala 175:152] + node _T_887 = and(io.lsu_pkt_d.bits.store, _T_886) @[lsu_dccm_ctl.scala 175:97] + node _T_888 = or(io.lsu_pkt_d.bits.load, _T_887) @[lsu_dccm_ctl.scala 175:70] + node _T_889 = and(io.lsu_pkt_d.valid, _T_888) @[lsu_dccm_ctl.scala 175:44] + node lsu_dccm_rden_d = and(_T_889, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 175:191] + node _T_890 = or(ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff) @[lsu_dccm_ctl.scala 178:63] + node _T_891 = eq(lsu_double_ecc_error_r_ff, UInt<1>("h00")) @[lsu_dccm_ctl.scala 178:96] + node _T_892 = and(_T_890, _T_891) @[lsu_dccm_ctl.scala 178:94] + io.ld_single_ecc_error_r_ff <= _T_892 @[lsu_dccm_ctl.scala 178:31] + node _T_893 = or(lsu_dccm_rden_d, io.dma_dccm_wen) @[lsu_dccm_ctl.scala 179:75] + node _T_894 = or(_T_893, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 179:93] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[lsu_dccm_ctl.scala 179:57] + node _T_896 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 180:44] + node _T_897 = bits(io.lsu_addr_d, 3, 2) @[lsu_dccm_ctl.scala 180:112] + node _T_898 = eq(_T_896, _T_897) @[lsu_dccm_ctl.scala 180:95] + node _T_899 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 181:25] + node _T_900 = bits(io.end_addr_d, 3, 2) @[lsu_dccm_ctl.scala 181:93] + node _T_901 = eq(_T_899, _T_900) @[lsu_dccm_ctl.scala 181:76] + node _T_902 = or(_T_898, _T_901) @[lsu_dccm_ctl.scala 180:171] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[lsu_dccm_ctl.scala 180:24] + node _T_904 = and(lsu_dccm_rden_d, _T_903) @[lsu_dccm_ctl.scala 180:22] + node _T_905 = or(_T_895, _T_904) @[lsu_dccm_ctl.scala 179:124] + node _T_906 = and(io.stbuf_reqvld_any, _T_905) @[lsu_dccm_ctl.scala 179:54] + io.lsu_stbuf_commit_any <= _T_906 @[lsu_dccm_ctl.scala 179:31] + node _T_907 = or(io.dma_dccm_wen, io.lsu_stbuf_commit_any) @[lsu_dccm_ctl.scala 185:41] + node _T_908 = or(_T_907, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 185:67] + io.dccm.wren <= _T_908 @[lsu_dccm_ctl.scala 185:22] + node _T_909 = and(lsu_dccm_rden_d, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 186:41] + io.dccm.rden <= _T_909 @[lsu_dccm_ctl.scala 186:22] + node _T_910 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 188:57] + node _T_911 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 189:36] + node _T_912 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 189:62] + node _T_913 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 189:97] + node _T_914 = mux(_T_911, _T_912, _T_913) @[lsu_dccm_ctl.scala 189:8] + node _T_915 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 190:25] + node _T_916 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 190:45] + node _T_917 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 190:78] + node _T_918 = mux(_T_915, _T_916, _T_917) @[lsu_dccm_ctl.scala 190:8] + node _T_919 = mux(_T_910, _T_914, _T_918) @[lsu_dccm_ctl.scala 188:28] + io.dccm.wr_addr_lo <= _T_919 @[lsu_dccm_ctl.scala 188:22] + node _T_920 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 192:57] + node _T_921 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 193:36] + node _T_922 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 193:63] + node _T_923 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 193:99] + node _T_924 = mux(_T_921, _T_922, _T_923) @[lsu_dccm_ctl.scala 193:8] + node _T_925 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 194:25] + node _T_926 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 194:46] + node _T_927 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 194:79] + node _T_928 = mux(_T_925, _T_926, _T_927) @[lsu_dccm_ctl.scala 194:8] + node _T_929 = mux(_T_920, _T_924, _T_928) @[lsu_dccm_ctl.scala 192:28] + io.dccm.wr_addr_hi <= _T_929 @[lsu_dccm_ctl.scala 192:22] + node _T_930 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 196:38] + io.dccm.rd_addr_lo <= _T_930 @[lsu_dccm_ctl.scala 196:22] + node _T_931 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 197:38] + io.dccm.rd_addr_hi <= _T_931 @[lsu_dccm_ctl.scala 197:22] + node _T_932 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 199:57] + node _T_933 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 200:36] + node _T_934 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 200:70] + node _T_935 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 200:110] + node _T_936 = cat(_T_934, _T_935) @[Cat.scala 29:58] + node _T_937 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 201:34] + node _T_938 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 201:74] + node _T_939 = cat(_T_937, _T_938) @[Cat.scala 29:58] + node _T_940 = mux(_T_933, _T_936, _T_939) @[lsu_dccm_ctl.scala 200:8] + node _T_941 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 202:25] + node _T_942 = bits(io.dma_dccm_wdata_ecc_lo, 6, 0) @[lsu_dccm_ctl.scala 202:60] + node _T_943 = bits(io.dma_dccm_wdata_lo, 31, 0) @[lsu_dccm_ctl.scala 202:101] + node _T_944 = cat(_T_942, _T_943) @[Cat.scala 29:58] + node _T_945 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 203:27] + node _T_946 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 203:65] + node _T_947 = cat(_T_945, _T_946) @[Cat.scala 29:58] + node _T_948 = mux(_T_941, _T_944, _T_947) @[lsu_dccm_ctl.scala 202:8] + node _T_949 = mux(_T_932, _T_940, _T_948) @[lsu_dccm_ctl.scala 199:28] + io.dccm.wr_data_lo <= _T_949 @[lsu_dccm_ctl.scala 199:22] + node _T_950 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 205:57] + node _T_951 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 206:36] + node _T_952 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 206:71] + node _T_953 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 206:111] + node _T_954 = cat(_T_952, _T_953) @[Cat.scala 29:58] + node _T_955 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 207:34] + node _T_956 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 207:74] + node _T_957 = cat(_T_955, _T_956) @[Cat.scala 29:58] + node _T_958 = mux(_T_951, _T_954, _T_957) @[lsu_dccm_ctl.scala 206:8] + node _T_959 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 208:25] + node _T_960 = bits(io.dma_dccm_wdata_ecc_hi, 6, 0) @[lsu_dccm_ctl.scala 208:61] + node _T_961 = bits(io.dma_dccm_wdata_hi, 31, 0) @[lsu_dccm_ctl.scala 208:102] + node _T_962 = cat(_T_960, _T_961) @[Cat.scala 29:58] + node _T_963 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 209:27] + node _T_964 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 209:65] + node _T_965 = cat(_T_963, _T_964) @[Cat.scala 29:58] + node _T_966 = mux(_T_959, _T_962, _T_965) @[lsu_dccm_ctl.scala 208:8] + node _T_967 = mux(_T_950, _T_958, _T_966) @[lsu_dccm_ctl.scala 205:28] + io.dccm.wr_data_hi <= _T_967 @[lsu_dccm_ctl.scala 205:22] + node _T_968 = bits(io.lsu_pkt_m.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_969 = mux(_T_968, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_970 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[Bitwise.scala 72:15] + node _T_971 = mux(_T_970, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_972 = and(_T_971, UInt<4>("h01")) @[lsu_dccm_ctl.scala 212:94] + node _T_973 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_974 = mux(_T_973, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_975 = and(_T_974, UInt<4>("h03")) @[lsu_dccm_ctl.scala 213:38] + node _T_976 = or(_T_972, _T_975) @[lsu_dccm_ctl.scala 212:107] + node _T_977 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_978 = mux(_T_977, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_979 = and(_T_978, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 214:38] + node _T_980 = or(_T_976, _T_979) @[lsu_dccm_ctl.scala 213:51] + node store_byteen_m = and(_T_969, _T_980) @[lsu_dccm_ctl.scala 212:58] + node _T_981 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_982 = mux(_T_981, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_983 = bits(io.lsu_pkt_r.bits.by, 0, 0) @[Bitwise.scala 72:15] + node _T_984 = mux(_T_983, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_985 = and(_T_984, UInt<4>("h01")) @[lsu_dccm_ctl.scala 216:94] + node _T_986 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_987 = mux(_T_986, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_988 = and(_T_987, UInt<4>("h03")) @[lsu_dccm_ctl.scala 217:38] + node _T_989 = or(_T_985, _T_988) @[lsu_dccm_ctl.scala 216:107] + node _T_990 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_991 = mux(_T_990, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_992 = and(_T_991, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 218:38] + node _T_993 = or(_T_989, _T_992) @[lsu_dccm_ctl.scala 217:51] + node store_byteen_r = and(_T_982, _T_993) @[lsu_dccm_ctl.scala 216:58] + wire store_byteen_ext_m : UInt<8> + store_byteen_ext_m <= UInt<1>("h00") + node _T_994 = bits(store_byteen_m, 3, 0) @[lsu_dccm_ctl.scala 220:39] + node _T_995 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 220:61] + node _T_996 = dshl(_T_994, _T_995) @[lsu_dccm_ctl.scala 220:45] + store_byteen_ext_m <= _T_996 @[lsu_dccm_ctl.scala 220:22] + wire store_byteen_ext_r : UInt<8> + store_byteen_ext_r <= UInt<1>("h00") + node _T_997 = bits(store_byteen_r, 3, 0) @[lsu_dccm_ctl.scala 222:39] + node _T_998 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 222:61] + node _T_999 = dshl(_T_997, _T_998) @[lsu_dccm_ctl.scala 222:45] + store_byteen_ext_r <= _T_999 @[lsu_dccm_ctl.scala 222:22] + node _T_1000 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 225:51] + node _T_1001 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 225:84] + node _T_1002 = eq(_T_1000, _T_1001) @[lsu_dccm_ctl.scala 225:67] + node dccm_wr_bypass_d_m_lo = and(_T_1002, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 225:101] + node _T_1003 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 226:51] + node _T_1004 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 226:84] + node _T_1005 = eq(_T_1003, _T_1004) @[lsu_dccm_ctl.scala 226:67] + node dccm_wr_bypass_d_m_hi = and(_T_1005, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 226:101] + node _T_1006 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 228:51] + node _T_1007 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 228:84] + node _T_1008 = eq(_T_1006, _T_1007) @[lsu_dccm_ctl.scala 228:67] + node dccm_wr_bypass_d_r_lo = and(_T_1008, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 228:101] + node _T_1009 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 229:51] + node _T_1010 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 229:84] + node _T_1011 = eq(_T_1009, _T_1010) @[lsu_dccm_ctl.scala 229:67] + node dccm_wr_bypass_d_r_hi = and(_T_1011, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 229:101] + wire dccm_wr_bypass_d_m_hi_Q : UInt<1> + dccm_wr_bypass_d_m_hi_Q <= UInt<1>("h00") + wire dccm_wr_bypass_d_m_lo_Q : UInt<1> + dccm_wr_bypass_d_m_lo_Q <= UInt<1>("h00") + wire dccm_wren_Q : UInt<1> + dccm_wren_Q <= UInt<1>("h00") + wire dccm_wr_data_Q : UInt<32> + dccm_wr_data_Q <= UInt<32>("h00") + wire store_data_pre_r : UInt<64> + store_data_pre_r <= UInt<64>("h00") + wire store_data_pre_hi_r : UInt<32> + store_data_pre_hi_r <= UInt<32>("h00") + wire store_data_pre_lo_r : UInt<32> + store_data_pre_lo_r <= UInt<32>("h00") + wire store_data_pre_m : UInt<64> + store_data_pre_m <= UInt<64>("h00") + wire store_data_hi_m : UInt<32> + store_data_hi_m <= UInt<32>("h00") + wire store_data_lo_m : UInt<32> + store_data_lo_m <= UInt<32>("h00") + node _T_1012 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1013 = bits(io.store_data_m, 31, 0) @[lsu_dccm_ctl.scala 258:64] + node _T_1014 = cat(_T_1012, _T_1013) @[Cat.scala 29:58] + node _T_1015 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 258:92] + node _T_1016 = mul(UInt<4>("h08"), _T_1015) @[lsu_dccm_ctl.scala 258:78] + node _T_1017 = dshl(_T_1014, _T_1016) @[lsu_dccm_ctl.scala 258:72] + store_data_pre_m <= _T_1017 @[lsu_dccm_ctl.scala 258:29] + node _T_1018 = bits(store_data_pre_m, 63, 32) @[lsu_dccm_ctl.scala 259:48] + store_data_hi_m <= _T_1018 @[lsu_dccm_ctl.scala 259:29] + node _T_1019 = bits(store_data_pre_m, 31, 0) @[lsu_dccm_ctl.scala 260:48] + store_data_lo_m <= _T_1019 @[lsu_dccm_ctl.scala 260:29] + node _T_1020 = bits(store_byteen_ext_m, 0, 0) @[lsu_dccm_ctl.scala 261:139] + node _T_1021 = bits(_T_1020, 0, 0) @[lsu_dccm_ctl.scala 261:143] + node _T_1022 = bits(store_data_lo_m, 7, 0) @[lsu_dccm_ctl.scala 261:167] + node _T_1023 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211] + node _T_1024 = bits(_T_1023, 0, 0) @[lsu_dccm_ctl.scala 261:237] + node _T_1025 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 261:262] + node _T_1026 = bits(io.sec_data_lo_m, 7, 0) @[lsu_dccm_ctl.scala 261:292] + node _T_1027 = mux(_T_1024, _T_1025, _T_1026) @[lsu_dccm_ctl.scala 261:185] + node _T_1028 = mux(_T_1021, _T_1022, _T_1027) @[lsu_dccm_ctl.scala 261:120] + node _T_1029 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1030 = xor(UInt<8>("h0ff"), _T_1029) @[Bitwise.scala 102:21] + node _T_1031 = shr(_T_1028, 4) @[Bitwise.scala 103:21] + node _T_1032 = and(_T_1031, _T_1030) @[Bitwise.scala 103:31] + node _T_1033 = bits(_T_1028, 3, 0) @[Bitwise.scala 103:46] + node _T_1034 = shl(_T_1033, 4) @[Bitwise.scala 103:65] + node _T_1035 = not(_T_1030) @[Bitwise.scala 103:77] + node _T_1036 = and(_T_1034, _T_1035) @[Bitwise.scala 103:75] + node _T_1037 = or(_T_1032, _T_1036) @[Bitwise.scala 103:39] + node _T_1038 = bits(_T_1030, 5, 0) @[Bitwise.scala 102:28] + node _T_1039 = shl(_T_1038, 2) @[Bitwise.scala 102:47] + node _T_1040 = xor(_T_1030, _T_1039) @[Bitwise.scala 102:21] + node _T_1041 = shr(_T_1037, 2) @[Bitwise.scala 103:21] + node _T_1042 = and(_T_1041, _T_1040) @[Bitwise.scala 103:31] + node _T_1043 = bits(_T_1037, 5, 0) @[Bitwise.scala 103:46] + node _T_1044 = shl(_T_1043, 2) @[Bitwise.scala 103:65] + node _T_1045 = not(_T_1040) @[Bitwise.scala 103:77] + node _T_1046 = and(_T_1044, _T_1045) @[Bitwise.scala 103:75] + node _T_1047 = or(_T_1042, _T_1046) @[Bitwise.scala 103:39] + node _T_1048 = bits(_T_1040, 6, 0) @[Bitwise.scala 102:28] + node _T_1049 = shl(_T_1048, 1) @[Bitwise.scala 102:47] + node _T_1050 = xor(_T_1040, _T_1049) @[Bitwise.scala 102:21] + node _T_1051 = shr(_T_1047, 1) @[Bitwise.scala 103:21] + node _T_1052 = and(_T_1051, _T_1050) @[Bitwise.scala 103:31] + node _T_1053 = bits(_T_1047, 6, 0) @[Bitwise.scala 103:46] + node _T_1054 = shl(_T_1053, 1) @[Bitwise.scala 103:65] + node _T_1055 = not(_T_1050) @[Bitwise.scala 103:77] + node _T_1056 = and(_T_1054, _T_1055) @[Bitwise.scala 103:75] + node _T_1057 = or(_T_1052, _T_1056) @[Bitwise.scala 103:39] + node _T_1058 = bits(store_byteen_ext_m, 1, 1) @[lsu_dccm_ctl.scala 261:139] + node _T_1059 = bits(_T_1058, 0, 0) @[lsu_dccm_ctl.scala 261:143] + node _T_1060 = bits(store_data_lo_m, 15, 8) @[lsu_dccm_ctl.scala 261:167] + node _T_1061 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211] + node _T_1062 = bits(_T_1061, 0, 0) @[lsu_dccm_ctl.scala 261:237] + node _T_1063 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 261:262] + node _T_1064 = bits(io.sec_data_lo_m, 15, 8) @[lsu_dccm_ctl.scala 261:292] + node _T_1065 = mux(_T_1062, _T_1063, _T_1064) @[lsu_dccm_ctl.scala 261:185] + node _T_1066 = mux(_T_1059, _T_1060, _T_1065) @[lsu_dccm_ctl.scala 261:120] + node _T_1067 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1068 = xor(UInt<8>("h0ff"), _T_1067) @[Bitwise.scala 102:21] + node _T_1069 = shr(_T_1066, 4) @[Bitwise.scala 103:21] + node _T_1070 = and(_T_1069, _T_1068) @[Bitwise.scala 103:31] + node _T_1071 = bits(_T_1066, 3, 0) @[Bitwise.scala 103:46] + node _T_1072 = shl(_T_1071, 4) @[Bitwise.scala 103:65] + node _T_1073 = not(_T_1068) @[Bitwise.scala 103:77] + node _T_1074 = and(_T_1072, _T_1073) @[Bitwise.scala 103:75] + node _T_1075 = or(_T_1070, _T_1074) @[Bitwise.scala 103:39] + node _T_1076 = bits(_T_1068, 5, 0) @[Bitwise.scala 102:28] + node _T_1077 = shl(_T_1076, 2) @[Bitwise.scala 102:47] + node _T_1078 = xor(_T_1068, _T_1077) @[Bitwise.scala 102:21] + node _T_1079 = shr(_T_1075, 2) @[Bitwise.scala 103:21] + node _T_1080 = and(_T_1079, _T_1078) @[Bitwise.scala 103:31] + node _T_1081 = bits(_T_1075, 5, 0) @[Bitwise.scala 103:46] + node _T_1082 = shl(_T_1081, 2) @[Bitwise.scala 103:65] + node _T_1083 = not(_T_1078) @[Bitwise.scala 103:77] + node _T_1084 = and(_T_1082, _T_1083) @[Bitwise.scala 103:75] + node _T_1085 = or(_T_1080, _T_1084) @[Bitwise.scala 103:39] + node _T_1086 = bits(_T_1078, 6, 0) @[Bitwise.scala 102:28] + node _T_1087 = shl(_T_1086, 1) @[Bitwise.scala 102:47] + node _T_1088 = xor(_T_1078, _T_1087) @[Bitwise.scala 102:21] + node _T_1089 = shr(_T_1085, 1) @[Bitwise.scala 103:21] + node _T_1090 = and(_T_1089, _T_1088) @[Bitwise.scala 103:31] + node _T_1091 = bits(_T_1085, 6, 0) @[Bitwise.scala 103:46] + node _T_1092 = shl(_T_1091, 1) @[Bitwise.scala 103:65] + node _T_1093 = not(_T_1088) @[Bitwise.scala 103:77] + node _T_1094 = and(_T_1092, _T_1093) @[Bitwise.scala 103:75] + node _T_1095 = or(_T_1090, _T_1094) @[Bitwise.scala 103:39] + node _T_1096 = bits(store_byteen_ext_m, 2, 2) @[lsu_dccm_ctl.scala 261:139] + node _T_1097 = bits(_T_1096, 0, 0) @[lsu_dccm_ctl.scala 261:143] + node _T_1098 = bits(store_data_lo_m, 23, 16) @[lsu_dccm_ctl.scala 261:167] + node _T_1099 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211] + node _T_1100 = bits(_T_1099, 0, 0) @[lsu_dccm_ctl.scala 261:237] + node _T_1101 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 261:262] + node _T_1102 = bits(io.sec_data_lo_m, 23, 16) @[lsu_dccm_ctl.scala 261:292] + node _T_1103 = mux(_T_1100, _T_1101, _T_1102) @[lsu_dccm_ctl.scala 261:185] + node _T_1104 = mux(_T_1097, _T_1098, _T_1103) @[lsu_dccm_ctl.scala 261:120] + node _T_1105 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1106 = xor(UInt<8>("h0ff"), _T_1105) @[Bitwise.scala 102:21] + node _T_1107 = shr(_T_1104, 4) @[Bitwise.scala 103:21] + node _T_1108 = and(_T_1107, _T_1106) @[Bitwise.scala 103:31] + node _T_1109 = bits(_T_1104, 3, 0) @[Bitwise.scala 103:46] + node _T_1110 = shl(_T_1109, 4) @[Bitwise.scala 103:65] + node _T_1111 = not(_T_1106) @[Bitwise.scala 103:77] + node _T_1112 = and(_T_1110, _T_1111) @[Bitwise.scala 103:75] + node _T_1113 = or(_T_1108, _T_1112) @[Bitwise.scala 103:39] + node _T_1114 = bits(_T_1106, 5, 0) @[Bitwise.scala 102:28] + node _T_1115 = shl(_T_1114, 2) @[Bitwise.scala 102:47] + node _T_1116 = xor(_T_1106, _T_1115) @[Bitwise.scala 102:21] + node _T_1117 = shr(_T_1113, 2) @[Bitwise.scala 103:21] + node _T_1118 = and(_T_1117, _T_1116) @[Bitwise.scala 103:31] + node _T_1119 = bits(_T_1113, 5, 0) @[Bitwise.scala 103:46] + node _T_1120 = shl(_T_1119, 2) @[Bitwise.scala 103:65] + node _T_1121 = not(_T_1116) @[Bitwise.scala 103:77] + node _T_1122 = and(_T_1120, _T_1121) @[Bitwise.scala 103:75] + node _T_1123 = or(_T_1118, _T_1122) @[Bitwise.scala 103:39] + node _T_1124 = bits(_T_1116, 6, 0) @[Bitwise.scala 102:28] + node _T_1125 = shl(_T_1124, 1) @[Bitwise.scala 102:47] + node _T_1126 = xor(_T_1116, _T_1125) @[Bitwise.scala 102:21] + node _T_1127 = shr(_T_1123, 1) @[Bitwise.scala 103:21] + node _T_1128 = and(_T_1127, _T_1126) @[Bitwise.scala 103:31] + node _T_1129 = bits(_T_1123, 6, 0) @[Bitwise.scala 103:46] + node _T_1130 = shl(_T_1129, 1) @[Bitwise.scala 103:65] + node _T_1131 = not(_T_1126) @[Bitwise.scala 103:77] + node _T_1132 = and(_T_1130, _T_1131) @[Bitwise.scala 103:75] + node _T_1133 = or(_T_1128, _T_1132) @[Bitwise.scala 103:39] + node _T_1134 = bits(store_byteen_ext_m, 3, 3) @[lsu_dccm_ctl.scala 261:139] + node _T_1135 = bits(_T_1134, 0, 0) @[lsu_dccm_ctl.scala 261:143] + node _T_1136 = bits(store_data_lo_m, 31, 24) @[lsu_dccm_ctl.scala 261:167] + node _T_1137 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211] + node _T_1138 = bits(_T_1137, 0, 0) @[lsu_dccm_ctl.scala 261:237] + node _T_1139 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 261:262] + node _T_1140 = bits(io.sec_data_lo_m, 31, 24) @[lsu_dccm_ctl.scala 261:292] + node _T_1141 = mux(_T_1138, _T_1139, _T_1140) @[lsu_dccm_ctl.scala 261:185] + node _T_1142 = mux(_T_1135, _T_1136, _T_1141) @[lsu_dccm_ctl.scala 261:120] + node _T_1143 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1144 = xor(UInt<8>("h0ff"), _T_1143) @[Bitwise.scala 102:21] + node _T_1145 = shr(_T_1142, 4) @[Bitwise.scala 103:21] + node _T_1146 = and(_T_1145, _T_1144) @[Bitwise.scala 103:31] + node _T_1147 = bits(_T_1142, 3, 0) @[Bitwise.scala 103:46] + node _T_1148 = shl(_T_1147, 4) @[Bitwise.scala 103:65] + node _T_1149 = not(_T_1144) @[Bitwise.scala 103:77] + node _T_1150 = and(_T_1148, _T_1149) @[Bitwise.scala 103:75] + node _T_1151 = or(_T_1146, _T_1150) @[Bitwise.scala 103:39] + node _T_1152 = bits(_T_1144, 5, 0) @[Bitwise.scala 102:28] + node _T_1153 = shl(_T_1152, 2) @[Bitwise.scala 102:47] + node _T_1154 = xor(_T_1144, _T_1153) @[Bitwise.scala 102:21] + node _T_1155 = shr(_T_1151, 2) @[Bitwise.scala 103:21] + node _T_1156 = and(_T_1155, _T_1154) @[Bitwise.scala 103:31] + node _T_1157 = bits(_T_1151, 5, 0) @[Bitwise.scala 103:46] + node _T_1158 = shl(_T_1157, 2) @[Bitwise.scala 103:65] + node _T_1159 = not(_T_1154) @[Bitwise.scala 103:77] + node _T_1160 = and(_T_1158, _T_1159) @[Bitwise.scala 103:75] + node _T_1161 = or(_T_1156, _T_1160) @[Bitwise.scala 103:39] + node _T_1162 = bits(_T_1154, 6, 0) @[Bitwise.scala 102:28] + node _T_1163 = shl(_T_1162, 1) @[Bitwise.scala 102:47] + node _T_1164 = xor(_T_1154, _T_1163) @[Bitwise.scala 102:21] + node _T_1165 = shr(_T_1161, 1) @[Bitwise.scala 103:21] + node _T_1166 = and(_T_1165, _T_1164) @[Bitwise.scala 103:31] + node _T_1167 = bits(_T_1161, 6, 0) @[Bitwise.scala 103:46] + node _T_1168 = shl(_T_1167, 1) @[Bitwise.scala 103:65] + node _T_1169 = not(_T_1164) @[Bitwise.scala 103:77] + node _T_1170 = and(_T_1168, _T_1169) @[Bitwise.scala 103:75] + node _T_1171 = or(_T_1166, _T_1170) @[Bitwise.scala 103:39] + wire _T_1172 : UInt<8>[4] @[lsu_dccm_ctl.scala 261:104] + _T_1172[0] <= _T_1057 @[lsu_dccm_ctl.scala 261:104] + _T_1172[1] <= _T_1095 @[lsu_dccm_ctl.scala 261:104] + _T_1172[2] <= _T_1133 @[lsu_dccm_ctl.scala 261:104] + _T_1172[3] <= _T_1171 @[lsu_dccm_ctl.scala 261:104] + node _T_1173 = cat(_T_1172[2], _T_1172[3]) @[Cat.scala 29:58] + node _T_1174 = cat(_T_1172[0], _T_1172[1]) @[Cat.scala 29:58] + node _T_1175 = cat(_T_1174, _T_1173) @[Cat.scala 29:58] + node _T_1176 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1177 = xor(UInt<32>("h0ffffffff"), _T_1176) @[Bitwise.scala 102:21] + node _T_1178 = shr(_T_1175, 16) @[Bitwise.scala 103:21] + node _T_1179 = and(_T_1178, _T_1177) @[Bitwise.scala 103:31] + node _T_1180 = bits(_T_1175, 15, 0) @[Bitwise.scala 103:46] + node _T_1181 = shl(_T_1180, 16) @[Bitwise.scala 103:65] + node _T_1182 = not(_T_1177) @[Bitwise.scala 103:77] + node _T_1183 = and(_T_1181, _T_1182) @[Bitwise.scala 103:75] + node _T_1184 = or(_T_1179, _T_1183) @[Bitwise.scala 103:39] + node _T_1185 = bits(_T_1177, 23, 0) @[Bitwise.scala 102:28] + node _T_1186 = shl(_T_1185, 8) @[Bitwise.scala 102:47] + node _T_1187 = xor(_T_1177, _T_1186) @[Bitwise.scala 102:21] + node _T_1188 = shr(_T_1184, 8) @[Bitwise.scala 103:21] + node _T_1189 = and(_T_1188, _T_1187) @[Bitwise.scala 103:31] + node _T_1190 = bits(_T_1184, 23, 0) @[Bitwise.scala 103:46] + node _T_1191 = shl(_T_1190, 8) @[Bitwise.scala 103:65] + node _T_1192 = not(_T_1187) @[Bitwise.scala 103:77] + node _T_1193 = and(_T_1191, _T_1192) @[Bitwise.scala 103:75] + node _T_1194 = or(_T_1189, _T_1193) @[Bitwise.scala 103:39] + node _T_1195 = bits(_T_1187, 27, 0) @[Bitwise.scala 102:28] + node _T_1196 = shl(_T_1195, 4) @[Bitwise.scala 102:47] + node _T_1197 = xor(_T_1187, _T_1196) @[Bitwise.scala 102:21] + node _T_1198 = shr(_T_1194, 4) @[Bitwise.scala 103:21] + node _T_1199 = and(_T_1198, _T_1197) @[Bitwise.scala 103:31] + node _T_1200 = bits(_T_1194, 27, 0) @[Bitwise.scala 103:46] + node _T_1201 = shl(_T_1200, 4) @[Bitwise.scala 103:65] + node _T_1202 = not(_T_1197) @[Bitwise.scala 103:77] + node _T_1203 = and(_T_1201, _T_1202) @[Bitwise.scala 103:75] + node _T_1204 = or(_T_1199, _T_1203) @[Bitwise.scala 103:39] + node _T_1205 = bits(_T_1197, 29, 0) @[Bitwise.scala 102:28] + node _T_1206 = shl(_T_1205, 2) @[Bitwise.scala 102:47] + node _T_1207 = xor(_T_1197, _T_1206) @[Bitwise.scala 102:21] + node _T_1208 = shr(_T_1204, 2) @[Bitwise.scala 103:21] + node _T_1209 = and(_T_1208, _T_1207) @[Bitwise.scala 103:31] + node _T_1210 = bits(_T_1204, 29, 0) @[Bitwise.scala 103:46] + node _T_1211 = shl(_T_1210, 2) @[Bitwise.scala 103:65] + node _T_1212 = not(_T_1207) @[Bitwise.scala 103:77] + node _T_1213 = and(_T_1211, _T_1212) @[Bitwise.scala 103:75] + node _T_1214 = or(_T_1209, _T_1213) @[Bitwise.scala 103:39] + node _T_1215 = bits(_T_1207, 30, 0) @[Bitwise.scala 102:28] + node _T_1216 = shl(_T_1215, 1) @[Bitwise.scala 102:47] + node _T_1217 = xor(_T_1207, _T_1216) @[Bitwise.scala 102:21] + node _T_1218 = shr(_T_1214, 1) @[Bitwise.scala 103:21] + node _T_1219 = and(_T_1218, _T_1217) @[Bitwise.scala 103:31] + node _T_1220 = bits(_T_1214, 30, 0) @[Bitwise.scala 103:46] + node _T_1221 = shl(_T_1220, 1) @[Bitwise.scala 103:65] + node _T_1222 = not(_T_1217) @[Bitwise.scala 103:77] + node _T_1223 = and(_T_1221, _T_1222) @[Bitwise.scala 103:75] + node _T_1224 = or(_T_1219, _T_1223) @[Bitwise.scala 103:39] + reg _T_1225 : UInt, io.lsu_store_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 261:72] + _T_1225 <= _T_1224 @[lsu_dccm_ctl.scala 261:72] + io.store_data_lo_r <= _T_1225 @[lsu_dccm_ctl.scala 261:29] + node _T_1226 = bits(store_byteen_ext_m, 4, 4) @[lsu_dccm_ctl.scala 262:105] + node _T_1227 = bits(_T_1226, 0, 0) @[lsu_dccm_ctl.scala 262:111] + node _T_1228 = bits(store_data_hi_m, 7, 0) @[lsu_dccm_ctl.scala 262:133] + node _T_1229 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177] + node _T_1230 = bits(_T_1229, 0, 0) @[lsu_dccm_ctl.scala 262:203] + node _T_1231 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 262:228] + node _T_1232 = bits(io.sec_data_hi_m, 7, 0) @[lsu_dccm_ctl.scala 262:258] + node _T_1233 = mux(_T_1230, _T_1231, _T_1232) @[lsu_dccm_ctl.scala 262:151] + node _T_1234 = mux(_T_1227, _T_1228, _T_1233) @[lsu_dccm_ctl.scala 262:86] + node _T_1235 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1236 = xor(UInt<8>("h0ff"), _T_1235) @[Bitwise.scala 102:21] + node _T_1237 = shr(_T_1234, 4) @[Bitwise.scala 103:21] + node _T_1238 = and(_T_1237, _T_1236) @[Bitwise.scala 103:31] + node _T_1239 = bits(_T_1234, 3, 0) @[Bitwise.scala 103:46] + node _T_1240 = shl(_T_1239, 4) @[Bitwise.scala 103:65] + node _T_1241 = not(_T_1236) @[Bitwise.scala 103:77] + node _T_1242 = and(_T_1240, _T_1241) @[Bitwise.scala 103:75] + node _T_1243 = or(_T_1238, _T_1242) @[Bitwise.scala 103:39] + node _T_1244 = bits(_T_1236, 5, 0) @[Bitwise.scala 102:28] + node _T_1245 = shl(_T_1244, 2) @[Bitwise.scala 102:47] + node _T_1246 = xor(_T_1236, _T_1245) @[Bitwise.scala 102:21] + node _T_1247 = shr(_T_1243, 2) @[Bitwise.scala 103:21] + node _T_1248 = and(_T_1247, _T_1246) @[Bitwise.scala 103:31] + node _T_1249 = bits(_T_1243, 5, 0) @[Bitwise.scala 103:46] + node _T_1250 = shl(_T_1249, 2) @[Bitwise.scala 103:65] + node _T_1251 = not(_T_1246) @[Bitwise.scala 103:77] + node _T_1252 = and(_T_1250, _T_1251) @[Bitwise.scala 103:75] + node _T_1253 = or(_T_1248, _T_1252) @[Bitwise.scala 103:39] + node _T_1254 = bits(_T_1246, 6, 0) @[Bitwise.scala 102:28] + node _T_1255 = shl(_T_1254, 1) @[Bitwise.scala 102:47] + node _T_1256 = xor(_T_1246, _T_1255) @[Bitwise.scala 102:21] + node _T_1257 = shr(_T_1253, 1) @[Bitwise.scala 103:21] + node _T_1258 = and(_T_1257, _T_1256) @[Bitwise.scala 103:31] + node _T_1259 = bits(_T_1253, 6, 0) @[Bitwise.scala 103:46] + node _T_1260 = shl(_T_1259, 1) @[Bitwise.scala 103:65] + node _T_1261 = not(_T_1256) @[Bitwise.scala 103:77] + node _T_1262 = and(_T_1260, _T_1261) @[Bitwise.scala 103:75] + node _T_1263 = or(_T_1258, _T_1262) @[Bitwise.scala 103:39] + node _T_1264 = bits(store_byteen_ext_m, 5, 5) @[lsu_dccm_ctl.scala 262:105] + node _T_1265 = bits(_T_1264, 0, 0) @[lsu_dccm_ctl.scala 262:111] + node _T_1266 = bits(store_data_hi_m, 15, 8) @[lsu_dccm_ctl.scala 262:133] + node _T_1267 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177] + node _T_1268 = bits(_T_1267, 0, 0) @[lsu_dccm_ctl.scala 262:203] + node _T_1269 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 262:228] + node _T_1270 = bits(io.sec_data_hi_m, 15, 8) @[lsu_dccm_ctl.scala 262:258] + node _T_1271 = mux(_T_1268, _T_1269, _T_1270) @[lsu_dccm_ctl.scala 262:151] + node _T_1272 = mux(_T_1265, _T_1266, _T_1271) @[lsu_dccm_ctl.scala 262:86] + node _T_1273 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1274 = xor(UInt<8>("h0ff"), _T_1273) @[Bitwise.scala 102:21] + node _T_1275 = shr(_T_1272, 4) @[Bitwise.scala 103:21] + node _T_1276 = and(_T_1275, _T_1274) @[Bitwise.scala 103:31] + node _T_1277 = bits(_T_1272, 3, 0) @[Bitwise.scala 103:46] + node _T_1278 = shl(_T_1277, 4) @[Bitwise.scala 103:65] + node _T_1279 = not(_T_1274) @[Bitwise.scala 103:77] + node _T_1280 = and(_T_1278, _T_1279) @[Bitwise.scala 103:75] + node _T_1281 = or(_T_1276, _T_1280) @[Bitwise.scala 103:39] + node _T_1282 = bits(_T_1274, 5, 0) @[Bitwise.scala 102:28] + node _T_1283 = shl(_T_1282, 2) @[Bitwise.scala 102:47] + node _T_1284 = xor(_T_1274, _T_1283) @[Bitwise.scala 102:21] + node _T_1285 = shr(_T_1281, 2) @[Bitwise.scala 103:21] + node _T_1286 = and(_T_1285, _T_1284) @[Bitwise.scala 103:31] + node _T_1287 = bits(_T_1281, 5, 0) @[Bitwise.scala 103:46] + node _T_1288 = shl(_T_1287, 2) @[Bitwise.scala 103:65] + node _T_1289 = not(_T_1284) @[Bitwise.scala 103:77] + node _T_1290 = and(_T_1288, _T_1289) @[Bitwise.scala 103:75] + node _T_1291 = or(_T_1286, _T_1290) @[Bitwise.scala 103:39] + node _T_1292 = bits(_T_1284, 6, 0) @[Bitwise.scala 102:28] + node _T_1293 = shl(_T_1292, 1) @[Bitwise.scala 102:47] + node _T_1294 = xor(_T_1284, _T_1293) @[Bitwise.scala 102:21] + node _T_1295 = shr(_T_1291, 1) @[Bitwise.scala 103:21] + node _T_1296 = and(_T_1295, _T_1294) @[Bitwise.scala 103:31] + node _T_1297 = bits(_T_1291, 6, 0) @[Bitwise.scala 103:46] + node _T_1298 = shl(_T_1297, 1) @[Bitwise.scala 103:65] + node _T_1299 = not(_T_1294) @[Bitwise.scala 103:77] + node _T_1300 = and(_T_1298, _T_1299) @[Bitwise.scala 103:75] + node _T_1301 = or(_T_1296, _T_1300) @[Bitwise.scala 103:39] + node _T_1302 = bits(store_byteen_ext_m, 6, 6) @[lsu_dccm_ctl.scala 262:105] + node _T_1303 = bits(_T_1302, 0, 0) @[lsu_dccm_ctl.scala 262:111] + node _T_1304 = bits(store_data_hi_m, 23, 16) @[lsu_dccm_ctl.scala 262:133] + node _T_1305 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177] + node _T_1306 = bits(_T_1305, 0, 0) @[lsu_dccm_ctl.scala 262:203] + node _T_1307 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 262:228] + node _T_1308 = bits(io.sec_data_hi_m, 23, 16) @[lsu_dccm_ctl.scala 262:258] + node _T_1309 = mux(_T_1306, _T_1307, _T_1308) @[lsu_dccm_ctl.scala 262:151] + node _T_1310 = mux(_T_1303, _T_1304, _T_1309) @[lsu_dccm_ctl.scala 262:86] + node _T_1311 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1312 = xor(UInt<8>("h0ff"), _T_1311) @[Bitwise.scala 102:21] + node _T_1313 = shr(_T_1310, 4) @[Bitwise.scala 103:21] + node _T_1314 = and(_T_1313, _T_1312) @[Bitwise.scala 103:31] + node _T_1315 = bits(_T_1310, 3, 0) @[Bitwise.scala 103:46] + node _T_1316 = shl(_T_1315, 4) @[Bitwise.scala 103:65] + node _T_1317 = not(_T_1312) @[Bitwise.scala 103:77] + node _T_1318 = and(_T_1316, _T_1317) @[Bitwise.scala 103:75] + node _T_1319 = or(_T_1314, _T_1318) @[Bitwise.scala 103:39] + node _T_1320 = bits(_T_1312, 5, 0) @[Bitwise.scala 102:28] + node _T_1321 = shl(_T_1320, 2) @[Bitwise.scala 102:47] + node _T_1322 = xor(_T_1312, _T_1321) @[Bitwise.scala 102:21] + node _T_1323 = shr(_T_1319, 2) @[Bitwise.scala 103:21] + node _T_1324 = and(_T_1323, _T_1322) @[Bitwise.scala 103:31] + node _T_1325 = bits(_T_1319, 5, 0) @[Bitwise.scala 103:46] + node _T_1326 = shl(_T_1325, 2) @[Bitwise.scala 103:65] + node _T_1327 = not(_T_1322) @[Bitwise.scala 103:77] + node _T_1328 = and(_T_1326, _T_1327) @[Bitwise.scala 103:75] + node _T_1329 = or(_T_1324, _T_1328) @[Bitwise.scala 103:39] + node _T_1330 = bits(_T_1322, 6, 0) @[Bitwise.scala 102:28] + node _T_1331 = shl(_T_1330, 1) @[Bitwise.scala 102:47] + node _T_1332 = xor(_T_1322, _T_1331) @[Bitwise.scala 102:21] + node _T_1333 = shr(_T_1329, 1) @[Bitwise.scala 103:21] + node _T_1334 = and(_T_1333, _T_1332) @[Bitwise.scala 103:31] + node _T_1335 = bits(_T_1329, 6, 0) @[Bitwise.scala 103:46] + node _T_1336 = shl(_T_1335, 1) @[Bitwise.scala 103:65] + node _T_1337 = not(_T_1332) @[Bitwise.scala 103:77] + node _T_1338 = and(_T_1336, _T_1337) @[Bitwise.scala 103:75] + node _T_1339 = or(_T_1334, _T_1338) @[Bitwise.scala 103:39] + node _T_1340 = bits(store_byteen_ext_m, 7, 7) @[lsu_dccm_ctl.scala 262:105] + node _T_1341 = bits(_T_1340, 0, 0) @[lsu_dccm_ctl.scala 262:111] + node _T_1342 = bits(store_data_hi_m, 31, 24) @[lsu_dccm_ctl.scala 262:133] + node _T_1343 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177] + node _T_1344 = bits(_T_1343, 0, 0) @[lsu_dccm_ctl.scala 262:203] + node _T_1345 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 262:228] + node _T_1346 = bits(io.sec_data_hi_m, 31, 24) @[lsu_dccm_ctl.scala 262:258] + node _T_1347 = mux(_T_1344, _T_1345, _T_1346) @[lsu_dccm_ctl.scala 262:151] + node _T_1348 = mux(_T_1341, _T_1342, _T_1347) @[lsu_dccm_ctl.scala 262:86] + node _T_1349 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1350 = xor(UInt<8>("h0ff"), _T_1349) @[Bitwise.scala 102:21] + node _T_1351 = shr(_T_1348, 4) @[Bitwise.scala 103:21] + node _T_1352 = and(_T_1351, _T_1350) @[Bitwise.scala 103:31] + node _T_1353 = bits(_T_1348, 3, 0) @[Bitwise.scala 103:46] + node _T_1354 = shl(_T_1353, 4) @[Bitwise.scala 103:65] + node _T_1355 = not(_T_1350) @[Bitwise.scala 103:77] + node _T_1356 = and(_T_1354, _T_1355) @[Bitwise.scala 103:75] + node _T_1357 = or(_T_1352, _T_1356) @[Bitwise.scala 103:39] + node _T_1358 = bits(_T_1350, 5, 0) @[Bitwise.scala 102:28] + node _T_1359 = shl(_T_1358, 2) @[Bitwise.scala 102:47] + node _T_1360 = xor(_T_1350, _T_1359) @[Bitwise.scala 102:21] + node _T_1361 = shr(_T_1357, 2) @[Bitwise.scala 103:21] + node _T_1362 = and(_T_1361, _T_1360) @[Bitwise.scala 103:31] + node _T_1363 = bits(_T_1357, 5, 0) @[Bitwise.scala 103:46] + node _T_1364 = shl(_T_1363, 2) @[Bitwise.scala 103:65] + node _T_1365 = not(_T_1360) @[Bitwise.scala 103:77] + node _T_1366 = and(_T_1364, _T_1365) @[Bitwise.scala 103:75] + node _T_1367 = or(_T_1362, _T_1366) @[Bitwise.scala 103:39] + node _T_1368 = bits(_T_1360, 6, 0) @[Bitwise.scala 102:28] + node _T_1369 = shl(_T_1368, 1) @[Bitwise.scala 102:47] + node _T_1370 = xor(_T_1360, _T_1369) @[Bitwise.scala 102:21] + node _T_1371 = shr(_T_1367, 1) @[Bitwise.scala 103:21] + node _T_1372 = and(_T_1371, _T_1370) @[Bitwise.scala 103:31] + node _T_1373 = bits(_T_1367, 6, 0) @[Bitwise.scala 103:46] + node _T_1374 = shl(_T_1373, 1) @[Bitwise.scala 103:65] + node _T_1375 = not(_T_1370) @[Bitwise.scala 103:77] + node _T_1376 = and(_T_1374, _T_1375) @[Bitwise.scala 103:75] + node _T_1377 = or(_T_1372, _T_1376) @[Bitwise.scala 103:39] + wire _T_1378 : UInt<8>[4] @[lsu_dccm_ctl.scala 262:70] + _T_1378[0] <= _T_1263 @[lsu_dccm_ctl.scala 262:70] + _T_1378[1] <= _T_1301 @[lsu_dccm_ctl.scala 262:70] + _T_1378[2] <= _T_1339 @[lsu_dccm_ctl.scala 262:70] + _T_1378[3] <= _T_1377 @[lsu_dccm_ctl.scala 262:70] + node _T_1379 = cat(_T_1378[2], _T_1378[3]) @[Cat.scala 29:58] + node _T_1380 = cat(_T_1378[0], _T_1378[1]) @[Cat.scala 29:58] + node _T_1381 = cat(_T_1380, _T_1379) @[Cat.scala 29:58] + node _T_1382 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1383 = xor(UInt<32>("h0ffffffff"), _T_1382) @[Bitwise.scala 102:21] + node _T_1384 = shr(_T_1381, 16) @[Bitwise.scala 103:21] + node _T_1385 = and(_T_1384, _T_1383) @[Bitwise.scala 103:31] + node _T_1386 = bits(_T_1381, 15, 0) @[Bitwise.scala 103:46] + node _T_1387 = shl(_T_1386, 16) @[Bitwise.scala 103:65] + node _T_1388 = not(_T_1383) @[Bitwise.scala 103:77] + node _T_1389 = and(_T_1387, _T_1388) @[Bitwise.scala 103:75] + node _T_1390 = or(_T_1385, _T_1389) @[Bitwise.scala 103:39] + node _T_1391 = bits(_T_1383, 23, 0) @[Bitwise.scala 102:28] + node _T_1392 = shl(_T_1391, 8) @[Bitwise.scala 102:47] + node _T_1393 = xor(_T_1383, _T_1392) @[Bitwise.scala 102:21] + node _T_1394 = shr(_T_1390, 8) @[Bitwise.scala 103:21] + node _T_1395 = and(_T_1394, _T_1393) @[Bitwise.scala 103:31] + node _T_1396 = bits(_T_1390, 23, 0) @[Bitwise.scala 103:46] + node _T_1397 = shl(_T_1396, 8) @[Bitwise.scala 103:65] + node _T_1398 = not(_T_1393) @[Bitwise.scala 103:77] + node _T_1399 = and(_T_1397, _T_1398) @[Bitwise.scala 103:75] + node _T_1400 = or(_T_1395, _T_1399) @[Bitwise.scala 103:39] + node _T_1401 = bits(_T_1393, 27, 0) @[Bitwise.scala 102:28] + node _T_1402 = shl(_T_1401, 4) @[Bitwise.scala 102:47] + node _T_1403 = xor(_T_1393, _T_1402) @[Bitwise.scala 102:21] + node _T_1404 = shr(_T_1400, 4) @[Bitwise.scala 103:21] + node _T_1405 = and(_T_1404, _T_1403) @[Bitwise.scala 103:31] + node _T_1406 = bits(_T_1400, 27, 0) @[Bitwise.scala 103:46] + node _T_1407 = shl(_T_1406, 4) @[Bitwise.scala 103:65] + node _T_1408 = not(_T_1403) @[Bitwise.scala 103:77] + node _T_1409 = and(_T_1407, _T_1408) @[Bitwise.scala 103:75] + node _T_1410 = or(_T_1405, _T_1409) @[Bitwise.scala 103:39] + node _T_1411 = bits(_T_1403, 29, 0) @[Bitwise.scala 102:28] + node _T_1412 = shl(_T_1411, 2) @[Bitwise.scala 102:47] + node _T_1413 = xor(_T_1403, _T_1412) @[Bitwise.scala 102:21] + node _T_1414 = shr(_T_1410, 2) @[Bitwise.scala 103:21] + node _T_1415 = and(_T_1414, _T_1413) @[Bitwise.scala 103:31] + node _T_1416 = bits(_T_1410, 29, 0) @[Bitwise.scala 103:46] + node _T_1417 = shl(_T_1416, 2) @[Bitwise.scala 103:65] + node _T_1418 = not(_T_1413) @[Bitwise.scala 103:77] + node _T_1419 = and(_T_1417, _T_1418) @[Bitwise.scala 103:75] + node _T_1420 = or(_T_1415, _T_1419) @[Bitwise.scala 103:39] + node _T_1421 = bits(_T_1413, 30, 0) @[Bitwise.scala 102:28] + node _T_1422 = shl(_T_1421, 1) @[Bitwise.scala 102:47] + node _T_1423 = xor(_T_1413, _T_1422) @[Bitwise.scala 102:21] + node _T_1424 = shr(_T_1420, 1) @[Bitwise.scala 103:21] + node _T_1425 = and(_T_1424, _T_1423) @[Bitwise.scala 103:31] + node _T_1426 = bits(_T_1420, 30, 0) @[Bitwise.scala 103:46] + node _T_1427 = shl(_T_1426, 1) @[Bitwise.scala 103:65] + node _T_1428 = not(_T_1423) @[Bitwise.scala 103:77] + node _T_1429 = and(_T_1427, _T_1428) @[Bitwise.scala 103:75] + node _T_1430 = or(_T_1425, _T_1429) @[Bitwise.scala 103:39] + node _T_1431 = and(io.ldst_dual_m, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 262:295] + node _T_1432 = and(_T_1431, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 262:316] + node _T_1433 = or(_T_1432, io.clk_override) @[lsu_dccm_ctl.scala 262:343] + node _T_1434 = bits(_T_1433, 0, 0) @[lib.scala 8:44] + node _T_1435 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_1 of rvclkhdr_5 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_1434 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1436 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1434 : @[Reg.scala 28:19] + _T_1436 <= _T_1430 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.store_data_hi_r <= _T_1436 @[lsu_dccm_ctl.scala 262:29] + node _T_1437 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105] + node _T_1438 = bits(store_byteen_ext_r, 0, 0) @[lsu_dccm_ctl.scala 263:150] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131] + node _T_1440 = and(_T_1437, _T_1439) @[lsu_dccm_ctl.scala 263:129] + node _T_1441 = bits(_T_1440, 0, 0) @[lsu_dccm_ctl.scala 263:155] + node _T_1442 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 263:179] + node _T_1443 = bits(io.store_data_lo_r, 7, 0) @[lsu_dccm_ctl.scala 263:211] + node _T_1444 = mux(_T_1441, _T_1442, _T_1443) @[lsu_dccm_ctl.scala 263:79] + node _T_1445 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1446 = xor(UInt<8>("h0ff"), _T_1445) @[Bitwise.scala 102:21] + node _T_1447 = shr(_T_1444, 4) @[Bitwise.scala 103:21] + node _T_1448 = and(_T_1447, _T_1446) @[Bitwise.scala 103:31] + node _T_1449 = bits(_T_1444, 3, 0) @[Bitwise.scala 103:46] + node _T_1450 = shl(_T_1449, 4) @[Bitwise.scala 103:65] + node _T_1451 = not(_T_1446) @[Bitwise.scala 103:77] + node _T_1452 = and(_T_1450, _T_1451) @[Bitwise.scala 103:75] + node _T_1453 = or(_T_1448, _T_1452) @[Bitwise.scala 103:39] + node _T_1454 = bits(_T_1446, 5, 0) @[Bitwise.scala 102:28] + node _T_1455 = shl(_T_1454, 2) @[Bitwise.scala 102:47] + node _T_1456 = xor(_T_1446, _T_1455) @[Bitwise.scala 102:21] + node _T_1457 = shr(_T_1453, 2) @[Bitwise.scala 103:21] + node _T_1458 = and(_T_1457, _T_1456) @[Bitwise.scala 103:31] + node _T_1459 = bits(_T_1453, 5, 0) @[Bitwise.scala 103:46] + node _T_1460 = shl(_T_1459, 2) @[Bitwise.scala 103:65] + node _T_1461 = not(_T_1456) @[Bitwise.scala 103:77] + node _T_1462 = and(_T_1460, _T_1461) @[Bitwise.scala 103:75] + node _T_1463 = or(_T_1458, _T_1462) @[Bitwise.scala 103:39] + node _T_1464 = bits(_T_1456, 6, 0) @[Bitwise.scala 102:28] + node _T_1465 = shl(_T_1464, 1) @[Bitwise.scala 102:47] + node _T_1466 = xor(_T_1456, _T_1465) @[Bitwise.scala 102:21] + node _T_1467 = shr(_T_1463, 1) @[Bitwise.scala 103:21] + node _T_1468 = and(_T_1467, _T_1466) @[Bitwise.scala 103:31] + node _T_1469 = bits(_T_1463, 6, 0) @[Bitwise.scala 103:46] + node _T_1470 = shl(_T_1469, 1) @[Bitwise.scala 103:65] + node _T_1471 = not(_T_1466) @[Bitwise.scala 103:77] + node _T_1472 = and(_T_1470, _T_1471) @[Bitwise.scala 103:75] + node _T_1473 = or(_T_1468, _T_1472) @[Bitwise.scala 103:39] + node _T_1474 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105] + node _T_1475 = bits(store_byteen_ext_r, 1, 1) @[lsu_dccm_ctl.scala 263:150] + node _T_1476 = eq(_T_1475, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131] + node _T_1477 = and(_T_1474, _T_1476) @[lsu_dccm_ctl.scala 263:129] + node _T_1478 = bits(_T_1477, 0, 0) @[lsu_dccm_ctl.scala 263:155] + node _T_1479 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 263:179] + node _T_1480 = bits(io.store_data_lo_r, 15, 8) @[lsu_dccm_ctl.scala 263:211] + node _T_1481 = mux(_T_1478, _T_1479, _T_1480) @[lsu_dccm_ctl.scala 263:79] + node _T_1482 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1483 = xor(UInt<8>("h0ff"), _T_1482) @[Bitwise.scala 102:21] + node _T_1484 = shr(_T_1481, 4) @[Bitwise.scala 103:21] + node _T_1485 = and(_T_1484, _T_1483) @[Bitwise.scala 103:31] + node _T_1486 = bits(_T_1481, 3, 0) @[Bitwise.scala 103:46] + node _T_1487 = shl(_T_1486, 4) @[Bitwise.scala 103:65] + node _T_1488 = not(_T_1483) @[Bitwise.scala 103:77] + node _T_1489 = and(_T_1487, _T_1488) @[Bitwise.scala 103:75] + node _T_1490 = or(_T_1485, _T_1489) @[Bitwise.scala 103:39] + node _T_1491 = bits(_T_1483, 5, 0) @[Bitwise.scala 102:28] + node _T_1492 = shl(_T_1491, 2) @[Bitwise.scala 102:47] + node _T_1493 = xor(_T_1483, _T_1492) @[Bitwise.scala 102:21] + node _T_1494 = shr(_T_1490, 2) @[Bitwise.scala 103:21] + node _T_1495 = and(_T_1494, _T_1493) @[Bitwise.scala 103:31] + node _T_1496 = bits(_T_1490, 5, 0) @[Bitwise.scala 103:46] + node _T_1497 = shl(_T_1496, 2) @[Bitwise.scala 103:65] + node _T_1498 = not(_T_1493) @[Bitwise.scala 103:77] + node _T_1499 = and(_T_1497, _T_1498) @[Bitwise.scala 103:75] + node _T_1500 = or(_T_1495, _T_1499) @[Bitwise.scala 103:39] + node _T_1501 = bits(_T_1493, 6, 0) @[Bitwise.scala 102:28] + node _T_1502 = shl(_T_1501, 1) @[Bitwise.scala 102:47] + node _T_1503 = xor(_T_1493, _T_1502) @[Bitwise.scala 102:21] + node _T_1504 = shr(_T_1500, 1) @[Bitwise.scala 103:21] + node _T_1505 = and(_T_1504, _T_1503) @[Bitwise.scala 103:31] + node _T_1506 = bits(_T_1500, 6, 0) @[Bitwise.scala 103:46] + node _T_1507 = shl(_T_1506, 1) @[Bitwise.scala 103:65] + node _T_1508 = not(_T_1503) @[Bitwise.scala 103:77] + node _T_1509 = and(_T_1507, _T_1508) @[Bitwise.scala 103:75] + node _T_1510 = or(_T_1505, _T_1509) @[Bitwise.scala 103:39] + node _T_1511 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105] + node _T_1512 = bits(store_byteen_ext_r, 2, 2) @[lsu_dccm_ctl.scala 263:150] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131] + node _T_1514 = and(_T_1511, _T_1513) @[lsu_dccm_ctl.scala 263:129] + node _T_1515 = bits(_T_1514, 0, 0) @[lsu_dccm_ctl.scala 263:155] + node _T_1516 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 263:179] + node _T_1517 = bits(io.store_data_lo_r, 23, 16) @[lsu_dccm_ctl.scala 263:211] + node _T_1518 = mux(_T_1515, _T_1516, _T_1517) @[lsu_dccm_ctl.scala 263:79] + node _T_1519 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1520 = xor(UInt<8>("h0ff"), _T_1519) @[Bitwise.scala 102:21] + node _T_1521 = shr(_T_1518, 4) @[Bitwise.scala 103:21] + node _T_1522 = and(_T_1521, _T_1520) @[Bitwise.scala 103:31] + node _T_1523 = bits(_T_1518, 3, 0) @[Bitwise.scala 103:46] + node _T_1524 = shl(_T_1523, 4) @[Bitwise.scala 103:65] + node _T_1525 = not(_T_1520) @[Bitwise.scala 103:77] + node _T_1526 = and(_T_1524, _T_1525) @[Bitwise.scala 103:75] + node _T_1527 = or(_T_1522, _T_1526) @[Bitwise.scala 103:39] + node _T_1528 = bits(_T_1520, 5, 0) @[Bitwise.scala 102:28] + node _T_1529 = shl(_T_1528, 2) @[Bitwise.scala 102:47] + node _T_1530 = xor(_T_1520, _T_1529) @[Bitwise.scala 102:21] + node _T_1531 = shr(_T_1527, 2) @[Bitwise.scala 103:21] + node _T_1532 = and(_T_1531, _T_1530) @[Bitwise.scala 103:31] + node _T_1533 = bits(_T_1527, 5, 0) @[Bitwise.scala 103:46] + node _T_1534 = shl(_T_1533, 2) @[Bitwise.scala 103:65] + node _T_1535 = not(_T_1530) @[Bitwise.scala 103:77] + node _T_1536 = and(_T_1534, _T_1535) @[Bitwise.scala 103:75] + node _T_1537 = or(_T_1532, _T_1536) @[Bitwise.scala 103:39] + node _T_1538 = bits(_T_1530, 6, 0) @[Bitwise.scala 102:28] + node _T_1539 = shl(_T_1538, 1) @[Bitwise.scala 102:47] + node _T_1540 = xor(_T_1530, _T_1539) @[Bitwise.scala 102:21] + node _T_1541 = shr(_T_1537, 1) @[Bitwise.scala 103:21] + node _T_1542 = and(_T_1541, _T_1540) @[Bitwise.scala 103:31] + node _T_1543 = bits(_T_1537, 6, 0) @[Bitwise.scala 103:46] + node _T_1544 = shl(_T_1543, 1) @[Bitwise.scala 103:65] + node _T_1545 = not(_T_1540) @[Bitwise.scala 103:77] + node _T_1546 = and(_T_1544, _T_1545) @[Bitwise.scala 103:75] + node _T_1547 = or(_T_1542, _T_1546) @[Bitwise.scala 103:39] + node _T_1548 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105] + node _T_1549 = bits(store_byteen_ext_r, 3, 3) @[lsu_dccm_ctl.scala 263:150] + node _T_1550 = eq(_T_1549, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131] + node _T_1551 = and(_T_1548, _T_1550) @[lsu_dccm_ctl.scala 263:129] + node _T_1552 = bits(_T_1551, 0, 0) @[lsu_dccm_ctl.scala 263:155] + node _T_1553 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 263:179] + node _T_1554 = bits(io.store_data_lo_r, 31, 24) @[lsu_dccm_ctl.scala 263:211] + node _T_1555 = mux(_T_1552, _T_1553, _T_1554) @[lsu_dccm_ctl.scala 263:79] + node _T_1556 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1557 = xor(UInt<8>("h0ff"), _T_1556) @[Bitwise.scala 102:21] + node _T_1558 = shr(_T_1555, 4) @[Bitwise.scala 103:21] + node _T_1559 = and(_T_1558, _T_1557) @[Bitwise.scala 103:31] + node _T_1560 = bits(_T_1555, 3, 0) @[Bitwise.scala 103:46] + node _T_1561 = shl(_T_1560, 4) @[Bitwise.scala 103:65] + node _T_1562 = not(_T_1557) @[Bitwise.scala 103:77] + node _T_1563 = and(_T_1561, _T_1562) @[Bitwise.scala 103:75] + node _T_1564 = or(_T_1559, _T_1563) @[Bitwise.scala 103:39] + node _T_1565 = bits(_T_1557, 5, 0) @[Bitwise.scala 102:28] + node _T_1566 = shl(_T_1565, 2) @[Bitwise.scala 102:47] + node _T_1567 = xor(_T_1557, _T_1566) @[Bitwise.scala 102:21] + node _T_1568 = shr(_T_1564, 2) @[Bitwise.scala 103:21] + node _T_1569 = and(_T_1568, _T_1567) @[Bitwise.scala 103:31] + node _T_1570 = bits(_T_1564, 5, 0) @[Bitwise.scala 103:46] + node _T_1571 = shl(_T_1570, 2) @[Bitwise.scala 103:65] + node _T_1572 = not(_T_1567) @[Bitwise.scala 103:77] + node _T_1573 = and(_T_1571, _T_1572) @[Bitwise.scala 103:75] + node _T_1574 = or(_T_1569, _T_1573) @[Bitwise.scala 103:39] + node _T_1575 = bits(_T_1567, 6, 0) @[Bitwise.scala 102:28] + node _T_1576 = shl(_T_1575, 1) @[Bitwise.scala 102:47] + node _T_1577 = xor(_T_1567, _T_1576) @[Bitwise.scala 102:21] + node _T_1578 = shr(_T_1574, 1) @[Bitwise.scala 103:21] + node _T_1579 = and(_T_1578, _T_1577) @[Bitwise.scala 103:31] + node _T_1580 = bits(_T_1574, 6, 0) @[Bitwise.scala 103:46] + node _T_1581 = shl(_T_1580, 1) @[Bitwise.scala 103:65] + node _T_1582 = not(_T_1577) @[Bitwise.scala 103:77] + node _T_1583 = and(_T_1581, _T_1582) @[Bitwise.scala 103:75] + node _T_1584 = or(_T_1579, _T_1583) @[Bitwise.scala 103:39] + wire _T_1585 : UInt<8>[4] @[lsu_dccm_ctl.scala 263:63] + _T_1585[0] <= _T_1473 @[lsu_dccm_ctl.scala 263:63] + _T_1585[1] <= _T_1510 @[lsu_dccm_ctl.scala 263:63] + _T_1585[2] <= _T_1547 @[lsu_dccm_ctl.scala 263:63] + _T_1585[3] <= _T_1584 @[lsu_dccm_ctl.scala 263:63] + node _T_1586 = cat(_T_1585[2], _T_1585[3]) @[Cat.scala 29:58] + node _T_1587 = cat(_T_1585[0], _T_1585[1]) @[Cat.scala 29:58] + node _T_1588 = cat(_T_1587, _T_1586) @[Cat.scala 29:58] + node _T_1589 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1590 = xor(UInt<32>("h0ffffffff"), _T_1589) @[Bitwise.scala 102:21] + node _T_1591 = shr(_T_1588, 16) @[Bitwise.scala 103:21] + node _T_1592 = and(_T_1591, _T_1590) @[Bitwise.scala 103:31] + node _T_1593 = bits(_T_1588, 15, 0) @[Bitwise.scala 103:46] + node _T_1594 = shl(_T_1593, 16) @[Bitwise.scala 103:65] + node _T_1595 = not(_T_1590) @[Bitwise.scala 103:77] + node _T_1596 = and(_T_1594, _T_1595) @[Bitwise.scala 103:75] + node _T_1597 = or(_T_1592, _T_1596) @[Bitwise.scala 103:39] + node _T_1598 = bits(_T_1590, 23, 0) @[Bitwise.scala 102:28] + node _T_1599 = shl(_T_1598, 8) @[Bitwise.scala 102:47] + node _T_1600 = xor(_T_1590, _T_1599) @[Bitwise.scala 102:21] + node _T_1601 = shr(_T_1597, 8) @[Bitwise.scala 103:21] + node _T_1602 = and(_T_1601, _T_1600) @[Bitwise.scala 103:31] + node _T_1603 = bits(_T_1597, 23, 0) @[Bitwise.scala 103:46] + node _T_1604 = shl(_T_1603, 8) @[Bitwise.scala 103:65] + node _T_1605 = not(_T_1600) @[Bitwise.scala 103:77] + node _T_1606 = and(_T_1604, _T_1605) @[Bitwise.scala 103:75] + node _T_1607 = or(_T_1602, _T_1606) @[Bitwise.scala 103:39] + node _T_1608 = bits(_T_1600, 27, 0) @[Bitwise.scala 102:28] + node _T_1609 = shl(_T_1608, 4) @[Bitwise.scala 102:47] + node _T_1610 = xor(_T_1600, _T_1609) @[Bitwise.scala 102:21] + node _T_1611 = shr(_T_1607, 4) @[Bitwise.scala 103:21] + node _T_1612 = and(_T_1611, _T_1610) @[Bitwise.scala 103:31] + node _T_1613 = bits(_T_1607, 27, 0) @[Bitwise.scala 103:46] + node _T_1614 = shl(_T_1613, 4) @[Bitwise.scala 103:65] + node _T_1615 = not(_T_1610) @[Bitwise.scala 103:77] + node _T_1616 = and(_T_1614, _T_1615) @[Bitwise.scala 103:75] + node _T_1617 = or(_T_1612, _T_1616) @[Bitwise.scala 103:39] + node _T_1618 = bits(_T_1610, 29, 0) @[Bitwise.scala 102:28] + node _T_1619 = shl(_T_1618, 2) @[Bitwise.scala 102:47] + node _T_1620 = xor(_T_1610, _T_1619) @[Bitwise.scala 102:21] + node _T_1621 = shr(_T_1617, 2) @[Bitwise.scala 103:21] + node _T_1622 = and(_T_1621, _T_1620) @[Bitwise.scala 103:31] + node _T_1623 = bits(_T_1617, 29, 0) @[Bitwise.scala 103:46] + node _T_1624 = shl(_T_1623, 2) @[Bitwise.scala 103:65] + node _T_1625 = not(_T_1620) @[Bitwise.scala 103:77] + node _T_1626 = and(_T_1624, _T_1625) @[Bitwise.scala 103:75] + node _T_1627 = or(_T_1622, _T_1626) @[Bitwise.scala 103:39] + node _T_1628 = bits(_T_1620, 30, 0) @[Bitwise.scala 102:28] + node _T_1629 = shl(_T_1628, 1) @[Bitwise.scala 102:47] + node _T_1630 = xor(_T_1620, _T_1629) @[Bitwise.scala 102:21] + node _T_1631 = shr(_T_1627, 1) @[Bitwise.scala 103:21] + node _T_1632 = and(_T_1631, _T_1630) @[Bitwise.scala 103:31] + node _T_1633 = bits(_T_1627, 30, 0) @[Bitwise.scala 103:46] + node _T_1634 = shl(_T_1633, 1) @[Bitwise.scala 103:65] + node _T_1635 = not(_T_1630) @[Bitwise.scala 103:77] + node _T_1636 = and(_T_1634, _T_1635) @[Bitwise.scala 103:75] + node _T_1637 = or(_T_1632, _T_1636) @[Bitwise.scala 103:39] + io.store_datafn_lo_r <= _T_1637 @[lsu_dccm_ctl.scala 263:29] + node _T_1638 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105] + node _T_1639 = bits(store_byteen_ext_r, 4, 4) @[lsu_dccm_ctl.scala 264:150] + node _T_1640 = eq(_T_1639, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131] + node _T_1641 = and(_T_1638, _T_1640) @[lsu_dccm_ctl.scala 264:129] + node _T_1642 = bits(_T_1641, 0, 0) @[lsu_dccm_ctl.scala 264:157] + node _T_1643 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 264:181] + node _T_1644 = bits(io.store_data_hi_r, 7, 0) @[lsu_dccm_ctl.scala 264:213] + node _T_1645 = mux(_T_1642, _T_1643, _T_1644) @[lsu_dccm_ctl.scala 264:79] + node _T_1646 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1647 = xor(UInt<8>("h0ff"), _T_1646) @[Bitwise.scala 102:21] + node _T_1648 = shr(_T_1645, 4) @[Bitwise.scala 103:21] + node _T_1649 = and(_T_1648, _T_1647) @[Bitwise.scala 103:31] + node _T_1650 = bits(_T_1645, 3, 0) @[Bitwise.scala 103:46] + node _T_1651 = shl(_T_1650, 4) @[Bitwise.scala 103:65] + node _T_1652 = not(_T_1647) @[Bitwise.scala 103:77] + node _T_1653 = and(_T_1651, _T_1652) @[Bitwise.scala 103:75] + node _T_1654 = or(_T_1649, _T_1653) @[Bitwise.scala 103:39] + node _T_1655 = bits(_T_1647, 5, 0) @[Bitwise.scala 102:28] + node _T_1656 = shl(_T_1655, 2) @[Bitwise.scala 102:47] + node _T_1657 = xor(_T_1647, _T_1656) @[Bitwise.scala 102:21] + node _T_1658 = shr(_T_1654, 2) @[Bitwise.scala 103:21] + node _T_1659 = and(_T_1658, _T_1657) @[Bitwise.scala 103:31] + node _T_1660 = bits(_T_1654, 5, 0) @[Bitwise.scala 103:46] + node _T_1661 = shl(_T_1660, 2) @[Bitwise.scala 103:65] + node _T_1662 = not(_T_1657) @[Bitwise.scala 103:77] + node _T_1663 = and(_T_1661, _T_1662) @[Bitwise.scala 103:75] + node _T_1664 = or(_T_1659, _T_1663) @[Bitwise.scala 103:39] + node _T_1665 = bits(_T_1657, 6, 0) @[Bitwise.scala 102:28] + node _T_1666 = shl(_T_1665, 1) @[Bitwise.scala 102:47] + node _T_1667 = xor(_T_1657, _T_1666) @[Bitwise.scala 102:21] + node _T_1668 = shr(_T_1664, 1) @[Bitwise.scala 103:21] + node _T_1669 = and(_T_1668, _T_1667) @[Bitwise.scala 103:31] + node _T_1670 = bits(_T_1664, 6, 0) @[Bitwise.scala 103:46] + node _T_1671 = shl(_T_1670, 1) @[Bitwise.scala 103:65] + node _T_1672 = not(_T_1667) @[Bitwise.scala 103:77] + node _T_1673 = and(_T_1671, _T_1672) @[Bitwise.scala 103:75] + node _T_1674 = or(_T_1669, _T_1673) @[Bitwise.scala 103:39] + node _T_1675 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105] + node _T_1676 = bits(store_byteen_ext_r, 5, 5) @[lsu_dccm_ctl.scala 264:150] + node _T_1677 = eq(_T_1676, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131] + node _T_1678 = and(_T_1675, _T_1677) @[lsu_dccm_ctl.scala 264:129] + node _T_1679 = bits(_T_1678, 0, 0) @[lsu_dccm_ctl.scala 264:157] + node _T_1680 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 264:181] + node _T_1681 = bits(io.store_data_hi_r, 15, 8) @[lsu_dccm_ctl.scala 264:213] + node _T_1682 = mux(_T_1679, _T_1680, _T_1681) @[lsu_dccm_ctl.scala 264:79] + node _T_1683 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1684 = xor(UInt<8>("h0ff"), _T_1683) @[Bitwise.scala 102:21] + node _T_1685 = shr(_T_1682, 4) @[Bitwise.scala 103:21] + node _T_1686 = and(_T_1685, _T_1684) @[Bitwise.scala 103:31] + node _T_1687 = bits(_T_1682, 3, 0) @[Bitwise.scala 103:46] + node _T_1688 = shl(_T_1687, 4) @[Bitwise.scala 103:65] + node _T_1689 = not(_T_1684) @[Bitwise.scala 103:77] + node _T_1690 = and(_T_1688, _T_1689) @[Bitwise.scala 103:75] + node _T_1691 = or(_T_1686, _T_1690) @[Bitwise.scala 103:39] + node _T_1692 = bits(_T_1684, 5, 0) @[Bitwise.scala 102:28] + node _T_1693 = shl(_T_1692, 2) @[Bitwise.scala 102:47] + node _T_1694 = xor(_T_1684, _T_1693) @[Bitwise.scala 102:21] + node _T_1695 = shr(_T_1691, 2) @[Bitwise.scala 103:21] + node _T_1696 = and(_T_1695, _T_1694) @[Bitwise.scala 103:31] + node _T_1697 = bits(_T_1691, 5, 0) @[Bitwise.scala 103:46] + node _T_1698 = shl(_T_1697, 2) @[Bitwise.scala 103:65] + node _T_1699 = not(_T_1694) @[Bitwise.scala 103:77] + node _T_1700 = and(_T_1698, _T_1699) @[Bitwise.scala 103:75] + node _T_1701 = or(_T_1696, _T_1700) @[Bitwise.scala 103:39] + node _T_1702 = bits(_T_1694, 6, 0) @[Bitwise.scala 102:28] + node _T_1703 = shl(_T_1702, 1) @[Bitwise.scala 102:47] + node _T_1704 = xor(_T_1694, _T_1703) @[Bitwise.scala 102:21] + node _T_1705 = shr(_T_1701, 1) @[Bitwise.scala 103:21] + node _T_1706 = and(_T_1705, _T_1704) @[Bitwise.scala 103:31] + node _T_1707 = bits(_T_1701, 6, 0) @[Bitwise.scala 103:46] + node _T_1708 = shl(_T_1707, 1) @[Bitwise.scala 103:65] + node _T_1709 = not(_T_1704) @[Bitwise.scala 103:77] + node _T_1710 = and(_T_1708, _T_1709) @[Bitwise.scala 103:75] + node _T_1711 = or(_T_1706, _T_1710) @[Bitwise.scala 103:39] + node _T_1712 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105] + node _T_1713 = bits(store_byteen_ext_r, 6, 6) @[lsu_dccm_ctl.scala 264:150] + node _T_1714 = eq(_T_1713, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131] + node _T_1715 = and(_T_1712, _T_1714) @[lsu_dccm_ctl.scala 264:129] + node _T_1716 = bits(_T_1715, 0, 0) @[lsu_dccm_ctl.scala 264:157] + node _T_1717 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 264:181] + node _T_1718 = bits(io.store_data_hi_r, 23, 16) @[lsu_dccm_ctl.scala 264:213] + node _T_1719 = mux(_T_1716, _T_1717, _T_1718) @[lsu_dccm_ctl.scala 264:79] + node _T_1720 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1721 = xor(UInt<8>("h0ff"), _T_1720) @[Bitwise.scala 102:21] + node _T_1722 = shr(_T_1719, 4) @[Bitwise.scala 103:21] + node _T_1723 = and(_T_1722, _T_1721) @[Bitwise.scala 103:31] + node _T_1724 = bits(_T_1719, 3, 0) @[Bitwise.scala 103:46] + node _T_1725 = shl(_T_1724, 4) @[Bitwise.scala 103:65] + node _T_1726 = not(_T_1721) @[Bitwise.scala 103:77] + node _T_1727 = and(_T_1725, _T_1726) @[Bitwise.scala 103:75] + node _T_1728 = or(_T_1723, _T_1727) @[Bitwise.scala 103:39] + node _T_1729 = bits(_T_1721, 5, 0) @[Bitwise.scala 102:28] + node _T_1730 = shl(_T_1729, 2) @[Bitwise.scala 102:47] + node _T_1731 = xor(_T_1721, _T_1730) @[Bitwise.scala 102:21] + node _T_1732 = shr(_T_1728, 2) @[Bitwise.scala 103:21] + node _T_1733 = and(_T_1732, _T_1731) @[Bitwise.scala 103:31] + node _T_1734 = bits(_T_1728, 5, 0) @[Bitwise.scala 103:46] + node _T_1735 = shl(_T_1734, 2) @[Bitwise.scala 103:65] + node _T_1736 = not(_T_1731) @[Bitwise.scala 103:77] + node _T_1737 = and(_T_1735, _T_1736) @[Bitwise.scala 103:75] + node _T_1738 = or(_T_1733, _T_1737) @[Bitwise.scala 103:39] + node _T_1739 = bits(_T_1731, 6, 0) @[Bitwise.scala 102:28] + node _T_1740 = shl(_T_1739, 1) @[Bitwise.scala 102:47] + node _T_1741 = xor(_T_1731, _T_1740) @[Bitwise.scala 102:21] + node _T_1742 = shr(_T_1738, 1) @[Bitwise.scala 103:21] + node _T_1743 = and(_T_1742, _T_1741) @[Bitwise.scala 103:31] + node _T_1744 = bits(_T_1738, 6, 0) @[Bitwise.scala 103:46] + node _T_1745 = shl(_T_1744, 1) @[Bitwise.scala 103:65] + node _T_1746 = not(_T_1741) @[Bitwise.scala 103:77] + node _T_1747 = and(_T_1745, _T_1746) @[Bitwise.scala 103:75] + node _T_1748 = or(_T_1743, _T_1747) @[Bitwise.scala 103:39] + node _T_1749 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105] + node _T_1750 = bits(store_byteen_ext_r, 7, 7) @[lsu_dccm_ctl.scala 264:150] + node _T_1751 = eq(_T_1750, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131] + node _T_1752 = and(_T_1749, _T_1751) @[lsu_dccm_ctl.scala 264:129] + node _T_1753 = bits(_T_1752, 0, 0) @[lsu_dccm_ctl.scala 264:157] + node _T_1754 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 264:181] + node _T_1755 = bits(io.store_data_hi_r, 31, 24) @[lsu_dccm_ctl.scala 264:213] + node _T_1756 = mux(_T_1753, _T_1754, _T_1755) @[lsu_dccm_ctl.scala 264:79] + node _T_1757 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1758 = xor(UInt<8>("h0ff"), _T_1757) @[Bitwise.scala 102:21] + node _T_1759 = shr(_T_1756, 4) @[Bitwise.scala 103:21] + node _T_1760 = and(_T_1759, _T_1758) @[Bitwise.scala 103:31] + node _T_1761 = bits(_T_1756, 3, 0) @[Bitwise.scala 103:46] + node _T_1762 = shl(_T_1761, 4) @[Bitwise.scala 103:65] + node _T_1763 = not(_T_1758) @[Bitwise.scala 103:77] + node _T_1764 = and(_T_1762, _T_1763) @[Bitwise.scala 103:75] + node _T_1765 = or(_T_1760, _T_1764) @[Bitwise.scala 103:39] + node _T_1766 = bits(_T_1758, 5, 0) @[Bitwise.scala 102:28] + node _T_1767 = shl(_T_1766, 2) @[Bitwise.scala 102:47] + node _T_1768 = xor(_T_1758, _T_1767) @[Bitwise.scala 102:21] + node _T_1769 = shr(_T_1765, 2) @[Bitwise.scala 103:21] + node _T_1770 = and(_T_1769, _T_1768) @[Bitwise.scala 103:31] + node _T_1771 = bits(_T_1765, 5, 0) @[Bitwise.scala 103:46] + node _T_1772 = shl(_T_1771, 2) @[Bitwise.scala 103:65] + node _T_1773 = not(_T_1768) @[Bitwise.scala 103:77] + node _T_1774 = and(_T_1772, _T_1773) @[Bitwise.scala 103:75] + node _T_1775 = or(_T_1770, _T_1774) @[Bitwise.scala 103:39] + node _T_1776 = bits(_T_1768, 6, 0) @[Bitwise.scala 102:28] + node _T_1777 = shl(_T_1776, 1) @[Bitwise.scala 102:47] + node _T_1778 = xor(_T_1768, _T_1777) @[Bitwise.scala 102:21] + node _T_1779 = shr(_T_1775, 1) @[Bitwise.scala 103:21] + node _T_1780 = and(_T_1779, _T_1778) @[Bitwise.scala 103:31] + node _T_1781 = bits(_T_1775, 6, 0) @[Bitwise.scala 103:46] + node _T_1782 = shl(_T_1781, 1) @[Bitwise.scala 103:65] + node _T_1783 = not(_T_1778) @[Bitwise.scala 103:77] + node _T_1784 = and(_T_1782, _T_1783) @[Bitwise.scala 103:75] + node _T_1785 = or(_T_1780, _T_1784) @[Bitwise.scala 103:39] + wire _T_1786 : UInt<8>[4] @[lsu_dccm_ctl.scala 264:63] + _T_1786[0] <= _T_1674 @[lsu_dccm_ctl.scala 264:63] + _T_1786[1] <= _T_1711 @[lsu_dccm_ctl.scala 264:63] + _T_1786[2] <= _T_1748 @[lsu_dccm_ctl.scala 264:63] + _T_1786[3] <= _T_1785 @[lsu_dccm_ctl.scala 264:63] + node _T_1787 = cat(_T_1786[2], _T_1786[3]) @[Cat.scala 29:58] + node _T_1788 = cat(_T_1786[0], _T_1786[1]) @[Cat.scala 29:58] + node _T_1789 = cat(_T_1788, _T_1787) @[Cat.scala 29:58] + node _T_1790 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1791 = xor(UInt<32>("h0ffffffff"), _T_1790) @[Bitwise.scala 102:21] + node _T_1792 = shr(_T_1789, 16) @[Bitwise.scala 103:21] + node _T_1793 = and(_T_1792, _T_1791) @[Bitwise.scala 103:31] + node _T_1794 = bits(_T_1789, 15, 0) @[Bitwise.scala 103:46] + node _T_1795 = shl(_T_1794, 16) @[Bitwise.scala 103:65] + node _T_1796 = not(_T_1791) @[Bitwise.scala 103:77] + node _T_1797 = and(_T_1795, _T_1796) @[Bitwise.scala 103:75] + node _T_1798 = or(_T_1793, _T_1797) @[Bitwise.scala 103:39] + node _T_1799 = bits(_T_1791, 23, 0) @[Bitwise.scala 102:28] + node _T_1800 = shl(_T_1799, 8) @[Bitwise.scala 102:47] + node _T_1801 = xor(_T_1791, _T_1800) @[Bitwise.scala 102:21] + node _T_1802 = shr(_T_1798, 8) @[Bitwise.scala 103:21] + node _T_1803 = and(_T_1802, _T_1801) @[Bitwise.scala 103:31] + node _T_1804 = bits(_T_1798, 23, 0) @[Bitwise.scala 103:46] + node _T_1805 = shl(_T_1804, 8) @[Bitwise.scala 103:65] + node _T_1806 = not(_T_1801) @[Bitwise.scala 103:77] + node _T_1807 = and(_T_1805, _T_1806) @[Bitwise.scala 103:75] + node _T_1808 = or(_T_1803, _T_1807) @[Bitwise.scala 103:39] + node _T_1809 = bits(_T_1801, 27, 0) @[Bitwise.scala 102:28] + node _T_1810 = shl(_T_1809, 4) @[Bitwise.scala 102:47] + node _T_1811 = xor(_T_1801, _T_1810) @[Bitwise.scala 102:21] + node _T_1812 = shr(_T_1808, 4) @[Bitwise.scala 103:21] + node _T_1813 = and(_T_1812, _T_1811) @[Bitwise.scala 103:31] + node _T_1814 = bits(_T_1808, 27, 0) @[Bitwise.scala 103:46] + node _T_1815 = shl(_T_1814, 4) @[Bitwise.scala 103:65] + node _T_1816 = not(_T_1811) @[Bitwise.scala 103:77] + node _T_1817 = and(_T_1815, _T_1816) @[Bitwise.scala 103:75] + node _T_1818 = or(_T_1813, _T_1817) @[Bitwise.scala 103:39] + node _T_1819 = bits(_T_1811, 29, 0) @[Bitwise.scala 102:28] + node _T_1820 = shl(_T_1819, 2) @[Bitwise.scala 102:47] + node _T_1821 = xor(_T_1811, _T_1820) @[Bitwise.scala 102:21] + node _T_1822 = shr(_T_1818, 2) @[Bitwise.scala 103:21] + node _T_1823 = and(_T_1822, _T_1821) @[Bitwise.scala 103:31] + node _T_1824 = bits(_T_1818, 29, 0) @[Bitwise.scala 103:46] + node _T_1825 = shl(_T_1824, 2) @[Bitwise.scala 103:65] + node _T_1826 = not(_T_1821) @[Bitwise.scala 103:77] + node _T_1827 = and(_T_1825, _T_1826) @[Bitwise.scala 103:75] + node _T_1828 = or(_T_1823, _T_1827) @[Bitwise.scala 103:39] + node _T_1829 = bits(_T_1821, 30, 0) @[Bitwise.scala 102:28] + node _T_1830 = shl(_T_1829, 1) @[Bitwise.scala 102:47] + node _T_1831 = xor(_T_1821, _T_1830) @[Bitwise.scala 102:21] + node _T_1832 = shr(_T_1828, 1) @[Bitwise.scala 103:21] + node _T_1833 = and(_T_1832, _T_1831) @[Bitwise.scala 103:31] + node _T_1834 = bits(_T_1828, 30, 0) @[Bitwise.scala 103:46] + node _T_1835 = shl(_T_1834, 1) @[Bitwise.scala 103:65] + node _T_1836 = not(_T_1831) @[Bitwise.scala 103:77] + node _T_1837 = and(_T_1835, _T_1836) @[Bitwise.scala 103:75] + node _T_1838 = or(_T_1833, _T_1837) @[Bitwise.scala 103:39] + io.store_datafn_hi_r <= _T_1838 @[lsu_dccm_ctl.scala 264:29] + node _T_1839 = bits(io.store_data_hi_r, 31, 0) @[lsu_dccm_ctl.scala 265:55] + node _T_1840 = bits(io.store_data_lo_r, 31, 0) @[lsu_dccm_ctl.scala 265:80] + node _T_1841 = cat(_T_1839, _T_1840) @[Cat.scala 29:58] + node _T_1842 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 265:108] + node _T_1843 = mul(UInt<4>("h08"), _T_1842) @[lsu_dccm_ctl.scala 265:94] + node _T_1844 = dshr(_T_1841, _T_1843) @[lsu_dccm_ctl.scala 265:88] + node _T_1845 = bits(store_byteen_r, 0, 0) @[lsu_dccm_ctl.scala 265:174] + node _T_1846 = bits(_T_1845, 0, 0) @[Bitwise.scala 72:15] + node _T_1847 = mux(_T_1846, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1848 = bits(store_byteen_r, 1, 1) @[lsu_dccm_ctl.scala 265:174] + node _T_1849 = bits(_T_1848, 0, 0) @[Bitwise.scala 72:15] + node _T_1850 = mux(_T_1849, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1851 = bits(store_byteen_r, 2, 2) @[lsu_dccm_ctl.scala 265:174] + node _T_1852 = bits(_T_1851, 0, 0) @[Bitwise.scala 72:15] + node _T_1853 = mux(_T_1852, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1854 = bits(store_byteen_r, 3, 3) @[lsu_dccm_ctl.scala 265:174] + node _T_1855 = bits(_T_1854, 0, 0) @[Bitwise.scala 72:15] + node _T_1856 = mux(_T_1855, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + wire _T_1857 : UInt<8>[4] @[lsu_dccm_ctl.scala 265:148] + _T_1857[0] <= _T_1847 @[lsu_dccm_ctl.scala 265:148] + _T_1857[1] <= _T_1850 @[lsu_dccm_ctl.scala 265:148] + _T_1857[2] <= _T_1853 @[lsu_dccm_ctl.scala 265:148] + _T_1857[3] <= _T_1856 @[lsu_dccm_ctl.scala 265:148] + node _T_1858 = cat(_T_1857[2], _T_1857[3]) @[Cat.scala 29:58] + node _T_1859 = cat(_T_1857[0], _T_1857[1]) @[Cat.scala 29:58] + node _T_1860 = cat(_T_1859, _T_1858) @[Cat.scala 29:58] + node _T_1861 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1862 = xor(UInt<32>("h0ffffffff"), _T_1861) @[Bitwise.scala 102:21] + node _T_1863 = shr(_T_1860, 16) @[Bitwise.scala 103:21] + node _T_1864 = and(_T_1863, _T_1862) @[Bitwise.scala 103:31] + node _T_1865 = bits(_T_1860, 15, 0) @[Bitwise.scala 103:46] + node _T_1866 = shl(_T_1865, 16) @[Bitwise.scala 103:65] + node _T_1867 = not(_T_1862) @[Bitwise.scala 103:77] + node _T_1868 = and(_T_1866, _T_1867) @[Bitwise.scala 103:75] + node _T_1869 = or(_T_1864, _T_1868) @[Bitwise.scala 103:39] + node _T_1870 = bits(_T_1862, 23, 0) @[Bitwise.scala 102:28] + node _T_1871 = shl(_T_1870, 8) @[Bitwise.scala 102:47] + node _T_1872 = xor(_T_1862, _T_1871) @[Bitwise.scala 102:21] + node _T_1873 = shr(_T_1869, 8) @[Bitwise.scala 103:21] + node _T_1874 = and(_T_1873, _T_1872) @[Bitwise.scala 103:31] + node _T_1875 = bits(_T_1869, 23, 0) @[Bitwise.scala 103:46] + node _T_1876 = shl(_T_1875, 8) @[Bitwise.scala 103:65] + node _T_1877 = not(_T_1872) @[Bitwise.scala 103:77] + node _T_1878 = and(_T_1876, _T_1877) @[Bitwise.scala 103:75] + node _T_1879 = or(_T_1874, _T_1878) @[Bitwise.scala 103:39] + node _T_1880 = bits(_T_1872, 27, 0) @[Bitwise.scala 102:28] + node _T_1881 = shl(_T_1880, 4) @[Bitwise.scala 102:47] + node _T_1882 = xor(_T_1872, _T_1881) @[Bitwise.scala 102:21] + node _T_1883 = shr(_T_1879, 4) @[Bitwise.scala 103:21] + node _T_1884 = and(_T_1883, _T_1882) @[Bitwise.scala 103:31] + node _T_1885 = bits(_T_1879, 27, 0) @[Bitwise.scala 103:46] + node _T_1886 = shl(_T_1885, 4) @[Bitwise.scala 103:65] + node _T_1887 = not(_T_1882) @[Bitwise.scala 103:77] + node _T_1888 = and(_T_1886, _T_1887) @[Bitwise.scala 103:75] + node _T_1889 = or(_T_1884, _T_1888) @[Bitwise.scala 103:39] + node _T_1890 = bits(_T_1882, 29, 0) @[Bitwise.scala 102:28] + node _T_1891 = shl(_T_1890, 2) @[Bitwise.scala 102:47] + node _T_1892 = xor(_T_1882, _T_1891) @[Bitwise.scala 102:21] + node _T_1893 = shr(_T_1889, 2) @[Bitwise.scala 103:21] + node _T_1894 = and(_T_1893, _T_1892) @[Bitwise.scala 103:31] + node _T_1895 = bits(_T_1889, 29, 0) @[Bitwise.scala 103:46] + node _T_1896 = shl(_T_1895, 2) @[Bitwise.scala 103:65] + node _T_1897 = not(_T_1892) @[Bitwise.scala 103:77] + node _T_1898 = and(_T_1896, _T_1897) @[Bitwise.scala 103:75] + node _T_1899 = or(_T_1894, _T_1898) @[Bitwise.scala 103:39] + node _T_1900 = bits(_T_1892, 30, 0) @[Bitwise.scala 102:28] + node _T_1901 = shl(_T_1900, 1) @[Bitwise.scala 102:47] + node _T_1902 = xor(_T_1892, _T_1901) @[Bitwise.scala 102:21] + node _T_1903 = shr(_T_1899, 1) @[Bitwise.scala 103:21] + node _T_1904 = and(_T_1903, _T_1902) @[Bitwise.scala 103:31] + node _T_1905 = bits(_T_1899, 30, 0) @[Bitwise.scala 103:46] + node _T_1906 = shl(_T_1905, 1) @[Bitwise.scala 103:65] + node _T_1907 = not(_T_1902) @[Bitwise.scala 103:77] + node _T_1908 = and(_T_1906, _T_1907) @[Bitwise.scala 103:75] + node _T_1909 = or(_T_1904, _T_1908) @[Bitwise.scala 103:39] + node _T_1910 = and(_T_1844, _T_1909) @[lsu_dccm_ctl.scala 265:115] + io.store_data_r <= _T_1910 @[lsu_dccm_ctl.scala 265:29] + node _T_1911 = bits(io.dccm.rd_data_lo, 31, 0) @[lsu_dccm_ctl.scala 267:48] + io.dccm_rdata_lo_m <= _T_1911 @[lsu_dccm_ctl.scala 267:27] + node _T_1912 = bits(io.dccm.rd_data_hi, 31, 0) @[lsu_dccm_ctl.scala 268:48] + io.dccm_rdata_hi_m <= _T_1912 @[lsu_dccm_ctl.scala 268:27] + node _T_1913 = bits(io.dccm.rd_data_lo, 38, 32) @[lsu_dccm_ctl.scala 269:48] + io.dccm_data_ecc_lo_m <= _T_1913 @[lsu_dccm_ctl.scala 269:27] + node _T_1914 = bits(io.dccm.rd_data_hi, 38, 32) @[lsu_dccm_ctl.scala 270:48] + io.dccm_data_ecc_hi_m <= _T_1914 @[lsu_dccm_ctl.scala 270:27] + node _T_1915 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[lsu_dccm_ctl.scala 272:58] + node _T_1916 = and(_T_1915, io.addr_in_pic_r) @[lsu_dccm_ctl.scala 272:84] + node _T_1917 = and(_T_1916, io.lsu_commit_r) @[lsu_dccm_ctl.scala 272:103] + node _T_1918 = or(_T_1917, io.dma_pic_wen) @[lsu_dccm_ctl.scala 272:122] + io.lsu_pic.picm_wren <= _T_1918 @[lsu_dccm_ctl.scala 272:35] + node _T_1919 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.load) @[lsu_dccm_ctl.scala 273:58] + node _T_1920 = and(_T_1919, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 273:84] + io.lsu_pic.picm_rden <= _T_1920 @[lsu_dccm_ctl.scala 273:35] + node _T_1921 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 274:58] + node _T_1922 = and(_T_1921, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 274:84] + io.lsu_pic.picm_mken <= _T_1922 @[lsu_dccm_ctl.scala 274:35] + node _T_1923 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] + node _T_1924 = bits(io.lsu_addr_d, 14, 0) @[lsu_dccm_ctl.scala 275:103] + node _T_1925 = cat(_T_1923, _T_1924) @[Cat.scala 29:58] + node _T_1926 = or(UInt<32>("h0f00c0000"), _T_1925) @[lsu_dccm_ctl.scala 275:62] + io.lsu_pic.picm_rdaddr <= _T_1926 @[lsu_dccm_ctl.scala 275:35] + node _T_1927 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] + node _T_1928 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 276:109] + node _T_1929 = bits(io.dma_dccm_ctl.dma_mem_addr, 14, 0) @[lsu_dccm_ctl.scala 276:144] + node _T_1930 = bits(io.lsu_addr_r, 14, 0) @[lsu_dccm_ctl.scala 276:172] + node _T_1931 = mux(_T_1928, _T_1929, _T_1930) @[lsu_dccm_ctl.scala 276:93] + node _T_1932 = cat(_T_1927, _T_1931) @[Cat.scala 29:58] + node _T_1933 = or(UInt<32>("h0f00c0000"), _T_1932) @[lsu_dccm_ctl.scala 276:62] + io.lsu_pic.picm_wraddr <= _T_1933 @[lsu_dccm_ctl.scala 276:35] + node _T_1934 = bits(picm_rd_data_m, 31, 0) @[lsu_dccm_ctl.scala 277:44] + io.picm_mask_data_m <= _T_1934 @[lsu_dccm_ctl.scala 277:27] + node _T_1935 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 278:57] + node _T_1936 = bits(io.dma_dccm_ctl.dma_mem_wdata, 31, 0) @[lsu_dccm_ctl.scala 278:93] + node _T_1937 = bits(io.store_datafn_lo_r, 31, 0) @[lsu_dccm_ctl.scala 278:120] + node _T_1938 = mux(_T_1935, _T_1936, _T_1937) @[lsu_dccm_ctl.scala 278:41] + io.lsu_pic.picm_wr_data <= _T_1938 @[lsu_dccm_ctl.scala 278:35] + reg _T_1939 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 280:61] + _T_1939 <= lsu_dccm_rden_d @[lsu_dccm_ctl.scala 280:61] + io.lsu_dccm_rden_m <= _T_1939 @[lsu_dccm_ctl.scala 280:24] + reg _T_1940 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 281:61] + _T_1940 <= io.lsu_dccm_rden_m @[lsu_dccm_ctl.scala 281:61] + io.lsu_dccm_rden_r <= _T_1940 @[lsu_dccm_ctl.scala 281:24] + reg _T_1941 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 282:73] + _T_1941 <= io.lsu_double_ecc_error_r @[lsu_dccm_ctl.scala 282:73] + lsu_double_ecc_error_r_ff <= _T_1941 @[lsu_dccm_ctl.scala 282:33] + reg _T_1942 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 283:73] + _T_1942 <= ld_single_ecc_error_hi_r_ns @[lsu_dccm_ctl.scala 283:73] + ld_single_ecc_error_hi_r_ff <= _T_1942 @[lsu_dccm_ctl.scala 283:33] + reg _T_1943 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 284:73] + _T_1943 <= ld_single_ecc_error_lo_r_ns @[lsu_dccm_ctl.scala 284:73] + ld_single_ecc_error_lo_r_ff <= _T_1943 @[lsu_dccm_ctl.scala 284:33] + node _T_1944 = bits(io.end_addr_r, 15, 0) @[lsu_dccm_ctl.scala 285:48] + node _T_1945 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 285:90] + node _T_1946 = bits(_T_1945, 0, 0) @[lib.scala 8:44] + node _T_1947 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 285:128] + inst rvclkhdr_2 of rvclkhdr_6 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_1946 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1948 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1946 : @[Reg.scala 28:19] + _T_1948 <= _T_1944 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ld_sec_addr_hi_r_ff <= _T_1948 @[lsu_dccm_ctl.scala 285:25] + node _T_1949 = bits(io.lsu_addr_r, 15, 0) @[lsu_dccm_ctl.scala 286:48] + node _T_1950 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 286:90] + node _T_1951 = bits(_T_1950, 0, 0) @[lib.scala 8:44] + node _T_1952 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 286:128] + inst rvclkhdr_3 of rvclkhdr_7 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_1951 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1953 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1951 : @[Reg.scala 28:19] + _T_1953 <= _T_1949 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ld_sec_addr_lo_r_ff <= _T_1953 @[lsu_dccm_ctl.scala 286:25] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_stbuf : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_stbuf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip store_stbuf_reqvld_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip dec_lsu_valid_raw_d : UInt<1>, flip store_data_hi_r : UInt<32>, flip store_data_lo_r : UInt<32>, flip store_datafn_hi_r : UInt<32>, flip store_datafn_lo_r : UInt<32>, flip lsu_stbuf_commit_any : UInt<1>, flip lsu_addr_d : UInt<16>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_cmpen_m : UInt<1>, flip scan_mode : UInt<1>, stbuf_reqvld_any : UInt<1>, stbuf_reqvld_flushed_any : UInt<1>, stbuf_addr_any : UInt<16>, stbuf_data_any : UInt<32>, lsu_stbuf_full_any : UInt<1>, lsu_stbuf_empty_any : UInt<1>, ldst_stbuf_reqvld_r : UInt<1>, stbuf_fwddata_hi_m : UInt<32>, stbuf_fwddata_lo_m : UInt<32>, stbuf_fwdbyteen_hi_m : UInt<4>, stbuf_fwdbyteen_lo_m : UInt<4>} + + io.stbuf_reqvld_any <= UInt<1>("h00") @[lsu_stbuf.scala 51:47] + io.stbuf_reqvld_flushed_any <= UInt<1>("h00") @[lsu_stbuf.scala 52:35] + io.stbuf_addr_any <= UInt<1>("h00") @[lsu_stbuf.scala 53:35] + io.stbuf_data_any <= UInt<1>("h00") @[lsu_stbuf.scala 54:35] + io.lsu_stbuf_full_any <= UInt<1>("h00") @[lsu_stbuf.scala 55:43] + io.lsu_stbuf_empty_any <= UInt<1>("h00") @[lsu_stbuf.scala 56:43] + io.ldst_stbuf_reqvld_r <= UInt<1>("h00") @[lsu_stbuf.scala 57:43] + io.stbuf_fwddata_hi_m <= UInt<1>("h00") @[lsu_stbuf.scala 58:43] + io.stbuf_fwddata_lo_m <= UInt<1>("h00") @[lsu_stbuf.scala 59:43] + io.stbuf_fwdbyteen_hi_m <= UInt<1>("h00") @[lsu_stbuf.scala 60:37] + io.stbuf_fwdbyteen_lo_m <= UInt<1>("h00") @[lsu_stbuf.scala 61:37] + wire stbuf_vld : UInt<4> + stbuf_vld <= UInt<1>("h00") + wire stbuf_wr_en : UInt<4> + stbuf_wr_en <= UInt<1>("h00") + wire stbuf_dma_kill_en : UInt<4> + stbuf_dma_kill_en <= UInt<1>("h00") + wire stbuf_dma_kill : UInt<4> + stbuf_dma_kill <= UInt<1>("h00") + wire stbuf_reset : UInt<4> + stbuf_reset <= UInt<1>("h00") + wire store_byteen_ext_r : UInt<8> + store_byteen_ext_r <= UInt<1>("h00") + wire stbuf_addr : UInt<16>[4] @[lsu_stbuf.scala 70:38] + stbuf_addr[0] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + stbuf_addr[1] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + stbuf_addr[2] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + stbuf_addr[3] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + wire stbuf_byteen : UInt<4>[4] @[lsu_stbuf.scala 72:38] + stbuf_byteen[0] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + stbuf_byteen[1] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + stbuf_byteen[2] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + stbuf_byteen[3] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + wire stbuf_data : UInt<32>[4] @[lsu_stbuf.scala 74:38] + stbuf_data[0] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + stbuf_data[1] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + stbuf_data[2] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + stbuf_data[3] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + wire stbuf_addrin : UInt<16>[4] @[lsu_stbuf.scala 76:38] + stbuf_addrin[0] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + stbuf_addrin[1] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + stbuf_addrin[2] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + stbuf_addrin[3] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + wire stbuf_datain : UInt<32>[4] @[lsu_stbuf.scala 78:38] + stbuf_datain[0] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + stbuf_datain[1] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + stbuf_datain[2] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + stbuf_datain[3] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + wire stbuf_byteenin : UInt<4>[4] @[lsu_stbuf.scala 80:38] + stbuf_byteenin[0] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + stbuf_byteenin[1] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + stbuf_byteenin[2] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + stbuf_byteenin[3] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + wire WrPtr : UInt<2> + WrPtr <= UInt<1>("h00") + wire RdPtr : UInt<2> + RdPtr <= UInt<1>("h00") + wire cmpaddr_hi_m : UInt<16> + cmpaddr_hi_m <= UInt<16>("h00") + wire stbuf_specvld_m : UInt<2> + stbuf_specvld_m <= UInt<2>("h00") + wire stbuf_specvld_r : UInt<2> + stbuf_specvld_r <= UInt<2>("h00") + wire cmpaddr_lo_m : UInt<16> + cmpaddr_lo_m <= UInt<16>("h00") + wire stbuf_fwdata_hi_pre_m : UInt<32> + stbuf_fwdata_hi_pre_m <= UInt<1>("h00") + wire stbuf_fwdata_lo_pre_m : UInt<32> + stbuf_fwdata_lo_pre_m <= UInt<1>("h00") + wire ld_byte_rhit_lo_lo : UInt<4> + ld_byte_rhit_lo_lo <= UInt<1>("h00") + wire ld_byte_rhit_hi_lo : UInt<4> + ld_byte_rhit_hi_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo_hi : UInt<4> + ld_byte_rhit_lo_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi_hi : UInt<4> + ld_byte_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_hit_lo : UInt<4> + ld_byte_hit_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo : UInt<4> + ld_byte_rhit_lo <= UInt<1>("h00") + wire ld_byte_hit_hi : UInt<4> + ld_byte_hit_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi : UInt<4> + ld_byte_rhit_hi <= UInt<1>("h00") + wire ldst_byteen_ext_r : UInt<8> + ldst_byteen_ext_r <= UInt<1>("h00") + wire ld_fwddata_rpipe_lo : UInt<32> + ld_fwddata_rpipe_lo <= UInt<1>("h00") + wire ld_fwddata_rpipe_hi : UInt<32> + ld_fwddata_rpipe_hi <= UInt<1>("h00") + wire datain1 : UInt<8>[4] @[lsu_stbuf.scala 103:33] + wire datain2 : UInt<8>[4] @[lsu_stbuf.scala 104:33] + wire datain3 : UInt<8>[4] @[lsu_stbuf.scala 105:33] + wire datain4 : UInt<8>[4] @[lsu_stbuf.scala 106:33] + node _T = bits(io.lsu_pkt_r.bits.by, 0, 0) @[lsu_stbuf.scala 110:26] + node _T_1 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[lsu_stbuf.scala 111:28] + node _T_2 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[lsu_stbuf.scala 112:28] + node _T_3 = bits(io.lsu_pkt_r.bits.dword, 0, 0) @[lsu_stbuf.scala 113:29] + node _T_4 = mux(_T, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_1, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = mux(_T_2, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_7 = mux(_T_3, UInt<8>("h0ff"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_8 = or(_T_4, _T_5) @[Mux.scala 27:72] + node _T_9 = or(_T_8, _T_6) @[Mux.scala 27:72] + node _T_10 = or(_T_9, _T_7) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<8> @[Mux.scala 27:72] + ldst_byteen_r <= _T_10 @[Mux.scala 27:72] + node dual_stbuf_write_r = and(io.ldst_dual_r, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 115:43] + node _T_11 = bits(io.lsu_addr_r, 1, 0) @[lsu_stbuf.scala 117:55] + node _T_12 = dshl(ldst_byteen_r, _T_11) @[lsu_stbuf.scala 117:39] + store_byteen_ext_r <= _T_12 @[lsu_stbuf.scala 117:22] + node _T_13 = bits(store_byteen_ext_r, 7, 4) @[lsu_stbuf.scala 118:46] + node _T_14 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_15 = mux(_T_14, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node store_byteen_hi_r = and(_T_13, _T_15) @[lsu_stbuf.scala 118:52] + node _T_16 = bits(store_byteen_ext_r, 3, 0) @[lsu_stbuf.scala 119:46] + node _T_17 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_18 = mux(_T_17, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node store_byteen_lo_r = and(_T_16, _T_18) @[lsu_stbuf.scala 119:52] + node _T_19 = add(RdPtr, UInt<1>("h01")) @[lsu_stbuf.scala 121:26] + node RdPtrPlus1 = tail(_T_19, 1) @[lsu_stbuf.scala 121:26] + node _T_20 = add(WrPtr, UInt<1>("h01")) @[lsu_stbuf.scala 122:26] + node WrPtrPlus1 = tail(_T_20, 1) @[lsu_stbuf.scala 122:26] + node _T_21 = add(WrPtr, UInt<2>("h02")) @[lsu_stbuf.scala 123:26] + node WrPtrPlus2 = tail(_T_21, 1) @[lsu_stbuf.scala 123:26] + node _T_22 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_stbuf.scala 125:46] + node _T_23 = and(_T_22, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 125:71] + io.ldst_stbuf_reqvld_r <= _T_23 @[lsu_stbuf.scala 125:26] + node _T_24 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 127:78] + node _T_25 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 127:137] + node _T_26 = eq(_T_24, _T_25) @[lsu_stbuf.scala 127:120] + node _T_27 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 127:191] + node _T_28 = and(_T_26, _T_27) @[lsu_stbuf.scala 127:179] + node _T_29 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 127:212] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_stbuf.scala 127:197] + node _T_31 = and(_T_28, _T_30) @[lsu_stbuf.scala 127:195] + node _T_32 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 127:230] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[lsu_stbuf.scala 127:218] + node _T_34 = and(_T_31, _T_33) @[lsu_stbuf.scala 127:216] + node _T_35 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 127:78] + node _T_36 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 127:137] + node _T_37 = eq(_T_35, _T_36) @[lsu_stbuf.scala 127:120] + node _T_38 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 127:191] + node _T_39 = and(_T_37, _T_38) @[lsu_stbuf.scala 127:179] + node _T_40 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 127:212] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[lsu_stbuf.scala 127:197] + node _T_42 = and(_T_39, _T_41) @[lsu_stbuf.scala 127:195] + node _T_43 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 127:230] + node _T_44 = eq(_T_43, UInt<1>("h00")) @[lsu_stbuf.scala 127:218] + node _T_45 = and(_T_42, _T_44) @[lsu_stbuf.scala 127:216] + node _T_46 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 127:78] + node _T_47 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 127:137] + node _T_48 = eq(_T_46, _T_47) @[lsu_stbuf.scala 127:120] + node _T_49 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 127:191] + node _T_50 = and(_T_48, _T_49) @[lsu_stbuf.scala 127:179] + node _T_51 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 127:212] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[lsu_stbuf.scala 127:197] + node _T_53 = and(_T_50, _T_52) @[lsu_stbuf.scala 127:195] + node _T_54 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 127:230] + node _T_55 = eq(_T_54, UInt<1>("h00")) @[lsu_stbuf.scala 127:218] + node _T_56 = and(_T_53, _T_55) @[lsu_stbuf.scala 127:216] + node _T_57 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 127:78] + node _T_58 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 127:137] + node _T_59 = eq(_T_57, _T_58) @[lsu_stbuf.scala 127:120] + node _T_60 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 127:191] + node _T_61 = and(_T_59, _T_60) @[lsu_stbuf.scala 127:179] + node _T_62 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 127:212] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[lsu_stbuf.scala 127:197] + node _T_64 = and(_T_61, _T_63) @[lsu_stbuf.scala 127:195] + node _T_65 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 127:230] + node _T_66 = eq(_T_65, UInt<1>("h00")) @[lsu_stbuf.scala 127:218] + node _T_67 = and(_T_64, _T_66) @[lsu_stbuf.scala 127:216] + node _T_68 = cat(_T_67, _T_56) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_45) @[Cat.scala 29:58] + node store_matchvec_lo_r = cat(_T_69, _T_34) @[Cat.scala 29:58] + node _T_70 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 128:78] + node _T_71 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 128:137] + node _T_72 = eq(_T_70, _T_71) @[lsu_stbuf.scala 128:120] + node _T_73 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 128:190] + node _T_74 = and(_T_72, _T_73) @[lsu_stbuf.scala 128:179] + node _T_75 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 128:211] + node _T_76 = eq(_T_75, UInt<1>("h00")) @[lsu_stbuf.scala 128:196] + node _T_77 = and(_T_74, _T_76) @[lsu_stbuf.scala 128:194] + node _T_78 = and(_T_77, dual_stbuf_write_r) @[lsu_stbuf.scala 128:215] + node _T_79 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 128:250] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[lsu_stbuf.scala 128:238] + node _T_81 = and(_T_78, _T_80) @[lsu_stbuf.scala 128:236] + node _T_82 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 128:78] + node _T_83 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 128:137] + node _T_84 = eq(_T_82, _T_83) @[lsu_stbuf.scala 128:120] + node _T_85 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 128:190] + node _T_86 = and(_T_84, _T_85) @[lsu_stbuf.scala 128:179] + node _T_87 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 128:211] + node _T_88 = eq(_T_87, UInt<1>("h00")) @[lsu_stbuf.scala 128:196] + node _T_89 = and(_T_86, _T_88) @[lsu_stbuf.scala 128:194] + node _T_90 = and(_T_89, dual_stbuf_write_r) @[lsu_stbuf.scala 128:215] + node _T_91 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 128:250] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[lsu_stbuf.scala 128:238] + node _T_93 = and(_T_90, _T_92) @[lsu_stbuf.scala 128:236] + node _T_94 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 128:78] + node _T_95 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 128:137] + node _T_96 = eq(_T_94, _T_95) @[lsu_stbuf.scala 128:120] + node _T_97 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 128:190] + node _T_98 = and(_T_96, _T_97) @[lsu_stbuf.scala 128:179] + node _T_99 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 128:211] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[lsu_stbuf.scala 128:196] + node _T_101 = and(_T_98, _T_100) @[lsu_stbuf.scala 128:194] + node _T_102 = and(_T_101, dual_stbuf_write_r) @[lsu_stbuf.scala 128:215] + node _T_103 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 128:250] + node _T_104 = eq(_T_103, UInt<1>("h00")) @[lsu_stbuf.scala 128:238] + node _T_105 = and(_T_102, _T_104) @[lsu_stbuf.scala 128:236] + node _T_106 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 128:78] + node _T_107 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 128:137] + node _T_108 = eq(_T_106, _T_107) @[lsu_stbuf.scala 128:120] + node _T_109 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 128:190] + node _T_110 = and(_T_108, _T_109) @[lsu_stbuf.scala 128:179] + node _T_111 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 128:211] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[lsu_stbuf.scala 128:196] + node _T_113 = and(_T_110, _T_112) @[lsu_stbuf.scala 128:194] + node _T_114 = and(_T_113, dual_stbuf_write_r) @[lsu_stbuf.scala 128:215] + node _T_115 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 128:250] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[lsu_stbuf.scala 128:238] + node _T_117 = and(_T_114, _T_116) @[lsu_stbuf.scala 128:236] + node _T_118 = cat(_T_117, _T_105) @[Cat.scala 29:58] + node _T_119 = cat(_T_118, _T_93) @[Cat.scala 29:58] + node store_matchvec_hi_r = cat(_T_119, _T_81) @[Cat.scala 29:58] + node store_coalesce_lo_r = orr(store_matchvec_lo_r) @[lsu_stbuf.scala 130:49] + node store_coalesce_hi_r = orr(store_matchvec_hi_r) @[lsu_stbuf.scala 131:49] + node _T_120 = eq(UInt<1>("h00"), WrPtr) @[lsu_stbuf.scala 134:18] + node _T_121 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 134:31] + node _T_122 = and(_T_120, _T_121) @[lsu_stbuf.scala 134:29] + node _T_123 = eq(UInt<1>("h00"), WrPtr) @[lsu_stbuf.scala 135:20] + node _T_124 = and(_T_123, dual_stbuf_write_r) @[lsu_stbuf.scala 135:31] + node _T_125 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 135:54] + node _T_126 = and(_T_124, _T_125) @[lsu_stbuf.scala 135:52] + node _T_127 = or(_T_122, _T_126) @[lsu_stbuf.scala 134:53] + node _T_128 = eq(UInt<1>("h00"), WrPtrPlus1) @[lsu_stbuf.scala 136:20] + node _T_129 = and(_T_128, dual_stbuf_write_r) @[lsu_stbuf.scala 136:36] + node _T_130 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 136:81] + node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_stbuf.scala 136:59] + node _T_132 = and(_T_129, _T_131) @[lsu_stbuf.scala 136:57] + node _T_133 = or(_T_127, _T_132) @[lsu_stbuf.scala 135:76] + node _T_134 = bits(store_matchvec_lo_r, 0, 0) @[lsu_stbuf.scala 137:28] + node _T_135 = or(_T_133, _T_134) @[lsu_stbuf.scala 136:105] + node _T_136 = bits(store_matchvec_hi_r, 0, 0) @[lsu_stbuf.scala 137:53] + node _T_137 = or(_T_135, _T_136) @[lsu_stbuf.scala 137:32] + node _T_138 = and(io.ldst_stbuf_reqvld_r, _T_137) @[lsu_stbuf.scala 133:79] + node _T_139 = eq(UInt<1>("h01"), WrPtr) @[lsu_stbuf.scala 134:18] + node _T_140 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 134:31] + node _T_141 = and(_T_139, _T_140) @[lsu_stbuf.scala 134:29] + node _T_142 = eq(UInt<1>("h01"), WrPtr) @[lsu_stbuf.scala 135:20] + node _T_143 = and(_T_142, dual_stbuf_write_r) @[lsu_stbuf.scala 135:31] + node _T_144 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 135:54] + node _T_145 = and(_T_143, _T_144) @[lsu_stbuf.scala 135:52] + node _T_146 = or(_T_141, _T_145) @[lsu_stbuf.scala 134:53] + node _T_147 = eq(UInt<1>("h01"), WrPtrPlus1) @[lsu_stbuf.scala 136:20] + node _T_148 = and(_T_147, dual_stbuf_write_r) @[lsu_stbuf.scala 136:36] + node _T_149 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 136:81] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_stbuf.scala 136:59] + node _T_151 = and(_T_148, _T_150) @[lsu_stbuf.scala 136:57] + node _T_152 = or(_T_146, _T_151) @[lsu_stbuf.scala 135:76] + node _T_153 = bits(store_matchvec_lo_r, 1, 1) @[lsu_stbuf.scala 137:28] + node _T_154 = or(_T_152, _T_153) @[lsu_stbuf.scala 136:105] + node _T_155 = bits(store_matchvec_hi_r, 1, 1) @[lsu_stbuf.scala 137:53] + node _T_156 = or(_T_154, _T_155) @[lsu_stbuf.scala 137:32] + node _T_157 = and(io.ldst_stbuf_reqvld_r, _T_156) @[lsu_stbuf.scala 133:79] + node _T_158 = eq(UInt<2>("h02"), WrPtr) @[lsu_stbuf.scala 134:18] + node _T_159 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 134:31] + node _T_160 = and(_T_158, _T_159) @[lsu_stbuf.scala 134:29] + node _T_161 = eq(UInt<2>("h02"), WrPtr) @[lsu_stbuf.scala 135:20] + node _T_162 = and(_T_161, dual_stbuf_write_r) @[lsu_stbuf.scala 135:31] + node _T_163 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 135:54] + node _T_164 = and(_T_162, _T_163) @[lsu_stbuf.scala 135:52] + node _T_165 = or(_T_160, _T_164) @[lsu_stbuf.scala 134:53] + node _T_166 = eq(UInt<2>("h02"), WrPtrPlus1) @[lsu_stbuf.scala 136:20] + node _T_167 = and(_T_166, dual_stbuf_write_r) @[lsu_stbuf.scala 136:36] + node _T_168 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 136:81] + node _T_169 = eq(_T_168, UInt<1>("h00")) @[lsu_stbuf.scala 136:59] + node _T_170 = and(_T_167, _T_169) @[lsu_stbuf.scala 136:57] + node _T_171 = or(_T_165, _T_170) @[lsu_stbuf.scala 135:76] + node _T_172 = bits(store_matchvec_lo_r, 2, 2) @[lsu_stbuf.scala 137:28] + node _T_173 = or(_T_171, _T_172) @[lsu_stbuf.scala 136:105] + node _T_174 = bits(store_matchvec_hi_r, 2, 2) @[lsu_stbuf.scala 137:53] + node _T_175 = or(_T_173, _T_174) @[lsu_stbuf.scala 137:32] + node _T_176 = and(io.ldst_stbuf_reqvld_r, _T_175) @[lsu_stbuf.scala 133:79] + node _T_177 = eq(UInt<2>("h03"), WrPtr) @[lsu_stbuf.scala 134:18] + node _T_178 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 134:31] + node _T_179 = and(_T_177, _T_178) @[lsu_stbuf.scala 134:29] + node _T_180 = eq(UInt<2>("h03"), WrPtr) @[lsu_stbuf.scala 135:20] + node _T_181 = and(_T_180, dual_stbuf_write_r) @[lsu_stbuf.scala 135:31] + node _T_182 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 135:54] + node _T_183 = and(_T_181, _T_182) @[lsu_stbuf.scala 135:52] + node _T_184 = or(_T_179, _T_183) @[lsu_stbuf.scala 134:53] + node _T_185 = eq(UInt<2>("h03"), WrPtrPlus1) @[lsu_stbuf.scala 136:20] + node _T_186 = and(_T_185, dual_stbuf_write_r) @[lsu_stbuf.scala 136:36] + node _T_187 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 136:81] + node _T_188 = eq(_T_187, UInt<1>("h00")) @[lsu_stbuf.scala 136:59] + node _T_189 = and(_T_186, _T_188) @[lsu_stbuf.scala 136:57] + node _T_190 = or(_T_184, _T_189) @[lsu_stbuf.scala 135:76] + node _T_191 = bits(store_matchvec_lo_r, 3, 3) @[lsu_stbuf.scala 137:28] + node _T_192 = or(_T_190, _T_191) @[lsu_stbuf.scala 136:105] + node _T_193 = bits(store_matchvec_hi_r, 3, 3) @[lsu_stbuf.scala 137:53] + node _T_194 = or(_T_192, _T_193) @[lsu_stbuf.scala 137:32] + node _T_195 = and(io.ldst_stbuf_reqvld_r, _T_194) @[lsu_stbuf.scala 133:79] + node _T_196 = cat(_T_195, _T_176) @[Cat.scala 29:58] + node _T_197 = cat(_T_196, _T_157) @[Cat.scala 29:58] + node _T_198 = cat(_T_197, _T_138) @[Cat.scala 29:58] + stbuf_wr_en <= _T_198 @[lsu_stbuf.scala 133:17] + node _T_199 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 138:81] + node _T_200 = eq(UInt<1>("h00"), RdPtr) @[lsu_stbuf.scala 138:124] + node _T_201 = bits(_T_200, 0, 0) @[lsu_stbuf.scala 138:135] + node _T_202 = and(_T_199, _T_201) @[lsu_stbuf.scala 138:112] + node _T_203 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 138:81] + node _T_204 = eq(UInt<1>("h01"), RdPtr) @[lsu_stbuf.scala 138:124] + node _T_205 = bits(_T_204, 0, 0) @[lsu_stbuf.scala 138:135] + node _T_206 = and(_T_203, _T_205) @[lsu_stbuf.scala 138:112] + node _T_207 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 138:81] + node _T_208 = eq(UInt<2>("h02"), RdPtr) @[lsu_stbuf.scala 138:124] + node _T_209 = bits(_T_208, 0, 0) @[lsu_stbuf.scala 138:135] + node _T_210 = and(_T_207, _T_209) @[lsu_stbuf.scala 138:112] + node _T_211 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 138:81] + node _T_212 = eq(UInt<2>("h03"), RdPtr) @[lsu_stbuf.scala 138:124] + node _T_213 = bits(_T_212, 0, 0) @[lsu_stbuf.scala 138:135] + node _T_214 = and(_T_211, _T_213) @[lsu_stbuf.scala 138:112] + node _T_215 = cat(_T_214, _T_210) @[Cat.scala 29:58] + node _T_216 = cat(_T_215, _T_206) @[Cat.scala 29:58] + node _T_217 = cat(_T_216, _T_202) @[Cat.scala 29:58] + stbuf_reset <= _T_217 @[lsu_stbuf.scala 138:17] + node _T_218 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:56] + node _T_219 = or(_T_218, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 139:72] + node _T_220 = eq(UInt<1>("h00"), WrPtr) @[lsu_stbuf.scala 139:111] + node _T_221 = bits(_T_220, 0, 0) @[lsu_stbuf.scala 139:122] + node _T_222 = and(_T_219, _T_221) @[lsu_stbuf.scala 139:99] + node _T_223 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:131] + node _T_224 = and(_T_222, _T_223) @[lsu_stbuf.scala 139:129] + node _T_225 = bits(store_matchvec_lo_r, 0, 0) @[lsu_stbuf.scala 139:174] + node _T_226 = or(_T_224, _T_225) @[lsu_stbuf.scala 139:153] + node _T_227 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:56] + node _T_228 = or(_T_227, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 139:72] + node _T_229 = eq(UInt<1>("h01"), WrPtr) @[lsu_stbuf.scala 139:111] + node _T_230 = bits(_T_229, 0, 0) @[lsu_stbuf.scala 139:122] + node _T_231 = and(_T_228, _T_230) @[lsu_stbuf.scala 139:99] + node _T_232 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:131] + node _T_233 = and(_T_231, _T_232) @[lsu_stbuf.scala 139:129] + node _T_234 = bits(store_matchvec_lo_r, 1, 1) @[lsu_stbuf.scala 139:174] + node _T_235 = or(_T_233, _T_234) @[lsu_stbuf.scala 139:153] + node _T_236 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:56] + node _T_237 = or(_T_236, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 139:72] + node _T_238 = eq(UInt<2>("h02"), WrPtr) @[lsu_stbuf.scala 139:111] + node _T_239 = bits(_T_238, 0, 0) @[lsu_stbuf.scala 139:122] + node _T_240 = and(_T_237, _T_239) @[lsu_stbuf.scala 139:99] + node _T_241 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:131] + node _T_242 = and(_T_240, _T_241) @[lsu_stbuf.scala 139:129] + node _T_243 = bits(store_matchvec_lo_r, 2, 2) @[lsu_stbuf.scala 139:174] + node _T_244 = or(_T_242, _T_243) @[lsu_stbuf.scala 139:153] + node _T_245 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:56] + node _T_246 = or(_T_245, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 139:72] + node _T_247 = eq(UInt<2>("h03"), WrPtr) @[lsu_stbuf.scala 139:111] + node _T_248 = bits(_T_247, 0, 0) @[lsu_stbuf.scala 139:122] + node _T_249 = and(_T_246, _T_248) @[lsu_stbuf.scala 139:99] + node _T_250 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:131] + node _T_251 = and(_T_249, _T_250) @[lsu_stbuf.scala 139:129] + node _T_252 = bits(store_matchvec_lo_r, 3, 3) @[lsu_stbuf.scala 139:174] + node _T_253 = or(_T_251, _T_252) @[lsu_stbuf.scala 139:153] + node _T_254 = cat(_T_253, _T_244) @[Cat.scala 29:58] + node _T_255 = cat(_T_254, _T_235) @[Cat.scala 29:58] + node sel_lo = cat(_T_255, _T_226) @[Cat.scala 29:58] + node _T_256 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 141:66] + node _T_257 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 141:84] + node _T_258 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 141:119] + node _T_259 = mux(_T_256, _T_257, _T_258) @[lsu_stbuf.scala 141:59] + node _T_260 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 141:66] + node _T_261 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 141:84] + node _T_262 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 141:119] + node _T_263 = mux(_T_260, _T_261, _T_262) @[lsu_stbuf.scala 141:59] + node _T_264 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 141:66] + node _T_265 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 141:84] + node _T_266 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 141:119] + node _T_267 = mux(_T_264, _T_265, _T_266) @[lsu_stbuf.scala 141:59] + node _T_268 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 141:66] + node _T_269 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 141:84] + node _T_270 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 141:119] + node _T_271 = mux(_T_268, _T_269, _T_270) @[lsu_stbuf.scala 141:59] + stbuf_addrin[0] <= _T_259 @[lsu_stbuf.scala 141:18] + stbuf_addrin[1] <= _T_263 @[lsu_stbuf.scala 141:18] + stbuf_addrin[2] <= _T_267 @[lsu_stbuf.scala 141:18] + stbuf_addrin[3] <= _T_271 @[lsu_stbuf.scala 141:18] + node _T_272 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 142:68] + node _T_273 = or(stbuf_byteen[0], store_byteen_lo_r) @[lsu_stbuf.scala 142:89] + node _T_274 = or(stbuf_byteen[0], store_byteen_hi_r) @[lsu_stbuf.scala 142:126] + node _T_275 = mux(_T_272, _T_273, _T_274) @[lsu_stbuf.scala 142:61] + node _T_276 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 142:68] + node _T_277 = or(stbuf_byteen[1], store_byteen_lo_r) @[lsu_stbuf.scala 142:89] + node _T_278 = or(stbuf_byteen[1], store_byteen_hi_r) @[lsu_stbuf.scala 142:126] + node _T_279 = mux(_T_276, _T_277, _T_278) @[lsu_stbuf.scala 142:61] + node _T_280 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 142:68] + node _T_281 = or(stbuf_byteen[2], store_byteen_lo_r) @[lsu_stbuf.scala 142:89] + node _T_282 = or(stbuf_byteen[2], store_byteen_hi_r) @[lsu_stbuf.scala 142:126] + node _T_283 = mux(_T_280, _T_281, _T_282) @[lsu_stbuf.scala 142:61] + node _T_284 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 142:68] + node _T_285 = or(stbuf_byteen[3], store_byteen_lo_r) @[lsu_stbuf.scala 142:89] + node _T_286 = or(stbuf_byteen[3], store_byteen_hi_r) @[lsu_stbuf.scala 142:126] + node _T_287 = mux(_T_284, _T_285, _T_286) @[lsu_stbuf.scala 142:61] + stbuf_byteenin[0] <= _T_275 @[lsu_stbuf.scala 142:20] + stbuf_byteenin[1] <= _T_279 @[lsu_stbuf.scala 142:20] + stbuf_byteenin[2] <= _T_283 @[lsu_stbuf.scala 142:20] + stbuf_byteenin[3] <= _T_287 @[lsu_stbuf.scala 142:20] + node _T_288 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 144:61] + node _T_289 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 144:86] + node _T_290 = eq(_T_289, UInt<1>("h00")) @[lsu_stbuf.scala 144:70] + node _T_291 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 144:109] + node _T_292 = or(_T_290, _T_291) @[lsu_stbuf.scala 144:90] + node _T_293 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 144:134] + node _T_294 = bits(stbuf_data[0], 7, 0) @[lsu_stbuf.scala 144:155] + node _T_295 = mux(_T_292, _T_293, _T_294) @[lsu_stbuf.scala 144:69] + node _T_296 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 145:27] + node _T_297 = eq(_T_296, UInt<1>("h00")) @[lsu_stbuf.scala 145:11] + node _T_298 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 145:50] + node _T_299 = or(_T_297, _T_298) @[lsu_stbuf.scala 145:31] + node _T_300 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 145:75] + node _T_301 = bits(stbuf_data[0], 7, 0) @[lsu_stbuf.scala 145:96] + node _T_302 = mux(_T_299, _T_300, _T_301) @[lsu_stbuf.scala 145:10] + node _T_303 = mux(_T_288, _T_295, _T_302) @[lsu_stbuf.scala 144:54] + node _T_304 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 144:61] + node _T_305 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 144:86] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[lsu_stbuf.scala 144:70] + node _T_307 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 144:109] + node _T_308 = or(_T_306, _T_307) @[lsu_stbuf.scala 144:90] + node _T_309 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 144:134] + node _T_310 = bits(stbuf_data[1], 7, 0) @[lsu_stbuf.scala 144:155] + node _T_311 = mux(_T_308, _T_309, _T_310) @[lsu_stbuf.scala 144:69] + node _T_312 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 145:27] + node _T_313 = eq(_T_312, UInt<1>("h00")) @[lsu_stbuf.scala 145:11] + node _T_314 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 145:50] + node _T_315 = or(_T_313, _T_314) @[lsu_stbuf.scala 145:31] + node _T_316 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 145:75] + node _T_317 = bits(stbuf_data[1], 7, 0) @[lsu_stbuf.scala 145:96] + node _T_318 = mux(_T_315, _T_316, _T_317) @[lsu_stbuf.scala 145:10] + node _T_319 = mux(_T_304, _T_311, _T_318) @[lsu_stbuf.scala 144:54] + node _T_320 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 144:61] + node _T_321 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 144:86] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[lsu_stbuf.scala 144:70] + node _T_323 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 144:109] + node _T_324 = or(_T_322, _T_323) @[lsu_stbuf.scala 144:90] + node _T_325 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 144:134] + node _T_326 = bits(stbuf_data[2], 7, 0) @[lsu_stbuf.scala 144:155] + node _T_327 = mux(_T_324, _T_325, _T_326) @[lsu_stbuf.scala 144:69] + node _T_328 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 145:27] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[lsu_stbuf.scala 145:11] + node _T_330 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 145:50] + node _T_331 = or(_T_329, _T_330) @[lsu_stbuf.scala 145:31] + node _T_332 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 145:75] + node _T_333 = bits(stbuf_data[2], 7, 0) @[lsu_stbuf.scala 145:96] + node _T_334 = mux(_T_331, _T_332, _T_333) @[lsu_stbuf.scala 145:10] + node _T_335 = mux(_T_320, _T_327, _T_334) @[lsu_stbuf.scala 144:54] + node _T_336 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 144:61] + node _T_337 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 144:86] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_stbuf.scala 144:70] + node _T_339 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 144:109] + node _T_340 = or(_T_338, _T_339) @[lsu_stbuf.scala 144:90] + node _T_341 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 144:134] + node _T_342 = bits(stbuf_data[3], 7, 0) @[lsu_stbuf.scala 144:155] + node _T_343 = mux(_T_340, _T_341, _T_342) @[lsu_stbuf.scala 144:69] + node _T_344 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 145:27] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[lsu_stbuf.scala 145:11] + node _T_346 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 145:50] + node _T_347 = or(_T_345, _T_346) @[lsu_stbuf.scala 145:31] + node _T_348 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 145:75] + node _T_349 = bits(stbuf_data[3], 7, 0) @[lsu_stbuf.scala 145:96] + node _T_350 = mux(_T_347, _T_348, _T_349) @[lsu_stbuf.scala 145:10] + node _T_351 = mux(_T_336, _T_343, _T_350) @[lsu_stbuf.scala 144:54] + datain1[0] <= _T_303 @[lsu_stbuf.scala 144:13] + datain1[1] <= _T_319 @[lsu_stbuf.scala 144:13] + datain1[2] <= _T_335 @[lsu_stbuf.scala 144:13] + datain1[3] <= _T_351 @[lsu_stbuf.scala 144:13] + node _T_352 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 147:61] + node _T_353 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 147:86] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_stbuf.scala 147:70] + node _T_355 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 147:109] + node _T_356 = or(_T_354, _T_355) @[lsu_stbuf.scala 147:90] + node _T_357 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 147:134] + node _T_358 = bits(stbuf_data[0], 15, 8) @[lsu_stbuf.scala 147:156] + node _T_359 = mux(_T_356, _T_357, _T_358) @[lsu_stbuf.scala 147:69] + node _T_360 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 148:27] + node _T_361 = eq(_T_360, UInt<1>("h00")) @[lsu_stbuf.scala 148:11] + node _T_362 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 148:50] + node _T_363 = or(_T_361, _T_362) @[lsu_stbuf.scala 148:31] + node _T_364 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 148:75] + node _T_365 = bits(stbuf_data[0], 15, 8) @[lsu_stbuf.scala 148:97] + node _T_366 = mux(_T_363, _T_364, _T_365) @[lsu_stbuf.scala 148:10] + node _T_367 = mux(_T_352, _T_359, _T_366) @[lsu_stbuf.scala 147:54] + node _T_368 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 147:61] + node _T_369 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 147:86] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[lsu_stbuf.scala 147:70] + node _T_371 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 147:109] + node _T_372 = or(_T_370, _T_371) @[lsu_stbuf.scala 147:90] + node _T_373 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 147:134] + node _T_374 = bits(stbuf_data[1], 15, 8) @[lsu_stbuf.scala 147:156] + node _T_375 = mux(_T_372, _T_373, _T_374) @[lsu_stbuf.scala 147:69] + node _T_376 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 148:27] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[lsu_stbuf.scala 148:11] + node _T_378 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 148:50] + node _T_379 = or(_T_377, _T_378) @[lsu_stbuf.scala 148:31] + node _T_380 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 148:75] + node _T_381 = bits(stbuf_data[1], 15, 8) @[lsu_stbuf.scala 148:97] + node _T_382 = mux(_T_379, _T_380, _T_381) @[lsu_stbuf.scala 148:10] + node _T_383 = mux(_T_368, _T_375, _T_382) @[lsu_stbuf.scala 147:54] + node _T_384 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 147:61] + node _T_385 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 147:86] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[lsu_stbuf.scala 147:70] + node _T_387 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 147:109] + node _T_388 = or(_T_386, _T_387) @[lsu_stbuf.scala 147:90] + node _T_389 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 147:134] + node _T_390 = bits(stbuf_data[2], 15, 8) @[lsu_stbuf.scala 147:156] + node _T_391 = mux(_T_388, _T_389, _T_390) @[lsu_stbuf.scala 147:69] + node _T_392 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 148:27] + node _T_393 = eq(_T_392, UInt<1>("h00")) @[lsu_stbuf.scala 148:11] + node _T_394 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 148:50] + node _T_395 = or(_T_393, _T_394) @[lsu_stbuf.scala 148:31] + node _T_396 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 148:75] + node _T_397 = bits(stbuf_data[2], 15, 8) @[lsu_stbuf.scala 148:97] + node _T_398 = mux(_T_395, _T_396, _T_397) @[lsu_stbuf.scala 148:10] + node _T_399 = mux(_T_384, _T_391, _T_398) @[lsu_stbuf.scala 147:54] + node _T_400 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 147:61] + node _T_401 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 147:86] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[lsu_stbuf.scala 147:70] + node _T_403 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 147:109] + node _T_404 = or(_T_402, _T_403) @[lsu_stbuf.scala 147:90] + node _T_405 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 147:134] + node _T_406 = bits(stbuf_data[3], 15, 8) @[lsu_stbuf.scala 147:156] + node _T_407 = mux(_T_404, _T_405, _T_406) @[lsu_stbuf.scala 147:69] + node _T_408 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 148:27] + node _T_409 = eq(_T_408, UInt<1>("h00")) @[lsu_stbuf.scala 148:11] + node _T_410 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 148:50] + node _T_411 = or(_T_409, _T_410) @[lsu_stbuf.scala 148:31] + node _T_412 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 148:75] + node _T_413 = bits(stbuf_data[3], 15, 8) @[lsu_stbuf.scala 148:97] + node _T_414 = mux(_T_411, _T_412, _T_413) @[lsu_stbuf.scala 148:10] + node _T_415 = mux(_T_400, _T_407, _T_414) @[lsu_stbuf.scala 147:54] + datain2[0] <= _T_367 @[lsu_stbuf.scala 147:13] + datain2[1] <= _T_383 @[lsu_stbuf.scala 147:13] + datain2[2] <= _T_399 @[lsu_stbuf.scala 147:13] + datain2[3] <= _T_415 @[lsu_stbuf.scala 147:13] + node _T_416 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 150:61] + node _T_417 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 150:86] + node _T_418 = eq(_T_417, UInt<1>("h00")) @[lsu_stbuf.scala 150:70] + node _T_419 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 150:109] + node _T_420 = or(_T_418, _T_419) @[lsu_stbuf.scala 150:90] + node _T_421 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 150:134] + node _T_422 = bits(stbuf_data[0], 23, 16) @[lsu_stbuf.scala 150:157] + node _T_423 = mux(_T_420, _T_421, _T_422) @[lsu_stbuf.scala 150:69] + node _T_424 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 151:27] + node _T_425 = eq(_T_424, UInt<1>("h00")) @[lsu_stbuf.scala 151:11] + node _T_426 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 151:50] + node _T_427 = or(_T_425, _T_426) @[lsu_stbuf.scala 151:31] + node _T_428 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 151:75] + node _T_429 = bits(stbuf_data[0], 23, 16) @[lsu_stbuf.scala 151:98] + node _T_430 = mux(_T_427, _T_428, _T_429) @[lsu_stbuf.scala 151:10] + node _T_431 = mux(_T_416, _T_423, _T_430) @[lsu_stbuf.scala 150:54] + node _T_432 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 150:61] + node _T_433 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 150:86] + node _T_434 = eq(_T_433, UInt<1>("h00")) @[lsu_stbuf.scala 150:70] + node _T_435 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 150:109] + node _T_436 = or(_T_434, _T_435) @[lsu_stbuf.scala 150:90] + node _T_437 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 150:134] + node _T_438 = bits(stbuf_data[1], 23, 16) @[lsu_stbuf.scala 150:157] + node _T_439 = mux(_T_436, _T_437, _T_438) @[lsu_stbuf.scala 150:69] + node _T_440 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 151:27] + node _T_441 = eq(_T_440, UInt<1>("h00")) @[lsu_stbuf.scala 151:11] + node _T_442 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 151:50] + node _T_443 = or(_T_441, _T_442) @[lsu_stbuf.scala 151:31] + node _T_444 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 151:75] + node _T_445 = bits(stbuf_data[1], 23, 16) @[lsu_stbuf.scala 151:98] + node _T_446 = mux(_T_443, _T_444, _T_445) @[lsu_stbuf.scala 151:10] + node _T_447 = mux(_T_432, _T_439, _T_446) @[lsu_stbuf.scala 150:54] + node _T_448 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 150:61] + node _T_449 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 150:86] + node _T_450 = eq(_T_449, UInt<1>("h00")) @[lsu_stbuf.scala 150:70] + node _T_451 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 150:109] + node _T_452 = or(_T_450, _T_451) @[lsu_stbuf.scala 150:90] + node _T_453 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 150:134] + node _T_454 = bits(stbuf_data[2], 23, 16) @[lsu_stbuf.scala 150:157] + node _T_455 = mux(_T_452, _T_453, _T_454) @[lsu_stbuf.scala 150:69] + node _T_456 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 151:27] + node _T_457 = eq(_T_456, UInt<1>("h00")) @[lsu_stbuf.scala 151:11] + node _T_458 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 151:50] + node _T_459 = or(_T_457, _T_458) @[lsu_stbuf.scala 151:31] + node _T_460 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 151:75] + node _T_461 = bits(stbuf_data[2], 23, 16) @[lsu_stbuf.scala 151:98] + node _T_462 = mux(_T_459, _T_460, _T_461) @[lsu_stbuf.scala 151:10] + node _T_463 = mux(_T_448, _T_455, _T_462) @[lsu_stbuf.scala 150:54] + node _T_464 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 150:61] + node _T_465 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 150:86] + node _T_466 = eq(_T_465, UInt<1>("h00")) @[lsu_stbuf.scala 150:70] + node _T_467 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 150:109] + node _T_468 = or(_T_466, _T_467) @[lsu_stbuf.scala 150:90] + node _T_469 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 150:134] + node _T_470 = bits(stbuf_data[3], 23, 16) @[lsu_stbuf.scala 150:157] + node _T_471 = mux(_T_468, _T_469, _T_470) @[lsu_stbuf.scala 150:69] + node _T_472 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 151:27] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[lsu_stbuf.scala 151:11] + node _T_474 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 151:50] + node _T_475 = or(_T_473, _T_474) @[lsu_stbuf.scala 151:31] + node _T_476 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 151:75] + node _T_477 = bits(stbuf_data[3], 23, 16) @[lsu_stbuf.scala 151:98] + node _T_478 = mux(_T_475, _T_476, _T_477) @[lsu_stbuf.scala 151:10] + node _T_479 = mux(_T_464, _T_471, _T_478) @[lsu_stbuf.scala 150:54] + datain3[0] <= _T_431 @[lsu_stbuf.scala 150:13] + datain3[1] <= _T_447 @[lsu_stbuf.scala 150:13] + datain3[2] <= _T_463 @[lsu_stbuf.scala 150:13] + datain3[3] <= _T_479 @[lsu_stbuf.scala 150:13] + node _T_480 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 153:61] + node _T_481 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 153:86] + node _T_482 = eq(_T_481, UInt<1>("h00")) @[lsu_stbuf.scala 153:70] + node _T_483 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 153:109] + node _T_484 = or(_T_482, _T_483) @[lsu_stbuf.scala 153:90] + node _T_485 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 153:134] + node _T_486 = bits(stbuf_data[0], 31, 24) @[lsu_stbuf.scala 153:157] + node _T_487 = mux(_T_484, _T_485, _T_486) @[lsu_stbuf.scala 153:69] + node _T_488 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 154:27] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[lsu_stbuf.scala 154:11] + node _T_490 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 154:50] + node _T_491 = or(_T_489, _T_490) @[lsu_stbuf.scala 154:31] + node _T_492 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 154:75] + node _T_493 = bits(stbuf_data[0], 31, 24) @[lsu_stbuf.scala 154:98] + node _T_494 = mux(_T_491, _T_492, _T_493) @[lsu_stbuf.scala 154:10] + node _T_495 = mux(_T_480, _T_487, _T_494) @[lsu_stbuf.scala 153:54] + node _T_496 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 153:61] + node _T_497 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 153:86] + node _T_498 = eq(_T_497, UInt<1>("h00")) @[lsu_stbuf.scala 153:70] + node _T_499 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 153:109] + node _T_500 = or(_T_498, _T_499) @[lsu_stbuf.scala 153:90] + node _T_501 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 153:134] + node _T_502 = bits(stbuf_data[1], 31, 24) @[lsu_stbuf.scala 153:157] + node _T_503 = mux(_T_500, _T_501, _T_502) @[lsu_stbuf.scala 153:69] + node _T_504 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 154:27] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[lsu_stbuf.scala 154:11] + node _T_506 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 154:50] + node _T_507 = or(_T_505, _T_506) @[lsu_stbuf.scala 154:31] + node _T_508 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 154:75] + node _T_509 = bits(stbuf_data[1], 31, 24) @[lsu_stbuf.scala 154:98] + node _T_510 = mux(_T_507, _T_508, _T_509) @[lsu_stbuf.scala 154:10] + node _T_511 = mux(_T_496, _T_503, _T_510) @[lsu_stbuf.scala 153:54] + node _T_512 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 153:61] + node _T_513 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 153:86] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[lsu_stbuf.scala 153:70] + node _T_515 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 153:109] + node _T_516 = or(_T_514, _T_515) @[lsu_stbuf.scala 153:90] + node _T_517 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 153:134] + node _T_518 = bits(stbuf_data[2], 31, 24) @[lsu_stbuf.scala 153:157] + node _T_519 = mux(_T_516, _T_517, _T_518) @[lsu_stbuf.scala 153:69] + node _T_520 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 154:27] + node _T_521 = eq(_T_520, UInt<1>("h00")) @[lsu_stbuf.scala 154:11] + node _T_522 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 154:50] + node _T_523 = or(_T_521, _T_522) @[lsu_stbuf.scala 154:31] + node _T_524 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 154:75] + node _T_525 = bits(stbuf_data[2], 31, 24) @[lsu_stbuf.scala 154:98] + node _T_526 = mux(_T_523, _T_524, _T_525) @[lsu_stbuf.scala 154:10] + node _T_527 = mux(_T_512, _T_519, _T_526) @[lsu_stbuf.scala 153:54] + node _T_528 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 153:61] + node _T_529 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 153:86] + node _T_530 = eq(_T_529, UInt<1>("h00")) @[lsu_stbuf.scala 153:70] + node _T_531 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 153:109] + node _T_532 = or(_T_530, _T_531) @[lsu_stbuf.scala 153:90] + node _T_533 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 153:134] + node _T_534 = bits(stbuf_data[3], 31, 24) @[lsu_stbuf.scala 153:157] + node _T_535 = mux(_T_532, _T_533, _T_534) @[lsu_stbuf.scala 153:69] + node _T_536 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 154:27] + node _T_537 = eq(_T_536, UInt<1>("h00")) @[lsu_stbuf.scala 154:11] + node _T_538 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 154:50] + node _T_539 = or(_T_537, _T_538) @[lsu_stbuf.scala 154:31] + node _T_540 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 154:75] + node _T_541 = bits(stbuf_data[3], 31, 24) @[lsu_stbuf.scala 154:98] + node _T_542 = mux(_T_539, _T_540, _T_541) @[lsu_stbuf.scala 154:10] + node _T_543 = mux(_T_528, _T_535, _T_542) @[lsu_stbuf.scala 153:54] + datain4[0] <= _T_495 @[lsu_stbuf.scala 153:13] + datain4[1] <= _T_511 @[lsu_stbuf.scala 153:13] + datain4[2] <= _T_527 @[lsu_stbuf.scala 153:13] + datain4[3] <= _T_543 @[lsu_stbuf.scala 153:13] + node _T_544 = cat(datain2[0], datain1[0]) @[Cat.scala 29:58] + node _T_545 = cat(datain4[0], datain3[0]) @[Cat.scala 29:58] + node _T_546 = cat(_T_545, _T_544) @[Cat.scala 29:58] + node _T_547 = cat(datain2[1], datain1[1]) @[Cat.scala 29:58] + node _T_548 = cat(datain4[1], datain3[1]) @[Cat.scala 29:58] + node _T_549 = cat(_T_548, _T_547) @[Cat.scala 29:58] + node _T_550 = cat(datain2[2], datain1[2]) @[Cat.scala 29:58] + node _T_551 = cat(datain4[2], datain3[2]) @[Cat.scala 29:58] + node _T_552 = cat(_T_551, _T_550) @[Cat.scala 29:58] + node _T_553 = cat(datain2[3], datain1[3]) @[Cat.scala 29:58] + node _T_554 = cat(datain4[3], datain3[3]) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_553) @[Cat.scala 29:58] + stbuf_datain[0] <= _T_546 @[lsu_stbuf.scala 156:18] + stbuf_datain[1] <= _T_549 @[lsu_stbuf.scala 156:18] + stbuf_datain[2] <= _T_552 @[lsu_stbuf.scala 156:18] + stbuf_datain[3] <= _T_555 @[lsu_stbuf.scala 156:18] + node _T_556 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 160:30] + node _T_557 = bits(_T_556, 0, 0) @[lsu_stbuf.scala 160:40] + node _T_558 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 160:58] + node _T_559 = mux(_T_557, UInt<1>("h01"), _T_558) @[lsu_stbuf.scala 160:18] + node _T_560 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 160:77] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[lsu_stbuf.scala 160:65] + node _T_562 = and(_T_559, _T_561) @[lsu_stbuf.scala 160:63] + reg _T_563 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 160:14] + _T_563 <= _T_562 @[lsu_stbuf.scala 160:14] + node _T_564 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 160:30] + node _T_565 = bits(_T_564, 0, 0) @[lsu_stbuf.scala 160:40] + node _T_566 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 160:58] + node _T_567 = mux(_T_565, UInt<1>("h01"), _T_566) @[lsu_stbuf.scala 160:18] + node _T_568 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 160:77] + node _T_569 = eq(_T_568, UInt<1>("h00")) @[lsu_stbuf.scala 160:65] + node _T_570 = and(_T_567, _T_569) @[lsu_stbuf.scala 160:63] + reg _T_571 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 160:14] + _T_571 <= _T_570 @[lsu_stbuf.scala 160:14] + node _T_572 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 160:30] + node _T_573 = bits(_T_572, 0, 0) @[lsu_stbuf.scala 160:40] + node _T_574 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 160:58] + node _T_575 = mux(_T_573, UInt<1>("h01"), _T_574) @[lsu_stbuf.scala 160:18] + node _T_576 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 160:77] + node _T_577 = eq(_T_576, UInt<1>("h00")) @[lsu_stbuf.scala 160:65] + node _T_578 = and(_T_575, _T_577) @[lsu_stbuf.scala 160:63] + reg _T_579 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 160:14] + _T_579 <= _T_578 @[lsu_stbuf.scala 160:14] + node _T_580 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 160:30] + node _T_581 = bits(_T_580, 0, 0) @[lsu_stbuf.scala 160:40] + node _T_582 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 160:58] + node _T_583 = mux(_T_581, UInt<1>("h01"), _T_582) @[lsu_stbuf.scala 160:18] + node _T_584 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 160:77] + node _T_585 = eq(_T_584, UInt<1>("h00")) @[lsu_stbuf.scala 160:65] + node _T_586 = and(_T_583, _T_585) @[lsu_stbuf.scala 160:63] + reg _T_587 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 160:14] + _T_587 <= _T_586 @[lsu_stbuf.scala 160:14] + node _T_588 = cat(_T_587, _T_579) @[Cat.scala 29:58] + node _T_589 = cat(_T_588, _T_571) @[Cat.scala 29:58] + node _T_590 = cat(_T_589, _T_563) @[Cat.scala 29:58] + stbuf_vld <= _T_590 @[lsu_stbuf.scala 159:15] + node _T_591 = bits(stbuf_dma_kill_en, 0, 0) @[lsu_stbuf.scala 163:36] + node _T_592 = bits(_T_591, 0, 0) @[lsu_stbuf.scala 163:40] + node _T_593 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 163:67] + node _T_594 = mux(_T_592, UInt<1>("h01"), _T_593) @[lsu_stbuf.scala 163:18] + node _T_595 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 163:86] + node _T_596 = eq(_T_595, UInt<1>("h00")) @[lsu_stbuf.scala 163:74] + node _T_597 = and(_T_594, _T_596) @[lsu_stbuf.scala 163:72] + reg _T_598 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:14] + _T_598 <= _T_597 @[lsu_stbuf.scala 163:14] + node _T_599 = bits(stbuf_dma_kill_en, 1, 1) @[lsu_stbuf.scala 163:36] + node _T_600 = bits(_T_599, 0, 0) @[lsu_stbuf.scala 163:40] + node _T_601 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 163:67] + node _T_602 = mux(_T_600, UInt<1>("h01"), _T_601) @[lsu_stbuf.scala 163:18] + node _T_603 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 163:86] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[lsu_stbuf.scala 163:74] + node _T_605 = and(_T_602, _T_604) @[lsu_stbuf.scala 163:72] + reg _T_606 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:14] + _T_606 <= _T_605 @[lsu_stbuf.scala 163:14] + node _T_607 = bits(stbuf_dma_kill_en, 2, 2) @[lsu_stbuf.scala 163:36] + node _T_608 = bits(_T_607, 0, 0) @[lsu_stbuf.scala 163:40] + node _T_609 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 163:67] + node _T_610 = mux(_T_608, UInt<1>("h01"), _T_609) @[lsu_stbuf.scala 163:18] + node _T_611 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 163:86] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[lsu_stbuf.scala 163:74] + node _T_613 = and(_T_610, _T_612) @[lsu_stbuf.scala 163:72] + reg _T_614 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:14] + _T_614 <= _T_613 @[lsu_stbuf.scala 163:14] + node _T_615 = bits(stbuf_dma_kill_en, 3, 3) @[lsu_stbuf.scala 163:36] + node _T_616 = bits(_T_615, 0, 0) @[lsu_stbuf.scala 163:40] + node _T_617 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 163:67] + node _T_618 = mux(_T_616, UInt<1>("h01"), _T_617) @[lsu_stbuf.scala 163:18] + node _T_619 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 163:86] + node _T_620 = eq(_T_619, UInt<1>("h00")) @[lsu_stbuf.scala 163:74] + node _T_621 = and(_T_618, _T_620) @[lsu_stbuf.scala 163:72] + reg _T_622 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:14] + _T_622 <= _T_621 @[lsu_stbuf.scala 163:14] + node _T_623 = cat(_T_622, _T_614) @[Cat.scala 29:58] + node _T_624 = cat(_T_623, _T_606) @[Cat.scala 29:58] + node _T_625 = cat(_T_624, _T_598) @[Cat.scala 29:58] + stbuf_dma_kill <= _T_625 @[lsu_stbuf.scala 162:20] + node _T_626 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 166:30] + node _T_627 = bits(_T_626, 0, 0) @[lsu_stbuf.scala 166:40] + node _T_628 = mux(_T_627, stbuf_byteenin[0], stbuf_byteen[0]) @[lsu_stbuf.scala 166:18] + node _T_629 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 166:127] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[lsu_stbuf.scala 166:115] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_633 = and(_T_628, _T_632) @[lsu_stbuf.scala 166:80] + reg _T_634 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 166:14] + _T_634 <= _T_633 @[lsu_stbuf.scala 166:14] + node _T_635 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 166:30] + node _T_636 = bits(_T_635, 0, 0) @[lsu_stbuf.scala 166:40] + node _T_637 = mux(_T_636, stbuf_byteenin[1], stbuf_byteen[1]) @[lsu_stbuf.scala 166:18] + node _T_638 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 166:127] + node _T_639 = eq(_T_638, UInt<1>("h00")) @[lsu_stbuf.scala 166:115] + node _T_640 = bits(_T_639, 0, 0) @[Bitwise.scala 72:15] + node _T_641 = mux(_T_640, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_642 = and(_T_637, _T_641) @[lsu_stbuf.scala 166:80] + reg _T_643 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 166:14] + _T_643 <= _T_642 @[lsu_stbuf.scala 166:14] + node _T_644 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 166:30] + node _T_645 = bits(_T_644, 0, 0) @[lsu_stbuf.scala 166:40] + node _T_646 = mux(_T_645, stbuf_byteenin[2], stbuf_byteen[2]) @[lsu_stbuf.scala 166:18] + node _T_647 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 166:127] + node _T_648 = eq(_T_647, UInt<1>("h00")) @[lsu_stbuf.scala 166:115] + node _T_649 = bits(_T_648, 0, 0) @[Bitwise.scala 72:15] + node _T_650 = mux(_T_649, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_651 = and(_T_646, _T_650) @[lsu_stbuf.scala 166:80] + reg _T_652 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 166:14] + _T_652 <= _T_651 @[lsu_stbuf.scala 166:14] + node _T_653 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 166:30] + node _T_654 = bits(_T_653, 0, 0) @[lsu_stbuf.scala 166:40] + node _T_655 = mux(_T_654, stbuf_byteenin[3], stbuf_byteen[3]) @[lsu_stbuf.scala 166:18] + node _T_656 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 166:127] + node _T_657 = eq(_T_656, UInt<1>("h00")) @[lsu_stbuf.scala 166:115] + node _T_658 = bits(_T_657, 0, 0) @[Bitwise.scala 72:15] + node _T_659 = mux(_T_658, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_660 = and(_T_655, _T_659) @[lsu_stbuf.scala 166:80] + reg _T_661 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 166:14] + _T_661 <= _T_660 @[lsu_stbuf.scala 166:14] + stbuf_byteen[0] <= _T_634 @[lsu_stbuf.scala 165:18] + stbuf_byteen[1] <= _T_643 @[lsu_stbuf.scala 165:18] + stbuf_byteen[2] <= _T_652 @[lsu_stbuf.scala 165:18] + stbuf_byteen[3] <= _T_661 @[lsu_stbuf.scala 165:18] + node _T_662 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 169:59] + node _T_663 = bits(_T_662, 0, 0) @[lsu_stbuf.scala 169:69] + inst rvclkhdr of rvclkhdr_8 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_663 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_664 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_663 : @[Reg.scala 28:19] + _T_664 <= stbuf_addrin[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_addr[0] <= _T_664 @[lsu_stbuf.scala 169:21] + node _T_665 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 170:59] + node _T_666 = bits(_T_665, 0, 0) @[lsu_stbuf.scala 170:69] + inst rvclkhdr_1 of rvclkhdr_9 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_666 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_667 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_666 : @[Reg.scala 28:19] + _T_667 <= stbuf_datain[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_data[0] <= _T_667 @[lsu_stbuf.scala 170:21] + node _T_668 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 169:59] + node _T_669 = bits(_T_668, 0, 0) @[lsu_stbuf.scala 169:69] + inst rvclkhdr_2 of rvclkhdr_10 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_669 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_670 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_669 : @[Reg.scala 28:19] + _T_670 <= stbuf_addrin[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_addr[1] <= _T_670 @[lsu_stbuf.scala 169:21] + node _T_671 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 170:59] + node _T_672 = bits(_T_671, 0, 0) @[lsu_stbuf.scala 170:69] + inst rvclkhdr_3 of rvclkhdr_11 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_672 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_673 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_672 : @[Reg.scala 28:19] + _T_673 <= stbuf_datain[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_data[1] <= _T_673 @[lsu_stbuf.scala 170:21] + node _T_674 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 169:59] + node _T_675 = bits(_T_674, 0, 0) @[lsu_stbuf.scala 169:69] + inst rvclkhdr_4 of rvclkhdr_12 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_675 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_676 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_675 : @[Reg.scala 28:19] + _T_676 <= stbuf_addrin[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_addr[2] <= _T_676 @[lsu_stbuf.scala 169:21] + node _T_677 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 170:59] + node _T_678 = bits(_T_677, 0, 0) @[lsu_stbuf.scala 170:69] + inst rvclkhdr_5 of rvclkhdr_13 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_678 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_679 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_678 : @[Reg.scala 28:19] + _T_679 <= stbuf_datain[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_data[2] <= _T_679 @[lsu_stbuf.scala 170:21] + node _T_680 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 169:59] + node _T_681 = bits(_T_680, 0, 0) @[lsu_stbuf.scala 169:69] + inst rvclkhdr_6 of rvclkhdr_14 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_681 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_682 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_681 : @[Reg.scala 28:19] + _T_682 <= stbuf_addrin[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_addr[3] <= _T_682 @[lsu_stbuf.scala 169:21] + node _T_683 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 170:59] + node _T_684 = bits(_T_683, 0, 0) @[lsu_stbuf.scala 170:69] + inst rvclkhdr_7 of rvclkhdr_15 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_684 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_685 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_684 : @[Reg.scala 28:19] + _T_685 <= stbuf_datain[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_data[3] <= _T_685 @[lsu_stbuf.scala 170:21] + node _T_686 = dshr(stbuf_vld, RdPtr) @[lsu_stbuf.scala 183:43] + node _T_687 = bits(_T_686, 0, 0) @[lsu_stbuf.scala 183:43] + node _T_688 = dshr(stbuf_dma_kill, RdPtr) @[lsu_stbuf.scala 183:67] + node _T_689 = bits(_T_688, 0, 0) @[lsu_stbuf.scala 183:67] + node _T_690 = and(_T_687, _T_689) @[lsu_stbuf.scala 183:51] + io.stbuf_reqvld_flushed_any <= _T_690 @[lsu_stbuf.scala 183:31] + node _T_691 = dshr(stbuf_vld, RdPtr) @[lsu_stbuf.scala 184:36] + node _T_692 = bits(_T_691, 0, 0) @[lsu_stbuf.scala 184:36] + node _T_693 = dshr(stbuf_dma_kill, RdPtr) @[lsu_stbuf.scala 184:61] + node _T_694 = bits(_T_693, 0, 0) @[lsu_stbuf.scala 184:61] + node _T_695 = eq(_T_694, UInt<1>("h00")) @[lsu_stbuf.scala 184:46] + node _T_696 = and(_T_692, _T_695) @[lsu_stbuf.scala 184:44] + node _T_697 = orr(stbuf_dma_kill_en) @[lsu_stbuf.scala 184:91] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[lsu_stbuf.scala 184:71] + node _T_699 = and(_T_696, _T_698) @[lsu_stbuf.scala 184:69] + io.stbuf_reqvld_any <= _T_699 @[lsu_stbuf.scala 184:24] + io.stbuf_addr_any <= stbuf_addr[RdPtr] @[lsu_stbuf.scala 185:22] + io.stbuf_data_any <= stbuf_data[RdPtr] @[lsu_stbuf.scala 186:22] + node _T_700 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[lsu_stbuf.scala 188:44] + node _T_701 = and(io.ldst_stbuf_reqvld_r, _T_700) @[lsu_stbuf.scala 188:42] + node _T_702 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[lsu_stbuf.scala 188:88] + node _T_703 = eq(_T_702, UInt<1>("h00")) @[lsu_stbuf.scala 188:66] + node _T_704 = and(_T_701, _T_703) @[lsu_stbuf.scala 188:64] + node _T_705 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[lsu_stbuf.scala 189:30] + node _T_706 = and(store_coalesce_hi_r, store_coalesce_lo_r) @[lsu_stbuf.scala 189:76] + node _T_707 = eq(_T_706, UInt<1>("h00")) @[lsu_stbuf.scala 189:54] + node _T_708 = and(_T_705, _T_707) @[lsu_stbuf.scala 189:52] + node _T_709 = or(_T_704, _T_708) @[lsu_stbuf.scala 188:113] + node WrPtrEn = bits(_T_709, 0, 0) @[lsu_stbuf.scala 189:101] + node _T_710 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[lsu_stbuf.scala 190:46] + node _T_711 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[lsu_stbuf.scala 190:91] + node _T_712 = eq(_T_711, UInt<1>("h00")) @[lsu_stbuf.scala 190:69] + node _T_713 = and(_T_710, _T_712) @[lsu_stbuf.scala 190:67] + node _T_714 = bits(_T_713, 0, 0) @[lsu_stbuf.scala 190:115] + node NxtWrPtr = mux(_T_714, WrPtrPlus2, WrPtrPlus1) @[lsu_stbuf.scala 190:21] + node RdPtrEn = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 191:42] + reg _T_715 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when WrPtrEn : @[Reg.scala 28:19] + _T_715 <= NxtWrPtr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + WrPtr <= _T_715 @[lsu_stbuf.scala 194:41] + reg _T_716 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when RdPtrEn : @[Reg.scala 28:19] + _T_716 <= RdPtrPlus1 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + RdPtr <= _T_716 @[lsu_stbuf.scala 195:41] + node _T_717 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 197:86] + node _T_718 = cat(UInt<3>("h00"), _T_717) @[Cat.scala 29:58] + node _T_719 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 197:86] + node _T_720 = cat(UInt<3>("h00"), _T_719) @[Cat.scala 29:58] + node _T_721 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 197:86] + node _T_722 = cat(UInt<3>("h00"), _T_721) @[Cat.scala 29:58] + node _T_723 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 197:86] + node _T_724 = cat(UInt<3>("h00"), _T_723) @[Cat.scala 29:58] + wire _T_725 : UInt<4>[4] @[lsu_stbuf.scala 197:59] + _T_725[0] <= _T_718 @[lsu_stbuf.scala 197:59] + _T_725[1] <= _T_720 @[lsu_stbuf.scala 197:59] + _T_725[2] <= _T_722 @[lsu_stbuf.scala 197:59] + _T_725[3] <= _T_724 @[lsu_stbuf.scala 197:59] + node _T_726 = add(_T_725[0], _T_725[1]) @[lsu_stbuf.scala 197:101] + node _T_727 = tail(_T_726, 1) @[lsu_stbuf.scala 197:101] + node _T_728 = add(_T_727, _T_725[2]) @[lsu_stbuf.scala 197:101] + node _T_729 = tail(_T_728, 1) @[lsu_stbuf.scala 197:101] + node _T_730 = add(_T_729, _T_725[3]) @[lsu_stbuf.scala 197:101] + node stbuf_numvld_any = tail(_T_730, 1) @[lsu_stbuf.scala 197:101] + node _T_731 = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 198:39] + node _T_732 = and(_T_731, io.addr_in_dccm_m) @[lsu_stbuf.scala 198:65] + node _T_733 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 198:87] + node isdccmst_m = and(_T_732, _T_733) @[lsu_stbuf.scala 198:85] + node _T_734 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 199:39] + node _T_735 = and(_T_734, io.addr_in_dccm_r) @[lsu_stbuf.scala 199:65] + node _T_736 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 199:87] + node isdccmst_r = and(_T_735, _T_736) @[lsu_stbuf.scala 199:85] + node _T_737 = cat(UInt<1>("h00"), isdccmst_m) @[Cat.scala 29:58] + node _T_738 = and(isdccmst_m, io.ldst_dual_m) @[lsu_stbuf.scala 201:62] + node _T_739 = dshl(_T_737, _T_738) @[lsu_stbuf.scala 201:47] + stbuf_specvld_m <= _T_739 @[lsu_stbuf.scala 201:19] + node _T_740 = cat(UInt<1>("h00"), isdccmst_r) @[Cat.scala 29:58] + node _T_741 = and(isdccmst_r, io.ldst_dual_r) @[lsu_stbuf.scala 202:62] + node _T_742 = dshl(_T_740, _T_741) @[lsu_stbuf.scala 202:47] + stbuf_specvld_r <= _T_742 @[lsu_stbuf.scala 202:19] + node _T_743 = cat(UInt<2>("h00"), stbuf_specvld_m) @[Cat.scala 29:58] + node _T_744 = add(stbuf_numvld_any, _T_743) @[lsu_stbuf.scala 203:44] + node _T_745 = tail(_T_744, 1) @[lsu_stbuf.scala 203:44] + node _T_746 = cat(UInt<2>("h00"), stbuf_specvld_r) @[Cat.scala 29:58] + node _T_747 = add(_T_745, _T_746) @[lsu_stbuf.scala 203:78] + node stbuf_specvld_any = tail(_T_747, 1) @[lsu_stbuf.scala 203:78] + node _T_748 = eq(io.ldst_dual_d, UInt<1>("h00")) @[lsu_stbuf.scala 205:34] + node _T_749 = and(_T_748, io.dec_lsu_valid_raw_d) @[lsu_stbuf.scala 205:50] + node _T_750 = bits(_T_749, 0, 0) @[lsu_stbuf.scala 205:76] + node _T_751 = geq(stbuf_specvld_any, UInt<3>("h04")) @[lsu_stbuf.scala 205:102] + node _T_752 = geq(stbuf_specvld_any, UInt<2>("h03")) @[lsu_stbuf.scala 205:143] + node _T_753 = mux(_T_750, _T_751, _T_752) @[lsu_stbuf.scala 205:32] + io.lsu_stbuf_full_any <= _T_753 @[lsu_stbuf.scala 205:26] + node _T_754 = eq(stbuf_numvld_any, UInt<1>("h00")) @[lsu_stbuf.scala 206:46] + io.lsu_stbuf_empty_any <= _T_754 @[lsu_stbuf.scala 206:26] + node _T_755 = bits(io.end_addr_m, 15, 2) @[lsu_stbuf.scala 208:32] + cmpaddr_hi_m <= _T_755 @[lsu_stbuf.scala 208:16] + node _T_756 = bits(io.lsu_addr_m, 15, 2) @[lsu_stbuf.scala 209:33] + cmpaddr_lo_m <= _T_756 @[lsu_stbuf.scala 209:17] + node _T_757 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 212:73] + node _T_758 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 212:131] + node _T_759 = eq(_T_757, _T_758) @[lsu_stbuf.scala 212:115] + node _T_760 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 212:150] + node _T_761 = and(_T_759, _T_760) @[lsu_stbuf.scala 212:139] + node _T_762 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 212:171] + node _T_763 = eq(_T_762, UInt<1>("h00")) @[lsu_stbuf.scala 212:156] + node _T_764 = and(_T_761, _T_763) @[lsu_stbuf.scala 212:154] + node _T_765 = and(_T_764, io.addr_in_dccm_m) @[lsu_stbuf.scala 212:175] + node _T_766 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 212:73] + node _T_767 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 212:131] + node _T_768 = eq(_T_766, _T_767) @[lsu_stbuf.scala 212:115] + node _T_769 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 212:150] + node _T_770 = and(_T_768, _T_769) @[lsu_stbuf.scala 212:139] + node _T_771 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 212:171] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[lsu_stbuf.scala 212:156] + node _T_773 = and(_T_770, _T_772) @[lsu_stbuf.scala 212:154] + node _T_774 = and(_T_773, io.addr_in_dccm_m) @[lsu_stbuf.scala 212:175] + node _T_775 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 212:73] + node _T_776 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 212:131] + node _T_777 = eq(_T_775, _T_776) @[lsu_stbuf.scala 212:115] + node _T_778 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 212:150] + node _T_779 = and(_T_777, _T_778) @[lsu_stbuf.scala 212:139] + node _T_780 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 212:171] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[lsu_stbuf.scala 212:156] + node _T_782 = and(_T_779, _T_781) @[lsu_stbuf.scala 212:154] + node _T_783 = and(_T_782, io.addr_in_dccm_m) @[lsu_stbuf.scala 212:175] + node _T_784 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 212:73] + node _T_785 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 212:131] + node _T_786 = eq(_T_784, _T_785) @[lsu_stbuf.scala 212:115] + node _T_787 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 212:150] + node _T_788 = and(_T_786, _T_787) @[lsu_stbuf.scala 212:139] + node _T_789 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 212:171] + node _T_790 = eq(_T_789, UInt<1>("h00")) @[lsu_stbuf.scala 212:156] + node _T_791 = and(_T_788, _T_790) @[lsu_stbuf.scala 212:154] + node _T_792 = and(_T_791, io.addr_in_dccm_m) @[lsu_stbuf.scala 212:175] + node _T_793 = cat(_T_792, _T_783) @[Cat.scala 29:58] + node _T_794 = cat(_T_793, _T_774) @[Cat.scala 29:58] + node stbuf_match_hi = cat(_T_794, _T_765) @[Cat.scala 29:58] + node _T_795 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 213:73] + node _T_796 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 213:131] + node _T_797 = eq(_T_795, _T_796) @[lsu_stbuf.scala 213:115] + node _T_798 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 213:150] + node _T_799 = and(_T_797, _T_798) @[lsu_stbuf.scala 213:139] + node _T_800 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 213:171] + node _T_801 = eq(_T_800, UInt<1>("h00")) @[lsu_stbuf.scala 213:156] + node _T_802 = and(_T_799, _T_801) @[lsu_stbuf.scala 213:154] + node _T_803 = and(_T_802, io.addr_in_dccm_m) @[lsu_stbuf.scala 213:175] + node _T_804 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 213:73] + node _T_805 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 213:131] + node _T_806 = eq(_T_804, _T_805) @[lsu_stbuf.scala 213:115] + node _T_807 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 213:150] + node _T_808 = and(_T_806, _T_807) @[lsu_stbuf.scala 213:139] + node _T_809 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 213:171] + node _T_810 = eq(_T_809, UInt<1>("h00")) @[lsu_stbuf.scala 213:156] + node _T_811 = and(_T_808, _T_810) @[lsu_stbuf.scala 213:154] + node _T_812 = and(_T_811, io.addr_in_dccm_m) @[lsu_stbuf.scala 213:175] + node _T_813 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 213:73] + node _T_814 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 213:131] + node _T_815 = eq(_T_813, _T_814) @[lsu_stbuf.scala 213:115] + node _T_816 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 213:150] + node _T_817 = and(_T_815, _T_816) @[lsu_stbuf.scala 213:139] + node _T_818 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 213:171] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[lsu_stbuf.scala 213:156] + node _T_820 = and(_T_817, _T_819) @[lsu_stbuf.scala 213:154] + node _T_821 = and(_T_820, io.addr_in_dccm_m) @[lsu_stbuf.scala 213:175] + node _T_822 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 213:73] + node _T_823 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 213:131] + node _T_824 = eq(_T_822, _T_823) @[lsu_stbuf.scala 213:115] + node _T_825 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 213:150] + node _T_826 = and(_T_824, _T_825) @[lsu_stbuf.scala 213:139] + node _T_827 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 213:171] + node _T_828 = eq(_T_827, UInt<1>("h00")) @[lsu_stbuf.scala 213:156] + node _T_829 = and(_T_826, _T_828) @[lsu_stbuf.scala 213:154] + node _T_830 = and(_T_829, io.addr_in_dccm_m) @[lsu_stbuf.scala 213:175] + node _T_831 = cat(_T_830, _T_821) @[Cat.scala 29:58] + node _T_832 = cat(_T_831, _T_812) @[Cat.scala 29:58] + node stbuf_match_lo = cat(_T_832, _T_803) @[Cat.scala 29:58] + node _T_833 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 214:74] + node _T_834 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 214:94] + node _T_835 = or(_T_833, _T_834) @[lsu_stbuf.scala 214:78] + node _T_836 = and(_T_835, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 214:99] + node _T_837 = and(_T_836, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 214:120] + node _T_838 = and(_T_837, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 214:144] + node _T_839 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 214:74] + node _T_840 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 214:94] + node _T_841 = or(_T_839, _T_840) @[lsu_stbuf.scala 214:78] + node _T_842 = and(_T_841, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 214:99] + node _T_843 = and(_T_842, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 214:120] + node _T_844 = and(_T_843, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 214:144] + node _T_845 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 214:74] + node _T_846 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 214:94] + node _T_847 = or(_T_845, _T_846) @[lsu_stbuf.scala 214:78] + node _T_848 = and(_T_847, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 214:99] + node _T_849 = and(_T_848, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 214:120] + node _T_850 = and(_T_849, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 214:144] + node _T_851 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 214:74] + node _T_852 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 214:94] + node _T_853 = or(_T_851, _T_852) @[lsu_stbuf.scala 214:78] + node _T_854 = and(_T_853, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 214:99] + node _T_855 = and(_T_854, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 214:120] + node _T_856 = and(_T_855, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 214:144] + node _T_857 = cat(_T_856, _T_850) @[Cat.scala 29:58] + node _T_858 = cat(_T_857, _T_844) @[Cat.scala 29:58] + node _T_859 = cat(_T_858, _T_838) @[Cat.scala 29:58] + stbuf_dma_kill_en <= _T_859 @[lsu_stbuf.scala 214:21] + node _T_860 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 217:112] + node _T_861 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 217:133] + node _T_862 = and(_T_860, _T_861) @[lsu_stbuf.scala 217:116] + node _T_863 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_0 = and(_T_862, _T_863) @[lsu_stbuf.scala 217:137] + node _T_864 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 217:112] + node _T_865 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 217:133] + node _T_866 = and(_T_864, _T_865) @[lsu_stbuf.scala 217:116] + node _T_867 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_1 = and(_T_866, _T_867) @[lsu_stbuf.scala 217:137] + node _T_868 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 217:112] + node _T_869 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 217:133] + node _T_870 = and(_T_868, _T_869) @[lsu_stbuf.scala 217:116] + node _T_871 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_2 = and(_T_870, _T_871) @[lsu_stbuf.scala 217:137] + node _T_872 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 217:112] + node _T_873 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 217:133] + node _T_874 = and(_T_872, _T_873) @[lsu_stbuf.scala 217:116] + node _T_875 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_3 = and(_T_874, _T_875) @[lsu_stbuf.scala 217:137] + node _T_876 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 217:112] + node _T_877 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 217:133] + node _T_878 = and(_T_876, _T_877) @[lsu_stbuf.scala 217:116] + node _T_879 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_0 = and(_T_878, _T_879) @[lsu_stbuf.scala 217:137] + node _T_880 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 217:112] + node _T_881 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 217:133] + node _T_882 = and(_T_880, _T_881) @[lsu_stbuf.scala 217:116] + node _T_883 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_1 = and(_T_882, _T_883) @[lsu_stbuf.scala 217:137] + node _T_884 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 217:112] + node _T_885 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 217:133] + node _T_886 = and(_T_884, _T_885) @[lsu_stbuf.scala 217:116] + node _T_887 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_2 = and(_T_886, _T_887) @[lsu_stbuf.scala 217:137] + node _T_888 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 217:112] + node _T_889 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 217:133] + node _T_890 = and(_T_888, _T_889) @[lsu_stbuf.scala 217:116] + node _T_891 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_3 = and(_T_890, _T_891) @[lsu_stbuf.scala 217:137] + node _T_892 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 217:112] + node _T_893 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 217:133] + node _T_894 = and(_T_892, _T_893) @[lsu_stbuf.scala 217:116] + node _T_895 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_0 = and(_T_894, _T_895) @[lsu_stbuf.scala 217:137] + node _T_896 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 217:112] + node _T_897 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 217:133] + node _T_898 = and(_T_896, _T_897) @[lsu_stbuf.scala 217:116] + node _T_899 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_1 = and(_T_898, _T_899) @[lsu_stbuf.scala 217:137] + node _T_900 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 217:112] + node _T_901 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 217:133] + node _T_902 = and(_T_900, _T_901) @[lsu_stbuf.scala 217:116] + node _T_903 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_2 = and(_T_902, _T_903) @[lsu_stbuf.scala 217:137] + node _T_904 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 217:112] + node _T_905 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 217:133] + node _T_906 = and(_T_904, _T_905) @[lsu_stbuf.scala 217:116] + node _T_907 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_3 = and(_T_906, _T_907) @[lsu_stbuf.scala 217:137] + node _T_908 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 217:112] + node _T_909 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 217:133] + node _T_910 = and(_T_908, _T_909) @[lsu_stbuf.scala 217:116] + node _T_911 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_0 = and(_T_910, _T_911) @[lsu_stbuf.scala 217:137] + node _T_912 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 217:112] + node _T_913 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 217:133] + node _T_914 = and(_T_912, _T_913) @[lsu_stbuf.scala 217:116] + node _T_915 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_1 = and(_T_914, _T_915) @[lsu_stbuf.scala 217:137] + node _T_916 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 217:112] + node _T_917 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 217:133] + node _T_918 = and(_T_916, _T_917) @[lsu_stbuf.scala 217:116] + node _T_919 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_2 = and(_T_918, _T_919) @[lsu_stbuf.scala 217:137] + node _T_920 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 217:112] + node _T_921 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 217:133] + node _T_922 = and(_T_920, _T_921) @[lsu_stbuf.scala 217:116] + node _T_923 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_3 = and(_T_922, _T_923) @[lsu_stbuf.scala 217:137] + node _T_924 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 218:112] + node _T_925 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 218:133] + node _T_926 = and(_T_924, _T_925) @[lsu_stbuf.scala 218:116] + node _T_927 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_0 = and(_T_926, _T_927) @[lsu_stbuf.scala 218:137] + node _T_928 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 218:112] + node _T_929 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 218:133] + node _T_930 = and(_T_928, _T_929) @[lsu_stbuf.scala 218:116] + node _T_931 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_1 = and(_T_930, _T_931) @[lsu_stbuf.scala 218:137] + node _T_932 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 218:112] + node _T_933 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 218:133] + node _T_934 = and(_T_932, _T_933) @[lsu_stbuf.scala 218:116] + node _T_935 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_2 = and(_T_934, _T_935) @[lsu_stbuf.scala 218:137] + node _T_936 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 218:112] + node _T_937 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 218:133] + node _T_938 = and(_T_936, _T_937) @[lsu_stbuf.scala 218:116] + node _T_939 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_3 = and(_T_938, _T_939) @[lsu_stbuf.scala 218:137] + node _T_940 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 218:112] + node _T_941 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 218:133] + node _T_942 = and(_T_940, _T_941) @[lsu_stbuf.scala 218:116] + node _T_943 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_0 = and(_T_942, _T_943) @[lsu_stbuf.scala 218:137] + node _T_944 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 218:112] + node _T_945 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 218:133] + node _T_946 = and(_T_944, _T_945) @[lsu_stbuf.scala 218:116] + node _T_947 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_1 = and(_T_946, _T_947) @[lsu_stbuf.scala 218:137] + node _T_948 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 218:112] + node _T_949 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 218:133] + node _T_950 = and(_T_948, _T_949) @[lsu_stbuf.scala 218:116] + node _T_951 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_2 = and(_T_950, _T_951) @[lsu_stbuf.scala 218:137] + node _T_952 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 218:112] + node _T_953 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 218:133] + node _T_954 = and(_T_952, _T_953) @[lsu_stbuf.scala 218:116] + node _T_955 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_3 = and(_T_954, _T_955) @[lsu_stbuf.scala 218:137] + node _T_956 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 218:112] + node _T_957 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 218:133] + node _T_958 = and(_T_956, _T_957) @[lsu_stbuf.scala 218:116] + node _T_959 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_0 = and(_T_958, _T_959) @[lsu_stbuf.scala 218:137] + node _T_960 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 218:112] + node _T_961 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 218:133] + node _T_962 = and(_T_960, _T_961) @[lsu_stbuf.scala 218:116] + node _T_963 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_1 = and(_T_962, _T_963) @[lsu_stbuf.scala 218:137] + node _T_964 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 218:112] + node _T_965 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 218:133] + node _T_966 = and(_T_964, _T_965) @[lsu_stbuf.scala 218:116] + node _T_967 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_2 = and(_T_966, _T_967) @[lsu_stbuf.scala 218:137] + node _T_968 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 218:112] + node _T_969 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 218:133] + node _T_970 = and(_T_968, _T_969) @[lsu_stbuf.scala 218:116] + node _T_971 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_3 = and(_T_970, _T_971) @[lsu_stbuf.scala 218:137] + node _T_972 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 218:112] + node _T_973 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 218:133] + node _T_974 = and(_T_972, _T_973) @[lsu_stbuf.scala 218:116] + node _T_975 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_0 = and(_T_974, _T_975) @[lsu_stbuf.scala 218:137] + node _T_976 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 218:112] + node _T_977 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 218:133] + node _T_978 = and(_T_976, _T_977) @[lsu_stbuf.scala 218:116] + node _T_979 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_1 = and(_T_978, _T_979) @[lsu_stbuf.scala 218:137] + node _T_980 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 218:112] + node _T_981 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 218:133] + node _T_982 = and(_T_980, _T_981) @[lsu_stbuf.scala 218:116] + node _T_983 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_2 = and(_T_982, _T_983) @[lsu_stbuf.scala 218:137] + node _T_984 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 218:112] + node _T_985 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 218:133] + node _T_986 = and(_T_984, _T_985) @[lsu_stbuf.scala 218:116] + node _T_987 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_3 = and(_T_986, _T_987) @[lsu_stbuf.scala 218:137] + node _T_988 = or(stbuf_fwdbyteenvec_hi_0_0, stbuf_fwdbyteenvec_hi_1_0) @[lsu_stbuf.scala 219:147] + node _T_989 = or(_T_988, stbuf_fwdbyteenvec_hi_2_0) @[lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_0 = or(_T_989, stbuf_fwdbyteenvec_hi_3_0) @[lsu_stbuf.scala 219:147] + node _T_990 = or(stbuf_fwdbyteenvec_hi_0_1, stbuf_fwdbyteenvec_hi_1_1) @[lsu_stbuf.scala 219:147] + node _T_991 = or(_T_990, stbuf_fwdbyteenvec_hi_2_1) @[lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_1 = or(_T_991, stbuf_fwdbyteenvec_hi_3_1) @[lsu_stbuf.scala 219:147] + node _T_992 = or(stbuf_fwdbyteenvec_hi_0_2, stbuf_fwdbyteenvec_hi_1_2) @[lsu_stbuf.scala 219:147] + node _T_993 = or(_T_992, stbuf_fwdbyteenvec_hi_2_2) @[lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_2 = or(_T_993, stbuf_fwdbyteenvec_hi_3_2) @[lsu_stbuf.scala 219:147] + node _T_994 = or(stbuf_fwdbyteenvec_hi_0_3, stbuf_fwdbyteenvec_hi_1_3) @[lsu_stbuf.scala 219:147] + node _T_995 = or(_T_994, stbuf_fwdbyteenvec_hi_2_3) @[lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_3 = or(_T_995, stbuf_fwdbyteenvec_hi_3_3) @[lsu_stbuf.scala 219:147] + node _T_996 = or(stbuf_fwdbyteenvec_lo_0_0, stbuf_fwdbyteenvec_lo_1_0) @[lsu_stbuf.scala 220:147] + node _T_997 = or(_T_996, stbuf_fwdbyteenvec_lo_2_0) @[lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_0 = or(_T_997, stbuf_fwdbyteenvec_lo_3_0) @[lsu_stbuf.scala 220:147] + node _T_998 = or(stbuf_fwdbyteenvec_lo_0_1, stbuf_fwdbyteenvec_lo_1_1) @[lsu_stbuf.scala 220:147] + node _T_999 = or(_T_998, stbuf_fwdbyteenvec_lo_2_1) @[lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_1 = or(_T_999, stbuf_fwdbyteenvec_lo_3_1) @[lsu_stbuf.scala 220:147] + node _T_1000 = or(stbuf_fwdbyteenvec_lo_0_2, stbuf_fwdbyteenvec_lo_1_2) @[lsu_stbuf.scala 220:147] + node _T_1001 = or(_T_1000, stbuf_fwdbyteenvec_lo_2_2) @[lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_2 = or(_T_1001, stbuf_fwdbyteenvec_lo_3_2) @[lsu_stbuf.scala 220:147] + node _T_1002 = or(stbuf_fwdbyteenvec_lo_0_3, stbuf_fwdbyteenvec_lo_1_3) @[lsu_stbuf.scala 220:147] + node _T_1003 = or(_T_1002, stbuf_fwdbyteenvec_lo_2_3) @[lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_3 = or(_T_1003, stbuf_fwdbyteenvec_lo_3_3) @[lsu_stbuf.scala 220:147] + node _T_1004 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 222:92] + node _T_1005 = bits(_T_1004, 0, 0) @[Bitwise.scala 72:15] + node _T_1006 = mux(_T_1005, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1007 = and(_T_1006, stbuf_data[0]) @[lsu_stbuf.scala 222:97] + node _T_1008 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 222:92] + node _T_1009 = bits(_T_1008, 0, 0) @[Bitwise.scala 72:15] + node _T_1010 = mux(_T_1009, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1011 = and(_T_1010, stbuf_data[1]) @[lsu_stbuf.scala 222:97] + node _T_1012 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 222:92] + node _T_1013 = bits(_T_1012, 0, 0) @[Bitwise.scala 72:15] + node _T_1014 = mux(_T_1013, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1015 = and(_T_1014, stbuf_data[2]) @[lsu_stbuf.scala 222:97] + node _T_1016 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 222:92] + node _T_1017 = bits(_T_1016, 0, 0) @[Bitwise.scala 72:15] + node _T_1018 = mux(_T_1017, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1019 = and(_T_1018, stbuf_data[3]) @[lsu_stbuf.scala 222:97] + wire _T_1020 : UInt<32>[4] @[lsu_stbuf.scala 222:65] + _T_1020[0] <= _T_1007 @[lsu_stbuf.scala 222:65] + _T_1020[1] <= _T_1011 @[lsu_stbuf.scala 222:65] + _T_1020[2] <= _T_1015 @[lsu_stbuf.scala 222:65] + _T_1020[3] <= _T_1019 @[lsu_stbuf.scala 222:65] + node _T_1021 = or(_T_1020[3], _T_1020[2]) @[lsu_stbuf.scala 222:130] + node _T_1022 = or(_T_1021, _T_1020[1]) @[lsu_stbuf.scala 222:130] + node stbuf_fwddata_hi_pre_m = or(_T_1022, _T_1020[0]) @[lsu_stbuf.scala 222:130] + node _T_1023 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 223:92] + node _T_1024 = bits(_T_1023, 0, 0) @[Bitwise.scala 72:15] + node _T_1025 = mux(_T_1024, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1026 = and(_T_1025, stbuf_data[0]) @[lsu_stbuf.scala 223:97] + node _T_1027 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 223:92] + node _T_1028 = bits(_T_1027, 0, 0) @[Bitwise.scala 72:15] + node _T_1029 = mux(_T_1028, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1030 = and(_T_1029, stbuf_data[1]) @[lsu_stbuf.scala 223:97] + node _T_1031 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 223:92] + node _T_1032 = bits(_T_1031, 0, 0) @[Bitwise.scala 72:15] + node _T_1033 = mux(_T_1032, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1034 = and(_T_1033, stbuf_data[2]) @[lsu_stbuf.scala 223:97] + node _T_1035 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 223:92] + node _T_1036 = bits(_T_1035, 0, 0) @[Bitwise.scala 72:15] + node _T_1037 = mux(_T_1036, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1038 = and(_T_1037, stbuf_data[3]) @[lsu_stbuf.scala 223:97] + wire _T_1039 : UInt<32>[4] @[lsu_stbuf.scala 223:65] + _T_1039[0] <= _T_1026 @[lsu_stbuf.scala 223:65] + _T_1039[1] <= _T_1030 @[lsu_stbuf.scala 223:65] + _T_1039[2] <= _T_1034 @[lsu_stbuf.scala 223:65] + _T_1039[3] <= _T_1038 @[lsu_stbuf.scala 223:65] + node _T_1040 = or(_T_1039[3], _T_1039[2]) @[lsu_stbuf.scala 223:130] + node _T_1041 = or(_T_1040, _T_1039[1]) @[lsu_stbuf.scala 223:130] + node stbuf_fwddata_lo_pre_m = or(_T_1041, _T_1039[0]) @[lsu_stbuf.scala 223:130] + node _T_1042 = bits(io.lsu_addr_r, 1, 0) @[lsu_stbuf.scala 226:54] + node _T_1043 = dshl(ldst_byteen_r, _T_1042) @[lsu_stbuf.scala 226:38] + ldst_byteen_ext_r <= _T_1043 @[lsu_stbuf.scala 226:21] + node ldst_byteen_hi_r = bits(ldst_byteen_ext_r, 7, 4) @[lsu_stbuf.scala 227:43] + node ldst_byteen_lo_r = bits(ldst_byteen_ext_r, 3, 0) @[lsu_stbuf.scala 228:43] + node _T_1044 = bits(io.lsu_addr_m, 31, 2) @[lsu_stbuf.scala 230:42] + node _T_1045 = bits(io.lsu_addr_r, 31, 2) @[lsu_stbuf.scala 230:66] + node _T_1046 = eq(_T_1044, _T_1045) @[lsu_stbuf.scala 230:49] + node _T_1047 = and(_T_1046, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 230:74] + node _T_1048 = and(_T_1047, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 230:95] + node _T_1049 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 230:123] + node ld_addr_rhit_lo_lo = and(_T_1048, _T_1049) @[lsu_stbuf.scala 230:121] + node _T_1050 = bits(io.end_addr_m, 31, 2) @[lsu_stbuf.scala 231:42] + node _T_1051 = bits(io.lsu_addr_r, 31, 2) @[lsu_stbuf.scala 231:66] + node _T_1052 = eq(_T_1050, _T_1051) @[lsu_stbuf.scala 231:49] + node _T_1053 = and(_T_1052, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 231:74] + node _T_1054 = and(_T_1053, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 231:95] + node _T_1055 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 231:123] + node ld_addr_rhit_lo_hi = and(_T_1054, _T_1055) @[lsu_stbuf.scala 231:121] + node _T_1056 = bits(io.lsu_addr_m, 31, 2) @[lsu_stbuf.scala 232:42] + node _T_1057 = bits(io.end_addr_r, 31, 2) @[lsu_stbuf.scala 232:66] + node _T_1058 = eq(_T_1056, _T_1057) @[lsu_stbuf.scala 232:49] + node _T_1059 = and(_T_1058, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 232:74] + node _T_1060 = and(_T_1059, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 232:95] + node _T_1061 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 232:123] + node _T_1062 = and(_T_1060, _T_1061) @[lsu_stbuf.scala 232:121] + node ld_addr_rhit_hi_lo = and(_T_1062, dual_stbuf_write_r) @[lsu_stbuf.scala 232:146] + node _T_1063 = bits(io.end_addr_m, 31, 2) @[lsu_stbuf.scala 233:42] + node _T_1064 = bits(io.end_addr_r, 31, 2) @[lsu_stbuf.scala 233:66] + node _T_1065 = eq(_T_1063, _T_1064) @[lsu_stbuf.scala 233:49] + node _T_1066 = and(_T_1065, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 233:74] + node _T_1067 = and(_T_1066, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 233:95] + node _T_1068 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 233:123] + node _T_1069 = and(_T_1067, _T_1068) @[lsu_stbuf.scala 233:121] + node ld_addr_rhit_hi_hi = and(_T_1069, dual_stbuf_write_r) @[lsu_stbuf.scala 233:146] + node _T_1070 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 235:97] + node _T_1071 = and(ld_addr_rhit_lo_lo, _T_1070) @[lsu_stbuf.scala 235:79] + node _T_1072 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 235:97] + node _T_1073 = and(ld_addr_rhit_lo_lo, _T_1072) @[lsu_stbuf.scala 235:79] + node _T_1074 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 235:97] + node _T_1075 = and(ld_addr_rhit_lo_lo, _T_1074) @[lsu_stbuf.scala 235:79] + node _T_1076 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 235:97] + node _T_1077 = and(ld_addr_rhit_lo_lo, _T_1076) @[lsu_stbuf.scala 235:79] + node _T_1078 = cat(_T_1077, _T_1075) @[Cat.scala 29:58] + node _T_1079 = cat(_T_1078, _T_1073) @[Cat.scala 29:58] + node _T_1080 = cat(_T_1079, _T_1071) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_1080 @[lsu_stbuf.scala 235:22] + node _T_1081 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 236:97] + node _T_1082 = and(ld_addr_rhit_lo_hi, _T_1081) @[lsu_stbuf.scala 236:79] + node _T_1083 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 236:97] + node _T_1084 = and(ld_addr_rhit_lo_hi, _T_1083) @[lsu_stbuf.scala 236:79] + node _T_1085 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 236:97] + node _T_1086 = and(ld_addr_rhit_lo_hi, _T_1085) @[lsu_stbuf.scala 236:79] + node _T_1087 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 236:97] + node _T_1088 = and(ld_addr_rhit_lo_hi, _T_1087) @[lsu_stbuf.scala 236:79] + node _T_1089 = cat(_T_1088, _T_1086) @[Cat.scala 29:58] + node _T_1090 = cat(_T_1089, _T_1084) @[Cat.scala 29:58] + node _T_1091 = cat(_T_1090, _T_1082) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_1091 @[lsu_stbuf.scala 236:22] + node _T_1092 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 237:97] + node _T_1093 = and(ld_addr_rhit_hi_lo, _T_1092) @[lsu_stbuf.scala 237:79] + node _T_1094 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 237:97] + node _T_1095 = and(ld_addr_rhit_hi_lo, _T_1094) @[lsu_stbuf.scala 237:79] + node _T_1096 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 237:97] + node _T_1097 = and(ld_addr_rhit_hi_lo, _T_1096) @[lsu_stbuf.scala 237:79] + node _T_1098 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 237:97] + node _T_1099 = and(ld_addr_rhit_hi_lo, _T_1098) @[lsu_stbuf.scala 237:79] + node _T_1100 = cat(_T_1099, _T_1097) @[Cat.scala 29:58] + node _T_1101 = cat(_T_1100, _T_1095) @[Cat.scala 29:58] + node _T_1102 = cat(_T_1101, _T_1093) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_1102 @[lsu_stbuf.scala 237:22] + node _T_1103 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 238:97] + node _T_1104 = and(ld_addr_rhit_hi_hi, _T_1103) @[lsu_stbuf.scala 238:79] + node _T_1105 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 238:97] + node _T_1106 = and(ld_addr_rhit_hi_hi, _T_1105) @[lsu_stbuf.scala 238:79] + node _T_1107 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 238:97] + node _T_1108 = and(ld_addr_rhit_hi_hi, _T_1107) @[lsu_stbuf.scala 238:79] + node _T_1109 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 238:97] + node _T_1110 = and(ld_addr_rhit_hi_hi, _T_1109) @[lsu_stbuf.scala 238:79] + node _T_1111 = cat(_T_1110, _T_1108) @[Cat.scala 29:58] + node _T_1112 = cat(_T_1111, _T_1106) @[Cat.scala 29:58] + node _T_1113 = cat(_T_1112, _T_1104) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_1113 @[lsu_stbuf.scala 238:22] + node _T_1114 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_stbuf.scala 240:75] + node _T_1115 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_stbuf.scala 240:99] + node _T_1116 = or(_T_1114, _T_1115) @[lsu_stbuf.scala 240:79] + node _T_1117 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_stbuf.scala 240:75] + node _T_1118 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_stbuf.scala 240:99] + node _T_1119 = or(_T_1117, _T_1118) @[lsu_stbuf.scala 240:79] + node _T_1120 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_stbuf.scala 240:75] + node _T_1121 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_stbuf.scala 240:99] + node _T_1122 = or(_T_1120, _T_1121) @[lsu_stbuf.scala 240:79] + node _T_1123 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_stbuf.scala 240:75] + node _T_1124 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_stbuf.scala 240:99] + node _T_1125 = or(_T_1123, _T_1124) @[lsu_stbuf.scala 240:79] + node _T_1126 = cat(_T_1125, _T_1122) @[Cat.scala 29:58] + node _T_1127 = cat(_T_1126, _T_1119) @[Cat.scala 29:58] + node _T_1128 = cat(_T_1127, _T_1116) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_1128 @[lsu_stbuf.scala 240:19] + node _T_1129 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_stbuf.scala 241:75] + node _T_1130 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_stbuf.scala 241:99] + node _T_1131 = or(_T_1129, _T_1130) @[lsu_stbuf.scala 241:79] + node _T_1132 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_stbuf.scala 241:75] + node _T_1133 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_stbuf.scala 241:99] + node _T_1134 = or(_T_1132, _T_1133) @[lsu_stbuf.scala 241:79] + node _T_1135 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_stbuf.scala 241:75] + node _T_1136 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_stbuf.scala 241:99] + node _T_1137 = or(_T_1135, _T_1136) @[lsu_stbuf.scala 241:79] + node _T_1138 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_stbuf.scala 241:75] + node _T_1139 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_stbuf.scala 241:99] + node _T_1140 = or(_T_1138, _T_1139) @[lsu_stbuf.scala 241:79] + node _T_1141 = cat(_T_1140, _T_1137) @[Cat.scala 29:58] + node _T_1142 = cat(_T_1141, _T_1134) @[Cat.scala 29:58] + node _T_1143 = cat(_T_1142, _T_1131) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_1143 @[lsu_stbuf.scala 241:19] + node _T_1144 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_stbuf.scala 243:48] + node _T_1145 = bits(_T_1144, 0, 0) @[Bitwise.scala 72:15] + node _T_1146 = mux(_T_1145, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1147 = bits(io.store_data_lo_r, 7, 0) @[lsu_stbuf.scala 243:73] + node _T_1148 = and(_T_1146, _T_1147) @[lsu_stbuf.scala 243:53] + node _T_1149 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_stbuf.scala 243:109] + node _T_1150 = bits(_T_1149, 0, 0) @[Bitwise.scala 72:15] + node _T_1151 = mux(_T_1150, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1152 = bits(io.store_data_hi_r, 7, 0) @[lsu_stbuf.scala 243:134] + node _T_1153 = and(_T_1151, _T_1152) @[lsu_stbuf.scala 243:114] + node fwdpipe1_lo = or(_T_1148, _T_1153) @[lsu_stbuf.scala 243:80] + node _T_1154 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_stbuf.scala 244:48] + node _T_1155 = bits(_T_1154, 0, 0) @[Bitwise.scala 72:15] + node _T_1156 = mux(_T_1155, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1157 = bits(io.store_data_lo_r, 15, 8) @[lsu_stbuf.scala 244:73] + node _T_1158 = and(_T_1156, _T_1157) @[lsu_stbuf.scala 244:53] + node _T_1159 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_stbuf.scala 244:110] + node _T_1160 = bits(_T_1159, 0, 0) @[Bitwise.scala 72:15] + node _T_1161 = mux(_T_1160, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1162 = bits(io.store_data_hi_r, 15, 8) @[lsu_stbuf.scala 244:135] + node _T_1163 = and(_T_1161, _T_1162) @[lsu_stbuf.scala 244:115] + node fwdpipe2_lo = or(_T_1158, _T_1163) @[lsu_stbuf.scala 244:81] + node _T_1164 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_stbuf.scala 245:48] + node _T_1165 = bits(_T_1164, 0, 0) @[Bitwise.scala 72:15] + node _T_1166 = mux(_T_1165, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1167 = bits(io.store_data_lo_r, 23, 16) @[lsu_stbuf.scala 245:73] + node _T_1168 = and(_T_1166, _T_1167) @[lsu_stbuf.scala 245:53] + node _T_1169 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_stbuf.scala 245:111] + node _T_1170 = bits(_T_1169, 0, 0) @[Bitwise.scala 72:15] + node _T_1171 = mux(_T_1170, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1172 = bits(io.store_data_hi_r, 23, 16) @[lsu_stbuf.scala 245:136] + node _T_1173 = and(_T_1171, _T_1172) @[lsu_stbuf.scala 245:116] + node fwdpipe3_lo = or(_T_1168, _T_1173) @[lsu_stbuf.scala 245:82] + node _T_1174 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_stbuf.scala 246:48] + node _T_1175 = bits(_T_1174, 0, 0) @[Bitwise.scala 72:15] + node _T_1176 = mux(_T_1175, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1177 = bits(io.store_data_lo_r, 31, 24) @[lsu_stbuf.scala 246:73] + node _T_1178 = and(_T_1176, _T_1177) @[lsu_stbuf.scala 246:53] + node _T_1179 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_stbuf.scala 246:111] + node _T_1180 = bits(_T_1179, 0, 0) @[Bitwise.scala 72:15] + node _T_1181 = mux(_T_1180, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1182 = bits(io.store_data_hi_r, 31, 24) @[lsu_stbuf.scala 246:136] + node _T_1183 = and(_T_1181, _T_1182) @[lsu_stbuf.scala 246:116] + node fwdpipe4_lo = or(_T_1178, _T_1183) @[lsu_stbuf.scala 246:82] + node _T_1184 = cat(fwdpipe2_lo, fwdpipe1_lo) @[Cat.scala 29:58] + node _T_1185 = cat(fwdpipe4_lo, fwdpipe3_lo) @[Cat.scala 29:58] + node _T_1186 = cat(_T_1185, _T_1184) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_1186 @[lsu_stbuf.scala 247:23] + node _T_1187 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_stbuf.scala 249:48] + node _T_1188 = bits(_T_1187, 0, 0) @[Bitwise.scala 72:15] + node _T_1189 = mux(_T_1188, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1190 = bits(io.store_data_lo_r, 7, 0) @[lsu_stbuf.scala 249:73] + node _T_1191 = and(_T_1189, _T_1190) @[lsu_stbuf.scala 249:53] + node _T_1192 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_stbuf.scala 249:109] + node _T_1193 = bits(_T_1192, 0, 0) @[Bitwise.scala 72:15] + node _T_1194 = mux(_T_1193, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1195 = bits(io.store_data_hi_r, 7, 0) @[lsu_stbuf.scala 249:134] + node _T_1196 = and(_T_1194, _T_1195) @[lsu_stbuf.scala 249:114] + node fwdpipe1_hi = or(_T_1191, _T_1196) @[lsu_stbuf.scala 249:80] + node _T_1197 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_stbuf.scala 250:48] + node _T_1198 = bits(_T_1197, 0, 0) @[Bitwise.scala 72:15] + node _T_1199 = mux(_T_1198, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1200 = bits(io.store_data_lo_r, 15, 8) @[lsu_stbuf.scala 250:73] + node _T_1201 = and(_T_1199, _T_1200) @[lsu_stbuf.scala 250:53] + node _T_1202 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_stbuf.scala 250:110] + node _T_1203 = bits(_T_1202, 0, 0) @[Bitwise.scala 72:15] + node _T_1204 = mux(_T_1203, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1205 = bits(io.store_data_hi_r, 15, 8) @[lsu_stbuf.scala 250:135] + node _T_1206 = and(_T_1204, _T_1205) @[lsu_stbuf.scala 250:115] + node fwdpipe2_hi = or(_T_1201, _T_1206) @[lsu_stbuf.scala 250:81] + node _T_1207 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_stbuf.scala 251:48] + node _T_1208 = bits(_T_1207, 0, 0) @[Bitwise.scala 72:15] + node _T_1209 = mux(_T_1208, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1210 = bits(io.store_data_lo_r, 23, 16) @[lsu_stbuf.scala 251:73] + node _T_1211 = and(_T_1209, _T_1210) @[lsu_stbuf.scala 251:53] + node _T_1212 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_stbuf.scala 251:111] + node _T_1213 = bits(_T_1212, 0, 0) @[Bitwise.scala 72:15] + node _T_1214 = mux(_T_1213, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1215 = bits(io.store_data_hi_r, 23, 16) @[lsu_stbuf.scala 251:136] + node _T_1216 = and(_T_1214, _T_1215) @[lsu_stbuf.scala 251:116] + node fwdpipe3_hi = or(_T_1211, _T_1216) @[lsu_stbuf.scala 251:82] + node _T_1217 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_stbuf.scala 252:48] + node _T_1218 = bits(_T_1217, 0, 0) @[Bitwise.scala 72:15] + node _T_1219 = mux(_T_1218, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1220 = bits(io.store_data_lo_r, 31, 24) @[lsu_stbuf.scala 252:73] + node _T_1221 = and(_T_1219, _T_1220) @[lsu_stbuf.scala 252:53] + node _T_1222 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_stbuf.scala 252:111] + node _T_1223 = bits(_T_1222, 0, 0) @[Bitwise.scala 72:15] + node _T_1224 = mux(_T_1223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1225 = bits(io.store_data_hi_r, 31, 24) @[lsu_stbuf.scala 252:136] + node _T_1226 = and(_T_1224, _T_1225) @[lsu_stbuf.scala 252:116] + node fwdpipe4_hi = or(_T_1221, _T_1226) @[lsu_stbuf.scala 252:82] + node _T_1227 = cat(fwdpipe2_hi, fwdpipe1_hi) @[Cat.scala 29:58] + node _T_1228 = cat(fwdpipe4_hi, fwdpipe3_hi) @[Cat.scala 29:58] + node _T_1229 = cat(_T_1228, _T_1227) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_1229 @[lsu_stbuf.scala 253:23] + node _T_1230 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_stbuf.scala 255:74] + node _T_1231 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_stbuf.scala 255:98] + node _T_1232 = or(_T_1230, _T_1231) @[lsu_stbuf.scala 255:78] + node _T_1233 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_stbuf.scala 255:74] + node _T_1234 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_stbuf.scala 255:98] + node _T_1235 = or(_T_1233, _T_1234) @[lsu_stbuf.scala 255:78] + node _T_1236 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_stbuf.scala 255:74] + node _T_1237 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_stbuf.scala 255:98] + node _T_1238 = or(_T_1236, _T_1237) @[lsu_stbuf.scala 255:78] + node _T_1239 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_stbuf.scala 255:74] + node _T_1240 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_stbuf.scala 255:98] + node _T_1241 = or(_T_1239, _T_1240) @[lsu_stbuf.scala 255:78] + node _T_1242 = cat(_T_1241, _T_1238) @[Cat.scala 29:58] + node _T_1243 = cat(_T_1242, _T_1235) @[Cat.scala 29:58] + node _T_1244 = cat(_T_1243, _T_1232) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_1244 @[lsu_stbuf.scala 255:18] + node _T_1245 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_stbuf.scala 256:74] + node _T_1246 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_stbuf.scala 256:98] + node _T_1247 = or(_T_1245, _T_1246) @[lsu_stbuf.scala 256:78] + node _T_1248 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_stbuf.scala 256:74] + node _T_1249 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_stbuf.scala 256:98] + node _T_1250 = or(_T_1248, _T_1249) @[lsu_stbuf.scala 256:78] + node _T_1251 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_stbuf.scala 256:74] + node _T_1252 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_stbuf.scala 256:98] + node _T_1253 = or(_T_1251, _T_1252) @[lsu_stbuf.scala 256:78] + node _T_1254 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_stbuf.scala 256:74] + node _T_1255 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_stbuf.scala 256:98] + node _T_1256 = or(_T_1254, _T_1255) @[lsu_stbuf.scala 256:78] + node _T_1257 = cat(_T_1256, _T_1253) @[Cat.scala 29:58] + node _T_1258 = cat(_T_1257, _T_1250) @[Cat.scala 29:58] + node _T_1259 = cat(_T_1258, _T_1247) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_1259 @[lsu_stbuf.scala 256:18] + node _T_1260 = bits(ld_byte_hit_hi, 0, 0) @[lsu_stbuf.scala 258:79] + node _T_1261 = or(_T_1260, stbuf_fwdbyteen_hi_pre_m_0) @[lsu_stbuf.scala 258:83] + node _T_1262 = bits(ld_byte_hit_hi, 1, 1) @[lsu_stbuf.scala 258:79] + node _T_1263 = or(_T_1262, stbuf_fwdbyteen_hi_pre_m_1) @[lsu_stbuf.scala 258:83] + node _T_1264 = bits(ld_byte_hit_hi, 2, 2) @[lsu_stbuf.scala 258:79] + node _T_1265 = or(_T_1264, stbuf_fwdbyteen_hi_pre_m_2) @[lsu_stbuf.scala 258:83] + node _T_1266 = bits(ld_byte_hit_hi, 3, 3) @[lsu_stbuf.scala 258:79] + node _T_1267 = or(_T_1266, stbuf_fwdbyteen_hi_pre_m_3) @[lsu_stbuf.scala 258:83] + node _T_1268 = cat(_T_1267, _T_1265) @[Cat.scala 29:58] + node _T_1269 = cat(_T_1268, _T_1263) @[Cat.scala 29:58] + node _T_1270 = cat(_T_1269, _T_1261) @[Cat.scala 29:58] + io.stbuf_fwdbyteen_hi_m <= _T_1270 @[lsu_stbuf.scala 258:27] + node _T_1271 = bits(ld_byte_hit_lo, 0, 0) @[lsu_stbuf.scala 259:79] + node _T_1272 = or(_T_1271, stbuf_fwdbyteen_lo_pre_m_0) @[lsu_stbuf.scala 259:83] + node _T_1273 = bits(ld_byte_hit_lo, 1, 1) @[lsu_stbuf.scala 259:79] + node _T_1274 = or(_T_1273, stbuf_fwdbyteen_lo_pre_m_1) @[lsu_stbuf.scala 259:83] + node _T_1275 = bits(ld_byte_hit_lo, 2, 2) @[lsu_stbuf.scala 259:79] + node _T_1276 = or(_T_1275, stbuf_fwdbyteen_lo_pre_m_2) @[lsu_stbuf.scala 259:83] + node _T_1277 = bits(ld_byte_hit_lo, 3, 3) @[lsu_stbuf.scala 259:79] + node _T_1278 = or(_T_1277, stbuf_fwdbyteen_lo_pre_m_3) @[lsu_stbuf.scala 259:83] + node _T_1279 = cat(_T_1278, _T_1276) @[Cat.scala 29:58] + node _T_1280 = cat(_T_1279, _T_1274) @[Cat.scala 29:58] + node _T_1281 = cat(_T_1280, _T_1272) @[Cat.scala 29:58] + io.stbuf_fwdbyteen_lo_m <= _T_1281 @[lsu_stbuf.scala 259:27] + node _T_1282 = bits(ld_byte_rhit_lo, 0, 0) @[lsu_stbuf.scala 262:46] + node _T_1283 = bits(ld_fwddata_rpipe_lo, 7, 0) @[lsu_stbuf.scala 262:69] + node _T_1284 = bits(stbuf_fwddata_lo_pre_m, 7, 0) @[lsu_stbuf.scala 262:97] + node stbuf_fwdpipe1_lo = mux(_T_1282, _T_1283, _T_1284) @[lsu_stbuf.scala 262:30] + node _T_1285 = bits(ld_byte_rhit_lo, 1, 1) @[lsu_stbuf.scala 263:46] + node _T_1286 = bits(ld_fwddata_rpipe_lo, 15, 8) @[lsu_stbuf.scala 263:69] + node _T_1287 = bits(stbuf_fwddata_lo_pre_m, 15, 8) @[lsu_stbuf.scala 263:98] + node stbuf_fwdpipe2_lo = mux(_T_1285, _T_1286, _T_1287) @[lsu_stbuf.scala 263:30] + node _T_1288 = bits(ld_byte_rhit_lo, 2, 2) @[lsu_stbuf.scala 264:46] + node _T_1289 = bits(ld_fwddata_rpipe_lo, 23, 16) @[lsu_stbuf.scala 264:69] + node _T_1290 = bits(stbuf_fwddata_lo_pre_m, 23, 16) @[lsu_stbuf.scala 264:99] + node stbuf_fwdpipe3_lo = mux(_T_1288, _T_1289, _T_1290) @[lsu_stbuf.scala 264:30] + node _T_1291 = bits(ld_byte_rhit_lo, 3, 3) @[lsu_stbuf.scala 265:46] + node _T_1292 = bits(ld_fwddata_rpipe_lo, 31, 24) @[lsu_stbuf.scala 265:69] + node _T_1293 = bits(stbuf_fwddata_lo_pre_m, 31, 24) @[lsu_stbuf.scala 265:99] + node stbuf_fwdpipe4_lo = mux(_T_1291, _T_1292, _T_1293) @[lsu_stbuf.scala 265:30] + node _T_1294 = cat(stbuf_fwdpipe2_lo, stbuf_fwdpipe1_lo) @[Cat.scala 29:58] + node _T_1295 = cat(stbuf_fwdpipe4_lo, stbuf_fwdpipe3_lo) @[Cat.scala 29:58] + node _T_1296 = cat(_T_1295, _T_1294) @[Cat.scala 29:58] + io.stbuf_fwddata_lo_m <= _T_1296 @[lsu_stbuf.scala 266:25] + node _T_1297 = bits(ld_byte_rhit_hi, 0, 0) @[lsu_stbuf.scala 268:46] + node _T_1298 = bits(ld_fwddata_rpipe_hi, 7, 0) @[lsu_stbuf.scala 268:69] + node _T_1299 = bits(stbuf_fwddata_hi_pre_m, 7, 0) @[lsu_stbuf.scala 268:97] + node stbuf_fwdpipe1_hi = mux(_T_1297, _T_1298, _T_1299) @[lsu_stbuf.scala 268:30] + node _T_1300 = bits(ld_byte_rhit_hi, 1, 1) @[lsu_stbuf.scala 269:46] + node _T_1301 = bits(ld_fwddata_rpipe_hi, 15, 8) @[lsu_stbuf.scala 269:69] + node _T_1302 = bits(stbuf_fwddata_hi_pre_m, 15, 8) @[lsu_stbuf.scala 269:98] + node stbuf_fwdpipe2_hi = mux(_T_1300, _T_1301, _T_1302) @[lsu_stbuf.scala 269:30] + node _T_1303 = bits(ld_byte_rhit_hi, 2, 2) @[lsu_stbuf.scala 270:46] + node _T_1304 = bits(ld_fwddata_rpipe_hi, 23, 16) @[lsu_stbuf.scala 270:69] + node _T_1305 = bits(stbuf_fwddata_hi_pre_m, 23, 16) @[lsu_stbuf.scala 270:99] + node stbuf_fwdpipe3_hi = mux(_T_1303, _T_1304, _T_1305) @[lsu_stbuf.scala 270:30] + node _T_1306 = bits(ld_byte_rhit_hi, 3, 3) @[lsu_stbuf.scala 271:46] + node _T_1307 = bits(ld_fwddata_rpipe_hi, 31, 24) @[lsu_stbuf.scala 271:69] + node _T_1308 = bits(stbuf_fwddata_hi_pre_m, 31, 24) @[lsu_stbuf.scala 271:99] + node stbuf_fwdpipe4_hi = mux(_T_1306, _T_1307, _T_1308) @[lsu_stbuf.scala 271:30] + node _T_1309 = cat(stbuf_fwdpipe2_hi, stbuf_fwdpipe1_hi) @[Cat.scala 29:58] + node _T_1310 = cat(stbuf_fwdpipe4_hi, stbuf_fwdpipe3_hi) @[Cat.scala 29:58] + node _T_1311 = cat(_T_1310, _T_1309) @[Cat.scala 29:58] + io.stbuf_fwddata_hi_m <= _T_1311 @[lsu_stbuf.scala 272:25] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_ecc : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c2_r_clk : Clock, flip clk_override : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip stbuf_data_any : UInt<32>, flip dec_tlu_core_ecc_disable : UInt<1>, flip lsu_dccm_rden_r : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_addr_r : UInt<16>, flip end_addr_r : UInt<16>, flip lsu_addr_m : UInt<16>, flip end_addr_m : UInt<16>, flip dccm_rdata_hi_r : UInt<32>, flip dccm_rdata_lo_r : UInt<32>, flip dccm_rdata_hi_m : UInt<32>, flip dccm_rdata_lo_m : UInt<32>, flip dccm_data_ecc_hi_r : UInt<7>, flip dccm_data_ecc_lo_r : UInt<7>, flip dccm_data_ecc_hi_m : UInt<7>, flip dccm_data_ecc_lo_m : UInt<7>, flip ld_single_ecc_error_r : UInt<1>, flip ld_single_ecc_error_r_ff : UInt<1>, flip lsu_dccm_rden_m : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_wen : UInt<1>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip scan_mode : UInt<1>, sec_data_hi_r : UInt<32>, sec_data_lo_r : UInt<32>, sec_data_hi_m : UInt<32>, sec_data_lo_m : UInt<32>, sec_data_hi_r_ff : UInt<32>, sec_data_lo_r_ff : UInt<32>, dma_dccm_wdata_ecc_hi : UInt<7>, dma_dccm_wdata_ecc_lo : UInt<7>, stbuf_ecc_any : UInt<7>, sec_data_ecc_hi_r_ff : UInt<7>, sec_data_ecc_lo_r_ff : UInt<7>, single_ecc_error_hi_r : UInt<1>, single_ecc_error_lo_r : UInt<1>, lsu_single_ecc_error_r : UInt<1>, lsu_double_ecc_error_r : UInt<1>, lsu_single_ecc_error_m : UInt<1>, lsu_double_ecc_error_m : UInt<1>} + + wire is_ldst_r : UInt<1> + is_ldst_r <= UInt<1>("h00") + wire is_ldst_hi_any : UInt<1> + is_ldst_hi_any <= UInt<1>("h00") + wire is_ldst_lo_any : UInt<1> + is_ldst_lo_any <= UInt<1>("h00") + wire dccm_wdata_hi_any : UInt<32> + dccm_wdata_hi_any <= UInt<32>("h00") + wire dccm_wdata_lo_any : UInt<32> + dccm_wdata_lo_any <= UInt<32>("h00") + wire dccm_rdata_hi_any : UInt<32> + dccm_rdata_hi_any <= UInt<32>("h00") + wire dccm_rdata_lo_any : UInt<32> + dccm_rdata_lo_any <= UInt<32>("h00") + wire dccm_data_ecc_hi_any : UInt<7> + dccm_data_ecc_hi_any <= UInt<7>("h00") + wire dccm_data_ecc_lo_any : UInt<7> + dccm_data_ecc_lo_any <= UInt<7>("h00") + wire double_ecc_error_hi_m : UInt<1> + double_ecc_error_hi_m <= UInt<1>("h00") + wire double_ecc_error_lo_m : UInt<1> + double_ecc_error_lo_m <= UInt<1>("h00") + wire double_ecc_error_hi_r : UInt<1> + double_ecc_error_hi_r <= UInt<1>("h00") + wire double_ecc_error_lo_r : UInt<1> + double_ecc_error_lo_r <= UInt<1>("h00") + wire ldst_dual_m : UInt<1> + ldst_dual_m <= UInt<1>("h00") + wire ldst_dual_r : UInt<1> + ldst_dual_r <= UInt<1>("h00") + wire is_ldst_m : UInt<1> + is_ldst_m <= UInt<1>("h00") + wire is_ldst_hi_m : UInt<1> + is_ldst_hi_m <= UInt<1>("h00") + wire is_ldst_lo_m : UInt<1> + is_ldst_lo_m <= UInt<1>("h00") + wire is_ldst_hi_r : UInt<1> + is_ldst_hi_r <= UInt<1>("h00") + wire is_ldst_lo_r : UInt<1> + is_ldst_lo_r <= UInt<1>("h00") + io.sec_data_hi_m <= UInt<1>("h00") @[lsu_ecc.scala 89:32] + io.sec_data_lo_m <= UInt<1>("h00") @[lsu_ecc.scala 90:32] + io.lsu_single_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 91:30] + io.lsu_double_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 92:30] + wire _T : UInt<1>[18] @[lib.scala 173:18] + wire _T_1 : UInt<1>[18] @[lib.scala 174:18] + wire _T_2 : UInt<1>[18] @[lib.scala 175:18] + wire _T_3 : UInt<1>[15] @[lib.scala 176:18] + wire _T_4 : UInt<1>[15] @[lib.scala 177:18] + wire _T_5 : UInt<1>[6] @[lib.scala 178:18] + node _T_6 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 185:36] + _T[0] <= _T_6 @[lib.scala 185:30] + node _T_7 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 186:36] + _T_1[0] <= _T_7 @[lib.scala 186:30] + node _T_8 = bits(dccm_rdata_hi_any, 1, 1) @[lib.scala 185:36] + _T[1] <= _T_8 @[lib.scala 185:30] + node _T_9 = bits(dccm_rdata_hi_any, 1, 1) @[lib.scala 187:36] + _T_2[0] <= _T_9 @[lib.scala 187:30] + node _T_10 = bits(dccm_rdata_hi_any, 2, 2) @[lib.scala 186:36] + _T_1[1] <= _T_10 @[lib.scala 186:30] + node _T_11 = bits(dccm_rdata_hi_any, 2, 2) @[lib.scala 187:36] + _T_2[1] <= _T_11 @[lib.scala 187:30] + node _T_12 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 185:36] + _T[2] <= _T_12 @[lib.scala 185:30] + node _T_13 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 186:36] + _T_1[2] <= _T_13 @[lib.scala 186:30] + node _T_14 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 187:36] + _T_2[2] <= _T_14 @[lib.scala 187:30] + node _T_15 = bits(dccm_rdata_hi_any, 4, 4) @[lib.scala 185:36] + _T[3] <= _T_15 @[lib.scala 185:30] + node _T_16 = bits(dccm_rdata_hi_any, 4, 4) @[lib.scala 188:36] + _T_3[0] <= _T_16 @[lib.scala 188:30] + node _T_17 = bits(dccm_rdata_hi_any, 5, 5) @[lib.scala 186:36] + _T_1[3] <= _T_17 @[lib.scala 186:30] + node _T_18 = bits(dccm_rdata_hi_any, 5, 5) @[lib.scala 188:36] + _T_3[1] <= _T_18 @[lib.scala 188:30] + node _T_19 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 185:36] + _T[4] <= _T_19 @[lib.scala 185:30] + node _T_20 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 186:36] + _T_1[4] <= _T_20 @[lib.scala 186:30] + node _T_21 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 188:36] + _T_3[2] <= _T_21 @[lib.scala 188:30] + node _T_22 = bits(dccm_rdata_hi_any, 7, 7) @[lib.scala 187:36] + _T_2[3] <= _T_22 @[lib.scala 187:30] + node _T_23 = bits(dccm_rdata_hi_any, 7, 7) @[lib.scala 188:36] + _T_3[3] <= _T_23 @[lib.scala 188:30] + node _T_24 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 185:36] + _T[5] <= _T_24 @[lib.scala 185:30] + node _T_25 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 187:36] + _T_2[4] <= _T_25 @[lib.scala 187:30] + node _T_26 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 188:36] + _T_3[4] <= _T_26 @[lib.scala 188:30] + node _T_27 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 186:36] + _T_1[5] <= _T_27 @[lib.scala 186:30] + node _T_28 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 187:36] + _T_2[5] <= _T_28 @[lib.scala 187:30] + node _T_29 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 188:36] + _T_3[5] <= _T_29 @[lib.scala 188:30] + node _T_30 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 185:36] + _T[6] <= _T_30 @[lib.scala 185:30] + node _T_31 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 186:36] + _T_1[6] <= _T_31 @[lib.scala 186:30] + node _T_32 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 187:36] + _T_2[6] <= _T_32 @[lib.scala 187:30] + node _T_33 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 188:36] + _T_3[6] <= _T_33 @[lib.scala 188:30] + node _T_34 = bits(dccm_rdata_hi_any, 11, 11) @[lib.scala 185:36] + _T[7] <= _T_34 @[lib.scala 185:30] + node _T_35 = bits(dccm_rdata_hi_any, 11, 11) @[lib.scala 189:36] + _T_4[0] <= _T_35 @[lib.scala 189:30] + node _T_36 = bits(dccm_rdata_hi_any, 12, 12) @[lib.scala 186:36] + _T_1[7] <= _T_36 @[lib.scala 186:30] + node _T_37 = bits(dccm_rdata_hi_any, 12, 12) @[lib.scala 189:36] + _T_4[1] <= _T_37 @[lib.scala 189:30] + node _T_38 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 185:36] + _T[8] <= _T_38 @[lib.scala 185:30] + node _T_39 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 186:36] + _T_1[8] <= _T_39 @[lib.scala 186:30] + node _T_40 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 189:36] + _T_4[2] <= _T_40 @[lib.scala 189:30] + node _T_41 = bits(dccm_rdata_hi_any, 14, 14) @[lib.scala 187:36] + _T_2[7] <= _T_41 @[lib.scala 187:30] + node _T_42 = bits(dccm_rdata_hi_any, 14, 14) @[lib.scala 189:36] + _T_4[3] <= _T_42 @[lib.scala 189:30] + node _T_43 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 185:36] + _T[9] <= _T_43 @[lib.scala 185:30] + node _T_44 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 187:36] + _T_2[8] <= _T_44 @[lib.scala 187:30] + node _T_45 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 189:36] + _T_4[4] <= _T_45 @[lib.scala 189:30] + node _T_46 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 186:36] + _T_1[9] <= _T_46 @[lib.scala 186:30] + node _T_47 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 187:36] + _T_2[9] <= _T_47 @[lib.scala 187:30] + node _T_48 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 189:36] + _T_4[5] <= _T_48 @[lib.scala 189:30] + node _T_49 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 185:36] + _T[10] <= _T_49 @[lib.scala 185:30] + node _T_50 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 186:36] + _T_1[10] <= _T_50 @[lib.scala 186:30] + node _T_51 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 187:36] + _T_2[10] <= _T_51 @[lib.scala 187:30] + node _T_52 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 189:36] + _T_4[6] <= _T_52 @[lib.scala 189:30] + node _T_53 = bits(dccm_rdata_hi_any, 18, 18) @[lib.scala 188:36] + _T_3[7] <= _T_53 @[lib.scala 188:30] + node _T_54 = bits(dccm_rdata_hi_any, 18, 18) @[lib.scala 189:36] + _T_4[7] <= _T_54 @[lib.scala 189:30] + node _T_55 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 185:36] + _T[11] <= _T_55 @[lib.scala 185:30] + node _T_56 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 188:36] + _T_3[8] <= _T_56 @[lib.scala 188:30] + node _T_57 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 189:36] + _T_4[8] <= _T_57 @[lib.scala 189:30] + node _T_58 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 186:36] + _T_1[11] <= _T_58 @[lib.scala 186:30] + node _T_59 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 188:36] + _T_3[9] <= _T_59 @[lib.scala 188:30] + node _T_60 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 189:36] + _T_4[9] <= _T_60 @[lib.scala 189:30] + node _T_61 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 185:36] + _T[12] <= _T_61 @[lib.scala 185:30] + node _T_62 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 186:36] + _T_1[12] <= _T_62 @[lib.scala 186:30] + node _T_63 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 188:36] + _T_3[10] <= _T_63 @[lib.scala 188:30] + node _T_64 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 189:36] + _T_4[10] <= _T_64 @[lib.scala 189:30] + node _T_65 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 187:36] + _T_2[11] <= _T_65 @[lib.scala 187:30] + node _T_66 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 188:36] + _T_3[11] <= _T_66 @[lib.scala 188:30] + node _T_67 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 189:36] + _T_4[11] <= _T_67 @[lib.scala 189:30] + node _T_68 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 185:36] + _T[13] <= _T_68 @[lib.scala 185:30] + node _T_69 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 187:36] + _T_2[12] <= _T_69 @[lib.scala 187:30] + node _T_70 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 188:36] + _T_3[12] <= _T_70 @[lib.scala 188:30] + node _T_71 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 189:36] + _T_4[12] <= _T_71 @[lib.scala 189:30] + node _T_72 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 186:36] + _T_1[13] <= _T_72 @[lib.scala 186:30] + node _T_73 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 187:36] + _T_2[13] <= _T_73 @[lib.scala 187:30] + node _T_74 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 188:36] + _T_3[13] <= _T_74 @[lib.scala 188:30] + node _T_75 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 189:36] + _T_4[13] <= _T_75 @[lib.scala 189:30] + node _T_76 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 185:36] + _T[14] <= _T_76 @[lib.scala 185:30] + node _T_77 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 186:36] + _T_1[14] <= _T_77 @[lib.scala 186:30] + node _T_78 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 187:36] + _T_2[14] <= _T_78 @[lib.scala 187:30] + node _T_79 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 188:36] + _T_3[14] <= _T_79 @[lib.scala 188:30] + node _T_80 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 189:36] + _T_4[14] <= _T_80 @[lib.scala 189:30] + node _T_81 = bits(dccm_rdata_hi_any, 26, 26) @[lib.scala 185:36] + _T[15] <= _T_81 @[lib.scala 185:30] + node _T_82 = bits(dccm_rdata_hi_any, 26, 26) @[lib.scala 190:36] + _T_5[0] <= _T_82 @[lib.scala 190:30] + node _T_83 = bits(dccm_rdata_hi_any, 27, 27) @[lib.scala 186:36] + _T_1[15] <= _T_83 @[lib.scala 186:30] + node _T_84 = bits(dccm_rdata_hi_any, 27, 27) @[lib.scala 190:36] + _T_5[1] <= _T_84 @[lib.scala 190:30] + node _T_85 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 185:36] + _T[16] <= _T_85 @[lib.scala 185:30] + node _T_86 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 186:36] + _T_1[16] <= _T_86 @[lib.scala 186:30] + node _T_87 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 190:36] + _T_5[2] <= _T_87 @[lib.scala 190:30] + node _T_88 = bits(dccm_rdata_hi_any, 29, 29) @[lib.scala 187:36] + _T_2[15] <= _T_88 @[lib.scala 187:30] + node _T_89 = bits(dccm_rdata_hi_any, 29, 29) @[lib.scala 190:36] + _T_5[3] <= _T_89 @[lib.scala 190:30] + node _T_90 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 185:36] + _T[17] <= _T_90 @[lib.scala 185:30] + node _T_91 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 187:36] + _T_2[16] <= _T_91 @[lib.scala 187:30] + node _T_92 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 190:36] + _T_5[4] <= _T_92 @[lib.scala 190:30] + node _T_93 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 186:36] + _T_1[17] <= _T_93 @[lib.scala 186:30] + node _T_94 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 187:36] + _T_2[17] <= _T_94 @[lib.scala 187:30] + node _T_95 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 190:36] + _T_5[5] <= _T_95 @[lib.scala 190:30] + node _T_96 = xorr(dccm_rdata_hi_any) @[lib.scala 193:30] + node _T_97 = xorr(dccm_data_ecc_hi_any) @[lib.scala 193:44] + node _T_98 = xor(_T_96, _T_97) @[lib.scala 193:35] + node _T_99 = not(UInt<1>("h00")) @[lib.scala 193:52] + node _T_100 = and(_T_98, _T_99) @[lib.scala 193:50] + node _T_101 = bits(dccm_data_ecc_hi_any, 5, 5) @[lib.scala 193:68] + node _T_102 = cat(_T_5[2], _T_5[1]) @[lib.scala 193:76] + node _T_103 = cat(_T_102, _T_5[0]) @[lib.scala 193:76] + node _T_104 = cat(_T_5[5], _T_5[4]) @[lib.scala 193:76] + node _T_105 = cat(_T_104, _T_5[3]) @[lib.scala 193:76] + node _T_106 = cat(_T_105, _T_103) @[lib.scala 193:76] + node _T_107 = xorr(_T_106) @[lib.scala 193:83] + node _T_108 = xor(_T_101, _T_107) @[lib.scala 193:71] + node _T_109 = bits(dccm_data_ecc_hi_any, 4, 4) @[lib.scala 193:95] + node _T_110 = cat(_T_4[2], _T_4[1]) @[lib.scala 193:103] + node _T_111 = cat(_T_110, _T_4[0]) @[lib.scala 193:103] + node _T_112 = cat(_T_4[4], _T_4[3]) @[lib.scala 193:103] + node _T_113 = cat(_T_4[6], _T_4[5]) @[lib.scala 193:103] + node _T_114 = cat(_T_113, _T_112) @[lib.scala 193:103] + node _T_115 = cat(_T_114, _T_111) @[lib.scala 193:103] + node _T_116 = cat(_T_4[8], _T_4[7]) @[lib.scala 193:103] + node _T_117 = cat(_T_4[10], _T_4[9]) @[lib.scala 193:103] + node _T_118 = cat(_T_117, _T_116) @[lib.scala 193:103] + node _T_119 = cat(_T_4[12], _T_4[11]) @[lib.scala 193:103] + node _T_120 = cat(_T_4[14], _T_4[13]) @[lib.scala 193:103] + node _T_121 = cat(_T_120, _T_119) @[lib.scala 193:103] + node _T_122 = cat(_T_121, _T_118) @[lib.scala 193:103] + node _T_123 = cat(_T_122, _T_115) @[lib.scala 193:103] + node _T_124 = xorr(_T_123) @[lib.scala 193:110] + node _T_125 = xor(_T_109, _T_124) @[lib.scala 193:98] + node _T_126 = bits(dccm_data_ecc_hi_any, 3, 3) @[lib.scala 193:122] + node _T_127 = cat(_T_3[2], _T_3[1]) @[lib.scala 193:130] + node _T_128 = cat(_T_127, _T_3[0]) @[lib.scala 193:130] + node _T_129 = cat(_T_3[4], _T_3[3]) @[lib.scala 193:130] + node _T_130 = cat(_T_3[6], _T_3[5]) @[lib.scala 193:130] + node _T_131 = cat(_T_130, _T_129) @[lib.scala 193:130] + node _T_132 = cat(_T_131, _T_128) @[lib.scala 193:130] + node _T_133 = cat(_T_3[8], _T_3[7]) @[lib.scala 193:130] + node _T_134 = cat(_T_3[10], _T_3[9]) @[lib.scala 193:130] + node _T_135 = cat(_T_134, _T_133) @[lib.scala 193:130] + node _T_136 = cat(_T_3[12], _T_3[11]) @[lib.scala 193:130] + node _T_137 = cat(_T_3[14], _T_3[13]) @[lib.scala 193:130] + node _T_138 = cat(_T_137, _T_136) @[lib.scala 193:130] + node _T_139 = cat(_T_138, _T_135) @[lib.scala 193:130] + node _T_140 = cat(_T_139, _T_132) @[lib.scala 193:130] + node _T_141 = xorr(_T_140) @[lib.scala 193:137] + node _T_142 = xor(_T_126, _T_141) @[lib.scala 193:125] + node _T_143 = bits(dccm_data_ecc_hi_any, 2, 2) @[lib.scala 193:149] + node _T_144 = cat(_T_2[1], _T_2[0]) @[lib.scala 193:157] + node _T_145 = cat(_T_2[3], _T_2[2]) @[lib.scala 193:157] + node _T_146 = cat(_T_145, _T_144) @[lib.scala 193:157] + node _T_147 = cat(_T_2[5], _T_2[4]) @[lib.scala 193:157] + node _T_148 = cat(_T_2[8], _T_2[7]) @[lib.scala 193:157] + node _T_149 = cat(_T_148, _T_2[6]) @[lib.scala 193:157] + node _T_150 = cat(_T_149, _T_147) @[lib.scala 193:157] + node _T_151 = cat(_T_150, _T_146) @[lib.scala 193:157] + node _T_152 = cat(_T_2[10], _T_2[9]) @[lib.scala 193:157] + node _T_153 = cat(_T_2[12], _T_2[11]) @[lib.scala 193:157] + node _T_154 = cat(_T_153, _T_152) @[lib.scala 193:157] + node _T_155 = cat(_T_2[14], _T_2[13]) @[lib.scala 193:157] + node _T_156 = cat(_T_2[17], _T_2[16]) @[lib.scala 193:157] + node _T_157 = cat(_T_156, _T_2[15]) @[lib.scala 193:157] + node _T_158 = cat(_T_157, _T_155) @[lib.scala 193:157] + node _T_159 = cat(_T_158, _T_154) @[lib.scala 193:157] + node _T_160 = cat(_T_159, _T_151) @[lib.scala 193:157] + node _T_161 = xorr(_T_160) @[lib.scala 193:164] + node _T_162 = xor(_T_143, _T_161) @[lib.scala 193:152] + node _T_163 = bits(dccm_data_ecc_hi_any, 1, 1) @[lib.scala 193:176] + node _T_164 = cat(_T_1[1], _T_1[0]) @[lib.scala 193:184] + node _T_165 = cat(_T_1[3], _T_1[2]) @[lib.scala 193:184] + node _T_166 = cat(_T_165, _T_164) @[lib.scala 193:184] + node _T_167 = cat(_T_1[5], _T_1[4]) @[lib.scala 193:184] + node _T_168 = cat(_T_1[8], _T_1[7]) @[lib.scala 193:184] + node _T_169 = cat(_T_168, _T_1[6]) @[lib.scala 193:184] + node _T_170 = cat(_T_169, _T_167) @[lib.scala 193:184] + node _T_171 = cat(_T_170, _T_166) @[lib.scala 193:184] + node _T_172 = cat(_T_1[10], _T_1[9]) @[lib.scala 193:184] + node _T_173 = cat(_T_1[12], _T_1[11]) @[lib.scala 193:184] + node _T_174 = cat(_T_173, _T_172) @[lib.scala 193:184] + node _T_175 = cat(_T_1[14], _T_1[13]) @[lib.scala 193:184] + node _T_176 = cat(_T_1[17], _T_1[16]) @[lib.scala 193:184] + node _T_177 = cat(_T_176, _T_1[15]) @[lib.scala 193:184] + node _T_178 = cat(_T_177, _T_175) @[lib.scala 193:184] + node _T_179 = cat(_T_178, _T_174) @[lib.scala 193:184] + node _T_180 = cat(_T_179, _T_171) @[lib.scala 193:184] + node _T_181 = xorr(_T_180) @[lib.scala 193:191] + node _T_182 = xor(_T_163, _T_181) @[lib.scala 193:179] + node _T_183 = bits(dccm_data_ecc_hi_any, 0, 0) @[lib.scala 193:203] + node _T_184 = cat(_T[1], _T[0]) @[lib.scala 193:211] + node _T_185 = cat(_T[3], _T[2]) @[lib.scala 193:211] + node _T_186 = cat(_T_185, _T_184) @[lib.scala 193:211] + node _T_187 = cat(_T[5], _T[4]) @[lib.scala 193:211] + node _T_188 = cat(_T[8], _T[7]) @[lib.scala 193:211] + node _T_189 = cat(_T_188, _T[6]) @[lib.scala 193:211] + node _T_190 = cat(_T_189, _T_187) @[lib.scala 193:211] + node _T_191 = cat(_T_190, _T_186) @[lib.scala 193:211] + node _T_192 = cat(_T[10], _T[9]) @[lib.scala 193:211] + node _T_193 = cat(_T[12], _T[11]) @[lib.scala 193:211] + node _T_194 = cat(_T_193, _T_192) @[lib.scala 193:211] + node _T_195 = cat(_T[14], _T[13]) @[lib.scala 193:211] + node _T_196 = cat(_T[17], _T[16]) @[lib.scala 193:211] + node _T_197 = cat(_T_196, _T[15]) @[lib.scala 193:211] + node _T_198 = cat(_T_197, _T_195) @[lib.scala 193:211] + node _T_199 = cat(_T_198, _T_194) @[lib.scala 193:211] + node _T_200 = cat(_T_199, _T_191) @[lib.scala 193:211] + node _T_201 = xorr(_T_200) @[lib.scala 193:218] + node _T_202 = xor(_T_183, _T_201) @[lib.scala 193:206] + node _T_203 = cat(_T_162, _T_182) @[Cat.scala 29:58] + node _T_204 = cat(_T_203, _T_202) @[Cat.scala 29:58] + node _T_205 = cat(_T_125, _T_142) @[Cat.scala 29:58] + node _T_206 = cat(_T_100, _T_108) @[Cat.scala 29:58] + node _T_207 = cat(_T_206, _T_205) @[Cat.scala 29:58] + node _T_208 = cat(_T_207, _T_204) @[Cat.scala 29:58] + node _T_209 = neq(_T_208, UInt<1>("h00")) @[lib.scala 194:44] + node _T_210 = and(is_ldst_hi_any, _T_209) @[lib.scala 194:32] + node _T_211 = bits(_T_208, 6, 6) @[lib.scala 194:64] + node single_ecc_error_hi_any = and(_T_210, _T_211) @[lib.scala 194:53] + node _T_212 = neq(_T_208, UInt<1>("h00")) @[lib.scala 195:44] + node _T_213 = and(is_ldst_hi_any, _T_212) @[lib.scala 195:32] + node _T_214 = bits(_T_208, 6, 6) @[lib.scala 195:65] + node _T_215 = not(_T_214) @[lib.scala 195:55] + node double_ecc_error_hi_any = and(_T_213, _T_215) @[lib.scala 195:53] + wire _T_216 : UInt<1>[39] @[lib.scala 196:26] + node _T_217 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_218 = eq(_T_217, UInt<1>("h01")) @[lib.scala 199:41] + _T_216[0] <= _T_218 @[lib.scala 199:23] + node _T_219 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_220 = eq(_T_219, UInt<2>("h02")) @[lib.scala 199:41] + _T_216[1] <= _T_220 @[lib.scala 199:23] + node _T_221 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_222 = eq(_T_221, UInt<2>("h03")) @[lib.scala 199:41] + _T_216[2] <= _T_222 @[lib.scala 199:23] + node _T_223 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_224 = eq(_T_223, UInt<3>("h04")) @[lib.scala 199:41] + _T_216[3] <= _T_224 @[lib.scala 199:23] + node _T_225 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_226 = eq(_T_225, UInt<3>("h05")) @[lib.scala 199:41] + _T_216[4] <= _T_226 @[lib.scala 199:23] + node _T_227 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_228 = eq(_T_227, UInt<3>("h06")) @[lib.scala 199:41] + _T_216[5] <= _T_228 @[lib.scala 199:23] + node _T_229 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_230 = eq(_T_229, UInt<3>("h07")) @[lib.scala 199:41] + _T_216[6] <= _T_230 @[lib.scala 199:23] + node _T_231 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_232 = eq(_T_231, UInt<4>("h08")) @[lib.scala 199:41] + _T_216[7] <= _T_232 @[lib.scala 199:23] + node _T_233 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_234 = eq(_T_233, UInt<4>("h09")) @[lib.scala 199:41] + _T_216[8] <= _T_234 @[lib.scala 199:23] + node _T_235 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_236 = eq(_T_235, UInt<4>("h0a")) @[lib.scala 199:41] + _T_216[9] <= _T_236 @[lib.scala 199:23] + node _T_237 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_238 = eq(_T_237, UInt<4>("h0b")) @[lib.scala 199:41] + _T_216[10] <= _T_238 @[lib.scala 199:23] + node _T_239 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_240 = eq(_T_239, UInt<4>("h0c")) @[lib.scala 199:41] + _T_216[11] <= _T_240 @[lib.scala 199:23] + node _T_241 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_242 = eq(_T_241, UInt<4>("h0d")) @[lib.scala 199:41] + _T_216[12] <= _T_242 @[lib.scala 199:23] + node _T_243 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_244 = eq(_T_243, UInt<4>("h0e")) @[lib.scala 199:41] + _T_216[13] <= _T_244 @[lib.scala 199:23] + node _T_245 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_246 = eq(_T_245, UInt<4>("h0f")) @[lib.scala 199:41] + _T_216[14] <= _T_246 @[lib.scala 199:23] + node _T_247 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_248 = eq(_T_247, UInt<5>("h010")) @[lib.scala 199:41] + _T_216[15] <= _T_248 @[lib.scala 199:23] + node _T_249 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_250 = eq(_T_249, UInt<5>("h011")) @[lib.scala 199:41] + _T_216[16] <= _T_250 @[lib.scala 199:23] + node _T_251 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_252 = eq(_T_251, UInt<5>("h012")) @[lib.scala 199:41] + _T_216[17] <= _T_252 @[lib.scala 199:23] + node _T_253 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_254 = eq(_T_253, UInt<5>("h013")) @[lib.scala 199:41] + _T_216[18] <= _T_254 @[lib.scala 199:23] + node _T_255 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_256 = eq(_T_255, UInt<5>("h014")) @[lib.scala 199:41] + _T_216[19] <= _T_256 @[lib.scala 199:23] + node _T_257 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_258 = eq(_T_257, UInt<5>("h015")) @[lib.scala 199:41] + _T_216[20] <= _T_258 @[lib.scala 199:23] + node _T_259 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_260 = eq(_T_259, UInt<5>("h016")) @[lib.scala 199:41] + _T_216[21] <= _T_260 @[lib.scala 199:23] + node _T_261 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_262 = eq(_T_261, UInt<5>("h017")) @[lib.scala 199:41] + _T_216[22] <= _T_262 @[lib.scala 199:23] + node _T_263 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_264 = eq(_T_263, UInt<5>("h018")) @[lib.scala 199:41] + _T_216[23] <= _T_264 @[lib.scala 199:23] + node _T_265 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_266 = eq(_T_265, UInt<5>("h019")) @[lib.scala 199:41] + _T_216[24] <= _T_266 @[lib.scala 199:23] + node _T_267 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_268 = eq(_T_267, UInt<5>("h01a")) @[lib.scala 199:41] + _T_216[25] <= _T_268 @[lib.scala 199:23] + node _T_269 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_270 = eq(_T_269, UInt<5>("h01b")) @[lib.scala 199:41] + _T_216[26] <= _T_270 @[lib.scala 199:23] + node _T_271 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_272 = eq(_T_271, UInt<5>("h01c")) @[lib.scala 199:41] + _T_216[27] <= _T_272 @[lib.scala 199:23] + node _T_273 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_274 = eq(_T_273, UInt<5>("h01d")) @[lib.scala 199:41] + _T_216[28] <= _T_274 @[lib.scala 199:23] + node _T_275 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_276 = eq(_T_275, UInt<5>("h01e")) @[lib.scala 199:41] + _T_216[29] <= _T_276 @[lib.scala 199:23] + node _T_277 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_278 = eq(_T_277, UInt<5>("h01f")) @[lib.scala 199:41] + _T_216[30] <= _T_278 @[lib.scala 199:23] + node _T_279 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_280 = eq(_T_279, UInt<6>("h020")) @[lib.scala 199:41] + _T_216[31] <= _T_280 @[lib.scala 199:23] + node _T_281 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_282 = eq(_T_281, UInt<6>("h021")) @[lib.scala 199:41] + _T_216[32] <= _T_282 @[lib.scala 199:23] + node _T_283 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_284 = eq(_T_283, UInt<6>("h022")) @[lib.scala 199:41] + _T_216[33] <= _T_284 @[lib.scala 199:23] + node _T_285 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_286 = eq(_T_285, UInt<6>("h023")) @[lib.scala 199:41] + _T_216[34] <= _T_286 @[lib.scala 199:23] + node _T_287 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_288 = eq(_T_287, UInt<6>("h024")) @[lib.scala 199:41] + _T_216[35] <= _T_288 @[lib.scala 199:23] + node _T_289 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_290 = eq(_T_289, UInt<6>("h025")) @[lib.scala 199:41] + _T_216[36] <= _T_290 @[lib.scala 199:23] + node _T_291 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_292 = eq(_T_291, UInt<6>("h026")) @[lib.scala 199:41] + _T_216[37] <= _T_292 @[lib.scala 199:23] + node _T_293 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_294 = eq(_T_293, UInt<6>("h027")) @[lib.scala 199:41] + _T_216[38] <= _T_294 @[lib.scala 199:23] + node _T_295 = bits(dccm_data_ecc_hi_any, 6, 6) @[lib.scala 201:37] + node _T_296 = bits(dccm_rdata_hi_any, 31, 26) @[lib.scala 201:45] + node _T_297 = bits(dccm_data_ecc_hi_any, 5, 5) @[lib.scala 201:60] + node _T_298 = bits(dccm_rdata_hi_any, 25, 11) @[lib.scala 201:68] + node _T_299 = bits(dccm_data_ecc_hi_any, 4, 4) @[lib.scala 201:83] + node _T_300 = bits(dccm_rdata_hi_any, 10, 4) @[lib.scala 201:91] + node _T_301 = bits(dccm_data_ecc_hi_any, 3, 3) @[lib.scala 201:105] + node _T_302 = bits(dccm_rdata_hi_any, 3, 1) @[lib.scala 201:113] + node _T_303 = bits(dccm_data_ecc_hi_any, 2, 2) @[lib.scala 201:126] + node _T_304 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 201:134] + node _T_305 = bits(dccm_data_ecc_hi_any, 1, 0) @[lib.scala 201:145] + node _T_306 = cat(_T_304, _T_305) @[Cat.scala 29:58] + node _T_307 = cat(_T_301, _T_302) @[Cat.scala 29:58] + node _T_308 = cat(_T_307, _T_303) @[Cat.scala 29:58] + node _T_309 = cat(_T_308, _T_306) @[Cat.scala 29:58] + node _T_310 = cat(_T_298, _T_299) @[Cat.scala 29:58] + node _T_311 = cat(_T_310, _T_300) @[Cat.scala 29:58] + node _T_312 = cat(_T_295, _T_296) @[Cat.scala 29:58] + node _T_313 = cat(_T_312, _T_297) @[Cat.scala 29:58] + node _T_314 = cat(_T_313, _T_311) @[Cat.scala 29:58] + node _T_315 = cat(_T_314, _T_309) @[Cat.scala 29:58] + node _T_316 = bits(single_ecc_error_hi_any, 0, 0) @[lib.scala 202:49] + node _T_317 = cat(_T_216[1], _T_216[0]) @[lib.scala 202:69] + node _T_318 = cat(_T_216[3], _T_216[2]) @[lib.scala 202:69] + node _T_319 = cat(_T_318, _T_317) @[lib.scala 202:69] + node _T_320 = cat(_T_216[5], _T_216[4]) @[lib.scala 202:69] + node _T_321 = cat(_T_216[8], _T_216[7]) @[lib.scala 202:69] + node _T_322 = cat(_T_321, _T_216[6]) @[lib.scala 202:69] + node _T_323 = cat(_T_322, _T_320) @[lib.scala 202:69] + node _T_324 = cat(_T_323, _T_319) @[lib.scala 202:69] + node _T_325 = cat(_T_216[10], _T_216[9]) @[lib.scala 202:69] + node _T_326 = cat(_T_216[13], _T_216[12]) @[lib.scala 202:69] + node _T_327 = cat(_T_326, _T_216[11]) @[lib.scala 202:69] + node _T_328 = cat(_T_327, _T_325) @[lib.scala 202:69] + node _T_329 = cat(_T_216[15], _T_216[14]) @[lib.scala 202:69] + node _T_330 = cat(_T_216[18], _T_216[17]) @[lib.scala 202:69] + node _T_331 = cat(_T_330, _T_216[16]) @[lib.scala 202:69] + node _T_332 = cat(_T_331, _T_329) @[lib.scala 202:69] + node _T_333 = cat(_T_332, _T_328) @[lib.scala 202:69] + node _T_334 = cat(_T_333, _T_324) @[lib.scala 202:69] + node _T_335 = cat(_T_216[20], _T_216[19]) @[lib.scala 202:69] + node _T_336 = cat(_T_216[23], _T_216[22]) @[lib.scala 202:69] + node _T_337 = cat(_T_336, _T_216[21]) @[lib.scala 202:69] + node _T_338 = cat(_T_337, _T_335) @[lib.scala 202:69] + node _T_339 = cat(_T_216[25], _T_216[24]) @[lib.scala 202:69] + node _T_340 = cat(_T_216[28], _T_216[27]) @[lib.scala 202:69] + node _T_341 = cat(_T_340, _T_216[26]) @[lib.scala 202:69] + node _T_342 = cat(_T_341, _T_339) @[lib.scala 202:69] + node _T_343 = cat(_T_342, _T_338) @[lib.scala 202:69] + node _T_344 = cat(_T_216[30], _T_216[29]) @[lib.scala 202:69] + node _T_345 = cat(_T_216[33], _T_216[32]) @[lib.scala 202:69] + node _T_346 = cat(_T_345, _T_216[31]) @[lib.scala 202:69] + node _T_347 = cat(_T_346, _T_344) @[lib.scala 202:69] + node _T_348 = cat(_T_216[35], _T_216[34]) @[lib.scala 202:69] + node _T_349 = cat(_T_216[38], _T_216[37]) @[lib.scala 202:69] + node _T_350 = cat(_T_349, _T_216[36]) @[lib.scala 202:69] + node _T_351 = cat(_T_350, _T_348) @[lib.scala 202:69] + node _T_352 = cat(_T_351, _T_347) @[lib.scala 202:69] + node _T_353 = cat(_T_352, _T_343) @[lib.scala 202:69] + node _T_354 = cat(_T_353, _T_334) @[lib.scala 202:69] + node _T_355 = xor(_T_354, _T_315) @[lib.scala 202:76] + node _T_356 = mux(_T_316, _T_355, _T_315) @[lib.scala 202:31] + node _T_357 = bits(_T_356, 37, 32) @[lib.scala 204:37] + node _T_358 = bits(_T_356, 30, 16) @[lib.scala 204:61] + node _T_359 = bits(_T_356, 14, 8) @[lib.scala 204:86] + node _T_360 = bits(_T_356, 6, 4) @[lib.scala 204:110] + node _T_361 = bits(_T_356, 2, 2) @[lib.scala 204:133] + node _T_362 = cat(_T_360, _T_361) @[Cat.scala 29:58] + node _T_363 = cat(_T_357, _T_358) @[Cat.scala 29:58] + node _T_364 = cat(_T_363, _T_359) @[Cat.scala 29:58] + node sec_data_hi_any = cat(_T_364, _T_362) @[Cat.scala 29:58] + node _T_365 = bits(_T_356, 38, 38) @[lib.scala 205:39] + node _T_366 = bits(_T_208, 6, 0) @[lib.scala 205:56] + node _T_367 = eq(_T_366, UInt<7>("h040")) @[lib.scala 205:62] + node _T_368 = xor(_T_365, _T_367) @[lib.scala 205:44] + node _T_369 = bits(_T_356, 31, 31) @[lib.scala 205:102] + node _T_370 = bits(_T_356, 15, 15) @[lib.scala 205:124] + node _T_371 = bits(_T_356, 7, 7) @[lib.scala 205:146] + node _T_372 = bits(_T_356, 3, 3) @[lib.scala 205:167] + node _T_373 = bits(_T_356, 1, 0) @[lib.scala 205:188] + node _T_374 = cat(_T_371, _T_372) @[Cat.scala 29:58] + node _T_375 = cat(_T_374, _T_373) @[Cat.scala 29:58] + node _T_376 = cat(_T_368, _T_369) @[Cat.scala 29:58] + node _T_377 = cat(_T_376, _T_370) @[Cat.scala 29:58] + node ecc_out_hi_nc = cat(_T_377, _T_375) @[Cat.scala 29:58] + wire _T_378 : UInt<1>[18] @[lib.scala 173:18] + wire _T_379 : UInt<1>[18] @[lib.scala 174:18] + wire _T_380 : UInt<1>[18] @[lib.scala 175:18] + wire _T_381 : UInt<1>[15] @[lib.scala 176:18] + wire _T_382 : UInt<1>[15] @[lib.scala 177:18] + wire _T_383 : UInt<1>[6] @[lib.scala 178:18] + node _T_384 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 185:36] + _T_378[0] <= _T_384 @[lib.scala 185:30] + node _T_385 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 186:36] + _T_379[0] <= _T_385 @[lib.scala 186:30] + node _T_386 = bits(dccm_rdata_lo_any, 1, 1) @[lib.scala 185:36] + _T_378[1] <= _T_386 @[lib.scala 185:30] + node _T_387 = bits(dccm_rdata_lo_any, 1, 1) @[lib.scala 187:36] + _T_380[0] <= _T_387 @[lib.scala 187:30] + node _T_388 = bits(dccm_rdata_lo_any, 2, 2) @[lib.scala 186:36] + _T_379[1] <= _T_388 @[lib.scala 186:30] + node _T_389 = bits(dccm_rdata_lo_any, 2, 2) @[lib.scala 187:36] + _T_380[1] <= _T_389 @[lib.scala 187:30] + node _T_390 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 185:36] + _T_378[2] <= _T_390 @[lib.scala 185:30] + node _T_391 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 186:36] + _T_379[2] <= _T_391 @[lib.scala 186:30] + node _T_392 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 187:36] + _T_380[2] <= _T_392 @[lib.scala 187:30] + node _T_393 = bits(dccm_rdata_lo_any, 4, 4) @[lib.scala 185:36] + _T_378[3] <= _T_393 @[lib.scala 185:30] + node _T_394 = bits(dccm_rdata_lo_any, 4, 4) @[lib.scala 188:36] + _T_381[0] <= _T_394 @[lib.scala 188:30] + node _T_395 = bits(dccm_rdata_lo_any, 5, 5) @[lib.scala 186:36] + _T_379[3] <= _T_395 @[lib.scala 186:30] + node _T_396 = bits(dccm_rdata_lo_any, 5, 5) @[lib.scala 188:36] + _T_381[1] <= _T_396 @[lib.scala 188:30] + node _T_397 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 185:36] + _T_378[4] <= _T_397 @[lib.scala 185:30] + node _T_398 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 186:36] + _T_379[4] <= _T_398 @[lib.scala 186:30] + node _T_399 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 188:36] + _T_381[2] <= _T_399 @[lib.scala 188:30] + node _T_400 = bits(dccm_rdata_lo_any, 7, 7) @[lib.scala 187:36] + _T_380[3] <= _T_400 @[lib.scala 187:30] + node _T_401 = bits(dccm_rdata_lo_any, 7, 7) @[lib.scala 188:36] + _T_381[3] <= _T_401 @[lib.scala 188:30] + node _T_402 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 185:36] + _T_378[5] <= _T_402 @[lib.scala 185:30] + node _T_403 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 187:36] + _T_380[4] <= _T_403 @[lib.scala 187:30] + node _T_404 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 188:36] + _T_381[4] <= _T_404 @[lib.scala 188:30] + node _T_405 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 186:36] + _T_379[5] <= _T_405 @[lib.scala 186:30] + node _T_406 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 187:36] + _T_380[5] <= _T_406 @[lib.scala 187:30] + node _T_407 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 188:36] + _T_381[5] <= _T_407 @[lib.scala 188:30] + node _T_408 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 185:36] + _T_378[6] <= _T_408 @[lib.scala 185:30] + node _T_409 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 186:36] + _T_379[6] <= _T_409 @[lib.scala 186:30] + node _T_410 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 187:36] + _T_380[6] <= _T_410 @[lib.scala 187:30] + node _T_411 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 188:36] + _T_381[6] <= _T_411 @[lib.scala 188:30] + node _T_412 = bits(dccm_rdata_lo_any, 11, 11) @[lib.scala 185:36] + _T_378[7] <= _T_412 @[lib.scala 185:30] + node _T_413 = bits(dccm_rdata_lo_any, 11, 11) @[lib.scala 189:36] + _T_382[0] <= _T_413 @[lib.scala 189:30] + node _T_414 = bits(dccm_rdata_lo_any, 12, 12) @[lib.scala 186:36] + _T_379[7] <= _T_414 @[lib.scala 186:30] + node _T_415 = bits(dccm_rdata_lo_any, 12, 12) @[lib.scala 189:36] + _T_382[1] <= _T_415 @[lib.scala 189:30] + node _T_416 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 185:36] + _T_378[8] <= _T_416 @[lib.scala 185:30] + node _T_417 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 186:36] + _T_379[8] <= _T_417 @[lib.scala 186:30] + node _T_418 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 189:36] + _T_382[2] <= _T_418 @[lib.scala 189:30] + node _T_419 = bits(dccm_rdata_lo_any, 14, 14) @[lib.scala 187:36] + _T_380[7] <= _T_419 @[lib.scala 187:30] + node _T_420 = bits(dccm_rdata_lo_any, 14, 14) @[lib.scala 189:36] + _T_382[3] <= _T_420 @[lib.scala 189:30] + node _T_421 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 185:36] + _T_378[9] <= _T_421 @[lib.scala 185:30] + node _T_422 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 187:36] + _T_380[8] <= _T_422 @[lib.scala 187:30] + node _T_423 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 189:36] + _T_382[4] <= _T_423 @[lib.scala 189:30] + node _T_424 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 186:36] + _T_379[9] <= _T_424 @[lib.scala 186:30] + node _T_425 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 187:36] + _T_380[9] <= _T_425 @[lib.scala 187:30] + node _T_426 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 189:36] + _T_382[5] <= _T_426 @[lib.scala 189:30] + node _T_427 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 185:36] + _T_378[10] <= _T_427 @[lib.scala 185:30] + node _T_428 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 186:36] + _T_379[10] <= _T_428 @[lib.scala 186:30] + node _T_429 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 187:36] + _T_380[10] <= _T_429 @[lib.scala 187:30] + node _T_430 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 189:36] + _T_382[6] <= _T_430 @[lib.scala 189:30] + node _T_431 = bits(dccm_rdata_lo_any, 18, 18) @[lib.scala 188:36] + _T_381[7] <= _T_431 @[lib.scala 188:30] + node _T_432 = bits(dccm_rdata_lo_any, 18, 18) @[lib.scala 189:36] + _T_382[7] <= _T_432 @[lib.scala 189:30] + node _T_433 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 185:36] + _T_378[11] <= _T_433 @[lib.scala 185:30] + node _T_434 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 188:36] + _T_381[8] <= _T_434 @[lib.scala 188:30] + node _T_435 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 189:36] + _T_382[8] <= _T_435 @[lib.scala 189:30] + node _T_436 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 186:36] + _T_379[11] <= _T_436 @[lib.scala 186:30] + node _T_437 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 188:36] + _T_381[9] <= _T_437 @[lib.scala 188:30] + node _T_438 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 189:36] + _T_382[9] <= _T_438 @[lib.scala 189:30] + node _T_439 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 185:36] + _T_378[12] <= _T_439 @[lib.scala 185:30] + node _T_440 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 186:36] + _T_379[12] <= _T_440 @[lib.scala 186:30] + node _T_441 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 188:36] + _T_381[10] <= _T_441 @[lib.scala 188:30] + node _T_442 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 189:36] + _T_382[10] <= _T_442 @[lib.scala 189:30] + node _T_443 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 187:36] + _T_380[11] <= _T_443 @[lib.scala 187:30] + node _T_444 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 188:36] + _T_381[11] <= _T_444 @[lib.scala 188:30] + node _T_445 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 189:36] + _T_382[11] <= _T_445 @[lib.scala 189:30] + node _T_446 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 185:36] + _T_378[13] <= _T_446 @[lib.scala 185:30] + node _T_447 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 187:36] + _T_380[12] <= _T_447 @[lib.scala 187:30] + node _T_448 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 188:36] + _T_381[12] <= _T_448 @[lib.scala 188:30] + node _T_449 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 189:36] + _T_382[12] <= _T_449 @[lib.scala 189:30] + node _T_450 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 186:36] + _T_379[13] <= _T_450 @[lib.scala 186:30] + node _T_451 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 187:36] + _T_380[13] <= _T_451 @[lib.scala 187:30] + node _T_452 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 188:36] + _T_381[13] <= _T_452 @[lib.scala 188:30] + node _T_453 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 189:36] + _T_382[13] <= _T_453 @[lib.scala 189:30] + node _T_454 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 185:36] + _T_378[14] <= _T_454 @[lib.scala 185:30] + node _T_455 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 186:36] + _T_379[14] <= _T_455 @[lib.scala 186:30] + node _T_456 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 187:36] + _T_380[14] <= _T_456 @[lib.scala 187:30] + node _T_457 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 188:36] + _T_381[14] <= _T_457 @[lib.scala 188:30] + node _T_458 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 189:36] + _T_382[14] <= _T_458 @[lib.scala 189:30] + node _T_459 = bits(dccm_rdata_lo_any, 26, 26) @[lib.scala 185:36] + _T_378[15] <= _T_459 @[lib.scala 185:30] + node _T_460 = bits(dccm_rdata_lo_any, 26, 26) @[lib.scala 190:36] + _T_383[0] <= _T_460 @[lib.scala 190:30] + node _T_461 = bits(dccm_rdata_lo_any, 27, 27) @[lib.scala 186:36] + _T_379[15] <= _T_461 @[lib.scala 186:30] + node _T_462 = bits(dccm_rdata_lo_any, 27, 27) @[lib.scala 190:36] + _T_383[1] <= _T_462 @[lib.scala 190:30] + node _T_463 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 185:36] + _T_378[16] <= _T_463 @[lib.scala 185:30] + node _T_464 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 186:36] + _T_379[16] <= _T_464 @[lib.scala 186:30] + node _T_465 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 190:36] + _T_383[2] <= _T_465 @[lib.scala 190:30] + node _T_466 = bits(dccm_rdata_lo_any, 29, 29) @[lib.scala 187:36] + _T_380[15] <= _T_466 @[lib.scala 187:30] + node _T_467 = bits(dccm_rdata_lo_any, 29, 29) @[lib.scala 190:36] + _T_383[3] <= _T_467 @[lib.scala 190:30] + node _T_468 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 185:36] + _T_378[17] <= _T_468 @[lib.scala 185:30] + node _T_469 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 187:36] + _T_380[16] <= _T_469 @[lib.scala 187:30] + node _T_470 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 190:36] + _T_383[4] <= _T_470 @[lib.scala 190:30] + node _T_471 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 186:36] + _T_379[17] <= _T_471 @[lib.scala 186:30] + node _T_472 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 187:36] + _T_380[17] <= _T_472 @[lib.scala 187:30] + node _T_473 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 190:36] + _T_383[5] <= _T_473 @[lib.scala 190:30] + node _T_474 = xorr(dccm_rdata_lo_any) @[lib.scala 193:30] + node _T_475 = xorr(dccm_data_ecc_lo_any) @[lib.scala 193:44] + node _T_476 = xor(_T_474, _T_475) @[lib.scala 193:35] + node _T_477 = not(UInt<1>("h00")) @[lib.scala 193:52] + node _T_478 = and(_T_476, _T_477) @[lib.scala 193:50] + node _T_479 = bits(dccm_data_ecc_lo_any, 5, 5) @[lib.scala 193:68] + node _T_480 = cat(_T_383[2], _T_383[1]) @[lib.scala 193:76] + node _T_481 = cat(_T_480, _T_383[0]) @[lib.scala 193:76] + node _T_482 = cat(_T_383[5], _T_383[4]) @[lib.scala 193:76] + node _T_483 = cat(_T_482, _T_383[3]) @[lib.scala 193:76] + node _T_484 = cat(_T_483, _T_481) @[lib.scala 193:76] + node _T_485 = xorr(_T_484) @[lib.scala 193:83] + node _T_486 = xor(_T_479, _T_485) @[lib.scala 193:71] + node _T_487 = bits(dccm_data_ecc_lo_any, 4, 4) @[lib.scala 193:95] + node _T_488 = cat(_T_382[2], _T_382[1]) @[lib.scala 193:103] + node _T_489 = cat(_T_488, _T_382[0]) @[lib.scala 193:103] + node _T_490 = cat(_T_382[4], _T_382[3]) @[lib.scala 193:103] + node _T_491 = cat(_T_382[6], _T_382[5]) @[lib.scala 193:103] + node _T_492 = cat(_T_491, _T_490) @[lib.scala 193:103] + node _T_493 = cat(_T_492, _T_489) @[lib.scala 193:103] + node _T_494 = cat(_T_382[8], _T_382[7]) @[lib.scala 193:103] + node _T_495 = cat(_T_382[10], _T_382[9]) @[lib.scala 193:103] + node _T_496 = cat(_T_495, _T_494) @[lib.scala 193:103] + node _T_497 = cat(_T_382[12], _T_382[11]) @[lib.scala 193:103] + node _T_498 = cat(_T_382[14], _T_382[13]) @[lib.scala 193:103] + node _T_499 = cat(_T_498, _T_497) @[lib.scala 193:103] + node _T_500 = cat(_T_499, _T_496) @[lib.scala 193:103] + node _T_501 = cat(_T_500, _T_493) @[lib.scala 193:103] + node _T_502 = xorr(_T_501) @[lib.scala 193:110] + node _T_503 = xor(_T_487, _T_502) @[lib.scala 193:98] + node _T_504 = bits(dccm_data_ecc_lo_any, 3, 3) @[lib.scala 193:122] + node _T_505 = cat(_T_381[2], _T_381[1]) @[lib.scala 193:130] + node _T_506 = cat(_T_505, _T_381[0]) @[lib.scala 193:130] + node _T_507 = cat(_T_381[4], _T_381[3]) @[lib.scala 193:130] + node _T_508 = cat(_T_381[6], _T_381[5]) @[lib.scala 193:130] + node _T_509 = cat(_T_508, _T_507) @[lib.scala 193:130] + node _T_510 = cat(_T_509, _T_506) @[lib.scala 193:130] + node _T_511 = cat(_T_381[8], _T_381[7]) @[lib.scala 193:130] + node _T_512 = cat(_T_381[10], _T_381[9]) @[lib.scala 193:130] + node _T_513 = cat(_T_512, _T_511) @[lib.scala 193:130] + node _T_514 = cat(_T_381[12], _T_381[11]) @[lib.scala 193:130] + node _T_515 = cat(_T_381[14], _T_381[13]) @[lib.scala 193:130] + node _T_516 = cat(_T_515, _T_514) @[lib.scala 193:130] + node _T_517 = cat(_T_516, _T_513) @[lib.scala 193:130] + node _T_518 = cat(_T_517, _T_510) @[lib.scala 193:130] + node _T_519 = xorr(_T_518) @[lib.scala 193:137] + node _T_520 = xor(_T_504, _T_519) @[lib.scala 193:125] + node _T_521 = bits(dccm_data_ecc_lo_any, 2, 2) @[lib.scala 193:149] + node _T_522 = cat(_T_380[1], _T_380[0]) @[lib.scala 193:157] + node _T_523 = cat(_T_380[3], _T_380[2]) @[lib.scala 193:157] + node _T_524 = cat(_T_523, _T_522) @[lib.scala 193:157] + node _T_525 = cat(_T_380[5], _T_380[4]) @[lib.scala 193:157] + node _T_526 = cat(_T_380[8], _T_380[7]) @[lib.scala 193:157] + node _T_527 = cat(_T_526, _T_380[6]) @[lib.scala 193:157] + node _T_528 = cat(_T_527, _T_525) @[lib.scala 193:157] + node _T_529 = cat(_T_528, _T_524) @[lib.scala 193:157] + node _T_530 = cat(_T_380[10], _T_380[9]) @[lib.scala 193:157] + node _T_531 = cat(_T_380[12], _T_380[11]) @[lib.scala 193:157] + node _T_532 = cat(_T_531, _T_530) @[lib.scala 193:157] + node _T_533 = cat(_T_380[14], _T_380[13]) @[lib.scala 193:157] + node _T_534 = cat(_T_380[17], _T_380[16]) @[lib.scala 193:157] + node _T_535 = cat(_T_534, _T_380[15]) @[lib.scala 193:157] + node _T_536 = cat(_T_535, _T_533) @[lib.scala 193:157] + node _T_537 = cat(_T_536, _T_532) @[lib.scala 193:157] + node _T_538 = cat(_T_537, _T_529) @[lib.scala 193:157] + node _T_539 = xorr(_T_538) @[lib.scala 193:164] + node _T_540 = xor(_T_521, _T_539) @[lib.scala 193:152] + node _T_541 = bits(dccm_data_ecc_lo_any, 1, 1) @[lib.scala 193:176] + node _T_542 = cat(_T_379[1], _T_379[0]) @[lib.scala 193:184] + node _T_543 = cat(_T_379[3], _T_379[2]) @[lib.scala 193:184] + node _T_544 = cat(_T_543, _T_542) @[lib.scala 193:184] + node _T_545 = cat(_T_379[5], _T_379[4]) @[lib.scala 193:184] + node _T_546 = cat(_T_379[8], _T_379[7]) @[lib.scala 193:184] + node _T_547 = cat(_T_546, _T_379[6]) @[lib.scala 193:184] + node _T_548 = cat(_T_547, _T_545) @[lib.scala 193:184] + node _T_549 = cat(_T_548, _T_544) @[lib.scala 193:184] + node _T_550 = cat(_T_379[10], _T_379[9]) @[lib.scala 193:184] + node _T_551 = cat(_T_379[12], _T_379[11]) @[lib.scala 193:184] + node _T_552 = cat(_T_551, _T_550) @[lib.scala 193:184] + node _T_553 = cat(_T_379[14], _T_379[13]) @[lib.scala 193:184] + node _T_554 = cat(_T_379[17], _T_379[16]) @[lib.scala 193:184] + node _T_555 = cat(_T_554, _T_379[15]) @[lib.scala 193:184] + node _T_556 = cat(_T_555, _T_553) @[lib.scala 193:184] + node _T_557 = cat(_T_556, _T_552) @[lib.scala 193:184] + node _T_558 = cat(_T_557, _T_549) @[lib.scala 193:184] + node _T_559 = xorr(_T_558) @[lib.scala 193:191] + node _T_560 = xor(_T_541, _T_559) @[lib.scala 193:179] + node _T_561 = bits(dccm_data_ecc_lo_any, 0, 0) @[lib.scala 193:203] + node _T_562 = cat(_T_378[1], _T_378[0]) @[lib.scala 193:211] + node _T_563 = cat(_T_378[3], _T_378[2]) @[lib.scala 193:211] + node _T_564 = cat(_T_563, _T_562) @[lib.scala 193:211] + node _T_565 = cat(_T_378[5], _T_378[4]) @[lib.scala 193:211] + node _T_566 = cat(_T_378[8], _T_378[7]) @[lib.scala 193:211] + node _T_567 = cat(_T_566, _T_378[6]) @[lib.scala 193:211] + node _T_568 = cat(_T_567, _T_565) @[lib.scala 193:211] + node _T_569 = cat(_T_568, _T_564) @[lib.scala 193:211] + node _T_570 = cat(_T_378[10], _T_378[9]) @[lib.scala 193:211] + node _T_571 = cat(_T_378[12], _T_378[11]) @[lib.scala 193:211] + node _T_572 = cat(_T_571, _T_570) @[lib.scala 193:211] + node _T_573 = cat(_T_378[14], _T_378[13]) @[lib.scala 193:211] + node _T_574 = cat(_T_378[17], _T_378[16]) @[lib.scala 193:211] + node _T_575 = cat(_T_574, _T_378[15]) @[lib.scala 193:211] + node _T_576 = cat(_T_575, _T_573) @[lib.scala 193:211] + node _T_577 = cat(_T_576, _T_572) @[lib.scala 193:211] + node _T_578 = cat(_T_577, _T_569) @[lib.scala 193:211] + node _T_579 = xorr(_T_578) @[lib.scala 193:218] + node _T_580 = xor(_T_561, _T_579) @[lib.scala 193:206] + node _T_581 = cat(_T_540, _T_560) @[Cat.scala 29:58] + node _T_582 = cat(_T_581, _T_580) @[Cat.scala 29:58] + node _T_583 = cat(_T_503, _T_520) @[Cat.scala 29:58] + node _T_584 = cat(_T_478, _T_486) @[Cat.scala 29:58] + node _T_585 = cat(_T_584, _T_583) @[Cat.scala 29:58] + node _T_586 = cat(_T_585, _T_582) @[Cat.scala 29:58] + node _T_587 = neq(_T_586, UInt<1>("h00")) @[lib.scala 194:44] + node _T_588 = and(is_ldst_lo_any, _T_587) @[lib.scala 194:32] + node _T_589 = bits(_T_586, 6, 6) @[lib.scala 194:64] + node single_ecc_error_lo_any = and(_T_588, _T_589) @[lib.scala 194:53] + node _T_590 = neq(_T_586, UInt<1>("h00")) @[lib.scala 195:44] + node _T_591 = and(is_ldst_lo_any, _T_590) @[lib.scala 195:32] + node _T_592 = bits(_T_586, 6, 6) @[lib.scala 195:65] + node _T_593 = not(_T_592) @[lib.scala 195:55] + node double_ecc_error_lo_any = and(_T_591, _T_593) @[lib.scala 195:53] + wire _T_594 : UInt<1>[39] @[lib.scala 196:26] + node _T_595 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_596 = eq(_T_595, UInt<1>("h01")) @[lib.scala 199:41] + _T_594[0] <= _T_596 @[lib.scala 199:23] + node _T_597 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_598 = eq(_T_597, UInt<2>("h02")) @[lib.scala 199:41] + _T_594[1] <= _T_598 @[lib.scala 199:23] + node _T_599 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_600 = eq(_T_599, UInt<2>("h03")) @[lib.scala 199:41] + _T_594[2] <= _T_600 @[lib.scala 199:23] + node _T_601 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_602 = eq(_T_601, UInt<3>("h04")) @[lib.scala 199:41] + _T_594[3] <= _T_602 @[lib.scala 199:23] + node _T_603 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_604 = eq(_T_603, UInt<3>("h05")) @[lib.scala 199:41] + _T_594[4] <= _T_604 @[lib.scala 199:23] + node _T_605 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_606 = eq(_T_605, UInt<3>("h06")) @[lib.scala 199:41] + _T_594[5] <= _T_606 @[lib.scala 199:23] + node _T_607 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_608 = eq(_T_607, UInt<3>("h07")) @[lib.scala 199:41] + _T_594[6] <= _T_608 @[lib.scala 199:23] + node _T_609 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_610 = eq(_T_609, UInt<4>("h08")) @[lib.scala 199:41] + _T_594[7] <= _T_610 @[lib.scala 199:23] + node _T_611 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_612 = eq(_T_611, UInt<4>("h09")) @[lib.scala 199:41] + _T_594[8] <= _T_612 @[lib.scala 199:23] + node _T_613 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_614 = eq(_T_613, UInt<4>("h0a")) @[lib.scala 199:41] + _T_594[9] <= _T_614 @[lib.scala 199:23] + node _T_615 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_616 = eq(_T_615, UInt<4>("h0b")) @[lib.scala 199:41] + _T_594[10] <= _T_616 @[lib.scala 199:23] + node _T_617 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_618 = eq(_T_617, UInt<4>("h0c")) @[lib.scala 199:41] + _T_594[11] <= _T_618 @[lib.scala 199:23] + node _T_619 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_620 = eq(_T_619, UInt<4>("h0d")) @[lib.scala 199:41] + _T_594[12] <= _T_620 @[lib.scala 199:23] + node _T_621 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_622 = eq(_T_621, UInt<4>("h0e")) @[lib.scala 199:41] + _T_594[13] <= _T_622 @[lib.scala 199:23] + node _T_623 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_624 = eq(_T_623, UInt<4>("h0f")) @[lib.scala 199:41] + _T_594[14] <= _T_624 @[lib.scala 199:23] + node _T_625 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_626 = eq(_T_625, UInt<5>("h010")) @[lib.scala 199:41] + _T_594[15] <= _T_626 @[lib.scala 199:23] + node _T_627 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_628 = eq(_T_627, UInt<5>("h011")) @[lib.scala 199:41] + _T_594[16] <= _T_628 @[lib.scala 199:23] + node _T_629 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_630 = eq(_T_629, UInt<5>("h012")) @[lib.scala 199:41] + _T_594[17] <= _T_630 @[lib.scala 199:23] + node _T_631 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_632 = eq(_T_631, UInt<5>("h013")) @[lib.scala 199:41] + _T_594[18] <= _T_632 @[lib.scala 199:23] + node _T_633 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_634 = eq(_T_633, UInt<5>("h014")) @[lib.scala 199:41] + _T_594[19] <= _T_634 @[lib.scala 199:23] + node _T_635 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_636 = eq(_T_635, UInt<5>("h015")) @[lib.scala 199:41] + _T_594[20] <= _T_636 @[lib.scala 199:23] + node _T_637 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_638 = eq(_T_637, UInt<5>("h016")) @[lib.scala 199:41] + _T_594[21] <= _T_638 @[lib.scala 199:23] + node _T_639 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_640 = eq(_T_639, UInt<5>("h017")) @[lib.scala 199:41] + _T_594[22] <= _T_640 @[lib.scala 199:23] + node _T_641 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_642 = eq(_T_641, UInt<5>("h018")) @[lib.scala 199:41] + _T_594[23] <= _T_642 @[lib.scala 199:23] + node _T_643 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_644 = eq(_T_643, UInt<5>("h019")) @[lib.scala 199:41] + _T_594[24] <= _T_644 @[lib.scala 199:23] + node _T_645 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_646 = eq(_T_645, UInt<5>("h01a")) @[lib.scala 199:41] + _T_594[25] <= _T_646 @[lib.scala 199:23] + node _T_647 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_648 = eq(_T_647, UInt<5>("h01b")) @[lib.scala 199:41] + _T_594[26] <= _T_648 @[lib.scala 199:23] + node _T_649 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_650 = eq(_T_649, UInt<5>("h01c")) @[lib.scala 199:41] + _T_594[27] <= _T_650 @[lib.scala 199:23] + node _T_651 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_652 = eq(_T_651, UInt<5>("h01d")) @[lib.scala 199:41] + _T_594[28] <= _T_652 @[lib.scala 199:23] + node _T_653 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_654 = eq(_T_653, UInt<5>("h01e")) @[lib.scala 199:41] + _T_594[29] <= _T_654 @[lib.scala 199:23] + node _T_655 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_656 = eq(_T_655, UInt<5>("h01f")) @[lib.scala 199:41] + _T_594[30] <= _T_656 @[lib.scala 199:23] + node _T_657 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_658 = eq(_T_657, UInt<6>("h020")) @[lib.scala 199:41] + _T_594[31] <= _T_658 @[lib.scala 199:23] + node _T_659 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_660 = eq(_T_659, UInt<6>("h021")) @[lib.scala 199:41] + _T_594[32] <= _T_660 @[lib.scala 199:23] + node _T_661 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_662 = eq(_T_661, UInt<6>("h022")) @[lib.scala 199:41] + _T_594[33] <= _T_662 @[lib.scala 199:23] + node _T_663 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_664 = eq(_T_663, UInt<6>("h023")) @[lib.scala 199:41] + _T_594[34] <= _T_664 @[lib.scala 199:23] + node _T_665 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_666 = eq(_T_665, UInt<6>("h024")) @[lib.scala 199:41] + _T_594[35] <= _T_666 @[lib.scala 199:23] + node _T_667 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_668 = eq(_T_667, UInt<6>("h025")) @[lib.scala 199:41] + _T_594[36] <= _T_668 @[lib.scala 199:23] + node _T_669 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_670 = eq(_T_669, UInt<6>("h026")) @[lib.scala 199:41] + _T_594[37] <= _T_670 @[lib.scala 199:23] + node _T_671 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_672 = eq(_T_671, UInt<6>("h027")) @[lib.scala 199:41] + _T_594[38] <= _T_672 @[lib.scala 199:23] + node _T_673 = bits(dccm_data_ecc_lo_any, 6, 6) @[lib.scala 201:37] + node _T_674 = bits(dccm_rdata_lo_any, 31, 26) @[lib.scala 201:45] + node _T_675 = bits(dccm_data_ecc_lo_any, 5, 5) @[lib.scala 201:60] + node _T_676 = bits(dccm_rdata_lo_any, 25, 11) @[lib.scala 201:68] + node _T_677 = bits(dccm_data_ecc_lo_any, 4, 4) @[lib.scala 201:83] + node _T_678 = bits(dccm_rdata_lo_any, 10, 4) @[lib.scala 201:91] + node _T_679 = bits(dccm_data_ecc_lo_any, 3, 3) @[lib.scala 201:105] + node _T_680 = bits(dccm_rdata_lo_any, 3, 1) @[lib.scala 201:113] + node _T_681 = bits(dccm_data_ecc_lo_any, 2, 2) @[lib.scala 201:126] + node _T_682 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 201:134] + node _T_683 = bits(dccm_data_ecc_lo_any, 1, 0) @[lib.scala 201:145] + node _T_684 = cat(_T_682, _T_683) @[Cat.scala 29:58] + node _T_685 = cat(_T_679, _T_680) @[Cat.scala 29:58] + node _T_686 = cat(_T_685, _T_681) @[Cat.scala 29:58] + node _T_687 = cat(_T_686, _T_684) @[Cat.scala 29:58] + node _T_688 = cat(_T_676, _T_677) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_678) @[Cat.scala 29:58] + node _T_690 = cat(_T_673, _T_674) @[Cat.scala 29:58] + node _T_691 = cat(_T_690, _T_675) @[Cat.scala 29:58] + node _T_692 = cat(_T_691, _T_689) @[Cat.scala 29:58] + node _T_693 = cat(_T_692, _T_687) @[Cat.scala 29:58] + node _T_694 = bits(single_ecc_error_lo_any, 0, 0) @[lib.scala 202:49] + node _T_695 = cat(_T_594[1], _T_594[0]) @[lib.scala 202:69] + node _T_696 = cat(_T_594[3], _T_594[2]) @[lib.scala 202:69] + node _T_697 = cat(_T_696, _T_695) @[lib.scala 202:69] + node _T_698 = cat(_T_594[5], _T_594[4]) @[lib.scala 202:69] + node _T_699 = cat(_T_594[8], _T_594[7]) @[lib.scala 202:69] + node _T_700 = cat(_T_699, _T_594[6]) @[lib.scala 202:69] + node _T_701 = cat(_T_700, _T_698) @[lib.scala 202:69] + node _T_702 = cat(_T_701, _T_697) @[lib.scala 202:69] + node _T_703 = cat(_T_594[10], _T_594[9]) @[lib.scala 202:69] + node _T_704 = cat(_T_594[13], _T_594[12]) @[lib.scala 202:69] + node _T_705 = cat(_T_704, _T_594[11]) @[lib.scala 202:69] + node _T_706 = cat(_T_705, _T_703) @[lib.scala 202:69] + node _T_707 = cat(_T_594[15], _T_594[14]) @[lib.scala 202:69] + node _T_708 = cat(_T_594[18], _T_594[17]) @[lib.scala 202:69] + node _T_709 = cat(_T_708, _T_594[16]) @[lib.scala 202:69] + node _T_710 = cat(_T_709, _T_707) @[lib.scala 202:69] + node _T_711 = cat(_T_710, _T_706) @[lib.scala 202:69] + node _T_712 = cat(_T_711, _T_702) @[lib.scala 202:69] + node _T_713 = cat(_T_594[20], _T_594[19]) @[lib.scala 202:69] + node _T_714 = cat(_T_594[23], _T_594[22]) @[lib.scala 202:69] + node _T_715 = cat(_T_714, _T_594[21]) @[lib.scala 202:69] + node _T_716 = cat(_T_715, _T_713) @[lib.scala 202:69] + node _T_717 = cat(_T_594[25], _T_594[24]) @[lib.scala 202:69] + node _T_718 = cat(_T_594[28], _T_594[27]) @[lib.scala 202:69] + node _T_719 = cat(_T_718, _T_594[26]) @[lib.scala 202:69] + node _T_720 = cat(_T_719, _T_717) @[lib.scala 202:69] + node _T_721 = cat(_T_720, _T_716) @[lib.scala 202:69] + node _T_722 = cat(_T_594[30], _T_594[29]) @[lib.scala 202:69] + node _T_723 = cat(_T_594[33], _T_594[32]) @[lib.scala 202:69] + node _T_724 = cat(_T_723, _T_594[31]) @[lib.scala 202:69] + node _T_725 = cat(_T_724, _T_722) @[lib.scala 202:69] + node _T_726 = cat(_T_594[35], _T_594[34]) @[lib.scala 202:69] + node _T_727 = cat(_T_594[38], _T_594[37]) @[lib.scala 202:69] + node _T_728 = cat(_T_727, _T_594[36]) @[lib.scala 202:69] + node _T_729 = cat(_T_728, _T_726) @[lib.scala 202:69] + node _T_730 = cat(_T_729, _T_725) @[lib.scala 202:69] + node _T_731 = cat(_T_730, _T_721) @[lib.scala 202:69] + node _T_732 = cat(_T_731, _T_712) @[lib.scala 202:69] + node _T_733 = xor(_T_732, _T_693) @[lib.scala 202:76] + node _T_734 = mux(_T_694, _T_733, _T_693) @[lib.scala 202:31] + node _T_735 = bits(_T_734, 37, 32) @[lib.scala 204:37] + node _T_736 = bits(_T_734, 30, 16) @[lib.scala 204:61] + node _T_737 = bits(_T_734, 14, 8) @[lib.scala 204:86] + node _T_738 = bits(_T_734, 6, 4) @[lib.scala 204:110] + node _T_739 = bits(_T_734, 2, 2) @[lib.scala 204:133] + node _T_740 = cat(_T_738, _T_739) @[Cat.scala 29:58] + node _T_741 = cat(_T_735, _T_736) @[Cat.scala 29:58] + node _T_742 = cat(_T_741, _T_737) @[Cat.scala 29:58] + node sec_data_lo_any = cat(_T_742, _T_740) @[Cat.scala 29:58] + node _T_743 = bits(_T_734, 38, 38) @[lib.scala 205:39] + node _T_744 = bits(_T_586, 6, 0) @[lib.scala 205:56] + node _T_745 = eq(_T_744, UInt<7>("h040")) @[lib.scala 205:62] + node _T_746 = xor(_T_743, _T_745) @[lib.scala 205:44] + node _T_747 = bits(_T_734, 31, 31) @[lib.scala 205:102] + node _T_748 = bits(_T_734, 15, 15) @[lib.scala 205:124] + node _T_749 = bits(_T_734, 7, 7) @[lib.scala 205:146] + node _T_750 = bits(_T_734, 3, 3) @[lib.scala 205:167] + node _T_751 = bits(_T_734, 1, 0) @[lib.scala 205:188] + node _T_752 = cat(_T_749, _T_750) @[Cat.scala 29:58] + node _T_753 = cat(_T_752, _T_751) @[Cat.scala 29:58] + node _T_754 = cat(_T_746, _T_747) @[Cat.scala 29:58] + node _T_755 = cat(_T_754, _T_748) @[Cat.scala 29:58] + node ecc_out_lo_nc = cat(_T_755, _T_753) @[Cat.scala 29:58] + node _T_756 = bits(dccm_wdata_lo_any, 0, 0) @[lib.scala 119:58] + node _T_757 = bits(dccm_wdata_lo_any, 1, 1) @[lib.scala 119:58] + node _T_758 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_759 = bits(dccm_wdata_lo_any, 4, 4) @[lib.scala 119:58] + node _T_760 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_761 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_762 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_763 = bits(dccm_wdata_lo_any, 11, 11) @[lib.scala 119:58] + node _T_764 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_765 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_766 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_767 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_768 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_769 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_770 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_771 = bits(dccm_wdata_lo_any, 26, 26) @[lib.scala 119:58] + node _T_772 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_773 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_774 = xor(_T_756, _T_757) @[lib.scala 119:74] + node _T_775 = xor(_T_774, _T_758) @[lib.scala 119:74] + node _T_776 = xor(_T_775, _T_759) @[lib.scala 119:74] + node _T_777 = xor(_T_776, _T_760) @[lib.scala 119:74] + node _T_778 = xor(_T_777, _T_761) @[lib.scala 119:74] + node _T_779 = xor(_T_778, _T_762) @[lib.scala 119:74] + node _T_780 = xor(_T_779, _T_763) @[lib.scala 119:74] + node _T_781 = xor(_T_780, _T_764) @[lib.scala 119:74] + node _T_782 = xor(_T_781, _T_765) @[lib.scala 119:74] + node _T_783 = xor(_T_782, _T_766) @[lib.scala 119:74] + node _T_784 = xor(_T_783, _T_767) @[lib.scala 119:74] + node _T_785 = xor(_T_784, _T_768) @[lib.scala 119:74] + node _T_786 = xor(_T_785, _T_769) @[lib.scala 119:74] + node _T_787 = xor(_T_786, _T_770) @[lib.scala 119:74] + node _T_788 = xor(_T_787, _T_771) @[lib.scala 119:74] + node _T_789 = xor(_T_788, _T_772) @[lib.scala 119:74] + node _T_790 = xor(_T_789, _T_773) @[lib.scala 119:74] + node _T_791 = bits(dccm_wdata_lo_any, 0, 0) @[lib.scala 119:58] + node _T_792 = bits(dccm_wdata_lo_any, 2, 2) @[lib.scala 119:58] + node _T_793 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_794 = bits(dccm_wdata_lo_any, 5, 5) @[lib.scala 119:58] + node _T_795 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_796 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_797 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_798 = bits(dccm_wdata_lo_any, 12, 12) @[lib.scala 119:58] + node _T_799 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_800 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_801 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_802 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_803 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_804 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_805 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_806 = bits(dccm_wdata_lo_any, 27, 27) @[lib.scala 119:58] + node _T_807 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_808 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_809 = xor(_T_791, _T_792) @[lib.scala 119:74] + node _T_810 = xor(_T_809, _T_793) @[lib.scala 119:74] + node _T_811 = xor(_T_810, _T_794) @[lib.scala 119:74] + node _T_812 = xor(_T_811, _T_795) @[lib.scala 119:74] + node _T_813 = xor(_T_812, _T_796) @[lib.scala 119:74] + node _T_814 = xor(_T_813, _T_797) @[lib.scala 119:74] + node _T_815 = xor(_T_814, _T_798) @[lib.scala 119:74] + node _T_816 = xor(_T_815, _T_799) @[lib.scala 119:74] + node _T_817 = xor(_T_816, _T_800) @[lib.scala 119:74] + node _T_818 = xor(_T_817, _T_801) @[lib.scala 119:74] + node _T_819 = xor(_T_818, _T_802) @[lib.scala 119:74] + node _T_820 = xor(_T_819, _T_803) @[lib.scala 119:74] + node _T_821 = xor(_T_820, _T_804) @[lib.scala 119:74] + node _T_822 = xor(_T_821, _T_805) @[lib.scala 119:74] + node _T_823 = xor(_T_822, _T_806) @[lib.scala 119:74] + node _T_824 = xor(_T_823, _T_807) @[lib.scala 119:74] + node _T_825 = xor(_T_824, _T_808) @[lib.scala 119:74] + node _T_826 = bits(dccm_wdata_lo_any, 1, 1) @[lib.scala 119:58] + node _T_827 = bits(dccm_wdata_lo_any, 2, 2) @[lib.scala 119:58] + node _T_828 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_829 = bits(dccm_wdata_lo_any, 7, 7) @[lib.scala 119:58] + node _T_830 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_831 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_832 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_833 = bits(dccm_wdata_lo_any, 14, 14) @[lib.scala 119:58] + node _T_834 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_835 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_836 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_837 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_838 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_839 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_840 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_841 = bits(dccm_wdata_lo_any, 29, 29) @[lib.scala 119:58] + node _T_842 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_843 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_844 = xor(_T_826, _T_827) @[lib.scala 119:74] + node _T_845 = xor(_T_844, _T_828) @[lib.scala 119:74] + node _T_846 = xor(_T_845, _T_829) @[lib.scala 119:74] + node _T_847 = xor(_T_846, _T_830) @[lib.scala 119:74] + node _T_848 = xor(_T_847, _T_831) @[lib.scala 119:74] + node _T_849 = xor(_T_848, _T_832) @[lib.scala 119:74] + node _T_850 = xor(_T_849, _T_833) @[lib.scala 119:74] + node _T_851 = xor(_T_850, _T_834) @[lib.scala 119:74] + node _T_852 = xor(_T_851, _T_835) @[lib.scala 119:74] + node _T_853 = xor(_T_852, _T_836) @[lib.scala 119:74] + node _T_854 = xor(_T_853, _T_837) @[lib.scala 119:74] + node _T_855 = xor(_T_854, _T_838) @[lib.scala 119:74] + node _T_856 = xor(_T_855, _T_839) @[lib.scala 119:74] + node _T_857 = xor(_T_856, _T_840) @[lib.scala 119:74] + node _T_858 = xor(_T_857, _T_841) @[lib.scala 119:74] + node _T_859 = xor(_T_858, _T_842) @[lib.scala 119:74] + node _T_860 = xor(_T_859, _T_843) @[lib.scala 119:74] + node _T_861 = bits(dccm_wdata_lo_any, 4, 4) @[lib.scala 119:58] + node _T_862 = bits(dccm_wdata_lo_any, 5, 5) @[lib.scala 119:58] + node _T_863 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_864 = bits(dccm_wdata_lo_any, 7, 7) @[lib.scala 119:58] + node _T_865 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_866 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_867 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_868 = bits(dccm_wdata_lo_any, 18, 18) @[lib.scala 119:58] + node _T_869 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_870 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_871 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_872 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_873 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_874 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_875 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_876 = xor(_T_861, _T_862) @[lib.scala 119:74] + node _T_877 = xor(_T_876, _T_863) @[lib.scala 119:74] + node _T_878 = xor(_T_877, _T_864) @[lib.scala 119:74] + node _T_879 = xor(_T_878, _T_865) @[lib.scala 119:74] + node _T_880 = xor(_T_879, _T_866) @[lib.scala 119:74] + node _T_881 = xor(_T_880, _T_867) @[lib.scala 119:74] + node _T_882 = xor(_T_881, _T_868) @[lib.scala 119:74] + node _T_883 = xor(_T_882, _T_869) @[lib.scala 119:74] + node _T_884 = xor(_T_883, _T_870) @[lib.scala 119:74] + node _T_885 = xor(_T_884, _T_871) @[lib.scala 119:74] + node _T_886 = xor(_T_885, _T_872) @[lib.scala 119:74] + node _T_887 = xor(_T_886, _T_873) @[lib.scala 119:74] + node _T_888 = xor(_T_887, _T_874) @[lib.scala 119:74] + node _T_889 = xor(_T_888, _T_875) @[lib.scala 119:74] + node _T_890 = bits(dccm_wdata_lo_any, 11, 11) @[lib.scala 119:58] + node _T_891 = bits(dccm_wdata_lo_any, 12, 12) @[lib.scala 119:58] + node _T_892 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_893 = bits(dccm_wdata_lo_any, 14, 14) @[lib.scala 119:58] + node _T_894 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_895 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_896 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_897 = bits(dccm_wdata_lo_any, 18, 18) @[lib.scala 119:58] + node _T_898 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_899 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_900 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_901 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_902 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_903 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_904 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_905 = xor(_T_890, _T_891) @[lib.scala 119:74] + node _T_906 = xor(_T_905, _T_892) @[lib.scala 119:74] + node _T_907 = xor(_T_906, _T_893) @[lib.scala 119:74] + node _T_908 = xor(_T_907, _T_894) @[lib.scala 119:74] + node _T_909 = xor(_T_908, _T_895) @[lib.scala 119:74] + node _T_910 = xor(_T_909, _T_896) @[lib.scala 119:74] + node _T_911 = xor(_T_910, _T_897) @[lib.scala 119:74] + node _T_912 = xor(_T_911, _T_898) @[lib.scala 119:74] + node _T_913 = xor(_T_912, _T_899) @[lib.scala 119:74] + node _T_914 = xor(_T_913, _T_900) @[lib.scala 119:74] + node _T_915 = xor(_T_914, _T_901) @[lib.scala 119:74] + node _T_916 = xor(_T_915, _T_902) @[lib.scala 119:74] + node _T_917 = xor(_T_916, _T_903) @[lib.scala 119:74] + node _T_918 = xor(_T_917, _T_904) @[lib.scala 119:74] + node _T_919 = bits(dccm_wdata_lo_any, 26, 26) @[lib.scala 119:58] + node _T_920 = bits(dccm_wdata_lo_any, 27, 27) @[lib.scala 119:58] + node _T_921 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_922 = bits(dccm_wdata_lo_any, 29, 29) @[lib.scala 119:58] + node _T_923 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_924 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_925 = xor(_T_919, _T_920) @[lib.scala 119:74] + node _T_926 = xor(_T_925, _T_921) @[lib.scala 119:74] + node _T_927 = xor(_T_926, _T_922) @[lib.scala 119:74] + node _T_928 = xor(_T_927, _T_923) @[lib.scala 119:74] + node _T_929 = xor(_T_928, _T_924) @[lib.scala 119:74] + node _T_930 = cat(_T_860, _T_825) @[Cat.scala 29:58] + node _T_931 = cat(_T_930, _T_790) @[Cat.scala 29:58] + node _T_932 = cat(_T_929, _T_918) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, _T_889) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] + node _T_935 = xorr(dccm_wdata_lo_any) @[lib.scala 127:13] + node _T_936 = xorr(_T_934) @[lib.scala 127:23] + node _T_937 = xor(_T_935, _T_936) @[lib.scala 127:18] + node dccm_wdata_ecc_lo_any = cat(_T_937, _T_934) @[Cat.scala 29:58] + node _T_938 = bits(dccm_wdata_hi_any, 0, 0) @[lib.scala 119:58] + node _T_939 = bits(dccm_wdata_hi_any, 1, 1) @[lib.scala 119:58] + node _T_940 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_941 = bits(dccm_wdata_hi_any, 4, 4) @[lib.scala 119:58] + node _T_942 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_943 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_944 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_945 = bits(dccm_wdata_hi_any, 11, 11) @[lib.scala 119:58] + node _T_946 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_947 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_948 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_949 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_950 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_951 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_952 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_953 = bits(dccm_wdata_hi_any, 26, 26) @[lib.scala 119:58] + node _T_954 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_955 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_956 = xor(_T_938, _T_939) @[lib.scala 119:74] + node _T_957 = xor(_T_956, _T_940) @[lib.scala 119:74] + node _T_958 = xor(_T_957, _T_941) @[lib.scala 119:74] + node _T_959 = xor(_T_958, _T_942) @[lib.scala 119:74] + node _T_960 = xor(_T_959, _T_943) @[lib.scala 119:74] + node _T_961 = xor(_T_960, _T_944) @[lib.scala 119:74] + node _T_962 = xor(_T_961, _T_945) @[lib.scala 119:74] + node _T_963 = xor(_T_962, _T_946) @[lib.scala 119:74] + node _T_964 = xor(_T_963, _T_947) @[lib.scala 119:74] + node _T_965 = xor(_T_964, _T_948) @[lib.scala 119:74] + node _T_966 = xor(_T_965, _T_949) @[lib.scala 119:74] + node _T_967 = xor(_T_966, _T_950) @[lib.scala 119:74] + node _T_968 = xor(_T_967, _T_951) @[lib.scala 119:74] + node _T_969 = xor(_T_968, _T_952) @[lib.scala 119:74] + node _T_970 = xor(_T_969, _T_953) @[lib.scala 119:74] + node _T_971 = xor(_T_970, _T_954) @[lib.scala 119:74] + node _T_972 = xor(_T_971, _T_955) @[lib.scala 119:74] + node _T_973 = bits(dccm_wdata_hi_any, 0, 0) @[lib.scala 119:58] + node _T_974 = bits(dccm_wdata_hi_any, 2, 2) @[lib.scala 119:58] + node _T_975 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_976 = bits(dccm_wdata_hi_any, 5, 5) @[lib.scala 119:58] + node _T_977 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_978 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_979 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_980 = bits(dccm_wdata_hi_any, 12, 12) @[lib.scala 119:58] + node _T_981 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_982 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_983 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_984 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_985 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_986 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_987 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_988 = bits(dccm_wdata_hi_any, 27, 27) @[lib.scala 119:58] + node _T_989 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_990 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_991 = xor(_T_973, _T_974) @[lib.scala 119:74] + node _T_992 = xor(_T_991, _T_975) @[lib.scala 119:74] + node _T_993 = xor(_T_992, _T_976) @[lib.scala 119:74] + node _T_994 = xor(_T_993, _T_977) @[lib.scala 119:74] + node _T_995 = xor(_T_994, _T_978) @[lib.scala 119:74] + node _T_996 = xor(_T_995, _T_979) @[lib.scala 119:74] + node _T_997 = xor(_T_996, _T_980) @[lib.scala 119:74] + node _T_998 = xor(_T_997, _T_981) @[lib.scala 119:74] + node _T_999 = xor(_T_998, _T_982) @[lib.scala 119:74] + node _T_1000 = xor(_T_999, _T_983) @[lib.scala 119:74] + node _T_1001 = xor(_T_1000, _T_984) @[lib.scala 119:74] + node _T_1002 = xor(_T_1001, _T_985) @[lib.scala 119:74] + node _T_1003 = xor(_T_1002, _T_986) @[lib.scala 119:74] + node _T_1004 = xor(_T_1003, _T_987) @[lib.scala 119:74] + node _T_1005 = xor(_T_1004, _T_988) @[lib.scala 119:74] + node _T_1006 = xor(_T_1005, _T_989) @[lib.scala 119:74] + node _T_1007 = xor(_T_1006, _T_990) @[lib.scala 119:74] + node _T_1008 = bits(dccm_wdata_hi_any, 1, 1) @[lib.scala 119:58] + node _T_1009 = bits(dccm_wdata_hi_any, 2, 2) @[lib.scala 119:58] + node _T_1010 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_1011 = bits(dccm_wdata_hi_any, 7, 7) @[lib.scala 119:58] + node _T_1012 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_1013 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_1014 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_1015 = bits(dccm_wdata_hi_any, 14, 14) @[lib.scala 119:58] + node _T_1016 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_1017 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_1018 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_1019 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1020 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1021 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1022 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1023 = bits(dccm_wdata_hi_any, 29, 29) @[lib.scala 119:58] + node _T_1024 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_1025 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_1026 = xor(_T_1008, _T_1009) @[lib.scala 119:74] + node _T_1027 = xor(_T_1026, _T_1010) @[lib.scala 119:74] + node _T_1028 = xor(_T_1027, _T_1011) @[lib.scala 119:74] + node _T_1029 = xor(_T_1028, _T_1012) @[lib.scala 119:74] + node _T_1030 = xor(_T_1029, _T_1013) @[lib.scala 119:74] + node _T_1031 = xor(_T_1030, _T_1014) @[lib.scala 119:74] + node _T_1032 = xor(_T_1031, _T_1015) @[lib.scala 119:74] + node _T_1033 = xor(_T_1032, _T_1016) @[lib.scala 119:74] + node _T_1034 = xor(_T_1033, _T_1017) @[lib.scala 119:74] + node _T_1035 = xor(_T_1034, _T_1018) @[lib.scala 119:74] + node _T_1036 = xor(_T_1035, _T_1019) @[lib.scala 119:74] + node _T_1037 = xor(_T_1036, _T_1020) @[lib.scala 119:74] + node _T_1038 = xor(_T_1037, _T_1021) @[lib.scala 119:74] + node _T_1039 = xor(_T_1038, _T_1022) @[lib.scala 119:74] + node _T_1040 = xor(_T_1039, _T_1023) @[lib.scala 119:74] + node _T_1041 = xor(_T_1040, _T_1024) @[lib.scala 119:74] + node _T_1042 = xor(_T_1041, _T_1025) @[lib.scala 119:74] + node _T_1043 = bits(dccm_wdata_hi_any, 4, 4) @[lib.scala 119:58] + node _T_1044 = bits(dccm_wdata_hi_any, 5, 5) @[lib.scala 119:58] + node _T_1045 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_1046 = bits(dccm_wdata_hi_any, 7, 7) @[lib.scala 119:58] + node _T_1047 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_1048 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_1049 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_1050 = bits(dccm_wdata_hi_any, 18, 18) @[lib.scala 119:58] + node _T_1051 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_1052 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_1053 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_1054 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1055 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1056 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1057 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1058 = xor(_T_1043, _T_1044) @[lib.scala 119:74] + node _T_1059 = xor(_T_1058, _T_1045) @[lib.scala 119:74] + node _T_1060 = xor(_T_1059, _T_1046) @[lib.scala 119:74] + node _T_1061 = xor(_T_1060, _T_1047) @[lib.scala 119:74] + node _T_1062 = xor(_T_1061, _T_1048) @[lib.scala 119:74] + node _T_1063 = xor(_T_1062, _T_1049) @[lib.scala 119:74] + node _T_1064 = xor(_T_1063, _T_1050) @[lib.scala 119:74] + node _T_1065 = xor(_T_1064, _T_1051) @[lib.scala 119:74] + node _T_1066 = xor(_T_1065, _T_1052) @[lib.scala 119:74] + node _T_1067 = xor(_T_1066, _T_1053) @[lib.scala 119:74] + node _T_1068 = xor(_T_1067, _T_1054) @[lib.scala 119:74] + node _T_1069 = xor(_T_1068, _T_1055) @[lib.scala 119:74] + node _T_1070 = xor(_T_1069, _T_1056) @[lib.scala 119:74] + node _T_1071 = xor(_T_1070, _T_1057) @[lib.scala 119:74] + node _T_1072 = bits(dccm_wdata_hi_any, 11, 11) @[lib.scala 119:58] + node _T_1073 = bits(dccm_wdata_hi_any, 12, 12) @[lib.scala 119:58] + node _T_1074 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_1075 = bits(dccm_wdata_hi_any, 14, 14) @[lib.scala 119:58] + node _T_1076 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_1077 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_1078 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_1079 = bits(dccm_wdata_hi_any, 18, 18) @[lib.scala 119:58] + node _T_1080 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_1081 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_1082 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_1083 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1084 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1085 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1086 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1087 = xor(_T_1072, _T_1073) @[lib.scala 119:74] + node _T_1088 = xor(_T_1087, _T_1074) @[lib.scala 119:74] + node _T_1089 = xor(_T_1088, _T_1075) @[lib.scala 119:74] + node _T_1090 = xor(_T_1089, _T_1076) @[lib.scala 119:74] + node _T_1091 = xor(_T_1090, _T_1077) @[lib.scala 119:74] + node _T_1092 = xor(_T_1091, _T_1078) @[lib.scala 119:74] + node _T_1093 = xor(_T_1092, _T_1079) @[lib.scala 119:74] + node _T_1094 = xor(_T_1093, _T_1080) @[lib.scala 119:74] + node _T_1095 = xor(_T_1094, _T_1081) @[lib.scala 119:74] + node _T_1096 = xor(_T_1095, _T_1082) @[lib.scala 119:74] + node _T_1097 = xor(_T_1096, _T_1083) @[lib.scala 119:74] + node _T_1098 = xor(_T_1097, _T_1084) @[lib.scala 119:74] + node _T_1099 = xor(_T_1098, _T_1085) @[lib.scala 119:74] + node _T_1100 = xor(_T_1099, _T_1086) @[lib.scala 119:74] + node _T_1101 = bits(dccm_wdata_hi_any, 26, 26) @[lib.scala 119:58] + node _T_1102 = bits(dccm_wdata_hi_any, 27, 27) @[lib.scala 119:58] + node _T_1103 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_1104 = bits(dccm_wdata_hi_any, 29, 29) @[lib.scala 119:58] + node _T_1105 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_1106 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_1107 = xor(_T_1101, _T_1102) @[lib.scala 119:74] + node _T_1108 = xor(_T_1107, _T_1103) @[lib.scala 119:74] + node _T_1109 = xor(_T_1108, _T_1104) @[lib.scala 119:74] + node _T_1110 = xor(_T_1109, _T_1105) @[lib.scala 119:74] + node _T_1111 = xor(_T_1110, _T_1106) @[lib.scala 119:74] + node _T_1112 = cat(_T_1042, _T_1007) @[Cat.scala 29:58] + node _T_1113 = cat(_T_1112, _T_972) @[Cat.scala 29:58] + node _T_1114 = cat(_T_1111, _T_1100) @[Cat.scala 29:58] + node _T_1115 = cat(_T_1114, _T_1071) @[Cat.scala 29:58] + node _T_1116 = cat(_T_1115, _T_1113) @[Cat.scala 29:58] + node _T_1117 = xorr(dccm_wdata_hi_any) @[lib.scala 127:13] + node _T_1118 = xorr(_T_1116) @[lib.scala 127:23] + node _T_1119 = xor(_T_1117, _T_1118) @[lib.scala 127:18] + node dccm_wdata_ecc_hi_any = cat(_T_1119, _T_1116) @[Cat.scala 29:58] + when UInt<1>("h00") : @[lsu_ecc.scala 102:30] + node _T_1120 = bits(io.lsu_addr_r, 2, 2) @[lsu_ecc.scala 103:33] + node _T_1121 = bits(io.end_addr_r, 2, 2) @[lsu_ecc.scala 103:54] + node _T_1122 = neq(_T_1120, _T_1121) @[lsu_ecc.scala 103:37] + ldst_dual_r <= _T_1122 @[lsu_ecc.scala 103:17] + node _T_1123 = or(io.lsu_pkt_r.bits.load, io.lsu_pkt_r.bits.store) @[lsu_ecc.scala 104:63] + node _T_1124 = and(io.lsu_pkt_r.valid, _T_1123) @[lsu_ecc.scala 104:37] + node _T_1125 = and(_T_1124, io.addr_in_dccm_r) @[lsu_ecc.scala 104:90] + node _T_1126 = and(_T_1125, io.lsu_dccm_rden_r) @[lsu_ecc.scala 104:110] + is_ldst_r <= _T_1126 @[lsu_ecc.scala 104:15] + node _T_1127 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 105:33] + node _T_1128 = and(is_ldst_r, _T_1127) @[lsu_ecc.scala 105:31] + is_ldst_lo_r <= _T_1128 @[lsu_ecc.scala 105:18] + node _T_1129 = and(is_ldst_r, ldst_dual_r) @[lsu_ecc.scala 106:31] + node _T_1130 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 106:48] + node _T_1131 = and(_T_1129, _T_1130) @[lsu_ecc.scala 106:46] + is_ldst_hi_r <= _T_1131 @[lsu_ecc.scala 106:18] + is_ldst_hi_any <= is_ldst_hi_r @[lsu_ecc.scala 107:21] + dccm_rdata_hi_any <= io.dccm_rdata_hi_r @[lsu_ecc.scala 108:24] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_r @[lsu_ecc.scala 109:26] + is_ldst_lo_any <= is_ldst_lo_r @[lsu_ecc.scala 110:20] + dccm_rdata_lo_any <= io.dccm_rdata_lo_r @[lsu_ecc.scala 111:25] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_r @[lsu_ecc.scala 112:26] + io.sec_data_hi_r <= sec_data_hi_any @[lsu_ecc.scala 113:22] + io.single_ecc_error_hi_r <= single_ecc_error_hi_any @[lsu_ecc.scala 114:31] + double_ecc_error_hi_r <= double_ecc_error_hi_any @[lsu_ecc.scala 115:28] + io.sec_data_lo_r <= sec_data_lo_any @[lsu_ecc.scala 116:25] + io.single_ecc_error_lo_r <= single_ecc_error_lo_any @[lsu_ecc.scala 117:31] + double_ecc_error_lo_r <= double_ecc_error_lo_any @[lsu_ecc.scala 118:28] + node _T_1132 = or(io.single_ecc_error_hi_r, io.single_ecc_error_lo_r) @[lsu_ecc.scala 119:59] + io.lsu_single_ecc_error_r <= _T_1132 @[lsu_ecc.scala 119:31] + node _T_1133 = or(double_ecc_error_hi_r, double_ecc_error_lo_r) @[lsu_ecc.scala 120:56] + io.lsu_double_ecc_error_r <= _T_1133 @[lsu_ecc.scala 120:31] + skip @[lsu_ecc.scala 102:30] + else : @[lsu_ecc.scala 122:16] + node _T_1134 = bits(io.lsu_addr_m, 2, 2) @[lsu_ecc.scala 123:35] + node _T_1135 = bits(io.end_addr_m, 2, 2) @[lsu_ecc.scala 123:56] + node _T_1136 = neq(_T_1134, _T_1135) @[lsu_ecc.scala 123:39] + ldst_dual_m <= _T_1136 @[lsu_ecc.scala 123:19] + node _T_1137 = or(io.lsu_pkt_m.bits.load, io.lsu_pkt_m.bits.store) @[lsu_ecc.scala 124:65] + node _T_1138 = and(io.lsu_pkt_m.valid, _T_1137) @[lsu_ecc.scala 124:39] + node _T_1139 = and(_T_1138, io.addr_in_dccm_m) @[lsu_ecc.scala 124:92] + node _T_1140 = and(_T_1139, io.lsu_dccm_rden_m) @[lsu_ecc.scala 124:112] + is_ldst_m <= _T_1140 @[lsu_ecc.scala 124:17] + node _T_1141 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 125:35] + node _T_1142 = and(is_ldst_m, _T_1141) @[lsu_ecc.scala 125:33] + is_ldst_lo_m <= _T_1142 @[lsu_ecc.scala 125:20] + node _T_1143 = or(ldst_dual_m, io.lsu_pkt_m.bits.dma) @[lsu_ecc.scala 126:48] + node _T_1144 = and(is_ldst_m, _T_1143) @[lsu_ecc.scala 126:33] + node _T_1145 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 126:75] + node _T_1146 = and(_T_1144, _T_1145) @[lsu_ecc.scala 126:73] + is_ldst_hi_m <= _T_1146 @[lsu_ecc.scala 126:20] + is_ldst_hi_any <= is_ldst_hi_m @[lsu_ecc.scala 127:23] + dccm_rdata_hi_any <= io.dccm_rdata_hi_m @[lsu_ecc.scala 128:26] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_m @[lsu_ecc.scala 129:28] + is_ldst_lo_any <= is_ldst_lo_m @[lsu_ecc.scala 130:22] + dccm_rdata_lo_any <= io.dccm_rdata_lo_m @[lsu_ecc.scala 131:27] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_m @[lsu_ecc.scala 132:28] + io.sec_data_hi_m <= sec_data_hi_any @[lsu_ecc.scala 133:27] + double_ecc_error_hi_m <= double_ecc_error_hi_any @[lsu_ecc.scala 134:30] + io.sec_data_lo_m <= sec_data_lo_any @[lsu_ecc.scala 135:27] + double_ecc_error_lo_m <= double_ecc_error_lo_any @[lsu_ecc.scala 136:30] + node _T_1147 = or(single_ecc_error_hi_any, single_ecc_error_lo_any) @[lsu_ecc.scala 137:60] + io.lsu_single_ecc_error_m <= _T_1147 @[lsu_ecc.scala 137:33] + node _T_1148 = or(double_ecc_error_hi_m, double_ecc_error_lo_m) @[lsu_ecc.scala 138:58] + io.lsu_double_ecc_error_m <= _T_1148 @[lsu_ecc.scala 138:33] + reg _T_1149 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 140:72] + _T_1149 <= io.lsu_single_ecc_error_m @[lsu_ecc.scala 140:72] + io.lsu_single_ecc_error_r <= _T_1149 @[lsu_ecc.scala 140:62] + reg _T_1150 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 141:72] + _T_1150 <= io.lsu_double_ecc_error_m @[lsu_ecc.scala 141:72] + io.lsu_double_ecc_error_r <= _T_1150 @[lsu_ecc.scala 141:62] + reg _T_1151 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 142:72] + _T_1151 <= single_ecc_error_lo_any @[lsu_ecc.scala 142:72] + io.single_ecc_error_lo_r <= _T_1151 @[lsu_ecc.scala 142:62] + reg _T_1152 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 143:72] + _T_1152 <= single_ecc_error_hi_any @[lsu_ecc.scala 143:72] + io.single_ecc_error_hi_r <= _T_1152 @[lsu_ecc.scala 143:62] + node _T_1153 = or(io.lsu_single_ecc_error_m, io.clk_override) @[lsu_ecc.scala 144:87] + inst rvclkhdr of rvclkhdr_16 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_1153 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1154 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1153 : @[Reg.scala 28:19] + _T_1154 <= io.sec_data_hi_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.sec_data_hi_r <= _T_1154 @[lsu_ecc.scala 144:34] + node _T_1155 = or(io.lsu_single_ecc_error_m, io.clk_override) @[lsu_ecc.scala 145:87] + inst rvclkhdr_1 of rvclkhdr_17 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_1155 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1156 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1155 : @[Reg.scala 28:19] + _T_1156 <= io.sec_data_lo_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.sec_data_lo_r <= _T_1156 @[lsu_ecc.scala 145:34] + skip @[lsu_ecc.scala 122:16] + node _T_1157 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 148:56] + node _T_1158 = bits(io.dma_dccm_wen, 0, 0) @[lsu_ecc.scala 148:104] + node _T_1159 = mux(_T_1158, io.dma_dccm_wdata_lo, io.stbuf_data_any) @[lsu_ecc.scala 148:87] + node _T_1160 = mux(_T_1157, io.sec_data_lo_r_ff, _T_1159) @[lsu_ecc.scala 148:27] + dccm_wdata_lo_any <= _T_1160 @[lsu_ecc.scala 148:21] + node _T_1161 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 149:56] + node _T_1162 = bits(io.dma_dccm_wen, 0, 0) @[lsu_ecc.scala 149:104] + node _T_1163 = mux(_T_1162, io.dma_dccm_wdata_hi, UInt<1>("h00")) @[lsu_ecc.scala 149:87] + node _T_1164 = mux(_T_1161, io.sec_data_hi_r_ff, _T_1163) @[lsu_ecc.scala 149:27] + dccm_wdata_hi_any <= _T_1164 @[lsu_ecc.scala 149:21] + io.sec_data_ecc_hi_r_ff <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 150:28] + io.sec_data_ecc_lo_r_ff <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 151:28] + io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 152:28] + io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 153:28] + io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 154:28] + node _T_1165 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_ecc.scala 156:75] + inst rvclkhdr_2 of rvclkhdr_18 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_1165 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1165 : @[Reg.scala 28:19] + _T_1166 <= io.sec_data_hi_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.sec_data_hi_r_ff <= _T_1166 @[lsu_ecc.scala 156:23] + node _T_1167 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_ecc.scala 157:75] + inst rvclkhdr_3 of rvclkhdr_19 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_1167 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1167 : @[Reg.scala 28:19] + _T_1168 <= io.sec_data_lo_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.sec_data_lo_r_ff <= _T_1168 @[lsu_ecc.scala 157:23] + + module lsu_trigger : + input clock : Clock + input reset : AsyncReset + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} + + wire trigger_enable : UInt<1> + trigger_enable <= UInt<1>("h00") + node _T = or(io.trigger_pkt_any[0].m, io.trigger_pkt_any[1].m) @[lsu_trigger.scala 16:73] + node _T_1 = or(_T, io.trigger_pkt_any[2].m) @[lsu_trigger.scala 16:73] + node _T_2 = or(_T_1, io.trigger_pkt_any[3].m) @[lsu_trigger.scala 16:73] + trigger_enable <= _T_2 @[lsu_trigger.scala 16:18] + node _T_3 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_5 = bits(io.store_data_m, 31, 16) @[lsu_trigger.scala 17:83] + node _T_6 = and(_T_4, _T_5) @[lsu_trigger.scala 17:66] + node _T_7 = or(io.lsu_pkt_m.bits.half, io.lsu_pkt_m.bits.word) @[lsu_trigger.scala 17:124] + node _T_8 = bits(_T_7, 0, 0) @[Bitwise.scala 72:15] + node _T_9 = mux(_T_8, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_10 = bits(io.store_data_m, 15, 8) @[lsu_trigger.scala 17:168] + node _T_11 = and(_T_9, _T_10) @[lsu_trigger.scala 17:151] + node _T_12 = bits(io.store_data_m, 7, 0) @[lsu_trigger.scala 17:192] + node _T_13 = cat(_T_6, _T_11) @[Cat.scala 29:58] + node store_data_trigger_m = cat(_T_13, _T_12) @[Cat.scala 29:58] + node _T_14 = bits(trigger_enable, 0, 0) @[Bitwise.scala 72:15] + node _T_15 = mux(_T_14, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node ldst_addr_trigger_m = and(io.lsu_addr_m, _T_15) @[lsu_trigger.scala 18:43] + node _T_16 = bits(io.trigger_pkt_any[0].select, 0, 0) @[lsu_trigger.scala 19:83] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[lsu_trigger.scala 19:53] + node _T_18 = and(io.trigger_pkt_any[0].select, io.trigger_pkt_any[0].store) @[lsu_trigger.scala 19:143] + node _T_19 = bits(_T_18, 0, 0) @[lsu_trigger.scala 19:174] + node _T_20 = mux(_T_17, ldst_addr_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = mux(_T_19, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72] + wire lsu_match_data_0 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_0 <= _T_22 @[Mux.scala 27:72] + node _T_23 = bits(io.trigger_pkt_any[1].select, 0, 0) @[lsu_trigger.scala 19:83] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[lsu_trigger.scala 19:53] + node _T_25 = and(io.trigger_pkt_any[1].select, io.trigger_pkt_any[1].store) @[lsu_trigger.scala 19:143] + node _T_26 = bits(_T_25, 0, 0) @[lsu_trigger.scala 19:174] + node _T_27 = mux(_T_24, ldst_addr_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_28 = mux(_T_26, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_29 = or(_T_27, _T_28) @[Mux.scala 27:72] + wire lsu_match_data_1 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_1 <= _T_29 @[Mux.scala 27:72] + node _T_30 = bits(io.trigger_pkt_any[2].select, 0, 0) @[lsu_trigger.scala 19:83] + node _T_31 = eq(_T_30, UInt<1>("h00")) @[lsu_trigger.scala 19:53] + node _T_32 = and(io.trigger_pkt_any[2].select, io.trigger_pkt_any[2].store) @[lsu_trigger.scala 19:143] + node _T_33 = bits(_T_32, 0, 0) @[lsu_trigger.scala 19:174] + node _T_34 = mux(_T_31, ldst_addr_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_35 = mux(_T_33, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_36 = or(_T_34, _T_35) @[Mux.scala 27:72] + wire lsu_match_data_2 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_2 <= _T_36 @[Mux.scala 27:72] + node _T_37 = bits(io.trigger_pkt_any[3].select, 0, 0) @[lsu_trigger.scala 19:83] + node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_trigger.scala 19:53] + node _T_39 = and(io.trigger_pkt_any[3].select, io.trigger_pkt_any[3].store) @[lsu_trigger.scala 19:143] + node _T_40 = bits(_T_39, 0, 0) @[lsu_trigger.scala 19:174] + node _T_41 = mux(_T_38, ldst_addr_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_42 = mux(_T_40, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_43 = or(_T_41, _T_42) @[Mux.scala 27:72] + wire lsu_match_data_3 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_3 <= _T_43 @[Mux.scala 27:72] + node _T_44 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 20:70] + node _T_45 = and(io.lsu_pkt_m.valid, _T_44) @[lsu_trigger.scala 20:68] + node _T_46 = and(_T_45, trigger_enable) @[lsu_trigger.scala 20:93] + node _T_47 = and(io.trigger_pkt_any[0].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 20:142] + node _T_48 = and(io.trigger_pkt_any[0].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 21:33] + node _T_49 = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[lsu_trigger.scala 21:60] + node _T_50 = and(_T_48, _T_49) @[lsu_trigger.scala 21:58] + node _T_51 = or(_T_47, _T_50) @[lsu_trigger.scala 20:168] + node _T_52 = and(_T_46, _T_51) @[lsu_trigger.scala 20:110] + node _T_53 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[lsu_trigger.scala 22:107] + wire _T_54 : UInt<1>[32] @[lib.scala 100:24] + node _T_55 = andr(io.trigger_pkt_any[0].tdata2) @[lib.scala 101:45] + node _T_56 = not(_T_55) @[lib.scala 101:39] + node _T_57 = and(_T_53, _T_56) @[lib.scala 101:37] + node _T_58 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 102:48] + node _T_59 = bits(lsu_match_data_0, 0, 0) @[lib.scala 102:60] + node _T_60 = eq(_T_58, _T_59) @[lib.scala 102:52] + node _T_61 = or(_T_57, _T_60) @[lib.scala 102:41] + _T_54[0] <= _T_61 @[lib.scala 102:18] + node _T_62 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 104:28] + node _T_63 = andr(_T_62) @[lib.scala 104:36] + node _T_64 = and(_T_63, _T_57) @[lib.scala 104:41] + node _T_65 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[lib.scala 104:74] + node _T_66 = bits(lsu_match_data_0, 1, 1) @[lib.scala 104:86] + node _T_67 = eq(_T_65, _T_66) @[lib.scala 104:78] + node _T_68 = mux(_T_64, UInt<1>("h01"), _T_67) @[lib.scala 104:23] + _T_54[1] <= _T_68 @[lib.scala 104:17] + node _T_69 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[lib.scala 104:28] + node _T_70 = andr(_T_69) @[lib.scala 104:36] + node _T_71 = and(_T_70, _T_57) @[lib.scala 104:41] + node _T_72 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[lib.scala 104:74] + node _T_73 = bits(lsu_match_data_0, 2, 2) @[lib.scala 104:86] + node _T_74 = eq(_T_72, _T_73) @[lib.scala 104:78] + node _T_75 = mux(_T_71, UInt<1>("h01"), _T_74) @[lib.scala 104:23] + _T_54[2] <= _T_75 @[lib.scala 104:17] + node _T_76 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[lib.scala 104:28] + node _T_77 = andr(_T_76) @[lib.scala 104:36] + node _T_78 = and(_T_77, _T_57) @[lib.scala 104:41] + node _T_79 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[lib.scala 104:74] + node _T_80 = bits(lsu_match_data_0, 3, 3) @[lib.scala 104:86] + node _T_81 = eq(_T_79, _T_80) @[lib.scala 104:78] + node _T_82 = mux(_T_78, UInt<1>("h01"), _T_81) @[lib.scala 104:23] + _T_54[3] <= _T_82 @[lib.scala 104:17] + node _T_83 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[lib.scala 104:28] + node _T_84 = andr(_T_83) @[lib.scala 104:36] + node _T_85 = and(_T_84, _T_57) @[lib.scala 104:41] + node _T_86 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[lib.scala 104:74] + node _T_87 = bits(lsu_match_data_0, 4, 4) @[lib.scala 104:86] + node _T_88 = eq(_T_86, _T_87) @[lib.scala 104:78] + node _T_89 = mux(_T_85, UInt<1>("h01"), _T_88) @[lib.scala 104:23] + _T_54[4] <= _T_89 @[lib.scala 104:17] + node _T_90 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[lib.scala 104:28] + node _T_91 = andr(_T_90) @[lib.scala 104:36] + node _T_92 = and(_T_91, _T_57) @[lib.scala 104:41] + node _T_93 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[lib.scala 104:74] + node _T_94 = bits(lsu_match_data_0, 5, 5) @[lib.scala 104:86] + node _T_95 = eq(_T_93, _T_94) @[lib.scala 104:78] + node _T_96 = mux(_T_92, UInt<1>("h01"), _T_95) @[lib.scala 104:23] + _T_54[5] <= _T_96 @[lib.scala 104:17] + node _T_97 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[lib.scala 104:28] + node _T_98 = andr(_T_97) @[lib.scala 104:36] + node _T_99 = and(_T_98, _T_57) @[lib.scala 104:41] + node _T_100 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[lib.scala 104:74] + node _T_101 = bits(lsu_match_data_0, 6, 6) @[lib.scala 104:86] + node _T_102 = eq(_T_100, _T_101) @[lib.scala 104:78] + node _T_103 = mux(_T_99, UInt<1>("h01"), _T_102) @[lib.scala 104:23] + _T_54[6] <= _T_103 @[lib.scala 104:17] + node _T_104 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[lib.scala 104:28] + node _T_105 = andr(_T_104) @[lib.scala 104:36] + node _T_106 = and(_T_105, _T_57) @[lib.scala 104:41] + node _T_107 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[lib.scala 104:74] + node _T_108 = bits(lsu_match_data_0, 7, 7) @[lib.scala 104:86] + node _T_109 = eq(_T_107, _T_108) @[lib.scala 104:78] + node _T_110 = mux(_T_106, UInt<1>("h01"), _T_109) @[lib.scala 104:23] + _T_54[7] <= _T_110 @[lib.scala 104:17] + node _T_111 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[lib.scala 104:28] + node _T_112 = andr(_T_111) @[lib.scala 104:36] + node _T_113 = and(_T_112, _T_57) @[lib.scala 104:41] + node _T_114 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[lib.scala 104:74] + node _T_115 = bits(lsu_match_data_0, 8, 8) @[lib.scala 104:86] + node _T_116 = eq(_T_114, _T_115) @[lib.scala 104:78] + node _T_117 = mux(_T_113, UInt<1>("h01"), _T_116) @[lib.scala 104:23] + _T_54[8] <= _T_117 @[lib.scala 104:17] + node _T_118 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[lib.scala 104:28] + node _T_119 = andr(_T_118) @[lib.scala 104:36] + node _T_120 = and(_T_119, _T_57) @[lib.scala 104:41] + node _T_121 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[lib.scala 104:74] + node _T_122 = bits(lsu_match_data_0, 9, 9) @[lib.scala 104:86] + node _T_123 = eq(_T_121, _T_122) @[lib.scala 104:78] + node _T_124 = mux(_T_120, UInt<1>("h01"), _T_123) @[lib.scala 104:23] + _T_54[9] <= _T_124 @[lib.scala 104:17] + node _T_125 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[lib.scala 104:28] + node _T_126 = andr(_T_125) @[lib.scala 104:36] + node _T_127 = and(_T_126, _T_57) @[lib.scala 104:41] + node _T_128 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[lib.scala 104:74] + node _T_129 = bits(lsu_match_data_0, 10, 10) @[lib.scala 104:86] + node _T_130 = eq(_T_128, _T_129) @[lib.scala 104:78] + node _T_131 = mux(_T_127, UInt<1>("h01"), _T_130) @[lib.scala 104:23] + _T_54[10] <= _T_131 @[lib.scala 104:17] + node _T_132 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[lib.scala 104:28] + node _T_133 = andr(_T_132) @[lib.scala 104:36] + node _T_134 = and(_T_133, _T_57) @[lib.scala 104:41] + node _T_135 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[lib.scala 104:74] + node _T_136 = bits(lsu_match_data_0, 11, 11) @[lib.scala 104:86] + node _T_137 = eq(_T_135, _T_136) @[lib.scala 104:78] + node _T_138 = mux(_T_134, UInt<1>("h01"), _T_137) @[lib.scala 104:23] + _T_54[11] <= _T_138 @[lib.scala 104:17] + node _T_139 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[lib.scala 104:28] + node _T_140 = andr(_T_139) @[lib.scala 104:36] + node _T_141 = and(_T_140, _T_57) @[lib.scala 104:41] + node _T_142 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[lib.scala 104:74] + node _T_143 = bits(lsu_match_data_0, 12, 12) @[lib.scala 104:86] + node _T_144 = eq(_T_142, _T_143) @[lib.scala 104:78] + node _T_145 = mux(_T_141, UInt<1>("h01"), _T_144) @[lib.scala 104:23] + _T_54[12] <= _T_145 @[lib.scala 104:17] + node _T_146 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[lib.scala 104:28] + node _T_147 = andr(_T_146) @[lib.scala 104:36] + node _T_148 = and(_T_147, _T_57) @[lib.scala 104:41] + node _T_149 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[lib.scala 104:74] + node _T_150 = bits(lsu_match_data_0, 13, 13) @[lib.scala 104:86] + node _T_151 = eq(_T_149, _T_150) @[lib.scala 104:78] + node _T_152 = mux(_T_148, UInt<1>("h01"), _T_151) @[lib.scala 104:23] + _T_54[13] <= _T_152 @[lib.scala 104:17] + node _T_153 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[lib.scala 104:28] + node _T_154 = andr(_T_153) @[lib.scala 104:36] + node _T_155 = and(_T_154, _T_57) @[lib.scala 104:41] + node _T_156 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[lib.scala 104:74] + node _T_157 = bits(lsu_match_data_0, 14, 14) @[lib.scala 104:86] + node _T_158 = eq(_T_156, _T_157) @[lib.scala 104:78] + node _T_159 = mux(_T_155, UInt<1>("h01"), _T_158) @[lib.scala 104:23] + _T_54[14] <= _T_159 @[lib.scala 104:17] + node _T_160 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[lib.scala 104:28] + node _T_161 = andr(_T_160) @[lib.scala 104:36] + node _T_162 = and(_T_161, _T_57) @[lib.scala 104:41] + node _T_163 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[lib.scala 104:74] + node _T_164 = bits(lsu_match_data_0, 15, 15) @[lib.scala 104:86] + node _T_165 = eq(_T_163, _T_164) @[lib.scala 104:78] + node _T_166 = mux(_T_162, UInt<1>("h01"), _T_165) @[lib.scala 104:23] + _T_54[15] <= _T_166 @[lib.scala 104:17] + node _T_167 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[lib.scala 104:28] + node _T_168 = andr(_T_167) @[lib.scala 104:36] + node _T_169 = and(_T_168, _T_57) @[lib.scala 104:41] + node _T_170 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[lib.scala 104:74] + node _T_171 = bits(lsu_match_data_0, 16, 16) @[lib.scala 104:86] + node _T_172 = eq(_T_170, _T_171) @[lib.scala 104:78] + node _T_173 = mux(_T_169, UInt<1>("h01"), _T_172) @[lib.scala 104:23] + _T_54[16] <= _T_173 @[lib.scala 104:17] + node _T_174 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[lib.scala 104:28] + node _T_175 = andr(_T_174) @[lib.scala 104:36] + node _T_176 = and(_T_175, _T_57) @[lib.scala 104:41] + node _T_177 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[lib.scala 104:74] + node _T_178 = bits(lsu_match_data_0, 17, 17) @[lib.scala 104:86] + node _T_179 = eq(_T_177, _T_178) @[lib.scala 104:78] + node _T_180 = mux(_T_176, UInt<1>("h01"), _T_179) @[lib.scala 104:23] + _T_54[17] <= _T_180 @[lib.scala 104:17] + node _T_181 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[lib.scala 104:28] + node _T_182 = andr(_T_181) @[lib.scala 104:36] + node _T_183 = and(_T_182, _T_57) @[lib.scala 104:41] + node _T_184 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[lib.scala 104:74] + node _T_185 = bits(lsu_match_data_0, 18, 18) @[lib.scala 104:86] + node _T_186 = eq(_T_184, _T_185) @[lib.scala 104:78] + node _T_187 = mux(_T_183, UInt<1>("h01"), _T_186) @[lib.scala 104:23] + _T_54[18] <= _T_187 @[lib.scala 104:17] + node _T_188 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[lib.scala 104:28] + node _T_189 = andr(_T_188) @[lib.scala 104:36] + node _T_190 = and(_T_189, _T_57) @[lib.scala 104:41] + node _T_191 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[lib.scala 104:74] + node _T_192 = bits(lsu_match_data_0, 19, 19) @[lib.scala 104:86] + node _T_193 = eq(_T_191, _T_192) @[lib.scala 104:78] + node _T_194 = mux(_T_190, UInt<1>("h01"), _T_193) @[lib.scala 104:23] + _T_54[19] <= _T_194 @[lib.scala 104:17] + node _T_195 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[lib.scala 104:28] + node _T_196 = andr(_T_195) @[lib.scala 104:36] + node _T_197 = and(_T_196, _T_57) @[lib.scala 104:41] + node _T_198 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[lib.scala 104:74] + node _T_199 = bits(lsu_match_data_0, 20, 20) @[lib.scala 104:86] + node _T_200 = eq(_T_198, _T_199) @[lib.scala 104:78] + node _T_201 = mux(_T_197, UInt<1>("h01"), _T_200) @[lib.scala 104:23] + _T_54[20] <= _T_201 @[lib.scala 104:17] + node _T_202 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[lib.scala 104:28] + node _T_203 = andr(_T_202) @[lib.scala 104:36] + node _T_204 = and(_T_203, _T_57) @[lib.scala 104:41] + node _T_205 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[lib.scala 104:74] + node _T_206 = bits(lsu_match_data_0, 21, 21) @[lib.scala 104:86] + node _T_207 = eq(_T_205, _T_206) @[lib.scala 104:78] + node _T_208 = mux(_T_204, UInt<1>("h01"), _T_207) @[lib.scala 104:23] + _T_54[21] <= _T_208 @[lib.scala 104:17] + node _T_209 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[lib.scala 104:28] + node _T_210 = andr(_T_209) @[lib.scala 104:36] + node _T_211 = and(_T_210, _T_57) @[lib.scala 104:41] + node _T_212 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[lib.scala 104:74] + node _T_213 = bits(lsu_match_data_0, 22, 22) @[lib.scala 104:86] + node _T_214 = eq(_T_212, _T_213) @[lib.scala 104:78] + node _T_215 = mux(_T_211, UInt<1>("h01"), _T_214) @[lib.scala 104:23] + _T_54[22] <= _T_215 @[lib.scala 104:17] + node _T_216 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[lib.scala 104:28] + node _T_217 = andr(_T_216) @[lib.scala 104:36] + node _T_218 = and(_T_217, _T_57) @[lib.scala 104:41] + node _T_219 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[lib.scala 104:74] + node _T_220 = bits(lsu_match_data_0, 23, 23) @[lib.scala 104:86] + node _T_221 = eq(_T_219, _T_220) @[lib.scala 104:78] + node _T_222 = mux(_T_218, UInt<1>("h01"), _T_221) @[lib.scala 104:23] + _T_54[23] <= _T_222 @[lib.scala 104:17] + node _T_223 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[lib.scala 104:28] + node _T_224 = andr(_T_223) @[lib.scala 104:36] + node _T_225 = and(_T_224, _T_57) @[lib.scala 104:41] + node _T_226 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[lib.scala 104:74] + node _T_227 = bits(lsu_match_data_0, 24, 24) @[lib.scala 104:86] + node _T_228 = eq(_T_226, _T_227) @[lib.scala 104:78] + node _T_229 = mux(_T_225, UInt<1>("h01"), _T_228) @[lib.scala 104:23] + _T_54[24] <= _T_229 @[lib.scala 104:17] + node _T_230 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[lib.scala 104:28] + node _T_231 = andr(_T_230) @[lib.scala 104:36] + node _T_232 = and(_T_231, _T_57) @[lib.scala 104:41] + node _T_233 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[lib.scala 104:74] + node _T_234 = bits(lsu_match_data_0, 25, 25) @[lib.scala 104:86] + node _T_235 = eq(_T_233, _T_234) @[lib.scala 104:78] + node _T_236 = mux(_T_232, UInt<1>("h01"), _T_235) @[lib.scala 104:23] + _T_54[25] <= _T_236 @[lib.scala 104:17] + node _T_237 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[lib.scala 104:28] + node _T_238 = andr(_T_237) @[lib.scala 104:36] + node _T_239 = and(_T_238, _T_57) @[lib.scala 104:41] + node _T_240 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[lib.scala 104:74] + node _T_241 = bits(lsu_match_data_0, 26, 26) @[lib.scala 104:86] + node _T_242 = eq(_T_240, _T_241) @[lib.scala 104:78] + node _T_243 = mux(_T_239, UInt<1>("h01"), _T_242) @[lib.scala 104:23] + _T_54[26] <= _T_243 @[lib.scala 104:17] + node _T_244 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[lib.scala 104:28] + node _T_245 = andr(_T_244) @[lib.scala 104:36] + node _T_246 = and(_T_245, _T_57) @[lib.scala 104:41] + node _T_247 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[lib.scala 104:74] + node _T_248 = bits(lsu_match_data_0, 27, 27) @[lib.scala 104:86] + node _T_249 = eq(_T_247, _T_248) @[lib.scala 104:78] + node _T_250 = mux(_T_246, UInt<1>("h01"), _T_249) @[lib.scala 104:23] + _T_54[27] <= _T_250 @[lib.scala 104:17] + node _T_251 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[lib.scala 104:28] + node _T_252 = andr(_T_251) @[lib.scala 104:36] + node _T_253 = and(_T_252, _T_57) @[lib.scala 104:41] + node _T_254 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[lib.scala 104:74] + node _T_255 = bits(lsu_match_data_0, 28, 28) @[lib.scala 104:86] + node _T_256 = eq(_T_254, _T_255) @[lib.scala 104:78] + node _T_257 = mux(_T_253, UInt<1>("h01"), _T_256) @[lib.scala 104:23] + _T_54[28] <= _T_257 @[lib.scala 104:17] + node _T_258 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[lib.scala 104:28] + node _T_259 = andr(_T_258) @[lib.scala 104:36] + node _T_260 = and(_T_259, _T_57) @[lib.scala 104:41] + node _T_261 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[lib.scala 104:74] + node _T_262 = bits(lsu_match_data_0, 29, 29) @[lib.scala 104:86] + node _T_263 = eq(_T_261, _T_262) @[lib.scala 104:78] + node _T_264 = mux(_T_260, UInt<1>("h01"), _T_263) @[lib.scala 104:23] + _T_54[29] <= _T_264 @[lib.scala 104:17] + node _T_265 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[lib.scala 104:28] + node _T_266 = andr(_T_265) @[lib.scala 104:36] + node _T_267 = and(_T_266, _T_57) @[lib.scala 104:41] + node _T_268 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[lib.scala 104:74] + node _T_269 = bits(lsu_match_data_0, 30, 30) @[lib.scala 104:86] + node _T_270 = eq(_T_268, _T_269) @[lib.scala 104:78] + node _T_271 = mux(_T_267, UInt<1>("h01"), _T_270) @[lib.scala 104:23] + _T_54[30] <= _T_271 @[lib.scala 104:17] + node _T_272 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[lib.scala 104:28] + node _T_273 = andr(_T_272) @[lib.scala 104:36] + node _T_274 = and(_T_273, _T_57) @[lib.scala 104:41] + node _T_275 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[lib.scala 104:74] + node _T_276 = bits(lsu_match_data_0, 31, 31) @[lib.scala 104:86] + node _T_277 = eq(_T_275, _T_276) @[lib.scala 104:78] + node _T_278 = mux(_T_274, UInt<1>("h01"), _T_277) @[lib.scala 104:23] + _T_54[31] <= _T_278 @[lib.scala 104:17] + node _T_279 = cat(_T_54[1], _T_54[0]) @[lib.scala 105:14] + node _T_280 = cat(_T_54[3], _T_54[2]) @[lib.scala 105:14] + node _T_281 = cat(_T_280, _T_279) @[lib.scala 105:14] + node _T_282 = cat(_T_54[5], _T_54[4]) @[lib.scala 105:14] + node _T_283 = cat(_T_54[7], _T_54[6]) @[lib.scala 105:14] + node _T_284 = cat(_T_283, _T_282) @[lib.scala 105:14] + node _T_285 = cat(_T_284, _T_281) @[lib.scala 105:14] + node _T_286 = cat(_T_54[9], _T_54[8]) @[lib.scala 105:14] + node _T_287 = cat(_T_54[11], _T_54[10]) @[lib.scala 105:14] + node _T_288 = cat(_T_287, _T_286) @[lib.scala 105:14] + node _T_289 = cat(_T_54[13], _T_54[12]) @[lib.scala 105:14] + node _T_290 = cat(_T_54[15], _T_54[14]) @[lib.scala 105:14] + node _T_291 = cat(_T_290, _T_289) @[lib.scala 105:14] + node _T_292 = cat(_T_291, _T_288) @[lib.scala 105:14] + node _T_293 = cat(_T_292, _T_285) @[lib.scala 105:14] + node _T_294 = cat(_T_54[17], _T_54[16]) @[lib.scala 105:14] + node _T_295 = cat(_T_54[19], _T_54[18]) @[lib.scala 105:14] + node _T_296 = cat(_T_295, _T_294) @[lib.scala 105:14] + node _T_297 = cat(_T_54[21], _T_54[20]) @[lib.scala 105:14] + node _T_298 = cat(_T_54[23], _T_54[22]) @[lib.scala 105:14] + node _T_299 = cat(_T_298, _T_297) @[lib.scala 105:14] + node _T_300 = cat(_T_299, _T_296) @[lib.scala 105:14] + node _T_301 = cat(_T_54[25], _T_54[24]) @[lib.scala 105:14] + node _T_302 = cat(_T_54[27], _T_54[26]) @[lib.scala 105:14] + node _T_303 = cat(_T_302, _T_301) @[lib.scala 105:14] + node _T_304 = cat(_T_54[29], _T_54[28]) @[lib.scala 105:14] + node _T_305 = cat(_T_54[31], _T_54[30]) @[lib.scala 105:14] + node _T_306 = cat(_T_305, _T_304) @[lib.scala 105:14] + node _T_307 = cat(_T_306, _T_303) @[lib.scala 105:14] + node _T_308 = cat(_T_307, _T_300) @[lib.scala 105:14] + node _T_309 = cat(_T_308, _T_293) @[lib.scala 105:14] + node _T_310 = andr(_T_309) @[lib.scala 105:25] + node _T_311 = and(_T_52, _T_310) @[lsu_trigger.scala 21:92] + node _T_312 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 20:70] + node _T_313 = and(io.lsu_pkt_m.valid, _T_312) @[lsu_trigger.scala 20:68] + node _T_314 = and(_T_313, trigger_enable) @[lsu_trigger.scala 20:93] + node _T_315 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 20:142] + node _T_316 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 21:33] + node _T_317 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[lsu_trigger.scala 21:60] + node _T_318 = and(_T_316, _T_317) @[lsu_trigger.scala 21:58] + node _T_319 = or(_T_315, _T_318) @[lsu_trigger.scala 20:168] + node _T_320 = and(_T_314, _T_319) @[lsu_trigger.scala 20:110] + node _T_321 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[lsu_trigger.scala 22:107] + wire _T_322 : UInt<1>[32] @[lib.scala 100:24] + node _T_323 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 101:45] + node _T_324 = not(_T_323) @[lib.scala 101:39] + node _T_325 = and(_T_321, _T_324) @[lib.scala 101:37] + node _T_326 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 102:48] + node _T_327 = bits(lsu_match_data_1, 0, 0) @[lib.scala 102:60] + node _T_328 = eq(_T_326, _T_327) @[lib.scala 102:52] + node _T_329 = or(_T_325, _T_328) @[lib.scala 102:41] + _T_322[0] <= _T_329 @[lib.scala 102:18] + node _T_330 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 104:28] + node _T_331 = andr(_T_330) @[lib.scala 104:36] + node _T_332 = and(_T_331, _T_325) @[lib.scala 104:41] + node _T_333 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 104:74] + node _T_334 = bits(lsu_match_data_1, 1, 1) @[lib.scala 104:86] + node _T_335 = eq(_T_333, _T_334) @[lib.scala 104:78] + node _T_336 = mux(_T_332, UInt<1>("h01"), _T_335) @[lib.scala 104:23] + _T_322[1] <= _T_336 @[lib.scala 104:17] + node _T_337 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 104:28] + node _T_338 = andr(_T_337) @[lib.scala 104:36] + node _T_339 = and(_T_338, _T_325) @[lib.scala 104:41] + node _T_340 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 104:74] + node _T_341 = bits(lsu_match_data_1, 2, 2) @[lib.scala 104:86] + node _T_342 = eq(_T_340, _T_341) @[lib.scala 104:78] + node _T_343 = mux(_T_339, UInt<1>("h01"), _T_342) @[lib.scala 104:23] + _T_322[2] <= _T_343 @[lib.scala 104:17] + node _T_344 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 104:28] + node _T_345 = andr(_T_344) @[lib.scala 104:36] + node _T_346 = and(_T_345, _T_325) @[lib.scala 104:41] + node _T_347 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 104:74] + node _T_348 = bits(lsu_match_data_1, 3, 3) @[lib.scala 104:86] + node _T_349 = eq(_T_347, _T_348) @[lib.scala 104:78] + node _T_350 = mux(_T_346, UInt<1>("h01"), _T_349) @[lib.scala 104:23] + _T_322[3] <= _T_350 @[lib.scala 104:17] + node _T_351 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 104:28] + node _T_352 = andr(_T_351) @[lib.scala 104:36] + node _T_353 = and(_T_352, _T_325) @[lib.scala 104:41] + node _T_354 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 104:74] + node _T_355 = bits(lsu_match_data_1, 4, 4) @[lib.scala 104:86] + node _T_356 = eq(_T_354, _T_355) @[lib.scala 104:78] + node _T_357 = mux(_T_353, UInt<1>("h01"), _T_356) @[lib.scala 104:23] + _T_322[4] <= _T_357 @[lib.scala 104:17] + node _T_358 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 104:28] + node _T_359 = andr(_T_358) @[lib.scala 104:36] + node _T_360 = and(_T_359, _T_325) @[lib.scala 104:41] + node _T_361 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 104:74] + node _T_362 = bits(lsu_match_data_1, 5, 5) @[lib.scala 104:86] + node _T_363 = eq(_T_361, _T_362) @[lib.scala 104:78] + node _T_364 = mux(_T_360, UInt<1>("h01"), _T_363) @[lib.scala 104:23] + _T_322[5] <= _T_364 @[lib.scala 104:17] + node _T_365 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 104:28] + node _T_366 = andr(_T_365) @[lib.scala 104:36] + node _T_367 = and(_T_366, _T_325) @[lib.scala 104:41] + node _T_368 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 104:74] + node _T_369 = bits(lsu_match_data_1, 6, 6) @[lib.scala 104:86] + node _T_370 = eq(_T_368, _T_369) @[lib.scala 104:78] + node _T_371 = mux(_T_367, UInt<1>("h01"), _T_370) @[lib.scala 104:23] + _T_322[6] <= _T_371 @[lib.scala 104:17] + node _T_372 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 104:28] + node _T_373 = andr(_T_372) @[lib.scala 104:36] + node _T_374 = and(_T_373, _T_325) @[lib.scala 104:41] + node _T_375 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 104:74] + node _T_376 = bits(lsu_match_data_1, 7, 7) @[lib.scala 104:86] + node _T_377 = eq(_T_375, _T_376) @[lib.scala 104:78] + node _T_378 = mux(_T_374, UInt<1>("h01"), _T_377) @[lib.scala 104:23] + _T_322[7] <= _T_378 @[lib.scala 104:17] + node _T_379 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 104:28] + node _T_380 = andr(_T_379) @[lib.scala 104:36] + node _T_381 = and(_T_380, _T_325) @[lib.scala 104:41] + node _T_382 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 104:74] + node _T_383 = bits(lsu_match_data_1, 8, 8) @[lib.scala 104:86] + node _T_384 = eq(_T_382, _T_383) @[lib.scala 104:78] + node _T_385 = mux(_T_381, UInt<1>("h01"), _T_384) @[lib.scala 104:23] + _T_322[8] <= _T_385 @[lib.scala 104:17] + node _T_386 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 104:28] + node _T_387 = andr(_T_386) @[lib.scala 104:36] + node _T_388 = and(_T_387, _T_325) @[lib.scala 104:41] + node _T_389 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 104:74] + node _T_390 = bits(lsu_match_data_1, 9, 9) @[lib.scala 104:86] + node _T_391 = eq(_T_389, _T_390) @[lib.scala 104:78] + node _T_392 = mux(_T_388, UInt<1>("h01"), _T_391) @[lib.scala 104:23] + _T_322[9] <= _T_392 @[lib.scala 104:17] + node _T_393 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 104:28] + node _T_394 = andr(_T_393) @[lib.scala 104:36] + node _T_395 = and(_T_394, _T_325) @[lib.scala 104:41] + node _T_396 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 104:74] + node _T_397 = bits(lsu_match_data_1, 10, 10) @[lib.scala 104:86] + node _T_398 = eq(_T_396, _T_397) @[lib.scala 104:78] + node _T_399 = mux(_T_395, UInt<1>("h01"), _T_398) @[lib.scala 104:23] + _T_322[10] <= _T_399 @[lib.scala 104:17] + node _T_400 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 104:28] + node _T_401 = andr(_T_400) @[lib.scala 104:36] + node _T_402 = and(_T_401, _T_325) @[lib.scala 104:41] + node _T_403 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 104:74] + node _T_404 = bits(lsu_match_data_1, 11, 11) @[lib.scala 104:86] + node _T_405 = eq(_T_403, _T_404) @[lib.scala 104:78] + node _T_406 = mux(_T_402, UInt<1>("h01"), _T_405) @[lib.scala 104:23] + _T_322[11] <= _T_406 @[lib.scala 104:17] + node _T_407 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 104:28] + node _T_408 = andr(_T_407) @[lib.scala 104:36] + node _T_409 = and(_T_408, _T_325) @[lib.scala 104:41] + node _T_410 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 104:74] + node _T_411 = bits(lsu_match_data_1, 12, 12) @[lib.scala 104:86] + node _T_412 = eq(_T_410, _T_411) @[lib.scala 104:78] + node _T_413 = mux(_T_409, UInt<1>("h01"), _T_412) @[lib.scala 104:23] + _T_322[12] <= _T_413 @[lib.scala 104:17] + node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 104:28] + node _T_415 = andr(_T_414) @[lib.scala 104:36] + node _T_416 = and(_T_415, _T_325) @[lib.scala 104:41] + node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 104:74] + node _T_418 = bits(lsu_match_data_1, 13, 13) @[lib.scala 104:86] + node _T_419 = eq(_T_417, _T_418) @[lib.scala 104:78] + node _T_420 = mux(_T_416, UInt<1>("h01"), _T_419) @[lib.scala 104:23] + _T_322[13] <= _T_420 @[lib.scala 104:17] + node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 104:28] + node _T_422 = andr(_T_421) @[lib.scala 104:36] + node _T_423 = and(_T_422, _T_325) @[lib.scala 104:41] + node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 104:74] + node _T_425 = bits(lsu_match_data_1, 14, 14) @[lib.scala 104:86] + node _T_426 = eq(_T_424, _T_425) @[lib.scala 104:78] + node _T_427 = mux(_T_423, UInt<1>("h01"), _T_426) @[lib.scala 104:23] + _T_322[14] <= _T_427 @[lib.scala 104:17] + node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 104:28] + node _T_429 = andr(_T_428) @[lib.scala 104:36] + node _T_430 = and(_T_429, _T_325) @[lib.scala 104:41] + node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 104:74] + node _T_432 = bits(lsu_match_data_1, 15, 15) @[lib.scala 104:86] + node _T_433 = eq(_T_431, _T_432) @[lib.scala 104:78] + node _T_434 = mux(_T_430, UInt<1>("h01"), _T_433) @[lib.scala 104:23] + _T_322[15] <= _T_434 @[lib.scala 104:17] + node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 104:28] + node _T_436 = andr(_T_435) @[lib.scala 104:36] + node _T_437 = and(_T_436, _T_325) @[lib.scala 104:41] + node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 104:74] + node _T_439 = bits(lsu_match_data_1, 16, 16) @[lib.scala 104:86] + node _T_440 = eq(_T_438, _T_439) @[lib.scala 104:78] + node _T_441 = mux(_T_437, UInt<1>("h01"), _T_440) @[lib.scala 104:23] + _T_322[16] <= _T_441 @[lib.scala 104:17] + node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 104:28] + node _T_443 = andr(_T_442) @[lib.scala 104:36] + node _T_444 = and(_T_443, _T_325) @[lib.scala 104:41] + node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 104:74] + node _T_446 = bits(lsu_match_data_1, 17, 17) @[lib.scala 104:86] + node _T_447 = eq(_T_445, _T_446) @[lib.scala 104:78] + node _T_448 = mux(_T_444, UInt<1>("h01"), _T_447) @[lib.scala 104:23] + _T_322[17] <= _T_448 @[lib.scala 104:17] + node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 104:28] + node _T_450 = andr(_T_449) @[lib.scala 104:36] + node _T_451 = and(_T_450, _T_325) @[lib.scala 104:41] + node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 104:74] + node _T_453 = bits(lsu_match_data_1, 18, 18) @[lib.scala 104:86] + node _T_454 = eq(_T_452, _T_453) @[lib.scala 104:78] + node _T_455 = mux(_T_451, UInt<1>("h01"), _T_454) @[lib.scala 104:23] + _T_322[18] <= _T_455 @[lib.scala 104:17] + node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 104:28] + node _T_457 = andr(_T_456) @[lib.scala 104:36] + node _T_458 = and(_T_457, _T_325) @[lib.scala 104:41] + node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 104:74] + node _T_460 = bits(lsu_match_data_1, 19, 19) @[lib.scala 104:86] + node _T_461 = eq(_T_459, _T_460) @[lib.scala 104:78] + node _T_462 = mux(_T_458, UInt<1>("h01"), _T_461) @[lib.scala 104:23] + _T_322[19] <= _T_462 @[lib.scala 104:17] + node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 104:28] + node _T_464 = andr(_T_463) @[lib.scala 104:36] + node _T_465 = and(_T_464, _T_325) @[lib.scala 104:41] + node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 104:74] + node _T_467 = bits(lsu_match_data_1, 20, 20) @[lib.scala 104:86] + node _T_468 = eq(_T_466, _T_467) @[lib.scala 104:78] + node _T_469 = mux(_T_465, UInt<1>("h01"), _T_468) @[lib.scala 104:23] + _T_322[20] <= _T_469 @[lib.scala 104:17] + node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 104:28] + node _T_471 = andr(_T_470) @[lib.scala 104:36] + node _T_472 = and(_T_471, _T_325) @[lib.scala 104:41] + node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 104:74] + node _T_474 = bits(lsu_match_data_1, 21, 21) @[lib.scala 104:86] + node _T_475 = eq(_T_473, _T_474) @[lib.scala 104:78] + node _T_476 = mux(_T_472, UInt<1>("h01"), _T_475) @[lib.scala 104:23] + _T_322[21] <= _T_476 @[lib.scala 104:17] + node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 104:28] + node _T_478 = andr(_T_477) @[lib.scala 104:36] + node _T_479 = and(_T_478, _T_325) @[lib.scala 104:41] + node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 104:74] + node _T_481 = bits(lsu_match_data_1, 22, 22) @[lib.scala 104:86] + node _T_482 = eq(_T_480, _T_481) @[lib.scala 104:78] + node _T_483 = mux(_T_479, UInt<1>("h01"), _T_482) @[lib.scala 104:23] + _T_322[22] <= _T_483 @[lib.scala 104:17] + node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 104:28] + node _T_485 = andr(_T_484) @[lib.scala 104:36] + node _T_486 = and(_T_485, _T_325) @[lib.scala 104:41] + node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 104:74] + node _T_488 = bits(lsu_match_data_1, 23, 23) @[lib.scala 104:86] + node _T_489 = eq(_T_487, _T_488) @[lib.scala 104:78] + node _T_490 = mux(_T_486, UInt<1>("h01"), _T_489) @[lib.scala 104:23] + _T_322[23] <= _T_490 @[lib.scala 104:17] + node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 104:28] + node _T_492 = andr(_T_491) @[lib.scala 104:36] + node _T_493 = and(_T_492, _T_325) @[lib.scala 104:41] + node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 104:74] + node _T_495 = bits(lsu_match_data_1, 24, 24) @[lib.scala 104:86] + node _T_496 = eq(_T_494, _T_495) @[lib.scala 104:78] + node _T_497 = mux(_T_493, UInt<1>("h01"), _T_496) @[lib.scala 104:23] + _T_322[24] <= _T_497 @[lib.scala 104:17] + node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 104:28] + node _T_499 = andr(_T_498) @[lib.scala 104:36] + node _T_500 = and(_T_499, _T_325) @[lib.scala 104:41] + node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 104:74] + node _T_502 = bits(lsu_match_data_1, 25, 25) @[lib.scala 104:86] + node _T_503 = eq(_T_501, _T_502) @[lib.scala 104:78] + node _T_504 = mux(_T_500, UInt<1>("h01"), _T_503) @[lib.scala 104:23] + _T_322[25] <= _T_504 @[lib.scala 104:17] + node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 104:28] + node _T_506 = andr(_T_505) @[lib.scala 104:36] + node _T_507 = and(_T_506, _T_325) @[lib.scala 104:41] + node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 104:74] + node _T_509 = bits(lsu_match_data_1, 26, 26) @[lib.scala 104:86] + node _T_510 = eq(_T_508, _T_509) @[lib.scala 104:78] + node _T_511 = mux(_T_507, UInt<1>("h01"), _T_510) @[lib.scala 104:23] + _T_322[26] <= _T_511 @[lib.scala 104:17] + node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 104:28] + node _T_513 = andr(_T_512) @[lib.scala 104:36] + node _T_514 = and(_T_513, _T_325) @[lib.scala 104:41] + node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 104:74] + node _T_516 = bits(lsu_match_data_1, 27, 27) @[lib.scala 104:86] + node _T_517 = eq(_T_515, _T_516) @[lib.scala 104:78] + node _T_518 = mux(_T_514, UInt<1>("h01"), _T_517) @[lib.scala 104:23] + _T_322[27] <= _T_518 @[lib.scala 104:17] + node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 104:28] + node _T_520 = andr(_T_519) @[lib.scala 104:36] + node _T_521 = and(_T_520, _T_325) @[lib.scala 104:41] + node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 104:74] + node _T_523 = bits(lsu_match_data_1, 28, 28) @[lib.scala 104:86] + node _T_524 = eq(_T_522, _T_523) @[lib.scala 104:78] + node _T_525 = mux(_T_521, UInt<1>("h01"), _T_524) @[lib.scala 104:23] + _T_322[28] <= _T_525 @[lib.scala 104:17] + node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 104:28] + node _T_527 = andr(_T_526) @[lib.scala 104:36] + node _T_528 = and(_T_527, _T_325) @[lib.scala 104:41] + node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 104:74] + node _T_530 = bits(lsu_match_data_1, 29, 29) @[lib.scala 104:86] + node _T_531 = eq(_T_529, _T_530) @[lib.scala 104:78] + node _T_532 = mux(_T_528, UInt<1>("h01"), _T_531) @[lib.scala 104:23] + _T_322[29] <= _T_532 @[lib.scala 104:17] + node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 104:28] + node _T_534 = andr(_T_533) @[lib.scala 104:36] + node _T_535 = and(_T_534, _T_325) @[lib.scala 104:41] + node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 104:74] + node _T_537 = bits(lsu_match_data_1, 30, 30) @[lib.scala 104:86] + node _T_538 = eq(_T_536, _T_537) @[lib.scala 104:78] + node _T_539 = mux(_T_535, UInt<1>("h01"), _T_538) @[lib.scala 104:23] + _T_322[30] <= _T_539 @[lib.scala 104:17] + node _T_540 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 104:28] + node _T_541 = andr(_T_540) @[lib.scala 104:36] + node _T_542 = and(_T_541, _T_325) @[lib.scala 104:41] + node _T_543 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 104:74] + node _T_544 = bits(lsu_match_data_1, 31, 31) @[lib.scala 104:86] + node _T_545 = eq(_T_543, _T_544) @[lib.scala 104:78] + node _T_546 = mux(_T_542, UInt<1>("h01"), _T_545) @[lib.scala 104:23] + _T_322[31] <= _T_546 @[lib.scala 104:17] + node _T_547 = cat(_T_322[1], _T_322[0]) @[lib.scala 105:14] + node _T_548 = cat(_T_322[3], _T_322[2]) @[lib.scala 105:14] + node _T_549 = cat(_T_548, _T_547) @[lib.scala 105:14] + node _T_550 = cat(_T_322[5], _T_322[4]) @[lib.scala 105:14] + node _T_551 = cat(_T_322[7], _T_322[6]) @[lib.scala 105:14] + node _T_552 = cat(_T_551, _T_550) @[lib.scala 105:14] + node _T_553 = cat(_T_552, _T_549) @[lib.scala 105:14] + node _T_554 = cat(_T_322[9], _T_322[8]) @[lib.scala 105:14] + node _T_555 = cat(_T_322[11], _T_322[10]) @[lib.scala 105:14] + node _T_556 = cat(_T_555, _T_554) @[lib.scala 105:14] + node _T_557 = cat(_T_322[13], _T_322[12]) @[lib.scala 105:14] + node _T_558 = cat(_T_322[15], _T_322[14]) @[lib.scala 105:14] + node _T_559 = cat(_T_558, _T_557) @[lib.scala 105:14] + node _T_560 = cat(_T_559, _T_556) @[lib.scala 105:14] + node _T_561 = cat(_T_560, _T_553) @[lib.scala 105:14] + node _T_562 = cat(_T_322[17], _T_322[16]) @[lib.scala 105:14] + node _T_563 = cat(_T_322[19], _T_322[18]) @[lib.scala 105:14] + node _T_564 = cat(_T_563, _T_562) @[lib.scala 105:14] + node _T_565 = cat(_T_322[21], _T_322[20]) @[lib.scala 105:14] + node _T_566 = cat(_T_322[23], _T_322[22]) @[lib.scala 105:14] + node _T_567 = cat(_T_566, _T_565) @[lib.scala 105:14] + node _T_568 = cat(_T_567, _T_564) @[lib.scala 105:14] + node _T_569 = cat(_T_322[25], _T_322[24]) @[lib.scala 105:14] + node _T_570 = cat(_T_322[27], _T_322[26]) @[lib.scala 105:14] + node _T_571 = cat(_T_570, _T_569) @[lib.scala 105:14] + node _T_572 = cat(_T_322[29], _T_322[28]) @[lib.scala 105:14] + node _T_573 = cat(_T_322[31], _T_322[30]) @[lib.scala 105:14] + node _T_574 = cat(_T_573, _T_572) @[lib.scala 105:14] + node _T_575 = cat(_T_574, _T_571) @[lib.scala 105:14] + node _T_576 = cat(_T_575, _T_568) @[lib.scala 105:14] + node _T_577 = cat(_T_576, _T_561) @[lib.scala 105:14] + node _T_578 = andr(_T_577) @[lib.scala 105:25] + node _T_579 = and(_T_320, _T_578) @[lsu_trigger.scala 21:92] + node _T_580 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 20:70] + node _T_581 = and(io.lsu_pkt_m.valid, _T_580) @[lsu_trigger.scala 20:68] + node _T_582 = and(_T_581, trigger_enable) @[lsu_trigger.scala 20:93] + node _T_583 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 20:142] + node _T_584 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 21:33] + node _T_585 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[lsu_trigger.scala 21:60] + node _T_586 = and(_T_584, _T_585) @[lsu_trigger.scala 21:58] + node _T_587 = or(_T_583, _T_586) @[lsu_trigger.scala 20:168] + node _T_588 = and(_T_582, _T_587) @[lsu_trigger.scala 20:110] + node _T_589 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[lsu_trigger.scala 22:107] + wire _T_590 : UInt<1>[32] @[lib.scala 100:24] + node _T_591 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 101:45] + node _T_592 = not(_T_591) @[lib.scala 101:39] + node _T_593 = and(_T_589, _T_592) @[lib.scala 101:37] + node _T_594 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 102:48] + node _T_595 = bits(lsu_match_data_2, 0, 0) @[lib.scala 102:60] + node _T_596 = eq(_T_594, _T_595) @[lib.scala 102:52] + node _T_597 = or(_T_593, _T_596) @[lib.scala 102:41] + _T_590[0] <= _T_597 @[lib.scala 102:18] + node _T_598 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 104:28] + node _T_599 = andr(_T_598) @[lib.scala 104:36] + node _T_600 = and(_T_599, _T_593) @[lib.scala 104:41] + node _T_601 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 104:74] + node _T_602 = bits(lsu_match_data_2, 1, 1) @[lib.scala 104:86] + node _T_603 = eq(_T_601, _T_602) @[lib.scala 104:78] + node _T_604 = mux(_T_600, UInt<1>("h01"), _T_603) @[lib.scala 104:23] + _T_590[1] <= _T_604 @[lib.scala 104:17] + node _T_605 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 104:28] + node _T_606 = andr(_T_605) @[lib.scala 104:36] + node _T_607 = and(_T_606, _T_593) @[lib.scala 104:41] + node _T_608 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 104:74] + node _T_609 = bits(lsu_match_data_2, 2, 2) @[lib.scala 104:86] + node _T_610 = eq(_T_608, _T_609) @[lib.scala 104:78] + node _T_611 = mux(_T_607, UInt<1>("h01"), _T_610) @[lib.scala 104:23] + _T_590[2] <= _T_611 @[lib.scala 104:17] + node _T_612 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 104:28] + node _T_613 = andr(_T_612) @[lib.scala 104:36] + node _T_614 = and(_T_613, _T_593) @[lib.scala 104:41] + node _T_615 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 104:74] + node _T_616 = bits(lsu_match_data_2, 3, 3) @[lib.scala 104:86] + node _T_617 = eq(_T_615, _T_616) @[lib.scala 104:78] + node _T_618 = mux(_T_614, UInt<1>("h01"), _T_617) @[lib.scala 104:23] + _T_590[3] <= _T_618 @[lib.scala 104:17] + node _T_619 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 104:28] + node _T_620 = andr(_T_619) @[lib.scala 104:36] + node _T_621 = and(_T_620, _T_593) @[lib.scala 104:41] + node _T_622 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 104:74] + node _T_623 = bits(lsu_match_data_2, 4, 4) @[lib.scala 104:86] + node _T_624 = eq(_T_622, _T_623) @[lib.scala 104:78] + node _T_625 = mux(_T_621, UInt<1>("h01"), _T_624) @[lib.scala 104:23] + _T_590[4] <= _T_625 @[lib.scala 104:17] + node _T_626 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 104:28] + node _T_627 = andr(_T_626) @[lib.scala 104:36] + node _T_628 = and(_T_627, _T_593) @[lib.scala 104:41] + node _T_629 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 104:74] + node _T_630 = bits(lsu_match_data_2, 5, 5) @[lib.scala 104:86] + node _T_631 = eq(_T_629, _T_630) @[lib.scala 104:78] + node _T_632 = mux(_T_628, UInt<1>("h01"), _T_631) @[lib.scala 104:23] + _T_590[5] <= _T_632 @[lib.scala 104:17] + node _T_633 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 104:28] + node _T_634 = andr(_T_633) @[lib.scala 104:36] + node _T_635 = and(_T_634, _T_593) @[lib.scala 104:41] + node _T_636 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 104:74] + node _T_637 = bits(lsu_match_data_2, 6, 6) @[lib.scala 104:86] + node _T_638 = eq(_T_636, _T_637) @[lib.scala 104:78] + node _T_639 = mux(_T_635, UInt<1>("h01"), _T_638) @[lib.scala 104:23] + _T_590[6] <= _T_639 @[lib.scala 104:17] + node _T_640 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 104:28] + node _T_641 = andr(_T_640) @[lib.scala 104:36] + node _T_642 = and(_T_641, _T_593) @[lib.scala 104:41] + node _T_643 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 104:74] + node _T_644 = bits(lsu_match_data_2, 7, 7) @[lib.scala 104:86] + node _T_645 = eq(_T_643, _T_644) @[lib.scala 104:78] + node _T_646 = mux(_T_642, UInt<1>("h01"), _T_645) @[lib.scala 104:23] + _T_590[7] <= _T_646 @[lib.scala 104:17] + node _T_647 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 104:28] + node _T_648 = andr(_T_647) @[lib.scala 104:36] + node _T_649 = and(_T_648, _T_593) @[lib.scala 104:41] + node _T_650 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 104:74] + node _T_651 = bits(lsu_match_data_2, 8, 8) @[lib.scala 104:86] + node _T_652 = eq(_T_650, _T_651) @[lib.scala 104:78] + node _T_653 = mux(_T_649, UInt<1>("h01"), _T_652) @[lib.scala 104:23] + _T_590[8] <= _T_653 @[lib.scala 104:17] + node _T_654 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 104:28] + node _T_655 = andr(_T_654) @[lib.scala 104:36] + node _T_656 = and(_T_655, _T_593) @[lib.scala 104:41] + node _T_657 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 104:74] + node _T_658 = bits(lsu_match_data_2, 9, 9) @[lib.scala 104:86] + node _T_659 = eq(_T_657, _T_658) @[lib.scala 104:78] + node _T_660 = mux(_T_656, UInt<1>("h01"), _T_659) @[lib.scala 104:23] + _T_590[9] <= _T_660 @[lib.scala 104:17] + node _T_661 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 104:28] + node _T_662 = andr(_T_661) @[lib.scala 104:36] + node _T_663 = and(_T_662, _T_593) @[lib.scala 104:41] + node _T_664 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 104:74] + node _T_665 = bits(lsu_match_data_2, 10, 10) @[lib.scala 104:86] + node _T_666 = eq(_T_664, _T_665) @[lib.scala 104:78] + node _T_667 = mux(_T_663, UInt<1>("h01"), _T_666) @[lib.scala 104:23] + _T_590[10] <= _T_667 @[lib.scala 104:17] + node _T_668 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 104:28] + node _T_669 = andr(_T_668) @[lib.scala 104:36] + node _T_670 = and(_T_669, _T_593) @[lib.scala 104:41] + node _T_671 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 104:74] + node _T_672 = bits(lsu_match_data_2, 11, 11) @[lib.scala 104:86] + node _T_673 = eq(_T_671, _T_672) @[lib.scala 104:78] + node _T_674 = mux(_T_670, UInt<1>("h01"), _T_673) @[lib.scala 104:23] + _T_590[11] <= _T_674 @[lib.scala 104:17] + node _T_675 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 104:28] + node _T_676 = andr(_T_675) @[lib.scala 104:36] + node _T_677 = and(_T_676, _T_593) @[lib.scala 104:41] + node _T_678 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 104:74] + node _T_679 = bits(lsu_match_data_2, 12, 12) @[lib.scala 104:86] + node _T_680 = eq(_T_678, _T_679) @[lib.scala 104:78] + node _T_681 = mux(_T_677, UInt<1>("h01"), _T_680) @[lib.scala 104:23] + _T_590[12] <= _T_681 @[lib.scala 104:17] + node _T_682 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 104:28] + node _T_683 = andr(_T_682) @[lib.scala 104:36] + node _T_684 = and(_T_683, _T_593) @[lib.scala 104:41] + node _T_685 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 104:74] + node _T_686 = bits(lsu_match_data_2, 13, 13) @[lib.scala 104:86] + node _T_687 = eq(_T_685, _T_686) @[lib.scala 104:78] + node _T_688 = mux(_T_684, UInt<1>("h01"), _T_687) @[lib.scala 104:23] + _T_590[13] <= _T_688 @[lib.scala 104:17] + node _T_689 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 104:28] + node _T_690 = andr(_T_689) @[lib.scala 104:36] + node _T_691 = and(_T_690, _T_593) @[lib.scala 104:41] + node _T_692 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 104:74] + node _T_693 = bits(lsu_match_data_2, 14, 14) @[lib.scala 104:86] + node _T_694 = eq(_T_692, _T_693) @[lib.scala 104:78] + node _T_695 = mux(_T_691, UInt<1>("h01"), _T_694) @[lib.scala 104:23] + _T_590[14] <= _T_695 @[lib.scala 104:17] + node _T_696 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 104:28] + node _T_697 = andr(_T_696) @[lib.scala 104:36] + node _T_698 = and(_T_697, _T_593) @[lib.scala 104:41] + node _T_699 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 104:74] + node _T_700 = bits(lsu_match_data_2, 15, 15) @[lib.scala 104:86] + node _T_701 = eq(_T_699, _T_700) @[lib.scala 104:78] + node _T_702 = mux(_T_698, UInt<1>("h01"), _T_701) @[lib.scala 104:23] + _T_590[15] <= _T_702 @[lib.scala 104:17] + node _T_703 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 104:28] + node _T_704 = andr(_T_703) @[lib.scala 104:36] + node _T_705 = and(_T_704, _T_593) @[lib.scala 104:41] + node _T_706 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 104:74] + node _T_707 = bits(lsu_match_data_2, 16, 16) @[lib.scala 104:86] + node _T_708 = eq(_T_706, _T_707) @[lib.scala 104:78] + node _T_709 = mux(_T_705, UInt<1>("h01"), _T_708) @[lib.scala 104:23] + _T_590[16] <= _T_709 @[lib.scala 104:17] + node _T_710 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 104:28] + node _T_711 = andr(_T_710) @[lib.scala 104:36] + node _T_712 = and(_T_711, _T_593) @[lib.scala 104:41] + node _T_713 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 104:74] + node _T_714 = bits(lsu_match_data_2, 17, 17) @[lib.scala 104:86] + node _T_715 = eq(_T_713, _T_714) @[lib.scala 104:78] + node _T_716 = mux(_T_712, UInt<1>("h01"), _T_715) @[lib.scala 104:23] + _T_590[17] <= _T_716 @[lib.scala 104:17] + node _T_717 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 104:28] + node _T_718 = andr(_T_717) @[lib.scala 104:36] + node _T_719 = and(_T_718, _T_593) @[lib.scala 104:41] + node _T_720 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 104:74] + node _T_721 = bits(lsu_match_data_2, 18, 18) @[lib.scala 104:86] + node _T_722 = eq(_T_720, _T_721) @[lib.scala 104:78] + node _T_723 = mux(_T_719, UInt<1>("h01"), _T_722) @[lib.scala 104:23] + _T_590[18] <= _T_723 @[lib.scala 104:17] + node _T_724 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 104:28] + node _T_725 = andr(_T_724) @[lib.scala 104:36] + node _T_726 = and(_T_725, _T_593) @[lib.scala 104:41] + node _T_727 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 104:74] + node _T_728 = bits(lsu_match_data_2, 19, 19) @[lib.scala 104:86] + node _T_729 = eq(_T_727, _T_728) @[lib.scala 104:78] + node _T_730 = mux(_T_726, UInt<1>("h01"), _T_729) @[lib.scala 104:23] + _T_590[19] <= _T_730 @[lib.scala 104:17] + node _T_731 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 104:28] + node _T_732 = andr(_T_731) @[lib.scala 104:36] + node _T_733 = and(_T_732, _T_593) @[lib.scala 104:41] + node _T_734 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 104:74] + node _T_735 = bits(lsu_match_data_2, 20, 20) @[lib.scala 104:86] + node _T_736 = eq(_T_734, _T_735) @[lib.scala 104:78] + node _T_737 = mux(_T_733, UInt<1>("h01"), _T_736) @[lib.scala 104:23] + _T_590[20] <= _T_737 @[lib.scala 104:17] + node _T_738 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 104:28] + node _T_739 = andr(_T_738) @[lib.scala 104:36] + node _T_740 = and(_T_739, _T_593) @[lib.scala 104:41] + node _T_741 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 104:74] + node _T_742 = bits(lsu_match_data_2, 21, 21) @[lib.scala 104:86] + node _T_743 = eq(_T_741, _T_742) @[lib.scala 104:78] + node _T_744 = mux(_T_740, UInt<1>("h01"), _T_743) @[lib.scala 104:23] + _T_590[21] <= _T_744 @[lib.scala 104:17] + node _T_745 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 104:28] + node _T_746 = andr(_T_745) @[lib.scala 104:36] + node _T_747 = and(_T_746, _T_593) @[lib.scala 104:41] + node _T_748 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 104:74] + node _T_749 = bits(lsu_match_data_2, 22, 22) @[lib.scala 104:86] + node _T_750 = eq(_T_748, _T_749) @[lib.scala 104:78] + node _T_751 = mux(_T_747, UInt<1>("h01"), _T_750) @[lib.scala 104:23] + _T_590[22] <= _T_751 @[lib.scala 104:17] + node _T_752 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 104:28] + node _T_753 = andr(_T_752) @[lib.scala 104:36] + node _T_754 = and(_T_753, _T_593) @[lib.scala 104:41] + node _T_755 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 104:74] + node _T_756 = bits(lsu_match_data_2, 23, 23) @[lib.scala 104:86] + node _T_757 = eq(_T_755, _T_756) @[lib.scala 104:78] + node _T_758 = mux(_T_754, UInt<1>("h01"), _T_757) @[lib.scala 104:23] + _T_590[23] <= _T_758 @[lib.scala 104:17] + node _T_759 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 104:28] + node _T_760 = andr(_T_759) @[lib.scala 104:36] + node _T_761 = and(_T_760, _T_593) @[lib.scala 104:41] + node _T_762 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 104:74] + node _T_763 = bits(lsu_match_data_2, 24, 24) @[lib.scala 104:86] + node _T_764 = eq(_T_762, _T_763) @[lib.scala 104:78] + node _T_765 = mux(_T_761, UInt<1>("h01"), _T_764) @[lib.scala 104:23] + _T_590[24] <= _T_765 @[lib.scala 104:17] + node _T_766 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 104:28] + node _T_767 = andr(_T_766) @[lib.scala 104:36] + node _T_768 = and(_T_767, _T_593) @[lib.scala 104:41] + node _T_769 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 104:74] + node _T_770 = bits(lsu_match_data_2, 25, 25) @[lib.scala 104:86] + node _T_771 = eq(_T_769, _T_770) @[lib.scala 104:78] + node _T_772 = mux(_T_768, UInt<1>("h01"), _T_771) @[lib.scala 104:23] + _T_590[25] <= _T_772 @[lib.scala 104:17] + node _T_773 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 104:28] + node _T_774 = andr(_T_773) @[lib.scala 104:36] + node _T_775 = and(_T_774, _T_593) @[lib.scala 104:41] + node _T_776 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 104:74] + node _T_777 = bits(lsu_match_data_2, 26, 26) @[lib.scala 104:86] + node _T_778 = eq(_T_776, _T_777) @[lib.scala 104:78] + node _T_779 = mux(_T_775, UInt<1>("h01"), _T_778) @[lib.scala 104:23] + _T_590[26] <= _T_779 @[lib.scala 104:17] + node _T_780 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 104:28] + node _T_781 = andr(_T_780) @[lib.scala 104:36] + node _T_782 = and(_T_781, _T_593) @[lib.scala 104:41] + node _T_783 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 104:74] + node _T_784 = bits(lsu_match_data_2, 27, 27) @[lib.scala 104:86] + node _T_785 = eq(_T_783, _T_784) @[lib.scala 104:78] + node _T_786 = mux(_T_782, UInt<1>("h01"), _T_785) @[lib.scala 104:23] + _T_590[27] <= _T_786 @[lib.scala 104:17] + node _T_787 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 104:28] + node _T_788 = andr(_T_787) @[lib.scala 104:36] + node _T_789 = and(_T_788, _T_593) @[lib.scala 104:41] + node _T_790 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 104:74] + node _T_791 = bits(lsu_match_data_2, 28, 28) @[lib.scala 104:86] + node _T_792 = eq(_T_790, _T_791) @[lib.scala 104:78] + node _T_793 = mux(_T_789, UInt<1>("h01"), _T_792) @[lib.scala 104:23] + _T_590[28] <= _T_793 @[lib.scala 104:17] + node _T_794 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 104:28] + node _T_795 = andr(_T_794) @[lib.scala 104:36] + node _T_796 = and(_T_795, _T_593) @[lib.scala 104:41] + node _T_797 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 104:74] + node _T_798 = bits(lsu_match_data_2, 29, 29) @[lib.scala 104:86] + node _T_799 = eq(_T_797, _T_798) @[lib.scala 104:78] + node _T_800 = mux(_T_796, UInt<1>("h01"), _T_799) @[lib.scala 104:23] + _T_590[29] <= _T_800 @[lib.scala 104:17] + node _T_801 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 104:28] + node _T_802 = andr(_T_801) @[lib.scala 104:36] + node _T_803 = and(_T_802, _T_593) @[lib.scala 104:41] + node _T_804 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 104:74] + node _T_805 = bits(lsu_match_data_2, 30, 30) @[lib.scala 104:86] + node _T_806 = eq(_T_804, _T_805) @[lib.scala 104:78] + node _T_807 = mux(_T_803, UInt<1>("h01"), _T_806) @[lib.scala 104:23] + _T_590[30] <= _T_807 @[lib.scala 104:17] + node _T_808 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 104:28] + node _T_809 = andr(_T_808) @[lib.scala 104:36] + node _T_810 = and(_T_809, _T_593) @[lib.scala 104:41] + node _T_811 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 104:74] + node _T_812 = bits(lsu_match_data_2, 31, 31) @[lib.scala 104:86] + node _T_813 = eq(_T_811, _T_812) @[lib.scala 104:78] + node _T_814 = mux(_T_810, UInt<1>("h01"), _T_813) @[lib.scala 104:23] + _T_590[31] <= _T_814 @[lib.scala 104:17] + node _T_815 = cat(_T_590[1], _T_590[0]) @[lib.scala 105:14] + node _T_816 = cat(_T_590[3], _T_590[2]) @[lib.scala 105:14] + node _T_817 = cat(_T_816, _T_815) @[lib.scala 105:14] + node _T_818 = cat(_T_590[5], _T_590[4]) @[lib.scala 105:14] + node _T_819 = cat(_T_590[7], _T_590[6]) @[lib.scala 105:14] + node _T_820 = cat(_T_819, _T_818) @[lib.scala 105:14] + node _T_821 = cat(_T_820, _T_817) @[lib.scala 105:14] + node _T_822 = cat(_T_590[9], _T_590[8]) @[lib.scala 105:14] + node _T_823 = cat(_T_590[11], _T_590[10]) @[lib.scala 105:14] + node _T_824 = cat(_T_823, _T_822) @[lib.scala 105:14] + node _T_825 = cat(_T_590[13], _T_590[12]) @[lib.scala 105:14] + node _T_826 = cat(_T_590[15], _T_590[14]) @[lib.scala 105:14] + node _T_827 = cat(_T_826, _T_825) @[lib.scala 105:14] + node _T_828 = cat(_T_827, _T_824) @[lib.scala 105:14] + node _T_829 = cat(_T_828, _T_821) @[lib.scala 105:14] + node _T_830 = cat(_T_590[17], _T_590[16]) @[lib.scala 105:14] + node _T_831 = cat(_T_590[19], _T_590[18]) @[lib.scala 105:14] + node _T_832 = cat(_T_831, _T_830) @[lib.scala 105:14] + node _T_833 = cat(_T_590[21], _T_590[20]) @[lib.scala 105:14] + node _T_834 = cat(_T_590[23], _T_590[22]) @[lib.scala 105:14] + node _T_835 = cat(_T_834, _T_833) @[lib.scala 105:14] + node _T_836 = cat(_T_835, _T_832) @[lib.scala 105:14] + node _T_837 = cat(_T_590[25], _T_590[24]) @[lib.scala 105:14] + node _T_838 = cat(_T_590[27], _T_590[26]) @[lib.scala 105:14] + node _T_839 = cat(_T_838, _T_837) @[lib.scala 105:14] + node _T_840 = cat(_T_590[29], _T_590[28]) @[lib.scala 105:14] + node _T_841 = cat(_T_590[31], _T_590[30]) @[lib.scala 105:14] + node _T_842 = cat(_T_841, _T_840) @[lib.scala 105:14] + node _T_843 = cat(_T_842, _T_839) @[lib.scala 105:14] + node _T_844 = cat(_T_843, _T_836) @[lib.scala 105:14] + node _T_845 = cat(_T_844, _T_829) @[lib.scala 105:14] + node _T_846 = andr(_T_845) @[lib.scala 105:25] + node _T_847 = and(_T_588, _T_846) @[lsu_trigger.scala 21:92] + node _T_848 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 20:70] + node _T_849 = and(io.lsu_pkt_m.valid, _T_848) @[lsu_trigger.scala 20:68] + node _T_850 = and(_T_849, trigger_enable) @[lsu_trigger.scala 20:93] + node _T_851 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 20:142] + node _T_852 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 21:33] + node _T_853 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[lsu_trigger.scala 21:60] + node _T_854 = and(_T_852, _T_853) @[lsu_trigger.scala 21:58] + node _T_855 = or(_T_851, _T_854) @[lsu_trigger.scala 20:168] + node _T_856 = and(_T_850, _T_855) @[lsu_trigger.scala 20:110] + node _T_857 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[lsu_trigger.scala 22:107] + wire _T_858 : UInt<1>[32] @[lib.scala 100:24] + node _T_859 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 101:45] + node _T_860 = not(_T_859) @[lib.scala 101:39] + node _T_861 = and(_T_857, _T_860) @[lib.scala 101:37] + node _T_862 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 102:48] + node _T_863 = bits(lsu_match_data_3, 0, 0) @[lib.scala 102:60] + node _T_864 = eq(_T_862, _T_863) @[lib.scala 102:52] + node _T_865 = or(_T_861, _T_864) @[lib.scala 102:41] + _T_858[0] <= _T_865 @[lib.scala 102:18] + node _T_866 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 104:28] + node _T_867 = andr(_T_866) @[lib.scala 104:36] + node _T_868 = and(_T_867, _T_861) @[lib.scala 104:41] + node _T_869 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 104:74] + node _T_870 = bits(lsu_match_data_3, 1, 1) @[lib.scala 104:86] + node _T_871 = eq(_T_869, _T_870) @[lib.scala 104:78] + node _T_872 = mux(_T_868, UInt<1>("h01"), _T_871) @[lib.scala 104:23] + _T_858[1] <= _T_872 @[lib.scala 104:17] + node _T_873 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 104:28] + node _T_874 = andr(_T_873) @[lib.scala 104:36] + node _T_875 = and(_T_874, _T_861) @[lib.scala 104:41] + node _T_876 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 104:74] + node _T_877 = bits(lsu_match_data_3, 2, 2) @[lib.scala 104:86] + node _T_878 = eq(_T_876, _T_877) @[lib.scala 104:78] + node _T_879 = mux(_T_875, UInt<1>("h01"), _T_878) @[lib.scala 104:23] + _T_858[2] <= _T_879 @[lib.scala 104:17] + node _T_880 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 104:28] + node _T_881 = andr(_T_880) @[lib.scala 104:36] + node _T_882 = and(_T_881, _T_861) @[lib.scala 104:41] + node _T_883 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 104:74] + node _T_884 = bits(lsu_match_data_3, 3, 3) @[lib.scala 104:86] + node _T_885 = eq(_T_883, _T_884) @[lib.scala 104:78] + node _T_886 = mux(_T_882, UInt<1>("h01"), _T_885) @[lib.scala 104:23] + _T_858[3] <= _T_886 @[lib.scala 104:17] + node _T_887 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 104:28] + node _T_888 = andr(_T_887) @[lib.scala 104:36] + node _T_889 = and(_T_888, _T_861) @[lib.scala 104:41] + node _T_890 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 104:74] + node _T_891 = bits(lsu_match_data_3, 4, 4) @[lib.scala 104:86] + node _T_892 = eq(_T_890, _T_891) @[lib.scala 104:78] + node _T_893 = mux(_T_889, UInt<1>("h01"), _T_892) @[lib.scala 104:23] + _T_858[4] <= _T_893 @[lib.scala 104:17] + node _T_894 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 104:28] + node _T_895 = andr(_T_894) @[lib.scala 104:36] + node _T_896 = and(_T_895, _T_861) @[lib.scala 104:41] + node _T_897 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 104:74] + node _T_898 = bits(lsu_match_data_3, 5, 5) @[lib.scala 104:86] + node _T_899 = eq(_T_897, _T_898) @[lib.scala 104:78] + node _T_900 = mux(_T_896, UInt<1>("h01"), _T_899) @[lib.scala 104:23] + _T_858[5] <= _T_900 @[lib.scala 104:17] + node _T_901 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 104:28] + node _T_902 = andr(_T_901) @[lib.scala 104:36] + node _T_903 = and(_T_902, _T_861) @[lib.scala 104:41] + node _T_904 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 104:74] + node _T_905 = bits(lsu_match_data_3, 6, 6) @[lib.scala 104:86] + node _T_906 = eq(_T_904, _T_905) @[lib.scala 104:78] + node _T_907 = mux(_T_903, UInt<1>("h01"), _T_906) @[lib.scala 104:23] + _T_858[6] <= _T_907 @[lib.scala 104:17] + node _T_908 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 104:28] + node _T_909 = andr(_T_908) @[lib.scala 104:36] + node _T_910 = and(_T_909, _T_861) @[lib.scala 104:41] + node _T_911 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 104:74] + node _T_912 = bits(lsu_match_data_3, 7, 7) @[lib.scala 104:86] + node _T_913 = eq(_T_911, _T_912) @[lib.scala 104:78] + node _T_914 = mux(_T_910, UInt<1>("h01"), _T_913) @[lib.scala 104:23] + _T_858[7] <= _T_914 @[lib.scala 104:17] + node _T_915 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 104:28] + node _T_916 = andr(_T_915) @[lib.scala 104:36] + node _T_917 = and(_T_916, _T_861) @[lib.scala 104:41] + node _T_918 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 104:74] + node _T_919 = bits(lsu_match_data_3, 8, 8) @[lib.scala 104:86] + node _T_920 = eq(_T_918, _T_919) @[lib.scala 104:78] + node _T_921 = mux(_T_917, UInt<1>("h01"), _T_920) @[lib.scala 104:23] + _T_858[8] <= _T_921 @[lib.scala 104:17] + node _T_922 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 104:28] + node _T_923 = andr(_T_922) @[lib.scala 104:36] + node _T_924 = and(_T_923, _T_861) @[lib.scala 104:41] + node _T_925 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 104:74] + node _T_926 = bits(lsu_match_data_3, 9, 9) @[lib.scala 104:86] + node _T_927 = eq(_T_925, _T_926) @[lib.scala 104:78] + node _T_928 = mux(_T_924, UInt<1>("h01"), _T_927) @[lib.scala 104:23] + _T_858[9] <= _T_928 @[lib.scala 104:17] + node _T_929 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 104:28] + node _T_930 = andr(_T_929) @[lib.scala 104:36] + node _T_931 = and(_T_930, _T_861) @[lib.scala 104:41] + node _T_932 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 104:74] + node _T_933 = bits(lsu_match_data_3, 10, 10) @[lib.scala 104:86] + node _T_934 = eq(_T_932, _T_933) @[lib.scala 104:78] + node _T_935 = mux(_T_931, UInt<1>("h01"), _T_934) @[lib.scala 104:23] + _T_858[10] <= _T_935 @[lib.scala 104:17] + node _T_936 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 104:28] + node _T_937 = andr(_T_936) @[lib.scala 104:36] + node _T_938 = and(_T_937, _T_861) @[lib.scala 104:41] + node _T_939 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 104:74] + node _T_940 = bits(lsu_match_data_3, 11, 11) @[lib.scala 104:86] + node _T_941 = eq(_T_939, _T_940) @[lib.scala 104:78] + node _T_942 = mux(_T_938, UInt<1>("h01"), _T_941) @[lib.scala 104:23] + _T_858[11] <= _T_942 @[lib.scala 104:17] + node _T_943 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 104:28] + node _T_944 = andr(_T_943) @[lib.scala 104:36] + node _T_945 = and(_T_944, _T_861) @[lib.scala 104:41] + node _T_946 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 104:74] + node _T_947 = bits(lsu_match_data_3, 12, 12) @[lib.scala 104:86] + node _T_948 = eq(_T_946, _T_947) @[lib.scala 104:78] + node _T_949 = mux(_T_945, UInt<1>("h01"), _T_948) @[lib.scala 104:23] + _T_858[12] <= _T_949 @[lib.scala 104:17] + node _T_950 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 104:28] + node _T_951 = andr(_T_950) @[lib.scala 104:36] + node _T_952 = and(_T_951, _T_861) @[lib.scala 104:41] + node _T_953 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 104:74] + node _T_954 = bits(lsu_match_data_3, 13, 13) @[lib.scala 104:86] + node _T_955 = eq(_T_953, _T_954) @[lib.scala 104:78] + node _T_956 = mux(_T_952, UInt<1>("h01"), _T_955) @[lib.scala 104:23] + _T_858[13] <= _T_956 @[lib.scala 104:17] + node _T_957 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 104:28] + node _T_958 = andr(_T_957) @[lib.scala 104:36] + node _T_959 = and(_T_958, _T_861) @[lib.scala 104:41] + node _T_960 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 104:74] + node _T_961 = bits(lsu_match_data_3, 14, 14) @[lib.scala 104:86] + node _T_962 = eq(_T_960, _T_961) @[lib.scala 104:78] + node _T_963 = mux(_T_959, UInt<1>("h01"), _T_962) @[lib.scala 104:23] + _T_858[14] <= _T_963 @[lib.scala 104:17] + node _T_964 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 104:28] + node _T_965 = andr(_T_964) @[lib.scala 104:36] + node _T_966 = and(_T_965, _T_861) @[lib.scala 104:41] + node _T_967 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 104:74] + node _T_968 = bits(lsu_match_data_3, 15, 15) @[lib.scala 104:86] + node _T_969 = eq(_T_967, _T_968) @[lib.scala 104:78] + node _T_970 = mux(_T_966, UInt<1>("h01"), _T_969) @[lib.scala 104:23] + _T_858[15] <= _T_970 @[lib.scala 104:17] + node _T_971 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 104:28] + node _T_972 = andr(_T_971) @[lib.scala 104:36] + node _T_973 = and(_T_972, _T_861) @[lib.scala 104:41] + node _T_974 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 104:74] + node _T_975 = bits(lsu_match_data_3, 16, 16) @[lib.scala 104:86] + node _T_976 = eq(_T_974, _T_975) @[lib.scala 104:78] + node _T_977 = mux(_T_973, UInt<1>("h01"), _T_976) @[lib.scala 104:23] + _T_858[16] <= _T_977 @[lib.scala 104:17] + node _T_978 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 104:28] + node _T_979 = andr(_T_978) @[lib.scala 104:36] + node _T_980 = and(_T_979, _T_861) @[lib.scala 104:41] + node _T_981 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 104:74] + node _T_982 = bits(lsu_match_data_3, 17, 17) @[lib.scala 104:86] + node _T_983 = eq(_T_981, _T_982) @[lib.scala 104:78] + node _T_984 = mux(_T_980, UInt<1>("h01"), _T_983) @[lib.scala 104:23] + _T_858[17] <= _T_984 @[lib.scala 104:17] + node _T_985 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 104:28] + node _T_986 = andr(_T_985) @[lib.scala 104:36] + node _T_987 = and(_T_986, _T_861) @[lib.scala 104:41] + node _T_988 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 104:74] + node _T_989 = bits(lsu_match_data_3, 18, 18) @[lib.scala 104:86] + node _T_990 = eq(_T_988, _T_989) @[lib.scala 104:78] + node _T_991 = mux(_T_987, UInt<1>("h01"), _T_990) @[lib.scala 104:23] + _T_858[18] <= _T_991 @[lib.scala 104:17] + node _T_992 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 104:28] + node _T_993 = andr(_T_992) @[lib.scala 104:36] + node _T_994 = and(_T_993, _T_861) @[lib.scala 104:41] + node _T_995 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 104:74] + node _T_996 = bits(lsu_match_data_3, 19, 19) @[lib.scala 104:86] + node _T_997 = eq(_T_995, _T_996) @[lib.scala 104:78] + node _T_998 = mux(_T_994, UInt<1>("h01"), _T_997) @[lib.scala 104:23] + _T_858[19] <= _T_998 @[lib.scala 104:17] + node _T_999 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 104:28] + node _T_1000 = andr(_T_999) @[lib.scala 104:36] + node _T_1001 = and(_T_1000, _T_861) @[lib.scala 104:41] + node _T_1002 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 104:74] + node _T_1003 = bits(lsu_match_data_3, 20, 20) @[lib.scala 104:86] + node _T_1004 = eq(_T_1002, _T_1003) @[lib.scala 104:78] + node _T_1005 = mux(_T_1001, UInt<1>("h01"), _T_1004) @[lib.scala 104:23] + _T_858[20] <= _T_1005 @[lib.scala 104:17] + node _T_1006 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 104:28] + node _T_1007 = andr(_T_1006) @[lib.scala 104:36] + node _T_1008 = and(_T_1007, _T_861) @[lib.scala 104:41] + node _T_1009 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 104:74] + node _T_1010 = bits(lsu_match_data_3, 21, 21) @[lib.scala 104:86] + node _T_1011 = eq(_T_1009, _T_1010) @[lib.scala 104:78] + node _T_1012 = mux(_T_1008, UInt<1>("h01"), _T_1011) @[lib.scala 104:23] + _T_858[21] <= _T_1012 @[lib.scala 104:17] + node _T_1013 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 104:28] + node _T_1014 = andr(_T_1013) @[lib.scala 104:36] + node _T_1015 = and(_T_1014, _T_861) @[lib.scala 104:41] + node _T_1016 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 104:74] + node _T_1017 = bits(lsu_match_data_3, 22, 22) @[lib.scala 104:86] + node _T_1018 = eq(_T_1016, _T_1017) @[lib.scala 104:78] + node _T_1019 = mux(_T_1015, UInt<1>("h01"), _T_1018) @[lib.scala 104:23] + _T_858[22] <= _T_1019 @[lib.scala 104:17] + node _T_1020 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 104:28] + node _T_1021 = andr(_T_1020) @[lib.scala 104:36] + node _T_1022 = and(_T_1021, _T_861) @[lib.scala 104:41] + node _T_1023 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 104:74] + node _T_1024 = bits(lsu_match_data_3, 23, 23) @[lib.scala 104:86] + node _T_1025 = eq(_T_1023, _T_1024) @[lib.scala 104:78] + node _T_1026 = mux(_T_1022, UInt<1>("h01"), _T_1025) @[lib.scala 104:23] + _T_858[23] <= _T_1026 @[lib.scala 104:17] + node _T_1027 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 104:28] + node _T_1028 = andr(_T_1027) @[lib.scala 104:36] + node _T_1029 = and(_T_1028, _T_861) @[lib.scala 104:41] + node _T_1030 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 104:74] + node _T_1031 = bits(lsu_match_data_3, 24, 24) @[lib.scala 104:86] + node _T_1032 = eq(_T_1030, _T_1031) @[lib.scala 104:78] + node _T_1033 = mux(_T_1029, UInt<1>("h01"), _T_1032) @[lib.scala 104:23] + _T_858[24] <= _T_1033 @[lib.scala 104:17] + node _T_1034 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 104:28] + node _T_1035 = andr(_T_1034) @[lib.scala 104:36] + node _T_1036 = and(_T_1035, _T_861) @[lib.scala 104:41] + node _T_1037 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 104:74] + node _T_1038 = bits(lsu_match_data_3, 25, 25) @[lib.scala 104:86] + node _T_1039 = eq(_T_1037, _T_1038) @[lib.scala 104:78] + node _T_1040 = mux(_T_1036, UInt<1>("h01"), _T_1039) @[lib.scala 104:23] + _T_858[25] <= _T_1040 @[lib.scala 104:17] + node _T_1041 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 104:28] + node _T_1042 = andr(_T_1041) @[lib.scala 104:36] + node _T_1043 = and(_T_1042, _T_861) @[lib.scala 104:41] + node _T_1044 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 104:74] + node _T_1045 = bits(lsu_match_data_3, 26, 26) @[lib.scala 104:86] + node _T_1046 = eq(_T_1044, _T_1045) @[lib.scala 104:78] + node _T_1047 = mux(_T_1043, UInt<1>("h01"), _T_1046) @[lib.scala 104:23] + _T_858[26] <= _T_1047 @[lib.scala 104:17] + node _T_1048 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 104:28] + node _T_1049 = andr(_T_1048) @[lib.scala 104:36] + node _T_1050 = and(_T_1049, _T_861) @[lib.scala 104:41] + node _T_1051 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 104:74] + node _T_1052 = bits(lsu_match_data_3, 27, 27) @[lib.scala 104:86] + node _T_1053 = eq(_T_1051, _T_1052) @[lib.scala 104:78] + node _T_1054 = mux(_T_1050, UInt<1>("h01"), _T_1053) @[lib.scala 104:23] + _T_858[27] <= _T_1054 @[lib.scala 104:17] + node _T_1055 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 104:28] + node _T_1056 = andr(_T_1055) @[lib.scala 104:36] + node _T_1057 = and(_T_1056, _T_861) @[lib.scala 104:41] + node _T_1058 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 104:74] + node _T_1059 = bits(lsu_match_data_3, 28, 28) @[lib.scala 104:86] + node _T_1060 = eq(_T_1058, _T_1059) @[lib.scala 104:78] + node _T_1061 = mux(_T_1057, UInt<1>("h01"), _T_1060) @[lib.scala 104:23] + _T_858[28] <= _T_1061 @[lib.scala 104:17] + node _T_1062 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 104:28] + node _T_1063 = andr(_T_1062) @[lib.scala 104:36] + node _T_1064 = and(_T_1063, _T_861) @[lib.scala 104:41] + node _T_1065 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 104:74] + node _T_1066 = bits(lsu_match_data_3, 29, 29) @[lib.scala 104:86] + node _T_1067 = eq(_T_1065, _T_1066) @[lib.scala 104:78] + node _T_1068 = mux(_T_1064, UInt<1>("h01"), _T_1067) @[lib.scala 104:23] + _T_858[29] <= _T_1068 @[lib.scala 104:17] + node _T_1069 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 104:28] + node _T_1070 = andr(_T_1069) @[lib.scala 104:36] + node _T_1071 = and(_T_1070, _T_861) @[lib.scala 104:41] + node _T_1072 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 104:74] + node _T_1073 = bits(lsu_match_data_3, 30, 30) @[lib.scala 104:86] + node _T_1074 = eq(_T_1072, _T_1073) @[lib.scala 104:78] + node _T_1075 = mux(_T_1071, UInt<1>("h01"), _T_1074) @[lib.scala 104:23] + _T_858[30] <= _T_1075 @[lib.scala 104:17] + node _T_1076 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 104:28] + node _T_1077 = andr(_T_1076) @[lib.scala 104:36] + node _T_1078 = and(_T_1077, _T_861) @[lib.scala 104:41] + node _T_1079 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 104:74] + node _T_1080 = bits(lsu_match_data_3, 31, 31) @[lib.scala 104:86] + node _T_1081 = eq(_T_1079, _T_1080) @[lib.scala 104:78] + node _T_1082 = mux(_T_1078, UInt<1>("h01"), _T_1081) @[lib.scala 104:23] + _T_858[31] <= _T_1082 @[lib.scala 104:17] + node _T_1083 = cat(_T_858[1], _T_858[0]) @[lib.scala 105:14] + node _T_1084 = cat(_T_858[3], _T_858[2]) @[lib.scala 105:14] + node _T_1085 = cat(_T_1084, _T_1083) @[lib.scala 105:14] + node _T_1086 = cat(_T_858[5], _T_858[4]) @[lib.scala 105:14] + node _T_1087 = cat(_T_858[7], _T_858[6]) @[lib.scala 105:14] + node _T_1088 = cat(_T_1087, _T_1086) @[lib.scala 105:14] + node _T_1089 = cat(_T_1088, _T_1085) @[lib.scala 105:14] + node _T_1090 = cat(_T_858[9], _T_858[8]) @[lib.scala 105:14] + node _T_1091 = cat(_T_858[11], _T_858[10]) @[lib.scala 105:14] + node _T_1092 = cat(_T_1091, _T_1090) @[lib.scala 105:14] + node _T_1093 = cat(_T_858[13], _T_858[12]) @[lib.scala 105:14] + node _T_1094 = cat(_T_858[15], _T_858[14]) @[lib.scala 105:14] + node _T_1095 = cat(_T_1094, _T_1093) @[lib.scala 105:14] + node _T_1096 = cat(_T_1095, _T_1092) @[lib.scala 105:14] + node _T_1097 = cat(_T_1096, _T_1089) @[lib.scala 105:14] + node _T_1098 = cat(_T_858[17], _T_858[16]) @[lib.scala 105:14] + node _T_1099 = cat(_T_858[19], _T_858[18]) @[lib.scala 105:14] + node _T_1100 = cat(_T_1099, _T_1098) @[lib.scala 105:14] + node _T_1101 = cat(_T_858[21], _T_858[20]) @[lib.scala 105:14] + node _T_1102 = cat(_T_858[23], _T_858[22]) @[lib.scala 105:14] + node _T_1103 = cat(_T_1102, _T_1101) @[lib.scala 105:14] + node _T_1104 = cat(_T_1103, _T_1100) @[lib.scala 105:14] + node _T_1105 = cat(_T_858[25], _T_858[24]) @[lib.scala 105:14] + node _T_1106 = cat(_T_858[27], _T_858[26]) @[lib.scala 105:14] + node _T_1107 = cat(_T_1106, _T_1105) @[lib.scala 105:14] + node _T_1108 = cat(_T_858[29], _T_858[28]) @[lib.scala 105:14] + node _T_1109 = cat(_T_858[31], _T_858[30]) @[lib.scala 105:14] + node _T_1110 = cat(_T_1109, _T_1108) @[lib.scala 105:14] + node _T_1111 = cat(_T_1110, _T_1107) @[lib.scala 105:14] + node _T_1112 = cat(_T_1111, _T_1104) @[lib.scala 105:14] + node _T_1113 = cat(_T_1112, _T_1097) @[lib.scala 105:14] + node _T_1114 = andr(_T_1113) @[lib.scala 105:25] + node _T_1115 = and(_T_856, _T_1114) @[lsu_trigger.scala 21:92] + node _T_1116 = cat(_T_1115, _T_847) @[Cat.scala 29:58] + node _T_1117 = cat(_T_1116, _T_579) @[Cat.scala 29:58] + node _T_1118 = cat(_T_1117, _T_311) @[Cat.scala 29:58] + io.lsu_trigger_match_m <= _T_1118 @[lsu_trigger.scala 20:25] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_clkdomain : + input clock : Clock + input reset : AsyncReset + output io : {flip active_clk : Clock, flip clk_override : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_bus_obuf_c1_clken : UInt<1>, lsu_busm_clken : UInt<1>, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>} + + wire lsu_c1_m_clken_q : UInt<1> @[lsu_clkdomain.scala 60:36] + wire lsu_c1_r_clken_q : UInt<1> @[lsu_clkdomain.scala 61:36] + wire lsu_free_c1_clken_q : UInt<1> @[lsu_clkdomain.scala 62:36] + node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[lsu_clkdomain.scala 64:47] + node lsu_c1_m_clken = or(_T, io.clk_override) @[lsu_clkdomain.scala 64:65] + node _T_1 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 65:51] + node lsu_c1_r_clken = or(_T_1, io.clk_override) @[lsu_clkdomain.scala 65:70] + node _T_2 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 67:47] + node lsu_c2_m_clken = or(_T_2, io.clk_override) @[lsu_clkdomain.scala 67:66] + node _T_3 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[lsu_clkdomain.scala 68:47] + node lsu_c2_r_clken = or(_T_3, io.clk_override) @[lsu_clkdomain.scala 68:66] + node _T_4 = and(lsu_c1_m_clken, io.lsu_pkt_d.bits.store) @[lsu_clkdomain.scala 70:49] + node lsu_store_c1_m_clken = or(_T_4, io.clk_override) @[lsu_clkdomain.scala 70:76] + node _T_5 = and(lsu_c1_r_clken, io.lsu_pkt_m.bits.store) @[lsu_clkdomain.scala 71:49] + node lsu_store_c1_r_clken = or(_T_5, io.clk_override) @[lsu_clkdomain.scala 71:76] + node _T_6 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[lsu_clkdomain.scala 72:55] + node _T_7 = or(_T_6, io.stbuf_reqvld_flushed_any) @[lsu_clkdomain.scala 72:77] + node lsu_stbuf_c1_clken = or(_T_7, io.clk_override) @[lsu_clkdomain.scala 72:107] + node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[lsu_clkdomain.scala 73:49] + node _T_8 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[lsu_clkdomain.scala 74:62] + node _T_9 = or(_T_8, io.clk_override) @[lsu_clkdomain.scala 74:80] + node _T_10 = and(_T_9, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 74:99] + io.lsu_bus_obuf_c1_clken <= _T_10 @[lsu_clkdomain.scala 74:30] + node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 75:32] + node _T_12 = or(_T_11, io.lsu_busreq_r) @[lsu_clkdomain.scala 75:61] + node _T_13 = or(_T_12, io.dec_tlu_force_halt) @[lsu_clkdomain.scala 75:79] + node lsu_bus_buf_c1_clken = or(_T_13, io.clk_override) @[lsu_clkdomain.scala 75:103] + node _T_14 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[lsu_clkdomain.scala 77:48] + node _T_15 = or(_T_14, io.lsu_pkt_m.valid) @[lsu_clkdomain.scala 77:69] + node _T_16 = or(_T_15, io.lsu_pkt_r.valid) @[lsu_clkdomain.scala 77:90] + node _T_17 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:114] + node _T_18 = or(_T_16, _T_17) @[lsu_clkdomain.scala 77:112] + node _T_19 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:145] + node _T_20 = or(_T_18, _T_19) @[lsu_clkdomain.scala 77:143] + node lsu_free_c1_clken = or(_T_20, io.clk_override) @[lsu_clkdomain.scala 77:169] + node _T_21 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[lsu_clkdomain.scala 78:50] + node lsu_free_c2_clken = or(_T_21, io.clk_override) @[lsu_clkdomain.scala 78:72] + node _T_22 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 79:25] + node _T_23 = or(_T_22, io.lsu_busreq_r) @[lsu_clkdomain.scala 79:54] + node _T_24 = or(_T_23, io.clk_override) @[lsu_clkdomain.scala 79:72] + node _T_25 = and(_T_24, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 79:91] + io.lsu_busm_clken <= _T_25 @[lsu_clkdomain.scala 79:21] + reg _T_26 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 82:62] + _T_26 <= lsu_free_c1_clken @[lsu_clkdomain.scala 82:62] + lsu_free_c1_clken_q <= _T_26 @[lsu_clkdomain.scala 82:26] + reg _T_27 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 84:67] + _T_27 <= lsu_c1_m_clken @[lsu_clkdomain.scala 84:67] + lsu_c1_m_clken_q <= _T_27 @[lsu_clkdomain.scala 84:26] + reg _T_28 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 85:67] + _T_28 <= lsu_c1_r_clken @[lsu_clkdomain.scala 85:67] + lsu_c1_r_clken_q <= _T_28 @[lsu_clkdomain.scala 85:26] + node _T_29 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 87:60] + io.lsu_c1_m_clk <= clock @[lsu_clkdomain.scala 87:26] + node _T_30 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 88:60] + io.lsu_c1_r_clk <= clock @[lsu_clkdomain.scala 88:26] + node _T_31 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 89:60] + io.lsu_c2_m_clk <= clock @[lsu_clkdomain.scala 89:26] + node _T_32 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 90:60] + io.lsu_c2_r_clk <= clock @[lsu_clkdomain.scala 90:26] + node _T_33 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 91:66] + io.lsu_store_c1_m_clk <= clock @[lsu_clkdomain.scala 91:26] + node _T_34 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 92:66] + io.lsu_store_c1_r_clk <= clock @[lsu_clkdomain.scala 92:26] + node _T_35 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:64] + io.lsu_stbuf_c1_clk <= clock @[lsu_clkdomain.scala 93:26] + node _T_36 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:67] + io.lsu_bus_ibuf_c1_clk <= clock @[lsu_clkdomain.scala 94:26] + node _T_37 = bits(io.lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 95:69] + inst rvclkhdr of rvclkhdr_20 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= _T_37 @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] + io.lsu_bus_obuf_c1_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 95:26] + node _T_38 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 96:66] + io.lsu_bus_buf_c1_clk <= clock @[lsu_clkdomain.scala 96:26] + node _T_39 = bits(io.lsu_busm_clken, 0, 0) @[lsu_clkdomain.scala 97:62] + inst rvclkhdr_1 of rvclkhdr_21 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_39 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] + io.lsu_busm_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 97:26] + node _T_40 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 98:63] + io.lsu_free_c2_clk <= clock @[lsu_clkdomain.scala 98:26] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_27 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_28 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_29 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_30 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_31 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_31 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_31 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_32 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_32 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_32 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_33 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_33 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_33 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_bus_buffer : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_nonblock_load_data : UInt<32>} + + wire buf_addr : UInt<32>[4] @[lsu_bus_buffer.scala 71:22] + wire buf_state : UInt<3>[4] @[lsu_bus_buffer.scala 72:23] + wire buf_write : UInt<4> + buf_write <= UInt<1>("h00") + wire CmdPtr0 : UInt<2> + CmdPtr0 <= UInt<1>("h00") + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[lsu_bus_buffer.scala 77:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[lsu_bus_buffer.scala 78:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_2 = eq(_T, _T_1) @[lsu_bus_buffer.scala 80:74] + node _T_3 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 80:109] + node _T_4 = and(_T_2, _T_3) @[lsu_bus_buffer.scala 80:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_6 = and(_T_4, _T_5) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_9 = eq(_T_7, _T_8) @[lsu_bus_buffer.scala 80:74] + node _T_10 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 80:109] + node _T_11 = and(_T_9, _T_10) @[lsu_bus_buffer.scala 80:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_13 = and(_T_11, _T_12) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_16 = eq(_T_14, _T_15) @[lsu_bus_buffer.scala 80:74] + node _T_17 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 80:109] + node _T_18 = and(_T_16, _T_17) @[lsu_bus_buffer.scala 80:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_20 = and(_T_18, _T_19) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_23 = eq(_T_21, _T_22) @[lsu_bus_buffer.scala 80:74] + node _T_24 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 80:109] + node _T_25 = and(_T_23, _T_24) @[lsu_bus_buffer.scala 80:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_27 = and(_T_25, _T_26) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_30 = eq(_T_28, _T_29) @[lsu_bus_buffer.scala 81:74] + node _T_31 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 81:109] + node _T_32 = and(_T_30, _T_31) @[lsu_bus_buffer.scala 81:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_34 = and(_T_32, _T_33) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_37 = eq(_T_35, _T_36) @[lsu_bus_buffer.scala 81:74] + node _T_38 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 81:109] + node _T_39 = and(_T_37, _T_38) @[lsu_bus_buffer.scala 81:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_41 = and(_T_39, _T_40) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_44 = eq(_T_42, _T_43) @[lsu_bus_buffer.scala 81:74] + node _T_45 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 81:109] + node _T_46 = and(_T_44, _T_45) @[lsu_bus_buffer.scala 81:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_48 = and(_T_46, _T_47) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_51 = eq(_T_49, _T_50) @[lsu_bus_buffer.scala 81:74] + node _T_52 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 81:109] + node _T_53 = and(_T_51, _T_52) @[lsu_bus_buffer.scala 81:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_55 = and(_T_53, _T_54) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[lsu_bus_buffer.scala 82:33] + wire ld_byte_ibuf_hit_lo : UInt<4> + ld_byte_ibuf_hit_lo <= UInt<1>("h00") + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[lsu_bus_buffer.scala 84:33] + wire ld_byte_ibuf_hit_hi : UInt<4> + ld_byte_ibuf_hit_hi <= UInt<1>("h00") + wire buf_byteen : UInt<4>[4] @[lsu_bus_buffer.scala 86:24] + buf_byteen[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + wire buf_nxtstate : UInt<3>[4] @[lsu_bus_buffer.scala 88:26] + buf_nxtstate[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + wire buf_wr_en : UInt<1>[4] @[lsu_bus_buffer.scala 90:23] + buf_wr_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + wire buf_data_en : UInt<1>[4] @[lsu_bus_buffer.scala 92:25] + buf_data_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + wire buf_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 94:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + wire buf_ldfwd_in : UInt<1>[4] @[lsu_bus_buffer.scala 96:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + wire buf_ldfwd_en : UInt<1>[4] @[lsu_bus_buffer.scala 98:26] + buf_ldfwd_en[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + wire buf_data_in : UInt<32>[4] @[lsu_bus_buffer.scala 100:25] + buf_data_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 102:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + wire buf_error_en : UInt<1>[4] @[lsu_bus_buffer.scala 104:26] + buf_error_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + wire bus_rsp_read_error : UInt<1> + bus_rsp_read_error <= UInt<1>("h00") + wire bus_rsp_rdata : UInt<64> + bus_rsp_rdata <= UInt<1>("h00") + wire bus_rsp_write_error : UInt<1> + bus_rsp_write_error <= UInt<1>("h00") + wire buf_dualtag : UInt<2>[4] @[lsu_bus_buffer.scala 109:25] + buf_dualtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + wire buf_ldfwd : UInt<4> + buf_ldfwd <= UInt<1>("h00") + wire buf_resp_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 112:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + wire any_done_wait_state : UInt<1> + any_done_wait_state <= UInt<1>("h00") + wire bus_rsp_write : UInt<1> + bus_rsp_write <= UInt<1>("h00") + wire bus_rsp_write_tag : UInt<3> + bus_rsp_write_tag <= UInt<1>("h00") + wire buf_ldfwdtag : UInt<2>[4] @[lsu_bus_buffer.scala 117:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + wire buf_rst : UInt<1>[4] @[lsu_bus_buffer.scala 119:21] + buf_rst[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + wire ibuf_drainvec_vld : UInt<4> + ibuf_drainvec_vld <= UInt<1>("h00") + wire buf_byteen_in : UInt<4>[4] @[lsu_bus_buffer.scala 122:27] + buf_byteen_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + wire buf_addr_in : UInt<32>[4] @[lsu_bus_buffer.scala 124:25] + buf_addr_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + wire buf_dual_in : UInt<4> + buf_dual_in <= UInt<1>("h00") + wire buf_samedw_in : UInt<4> + buf_samedw_in <= UInt<1>("h00") + wire buf_nomerge_in : UInt<4> + buf_nomerge_in <= UInt<1>("h00") + wire buf_dualhi_in : UInt<4> + buf_dualhi_in <= UInt<1>("h00") + wire buf_dualtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 130:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + wire buf_sideeffect_in : UInt<4> + buf_sideeffect_in <= UInt<1>("h00") + wire buf_unsign_in : UInt<4> + buf_unsign_in <= UInt<1>("h00") + wire buf_sz_in : UInt<2>[4] @[lsu_bus_buffer.scala 134:23] + buf_sz_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + wire buf_write_in : UInt<4> + buf_write_in <= UInt<1>("h00") + wire buf_unsign : UInt<4> + buf_unsign <= UInt<1>("h00") + wire buf_error : UInt<4> + buf_error <= UInt<1>("h00") + wire CmdPtr1 : UInt<2> + CmdPtr1 <= UInt<1>("h00") + wire ibuf_data : UInt<32> + ibuf_data <= UInt<1>("h00") + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[lsu_bus_buffer.scala 142:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 142:98] + node _T_58 = or(_T_56, _T_57) @[lsu_bus_buffer.scala 142:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[lsu_bus_buffer.scala 142:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 142:98] + node _T_61 = or(_T_59, _T_60) @[lsu_bus_buffer.scala 142:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[lsu_bus_buffer.scala 142:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 142:98] + node _T_64 = or(_T_62, _T_63) @[lsu_bus_buffer.scala 142:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[lsu_bus_buffer.scala 142:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 142:98] + node _T_67 = or(_T_65, _T_66) @[lsu_bus_buffer.scala 142:77] + node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] + io.ld_byte_hit_buf_lo <= _T_70 @[lsu_bus_buffer.scala 142:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[lsu_bus_buffer.scala 143:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 143:98] + node _T_73 = or(_T_71, _T_72) @[lsu_bus_buffer.scala 143:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[lsu_bus_buffer.scala 143:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 143:98] + node _T_76 = or(_T_74, _T_75) @[lsu_bus_buffer.scala 143:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[lsu_bus_buffer.scala 143:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 143:98] + node _T_79 = or(_T_77, _T_78) @[lsu_bus_buffer.scala 143:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[lsu_bus_buffer.scala 143:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 143:98] + node _T_82 = or(_T_80, _T_81) @[lsu_bus_buffer.scala 143:77] + node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] + io.ld_byte_hit_buf_hi <= _T_85 @[lsu_bus_buffer.scala 143:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[lsu_bus_buffer.scala 145:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_89 = and(_T_87, _T_88) @[lsu_bus_buffer.scala 145:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[lsu_bus_buffer.scala 145:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_93 = and(_T_91, _T_92) @[lsu_bus_buffer.scala 145:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[lsu_bus_buffer.scala 145:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_97 = and(_T_95, _T_96) @[lsu_bus_buffer.scala 145:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[lsu_bus_buffer.scala 145:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_101 = and(_T_99, _T_100) @[lsu_bus_buffer.scala 145:114] + node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] + node _T_104 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[lsu_bus_buffer.scala 145:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_107 = and(_T_105, _T_106) @[lsu_bus_buffer.scala 145:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[lsu_bus_buffer.scala 145:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_111 = and(_T_109, _T_110) @[lsu_bus_buffer.scala 145:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[lsu_bus_buffer.scala 145:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_115 = and(_T_113, _T_114) @[lsu_bus_buffer.scala 145:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[lsu_bus_buffer.scala 145:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_119 = and(_T_117, _T_118) @[lsu_bus_buffer.scala 145:114] + node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] + node _T_122 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[lsu_bus_buffer.scala 145:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_125 = and(_T_123, _T_124) @[lsu_bus_buffer.scala 145:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[lsu_bus_buffer.scala 145:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_buffer.scala 145:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[lsu_bus_buffer.scala 145:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_buffer.scala 145:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[lsu_bus_buffer.scala 145:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_buffer.scala 145:114] + node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] + node _T_140 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[lsu_bus_buffer.scala 145:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_143 = and(_T_141, _T_142) @[lsu_bus_buffer.scala 145:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[lsu_bus_buffer.scala 145:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_147 = and(_T_145, _T_146) @[lsu_bus_buffer.scala 145:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[lsu_bus_buffer.scala 145:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_151 = and(_T_149, _T_150) @[lsu_bus_buffer.scala 145:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[lsu_bus_buffer.scala 145:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_155 = and(_T_153, _T_154) @[lsu_bus_buffer.scala 145:114] + node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] + node _T_158 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[lsu_bus_buffer.scala 146:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_161 = and(_T_159, _T_160) @[lsu_bus_buffer.scala 146:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[lsu_bus_buffer.scala 146:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_165 = and(_T_163, _T_164) @[lsu_bus_buffer.scala 146:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[lsu_bus_buffer.scala 146:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_169 = and(_T_167, _T_168) @[lsu_bus_buffer.scala 146:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[lsu_bus_buffer.scala 146:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_173 = and(_T_171, _T_172) @[lsu_bus_buffer.scala 146:114] + node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] + node _T_176 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[lsu_bus_buffer.scala 146:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_179 = and(_T_177, _T_178) @[lsu_bus_buffer.scala 146:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[lsu_bus_buffer.scala 146:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_183 = and(_T_181, _T_182) @[lsu_bus_buffer.scala 146:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[lsu_bus_buffer.scala 146:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_187 = and(_T_185, _T_186) @[lsu_bus_buffer.scala 146:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[lsu_bus_buffer.scala 146:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_191 = and(_T_189, _T_190) @[lsu_bus_buffer.scala 146:114] + node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] + node _T_194 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[lsu_bus_buffer.scala 146:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_197 = and(_T_195, _T_196) @[lsu_bus_buffer.scala 146:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[lsu_bus_buffer.scala 146:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_201 = and(_T_199, _T_200) @[lsu_bus_buffer.scala 146:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[lsu_bus_buffer.scala 146:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_205 = and(_T_203, _T_204) @[lsu_bus_buffer.scala 146:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[lsu_bus_buffer.scala 146:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_209 = and(_T_207, _T_208) @[lsu_bus_buffer.scala 146:114] + node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] + node _T_212 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[lsu_bus_buffer.scala 146:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_215 = and(_T_213, _T_214) @[lsu_bus_buffer.scala 146:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[lsu_bus_buffer.scala 146:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_219 = and(_T_217, _T_218) @[lsu_bus_buffer.scala 146:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[lsu_bus_buffer.scala 146:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_223 = and(_T_221, _T_222) @[lsu_bus_buffer.scala 146:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[lsu_bus_buffer.scala 146:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_227 = and(_T_225, _T_226) @[lsu_bus_buffer.scala 146:114] + node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] + node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] + wire buf_age_younger : UInt<4>[4] @[lsu_bus_buffer.scala 148:29] + buf_age_younger[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_232 = orr(_T_231) @[lsu_bus_buffer.scala 150:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_234 = and(_T_230, _T_233) @[lsu_bus_buffer.scala 150:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_237 = and(_T_234, _T_236) @[lsu_bus_buffer.scala 150:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_240 = orr(_T_239) @[lsu_bus_buffer.scala 150:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_242 = and(_T_238, _T_241) @[lsu_bus_buffer.scala 150:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_245 = and(_T_242, _T_244) @[lsu_bus_buffer.scala 150:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_248 = orr(_T_247) @[lsu_bus_buffer.scala 150:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_250 = and(_T_246, _T_249) @[lsu_bus_buffer.scala 150:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_253 = and(_T_250, _T_252) @[lsu_bus_buffer.scala 150:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_256 = orr(_T_255) @[lsu_bus_buffer.scala 150:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_258 = and(_T_254, _T_257) @[lsu_bus_buffer.scala 150:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_261 = and(_T_258, _T_260) @[lsu_bus_buffer.scala 150:148] + node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] + node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] + node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_267 = orr(_T_266) @[lsu_bus_buffer.scala 150:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_269 = and(_T_265, _T_268) @[lsu_bus_buffer.scala 150:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_272 = and(_T_269, _T_271) @[lsu_bus_buffer.scala 150:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_275 = orr(_T_274) @[lsu_bus_buffer.scala 150:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_277 = and(_T_273, _T_276) @[lsu_bus_buffer.scala 150:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_280 = and(_T_277, _T_279) @[lsu_bus_buffer.scala 150:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_283 = orr(_T_282) @[lsu_bus_buffer.scala 150:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_285 = and(_T_281, _T_284) @[lsu_bus_buffer.scala 150:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_288 = and(_T_285, _T_287) @[lsu_bus_buffer.scala 150:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_291 = orr(_T_290) @[lsu_bus_buffer.scala 150:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_293 = and(_T_289, _T_292) @[lsu_bus_buffer.scala 150:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_296 = and(_T_293, _T_295) @[lsu_bus_buffer.scala 150:148] + node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_302 = orr(_T_301) @[lsu_bus_buffer.scala 150:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_304 = and(_T_300, _T_303) @[lsu_bus_buffer.scala 150:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_307 = and(_T_304, _T_306) @[lsu_bus_buffer.scala 150:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_310 = orr(_T_309) @[lsu_bus_buffer.scala 150:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_312 = and(_T_308, _T_311) @[lsu_bus_buffer.scala 150:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_315 = and(_T_312, _T_314) @[lsu_bus_buffer.scala 150:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_318 = orr(_T_317) @[lsu_bus_buffer.scala 150:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_320 = and(_T_316, _T_319) @[lsu_bus_buffer.scala 150:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_323 = and(_T_320, _T_322) @[lsu_bus_buffer.scala 150:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_326 = orr(_T_325) @[lsu_bus_buffer.scala 150:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_328 = and(_T_324, _T_327) @[lsu_bus_buffer.scala 150:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_331 = and(_T_328, _T_330) @[lsu_bus_buffer.scala 150:148] + node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] + node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] + node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_337 = orr(_T_336) @[lsu_bus_buffer.scala 150:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_339 = and(_T_335, _T_338) @[lsu_bus_buffer.scala 150:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_342 = and(_T_339, _T_341) @[lsu_bus_buffer.scala 150:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_345 = orr(_T_344) @[lsu_bus_buffer.scala 150:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_347 = and(_T_343, _T_346) @[lsu_bus_buffer.scala 150:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_350 = and(_T_347, _T_349) @[lsu_bus_buffer.scala 150:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_353 = orr(_T_352) @[lsu_bus_buffer.scala 150:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_355 = and(_T_351, _T_354) @[lsu_bus_buffer.scala 150:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_358 = and(_T_355, _T_357) @[lsu_bus_buffer.scala 150:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_361 = orr(_T_360) @[lsu_bus_buffer.scala 150:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_363 = and(_T_359, _T_362) @[lsu_bus_buffer.scala 150:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_366 = and(_T_363, _T_365) @[lsu_bus_buffer.scala 150:148] + node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] + ld_byte_hitvecfn_lo[0] <= _T_264 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[lsu_bus_buffer.scala 150:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_372 = orr(_T_371) @[lsu_bus_buffer.scala 151:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_374 = and(_T_370, _T_373) @[lsu_bus_buffer.scala 151:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_377 = and(_T_374, _T_376) @[lsu_bus_buffer.scala 151:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_380 = orr(_T_379) @[lsu_bus_buffer.scala 151:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_382 = and(_T_378, _T_381) @[lsu_bus_buffer.scala 151:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_385 = and(_T_382, _T_384) @[lsu_bus_buffer.scala 151:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_388 = orr(_T_387) @[lsu_bus_buffer.scala 151:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_390 = and(_T_386, _T_389) @[lsu_bus_buffer.scala 151:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_393 = and(_T_390, _T_392) @[lsu_bus_buffer.scala 151:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_396 = orr(_T_395) @[lsu_bus_buffer.scala 151:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_398 = and(_T_394, _T_397) @[lsu_bus_buffer.scala 151:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_401 = and(_T_398, _T_400) @[lsu_bus_buffer.scala 151:148] + node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_407 = orr(_T_406) @[lsu_bus_buffer.scala 151:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_409 = and(_T_405, _T_408) @[lsu_bus_buffer.scala 151:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_412 = and(_T_409, _T_411) @[lsu_bus_buffer.scala 151:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_415 = orr(_T_414) @[lsu_bus_buffer.scala 151:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_417 = and(_T_413, _T_416) @[lsu_bus_buffer.scala 151:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_420 = and(_T_417, _T_419) @[lsu_bus_buffer.scala 151:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_423 = orr(_T_422) @[lsu_bus_buffer.scala 151:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_425 = and(_T_421, _T_424) @[lsu_bus_buffer.scala 151:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_428 = and(_T_425, _T_427) @[lsu_bus_buffer.scala 151:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_431 = orr(_T_430) @[lsu_bus_buffer.scala 151:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_433 = and(_T_429, _T_432) @[lsu_bus_buffer.scala 151:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_436 = and(_T_433, _T_435) @[lsu_bus_buffer.scala 151:148] + node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] + node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_442 = orr(_T_441) @[lsu_bus_buffer.scala 151:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_444 = and(_T_440, _T_443) @[lsu_bus_buffer.scala 151:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_447 = and(_T_444, _T_446) @[lsu_bus_buffer.scala 151:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_450 = orr(_T_449) @[lsu_bus_buffer.scala 151:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_452 = and(_T_448, _T_451) @[lsu_bus_buffer.scala 151:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_455 = and(_T_452, _T_454) @[lsu_bus_buffer.scala 151:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_458 = orr(_T_457) @[lsu_bus_buffer.scala 151:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_460 = and(_T_456, _T_459) @[lsu_bus_buffer.scala 151:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_463 = and(_T_460, _T_462) @[lsu_bus_buffer.scala 151:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_466 = orr(_T_465) @[lsu_bus_buffer.scala 151:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_468 = and(_T_464, _T_467) @[lsu_bus_buffer.scala 151:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_471 = and(_T_468, _T_470) @[lsu_bus_buffer.scala 151:148] + node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_477 = orr(_T_476) @[lsu_bus_buffer.scala 151:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_479 = and(_T_475, _T_478) @[lsu_bus_buffer.scala 151:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_482 = and(_T_479, _T_481) @[lsu_bus_buffer.scala 151:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_485 = orr(_T_484) @[lsu_bus_buffer.scala 151:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_487 = and(_T_483, _T_486) @[lsu_bus_buffer.scala 151:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_490 = and(_T_487, _T_489) @[lsu_bus_buffer.scala 151:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_493 = orr(_T_492) @[lsu_bus_buffer.scala 151:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_495 = and(_T_491, _T_494) @[lsu_bus_buffer.scala 151:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_498 = and(_T_495, _T_497) @[lsu_bus_buffer.scala 151:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_501 = orr(_T_500) @[lsu_bus_buffer.scala 151:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_503 = and(_T_499, _T_502) @[lsu_bus_buffer.scala 151:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_506 = and(_T_503, _T_505) @[lsu_bus_buffer.scala 151:148] + node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] + node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] + ld_byte_hitvecfn_hi[0] <= _T_404 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[lsu_bus_buffer.scala 151:23] + wire ibuf_addr : UInt<32> + ibuf_addr <= UInt<1>("h00") + wire ibuf_write : UInt<1> + ibuf_write <= UInt<1>("h00") + wire ibuf_valid : UInt<1> + ibuf_valid <= UInt<1>("h00") + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 156:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 156:64] + node _T_512 = eq(_T_510, _T_511) @[lsu_bus_buffer.scala 156:51] + node _T_513 = and(_T_512, ibuf_write) @[lsu_bus_buffer.scala 156:73] + node _T_514 = and(_T_513, ibuf_valid) @[lsu_bus_buffer.scala 156:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[lsu_bus_buffer.scala 156:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 157:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 157:64] + node _T_517 = eq(_T_515, _T_516) @[lsu_bus_buffer.scala 157:51] + node _T_518 = and(_T_517, ibuf_write) @[lsu_bus_buffer.scala 157:73] + node _T_519 = and(_T_518, ibuf_valid) @[lsu_bus_buffer.scala 157:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[lsu_bus_buffer.scala 157:99] + wire ibuf_byteen : UInt<4> + ibuf_byteen <= UInt<1>("h00") + node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] + node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_522 = and(_T_521, ibuf_byteen) @[lsu_bus_buffer.scala 161:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[lsu_bus_buffer.scala 161:69] + ld_byte_ibuf_hit_lo <= _T_523 @[lsu_bus_buffer.scala 161:23] + node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(_T_525, ibuf_byteen) @[lsu_bus_buffer.scala 162:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[lsu_bus_buffer.scala 162:69] + ld_byte_ibuf_hit_hi <= _T_527 @[lsu_bus_buffer.scala 162:23] + wire buf_data : UInt<32>[4] @[lsu_bus_buffer.scala 164:22] + buf_data[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + wire fwd_data : UInt<32> + fwd_data <= UInt<1>("h00") + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 167:81] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 167:81] + node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] + node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 167:81] + node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] + node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 167:81] + node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] + node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] + node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] + node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 168:81] + node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 168:81] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 168:81] + node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] + node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 168:81] + node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] + node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] + node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[lsu_bus_buffer.scala 169:86] + node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] + node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_559 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_560 = and(_T_558, _T_559) @[lsu_bus_buffer.scala 169:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[lsu_bus_buffer.scala 169:86] + node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] + node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_564 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_565 = and(_T_563, _T_564) @[lsu_bus_buffer.scala 169:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[lsu_bus_buffer.scala 169:86] + node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_569 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_570 = and(_T_568, _T_569) @[lsu_bus_buffer.scala 169:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[lsu_bus_buffer.scala 169:86] + node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] + node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_574 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_575 = and(_T_573, _T_574) @[lsu_bus_buffer.scala 169:91] + node _T_576 = or(_T_560, _T_565) @[lsu_bus_buffer.scala 169:123] + node _T_577 = or(_T_576, _T_570) @[lsu_bus_buffer.scala 169:123] + node _T_578 = or(_T_577, _T_575) @[lsu_bus_buffer.scala 169:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[lsu_bus_buffer.scala 170:60] + node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_583 = and(_T_581, _T_582) @[lsu_bus_buffer.scala 170:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[lsu_bus_buffer.scala 170:60] + node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] + node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_587 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_588 = and(_T_586, _T_587) @[lsu_bus_buffer.scala 170:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[lsu_bus_buffer.scala 170:60] + node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] + node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_592 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_593 = and(_T_591, _T_592) @[lsu_bus_buffer.scala 170:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[lsu_bus_buffer.scala 170:60] + node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] + node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_597 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_598 = and(_T_596, _T_597) @[lsu_bus_buffer.scala 170:65] + node _T_599 = or(_T_583, _T_588) @[lsu_bus_buffer.scala 170:97] + node _T_600 = or(_T_599, _T_593) @[lsu_bus_buffer.scala 170:97] + node _T_601 = or(_T_600, _T_598) @[lsu_bus_buffer.scala 170:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[lsu_bus_buffer.scala 171:60] + node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] + node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_605 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_606 = and(_T_604, _T_605) @[lsu_bus_buffer.scala 171:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[lsu_bus_buffer.scala 171:60] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_611 = and(_T_609, _T_610) @[lsu_bus_buffer.scala 171:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[lsu_bus_buffer.scala 171:60] + node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] + node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_615 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_616 = and(_T_614, _T_615) @[lsu_bus_buffer.scala 171:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[lsu_bus_buffer.scala 171:60] + node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_620 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_621 = and(_T_619, _T_620) @[lsu_bus_buffer.scala 171:65] + node _T_622 = or(_T_606, _T_611) @[lsu_bus_buffer.scala 171:97] + node _T_623 = or(_T_622, _T_616) @[lsu_bus_buffer.scala 171:97] + node _T_624 = or(_T_623, _T_621) @[lsu_bus_buffer.scala 171:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[lsu_bus_buffer.scala 172:60] + node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_629 = and(_T_627, _T_628) @[lsu_bus_buffer.scala 172:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[lsu_bus_buffer.scala 172:60] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_634 = and(_T_632, _T_633) @[lsu_bus_buffer.scala 172:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[lsu_bus_buffer.scala 172:60] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_639 = and(_T_637, _T_638) @[lsu_bus_buffer.scala 172:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[lsu_bus_buffer.scala 172:60] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_643 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_644 = and(_T_642, _T_643) @[lsu_bus_buffer.scala 172:65] + node _T_645 = or(_T_629, _T_634) @[lsu_bus_buffer.scala 172:97] + node _T_646 = or(_T_645, _T_639) @[lsu_bus_buffer.scala 172:97] + node _T_647 = or(_T_646, _T_644) @[lsu_bus_buffer.scala 172:97] + node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] + node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[lsu_bus_buffer.scala 173:32] + node _T_652 = or(_T_650, _T_651) @[lsu_bus_buffer.scala 172:103] + io.ld_fwddata_buf_lo <= _T_652 @[lsu_bus_buffer.scala 169:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[lsu_bus_buffer.scala 175:86] + node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] + node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_656 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_657 = and(_T_655, _T_656) @[lsu_bus_buffer.scala 175:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[lsu_bus_buffer.scala 175:86] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_662 = and(_T_660, _T_661) @[lsu_bus_buffer.scala 175:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[lsu_bus_buffer.scala 175:86] + node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] + node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_666 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_667 = and(_T_665, _T_666) @[lsu_bus_buffer.scala 175:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[lsu_bus_buffer.scala 175:86] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_672 = and(_T_670, _T_671) @[lsu_bus_buffer.scala 175:91] + node _T_673 = or(_T_657, _T_662) @[lsu_bus_buffer.scala 175:123] + node _T_674 = or(_T_673, _T_667) @[lsu_bus_buffer.scala 175:123] + node _T_675 = or(_T_674, _T_672) @[lsu_bus_buffer.scala 175:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[lsu_bus_buffer.scala 176:60] + node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] + node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_679 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_680 = and(_T_678, _T_679) @[lsu_bus_buffer.scala 176:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[lsu_bus_buffer.scala 176:60] + node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] + node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_684 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_685 = and(_T_683, _T_684) @[lsu_bus_buffer.scala 176:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[lsu_bus_buffer.scala 176:60] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] + node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_689 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_690 = and(_T_688, _T_689) @[lsu_bus_buffer.scala 176:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[lsu_bus_buffer.scala 176:60] + node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] + node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_694 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_695 = and(_T_693, _T_694) @[lsu_bus_buffer.scala 176:65] + node _T_696 = or(_T_680, _T_685) @[lsu_bus_buffer.scala 176:97] + node _T_697 = or(_T_696, _T_690) @[lsu_bus_buffer.scala 176:97] + node _T_698 = or(_T_697, _T_695) @[lsu_bus_buffer.scala 176:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[lsu_bus_buffer.scala 177:60] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] + node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_702 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_703 = and(_T_701, _T_702) @[lsu_bus_buffer.scala 177:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[lsu_bus_buffer.scala 177:60] + node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] + node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_707 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_708 = and(_T_706, _T_707) @[lsu_bus_buffer.scala 177:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[lsu_bus_buffer.scala 177:60] + node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_713 = and(_T_711, _T_712) @[lsu_bus_buffer.scala 177:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[lsu_bus_buffer.scala 177:60] + node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] + node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_717 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_718 = and(_T_716, _T_717) @[lsu_bus_buffer.scala 177:65] + node _T_719 = or(_T_703, _T_708) @[lsu_bus_buffer.scala 177:97] + node _T_720 = or(_T_719, _T_713) @[lsu_bus_buffer.scala 177:97] + node _T_721 = or(_T_720, _T_718) @[lsu_bus_buffer.scala 177:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[lsu_bus_buffer.scala 178:60] + node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] + node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_725 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_726 = and(_T_724, _T_725) @[lsu_bus_buffer.scala 178:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[lsu_bus_buffer.scala 178:60] + node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] + node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_730 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_731 = and(_T_729, _T_730) @[lsu_bus_buffer.scala 178:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[lsu_bus_buffer.scala 178:60] + node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] + node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_735 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_736 = and(_T_734, _T_735) @[lsu_bus_buffer.scala 178:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[lsu_bus_buffer.scala 178:60] + node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] + node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_740 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_741 = and(_T_739, _T_740) @[lsu_bus_buffer.scala 178:65] + node _T_742 = or(_T_726, _T_731) @[lsu_bus_buffer.scala 178:97] + node _T_743 = or(_T_742, _T_736) @[lsu_bus_buffer.scala 178:97] + node _T_744 = or(_T_743, _T_741) @[lsu_bus_buffer.scala 178:97] + node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] + node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 179:32] + node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 178:103] + io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 175:24] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 181:77] + node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = or(_T_750, _T_751) @[Mux.scala 27:72] + node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_r <= _T_754 @[Mux.scala 27:72] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 186:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[lsu_bus_buffer.scala 186:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 187:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[lsu_bus_buffer.scala 187:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[lsu_bus_buffer.scala 187:60] + node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 188:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[lsu_bus_buffer.scala 188:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[lsu_bus_buffer.scala 188:60] + node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 189:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[lsu_bus_buffer.scala 189:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[lsu_bus_buffer.scala 189:60] + node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] + node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_762, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_766, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = or(_T_769, _T_770) @[Mux.scala 27:72] + node _T_774 = or(_T_773, _T_771) @[Mux.scala 27:72] + node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] + wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 191:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[lsu_bus_buffer.scala 191:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 192:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[lsu_bus_buffer.scala 192:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[lsu_bus_buffer.scala 192:50] + node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 193:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[lsu_bus_buffer.scala 193:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[lsu_bus_buffer.scala 193:50] + node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 194:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[lsu_bus_buffer.scala 194:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[lsu_bus_buffer.scala 194:50] + node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_783, _T_785, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_787, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = or(_T_790, _T_791) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_792) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] + wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 196:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[lsu_bus_buffer.scala 196:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 197:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[lsu_bus_buffer.scala 197:24] + node _T_801 = bits(io.store_data_r, 31, 24) @[lsu_bus_buffer.scala 197:64] + node _T_802 = cat(UInt<24>("h00"), _T_801) @[Cat.scala 29:58] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 198:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[lsu_bus_buffer.scala 198:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[lsu_bus_buffer.scala 198:63] + node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 199:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[lsu_bus_buffer.scala 199:24] + node _T_809 = bits(io.store_data_r, 31, 8) @[lsu_bus_buffer.scala 199:62] + node _T_810 = cat(UInt<8>("h00"), _T_809) @[Cat.scala 29:58] + node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_804, _T_806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_808, _T_810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = or(_T_811, _T_812) @[Mux.scala 27:72] + node _T_816 = or(_T_815, _T_813) @[Mux.scala 27:72] + node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] + wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] + store_data_hi_r <= _T_817 @[Mux.scala 27:72] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 201:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[lsu_bus_buffer.scala 201:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 202:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[lsu_bus_buffer.scala 202:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[lsu_bus_buffer.scala 202:52] + node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 203:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[lsu_bus_buffer.scala 203:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[lsu_bus_buffer.scala 203:52] + node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 204:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[lsu_bus_buffer.scala 204:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[lsu_bus_buffer.scala 204:52] + node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] + node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_834 = mux(_T_825, _T_827, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_835 = mux(_T_829, _T_831, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_836 = or(_T_832, _T_833) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] + wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] + store_data_lo_r <= _T_838 @[Mux.scala 27:72] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[lsu_bus_buffer.scala 207:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[lsu_bus_buffer.scala 207:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[lsu_bus_buffer.scala 207:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 208:72] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[lsu_bus_buffer.scala 208:79] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[lsu_bus_buffer.scala 209:45] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[lsu_bus_buffer.scala 209:31] + node _T_845 = mux(io.lsu_pkt_r.bits.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = mux(io.lsu_pkt_r.bits.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_847 = mux(io.lsu_pkt_r.bits.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_848 = or(_T_845, _T_846) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] + wire is_aligned_r : UInt<1> @[Mux.scala 27:72] + is_aligned_r <= _T_849 @[Mux.scala 27:72] + node _T_850 = or(io.lsu_pkt_r.bits.load, io.no_word_merge_r) @[lsu_bus_buffer.scala 211:60] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[lsu_bus_buffer.scala 211:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 211:84] + node ibuf_byp = and(_T_851, _T_852) @[lsu_bus_buffer.scala 211:82] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 212:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[lsu_bus_buffer.scala 212:56] + node ibuf_wr_en = and(_T_853, _T_854) @[lsu_bus_buffer.scala 212:54] + wire ibuf_drain_vld : UInt<1> + ibuf_drain_vld <= UInt<1>("h00") + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 214:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[lsu_bus_buffer.scala 214:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 214:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 215:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[lsu_bus_buffer.scala 215:42] + node _T_859 = and(_T_858, ibuf_valid) @[lsu_bus_buffer.scala 215:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 215:112] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 215:137] + node _T_862 = neq(_T_860, _T_861) @[lsu_bus_buffer.scala 215:120] + node _T_863 = or(io.lsu_pkt_m.bits.load, _T_862) @[lsu_bus_buffer.scala 215:100] + node ibuf_force_drain = and(_T_859, _T_863) @[lsu_bus_buffer.scala 215:74] + wire ibuf_sideeffect : UInt<1> + ibuf_sideeffect <= UInt<1>("h00") + wire ibuf_timer : UInt<3> + ibuf_timer <= UInt<1>("h00") + wire ibuf_merge_en : UInt<1> + ibuf_merge_en <= UInt<1>("h00") + wire ibuf_merge_in : UInt<1> + ibuf_merge_in <= UInt<1>("h00") + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 220:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[lsu_bus_buffer.scala 220:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 220:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[lsu_bus_buffer.scala 220:82] + node _T_868 = and(_T_865, _T_867) @[lsu_bus_buffer.scala 220:80] + node _T_869 = or(_T_868, ibuf_byp) @[lsu_bus_buffer.scala 221:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[lsu_bus_buffer.scala 221:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[lsu_bus_buffer.scala 221:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 221:55] + node _T_873 = or(_T_871, _T_872) @[lsu_bus_buffer.scala 221:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[lsu_bus_buffer.scala 221:67] + node _T_875 = and(ibuf_valid, _T_874) @[lsu_bus_buffer.scala 220:32] + ibuf_drain_vld <= _T_875 @[lsu_bus_buffer.scala 220:18] + wire ibuf_tag : UInt<2> + ibuf_tag <= UInt<1>("h00") + wire WrPtr1_r : UInt<2> + WrPtr1_r <= UInt<1>("h00") + wire WrPtr0_r : UInt<2> + WrPtr0_r <= UInt<1>("h00") + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 226:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[lsu_bus_buffer.scala 226:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[lsu_bus_buffer.scala 226:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 229:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 230:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[lsu_bus_buffer.scala 230:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 230:95] + node _T_881 = or(_T_879, _T_880) @[lsu_bus_buffer.scala 230:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 231:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 231:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[lsu_bus_buffer.scala 231:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[lsu_bus_buffer.scala 230:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 235:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 235:45] + node _T_888 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 235:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[lsu_bus_buffer.scala 235:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[lsu_bus_buffer.scala 236:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 236:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[lsu_bus_buffer.scala 236:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[lsu_bus_buffer.scala 234:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 235:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 235:45] + node _T_897 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 235:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[lsu_bus_buffer.scala 235:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[lsu_bus_buffer.scala 236:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 236:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[lsu_bus_buffer.scala 236:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[lsu_bus_buffer.scala 234:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 235:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 235:45] + node _T_906 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 235:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[lsu_bus_buffer.scala 235:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[lsu_bus_buffer.scala 236:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 236:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[lsu_bus_buffer.scala 236:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[lsu_bus_buffer.scala 234:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 235:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 235:45] + node _T_915 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 235:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[lsu_bus_buffer.scala 235:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[lsu_bus_buffer.scala 236:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 236:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[lsu_bus_buffer.scala 236:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[lsu_bus_buffer.scala 234:46] + node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] + node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] + node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 237:60] + node _T_924 = bits(_T_923, 0, 0) @[lsu_bus_buffer.scala 237:81] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 237:95] + node _T_926 = tail(_T_925, 1) @[lsu_bus_buffer.scala 237:95] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[lsu_bus_buffer.scala 237:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[lsu_bus_buffer.scala 237:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 239:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 239:54] + node _T_930 = and(_T_929, ibuf_valid) @[lsu_bus_buffer.scala 239:80] + node _T_931 = and(_T_930, ibuf_write) @[lsu_bus_buffer.scala 239:93] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_buffer.scala 239:122] + node _T_933 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 239:142] + node _T_934 = eq(_T_932, _T_933) @[lsu_bus_buffer.scala 239:129] + node _T_935 = and(_T_931, _T_934) @[lsu_bus_buffer.scala 239:106] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 239:152] + node _T_937 = and(_T_935, _T_936) @[lsu_bus_buffer.scala 239:150] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 239:175] + node _T_939 = and(_T_937, _T_938) @[lsu_bus_buffer.scala 239:173] + ibuf_merge_en <= _T_939 @[lsu_bus_buffer.scala 239:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 240:20] + ibuf_merge_in <= _T_940 @[lsu_bus_buffer.scala 240:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[lsu_bus_buffer.scala 241:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 241:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 241:114] + node _T_945 = or(_T_943, _T_944) @[lsu_bus_buffer.scala 241:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 241:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[lsu_bus_buffer.scala 241:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[lsu_bus_buffer.scala 241:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 241:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 241:114] + node _T_952 = or(_T_950, _T_951) @[lsu_bus_buffer.scala 241:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 241:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[lsu_bus_buffer.scala 241:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[lsu_bus_buffer.scala 241:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 241:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 241:114] + node _T_959 = or(_T_957, _T_958) @[lsu_bus_buffer.scala 241:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 241:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[lsu_bus_buffer.scala 241:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[lsu_bus_buffer.scala 241:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 241:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 241:114] + node _T_966 = or(_T_964, _T_965) @[lsu_bus_buffer.scala 241:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 241:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[lsu_bus_buffer.scala 241:48] + node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] + node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] + node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[lsu_bus_buffer.scala 242:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 242:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 242:118] + node _T_975 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 242:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[lsu_bus_buffer.scala 242:81] + node _T_977 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 242:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[lsu_bus_buffer.scala 242:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[lsu_bus_buffer.scala 242:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 242:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 242:118] + node _T_983 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 242:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[lsu_bus_buffer.scala 242:81] + node _T_985 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 242:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[lsu_bus_buffer.scala 242:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[lsu_bus_buffer.scala 242:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 242:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 242:118] + node _T_991 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 242:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[lsu_bus_buffer.scala 242:81] + node _T_993 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 242:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[lsu_bus_buffer.scala 242:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[lsu_bus_buffer.scala 242:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 242:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 242:118] + node _T_999 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 242:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[lsu_bus_buffer.scala 242:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 242:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[lsu_bus_buffer.scala 242:45] + node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] + node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] + node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[lsu_bus_buffer.scala 244:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 244:93] + node _T_1007 = and(_T_1005, _T_1006) @[lsu_bus_buffer.scala 244:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 244:54] + _T_1008 <= _T_1007 @[lsu_bus_buffer.scala 244:54] + ibuf_valid <= _T_1008 @[lsu_bus_buffer.scala 244:14] + reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_tag <= _T_1009 @[lsu_bus_buffer.scala 245:12] + reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_dual : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dual <= io.ldst_dual_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_samedw : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_samedw <= ldst_samedw_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_nomerge : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_nomerge <= io.no_dword_merge_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1010 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_sideeffect <= _T_1010 @[lsu_bus_buffer.scala 250:19] + reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_unsign <= io.lsu_pkt_r.bits.unsign @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1011 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1011 <= io.lsu_pkt_r.bits.store @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_write <= _T_1011 @[lsu_bus_buffer.scala 252:14] + reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr of rvclkhdr_22 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1012 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1012 <= ibuf_addr_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 254:13] + reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 255:15] + inst rvclkhdr_1 of rvclkhdr_23 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1014 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1014 <= ibuf_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 256:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 257:55] + _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 257:55] + ibuf_timer <= _T_1015 @[lsu_bus_buffer.scala 257:14] + wire buf_numvld_wrcmd_any : UInt<4> + buf_numvld_wrcmd_any <= UInt<1>("h00") + wire buf_numvld_cmd_any : UInt<4> + buf_numvld_cmd_any <= UInt<1>("h00") + wire obuf_wr_timer : UInt<3> + obuf_wr_timer <= UInt<1>("h00") + wire buf_nomerge : UInt<1>[4] @[lsu_bus_buffer.scala 261:25] + buf_nomerge[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + wire buf_sideeffect : UInt<4> + buf_sideeffect <= UInt<1>("h00") + wire obuf_force_wr_en : UInt<1> + obuf_force_wr_en <= UInt<1>("h00") + wire obuf_wr_en : UInt<1> + obuf_wr_en <= UInt<1>("h00") + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 267:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 267:72] + node _T_1018 = and(_T_1016, _T_1017) @[lsu_bus_buffer.scala 267:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 267:97] + node _T_1020 = and(_T_1018, _T_1019) @[lsu_bus_buffer.scala 267:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:5] + node _T_1022 = and(_T_1020, _T_1021) @[lsu_bus_buffer.scala 267:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 268:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 268:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 268:114] + node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1030 = mux(_T_1026, buf_nomerge[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1031 = or(_T_1027, _T_1028) @[Mux.scala 27:72] + node _T_1032 = or(_T_1031, _T_1029) @[Mux.scala 27:72] + node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] + wire _T_1034 : UInt<1> @[Mux.scala 27:72] + _T_1034 <= _T_1033 @[Mux.scala 27:72] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:31] + node _T_1036 = and(_T_1022, _T_1035) @[lsu_bus_buffer.scala 268:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 269:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 269:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 269:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 269:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 269:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 269:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 269:111] + node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1048 = mux(_T_1043, _T_1044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1049 = or(_T_1045, _T_1046) @[Mux.scala 27:72] + node _T_1050 = or(_T_1049, _T_1047) @[Mux.scala 27:72] + node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] + wire _T_1052 : UInt<1> @[Mux.scala 27:72] + _T_1052 <= _T_1051 @[Mux.scala 27:72] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:5] + node _T_1054 = and(_T_1036, _T_1053) @[lsu_bus_buffer.scala 268:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[lsu_bus_buffer.scala 269:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[lsu_bus_buffer.scala 270:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 270:95] + node _T_1058 = and(_T_1056, _T_1057) @[lsu_bus_buffer.scala 270:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 270:123] + node _T_1060 = tail(_T_1059, 1) @[lsu_bus_buffer.scala 270:123] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[lsu_bus_buffer.scala 270:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[lsu_bus_buffer.scala 270:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[lsu_bus_buffer.scala 271:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:60] + node _T_1065 = and(_T_1063, _T_1064) @[lsu_bus_buffer.scala 271:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 271:93] + node _T_1067 = and(_T_1065, _T_1066) @[lsu_bus_buffer.scala 271:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 271:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 271:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 271:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 271:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = or(_T_1077, _T_1078) @[Mux.scala 27:72] + node _T_1082 = or(_T_1081, _T_1079) @[Mux.scala 27:72] + node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] + wire _T_1084 : UInt<30> @[Mux.scala 27:72] + _T_1084 <= _T_1083 @[Mux.scala 27:72] + node _T_1085 = neq(_T_1068, _T_1084) @[lsu_bus_buffer.scala 271:123] + node _T_1086 = and(_T_1067, _T_1085) @[lsu_bus_buffer.scala 271:101] + obuf_force_wr_en <= _T_1086 @[lsu_bus_buffer.scala 271:20] + wire buf_numvld_pend_any : UInt<4> + buf_numvld_pend_any <= UInt<1>("h00") + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 273:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[lsu_bus_buffer.scala 273:31] + node _T_1089 = eq(io.lsu_pkt_r.bits.store, UInt<1>("h00")) @[lsu_bus_buffer.scala 273:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[lsu_bus_buffer.scala 273:89] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[lsu_bus_buffer.scala 273:61] + wire bus_sideeffect_pend : UInt<1> + bus_sideeffect_pend <= UInt<1>("h00") + wire found_cmdptr0 : UInt<1> + found_cmdptr0 <= UInt<1>("h00") + wire buf_cmd_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 276:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + wire buf_dual : UInt<1>[4] @[lsu_bus_buffer.scala 278:22] + buf_dual[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + wire buf_samedw : UInt<1>[4] @[lsu_bus_buffer.scala 280:24] + buf_samedw[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + wire found_cmdptr1 : UInt<1> + found_cmdptr1 <= UInt<1>("h00") + wire bus_cmd_ready : UInt<1> + bus_cmd_ready <= UInt<1>("h00") + wire obuf_valid : UInt<1> + obuf_valid <= UInt<1>("h00") + wire obuf_nosend : UInt<1> + obuf_nosend <= UInt<1>("h00") + wire bus_addr_match_pending : UInt<1> + bus_addr_match_pending <= UInt<1>("h00") + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[lsu_bus_buffer.scala 289:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[lsu_bus_buffer.scala 289:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[lsu_bus_buffer.scala 289:52] + node _T_1094 = and(_T_1091, _T_1093) @[lsu_bus_buffer.scala 289:50] + node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1099 = mux(_T_1095, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_1096, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1097, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_1098, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = or(_T_1099, _T_1100) @[Mux.scala 27:72] + node _T_1104 = or(_T_1103, _T_1101) @[Mux.scala 27:72] + node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] + wire _T_1106 : UInt<3> @[Mux.scala 27:72] + _T_1106 <= _T_1105 @[Mux.scala 27:72] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[lsu_bus_buffer.scala 290:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[lsu_bus_buffer.scala 290:47] + node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1113 = bits(_T_1111, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1115 = bits(_T_1111, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1117 = bits(_T_1111, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1119 = bits(_T_1111, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1120 = mux(_T_1112, _T_1113, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1116, _T_1117, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1118, _T_1119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = or(_T_1120, _T_1121) @[Mux.scala 27:72] + node _T_1125 = or(_T_1124, _T_1122) @[Mux.scala 27:72] + node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] + wire _T_1127 : UInt<1> @[Mux.scala 27:72] + _T_1127 <= _T_1126 @[Mux.scala 27:72] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:23] + node _T_1129 = and(_T_1108, _T_1128) @[lsu_bus_buffer.scala 291:21] + node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1131 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1133 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1135 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1137 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1138 = mux(_T_1130, _T_1131, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1139 = mux(_T_1132, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1140 = mux(_T_1134, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1141 = mux(_T_1136, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1142 = or(_T_1138, _T_1139) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1140) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] + wire _T_1145 : UInt<1> @[Mux.scala 27:72] + _T_1145 <= _T_1144 @[Mux.scala 27:72] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[lsu_bus_buffer.scala 291:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:105] + node _T_1148 = and(_T_1129, _T_1147) @[lsu_bus_buffer.scala 291:103] + node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] + node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] + node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1153 = bits(_T_1151, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1155 = bits(_T_1151, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1157 = bits(_T_1151, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1159 = bits(_T_1151, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1160 = mux(_T_1152, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1161 = mux(_T_1154, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1162 = mux(_T_1156, _T_1157, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1163 = mux(_T_1158, _T_1159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1164 = or(_T_1160, _T_1161) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1162) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1163) @[Mux.scala 27:72] + wire _T_1167 : UInt<1> @[Mux.scala 27:72] + _T_1167 <= _T_1166 @[Mux.scala 27:72] + node _T_1168 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1170 = cat(_T_1169, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1172 = bits(_T_1170, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1174 = bits(_T_1170, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1176 = bits(_T_1170, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1178 = bits(_T_1170, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1179 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1180 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1181 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1182 = mux(_T_1177, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1183 = or(_T_1179, _T_1180) @[Mux.scala 27:72] + node _T_1184 = or(_T_1183, _T_1181) @[Mux.scala 27:72] + node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] + wire _T_1186 : UInt<1> @[Mux.scala 27:72] + _T_1186 <= _T_1185 @[Mux.scala 27:72] + node _T_1187 = and(_T_1167, _T_1186) @[lsu_bus_buffer.scala 292:77] + node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1189 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1191 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1193 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1195 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1194, _T_1195, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = or(_T_1196, _T_1197) @[Mux.scala 27:72] + node _T_1201 = or(_T_1200, _T_1198) @[Mux.scala 27:72] + node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] + wire _T_1203 : UInt<1> @[Mux.scala 27:72] + _T_1203 <= _T_1202 @[Mux.scala 27:72] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:150] + node _T_1205 = and(_T_1187, _T_1204) @[lsu_bus_buffer.scala 292:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[lsu_bus_buffer.scala 292:181] + node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] + node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] + node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] + node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1212 = bits(_T_1210, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1214 = bits(_T_1210, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1216 = bits(_T_1210, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1218 = bits(_T_1210, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1219 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = or(_T_1219, _T_1220) @[Mux.scala 27:72] + node _T_1224 = or(_T_1223, _T_1221) @[Mux.scala 27:72] + node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] + wire _T_1226 : UInt<1> @[Mux.scala 27:72] + _T_1226 <= _T_1225 @[Mux.scala 27:72] + node _T_1227 = or(_T_1207, _T_1226) @[lsu_bus_buffer.scala 292:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[lsu_bus_buffer.scala 292:269] + node _T_1229 = and(_T_1148, _T_1228) @[lsu_bus_buffer.scala 291:164] + node _T_1230 = or(_T_1094, _T_1229) @[lsu_bus_buffer.scala 289:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[lsu_bus_buffer.scala 293:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[lsu_bus_buffer.scala 293:60] + node _T_1234 = and(_T_1230, _T_1233) @[lsu_bus_buffer.scala 293:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:77] + node _T_1236 = and(_T_1234, _T_1235) @[lsu_bus_buffer.scala 293:75] + node _T_1237 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:94] + node _T_1238 = and(_T_1236, _T_1237) @[lsu_bus_buffer.scala 293:92] + node _T_1239 = and(_T_1238, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 293:118] + obuf_wr_en <= _T_1239 @[lsu_bus_buffer.scala 289:14] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_1240 = and(obuf_valid, obuf_nosend) @[lsu_bus_buffer.scala 296:47] + node _T_1241 = or(bus_cmd_sent, _T_1240) @[lsu_bus_buffer.scala 296:33] + node _T_1242 = eq(obuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 296:65] + node _T_1243 = and(_T_1241, _T_1242) @[lsu_bus_buffer.scala 296:63] + node _T_1244 = and(_T_1243, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 296:77] + node obuf_rst = or(_T_1244, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 296:98] + node _T_1245 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1246 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1247 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1248 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1249 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1250 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1251 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1252 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1253 = mux(_T_1245, _T_1246, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1254 = mux(_T_1247, _T_1248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1255 = mux(_T_1249, _T_1250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1256 = mux(_T_1251, _T_1252, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1257 = or(_T_1253, _T_1254) @[Mux.scala 27:72] + node _T_1258 = or(_T_1257, _T_1255) @[Mux.scala 27:72] + node _T_1259 = or(_T_1258, _T_1256) @[Mux.scala 27:72] + wire _T_1260 : UInt<1> @[Mux.scala 27:72] + _T_1260 <= _T_1259 @[Mux.scala 27:72] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1260) @[lsu_bus_buffer.scala 297:26] + node _T_1261 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1262 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1263 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1264 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1265 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1266 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1267 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1268 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1269 = mux(_T_1261, _T_1262, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1270 = mux(_T_1263, _T_1264, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1271 = mux(_T_1265, _T_1266, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1272 = mux(_T_1267, _T_1268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1273 = or(_T_1269, _T_1270) @[Mux.scala 27:72] + node _T_1274 = or(_T_1273, _T_1271) @[Mux.scala 27:72] + node _T_1275 = or(_T_1274, _T_1272) @[Mux.scala 27:72] + wire _T_1276 : UInt<1> @[Mux.scala 27:72] + _T_1276 <= _T_1275 @[Mux.scala 27:72] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1276) @[lsu_bus_buffer.scala 298:31] + node _T_1277 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1278 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1279 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1280 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1281 = mux(_T_1277, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1282 = mux(_T_1278, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1283 = mux(_T_1279, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1284 = mux(_T_1280, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1285 = or(_T_1281, _T_1282) @[Mux.scala 27:72] + node _T_1286 = or(_T_1285, _T_1283) @[Mux.scala 27:72] + node _T_1287 = or(_T_1286, _T_1284) @[Mux.scala 27:72] + wire _T_1288 : UInt<32> @[Mux.scala 27:72] + _T_1288 <= _T_1287 @[Mux.scala 27:72] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1288) @[lsu_bus_buffer.scala 299:25] + wire buf_sz : UInt<2>[4] @[lsu_bus_buffer.scala 300:20] + buf_sz[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + node _T_1289 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_1290 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1291 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1292 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1293 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1294 = mux(_T_1290, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1295 = mux(_T_1291, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1296 = mux(_T_1292, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1297 = mux(_T_1293, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1298 = or(_T_1294, _T_1295) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1296) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1297) @[Mux.scala 27:72] + wire _T_1301 : UInt<2> @[Mux.scala 27:72] + _T_1301 <= _T_1300 @[Mux.scala 27:72] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1289, _T_1301) @[lsu_bus_buffer.scala 302:23] + wire obuf_merge_en : UInt<1> + obuf_merge_en <= UInt<1>("h00") + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 305:25] + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 307:25] + wire obuf_cmd_done : UInt<1> + obuf_cmd_done <= UInt<1>("h00") + wire bus_wcmd_sent : UInt<1> + bus_wcmd_sent <= UInt<1>("h00") + node _T_1302 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 310:39] + node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[lsu_bus_buffer.scala 310:26] + node _T_1304 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 310:68] + node obuf_cmd_done_in = and(_T_1303, _T_1304) @[lsu_bus_buffer.scala 310:51] + wire obuf_data_done : UInt<1> + obuf_data_done <= UInt<1>("h00") + wire bus_wdata_sent : UInt<1> + bus_wdata_sent <= UInt<1>("h00") + node _T_1305 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 313:40] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[lsu_bus_buffer.scala 313:27] + node _T_1307 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 313:70] + node obuf_data_done_in = and(_T_1306, _T_1307) @[lsu_bus_buffer.scala 313:52] + node _T_1308 = bits(obuf_sz_in, 1, 0) @[lsu_bus_buffer.scala 314:67] + node _T_1309 = eq(_T_1308, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:72] + node _T_1310 = bits(obuf_sz_in, 0, 0) @[lsu_bus_buffer.scala 314:92] + node _T_1311 = bits(obuf_addr_in, 0, 0) @[lsu_bus_buffer.scala 314:111] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:98] + node _T_1313 = and(_T_1310, _T_1312) @[lsu_bus_buffer.scala 314:96] + node _T_1314 = or(_T_1309, _T_1313) @[lsu_bus_buffer.scala 314:79] + node _T_1315 = bits(obuf_sz_in, 1, 1) @[lsu_bus_buffer.scala 314:129] + node _T_1316 = bits(obuf_addr_in, 1, 0) @[lsu_bus_buffer.scala 314:147] + node _T_1317 = orr(_T_1316) @[lsu_bus_buffer.scala 314:153] + node _T_1318 = eq(_T_1317, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:134] + node _T_1319 = and(_T_1315, _T_1318) @[lsu_bus_buffer.scala 314:132] + node _T_1320 = or(_T_1314, _T_1319) @[lsu_bus_buffer.scala 314:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1320) @[lsu_bus_buffer.scala 314:28] + wire obuf_nosend_in : UInt<1> + obuf_nosend_in <= UInt<1>("h00") + wire obuf_rdrsp_pend : UInt<1> + obuf_rdrsp_pend <= UInt<1>("h00") + wire bus_rsp_read : UInt<1> + bus_rsp_read <= UInt<1>("h00") + wire bus_rsp_read_tag : UInt<3> + bus_rsp_read_tag <= UInt<1>("h00") + wire obuf_rdrsp_tag : UInt<3> + obuf_rdrsp_tag <= UInt<1>("h00") + wire obuf_write : UInt<1> + obuf_write <= UInt<1>("h00") + node _T_1321 = eq(obuf_nosend_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:45] + node _T_1322 = and(obuf_wr_en, _T_1321) @[lsu_bus_buffer.scala 322:43] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:30] + node _T_1324 = and(_T_1323, obuf_rdrsp_pend) @[lsu_bus_buffer.scala 322:62] + node _T_1325 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 322:117] + node _T_1326 = and(bus_rsp_read, _T_1325) @[lsu_bus_buffer.scala 322:97] + node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:82] + node _T_1328 = and(_T_1324, _T_1327) @[lsu_bus_buffer.scala 322:80] + node _T_1329 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:157] + node _T_1330 = and(bus_cmd_sent, _T_1329) @[lsu_bus_buffer.scala 322:155] + node _T_1331 = or(_T_1328, _T_1330) @[lsu_bus_buffer.scala 322:139] + node _T_1332 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:173] + node obuf_rdrsp_pend_in = and(_T_1331, _T_1332) @[lsu_bus_buffer.scala 322:171] + node obuf_rdrsp_pend_en = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 323:47] + wire obuf_tag0 : UInt<3> + obuf_tag0 <= UInt<1>("h00") + node _T_1333 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 325:46] + node _T_1334 = and(bus_cmd_sent, _T_1333) @[lsu_bus_buffer.scala 325:44] + node obuf_rdrsp_tag_in = mux(_T_1334, obuf_tag0, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 325:30] + wire obuf_addr : UInt<32> + obuf_addr <= UInt<1>("h00") + wire obuf_sideeffect : UInt<1> + obuf_sideeffect <= UInt<1>("h00") + node _T_1335 = bits(obuf_addr_in, 31, 3) @[lsu_bus_buffer.scala 328:34] + node _T_1336 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 328:52] + node _T_1337 = eq(_T_1335, _T_1336) @[lsu_bus_buffer.scala 328:40] + node _T_1338 = and(_T_1337, obuf_aligned_in) @[lsu_bus_buffer.scala 328:60] + node _T_1339 = eq(obuf_sideeffect, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:80] + node _T_1340 = and(_T_1338, _T_1339) @[lsu_bus_buffer.scala 328:78] + node _T_1341 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:99] + node _T_1342 = and(_T_1340, _T_1341) @[lsu_bus_buffer.scala 328:97] + node _T_1343 = eq(obuf_write_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:113] + node _T_1344 = and(_T_1342, _T_1343) @[lsu_bus_buffer.scala 328:111] + node _T_1345 = eq(io.tlu_busbuff.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:130] + node _T_1346 = and(_T_1344, _T_1345) @[lsu_bus_buffer.scala 328:128] + node _T_1347 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 329:20] + node _T_1348 = and(obuf_valid, _T_1347) @[lsu_bus_buffer.scala 329:18] + node _T_1349 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 329:90] + node _T_1350 = and(bus_rsp_read, _T_1349) @[lsu_bus_buffer.scala 329:70] + node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[lsu_bus_buffer.scala 329:55] + node _T_1352 = and(obuf_rdrsp_pend, _T_1351) @[lsu_bus_buffer.scala 329:53] + node _T_1353 = or(_T_1348, _T_1352) @[lsu_bus_buffer.scala 329:34] + node _T_1354 = and(_T_1346, _T_1353) @[lsu_bus_buffer.scala 328:177] + obuf_nosend_in <= _T_1354 @[lsu_bus_buffer.scala 328:18] + node _T_1355 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 330:60] + node _T_1356 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1357 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] + node _T_1358 = mux(_T_1355, _T_1356, _T_1357) @[lsu_bus_buffer.scala 330:46] + node _T_1359 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1360 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1361 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1362 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1363 = mux(_T_1359, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1364 = mux(_T_1360, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1365 = mux(_T_1361, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1362, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = or(_T_1363, _T_1364) @[Mux.scala 27:72] + node _T_1368 = or(_T_1367, _T_1365) @[Mux.scala 27:72] + node _T_1369 = or(_T_1368, _T_1366) @[Mux.scala 27:72] + wire _T_1370 : UInt<32> @[Mux.scala 27:72] + _T_1370 <= _T_1369 @[Mux.scala 27:72] + node _T_1371 = bits(_T_1370, 2, 2) @[lsu_bus_buffer.scala 331:36] + node _T_1372 = bits(_T_1371, 0, 0) @[lsu_bus_buffer.scala 331:46] + node _T_1373 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1374 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1375 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1376 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1377 = mux(_T_1373, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1378 = mux(_T_1374, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1379 = mux(_T_1375, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1376, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = or(_T_1377, _T_1378) @[Mux.scala 27:72] + node _T_1382 = or(_T_1381, _T_1379) @[Mux.scala 27:72] + node _T_1383 = or(_T_1382, _T_1380) @[Mux.scala 27:72] + wire _T_1384 : UInt<4> @[Mux.scala 27:72] + _T_1384 <= _T_1383 @[Mux.scala 27:72] + node _T_1385 = cat(_T_1384, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1386 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1387 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1388 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1389 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1390 = mux(_T_1386, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1391 = mux(_T_1387, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1392 = mux(_T_1388, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1393 = mux(_T_1389, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1394 = or(_T_1390, _T_1391) @[Mux.scala 27:72] + node _T_1395 = or(_T_1394, _T_1392) @[Mux.scala 27:72] + node _T_1396 = or(_T_1395, _T_1393) @[Mux.scala 27:72] + wire _T_1397 : UInt<4> @[Mux.scala 27:72] + _T_1397 <= _T_1396 @[Mux.scala 27:72] + node _T_1398 = cat(UInt<4>("h00"), _T_1397) @[Cat.scala 29:58] + node _T_1399 = mux(_T_1372, _T_1385, _T_1398) @[lsu_bus_buffer.scala 331:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1358, _T_1399) @[lsu_bus_buffer.scala 330:28] + node _T_1400 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 332:60] + node _T_1401 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1402 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] + node _T_1403 = mux(_T_1400, _T_1401, _T_1402) @[lsu_bus_buffer.scala 332:46] + node _T_1404 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1405 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1406 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1407 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1408 = mux(_T_1404, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1409 = mux(_T_1405, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1410 = mux(_T_1406, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1411 = mux(_T_1407, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1412 = or(_T_1408, _T_1409) @[Mux.scala 27:72] + node _T_1413 = or(_T_1412, _T_1410) @[Mux.scala 27:72] + node _T_1414 = or(_T_1413, _T_1411) @[Mux.scala 27:72] + wire _T_1415 : UInt<32> @[Mux.scala 27:72] + _T_1415 <= _T_1414 @[Mux.scala 27:72] + node _T_1416 = bits(_T_1415, 2, 2) @[lsu_bus_buffer.scala 333:36] + node _T_1417 = bits(_T_1416, 0, 0) @[lsu_bus_buffer.scala 333:46] + node _T_1418 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1419 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1420 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1421 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1422 = mux(_T_1418, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1423 = mux(_T_1419, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1424 = mux(_T_1420, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1425 = mux(_T_1421, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = or(_T_1422, _T_1423) @[Mux.scala 27:72] + node _T_1427 = or(_T_1426, _T_1424) @[Mux.scala 27:72] + node _T_1428 = or(_T_1427, _T_1425) @[Mux.scala 27:72] + wire _T_1429 : UInt<4> @[Mux.scala 27:72] + _T_1429 <= _T_1428 @[Mux.scala 27:72] + node _T_1430 = cat(_T_1429, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1431 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1432 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1433 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1434 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1435 = mux(_T_1431, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1436 = mux(_T_1432, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1437 = mux(_T_1433, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1438 = mux(_T_1434, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1439 = or(_T_1435, _T_1436) @[Mux.scala 27:72] + node _T_1440 = or(_T_1439, _T_1437) @[Mux.scala 27:72] + node _T_1441 = or(_T_1440, _T_1438) @[Mux.scala 27:72] + wire _T_1442 : UInt<4> @[Mux.scala 27:72] + _T_1442 <= _T_1441 @[Mux.scala 27:72] + node _T_1443 = cat(UInt<4>("h00"), _T_1442) @[Cat.scala 29:58] + node _T_1444 = mux(_T_1417, _T_1430, _T_1443) @[lsu_bus_buffer.scala 333:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1403, _T_1444) @[lsu_bus_buffer.scala 332:28] + node _T_1445 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 335:58] + node _T_1446 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1447 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] + node _T_1448 = mux(_T_1445, _T_1446, _T_1447) @[lsu_bus_buffer.scala 335:44] + node _T_1449 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1450 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1451 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1452 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1453 = mux(_T_1449, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1454 = mux(_T_1450, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1455 = mux(_T_1451, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = mux(_T_1452, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1457 = or(_T_1453, _T_1454) @[Mux.scala 27:72] + node _T_1458 = or(_T_1457, _T_1455) @[Mux.scala 27:72] + node _T_1459 = or(_T_1458, _T_1456) @[Mux.scala 27:72] + wire _T_1460 : UInt<32> @[Mux.scala 27:72] + _T_1460 <= _T_1459 @[Mux.scala 27:72] + node _T_1461 = bits(_T_1460, 2, 2) @[lsu_bus_buffer.scala 336:36] + node _T_1462 = bits(_T_1461, 0, 0) @[lsu_bus_buffer.scala 336:46] + node _T_1463 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1464 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1465 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1466 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1467 = mux(_T_1463, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1468 = mux(_T_1464, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1469 = mux(_T_1465, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1466, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = or(_T_1467, _T_1468) @[Mux.scala 27:72] + node _T_1472 = or(_T_1471, _T_1469) @[Mux.scala 27:72] + node _T_1473 = or(_T_1472, _T_1470) @[Mux.scala 27:72] + wire _T_1474 : UInt<32> @[Mux.scala 27:72] + _T_1474 <= _T_1473 @[Mux.scala 27:72] + node _T_1475 = cat(_T_1474, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1476 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1477 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1478 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1479 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1480 = mux(_T_1476, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1477, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1478, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1479, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = or(_T_1480, _T_1481) @[Mux.scala 27:72] + node _T_1485 = or(_T_1484, _T_1482) @[Mux.scala 27:72] + node _T_1486 = or(_T_1485, _T_1483) @[Mux.scala 27:72] + wire _T_1487 : UInt<32> @[Mux.scala 27:72] + _T_1487 <= _T_1486 @[Mux.scala 27:72] + node _T_1488 = cat(UInt<32>("h00"), _T_1487) @[Cat.scala 29:58] + node _T_1489 = mux(_T_1462, _T_1475, _T_1488) @[lsu_bus_buffer.scala 336:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1448, _T_1489) @[lsu_bus_buffer.scala 335:26] + node _T_1490 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 337:58] + node _T_1491 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1492 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] + node _T_1493 = mux(_T_1490, _T_1491, _T_1492) @[lsu_bus_buffer.scala 337:44] + node _T_1494 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1495 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1496 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1497 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1498 = mux(_T_1494, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1495, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1496, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1497, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = or(_T_1498, _T_1499) @[Mux.scala 27:72] + node _T_1503 = or(_T_1502, _T_1500) @[Mux.scala 27:72] + node _T_1504 = or(_T_1503, _T_1501) @[Mux.scala 27:72] + wire _T_1505 : UInt<32> @[Mux.scala 27:72] + _T_1505 <= _T_1504 @[Mux.scala 27:72] + node _T_1506 = bits(_T_1505, 2, 2) @[lsu_bus_buffer.scala 338:36] + node _T_1507 = bits(_T_1506, 0, 0) @[lsu_bus_buffer.scala 338:46] + node _T_1508 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1509 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1510 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1511 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1512 = mux(_T_1508, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1509, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1510, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1511, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = or(_T_1512, _T_1513) @[Mux.scala 27:72] + node _T_1517 = or(_T_1516, _T_1514) @[Mux.scala 27:72] + node _T_1518 = or(_T_1517, _T_1515) @[Mux.scala 27:72] + wire _T_1519 : UInt<32> @[Mux.scala 27:72] + _T_1519 <= _T_1518 @[Mux.scala 27:72] + node _T_1520 = cat(_T_1519, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1521 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1522 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1523 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1524 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1525 = mux(_T_1521, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1522, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1523, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1524, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = or(_T_1525, _T_1526) @[Mux.scala 27:72] + node _T_1530 = or(_T_1529, _T_1527) @[Mux.scala 27:72] + node _T_1531 = or(_T_1530, _T_1528) @[Mux.scala 27:72] + wire _T_1532 : UInt<32> @[Mux.scala 27:72] + _T_1532 <= _T_1531 @[Mux.scala 27:72] + node _T_1533 = cat(UInt<32>("h00"), _T_1532) @[Cat.scala 29:58] + node _T_1534 = mux(_T_1507, _T_1520, _T_1533) @[lsu_bus_buffer.scala 338:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1493, _T_1534) @[lsu_bus_buffer.scala 337:26] + node _T_1535 = bits(obuf_byteen0_in, 0, 0) @[lsu_bus_buffer.scala 339:59] + node _T_1536 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 339:97] + node _T_1537 = and(obuf_merge_en, _T_1536) @[lsu_bus_buffer.scala 339:80] + node _T_1538 = or(_T_1535, _T_1537) @[lsu_bus_buffer.scala 339:63] + node _T_1539 = bits(obuf_byteen0_in, 1, 1) @[lsu_bus_buffer.scala 339:59] + node _T_1540 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 339:97] + node _T_1541 = and(obuf_merge_en, _T_1540) @[lsu_bus_buffer.scala 339:80] + node _T_1542 = or(_T_1539, _T_1541) @[lsu_bus_buffer.scala 339:63] + node _T_1543 = bits(obuf_byteen0_in, 2, 2) @[lsu_bus_buffer.scala 339:59] + node _T_1544 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 339:97] + node _T_1545 = and(obuf_merge_en, _T_1544) @[lsu_bus_buffer.scala 339:80] + node _T_1546 = or(_T_1543, _T_1545) @[lsu_bus_buffer.scala 339:63] + node _T_1547 = bits(obuf_byteen0_in, 3, 3) @[lsu_bus_buffer.scala 339:59] + node _T_1548 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 339:97] + node _T_1549 = and(obuf_merge_en, _T_1548) @[lsu_bus_buffer.scala 339:80] + node _T_1550 = or(_T_1547, _T_1549) @[lsu_bus_buffer.scala 339:63] + node _T_1551 = bits(obuf_byteen0_in, 4, 4) @[lsu_bus_buffer.scala 339:59] + node _T_1552 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 339:97] + node _T_1553 = and(obuf_merge_en, _T_1552) @[lsu_bus_buffer.scala 339:80] + node _T_1554 = or(_T_1551, _T_1553) @[lsu_bus_buffer.scala 339:63] + node _T_1555 = bits(obuf_byteen0_in, 5, 5) @[lsu_bus_buffer.scala 339:59] + node _T_1556 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 339:97] + node _T_1557 = and(obuf_merge_en, _T_1556) @[lsu_bus_buffer.scala 339:80] + node _T_1558 = or(_T_1555, _T_1557) @[lsu_bus_buffer.scala 339:63] + node _T_1559 = bits(obuf_byteen0_in, 6, 6) @[lsu_bus_buffer.scala 339:59] + node _T_1560 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 339:97] + node _T_1561 = and(obuf_merge_en, _T_1560) @[lsu_bus_buffer.scala 339:80] + node _T_1562 = or(_T_1559, _T_1561) @[lsu_bus_buffer.scala 339:63] + node _T_1563 = bits(obuf_byteen0_in, 7, 7) @[lsu_bus_buffer.scala 339:59] + node _T_1564 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 339:97] + node _T_1565 = and(obuf_merge_en, _T_1564) @[lsu_bus_buffer.scala 339:80] + node _T_1566 = or(_T_1563, _T_1565) @[lsu_bus_buffer.scala 339:63] + node _T_1567 = cat(_T_1566, _T_1562) @[Cat.scala 29:58] + node _T_1568 = cat(_T_1567, _T_1558) @[Cat.scala 29:58] + node _T_1569 = cat(_T_1568, _T_1554) @[Cat.scala 29:58] + node _T_1570 = cat(_T_1569, _T_1550) @[Cat.scala 29:58] + node _T_1571 = cat(_T_1570, _T_1546) @[Cat.scala 29:58] + node _T_1572 = cat(_T_1571, _T_1542) @[Cat.scala 29:58] + node obuf_byteen_in = cat(_T_1572, _T_1538) @[Cat.scala 29:58] + node _T_1573 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 340:76] + node _T_1574 = and(obuf_merge_en, _T_1573) @[lsu_bus_buffer.scala 340:59] + node _T_1575 = bits(obuf_data1_in, 7, 0) @[lsu_bus_buffer.scala 340:94] + node _T_1576 = bits(obuf_data0_in, 7, 0) @[lsu_bus_buffer.scala 340:123] + node _T_1577 = mux(_T_1574, _T_1575, _T_1576) @[lsu_bus_buffer.scala 340:44] + node _T_1578 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 340:76] + node _T_1579 = and(obuf_merge_en, _T_1578) @[lsu_bus_buffer.scala 340:59] + node _T_1580 = bits(obuf_data1_in, 15, 8) @[lsu_bus_buffer.scala 340:94] + node _T_1581 = bits(obuf_data0_in, 15, 8) @[lsu_bus_buffer.scala 340:123] + node _T_1582 = mux(_T_1579, _T_1580, _T_1581) @[lsu_bus_buffer.scala 340:44] + node _T_1583 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 340:76] + node _T_1584 = and(obuf_merge_en, _T_1583) @[lsu_bus_buffer.scala 340:59] + node _T_1585 = bits(obuf_data1_in, 23, 16) @[lsu_bus_buffer.scala 340:94] + node _T_1586 = bits(obuf_data0_in, 23, 16) @[lsu_bus_buffer.scala 340:123] + node _T_1587 = mux(_T_1584, _T_1585, _T_1586) @[lsu_bus_buffer.scala 340:44] + node _T_1588 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 340:76] + node _T_1589 = and(obuf_merge_en, _T_1588) @[lsu_bus_buffer.scala 340:59] + node _T_1590 = bits(obuf_data1_in, 31, 24) @[lsu_bus_buffer.scala 340:94] + node _T_1591 = bits(obuf_data0_in, 31, 24) @[lsu_bus_buffer.scala 340:123] + node _T_1592 = mux(_T_1589, _T_1590, _T_1591) @[lsu_bus_buffer.scala 340:44] + node _T_1593 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 340:76] + node _T_1594 = and(obuf_merge_en, _T_1593) @[lsu_bus_buffer.scala 340:59] + node _T_1595 = bits(obuf_data1_in, 39, 32) @[lsu_bus_buffer.scala 340:94] + node _T_1596 = bits(obuf_data0_in, 39, 32) @[lsu_bus_buffer.scala 340:123] + node _T_1597 = mux(_T_1594, _T_1595, _T_1596) @[lsu_bus_buffer.scala 340:44] + node _T_1598 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 340:76] + node _T_1599 = and(obuf_merge_en, _T_1598) @[lsu_bus_buffer.scala 340:59] + node _T_1600 = bits(obuf_data1_in, 47, 40) @[lsu_bus_buffer.scala 340:94] + node _T_1601 = bits(obuf_data0_in, 47, 40) @[lsu_bus_buffer.scala 340:123] + node _T_1602 = mux(_T_1599, _T_1600, _T_1601) @[lsu_bus_buffer.scala 340:44] + node _T_1603 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 340:76] + node _T_1604 = and(obuf_merge_en, _T_1603) @[lsu_bus_buffer.scala 340:59] + node _T_1605 = bits(obuf_data1_in, 55, 48) @[lsu_bus_buffer.scala 340:94] + node _T_1606 = bits(obuf_data0_in, 55, 48) @[lsu_bus_buffer.scala 340:123] + node _T_1607 = mux(_T_1604, _T_1605, _T_1606) @[lsu_bus_buffer.scala 340:44] + node _T_1608 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 340:76] + node _T_1609 = and(obuf_merge_en, _T_1608) @[lsu_bus_buffer.scala 340:59] + node _T_1610 = bits(obuf_data1_in, 63, 56) @[lsu_bus_buffer.scala 340:94] + node _T_1611 = bits(obuf_data0_in, 63, 56) @[lsu_bus_buffer.scala 340:123] + node _T_1612 = mux(_T_1609, _T_1610, _T_1611) @[lsu_bus_buffer.scala 340:44] + node _T_1613 = cat(_T_1612, _T_1607) @[Cat.scala 29:58] + node _T_1614 = cat(_T_1613, _T_1602) @[Cat.scala 29:58] + node _T_1615 = cat(_T_1614, _T_1597) @[Cat.scala 29:58] + node _T_1616 = cat(_T_1615, _T_1592) @[Cat.scala 29:58] + node _T_1617 = cat(_T_1616, _T_1587) @[Cat.scala 29:58] + node _T_1618 = cat(_T_1617, _T_1582) @[Cat.scala 29:58] + node obuf_data_in = cat(_T_1618, _T_1577) @[Cat.scala 29:58] + wire buf_dualhi : UInt<1>[4] @[lsu_bus_buffer.scala 342:24] + buf_dualhi[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + node _T_1619 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 344:30] + node _T_1620 = and(_T_1619, found_cmdptr0) @[lsu_bus_buffer.scala 344:43] + node _T_1621 = and(_T_1620, found_cmdptr1) @[lsu_bus_buffer.scala 344:59] + node _T_1622 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1623 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1624 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1625 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1626 = mux(_T_1622, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1627 = mux(_T_1623, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1628 = mux(_T_1624, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1629 = mux(_T_1625, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1630 = or(_T_1626, _T_1627) @[Mux.scala 27:72] + node _T_1631 = or(_T_1630, _T_1628) @[Mux.scala 27:72] + node _T_1632 = or(_T_1631, _T_1629) @[Mux.scala 27:72] + wire _T_1633 : UInt<3> @[Mux.scala 27:72] + _T_1633 <= _T_1632 @[Mux.scala 27:72] + node _T_1634 = eq(_T_1633, UInt<3>("h02")) @[lsu_bus_buffer.scala 344:107] + node _T_1635 = and(_T_1621, _T_1634) @[lsu_bus_buffer.scala 344:75] + node _T_1636 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1637 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1638 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1639 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1640 = mux(_T_1636, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1641 = mux(_T_1637, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1642 = mux(_T_1638, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1643 = mux(_T_1639, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1644 = or(_T_1640, _T_1641) @[Mux.scala 27:72] + node _T_1645 = or(_T_1644, _T_1642) @[Mux.scala 27:72] + node _T_1646 = or(_T_1645, _T_1643) @[Mux.scala 27:72] + wire _T_1647 : UInt<3> @[Mux.scala 27:72] + _T_1647 <= _T_1646 @[Mux.scala 27:72] + node _T_1648 = eq(_T_1647, UInt<3>("h02")) @[lsu_bus_buffer.scala 344:150] + node _T_1649 = and(_T_1635, _T_1648) @[lsu_bus_buffer.scala 344:118] + node _T_1650 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1651 = cat(_T_1650, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1652 = cat(_T_1651, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1653 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1654 = bits(_T_1652, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1655 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1656 = bits(_T_1652, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1657 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1658 = bits(_T_1652, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1659 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1660 = bits(_T_1652, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1661 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1662 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1663 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1664 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1665 = or(_T_1661, _T_1662) @[Mux.scala 27:72] + node _T_1666 = or(_T_1665, _T_1663) @[Mux.scala 27:72] + node _T_1667 = or(_T_1666, _T_1664) @[Mux.scala 27:72] + wire _T_1668 : UInt<1> @[Mux.scala 27:72] + _T_1668 <= _T_1667 @[Mux.scala 27:72] + node _T_1669 = eq(_T_1668, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:5] + node _T_1670 = and(_T_1649, _T_1669) @[lsu_bus_buffer.scala 344:161] + node _T_1671 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1672 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1673 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1674 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1675 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1676 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1677 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1678 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1679 = mux(_T_1671, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1680 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1681 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1682 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1683 = or(_T_1679, _T_1680) @[Mux.scala 27:72] + node _T_1684 = or(_T_1683, _T_1681) @[Mux.scala 27:72] + node _T_1685 = or(_T_1684, _T_1682) @[Mux.scala 27:72] + wire _T_1686 : UInt<1> @[Mux.scala 27:72] + _T_1686 <= _T_1685 @[Mux.scala 27:72] + node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:87] + node _T_1688 = and(_T_1670, _T_1687) @[lsu_bus_buffer.scala 345:85] + node _T_1689 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1690 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1691 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1692 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1693 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1694 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1695 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1696 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1697 = mux(_T_1689, _T_1690, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1698 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1699 = mux(_T_1693, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1700 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1701 = or(_T_1697, _T_1698) @[Mux.scala 27:72] + node _T_1702 = or(_T_1701, _T_1699) @[Mux.scala 27:72] + node _T_1703 = or(_T_1702, _T_1700) @[Mux.scala 27:72] + wire _T_1704 : UInt<1> @[Mux.scala 27:72] + _T_1704 <= _T_1703 @[Mux.scala 27:72] + node _T_1705 = eq(_T_1704, UInt<1>("h00")) @[lsu_bus_buffer.scala 346:6] + node _T_1706 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1707 = cat(_T_1706, buf_dual[1]) @[Cat.scala 29:58] + node _T_1708 = cat(_T_1707, buf_dual[0]) @[Cat.scala 29:58] + node _T_1709 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1710 = bits(_T_1708, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1711 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1712 = bits(_T_1708, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1713 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1714 = bits(_T_1708, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1715 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1716 = bits(_T_1708, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1717 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1718 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1719 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1720 = mux(_T_1715, _T_1716, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1721 = or(_T_1717, _T_1718) @[Mux.scala 27:72] + node _T_1722 = or(_T_1721, _T_1719) @[Mux.scala 27:72] + node _T_1723 = or(_T_1722, _T_1720) @[Mux.scala 27:72] + wire _T_1724 : UInt<1> @[Mux.scala 27:72] + _T_1724 <= _T_1723 @[Mux.scala 27:72] + node _T_1725 = and(_T_1705, _T_1724) @[lsu_bus_buffer.scala 346:36] + node _T_1726 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] + node _T_1727 = cat(_T_1726, buf_dualhi[1]) @[Cat.scala 29:58] + node _T_1728 = cat(_T_1727, buf_dualhi[0]) @[Cat.scala 29:58] + node _T_1729 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1730 = bits(_T_1728, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1731 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1732 = bits(_T_1728, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1733 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1734 = bits(_T_1728, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1735 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1736 = bits(_T_1728, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1737 = mux(_T_1729, _T_1730, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1738 = mux(_T_1731, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1739 = mux(_T_1733, _T_1734, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1740 = mux(_T_1735, _T_1736, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1741 = or(_T_1737, _T_1738) @[Mux.scala 27:72] + node _T_1742 = or(_T_1741, _T_1739) @[Mux.scala 27:72] + node _T_1743 = or(_T_1742, _T_1740) @[Mux.scala 27:72] + wire _T_1744 : UInt<1> @[Mux.scala 27:72] + _T_1744 <= _T_1743 @[Mux.scala 27:72] + node _T_1745 = eq(_T_1744, UInt<1>("h00")) @[lsu_bus_buffer.scala 346:107] + node _T_1746 = and(_T_1725, _T_1745) @[lsu_bus_buffer.scala 346:105] + node _T_1747 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1748 = cat(_T_1747, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1749 = cat(_T_1748, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1750 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1751 = bits(_T_1749, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1752 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1753 = bits(_T_1749, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1754 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1755 = bits(_T_1749, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1756 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1757 = bits(_T_1749, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1758 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1759 = mux(_T_1752, _T_1753, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1760 = mux(_T_1754, _T_1755, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1761 = mux(_T_1756, _T_1757, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = or(_T_1758, _T_1759) @[Mux.scala 27:72] + node _T_1763 = or(_T_1762, _T_1760) @[Mux.scala 27:72] + node _T_1764 = or(_T_1763, _T_1761) @[Mux.scala 27:72] + wire _T_1765 : UInt<1> @[Mux.scala 27:72] + _T_1765 <= _T_1764 @[Mux.scala 27:72] + node _T_1766 = and(_T_1746, _T_1765) @[lsu_bus_buffer.scala 346:177] + node _T_1767 = and(_T_1688, _T_1766) @[lsu_bus_buffer.scala 345:122] + node _T_1768 = and(ibuf_buf_byp, ldst_samedw_r) @[lsu_bus_buffer.scala 347:19] + node _T_1769 = and(_T_1768, io.ldst_dual_r) @[lsu_bus_buffer.scala 347:35] + node _T_1770 = or(_T_1767, _T_1769) @[lsu_bus_buffer.scala 346:250] + obuf_merge_en <= _T_1770 @[lsu_bus_buffer.scala 344:17] + reg obuf_wr_enQ : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + obuf_wr_enQ <= obuf_wr_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1771 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 349:58] + node _T_1772 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 349:93] + node _T_1773 = and(_T_1771, _T_1772) @[lsu_bus_buffer.scala 349:91] + reg _T_1774 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 349:54] + _T_1774 <= _T_1773 @[lsu_bus_buffer.scala 349:54] + obuf_valid <= _T_1774 @[lsu_bus_buffer.scala 349:14] + reg _T_1775 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1775 <= obuf_nosend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_nosend <= _T_1775 @[lsu_bus_buffer.scala 350:15] + reg _T_1776 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_rdrsp_pend_en : @[Reg.scala 28:19] + _T_1776 <= obuf_rdrsp_pend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_rdrsp_pend <= _T_1776 @[lsu_bus_buffer.scala 351:19] + reg _T_1777 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1777 <= obuf_cmd_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_cmd_done <= _T_1777 @[lsu_bus_buffer.scala 352:17] + reg _T_1778 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1778 <= obuf_data_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_data_done <= _T_1778 @[lsu_bus_buffer.scala 353:18] + reg _T_1779 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1779 <= obuf_rdrsp_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_rdrsp_tag <= _T_1779 @[lsu_bus_buffer.scala 354:18] + node _T_1780 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1780 : @[Reg.scala 28:19] + _T_1781 <= obuf_tag0_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_tag0 <= _T_1781 @[lsu_bus_buffer.scala 356:13] + node _T_1782 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_tag1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1782 : @[Reg.scala 28:19] + obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1783 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_merge : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1783 : @[Reg.scala 28:19] + obuf_merge <= obuf_merge_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1784 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1785 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1784 : @[Reg.scala 28:19] + _T_1785 <= obuf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_write <= _T_1785 @[lsu_bus_buffer.scala 359:14] + node _T_1786 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1787 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1786 : @[Reg.scala 28:19] + _T_1787 <= obuf_sideeffect_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_sideeffect <= _T_1787 @[lsu_bus_buffer.scala 360:19] + node _T_1788 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_sz : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1788 : @[Reg.scala 28:19] + obuf_sz <= obuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1789 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_byteen : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1789 : @[Reg.scala 28:19] + obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_2 of rvclkhdr_24 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1790 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1790 <= obuf_addr_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_addr <= _T_1790 @[lsu_bus_buffer.scala 363:13] + inst rvclkhdr_3 of rvclkhdr_25 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg obuf_data : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_data <= obuf_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1791 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1791 <= obuf_data_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_wr_timer <= _T_1791 @[lsu_bus_buffer.scala 365:17] + wire WrPtr0_m : UInt<2> + WrPtr0_m <= UInt<1>("h00") + node _T_1792 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1793 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:30] + node _T_1794 = and(ibuf_valid, _T_1793) @[lsu_bus_buffer.scala 370:19] + node _T_1795 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:18] + node _T_1796 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:57] + node _T_1797 = and(io.ldst_dual_r, _T_1796) @[lsu_bus_buffer.scala 371:45] + node _T_1798 = or(_T_1795, _T_1797) @[lsu_bus_buffer.scala 371:27] + node _T_1799 = and(io.lsu_busreq_r, _T_1798) @[lsu_bus_buffer.scala 370:58] + node _T_1800 = or(_T_1794, _T_1799) @[lsu_bus_buffer.scala 370:39] + node _T_1801 = eq(_T_1800, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1802 = and(_T_1792, _T_1801) @[lsu_bus_buffer.scala 369:76] + node _T_1803 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1804 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 370:30] + node _T_1805 = and(ibuf_valid, _T_1804) @[lsu_bus_buffer.scala 370:19] + node _T_1806 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:18] + node _T_1807 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:57] + node _T_1808 = and(io.ldst_dual_r, _T_1807) @[lsu_bus_buffer.scala 371:45] + node _T_1809 = or(_T_1806, _T_1808) @[lsu_bus_buffer.scala 371:27] + node _T_1810 = and(io.lsu_busreq_r, _T_1809) @[lsu_bus_buffer.scala 370:58] + node _T_1811 = or(_T_1805, _T_1810) @[lsu_bus_buffer.scala 370:39] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1813 = and(_T_1803, _T_1812) @[lsu_bus_buffer.scala 369:76] + node _T_1814 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1815 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 370:30] + node _T_1816 = and(ibuf_valid, _T_1815) @[lsu_bus_buffer.scala 370:19] + node _T_1817 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:18] + node _T_1818 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:57] + node _T_1819 = and(io.ldst_dual_r, _T_1818) @[lsu_bus_buffer.scala 371:45] + node _T_1820 = or(_T_1817, _T_1819) @[lsu_bus_buffer.scala 371:27] + node _T_1821 = and(io.lsu_busreq_r, _T_1820) @[lsu_bus_buffer.scala 370:58] + node _T_1822 = or(_T_1816, _T_1821) @[lsu_bus_buffer.scala 370:39] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1824 = and(_T_1814, _T_1823) @[lsu_bus_buffer.scala 369:76] + node _T_1825 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1826 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 370:30] + node _T_1827 = and(ibuf_valid, _T_1826) @[lsu_bus_buffer.scala 370:19] + node _T_1828 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:18] + node _T_1829 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:57] + node _T_1830 = and(io.ldst_dual_r, _T_1829) @[lsu_bus_buffer.scala 371:45] + node _T_1831 = or(_T_1828, _T_1830) @[lsu_bus_buffer.scala 371:27] + node _T_1832 = and(io.lsu_busreq_r, _T_1831) @[lsu_bus_buffer.scala 370:58] + node _T_1833 = or(_T_1827, _T_1832) @[lsu_bus_buffer.scala 370:39] + node _T_1834 = eq(_T_1833, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1835 = and(_T_1825, _T_1834) @[lsu_bus_buffer.scala 369:76] + node _T_1836 = mux(_T_1835, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1837 = mux(_T_1824, UInt<2>("h02"), _T_1836) @[Mux.scala 98:16] + node _T_1838 = mux(_T_1813, UInt<1>("h01"), _T_1837) @[Mux.scala 98:16] + node _T_1839 = mux(_T_1802, UInt<1>("h00"), _T_1838) @[Mux.scala 98:16] + WrPtr0_m <= _T_1839 @[lsu_bus_buffer.scala 369:12] + wire WrPtr1_m : UInt<2> + WrPtr1_m <= UInt<1>("h00") + node _T_1840 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1841 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:103] + node _T_1842 = and(ibuf_valid, _T_1841) @[lsu_bus_buffer.scala 375:92] + node _T_1843 = eq(WrPtr0_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 376:33] + node _T_1844 = and(io.lsu_busreq_m, _T_1843) @[lsu_bus_buffer.scala 376:22] + node _T_1845 = or(_T_1842, _T_1844) @[lsu_bus_buffer.scala 375:112] + node _T_1846 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:36] + node _T_1847 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:34] + node _T_1848 = and(io.ldst_dual_r, _T_1847) @[lsu_bus_buffer.scala 378:23] + node _T_1849 = or(_T_1846, _T_1848) @[lsu_bus_buffer.scala 377:46] + node _T_1850 = and(io.lsu_busreq_r, _T_1849) @[lsu_bus_buffer.scala 377:22] + node _T_1851 = or(_T_1845, _T_1850) @[lsu_bus_buffer.scala 376:42] + node _T_1852 = eq(_T_1851, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1853 = and(_T_1840, _T_1852) @[lsu_bus_buffer.scala 375:76] + node _T_1854 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1855 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 375:103] + node _T_1856 = and(ibuf_valid, _T_1855) @[lsu_bus_buffer.scala 375:92] + node _T_1857 = eq(WrPtr0_m, UInt<1>("h01")) @[lsu_bus_buffer.scala 376:33] + node _T_1858 = and(io.lsu_busreq_m, _T_1857) @[lsu_bus_buffer.scala 376:22] + node _T_1859 = or(_T_1856, _T_1858) @[lsu_bus_buffer.scala 375:112] + node _T_1860 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 377:36] + node _T_1861 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 378:34] + node _T_1862 = and(io.ldst_dual_r, _T_1861) @[lsu_bus_buffer.scala 378:23] + node _T_1863 = or(_T_1860, _T_1862) @[lsu_bus_buffer.scala 377:46] + node _T_1864 = and(io.lsu_busreq_r, _T_1863) @[lsu_bus_buffer.scala 377:22] + node _T_1865 = or(_T_1859, _T_1864) @[lsu_bus_buffer.scala 376:42] + node _T_1866 = eq(_T_1865, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1867 = and(_T_1854, _T_1866) @[lsu_bus_buffer.scala 375:76] + node _T_1868 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1869 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 375:103] + node _T_1870 = and(ibuf_valid, _T_1869) @[lsu_bus_buffer.scala 375:92] + node _T_1871 = eq(WrPtr0_m, UInt<2>("h02")) @[lsu_bus_buffer.scala 376:33] + node _T_1872 = and(io.lsu_busreq_m, _T_1871) @[lsu_bus_buffer.scala 376:22] + node _T_1873 = or(_T_1870, _T_1872) @[lsu_bus_buffer.scala 375:112] + node _T_1874 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 377:36] + node _T_1875 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 378:34] + node _T_1876 = and(io.ldst_dual_r, _T_1875) @[lsu_bus_buffer.scala 378:23] + node _T_1877 = or(_T_1874, _T_1876) @[lsu_bus_buffer.scala 377:46] + node _T_1878 = and(io.lsu_busreq_r, _T_1877) @[lsu_bus_buffer.scala 377:22] + node _T_1879 = or(_T_1873, _T_1878) @[lsu_bus_buffer.scala 376:42] + node _T_1880 = eq(_T_1879, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1881 = and(_T_1868, _T_1880) @[lsu_bus_buffer.scala 375:76] + node _T_1882 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1883 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 375:103] + node _T_1884 = and(ibuf_valid, _T_1883) @[lsu_bus_buffer.scala 375:92] + node _T_1885 = eq(WrPtr0_m, UInt<2>("h03")) @[lsu_bus_buffer.scala 376:33] + node _T_1886 = and(io.lsu_busreq_m, _T_1885) @[lsu_bus_buffer.scala 376:22] + node _T_1887 = or(_T_1884, _T_1886) @[lsu_bus_buffer.scala 375:112] + node _T_1888 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 377:36] + node _T_1889 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 378:34] + node _T_1890 = and(io.ldst_dual_r, _T_1889) @[lsu_bus_buffer.scala 378:23] + node _T_1891 = or(_T_1888, _T_1890) @[lsu_bus_buffer.scala 377:46] + node _T_1892 = and(io.lsu_busreq_r, _T_1891) @[lsu_bus_buffer.scala 377:22] + node _T_1893 = or(_T_1887, _T_1892) @[lsu_bus_buffer.scala 376:42] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1895 = and(_T_1882, _T_1894) @[lsu_bus_buffer.scala 375:76] + node _T_1896 = mux(_T_1895, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1897 = mux(_T_1881, UInt<2>("h02"), _T_1896) @[Mux.scala 98:16] + node _T_1898 = mux(_T_1867, UInt<1>("h01"), _T_1897) @[Mux.scala 98:16] + node _T_1899 = mux(_T_1853, UInt<1>("h00"), _T_1898) @[Mux.scala 98:16] + WrPtr1_m <= _T_1899 @[lsu_bus_buffer.scala 375:12] + wire buf_age : UInt<4>[4] @[lsu_bus_buffer.scala 380:21] + buf_age[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + node _T_1900 = orr(buf_age[0]) @[lsu_bus_buffer.scala 383:58] + node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1902 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1903 = and(_T_1901, _T_1902) @[lsu_bus_buffer.scala 383:63] + node _T_1904 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1905 = and(_T_1903, _T_1904) @[lsu_bus_buffer.scala 383:88] + node _T_1906 = orr(buf_age[1]) @[lsu_bus_buffer.scala 383:58] + node _T_1907 = eq(_T_1906, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1908 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1909 = and(_T_1907, _T_1908) @[lsu_bus_buffer.scala 383:63] + node _T_1910 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1911 = and(_T_1909, _T_1910) @[lsu_bus_buffer.scala 383:88] + node _T_1912 = orr(buf_age[2]) @[lsu_bus_buffer.scala 383:58] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1914 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1915 = and(_T_1913, _T_1914) @[lsu_bus_buffer.scala 383:63] + node _T_1916 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1917 = and(_T_1915, _T_1916) @[lsu_bus_buffer.scala 383:88] + node _T_1918 = orr(buf_age[3]) @[lsu_bus_buffer.scala 383:58] + node _T_1919 = eq(_T_1918, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1920 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1921 = and(_T_1919, _T_1920) @[lsu_bus_buffer.scala 383:63] + node _T_1922 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1923 = and(_T_1921, _T_1922) @[lsu_bus_buffer.scala 383:88] + node _T_1924 = cat(_T_1923, _T_1917) @[Cat.scala 29:58] + node _T_1925 = cat(_T_1924, _T_1911) @[Cat.scala 29:58] + node CmdPtr0Dec = cat(_T_1925, _T_1905) @[Cat.scala 29:58] + node _T_1926 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1927 = and(buf_age[0], _T_1926) @[lsu_bus_buffer.scala 384:59] + node _T_1928 = orr(_T_1927) @[lsu_bus_buffer.scala 384:76] + node _T_1929 = eq(_T_1928, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1930 = bits(CmdPtr0Dec, 0, 0) @[lsu_bus_buffer.scala 384:94] + node _T_1931 = eq(_T_1930, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1932 = and(_T_1929, _T_1931) @[lsu_bus_buffer.scala 384:81] + node _T_1933 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1934 = and(_T_1932, _T_1933) @[lsu_bus_buffer.scala 384:98] + node _T_1935 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1936 = and(_T_1934, _T_1935) @[lsu_bus_buffer.scala 384:123] + node _T_1937 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1938 = and(buf_age[1], _T_1937) @[lsu_bus_buffer.scala 384:59] + node _T_1939 = orr(_T_1938) @[lsu_bus_buffer.scala 384:76] + node _T_1940 = eq(_T_1939, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1941 = bits(CmdPtr0Dec, 1, 1) @[lsu_bus_buffer.scala 384:94] + node _T_1942 = eq(_T_1941, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1943 = and(_T_1940, _T_1942) @[lsu_bus_buffer.scala 384:81] + node _T_1944 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1945 = and(_T_1943, _T_1944) @[lsu_bus_buffer.scala 384:98] + node _T_1946 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1947 = and(_T_1945, _T_1946) @[lsu_bus_buffer.scala 384:123] + node _T_1948 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1949 = and(buf_age[2], _T_1948) @[lsu_bus_buffer.scala 384:59] + node _T_1950 = orr(_T_1949) @[lsu_bus_buffer.scala 384:76] + node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1952 = bits(CmdPtr0Dec, 2, 2) @[lsu_bus_buffer.scala 384:94] + node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1954 = and(_T_1951, _T_1953) @[lsu_bus_buffer.scala 384:81] + node _T_1955 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1956 = and(_T_1954, _T_1955) @[lsu_bus_buffer.scala 384:98] + node _T_1957 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1958 = and(_T_1956, _T_1957) @[lsu_bus_buffer.scala 384:123] + node _T_1959 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1960 = and(buf_age[3], _T_1959) @[lsu_bus_buffer.scala 384:59] + node _T_1961 = orr(_T_1960) @[lsu_bus_buffer.scala 384:76] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1963 = bits(CmdPtr0Dec, 3, 3) @[lsu_bus_buffer.scala 384:94] + node _T_1964 = eq(_T_1963, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1965 = and(_T_1962, _T_1964) @[lsu_bus_buffer.scala 384:81] + node _T_1966 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1967 = and(_T_1965, _T_1966) @[lsu_bus_buffer.scala 384:98] + node _T_1968 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1969 = and(_T_1967, _T_1968) @[lsu_bus_buffer.scala 384:123] + node _T_1970 = cat(_T_1969, _T_1958) @[Cat.scala 29:58] + node _T_1971 = cat(_T_1970, _T_1947) @[Cat.scala 29:58] + node CmdPtr1Dec = cat(_T_1971, _T_1936) @[Cat.scala 29:58] + wire buf_rsp_pickage : UInt<4>[4] @[lsu_bus_buffer.scala 385:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + node _T_1972 = orr(buf_rsp_pickage[0]) @[lsu_bus_buffer.scala 387:65] + node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1974 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1975 = and(_T_1973, _T_1974) @[lsu_bus_buffer.scala 387:70] + node _T_1976 = orr(buf_rsp_pickage[1]) @[lsu_bus_buffer.scala 387:65] + node _T_1977 = eq(_T_1976, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1978 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1979 = and(_T_1977, _T_1978) @[lsu_bus_buffer.scala 387:70] + node _T_1980 = orr(buf_rsp_pickage[2]) @[lsu_bus_buffer.scala 387:65] + node _T_1981 = eq(_T_1980, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1982 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1983 = and(_T_1981, _T_1982) @[lsu_bus_buffer.scala 387:70] + node _T_1984 = orr(buf_rsp_pickage[3]) @[lsu_bus_buffer.scala 387:65] + node _T_1985 = eq(_T_1984, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1986 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1987 = and(_T_1985, _T_1986) @[lsu_bus_buffer.scala 387:70] + node _T_1988 = cat(_T_1987, _T_1983) @[Cat.scala 29:58] + node _T_1989 = cat(_T_1988, _T_1979) @[Cat.scala 29:58] + node RspPtrDec = cat(_T_1989, _T_1975) @[Cat.scala 29:58] + node _T_1990 = orr(CmdPtr0Dec) @[lsu_bus_buffer.scala 388:31] + found_cmdptr0 <= _T_1990 @[lsu_bus_buffer.scala 388:17] + node _T_1991 = orr(CmdPtr1Dec) @[lsu_bus_buffer.scala 389:31] + found_cmdptr1 <= _T_1991 @[lsu_bus_buffer.scala 389:17] + wire RspPtr : UInt<2> + RspPtr <= UInt<1>("h00") + node _T_1992 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1993 = cat(_T_1992, CmdPtr0Dec) @[Cat.scala 29:58] + node _T_1994 = bits(_T_1993, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_1995 = bits(_T_1993, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_1996 = or(_T_1994, _T_1995) @[lsu_bus_buffer.scala 391:42] + node _T_1997 = bits(_T_1993, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_1998 = or(_T_1996, _T_1997) @[lsu_bus_buffer.scala 391:48] + node _T_1999 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2000 = or(_T_1998, _T_1999) @[lsu_bus_buffer.scala 391:54] + node _T_2001 = bits(_T_1993, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2002 = bits(_T_1993, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2003 = or(_T_2001, _T_2002) @[lsu_bus_buffer.scala 391:67] + node _T_2004 = bits(_T_1993, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2005 = or(_T_2003, _T_2004) @[lsu_bus_buffer.scala 391:73] + node _T_2006 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2007 = or(_T_2005, _T_2006) @[lsu_bus_buffer.scala 391:79] + node _T_2008 = bits(_T_1993, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2009 = bits(_T_1993, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2010 = or(_T_2008, _T_2009) @[lsu_bus_buffer.scala 391:92] + node _T_2011 = bits(_T_1993, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2012 = or(_T_2010, _T_2011) @[lsu_bus_buffer.scala 391:98] + node _T_2013 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2014 = or(_T_2012, _T_2013) @[lsu_bus_buffer.scala 391:104] + node _T_2015 = cat(_T_2000, _T_2007) @[Cat.scala 29:58] + node _T_2016 = cat(_T_2015, _T_2014) @[Cat.scala 29:58] + CmdPtr0 <= _T_2016 @[lsu_bus_buffer.scala 396:11] + node _T_2017 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2018 = cat(_T_2017, CmdPtr1Dec) @[Cat.scala 29:58] + node _T_2019 = bits(_T_2018, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_2020 = bits(_T_2018, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_2021 = or(_T_2019, _T_2020) @[lsu_bus_buffer.scala 391:42] + node _T_2022 = bits(_T_2018, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_2023 = or(_T_2021, _T_2022) @[lsu_bus_buffer.scala 391:48] + node _T_2024 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2025 = or(_T_2023, _T_2024) @[lsu_bus_buffer.scala 391:54] + node _T_2026 = bits(_T_2018, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2027 = bits(_T_2018, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2028 = or(_T_2026, _T_2027) @[lsu_bus_buffer.scala 391:67] + node _T_2029 = bits(_T_2018, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2030 = or(_T_2028, _T_2029) @[lsu_bus_buffer.scala 391:73] + node _T_2031 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2032 = or(_T_2030, _T_2031) @[lsu_bus_buffer.scala 391:79] + node _T_2033 = bits(_T_2018, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2034 = bits(_T_2018, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2035 = or(_T_2033, _T_2034) @[lsu_bus_buffer.scala 391:92] + node _T_2036 = bits(_T_2018, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2037 = or(_T_2035, _T_2036) @[lsu_bus_buffer.scala 391:98] + node _T_2038 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2039 = or(_T_2037, _T_2038) @[lsu_bus_buffer.scala 391:104] + node _T_2040 = cat(_T_2025, _T_2032) @[Cat.scala 29:58] + node _T_2041 = cat(_T_2040, _T_2039) @[Cat.scala 29:58] + CmdPtr1 <= _T_2041 @[lsu_bus_buffer.scala 398:11] + node _T_2042 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2043 = cat(_T_2042, RspPtrDec) @[Cat.scala 29:58] + node _T_2044 = bits(_T_2043, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_2045 = bits(_T_2043, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_2046 = or(_T_2044, _T_2045) @[lsu_bus_buffer.scala 391:42] + node _T_2047 = bits(_T_2043, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_2048 = or(_T_2046, _T_2047) @[lsu_bus_buffer.scala 391:48] + node _T_2049 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2050 = or(_T_2048, _T_2049) @[lsu_bus_buffer.scala 391:54] + node _T_2051 = bits(_T_2043, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2052 = bits(_T_2043, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2053 = or(_T_2051, _T_2052) @[lsu_bus_buffer.scala 391:67] + node _T_2054 = bits(_T_2043, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2055 = or(_T_2053, _T_2054) @[lsu_bus_buffer.scala 391:73] + node _T_2056 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2057 = or(_T_2055, _T_2056) @[lsu_bus_buffer.scala 391:79] + node _T_2058 = bits(_T_2043, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2059 = bits(_T_2043, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2060 = or(_T_2058, _T_2059) @[lsu_bus_buffer.scala 391:92] + node _T_2061 = bits(_T_2043, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2062 = or(_T_2060, _T_2061) @[lsu_bus_buffer.scala 391:98] + node _T_2063 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2064 = or(_T_2062, _T_2063) @[lsu_bus_buffer.scala 391:104] + node _T_2065 = cat(_T_2050, _T_2057) @[Cat.scala 29:58] + node _T_2066 = cat(_T_2065, _T_2064) @[Cat.scala 29:58] + RspPtr <= _T_2066 @[lsu_bus_buffer.scala 399:10] + wire buf_state_en : UInt<1>[4] @[lsu_bus_buffer.scala 400:26] + buf_state_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + wire buf_rspageQ : UInt<4>[4] @[lsu_bus_buffer.scala 402:25] + buf_rspageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + wire buf_rspage_set : UInt<4>[4] @[lsu_bus_buffer.scala 404:28] + buf_rspage_set[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + wire buf_rspage_in : UInt<4>[4] @[lsu_bus_buffer.scala 406:27] + buf_rspage_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + wire buf_rspage : UInt<4>[4] @[lsu_bus_buffer.scala 408:24] + buf_rspage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + node _T_2067 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2068 = and(_T_2067, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2069 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2070 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2071 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2072 = and(_T_2070, _T_2071) @[lsu_bus_buffer.scala 412:57] + node _T_2073 = or(_T_2069, _T_2072) @[lsu_bus_buffer.scala 412:31] + node _T_2074 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2075 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2076 = and(_T_2074, _T_2075) @[lsu_bus_buffer.scala 413:41] + node _T_2077 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2078 = and(_T_2076, _T_2077) @[lsu_bus_buffer.scala 413:71] + node _T_2079 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2080 = and(_T_2078, _T_2079) @[lsu_bus_buffer.scala 413:92] + node _T_2081 = or(_T_2073, _T_2080) @[lsu_bus_buffer.scala 412:86] + node _T_2082 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2083 = and(_T_2082, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2084 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2085 = and(_T_2083, _T_2084) @[lsu_bus_buffer.scala 414:52] + node _T_2086 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2087 = and(_T_2085, _T_2086) @[lsu_bus_buffer.scala 414:73] + node _T_2088 = or(_T_2081, _T_2087) @[lsu_bus_buffer.scala 413:114] + node _T_2089 = and(_T_2068, _T_2088) @[lsu_bus_buffer.scala 411:113] + node _T_2090 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2091 = or(_T_2089, _T_2090) @[lsu_bus_buffer.scala 414:97] + node _T_2092 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2093 = and(_T_2092, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2094 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2095 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2096 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2097 = and(_T_2095, _T_2096) @[lsu_bus_buffer.scala 412:57] + node _T_2098 = or(_T_2094, _T_2097) @[lsu_bus_buffer.scala 412:31] + node _T_2099 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2100 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2101 = and(_T_2099, _T_2100) @[lsu_bus_buffer.scala 413:41] + node _T_2102 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2103 = and(_T_2101, _T_2102) @[lsu_bus_buffer.scala 413:71] + node _T_2104 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2105 = and(_T_2103, _T_2104) @[lsu_bus_buffer.scala 413:92] + node _T_2106 = or(_T_2098, _T_2105) @[lsu_bus_buffer.scala 412:86] + node _T_2107 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2108 = and(_T_2107, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2109 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2110 = and(_T_2108, _T_2109) @[lsu_bus_buffer.scala 414:52] + node _T_2111 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2112 = and(_T_2110, _T_2111) @[lsu_bus_buffer.scala 414:73] + node _T_2113 = or(_T_2106, _T_2112) @[lsu_bus_buffer.scala 413:114] + node _T_2114 = and(_T_2093, _T_2113) @[lsu_bus_buffer.scala 411:113] + node _T_2115 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2116 = or(_T_2114, _T_2115) @[lsu_bus_buffer.scala 414:97] + node _T_2117 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2118 = and(_T_2117, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2119 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2120 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2121 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2122 = and(_T_2120, _T_2121) @[lsu_bus_buffer.scala 412:57] + node _T_2123 = or(_T_2119, _T_2122) @[lsu_bus_buffer.scala 412:31] + node _T_2124 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2125 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2126 = and(_T_2124, _T_2125) @[lsu_bus_buffer.scala 413:41] + node _T_2127 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2128 = and(_T_2126, _T_2127) @[lsu_bus_buffer.scala 413:71] + node _T_2129 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2130 = and(_T_2128, _T_2129) @[lsu_bus_buffer.scala 413:92] + node _T_2131 = or(_T_2123, _T_2130) @[lsu_bus_buffer.scala 412:86] + node _T_2132 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2133 = and(_T_2132, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2134 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2135 = and(_T_2133, _T_2134) @[lsu_bus_buffer.scala 414:52] + node _T_2136 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2137 = and(_T_2135, _T_2136) @[lsu_bus_buffer.scala 414:73] + node _T_2138 = or(_T_2131, _T_2137) @[lsu_bus_buffer.scala 413:114] + node _T_2139 = and(_T_2118, _T_2138) @[lsu_bus_buffer.scala 411:113] + node _T_2140 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2141 = or(_T_2139, _T_2140) @[lsu_bus_buffer.scala 414:97] + node _T_2142 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2143 = and(_T_2142, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2144 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2145 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2146 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2147 = and(_T_2145, _T_2146) @[lsu_bus_buffer.scala 412:57] + node _T_2148 = or(_T_2144, _T_2147) @[lsu_bus_buffer.scala 412:31] + node _T_2149 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2150 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2151 = and(_T_2149, _T_2150) @[lsu_bus_buffer.scala 413:41] + node _T_2152 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2153 = and(_T_2151, _T_2152) @[lsu_bus_buffer.scala 413:71] + node _T_2154 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2155 = and(_T_2153, _T_2154) @[lsu_bus_buffer.scala 413:92] + node _T_2156 = or(_T_2148, _T_2155) @[lsu_bus_buffer.scala 412:86] + node _T_2157 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2158 = and(_T_2157, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2159 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2160 = and(_T_2158, _T_2159) @[lsu_bus_buffer.scala 414:52] + node _T_2161 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2162 = and(_T_2160, _T_2161) @[lsu_bus_buffer.scala 414:73] + node _T_2163 = or(_T_2156, _T_2162) @[lsu_bus_buffer.scala 413:114] + node _T_2164 = and(_T_2143, _T_2163) @[lsu_bus_buffer.scala 411:113] + node _T_2165 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2166 = or(_T_2164, _T_2165) @[lsu_bus_buffer.scala 414:97] + node _T_2167 = cat(_T_2166, _T_2141) @[Cat.scala 29:58] + node _T_2168 = cat(_T_2167, _T_2116) @[Cat.scala 29:58] + node buf_age_in_0 = cat(_T_2168, _T_2091) @[Cat.scala 29:58] + node _T_2169 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2170 = and(_T_2169, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2171 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2172 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2173 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2174 = and(_T_2172, _T_2173) @[lsu_bus_buffer.scala 412:57] + node _T_2175 = or(_T_2171, _T_2174) @[lsu_bus_buffer.scala 412:31] + node _T_2176 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2177 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2178 = and(_T_2176, _T_2177) @[lsu_bus_buffer.scala 413:41] + node _T_2179 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2180 = and(_T_2178, _T_2179) @[lsu_bus_buffer.scala 413:71] + node _T_2181 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2182 = and(_T_2180, _T_2181) @[lsu_bus_buffer.scala 413:92] + node _T_2183 = or(_T_2175, _T_2182) @[lsu_bus_buffer.scala 412:86] + node _T_2184 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2185 = and(_T_2184, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2186 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2187 = and(_T_2185, _T_2186) @[lsu_bus_buffer.scala 414:52] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2189 = and(_T_2187, _T_2188) @[lsu_bus_buffer.scala 414:73] + node _T_2190 = or(_T_2183, _T_2189) @[lsu_bus_buffer.scala 413:114] + node _T_2191 = and(_T_2170, _T_2190) @[lsu_bus_buffer.scala 411:113] + node _T_2192 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2193 = or(_T_2191, _T_2192) @[lsu_bus_buffer.scala 414:97] + node _T_2194 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2195 = and(_T_2194, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2196 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2197 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2198 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2199 = and(_T_2197, _T_2198) @[lsu_bus_buffer.scala 412:57] + node _T_2200 = or(_T_2196, _T_2199) @[lsu_bus_buffer.scala 412:31] + node _T_2201 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2202 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2203 = and(_T_2201, _T_2202) @[lsu_bus_buffer.scala 413:41] + node _T_2204 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2205 = and(_T_2203, _T_2204) @[lsu_bus_buffer.scala 413:71] + node _T_2206 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2207 = and(_T_2205, _T_2206) @[lsu_bus_buffer.scala 413:92] + node _T_2208 = or(_T_2200, _T_2207) @[lsu_bus_buffer.scala 412:86] + node _T_2209 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2210 = and(_T_2209, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2211 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2212 = and(_T_2210, _T_2211) @[lsu_bus_buffer.scala 414:52] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2214 = and(_T_2212, _T_2213) @[lsu_bus_buffer.scala 414:73] + node _T_2215 = or(_T_2208, _T_2214) @[lsu_bus_buffer.scala 413:114] + node _T_2216 = and(_T_2195, _T_2215) @[lsu_bus_buffer.scala 411:113] + node _T_2217 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2218 = or(_T_2216, _T_2217) @[lsu_bus_buffer.scala 414:97] + node _T_2219 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2220 = and(_T_2219, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2221 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2222 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2223 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2224 = and(_T_2222, _T_2223) @[lsu_bus_buffer.scala 412:57] + node _T_2225 = or(_T_2221, _T_2224) @[lsu_bus_buffer.scala 412:31] + node _T_2226 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2227 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2228 = and(_T_2226, _T_2227) @[lsu_bus_buffer.scala 413:41] + node _T_2229 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2230 = and(_T_2228, _T_2229) @[lsu_bus_buffer.scala 413:71] + node _T_2231 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2232 = and(_T_2230, _T_2231) @[lsu_bus_buffer.scala 413:92] + node _T_2233 = or(_T_2225, _T_2232) @[lsu_bus_buffer.scala 412:86] + node _T_2234 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2235 = and(_T_2234, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2236 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2237 = and(_T_2235, _T_2236) @[lsu_bus_buffer.scala 414:52] + node _T_2238 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2239 = and(_T_2237, _T_2238) @[lsu_bus_buffer.scala 414:73] + node _T_2240 = or(_T_2233, _T_2239) @[lsu_bus_buffer.scala 413:114] + node _T_2241 = and(_T_2220, _T_2240) @[lsu_bus_buffer.scala 411:113] + node _T_2242 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2243 = or(_T_2241, _T_2242) @[lsu_bus_buffer.scala 414:97] + node _T_2244 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2245 = and(_T_2244, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2246 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2247 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2248 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2249 = and(_T_2247, _T_2248) @[lsu_bus_buffer.scala 412:57] + node _T_2250 = or(_T_2246, _T_2249) @[lsu_bus_buffer.scala 412:31] + node _T_2251 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2252 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2253 = and(_T_2251, _T_2252) @[lsu_bus_buffer.scala 413:41] + node _T_2254 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2255 = and(_T_2253, _T_2254) @[lsu_bus_buffer.scala 413:71] + node _T_2256 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2257 = and(_T_2255, _T_2256) @[lsu_bus_buffer.scala 413:92] + node _T_2258 = or(_T_2250, _T_2257) @[lsu_bus_buffer.scala 412:86] + node _T_2259 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2260 = and(_T_2259, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2261 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2262 = and(_T_2260, _T_2261) @[lsu_bus_buffer.scala 414:52] + node _T_2263 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2264 = and(_T_2262, _T_2263) @[lsu_bus_buffer.scala 414:73] + node _T_2265 = or(_T_2258, _T_2264) @[lsu_bus_buffer.scala 413:114] + node _T_2266 = and(_T_2245, _T_2265) @[lsu_bus_buffer.scala 411:113] + node _T_2267 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2268 = or(_T_2266, _T_2267) @[lsu_bus_buffer.scala 414:97] + node _T_2269 = cat(_T_2268, _T_2243) @[Cat.scala 29:58] + node _T_2270 = cat(_T_2269, _T_2218) @[Cat.scala 29:58] + node buf_age_in_1 = cat(_T_2270, _T_2193) @[Cat.scala 29:58] + node _T_2271 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2272 = and(_T_2271, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2273 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2274 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2275 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2276 = and(_T_2274, _T_2275) @[lsu_bus_buffer.scala 412:57] + node _T_2277 = or(_T_2273, _T_2276) @[lsu_bus_buffer.scala 412:31] + node _T_2278 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2279 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2280 = and(_T_2278, _T_2279) @[lsu_bus_buffer.scala 413:41] + node _T_2281 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2282 = and(_T_2280, _T_2281) @[lsu_bus_buffer.scala 413:71] + node _T_2283 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2284 = and(_T_2282, _T_2283) @[lsu_bus_buffer.scala 413:92] + node _T_2285 = or(_T_2277, _T_2284) @[lsu_bus_buffer.scala 412:86] + node _T_2286 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2287 = and(_T_2286, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2288 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2289 = and(_T_2287, _T_2288) @[lsu_bus_buffer.scala 414:52] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2291 = and(_T_2289, _T_2290) @[lsu_bus_buffer.scala 414:73] + node _T_2292 = or(_T_2285, _T_2291) @[lsu_bus_buffer.scala 413:114] + node _T_2293 = and(_T_2272, _T_2292) @[lsu_bus_buffer.scala 411:113] + node _T_2294 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2295 = or(_T_2293, _T_2294) @[lsu_bus_buffer.scala 414:97] + node _T_2296 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2297 = and(_T_2296, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2298 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2299 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2300 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2301 = and(_T_2299, _T_2300) @[lsu_bus_buffer.scala 412:57] + node _T_2302 = or(_T_2298, _T_2301) @[lsu_bus_buffer.scala 412:31] + node _T_2303 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2304 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2305 = and(_T_2303, _T_2304) @[lsu_bus_buffer.scala 413:41] + node _T_2306 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2307 = and(_T_2305, _T_2306) @[lsu_bus_buffer.scala 413:71] + node _T_2308 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2309 = and(_T_2307, _T_2308) @[lsu_bus_buffer.scala 413:92] + node _T_2310 = or(_T_2302, _T_2309) @[lsu_bus_buffer.scala 412:86] + node _T_2311 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2312 = and(_T_2311, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2313 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2314 = and(_T_2312, _T_2313) @[lsu_bus_buffer.scala 414:52] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2316 = and(_T_2314, _T_2315) @[lsu_bus_buffer.scala 414:73] + node _T_2317 = or(_T_2310, _T_2316) @[lsu_bus_buffer.scala 413:114] + node _T_2318 = and(_T_2297, _T_2317) @[lsu_bus_buffer.scala 411:113] + node _T_2319 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2320 = or(_T_2318, _T_2319) @[lsu_bus_buffer.scala 414:97] + node _T_2321 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2322 = and(_T_2321, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2323 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2324 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2325 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2326 = and(_T_2324, _T_2325) @[lsu_bus_buffer.scala 412:57] + node _T_2327 = or(_T_2323, _T_2326) @[lsu_bus_buffer.scala 412:31] + node _T_2328 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2329 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2330 = and(_T_2328, _T_2329) @[lsu_bus_buffer.scala 413:41] + node _T_2331 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2332 = and(_T_2330, _T_2331) @[lsu_bus_buffer.scala 413:71] + node _T_2333 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2334 = and(_T_2332, _T_2333) @[lsu_bus_buffer.scala 413:92] + node _T_2335 = or(_T_2327, _T_2334) @[lsu_bus_buffer.scala 412:86] + node _T_2336 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2337 = and(_T_2336, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2338 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2339 = and(_T_2337, _T_2338) @[lsu_bus_buffer.scala 414:52] + node _T_2340 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2341 = and(_T_2339, _T_2340) @[lsu_bus_buffer.scala 414:73] + node _T_2342 = or(_T_2335, _T_2341) @[lsu_bus_buffer.scala 413:114] + node _T_2343 = and(_T_2322, _T_2342) @[lsu_bus_buffer.scala 411:113] + node _T_2344 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2345 = or(_T_2343, _T_2344) @[lsu_bus_buffer.scala 414:97] + node _T_2346 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2347 = and(_T_2346, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2348 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2349 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2350 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2351 = and(_T_2349, _T_2350) @[lsu_bus_buffer.scala 412:57] + node _T_2352 = or(_T_2348, _T_2351) @[lsu_bus_buffer.scala 412:31] + node _T_2353 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2354 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2355 = and(_T_2353, _T_2354) @[lsu_bus_buffer.scala 413:41] + node _T_2356 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2357 = and(_T_2355, _T_2356) @[lsu_bus_buffer.scala 413:71] + node _T_2358 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2359 = and(_T_2357, _T_2358) @[lsu_bus_buffer.scala 413:92] + node _T_2360 = or(_T_2352, _T_2359) @[lsu_bus_buffer.scala 412:86] + node _T_2361 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2362 = and(_T_2361, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2363 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2364 = and(_T_2362, _T_2363) @[lsu_bus_buffer.scala 414:52] + node _T_2365 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2366 = and(_T_2364, _T_2365) @[lsu_bus_buffer.scala 414:73] + node _T_2367 = or(_T_2360, _T_2366) @[lsu_bus_buffer.scala 413:114] + node _T_2368 = and(_T_2347, _T_2367) @[lsu_bus_buffer.scala 411:113] + node _T_2369 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2370 = or(_T_2368, _T_2369) @[lsu_bus_buffer.scala 414:97] + node _T_2371 = cat(_T_2370, _T_2345) @[Cat.scala 29:58] + node _T_2372 = cat(_T_2371, _T_2320) @[Cat.scala 29:58] + node buf_age_in_2 = cat(_T_2372, _T_2295) @[Cat.scala 29:58] + node _T_2373 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2374 = and(_T_2373, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2375 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2376 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2377 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2378 = and(_T_2376, _T_2377) @[lsu_bus_buffer.scala 412:57] + node _T_2379 = or(_T_2375, _T_2378) @[lsu_bus_buffer.scala 412:31] + node _T_2380 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2381 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2382 = and(_T_2380, _T_2381) @[lsu_bus_buffer.scala 413:41] + node _T_2383 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2384 = and(_T_2382, _T_2383) @[lsu_bus_buffer.scala 413:71] + node _T_2385 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2386 = and(_T_2384, _T_2385) @[lsu_bus_buffer.scala 413:92] + node _T_2387 = or(_T_2379, _T_2386) @[lsu_bus_buffer.scala 412:86] + node _T_2388 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2389 = and(_T_2388, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2390 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2391 = and(_T_2389, _T_2390) @[lsu_bus_buffer.scala 414:52] + node _T_2392 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2393 = and(_T_2391, _T_2392) @[lsu_bus_buffer.scala 414:73] + node _T_2394 = or(_T_2387, _T_2393) @[lsu_bus_buffer.scala 413:114] + node _T_2395 = and(_T_2374, _T_2394) @[lsu_bus_buffer.scala 411:113] + node _T_2396 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2397 = or(_T_2395, _T_2396) @[lsu_bus_buffer.scala 414:97] + node _T_2398 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2399 = and(_T_2398, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2400 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2401 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2402 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2403 = and(_T_2401, _T_2402) @[lsu_bus_buffer.scala 412:57] + node _T_2404 = or(_T_2400, _T_2403) @[lsu_bus_buffer.scala 412:31] + node _T_2405 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2406 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2407 = and(_T_2405, _T_2406) @[lsu_bus_buffer.scala 413:41] + node _T_2408 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2409 = and(_T_2407, _T_2408) @[lsu_bus_buffer.scala 413:71] + node _T_2410 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2411 = and(_T_2409, _T_2410) @[lsu_bus_buffer.scala 413:92] + node _T_2412 = or(_T_2404, _T_2411) @[lsu_bus_buffer.scala 412:86] + node _T_2413 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2414 = and(_T_2413, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2415 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2416 = and(_T_2414, _T_2415) @[lsu_bus_buffer.scala 414:52] + node _T_2417 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2418 = and(_T_2416, _T_2417) @[lsu_bus_buffer.scala 414:73] + node _T_2419 = or(_T_2412, _T_2418) @[lsu_bus_buffer.scala 413:114] + node _T_2420 = and(_T_2399, _T_2419) @[lsu_bus_buffer.scala 411:113] + node _T_2421 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2422 = or(_T_2420, _T_2421) @[lsu_bus_buffer.scala 414:97] + node _T_2423 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2424 = and(_T_2423, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2425 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2426 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2427 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2428 = and(_T_2426, _T_2427) @[lsu_bus_buffer.scala 412:57] + node _T_2429 = or(_T_2425, _T_2428) @[lsu_bus_buffer.scala 412:31] + node _T_2430 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2431 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2432 = and(_T_2430, _T_2431) @[lsu_bus_buffer.scala 413:41] + node _T_2433 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2434 = and(_T_2432, _T_2433) @[lsu_bus_buffer.scala 413:71] + node _T_2435 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2436 = and(_T_2434, _T_2435) @[lsu_bus_buffer.scala 413:92] + node _T_2437 = or(_T_2429, _T_2436) @[lsu_bus_buffer.scala 412:86] + node _T_2438 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2439 = and(_T_2438, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2440 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2441 = and(_T_2439, _T_2440) @[lsu_bus_buffer.scala 414:52] + node _T_2442 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2443 = and(_T_2441, _T_2442) @[lsu_bus_buffer.scala 414:73] + node _T_2444 = or(_T_2437, _T_2443) @[lsu_bus_buffer.scala 413:114] + node _T_2445 = and(_T_2424, _T_2444) @[lsu_bus_buffer.scala 411:113] + node _T_2446 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2447 = or(_T_2445, _T_2446) @[lsu_bus_buffer.scala 414:97] + node _T_2448 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2449 = and(_T_2448, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2450 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2451 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2452 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2453 = and(_T_2451, _T_2452) @[lsu_bus_buffer.scala 412:57] + node _T_2454 = or(_T_2450, _T_2453) @[lsu_bus_buffer.scala 412:31] + node _T_2455 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2456 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2457 = and(_T_2455, _T_2456) @[lsu_bus_buffer.scala 413:41] + node _T_2458 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2459 = and(_T_2457, _T_2458) @[lsu_bus_buffer.scala 413:71] + node _T_2460 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2461 = and(_T_2459, _T_2460) @[lsu_bus_buffer.scala 413:92] + node _T_2462 = or(_T_2454, _T_2461) @[lsu_bus_buffer.scala 412:86] + node _T_2463 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2464 = and(_T_2463, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2465 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2466 = and(_T_2464, _T_2465) @[lsu_bus_buffer.scala 414:52] + node _T_2467 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2468 = and(_T_2466, _T_2467) @[lsu_bus_buffer.scala 414:73] + node _T_2469 = or(_T_2462, _T_2468) @[lsu_bus_buffer.scala 413:114] + node _T_2470 = and(_T_2449, _T_2469) @[lsu_bus_buffer.scala 411:113] + node _T_2471 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2472 = or(_T_2470, _T_2471) @[lsu_bus_buffer.scala 414:97] + node _T_2473 = cat(_T_2472, _T_2447) @[Cat.scala 29:58] + node _T_2474 = cat(_T_2473, _T_2422) @[Cat.scala 29:58] + node buf_age_in_3 = cat(_T_2474, _T_2397) @[Cat.scala 29:58] + wire buf_ageQ : UInt<4>[4] @[lsu_bus_buffer.scala 415:22] + buf_ageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + node _T_2475 = bits(buf_ageQ[0], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2476 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2477 = and(_T_2476, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2478 = eq(_T_2477, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2479 = and(_T_2475, _T_2478) @[lsu_bus_buffer.scala 417:76] + node _T_2480 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2481 = and(_T_2479, _T_2480) @[lsu_bus_buffer.scala 417:130] + node _T_2482 = bits(buf_ageQ[0], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2483 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2484 = and(_T_2483, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2485 = eq(_T_2484, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2486 = and(_T_2482, _T_2485) @[lsu_bus_buffer.scala 417:76] + node _T_2487 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2488 = and(_T_2486, _T_2487) @[lsu_bus_buffer.scala 417:130] + node _T_2489 = bits(buf_ageQ[0], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2490 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2491 = and(_T_2490, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2492 = eq(_T_2491, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2493 = and(_T_2489, _T_2492) @[lsu_bus_buffer.scala 417:76] + node _T_2494 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2495 = and(_T_2493, _T_2494) @[lsu_bus_buffer.scala 417:130] + node _T_2496 = bits(buf_ageQ[0], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2497 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2498 = and(_T_2497, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2499 = eq(_T_2498, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2500 = and(_T_2496, _T_2499) @[lsu_bus_buffer.scala 417:76] + node _T_2501 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2502 = and(_T_2500, _T_2501) @[lsu_bus_buffer.scala 417:130] + node _T_2503 = cat(_T_2502, _T_2495) @[Cat.scala 29:58] + node _T_2504 = cat(_T_2503, _T_2488) @[Cat.scala 29:58] + node _T_2505 = cat(_T_2504, _T_2481) @[Cat.scala 29:58] + node _T_2506 = bits(buf_ageQ[1], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2507 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2508 = and(_T_2507, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2509 = eq(_T_2508, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2510 = and(_T_2506, _T_2509) @[lsu_bus_buffer.scala 417:76] + node _T_2511 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2512 = and(_T_2510, _T_2511) @[lsu_bus_buffer.scala 417:130] + node _T_2513 = bits(buf_ageQ[1], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2514 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2515 = and(_T_2514, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2516 = eq(_T_2515, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2517 = and(_T_2513, _T_2516) @[lsu_bus_buffer.scala 417:76] + node _T_2518 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2519 = and(_T_2517, _T_2518) @[lsu_bus_buffer.scala 417:130] + node _T_2520 = bits(buf_ageQ[1], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2521 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2522 = and(_T_2521, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2523 = eq(_T_2522, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2524 = and(_T_2520, _T_2523) @[lsu_bus_buffer.scala 417:76] + node _T_2525 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2526 = and(_T_2524, _T_2525) @[lsu_bus_buffer.scala 417:130] + node _T_2527 = bits(buf_ageQ[1], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2528 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2529 = and(_T_2528, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2530 = eq(_T_2529, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2531 = and(_T_2527, _T_2530) @[lsu_bus_buffer.scala 417:76] + node _T_2532 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2533 = and(_T_2531, _T_2532) @[lsu_bus_buffer.scala 417:130] + node _T_2534 = cat(_T_2533, _T_2526) @[Cat.scala 29:58] + node _T_2535 = cat(_T_2534, _T_2519) @[Cat.scala 29:58] + node _T_2536 = cat(_T_2535, _T_2512) @[Cat.scala 29:58] + node _T_2537 = bits(buf_ageQ[2], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2538 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2539 = and(_T_2538, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2540 = eq(_T_2539, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2541 = and(_T_2537, _T_2540) @[lsu_bus_buffer.scala 417:76] + node _T_2542 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2543 = and(_T_2541, _T_2542) @[lsu_bus_buffer.scala 417:130] + node _T_2544 = bits(buf_ageQ[2], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2545 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2546 = and(_T_2545, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2547 = eq(_T_2546, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2548 = and(_T_2544, _T_2547) @[lsu_bus_buffer.scala 417:76] + node _T_2549 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2550 = and(_T_2548, _T_2549) @[lsu_bus_buffer.scala 417:130] + node _T_2551 = bits(buf_ageQ[2], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2552 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2555 = and(_T_2551, _T_2554) @[lsu_bus_buffer.scala 417:76] + node _T_2556 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2557 = and(_T_2555, _T_2556) @[lsu_bus_buffer.scala 417:130] + node _T_2558 = bits(buf_ageQ[2], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2559 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2560 = and(_T_2559, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2561 = eq(_T_2560, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2562 = and(_T_2558, _T_2561) @[lsu_bus_buffer.scala 417:76] + node _T_2563 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2564 = and(_T_2562, _T_2563) @[lsu_bus_buffer.scala 417:130] + node _T_2565 = cat(_T_2564, _T_2557) @[Cat.scala 29:58] + node _T_2566 = cat(_T_2565, _T_2550) @[Cat.scala 29:58] + node _T_2567 = cat(_T_2566, _T_2543) @[Cat.scala 29:58] + node _T_2568 = bits(buf_ageQ[3], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2569 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2570 = and(_T_2569, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2571 = eq(_T_2570, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2572 = and(_T_2568, _T_2571) @[lsu_bus_buffer.scala 417:76] + node _T_2573 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2574 = and(_T_2572, _T_2573) @[lsu_bus_buffer.scala 417:130] + node _T_2575 = bits(buf_ageQ[3], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2576 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2577 = and(_T_2576, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2578 = eq(_T_2577, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2579 = and(_T_2575, _T_2578) @[lsu_bus_buffer.scala 417:76] + node _T_2580 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2581 = and(_T_2579, _T_2580) @[lsu_bus_buffer.scala 417:130] + node _T_2582 = bits(buf_ageQ[3], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2583 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2586 = and(_T_2582, _T_2585) @[lsu_bus_buffer.scala 417:76] + node _T_2587 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2588 = and(_T_2586, _T_2587) @[lsu_bus_buffer.scala 417:130] + node _T_2589 = bits(buf_ageQ[3], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2590 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2591 = and(_T_2590, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2592 = eq(_T_2591, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2593 = and(_T_2589, _T_2592) @[lsu_bus_buffer.scala 417:76] + node _T_2594 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2595 = and(_T_2593, _T_2594) @[lsu_bus_buffer.scala 417:130] + node _T_2596 = cat(_T_2595, _T_2588) @[Cat.scala 29:58] + node _T_2597 = cat(_T_2596, _T_2581) @[Cat.scala 29:58] + node _T_2598 = cat(_T_2597, _T_2574) @[Cat.scala 29:58] + buf_age[0] <= _T_2505 @[lsu_bus_buffer.scala 417:11] + buf_age[1] <= _T_2536 @[lsu_bus_buffer.scala 417:11] + buf_age[2] <= _T_2567 @[lsu_bus_buffer.scala 417:11] + buf_age[3] <= _T_2598 @[lsu_bus_buffer.scala 417:11] + node _T_2599 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2600 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2601 = eq(_T_2600, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2602 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2603 = and(_T_2601, _T_2602) @[lsu_bus_buffer.scala 418:104] + node _T_2604 = mux(_T_2599, UInt<1>("h00"), _T_2603) @[lsu_bus_buffer.scala 418:72] + node _T_2605 = eq(UInt<1>("h00"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2606 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2607 = eq(_T_2606, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2608 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2609 = and(_T_2607, _T_2608) @[lsu_bus_buffer.scala 418:104] + node _T_2610 = mux(_T_2605, UInt<1>("h00"), _T_2609) @[lsu_bus_buffer.scala 418:72] + node _T_2611 = eq(UInt<1>("h00"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2612 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2614 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2615 = and(_T_2613, _T_2614) @[lsu_bus_buffer.scala 418:104] + node _T_2616 = mux(_T_2611, UInt<1>("h00"), _T_2615) @[lsu_bus_buffer.scala 418:72] + node _T_2617 = eq(UInt<1>("h00"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2618 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2619 = eq(_T_2618, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2620 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2621 = and(_T_2619, _T_2620) @[lsu_bus_buffer.scala 418:104] + node _T_2622 = mux(_T_2617, UInt<1>("h00"), _T_2621) @[lsu_bus_buffer.scala 418:72] + node _T_2623 = cat(_T_2622, _T_2616) @[Cat.scala 29:58] + node _T_2624 = cat(_T_2623, _T_2610) @[Cat.scala 29:58] + node _T_2625 = cat(_T_2624, _T_2604) @[Cat.scala 29:58] + node _T_2626 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2627 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2628 = eq(_T_2627, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2629 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2630 = and(_T_2628, _T_2629) @[lsu_bus_buffer.scala 418:104] + node _T_2631 = mux(_T_2626, UInt<1>("h00"), _T_2630) @[lsu_bus_buffer.scala 418:72] + node _T_2632 = eq(UInt<1>("h01"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2633 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2634 = eq(_T_2633, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2635 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2636 = and(_T_2634, _T_2635) @[lsu_bus_buffer.scala 418:104] + node _T_2637 = mux(_T_2632, UInt<1>("h00"), _T_2636) @[lsu_bus_buffer.scala 418:72] + node _T_2638 = eq(UInt<1>("h01"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2639 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2640 = eq(_T_2639, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2641 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2642 = and(_T_2640, _T_2641) @[lsu_bus_buffer.scala 418:104] + node _T_2643 = mux(_T_2638, UInt<1>("h00"), _T_2642) @[lsu_bus_buffer.scala 418:72] + node _T_2644 = eq(UInt<1>("h01"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2645 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2646 = eq(_T_2645, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2647 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2648 = and(_T_2646, _T_2647) @[lsu_bus_buffer.scala 418:104] + node _T_2649 = mux(_T_2644, UInt<1>("h00"), _T_2648) @[lsu_bus_buffer.scala 418:72] + node _T_2650 = cat(_T_2649, _T_2643) @[Cat.scala 29:58] + node _T_2651 = cat(_T_2650, _T_2637) @[Cat.scala 29:58] + node _T_2652 = cat(_T_2651, _T_2631) @[Cat.scala 29:58] + node _T_2653 = eq(UInt<2>("h02"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2654 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2655 = eq(_T_2654, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2656 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2657 = and(_T_2655, _T_2656) @[lsu_bus_buffer.scala 418:104] + node _T_2658 = mux(_T_2653, UInt<1>("h00"), _T_2657) @[lsu_bus_buffer.scala 418:72] + node _T_2659 = eq(UInt<2>("h02"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2660 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2661 = eq(_T_2660, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2662 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2663 = and(_T_2661, _T_2662) @[lsu_bus_buffer.scala 418:104] + node _T_2664 = mux(_T_2659, UInt<1>("h00"), _T_2663) @[lsu_bus_buffer.scala 418:72] + node _T_2665 = eq(UInt<2>("h02"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2666 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2667 = eq(_T_2666, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2668 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2669 = and(_T_2667, _T_2668) @[lsu_bus_buffer.scala 418:104] + node _T_2670 = mux(_T_2665, UInt<1>("h00"), _T_2669) @[lsu_bus_buffer.scala 418:72] + node _T_2671 = eq(UInt<2>("h02"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2672 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2673 = eq(_T_2672, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2674 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2675 = and(_T_2673, _T_2674) @[lsu_bus_buffer.scala 418:104] + node _T_2676 = mux(_T_2671, UInt<1>("h00"), _T_2675) @[lsu_bus_buffer.scala 418:72] + node _T_2677 = cat(_T_2676, _T_2670) @[Cat.scala 29:58] + node _T_2678 = cat(_T_2677, _T_2664) @[Cat.scala 29:58] + node _T_2679 = cat(_T_2678, _T_2658) @[Cat.scala 29:58] + node _T_2680 = eq(UInt<2>("h03"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2681 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2682 = eq(_T_2681, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2683 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2684 = and(_T_2682, _T_2683) @[lsu_bus_buffer.scala 418:104] + node _T_2685 = mux(_T_2680, UInt<1>("h00"), _T_2684) @[lsu_bus_buffer.scala 418:72] + node _T_2686 = eq(UInt<2>("h03"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2687 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2688 = eq(_T_2687, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2689 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2690 = and(_T_2688, _T_2689) @[lsu_bus_buffer.scala 418:104] + node _T_2691 = mux(_T_2686, UInt<1>("h00"), _T_2690) @[lsu_bus_buffer.scala 418:72] + node _T_2692 = eq(UInt<2>("h03"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2693 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2694 = eq(_T_2693, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2695 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2696 = and(_T_2694, _T_2695) @[lsu_bus_buffer.scala 418:104] + node _T_2697 = mux(_T_2692, UInt<1>("h00"), _T_2696) @[lsu_bus_buffer.scala 418:72] + node _T_2698 = eq(UInt<2>("h03"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2699 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2700 = eq(_T_2699, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2701 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2702 = and(_T_2700, _T_2701) @[lsu_bus_buffer.scala 418:104] + node _T_2703 = mux(_T_2698, UInt<1>("h00"), _T_2702) @[lsu_bus_buffer.scala 418:72] + node _T_2704 = cat(_T_2703, _T_2697) @[Cat.scala 29:58] + node _T_2705 = cat(_T_2704, _T_2691) @[Cat.scala 29:58] + node _T_2706 = cat(_T_2705, _T_2685) @[Cat.scala 29:58] + buf_age_younger[0] <= _T_2625 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[1] <= _T_2652 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[2] <= _T_2679 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[3] <= _T_2706 @[lsu_bus_buffer.scala 418:19] + node _T_2707 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2708 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2709 = and(_T_2707, _T_2708) @[lsu_bus_buffer.scala 419:87] + node _T_2710 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2711 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2712 = and(_T_2710, _T_2711) @[lsu_bus_buffer.scala 419:87] + node _T_2713 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2714 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2715 = and(_T_2713, _T_2714) @[lsu_bus_buffer.scala 419:87] + node _T_2716 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2717 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2718 = and(_T_2716, _T_2717) @[lsu_bus_buffer.scala 419:87] + node _T_2719 = cat(_T_2718, _T_2715) @[Cat.scala 29:58] + node _T_2720 = cat(_T_2719, _T_2712) @[Cat.scala 29:58] + node _T_2721 = cat(_T_2720, _T_2709) @[Cat.scala 29:58] + node _T_2722 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2723 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2724 = and(_T_2722, _T_2723) @[lsu_bus_buffer.scala 419:87] + node _T_2725 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2726 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2727 = and(_T_2725, _T_2726) @[lsu_bus_buffer.scala 419:87] + node _T_2728 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2729 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2730 = and(_T_2728, _T_2729) @[lsu_bus_buffer.scala 419:87] + node _T_2731 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2732 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2733 = and(_T_2731, _T_2732) @[lsu_bus_buffer.scala 419:87] + node _T_2734 = cat(_T_2733, _T_2730) @[Cat.scala 29:58] + node _T_2735 = cat(_T_2734, _T_2727) @[Cat.scala 29:58] + node _T_2736 = cat(_T_2735, _T_2724) @[Cat.scala 29:58] + node _T_2737 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2738 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2739 = and(_T_2737, _T_2738) @[lsu_bus_buffer.scala 419:87] + node _T_2740 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2741 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2742 = and(_T_2740, _T_2741) @[lsu_bus_buffer.scala 419:87] + node _T_2743 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2744 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2745 = and(_T_2743, _T_2744) @[lsu_bus_buffer.scala 419:87] + node _T_2746 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2747 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2748 = and(_T_2746, _T_2747) @[lsu_bus_buffer.scala 419:87] + node _T_2749 = cat(_T_2748, _T_2745) @[Cat.scala 29:58] + node _T_2750 = cat(_T_2749, _T_2742) @[Cat.scala 29:58] + node _T_2751 = cat(_T_2750, _T_2739) @[Cat.scala 29:58] + node _T_2752 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2753 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2754 = and(_T_2752, _T_2753) @[lsu_bus_buffer.scala 419:87] + node _T_2755 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2756 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2757 = and(_T_2755, _T_2756) @[lsu_bus_buffer.scala 419:87] + node _T_2758 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2759 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2760 = and(_T_2758, _T_2759) @[lsu_bus_buffer.scala 419:87] + node _T_2761 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2762 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2763 = and(_T_2761, _T_2762) @[lsu_bus_buffer.scala 419:87] + node _T_2764 = cat(_T_2763, _T_2760) @[Cat.scala 29:58] + node _T_2765 = cat(_T_2764, _T_2757) @[Cat.scala 29:58] + node _T_2766 = cat(_T_2765, _T_2754) @[Cat.scala 29:58] + buf_rsp_pickage[0] <= _T_2721 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[1] <= _T_2736 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[2] <= _T_2751 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[3] <= _T_2766 @[lsu_bus_buffer.scala 419:19] + node _T_2767 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2768 = and(_T_2767, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2769 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2770 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2771 = or(_T_2769, _T_2770) @[lsu_bus_buffer.scala 422:32] + node _T_2772 = eq(_T_2771, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2773 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2774 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2775 = and(_T_2773, _T_2774) @[lsu_bus_buffer.scala 423:41] + node _T_2776 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2777 = and(_T_2775, _T_2776) @[lsu_bus_buffer.scala 423:71] + node _T_2778 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2779 = and(_T_2777, _T_2778) @[lsu_bus_buffer.scala 423:90] + node _T_2780 = or(_T_2772, _T_2779) @[lsu_bus_buffer.scala 422:59] + node _T_2781 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2782 = and(_T_2781, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2783 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2784 = and(_T_2782, _T_2783) @[lsu_bus_buffer.scala 424:52] + node _T_2785 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2786 = and(_T_2784, _T_2785) @[lsu_bus_buffer.scala 424:71] + node _T_2787 = or(_T_2780, _T_2786) @[lsu_bus_buffer.scala 423:110] + node _T_2788 = and(_T_2768, _T_2787) @[lsu_bus_buffer.scala 421:112] + node _T_2789 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2790 = and(_T_2789, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2791 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2792 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2793 = or(_T_2791, _T_2792) @[lsu_bus_buffer.scala 422:32] + node _T_2794 = eq(_T_2793, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2795 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2796 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2797 = and(_T_2795, _T_2796) @[lsu_bus_buffer.scala 423:41] + node _T_2798 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2799 = and(_T_2797, _T_2798) @[lsu_bus_buffer.scala 423:71] + node _T_2800 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2801 = and(_T_2799, _T_2800) @[lsu_bus_buffer.scala 423:90] + node _T_2802 = or(_T_2794, _T_2801) @[lsu_bus_buffer.scala 422:59] + node _T_2803 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2804 = and(_T_2803, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2805 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2806 = and(_T_2804, _T_2805) @[lsu_bus_buffer.scala 424:52] + node _T_2807 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2808 = and(_T_2806, _T_2807) @[lsu_bus_buffer.scala 424:71] + node _T_2809 = or(_T_2802, _T_2808) @[lsu_bus_buffer.scala 423:110] + node _T_2810 = and(_T_2790, _T_2809) @[lsu_bus_buffer.scala 421:112] + node _T_2811 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2812 = and(_T_2811, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2813 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2814 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2815 = or(_T_2813, _T_2814) @[lsu_bus_buffer.scala 422:32] + node _T_2816 = eq(_T_2815, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2817 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2818 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2819 = and(_T_2817, _T_2818) @[lsu_bus_buffer.scala 423:41] + node _T_2820 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2821 = and(_T_2819, _T_2820) @[lsu_bus_buffer.scala 423:71] + node _T_2822 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_2823 = and(_T_2821, _T_2822) @[lsu_bus_buffer.scala 423:90] + node _T_2824 = or(_T_2816, _T_2823) @[lsu_bus_buffer.scala 422:59] + node _T_2825 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2826 = and(_T_2825, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2827 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2828 = and(_T_2826, _T_2827) @[lsu_bus_buffer.scala 424:52] + node _T_2829 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_2830 = and(_T_2828, _T_2829) @[lsu_bus_buffer.scala 424:71] + node _T_2831 = or(_T_2824, _T_2830) @[lsu_bus_buffer.scala 423:110] + node _T_2832 = and(_T_2812, _T_2831) @[lsu_bus_buffer.scala 421:112] + node _T_2833 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2834 = and(_T_2833, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2835 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2836 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2837 = or(_T_2835, _T_2836) @[lsu_bus_buffer.scala 422:32] + node _T_2838 = eq(_T_2837, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2839 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2840 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2841 = and(_T_2839, _T_2840) @[lsu_bus_buffer.scala 423:41] + node _T_2842 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2843 = and(_T_2841, _T_2842) @[lsu_bus_buffer.scala 423:71] + node _T_2844 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_2845 = and(_T_2843, _T_2844) @[lsu_bus_buffer.scala 423:90] + node _T_2846 = or(_T_2838, _T_2845) @[lsu_bus_buffer.scala 422:59] + node _T_2847 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2848 = and(_T_2847, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2849 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2850 = and(_T_2848, _T_2849) @[lsu_bus_buffer.scala 424:52] + node _T_2851 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_2852 = and(_T_2850, _T_2851) @[lsu_bus_buffer.scala 424:71] + node _T_2853 = or(_T_2846, _T_2852) @[lsu_bus_buffer.scala 423:110] + node _T_2854 = and(_T_2834, _T_2853) @[lsu_bus_buffer.scala 421:112] + node _T_2855 = cat(_T_2854, _T_2832) @[Cat.scala 29:58] + node _T_2856 = cat(_T_2855, _T_2810) @[Cat.scala 29:58] + node _T_2857 = cat(_T_2856, _T_2788) @[Cat.scala 29:58] + node _T_2858 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2859 = and(_T_2858, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2860 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2861 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2862 = or(_T_2860, _T_2861) @[lsu_bus_buffer.scala 422:32] + node _T_2863 = eq(_T_2862, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2864 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2865 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2866 = and(_T_2864, _T_2865) @[lsu_bus_buffer.scala 423:41] + node _T_2867 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2868 = and(_T_2866, _T_2867) @[lsu_bus_buffer.scala 423:71] + node _T_2869 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2870 = and(_T_2868, _T_2869) @[lsu_bus_buffer.scala 423:90] + node _T_2871 = or(_T_2863, _T_2870) @[lsu_bus_buffer.scala 422:59] + node _T_2872 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2873 = and(_T_2872, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2874 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2875 = and(_T_2873, _T_2874) @[lsu_bus_buffer.scala 424:52] + node _T_2876 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2877 = and(_T_2875, _T_2876) @[lsu_bus_buffer.scala 424:71] + node _T_2878 = or(_T_2871, _T_2877) @[lsu_bus_buffer.scala 423:110] + node _T_2879 = and(_T_2859, _T_2878) @[lsu_bus_buffer.scala 421:112] + node _T_2880 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2881 = and(_T_2880, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2882 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2883 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2884 = or(_T_2882, _T_2883) @[lsu_bus_buffer.scala 422:32] + node _T_2885 = eq(_T_2884, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2886 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2887 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2888 = and(_T_2886, _T_2887) @[lsu_bus_buffer.scala 423:41] + node _T_2889 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2890 = and(_T_2888, _T_2889) @[lsu_bus_buffer.scala 423:71] + node _T_2891 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2892 = and(_T_2890, _T_2891) @[lsu_bus_buffer.scala 423:90] + node _T_2893 = or(_T_2885, _T_2892) @[lsu_bus_buffer.scala 422:59] + node _T_2894 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2895 = and(_T_2894, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2896 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2897 = and(_T_2895, _T_2896) @[lsu_bus_buffer.scala 424:52] + node _T_2898 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2899 = and(_T_2897, _T_2898) @[lsu_bus_buffer.scala 424:71] + node _T_2900 = or(_T_2893, _T_2899) @[lsu_bus_buffer.scala 423:110] + node _T_2901 = and(_T_2881, _T_2900) @[lsu_bus_buffer.scala 421:112] + node _T_2902 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2903 = and(_T_2902, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2904 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2905 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2906 = or(_T_2904, _T_2905) @[lsu_bus_buffer.scala 422:32] + node _T_2907 = eq(_T_2906, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2908 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2909 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2910 = and(_T_2908, _T_2909) @[lsu_bus_buffer.scala 423:41] + node _T_2911 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2912 = and(_T_2910, _T_2911) @[lsu_bus_buffer.scala 423:71] + node _T_2913 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_2914 = and(_T_2912, _T_2913) @[lsu_bus_buffer.scala 423:90] + node _T_2915 = or(_T_2907, _T_2914) @[lsu_bus_buffer.scala 422:59] + node _T_2916 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2917 = and(_T_2916, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2918 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2919 = and(_T_2917, _T_2918) @[lsu_bus_buffer.scala 424:52] + node _T_2920 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_2921 = and(_T_2919, _T_2920) @[lsu_bus_buffer.scala 424:71] + node _T_2922 = or(_T_2915, _T_2921) @[lsu_bus_buffer.scala 423:110] + node _T_2923 = and(_T_2903, _T_2922) @[lsu_bus_buffer.scala 421:112] + node _T_2924 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2925 = and(_T_2924, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2926 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2927 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2928 = or(_T_2926, _T_2927) @[lsu_bus_buffer.scala 422:32] + node _T_2929 = eq(_T_2928, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2930 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2931 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2932 = and(_T_2930, _T_2931) @[lsu_bus_buffer.scala 423:41] + node _T_2933 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2934 = and(_T_2932, _T_2933) @[lsu_bus_buffer.scala 423:71] + node _T_2935 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_2936 = and(_T_2934, _T_2935) @[lsu_bus_buffer.scala 423:90] + node _T_2937 = or(_T_2929, _T_2936) @[lsu_bus_buffer.scala 422:59] + node _T_2938 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2939 = and(_T_2938, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2940 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2941 = and(_T_2939, _T_2940) @[lsu_bus_buffer.scala 424:52] + node _T_2942 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_2943 = and(_T_2941, _T_2942) @[lsu_bus_buffer.scala 424:71] + node _T_2944 = or(_T_2937, _T_2943) @[lsu_bus_buffer.scala 423:110] + node _T_2945 = and(_T_2925, _T_2944) @[lsu_bus_buffer.scala 421:112] + node _T_2946 = cat(_T_2945, _T_2923) @[Cat.scala 29:58] + node _T_2947 = cat(_T_2946, _T_2901) @[Cat.scala 29:58] + node _T_2948 = cat(_T_2947, _T_2879) @[Cat.scala 29:58] + node _T_2949 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2950 = and(_T_2949, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2951 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2952 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2953 = or(_T_2951, _T_2952) @[lsu_bus_buffer.scala 422:32] + node _T_2954 = eq(_T_2953, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2955 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2956 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2957 = and(_T_2955, _T_2956) @[lsu_bus_buffer.scala 423:41] + node _T_2958 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_2959 = and(_T_2957, _T_2958) @[lsu_bus_buffer.scala 423:71] + node _T_2960 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2961 = and(_T_2959, _T_2960) @[lsu_bus_buffer.scala 423:90] + node _T_2962 = or(_T_2954, _T_2961) @[lsu_bus_buffer.scala 422:59] + node _T_2963 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2964 = and(_T_2963, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2965 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_2966 = and(_T_2964, _T_2965) @[lsu_bus_buffer.scala 424:52] + node _T_2967 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2968 = and(_T_2966, _T_2967) @[lsu_bus_buffer.scala 424:71] + node _T_2969 = or(_T_2962, _T_2968) @[lsu_bus_buffer.scala 423:110] + node _T_2970 = and(_T_2950, _T_2969) @[lsu_bus_buffer.scala 421:112] + node _T_2971 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2972 = and(_T_2971, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2973 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2974 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2975 = or(_T_2973, _T_2974) @[lsu_bus_buffer.scala 422:32] + node _T_2976 = eq(_T_2975, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2977 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2978 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2979 = and(_T_2977, _T_2978) @[lsu_bus_buffer.scala 423:41] + node _T_2980 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_2981 = and(_T_2979, _T_2980) @[lsu_bus_buffer.scala 423:71] + node _T_2982 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2983 = and(_T_2981, _T_2982) @[lsu_bus_buffer.scala 423:90] + node _T_2984 = or(_T_2976, _T_2983) @[lsu_bus_buffer.scala 422:59] + node _T_2985 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2986 = and(_T_2985, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2987 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_2988 = and(_T_2986, _T_2987) @[lsu_bus_buffer.scala 424:52] + node _T_2989 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2990 = and(_T_2988, _T_2989) @[lsu_bus_buffer.scala 424:71] + node _T_2991 = or(_T_2984, _T_2990) @[lsu_bus_buffer.scala 423:110] + node _T_2992 = and(_T_2972, _T_2991) @[lsu_bus_buffer.scala 421:112] + node _T_2993 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2994 = and(_T_2993, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2995 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2996 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2997 = or(_T_2995, _T_2996) @[lsu_bus_buffer.scala 422:32] + node _T_2998 = eq(_T_2997, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2999 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3000 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3001 = and(_T_2999, _T_3000) @[lsu_bus_buffer.scala 423:41] + node _T_3002 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_3003 = and(_T_3001, _T_3002) @[lsu_bus_buffer.scala 423:71] + node _T_3004 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_3005 = and(_T_3003, _T_3004) @[lsu_bus_buffer.scala 423:90] + node _T_3006 = or(_T_2998, _T_3005) @[lsu_bus_buffer.scala 422:59] + node _T_3007 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3008 = and(_T_3007, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3009 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_3010 = and(_T_3008, _T_3009) @[lsu_bus_buffer.scala 424:52] + node _T_3011 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_3012 = and(_T_3010, _T_3011) @[lsu_bus_buffer.scala 424:71] + node _T_3013 = or(_T_3006, _T_3012) @[lsu_bus_buffer.scala 423:110] + node _T_3014 = and(_T_2994, _T_3013) @[lsu_bus_buffer.scala 421:112] + node _T_3015 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3016 = and(_T_3015, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_3017 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3018 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3019 = or(_T_3017, _T_3018) @[lsu_bus_buffer.scala 422:32] + node _T_3020 = eq(_T_3019, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3021 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3022 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3023 = and(_T_3021, _T_3022) @[lsu_bus_buffer.scala 423:41] + node _T_3024 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_3025 = and(_T_3023, _T_3024) @[lsu_bus_buffer.scala 423:71] + node _T_3026 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_3027 = and(_T_3025, _T_3026) @[lsu_bus_buffer.scala 423:90] + node _T_3028 = or(_T_3020, _T_3027) @[lsu_bus_buffer.scala 422:59] + node _T_3029 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3030 = and(_T_3029, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3031 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_3032 = and(_T_3030, _T_3031) @[lsu_bus_buffer.scala 424:52] + node _T_3033 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_3034 = and(_T_3032, _T_3033) @[lsu_bus_buffer.scala 424:71] + node _T_3035 = or(_T_3028, _T_3034) @[lsu_bus_buffer.scala 423:110] + node _T_3036 = and(_T_3016, _T_3035) @[lsu_bus_buffer.scala 421:112] + node _T_3037 = cat(_T_3036, _T_3014) @[Cat.scala 29:58] + node _T_3038 = cat(_T_3037, _T_2992) @[Cat.scala 29:58] + node _T_3039 = cat(_T_3038, _T_2970) @[Cat.scala 29:58] + node _T_3040 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3041 = and(_T_3040, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3042 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3043 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3044 = or(_T_3042, _T_3043) @[lsu_bus_buffer.scala 422:32] + node _T_3045 = eq(_T_3044, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3046 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3047 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3048 = and(_T_3046, _T_3047) @[lsu_bus_buffer.scala 423:41] + node _T_3049 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3050 = and(_T_3048, _T_3049) @[lsu_bus_buffer.scala 423:71] + node _T_3051 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_3052 = and(_T_3050, _T_3051) @[lsu_bus_buffer.scala 423:90] + node _T_3053 = or(_T_3045, _T_3052) @[lsu_bus_buffer.scala 422:59] + node _T_3054 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3055 = and(_T_3054, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3056 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3057 = and(_T_3055, _T_3056) @[lsu_bus_buffer.scala 424:52] + node _T_3058 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_3059 = and(_T_3057, _T_3058) @[lsu_bus_buffer.scala 424:71] + node _T_3060 = or(_T_3053, _T_3059) @[lsu_bus_buffer.scala 423:110] + node _T_3061 = and(_T_3041, _T_3060) @[lsu_bus_buffer.scala 421:112] + node _T_3062 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3063 = and(_T_3062, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3064 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3065 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3066 = or(_T_3064, _T_3065) @[lsu_bus_buffer.scala 422:32] + node _T_3067 = eq(_T_3066, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3068 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3069 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3070 = and(_T_3068, _T_3069) @[lsu_bus_buffer.scala 423:41] + node _T_3071 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3072 = and(_T_3070, _T_3071) @[lsu_bus_buffer.scala 423:71] + node _T_3073 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_3074 = and(_T_3072, _T_3073) @[lsu_bus_buffer.scala 423:90] + node _T_3075 = or(_T_3067, _T_3074) @[lsu_bus_buffer.scala 422:59] + node _T_3076 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3077 = and(_T_3076, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3078 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3079 = and(_T_3077, _T_3078) @[lsu_bus_buffer.scala 424:52] + node _T_3080 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_3081 = and(_T_3079, _T_3080) @[lsu_bus_buffer.scala 424:71] + node _T_3082 = or(_T_3075, _T_3081) @[lsu_bus_buffer.scala 423:110] + node _T_3083 = and(_T_3063, _T_3082) @[lsu_bus_buffer.scala 421:112] + node _T_3084 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3085 = and(_T_3084, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3086 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3087 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3088 = or(_T_3086, _T_3087) @[lsu_bus_buffer.scala 422:32] + node _T_3089 = eq(_T_3088, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3090 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3091 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3092 = and(_T_3090, _T_3091) @[lsu_bus_buffer.scala 423:41] + node _T_3093 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3094 = and(_T_3092, _T_3093) @[lsu_bus_buffer.scala 423:71] + node _T_3095 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_3096 = and(_T_3094, _T_3095) @[lsu_bus_buffer.scala 423:90] + node _T_3097 = or(_T_3089, _T_3096) @[lsu_bus_buffer.scala 422:59] + node _T_3098 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3099 = and(_T_3098, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3100 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3101 = and(_T_3099, _T_3100) @[lsu_bus_buffer.scala 424:52] + node _T_3102 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_3103 = and(_T_3101, _T_3102) @[lsu_bus_buffer.scala 424:71] + node _T_3104 = or(_T_3097, _T_3103) @[lsu_bus_buffer.scala 423:110] + node _T_3105 = and(_T_3085, _T_3104) @[lsu_bus_buffer.scala 421:112] + node _T_3106 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3107 = and(_T_3106, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3108 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3109 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3110 = or(_T_3108, _T_3109) @[lsu_bus_buffer.scala 422:32] + node _T_3111 = eq(_T_3110, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3112 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3113 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3114 = and(_T_3112, _T_3113) @[lsu_bus_buffer.scala 423:41] + node _T_3115 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3116 = and(_T_3114, _T_3115) @[lsu_bus_buffer.scala 423:71] + node _T_3117 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_3118 = and(_T_3116, _T_3117) @[lsu_bus_buffer.scala 423:90] + node _T_3119 = or(_T_3111, _T_3118) @[lsu_bus_buffer.scala 422:59] + node _T_3120 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3121 = and(_T_3120, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3122 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3123 = and(_T_3121, _T_3122) @[lsu_bus_buffer.scala 424:52] + node _T_3124 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_3125 = and(_T_3123, _T_3124) @[lsu_bus_buffer.scala 424:71] + node _T_3126 = or(_T_3119, _T_3125) @[lsu_bus_buffer.scala 423:110] + node _T_3127 = and(_T_3107, _T_3126) @[lsu_bus_buffer.scala 421:112] + node _T_3128 = cat(_T_3127, _T_3105) @[Cat.scala 29:58] + node _T_3129 = cat(_T_3128, _T_3083) @[Cat.scala 29:58] + node _T_3130 = cat(_T_3129, _T_3061) @[Cat.scala 29:58] + buf_rspage_set[0] <= _T_2857 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[1] <= _T_2948 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[2] <= _T_3039 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[3] <= _T_3130 @[lsu_bus_buffer.scala 421:18] + node _T_3131 = bits(buf_rspage_set[0], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3132 = bits(buf_rspage[0], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3133 = or(_T_3131, _T_3132) @[lsu_bus_buffer.scala 425:88] + node _T_3134 = bits(buf_rspage_set[0], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3135 = bits(buf_rspage[0], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3136 = or(_T_3134, _T_3135) @[lsu_bus_buffer.scala 425:88] + node _T_3137 = bits(buf_rspage_set[0], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3138 = bits(buf_rspage[0], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3139 = or(_T_3137, _T_3138) @[lsu_bus_buffer.scala 425:88] + node _T_3140 = bits(buf_rspage_set[0], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3141 = bits(buf_rspage[0], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3142 = or(_T_3140, _T_3141) @[lsu_bus_buffer.scala 425:88] + node _T_3143 = cat(_T_3142, _T_3139) @[Cat.scala 29:58] + node _T_3144 = cat(_T_3143, _T_3136) @[Cat.scala 29:58] + node _T_3145 = cat(_T_3144, _T_3133) @[Cat.scala 29:58] + node _T_3146 = bits(buf_rspage_set[1], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3147 = bits(buf_rspage[1], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3148 = or(_T_3146, _T_3147) @[lsu_bus_buffer.scala 425:88] + node _T_3149 = bits(buf_rspage_set[1], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3150 = bits(buf_rspage[1], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3151 = or(_T_3149, _T_3150) @[lsu_bus_buffer.scala 425:88] + node _T_3152 = bits(buf_rspage_set[1], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3153 = bits(buf_rspage[1], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3154 = or(_T_3152, _T_3153) @[lsu_bus_buffer.scala 425:88] + node _T_3155 = bits(buf_rspage_set[1], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3156 = bits(buf_rspage[1], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3157 = or(_T_3155, _T_3156) @[lsu_bus_buffer.scala 425:88] + node _T_3158 = cat(_T_3157, _T_3154) @[Cat.scala 29:58] + node _T_3159 = cat(_T_3158, _T_3151) @[Cat.scala 29:58] + node _T_3160 = cat(_T_3159, _T_3148) @[Cat.scala 29:58] + node _T_3161 = bits(buf_rspage_set[2], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3162 = bits(buf_rspage[2], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3163 = or(_T_3161, _T_3162) @[lsu_bus_buffer.scala 425:88] + node _T_3164 = bits(buf_rspage_set[2], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3165 = bits(buf_rspage[2], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3166 = or(_T_3164, _T_3165) @[lsu_bus_buffer.scala 425:88] + node _T_3167 = bits(buf_rspage_set[2], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3168 = bits(buf_rspage[2], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3169 = or(_T_3167, _T_3168) @[lsu_bus_buffer.scala 425:88] + node _T_3170 = bits(buf_rspage_set[2], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3171 = bits(buf_rspage[2], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3172 = or(_T_3170, _T_3171) @[lsu_bus_buffer.scala 425:88] + node _T_3173 = cat(_T_3172, _T_3169) @[Cat.scala 29:58] + node _T_3174 = cat(_T_3173, _T_3166) @[Cat.scala 29:58] + node _T_3175 = cat(_T_3174, _T_3163) @[Cat.scala 29:58] + node _T_3176 = bits(buf_rspage_set[3], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3177 = bits(buf_rspage[3], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3178 = or(_T_3176, _T_3177) @[lsu_bus_buffer.scala 425:88] + node _T_3179 = bits(buf_rspage_set[3], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3180 = bits(buf_rspage[3], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3181 = or(_T_3179, _T_3180) @[lsu_bus_buffer.scala 425:88] + node _T_3182 = bits(buf_rspage_set[3], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3183 = bits(buf_rspage[3], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3184 = or(_T_3182, _T_3183) @[lsu_bus_buffer.scala 425:88] + node _T_3185 = bits(buf_rspage_set[3], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3186 = bits(buf_rspage[3], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3187 = or(_T_3185, _T_3186) @[lsu_bus_buffer.scala 425:88] + node _T_3188 = cat(_T_3187, _T_3184) @[Cat.scala 29:58] + node _T_3189 = cat(_T_3188, _T_3181) @[Cat.scala 29:58] + node _T_3190 = cat(_T_3189, _T_3178) @[Cat.scala 29:58] + buf_rspage_in[0] <= _T_3145 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[1] <= _T_3160 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[2] <= _T_3175 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[3] <= _T_3190 @[lsu_bus_buffer.scala 425:17] + node _T_3191 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3192 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3193 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3194 = or(_T_3192, _T_3193) @[lsu_bus_buffer.scala 426:110] + node _T_3195 = eq(_T_3194, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3196 = and(_T_3191, _T_3195) @[lsu_bus_buffer.scala 426:82] + node _T_3197 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3198 = and(_T_3196, _T_3197) @[lsu_bus_buffer.scala 426:136] + node _T_3199 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3200 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3201 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3202 = or(_T_3200, _T_3201) @[lsu_bus_buffer.scala 426:110] + node _T_3203 = eq(_T_3202, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3204 = and(_T_3199, _T_3203) @[lsu_bus_buffer.scala 426:82] + node _T_3205 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3206 = and(_T_3204, _T_3205) @[lsu_bus_buffer.scala 426:136] + node _T_3207 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3208 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3209 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3210 = or(_T_3208, _T_3209) @[lsu_bus_buffer.scala 426:110] + node _T_3211 = eq(_T_3210, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3212 = and(_T_3207, _T_3211) @[lsu_bus_buffer.scala 426:82] + node _T_3213 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3214 = and(_T_3212, _T_3213) @[lsu_bus_buffer.scala 426:136] + node _T_3215 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3216 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3217 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3218 = or(_T_3216, _T_3217) @[lsu_bus_buffer.scala 426:110] + node _T_3219 = eq(_T_3218, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3220 = and(_T_3215, _T_3219) @[lsu_bus_buffer.scala 426:82] + node _T_3221 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3222 = and(_T_3220, _T_3221) @[lsu_bus_buffer.scala 426:136] + node _T_3223 = cat(_T_3222, _T_3214) @[Cat.scala 29:58] + node _T_3224 = cat(_T_3223, _T_3206) @[Cat.scala 29:58] + node _T_3225 = cat(_T_3224, _T_3198) @[Cat.scala 29:58] + node _T_3226 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3227 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3228 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3229 = or(_T_3227, _T_3228) @[lsu_bus_buffer.scala 426:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3231 = and(_T_3226, _T_3230) @[lsu_bus_buffer.scala 426:82] + node _T_3232 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3233 = and(_T_3231, _T_3232) @[lsu_bus_buffer.scala 426:136] + node _T_3234 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3235 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3236 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3237 = or(_T_3235, _T_3236) @[lsu_bus_buffer.scala 426:110] + node _T_3238 = eq(_T_3237, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3239 = and(_T_3234, _T_3238) @[lsu_bus_buffer.scala 426:82] + node _T_3240 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3241 = and(_T_3239, _T_3240) @[lsu_bus_buffer.scala 426:136] + node _T_3242 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3243 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3244 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3245 = or(_T_3243, _T_3244) @[lsu_bus_buffer.scala 426:110] + node _T_3246 = eq(_T_3245, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3247 = and(_T_3242, _T_3246) @[lsu_bus_buffer.scala 426:82] + node _T_3248 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3249 = and(_T_3247, _T_3248) @[lsu_bus_buffer.scala 426:136] + node _T_3250 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3251 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3252 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3253 = or(_T_3251, _T_3252) @[lsu_bus_buffer.scala 426:110] + node _T_3254 = eq(_T_3253, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3255 = and(_T_3250, _T_3254) @[lsu_bus_buffer.scala 426:82] + node _T_3256 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3257 = and(_T_3255, _T_3256) @[lsu_bus_buffer.scala 426:136] + node _T_3258 = cat(_T_3257, _T_3249) @[Cat.scala 29:58] + node _T_3259 = cat(_T_3258, _T_3241) @[Cat.scala 29:58] + node _T_3260 = cat(_T_3259, _T_3233) @[Cat.scala 29:58] + node _T_3261 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3262 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3263 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3264 = or(_T_3262, _T_3263) @[lsu_bus_buffer.scala 426:110] + node _T_3265 = eq(_T_3264, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3266 = and(_T_3261, _T_3265) @[lsu_bus_buffer.scala 426:82] + node _T_3267 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3268 = and(_T_3266, _T_3267) @[lsu_bus_buffer.scala 426:136] + node _T_3269 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3270 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3271 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3272 = or(_T_3270, _T_3271) @[lsu_bus_buffer.scala 426:110] + node _T_3273 = eq(_T_3272, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3274 = and(_T_3269, _T_3273) @[lsu_bus_buffer.scala 426:82] + node _T_3275 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3276 = and(_T_3274, _T_3275) @[lsu_bus_buffer.scala 426:136] + node _T_3277 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3278 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3279 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3280 = or(_T_3278, _T_3279) @[lsu_bus_buffer.scala 426:110] + node _T_3281 = eq(_T_3280, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3282 = and(_T_3277, _T_3281) @[lsu_bus_buffer.scala 426:82] + node _T_3283 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3284 = and(_T_3282, _T_3283) @[lsu_bus_buffer.scala 426:136] + node _T_3285 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3286 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3287 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3288 = or(_T_3286, _T_3287) @[lsu_bus_buffer.scala 426:110] + node _T_3289 = eq(_T_3288, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3290 = and(_T_3285, _T_3289) @[lsu_bus_buffer.scala 426:82] + node _T_3291 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3292 = and(_T_3290, _T_3291) @[lsu_bus_buffer.scala 426:136] + node _T_3293 = cat(_T_3292, _T_3284) @[Cat.scala 29:58] + node _T_3294 = cat(_T_3293, _T_3276) @[Cat.scala 29:58] + node _T_3295 = cat(_T_3294, _T_3268) @[Cat.scala 29:58] + node _T_3296 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3297 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3298 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3299 = or(_T_3297, _T_3298) @[lsu_bus_buffer.scala 426:110] + node _T_3300 = eq(_T_3299, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3301 = and(_T_3296, _T_3300) @[lsu_bus_buffer.scala 426:82] + node _T_3302 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3303 = and(_T_3301, _T_3302) @[lsu_bus_buffer.scala 426:136] + node _T_3304 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3305 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3306 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3307 = or(_T_3305, _T_3306) @[lsu_bus_buffer.scala 426:110] + node _T_3308 = eq(_T_3307, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3309 = and(_T_3304, _T_3308) @[lsu_bus_buffer.scala 426:82] + node _T_3310 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3311 = and(_T_3309, _T_3310) @[lsu_bus_buffer.scala 426:136] + node _T_3312 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3313 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3314 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3315 = or(_T_3313, _T_3314) @[lsu_bus_buffer.scala 426:110] + node _T_3316 = eq(_T_3315, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3317 = and(_T_3312, _T_3316) @[lsu_bus_buffer.scala 426:82] + node _T_3318 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3319 = and(_T_3317, _T_3318) @[lsu_bus_buffer.scala 426:136] + node _T_3320 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3321 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3322 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3323 = or(_T_3321, _T_3322) @[lsu_bus_buffer.scala 426:110] + node _T_3324 = eq(_T_3323, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3325 = and(_T_3320, _T_3324) @[lsu_bus_buffer.scala 426:82] + node _T_3326 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3327 = and(_T_3325, _T_3326) @[lsu_bus_buffer.scala 426:136] + node _T_3328 = cat(_T_3327, _T_3319) @[Cat.scala 29:58] + node _T_3329 = cat(_T_3328, _T_3311) @[Cat.scala 29:58] + node _T_3330 = cat(_T_3329, _T_3303) @[Cat.scala 29:58] + buf_rspage[0] <= _T_3225 @[lsu_bus_buffer.scala 426:14] + buf_rspage[1] <= _T_3260 @[lsu_bus_buffer.scala 426:14] + buf_rspage[2] <= _T_3295 @[lsu_bus_buffer.scala 426:14] + buf_rspage[3] <= _T_3330 @[lsu_bus_buffer.scala 426:14] + node _T_3331 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 427:75] + node _T_3332 = and(ibuf_drain_vld, _T_3331) @[lsu_bus_buffer.scala 427:63] + node _T_3333 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 427:75] + node _T_3334 = and(ibuf_drain_vld, _T_3333) @[lsu_bus_buffer.scala 427:63] + node _T_3335 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 427:75] + node _T_3336 = and(ibuf_drain_vld, _T_3335) @[lsu_bus_buffer.scala 427:63] + node _T_3337 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 427:75] + node _T_3338 = and(ibuf_drain_vld, _T_3337) @[lsu_bus_buffer.scala 427:63] + node _T_3339 = cat(_T_3338, _T_3336) @[Cat.scala 29:58] + node _T_3340 = cat(_T_3339, _T_3334) @[Cat.scala 29:58] + node _T_3341 = cat(_T_3340, _T_3332) @[Cat.scala 29:58] + ibuf_drainvec_vld <= _T_3341 @[lsu_bus_buffer.scala 427:21] + node _T_3342 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 428:64] + node _T_3343 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3344 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3345 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 429:46] + node _T_3346 = and(_T_3344, _T_3345) @[lsu_bus_buffer.scala 429:35] + node _T_3347 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3348 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3349 = mux(_T_3346, _T_3347, _T_3348) @[lsu_bus_buffer.scala 429:8] + node _T_3350 = mux(_T_3342, _T_3343, _T_3349) @[lsu_bus_buffer.scala 428:46] + node _T_3351 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 428:64] + node _T_3352 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3353 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3354 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 429:46] + node _T_3355 = and(_T_3353, _T_3354) @[lsu_bus_buffer.scala 429:35] + node _T_3356 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3357 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3358 = mux(_T_3355, _T_3356, _T_3357) @[lsu_bus_buffer.scala 429:8] + node _T_3359 = mux(_T_3351, _T_3352, _T_3358) @[lsu_bus_buffer.scala 428:46] + node _T_3360 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 428:64] + node _T_3361 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3362 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3363 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 429:46] + node _T_3364 = and(_T_3362, _T_3363) @[lsu_bus_buffer.scala 429:35] + node _T_3365 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3366 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3367 = mux(_T_3364, _T_3365, _T_3366) @[lsu_bus_buffer.scala 429:8] + node _T_3368 = mux(_T_3360, _T_3361, _T_3367) @[lsu_bus_buffer.scala 428:46] + node _T_3369 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 428:64] + node _T_3370 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3371 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3372 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 429:46] + node _T_3373 = and(_T_3371, _T_3372) @[lsu_bus_buffer.scala 429:35] + node _T_3374 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3375 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3376 = mux(_T_3373, _T_3374, _T_3375) @[lsu_bus_buffer.scala 429:8] + node _T_3377 = mux(_T_3369, _T_3370, _T_3376) @[lsu_bus_buffer.scala 428:46] + buf_byteen_in[0] <= _T_3350 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[1] <= _T_3359 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[2] <= _T_3368 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[3] <= _T_3377 @[lsu_bus_buffer.scala 428:17] + node _T_3378 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 430:62] + node _T_3379 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3380 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 430:119] + node _T_3381 = and(_T_3379, _T_3380) @[lsu_bus_buffer.scala 430:108] + node _T_3382 = mux(_T_3381, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3383 = mux(_T_3378, ibuf_addr, _T_3382) @[lsu_bus_buffer.scala 430:44] + node _T_3384 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 430:62] + node _T_3385 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3386 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 430:119] + node _T_3387 = and(_T_3385, _T_3386) @[lsu_bus_buffer.scala 430:108] + node _T_3388 = mux(_T_3387, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3389 = mux(_T_3384, ibuf_addr, _T_3388) @[lsu_bus_buffer.scala 430:44] + node _T_3390 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 430:62] + node _T_3391 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3392 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 430:119] + node _T_3393 = and(_T_3391, _T_3392) @[lsu_bus_buffer.scala 430:108] + node _T_3394 = mux(_T_3393, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3395 = mux(_T_3390, ibuf_addr, _T_3394) @[lsu_bus_buffer.scala 430:44] + node _T_3396 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 430:62] + node _T_3397 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3398 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 430:119] + node _T_3399 = and(_T_3397, _T_3398) @[lsu_bus_buffer.scala 430:108] + node _T_3400 = mux(_T_3399, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3401 = mux(_T_3396, ibuf_addr, _T_3400) @[lsu_bus_buffer.scala 430:44] + buf_addr_in[0] <= _T_3383 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[1] <= _T_3389 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[2] <= _T_3395 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[3] <= _T_3401 @[lsu_bus_buffer.scala 430:15] + node _T_3402 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 431:63] + node _T_3403 = mux(_T_3402, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3404 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 431:63] + node _T_3405 = mux(_T_3404, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3406 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 431:63] + node _T_3407 = mux(_T_3406, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3408 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 431:63] + node _T_3409 = mux(_T_3408, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3410 = cat(_T_3409, _T_3407) @[Cat.scala 29:58] + node _T_3411 = cat(_T_3410, _T_3405) @[Cat.scala 29:58] + node _T_3412 = cat(_T_3411, _T_3403) @[Cat.scala 29:58] + buf_dual_in <= _T_3412 @[lsu_bus_buffer.scala 431:15] + node _T_3413 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 432:65] + node _T_3414 = mux(_T_3413, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3415 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 432:65] + node _T_3416 = mux(_T_3415, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3417 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 432:65] + node _T_3418 = mux(_T_3417, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3419 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 432:65] + node _T_3420 = mux(_T_3419, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3421 = cat(_T_3420, _T_3418) @[Cat.scala 29:58] + node _T_3422 = cat(_T_3421, _T_3416) @[Cat.scala 29:58] + node _T_3423 = cat(_T_3422, _T_3414) @[Cat.scala 29:58] + buf_samedw_in <= _T_3423 @[lsu_bus_buffer.scala 432:17] + node _T_3424 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 433:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3427 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 433:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3430 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 433:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3433 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 433:66] + node _T_3434 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3435 = mux(_T_3433, _T_3434, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3436 = cat(_T_3435, _T_3432) @[Cat.scala 29:58] + node _T_3437 = cat(_T_3436, _T_3429) @[Cat.scala 29:58] + node _T_3438 = cat(_T_3437, _T_3426) @[Cat.scala 29:58] + buf_nomerge_in <= _T_3438 @[lsu_bus_buffer.scala 433:18] + node _T_3439 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 434:65] + node _T_3440 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3441 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 434:118] + node _T_3442 = and(_T_3440, _T_3441) @[lsu_bus_buffer.scala 434:107] + node _T_3443 = mux(_T_3439, ibuf_dual, _T_3442) @[lsu_bus_buffer.scala 434:47] + node _T_3444 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 434:65] + node _T_3445 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3446 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 434:118] + node _T_3447 = and(_T_3445, _T_3446) @[lsu_bus_buffer.scala 434:107] + node _T_3448 = mux(_T_3444, ibuf_dual, _T_3447) @[lsu_bus_buffer.scala 434:47] + node _T_3449 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 434:65] + node _T_3450 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3451 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 434:118] + node _T_3452 = and(_T_3450, _T_3451) @[lsu_bus_buffer.scala 434:107] + node _T_3453 = mux(_T_3449, ibuf_dual, _T_3452) @[lsu_bus_buffer.scala 434:47] + node _T_3454 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 434:65] + node _T_3455 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3456 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 434:118] + node _T_3457 = and(_T_3455, _T_3456) @[lsu_bus_buffer.scala 434:107] + node _T_3458 = mux(_T_3454, ibuf_dual, _T_3457) @[lsu_bus_buffer.scala 434:47] + node _T_3459 = cat(_T_3458, _T_3453) @[Cat.scala 29:58] + node _T_3460 = cat(_T_3459, _T_3448) @[Cat.scala 29:58] + node _T_3461 = cat(_T_3460, _T_3443) @[Cat.scala 29:58] + buf_dualhi_in <= _T_3461 @[lsu_bus_buffer.scala 434:17] + node _T_3462 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 435:65] + node _T_3463 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3464 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 435:125] + node _T_3465 = and(_T_3463, _T_3464) @[lsu_bus_buffer.scala 435:114] + node _T_3466 = mux(_T_3465, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3467 = mux(_T_3462, ibuf_dualtag, _T_3466) @[lsu_bus_buffer.scala 435:47] + node _T_3468 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 435:65] + node _T_3469 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3470 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 435:125] + node _T_3471 = and(_T_3469, _T_3470) @[lsu_bus_buffer.scala 435:114] + node _T_3472 = mux(_T_3471, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3473 = mux(_T_3468, ibuf_dualtag, _T_3472) @[lsu_bus_buffer.scala 435:47] + node _T_3474 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 435:65] + node _T_3475 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3476 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 435:125] + node _T_3477 = and(_T_3475, _T_3476) @[lsu_bus_buffer.scala 435:114] + node _T_3478 = mux(_T_3477, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3479 = mux(_T_3474, ibuf_dualtag, _T_3478) @[lsu_bus_buffer.scala 435:47] + node _T_3480 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 435:65] + node _T_3481 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3482 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 435:125] + node _T_3483 = and(_T_3481, _T_3482) @[lsu_bus_buffer.scala 435:114] + node _T_3484 = mux(_T_3483, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3485 = mux(_T_3480, ibuf_dualtag, _T_3484) @[lsu_bus_buffer.scala 435:47] + buf_dualtag_in[0] <= _T_3467 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[1] <= _T_3473 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[2] <= _T_3479 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[3] <= _T_3485 @[lsu_bus_buffer.scala 435:18] + node _T_3486 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 436:69] + node _T_3487 = mux(_T_3486, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3488 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 436:69] + node _T_3489 = mux(_T_3488, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3490 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 436:69] + node _T_3491 = mux(_T_3490, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3492 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 436:69] + node _T_3493 = mux(_T_3492, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3494 = cat(_T_3493, _T_3491) @[Cat.scala 29:58] + node _T_3495 = cat(_T_3494, _T_3489) @[Cat.scala 29:58] + node _T_3496 = cat(_T_3495, _T_3487) @[Cat.scala 29:58] + buf_sideeffect_in <= _T_3496 @[lsu_bus_buffer.scala 436:21] + node _T_3497 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 437:65] + node _T_3498 = mux(_T_3497, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3499 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 437:65] + node _T_3500 = mux(_T_3499, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3501 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 437:65] + node _T_3502 = mux(_T_3501, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3503 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 437:65] + node _T_3504 = mux(_T_3503, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3505 = cat(_T_3504, _T_3502) @[Cat.scala 29:58] + node _T_3506 = cat(_T_3505, _T_3500) @[Cat.scala 29:58] + node _T_3507 = cat(_T_3506, _T_3498) @[Cat.scala 29:58] + buf_unsign_in <= _T_3507 @[lsu_bus_buffer.scala 437:17] + node _T_3508 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 438:60] + node _T_3509 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[lsu_bus_buffer.scala 438:42] + node _T_3511 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 438:60] + node _T_3512 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[lsu_bus_buffer.scala 438:42] + node _T_3514 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 438:60] + node _T_3515 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[lsu_bus_buffer.scala 438:42] + node _T_3517 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 438:60] + node _T_3518 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3519 = mux(_T_3517, ibuf_sz, _T_3518) @[lsu_bus_buffer.scala 438:42] + buf_sz_in[0] <= _T_3510 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[1] <= _T_3513 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[2] <= _T_3516 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[3] <= _T_3519 @[lsu_bus_buffer.scala 438:13] + node _T_3520 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 439:64] + node _T_3521 = mux(_T_3520, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3522 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 439:64] + node _T_3523 = mux(_T_3522, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3524 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 439:64] + node _T_3525 = mux(_T_3524, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3526 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 439:64] + node _T_3527 = mux(_T_3526, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3528 = cat(_T_3527, _T_3525) @[Cat.scala 29:58] + node _T_3529 = cat(_T_3528, _T_3523) @[Cat.scala 29:58] + node _T_3530 = cat(_T_3529, _T_3521) @[Cat.scala 29:58] + buf_write_in <= _T_3530 @[lsu_bus_buffer.scala 439:16] + node _T_3531 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3531 : @[Conditional.scala 40:58] + node _T_3532 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3533 = mux(_T_3532, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[0] <= _T_3533 @[lsu_bus_buffer.scala 444:25] + node _T_3534 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3535 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3536 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3537 = and(_T_3535, _T_3536) @[lsu_bus_buffer.scala 445:95] + node _T_3538 = eq(UInt<1>("h00"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3539 = and(_T_3537, _T_3538) @[lsu_bus_buffer.scala 445:112] + node _T_3540 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3541 = eq(UInt<1>("h00"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3542 = and(_T_3540, _T_3541) @[lsu_bus_buffer.scala 445:161] + node _T_3543 = or(_T_3539, _T_3542) @[lsu_bus_buffer.scala 445:132] + node _T_3544 = and(_T_3534, _T_3543) @[lsu_bus_buffer.scala 445:63] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[lsu_bus_buffer.scala 445:201] + node _T_3547 = or(_T_3544, _T_3546) @[lsu_bus_buffer.scala 445:183] + buf_state_en[0] <= _T_3547 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 446:22] + buf_data_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 447:24] + node _T_3548 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3549 = and(ibuf_drain_vld, _T_3548) @[lsu_bus_buffer.scala 448:47] + node _T_3550 = bits(_T_3549, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3551 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3552 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3553 = mux(_T_3550, _T_3551, _T_3552) @[lsu_bus_buffer.scala 448:30] + buf_data_in[0] <= _T_3553 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3554 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3554 : @[Conditional.scala 39:67] + node _T_3555 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3556 = mux(_T_3555, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[0] <= _T_3556 @[lsu_bus_buffer.scala 453:25] + node _T_3557 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[0] <= _T_3557 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3558 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3558 : @[Conditional.scala 39:67] + node _T_3559 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3560 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3561 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3562 = and(_T_3560, _T_3561) @[lsu_bus_buffer.scala 459:104] + node _T_3563 = mux(_T_3562, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3564 = mux(_T_3559, UInt<3>("h00"), _T_3563) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[0] <= _T_3564 @[lsu_bus_buffer.scala 459:25] + node _T_3565 = eq(obuf_tag0, UInt<3>("h00")) @[lsu_bus_buffer.scala 460:48] + node _T_3566 = eq(obuf_tag1, UInt<3>("h00")) @[lsu_bus_buffer.scala 460:104] + node _T_3567 = and(obuf_merge, _T_3566) @[lsu_bus_buffer.scala 460:91] + node _T_3568 = or(_T_3565, _T_3567) @[lsu_bus_buffer.scala 460:77] + node _T_3569 = and(_T_3568, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3570 = and(_T_3569, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[0] <= _T_3570 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[lsu_bus_buffer.scala 461:29] + node _T_3571 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3572 = or(_T_3571, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[0] <= _T_3572 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3573 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 464:56] + node _T_3574 = eq(_T_3573, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3575 = and(buf_state_en[0], _T_3574) @[lsu_bus_buffer.scala 464:44] + node _T_3576 = and(_T_3575, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3577 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3578 = and(_T_3576, _T_3577) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[0] <= _T_3578 @[lsu_bus_buffer.scala 464:25] + node _T_3579 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[0] <= _T_3579 @[lsu_bus_buffer.scala 465:28] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3581 = and(_T_3580, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3582 = and(_T_3581, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[0] <= _T_3582 @[lsu_bus_buffer.scala 466:24] + node _T_3583 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3584 = and(_T_3583, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3585 = and(_T_3584, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[0] <= _T_3585 @[lsu_bus_buffer.scala 467:25] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3587 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3588 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3589 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3590 = mux(_T_3587, _T_3588, _T_3589) @[lsu_bus_buffer.scala 468:73] + node _T_3591 = mux(buf_error_en[0], _T_3586, _T_3590) @[lsu_bus_buffer.scala 468:30] + buf_data_in[0] <= _T_3591 @[lsu_bus_buffer.scala 468:24] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3592 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3592 : @[Conditional.scala 39:67] + node _T_3593 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 472:69] + node _T_3594 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3595 = and(_T_3593, _T_3594) @[lsu_bus_buffer.scala 472:73] + node _T_3596 = or(io.dec_tlu_force_halt, _T_3595) @[lsu_bus_buffer.scala 472:57] + node _T_3597 = bits(_T_3596, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3598 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3599 = and(buf_dual[0], _T_3598) @[lsu_bus_buffer.scala 473:28] + node _T_3600 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 473:57] + node _T_3601 = eq(_T_3600, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3602 = and(_T_3599, _T_3601) @[lsu_bus_buffer.scala 473:45] + node _T_3603 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3604 = and(_T_3602, _T_3603) @[lsu_bus_buffer.scala 473:61] + node _T_3605 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 474:27] + node _T_3606 = or(_T_3605, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3607 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3608 = and(buf_dual[0], _T_3607) @[lsu_bus_buffer.scala 474:68] + node _T_3609 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 474:97] + node _T_3610 = eq(_T_3609, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3611 = and(_T_3608, _T_3610) @[lsu_bus_buffer.scala 474:85] + node _T_3612 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3613 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3614 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3615 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3616 = eq(buf_dualtag[0], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3617 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_3618 = eq(buf_dualtag[0], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_3619 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_3620 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3621 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3622 = mux(_T_3616, _T_3617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3623 = mux(_T_3618, _T_3619, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3624 = or(_T_3620, _T_3621) @[Mux.scala 27:72] + node _T_3625 = or(_T_3624, _T_3622) @[Mux.scala 27:72] + node _T_3626 = or(_T_3625, _T_3623) @[Mux.scala 27:72] + wire _T_3627 : UInt<1> @[Mux.scala 27:72] + _T_3627 <= _T_3626 @[Mux.scala 27:72] + node _T_3628 = and(_T_3611, _T_3627) @[lsu_bus_buffer.scala 474:101] + node _T_3629 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_3630 = and(_T_3628, _T_3629) @[lsu_bus_buffer.scala 474:138] + node _T_3631 = and(_T_3630, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_3632 = or(_T_3606, _T_3631) @[lsu_bus_buffer.scala 474:53] + node _T_3633 = mux(_T_3632, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_3634 = mux(_T_3604, UInt<3>("h04"), _T_3633) @[lsu_bus_buffer.scala 473:14] + node _T_3635 = mux(_T_3597, UInt<3>("h00"), _T_3634) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[0] <= _T_3635 @[lsu_bus_buffer.scala 472:27] + node _T_3636 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 475:73] + node _T_3637 = and(bus_rsp_write, _T_3636) @[lsu_bus_buffer.scala 475:52] + node _T_3638 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 476:46] + node _T_3639 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 477:23] + node _T_3640 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 477:47] + node _T_3641 = and(_T_3639, _T_3640) @[lsu_bus_buffer.scala 477:27] + node _T_3642 = or(_T_3638, _T_3641) @[lsu_bus_buffer.scala 476:77] + node _T_3643 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 478:26] + node _T_3644 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 478:54] + node _T_3645 = not(_T_3644) @[lsu_bus_buffer.scala 478:44] + node _T_3646 = and(_T_3643, _T_3645) @[lsu_bus_buffer.scala 478:42] + node _T_3647 = and(_T_3646, buf_samedw[0]) @[lsu_bus_buffer.scala 478:58] + node _T_3648 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 478:94] + node _T_3649 = and(_T_3647, _T_3648) @[lsu_bus_buffer.scala 478:74] + node _T_3650 = or(_T_3642, _T_3649) @[lsu_bus_buffer.scala 477:71] + node _T_3651 = and(bus_rsp_read, _T_3650) @[lsu_bus_buffer.scala 476:25] + node _T_3652 = or(_T_3637, _T_3651) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[0] <= _T_3652 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[lsu_bus_buffer.scala 479:29] + node _T_3653 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_3654 = or(_T_3653, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[0] <= _T_3654 @[lsu_bus_buffer.scala 480:25] + node _T_3655 = and(buf_state_bus_en[0], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_3656 = and(_T_3655, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[0] <= _T_3656 @[lsu_bus_buffer.scala 481:24] + node _T_3657 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_3658 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 482:111] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[lsu_bus_buffer.scala 482:91] + node _T_3660 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 483:42] + node _T_3661 = and(bus_rsp_read_error, _T_3660) @[lsu_bus_buffer.scala 483:31] + node _T_3662 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 483:66] + node _T_3663 = and(_T_3661, _T_3662) @[lsu_bus_buffer.scala 483:46] + node _T_3664 = or(_T_3659, _T_3663) @[lsu_bus_buffer.scala 482:143] + node _T_3665 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 484:54] + node _T_3666 = and(bus_rsp_write_error, _T_3665) @[lsu_bus_buffer.scala 484:33] + node _T_3667 = or(_T_3664, _T_3666) @[lsu_bus_buffer.scala 483:88] + node _T_3668 = and(_T_3657, _T_3667) @[lsu_bus_buffer.scala 482:68] + buf_error_en[0] <= _T_3668 @[lsu_bus_buffer.scala 482:25] + node _T_3669 = eq(buf_error_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_3670 = and(buf_state_en[0], _T_3669) @[lsu_bus_buffer.scala 485:48] + node _T_3671 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_3672 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_3673 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_3674 = mux(_T_3671, _T_3672, _T_3673) @[lsu_bus_buffer.scala 485:72] + node _T_3675 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_3676 = mux(_T_3670, _T_3674, _T_3675) @[lsu_bus_buffer.scala 485:30] + buf_data_in[0] <= _T_3676 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3677 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3677 : @[Conditional.scala 39:67] + node _T_3678 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_3679 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 490:86] + node _T_3680 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 490:101] + node _T_3681 = bits(_T_3680, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_3682 = or(_T_3679, _T_3681) @[lsu_bus_buffer.scala 490:90] + node _T_3683 = or(_T_3682, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_3684 = mux(_T_3683, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_3685 = mux(_T_3678, UInt<3>("h00"), _T_3684) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[0] <= _T_3685 @[lsu_bus_buffer.scala 490:25] + node _T_3686 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 491:66] + node _T_3687 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 492:21] + node _T_3688 = bits(_T_3687, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_3689 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[lsu_bus_buffer.scala 492:58] + node _T_3690 = and(_T_3688, _T_3689) @[lsu_bus_buffer.scala 492:38] + node _T_3691 = or(_T_3686, _T_3690) @[lsu_bus_buffer.scala 491:95] + node _T_3692 = and(bus_rsp_read, _T_3691) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[0] <= _T_3692 @[lsu_bus_buffer.scala 491:29] + node _T_3693 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_3694 = or(_T_3693, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[0] <= _T_3694 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3695 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3695 : @[Conditional.scala 39:67] + node _T_3696 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_3697 = mux(_T_3696, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[0] <= _T_3697 @[lsu_bus_buffer.scala 498:25] + node _T_3698 = eq(RspPtr, UInt<2>("h00")) @[lsu_bus_buffer.scala 499:37] + node _T_3699 = eq(buf_dualtag[0], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_3700 = and(buf_dual[0], _T_3699) @[lsu_bus_buffer.scala 499:80] + node _T_3701 = or(_T_3698, _T_3700) @[lsu_bus_buffer.scala 499:65] + node _T_3702 = or(_T_3701, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[0] <= _T_3702 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3703 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3703 : @[Conditional.scala 39:67] + buf_nxtstate[0] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_3704 = bits(buf_state_en[0], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3704 : @[Reg.scala 28:19] + _T_3705 <= buf_nxtstate[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[0] <= _T_3705 @[lsu_bus_buffer.scala 512:18] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_3706 <= buf_age_in_0 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[0] <= _T_3706 @[lsu_bus_buffer.scala 513:17] + reg _T_3707 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_3707 <= buf_rspage_in[0] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[0] <= _T_3707 @[lsu_bus_buffer.scala 514:20] + node _T_3708 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_3709 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3708 : @[Reg.scala 28:19] + _T_3709 <= buf_dualtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[0] <= _T_3709 @[lsu_bus_buffer.scala 515:20] + node _T_3710 = bits(buf_dual_in, 0, 0) @[lsu_bus_buffer.scala 516:74] + node _T_3711 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_3712 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3711 : @[Reg.scala 28:19] + _T_3712 <= _T_3710 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[0] <= _T_3712 @[lsu_bus_buffer.scala 516:17] + node _T_3713 = bits(buf_samedw_in, 0, 0) @[lsu_bus_buffer.scala 517:78] + node _T_3714 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_3715 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3714 : @[Reg.scala 28:19] + _T_3715 <= _T_3713 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[0] <= _T_3715 @[lsu_bus_buffer.scala 517:19] + node _T_3716 = bits(buf_nomerge_in, 0, 0) @[lsu_bus_buffer.scala 518:80] + node _T_3717 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_3718 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3717 : @[Reg.scala 28:19] + _T_3718 <= _T_3716 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[0] <= _T_3718 @[lsu_bus_buffer.scala 518:20] + node _T_3719 = bits(buf_dualhi_in, 0, 0) @[lsu_bus_buffer.scala 519:78] + node _T_3720 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_3721 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3720 : @[Reg.scala 28:19] + _T_3721 <= _T_3719 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[0] <= _T_3721 @[lsu_bus_buffer.scala 519:19] + node _T_3722 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3722 : @[Conditional.scala 40:58] + node _T_3723 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3724 = mux(_T_3723, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[1] <= _T_3724 @[lsu_bus_buffer.scala 444:25] + node _T_3725 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3726 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3727 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3728 = and(_T_3726, _T_3727) @[lsu_bus_buffer.scala 445:95] + node _T_3729 = eq(UInt<1>("h01"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3730 = and(_T_3728, _T_3729) @[lsu_bus_buffer.scala 445:112] + node _T_3731 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3732 = eq(UInt<1>("h01"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3733 = and(_T_3731, _T_3732) @[lsu_bus_buffer.scala 445:161] + node _T_3734 = or(_T_3730, _T_3733) @[lsu_bus_buffer.scala 445:132] + node _T_3735 = and(_T_3725, _T_3734) @[lsu_bus_buffer.scala 445:63] + node _T_3736 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3737 = and(ibuf_drain_vld, _T_3736) @[lsu_bus_buffer.scala 445:201] + node _T_3738 = or(_T_3735, _T_3737) @[lsu_bus_buffer.scala 445:183] + buf_state_en[1] <= _T_3738 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 446:22] + buf_data_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 447:24] + node _T_3739 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3740 = and(ibuf_drain_vld, _T_3739) @[lsu_bus_buffer.scala 448:47] + node _T_3741 = bits(_T_3740, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3742 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3743 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3744 = mux(_T_3741, _T_3742, _T_3743) @[lsu_bus_buffer.scala 448:30] + buf_data_in[1] <= _T_3744 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3745 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3745 : @[Conditional.scala 39:67] + node _T_3746 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3747 = mux(_T_3746, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[1] <= _T_3747 @[lsu_bus_buffer.scala 453:25] + node _T_3748 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[1] <= _T_3748 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3749 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3749 : @[Conditional.scala 39:67] + node _T_3750 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3751 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3752 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3753 = and(_T_3751, _T_3752) @[lsu_bus_buffer.scala 459:104] + node _T_3754 = mux(_T_3753, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3755 = mux(_T_3750, UInt<3>("h00"), _T_3754) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[1] <= _T_3755 @[lsu_bus_buffer.scala 459:25] + node _T_3756 = eq(obuf_tag0, UInt<3>("h01")) @[lsu_bus_buffer.scala 460:48] + node _T_3757 = eq(obuf_tag1, UInt<3>("h01")) @[lsu_bus_buffer.scala 460:104] + node _T_3758 = and(obuf_merge, _T_3757) @[lsu_bus_buffer.scala 460:91] + node _T_3759 = or(_T_3756, _T_3758) @[lsu_bus_buffer.scala 460:77] + node _T_3760 = and(_T_3759, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3761 = and(_T_3760, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[1] <= _T_3761 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[lsu_bus_buffer.scala 461:29] + node _T_3762 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3763 = or(_T_3762, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[1] <= _T_3763 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3764 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 464:56] + node _T_3765 = eq(_T_3764, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3766 = and(buf_state_en[1], _T_3765) @[lsu_bus_buffer.scala 464:44] + node _T_3767 = and(_T_3766, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3768 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3769 = and(_T_3767, _T_3768) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[1] <= _T_3769 @[lsu_bus_buffer.scala 464:25] + node _T_3770 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[1] <= _T_3770 @[lsu_bus_buffer.scala 465:28] + node _T_3771 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3772 = and(_T_3771, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3773 = and(_T_3772, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[1] <= _T_3773 @[lsu_bus_buffer.scala 466:24] + node _T_3774 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3775 = and(_T_3774, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3776 = and(_T_3775, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[1] <= _T_3776 @[lsu_bus_buffer.scala 467:25] + node _T_3777 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3778 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3779 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3780 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3781 = mux(_T_3778, _T_3779, _T_3780) @[lsu_bus_buffer.scala 468:73] + node _T_3782 = mux(buf_error_en[1], _T_3777, _T_3781) @[lsu_bus_buffer.scala 468:30] + buf_data_in[1] <= _T_3782 @[lsu_bus_buffer.scala 468:24] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3783 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3783 : @[Conditional.scala 39:67] + node _T_3784 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 472:69] + node _T_3785 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3786 = and(_T_3784, _T_3785) @[lsu_bus_buffer.scala 472:73] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[lsu_bus_buffer.scala 472:57] + node _T_3788 = bits(_T_3787, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[lsu_bus_buffer.scala 473:28] + node _T_3791 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 473:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3793 = and(_T_3790, _T_3792) @[lsu_bus_buffer.scala 473:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3795 = and(_T_3793, _T_3794) @[lsu_bus_buffer.scala 473:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 474:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[lsu_bus_buffer.scala 474:68] + node _T_3800 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 474:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3802 = and(_T_3799, _T_3801) @[lsu_bus_buffer.scala 474:85] + node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3804 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3806 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3808 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_3810 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3814 = mux(_T_3809, _T_3810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3815 = or(_T_3811, _T_3812) @[Mux.scala 27:72] + node _T_3816 = or(_T_3815, _T_3813) @[Mux.scala 27:72] + node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] + wire _T_3818 : UInt<1> @[Mux.scala 27:72] + _T_3818 <= _T_3817 @[Mux.scala 27:72] + node _T_3819 = and(_T_3802, _T_3818) @[lsu_bus_buffer.scala 474:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_3821 = and(_T_3819, _T_3820) @[lsu_bus_buffer.scala 474:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_3823 = or(_T_3797, _T_3822) @[lsu_bus_buffer.scala 474:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[lsu_bus_buffer.scala 473:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[1] <= _T_3826 @[lsu_bus_buffer.scala 472:27] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 475:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[lsu_bus_buffer.scala 475:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 476:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 477:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 477:47] + node _T_3832 = and(_T_3830, _T_3831) @[lsu_bus_buffer.scala 477:27] + node _T_3833 = or(_T_3829, _T_3832) @[lsu_bus_buffer.scala 476:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 478:26] + node _T_3835 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 478:54] + node _T_3836 = not(_T_3835) @[lsu_bus_buffer.scala 478:44] + node _T_3837 = and(_T_3834, _T_3836) @[lsu_bus_buffer.scala 478:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[lsu_bus_buffer.scala 478:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 478:94] + node _T_3840 = and(_T_3838, _T_3839) @[lsu_bus_buffer.scala 478:74] + node _T_3841 = or(_T_3833, _T_3840) @[lsu_bus_buffer.scala 477:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[lsu_bus_buffer.scala 476:25] + node _T_3843 = or(_T_3828, _T_3842) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[1] <= _T_3843 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[lsu_bus_buffer.scala 479:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[1] <= _T_3845 @[lsu_bus_buffer.scala 480:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[1] <= _T_3847 @[lsu_bus_buffer.scala 481:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 482:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[lsu_bus_buffer.scala 482:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 483:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[lsu_bus_buffer.scala 483:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 483:66] + node _T_3854 = and(_T_3852, _T_3853) @[lsu_bus_buffer.scala 483:46] + node _T_3855 = or(_T_3850, _T_3854) @[lsu_bus_buffer.scala 482:143] + node _T_3856 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 484:54] + node _T_3857 = and(bus_rsp_write_error, _T_3856) @[lsu_bus_buffer.scala 484:33] + node _T_3858 = or(_T_3855, _T_3857) @[lsu_bus_buffer.scala 483:88] + node _T_3859 = and(_T_3848, _T_3858) @[lsu_bus_buffer.scala 482:68] + buf_error_en[1] <= _T_3859 @[lsu_bus_buffer.scala 482:25] + node _T_3860 = eq(buf_error_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_3861 = and(buf_state_en[1], _T_3860) @[lsu_bus_buffer.scala 485:48] + node _T_3862 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_3863 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_3864 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_3865 = mux(_T_3862, _T_3863, _T_3864) @[lsu_bus_buffer.scala 485:72] + node _T_3866 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_3867 = mux(_T_3861, _T_3865, _T_3866) @[lsu_bus_buffer.scala 485:30] + buf_data_in[1] <= _T_3867 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3868 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3868 : @[Conditional.scala 39:67] + node _T_3869 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_3870 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 490:86] + node _T_3871 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 490:101] + node _T_3872 = bits(_T_3871, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_3873 = or(_T_3870, _T_3872) @[lsu_bus_buffer.scala 490:90] + node _T_3874 = or(_T_3873, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_3875 = mux(_T_3874, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_3876 = mux(_T_3869, UInt<3>("h00"), _T_3875) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[1] <= _T_3876 @[lsu_bus_buffer.scala 490:25] + node _T_3877 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 491:66] + node _T_3878 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 492:21] + node _T_3879 = bits(_T_3878, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_3880 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[lsu_bus_buffer.scala 492:58] + node _T_3881 = and(_T_3879, _T_3880) @[lsu_bus_buffer.scala 492:38] + node _T_3882 = or(_T_3877, _T_3881) @[lsu_bus_buffer.scala 491:95] + node _T_3883 = and(bus_rsp_read, _T_3882) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[1] <= _T_3883 @[lsu_bus_buffer.scala 491:29] + node _T_3884 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_3885 = or(_T_3884, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[1] <= _T_3885 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3886 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3886 : @[Conditional.scala 39:67] + node _T_3887 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_3888 = mux(_T_3887, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[1] <= _T_3888 @[lsu_bus_buffer.scala 498:25] + node _T_3889 = eq(RspPtr, UInt<2>("h01")) @[lsu_bus_buffer.scala 499:37] + node _T_3890 = eq(buf_dualtag[1], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_3891 = and(buf_dual[1], _T_3890) @[lsu_bus_buffer.scala 499:80] + node _T_3892 = or(_T_3889, _T_3891) @[lsu_bus_buffer.scala 499:65] + node _T_3893 = or(_T_3892, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[1] <= _T_3893 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3894 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3894 : @[Conditional.scala 39:67] + buf_nxtstate[1] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_3895 = bits(buf_state_en[1], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_3896 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3895 : @[Reg.scala 28:19] + _T_3896 <= buf_nxtstate[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[1] <= _T_3896 @[lsu_bus_buffer.scala 512:18] + reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_3897 <= buf_age_in_1 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[1] <= _T_3897 @[lsu_bus_buffer.scala 513:17] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_3898 <= buf_rspage_in[1] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[1] <= _T_3898 @[lsu_bus_buffer.scala 514:20] + node _T_3899 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_3900 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3899 : @[Reg.scala 28:19] + _T_3900 <= buf_dualtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[1] <= _T_3900 @[lsu_bus_buffer.scala 515:20] + node _T_3901 = bits(buf_dual_in, 1, 1) @[lsu_bus_buffer.scala 516:74] + node _T_3902 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_3903 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3902 : @[Reg.scala 28:19] + _T_3903 <= _T_3901 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[1] <= _T_3903 @[lsu_bus_buffer.scala 516:17] + node _T_3904 = bits(buf_samedw_in, 1, 1) @[lsu_bus_buffer.scala 517:78] + node _T_3905 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_3906 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3905 : @[Reg.scala 28:19] + _T_3906 <= _T_3904 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[1] <= _T_3906 @[lsu_bus_buffer.scala 517:19] + node _T_3907 = bits(buf_nomerge_in, 1, 1) @[lsu_bus_buffer.scala 518:80] + node _T_3908 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_3909 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3908 : @[Reg.scala 28:19] + _T_3909 <= _T_3907 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[1] <= _T_3909 @[lsu_bus_buffer.scala 518:20] + node _T_3910 = bits(buf_dualhi_in, 1, 1) @[lsu_bus_buffer.scala 519:78] + node _T_3911 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_3912 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3911 : @[Reg.scala 28:19] + _T_3912 <= _T_3910 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[1] <= _T_3912 @[lsu_bus_buffer.scala 519:19] + node _T_3913 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3913 : @[Conditional.scala 40:58] + node _T_3914 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3915 = mux(_T_3914, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[2] <= _T_3915 @[lsu_bus_buffer.scala 444:25] + node _T_3916 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3917 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3918 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3919 = and(_T_3917, _T_3918) @[lsu_bus_buffer.scala 445:95] + node _T_3920 = eq(UInt<2>("h02"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3921 = and(_T_3919, _T_3920) @[lsu_bus_buffer.scala 445:112] + node _T_3922 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3923 = eq(UInt<2>("h02"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3924 = and(_T_3922, _T_3923) @[lsu_bus_buffer.scala 445:161] + node _T_3925 = or(_T_3921, _T_3924) @[lsu_bus_buffer.scala 445:132] + node _T_3926 = and(_T_3916, _T_3925) @[lsu_bus_buffer.scala 445:63] + node _T_3927 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3928 = and(ibuf_drain_vld, _T_3927) @[lsu_bus_buffer.scala 445:201] + node _T_3929 = or(_T_3926, _T_3928) @[lsu_bus_buffer.scala 445:183] + buf_state_en[2] <= _T_3929 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 446:22] + buf_data_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 447:24] + node _T_3930 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3931 = and(ibuf_drain_vld, _T_3930) @[lsu_bus_buffer.scala 448:47] + node _T_3932 = bits(_T_3931, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3933 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3934 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3935 = mux(_T_3932, _T_3933, _T_3934) @[lsu_bus_buffer.scala 448:30] + buf_data_in[2] <= _T_3935 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3936 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3936 : @[Conditional.scala 39:67] + node _T_3937 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3938 = mux(_T_3937, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[2] <= _T_3938 @[lsu_bus_buffer.scala 453:25] + node _T_3939 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[2] <= _T_3939 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3940 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3940 : @[Conditional.scala 39:67] + node _T_3941 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3942 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3943 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3944 = and(_T_3942, _T_3943) @[lsu_bus_buffer.scala 459:104] + node _T_3945 = mux(_T_3944, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3946 = mux(_T_3941, UInt<3>("h00"), _T_3945) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[2] <= _T_3946 @[lsu_bus_buffer.scala 459:25] + node _T_3947 = eq(obuf_tag0, UInt<3>("h02")) @[lsu_bus_buffer.scala 460:48] + node _T_3948 = eq(obuf_tag1, UInt<3>("h02")) @[lsu_bus_buffer.scala 460:104] + node _T_3949 = and(obuf_merge, _T_3948) @[lsu_bus_buffer.scala 460:91] + node _T_3950 = or(_T_3947, _T_3949) @[lsu_bus_buffer.scala 460:77] + node _T_3951 = and(_T_3950, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3952 = and(_T_3951, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[2] <= _T_3952 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[lsu_bus_buffer.scala 461:29] + node _T_3953 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3954 = or(_T_3953, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[2] <= _T_3954 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3955 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 464:56] + node _T_3956 = eq(_T_3955, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3957 = and(buf_state_en[2], _T_3956) @[lsu_bus_buffer.scala 464:44] + node _T_3958 = and(_T_3957, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3959 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3960 = and(_T_3958, _T_3959) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[2] <= _T_3960 @[lsu_bus_buffer.scala 464:25] + node _T_3961 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[2] <= _T_3961 @[lsu_bus_buffer.scala 465:28] + node _T_3962 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3963 = and(_T_3962, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3964 = and(_T_3963, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[2] <= _T_3964 @[lsu_bus_buffer.scala 466:24] + node _T_3965 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3966 = and(_T_3965, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3967 = and(_T_3966, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[2] <= _T_3967 @[lsu_bus_buffer.scala 467:25] + node _T_3968 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3969 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3970 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3971 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3972 = mux(_T_3969, _T_3970, _T_3971) @[lsu_bus_buffer.scala 468:73] + node _T_3973 = mux(buf_error_en[2], _T_3968, _T_3972) @[lsu_bus_buffer.scala 468:30] + buf_data_in[2] <= _T_3973 @[lsu_bus_buffer.scala 468:24] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3974 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3974 : @[Conditional.scala 39:67] + node _T_3975 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 472:69] + node _T_3976 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3977 = and(_T_3975, _T_3976) @[lsu_bus_buffer.scala 472:73] + node _T_3978 = or(io.dec_tlu_force_halt, _T_3977) @[lsu_bus_buffer.scala 472:57] + node _T_3979 = bits(_T_3978, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3980 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3981 = and(buf_dual[2], _T_3980) @[lsu_bus_buffer.scala 473:28] + node _T_3982 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 473:57] + node _T_3983 = eq(_T_3982, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3984 = and(_T_3981, _T_3983) @[lsu_bus_buffer.scala 473:45] + node _T_3985 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3986 = and(_T_3984, _T_3985) @[lsu_bus_buffer.scala 473:61] + node _T_3987 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 474:27] + node _T_3988 = or(_T_3987, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3989 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3990 = and(buf_dual[2], _T_3989) @[lsu_bus_buffer.scala 474:68] + node _T_3991 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 474:97] + node _T_3992 = eq(_T_3991, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3993 = and(_T_3990, _T_3992) @[lsu_bus_buffer.scala 474:85] + node _T_3994 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3995 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3996 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3997 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3998 = eq(buf_dualtag[2], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3999 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4000 = eq(buf_dualtag[2], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4001 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4002 = mux(_T_3994, _T_3995, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4003 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4004 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4005 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4006 = or(_T_4002, _T_4003) @[Mux.scala 27:72] + node _T_4007 = or(_T_4006, _T_4004) @[Mux.scala 27:72] + node _T_4008 = or(_T_4007, _T_4005) @[Mux.scala 27:72] + wire _T_4009 : UInt<1> @[Mux.scala 27:72] + _T_4009 <= _T_4008 @[Mux.scala 27:72] + node _T_4010 = and(_T_3993, _T_4009) @[lsu_bus_buffer.scala 474:101] + node _T_4011 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_4012 = and(_T_4010, _T_4011) @[lsu_bus_buffer.scala 474:138] + node _T_4013 = and(_T_4012, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_4014 = or(_T_3988, _T_4013) @[lsu_bus_buffer.scala 474:53] + node _T_4015 = mux(_T_4014, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_4016 = mux(_T_3986, UInt<3>("h04"), _T_4015) @[lsu_bus_buffer.scala 473:14] + node _T_4017 = mux(_T_3979, UInt<3>("h00"), _T_4016) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[2] <= _T_4017 @[lsu_bus_buffer.scala 472:27] + node _T_4018 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 475:73] + node _T_4019 = and(bus_rsp_write, _T_4018) @[lsu_bus_buffer.scala 475:52] + node _T_4020 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 476:46] + node _T_4021 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 477:23] + node _T_4022 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 477:47] + node _T_4023 = and(_T_4021, _T_4022) @[lsu_bus_buffer.scala 477:27] + node _T_4024 = or(_T_4020, _T_4023) @[lsu_bus_buffer.scala 476:77] + node _T_4025 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 478:26] + node _T_4026 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 478:54] + node _T_4027 = not(_T_4026) @[lsu_bus_buffer.scala 478:44] + node _T_4028 = and(_T_4025, _T_4027) @[lsu_bus_buffer.scala 478:42] + node _T_4029 = and(_T_4028, buf_samedw[2]) @[lsu_bus_buffer.scala 478:58] + node _T_4030 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 478:94] + node _T_4031 = and(_T_4029, _T_4030) @[lsu_bus_buffer.scala 478:74] + node _T_4032 = or(_T_4024, _T_4031) @[lsu_bus_buffer.scala 477:71] + node _T_4033 = and(bus_rsp_read, _T_4032) @[lsu_bus_buffer.scala 476:25] + node _T_4034 = or(_T_4019, _T_4033) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[2] <= _T_4034 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[lsu_bus_buffer.scala 479:29] + node _T_4035 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_4036 = or(_T_4035, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[2] <= _T_4036 @[lsu_bus_buffer.scala 480:25] + node _T_4037 = and(buf_state_bus_en[2], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_4038 = and(_T_4037, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[2] <= _T_4038 @[lsu_bus_buffer.scala 481:24] + node _T_4039 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_4040 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 482:111] + node _T_4041 = and(bus_rsp_read_error, _T_4040) @[lsu_bus_buffer.scala 482:91] + node _T_4042 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 483:42] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[lsu_bus_buffer.scala 483:31] + node _T_4044 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 483:66] + node _T_4045 = and(_T_4043, _T_4044) @[lsu_bus_buffer.scala 483:46] + node _T_4046 = or(_T_4041, _T_4045) @[lsu_bus_buffer.scala 482:143] + node _T_4047 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 484:54] + node _T_4048 = and(bus_rsp_write_error, _T_4047) @[lsu_bus_buffer.scala 484:33] + node _T_4049 = or(_T_4046, _T_4048) @[lsu_bus_buffer.scala 483:88] + node _T_4050 = and(_T_4039, _T_4049) @[lsu_bus_buffer.scala 482:68] + buf_error_en[2] <= _T_4050 @[lsu_bus_buffer.scala 482:25] + node _T_4051 = eq(buf_error_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_4052 = and(buf_state_en[2], _T_4051) @[lsu_bus_buffer.scala 485:48] + node _T_4053 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_4054 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_4055 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_4056 = mux(_T_4053, _T_4054, _T_4055) @[lsu_bus_buffer.scala 485:72] + node _T_4057 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_4058 = mux(_T_4052, _T_4056, _T_4057) @[lsu_bus_buffer.scala 485:30] + buf_data_in[2] <= _T_4058 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4059 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4059 : @[Conditional.scala 39:67] + node _T_4060 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_4061 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 490:86] + node _T_4062 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 490:101] + node _T_4063 = bits(_T_4062, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_4064 = or(_T_4061, _T_4063) @[lsu_bus_buffer.scala 490:90] + node _T_4065 = or(_T_4064, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_4066 = mux(_T_4065, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_4067 = mux(_T_4060, UInt<3>("h00"), _T_4066) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[2] <= _T_4067 @[lsu_bus_buffer.scala 490:25] + node _T_4068 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 491:66] + node _T_4069 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 492:21] + node _T_4070 = bits(_T_4069, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_4071 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[lsu_bus_buffer.scala 492:58] + node _T_4072 = and(_T_4070, _T_4071) @[lsu_bus_buffer.scala 492:38] + node _T_4073 = or(_T_4068, _T_4072) @[lsu_bus_buffer.scala 491:95] + node _T_4074 = and(bus_rsp_read, _T_4073) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[2] <= _T_4074 @[lsu_bus_buffer.scala 491:29] + node _T_4075 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_4076 = or(_T_4075, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[2] <= _T_4076 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4077 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4077 : @[Conditional.scala 39:67] + node _T_4078 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_4079 = mux(_T_4078, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[2] <= _T_4079 @[lsu_bus_buffer.scala 498:25] + node _T_4080 = eq(RspPtr, UInt<2>("h02")) @[lsu_bus_buffer.scala 499:37] + node _T_4081 = eq(buf_dualtag[2], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_4082 = and(buf_dual[2], _T_4081) @[lsu_bus_buffer.scala 499:80] + node _T_4083 = or(_T_4080, _T_4082) @[lsu_bus_buffer.scala 499:65] + node _T_4084 = or(_T_4083, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[2] <= _T_4084 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4085 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4085 : @[Conditional.scala 39:67] + buf_nxtstate[2] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_4086 = bits(buf_state_en[2], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_4087 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4086 : @[Reg.scala 28:19] + _T_4087 <= buf_nxtstate[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[2] <= _T_4087 @[lsu_bus_buffer.scala 512:18] + reg _T_4088 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_4088 <= buf_age_in_2 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[2] <= _T_4088 @[lsu_bus_buffer.scala 513:17] + reg _T_4089 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_4089 <= buf_rspage_in[2] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[2] <= _T_4089 @[lsu_bus_buffer.scala 514:20] + node _T_4090 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4090 : @[Reg.scala 28:19] + _T_4091 <= buf_dualtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[2] <= _T_4091 @[lsu_bus_buffer.scala 515:20] + node _T_4092 = bits(buf_dual_in, 2, 2) @[lsu_bus_buffer.scala 516:74] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_4094 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4093 : @[Reg.scala 28:19] + _T_4094 <= _T_4092 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[2] <= _T_4094 @[lsu_bus_buffer.scala 516:17] + node _T_4095 = bits(buf_samedw_in, 2, 2) @[lsu_bus_buffer.scala 517:78] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4096 : @[Reg.scala 28:19] + _T_4097 <= _T_4095 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[2] <= _T_4097 @[lsu_bus_buffer.scala 517:19] + node _T_4098 = bits(buf_nomerge_in, 2, 2) @[lsu_bus_buffer.scala 518:80] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4099 : @[Reg.scala 28:19] + _T_4100 <= _T_4098 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[2] <= _T_4100 @[lsu_bus_buffer.scala 518:20] + node _T_4101 = bits(buf_dualhi_in, 2, 2) @[lsu_bus_buffer.scala 519:78] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4102 : @[Reg.scala 28:19] + _T_4103 <= _T_4101 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[2] <= _T_4103 @[lsu_bus_buffer.scala 519:19] + node _T_4104 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4104 : @[Conditional.scala 40:58] + node _T_4105 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_4106 = mux(_T_4105, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[3] <= _T_4106 @[lsu_bus_buffer.scala 444:25] + node _T_4107 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_4108 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_4109 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_4110 = and(_T_4108, _T_4109) @[lsu_bus_buffer.scala 445:95] + node _T_4111 = eq(UInt<2>("h03"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_4112 = and(_T_4110, _T_4111) @[lsu_bus_buffer.scala 445:112] + node _T_4113 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_4114 = eq(UInt<2>("h03"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_4115 = and(_T_4113, _T_4114) @[lsu_bus_buffer.scala 445:161] + node _T_4116 = or(_T_4112, _T_4115) @[lsu_bus_buffer.scala 445:132] + node _T_4117 = and(_T_4107, _T_4116) @[lsu_bus_buffer.scala 445:63] + node _T_4118 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_4119 = and(ibuf_drain_vld, _T_4118) @[lsu_bus_buffer.scala 445:201] + node _T_4120 = or(_T_4117, _T_4119) @[lsu_bus_buffer.scala 445:183] + buf_state_en[3] <= _T_4120 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 446:22] + buf_data_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 447:24] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[lsu_bus_buffer.scala 448:47] + node _T_4123 = bits(_T_4122, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_4124 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_4125 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_4126 = mux(_T_4123, _T_4124, _T_4125) @[lsu_bus_buffer.scala 448:30] + buf_data_in[3] <= _T_4126 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_4127 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4127 : @[Conditional.scala 39:67] + node _T_4128 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_4129 = mux(_T_4128, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[3] <= _T_4129 @[lsu_bus_buffer.scala 453:25] + node _T_4130 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[3] <= _T_4130 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4131 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4131 : @[Conditional.scala 39:67] + node _T_4132 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_4133 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_4134 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_4135 = and(_T_4133, _T_4134) @[lsu_bus_buffer.scala 459:104] + node _T_4136 = mux(_T_4135, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_4137 = mux(_T_4132, UInt<3>("h00"), _T_4136) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[3] <= _T_4137 @[lsu_bus_buffer.scala 459:25] + node _T_4138 = eq(obuf_tag0, UInt<3>("h03")) @[lsu_bus_buffer.scala 460:48] + node _T_4139 = eq(obuf_tag1, UInt<3>("h03")) @[lsu_bus_buffer.scala 460:104] + node _T_4140 = and(obuf_merge, _T_4139) @[lsu_bus_buffer.scala 460:91] + node _T_4141 = or(_T_4138, _T_4140) @[lsu_bus_buffer.scala 460:77] + node _T_4142 = and(_T_4141, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_4143 = and(_T_4142, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[3] <= _T_4143 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[lsu_bus_buffer.scala 461:29] + node _T_4144 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_4145 = or(_T_4144, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[3] <= _T_4145 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_4146 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 464:56] + node _T_4147 = eq(_T_4146, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_4148 = and(buf_state_en[3], _T_4147) @[lsu_bus_buffer.scala 464:44] + node _T_4149 = and(_T_4148, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_4150 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_4151 = and(_T_4149, _T_4150) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[3] <= _T_4151 @[lsu_bus_buffer.scala 464:25] + node _T_4152 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[3] <= _T_4152 @[lsu_bus_buffer.scala 465:28] + node _T_4153 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_4154 = and(_T_4153, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_4155 = and(_T_4154, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[3] <= _T_4155 @[lsu_bus_buffer.scala 466:24] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_4157 = and(_T_4156, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_4158 = and(_T_4157, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[3] <= _T_4158 @[lsu_bus_buffer.scala 467:25] + node _T_4159 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_4160 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_4161 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_4163 = mux(_T_4160, _T_4161, _T_4162) @[lsu_bus_buffer.scala 468:73] + node _T_4164 = mux(buf_error_en[3], _T_4159, _T_4163) @[lsu_bus_buffer.scala 468:30] + buf_data_in[3] <= _T_4164 @[lsu_bus_buffer.scala 468:24] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4165 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4165 : @[Conditional.scala 39:67] + node _T_4166 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 472:69] + node _T_4167 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_4168 = and(_T_4166, _T_4167) @[lsu_bus_buffer.scala 472:73] + node _T_4169 = or(io.dec_tlu_force_halt, _T_4168) @[lsu_bus_buffer.scala 472:57] + node _T_4170 = bits(_T_4169, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_4171 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_4172 = and(buf_dual[3], _T_4171) @[lsu_bus_buffer.scala 473:28] + node _T_4173 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 473:57] + node _T_4174 = eq(_T_4173, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_4175 = and(_T_4172, _T_4174) @[lsu_bus_buffer.scala 473:45] + node _T_4176 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_4177 = and(_T_4175, _T_4176) @[lsu_bus_buffer.scala 473:61] + node _T_4178 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 474:27] + node _T_4179 = or(_T_4178, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_4180 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_4181 = and(buf_dual[3], _T_4180) @[lsu_bus_buffer.scala 474:68] + node _T_4182 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 474:97] + node _T_4183 = eq(_T_4182, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_4184 = and(_T_4181, _T_4183) @[lsu_bus_buffer.scala 474:85] + node _T_4185 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_4186 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_4187 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_4188 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_4189 = eq(buf_dualtag[3], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_4190 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4191 = eq(buf_dualtag[3], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4192 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4193 = mux(_T_4185, _T_4186, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4194 = mux(_T_4187, _T_4188, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4195 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4196 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4197 = or(_T_4193, _T_4194) @[Mux.scala 27:72] + node _T_4198 = or(_T_4197, _T_4195) @[Mux.scala 27:72] + node _T_4199 = or(_T_4198, _T_4196) @[Mux.scala 27:72] + wire _T_4200 : UInt<1> @[Mux.scala 27:72] + _T_4200 <= _T_4199 @[Mux.scala 27:72] + node _T_4201 = and(_T_4184, _T_4200) @[lsu_bus_buffer.scala 474:101] + node _T_4202 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_4203 = and(_T_4201, _T_4202) @[lsu_bus_buffer.scala 474:138] + node _T_4204 = and(_T_4203, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_4205 = or(_T_4179, _T_4204) @[lsu_bus_buffer.scala 474:53] + node _T_4206 = mux(_T_4205, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_4207 = mux(_T_4177, UInt<3>("h04"), _T_4206) @[lsu_bus_buffer.scala 473:14] + node _T_4208 = mux(_T_4170, UInt<3>("h00"), _T_4207) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[3] <= _T_4208 @[lsu_bus_buffer.scala 472:27] + node _T_4209 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 475:73] + node _T_4210 = and(bus_rsp_write, _T_4209) @[lsu_bus_buffer.scala 475:52] + node _T_4211 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 476:46] + node _T_4212 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 477:23] + node _T_4213 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 477:47] + node _T_4214 = and(_T_4212, _T_4213) @[lsu_bus_buffer.scala 477:27] + node _T_4215 = or(_T_4211, _T_4214) @[lsu_bus_buffer.scala 476:77] + node _T_4216 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 478:26] + node _T_4217 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 478:54] + node _T_4218 = not(_T_4217) @[lsu_bus_buffer.scala 478:44] + node _T_4219 = and(_T_4216, _T_4218) @[lsu_bus_buffer.scala 478:42] + node _T_4220 = and(_T_4219, buf_samedw[3]) @[lsu_bus_buffer.scala 478:58] + node _T_4221 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 478:94] + node _T_4222 = and(_T_4220, _T_4221) @[lsu_bus_buffer.scala 478:74] + node _T_4223 = or(_T_4215, _T_4222) @[lsu_bus_buffer.scala 477:71] + node _T_4224 = and(bus_rsp_read, _T_4223) @[lsu_bus_buffer.scala 476:25] + node _T_4225 = or(_T_4210, _T_4224) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[3] <= _T_4225 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[lsu_bus_buffer.scala 479:29] + node _T_4226 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_4227 = or(_T_4226, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[3] <= _T_4227 @[lsu_bus_buffer.scala 480:25] + node _T_4228 = and(buf_state_bus_en[3], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_4229 = and(_T_4228, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[3] <= _T_4229 @[lsu_bus_buffer.scala 481:24] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_4231 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 482:111] + node _T_4232 = and(bus_rsp_read_error, _T_4231) @[lsu_bus_buffer.scala 482:91] + node _T_4233 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 483:42] + node _T_4234 = and(bus_rsp_read_error, _T_4233) @[lsu_bus_buffer.scala 483:31] + node _T_4235 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 483:66] + node _T_4236 = and(_T_4234, _T_4235) @[lsu_bus_buffer.scala 483:46] + node _T_4237 = or(_T_4232, _T_4236) @[lsu_bus_buffer.scala 482:143] + node _T_4238 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 484:54] + node _T_4239 = and(bus_rsp_write_error, _T_4238) @[lsu_bus_buffer.scala 484:33] + node _T_4240 = or(_T_4237, _T_4239) @[lsu_bus_buffer.scala 483:88] + node _T_4241 = and(_T_4230, _T_4240) @[lsu_bus_buffer.scala 482:68] + buf_error_en[3] <= _T_4241 @[lsu_bus_buffer.scala 482:25] + node _T_4242 = eq(buf_error_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_4243 = and(buf_state_en[3], _T_4242) @[lsu_bus_buffer.scala 485:48] + node _T_4244 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_4245 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_4246 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_4247 = mux(_T_4244, _T_4245, _T_4246) @[lsu_bus_buffer.scala 485:72] + node _T_4248 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_4249 = mux(_T_4243, _T_4247, _T_4248) @[lsu_bus_buffer.scala 485:30] + buf_data_in[3] <= _T_4249 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4250 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4250 : @[Conditional.scala 39:67] + node _T_4251 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_4252 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 490:86] + node _T_4253 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 490:101] + node _T_4254 = bits(_T_4253, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_4255 = or(_T_4252, _T_4254) @[lsu_bus_buffer.scala 490:90] + node _T_4256 = or(_T_4255, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_4257 = mux(_T_4256, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_4258 = mux(_T_4251, UInt<3>("h00"), _T_4257) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[3] <= _T_4258 @[lsu_bus_buffer.scala 490:25] + node _T_4259 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 491:66] + node _T_4260 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 492:21] + node _T_4261 = bits(_T_4260, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_4262 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[lsu_bus_buffer.scala 492:58] + node _T_4263 = and(_T_4261, _T_4262) @[lsu_bus_buffer.scala 492:38] + node _T_4264 = or(_T_4259, _T_4263) @[lsu_bus_buffer.scala 491:95] + node _T_4265 = and(bus_rsp_read, _T_4264) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[3] <= _T_4265 @[lsu_bus_buffer.scala 491:29] + node _T_4266 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_4267 = or(_T_4266, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[3] <= _T_4267 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4268 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4268 : @[Conditional.scala 39:67] + node _T_4269 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_4270 = mux(_T_4269, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[3] <= _T_4270 @[lsu_bus_buffer.scala 498:25] + node _T_4271 = eq(RspPtr, UInt<2>("h03")) @[lsu_bus_buffer.scala 499:37] + node _T_4272 = eq(buf_dualtag[3], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_4273 = and(buf_dual[3], _T_4272) @[lsu_bus_buffer.scala 499:80] + node _T_4274 = or(_T_4271, _T_4273) @[lsu_bus_buffer.scala 499:65] + node _T_4275 = or(_T_4274, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[3] <= _T_4275 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4276 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4276 : @[Conditional.scala 39:67] + buf_nxtstate[3] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_4277 = bits(buf_state_en[3], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_4278 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4277 : @[Reg.scala 28:19] + _T_4278 <= buf_nxtstate[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[3] <= _T_4278 @[lsu_bus_buffer.scala 512:18] + reg _T_4279 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_4279 <= buf_age_in_3 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[3] <= _T_4279 @[lsu_bus_buffer.scala 513:17] + reg _T_4280 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_4280 <= buf_rspage_in[3] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[3] <= _T_4280 @[lsu_bus_buffer.scala 514:20] + node _T_4281 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_4282 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4281 : @[Reg.scala 28:19] + _T_4282 <= buf_dualtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[3] <= _T_4282 @[lsu_bus_buffer.scala 515:20] + node _T_4283 = bits(buf_dual_in, 3, 3) @[lsu_bus_buffer.scala 516:74] + node _T_4284 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_4285 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4284 : @[Reg.scala 28:19] + _T_4285 <= _T_4283 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[3] <= _T_4285 @[lsu_bus_buffer.scala 516:17] + node _T_4286 = bits(buf_samedw_in, 3, 3) @[lsu_bus_buffer.scala 517:78] + node _T_4287 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_4288 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4287 : @[Reg.scala 28:19] + _T_4288 <= _T_4286 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[3] <= _T_4288 @[lsu_bus_buffer.scala 517:19] + node _T_4289 = bits(buf_nomerge_in, 3, 3) @[lsu_bus_buffer.scala 518:80] + node _T_4290 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_4291 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4290 : @[Reg.scala 28:19] + _T_4291 <= _T_4289 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[3] <= _T_4291 @[lsu_bus_buffer.scala 518:20] + node _T_4292 = bits(buf_dualhi_in, 3, 3) @[lsu_bus_buffer.scala 519:78] + node _T_4293 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_4294 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4293 : @[Reg.scala 28:19] + _T_4294 <= _T_4292 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[3] <= _T_4294 @[lsu_bus_buffer.scala 519:19] + node _T_4295 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4295 : @[Reg.scala 28:19] + _T_4296 <= buf_ldfwd_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4297 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4298 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4297 : @[Reg.scala 28:19] + _T_4298 <= buf_ldfwd_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4299 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4300 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4299 : @[Reg.scala 28:19] + _T_4300 <= buf_ldfwd_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4301 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4302 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4301 : @[Reg.scala 28:19] + _T_4302 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4303 = cat(_T_4302, _T_4300) @[Cat.scala 29:58] + node _T_4304 = cat(_T_4303, _T_4298) @[Cat.scala 29:58] + node _T_4305 = cat(_T_4304, _T_4296) @[Cat.scala 29:58] + buf_ldfwd <= _T_4305 @[lsu_bus_buffer.scala 522:13] + node _T_4306 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4307 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4306 : @[Reg.scala 28:19] + _T_4307 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4308 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4309 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4308 : @[Reg.scala 28:19] + _T_4309 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4310 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4311 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4310 : @[Reg.scala 28:19] + _T_4311 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4312 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4313 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4312 : @[Reg.scala 28:19] + _T_4313 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_ldfwdtag[0] <= _T_4307 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[1] <= _T_4309 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[2] <= _T_4311 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[3] <= _T_4313 @[lsu_bus_buffer.scala 523:16] + node _T_4314 = bits(buf_sideeffect_in, 0, 0) @[lsu_bus_buffer.scala 524:105] + node _T_4315 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4316 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4315 : @[Reg.scala 28:19] + _T_4316 <= _T_4314 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4317 = bits(buf_sideeffect_in, 1, 1) @[lsu_bus_buffer.scala 524:105] + node _T_4318 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4319 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4318 : @[Reg.scala 28:19] + _T_4319 <= _T_4317 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4320 = bits(buf_sideeffect_in, 2, 2) @[lsu_bus_buffer.scala 524:105] + node _T_4321 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4322 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4321 : @[Reg.scala 28:19] + _T_4322 <= _T_4320 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4323 = bits(buf_sideeffect_in, 3, 3) @[lsu_bus_buffer.scala 524:105] + node _T_4324 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4325 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4324 : @[Reg.scala 28:19] + _T_4325 <= _T_4323 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4326 = cat(_T_4325, _T_4322) @[Cat.scala 29:58] + node _T_4327 = cat(_T_4326, _T_4319) @[Cat.scala 29:58] + node _T_4328 = cat(_T_4327, _T_4316) @[Cat.scala 29:58] + buf_sideeffect <= _T_4328 @[lsu_bus_buffer.scala 524:18] + node _T_4329 = bits(buf_unsign_in, 0, 0) @[lsu_bus_buffer.scala 525:97] + node _T_4330 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4331 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4330 : @[Reg.scala 28:19] + _T_4331 <= _T_4329 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4332 = bits(buf_unsign_in, 1, 1) @[lsu_bus_buffer.scala 525:97] + node _T_4333 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4334 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4333 : @[Reg.scala 28:19] + _T_4334 <= _T_4332 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4335 = bits(buf_unsign_in, 2, 2) @[lsu_bus_buffer.scala 525:97] + node _T_4336 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4337 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4336 : @[Reg.scala 28:19] + _T_4337 <= _T_4335 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4338 = bits(buf_unsign_in, 3, 3) @[lsu_bus_buffer.scala 525:97] + node _T_4339 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4340 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4339 : @[Reg.scala 28:19] + _T_4340 <= _T_4338 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4341 = cat(_T_4340, _T_4337) @[Cat.scala 29:58] + node _T_4342 = cat(_T_4341, _T_4334) @[Cat.scala 29:58] + node _T_4343 = cat(_T_4342, _T_4331) @[Cat.scala 29:58] + buf_unsign <= _T_4343 @[lsu_bus_buffer.scala 525:14] + node _T_4344 = bits(buf_write_in, 0, 0) @[lsu_bus_buffer.scala 526:95] + node _T_4345 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4346 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4345 : @[Reg.scala 28:19] + _T_4346 <= _T_4344 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4347 = bits(buf_write_in, 1, 1) @[lsu_bus_buffer.scala 526:95] + node _T_4348 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4349 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4348 : @[Reg.scala 28:19] + _T_4349 <= _T_4347 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4350 = bits(buf_write_in, 2, 2) @[lsu_bus_buffer.scala 526:95] + node _T_4351 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4352 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4351 : @[Reg.scala 28:19] + _T_4352 <= _T_4350 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4353 = bits(buf_write_in, 3, 3) @[lsu_bus_buffer.scala 526:95] + node _T_4354 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4355 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4354 : @[Reg.scala 28:19] + _T_4355 <= _T_4353 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4356 = cat(_T_4355, _T_4352) @[Cat.scala 29:58] + node _T_4357 = cat(_T_4356, _T_4349) @[Cat.scala 29:58] + node _T_4358 = cat(_T_4357, _T_4346) @[Cat.scala 29:58] + buf_write <= _T_4358 @[lsu_bus_buffer.scala 526:13] + node _T_4359 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4360 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4359 : @[Reg.scala 28:19] + _T_4360 <= buf_sz_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4361 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4362 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4361 : @[Reg.scala 28:19] + _T_4362 <= buf_sz_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4363 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4364 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4363 : @[Reg.scala 28:19] + _T_4364 <= buf_sz_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4365 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4366 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4365 : @[Reg.scala 28:19] + _T_4366 <= buf_sz_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_sz[0] <= _T_4360 @[lsu_bus_buffer.scala 527:10] + buf_sz[1] <= _T_4362 @[lsu_bus_buffer.scala 527:10] + buf_sz[2] <= _T_4364 @[lsu_bus_buffer.scala 527:10] + buf_sz[3] <= _T_4366 @[lsu_bus_buffer.scala 527:10] + node _T_4367 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_4 of rvclkhdr_26 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_4367 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4368 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4367 : @[Reg.scala 28:19] + _T_4368 <= buf_addr_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4369 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_5 of rvclkhdr_27 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_4369 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4370 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4369 : @[Reg.scala 28:19] + _T_4370 <= buf_addr_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4371 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_6 of rvclkhdr_28 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_4371 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4372 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4371 : @[Reg.scala 28:19] + _T_4372 <= buf_addr_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4373 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_7 of rvclkhdr_29 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_4373 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4374 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4373 : @[Reg.scala 28:19] + _T_4374 <= buf_addr_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_addr[0] <= _T_4368 @[lsu_bus_buffer.scala 528:12] + buf_addr[1] <= _T_4370 @[lsu_bus_buffer.scala 528:12] + buf_addr[2] <= _T_4372 @[lsu_bus_buffer.scala 528:12] + buf_addr[3] <= _T_4374 @[lsu_bus_buffer.scala 528:12] + node _T_4375 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4376 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4375 : @[Reg.scala 28:19] + _T_4376 <= buf_byteen_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4377 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4378 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4377 : @[Reg.scala 28:19] + _T_4378 <= buf_byteen_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4379 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4380 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4379 : @[Reg.scala 28:19] + _T_4380 <= buf_byteen_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4381 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4382 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4381 : @[Reg.scala 28:19] + _T_4382 <= buf_byteen_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen[0] <= _T_4376 @[lsu_bus_buffer.scala 529:14] + buf_byteen[1] <= _T_4378 @[lsu_bus_buffer.scala 529:14] + buf_byteen[2] <= _T_4380 @[lsu_bus_buffer.scala 529:14] + buf_byteen[3] <= _T_4382 @[lsu_bus_buffer.scala 529:14] + inst rvclkhdr_8 of rvclkhdr_30 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4383 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[0] : @[Reg.scala 28:19] + _T_4383 <= buf_data_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_9 of rvclkhdr_31 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4384 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[1] : @[Reg.scala 28:19] + _T_4384 <= buf_data_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_10 of rvclkhdr_32 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4385 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[2] : @[Reg.scala 28:19] + _T_4385 <= buf_data_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_11 of rvclkhdr_33 @[lib.scala 404:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 407:17] + rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4386 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[3] : @[Reg.scala 28:19] + _T_4386 <= buf_data_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_data[0] <= _T_4383 @[lsu_bus_buffer.scala 530:12] + buf_data[1] <= _T_4384 @[lsu_bus_buffer.scala 530:12] + buf_data[2] <= _T_4385 @[lsu_bus_buffer.scala 530:12] + buf_data[3] <= _T_4386 @[lsu_bus_buffer.scala 530:12] + node _T_4387 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4388 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 531:133] + node _T_4389 = mux(buf_error_en[0], UInt<1>("h01"), _T_4388) @[lsu_bus_buffer.scala 531:98] + node _T_4390 = and(_T_4387, _T_4389) @[lsu_bus_buffer.scala 531:93] + reg _T_4391 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4391 <= _T_4390 @[lsu_bus_buffer.scala 531:80] + node _T_4392 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4393 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 531:133] + node _T_4394 = mux(buf_error_en[1], UInt<1>("h01"), _T_4393) @[lsu_bus_buffer.scala 531:98] + node _T_4395 = and(_T_4392, _T_4394) @[lsu_bus_buffer.scala 531:93] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4396 <= _T_4395 @[lsu_bus_buffer.scala 531:80] + node _T_4397 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4398 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 531:133] + node _T_4399 = mux(buf_error_en[2], UInt<1>("h01"), _T_4398) @[lsu_bus_buffer.scala 531:98] + node _T_4400 = and(_T_4397, _T_4399) @[lsu_bus_buffer.scala 531:93] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4401 <= _T_4400 @[lsu_bus_buffer.scala 531:80] + node _T_4402 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4403 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 531:133] + node _T_4404 = mux(buf_error_en[3], UInt<1>("h01"), _T_4403) @[lsu_bus_buffer.scala 531:98] + node _T_4405 = and(_T_4402, _T_4404) @[lsu_bus_buffer.scala 531:93] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4406 <= _T_4405 @[lsu_bus_buffer.scala 531:80] + node _T_4407 = cat(_T_4406, _T_4401) @[Cat.scala 29:58] + node _T_4408 = cat(_T_4407, _T_4396) @[Cat.scala 29:58] + node _T_4409 = cat(_T_4408, _T_4391) @[Cat.scala 29:58] + buf_error <= _T_4409 @[lsu_bus_buffer.scala 531:13] + node _T_4410 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4411 = mux(io.ldst_dual_m, _T_4410, io.lsu_busreq_m) @[lsu_bus_buffer.scala 532:28] + node _T_4412 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4413 = mux(io.ldst_dual_r, _T_4412, io.lsu_busreq_r) @[lsu_bus_buffer.scala 532:94] + node _T_4414 = add(_T_4411, _T_4413) @[lsu_bus_buffer.scala 532:88] + node _T_4415 = add(_T_4414, ibuf_valid) @[lsu_bus_buffer.scala 532:154] + node _T_4416 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4417 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4418 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4419 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4420 = add(_T_4416, _T_4417) @[lsu_bus_buffer.scala 532:217] + node _T_4421 = add(_T_4420, _T_4418) @[lsu_bus_buffer.scala 532:217] + node _T_4422 = add(_T_4421, _T_4419) @[lsu_bus_buffer.scala 532:217] + node _T_4423 = add(_T_4415, _T_4422) @[lsu_bus_buffer.scala 532:169] + node buf_numvld_any = tail(_T_4423, 1) @[lsu_bus_buffer.scala 532:169] + node _T_4424 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 533:60] + node _T_4425 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4426 = and(_T_4424, _T_4425) @[lsu_bus_buffer.scala 533:64] + node _T_4427 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4428 = and(_T_4426, _T_4427) @[lsu_bus_buffer.scala 533:89] + node _T_4429 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 533:60] + node _T_4430 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4431 = and(_T_4429, _T_4430) @[lsu_bus_buffer.scala 533:64] + node _T_4432 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4433 = and(_T_4431, _T_4432) @[lsu_bus_buffer.scala 533:89] + node _T_4434 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 533:60] + node _T_4435 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4436 = and(_T_4434, _T_4435) @[lsu_bus_buffer.scala 533:64] + node _T_4437 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4438 = and(_T_4436, _T_4437) @[lsu_bus_buffer.scala 533:89] + node _T_4439 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 533:60] + node _T_4440 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4441 = and(_T_4439, _T_4440) @[lsu_bus_buffer.scala 533:64] + node _T_4442 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4443 = and(_T_4441, _T_4442) @[lsu_bus_buffer.scala 533:89] + node _T_4444 = add(_T_4443, _T_4438) @[lsu_bus_buffer.scala 533:142] + node _T_4445 = add(_T_4444, _T_4433) @[lsu_bus_buffer.scala 533:142] + node _T_4446 = add(_T_4445, _T_4428) @[lsu_bus_buffer.scala 533:142] + buf_numvld_wrcmd_any <= _T_4446 @[lsu_bus_buffer.scala 533:24] + node _T_4447 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4448 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4449 = and(_T_4447, _T_4448) @[lsu_bus_buffer.scala 534:73] + node _T_4450 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4451 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4452 = and(_T_4450, _T_4451) @[lsu_bus_buffer.scala 534:73] + node _T_4453 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4454 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4455 = and(_T_4453, _T_4454) @[lsu_bus_buffer.scala 534:73] + node _T_4456 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4457 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4458 = and(_T_4456, _T_4457) @[lsu_bus_buffer.scala 534:73] + node _T_4459 = add(_T_4458, _T_4455) @[lsu_bus_buffer.scala 534:126] + node _T_4460 = add(_T_4459, _T_4452) @[lsu_bus_buffer.scala 534:126] + node _T_4461 = add(_T_4460, _T_4449) @[lsu_bus_buffer.scala 534:126] + buf_numvld_cmd_any <= _T_4461 @[lsu_bus_buffer.scala 534:22] + node _T_4462 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4463 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4464 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4465 = and(_T_4463, _T_4464) @[lsu_bus_buffer.scala 535:100] + node _T_4466 = or(_T_4462, _T_4465) @[lsu_bus_buffer.scala 535:74] + node _T_4467 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4468 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4469 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4470 = and(_T_4468, _T_4469) @[lsu_bus_buffer.scala 535:100] + node _T_4471 = or(_T_4467, _T_4470) @[lsu_bus_buffer.scala 535:74] + node _T_4472 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4473 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4474 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4475 = and(_T_4473, _T_4474) @[lsu_bus_buffer.scala 535:100] + node _T_4476 = or(_T_4472, _T_4475) @[lsu_bus_buffer.scala 535:74] + node _T_4477 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4478 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4479 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4480 = and(_T_4478, _T_4479) @[lsu_bus_buffer.scala 535:100] + node _T_4481 = or(_T_4477, _T_4480) @[lsu_bus_buffer.scala 535:74] + node _T_4482 = add(_T_4481, _T_4476) @[lsu_bus_buffer.scala 535:154] + node _T_4483 = add(_T_4482, _T_4471) @[lsu_bus_buffer.scala 535:154] + node _T_4484 = add(_T_4483, _T_4466) @[lsu_bus_buffer.scala 535:154] + buf_numvld_pend_any <= _T_4484 @[lsu_bus_buffer.scala 535:23] + node _T_4485 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4486 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4487 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4488 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4489 = or(_T_4488, _T_4487) @[lsu_bus_buffer.scala 536:93] + node _T_4490 = or(_T_4489, _T_4486) @[lsu_bus_buffer.scala 536:93] + node _T_4491 = or(_T_4490, _T_4485) @[lsu_bus_buffer.scala 536:93] + any_done_wait_state <= _T_4491 @[lsu_bus_buffer.scala 536:23] + node _T_4492 = orr(buf_numvld_pend_any) @[lsu_bus_buffer.scala 537:53] + io.lsu_bus_buffer_pend_any <= _T_4492 @[lsu_bus_buffer.scala 537:30] + node _T_4493 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[lsu_bus_buffer.scala 538:52] + node _T_4494 = geq(buf_numvld_any, UInt<2>("h03")) @[lsu_bus_buffer.scala 538:92] + node _T_4495 = eq(buf_numvld_any, UInt<3>("h04")) @[lsu_bus_buffer.scala 538:121] + node _T_4496 = mux(_T_4493, _T_4494, _T_4495) @[lsu_bus_buffer.scala 538:36] + io.lsu_bus_buffer_full_any <= _T_4496 @[lsu_bus_buffer.scala 538:30] + node _T_4497 = orr(buf_state[0]) @[lsu_bus_buffer.scala 539:52] + node _T_4498 = orr(buf_state[1]) @[lsu_bus_buffer.scala 539:52] + node _T_4499 = orr(buf_state[2]) @[lsu_bus_buffer.scala 539:52] + node _T_4500 = orr(buf_state[3]) @[lsu_bus_buffer.scala 539:52] + node _T_4501 = or(_T_4497, _T_4498) @[lsu_bus_buffer.scala 539:65] + node _T_4502 = or(_T_4501, _T_4499) @[lsu_bus_buffer.scala 539:65] + node _T_4503 = or(_T_4502, _T_4500) @[lsu_bus_buffer.scala 539:65] + node _T_4504 = eq(_T_4503, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:34] + node _T_4505 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:72] + node _T_4506 = and(_T_4504, _T_4505) @[lsu_bus_buffer.scala 539:70] + node _T_4507 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:86] + node _T_4508 = and(_T_4506, _T_4507) @[lsu_bus_buffer.scala 539:84] + io.lsu_bus_buffer_empty_any <= _T_4508 @[lsu_bus_buffer.scala 539:31] + node _T_4509 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[lsu_bus_buffer.scala 541:64] + node _T_4510 = and(_T_4509, io.lsu_pkt_m.bits.load) @[lsu_bus_buffer.scala 541:85] + node _T_4511 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_bus_buffer.scala 541:112] + node _T_4512 = and(_T_4510, _T_4511) @[lsu_bus_buffer.scala 541:110] + node _T_4513 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 541:129] + node _T_4514 = and(_T_4512, _T_4513) @[lsu_bus_buffer.scala 541:127] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= _T_4514 @[lsu_bus_buffer.scala 541:45] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= WrPtr0_m @[lsu_bus_buffer.scala 542:43] + wire lsu_nonblock_load_valid_r : UInt<1> + lsu_nonblock_load_valid_r <= UInt<1>("h00") + node _T_4515 = eq(io.lsu_commit_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:74] + node _T_4516 = and(lsu_nonblock_load_valid_r, _T_4515) @[lsu_bus_buffer.scala 544:72] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= _T_4516 @[lsu_bus_buffer.scala 544:43] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 545:47] + node _T_4517 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4518 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 546:106] + node _T_4519 = eq(_T_4518, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4520 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4521 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 546:106] + node _T_4522 = eq(_T_4521, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4523 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4524 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 546:106] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4526 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4527 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 546:106] + node _T_4528 = eq(_T_4527, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4529 = mux(_T_4517, _T_4519, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4530 = mux(_T_4520, _T_4522, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4531 = mux(_T_4523, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4532 = mux(_T_4526, _T_4528, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4533 = or(_T_4529, _T_4530) @[Mux.scala 27:72] + node _T_4534 = or(_T_4533, _T_4531) @[Mux.scala 27:72] + node _T_4535 = or(_T_4534, _T_4532) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_load_data_ready <= _T_4535 @[Mux.scala 27:72] + node _T_4536 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4537 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 547:117] + node _T_4538 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 547:133] + node _T_4539 = eq(_T_4538, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4540 = and(_T_4537, _T_4539) @[lsu_bus_buffer.scala 547:121] + node _T_4541 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4542 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 547:117] + node _T_4543 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 547:133] + node _T_4544 = eq(_T_4543, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4545 = and(_T_4542, _T_4544) @[lsu_bus_buffer.scala 547:121] + node _T_4546 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4547 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 547:117] + node _T_4548 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 547:133] + node _T_4549 = eq(_T_4548, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4550 = and(_T_4547, _T_4549) @[lsu_bus_buffer.scala 547:121] + node _T_4551 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4552 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 547:117] + node _T_4553 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 547:133] + node _T_4554 = eq(_T_4553, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4555 = and(_T_4552, _T_4554) @[lsu_bus_buffer.scala 547:121] + node _T_4556 = mux(_T_4536, _T_4540, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4557 = mux(_T_4541, _T_4545, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4558 = mux(_T_4546, _T_4550, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4559 = mux(_T_4551, _T_4555, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4560 = or(_T_4556, _T_4557) @[Mux.scala 27:72] + node _T_4561 = or(_T_4560, _T_4558) @[Mux.scala 27:72] + node _T_4562 = or(_T_4561, _T_4559) @[Mux.scala 27:72] + wire _T_4563 : UInt<1> @[Mux.scala 27:72] + _T_4563 <= _T_4562 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_error <= _T_4563 @[lsu_bus_buffer.scala 547:48] + node _T_4564 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4565 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 548:114] + node _T_4566 = eq(_T_4565, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4567 = and(_T_4564, _T_4566) @[lsu_bus_buffer.scala 548:102] + node _T_4568 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4569 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4570 = or(_T_4568, _T_4569) @[lsu_bus_buffer.scala 548:134] + node _T_4571 = and(_T_4567, _T_4570) @[lsu_bus_buffer.scala 548:118] + node _T_4572 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4573 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 548:114] + node _T_4574 = eq(_T_4573, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4575 = and(_T_4572, _T_4574) @[lsu_bus_buffer.scala 548:102] + node _T_4576 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4577 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4578 = or(_T_4576, _T_4577) @[lsu_bus_buffer.scala 548:134] + node _T_4579 = and(_T_4575, _T_4578) @[lsu_bus_buffer.scala 548:118] + node _T_4580 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4581 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 548:114] + node _T_4582 = eq(_T_4581, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4583 = and(_T_4580, _T_4582) @[lsu_bus_buffer.scala 548:102] + node _T_4584 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4585 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4586 = or(_T_4584, _T_4585) @[lsu_bus_buffer.scala 548:134] + node _T_4587 = and(_T_4583, _T_4586) @[lsu_bus_buffer.scala 548:118] + node _T_4588 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4589 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 548:114] + node _T_4590 = eq(_T_4589, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4591 = and(_T_4588, _T_4590) @[lsu_bus_buffer.scala 548:102] + node _T_4592 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4593 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4594 = or(_T_4592, _T_4593) @[lsu_bus_buffer.scala 548:134] + node _T_4595 = and(_T_4591, _T_4594) @[lsu_bus_buffer.scala 548:118] + node _T_4596 = mux(_T_4571, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4597 = mux(_T_4579, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4598 = mux(_T_4587, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4599 = mux(_T_4595, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4600 = or(_T_4596, _T_4597) @[Mux.scala 27:72] + node _T_4601 = or(_T_4600, _T_4598) @[Mux.scala 27:72] + node _T_4602 = or(_T_4601, _T_4599) @[Mux.scala 27:72] + wire _T_4603 : UInt<2> @[Mux.scala 27:72] + _T_4603 <= _T_4602 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= _T_4603 @[lsu_bus_buffer.scala 548:45] + node _T_4604 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4605 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 549:101] + node _T_4606 = eq(_T_4605, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4607 = and(_T_4604, _T_4606) @[lsu_bus_buffer.scala 549:89] + node _T_4608 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4609 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4610 = or(_T_4608, _T_4609) @[lsu_bus_buffer.scala 549:121] + node _T_4611 = and(_T_4607, _T_4610) @[lsu_bus_buffer.scala 549:105] + node _T_4612 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4613 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 549:101] + node _T_4614 = eq(_T_4613, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4615 = and(_T_4612, _T_4614) @[lsu_bus_buffer.scala 549:89] + node _T_4616 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4617 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4618 = or(_T_4616, _T_4617) @[lsu_bus_buffer.scala 549:121] + node _T_4619 = and(_T_4615, _T_4618) @[lsu_bus_buffer.scala 549:105] + node _T_4620 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4621 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 549:101] + node _T_4622 = eq(_T_4621, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4623 = and(_T_4620, _T_4622) @[lsu_bus_buffer.scala 549:89] + node _T_4624 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4625 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4626 = or(_T_4624, _T_4625) @[lsu_bus_buffer.scala 549:121] + node _T_4627 = and(_T_4623, _T_4626) @[lsu_bus_buffer.scala 549:105] + node _T_4628 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4629 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 549:101] + node _T_4630 = eq(_T_4629, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4631 = and(_T_4628, _T_4630) @[lsu_bus_buffer.scala 549:89] + node _T_4632 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4633 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4634 = or(_T_4632, _T_4633) @[lsu_bus_buffer.scala 549:121] + node _T_4635 = and(_T_4631, _T_4634) @[lsu_bus_buffer.scala 549:105] + node _T_4636 = mux(_T_4611, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4637 = mux(_T_4619, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4638 = mux(_T_4627, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4639 = mux(_T_4635, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4640 = or(_T_4636, _T_4637) @[Mux.scala 27:72] + node _T_4641 = or(_T_4640, _T_4638) @[Mux.scala 27:72] + node _T_4642 = or(_T_4641, _T_4639) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_lo <= _T_4642 @[Mux.scala 27:72] + node _T_4643 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4644 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 550:101] + node _T_4645 = eq(_T_4644, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4646 = and(_T_4643, _T_4645) @[lsu_bus_buffer.scala 550:89] + node _T_4647 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 550:120] + node _T_4648 = and(_T_4646, _T_4647) @[lsu_bus_buffer.scala 550:105] + node _T_4649 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4650 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 550:101] + node _T_4651 = eq(_T_4650, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4652 = and(_T_4649, _T_4651) @[lsu_bus_buffer.scala 550:89] + node _T_4653 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 550:120] + node _T_4654 = and(_T_4652, _T_4653) @[lsu_bus_buffer.scala 550:105] + node _T_4655 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4656 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 550:101] + node _T_4657 = eq(_T_4656, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4658 = and(_T_4655, _T_4657) @[lsu_bus_buffer.scala 550:89] + node _T_4659 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 550:120] + node _T_4660 = and(_T_4658, _T_4659) @[lsu_bus_buffer.scala 550:105] + node _T_4661 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4662 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 550:101] + node _T_4663 = eq(_T_4662, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4664 = and(_T_4661, _T_4663) @[lsu_bus_buffer.scala 550:89] + node _T_4665 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 550:120] + node _T_4666 = and(_T_4664, _T_4665) @[lsu_bus_buffer.scala 550:105] + node _T_4667 = mux(_T_4648, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4668 = mux(_T_4654, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4669 = mux(_T_4660, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4670 = mux(_T_4666, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4671 = or(_T_4667, _T_4668) @[Mux.scala 27:72] + node _T_4672 = or(_T_4671, _T_4669) @[Mux.scala 27:72] + node _T_4673 = or(_T_4672, _T_4670) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_hi <= _T_4673 @[Mux.scala 27:72] + node _T_4674 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_4675 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_4676 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_4677 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_4678 = mux(_T_4674, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4679 = mux(_T_4675, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4680 = mux(_T_4676, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4681 = mux(_T_4677, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4682 = or(_T_4678, _T_4679) @[Mux.scala 27:72] + node _T_4683 = or(_T_4682, _T_4680) @[Mux.scala 27:72] + node _T_4684 = or(_T_4683, _T_4681) @[Mux.scala 27:72] + wire _T_4685 : UInt<32> @[Mux.scala 27:72] + _T_4685 <= _T_4684 @[Mux.scala 27:72] + node lsu_nonblock_addr_offset = bits(_T_4685, 1, 0) @[lsu_bus_buffer.scala 551:96] + node _T_4686 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_4687 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_4688 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_4689 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_4690 = mux(_T_4686, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4691 = mux(_T_4687, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4692 = mux(_T_4688, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4693 = mux(_T_4689, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4694 = or(_T_4690, _T_4691) @[Mux.scala 27:72] + node _T_4695 = or(_T_4694, _T_4692) @[Mux.scala 27:72] + node _T_4696 = or(_T_4695, _T_4693) @[Mux.scala 27:72] + wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] + lsu_nonblock_sz <= _T_4696 @[Mux.scala 27:72] + node _T_4697 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_4698 = bits(buf_unsign, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_4699 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_4700 = bits(buf_unsign, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_4701 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_4702 = bits(buf_unsign, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4703 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4704 = bits(buf_unsign, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4705 = mux(_T_4697, _T_4698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4706 = mux(_T_4699, _T_4700, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4707 = mux(_T_4701, _T_4702, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4708 = mux(_T_4703, _T_4704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4709 = or(_T_4705, _T_4706) @[Mux.scala 27:72] + node _T_4710 = or(_T_4709, _T_4707) @[Mux.scala 27:72] + node _T_4711 = or(_T_4710, _T_4708) @[Mux.scala 27:72] + wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_unsign <= _T_4711 @[Mux.scala 27:72] + node _T_4712 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] + node _T_4713 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[lsu_bus_buffer.scala 555:121] + node lsu_nonblock_data_unalgn = dshr(_T_4712, _T_4713) @[lsu_bus_buffer.scala 555:92] + node _T_4714 = eq(io.dctl_busbuff.lsu_nonblock_load_data_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 557:82] + node _T_4715 = and(lsu_nonblock_load_data_ready, _T_4714) @[lsu_bus_buffer.scala 557:80] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= _T_4715 @[lsu_bus_buffer.scala 557:48] + node _T_4716 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 558:81] + node _T_4717 = and(lsu_nonblock_unsign, _T_4716) @[lsu_bus_buffer.scala 558:63] + node _T_4718 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 558:131] + node _T_4719 = cat(UInt<24>("h00"), _T_4718) @[Cat.scala 29:58] + node _T_4720 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 559:45] + node _T_4721 = and(lsu_nonblock_unsign, _T_4720) @[lsu_bus_buffer.scala 559:26] + node _T_4722 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 559:95] + node _T_4723 = cat(UInt<16>("h00"), _T_4722) @[Cat.scala 29:58] + node _T_4724 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 560:6] + node _T_4725 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 560:45] + node _T_4726 = and(_T_4724, _T_4725) @[lsu_bus_buffer.scala 560:27] + node _T_4727 = bits(lsu_nonblock_data_unalgn, 7, 7) @[lsu_bus_buffer.scala 560:93] + node _T_4728 = bits(_T_4727, 0, 0) @[Bitwise.scala 72:15] + node _T_4729 = mux(_T_4728, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_4730 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 560:123] + node _T_4731 = cat(_T_4729, _T_4730) @[Cat.scala 29:58] + node _T_4732 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 561:6] + node _T_4733 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 561:45] + node _T_4734 = and(_T_4732, _T_4733) @[lsu_bus_buffer.scala 561:27] + node _T_4735 = bits(lsu_nonblock_data_unalgn, 15, 15) @[lsu_bus_buffer.scala 561:93] + node _T_4736 = bits(_T_4735, 0, 0) @[Bitwise.scala 72:15] + node _T_4737 = mux(_T_4736, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_4738 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 561:124] + node _T_4739 = cat(_T_4737, _T_4738) @[Cat.scala 29:58] + node _T_4740 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[lsu_bus_buffer.scala 562:21] + node _T_4741 = mux(_T_4717, _T_4719, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4742 = mux(_T_4721, _T_4723, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4743 = mux(_T_4726, _T_4731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4744 = mux(_T_4734, _T_4739, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4745 = mux(_T_4740, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4746 = or(_T_4741, _T_4742) @[Mux.scala 27:72] + node _T_4747 = or(_T_4746, _T_4743) @[Mux.scala 27:72] + node _T_4748 = or(_T_4747, _T_4744) @[Mux.scala 27:72] + node _T_4749 = or(_T_4748, _T_4745) @[Mux.scala 27:72] + wire _T_4750 : UInt<64> @[Mux.scala 27:72] + _T_4750 <= _T_4749 @[Mux.scala 27:72] + io.lsu_nonblock_load_data <= _T_4750 @[lsu_bus_buffer.scala 558:29] + node _T_4751 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4752 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 563:89] + node _T_4753 = and(_T_4751, _T_4752) @[lsu_bus_buffer.scala 563:73] + node _T_4754 = and(_T_4753, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4755 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4756 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 563:89] + node _T_4757 = and(_T_4755, _T_4756) @[lsu_bus_buffer.scala 563:73] + node _T_4758 = and(_T_4757, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4759 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4760 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 563:89] + node _T_4761 = and(_T_4759, _T_4760) @[lsu_bus_buffer.scala 563:73] + node _T_4762 = and(_T_4761, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4763 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4764 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 563:89] + node _T_4765 = and(_T_4763, _T_4764) @[lsu_bus_buffer.scala 563:73] + node _T_4766 = and(_T_4765, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4767 = or(_T_4754, _T_4758) @[lsu_bus_buffer.scala 563:153] + node _T_4768 = or(_T_4767, _T_4762) @[lsu_bus_buffer.scala 563:153] + node _T_4769 = or(_T_4768, _T_4766) @[lsu_bus_buffer.scala 563:153] + node _T_4770 = and(obuf_valid, obuf_sideeffect) @[lsu_bus_buffer.scala 563:171] + node _T_4771 = and(_T_4770, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:189] + node _T_4772 = or(_T_4769, _T_4771) @[lsu_bus_buffer.scala 563:157] + bus_sideeffect_pend <= _T_4772 @[lsu_bus_buffer.scala 563:23] + node _T_4773 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4774 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4775 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4776 = eq(_T_4774, _T_4775) @[lsu_bus_buffer.scala 565:37] + node _T_4777 = and(obuf_valid, _T_4776) @[lsu_bus_buffer.scala 565:19] + node _T_4778 = eq(obuf_tag0, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:73] + node _T_4779 = eq(obuf_tag1, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:107] + node _T_4780 = and(obuf_merge, _T_4779) @[lsu_bus_buffer.scala 565:95] + node _T_4781 = or(_T_4778, _T_4780) @[lsu_bus_buffer.scala 565:81] + node _T_4782 = eq(_T_4781, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4783 = and(_T_4777, _T_4782) @[lsu_bus_buffer.scala 565:59] + node _T_4784 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4785 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4786 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4787 = eq(_T_4785, _T_4786) @[lsu_bus_buffer.scala 565:37] + node _T_4788 = and(obuf_valid, _T_4787) @[lsu_bus_buffer.scala 565:19] + node _T_4789 = eq(obuf_tag0, UInt<1>("h01")) @[lsu_bus_buffer.scala 565:73] + node _T_4790 = eq(obuf_tag1, UInt<1>("h01")) @[lsu_bus_buffer.scala 565:107] + node _T_4791 = and(obuf_merge, _T_4790) @[lsu_bus_buffer.scala 565:95] + node _T_4792 = or(_T_4789, _T_4791) @[lsu_bus_buffer.scala 565:81] + node _T_4793 = eq(_T_4792, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4794 = and(_T_4788, _T_4793) @[lsu_bus_buffer.scala 565:59] + node _T_4795 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4796 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4797 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4798 = eq(_T_4796, _T_4797) @[lsu_bus_buffer.scala 565:37] + node _T_4799 = and(obuf_valid, _T_4798) @[lsu_bus_buffer.scala 565:19] + node _T_4800 = eq(obuf_tag0, UInt<2>("h02")) @[lsu_bus_buffer.scala 565:73] + node _T_4801 = eq(obuf_tag1, UInt<2>("h02")) @[lsu_bus_buffer.scala 565:107] + node _T_4802 = and(obuf_merge, _T_4801) @[lsu_bus_buffer.scala 565:95] + node _T_4803 = or(_T_4800, _T_4802) @[lsu_bus_buffer.scala 565:81] + node _T_4804 = eq(_T_4803, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4805 = and(_T_4799, _T_4804) @[lsu_bus_buffer.scala 565:59] + node _T_4806 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4807 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4808 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4809 = eq(_T_4807, _T_4808) @[lsu_bus_buffer.scala 565:37] + node _T_4810 = and(obuf_valid, _T_4809) @[lsu_bus_buffer.scala 565:19] + node _T_4811 = eq(obuf_tag0, UInt<2>("h03")) @[lsu_bus_buffer.scala 565:73] + node _T_4812 = eq(obuf_tag1, UInt<2>("h03")) @[lsu_bus_buffer.scala 565:107] + node _T_4813 = and(obuf_merge, _T_4812) @[lsu_bus_buffer.scala 565:95] + node _T_4814 = or(_T_4811, _T_4813) @[lsu_bus_buffer.scala 565:81] + node _T_4815 = eq(_T_4814, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4816 = and(_T_4810, _T_4815) @[lsu_bus_buffer.scala 565:59] + node _T_4817 = mux(_T_4773, _T_4783, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4818 = mux(_T_4784, _T_4794, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4819 = mux(_T_4795, _T_4805, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4820 = mux(_T_4806, _T_4816, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4821 = or(_T_4817, _T_4818) @[Mux.scala 27:72] + node _T_4822 = or(_T_4821, _T_4819) @[Mux.scala 27:72] + node _T_4823 = or(_T_4822, _T_4820) @[Mux.scala 27:72] + wire _T_4824 : UInt<1> @[Mux.scala 27:72] + _T_4824 <= _T_4823 @[Mux.scala 27:72] + bus_addr_match_pending <= _T_4824 @[lsu_bus_buffer.scala 564:26] + node _T_4825 = or(obuf_cmd_done, obuf_data_done) @[lsu_bus_buffer.scala 567:54] + node _T_4826 = mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 567:75] + node _T_4827 = and(io.lsu_axi.aw.ready, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 567:153] + node _T_4828 = mux(_T_4825, _T_4826, _T_4827) @[lsu_bus_buffer.scala 567:39] + node _T_4829 = mux(obuf_write, _T_4828, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 567:23] + bus_cmd_ready <= _T_4829 @[lsu_bus_buffer.scala 567:17] + node _T_4830 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 568:40] + bus_wcmd_sent <= _T_4830 @[lsu_bus_buffer.scala 568:17] + node _T_4831 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 569:40] + bus_wdata_sent <= _T_4831 @[lsu_bus_buffer.scala 569:18] + node _T_4832 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 570:35] + node _T_4833 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 570:70] + node _T_4834 = and(_T_4832, _T_4833) @[lsu_bus_buffer.scala 570:52] + node _T_4835 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 570:112] + node _T_4836 = or(_T_4834, _T_4835) @[lsu_bus_buffer.scala 570:89] + bus_cmd_sent <= _T_4836 @[lsu_bus_buffer.scala 570:16] + node _T_4837 = and(io.lsu_axi.r.valid, io.lsu_axi.r.ready) @[lsu_bus_buffer.scala 571:38] + bus_rsp_read <= _T_4837 @[lsu_bus_buffer.scala 571:16] + node _T_4838 = and(io.lsu_axi.b.valid, io.lsu_axi.b.ready) @[lsu_bus_buffer.scala 572:39] + bus_rsp_write <= _T_4838 @[lsu_bus_buffer.scala 572:17] + bus_rsp_read_tag <= io.lsu_axi.r.bits.id @[lsu_bus_buffer.scala 573:20] + bus_rsp_write_tag <= io.lsu_axi.b.bits.id @[lsu_bus_buffer.scala 574:21] + node _T_4839 = neq(io.lsu_axi.b.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 575:66] + node _T_4840 = and(bus_rsp_write, _T_4839) @[lsu_bus_buffer.scala 575:40] + bus_rsp_write_error <= _T_4840 @[lsu_bus_buffer.scala 575:23] + node _T_4841 = neq(io.lsu_axi.r.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 576:64] + node _T_4842 = and(bus_rsp_read, _T_4841) @[lsu_bus_buffer.scala 576:38] + bus_rsp_read_error <= _T_4842 @[lsu_bus_buffer.scala 576:22] + bus_rsp_rdata <= io.lsu_axi.r.bits.data @[lsu_bus_buffer.scala 577:17] + node _T_4843 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 580:37] + node _T_4844 = eq(obuf_cmd_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:52] + node _T_4845 = and(_T_4843, _T_4844) @[lsu_bus_buffer.scala 580:50] + node _T_4846 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:69] + node _T_4847 = and(_T_4845, _T_4846) @[lsu_bus_buffer.scala 580:67] + io.lsu_axi.aw.valid <= _T_4847 @[lsu_bus_buffer.scala 580:23] + io.lsu_axi.aw.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 581:25] + node _T_4848 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 582:75] + node _T_4849 = cat(_T_4848, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4850 = mux(obuf_sideeffect, obuf_addr, _T_4849) @[lsu_bus_buffer.scala 582:33] + io.lsu_axi.aw.bits.addr <= _T_4850 @[lsu_bus_buffer.scala 582:27] + node _T_4851 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4852 = mux(obuf_sideeffect, _T_4851, UInt<3>("h03")) @[lsu_bus_buffer.scala 583:33] + io.lsu_axi.aw.bits.size <= _T_4852 @[lsu_bus_buffer.scala 583:27] + io.lsu_axi.aw.bits.prot <= UInt<3>("h01") @[lsu_bus_buffer.scala 584:27] + node _T_4853 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 585:34] + io.lsu_axi.aw.bits.cache <= _T_4853 @[lsu_bus_buffer.scala 585:28] + node _T_4854 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 586:41] + io.lsu_axi.aw.bits.region <= _T_4854 @[lsu_bus_buffer.scala 586:29] + io.lsu_axi.aw.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 587:26] + io.lsu_axi.aw.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 588:28] + io.lsu_axi.aw.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 589:26] + io.lsu_axi.aw.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 590:27] + node _T_4855 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 592:36] + node _T_4856 = eq(obuf_data_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 592:51] + node _T_4857 = and(_T_4855, _T_4856) @[lsu_bus_buffer.scala 592:49] + node _T_4858 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 592:69] + node _T_4859 = and(_T_4857, _T_4858) @[lsu_bus_buffer.scala 592:67] + io.lsu_axi.w.valid <= _T_4859 @[lsu_bus_buffer.scala 592:22] + node _T_4860 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] + node _T_4861 = mux(_T_4860, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_4862 = and(obuf_byteen, _T_4861) @[lsu_bus_buffer.scala 593:41] + io.lsu_axi.w.bits.strb <= _T_4862 @[lsu_bus_buffer.scala 593:26] + io.lsu_axi.w.bits.data <= obuf_data @[lsu_bus_buffer.scala 594:26] + io.lsu_axi.w.bits.last <= UInt<1>("h01") @[lsu_bus_buffer.scala 595:26] + node _T_4863 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:39] + node _T_4864 = and(obuf_valid, _T_4863) @[lsu_bus_buffer.scala 597:37] + node _T_4865 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:53] + node _T_4866 = and(_T_4864, _T_4865) @[lsu_bus_buffer.scala 597:51] + node _T_4867 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:68] + node _T_4868 = and(_T_4866, _T_4867) @[lsu_bus_buffer.scala 597:66] + io.lsu_axi.ar.valid <= _T_4868 @[lsu_bus_buffer.scala 597:23] + io.lsu_axi.ar.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 598:25] + node _T_4869 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 599:75] + node _T_4870 = cat(_T_4869, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4871 = mux(obuf_sideeffect, obuf_addr, _T_4870) @[lsu_bus_buffer.scala 599:33] + io.lsu_axi.ar.bits.addr <= _T_4871 @[lsu_bus_buffer.scala 599:27] + node _T_4872 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4873 = mux(obuf_sideeffect, _T_4872, UInt<3>("h03")) @[lsu_bus_buffer.scala 600:33] + io.lsu_axi.ar.bits.size <= _T_4873 @[lsu_bus_buffer.scala 600:27] + io.lsu_axi.ar.bits.prot <= UInt<3>("h01") @[lsu_bus_buffer.scala 601:27] + node _T_4874 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 602:34] + io.lsu_axi.ar.bits.cache <= _T_4874 @[lsu_bus_buffer.scala 602:28] + node _T_4875 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 603:41] + io.lsu_axi.ar.bits.region <= _T_4875 @[lsu_bus_buffer.scala 603:29] + io.lsu_axi.ar.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 604:26] + io.lsu_axi.ar.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 605:28] + io.lsu_axi.ar.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 606:26] + io.lsu_axi.ar.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 607:27] + io.lsu_axi.b.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 608:22] + io.lsu_axi.r.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 609:22] + node _T_4876 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4877 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 610:137] + node _T_4878 = and(io.lsu_bus_clk_en_q, _T_4877) @[lsu_bus_buffer.scala 610:126] + node _T_4879 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 610:152] + node _T_4880 = and(_T_4878, _T_4879) @[lsu_bus_buffer.scala 610:141] + node _T_4881 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4882 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 610:137] + node _T_4883 = and(io.lsu_bus_clk_en_q, _T_4882) @[lsu_bus_buffer.scala 610:126] + node _T_4884 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 610:152] + node _T_4885 = and(_T_4883, _T_4884) @[lsu_bus_buffer.scala 610:141] + node _T_4886 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4887 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 610:137] + node _T_4888 = and(io.lsu_bus_clk_en_q, _T_4887) @[lsu_bus_buffer.scala 610:126] + node _T_4889 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 610:152] + node _T_4890 = and(_T_4888, _T_4889) @[lsu_bus_buffer.scala 610:141] + node _T_4891 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4892 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 610:137] + node _T_4893 = and(io.lsu_bus_clk_en_q, _T_4892) @[lsu_bus_buffer.scala 610:126] + node _T_4894 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 610:152] + node _T_4895 = and(_T_4893, _T_4894) @[lsu_bus_buffer.scala 610:141] + node _T_4896 = mux(_T_4876, _T_4880, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4897 = mux(_T_4881, _T_4885, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4898 = mux(_T_4886, _T_4890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4899 = mux(_T_4891, _T_4895, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4900 = or(_T_4896, _T_4897) @[Mux.scala 27:72] + node _T_4901 = or(_T_4900, _T_4898) @[Mux.scala 27:72] + node _T_4902 = or(_T_4901, _T_4899) @[Mux.scala 27:72] + wire _T_4903 : UInt<1> @[Mux.scala 27:72] + _T_4903 <= _T_4902 @[Mux.scala 27:72] + io.tlu_busbuff.lsu_imprecise_error_store_any <= _T_4903 @[lsu_bus_buffer.scala 610:48] + node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4905 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 611:104] + node _T_4906 = and(_T_4904, _T_4905) @[lsu_bus_buffer.scala 611:93] + node _T_4907 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 611:119] + node _T_4908 = and(_T_4906, _T_4907) @[lsu_bus_buffer.scala 611:108] + node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4910 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 611:104] + node _T_4911 = and(_T_4909, _T_4910) @[lsu_bus_buffer.scala 611:93] + node _T_4912 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 611:119] + node _T_4913 = and(_T_4911, _T_4912) @[lsu_bus_buffer.scala 611:108] + node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4915 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 611:104] + node _T_4916 = and(_T_4914, _T_4915) @[lsu_bus_buffer.scala 611:93] + node _T_4917 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 611:119] + node _T_4918 = and(_T_4916, _T_4917) @[lsu_bus_buffer.scala 611:108] + node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4920 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 611:104] + node _T_4921 = and(_T_4919, _T_4920) @[lsu_bus_buffer.scala 611:93] + node _T_4922 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 611:119] + node _T_4923 = and(_T_4921, _T_4922) @[lsu_bus_buffer.scala 611:108] + node _T_4924 = mux(_T_4908, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4925 = mux(_T_4913, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4926 = mux(_T_4918, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4927 = mux(_T_4923, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4928 = or(_T_4924, _T_4925) @[Mux.scala 27:72] + node _T_4929 = or(_T_4928, _T_4926) @[Mux.scala 27:72] + node _T_4930 = or(_T_4929, _T_4927) @[Mux.scala 27:72] + wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72] + lsu_imprecise_error_store_tag <= _T_4930 @[Mux.scala 27:72] + node _T_4931 = eq(io.tlu_busbuff.lsu_imprecise_error_store_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 613:97] + node _T_4932 = and(io.dctl_busbuff.lsu_nonblock_load_data_error, _T_4931) @[lsu_bus_buffer.scala 613:95] + io.tlu_busbuff.lsu_imprecise_error_load_any <= _T_4932 @[lsu_bus_buffer.scala 613:47] + node _T_4933 = mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.dctl_busbuff.lsu_nonblock_load_data_tag]) @[lsu_bus_buffer.scala 614:53] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= _T_4933 @[lsu_bus_buffer.scala 614:47] + node _T_4934 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 620:59] + node _T_4935 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 620:104] + node _T_4936 = or(_T_4934, _T_4935) @[lsu_bus_buffer.scala 620:82] + node _T_4937 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 620:149] + node _T_4938 = or(_T_4936, _T_4937) @[lsu_bus_buffer.scala 620:126] + io.tlu_busbuff.lsu_pmu_bus_trxn <= _T_4938 @[lsu_bus_buffer.scala 620:35] + node _T_4939 = and(io.lsu_busreq_r, io.ldst_dual_r) @[lsu_bus_buffer.scala 621:60] + node _T_4940 = and(_T_4939, io.lsu_commit_r) @[lsu_bus_buffer.scala 621:77] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= _T_4940 @[lsu_bus_buffer.scala 621:41] + node _T_4941 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[lsu_bus_buffer.scala 622:83] + io.tlu_busbuff.lsu_pmu_bus_error <= _T_4941 @[lsu_bus_buffer.scala 622:36] + node _T_4942 = eq(io.lsu_axi.aw.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:61] + node _T_4943 = and(io.lsu_axi.aw.valid, _T_4942) @[lsu_bus_buffer.scala 624:59] + node _T_4944 = eq(io.lsu_axi.w.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:107] + node _T_4945 = and(io.lsu_axi.w.valid, _T_4944) @[lsu_bus_buffer.scala 624:105] + node _T_4946 = or(_T_4943, _T_4945) @[lsu_bus_buffer.scala 624:83] + node _T_4947 = eq(io.lsu_axi.ar.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:153] + node _T_4948 = and(io.lsu_axi.ar.valid, _T_4947) @[lsu_bus_buffer.scala 624:151] + node _T_4949 = or(_T_4946, _T_4948) @[lsu_bus_buffer.scala 624:128] + io.tlu_busbuff.lsu_pmu_bus_busy <= _T_4949 @[lsu_bus_buffer.scala 624:35] + reg _T_4950 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 626:49] + _T_4950 <= WrPtr0_m @[lsu_bus_buffer.scala 626:49] + WrPtr0_r <= _T_4950 @[lsu_bus_buffer.scala 626:12] + reg _T_4951 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 627:49] + _T_4951 <= WrPtr1_m @[lsu_bus_buffer.scala 627:49] + WrPtr1_r <= _T_4951 @[lsu_bus_buffer.scala 627:12] + node _T_4952 = eq(io.flush_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 628:75] + node _T_4953 = and(io.lsu_busreq_m, _T_4952) @[lsu_bus_buffer.scala 628:73] + node _T_4954 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 628:89] + node _T_4955 = and(_T_4953, _T_4954) @[lsu_bus_buffer.scala 628:87] + reg _T_4956 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 628:56] + _T_4956 <= _T_4955 @[lsu_bus_buffer.scala 628:56] + io.lsu_busreq_r <= _T_4956 @[lsu_bus_buffer.scala 628:19] + reg _T_4957 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 629:66] + _T_4957 <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_buffer.scala 629:66] + lsu_nonblock_load_valid_r <= _T_4957 @[lsu_bus_buffer.scala 629:29] + + module lsu_bus_intf : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip clk_override : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip active_clk : Clock, flip lsu_busm_clk : Clock, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, bus_read_data_m : UInt<32>, lsu_nonblock_load_data : UInt<32>, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, flip lsu_bus_clk_en : UInt<1>} + + wire lsu_bus_clk_en_q : UInt<1> + lsu_bus_clk_en_q <= UInt<1>("h00") + wire ldst_byteen_m : UInt<4> + ldst_byteen_m <= UInt<1>("h00") + wire ldst_byteen_r : UInt<4> + ldst_byteen_r <= UInt<1>("h00") + wire ldst_byteen_ext_m : UInt<8> + ldst_byteen_ext_m <= UInt<1>("h00") + wire ldst_byteen_ext_r : UInt<8> + ldst_byteen_ext_r <= UInt<1>("h00") + wire ldst_byteen_hi_m : UInt<4> + ldst_byteen_hi_m <= UInt<1>("h00") + wire ldst_byteen_hi_r : UInt<4> + ldst_byteen_hi_r <= UInt<1>("h00") + wire ldst_byteen_lo_m : UInt<4> + ldst_byteen_lo_m <= UInt<1>("h00") + wire ldst_byteen_lo_r : UInt<4> + ldst_byteen_lo_r <= UInt<1>("h00") + wire is_sideeffects_r : UInt<1> + is_sideeffects_r <= UInt<1>("h00") + wire store_data_ext_r : UInt<64> + store_data_ext_r <= UInt<1>("h00") + wire store_data_hi_r : UInt<32> + store_data_hi_r <= UInt<1>("h00") + wire store_data_lo_r : UInt<32> + store_data_lo_r <= UInt<1>("h00") + wire addr_match_dw_lo_r_m : UInt<1> + addr_match_dw_lo_r_m <= UInt<1>("h00") + wire addr_match_word_lo_r_m : UInt<1> + addr_match_word_lo_r_m <= UInt<1>("h00") + wire no_word_merge_r : UInt<1> + no_word_merge_r <= UInt<1>("h00") + wire no_dword_merge_r : UInt<1> + no_dword_merge_r <= UInt<1>("h00") + wire ld_addr_rhit_lo_lo : UInt<1> + ld_addr_rhit_lo_lo <= UInt<1>("h00") + wire ld_addr_rhit_hi_lo : UInt<1> + ld_addr_rhit_hi_lo <= UInt<1>("h00") + wire ld_addr_rhit_lo_hi : UInt<1> + ld_addr_rhit_lo_hi <= UInt<1>("h00") + wire ld_addr_rhit_hi_hi : UInt<1> + ld_addr_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_rhit_lo_lo : UInt<4> + ld_byte_rhit_lo_lo <= UInt<1>("h00") + wire ld_byte_rhit_hi_lo : UInt<4> + ld_byte_rhit_hi_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo_hi : UInt<4> + ld_byte_rhit_lo_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi_hi : UInt<4> + ld_byte_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_hit_lo : UInt<4> + ld_byte_hit_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo : UInt<4> + ld_byte_rhit_lo <= UInt<1>("h00") + wire ld_byte_hit_hi : UInt<4> + ld_byte_hit_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi : UInt<4> + ld_byte_rhit_hi <= UInt<1>("h00") + wire ld_fwddata_rpipe_lo : UInt<32> + ld_fwddata_rpipe_lo <= UInt<1>("h00") + wire ld_fwddata_rpipe_hi : UInt<32> + ld_fwddata_rpipe_hi <= UInt<1>("h00") + wire ld_byte_hit_buf_lo : UInt<4> + ld_byte_hit_buf_lo <= UInt<1>("h00") + wire ld_byte_hit_buf_hi : UInt<4> + ld_byte_hit_buf_hi <= UInt<1>("h00") + wire ld_fwddata_buf_lo : UInt<32> + ld_fwddata_buf_lo <= UInt<1>("h00") + wire ld_fwddata_buf_hi : UInt<32> + ld_fwddata_buf_hi <= UInt<1>("h00") + wire ld_fwddata_lo : UInt<64> + ld_fwddata_lo <= UInt<1>("h00") + wire ld_fwddata_hi : UInt<64> + ld_fwddata_hi <= UInt<1>("h00") + wire ld_fwddata_m : UInt<64> + ld_fwddata_m <= UInt<1>("h00") + wire ld_full_hit_hi_m : UInt<1> + ld_full_hit_hi_m <= UInt<1>("h01") + wire ld_full_hit_lo_m : UInt<1> + ld_full_hit_lo_m <= UInt<1>("h01") + wire ld_full_hit_m : UInt<1> + ld_full_hit_m <= UInt<1>("h00") + inst bus_buffer of lsu_bus_buffer @[lsu_bus_intf.scala 100:39] + bus_buffer.clock <= clock + bus_buffer.reset <= reset + bus_buffer.io.scan_mode <= io.scan_mode @[lsu_bus_intf.scala 102:29] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_store_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_load_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_busy <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_error <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_error @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_trxn <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu_bus_intf.scala 103:18] + bus_buffer.io.clk_override <= io.clk_override @[lsu_bus_intf.scala 104:51] + bus_buffer.io.lsu_bus_obuf_c1_clken <= io.lsu_bus_obuf_c1_clken @[lsu_bus_intf.scala 105:51] + bus_buffer.io.lsu_busm_clken <= io.lsu_busm_clken @[lsu_bus_intf.scala 106:51] + bus_buffer.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu_bus_intf.scala 107:51] + bus_buffer.io.lsu_c2_r_clk <= io.lsu_c2_r_clk @[lsu_bus_intf.scala 108:51] + bus_buffer.io.lsu_bus_ibuf_c1_clk <= io.lsu_bus_ibuf_c1_clk @[lsu_bus_intf.scala 109:51] + bus_buffer.io.lsu_bus_obuf_c1_clk <= io.lsu_bus_obuf_c1_clk @[lsu_bus_intf.scala 110:51] + bus_buffer.io.lsu_bus_buf_c1_clk <= io.lsu_bus_buf_c1_clk @[lsu_bus_intf.scala 111:51] + bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[lsu_bus_intf.scala 112:51] + bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[lsu_bus_intf.scala 113:51] + bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu_bus_intf.scala 114:51] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.store <= io.lsu_pkt_m.bits.store @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.load <= io.lsu_pkt_m.bits.load @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.word <= io.lsu_pkt_m.bits.word @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.half <= io.lsu_pkt_m.bits.half @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.by <= io.lsu_pkt_m.bits.by @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_m <= io.lsu_pkt_r.bits.store_data_bypass_m @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.load_ldst_bypass_d <= io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_d <= io.lsu_pkt_r.bits.store_data_bypass_d @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.dma <= io.lsu_pkt_r.bits.dma @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.unsign <= io.lsu_pkt_r.bits.unsign @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.store <= io.lsu_pkt_r.bits.store @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.load <= io.lsu_pkt_r.bits.load @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.dword <= io.lsu_pkt_r.bits.dword @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.word <= io.lsu_pkt_r.bits.word @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.half <= io.lsu_pkt_r.bits.half @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.by <= io.lsu_pkt_r.bits.by @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.stack <= io.lsu_pkt_r.bits.stack @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.fast_int <= io.lsu_pkt_r.bits.fast_int @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[lsu_bus_intf.scala 121:51] + bus_buffer.io.end_addr_m <= io.end_addr_m @[lsu_bus_intf.scala 122:51] + bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[lsu_bus_intf.scala 123:51] + bus_buffer.io.end_addr_r <= io.end_addr_r @[lsu_bus_intf.scala 124:51] + bus_buffer.io.store_data_r <= io.store_data_r @[lsu_bus_intf.scala 125:51] + bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[lsu_bus_intf.scala 127:51] + bus_buffer.io.flush_m_up <= io.flush_m_up @[lsu_bus_intf.scala 128:51] + bus_buffer.io.flush_r <= io.flush_r @[lsu_bus_intf.scala 129:51] + bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[lsu_bus_intf.scala 130:51] + bus_buffer.io.lsu_axi.r.bits.last <= io.axi.r.bits.last @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.resp <= io.axi.r.bits.resp @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.data <= io.axi.r.bits.data @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.id <= io.axi.r.bits.id @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.valid <= io.axi.r.valid @[lsu_bus_intf.scala 131:51] + io.axi.r.ready <= bus_buffer.io.lsu_axi.r.ready @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.qos <= bus_buffer.io.lsu_axi.ar.bits.qos @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.prot <= bus_buffer.io.lsu_axi.ar.bits.prot @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.cache <= bus_buffer.io.lsu_axi.ar.bits.cache @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.lock <= bus_buffer.io.lsu_axi.ar.bits.lock @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.burst <= bus_buffer.io.lsu_axi.ar.bits.burst @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.size <= bus_buffer.io.lsu_axi.ar.bits.size @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.len <= bus_buffer.io.lsu_axi.ar.bits.len @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.region <= bus_buffer.io.lsu_axi.ar.bits.region @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.addr <= bus_buffer.io.lsu_axi.ar.bits.addr @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.id <= bus_buffer.io.lsu_axi.ar.bits.id @[lsu_bus_intf.scala 131:51] + io.axi.ar.valid <= bus_buffer.io.lsu_axi.ar.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.ar.ready <= io.axi.ar.ready @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.bits.id <= io.axi.b.bits.id @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.bits.resp <= io.axi.b.bits.resp @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.valid <= io.axi.b.valid @[lsu_bus_intf.scala 131:51] + io.axi.b.ready <= bus_buffer.io.lsu_axi.b.ready @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.last <= bus_buffer.io.lsu_axi.w.bits.last @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.strb <= bus_buffer.io.lsu_axi.w.bits.strb @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.data <= bus_buffer.io.lsu_axi.w.bits.data @[lsu_bus_intf.scala 131:51] + io.axi.w.valid <= bus_buffer.io.lsu_axi.w.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.w.ready <= io.axi.w.ready @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.qos <= bus_buffer.io.lsu_axi.aw.bits.qos @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.prot <= bus_buffer.io.lsu_axi.aw.bits.prot @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.cache <= bus_buffer.io.lsu_axi.aw.bits.cache @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.lock <= bus_buffer.io.lsu_axi.aw.bits.lock @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.burst <= bus_buffer.io.lsu_axi.aw.bits.burst @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.size <= bus_buffer.io.lsu_axi.aw.bits.size @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.len <= bus_buffer.io.lsu_axi.aw.bits.len @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.region <= bus_buffer.io.lsu_axi.aw.bits.region @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.addr <= bus_buffer.io.lsu_axi.aw.bits.addr @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.id <= bus_buffer.io.lsu_axi.aw.bits.id @[lsu_bus_intf.scala 131:51] + io.axi.aw.valid <= bus_buffer.io.lsu_axi.aw.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.aw.ready <= io.axi.aw.ready @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 132:51] + io.lsu_nonblock_load_data <= bus_buffer.io.lsu_nonblock_load_data @[lsu_bus_intf.scala 133:29] + io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[lsu_bus_intf.scala 134:38] + io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[lsu_bus_intf.scala 135:38] + io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[lsu_bus_intf.scala 136:38] + io.lsu_bus_buffer_empty_any <= bus_buffer.io.lsu_bus_buffer_empty_any @[lsu_bus_intf.scala 137:38] + ld_byte_hit_buf_lo <= bus_buffer.io.ld_byte_hit_buf_lo @[lsu_bus_intf.scala 139:38] + ld_byte_hit_buf_hi <= bus_buffer.io.ld_byte_hit_buf_hi @[lsu_bus_intf.scala 140:38] + ld_fwddata_buf_lo <= bus_buffer.io.ld_fwddata_buf_lo @[lsu_bus_intf.scala 141:38] + ld_fwddata_buf_hi <= bus_buffer.io.ld_fwddata_buf_hi @[lsu_bus_intf.scala 142:38] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_data_error <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_intf.scala 143:19] + bus_buffer.io.no_word_merge_r <= no_word_merge_r @[lsu_bus_intf.scala 144:51] + bus_buffer.io.no_dword_merge_r <= no_dword_merge_r @[lsu_bus_intf.scala 145:51] + bus_buffer.io.is_sideeffects_r <= is_sideeffects_r @[lsu_bus_intf.scala 146:51] + bus_buffer.io.ldst_dual_d <= io.ldst_dual_d @[lsu_bus_intf.scala 147:51] + bus_buffer.io.ldst_dual_m <= io.ldst_dual_m @[lsu_bus_intf.scala 148:51] + bus_buffer.io.ldst_dual_r <= io.ldst_dual_r @[lsu_bus_intf.scala 149:51] + bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[lsu_bus_intf.scala 150:51] + bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[lsu_bus_intf.scala 151:51] + bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[lsu_bus_intf.scala 152:51] + node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[lsu_bus_intf.scala 154:63] + node _T_1 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[lsu_bus_intf.scala 154:107] + node _T_2 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[lsu_bus_intf.scala 154:148] + node _T_3 = mux(_T, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4 = mux(_T_1, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_2, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = or(_T_3, _T_4) @[Mux.scala 27:72] + node _T_7 = or(_T_6, _T_5) @[Mux.scala 27:72] + wire _T_8 : UInt<4> @[Mux.scala 27:72] + _T_8 <= _T_7 @[Mux.scala 27:72] + ldst_byteen_m <= _T_8 @[lsu_bus_intf.scala 154:27] + node _T_9 = bits(io.lsu_addr_r, 31, 3) @[lsu_bus_intf.scala 155:44] + node _T_10 = bits(io.lsu_addr_m, 31, 3) @[lsu_bus_intf.scala 155:68] + node _T_11 = eq(_T_9, _T_10) @[lsu_bus_intf.scala 155:51] + addr_match_dw_lo_r_m <= _T_11 @[lsu_bus_intf.scala 155:27] + node _T_12 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_intf.scala 156:68] + node _T_13 = bits(io.lsu_addr_m, 2, 2) @[lsu_bus_intf.scala 156:85] + node _T_14 = xor(_T_12, _T_13) @[lsu_bus_intf.scala 156:71] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[lsu_bus_intf.scala 156:53] + node _T_16 = and(addr_match_dw_lo_r_m, _T_15) @[lsu_bus_intf.scala 156:51] + addr_match_word_lo_r_m <= _T_16 @[lsu_bus_intf.scala 156:27] + node _T_17 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 157:48] + node _T_18 = and(io.lsu_busreq_r, _T_17) @[lsu_bus_intf.scala 157:46] + node _T_19 = and(_T_18, io.lsu_busreq_m) @[lsu_bus_intf.scala 157:64] + node _T_20 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 157:110] + node _T_21 = or(io.lsu_pkt_m.bits.load, _T_20) @[lsu_bus_intf.scala 157:108] + node _T_22 = and(_T_19, _T_21) @[lsu_bus_intf.scala 157:82] + no_word_merge_r <= _T_22 @[lsu_bus_intf.scala 157:27] + node _T_23 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 158:48] + node _T_24 = and(io.lsu_busreq_r, _T_23) @[lsu_bus_intf.scala 158:46] + node _T_25 = and(_T_24, io.lsu_busreq_m) @[lsu_bus_intf.scala 158:64] + node _T_26 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 158:110] + node _T_27 = or(io.lsu_pkt_m.bits.load, _T_26) @[lsu_bus_intf.scala 158:108] + node _T_28 = and(_T_25, _T_27) @[lsu_bus_intf.scala 158:82] + no_dword_merge_r <= _T_28 @[lsu_bus_intf.scala 158:27] + node _T_29 = bits(ldst_byteen_m, 3, 0) @[lsu_bus_intf.scala 160:43] + node _T_30 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 160:65] + node _T_31 = dshl(_T_29, _T_30) @[lsu_bus_intf.scala 160:49] + ldst_byteen_ext_m <= _T_31 @[lsu_bus_intf.scala 160:27] + node _T_32 = bits(ldst_byteen_r, 3, 0) @[lsu_bus_intf.scala 161:43] + node _T_33 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 161:65] + node _T_34 = dshl(_T_32, _T_33) @[lsu_bus_intf.scala 161:49] + ldst_byteen_ext_r <= _T_34 @[lsu_bus_intf.scala 161:27] + node _T_35 = bits(io.store_data_r, 31, 0) @[lsu_bus_intf.scala 162:45] + node _T_36 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 162:72] + node _T_37 = cat(_T_36, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_38 = dshl(_T_35, _T_37) @[lsu_bus_intf.scala 162:52] + store_data_ext_r <= _T_38 @[lsu_bus_intf.scala 162:27] + node _T_39 = bits(ldst_byteen_ext_m, 7, 4) @[lsu_bus_intf.scala 163:47] + ldst_byteen_hi_m <= _T_39 @[lsu_bus_intf.scala 163:27] + node _T_40 = bits(ldst_byteen_ext_m, 3, 0) @[lsu_bus_intf.scala 164:47] + ldst_byteen_lo_m <= _T_40 @[lsu_bus_intf.scala 164:27] + node _T_41 = bits(ldst_byteen_ext_r, 7, 4) @[lsu_bus_intf.scala 165:47] + ldst_byteen_hi_r <= _T_41 @[lsu_bus_intf.scala 165:27] + node _T_42 = bits(ldst_byteen_ext_r, 3, 0) @[lsu_bus_intf.scala 166:47] + ldst_byteen_lo_r <= _T_42 @[lsu_bus_intf.scala 166:27] + node _T_43 = bits(store_data_ext_r, 63, 32) @[lsu_bus_intf.scala 168:46] + store_data_hi_r <= _T_43 @[lsu_bus_intf.scala 168:27] + node _T_44 = bits(store_data_ext_r, 31, 0) @[lsu_bus_intf.scala 169:46] + store_data_lo_r <= _T_44 @[lsu_bus_intf.scala 169:27] + node _T_45 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 170:44] + node _T_46 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 170:68] + node _T_47 = eq(_T_45, _T_46) @[lsu_bus_intf.scala 170:51] + node _T_48 = and(_T_47, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 170:76] + node _T_49 = and(_T_48, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 170:97] + node _T_50 = and(_T_49, io.lsu_busreq_m) @[lsu_bus_intf.scala 170:123] + ld_addr_rhit_lo_lo <= _T_50 @[lsu_bus_intf.scala 170:27] + node _T_51 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 171:44] + node _T_52 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 171:68] + node _T_53 = eq(_T_51, _T_52) @[lsu_bus_intf.scala 171:51] + node _T_54 = and(_T_53, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 171:76] + node _T_55 = and(_T_54, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 171:97] + node _T_56 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_intf.scala 171:123] + ld_addr_rhit_lo_hi <= _T_56 @[lsu_bus_intf.scala 171:27] + node _T_57 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 172:44] + node _T_58 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 172:68] + node _T_59 = eq(_T_57, _T_58) @[lsu_bus_intf.scala 172:51] + node _T_60 = and(_T_59, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 172:76] + node _T_61 = and(_T_60, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 172:97] + node _T_62 = and(_T_61, io.lsu_busreq_m) @[lsu_bus_intf.scala 172:123] + ld_addr_rhit_hi_lo <= _T_62 @[lsu_bus_intf.scala 172:27] + node _T_63 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 173:44] + node _T_64 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 173:68] + node _T_65 = eq(_T_63, _T_64) @[lsu_bus_intf.scala 173:51] + node _T_66 = and(_T_65, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 173:76] + node _T_67 = and(_T_66, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 173:97] + node _T_68 = and(_T_67, io.lsu_busreq_m) @[lsu_bus_intf.scala 173:123] + ld_addr_rhit_hi_hi <= _T_68 @[lsu_bus_intf.scala 173:27] + node _T_69 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 175:88] + node _T_70 = and(ld_addr_rhit_lo_lo, _T_69) @[lsu_bus_intf.scala 175:70] + node _T_71 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 175:110] + node _T_72 = and(_T_70, _T_71) @[lsu_bus_intf.scala 175:92] + node _T_73 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 175:88] + node _T_74 = and(ld_addr_rhit_lo_lo, _T_73) @[lsu_bus_intf.scala 175:70] + node _T_75 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 175:110] + node _T_76 = and(_T_74, _T_75) @[lsu_bus_intf.scala 175:92] + node _T_77 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 175:88] + node _T_78 = and(ld_addr_rhit_lo_lo, _T_77) @[lsu_bus_intf.scala 175:70] + node _T_79 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 175:110] + node _T_80 = and(_T_78, _T_79) @[lsu_bus_intf.scala 175:92] + node _T_81 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 175:88] + node _T_82 = and(ld_addr_rhit_lo_lo, _T_81) @[lsu_bus_intf.scala 175:70] + node _T_83 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 175:110] + node _T_84 = and(_T_82, _T_83) @[lsu_bus_intf.scala 175:92] + node _T_85 = cat(_T_84, _T_80) @[Cat.scala 29:58] + node _T_86 = cat(_T_85, _T_76) @[Cat.scala 29:58] + node _T_87 = cat(_T_86, _T_72) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_87 @[lsu_bus_intf.scala 175:27] + node _T_88 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 176:88] + node _T_89 = and(ld_addr_rhit_lo_hi, _T_88) @[lsu_bus_intf.scala 176:70] + node _T_90 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 176:110] + node _T_91 = and(_T_89, _T_90) @[lsu_bus_intf.scala 176:92] + node _T_92 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 176:88] + node _T_93 = and(ld_addr_rhit_lo_hi, _T_92) @[lsu_bus_intf.scala 176:70] + node _T_94 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 176:110] + node _T_95 = and(_T_93, _T_94) @[lsu_bus_intf.scala 176:92] + node _T_96 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 176:88] + node _T_97 = and(ld_addr_rhit_lo_hi, _T_96) @[lsu_bus_intf.scala 176:70] + node _T_98 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 176:110] + node _T_99 = and(_T_97, _T_98) @[lsu_bus_intf.scala 176:92] + node _T_100 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 176:88] + node _T_101 = and(ld_addr_rhit_lo_hi, _T_100) @[lsu_bus_intf.scala 176:70] + node _T_102 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 176:110] + node _T_103 = and(_T_101, _T_102) @[lsu_bus_intf.scala 176:92] + node _T_104 = cat(_T_103, _T_99) @[Cat.scala 29:58] + node _T_105 = cat(_T_104, _T_95) @[Cat.scala 29:58] + node _T_106 = cat(_T_105, _T_91) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_106 @[lsu_bus_intf.scala 176:27] + node _T_107 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 177:88] + node _T_108 = and(ld_addr_rhit_hi_lo, _T_107) @[lsu_bus_intf.scala 177:70] + node _T_109 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 177:110] + node _T_110 = and(_T_108, _T_109) @[lsu_bus_intf.scala 177:92] + node _T_111 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 177:88] + node _T_112 = and(ld_addr_rhit_hi_lo, _T_111) @[lsu_bus_intf.scala 177:70] + node _T_113 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 177:110] + node _T_114 = and(_T_112, _T_113) @[lsu_bus_intf.scala 177:92] + node _T_115 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 177:88] + node _T_116 = and(ld_addr_rhit_hi_lo, _T_115) @[lsu_bus_intf.scala 177:70] + node _T_117 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 177:110] + node _T_118 = and(_T_116, _T_117) @[lsu_bus_intf.scala 177:92] + node _T_119 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 177:88] + node _T_120 = and(ld_addr_rhit_hi_lo, _T_119) @[lsu_bus_intf.scala 177:70] + node _T_121 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 177:110] + node _T_122 = and(_T_120, _T_121) @[lsu_bus_intf.scala 177:92] + node _T_123 = cat(_T_122, _T_118) @[Cat.scala 29:58] + node _T_124 = cat(_T_123, _T_114) @[Cat.scala 29:58] + node _T_125 = cat(_T_124, _T_110) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_125 @[lsu_bus_intf.scala 177:27] + node _T_126 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 178:88] + node _T_127 = and(ld_addr_rhit_hi_hi, _T_126) @[lsu_bus_intf.scala 178:70] + node _T_128 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 178:110] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_intf.scala 178:92] + node _T_130 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 178:88] + node _T_131 = and(ld_addr_rhit_hi_hi, _T_130) @[lsu_bus_intf.scala 178:70] + node _T_132 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 178:110] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_intf.scala 178:92] + node _T_134 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 178:88] + node _T_135 = and(ld_addr_rhit_hi_hi, _T_134) @[lsu_bus_intf.scala 178:70] + node _T_136 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 178:110] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_intf.scala 178:92] + node _T_138 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 178:88] + node _T_139 = and(ld_addr_rhit_hi_hi, _T_138) @[lsu_bus_intf.scala 178:70] + node _T_140 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 178:110] + node _T_141 = and(_T_139, _T_140) @[lsu_bus_intf.scala 178:92] + node _T_142 = cat(_T_141, _T_137) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_133) @[Cat.scala 29:58] + node _T_144 = cat(_T_143, _T_129) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_144 @[lsu_bus_intf.scala 178:27] + node _T_145 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 180:69] + node _T_146 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 180:93] + node _T_147 = or(_T_145, _T_146) @[lsu_bus_intf.scala 180:73] + node _T_148 = bits(ld_byte_hit_buf_lo, 0, 0) @[lsu_bus_intf.scala 180:117] + node _T_149 = or(_T_147, _T_148) @[lsu_bus_intf.scala 180:97] + node _T_150 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 180:69] + node _T_151 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 180:93] + node _T_152 = or(_T_150, _T_151) @[lsu_bus_intf.scala 180:73] + node _T_153 = bits(ld_byte_hit_buf_lo, 1, 1) @[lsu_bus_intf.scala 180:117] + node _T_154 = or(_T_152, _T_153) @[lsu_bus_intf.scala 180:97] + node _T_155 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 180:69] + node _T_156 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 180:93] + node _T_157 = or(_T_155, _T_156) @[lsu_bus_intf.scala 180:73] + node _T_158 = bits(ld_byte_hit_buf_lo, 2, 2) @[lsu_bus_intf.scala 180:117] + node _T_159 = or(_T_157, _T_158) @[lsu_bus_intf.scala 180:97] + node _T_160 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 180:69] + node _T_161 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 180:93] + node _T_162 = or(_T_160, _T_161) @[lsu_bus_intf.scala 180:73] + node _T_163 = bits(ld_byte_hit_buf_lo, 3, 3) @[lsu_bus_intf.scala 180:117] + node _T_164 = or(_T_162, _T_163) @[lsu_bus_intf.scala 180:97] + node _T_165 = cat(_T_164, _T_159) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, _T_154) @[Cat.scala 29:58] + node _T_167 = cat(_T_166, _T_149) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_167 @[lsu_bus_intf.scala 180:27] + node _T_168 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 181:69] + node _T_169 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 181:93] + node _T_170 = or(_T_168, _T_169) @[lsu_bus_intf.scala 181:73] + node _T_171 = bits(ld_byte_hit_buf_hi, 0, 0) @[lsu_bus_intf.scala 181:117] + node _T_172 = or(_T_170, _T_171) @[lsu_bus_intf.scala 181:97] + node _T_173 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 181:69] + node _T_174 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 181:93] + node _T_175 = or(_T_173, _T_174) @[lsu_bus_intf.scala 181:73] + node _T_176 = bits(ld_byte_hit_buf_hi, 1, 1) @[lsu_bus_intf.scala 181:117] + node _T_177 = or(_T_175, _T_176) @[lsu_bus_intf.scala 181:97] + node _T_178 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 181:69] + node _T_179 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 181:93] + node _T_180 = or(_T_178, _T_179) @[lsu_bus_intf.scala 181:73] + node _T_181 = bits(ld_byte_hit_buf_hi, 2, 2) @[lsu_bus_intf.scala 181:117] + node _T_182 = or(_T_180, _T_181) @[lsu_bus_intf.scala 181:97] + node _T_183 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 181:69] + node _T_184 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 181:93] + node _T_185 = or(_T_183, _T_184) @[lsu_bus_intf.scala 181:73] + node _T_186 = bits(ld_byte_hit_buf_hi, 3, 3) @[lsu_bus_intf.scala 181:117] + node _T_187 = or(_T_185, _T_186) @[lsu_bus_intf.scala 181:97] + node _T_188 = cat(_T_187, _T_182) @[Cat.scala 29:58] + node _T_189 = cat(_T_188, _T_177) @[Cat.scala 29:58] + node _T_190 = cat(_T_189, _T_172) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_190 @[lsu_bus_intf.scala 181:27] + node _T_191 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 182:69] + node _T_192 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 182:93] + node _T_193 = or(_T_191, _T_192) @[lsu_bus_intf.scala 182:73] + node _T_194 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 182:69] + node _T_195 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 182:93] + node _T_196 = or(_T_194, _T_195) @[lsu_bus_intf.scala 182:73] + node _T_197 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 182:69] + node _T_198 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 182:93] + node _T_199 = or(_T_197, _T_198) @[lsu_bus_intf.scala 182:73] + node _T_200 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 182:69] + node _T_201 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 182:93] + node _T_202 = or(_T_200, _T_201) @[lsu_bus_intf.scala 182:73] + node _T_203 = cat(_T_202, _T_199) @[Cat.scala 29:58] + node _T_204 = cat(_T_203, _T_196) @[Cat.scala 29:58] + node _T_205 = cat(_T_204, _T_193) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_205 @[lsu_bus_intf.scala 182:27] + node _T_206 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 183:69] + node _T_207 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 183:93] + node _T_208 = or(_T_206, _T_207) @[lsu_bus_intf.scala 183:73] + node _T_209 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 183:69] + node _T_210 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 183:93] + node _T_211 = or(_T_209, _T_210) @[lsu_bus_intf.scala 183:73] + node _T_212 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 183:69] + node _T_213 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 183:93] + node _T_214 = or(_T_212, _T_213) @[lsu_bus_intf.scala 183:73] + node _T_215 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 183:69] + node _T_216 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 183:93] + node _T_217 = or(_T_215, _T_216) @[lsu_bus_intf.scala 183:73] + node _T_218 = cat(_T_217, _T_214) @[Cat.scala 29:58] + node _T_219 = cat(_T_218, _T_211) @[Cat.scala 29:58] + node _T_220 = cat(_T_219, _T_208) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_220 @[lsu_bus_intf.scala 183:27] + node _T_221 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 184:79] + node _T_222 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 184:101] + node _T_223 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 184:136] + node _T_224 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 184:158] + node _T_225 = mux(_T_221, _T_222, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_226 = mux(_T_223, _T_224, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_227 = or(_T_225, _T_226) @[Mux.scala 27:72] + wire _T_228 : UInt<8> @[Mux.scala 27:72] + _T_228 <= _T_227 @[Mux.scala 27:72] + node _T_229 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 184:79] + node _T_230 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 184:101] + node _T_231 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 184:136] + node _T_232 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 184:158] + node _T_233 = mux(_T_229, _T_230, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_234 = mux(_T_231, _T_232, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_235 = or(_T_233, _T_234) @[Mux.scala 27:72] + wire _T_236 : UInt<8> @[Mux.scala 27:72] + _T_236 <= _T_235 @[Mux.scala 27:72] + node _T_237 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 184:79] + node _T_238 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 184:101] + node _T_239 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 184:136] + node _T_240 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 184:158] + node _T_241 = mux(_T_237, _T_238, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_242 = mux(_T_239, _T_240, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_243 = or(_T_241, _T_242) @[Mux.scala 27:72] + wire _T_244 : UInt<8> @[Mux.scala 27:72] + _T_244 <= _T_243 @[Mux.scala 27:72] + node _T_245 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 184:79] + node _T_246 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 184:101] + node _T_247 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 184:136] + node _T_248 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 184:158] + node _T_249 = mux(_T_245, _T_246, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_250 = mux(_T_247, _T_248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_251 = or(_T_249, _T_250) @[Mux.scala 27:72] + wire _T_252 : UInt<8> @[Mux.scala 27:72] + _T_252 <= _T_251 @[Mux.scala 27:72] + node _T_253 = cat(_T_252, _T_244) @[Cat.scala 29:58] + node _T_254 = cat(_T_253, _T_236) @[Cat.scala 29:58] + node _T_255 = cat(_T_254, _T_228) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_255 @[lsu_bus_intf.scala 184:27] + node _T_256 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 185:79] + node _T_257 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 185:101] + node _T_258 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 185:136] + node _T_259 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 185:158] + node _T_260 = mux(_T_256, _T_257, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = or(_T_260, _T_261) @[Mux.scala 27:72] + wire _T_263 : UInt<8> @[Mux.scala 27:72] + _T_263 <= _T_262 @[Mux.scala 27:72] + node _T_264 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 185:79] + node _T_265 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 185:101] + node _T_266 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 185:136] + node _T_267 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 185:158] + node _T_268 = mux(_T_264, _T_265, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_269 = mux(_T_266, _T_267, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_270 = or(_T_268, _T_269) @[Mux.scala 27:72] + wire _T_271 : UInt<8> @[Mux.scala 27:72] + _T_271 <= _T_270 @[Mux.scala 27:72] + node _T_272 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 185:79] + node _T_273 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 185:101] + node _T_274 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 185:136] + node _T_275 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 185:158] + node _T_276 = mux(_T_272, _T_273, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_277 = mux(_T_274, _T_275, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_278 = or(_T_276, _T_277) @[Mux.scala 27:72] + wire _T_279 : UInt<8> @[Mux.scala 27:72] + _T_279 <= _T_278 @[Mux.scala 27:72] + node _T_280 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 185:79] + node _T_281 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 185:101] + node _T_282 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 185:136] + node _T_283 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 185:158] + node _T_284 = mux(_T_280, _T_281, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_285 = mux(_T_282, _T_283, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_286 = or(_T_284, _T_285) @[Mux.scala 27:72] + wire _T_287 : UInt<8> @[Mux.scala 27:72] + _T_287 <= _T_286 @[Mux.scala 27:72] + node _T_288 = cat(_T_287, _T_279) @[Cat.scala 29:58] + node _T_289 = cat(_T_288, _T_271) @[Cat.scala 29:58] + node _T_290 = cat(_T_289, _T_263) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_290 @[lsu_bus_intf.scala 185:27] + node _T_291 = bits(ld_byte_rhit_lo, 0, 0) @[lsu_bus_intf.scala 186:70] + node _T_292 = bits(ld_fwddata_rpipe_lo, 7, 0) @[lsu_bus_intf.scala 186:94] + node _T_293 = bits(ld_fwddata_buf_lo, 7, 0) @[lsu_bus_intf.scala 186:128] + node _T_294 = mux(_T_291, _T_292, _T_293) @[lsu_bus_intf.scala 186:54] + node _T_295 = bits(ld_byte_rhit_lo, 1, 1) @[lsu_bus_intf.scala 186:70] + node _T_296 = bits(ld_fwddata_rpipe_lo, 15, 8) @[lsu_bus_intf.scala 186:94] + node _T_297 = bits(ld_fwddata_buf_lo, 15, 8) @[lsu_bus_intf.scala 186:128] + node _T_298 = mux(_T_295, _T_296, _T_297) @[lsu_bus_intf.scala 186:54] + node _T_299 = bits(ld_byte_rhit_lo, 2, 2) @[lsu_bus_intf.scala 186:70] + node _T_300 = bits(ld_fwddata_rpipe_lo, 23, 16) @[lsu_bus_intf.scala 186:94] + node _T_301 = bits(ld_fwddata_buf_lo, 23, 16) @[lsu_bus_intf.scala 186:128] + node _T_302 = mux(_T_299, _T_300, _T_301) @[lsu_bus_intf.scala 186:54] + node _T_303 = bits(ld_byte_rhit_lo, 3, 3) @[lsu_bus_intf.scala 186:70] + node _T_304 = bits(ld_fwddata_rpipe_lo, 31, 24) @[lsu_bus_intf.scala 186:94] + node _T_305 = bits(ld_fwddata_buf_lo, 31, 24) @[lsu_bus_intf.scala 186:128] + node _T_306 = mux(_T_303, _T_304, _T_305) @[lsu_bus_intf.scala 186:54] + node _T_307 = cat(_T_306, _T_302) @[Cat.scala 29:58] + node _T_308 = cat(_T_307, _T_298) @[Cat.scala 29:58] + node _T_309 = cat(_T_308, _T_294) @[Cat.scala 29:58] + ld_fwddata_lo <= _T_309 @[lsu_bus_intf.scala 186:27] + node _T_310 = bits(ld_byte_rhit_hi, 0, 0) @[lsu_bus_intf.scala 187:70] + node _T_311 = bits(ld_fwddata_rpipe_hi, 7, 0) @[lsu_bus_intf.scala 187:94] + node _T_312 = bits(ld_fwddata_buf_hi, 7, 0) @[lsu_bus_intf.scala 187:128] + node _T_313 = mux(_T_310, _T_311, _T_312) @[lsu_bus_intf.scala 187:54] + node _T_314 = bits(ld_byte_rhit_hi, 1, 1) @[lsu_bus_intf.scala 187:70] + node _T_315 = bits(ld_fwddata_rpipe_hi, 15, 8) @[lsu_bus_intf.scala 187:94] + node _T_316 = bits(ld_fwddata_buf_hi, 15, 8) @[lsu_bus_intf.scala 187:128] + node _T_317 = mux(_T_314, _T_315, _T_316) @[lsu_bus_intf.scala 187:54] + node _T_318 = bits(ld_byte_rhit_hi, 2, 2) @[lsu_bus_intf.scala 187:70] + node _T_319 = bits(ld_fwddata_rpipe_hi, 23, 16) @[lsu_bus_intf.scala 187:94] + node _T_320 = bits(ld_fwddata_buf_hi, 23, 16) @[lsu_bus_intf.scala 187:128] + node _T_321 = mux(_T_318, _T_319, _T_320) @[lsu_bus_intf.scala 187:54] + node _T_322 = bits(ld_byte_rhit_hi, 3, 3) @[lsu_bus_intf.scala 187:70] + node _T_323 = bits(ld_fwddata_rpipe_hi, 31, 24) @[lsu_bus_intf.scala 187:94] + node _T_324 = bits(ld_fwddata_buf_hi, 31, 24) @[lsu_bus_intf.scala 187:128] + node _T_325 = mux(_T_322, _T_323, _T_324) @[lsu_bus_intf.scala 187:54] + node _T_326 = cat(_T_325, _T_321) @[Cat.scala 29:58] + node _T_327 = cat(_T_326, _T_317) @[Cat.scala 29:58] + node _T_328 = cat(_T_327, _T_313) @[Cat.scala 29:58] + ld_fwddata_hi <= _T_328 @[lsu_bus_intf.scala 187:27] + node _T_329 = bits(ld_byte_hit_lo, 0, 0) @[lsu_bus_intf.scala 188:66] + node _T_330 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 188:89] + node _T_331 = eq(_T_330, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_332 = or(_T_329, _T_331) @[lsu_bus_intf.scala 188:70] + node _T_333 = bits(ld_byte_hit_lo, 1, 1) @[lsu_bus_intf.scala 188:66] + node _T_334 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 188:89] + node _T_335 = eq(_T_334, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_336 = or(_T_333, _T_335) @[lsu_bus_intf.scala 188:70] + node _T_337 = bits(ld_byte_hit_lo, 2, 2) @[lsu_bus_intf.scala 188:66] + node _T_338 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 188:89] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_340 = or(_T_337, _T_339) @[lsu_bus_intf.scala 188:70] + node _T_341 = bits(ld_byte_hit_lo, 3, 3) @[lsu_bus_intf.scala 188:66] + node _T_342 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 188:89] + node _T_343 = eq(_T_342, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_344 = or(_T_341, _T_343) @[lsu_bus_intf.scala 188:70] + node _T_345 = and(_T_332, _T_336) @[lsu_bus_intf.scala 188:111] + node _T_346 = and(_T_345, _T_340) @[lsu_bus_intf.scala 188:111] + node _T_347 = and(_T_346, _T_344) @[lsu_bus_intf.scala 188:111] + ld_full_hit_lo_m <= _T_347 @[lsu_bus_intf.scala 188:27] + node _T_348 = bits(ld_byte_hit_hi, 0, 0) @[lsu_bus_intf.scala 189:66] + node _T_349 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 189:89] + node _T_350 = eq(_T_349, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_351 = or(_T_348, _T_350) @[lsu_bus_intf.scala 189:70] + node _T_352 = bits(ld_byte_hit_hi, 1, 1) @[lsu_bus_intf.scala 189:66] + node _T_353 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 189:89] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_355 = or(_T_352, _T_354) @[lsu_bus_intf.scala 189:70] + node _T_356 = bits(ld_byte_hit_hi, 2, 2) @[lsu_bus_intf.scala 189:66] + node _T_357 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 189:89] + node _T_358 = eq(_T_357, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_359 = or(_T_356, _T_358) @[lsu_bus_intf.scala 189:70] + node _T_360 = bits(ld_byte_hit_hi, 3, 3) @[lsu_bus_intf.scala 189:66] + node _T_361 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 189:89] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_363 = or(_T_360, _T_362) @[lsu_bus_intf.scala 189:70] + node _T_364 = and(_T_351, _T_355) @[lsu_bus_intf.scala 189:111] + node _T_365 = and(_T_364, _T_359) @[lsu_bus_intf.scala 189:111] + node _T_366 = and(_T_365, _T_363) @[lsu_bus_intf.scala 189:111] + ld_full_hit_hi_m <= _T_366 @[lsu_bus_intf.scala 189:27] + node _T_367 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[lsu_bus_intf.scala 190:47] + node _T_368 = and(_T_367, io.lsu_busreq_m) @[lsu_bus_intf.scala 190:66] + node _T_369 = and(_T_368, io.lsu_pkt_m.bits.load) @[lsu_bus_intf.scala 190:84] + node _T_370 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[lsu_bus_intf.scala 190:111] + node _T_371 = and(_T_369, _T_370) @[lsu_bus_intf.scala 190:109] + ld_full_hit_m <= _T_371 @[lsu_bus_intf.scala 190:27] + node _T_372 = bits(ld_fwddata_hi, 31, 0) @[lsu_bus_intf.scala 191:47] + node _T_373 = bits(ld_fwddata_lo, 31, 0) @[lsu_bus_intf.scala 191:68] + node _T_374 = cat(_T_372, _T_373) @[Cat.scala 29:58] + node _T_375 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 191:97] + node _T_376 = mul(UInt<4>("h08"), _T_375) @[lsu_bus_intf.scala 191:83] + node _T_377 = dshr(_T_374, _T_376) @[lsu_bus_intf.scala 191:76] + ld_fwddata_m <= _T_377 @[lsu_bus_intf.scala 191:27] + node _T_378 = bits(ld_fwddata_m, 31, 0) @[lsu_bus_intf.scala 192:42] + io.bus_read_data_m <= _T_378 @[lsu_bus_intf.scala 192:27] + reg _T_379 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 195:32] + _T_379 <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 195:32] + lsu_bus_clk_en_q <= _T_379 @[lsu_bus_intf.scala 195:22] + reg _T_380 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 199:33] + _T_380 <= io.is_sideeffects_m @[lsu_bus_intf.scala 199:33] + is_sideeffects_r <= _T_380 @[lsu_bus_intf.scala 199:23] + reg _T_381 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<4>("h00"))) @[lsu_bus_intf.scala 200:33] + _T_381 <= ldst_byteen_m @[lsu_bus_intf.scala 200:33] + ldst_byteen_r <= _T_381 @[lsu_bus_intf.scala 200:23] + + module lsu : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>}, lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_active : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_pmu_misaligned_m : UInt<1>, lsu_trigger_match_m : UInt<4>, flip lsu_bus_clk_en : UInt<1>, flip scan_mode : UInt<1>, flip active_clk : Clock, lsu_nonblock_load_data : UInt<32>} + + wire dma_dccm_wdata : UInt<64> + dma_dccm_wdata <= UInt<64>("h00") + wire dma_dccm_wdata_lo : UInt<32> + dma_dccm_wdata_lo <= UInt<32>("h00") + wire dma_dccm_wdata_hi : UInt<32> + dma_dccm_wdata_hi <= UInt<32>("h00") + wire dma_mem_tag_m : UInt<3> + dma_mem_tag_m <= UInt<3>("h00") + wire lsu_raw_fwd_lo_r : UInt<1> + lsu_raw_fwd_lo_r <= UInt<1>("h00") + wire lsu_raw_fwd_hi_r : UInt<1> + lsu_raw_fwd_hi_r <= UInt<1>("h00") + wire lsu_busm_clken : UInt<1> + lsu_busm_clken <= UInt<1>("h00") + wire lsu_bus_obuf_c1_clken : UInt<1> + lsu_bus_obuf_c1_clken <= UInt<1>("h00") + wire lsu_busreq_r : UInt<1> + lsu_busreq_r <= UInt<1>("h00") + inst lsu_lsc_ctl of lsu_lsc_ctl @[lsu.scala 72:30] + lsu_lsc_ctl.clock <= clock + lsu_lsc_ctl.reset <= reset + io.lsu_result_corr_r <= lsu_lsc_ctl.io.lsu_result_corr_r @[lsu.scala 75:24] + inst dccm_ctl of lsu_dccm_ctl @[lsu.scala 76:30] + dccm_ctl.clock <= clock + dccm_ctl.reset <= reset + inst stbuf of lsu_stbuf @[lsu.scala 77:30] + stbuf.clock <= clock + stbuf.reset <= reset + inst ecc of lsu_ecc @[lsu.scala 78:30] + ecc.clock <= clock + ecc.reset <= reset + inst trigger of lsu_trigger @[lsu.scala 79:30] + trigger.clock <= clock + trigger.reset <= reset + inst clkdomain of lsu_clkdomain @[lsu.scala 80:30] + clkdomain.clock <= clock + clkdomain.reset <= reset + inst bus_intf of lsu_bus_intf @[lsu.scala 81:30] + bus_intf.clock <= clock + bus_intf.reset <= reset + node lsu_raw_fwd_lo_m = orr(stbuf.io.stbuf_fwdbyteen_lo_m) @[lsu.scala 83:56] + node lsu_raw_fwd_hi_m = orr(stbuf.io.stbuf_fwdbyteen_hi_m) @[lsu.scala 84:56] + node _T = or(stbuf.io.lsu_stbuf_full_any, bus_intf.io.lsu_bus_buffer_full_any) @[lsu.scala 87:57] + node _T_1 = or(_T, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 87:95] + io.lsu_store_stall_any <= _T_1 @[lsu.scala 87:26] + node _T_2 = or(bus_intf.io.lsu_bus_buffer_full_any, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 88:64] + io.lsu_load_stall_any <= _T_2 @[lsu.scala 88:25] + io.lsu_fastint_stall_any <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 89:28] + node _T_3 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 94:58] + node _T_4 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_3) @[lsu.scala 94:56] + node _T_5 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 94:126] + node _T_6 = and(_T_4, _T_5) @[lsu.scala 94:93] + node ldst_nodma_mtor = and(_T_6, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 94:158] + node _T_7 = or(io.dec_lsu_valid_raw_d, ldst_nodma_mtor) @[lsu.scala 95:53] + node _T_8 = or(_T_7, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 95:71] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[lsu.scala 95:28] + io.lsu_dma.dccm_ready <= _T_9 @[lsu.scala 95:25] + node _T_10 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 96:58] + node _T_11 = and(_T_10, lsu_lsc_ctl.io.addr_in_dccm_d) @[lsu.scala 96:97] + node _T_12 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_sz, 1, 1) @[lsu.scala 96:164] + node dma_dccm_wen = and(_T_11, _T_12) @[lsu.scala 96:129] + node _T_13 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 97:58] + node dma_pic_wen = and(_T_13, lsu_lsc_ctl.io.addr_in_pic_d) @[lsu.scala 97:97] + node _T_14 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu.scala 98:100] + node _T_15 = cat(_T_14, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_16 = dshr(io.lsu_dma.dma_lsc_ctl.dma_mem_wdata, _T_15) @[lsu.scala 98:58] + dma_dccm_wdata <= _T_16 @[lsu.scala 98:18] + node _T_17 = bits(dma_dccm_wdata, 63, 32) @[lsu.scala 99:38] + dma_dccm_wdata_hi <= _T_17 @[lsu.scala 99:21] + node _T_18 = bits(dma_dccm_wdata, 31, 0) @[lsu.scala 100:38] + dma_dccm_wdata_lo <= _T_18 @[lsu.scala 100:21] + node _T_19 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 109:58] + node _T_20 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_19) @[lsu.scala 109:56] + node _T_21 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 109:130] + node _T_22 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, _T_21) @[lsu.scala 109:128] + node _T_23 = or(_T_20, _T_22) @[lsu.scala 109:94] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[lsu.scala 109:22] + node _T_25 = and(_T_24, bus_intf.io.lsu_bus_buffer_empty_any) @[lsu.scala 109:167] + io.lsu_idle_any <= _T_25 @[lsu.scala 109:19] + node _T_26 = or(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_r.valid) @[lsu.scala 110:53] + node _T_27 = or(_T_26, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 110:86] + node _T_28 = eq(bus_intf.io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu.scala 110:128] + node _T_29 = or(_T_27, _T_28) @[lsu.scala 110:126] + io.lsu_active <= _T_29 @[lsu.scala 110:18] + node _T_30 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, lsu_lsc_ctl.io.lsu_pkt_r.bits.store) @[lsu.scala 112:61] + node _T_31 = and(_T_30, lsu_lsc_ctl.io.addr_in_dccm_r) @[lsu.scala 112:99] + node _T_32 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[lsu.scala 112:133] + node _T_33 = and(_T_31, _T_32) @[lsu.scala 112:131] + node _T_34 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 112:145] + node _T_35 = or(lsu_lsc_ctl.io.lsu_pkt_r.bits.by, lsu_lsc_ctl.io.lsu_pkt_r.bits.half) @[lsu.scala 112:217] + node _T_36 = eq(ecc.io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu.scala 112:257] + node _T_37 = and(_T_35, _T_36) @[lsu.scala 112:255] + node _T_38 = or(_T_34, _T_37) @[lsu.scala 112:180] + node store_stbuf_reqvld_r = and(_T_33, _T_38) @[lsu.scala 112:142] + node _T_39 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 114:90] + node _T_40 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_39) @[lsu.scala 114:52] + node _T_41 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 114:162] + node lsu_cmpen_m = and(_T_40, _T_41) @[lsu.scala 114:129] + node _T_42 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 116:92] + node _T_43 = and(_T_42, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 116:131] + node _T_44 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_43) @[lsu.scala 116:53] + node _T_45 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[lsu.scala 116:167] + node _T_46 = and(_T_44, _T_45) @[lsu.scala 116:165] + node _T_47 = eq(lsu_lsc_ctl.io.lsu_exc_m, UInt<1>("h00")) @[lsu.scala 116:181] + node _T_48 = and(_T_46, _T_47) @[lsu.scala 116:179] + node _T_49 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu.scala 116:209] + node lsu_busreq_m = and(_T_48, _T_49) @[lsu.scala 116:207] + node _T_50 = bits(lsu_lsc_ctl.io.lsu_addr_m, 0, 0) @[lsu.scala 120:127] + node _T_51 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.half, _T_50) @[lsu.scala 120:100] + node _T_52 = bits(lsu_lsc_ctl.io.lsu_addr_m, 1, 0) @[lsu.scala 120:197] + node _T_53 = orr(_T_52) @[lsu.scala 120:203] + node _T_54 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.word, _T_53) @[lsu.scala 120:170] + node _T_55 = or(_T_51, _T_54) @[lsu.scala 120:132] + node _T_56 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_55) @[lsu.scala 120:61] + io.lsu_pmu_misaligned_m <= _T_56 @[lsu.scala 120:27] + node _T_57 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.load) @[lsu.scala 121:73] + node _T_58 = and(_T_57, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 121:110] + io.lsu_tlu.lsu_pmu_load_external_m <= _T_58 @[lsu.scala 121:39] + node _T_59 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 122:73] + node _T_60 = and(_T_59, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 122:111] + io.lsu_tlu.lsu_pmu_store_external_m <= _T_60 @[lsu.scala 122:39] + lsu_lsc_ctl.io.clk_override <= io.clk_override @[lsu.scala 126:46] + lsu_lsc_ctl.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[lsu.scala 127:46] + lsu_lsc_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 128:46] + lsu_lsc_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[lsu.scala 129:46] + lsu_lsc_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 130:46] + lsu_lsc_ctl.io.lsu_store_c1_m_clk <= clkdomain.io.lsu_store_c1_m_clk @[lsu.scala 131:46] + lsu_lsc_ctl.io.lsu_ld_data_r <= dccm_ctl.io.lsu_ld_data_r @[lsu.scala 132:46] + lsu_lsc_ctl.io.lsu_ld_data_corr_r <= dccm_ctl.io.lsu_ld_data_corr_r @[lsu.scala 133:46] + lsu_lsc_ctl.io.lsu_single_ecc_error_r <= ecc.io.lsu_single_ecc_error_r @[lsu.scala 134:46] + lsu_lsc_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[lsu.scala 135:46] + lsu_lsc_ctl.io.lsu_ld_data_m <= dccm_ctl.io.lsu_ld_data_m @[lsu.scala 136:46] + lsu_lsc_ctl.io.lsu_single_ecc_error_m <= ecc.io.lsu_single_ecc_error_m @[lsu.scala 137:46] + lsu_lsc_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[lsu.scala 138:46] + lsu_lsc_ctl.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 139:46] + lsu_lsc_ctl.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 140:46] + node _T_61 = bits(lsu_lsc_ctl.io.lsu_addr_d, 2, 2) @[lsu.scala 141:74] + node _T_62 = bits(lsu_lsc_ctl.io.end_addr_d, 2, 2) @[lsu.scala 141:107] + node _T_63 = neq(_T_61, _T_62) @[lsu.scala 141:78] + lsu_lsc_ctl.io.ldst_dual_d <= _T_63 @[lsu.scala 141:46] + node _T_64 = bits(lsu_lsc_ctl.io.lsu_addr_m, 2, 2) @[lsu.scala 142:74] + node _T_65 = bits(lsu_lsc_ctl.io.end_addr_m, 2, 2) @[lsu.scala 142:107] + node _T_66 = neq(_T_64, _T_65) @[lsu.scala 142:78] + lsu_lsc_ctl.io.ldst_dual_m <= _T_66 @[lsu.scala 142:46] + node _T_67 = bits(lsu_lsc_ctl.io.lsu_addr_r, 2, 2) @[lsu.scala 143:74] + node _T_68 = bits(lsu_lsc_ctl.io.end_addr_r, 2, 2) @[lsu.scala 143:107] + node _T_69 = neq(_T_67, _T_68) @[lsu.scala 143:78] + lsu_lsc_ctl.io.ldst_dual_r <= _T_69 @[lsu.scala 143:46] + io.lsu_exu.lsu_result_m <= lsu_lsc_ctl.io.lsu_exu.lsu_result_m @[lsu.scala 144:46] + lsu_lsc_ctl.io.lsu_exu.exu_lsu_rs2_d <= io.lsu_exu.exu_lsu_rs2_d @[lsu.scala 144:46] + lsu_lsc_ctl.io.lsu_exu.exu_lsu_rs1_d <= io.lsu_exu.exu_lsu_rs1_d @[lsu.scala 144:46] + lsu_lsc_ctl.io.lsu_p.bits.store_data_bypass_m <= io.lsu_p.bits.store_data_bypass_m @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.load_ldst_bypass_d <= io.lsu_p.bits.load_ldst_bypass_d @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.store_data_bypass_d <= io.lsu_p.bits.store_data_bypass_d @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.dma <= io.lsu_p.bits.dma @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.unsign <= io.lsu_p.bits.unsign @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.store <= io.lsu_p.bits.store @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.load <= io.lsu_p.bits.load @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.dword <= io.lsu_p.bits.dword @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.word <= io.lsu_p.bits.word @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.half <= io.lsu_p.bits.half @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.by <= io.lsu_p.bits.by @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.stack <= io.lsu_p.bits.stack @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.fast_int <= io.lsu_p.bits.fast_int @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.valid <= io.lsu_p.valid @[lsu.scala 145:46] + lsu_lsc_ctl.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 146:46] + lsu_lsc_ctl.io.dec_lsu_offset_d <= io.dec_lsu_offset_d @[lsu.scala 147:46] + lsu_lsc_ctl.io.picm_mask_data_m <= dccm_ctl.io.picm_mask_data_m @[lsu.scala 148:46] + lsu_lsc_ctl.io.bus_read_data_m <= bus_intf.io.bus_read_data_m @[lsu.scala 149:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[lsu.scala 150:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[lsu.scala 150:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[lsu.scala 150:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[lsu.scala 150:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_dccm_req <= io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[lsu.scala 150:46] + lsu_lsc_ctl.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu.scala 151:46] + lsu_lsc_ctl.io.scan_mode <= io.scan_mode @[lsu.scala 152:46] + io.lsu_single_ecc_error_incr <= lsu_lsc_ctl.io.lsu_single_ecc_error_incr @[lsu.scala 160:49] + io.lsu_error_pkt_r.bits.addr <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.addr @[lsu.scala 161:49] + io.lsu_error_pkt_r.bits.mscause <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.mscause @[lsu.scala 161:49] + io.lsu_error_pkt_r.bits.exc_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.exc_type @[lsu.scala 161:49] + io.lsu_error_pkt_r.bits.inst_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.inst_type @[lsu.scala 161:49] + io.lsu_error_pkt_r.bits.single_ecc_error <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.single_ecc_error @[lsu.scala 161:49] + io.lsu_error_pkt_r.valid <= lsu_lsc_ctl.io.lsu_error_pkt_r.valid @[lsu.scala 161:49] + io.lsu_fir_addr <= lsu_lsc_ctl.io.lsu_fir_addr @[lsu.scala 162:49] + io.lsu_fir_error <= lsu_lsc_ctl.io.lsu_fir_error @[lsu.scala 163:49] + dccm_ctl.io.clk_override <= io.clk_override @[lsu.scala 166:46] + node _T_70 = bits(lsu_lsc_ctl.io.lsu_addr_m, 2, 2) @[lsu.scala 167:74] + node _T_71 = bits(lsu_lsc_ctl.io.end_addr_m, 2, 2) @[lsu.scala 167:107] + node _T_72 = neq(_T_70, _T_71) @[lsu.scala 167:78] + dccm_ctl.io.ldst_dual_m <= _T_72 @[lsu.scala 167:46] + node _T_73 = bits(lsu_lsc_ctl.io.lsu_addr_r, 2, 2) @[lsu.scala 168:74] + node _T_74 = bits(lsu_lsc_ctl.io.end_addr_r, 2, 2) @[lsu.scala 168:107] + node _T_75 = neq(_T_73, _T_74) @[lsu.scala 168:78] + dccm_ctl.io.ldst_dual_r <= _T_75 @[lsu.scala 168:46] + dccm_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[lsu.scala 169:46] + dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 170:46] + dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 171:46] + dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 172:46] + dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_store_c1_r_clk @[lsu.scala 173:46] + dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dma @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.bits.unsign @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.store <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.load <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dword @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.word <= lsu_lsc_ctl.io.lsu_pkt_d.bits.word @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.half <= lsu_lsc_ctl.io.lsu_pkt_d.bits.half @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.by <= lsu_lsc_ctl.io.lsu_pkt_d.bits.by @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_d.bits.stack @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.bits.fast_int @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 176:46] + dccm_ctl.io.addr_in_dccm_d <= lsu_lsc_ctl.io.addr_in_dccm_d @[lsu.scala 177:46] + dccm_ctl.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 178:46] + dccm_ctl.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 179:46] + dccm_ctl.io.addr_in_pic_d <= lsu_lsc_ctl.io.addr_in_pic_d @[lsu.scala 180:46] + dccm_ctl.io.addr_in_pic_m <= lsu_lsc_ctl.io.addr_in_pic_m @[lsu.scala 181:46] + dccm_ctl.io.addr_in_pic_r <= lsu_lsc_ctl.io.addr_in_pic_r @[lsu.scala 182:46] + dccm_ctl.io.lsu_raw_fwd_lo_r <= lsu_raw_fwd_lo_r @[lsu.scala 183:46] + dccm_ctl.io.lsu_raw_fwd_hi_r <= lsu_raw_fwd_hi_r @[lsu.scala 184:46] + dccm_ctl.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 185:46] + dccm_ctl.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 186:46] + node _T_76 = bits(lsu_lsc_ctl.io.lsu_addr_m, 15, 0) @[lsu.scala 187:74] + dccm_ctl.io.lsu_addr_m <= _T_76 @[lsu.scala 187:46] + dccm_ctl.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 188:46] + node _T_77 = bits(lsu_lsc_ctl.io.end_addr_d, 15, 0) @[lsu.scala 189:74] + dccm_ctl.io.end_addr_d <= _T_77 @[lsu.scala 189:46] + node _T_78 = bits(lsu_lsc_ctl.io.end_addr_m, 15, 0) @[lsu.scala 190:74] + dccm_ctl.io.end_addr_m <= _T_78 @[lsu.scala 190:46] + node _T_79 = bits(lsu_lsc_ctl.io.end_addr_r, 15, 0) @[lsu.scala 191:74] + dccm_ctl.io.end_addr_r <= _T_79 @[lsu.scala 191:46] + dccm_ctl.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 192:46] + dccm_ctl.io.stbuf_addr_any <= stbuf.io.stbuf_addr_any @[lsu.scala 193:46] + dccm_ctl.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 194:46] + dccm_ctl.io.stbuf_ecc_any <= ecc.io.stbuf_ecc_any @[lsu.scala 195:46] + dccm_ctl.io.stbuf_fwddata_hi_m <= stbuf.io.stbuf_fwddata_hi_m @[lsu.scala 196:46] + dccm_ctl.io.stbuf_fwddata_lo_m <= stbuf.io.stbuf_fwddata_lo_m @[lsu.scala 197:46] + dccm_ctl.io.stbuf_fwdbyteen_lo_m <= stbuf.io.stbuf_fwdbyteen_lo_m @[lsu.scala 198:46] + dccm_ctl.io.stbuf_fwdbyteen_hi_m <= stbuf.io.stbuf_fwdbyteen_hi_m @[lsu.scala 199:46] + dccm_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[lsu.scala 200:46] + dccm_ctl.io.single_ecc_error_hi_r <= ecc.io.single_ecc_error_hi_r @[lsu.scala 201:46] + dccm_ctl.io.single_ecc_error_lo_r <= ecc.io.single_ecc_error_lo_r @[lsu.scala 202:46] + dccm_ctl.io.sec_data_hi_r <= ecc.io.sec_data_hi_r @[lsu.scala 203:46] + dccm_ctl.io.sec_data_lo_r <= ecc.io.sec_data_lo_r @[lsu.scala 204:46] + dccm_ctl.io.sec_data_hi_r_ff <= ecc.io.sec_data_hi_r_ff @[lsu.scala 205:46] + dccm_ctl.io.sec_data_lo_r_ff <= ecc.io.sec_data_lo_r_ff @[lsu.scala 206:46] + dccm_ctl.io.sec_data_ecc_hi_r_ff <= ecc.io.sec_data_ecc_hi_r_ff @[lsu.scala 207:46] + dccm_ctl.io.sec_data_ecc_lo_r_ff <= ecc.io.sec_data_ecc_lo_r_ff @[lsu.scala 208:46] + dccm_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[lsu.scala 209:46] + dccm_ctl.io.sec_data_hi_m <= ecc.io.sec_data_hi_m @[lsu.scala 210:46] + dccm_ctl.io.sec_data_lo_m <= ecc.io.sec_data_lo_m @[lsu.scala 211:46] + dccm_ctl.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[lsu.scala 212:46] + dccm_ctl.io.dma_dccm_wen <= dma_dccm_wen @[lsu.scala 213:46] + dccm_ctl.io.dma_pic_wen <= dma_pic_wen @[lsu.scala 214:46] + dccm_ctl.io.dma_mem_tag_m <= dma_mem_tag_m @[lsu.scala 215:46] + dccm_ctl.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[lsu.scala 216:46] + dccm_ctl.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[lsu.scala 217:46] + dccm_ctl.io.dma_dccm_wdata_ecc_hi <= ecc.io.dma_dccm_wdata_ecc_hi @[lsu.scala 218:46] + dccm_ctl.io.dma_dccm_wdata_ecc_lo <= ecc.io.dma_dccm_wdata_ecc_lo @[lsu.scala 219:46] + dccm_ctl.io.scan_mode <= io.scan_mode @[lsu.scala 220:46] + io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rdata @[lsu.scala 222:27] + io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rtag @[lsu.scala 222:27] + io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_ecc_error @[lsu.scala 222:27] + io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rvalid @[lsu.scala 222:27] + dccm_ctl.io.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[lsu.scala 222:27] + dccm_ctl.io.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[lsu.scala 222:27] + dccm_ctl.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[lsu.scala 223:11] + dccm_ctl.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[lsu.scala 223:11] + io.dccm.wr_data_hi <= dccm_ctl.io.dccm.wr_data_hi @[lsu.scala 223:11] + io.dccm.wr_data_lo <= dccm_ctl.io.dccm.wr_data_lo @[lsu.scala 223:11] + io.dccm.rd_addr_hi <= dccm_ctl.io.dccm.rd_addr_hi @[lsu.scala 223:11] + io.dccm.rd_addr_lo <= dccm_ctl.io.dccm.rd_addr_lo @[lsu.scala 223:11] + io.dccm.wr_addr_hi <= dccm_ctl.io.dccm.wr_addr_hi @[lsu.scala 223:11] + io.dccm.wr_addr_lo <= dccm_ctl.io.dccm.wr_addr_lo @[lsu.scala 223:11] + io.dccm.rden <= dccm_ctl.io.dccm.rden @[lsu.scala 223:11] + io.dccm.wren <= dccm_ctl.io.dccm.wren @[lsu.scala 223:11] + dccm_ctl.io.lsu_pic.picm_rd_data <= io.lsu_pic.picm_rd_data @[lsu.scala 224:14] + io.lsu_pic.picm_wr_data <= dccm_ctl.io.lsu_pic.picm_wr_data @[lsu.scala 224:14] + io.lsu_pic.picm_wraddr <= dccm_ctl.io.lsu_pic.picm_wraddr @[lsu.scala 224:14] + io.lsu_pic.picm_rdaddr <= dccm_ctl.io.lsu_pic.picm_rdaddr @[lsu.scala 224:14] + io.lsu_pic.picm_mken <= dccm_ctl.io.lsu_pic.picm_mken @[lsu.scala 224:14] + io.lsu_pic.picm_rden <= dccm_ctl.io.lsu_pic.picm_rden @[lsu.scala 224:14] + io.lsu_pic.picm_wren <= dccm_ctl.io.lsu_pic.picm_wren @[lsu.scala 224:14] + node _T_80 = bits(lsu_lsc_ctl.io.lsu_addr_d, 2, 2) @[lsu.scala 227:78] + node _T_81 = bits(lsu_lsc_ctl.io.end_addr_d, 2, 2) @[lsu.scala 227:111] + node _T_82 = neq(_T_80, _T_81) @[lsu.scala 227:82] + stbuf.io.ldst_dual_d <= _T_82 @[lsu.scala 227:50] + node _T_83 = bits(lsu_lsc_ctl.io.lsu_addr_m, 2, 2) @[lsu.scala 228:78] + node _T_84 = bits(lsu_lsc_ctl.io.end_addr_m, 2, 2) @[lsu.scala 228:111] + node _T_85 = neq(_T_83, _T_84) @[lsu.scala 228:82] + stbuf.io.ldst_dual_m <= _T_85 @[lsu.scala 228:50] + node _T_86 = bits(lsu_lsc_ctl.io.lsu_addr_r, 2, 2) @[lsu.scala 229:78] + node _T_87 = bits(lsu_lsc_ctl.io.end_addr_r, 2, 2) @[lsu.scala 229:111] + node _T_88 = neq(_T_86, _T_87) @[lsu.scala 229:82] + stbuf.io.ldst_dual_r <= _T_88 @[lsu.scala 229:50] + stbuf.io.lsu_stbuf_c1_clk <= clkdomain.io.lsu_stbuf_c1_clk @[lsu.scala 230:54] + stbuf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 231:54] + stbuf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 232:48] + stbuf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 233:48] + stbuf.io.store_stbuf_reqvld_r <= store_stbuf_reqvld_r @[lsu.scala 234:48] + stbuf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 235:49] + stbuf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 236:49] + stbuf.io.store_data_hi_r <= dccm_ctl.io.store_data_hi_r @[lsu.scala 237:62] + stbuf.io.store_data_lo_r <= dccm_ctl.io.store_data_lo_r @[lsu.scala 238:62] + stbuf.io.store_datafn_hi_r <= dccm_ctl.io.store_datafn_hi_r @[lsu.scala 239:49] + stbuf.io.store_datafn_lo_r <= dccm_ctl.io.store_datafn_lo_r @[lsu.scala 240:56] + stbuf.io.lsu_stbuf_commit_any <= dccm_ctl.io.lsu_stbuf_commit_any @[lsu.scala 241:52] + stbuf.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 242:64] + stbuf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 243:64] + stbuf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 244:64] + stbuf.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[lsu.scala 245:64] + stbuf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 246:64] + stbuf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 247:64] + stbuf.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 248:49] + stbuf.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 249:56] + stbuf.io.lsu_cmpen_m <= lsu_cmpen_m @[lsu.scala 250:54] + stbuf.io.scan_mode <= io.scan_mode @[lsu.scala 251:49] + ecc.io.clk_override <= io.clk_override @[lsu.scala 255:50] + ecc.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 256:52] + ecc.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 257:52] + ecc.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 258:52] + ecc.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 259:54] + ecc.io.dec_tlu_core_ecc_disable <= io.dec_tlu_core_ecc_disable @[lsu.scala 260:50] + ecc.io.lsu_dccm_rden_r <= dccm_ctl.io.lsu_dccm_rden_r @[lsu.scala 261:56] + ecc.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 262:50] + ecc.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 263:58] + ecc.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 264:58] + ecc.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 265:58] + ecc.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 266:58] + ecc.io.dccm_rdata_hi_r <= dccm_ctl.io.dccm_rdata_hi_r @[lsu.scala 267:54] + ecc.io.dccm_rdata_lo_r <= dccm_ctl.io.dccm_rdata_lo_r @[lsu.scala 268:54] + ecc.io.dccm_rdata_hi_m <= dccm_ctl.io.dccm_rdata_hi_m @[lsu.scala 269:54] + ecc.io.dccm_rdata_lo_m <= dccm_ctl.io.dccm_rdata_lo_m @[lsu.scala 270:54] + ecc.io.dccm_data_ecc_hi_r <= dccm_ctl.io.dccm_data_ecc_hi_r @[lsu.scala 271:50] + ecc.io.dccm_data_ecc_lo_r <= dccm_ctl.io.dccm_data_ecc_lo_r @[lsu.scala 272:50] + ecc.io.dccm_data_ecc_hi_m <= dccm_ctl.io.dccm_data_ecc_hi_m @[lsu.scala 273:50] + ecc.io.dccm_data_ecc_lo_m <= dccm_ctl.io.dccm_data_ecc_lo_m @[lsu.scala 274:50] + ecc.io.ld_single_ecc_error_r <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 275:50] + ecc.io.ld_single_ecc_error_r_ff <= dccm_ctl.io.ld_single_ecc_error_r_ff @[lsu.scala 276:50] + ecc.io.lsu_dccm_rden_m <= dccm_ctl.io.lsu_dccm_rden_m @[lsu.scala 277:50] + ecc.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 278:50] + ecc.io.dma_dccm_wen <= dma_dccm_wen @[lsu.scala 279:50] + ecc.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[lsu.scala 280:50] + ecc.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[lsu.scala 281:50] + ecc.io.scan_mode <= io.scan_mode @[lsu.scala 282:50] + trigger.io.trigger_pkt_any[0].tdata2 <= io.trigger_pkt_any[0].tdata2 @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].m <= io.trigger_pkt_any[0].m @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].execute <= io.trigger_pkt_any[0].execute @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].load <= io.trigger_pkt_any[0].load @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].store <= io.trigger_pkt_any[0].store @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].match_pkt <= io.trigger_pkt_any[0].match_pkt @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].select <= io.trigger_pkt_any[0].select @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].tdata2 <= io.trigger_pkt_any[1].tdata2 @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].m <= io.trigger_pkt_any[1].m @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].execute <= io.trigger_pkt_any[1].execute @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].load <= io.trigger_pkt_any[1].load @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].store <= io.trigger_pkt_any[1].store @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].match_pkt <= io.trigger_pkt_any[1].match_pkt @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].select <= io.trigger_pkt_any[1].select @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].tdata2 <= io.trigger_pkt_any[2].tdata2 @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].m <= io.trigger_pkt_any[2].m @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].execute <= io.trigger_pkt_any[2].execute @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].load <= io.trigger_pkt_any[2].load @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].store <= io.trigger_pkt_any[2].store @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].match_pkt <= io.trigger_pkt_any[2].match_pkt @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].select <= io.trigger_pkt_any[2].select @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].tdata2 <= io.trigger_pkt_any[3].tdata2 @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].m <= io.trigger_pkt_any[3].m @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].execute <= io.trigger_pkt_any[3].execute @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].load <= io.trigger_pkt_any[3].load @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].store <= io.trigger_pkt_any[3].store @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].match_pkt <= io.trigger_pkt_any[3].match_pkt @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].select <= io.trigger_pkt_any[3].select @[lsu.scala 286:50] + trigger.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 287:50] + trigger.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 288:50] + trigger.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[lsu.scala 289:50] + io.lsu_trigger_match_m <= trigger.io.lsu_trigger_match_m @[lsu.scala 291:50] + clkdomain.io.active_clk <= io.active_clk @[lsu.scala 295:50] + clkdomain.io.clk_override <= io.clk_override @[lsu.scala 296:50] + clkdomain.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu.scala 297:50] + clkdomain.io.dma_dccm_req <= io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[lsu.scala 298:50] + clkdomain.io.ldst_stbuf_reqvld_r <= stbuf.io.ldst_stbuf_reqvld_r @[lsu.scala 299:50] + clkdomain.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 300:50] + clkdomain.io.stbuf_reqvld_flushed_any <= stbuf.io.stbuf_reqvld_flushed_any @[lsu.scala 301:50] + clkdomain.io.lsu_busreq_r <= bus_intf.io.lsu_busreq_r @[lsu.scala 302:50] + clkdomain.io.lsu_bus_buffer_pend_any <= bus_intf.io.lsu_bus_buffer_pend_any @[lsu.scala 303:50] + clkdomain.io.lsu_bus_buffer_empty_any <= bus_intf.io.lsu_bus_buffer_empty_any @[lsu.scala 304:50] + clkdomain.io.lsu_stbuf_empty_any <= stbuf.io.lsu_stbuf_empty_any @[lsu.scala 305:50] + clkdomain.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 306:50] + clkdomain.io.lsu_p.bits.store_data_bypass_m <= io.lsu_p.bits.store_data_bypass_m @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.load_ldst_bypass_d <= io.lsu_p.bits.load_ldst_bypass_d @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.store_data_bypass_d <= io.lsu_p.bits.store_data_bypass_d @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.dma <= io.lsu_p.bits.dma @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.unsign <= io.lsu_p.bits.unsign @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.store <= io.lsu_p.bits.store @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.load <= io.lsu_p.bits.load @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.dword <= io.lsu_p.bits.dword @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.word <= io.lsu_p.bits.word @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.half <= io.lsu_p.bits.half @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.by <= io.lsu_p.bits.by @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.stack <= io.lsu_p.bits.stack @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.fast_int <= io.lsu_p.bits.fast_int @[lsu.scala 307:50] + clkdomain.io.lsu_p.valid <= io.lsu_p.valid @[lsu.scala 307:50] + clkdomain.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dma @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.bits.unsign @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.store <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.load <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dword @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.word <= lsu_lsc_ctl.io.lsu_pkt_d.bits.word @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.half <= lsu_lsc_ctl.io.lsu_pkt_d.bits.half @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.by <= lsu_lsc_ctl.io.lsu_pkt_d.bits.by @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_d.bits.stack @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.bits.fast_int @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 310:50] + clkdomain.io.scan_mode <= io.scan_mode @[lsu.scala 311:50] + bus_intf.io.scan_mode <= io.scan_mode @[lsu.scala 315:49] + io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu.scala 316:26] + bus_intf.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu.scala 316:26] + bus_intf.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu.scala 316:26] + bus_intf.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_error @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu.scala 316:26] + bus_intf.io.clk_override <= io.clk_override @[lsu.scala 317:49] + bus_intf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 318:49] + bus_intf.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 319:49] + bus_intf.io.lsu_busm_clken <= lsu_busm_clken @[lsu.scala 320:49] + bus_intf.io.lsu_bus_obuf_c1_clken <= lsu_bus_obuf_c1_clken @[lsu.scala 321:49] + bus_intf.io.lsu_bus_ibuf_c1_clk <= clkdomain.io.lsu_bus_ibuf_c1_clk @[lsu.scala 322:49] + bus_intf.io.lsu_bus_obuf_c1_clk <= clkdomain.io.lsu_bus_obuf_c1_clk @[lsu.scala 323:49] + bus_intf.io.lsu_bus_buf_c1_clk <= clkdomain.io.lsu_bus_buf_c1_clk @[lsu.scala 324:49] + bus_intf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 325:49] + bus_intf.io.active_clk <= io.active_clk @[lsu.scala 326:49] + bus_intf.io.lsu_busm_clk <= clkdomain.io.lsu_busm_clk @[lsu.scala 327:49] + bus_intf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 328:49] + bus_intf.io.lsu_busreq_m <= lsu_busreq_m @[lsu.scala 329:49] + node _T_89 = bits(lsu_lsc_ctl.io.lsu_addr_d, 2, 2) @[lsu.scala 330:77] + node _T_90 = bits(lsu_lsc_ctl.io.end_addr_d, 2, 2) @[lsu.scala 330:110] + node _T_91 = neq(_T_89, _T_90) @[lsu.scala 330:81] + bus_intf.io.ldst_dual_d <= _T_91 @[lsu.scala 330:49] + node _T_92 = bits(lsu_lsc_ctl.io.lsu_addr_m, 2, 2) @[lsu.scala 331:77] + node _T_93 = bits(lsu_lsc_ctl.io.end_addr_m, 2, 2) @[lsu.scala 331:110] + node _T_94 = neq(_T_92, _T_93) @[lsu.scala 331:81] + bus_intf.io.ldst_dual_m <= _T_94 @[lsu.scala 331:49] + node _T_95 = bits(lsu_lsc_ctl.io.lsu_addr_r, 2, 2) @[lsu.scala 332:77] + node _T_96 = bits(lsu_lsc_ctl.io.end_addr_r, 2, 2) @[lsu.scala 332:110] + node _T_97 = neq(_T_95, _T_96) @[lsu.scala 332:81] + bus_intf.io.ldst_dual_r <= _T_97 @[lsu.scala 332:49] + node _T_98 = and(lsu_lsc_ctl.io.addr_external_m, lsu_lsc_ctl.io.lsu_pkt_m.valid) @[lsu.scala 333:119] + node _T_99 = bits(_T_98, 0, 0) @[Bitwise.scala 72:15] + node _T_100 = mux(_T_99, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_101 = and(lsu_lsc_ctl.io.lsu_addr_m, _T_100) @[lsu.scala 333:78] + bus_intf.io.lsu_addr_m <= _T_101 @[lsu.scala 333:49] + node _T_102 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15] + node _T_103 = mux(_T_102, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_104 = and(lsu_lsc_ctl.io.lsu_addr_r, _T_103) @[lsu.scala 334:78] + bus_intf.io.lsu_addr_r <= _T_104 @[lsu.scala 334:49] + node _T_105 = and(lsu_lsc_ctl.io.addr_external_m, lsu_lsc_ctl.io.lsu_pkt_m.valid) @[lsu.scala 335:119] + node _T_106 = bits(_T_105, 0, 0) @[Bitwise.scala 72:15] + node _T_107 = mux(_T_106, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_108 = and(lsu_lsc_ctl.io.end_addr_m, _T_107) @[lsu.scala 335:78] + bus_intf.io.end_addr_m <= _T_108 @[lsu.scala 335:49] + node _T_109 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15] + node _T_110 = mux(_T_109, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_111 = and(lsu_lsc_ctl.io.end_addr_r, _T_110) @[lsu.scala 336:78] + bus_intf.io.end_addr_r <= _T_111 @[lsu.scala 336:49] + node _T_112 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15] + node _T_113 = mux(_T_112, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_114 = and(dccm_ctl.io.store_data_r, _T_113) @[lsu.scala 337:77] + bus_intf.io.store_data_r <= _T_114 @[lsu.scala 337:49] + bus_intf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 339:49] + bus_intf.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu.scala 340:49] + bus_intf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 341:49] + bus_intf.io.is_sideeffects_m <= lsu_lsc_ctl.io.is_sideeffects_m @[lsu.scala 342:49] + bus_intf.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 343:49] + bus_intf.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 344:49] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu.scala 346:27] + io.lsu_nonblock_load_data <= bus_intf.io.lsu_nonblock_load_data @[lsu.scala 347:29] + lsu_busreq_r <= bus_intf.io.lsu_busreq_r @[lsu.scala 348:16] + bus_intf.io.axi.r.bits.last <= io.axi.r.bits.last @[lsu.scala 349:49] + bus_intf.io.axi.r.bits.resp <= io.axi.r.bits.resp @[lsu.scala 349:49] + bus_intf.io.axi.r.bits.data <= io.axi.r.bits.data @[lsu.scala 349:49] + bus_intf.io.axi.r.bits.id <= io.axi.r.bits.id @[lsu.scala 349:49] + bus_intf.io.axi.r.valid <= io.axi.r.valid @[lsu.scala 349:49] + io.axi.r.ready <= bus_intf.io.axi.r.ready @[lsu.scala 349:49] + io.axi.ar.bits.qos <= bus_intf.io.axi.ar.bits.qos @[lsu.scala 349:49] + io.axi.ar.bits.prot <= bus_intf.io.axi.ar.bits.prot @[lsu.scala 349:49] + io.axi.ar.bits.cache <= bus_intf.io.axi.ar.bits.cache @[lsu.scala 349:49] + io.axi.ar.bits.lock <= bus_intf.io.axi.ar.bits.lock @[lsu.scala 349:49] + io.axi.ar.bits.burst <= bus_intf.io.axi.ar.bits.burst @[lsu.scala 349:49] + io.axi.ar.bits.size <= bus_intf.io.axi.ar.bits.size @[lsu.scala 349:49] + io.axi.ar.bits.len <= bus_intf.io.axi.ar.bits.len @[lsu.scala 349:49] + io.axi.ar.bits.region <= bus_intf.io.axi.ar.bits.region @[lsu.scala 349:49] + io.axi.ar.bits.addr <= bus_intf.io.axi.ar.bits.addr @[lsu.scala 349:49] + io.axi.ar.bits.id <= bus_intf.io.axi.ar.bits.id @[lsu.scala 349:49] + io.axi.ar.valid <= bus_intf.io.axi.ar.valid @[lsu.scala 349:49] + bus_intf.io.axi.ar.ready <= io.axi.ar.ready @[lsu.scala 349:49] + bus_intf.io.axi.b.bits.id <= io.axi.b.bits.id @[lsu.scala 349:49] + bus_intf.io.axi.b.bits.resp <= io.axi.b.bits.resp @[lsu.scala 349:49] + bus_intf.io.axi.b.valid <= io.axi.b.valid @[lsu.scala 349:49] + io.axi.b.ready <= bus_intf.io.axi.b.ready @[lsu.scala 349:49] + io.axi.w.bits.last <= bus_intf.io.axi.w.bits.last @[lsu.scala 349:49] + io.axi.w.bits.strb <= bus_intf.io.axi.w.bits.strb @[lsu.scala 349:49] + io.axi.w.bits.data <= bus_intf.io.axi.w.bits.data @[lsu.scala 349:49] + io.axi.w.valid <= bus_intf.io.axi.w.valid @[lsu.scala 349:49] + bus_intf.io.axi.w.ready <= io.axi.w.ready @[lsu.scala 349:49] + io.axi.aw.bits.qos <= bus_intf.io.axi.aw.bits.qos @[lsu.scala 349:49] + io.axi.aw.bits.prot <= bus_intf.io.axi.aw.bits.prot @[lsu.scala 349:49] + io.axi.aw.bits.cache <= bus_intf.io.axi.aw.bits.cache @[lsu.scala 349:49] + io.axi.aw.bits.lock <= bus_intf.io.axi.aw.bits.lock @[lsu.scala 349:49] + io.axi.aw.bits.burst <= bus_intf.io.axi.aw.bits.burst @[lsu.scala 349:49] + io.axi.aw.bits.size <= bus_intf.io.axi.aw.bits.size @[lsu.scala 349:49] + io.axi.aw.bits.len <= bus_intf.io.axi.aw.bits.len @[lsu.scala 349:49] + io.axi.aw.bits.region <= bus_intf.io.axi.aw.bits.region @[lsu.scala 349:49] + io.axi.aw.bits.addr <= bus_intf.io.axi.aw.bits.addr @[lsu.scala 349:49] + io.axi.aw.bits.id <= bus_intf.io.axi.aw.bits.id @[lsu.scala 349:49] + io.axi.aw.valid <= bus_intf.io.axi.aw.valid @[lsu.scala 349:49] + bus_intf.io.axi.aw.ready <= io.axi.aw.ready @[lsu.scala 349:49] + bus_intf.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 350:49] + reg _T_115 : UInt, clkdomain.io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 352:67] + _T_115 <= io.lsu_dma.dma_mem_tag @[lsu.scala 352:67] + dma_mem_tag_m <= _T_115 @[lsu.scala 352:57] + reg _T_116 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 353:67] + _T_116 <= lsu_raw_fwd_hi_m @[lsu.scala 353:67] + lsu_raw_fwd_hi_r <= _T_116 @[lsu.scala 353:57] + reg _T_117 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 354:67] + _T_117 <= lsu_raw_fwd_lo_m @[lsu.scala 354:67] + lsu_raw_fwd_lo_r <= _T_117 @[lsu.scala 354:57] + diff --git a/lsu.v b/lsu.v new file mode 100644 index 00000000..2d1d7bc1 --- /dev/null +++ b/lsu.v @@ -0,0 +1,11116 @@ +module lsu_addrcheck( + input reset, + input io_lsu_c2_m_clk, + input [31:0] io_start_addr_d, + input [31:0] io_end_addr_d, + input io_lsu_pkt_d_valid, + input io_lsu_pkt_d_bits_fast_int, + input io_lsu_pkt_d_bits_by, + input io_lsu_pkt_d_bits_half, + input io_lsu_pkt_d_bits_word, + input io_lsu_pkt_d_bits_load, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_d_bits_dma, + input [31:0] io_dec_tlu_mrac_ff, + input [3:0] io_rs1_region_d, + output io_is_sideeffects_m, + output io_addr_in_dccm_d, + output io_addr_in_pic_d, + output io_addr_external_d, + output io_access_fault_d, + output io_misaligned_fault_d, + output [3:0] io_exc_mscause_d, + output io_fir_dccm_access_error_d, + output io_fir_nondccm_access_error_d +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 370:49] + wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 375:39] + wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 370:49] + wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 375:39] + wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45] + wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 375:39] + wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 375:39] + wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60] + wire _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:55] + wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:91] + wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58] + wire [31:0] _T_26 = io_dec_tlu_mrac_ff >> csr_idx; // @[lsu_addrcheck.scala 61:50] + wire _T_29 = start_addr_dccm_or_pic | addr_in_iccm; // @[lsu_addrcheck.scala 61:121] + wire _T_30 = ~_T_29; // @[lsu_addrcheck.scala 61:62] + wire _T_31 = _T_26[0] & _T_30; // @[lsu_addrcheck.scala 61:60] + wire _T_32 = _T_31 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 61:137] + wire _T_33 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[lsu_addrcheck.scala 61:185] + wire is_sideeffects_d = _T_32 & _T_33; // @[lsu_addrcheck.scala 61:158] + wire _T_35 = io_start_addr_d[1:0] == 2'h0; // @[lsu_addrcheck.scala 62:80] + wire _T_36 = io_lsu_pkt_d_bits_word & _T_35; // @[lsu_addrcheck.scala 62:56] + wire _T_38 = ~io_start_addr_d[0]; // @[lsu_addrcheck.scala 62:138] + wire _T_39 = io_lsu_pkt_d_bits_half & _T_38; // @[lsu_addrcheck.scala 62:116] + wire _T_40 = _T_36 | _T_39; // @[lsu_addrcheck.scala 62:90] + wire is_aligned_d = _T_40 | io_lsu_pkt_d_bits_by; // @[lsu_addrcheck.scala 62:148] + wire [31:0] _T_51 = io_start_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 67:56] + wire _T_53 = _T_51 == 32'h7fffffff; // @[lsu_addrcheck.scala 67:88] + wire [31:0] _T_56 = io_start_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 68:56] + wire _T_58 = _T_56 == 32'hffffffff; // @[lsu_addrcheck.scala 68:88] + wire _T_60 = _T_53 | _T_58; // @[lsu_addrcheck.scala 67:153] + wire [31:0] _T_62 = io_start_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 69:56] + wire _T_64 = _T_62 == 32'hbfffffff; // @[lsu_addrcheck.scala 69:88] + wire _T_66 = _T_60 | _T_64; // @[lsu_addrcheck.scala 68:153] + wire [31:0] _T_68 = io_start_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 70:56] + wire _T_70 = _T_68 == 32'h8fffffff; // @[lsu_addrcheck.scala 70:88] + wire _T_72 = _T_66 | _T_70; // @[lsu_addrcheck.scala 69:153] + wire [31:0] _T_98 = io_end_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 76:57] + wire _T_100 = _T_98 == 32'h7fffffff; // @[lsu_addrcheck.scala 76:89] + wire [31:0] _T_103 = io_end_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 77:58] + wire _T_105 = _T_103 == 32'hffffffff; // @[lsu_addrcheck.scala 77:90] + wire _T_107 = _T_100 | _T_105; // @[lsu_addrcheck.scala 76:154] + wire [31:0] _T_109 = io_end_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 78:58] + wire _T_111 = _T_109 == 32'hbfffffff; // @[lsu_addrcheck.scala 78:90] + wire _T_113 = _T_107 | _T_111; // @[lsu_addrcheck.scala 77:155] + wire [31:0] _T_115 = io_end_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 79:58] + wire _T_117 = _T_115 == 32'h8fffffff; // @[lsu_addrcheck.scala 79:90] + wire _T_119 = _T_113 | _T_117; // @[lsu_addrcheck.scala 78:155] + wire non_dccm_access_ok = _T_72 & _T_119; // @[lsu_addrcheck.scala 75:7] + wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[lsu_addrcheck.scala 85:57] + wire _T_146 = io_start_addr_d[1:0] != 2'h0; // @[lsu_addrcheck.scala 86:76] + wire _T_147 = ~io_lsu_pkt_d_bits_word; // @[lsu_addrcheck.scala 86:92] + wire _T_148 = _T_146 | _T_147; // @[lsu_addrcheck.scala 86:90] + wire picm_access_fault_d = io_addr_in_pic_d & _T_148; // @[lsu_addrcheck.scala 86:51] + wire _T_149 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[lsu_addrcheck.scala 91:87] + wire _T_150 = ~_T_149; // @[lsu_addrcheck.scala 91:64] + wire _T_151 = start_addr_in_dccm_region_d & _T_150; // @[lsu_addrcheck.scala 91:62] + wire _T_152 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[lsu_addrcheck.scala 93:57] + wire _T_153 = ~_T_152; // @[lsu_addrcheck.scala 93:36] + wire _T_154 = end_addr_in_dccm_region_d & _T_153; // @[lsu_addrcheck.scala 93:34] + wire _T_155 = _T_151 | _T_154; // @[lsu_addrcheck.scala 91:112] + wire _T_156 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 95:29] + wire _T_157 = _T_155 | _T_156; // @[lsu_addrcheck.scala 93:85] + wire _T_158 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 97:29] + wire unmapped_access_fault_d = _T_157 | _T_158; // @[lsu_addrcheck.scala 95:85] + wire _T_160 = ~start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 99:33] + wire _T_161 = ~non_dccm_access_ok; // @[lsu_addrcheck.scala 99:64] + wire mpu_access_fault_d = _T_160 & _T_161; // @[lsu_addrcheck.scala 99:62] + wire _T_163 = unmapped_access_fault_d | mpu_access_fault_d; // @[lsu_addrcheck.scala 111:49] + wire _T_164 = _T_163 | picm_access_fault_d; // @[lsu_addrcheck.scala 111:70] + wire _T_165 = _T_164 | regpred_access_fault_d; // @[lsu_addrcheck.scala 111:92] + wire _T_166 = _T_165 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 111:118] + wire _T_167 = ~io_lsu_pkt_d_bits_dma; // @[lsu_addrcheck.scala 111:141] + wire [3:0] _T_173 = picm_access_fault_d ? 4'h6 : 4'h0; // @[lsu_addrcheck.scala 112:164] + wire [3:0] _T_174 = regpred_access_fault_d ? 4'h5 : _T_173; // @[lsu_addrcheck.scala 112:120] + wire [3:0] _T_175 = mpu_access_fault_d ? 4'h3 : _T_174; // @[lsu_addrcheck.scala 112:80] + wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_175; // @[lsu_addrcheck.scala 112:35] + wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[lsu_addrcheck.scala 113:61] + wire _T_178 = ~is_aligned_d; // @[lsu_addrcheck.scala 114:59] + wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_178; // @[lsu_addrcheck.scala 114:57] + wire _T_179 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[lsu_addrcheck.scala 115:90] + wire _T_180 = regcross_misaligned_fault_d | _T_179; // @[lsu_addrcheck.scala 115:57] + wire _T_181 = _T_180 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 115:113] + wire [3:0] _T_185 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[lsu_addrcheck.scala 116:80] + wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_185; // @[lsu_addrcheck.scala 116:39] + wire _T_190 = ~start_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:66] + wire _T_191 = start_addr_in_dccm_region_d & _T_190; // @[lsu_addrcheck.scala 118:64] + wire _T_192 = ~end_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:120] + wire _T_193 = end_addr_in_dccm_region_d & _T_192; // @[lsu_addrcheck.scala 118:118] + wire _T_194 = _T_191 | _T_193; // @[lsu_addrcheck.scala 118:88] + wire _T_195 = _T_194 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 118:142] + wire _T_197 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 119:66] + wire _T_198 = ~_T_197; // @[lsu_addrcheck.scala 119:36] + wire _T_199 = _T_198 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 119:95] + reg _T_201; // @[lsu_addrcheck.scala 121:60] + assign io_is_sideeffects_m = _T_201; // @[lsu_addrcheck.scala 121:50] + assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 56:32] + assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 57:32] + assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[lsu_addrcheck.scala 59:30] + assign io_access_fault_d = _T_166 & _T_167; // @[lsu_addrcheck.scala 111:21] + assign io_misaligned_fault_d = _T_181 & _T_167; // @[lsu_addrcheck.scala 115:25] + assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[lsu_addrcheck.scala 117:21] + assign io_fir_dccm_access_error_d = _T_195 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 118:31] + assign io_fir_nondccm_access_error_d = _T_199 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 119:33] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_201 = _RAND_0[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_201 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_201 <= 1'h0; + end else begin + _T_201 <= _T_32 & _T_33; + end + end +endmodule +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module lsu_lsc_ctl( + input clock, + input reset, + input io_clk_override, + input io_lsu_c1_m_clk, + input io_lsu_c1_r_clk, + input io_lsu_c2_m_clk, + input io_lsu_c2_r_clk, + input io_lsu_store_c1_m_clk, + input [31:0] io_lsu_ld_data_corr_r, + input io_lsu_single_ecc_error_r, + input io_lsu_double_ecc_error_r, + input [31:0] io_lsu_ld_data_m, + input io_lsu_single_ecc_error_m, + input io_lsu_double_ecc_error_m, + input io_flush_m_up, + input io_flush_r, + input io_ldst_dual_d, + input [31:0] io_lsu_exu_exu_lsu_rs1_d, + input [31:0] io_lsu_exu_exu_lsu_rs2_d, + output [31:0] io_lsu_exu_lsu_result_m, + input io_lsu_p_valid, + input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_by, + input io_lsu_p_bits_half, + input io_lsu_p_bits_word, + input io_lsu_p_bits_dword, + input io_lsu_p_bits_load, + input io_lsu_p_bits_store, + input io_lsu_p_bits_unsign, + input io_lsu_p_bits_dma, + input io_lsu_p_bits_store_data_bypass_d, + input io_lsu_p_bits_load_ldst_bypass_d, + input io_lsu_p_bits_store_data_bypass_m, + input io_dec_lsu_valid_raw_d, + input [11:0] io_dec_lsu_offset_d, + input [31:0] io_picm_mask_data_m, + input [31:0] io_bus_read_data_m, + output [31:0] io_lsu_result_corr_r, + output [31:0] io_lsu_addr_d, + output [31:0] io_lsu_addr_m, + output [31:0] io_lsu_addr_r, + output [31:0] io_end_addr_d, + output [31:0] io_end_addr_m, + output [31:0] io_end_addr_r, + output [31:0] io_store_data_m, + input [31:0] io_dec_tlu_mrac_ff, + output io_lsu_exc_m, + output io_is_sideeffects_m, + output io_lsu_commit_r, + output io_lsu_single_ecc_error_incr, + output io_lsu_error_pkt_r_valid, + output io_lsu_error_pkt_r_bits_single_ecc_error, + output io_lsu_error_pkt_r_bits_inst_type, + output io_lsu_error_pkt_r_bits_exc_type, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, + output [30:0] io_lsu_fir_addr, + output [1:0] io_lsu_fir_error, + output io_addr_in_dccm_d, + output io_addr_in_dccm_m, + output io_addr_in_dccm_r, + output io_addr_in_pic_d, + output io_addr_in_pic_m, + output io_addr_in_pic_r, + output io_addr_external_m, + input io_dma_lsc_ctl_dma_dccm_req, + input [31:0] io_dma_lsc_ctl_dma_mem_addr, + input [2:0] io_dma_lsc_ctl_dma_mem_sz, + input io_dma_lsc_ctl_dma_mem_write, + input [63:0] io_dma_lsc_ctl_dma_mem_wdata, + output io_lsu_pkt_d_valid, + output io_lsu_pkt_d_bits_fast_int, + output io_lsu_pkt_d_bits_by, + output io_lsu_pkt_d_bits_half, + output io_lsu_pkt_d_bits_word, + output io_lsu_pkt_d_bits_dword, + output io_lsu_pkt_d_bits_load, + output io_lsu_pkt_d_bits_store, + output io_lsu_pkt_d_bits_unsign, + output io_lsu_pkt_d_bits_dma, + output io_lsu_pkt_d_bits_store_data_bypass_d, + output io_lsu_pkt_d_bits_load_ldst_bypass_d, + output io_lsu_pkt_d_bits_store_data_bypass_m, + output io_lsu_pkt_m_valid, + output io_lsu_pkt_m_bits_fast_int, + output io_lsu_pkt_m_bits_by, + output io_lsu_pkt_m_bits_half, + output io_lsu_pkt_m_bits_word, + output io_lsu_pkt_m_bits_dword, + output io_lsu_pkt_m_bits_load, + output io_lsu_pkt_m_bits_store, + output io_lsu_pkt_m_bits_unsign, + output io_lsu_pkt_m_bits_dma, + output io_lsu_pkt_m_bits_store_data_bypass_m, + output io_lsu_pkt_r_valid, + output io_lsu_pkt_r_bits_by, + output io_lsu_pkt_r_bits_half, + output io_lsu_pkt_r_bits_word, + output io_lsu_pkt_r_bits_dword, + output io_lsu_pkt_r_bits_load, + output io_lsu_pkt_r_bits_store, + output io_lsu_pkt_r_bits_unsign, + output io_lsu_pkt_r_bits_dma +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; +`endif // RANDOMIZE_REG_INIT + wire addrcheck_reset; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_start_addr_d; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_end_addr_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 117:25] + wire [3:0] addrcheck_io_rs1_region_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_external_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_access_fault_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_misaligned_fault_d; // @[lsu_lsc_ctl.scala 117:25] + wire [3:0] addrcheck_io_exc_mscause_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_fir_dccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_fir_nondccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25] + wire rvclkhdr_io_clk; // @[lib.scala 417:23] + wire rvclkhdr_io_en; // @[lib.scala 417:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_lsu_exu_exu_lsu_rs1_d : io_dma_lsc_ctl_dma_mem_addr; // @[lsu_lsc_ctl.scala 99:28] + wire [11:0] _T_4 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] + wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_4; // @[lsu_lsc_ctl.scala 100:51] + wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_exu_lsu_result_m : lsu_rs1_d; // @[lsu_lsc_ctl.scala 103:28] + wire [12:0] _T_7 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58] + wire [12:0] _T_9 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _T_11 = _T_7 + _T_9; // @[lib.scala 92:39] + wire _T_14 = lsu_offset_d[11] ^ _T_11[12]; // @[lib.scala 93:46] + wire _T_15 = ~_T_14; // @[lib.scala 93:33] + wire [19:0] _T_17 = _T_15 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_19 = _T_17 & rs1_d[31:12]; // @[lib.scala 93:58] + wire _T_21 = ~lsu_offset_d[11]; // @[lib.scala 94:18] + wire _T_23 = _T_21 & _T_11[12]; // @[lib.scala 94:30] + wire [19:0] _T_25 = _T_23 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_28 = rs1_d[31:12] + 20'h1; // @[lib.scala 94:54] + wire [19:0] _T_29 = _T_25 & _T_28; // @[lib.scala 94:41] + wire [19:0] _T_30 = _T_19 | _T_29; // @[lib.scala 93:72] + wire _T_33 = ~_T_11[12]; // @[lib.scala 95:31] + wire _T_34 = lsu_offset_d[11] & _T_33; // @[lib.scala 95:29] + wire [19:0] _T_36 = _T_34 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_39 = rs1_d[31:12] - 20'h1; // @[lib.scala 95:54] + wire [19:0] _T_40 = _T_36 & _T_39; // @[lib.scala 95:41] + wire [19:0] _T_41 = _T_30 | _T_40; // @[lib.scala 94:61] + wire [2:0] _T_44 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_45 = _T_44 & 3'h1; // @[lsu_lsc_ctl.scala 108:58] + wire [2:0] _T_47 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_48 = _T_47 & 3'h3; // @[lsu_lsc_ctl.scala 109:40] + wire [2:0] _T_49 = _T_45 | _T_48; // @[lsu_lsc_ctl.scala 108:70] + wire [2:0] _T_51 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] addr_offset_d = _T_49 | _T_51; // @[lsu_lsc_ctl.scala 109:52] + wire [12:0] _T_55 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58] + wire [11:0] _T_58 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _GEN_9 = {{1'd0}, _T_58}; // @[lsu_lsc_ctl.scala 112:60] + wire [12:0] end_addr_offset_d = _T_55 + _GEN_9; // @[lsu_lsc_ctl.scala 112:60] + wire [18:0] _T_63 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_65 = {_T_63,end_addr_offset_d}; // @[Cat.scala 29:58] + reg access_fault_m; // @[lsu_lsc_ctl.scala 148:75] + reg misaligned_fault_m; // @[lsu_lsc_ctl.scala 149:75] + reg [3:0] exc_mscause_m; // @[lsu_lsc_ctl.scala 150:75] + reg fir_dccm_access_error_m; // @[lsu_lsc_ctl.scala 151:75] + reg fir_nondccm_access_error_m; // @[lsu_lsc_ctl.scala 152:75] + wire _T_70 = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:34] + wire _T_71 = ~io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 155:64] + wire _T_72 = io_lsu_single_ecc_error_r & _T_71; // @[lsu_lsc_ctl.scala 155:62] + wire _T_73 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 155:111] + wire _T_74 = _T_72 & _T_73; // @[lsu_lsc_ctl.scala 155:92] + wire _T_77 = _T_70 | io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 177:67] + wire _T_78 = _T_77 & io_lsu_pkt_m_valid; // @[lsu_lsc_ctl.scala 177:96] + wire _T_79 = ~io_lsu_pkt_m_bits_dma; // @[lsu_lsc_ctl.scala 177:119] + wire _T_80 = _T_78 & _T_79; // @[lsu_lsc_ctl.scala 177:117] + wire _T_81 = ~io_lsu_pkt_m_bits_fast_int; // @[lsu_lsc_ctl.scala 177:144] + wire _T_82 = _T_80 & _T_81; // @[lsu_lsc_ctl.scala 177:142] + wire _T_83 = ~io_flush_m_up; // @[lsu_lsc_ctl.scala 177:174] + wire lsu_error_pkt_m_valid = _T_82 & _T_83; // @[lsu_lsc_ctl.scala 177:172] + wire _T_85 = ~lsu_error_pkt_m_valid; // @[lsu_lsc_ctl.scala 178:75] + wire _T_86 = io_lsu_single_ecc_error_m & _T_85; // @[lsu_lsc_ctl.scala 178:73] + wire lsu_error_pkt_m_bits_single_ecc_error = _T_86 & _T_79; // @[lsu_lsc_ctl.scala 178:99] + wire lsu_error_pkt_m_bits_exc_type = ~misaligned_fault_m; // @[lsu_lsc_ctl.scala 180:46] + wire _T_91 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[lsu_lsc_ctl.scala 181:78] + wire _T_92 = ~access_fault_m; // @[lsu_lsc_ctl.scala 181:102] + wire _T_93 = _T_91 & _T_92; // @[lsu_lsc_ctl.scala 181:100] + wire _T_100 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 183:166] + wire _T_105 = lsu_error_pkt_m_valid | lsu_error_pkt_m_bits_single_ecc_error; // @[lsu_lsc_ctl.scala 184:73] + wire _T_106 = _T_105 | io_clk_override; // @[lsu_lsc_ctl.scala 184:113] + reg _T_110_bits_inst_type; // @[Reg.scala 27:20] + reg _T_110_bits_exc_type; // @[Reg.scala 27:20] + reg [3:0] _T_110_bits_mscause; // @[Reg.scala 27:20] + reg [31:0] _T_110_bits_addr; // @[Reg.scala 27:20] + reg _T_111; // @[lsu_lsc_ctl.scala 185:83] + reg _T_112; // @[lsu_lsc_ctl.scala 186:67] + reg [1:0] _T_113; // @[lsu_lsc_ctl.scala 187:75] + wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 195:30] + wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 196:62] + wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 197:62] + wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 198:62] + wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 199:62] + wire _T_125 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 212:64] + wire _T_126 = io_flush_m_up & _T_125; // @[lsu_lsc_ctl.scala 212:61] + wire _T_127 = ~_T_126; // @[lsu_lsc_ctl.scala 212:45] + wire _T_128 = io_lsu_p_valid & _T_127; // @[lsu_lsc_ctl.scala 212:43] + wire _T_130 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 213:68] + wire _T_131 = io_flush_m_up & _T_130; // @[lsu_lsc_ctl.scala 213:65] + wire _T_132 = ~_T_131; // @[lsu_lsc_ctl.scala 213:49] + wire _T_135 = io_flush_m_up & _T_79; // @[lsu_lsc_ctl.scala 214:65] + wire _T_136 = ~_T_135; // @[lsu_lsc_ctl.scala 214:49] + reg _T_139_bits_fast_int; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_by; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_half; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_word; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_dword; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_load; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_store; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_unsign; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_dma; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:65] + reg _T_141_bits_by; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_half; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_word; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_dword; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_load; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_store; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_unsign; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_dma; // @[lsu_lsc_ctl.scala 217:65] + reg _T_142; // @[lsu_lsc_ctl.scala 218:65] + reg _T_143; // @[lsu_lsc_ctl.scala 219:65] + wire [5:0] _T_146 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] + wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_146; // @[lsu_lsc_ctl.scala 221:66] + reg _T_154; // @[lsu_lsc_ctl.scala 224:48] + reg _T_156; // @[lsu_lsc_ctl.scala 224:110] + wire int_ = _T_154 != _T_156; // @[lsu_lsc_ctl.scala 224:72] + reg _T_158; // @[lsu_lsc_ctl.scala 225:48] + reg _T_160; // @[lsu_lsc_ctl.scala 225:110] + wire int1 = _T_158 != _T_160; // @[lsu_lsc_ctl.scala 225:72] + reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 226:72] + reg [31:0] _T_161; // @[lsu_lsc_ctl.scala 227:62] + reg [31:0] _T_162; // @[lsu_lsc_ctl.scala 228:62] + reg [28:0] end_addr_pre_m; // @[Reg.scala 27:20] + wire [28:0] _T_164 = int_ ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 229:27] + reg [2:0] _T_166; // @[lsu_lsc_ctl.scala 229:103] + reg [28:0] end_addr_pre_r; // @[Reg.scala 27:20] + wire [28:0] _T_169 = int1 ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 230:27] + reg [2:0] _T_171; // @[lsu_lsc_ctl.scala 230:104] + wire _T_174 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 231:69] + wire _T_175 = _T_174 | io_clk_override; // @[lsu_lsc_ctl.scala 231:87] + wire _T_179 = io_lsu_pkt_m_valid & int_; // @[lsu_lsc_ctl.scala 232:69] + wire _T_180 = _T_179 | io_clk_override; // @[lsu_lsc_ctl.scala 232:76] + reg _T_183; // @[lsu_lsc_ctl.scala 233:62] + reg _T_184; // @[lsu_lsc_ctl.scala 234:62] + reg _T_185; // @[lsu_lsc_ctl.scala 235:62] + reg _T_186; // @[lsu_lsc_ctl.scala 236:62] + reg _T_187; // @[lsu_lsc_ctl.scala 237:62] + reg addr_external_r; // @[lsu_lsc_ctl.scala 238:66] + wire _T_188 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 239:77] + reg [31:0] bus_read_data_r; // @[Reg.scala 27:20] + wire _T_191 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 246:68] + wire _T_192 = io_lsu_pkt_r_valid & _T_191; // @[lsu_lsc_ctl.scala 246:41] + wire _T_193 = ~io_flush_r; // @[lsu_lsc_ctl.scala 246:96] + wire _T_194 = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 246:94] + wire _T_195 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 246:110] + wire _T_198 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 247:69] + wire [31:0] _T_200 = _T_198 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_201 = io_picm_mask_data_m | _T_200; // @[lsu_lsc_ctl.scala 247:59] + wire [31:0] _T_203 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_exu_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 247:94] + wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 268:33] + wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 269:33] + wire _T_208 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 270:74] + wire [31:0] _T_210 = _T_208 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_213 = _T_210 & _T_212; // @[lsu_lsc_ctl.scala 270:102] + wire _T_214 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 271:43] + wire [31:0] _T_216 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_218 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_219 = _T_216 & _T_218; // @[lsu_lsc_ctl.scala 271:71] + wire [31:0] _T_220 = _T_213 | _T_219; // @[lsu_lsc_ctl.scala 270:141] + wire _T_221 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 272:17] + wire _T_222 = _T_221 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 272:43] + wire [31:0] _T_224 = _T_222 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_227 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = {_T_227,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_230 = _T_224 & _T_229; // @[lsu_lsc_ctl.scala 272:71] + wire [31:0] _T_231 = _T_220 | _T_230; // @[lsu_lsc_ctl.scala 271:114] + wire _T_233 = _T_221 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 273:43] + wire [31:0] _T_235 = _T_233 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_238 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_240 = {_T_238,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_241 = _T_235 & _T_240; // @[lsu_lsc_ctl.scala 273:71] + wire [31:0] _T_242 = _T_231 | _T_241; // @[lsu_lsc_ctl.scala 272:134] + wire [31:0] _T_244 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_244 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 274:43] + wire _T_248 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 275:66] + wire [31:0] _T_250 = _T_248 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_252 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_253 = _T_250 & _T_252; // @[lsu_lsc_ctl.scala 275:94] + wire _T_254 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 276:43] + wire [31:0] _T_256 = _T_254 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_258 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_259 = _T_256 & _T_258; // @[lsu_lsc_ctl.scala 276:71] + wire [31:0] _T_260 = _T_253 | _T_259; // @[lsu_lsc_ctl.scala 275:138] + wire _T_261 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 277:17] + wire _T_262 = _T_261 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 277:43] + wire [31:0] _T_264 = _T_262 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_267 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_269 = {_T_267,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_270 = _T_264 & _T_269; // @[lsu_lsc_ctl.scala 277:71] + wire [31:0] _T_271 = _T_260 | _T_270; // @[lsu_lsc_ctl.scala 276:119] + wire _T_273 = _T_261 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 278:43] + wire [31:0] _T_275 = _T_273 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_278 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = {_T_278,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_281 = _T_275 & _T_280; // @[lsu_lsc_ctl.scala 278:71] + wire [31:0] _T_282 = _T_271 | _T_281; // @[lsu_lsc_ctl.scala 277:144] + wire [31:0] _T_284 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_286 = _T_284 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 279:43] + lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 117:25] + .reset(addrcheck_reset), + .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk), + .io_start_addr_d(addrcheck_io_start_addr_d), + .io_end_addr_d(addrcheck_io_end_addr_d), + .io_lsu_pkt_d_valid(addrcheck_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_fast_int(addrcheck_io_lsu_pkt_d_bits_fast_int), + .io_lsu_pkt_d_bits_by(addrcheck_io_lsu_pkt_d_bits_by), + .io_lsu_pkt_d_bits_half(addrcheck_io_lsu_pkt_d_bits_half), + .io_lsu_pkt_d_bits_word(addrcheck_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_load(addrcheck_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(addrcheck_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_dma(addrcheck_io_lsu_pkt_d_bits_dma), + .io_dec_tlu_mrac_ff(addrcheck_io_dec_tlu_mrac_ff), + .io_rs1_region_d(addrcheck_io_rs1_region_d), + .io_is_sideeffects_m(addrcheck_io_is_sideeffects_m), + .io_addr_in_dccm_d(addrcheck_io_addr_in_dccm_d), + .io_addr_in_pic_d(addrcheck_io_addr_in_pic_d), + .io_addr_external_d(addrcheck_io_addr_external_d), + .io_access_fault_d(addrcheck_io_access_fault_d), + .io_misaligned_fault_d(addrcheck_io_misaligned_fault_d), + .io_exc_mscause_d(addrcheck_io_exc_mscause_d), + .io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d), + .io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d) + ); + rvclkhdr rvclkhdr ( // @[lib.scala 417:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + assign io_lsu_exu_lsu_result_m = _T_242 | _T_246; // @[lsu_lsc_ctl.scala 270:35] + assign io_lsu_result_corr_r = _T_282 | _T_286; // @[lsu_lsc_ctl.scala 275:27] + assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 244:28] + assign io_lsu_addr_m = _T_161; // @[lsu_lsc_ctl.scala 227:24] + assign io_lsu_addr_r = _T_162; // @[lsu_lsc_ctl.scala 228:24] + assign io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 114:24] + assign io_end_addr_m = {_T_164,_T_166}; // @[lsu_lsc_ctl.scala 229:17] + assign io_end_addr_r = {_T_169,_T_171}; // @[lsu_lsc_ctl.scala 230:17] + assign io_store_data_m = _T_201 & _T_203; // @[lsu_lsc_ctl.scala 247:29] + assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:16] + assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 127:42] + assign io_lsu_commit_r = _T_194 & _T_195; // @[lsu_lsc_ctl.scala 246:19] + assign io_lsu_single_ecc_error_incr = _T_74 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 155:32] + assign io_lsu_error_pkt_r_valid = _T_112; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 186:30] + assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_111; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 185:46] + assign io_lsu_error_pkt_r_bits_inst_type = _T_110_bits_inst_type; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_exc_type = _T_110_bits_exc_type; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_mscause = _T_110_bits_mscause; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_addr = _T_110_bits_addr; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 242:28] + assign io_lsu_fir_error = _T_113; // @[lsu_lsc_ctl.scala 187:38] + assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 128:42] + assign io_addr_in_dccm_m = _T_183; // @[lsu_lsc_ctl.scala 233:24] + assign io_addr_in_dccm_r = _T_184; // @[lsu_lsc_ctl.scala 234:24] + assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 129:42] + assign io_addr_in_pic_m = _T_185; // @[lsu_lsc_ctl.scala 235:24] + assign io_addr_in_pic_r = _T_186; // @[lsu_lsc_ctl.scala 236:24] + assign io_addr_external_m = _T_187; // @[lsu_lsc_ctl.scala 237:24] + assign io_lsu_pkt_d_valid = _T_128 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24] + assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_m_valid = _T_142; // @[lsu_lsc_ctl.scala 216:28 lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_m_bits_fast_int = _T_139_bits_fast_int; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_by = _T_139_bits_by; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_half = _T_139_bits_half; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_word = _T_139_bits_word; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_dword = _T_139_bits_dword; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_load = _T_139_bits_load; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store = _T_139_bits_store; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_unsign = _T_139_bits_unsign; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_dma = _T_139_bits_dma; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_139_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_valid = _T_143; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28] + assign io_lsu_pkt_r_bits_by = _T_141_bits_by; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_half = _T_141_bits_half; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_word = _T_141_bits_word; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_dword = _T_141_bits_dword; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_load = _T_141_bits_load; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store = _T_141_bits_store; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_unsign = _T_141_bits_unsign; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_dma = _T_141_bits_dma; // @[lsu_lsc_ctl.scala 217:28] + assign addrcheck_reset = reset; + assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_start_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 121:42] + assign addrcheck_io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 122:42] + assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 124:42] + assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[lsu_lsc_ctl.scala 125:42] + assign rvclkhdr_io_clk = clock; // @[lib.scala 419:18] + assign rvclkhdr_io_en = _T_105 | io_clk_override; // @[lib.scala 420:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_174 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_179 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + access_fault_m = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + misaligned_fault_m = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + exc_mscause_m = _RAND_2[3:0]; + _RAND_3 = {1{`RANDOM}}; + fir_dccm_access_error_m = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + fir_nondccm_access_error_m = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_110_bits_inst_type = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_110_bits_exc_type = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_110_bits_mscause = _RAND_7[3:0]; + _RAND_8 = {1{`RANDOM}}; + _T_110_bits_addr = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + _T_111 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + _T_112 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_113 = _RAND_11[1:0]; + _RAND_12 = {1{`RANDOM}}; + _T_139_bits_fast_int = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + _T_139_bits_by = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + _T_139_bits_half = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + _T_139_bits_word = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + _T_139_bits_dword = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + _T_139_bits_load = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + _T_139_bits_store = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + _T_139_bits_unsign = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + _T_139_bits_dma = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + _T_139_bits_store_data_bypass_m = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + _T_141_bits_by = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + _T_141_bits_half = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + _T_141_bits_word = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + _T_141_bits_dword = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + _T_141_bits_load = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + _T_141_bits_store = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + _T_141_bits_unsign = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + _T_141_bits_dma = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + _T_142 = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + _T_143 = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + _T_154 = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + _T_156 = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + _T_158 = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + _T_160 = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + store_data_pre_m = _RAND_36[31:0]; + _RAND_37 = {1{`RANDOM}}; + _T_161 = _RAND_37[31:0]; + _RAND_38 = {1{`RANDOM}}; + _T_162 = _RAND_38[31:0]; + _RAND_39 = {1{`RANDOM}}; + end_addr_pre_m = _RAND_39[28:0]; + _RAND_40 = {1{`RANDOM}}; + _T_166 = _RAND_40[2:0]; + _RAND_41 = {1{`RANDOM}}; + end_addr_pre_r = _RAND_41[28:0]; + _RAND_42 = {1{`RANDOM}}; + _T_171 = _RAND_42[2:0]; + _RAND_43 = {1{`RANDOM}}; + _T_183 = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + _T_184 = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + _T_185 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + _T_186 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + _T_187 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + addr_external_r = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + bus_read_data_r = _RAND_49[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + access_fault_m = 1'h0; + end + if (reset) begin + misaligned_fault_m = 1'h0; + end + if (reset) begin + exc_mscause_m = 4'h0; + end + if (reset) begin + fir_dccm_access_error_m = 1'h0; + end + if (reset) begin + fir_nondccm_access_error_m = 1'h0; + end + if (reset) begin + _T_110_bits_inst_type = 1'h0; + end + if (reset) begin + _T_110_bits_exc_type = 1'h0; + end + if (reset) begin + _T_110_bits_mscause = 4'h0; + end + if (reset) begin + _T_110_bits_addr = 32'h0; + end + if (reset) begin + _T_111 = 1'h0; + end + if (reset) begin + _T_112 = 1'h0; + end + if (reset) begin + _T_113 = 2'h0; + end + if (reset) begin + _T_139_bits_fast_int = 1'h0; + end + if (reset) begin + _T_139_bits_by = 1'h0; + end + if (reset) begin + _T_139_bits_half = 1'h0; + end + if (reset) begin + _T_139_bits_word = 1'h0; + end + if (reset) begin + _T_139_bits_dword = 1'h0; + end + if (reset) begin + _T_139_bits_load = 1'h0; + end + if (reset) begin + _T_139_bits_store = 1'h0; + end + if (reset) begin + _T_139_bits_unsign = 1'h0; + end + if (reset) begin + _T_139_bits_dma = 1'h0; + end + if (reset) begin + _T_139_bits_store_data_bypass_m = 1'h0; + end + if (reset) begin + _T_141_bits_by = 1'h0; + end + if (reset) begin + _T_141_bits_half = 1'h0; + end + if (reset) begin + _T_141_bits_word = 1'h0; + end + if (reset) begin + _T_141_bits_dword = 1'h0; + end + if (reset) begin + _T_141_bits_load = 1'h0; + end + if (reset) begin + _T_141_bits_store = 1'h0; + end + if (reset) begin + _T_141_bits_unsign = 1'h0; + end + if (reset) begin + _T_141_bits_dma = 1'h0; + end + if (reset) begin + _T_142 = 1'h0; + end + if (reset) begin + _T_143 = 1'h0; + end + if (reset) begin + _T_154 = 1'h0; + end + if (reset) begin + _T_156 = 1'h0; + end + if (reset) begin + _T_158 = 1'h0; + end + if (reset) begin + _T_160 = 1'h0; + end + if (reset) begin + store_data_pre_m = 32'h0; + end + if (reset) begin + _T_161 = 32'h0; + end + if (reset) begin + _T_162 = 32'h0; + end + if (reset) begin + end_addr_pre_m = 29'h0; + end + if (reset) begin + _T_166 = 3'h0; + end + if (reset) begin + end_addr_pre_r = 29'h0; + end + if (reset) begin + _T_171 = 3'h0; + end + if (reset) begin + _T_183 = 1'h0; + end + if (reset) begin + _T_184 = 1'h0; + end + if (reset) begin + _T_185 = 1'h0; + end + if (reset) begin + _T_186 = 1'h0; + end + if (reset) begin + _T_187 = 1'h0; + end + if (reset) begin + addr_external_r = 1'h0; + end + if (reset) begin + bus_read_data_r = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + access_fault_m <= 1'h0; + end else begin + access_fault_m <= addrcheck_io_access_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + misaligned_fault_m <= 1'h0; + end else begin + misaligned_fault_m <= addrcheck_io_misaligned_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + exc_mscause_m <= 4'h0; + end else begin + exc_mscause_m <= addrcheck_io_exc_mscause_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_dccm_access_error_m <= 1'h0; + end else begin + fir_dccm_access_error_m <= addrcheck_io_fir_dccm_access_error_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_nondccm_access_error_m <= 1'h0; + end else begin + fir_nondccm_access_error_m <= addrcheck_io_fir_nondccm_access_error_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_inst_type <= 1'h0; + end else if (_T_106) begin + _T_110_bits_inst_type <= io_lsu_pkt_m_bits_store; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_exc_type <= 1'h0; + end else if (_T_106) begin + _T_110_bits_exc_type <= lsu_error_pkt_m_bits_exc_type; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_mscause <= 4'h0; + end else if (_T_106) begin + if (_T_93) begin + _T_110_bits_mscause <= 4'h1; + end else begin + _T_110_bits_mscause <= exc_mscause_m; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_addr <= 32'h0; + end else if (_T_106) begin + _T_110_bits_addr <= io_lsu_addr_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_111 <= 1'h0; + end else begin + _T_111 <= _T_86 & _T_79; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_112 <= 1'h0; + end else begin + _T_112 <= _T_82 & _T_83; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_113 <= 2'h0; + end else if (fir_nondccm_access_error_m) begin + _T_113 <= 2'h3; + end else if (fir_dccm_access_error_m) begin + _T_113 <= 2'h2; + end else if (_T_100) begin + _T_113 <= 2'h1; + end else begin + _T_113 <= 2'h0; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_fast_int <= 1'h0; + end else begin + _T_139_bits_fast_int <= io_lsu_pkt_d_bits_fast_int; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_by <= 1'h0; + end else begin + _T_139_bits_by <= io_lsu_pkt_d_bits_by; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_half <= 1'h0; + end else begin + _T_139_bits_half <= io_lsu_pkt_d_bits_half; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_word <= 1'h0; + end else begin + _T_139_bits_word <= io_lsu_pkt_d_bits_word; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_dword <= 1'h0; + end else begin + _T_139_bits_dword <= io_lsu_pkt_d_bits_dword; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_load <= 1'h0; + end else begin + _T_139_bits_load <= io_lsu_pkt_d_bits_load; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_store <= 1'h0; + end else begin + _T_139_bits_store <= io_lsu_pkt_d_bits_store; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_unsign <= 1'h0; + end else begin + _T_139_bits_unsign <= io_lsu_pkt_d_bits_unsign; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_dma <= 1'h0; + end else begin + _T_139_bits_dma <= io_lsu_pkt_d_bits_dma; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_store_data_bypass_m <= 1'h0; + end else begin + _T_139_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_by <= 1'h0; + end else begin + _T_141_bits_by <= io_lsu_pkt_m_bits_by; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_half <= 1'h0; + end else begin + _T_141_bits_half <= io_lsu_pkt_m_bits_half; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_word <= 1'h0; + end else begin + _T_141_bits_word <= io_lsu_pkt_m_bits_word; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_dword <= 1'h0; + end else begin + _T_141_bits_dword <= io_lsu_pkt_m_bits_dword; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_load <= 1'h0; + end else begin + _T_141_bits_load <= io_lsu_pkt_m_bits_load; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_store <= 1'h0; + end else begin + _T_141_bits_store <= io_lsu_pkt_m_bits_store; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_unsign <= 1'h0; + end else begin + _T_141_bits_unsign <= io_lsu_pkt_m_bits_unsign; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_dma <= 1'h0; + end else begin + _T_141_bits_dma <= io_lsu_pkt_m_bits_dma; + end + end + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_142 <= 1'h0; + end else begin + _T_142 <= io_lsu_pkt_d_valid & _T_132; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_143 <= 1'h0; + end else begin + _T_143 <= io_lsu_pkt_m_valid & _T_136; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_154 <= 1'h0; + end else begin + _T_154 <= io_lsu_addr_d[2]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_156 <= 1'h0; + end else begin + _T_156 <= io_end_addr_d[2]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_158 <= 1'h0; + end else begin + _T_158 <= io_lsu_addr_m[2]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_160 <= 1'h0; + end else begin + _T_160 <= io_end_addr_m[2]; + end + end + always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin + if (reset) begin + store_data_pre_m <= 32'h0; + end else if (io_lsu_pkt_d_bits_store_data_bypass_d) begin + store_data_pre_m <= io_lsu_exu_lsu_result_m; + end else if (io_dma_lsc_ctl_dma_dccm_req) begin + store_data_pre_m <= dma_mem_wdata_shifted[31:0]; + end else begin + store_data_pre_m <= io_lsu_exu_exu_lsu_rs2_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_161 <= 32'h0; + end else begin + _T_161 <= io_lsu_addr_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_162 <= 32'h0; + end else begin + _T_162 <= io_lsu_addr_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + end_addr_pre_m <= 29'h0; + end else if (_T_175) begin + end_addr_pre_m <= io_end_addr_d[31:3]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_166 <= 3'h0; + end else begin + _T_166 <= io_end_addr_d[2:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + end_addr_pre_r <= 29'h0; + end else if (_T_180) begin + end_addr_pre_r <= io_end_addr_m[31:3]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_171 <= 3'h0; + end else begin + _T_171 <= io_end_addr_m[2:0]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_183 <= 1'h0; + end else begin + _T_183 <= io_addr_in_dccm_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_184 <= 1'h0; + end else begin + _T_184 <= io_addr_in_dccm_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_185 <= 1'h0; + end else begin + _T_185 <= io_addr_in_pic_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_186 <= 1'h0; + end else begin + _T_186 <= io_addr_in_pic_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_187 <= 1'h0; + end else begin + _T_187 <= addrcheck_io_addr_external_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + addr_external_r <= 1'h0; + end else begin + addr_external_r <= io_addr_external_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + bus_read_data_r <= 32'h0; + end else if (_T_188) begin + bus_read_data_r <= io_bus_read_data_m; + end + end +endmodule +module lsu_dccm_ctl( + input clock, + input reset, + input io_clk_override, + input io_lsu_c2_m_clk, + input io_lsu_free_c2_clk, + input io_lsu_store_c1_r_clk, + input io_lsu_pkt_d_valid, + input io_lsu_pkt_d_bits_word, + input io_lsu_pkt_d_bits_dword, + input io_lsu_pkt_d_bits_load, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_d_bits_dma, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_dma, + input io_addr_in_dccm_d, + input io_addr_in_dccm_m, + input io_addr_in_dccm_r, + input io_addr_in_pic_d, + input io_addr_in_pic_m, + input io_addr_in_pic_r, + input io_lsu_raw_fwd_lo_r, + input io_lsu_raw_fwd_hi_r, + input io_lsu_commit_r, + input io_ldst_dual_m, + input [31:0] io_lsu_addr_d, + input [15:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [15:0] io_end_addr_d, + input [15:0] io_end_addr_m, + input [15:0] io_end_addr_r, + input io_stbuf_reqvld_any, + input [15:0] io_stbuf_addr_any, + input [31:0] io_stbuf_data_any, + input [6:0] io_stbuf_ecc_any, + input [31:0] io_stbuf_fwddata_hi_m, + input [31:0] io_stbuf_fwddata_lo_m, + input [3:0] io_stbuf_fwdbyteen_lo_m, + input [3:0] io_stbuf_fwdbyteen_hi_m, + output [31:0] io_lsu_ld_data_corr_r, + input io_lsu_double_ecc_error_r, + input io_single_ecc_error_hi_r, + input io_single_ecc_error_lo_r, + input [31:0] io_sec_data_hi_r_ff, + input [31:0] io_sec_data_lo_r_ff, + input [6:0] io_sec_data_ecc_hi_r_ff, + input [6:0] io_sec_data_ecc_lo_r_ff, + output [31:0] io_dccm_rdata_hi_m, + output [31:0] io_dccm_rdata_lo_m, + output [6:0] io_dccm_data_ecc_hi_m, + output [6:0] io_dccm_data_ecc_lo_m, + output [31:0] io_lsu_ld_data_m, + input io_lsu_double_ecc_error_m, + input [31:0] io_sec_data_hi_m, + input [31:0] io_sec_data_lo_m, + input [31:0] io_store_data_m, + input io_dma_dccm_wen, + input io_dma_pic_wen, + input [2:0] io_dma_mem_tag_m, + input [31:0] io_dma_dccm_wdata_lo, + input [31:0] io_dma_dccm_wdata_hi, + input [6:0] io_dma_dccm_wdata_ecc_hi, + input [6:0] io_dma_dccm_wdata_ecc_lo, + output [31:0] io_store_data_hi_r, + output [31:0] io_store_data_lo_r, + output [31:0] io_store_datafn_hi_r, + output [31:0] io_store_datafn_lo_r, + output [31:0] io_store_data_r, + output io_ld_single_ecc_error_r, + output io_ld_single_ecc_error_r_ff, + output [31:0] io_picm_mask_data_m, + output io_lsu_stbuf_commit_any, + output io_lsu_dccm_rden_m, + input [31:0] io_dma_dccm_ctl_dma_mem_addr, + input [63:0] io_dma_dccm_ctl_dma_mem_wdata, + output io_dma_dccm_ctl_dccm_dma_rvalid, + output io_dma_dccm_ctl_dccm_dma_ecc_error, + output [2:0] io_dma_dccm_ctl_dccm_dma_rtag, + output [63:0] io_dma_dccm_ctl_dccm_dma_rdata, + output io_dccm_wren, + output io_dccm_rden, + output [15:0] io_dccm_wr_addr_lo, + output [15:0] io_dccm_wr_addr_hi, + output [15:0] io_dccm_rd_addr_lo, + output [15:0] io_dccm_rd_addr_hi, + output [38:0] io_dccm_wr_data_lo, + output [38:0] io_dccm_wr_data_hi, + input [38:0] io_dccm_rd_data_lo, + input [38:0] io_dccm_rd_data_hi, + output io_lsu_pic_picm_wren, + output io_lsu_pic_picm_rden, + output io_lsu_pic_picm_mken, + output [31:0] io_lsu_pic_picm_rdaddr, + output [31:0] io_lsu_pic_picm_wraddr, + output [31:0] io_lsu_pic_picm_wr_data, + input [31:0] io_lsu_pic_picm_rd_data +); +`ifdef RANDOMIZE_REG_INIT + reg [63:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire [63:0] picm_rd_data_m = {io_lsu_pic_picm_rd_data,io_lsu_pic_picm_rd_data}; // @[Cat.scala 29:58] + wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58] + wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58] + wire _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_load; // @[lsu_dccm_ctl.scala 145:63] + wire [7:0] _T_6 = {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m}; // @[Cat.scala 29:58] + wire [63:0] _T_9 = {io_stbuf_fwddata_hi_m,io_stbuf_fwddata_lo_m}; // @[Cat.scala 29:58] + wire [7:0] _T_14 = io_addr_in_dccm_m ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_16 = _T_14 & dccm_rdata_corr_m[7:0]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_17 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : _T_16; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_18 = _T_6[0] ? _T_9[7:0] : _T_17; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_22 = {{4'd0}, _T_18[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_24 = {_T_18[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_26 = _T_24 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_27 = _T_22 | _T_26; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_4 = {{2'd0}, _T_27[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_32 = _GEN_4 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_34 = {_T_27[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_36 = _T_34 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_37 = _T_32 | _T_36; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_5 = {{1'd0}, _T_37[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_42 = _GEN_5 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_44 = {_T_37[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_46 = _T_44 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_47 = _T_42 | _T_46; // @[Bitwise.scala 103:39] + wire [7:0] _T_58 = _T_14 & dccm_rdata_corr_m[15:8]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_59 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : _T_58; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_60 = _T_6[1] ? _T_9[15:8] : _T_59; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_64 = {{4'd0}, _T_60[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_66 = {_T_60[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_68 = _T_66 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_69 = _T_64 | _T_68; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_6 = {{2'd0}, _T_69[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_74 = _GEN_6 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_76 = {_T_69[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_78 = _T_76 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_79 = _T_74 | _T_78; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_7 = {{1'd0}, _T_79[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_84 = _GEN_7 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_86 = {_T_79[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_88 = _T_86 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_89 = _T_84 | _T_88; // @[Bitwise.scala 103:39] + wire [7:0] _T_100 = _T_14 & dccm_rdata_corr_m[23:16]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_101 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : _T_100; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_102 = _T_6[2] ? _T_9[23:16] : _T_101; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_106 = {{4'd0}, _T_102[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_108 = {_T_102[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_110 = _T_108 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_111 = _T_106 | _T_110; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_8 = {{2'd0}, _T_111[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_116 = _GEN_8 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_118 = {_T_111[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_120 = _T_118 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_121 = _T_116 | _T_120; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_9 = {{1'd0}, _T_121[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_126 = _GEN_9 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_128 = {_T_121[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_130 = _T_128 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_131 = _T_126 | _T_130; // @[Bitwise.scala 103:39] + wire [7:0] _T_142 = _T_14 & dccm_rdata_corr_m[31:24]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_143 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : _T_142; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_144 = _T_6[3] ? _T_9[31:24] : _T_143; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_148 = {{4'd0}, _T_144[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_150 = {_T_144[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_152 = _T_150 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_153 = _T_148 | _T_152; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_10 = {{2'd0}, _T_153[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_158 = _GEN_10 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_160 = {_T_153[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_162 = _T_160 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_163 = _T_158 | _T_162; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_11 = {{1'd0}, _T_163[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_168 = _GEN_11 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_170 = {_T_163[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_172 = _T_170 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_173 = _T_168 | _T_172; // @[Bitwise.scala 103:39] + wire [7:0] _T_184 = _T_14 & dccm_rdata_corr_m[39:32]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_185 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : _T_184; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_186 = _T_6[4] ? _T_9[39:32] : _T_185; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_190 = {{4'd0}, _T_186[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_192 = {_T_186[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_194 = _T_192 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_195 = _T_190 | _T_194; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_12 = {{2'd0}, _T_195[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_200 = _GEN_12 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_202 = {_T_195[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_204 = _T_202 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_205 = _T_200 | _T_204; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_13 = {{1'd0}, _T_205[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_210 = _GEN_13 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_212 = {_T_205[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_214 = _T_212 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_215 = _T_210 | _T_214; // @[Bitwise.scala 103:39] + wire [7:0] _T_226 = _T_14 & dccm_rdata_corr_m[47:40]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_227 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : _T_226; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_228 = _T_6[5] ? _T_9[47:40] : _T_227; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_232 = {{4'd0}, _T_228[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_234 = {_T_228[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_236 = _T_234 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_237 = _T_232 | _T_236; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_14 = {{2'd0}, _T_237[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_242 = _GEN_14 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_244 = {_T_237[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_246 = _T_244 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_247 = _T_242 | _T_246; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_15 = {{1'd0}, _T_247[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_252 = _GEN_15 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_254 = {_T_247[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_256 = _T_254 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_257 = _T_252 | _T_256; // @[Bitwise.scala 103:39] + wire [7:0] _T_268 = _T_14 & dccm_rdata_corr_m[55:48]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_269 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : _T_268; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_270 = _T_6[6] ? _T_9[55:48] : _T_269; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_274 = {{4'd0}, _T_270[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_276 = {_T_270[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_278 = _T_276 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_279 = _T_274 | _T_278; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_16 = {{2'd0}, _T_279[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_284 = _GEN_16 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_286 = {_T_279[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_288 = _T_286 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_289 = _T_284 | _T_288; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_17 = {{1'd0}, _T_289[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_294 = _GEN_17 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_296 = {_T_289[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_298 = _T_296 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_299 = _T_294 | _T_298; // @[Bitwise.scala 103:39] + wire [7:0] _T_310 = _T_14 & dccm_rdata_corr_m[63:56]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_311 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : _T_310; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_312 = _T_6[7] ? _T_9[63:56] : _T_311; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_316 = {{4'd0}, _T_312[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_318 = {_T_312[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_320 = _T_318 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_321 = _T_316 | _T_320; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_18 = {{2'd0}, _T_321[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_326 = _GEN_18 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_328 = {_T_321[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_330 = _T_328 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_331 = _T_326 | _T_330; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_19 = {{1'd0}, _T_331[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_336 = _GEN_19 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_338 = {_T_331[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_340 = _T_338 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_341 = _T_336 | _T_340; // @[Bitwise.scala 103:39] + wire [63:0] _T_349 = {_T_47,_T_89,_T_131,_T_173,_T_215,_T_257,_T_299,_T_341}; // @[Cat.scala 29:58] + wire [63:0] _T_353 = {{32'd0}, _T_349[63:32]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_355 = {_T_349[31:0], 32'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_357 = _T_355 & 64'hffffffff00000000; // @[Bitwise.scala 103:75] + wire [63:0] _T_358 = _T_353 | _T_357; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_20 = {{16'd0}, _T_358[63:16]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_363 = _GEN_20 & 64'hffff0000ffff; // @[Bitwise.scala 103:31] + wire [63:0] _T_365 = {_T_358[47:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_367 = _T_365 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75] + wire [63:0] _T_368 = _T_363 | _T_367; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_21 = {{8'd0}, _T_368[63:8]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_373 = _GEN_21 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31] + wire [63:0] _T_375 = {_T_368[55:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_377 = _T_375 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75] + wire [63:0] _T_378 = _T_373 | _T_377; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_22 = {{4'd0}, _T_378[63:4]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_383 = _GEN_22 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31] + wire [63:0] _T_385 = {_T_378[59:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_387 = _T_385 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75] + wire [63:0] _T_388 = _T_383 | _T_387; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_23 = {{2'd0}, _T_388[63:2]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_393 = _GEN_23 & 64'h3333333333333333; // @[Bitwise.scala 103:31] + wire [63:0] _T_395 = {_T_388[61:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_397 = _T_395 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75] + wire [63:0] _T_398 = _T_393 | _T_397; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_24 = {{1'd0}, _T_398[63:1]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_403 = _GEN_24 & 64'h5555555555555555; // @[Bitwise.scala 103:31] + wire [63:0] _T_405 = {_T_398[62:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_407 = _T_405 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] lsu_rdata_corr_m = _T_403 | _T_407; // @[Bitwise.scala 103:39] + wire [63:0] _T_4 = {lsu_rdata_corr_m[31:0],lsu_rdata_corr_m[31:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_419 = _T_14 & dccm_rdata_m[7:0]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_420 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : _T_419; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_421 = _T_6[0] ? _T_9[7:0] : _T_420; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_425 = {{4'd0}, _T_421[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_427 = {_T_421[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_429 = _T_427 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_430 = _T_425 | _T_429; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_25 = {{2'd0}, _T_430[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_435 = _GEN_25 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_437 = {_T_430[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_439 = _T_437 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_440 = _T_435 | _T_439; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_26 = {{1'd0}, _T_440[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_445 = _GEN_26 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_447 = {_T_440[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_449 = _T_447 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_450 = _T_445 | _T_449; // @[Bitwise.scala 103:39] + wire [7:0] _T_461 = _T_14 & dccm_rdata_m[15:8]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_462 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : _T_461; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_463 = _T_6[1] ? _T_9[15:8] : _T_462; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_467 = {{4'd0}, _T_463[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_469 = {_T_463[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_471 = _T_469 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_472 = _T_467 | _T_471; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_27 = {{2'd0}, _T_472[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_477 = _GEN_27 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_479 = {_T_472[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_481 = _T_479 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_482 = _T_477 | _T_481; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_28 = {{1'd0}, _T_482[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_487 = _GEN_28 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_489 = {_T_482[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_491 = _T_489 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_492 = _T_487 | _T_491; // @[Bitwise.scala 103:39] + wire [7:0] _T_503 = _T_14 & dccm_rdata_m[23:16]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_504 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : _T_503; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_505 = _T_6[2] ? _T_9[23:16] : _T_504; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_509 = {{4'd0}, _T_505[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_511 = {_T_505[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_513 = _T_511 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_514 = _T_509 | _T_513; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_29 = {{2'd0}, _T_514[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_519 = _GEN_29 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_521 = {_T_514[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_523 = _T_521 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_524 = _T_519 | _T_523; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_30 = {{1'd0}, _T_524[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_529 = _GEN_30 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_531 = {_T_524[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_533 = _T_531 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_534 = _T_529 | _T_533; // @[Bitwise.scala 103:39] + wire [7:0] _T_545 = _T_14 & dccm_rdata_m[31:24]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_546 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : _T_545; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_547 = _T_6[3] ? _T_9[31:24] : _T_546; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_551 = {{4'd0}, _T_547[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_553 = {_T_547[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_555 = _T_553 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_556 = _T_551 | _T_555; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_31 = {{2'd0}, _T_556[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_561 = _GEN_31 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_563 = {_T_556[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_565 = _T_563 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_566 = _T_561 | _T_565; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_32 = {{1'd0}, _T_566[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_571 = _GEN_32 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_573 = {_T_566[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_575 = _T_573 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_576 = _T_571 | _T_575; // @[Bitwise.scala 103:39] + wire [7:0] _T_587 = _T_14 & dccm_rdata_m[39:32]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_588 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : _T_587; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_589 = _T_6[4] ? _T_9[39:32] : _T_588; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_593 = {{4'd0}, _T_589[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_595 = {_T_589[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_597 = _T_595 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_598 = _T_593 | _T_597; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_33 = {{2'd0}, _T_598[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_603 = _GEN_33 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_605 = {_T_598[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_607 = _T_605 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_608 = _T_603 | _T_607; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_34 = {{1'd0}, _T_608[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_613 = _GEN_34 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_615 = {_T_608[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_617 = _T_615 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_618 = _T_613 | _T_617; // @[Bitwise.scala 103:39] + wire [7:0] _T_629 = _T_14 & dccm_rdata_m[47:40]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_630 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : _T_629; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_631 = _T_6[5] ? _T_9[47:40] : _T_630; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_635 = {{4'd0}, _T_631[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_637 = {_T_631[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_639 = _T_637 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_640 = _T_635 | _T_639; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_35 = {{2'd0}, _T_640[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_645 = _GEN_35 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_647 = {_T_640[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_649 = _T_647 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_650 = _T_645 | _T_649; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_36 = {{1'd0}, _T_650[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_655 = _GEN_36 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_657 = {_T_650[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_659 = _T_657 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_660 = _T_655 | _T_659; // @[Bitwise.scala 103:39] + wire [7:0] _T_671 = _T_14 & dccm_rdata_m[55:48]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_672 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : _T_671; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_673 = _T_6[6] ? _T_9[55:48] : _T_672; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_677 = {{4'd0}, _T_673[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_679 = {_T_673[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_681 = _T_679 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_682 = _T_677 | _T_681; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_37 = {{2'd0}, _T_682[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_687 = _GEN_37 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_689 = {_T_682[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_691 = _T_689 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_692 = _T_687 | _T_691; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_38 = {{1'd0}, _T_692[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_697 = _GEN_38 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_699 = {_T_692[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_701 = _T_699 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_702 = _T_697 | _T_701; // @[Bitwise.scala 103:39] + wire [7:0] _T_713 = _T_14 & dccm_rdata_m[63:56]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_714 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : _T_713; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_715 = _T_6[7] ? _T_9[63:56] : _T_714; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_719 = {{4'd0}, _T_715[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_721 = {_T_715[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_723 = _T_721 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_724 = _T_719 | _T_723; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_39 = {{2'd0}, _T_724[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_729 = _GEN_39 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_731 = {_T_724[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_733 = _T_731 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_734 = _T_729 | _T_733; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_40 = {{1'd0}, _T_734[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_739 = _GEN_40 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_741 = {_T_734[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_743 = _T_741 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_744 = _T_739 | _T_743; // @[Bitwise.scala 103:39] + wire [63:0] _T_752 = {_T_450,_T_492,_T_534,_T_576,_T_618,_T_660,_T_702,_T_744}; // @[Cat.scala 29:58] + wire [63:0] _T_756 = {{32'd0}, _T_752[63:32]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_758 = {_T_752[31:0], 32'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_760 = _T_758 & 64'hffffffff00000000; // @[Bitwise.scala 103:75] + wire [63:0] _T_761 = _T_756 | _T_760; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_41 = {{16'd0}, _T_761[63:16]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_766 = _GEN_41 & 64'hffff0000ffff; // @[Bitwise.scala 103:31] + wire [63:0] _T_768 = {_T_761[47:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_770 = _T_768 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75] + wire [63:0] _T_771 = _T_766 | _T_770; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_42 = {{8'd0}, _T_771[63:8]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_776 = _GEN_42 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31] + wire [63:0] _T_778 = {_T_771[55:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_780 = _T_778 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75] + wire [63:0] _T_781 = _T_776 | _T_780; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_43 = {{4'd0}, _T_781[63:4]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_786 = _GEN_43 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31] + wire [63:0] _T_788 = {_T_781[59:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_790 = _T_788 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75] + wire [63:0] _T_791 = _T_786 | _T_790; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_44 = {{2'd0}, _T_791[63:2]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_796 = _GEN_44 & 64'h3333333333333333; // @[Bitwise.scala 103:31] + wire [63:0] _T_798 = {_T_791[61:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_800 = _T_798 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75] + wire [63:0] _T_801 = _T_796 | _T_800; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_45 = {{1'd0}, _T_801[63:1]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_806 = _GEN_45 & 64'h5555555555555555; // @[Bitwise.scala 103:31] + wire [63:0] _T_808 = {_T_801[62:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_810 = _T_808 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] lsu_rdata_m = _T_806 | _T_810; // @[Bitwise.scala 103:39] + wire _T_813 = io_addr_in_pic_m | io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 157:123] + wire _T_814 = _T & _T_813; // @[lsu_dccm_ctl.scala 157:103] + wire _T_815 = _T_814 | io_clk_override; // @[lsu_dccm_ctl.scala 157:145] + reg [63:0] _T_818; // @[Reg.scala 27:20] + wire [3:0] _GEN_46 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_dccm_ctl.scala 159:54] + wire [5:0] _T_823 = 4'h8 * _GEN_46; // @[lsu_dccm_ctl.scala 159:54] + wire [63:0] lsu_ld_data_corr_m = lsu_rdata_corr_m >> _T_823; // @[lsu_dccm_ctl.scala 159:48] + wire [63:0] _T_821 = lsu_rdata_m >> _T_823; // @[lsu_dccm_ctl.scala 158:43] + wire _T_827 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:60] + wire _T_830 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:133] + wire _T_831 = _T_827 | _T_830; // @[lsu_dccm_ctl.scala 163:101] + wire _T_832 = _T_831 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 163:175] + wire _T_833 = _T_832 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 163:196] + wire _T_834 = _T_833 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 163:222] + wire _T_835 = _T_834 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 163:246] + wire _T_838 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:37] + wire _T_841 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:110] + wire _T_842 = _T_838 | _T_841; // @[lsu_dccm_ctl.scala 164:78] + wire _T_843 = _T_842 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 164:152] + wire _T_844 = _T_843 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 164:173] + wire _T_845 = _T_844 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 164:199] + wire _T_846 = _T_845 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 164:223] + wire kill_ecc_corr_lo_r = _T_835 | _T_846; // @[lsu_dccm_ctl.scala 163:267] + wire _T_849 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:60] + wire _T_852 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:133] + wire _T_853 = _T_849 | _T_852; // @[lsu_dccm_ctl.scala 166:101] + wire _T_854 = _T_853 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 166:175] + wire _T_855 = _T_854 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 166:196] + wire _T_856 = _T_855 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 166:222] + wire _T_857 = _T_856 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 166:246] + wire _T_860 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:37] + wire _T_863 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:110] + wire _T_864 = _T_860 | _T_863; // @[lsu_dccm_ctl.scala 167:78] + wire _T_865 = _T_864 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 167:152] + wire _T_866 = _T_865 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 167:173] + wire _T_867 = _T_866 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 167:199] + wire _T_868 = _T_867 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 167:223] + wire kill_ecc_corr_hi_r = _T_857 | _T_868; // @[lsu_dccm_ctl.scala 166:267] + wire _T_869 = io_lsu_pkt_r_bits_load & io_single_ecc_error_lo_r; // @[lsu_dccm_ctl.scala 169:60] + wire _T_870 = ~io_lsu_raw_fwd_lo_r; // @[lsu_dccm_ctl.scala 169:89] + wire ld_single_ecc_error_lo_r = _T_869 & _T_870; // @[lsu_dccm_ctl.scala 169:87] + wire _T_871 = io_lsu_pkt_r_bits_load & io_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 170:60] + wire _T_872 = ~io_lsu_raw_fwd_hi_r; // @[lsu_dccm_ctl.scala 170:89] + wire ld_single_ecc_error_hi_r = _T_871 & _T_872; // @[lsu_dccm_ctl.scala 170:87] + wire _T_873 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 171:63] + wire _T_874 = ~io_lsu_double_ecc_error_r; // @[lsu_dccm_ctl.scala 171:93] + wire _T_876 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_dccm_ctl.scala 172:81] + wire _T_877 = ld_single_ecc_error_lo_r & _T_876; // @[lsu_dccm_ctl.scala 172:62] + wire _T_878 = ~kill_ecc_corr_lo_r; // @[lsu_dccm_ctl.scala 172:108] + wire _T_880 = ld_single_ecc_error_hi_r & _T_876; // @[lsu_dccm_ctl.scala 173:62] + wire _T_881 = ~kill_ecc_corr_hi_r; // @[lsu_dccm_ctl.scala 173:108] + wire _T_882 = io_lsu_pkt_d_bits_word | io_lsu_pkt_d_bits_dword; // @[lsu_dccm_ctl.scala 175:125] + wire _T_883 = ~_T_882; // @[lsu_dccm_ctl.scala 175:100] + wire _T_885 = io_lsu_addr_d[1:0] != 2'h0; // @[lsu_dccm_ctl.scala 175:174] + wire _T_886 = _T_883 | _T_885; // @[lsu_dccm_ctl.scala 175:152] + wire _T_887 = io_lsu_pkt_d_bits_store & _T_886; // @[lsu_dccm_ctl.scala 175:97] + wire _T_888 = io_lsu_pkt_d_bits_load | _T_887; // @[lsu_dccm_ctl.scala 175:70] + wire _T_889 = io_lsu_pkt_d_valid & _T_888; // @[lsu_dccm_ctl.scala 175:44] + wire lsu_dccm_rden_d = _T_889 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 175:191] + reg ld_single_ecc_error_lo_r_ff; // @[lsu_dccm_ctl.scala 284:73] + reg ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 283:73] + wire _T_890 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 178:63] + reg lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 282:73] + wire _T_891 = ~lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 178:96] + wire _T_893 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[lsu_dccm_ctl.scala 179:75] + wire _T_894 = _T_893 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 179:93] + wire _T_895 = ~_T_894; // @[lsu_dccm_ctl.scala 179:57] + wire _T_898 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[lsu_dccm_ctl.scala 180:95] + wire _T_901 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[lsu_dccm_ctl.scala 181:76] + wire _T_902 = _T_898 | _T_901; // @[lsu_dccm_ctl.scala 180:171] + wire _T_903 = ~_T_902; // @[lsu_dccm_ctl.scala 180:24] + wire _T_904 = lsu_dccm_rden_d & _T_903; // @[lsu_dccm_ctl.scala 180:22] + wire _T_905 = _T_895 | _T_904; // @[lsu_dccm_ctl.scala 179:124] + wire _T_907 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[lsu_dccm_ctl.scala 185:41] + reg [15:0] ld_sec_addr_lo_r_ff; // @[Reg.scala 27:20] + reg [15:0] ld_sec_addr_hi_r_ff; // @[Reg.scala 27:20] + wire [15:0] _T_914 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[lsu_dccm_ctl.scala 189:8] + wire [15:0] _T_918 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 190:8] + wire [15:0] _T_924 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[lsu_dccm_ctl.scala 193:8] + wire [15:0] _T_928 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 194:8] + wire [38:0] _T_936 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58] + wire [38:0] _T_939 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58] + wire [38:0] _T_940 = ld_single_ecc_error_lo_r_ff ? _T_936 : _T_939; // @[lsu_dccm_ctl.scala 200:8] + wire [38:0] _T_944 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58] + wire [38:0] _T_947 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58] + wire [38:0] _T_948 = io_dma_dccm_wen ? _T_944 : _T_947; // @[lsu_dccm_ctl.scala 202:8] + wire [38:0] _T_958 = ld_single_ecc_error_hi_r_ff ? _T_939 : _T_936; // @[lsu_dccm_ctl.scala 206:8] + wire [38:0] _T_962 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58] + wire [38:0] _T_966 = io_dma_dccm_wen ? _T_962 : _T_947; // @[lsu_dccm_ctl.scala 208:8] + wire [3:0] _T_969 = io_lsu_pkt_m_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_971 = io_lsu_pkt_m_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_972 = _T_971 & 4'h1; // @[lsu_dccm_ctl.scala 212:94] + wire [3:0] _T_974 = io_lsu_pkt_m_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_975 = _T_974 & 4'h3; // @[lsu_dccm_ctl.scala 213:38] + wire [3:0] _T_976 = _T_972 | _T_975; // @[lsu_dccm_ctl.scala 212:107] + wire [3:0] _T_978 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_980 = _T_976 | _T_978; // @[lsu_dccm_ctl.scala 213:51] + wire [3:0] store_byteen_m = _T_969 & _T_980; // @[lsu_dccm_ctl.scala 212:58] + wire [3:0] _T_982 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_984 = io_lsu_pkt_r_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_985 = _T_984 & 4'h1; // @[lsu_dccm_ctl.scala 216:94] + wire [3:0] _T_987 = io_lsu_pkt_r_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_988 = _T_987 & 4'h3; // @[lsu_dccm_ctl.scala 217:38] + wire [3:0] _T_989 = _T_985 | _T_988; // @[lsu_dccm_ctl.scala 216:107] + wire [3:0] _T_991 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_993 = _T_989 | _T_991; // @[lsu_dccm_ctl.scala 217:51] + wire [3:0] store_byteen_r = _T_982 & _T_993; // @[lsu_dccm_ctl.scala 216:58] + wire [6:0] _GEN_48 = {{3'd0}, store_byteen_m}; // @[lsu_dccm_ctl.scala 220:45] + wire [6:0] _T_996 = _GEN_48 << io_lsu_addr_m[1:0]; // @[lsu_dccm_ctl.scala 220:45] + wire [6:0] _GEN_49 = {{3'd0}, store_byteen_r}; // @[lsu_dccm_ctl.scala 222:45] + wire [6:0] _T_999 = _GEN_49 << io_lsu_addr_r[1:0]; // @[lsu_dccm_ctl.scala 222:45] + wire _T_1002 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[lsu_dccm_ctl.scala 225:67] + wire dccm_wr_bypass_d_m_lo = _T_1002 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 225:101] + wire _T_1005 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[lsu_dccm_ctl.scala 226:67] + wire dccm_wr_bypass_d_m_hi = _T_1005 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 226:101] + wire _T_1008 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 228:67] + wire dccm_wr_bypass_d_r_lo = _T_1008 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 228:101] + wire _T_1011 = io_stbuf_addr_any[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 229:67] + wire dccm_wr_bypass_d_r_hi = _T_1011 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 229:101] + wire [63:0] _T_1014 = {32'h0,io_store_data_m}; // @[Cat.scala 29:58] + wire [126:0] _GEN_51 = {{63'd0}, _T_1014}; // @[lsu_dccm_ctl.scala 258:72] + wire [126:0] _T_1017 = _GEN_51 << _T_823; // @[lsu_dccm_ctl.scala 258:72] + wire [63:0] store_data_pre_m = _T_1017[63:0]; // @[lsu_dccm_ctl.scala 258:29] + wire [31:0] store_data_hi_m = store_data_pre_m[63:32]; // @[lsu_dccm_ctl.scala 259:48] + wire [31:0] store_data_lo_m = store_data_pre_m[31:0]; // @[lsu_dccm_ctl.scala 260:48] + wire [7:0] store_byteen_ext_m = {{1'd0}, _T_996}; // @[lsu_dccm_ctl.scala 220:22] + wire _T_1023 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo; // @[lsu_dccm_ctl.scala 261:211] + wire [7:0] _T_1027 = _T_1023 ? io_stbuf_data_any[7:0] : io_sec_data_lo_m[7:0]; // @[lsu_dccm_ctl.scala 261:185] + wire [7:0] _T_1028 = store_byteen_ext_m[0] ? store_data_lo_m[7:0] : _T_1027; // @[lsu_dccm_ctl.scala 261:120] + wire [7:0] _T_1032 = {{4'd0}, _T_1028[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1034 = {_T_1028[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1036 = _T_1034 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1037 = _T_1032 | _T_1036; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_52 = {{2'd0}, _T_1037[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1042 = _GEN_52 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1044 = {_T_1037[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1046 = _T_1044 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1047 = _T_1042 | _T_1046; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_53 = {{1'd0}, _T_1047[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1052 = _GEN_53 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1054 = {_T_1047[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1056 = _T_1054 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1057 = _T_1052 | _T_1056; // @[Bitwise.scala 103:39] + wire [7:0] _T_1065 = _T_1023 ? io_stbuf_data_any[15:8] : io_sec_data_lo_m[15:8]; // @[lsu_dccm_ctl.scala 261:185] + wire [7:0] _T_1066 = store_byteen_ext_m[1] ? store_data_lo_m[15:8] : _T_1065; // @[lsu_dccm_ctl.scala 261:120] + wire [7:0] _T_1070 = {{4'd0}, _T_1066[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1072 = {_T_1066[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1074 = _T_1072 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1075 = _T_1070 | _T_1074; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_54 = {{2'd0}, _T_1075[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1080 = _GEN_54 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1082 = {_T_1075[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1084 = _T_1082 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1085 = _T_1080 | _T_1084; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_55 = {{1'd0}, _T_1085[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1090 = _GEN_55 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1092 = {_T_1085[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1094 = _T_1092 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1095 = _T_1090 | _T_1094; // @[Bitwise.scala 103:39] + wire [7:0] _T_1103 = _T_1023 ? io_stbuf_data_any[23:16] : io_sec_data_lo_m[23:16]; // @[lsu_dccm_ctl.scala 261:185] + wire [7:0] _T_1104 = store_byteen_ext_m[2] ? store_data_lo_m[23:16] : _T_1103; // @[lsu_dccm_ctl.scala 261:120] + wire [7:0] _T_1108 = {{4'd0}, _T_1104[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1110 = {_T_1104[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1112 = _T_1110 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1113 = _T_1108 | _T_1112; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_56 = {{2'd0}, _T_1113[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1118 = _GEN_56 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1120 = {_T_1113[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1122 = _T_1120 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1123 = _T_1118 | _T_1122; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_57 = {{1'd0}, _T_1123[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1128 = _GEN_57 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1130 = {_T_1123[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1132 = _T_1130 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1133 = _T_1128 | _T_1132; // @[Bitwise.scala 103:39] + wire [7:0] _T_1141 = _T_1023 ? io_stbuf_data_any[31:24] : io_sec_data_lo_m[31:24]; // @[lsu_dccm_ctl.scala 261:185] + wire [7:0] _T_1142 = store_byteen_ext_m[3] ? store_data_lo_m[31:24] : _T_1141; // @[lsu_dccm_ctl.scala 261:120] + wire [7:0] _T_1146 = {{4'd0}, _T_1142[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1148 = {_T_1142[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1150 = _T_1148 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1151 = _T_1146 | _T_1150; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_58 = {{2'd0}, _T_1151[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1156 = _GEN_58 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1158 = {_T_1151[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1160 = _T_1158 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1161 = _T_1156 | _T_1160; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_59 = {{1'd0}, _T_1161[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1166 = _GEN_59 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1168 = {_T_1161[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1170 = _T_1168 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1171 = _T_1166 | _T_1170; // @[Bitwise.scala 103:39] + wire [31:0] _T_1175 = {_T_1057,_T_1095,_T_1133,_T_1171}; // @[Cat.scala 29:58] + wire [31:0] _T_1179 = {{16'd0}, _T_1175[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1181 = {_T_1175[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1183 = _T_1181 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1184 = _T_1179 | _T_1183; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_60 = {{8'd0}, _T_1184[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1189 = _GEN_60 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1191 = {_T_1184[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1193 = _T_1191 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1194 = _T_1189 | _T_1193; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_61 = {{4'd0}, _T_1194[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1199 = _GEN_61 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1201 = {_T_1194[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1203 = _T_1201 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1204 = _T_1199 | _T_1203; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_62 = {{2'd0}, _T_1204[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1209 = _GEN_62 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1211 = {_T_1204[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1213 = _T_1211 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1214 = _T_1209 | _T_1213; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_63 = {{1'd0}, _T_1214[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1219 = _GEN_63 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1221 = {_T_1214[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1223 = _T_1221 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + reg [31:0] _T_1225; // @[lsu_dccm_ctl.scala 261:72] + wire _T_1229 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi; // @[lsu_dccm_ctl.scala 262:177] + wire [7:0] _T_1233 = _T_1229 ? io_stbuf_data_any[7:0] : io_sec_data_hi_m[7:0]; // @[lsu_dccm_ctl.scala 262:151] + wire [7:0] _T_1234 = store_byteen_ext_m[4] ? store_data_hi_m[7:0] : _T_1233; // @[lsu_dccm_ctl.scala 262:86] + wire [7:0] _T_1238 = {{4'd0}, _T_1234[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1240 = {_T_1234[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1242 = _T_1240 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1243 = _T_1238 | _T_1242; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_64 = {{2'd0}, _T_1243[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1248 = _GEN_64 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1250 = {_T_1243[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1252 = _T_1250 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1253 = _T_1248 | _T_1252; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_65 = {{1'd0}, _T_1253[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1258 = _GEN_65 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1260 = {_T_1253[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1262 = _T_1260 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1263 = _T_1258 | _T_1262; // @[Bitwise.scala 103:39] + wire [7:0] _T_1271 = _T_1229 ? io_stbuf_data_any[15:8] : io_sec_data_hi_m[15:8]; // @[lsu_dccm_ctl.scala 262:151] + wire [7:0] _T_1272 = store_byteen_ext_m[5] ? store_data_hi_m[15:8] : _T_1271; // @[lsu_dccm_ctl.scala 262:86] + wire [7:0] _T_1276 = {{4'd0}, _T_1272[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1278 = {_T_1272[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1280 = _T_1278 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1281 = _T_1276 | _T_1280; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_66 = {{2'd0}, _T_1281[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1286 = _GEN_66 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1288 = {_T_1281[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1290 = _T_1288 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1291 = _T_1286 | _T_1290; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_67 = {{1'd0}, _T_1291[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1296 = _GEN_67 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1298 = {_T_1291[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1300 = _T_1298 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1301 = _T_1296 | _T_1300; // @[Bitwise.scala 103:39] + wire [7:0] _T_1309 = _T_1229 ? io_stbuf_data_any[23:16] : io_sec_data_hi_m[23:16]; // @[lsu_dccm_ctl.scala 262:151] + wire [7:0] _T_1310 = store_byteen_ext_m[6] ? store_data_hi_m[23:16] : _T_1309; // @[lsu_dccm_ctl.scala 262:86] + wire [7:0] _T_1314 = {{4'd0}, _T_1310[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1316 = {_T_1310[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1318 = _T_1316 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1319 = _T_1314 | _T_1318; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_68 = {{2'd0}, _T_1319[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1324 = _GEN_68 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1326 = {_T_1319[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1328 = _T_1326 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1329 = _T_1324 | _T_1328; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_69 = {{1'd0}, _T_1329[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1334 = _GEN_69 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1336 = {_T_1329[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1338 = _T_1336 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1339 = _T_1334 | _T_1338; // @[Bitwise.scala 103:39] + wire [7:0] _T_1347 = _T_1229 ? io_stbuf_data_any[31:24] : io_sec_data_hi_m[31:24]; // @[lsu_dccm_ctl.scala 262:151] + wire [7:0] _T_1348 = store_byteen_ext_m[7] ? store_data_hi_m[31:24] : _T_1347; // @[lsu_dccm_ctl.scala 262:86] + wire [7:0] _T_1352 = {{4'd0}, _T_1348[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1354 = {_T_1348[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1356 = _T_1354 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1357 = _T_1352 | _T_1356; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_70 = {{2'd0}, _T_1357[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1362 = _GEN_70 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1364 = {_T_1357[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1366 = _T_1364 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1367 = _T_1362 | _T_1366; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_71 = {{1'd0}, _T_1367[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1372 = _GEN_71 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1374 = {_T_1367[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1376 = _T_1374 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1377 = _T_1372 | _T_1376; // @[Bitwise.scala 103:39] + wire [31:0] _T_1381 = {_T_1263,_T_1301,_T_1339,_T_1377}; // @[Cat.scala 29:58] + wire [31:0] _T_1385 = {{16'd0}, _T_1381[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1387 = {_T_1381[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1389 = _T_1387 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1390 = _T_1385 | _T_1389; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_72 = {{8'd0}, _T_1390[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1395 = _GEN_72 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1397 = {_T_1390[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1399 = _T_1397 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1400 = _T_1395 | _T_1399; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_73 = {{4'd0}, _T_1400[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1405 = _GEN_73 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1407 = {_T_1400[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1409 = _T_1407 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1410 = _T_1405 | _T_1409; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_74 = {{2'd0}, _T_1410[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1415 = _GEN_74 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1417 = {_T_1410[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1419 = _T_1417 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1420 = _T_1415 | _T_1419; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_75 = {{1'd0}, _T_1420[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1425 = _GEN_75 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1427 = {_T_1420[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1429 = _T_1427 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire [31:0] _T_1430 = _T_1425 | _T_1429; // @[Bitwise.scala 103:39] + wire _T_1431 = io_ldst_dual_m & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 262:295] + wire _T_1432 = _T_1431 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 262:316] + wire _T_1433 = _T_1432 | io_clk_override; // @[lsu_dccm_ctl.scala 262:343] + reg [31:0] _T_1436; // @[Reg.scala 27:20] + wire _T_1437 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[lsu_dccm_ctl.scala 263:105] + wire [7:0] store_byteen_ext_r = {{1'd0}, _T_999}; // @[lsu_dccm_ctl.scala 222:22] + wire _T_1439 = ~store_byteen_ext_r[0]; // @[lsu_dccm_ctl.scala 263:131] + wire _T_1440 = _T_1437 & _T_1439; // @[lsu_dccm_ctl.scala 263:129] + wire [7:0] _T_1444 = _T_1440 ? io_stbuf_data_any[7:0] : io_store_data_lo_r[7:0]; // @[lsu_dccm_ctl.scala 263:79] + wire [7:0] _T_1448 = {{4'd0}, _T_1444[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1450 = {_T_1444[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1452 = _T_1450 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1453 = _T_1448 | _T_1452; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_76 = {{2'd0}, _T_1453[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1458 = _GEN_76 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1460 = {_T_1453[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1462 = _T_1460 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1463 = _T_1458 | _T_1462; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_77 = {{1'd0}, _T_1463[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1468 = _GEN_77 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1470 = {_T_1463[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1472 = _T_1470 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1473 = _T_1468 | _T_1472; // @[Bitwise.scala 103:39] + wire _T_1476 = ~store_byteen_ext_r[1]; // @[lsu_dccm_ctl.scala 263:131] + wire _T_1477 = _T_1437 & _T_1476; // @[lsu_dccm_ctl.scala 263:129] + wire [7:0] _T_1481 = _T_1477 ? io_stbuf_data_any[15:8] : io_store_data_lo_r[15:8]; // @[lsu_dccm_ctl.scala 263:79] + wire [7:0] _T_1485 = {{4'd0}, _T_1481[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1487 = {_T_1481[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1489 = _T_1487 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1490 = _T_1485 | _T_1489; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_78 = {{2'd0}, _T_1490[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1495 = _GEN_78 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1497 = {_T_1490[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1499 = _T_1497 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1500 = _T_1495 | _T_1499; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_79 = {{1'd0}, _T_1500[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1505 = _GEN_79 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1507 = {_T_1500[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1509 = _T_1507 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1510 = _T_1505 | _T_1509; // @[Bitwise.scala 103:39] + wire _T_1513 = ~store_byteen_ext_r[2]; // @[lsu_dccm_ctl.scala 263:131] + wire _T_1514 = _T_1437 & _T_1513; // @[lsu_dccm_ctl.scala 263:129] + wire [7:0] _T_1518 = _T_1514 ? io_stbuf_data_any[23:16] : io_store_data_lo_r[23:16]; // @[lsu_dccm_ctl.scala 263:79] + wire [7:0] _T_1522 = {{4'd0}, _T_1518[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1524 = {_T_1518[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1526 = _T_1524 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1527 = _T_1522 | _T_1526; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_80 = {{2'd0}, _T_1527[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1532 = _GEN_80 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1534 = {_T_1527[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1536 = _T_1534 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1537 = _T_1532 | _T_1536; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_81 = {{1'd0}, _T_1537[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1542 = _GEN_81 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1544 = {_T_1537[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1546 = _T_1544 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1547 = _T_1542 | _T_1546; // @[Bitwise.scala 103:39] + wire _T_1550 = ~store_byteen_ext_r[3]; // @[lsu_dccm_ctl.scala 263:131] + wire _T_1551 = _T_1437 & _T_1550; // @[lsu_dccm_ctl.scala 263:129] + wire [7:0] _T_1555 = _T_1551 ? io_stbuf_data_any[31:24] : io_store_data_lo_r[31:24]; // @[lsu_dccm_ctl.scala 263:79] + wire [7:0] _T_1559 = {{4'd0}, _T_1555[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1561 = {_T_1555[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1563 = _T_1561 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1564 = _T_1559 | _T_1563; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_82 = {{2'd0}, _T_1564[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1569 = _GEN_82 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1571 = {_T_1564[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1573 = _T_1571 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1574 = _T_1569 | _T_1573; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_83 = {{1'd0}, _T_1574[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1579 = _GEN_83 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1581 = {_T_1574[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1583 = _T_1581 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1584 = _T_1579 | _T_1583; // @[Bitwise.scala 103:39] + wire [31:0] _T_1588 = {_T_1473,_T_1510,_T_1547,_T_1584}; // @[Cat.scala 29:58] + wire [31:0] _T_1592 = {{16'd0}, _T_1588[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1594 = {_T_1588[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1596 = _T_1594 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1597 = _T_1592 | _T_1596; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_84 = {{8'd0}, _T_1597[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1602 = _GEN_84 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1604 = {_T_1597[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1606 = _T_1604 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1607 = _T_1602 | _T_1606; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_85 = {{4'd0}, _T_1607[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1612 = _GEN_85 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1614 = {_T_1607[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1616 = _T_1614 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1617 = _T_1612 | _T_1616; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_86 = {{2'd0}, _T_1617[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1622 = _GEN_86 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1624 = {_T_1617[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1626 = _T_1624 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1627 = _T_1622 | _T_1626; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_87 = {{1'd0}, _T_1627[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1632 = _GEN_87 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1634 = {_T_1627[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1636 = _T_1634 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire _T_1638 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi; // @[lsu_dccm_ctl.scala 264:105] + wire _T_1640 = ~store_byteen_ext_r[4]; // @[lsu_dccm_ctl.scala 264:131] + wire _T_1641 = _T_1638 & _T_1640; // @[lsu_dccm_ctl.scala 264:129] + wire [7:0] _T_1645 = _T_1641 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[lsu_dccm_ctl.scala 264:79] + wire [7:0] _T_1649 = {{4'd0}, _T_1645[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1651 = {_T_1645[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1653 = _T_1651 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1654 = _T_1649 | _T_1653; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_88 = {{2'd0}, _T_1654[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1659 = _GEN_88 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1661 = {_T_1654[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1663 = _T_1661 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1664 = _T_1659 | _T_1663; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_89 = {{1'd0}, _T_1664[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1669 = _GEN_89 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1671 = {_T_1664[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1673 = _T_1671 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1674 = _T_1669 | _T_1673; // @[Bitwise.scala 103:39] + wire _T_1677 = ~store_byteen_ext_r[5]; // @[lsu_dccm_ctl.scala 264:131] + wire _T_1678 = _T_1638 & _T_1677; // @[lsu_dccm_ctl.scala 264:129] + wire [7:0] _T_1682 = _T_1678 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[lsu_dccm_ctl.scala 264:79] + wire [7:0] _T_1686 = {{4'd0}, _T_1682[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1688 = {_T_1682[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1690 = _T_1688 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1691 = _T_1686 | _T_1690; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_90 = {{2'd0}, _T_1691[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1696 = _GEN_90 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1698 = {_T_1691[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1700 = _T_1698 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1701 = _T_1696 | _T_1700; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_91 = {{1'd0}, _T_1701[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1706 = _GEN_91 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1708 = {_T_1701[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1710 = _T_1708 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1711 = _T_1706 | _T_1710; // @[Bitwise.scala 103:39] + wire _T_1714 = ~store_byteen_ext_r[6]; // @[lsu_dccm_ctl.scala 264:131] + wire _T_1715 = _T_1638 & _T_1714; // @[lsu_dccm_ctl.scala 264:129] + wire [7:0] _T_1719 = _T_1715 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[lsu_dccm_ctl.scala 264:79] + wire [7:0] _T_1723 = {{4'd0}, _T_1719[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1725 = {_T_1719[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1727 = _T_1725 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1728 = _T_1723 | _T_1727; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_92 = {{2'd0}, _T_1728[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1733 = _GEN_92 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1735 = {_T_1728[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1737 = _T_1735 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1738 = _T_1733 | _T_1737; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_93 = {{1'd0}, _T_1738[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1743 = _GEN_93 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1745 = {_T_1738[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1747 = _T_1745 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1748 = _T_1743 | _T_1747; // @[Bitwise.scala 103:39] + wire _T_1751 = ~store_byteen_ext_r[7]; // @[lsu_dccm_ctl.scala 264:131] + wire _T_1752 = _T_1638 & _T_1751; // @[lsu_dccm_ctl.scala 264:129] + wire [7:0] _T_1756 = _T_1752 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[lsu_dccm_ctl.scala 264:79] + wire [7:0] _T_1760 = {{4'd0}, _T_1756[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1762 = {_T_1756[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1764 = _T_1762 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1765 = _T_1760 | _T_1764; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_94 = {{2'd0}, _T_1765[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1770 = _GEN_94 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1772 = {_T_1765[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1774 = _T_1772 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1775 = _T_1770 | _T_1774; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_95 = {{1'd0}, _T_1775[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1780 = _GEN_95 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1782 = {_T_1775[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1784 = _T_1782 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1785 = _T_1780 | _T_1784; // @[Bitwise.scala 103:39] + wire [31:0] _T_1789 = {_T_1674,_T_1711,_T_1748,_T_1785}; // @[Cat.scala 29:58] + wire [31:0] _T_1793 = {{16'd0}, _T_1789[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1795 = {_T_1789[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1797 = _T_1795 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1798 = _T_1793 | _T_1797; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_96 = {{8'd0}, _T_1798[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1803 = _GEN_96 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1805 = {_T_1798[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1807 = _T_1805 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1808 = _T_1803 | _T_1807; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_97 = {{4'd0}, _T_1808[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1813 = _GEN_97 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1815 = {_T_1808[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1817 = _T_1815 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1818 = _T_1813 | _T_1817; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_98 = {{2'd0}, _T_1818[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1823 = _GEN_98 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1825 = {_T_1818[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1827 = _T_1825 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1828 = _T_1823 | _T_1827; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_99 = {{1'd0}, _T_1828[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1833 = _GEN_99 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1835 = {_T_1828[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1837 = _T_1835 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] _T_1841 = {io_store_data_hi_r,io_store_data_lo_r}; // @[Cat.scala 29:58] + wire [3:0] _GEN_100 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[lsu_dccm_ctl.scala 265:94] + wire [5:0] _T_1843 = 4'h8 * _GEN_100; // @[lsu_dccm_ctl.scala 265:94] + wire [63:0] _T_1844 = _T_1841 >> _T_1843; // @[lsu_dccm_ctl.scala 265:88] + wire [7:0] _T_1847 = store_byteen_r[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1850 = store_byteen_r[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1853 = store_byteen_r[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1856 = store_byteen_r[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1860 = {_T_1847,_T_1850,_T_1853,_T_1856}; // @[Cat.scala 29:58] + wire [31:0] _T_1864 = {{16'd0}, _T_1860[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1866 = {_T_1860[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1868 = _T_1866 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1869 = _T_1864 | _T_1868; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_101 = {{8'd0}, _T_1869[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1874 = _GEN_101 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1876 = {_T_1869[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1878 = _T_1876 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1879 = _T_1874 | _T_1878; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_102 = {{4'd0}, _T_1879[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1884 = _GEN_102 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1886 = {_T_1879[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1888 = _T_1886 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1889 = _T_1884 | _T_1888; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_103 = {{2'd0}, _T_1889[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1894 = _GEN_103 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1896 = {_T_1889[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1898 = _T_1896 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1899 = _T_1894 | _T_1898; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_104 = {{1'd0}, _T_1899[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1904 = _GEN_104 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1906 = {_T_1899[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1908 = _T_1906 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire [31:0] _T_1909 = _T_1904 | _T_1908; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_105 = {{32'd0}, _T_1909}; // @[lsu_dccm_ctl.scala 265:115] + wire [63:0] _T_1910 = _T_1844 & _GEN_105; // @[lsu_dccm_ctl.scala 265:115] + wire _T_1915 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_dccm_ctl.scala 272:58] + wire _T_1916 = _T_1915 & io_addr_in_pic_r; // @[lsu_dccm_ctl.scala 272:84] + wire _T_1917 = _T_1916 & io_lsu_commit_r; // @[lsu_dccm_ctl.scala 272:103] + wire _T_1919 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_load; // @[lsu_dccm_ctl.scala 273:58] + wire _T_1921 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 274:58] + wire [31:0] _T_1925 = {17'h0,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58] + wire [14:0] _T_1931 = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[lsu_dccm_ctl.scala 276:93] + wire [31:0] _T_1932 = {17'h0,_T_1931}; // @[Cat.scala 29:58] + reg _T_1939; // @[lsu_dccm_ctl.scala 280:61] + wire _T_1945 = io_ld_single_ecc_error_r | io_clk_override; // @[lsu_dccm_ctl.scala 285:90] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + assign io_lsu_ld_data_corr_r = _T_818[31:0]; // @[lsu_dccm_ctl.scala 157:28] + assign io_dccm_rdata_hi_m = io_dccm_rd_data_hi[31:0]; // @[lsu_dccm_ctl.scala 268:27] + assign io_dccm_rdata_lo_m = io_dccm_rd_data_lo[31:0]; // @[lsu_dccm_ctl.scala 267:27] + assign io_dccm_data_ecc_hi_m = io_dccm_rd_data_hi[38:32]; // @[lsu_dccm_ctl.scala 270:27] + assign io_dccm_data_ecc_lo_m = io_dccm_rd_data_lo[38:32]; // @[lsu_dccm_ctl.scala 269:27] + assign io_lsu_ld_data_m = _T_821[31:0]; // @[lsu_dccm_ctl.scala 121:20 lsu_dccm_ctl.scala 158:28] + assign io_store_data_hi_r = _T_1436; // @[lsu_dccm_ctl.scala 262:29] + assign io_store_data_lo_r = _T_1225; // @[lsu_dccm_ctl.scala 261:29] + assign io_store_datafn_hi_r = _T_1833 | _T_1837; // @[lsu_dccm_ctl.scala 264:29] + assign io_store_datafn_lo_r = _T_1632 | _T_1636; // @[lsu_dccm_ctl.scala 263:29] + assign io_store_data_r = _T_1910[31:0]; // @[lsu_dccm_ctl.scala 265:29] + assign io_ld_single_ecc_error_r = _T_873 & _T_874; // @[lsu_dccm_ctl.scala 171:34] + assign io_ld_single_ecc_error_r_ff = _T_890 & _T_891; // @[lsu_dccm_ctl.scala 178:31] + assign io_picm_mask_data_m = picm_rd_data_m[31:0]; // @[lsu_dccm_ctl.scala 277:27] + assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_905; // @[lsu_dccm_ctl.scala 179:31] + assign io_lsu_dccm_rden_m = _T_1939; // @[lsu_dccm_ctl.scala 280:24] + assign io_dma_dccm_ctl_dccm_dma_rvalid = _T & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 145:41] + assign io_dma_dccm_ctl_dccm_dma_ecc_error = io_lsu_double_ecc_error_m; // @[lsu_dccm_ctl.scala 146:41] + assign io_dma_dccm_ctl_dccm_dma_rtag = io_dma_mem_tag_m; // @[lsu_dccm_ctl.scala 148:41] + assign io_dma_dccm_ctl_dccm_dma_rdata = io_ldst_dual_m ? lsu_rdata_corr_m : _T_4; // @[lsu_dccm_ctl.scala 147:41] + assign io_dccm_wren = _T_907 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 185:22] + assign io_dccm_rden = lsu_dccm_rden_d & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 186:22] + assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_914 : _T_918; // @[lsu_dccm_ctl.scala 188:22] + assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_924 : _T_928; // @[lsu_dccm_ctl.scala 192:22] + assign io_dccm_rd_addr_lo = io_lsu_addr_d[15:0]; // @[lsu_dccm_ctl.scala 196:22] + assign io_dccm_rd_addr_hi = io_end_addr_d; // @[lsu_dccm_ctl.scala 197:22] + assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_940 : _T_948; // @[lsu_dccm_ctl.scala 199:22] + assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_958 : _T_966; // @[lsu_dccm_ctl.scala 205:22] + assign io_lsu_pic_picm_wren = _T_1917 | io_dma_pic_wen; // @[lsu_dccm_ctl.scala 272:35] + assign io_lsu_pic_picm_rden = _T_1919 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 273:35] + assign io_lsu_pic_picm_mken = _T_1921 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 274:35] + assign io_lsu_pic_picm_rdaddr = 32'hf00c0000 | _T_1925; // @[lsu_dccm_ctl.scala 275:35] + assign io_lsu_pic_picm_wraddr = 32'hf00c0000 | _T_1932; // @[lsu_dccm_ctl.scala 276:35] + assign io_lsu_pic_picm_wr_data = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[lsu_dccm_ctl.scala 278:35] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = _T_814 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_1432 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {2{`RANDOM}}; + _T_818 = _RAND_0[63:0]; + _RAND_1 = {1{`RANDOM}}; + ld_single_ecc_error_lo_r_ff = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + ld_single_ecc_error_hi_r_ff = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + lsu_double_ecc_error_r_ff = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ld_sec_addr_lo_r_ff = _RAND_4[15:0]; + _RAND_5 = {1{`RANDOM}}; + ld_sec_addr_hi_r_ff = _RAND_5[15:0]; + _RAND_6 = {1{`RANDOM}}; + _T_1225 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + _T_1436 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + _T_1939 = _RAND_8[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_818 = 64'h0; + end + if (reset) begin + ld_single_ecc_error_lo_r_ff = 1'h0; + end + if (reset) begin + ld_single_ecc_error_hi_r_ff = 1'h0; + end + if (reset) begin + lsu_double_ecc_error_r_ff = 1'h0; + end + if (reset) begin + ld_sec_addr_lo_r_ff = 16'h0; + end + if (reset) begin + ld_sec_addr_hi_r_ff = 16'h0; + end + if (reset) begin + _T_1225 = 32'h0; + end + if (reset) begin + _T_1436 = 32'h0; + end + if (reset) begin + _T_1939 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_818 <= 64'h0; + end else if (_T_815) begin + _T_818 <= lsu_ld_data_corr_m; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ld_single_ecc_error_lo_r_ff <= 1'h0; + end else begin + ld_single_ecc_error_lo_r_ff <= _T_877 & _T_878; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ld_single_ecc_error_hi_r_ff <= 1'h0; + end else begin + ld_single_ecc_error_hi_r_ff <= _T_880 & _T_881; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + lsu_double_ecc_error_r_ff <= 1'h0; + end else begin + lsu_double_ecc_error_r_ff <= io_lsu_double_ecc_error_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ld_sec_addr_lo_r_ff <= 16'h0; + end else if (_T_1945) begin + ld_sec_addr_lo_r_ff <= io_lsu_addr_r[15:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ld_sec_addr_hi_r_ff <= 16'h0; + end else if (_T_1945) begin + ld_sec_addr_hi_r_ff <= io_end_addr_r; + end + end + always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin + if (reset) begin + _T_1225 <= 32'h0; + end else begin + _T_1225 <= _T_1219 | _T_1223; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1436 <= 32'h0; + end else if (_T_1433) begin + _T_1436 <= _T_1430; + end + end + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_1939 <= 1'h0; + end else begin + _T_1939 <= _T_889 & io_addr_in_dccm_d; + end + end +endmodule +module lsu_stbuf( + input clock, + input reset, + input io_lsu_stbuf_c1_clk, + input io_lsu_free_c2_clk, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_dword, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_dma, + input io_store_stbuf_reqvld_r, + input io_lsu_commit_r, + input io_dec_lsu_valid_raw_d, + input [31:0] io_store_data_hi_r, + input [31:0] io_store_data_lo_r, + input [31:0] io_store_datafn_hi_r, + input [31:0] io_store_datafn_lo_r, + input io_lsu_stbuf_commit_any, + input [31:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_m, + input [31:0] io_end_addr_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input io_addr_in_dccm_m, + input io_addr_in_dccm_r, + output io_stbuf_reqvld_any, + output io_stbuf_reqvld_flushed_any, + output [15:0] io_stbuf_addr_any, + output [31:0] io_stbuf_data_any, + output io_lsu_stbuf_full_any, + output io_ldst_stbuf_reqvld_r, + output [31:0] io_stbuf_fwddata_hi_m, + output [31:0] io_stbuf_fwddata_lo_m, + output [3:0] io_stbuf_fwdbyteen_hi_m, + output [3:0] io_stbuf_fwdbyteen_lo_m +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire [1:0] _T_5 = io_lsu_pkt_r_bits_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [7:0] _T_7 = io_lsu_pkt_r_bits_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_18 = {{1'd0}, io_lsu_pkt_r_bits_by}; // @[Mux.scala 27:72] + wire [1:0] _T_8 = _GEN_18 | _T_5; // @[Mux.scala 27:72] + wire [3:0] _GEN_19 = {{2'd0}, _T_8}; // @[Mux.scala 27:72] + wire [3:0] _T_9 = _GEN_19 | _T_6; // @[Mux.scala 27:72] + wire [7:0] _GEN_20 = {{4'd0}, _T_9}; // @[Mux.scala 27:72] + wire [7:0] ldst_byteen_r = _GEN_20 | _T_7; // @[Mux.scala 27:72] + wire dual_stbuf_write_r = io_ldst_dual_r & io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 115:43] + wire [10:0] _GEN_21 = {{3'd0}, ldst_byteen_r}; // @[lsu_stbuf.scala 117:39] + wire [10:0] _T_12 = _GEN_21 << io_lsu_addr_r[1:0]; // @[lsu_stbuf.scala 117:39] + wire [7:0] store_byteen_ext_r = _T_12[7:0]; // @[lsu_stbuf.scala 117:22] + wire [3:0] _T_15 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_15; // @[lsu_stbuf.scala 118:52] + wire [3:0] store_byteen_lo_r = store_byteen_ext_r[3:0] & _T_15; // @[lsu_stbuf.scala 119:52] + reg [1:0] RdPtr; // @[Reg.scala 27:20] + wire [1:0] RdPtrPlus1 = RdPtr + 2'h1; // @[lsu_stbuf.scala 121:26] + reg [1:0] WrPtr; // @[Reg.scala 27:20] + wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[lsu_stbuf.scala 122:26] + wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[lsu_stbuf.scala 123:26] + wire _T_22 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_stbuf.scala 125:46] + reg [15:0] stbuf_addr_0; // @[Reg.scala 27:20] + wire _T_26 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120] + reg _T_587; // @[lsu_stbuf.scala 160:14] + reg _T_579; // @[lsu_stbuf.scala 160:14] + reg _T_571; // @[lsu_stbuf.scala 160:14] + reg _T_563; // @[lsu_stbuf.scala 160:14] + wire [3:0] stbuf_vld = {_T_587,_T_579,_T_571,_T_563}; // @[Cat.scala 29:58] + wire _T_28 = _T_26 & stbuf_vld[0]; // @[lsu_stbuf.scala 127:179] + reg _T_622; // @[lsu_stbuf.scala 163:14] + reg _T_614; // @[lsu_stbuf.scala 163:14] + reg _T_606; // @[lsu_stbuf.scala 163:14] + reg _T_598; // @[lsu_stbuf.scala 163:14] + wire [3:0] stbuf_dma_kill = {_T_622,_T_614,_T_606,_T_598}; // @[Cat.scala 29:58] + wire _T_30 = ~stbuf_dma_kill[0]; // @[lsu_stbuf.scala 127:197] + wire _T_31 = _T_28 & _T_30; // @[lsu_stbuf.scala 127:195] + wire _T_211 = io_lsu_stbuf_commit_any | io_stbuf_reqvld_flushed_any; // @[lsu_stbuf.scala 138:81] + wire _T_212 = 2'h3 == RdPtr; // @[lsu_stbuf.scala 138:124] + wire _T_214 = _T_211 & _T_212; // @[lsu_stbuf.scala 138:112] + wire _T_208 = 2'h2 == RdPtr; // @[lsu_stbuf.scala 138:124] + wire _T_210 = _T_211 & _T_208; // @[lsu_stbuf.scala 138:112] + wire _T_204 = 2'h1 == RdPtr; // @[lsu_stbuf.scala 138:124] + wire _T_206 = _T_211 & _T_204; // @[lsu_stbuf.scala 138:112] + wire _T_200 = 2'h0 == RdPtr; // @[lsu_stbuf.scala 138:124] + wire _T_202 = _T_211 & _T_200; // @[lsu_stbuf.scala 138:112] + wire [3:0] stbuf_reset = {_T_214,_T_210,_T_206,_T_202}; // @[Cat.scala 29:58] + wire _T_33 = ~stbuf_reset[0]; // @[lsu_stbuf.scala 127:218] + wire _T_34 = _T_31 & _T_33; // @[lsu_stbuf.scala 127:216] + reg [15:0] stbuf_addr_1; // @[Reg.scala 27:20] + wire _T_37 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120] + wire _T_39 = _T_37 & stbuf_vld[1]; // @[lsu_stbuf.scala 127:179] + wire _T_41 = ~stbuf_dma_kill[1]; // @[lsu_stbuf.scala 127:197] + wire _T_42 = _T_39 & _T_41; // @[lsu_stbuf.scala 127:195] + wire _T_44 = ~stbuf_reset[1]; // @[lsu_stbuf.scala 127:218] + wire _T_45 = _T_42 & _T_44; // @[lsu_stbuf.scala 127:216] + reg [15:0] stbuf_addr_2; // @[Reg.scala 27:20] + wire _T_48 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120] + wire _T_50 = _T_48 & stbuf_vld[2]; // @[lsu_stbuf.scala 127:179] + wire _T_52 = ~stbuf_dma_kill[2]; // @[lsu_stbuf.scala 127:197] + wire _T_53 = _T_50 & _T_52; // @[lsu_stbuf.scala 127:195] + wire _T_55 = ~stbuf_reset[2]; // @[lsu_stbuf.scala 127:218] + wire _T_56 = _T_53 & _T_55; // @[lsu_stbuf.scala 127:216] + reg [15:0] stbuf_addr_3; // @[Reg.scala 27:20] + wire _T_59 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120] + wire _T_61 = _T_59 & stbuf_vld[3]; // @[lsu_stbuf.scala 127:179] + wire _T_63 = ~stbuf_dma_kill[3]; // @[lsu_stbuf.scala 127:197] + wire _T_64 = _T_61 & _T_63; // @[lsu_stbuf.scala 127:195] + wire _T_66 = ~stbuf_reset[3]; // @[lsu_stbuf.scala 127:218] + wire _T_67 = _T_64 & _T_66; // @[lsu_stbuf.scala 127:216] + wire [3:0] store_matchvec_lo_r = {_T_67,_T_56,_T_45,_T_34}; // @[Cat.scala 29:58] + wire _T_72 = stbuf_addr_0[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120] + wire _T_74 = _T_72 & stbuf_vld[0]; // @[lsu_stbuf.scala 128:179] + wire _T_77 = _T_74 & _T_30; // @[lsu_stbuf.scala 128:194] + wire _T_78 = _T_77 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215] + wire _T_81 = _T_78 & _T_33; // @[lsu_stbuf.scala 128:236] + wire _T_84 = stbuf_addr_1[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120] + wire _T_86 = _T_84 & stbuf_vld[1]; // @[lsu_stbuf.scala 128:179] + wire _T_89 = _T_86 & _T_41; // @[lsu_stbuf.scala 128:194] + wire _T_90 = _T_89 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215] + wire _T_93 = _T_90 & _T_44; // @[lsu_stbuf.scala 128:236] + wire _T_96 = stbuf_addr_2[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120] + wire _T_98 = _T_96 & stbuf_vld[2]; // @[lsu_stbuf.scala 128:179] + wire _T_101 = _T_98 & _T_52; // @[lsu_stbuf.scala 128:194] + wire _T_102 = _T_101 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215] + wire _T_105 = _T_102 & _T_55; // @[lsu_stbuf.scala 128:236] + wire _T_108 = stbuf_addr_3[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120] + wire _T_110 = _T_108 & stbuf_vld[3]; // @[lsu_stbuf.scala 128:179] + wire _T_113 = _T_110 & _T_63; // @[lsu_stbuf.scala 128:194] + wire _T_114 = _T_113 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215] + wire _T_117 = _T_114 & _T_66; // @[lsu_stbuf.scala 128:236] + wire [3:0] store_matchvec_hi_r = {_T_117,_T_105,_T_93,_T_81}; // @[Cat.scala 29:58] + wire store_coalesce_lo_r = |store_matchvec_lo_r; // @[lsu_stbuf.scala 130:49] + wire store_coalesce_hi_r = |store_matchvec_hi_r; // @[lsu_stbuf.scala 131:49] + wire _T_120 = 2'h0 == WrPtr; // @[lsu_stbuf.scala 134:18] + wire _T_121 = ~store_coalesce_lo_r; // @[lsu_stbuf.scala 134:31] + wire _T_122 = _T_120 & _T_121; // @[lsu_stbuf.scala 134:29] + wire _T_124 = _T_120 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31] + wire _T_125 = ~store_coalesce_hi_r; // @[lsu_stbuf.scala 135:54] + wire _T_126 = _T_124 & _T_125; // @[lsu_stbuf.scala 135:52] + wire _T_127 = _T_122 | _T_126; // @[lsu_stbuf.scala 134:53] + wire _T_128 = 2'h0 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20] + wire _T_129 = _T_128 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36] + wire _T_130 = store_coalesce_lo_r | store_coalesce_hi_r; // @[lsu_stbuf.scala 136:81] + wire _T_131 = ~_T_130; // @[lsu_stbuf.scala 136:59] + wire _T_132 = _T_129 & _T_131; // @[lsu_stbuf.scala 136:57] + wire _T_133 = _T_127 | _T_132; // @[lsu_stbuf.scala 135:76] + wire _T_135 = _T_133 | store_matchvec_lo_r[0]; // @[lsu_stbuf.scala 136:105] + wire _T_137 = _T_135 | store_matchvec_hi_r[0]; // @[lsu_stbuf.scala 137:32] + wire _T_138 = io_ldst_stbuf_reqvld_r & _T_137; // @[lsu_stbuf.scala 133:79] + wire _T_139 = 2'h1 == WrPtr; // @[lsu_stbuf.scala 134:18] + wire _T_141 = _T_139 & _T_121; // @[lsu_stbuf.scala 134:29] + wire _T_143 = _T_139 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31] + wire _T_145 = _T_143 & _T_125; // @[lsu_stbuf.scala 135:52] + wire _T_146 = _T_141 | _T_145; // @[lsu_stbuf.scala 134:53] + wire _T_147 = 2'h1 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20] + wire _T_148 = _T_147 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36] + wire _T_151 = _T_148 & _T_131; // @[lsu_stbuf.scala 136:57] + wire _T_152 = _T_146 | _T_151; // @[lsu_stbuf.scala 135:76] + wire _T_154 = _T_152 | store_matchvec_lo_r[1]; // @[lsu_stbuf.scala 136:105] + wire _T_156 = _T_154 | store_matchvec_hi_r[1]; // @[lsu_stbuf.scala 137:32] + wire _T_157 = io_ldst_stbuf_reqvld_r & _T_156; // @[lsu_stbuf.scala 133:79] + wire _T_158 = 2'h2 == WrPtr; // @[lsu_stbuf.scala 134:18] + wire _T_160 = _T_158 & _T_121; // @[lsu_stbuf.scala 134:29] + wire _T_162 = _T_158 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31] + wire _T_164 = _T_162 & _T_125; // @[lsu_stbuf.scala 135:52] + wire _T_165 = _T_160 | _T_164; // @[lsu_stbuf.scala 134:53] + wire _T_166 = 2'h2 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20] + wire _T_167 = _T_166 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36] + wire _T_170 = _T_167 & _T_131; // @[lsu_stbuf.scala 136:57] + wire _T_171 = _T_165 | _T_170; // @[lsu_stbuf.scala 135:76] + wire _T_173 = _T_171 | store_matchvec_lo_r[2]; // @[lsu_stbuf.scala 136:105] + wire _T_175 = _T_173 | store_matchvec_hi_r[2]; // @[lsu_stbuf.scala 137:32] + wire _T_176 = io_ldst_stbuf_reqvld_r & _T_175; // @[lsu_stbuf.scala 133:79] + wire _T_177 = 2'h3 == WrPtr; // @[lsu_stbuf.scala 134:18] + wire _T_179 = _T_177 & _T_121; // @[lsu_stbuf.scala 134:29] + wire _T_181 = _T_177 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31] + wire _T_183 = _T_181 & _T_125; // @[lsu_stbuf.scala 135:52] + wire _T_184 = _T_179 | _T_183; // @[lsu_stbuf.scala 134:53] + wire _T_185 = 2'h3 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20] + wire _T_186 = _T_185 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36] + wire _T_189 = _T_186 & _T_131; // @[lsu_stbuf.scala 136:57] + wire _T_190 = _T_184 | _T_189; // @[lsu_stbuf.scala 135:76] + wire _T_192 = _T_190 | store_matchvec_lo_r[3]; // @[lsu_stbuf.scala 136:105] + wire _T_194 = _T_192 | store_matchvec_hi_r[3]; // @[lsu_stbuf.scala 137:32] + wire _T_195 = io_ldst_stbuf_reqvld_r & _T_194; // @[lsu_stbuf.scala 133:79] + wire [3:0] stbuf_wr_en = {_T_195,_T_176,_T_157,_T_138}; // @[Cat.scala 29:58] + wire _T_218 = ~io_ldst_dual_r; // @[lsu_stbuf.scala 139:56] + wire _T_219 = _T_218 | io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 139:72] + wire _T_222 = _T_219 & _T_120; // @[lsu_stbuf.scala 139:99] + wire _T_224 = _T_222 & _T_121; // @[lsu_stbuf.scala 139:129] + wire _T_226 = _T_224 | store_matchvec_lo_r[0]; // @[lsu_stbuf.scala 139:153] + wire _T_231 = _T_219 & _T_139; // @[lsu_stbuf.scala 139:99] + wire _T_233 = _T_231 & _T_121; // @[lsu_stbuf.scala 139:129] + wire _T_235 = _T_233 | store_matchvec_lo_r[1]; // @[lsu_stbuf.scala 139:153] + wire _T_240 = _T_219 & _T_158; // @[lsu_stbuf.scala 139:99] + wire _T_242 = _T_240 & _T_121; // @[lsu_stbuf.scala 139:129] + wire _T_244 = _T_242 | store_matchvec_lo_r[2]; // @[lsu_stbuf.scala 139:153] + wire _T_249 = _T_219 & _T_177; // @[lsu_stbuf.scala 139:99] + wire _T_251 = _T_249 & _T_121; // @[lsu_stbuf.scala 139:129] + wire _T_253 = _T_251 | store_matchvec_lo_r[3]; // @[lsu_stbuf.scala 139:153] + wire [3:0] sel_lo = {_T_253,_T_244,_T_235,_T_226}; // @[Cat.scala 29:58] + reg [3:0] stbuf_byteen_0; // @[lsu_stbuf.scala 166:14] + wire [3:0] _T_273 = stbuf_byteen_0 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89] + wire [3:0] _T_274 = stbuf_byteen_0 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126] + wire [3:0] stbuf_byteenin_0 = sel_lo[0] ? _T_273 : _T_274; // @[lsu_stbuf.scala 142:61] + reg [3:0] stbuf_byteen_1; // @[lsu_stbuf.scala 166:14] + wire [3:0] _T_277 = stbuf_byteen_1 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89] + wire [3:0] _T_278 = stbuf_byteen_1 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126] + wire [3:0] stbuf_byteenin_1 = sel_lo[1] ? _T_277 : _T_278; // @[lsu_stbuf.scala 142:61] + reg [3:0] stbuf_byteen_2; // @[lsu_stbuf.scala 166:14] + wire [3:0] _T_281 = stbuf_byteen_2 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89] + wire [3:0] _T_282 = stbuf_byteen_2 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126] + wire [3:0] stbuf_byteenin_2 = sel_lo[2] ? _T_281 : _T_282; // @[lsu_stbuf.scala 142:61] + reg [3:0] stbuf_byteen_3; // @[lsu_stbuf.scala 166:14] + wire [3:0] _T_285 = stbuf_byteen_3 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89] + wire [3:0] _T_286 = stbuf_byteen_3 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126] + wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_285 : _T_286; // @[lsu_stbuf.scala 142:61] + wire _T_290 = ~stbuf_byteen_0[0]; // @[lsu_stbuf.scala 144:70] + wire _T_292 = _T_290 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90] + reg [31:0] stbuf_data_0; // @[Reg.scala 27:20] + wire [7:0] _T_295 = _T_292 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 144:69] + wire _T_299 = _T_290 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31] + wire [7:0] _T_302 = _T_299 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 145:10] + wire [7:0] datain1_0 = sel_lo[0] ? _T_295 : _T_302; // @[lsu_stbuf.scala 144:54] + wire _T_306 = ~stbuf_byteen_1[0]; // @[lsu_stbuf.scala 144:70] + wire _T_308 = _T_306 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90] + reg [31:0] stbuf_data_1; // @[Reg.scala 27:20] + wire [7:0] _T_311 = _T_308 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 144:69] + wire _T_315 = _T_306 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31] + wire [7:0] _T_318 = _T_315 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 145:10] + wire [7:0] datain1_1 = sel_lo[1] ? _T_311 : _T_318; // @[lsu_stbuf.scala 144:54] + wire _T_322 = ~stbuf_byteen_2[0]; // @[lsu_stbuf.scala 144:70] + wire _T_324 = _T_322 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90] + reg [31:0] stbuf_data_2; // @[Reg.scala 27:20] + wire [7:0] _T_327 = _T_324 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 144:69] + wire _T_331 = _T_322 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31] + wire [7:0] _T_334 = _T_331 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 145:10] + wire [7:0] datain1_2 = sel_lo[2] ? _T_327 : _T_334; // @[lsu_stbuf.scala 144:54] + wire _T_338 = ~stbuf_byteen_3[0]; // @[lsu_stbuf.scala 144:70] + wire _T_340 = _T_338 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90] + reg [31:0] stbuf_data_3; // @[Reg.scala 27:20] + wire [7:0] _T_343 = _T_340 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 144:69] + wire _T_347 = _T_338 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31] + wire [7:0] _T_350 = _T_347 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 145:10] + wire [7:0] datain1_3 = sel_lo[3] ? _T_343 : _T_350; // @[lsu_stbuf.scala 144:54] + wire _T_354 = ~stbuf_byteen_0[1]; // @[lsu_stbuf.scala 147:70] + wire _T_356 = _T_354 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90] + wire [7:0] _T_359 = _T_356 ? io_store_datafn_lo_r[15:8] : stbuf_data_0[15:8]; // @[lsu_stbuf.scala 147:69] + wire _T_363 = _T_354 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31] + wire [7:0] _T_366 = _T_363 ? io_store_datafn_hi_r[15:8] : stbuf_data_0[15:8]; // @[lsu_stbuf.scala 148:10] + wire [7:0] datain2_0 = sel_lo[0] ? _T_359 : _T_366; // @[lsu_stbuf.scala 147:54] + wire _T_370 = ~stbuf_byteen_1[1]; // @[lsu_stbuf.scala 147:70] + wire _T_372 = _T_370 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90] + wire [7:0] _T_375 = _T_372 ? io_store_datafn_lo_r[15:8] : stbuf_data_1[15:8]; // @[lsu_stbuf.scala 147:69] + wire _T_379 = _T_370 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31] + wire [7:0] _T_382 = _T_379 ? io_store_datafn_hi_r[15:8] : stbuf_data_1[15:8]; // @[lsu_stbuf.scala 148:10] + wire [7:0] datain2_1 = sel_lo[1] ? _T_375 : _T_382; // @[lsu_stbuf.scala 147:54] + wire _T_386 = ~stbuf_byteen_2[1]; // @[lsu_stbuf.scala 147:70] + wire _T_388 = _T_386 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90] + wire [7:0] _T_391 = _T_388 ? io_store_datafn_lo_r[15:8] : stbuf_data_2[15:8]; // @[lsu_stbuf.scala 147:69] + wire _T_395 = _T_386 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31] + wire [7:0] _T_398 = _T_395 ? io_store_datafn_hi_r[15:8] : stbuf_data_2[15:8]; // @[lsu_stbuf.scala 148:10] + wire [7:0] datain2_2 = sel_lo[2] ? _T_391 : _T_398; // @[lsu_stbuf.scala 147:54] + wire _T_402 = ~stbuf_byteen_3[1]; // @[lsu_stbuf.scala 147:70] + wire _T_404 = _T_402 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90] + wire [7:0] _T_407 = _T_404 ? io_store_datafn_lo_r[15:8] : stbuf_data_3[15:8]; // @[lsu_stbuf.scala 147:69] + wire _T_411 = _T_402 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31] + wire [7:0] _T_414 = _T_411 ? io_store_datafn_hi_r[15:8] : stbuf_data_3[15:8]; // @[lsu_stbuf.scala 148:10] + wire [7:0] datain2_3 = sel_lo[3] ? _T_407 : _T_414; // @[lsu_stbuf.scala 147:54] + wire _T_418 = ~stbuf_byteen_0[2]; // @[lsu_stbuf.scala 150:70] + wire _T_420 = _T_418 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90] + wire [7:0] _T_423 = _T_420 ? io_store_datafn_lo_r[23:16] : stbuf_data_0[23:16]; // @[lsu_stbuf.scala 150:69] + wire _T_427 = _T_418 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31] + wire [7:0] _T_430 = _T_427 ? io_store_datafn_hi_r[23:16] : stbuf_data_0[23:16]; // @[lsu_stbuf.scala 151:10] + wire [7:0] datain3_0 = sel_lo[0] ? _T_423 : _T_430; // @[lsu_stbuf.scala 150:54] + wire _T_434 = ~stbuf_byteen_1[2]; // @[lsu_stbuf.scala 150:70] + wire _T_436 = _T_434 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90] + wire [7:0] _T_439 = _T_436 ? io_store_datafn_lo_r[23:16] : stbuf_data_1[23:16]; // @[lsu_stbuf.scala 150:69] + wire _T_443 = _T_434 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31] + wire [7:0] _T_446 = _T_443 ? io_store_datafn_hi_r[23:16] : stbuf_data_1[23:16]; // @[lsu_stbuf.scala 151:10] + wire [7:0] datain3_1 = sel_lo[1] ? _T_439 : _T_446; // @[lsu_stbuf.scala 150:54] + wire _T_450 = ~stbuf_byteen_2[2]; // @[lsu_stbuf.scala 150:70] + wire _T_452 = _T_450 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90] + wire [7:0] _T_455 = _T_452 ? io_store_datafn_lo_r[23:16] : stbuf_data_2[23:16]; // @[lsu_stbuf.scala 150:69] + wire _T_459 = _T_450 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31] + wire [7:0] _T_462 = _T_459 ? io_store_datafn_hi_r[23:16] : stbuf_data_2[23:16]; // @[lsu_stbuf.scala 151:10] + wire [7:0] datain3_2 = sel_lo[2] ? _T_455 : _T_462; // @[lsu_stbuf.scala 150:54] + wire _T_466 = ~stbuf_byteen_3[2]; // @[lsu_stbuf.scala 150:70] + wire _T_468 = _T_466 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90] + wire [7:0] _T_471 = _T_468 ? io_store_datafn_lo_r[23:16] : stbuf_data_3[23:16]; // @[lsu_stbuf.scala 150:69] + wire _T_475 = _T_466 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31] + wire [7:0] _T_478 = _T_475 ? io_store_datafn_hi_r[23:16] : stbuf_data_3[23:16]; // @[lsu_stbuf.scala 151:10] + wire [7:0] datain3_3 = sel_lo[3] ? _T_471 : _T_478; // @[lsu_stbuf.scala 150:54] + wire _T_482 = ~stbuf_byteen_0[3]; // @[lsu_stbuf.scala 153:70] + wire _T_484 = _T_482 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90] + wire [7:0] _T_487 = _T_484 ? io_store_datafn_lo_r[31:24] : stbuf_data_0[31:24]; // @[lsu_stbuf.scala 153:69] + wire _T_491 = _T_482 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31] + wire [7:0] _T_494 = _T_491 ? io_store_datafn_hi_r[31:24] : stbuf_data_0[31:24]; // @[lsu_stbuf.scala 154:10] + wire [7:0] datain4_0 = sel_lo[0] ? _T_487 : _T_494; // @[lsu_stbuf.scala 153:54] + wire _T_498 = ~stbuf_byteen_1[3]; // @[lsu_stbuf.scala 153:70] + wire _T_500 = _T_498 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90] + wire [7:0] _T_503 = _T_500 ? io_store_datafn_lo_r[31:24] : stbuf_data_1[31:24]; // @[lsu_stbuf.scala 153:69] + wire _T_507 = _T_498 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31] + wire [7:0] _T_510 = _T_507 ? io_store_datafn_hi_r[31:24] : stbuf_data_1[31:24]; // @[lsu_stbuf.scala 154:10] + wire [7:0] datain4_1 = sel_lo[1] ? _T_503 : _T_510; // @[lsu_stbuf.scala 153:54] + wire _T_514 = ~stbuf_byteen_2[3]; // @[lsu_stbuf.scala 153:70] + wire _T_516 = _T_514 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90] + wire [7:0] _T_519 = _T_516 ? io_store_datafn_lo_r[31:24] : stbuf_data_2[31:24]; // @[lsu_stbuf.scala 153:69] + wire _T_523 = _T_514 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31] + wire [7:0] _T_526 = _T_523 ? io_store_datafn_hi_r[31:24] : stbuf_data_2[31:24]; // @[lsu_stbuf.scala 154:10] + wire [7:0] datain4_2 = sel_lo[2] ? _T_519 : _T_526; // @[lsu_stbuf.scala 153:54] + wire _T_530 = ~stbuf_byteen_3[3]; // @[lsu_stbuf.scala 153:70] + wire _T_532 = _T_530 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90] + wire [7:0] _T_535 = _T_532 ? io_store_datafn_lo_r[31:24] : stbuf_data_3[31:24]; // @[lsu_stbuf.scala 153:69] + wire _T_539 = _T_530 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31] + wire [7:0] _T_542 = _T_539 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[lsu_stbuf.scala 154:10] + wire [7:0] datain4_3 = sel_lo[3] ? _T_535 : _T_542; // @[lsu_stbuf.scala 153:54] + wire [31:0] stbuf_datain_0 = {datain4_0,datain3_0,datain2_0,datain1_0}; // @[Cat.scala 29:58] + wire [31:0] stbuf_datain_1 = {datain4_1,datain3_1,datain2_1,datain1_1}; // @[Cat.scala 29:58] + wire [31:0] stbuf_datain_2 = {datain4_2,datain3_2,datain2_2,datain1_2}; // @[Cat.scala 29:58] + wire [31:0] stbuf_datain_3 = {datain4_3,datain3_3,datain2_3,datain1_3}; // @[Cat.scala 29:58] + wire _T_559 = stbuf_wr_en[0] | stbuf_vld[0]; // @[lsu_stbuf.scala 160:18] + wire _T_567 = stbuf_wr_en[1] | stbuf_vld[1]; // @[lsu_stbuf.scala 160:18] + wire _T_575 = stbuf_wr_en[2] | stbuf_vld[2]; // @[lsu_stbuf.scala 160:18] + wire _T_583 = stbuf_wr_en[3] | stbuf_vld[3]; // @[lsu_stbuf.scala 160:18] + wire [15:0] cmpaddr_hi_m = {{2'd0}, io_end_addr_m[15:2]}; // @[lsu_stbuf.scala 208:16] + wire _T_786 = stbuf_addr_3[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115] + wire _T_788 = _T_786 & stbuf_vld[3]; // @[lsu_stbuf.scala 212:139] + wire _T_791 = _T_788 & _T_63; // @[lsu_stbuf.scala 212:154] + wire _T_792 = _T_791 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175] + wire _T_777 = stbuf_addr_2[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115] + wire _T_779 = _T_777 & stbuf_vld[2]; // @[lsu_stbuf.scala 212:139] + wire _T_782 = _T_779 & _T_52; // @[lsu_stbuf.scala 212:154] + wire _T_783 = _T_782 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175] + wire _T_768 = stbuf_addr_1[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115] + wire _T_770 = _T_768 & stbuf_vld[1]; // @[lsu_stbuf.scala 212:139] + wire _T_773 = _T_770 & _T_41; // @[lsu_stbuf.scala 212:154] + wire _T_774 = _T_773 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175] + wire _T_759 = stbuf_addr_0[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115] + wire _T_761 = _T_759 & stbuf_vld[0]; // @[lsu_stbuf.scala 212:139] + wire _T_764 = _T_761 & _T_30; // @[lsu_stbuf.scala 212:154] + wire _T_765 = _T_764 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175] + wire [3:0] stbuf_match_hi = {_T_792,_T_783,_T_774,_T_765}; // @[Cat.scala 29:58] + wire [15:0] cmpaddr_lo_m = {{2'd0}, io_lsu_addr_m[15:2]}; // @[lsu_stbuf.scala 209:17] + wire _T_824 = stbuf_addr_3[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115] + wire _T_826 = _T_824 & stbuf_vld[3]; // @[lsu_stbuf.scala 213:139] + wire _T_829 = _T_826 & _T_63; // @[lsu_stbuf.scala 213:154] + wire _T_830 = _T_829 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175] + wire _T_815 = stbuf_addr_2[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115] + wire _T_817 = _T_815 & stbuf_vld[2]; // @[lsu_stbuf.scala 213:139] + wire _T_820 = _T_817 & _T_52; // @[lsu_stbuf.scala 213:154] + wire _T_821 = _T_820 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175] + wire _T_806 = stbuf_addr_1[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115] + wire _T_808 = _T_806 & stbuf_vld[1]; // @[lsu_stbuf.scala 213:139] + wire _T_811 = _T_808 & _T_41; // @[lsu_stbuf.scala 213:154] + wire _T_812 = _T_811 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175] + wire _T_797 = stbuf_addr_0[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115] + wire _T_799 = _T_797 & stbuf_vld[0]; // @[lsu_stbuf.scala 213:139] + wire _T_802 = _T_799 & _T_30; // @[lsu_stbuf.scala 213:154] + wire _T_803 = _T_802 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175] + wire [3:0] stbuf_match_lo = {_T_830,_T_821,_T_812,_T_803}; // @[Cat.scala 29:58] + wire _T_853 = stbuf_match_hi[3] | stbuf_match_lo[3]; // @[lsu_stbuf.scala 214:78] + wire _T_854 = _T_853 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99] + wire _T_855 = _T_854 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120] + wire _T_856 = _T_855 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144] + wire _T_847 = stbuf_match_hi[2] | stbuf_match_lo[2]; // @[lsu_stbuf.scala 214:78] + wire _T_848 = _T_847 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99] + wire _T_849 = _T_848 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120] + wire _T_850 = _T_849 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144] + wire _T_841 = stbuf_match_hi[1] | stbuf_match_lo[1]; // @[lsu_stbuf.scala 214:78] + wire _T_842 = _T_841 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99] + wire _T_843 = _T_842 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120] + wire _T_844 = _T_843 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144] + wire _T_835 = stbuf_match_hi[0] | stbuf_match_lo[0]; // @[lsu_stbuf.scala 214:78] + wire _T_836 = _T_835 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99] + wire _T_837 = _T_836 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120] + wire _T_838 = _T_837 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144] + wire [3:0] stbuf_dma_kill_en = {_T_856,_T_850,_T_844,_T_838}; // @[Cat.scala 29:58] + wire _T_594 = stbuf_dma_kill_en[0] | stbuf_dma_kill[0]; // @[lsu_stbuf.scala 163:18] + wire _T_602 = stbuf_dma_kill_en[1] | stbuf_dma_kill[1]; // @[lsu_stbuf.scala 163:18] + wire _T_610 = stbuf_dma_kill_en[2] | stbuf_dma_kill[2]; // @[lsu_stbuf.scala 163:18] + wire _T_618 = stbuf_dma_kill_en[3] | stbuf_dma_kill[3]; // @[lsu_stbuf.scala 163:18] + wire [3:0] _T_628 = stbuf_wr_en[0] ? stbuf_byteenin_0 : stbuf_byteen_0; // @[lsu_stbuf.scala 166:18] + wire [3:0] _T_632 = _T_33 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_637 = stbuf_wr_en[1] ? stbuf_byteenin_1 : stbuf_byteen_1; // @[lsu_stbuf.scala 166:18] + wire [3:0] _T_641 = _T_44 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_646 = stbuf_wr_en[2] ? stbuf_byteenin_2 : stbuf_byteen_2; // @[lsu_stbuf.scala 166:18] + wire [3:0] _T_650 = _T_55 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_655 = stbuf_wr_en[3] ? stbuf_byteenin_3 : stbuf_byteen_3; // @[lsu_stbuf.scala 166:18] + wire [3:0] _T_659 = _T_66 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_686 = stbuf_vld >> RdPtr; // @[lsu_stbuf.scala 183:43] + wire [3:0] _T_688 = stbuf_dma_kill >> RdPtr; // @[lsu_stbuf.scala 183:67] + wire _T_695 = ~_T_688[0]; // @[lsu_stbuf.scala 184:46] + wire _T_696 = _T_686[0] & _T_695; // @[lsu_stbuf.scala 184:44] + wire _T_697 = |stbuf_dma_kill_en; // @[lsu_stbuf.scala 184:91] + wire _T_698 = ~_T_697; // @[lsu_stbuf.scala 184:71] + wire [15:0] _GEN_9 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[lsu_stbuf.scala 185:22] + wire [15:0] _GEN_10 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_9; // @[lsu_stbuf.scala 185:22] + wire [31:0] _GEN_13 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[lsu_stbuf.scala 186:22] + wire [31:0] _GEN_14 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_13; // @[lsu_stbuf.scala 186:22] + wire _T_700 = ~dual_stbuf_write_r; // @[lsu_stbuf.scala 188:44] + wire _T_701 = io_ldst_stbuf_reqvld_r & _T_700; // @[lsu_stbuf.scala 188:42] + wire _T_702 = store_coalesce_hi_r | store_coalesce_lo_r; // @[lsu_stbuf.scala 188:88] + wire _T_703 = ~_T_702; // @[lsu_stbuf.scala 188:66] + wire _T_704 = _T_701 & _T_703; // @[lsu_stbuf.scala 188:64] + wire _T_705 = io_ldst_stbuf_reqvld_r & dual_stbuf_write_r; // @[lsu_stbuf.scala 189:30] + wire _T_706 = store_coalesce_hi_r & store_coalesce_lo_r; // @[lsu_stbuf.scala 189:76] + wire _T_707 = ~_T_706; // @[lsu_stbuf.scala 189:54] + wire _T_708 = _T_705 & _T_707; // @[lsu_stbuf.scala 189:52] + wire WrPtrEn = _T_704 | _T_708; // @[lsu_stbuf.scala 188:113] + wire _T_713 = _T_705 & _T_703; // @[lsu_stbuf.scala 190:67] + wire [3:0] _T_718 = {3'h0,stbuf_vld[0]}; // @[Cat.scala 29:58] + wire [3:0] _T_720 = {3'h0,stbuf_vld[1]}; // @[Cat.scala 29:58] + wire [3:0] _T_722 = {3'h0,stbuf_vld[2]}; // @[Cat.scala 29:58] + wire [3:0] _T_724 = {3'h0,stbuf_vld[3]}; // @[Cat.scala 29:58] + wire [3:0] _T_727 = _T_718 + _T_720; // @[lsu_stbuf.scala 197:101] + wire [3:0] _T_729 = _T_727 + _T_722; // @[lsu_stbuf.scala 197:101] + wire [3:0] stbuf_numvld_any = _T_729 + _T_724; // @[lsu_stbuf.scala 197:101] + wire _T_731 = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 198:39] + wire _T_732 = _T_731 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 198:65] + wire _T_733 = ~io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 198:87] + wire isdccmst_m = _T_732 & _T_733; // @[lsu_stbuf.scala 198:85] + wire _T_734 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 199:39] + wire _T_735 = _T_734 & io_addr_in_dccm_r; // @[lsu_stbuf.scala 199:65] + wire _T_736 = ~io_lsu_pkt_r_bits_dma; // @[lsu_stbuf.scala 199:87] + wire isdccmst_r = _T_735 & _T_736; // @[lsu_stbuf.scala 199:85] + wire [1:0] _T_737 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58] + wire _T_738 = isdccmst_m & io_ldst_dual_m; // @[lsu_stbuf.scala 201:62] + wire [2:0] _GEN_22 = {{1'd0}, _T_737}; // @[lsu_stbuf.scala 201:47] + wire [2:0] _T_739 = _GEN_22 << _T_738; // @[lsu_stbuf.scala 201:47] + wire [1:0] _T_740 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58] + wire _T_741 = isdccmst_r & io_ldst_dual_r; // @[lsu_stbuf.scala 202:62] + wire [2:0] _GEN_23 = {{1'd0}, _T_740}; // @[lsu_stbuf.scala 202:47] + wire [2:0] _T_742 = _GEN_23 << _T_741; // @[lsu_stbuf.scala 202:47] + wire [1:0] stbuf_specvld_m = _T_739[1:0]; // @[lsu_stbuf.scala 201:19] + wire [3:0] _T_743 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58] + wire [3:0] _T_745 = stbuf_numvld_any + _T_743; // @[lsu_stbuf.scala 203:44] + wire [1:0] stbuf_specvld_r = _T_742[1:0]; // @[lsu_stbuf.scala 202:19] + wire [3:0] _T_746 = {2'h0,stbuf_specvld_r}; // @[Cat.scala 29:58] + wire [3:0] stbuf_specvld_any = _T_745 + _T_746; // @[lsu_stbuf.scala 203:78] + wire _T_748 = ~io_ldst_dual_d; // @[lsu_stbuf.scala 205:34] + wire _T_749 = _T_748 & io_dec_lsu_valid_raw_d; // @[lsu_stbuf.scala 205:50] + wire _T_751 = stbuf_specvld_any >= 4'h4; // @[lsu_stbuf.scala 205:102] + wire _T_752 = stbuf_specvld_any >= 4'h3; // @[lsu_stbuf.scala 205:143] + wire _T_862 = stbuf_match_hi[0] & stbuf_byteen_0[0]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_0 = _T_862 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137] + wire _T_866 = stbuf_match_hi[0] & stbuf_byteen_0[1]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_1 = _T_866 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137] + wire _T_870 = stbuf_match_hi[0] & stbuf_byteen_0[2]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_2 = _T_870 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137] + wire _T_874 = stbuf_match_hi[0] & stbuf_byteen_0[3]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_3 = _T_874 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137] + wire _T_878 = stbuf_match_hi[1] & stbuf_byteen_1[0]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_0 = _T_878 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137] + wire _T_882 = stbuf_match_hi[1] & stbuf_byteen_1[1]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_1 = _T_882 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137] + wire _T_886 = stbuf_match_hi[1] & stbuf_byteen_1[2]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_2 = _T_886 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137] + wire _T_890 = stbuf_match_hi[1] & stbuf_byteen_1[3]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_3 = _T_890 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137] + wire _T_894 = stbuf_match_hi[2] & stbuf_byteen_2[0]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_0 = _T_894 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137] + wire _T_898 = stbuf_match_hi[2] & stbuf_byteen_2[1]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_1 = _T_898 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137] + wire _T_902 = stbuf_match_hi[2] & stbuf_byteen_2[2]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_2 = _T_902 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137] + wire _T_906 = stbuf_match_hi[2] & stbuf_byteen_2[3]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_3 = _T_906 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137] + wire _T_910 = stbuf_match_hi[3] & stbuf_byteen_3[0]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_0 = _T_910 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137] + wire _T_914 = stbuf_match_hi[3] & stbuf_byteen_3[1]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_1 = _T_914 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137] + wire _T_918 = stbuf_match_hi[3] & stbuf_byteen_3[2]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_2 = _T_918 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137] + wire _T_922 = stbuf_match_hi[3] & stbuf_byteen_3[3]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_3 = _T_922 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137] + wire _T_926 = stbuf_match_lo[0] & stbuf_byteen_0[0]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_0 = _T_926 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137] + wire _T_930 = stbuf_match_lo[0] & stbuf_byteen_0[1]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_1 = _T_930 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137] + wire _T_934 = stbuf_match_lo[0] & stbuf_byteen_0[2]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_2 = _T_934 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137] + wire _T_938 = stbuf_match_lo[0] & stbuf_byteen_0[3]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_3 = _T_938 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137] + wire _T_942 = stbuf_match_lo[1] & stbuf_byteen_1[0]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_0 = _T_942 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137] + wire _T_946 = stbuf_match_lo[1] & stbuf_byteen_1[1]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_1 = _T_946 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137] + wire _T_950 = stbuf_match_lo[1] & stbuf_byteen_1[2]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_2 = _T_950 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137] + wire _T_954 = stbuf_match_lo[1] & stbuf_byteen_1[3]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_3 = _T_954 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137] + wire _T_958 = stbuf_match_lo[2] & stbuf_byteen_2[0]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_0 = _T_958 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137] + wire _T_962 = stbuf_match_lo[2] & stbuf_byteen_2[1]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_1 = _T_962 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137] + wire _T_966 = stbuf_match_lo[2] & stbuf_byteen_2[2]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_2 = _T_966 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137] + wire _T_970 = stbuf_match_lo[2] & stbuf_byteen_2[3]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_3 = _T_970 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137] + wire _T_974 = stbuf_match_lo[3] & stbuf_byteen_3[0]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_0 = _T_974 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137] + wire _T_978 = stbuf_match_lo[3] & stbuf_byteen_3[1]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_1 = _T_978 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137] + wire _T_982 = stbuf_match_lo[3] & stbuf_byteen_3[2]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_2 = _T_982 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137] + wire _T_986 = stbuf_match_lo[3] & stbuf_byteen_3[3]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_3 = _T_986 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137] + wire _T_988 = stbuf_fwdbyteenvec_hi_0_0 | stbuf_fwdbyteenvec_hi_1_0; // @[lsu_stbuf.scala 219:147] + wire _T_989 = _T_988 | stbuf_fwdbyteenvec_hi_2_0; // @[lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_0 = _T_989 | stbuf_fwdbyteenvec_hi_3_0; // @[lsu_stbuf.scala 219:147] + wire _T_990 = stbuf_fwdbyteenvec_hi_0_1 | stbuf_fwdbyteenvec_hi_1_1; // @[lsu_stbuf.scala 219:147] + wire _T_991 = _T_990 | stbuf_fwdbyteenvec_hi_2_1; // @[lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_1 = _T_991 | stbuf_fwdbyteenvec_hi_3_1; // @[lsu_stbuf.scala 219:147] + wire _T_992 = stbuf_fwdbyteenvec_hi_0_2 | stbuf_fwdbyteenvec_hi_1_2; // @[lsu_stbuf.scala 219:147] + wire _T_993 = _T_992 | stbuf_fwdbyteenvec_hi_2_2; // @[lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_2 = _T_993 | stbuf_fwdbyteenvec_hi_3_2; // @[lsu_stbuf.scala 219:147] + wire _T_994 = stbuf_fwdbyteenvec_hi_0_3 | stbuf_fwdbyteenvec_hi_1_3; // @[lsu_stbuf.scala 219:147] + wire _T_995 = _T_994 | stbuf_fwdbyteenvec_hi_2_3; // @[lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_3 = _T_995 | stbuf_fwdbyteenvec_hi_3_3; // @[lsu_stbuf.scala 219:147] + wire _T_996 = stbuf_fwdbyteenvec_lo_0_0 | stbuf_fwdbyteenvec_lo_1_0; // @[lsu_stbuf.scala 220:147] + wire _T_997 = _T_996 | stbuf_fwdbyteenvec_lo_2_0; // @[lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_0 = _T_997 | stbuf_fwdbyteenvec_lo_3_0; // @[lsu_stbuf.scala 220:147] + wire _T_998 = stbuf_fwdbyteenvec_lo_0_1 | stbuf_fwdbyteenvec_lo_1_1; // @[lsu_stbuf.scala 220:147] + wire _T_999 = _T_998 | stbuf_fwdbyteenvec_lo_2_1; // @[lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_1 = _T_999 | stbuf_fwdbyteenvec_lo_3_1; // @[lsu_stbuf.scala 220:147] + wire _T_1000 = stbuf_fwdbyteenvec_lo_0_2 | stbuf_fwdbyteenvec_lo_1_2; // @[lsu_stbuf.scala 220:147] + wire _T_1001 = _T_1000 | stbuf_fwdbyteenvec_lo_2_2; // @[lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_2 = _T_1001 | stbuf_fwdbyteenvec_lo_3_2; // @[lsu_stbuf.scala 220:147] + wire _T_1002 = stbuf_fwdbyteenvec_lo_0_3 | stbuf_fwdbyteenvec_lo_1_3; // @[lsu_stbuf.scala 220:147] + wire _T_1003 = _T_1002 | stbuf_fwdbyteenvec_lo_2_3; // @[lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_3 = _T_1003 | stbuf_fwdbyteenvec_lo_3_3; // @[lsu_stbuf.scala 220:147] + wire [31:0] _T_1006 = stbuf_match_hi[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1007 = _T_1006 & stbuf_data_0; // @[lsu_stbuf.scala 222:97] + wire [31:0] _T_1010 = stbuf_match_hi[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1011 = _T_1010 & stbuf_data_1; // @[lsu_stbuf.scala 222:97] + wire [31:0] _T_1014 = stbuf_match_hi[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1015 = _T_1014 & stbuf_data_2; // @[lsu_stbuf.scala 222:97] + wire [31:0] _T_1018 = stbuf_match_hi[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1019 = _T_1018 & stbuf_data_3; // @[lsu_stbuf.scala 222:97] + wire [31:0] _T_1021 = _T_1019 | _T_1015; // @[lsu_stbuf.scala 222:130] + wire [31:0] _T_1022 = _T_1021 | _T_1011; // @[lsu_stbuf.scala 222:130] + wire [31:0] stbuf_fwddata_hi_pre_m = _T_1022 | _T_1007; // @[lsu_stbuf.scala 222:130] + wire [31:0] _T_1025 = stbuf_match_lo[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1026 = _T_1025 & stbuf_data_0; // @[lsu_stbuf.scala 223:97] + wire [31:0] _T_1029 = stbuf_match_lo[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1030 = _T_1029 & stbuf_data_1; // @[lsu_stbuf.scala 223:97] + wire [31:0] _T_1033 = stbuf_match_lo[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1034 = _T_1033 & stbuf_data_2; // @[lsu_stbuf.scala 223:97] + wire [31:0] _T_1037 = stbuf_match_lo[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1038 = _T_1037 & stbuf_data_3; // @[lsu_stbuf.scala 223:97] + wire [31:0] _T_1040 = _T_1038 | _T_1034; // @[lsu_stbuf.scala 223:130] + wire [31:0] _T_1041 = _T_1040 | _T_1030; // @[lsu_stbuf.scala 223:130] + wire [31:0] stbuf_fwddata_lo_pre_m = _T_1041 | _T_1026; // @[lsu_stbuf.scala 223:130] + wire _T_1046 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_stbuf.scala 230:49] + wire _T_1047 = _T_1046 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 230:74] + wire _T_1048 = _T_1047 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 230:95] + wire ld_addr_rhit_lo_lo = _T_1048 & _T_736; // @[lsu_stbuf.scala 230:121] + wire _T_1052 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_stbuf.scala 231:49] + wire _T_1053 = _T_1052 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 231:74] + wire _T_1054 = _T_1053 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 231:95] + wire ld_addr_rhit_lo_hi = _T_1054 & _T_736; // @[lsu_stbuf.scala 231:121] + wire _T_1058 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_stbuf.scala 232:49] + wire _T_1059 = _T_1058 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 232:74] + wire _T_1060 = _T_1059 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 232:95] + wire _T_1062 = _T_1060 & _T_736; // @[lsu_stbuf.scala 232:121] + wire ld_addr_rhit_hi_lo = _T_1062 & dual_stbuf_write_r; // @[lsu_stbuf.scala 232:146] + wire _T_1065 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_stbuf.scala 233:49] + wire _T_1066 = _T_1065 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 233:74] + wire _T_1067 = _T_1066 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 233:95] + wire _T_1069 = _T_1067 & _T_736; // @[lsu_stbuf.scala 233:121] + wire ld_addr_rhit_hi_hi = _T_1069 & dual_stbuf_write_r; // @[lsu_stbuf.scala 233:146] + wire _T_1071 = ld_addr_rhit_lo_lo & store_byteen_ext_r[0]; // @[lsu_stbuf.scala 235:79] + wire _T_1073 = ld_addr_rhit_lo_lo & store_byteen_ext_r[1]; // @[lsu_stbuf.scala 235:79] + wire _T_1075 = ld_addr_rhit_lo_lo & store_byteen_ext_r[2]; // @[lsu_stbuf.scala 235:79] + wire _T_1077 = ld_addr_rhit_lo_lo & store_byteen_ext_r[3]; // @[lsu_stbuf.scala 235:79] + wire [3:0] ld_byte_rhit_lo_lo = {_T_1077,_T_1075,_T_1073,_T_1071}; // @[Cat.scala 29:58] + wire _T_1082 = ld_addr_rhit_lo_hi & store_byteen_ext_r[0]; // @[lsu_stbuf.scala 236:79] + wire _T_1084 = ld_addr_rhit_lo_hi & store_byteen_ext_r[1]; // @[lsu_stbuf.scala 236:79] + wire _T_1086 = ld_addr_rhit_lo_hi & store_byteen_ext_r[2]; // @[lsu_stbuf.scala 236:79] + wire _T_1088 = ld_addr_rhit_lo_hi & store_byteen_ext_r[3]; // @[lsu_stbuf.scala 236:79] + wire [3:0] ld_byte_rhit_lo_hi = {_T_1088,_T_1086,_T_1084,_T_1082}; // @[Cat.scala 29:58] + wire _T_1093 = ld_addr_rhit_hi_lo & store_byteen_ext_r[4]; // @[lsu_stbuf.scala 237:79] + wire _T_1095 = ld_addr_rhit_hi_lo & store_byteen_ext_r[5]; // @[lsu_stbuf.scala 237:79] + wire _T_1097 = ld_addr_rhit_hi_lo & store_byteen_ext_r[6]; // @[lsu_stbuf.scala 237:79] + wire _T_1099 = ld_addr_rhit_hi_lo & store_byteen_ext_r[7]; // @[lsu_stbuf.scala 237:79] + wire [3:0] ld_byte_rhit_hi_lo = {_T_1099,_T_1097,_T_1095,_T_1093}; // @[Cat.scala 29:58] + wire _T_1104 = ld_addr_rhit_hi_hi & store_byteen_ext_r[4]; // @[lsu_stbuf.scala 238:79] + wire _T_1106 = ld_addr_rhit_hi_hi & store_byteen_ext_r[5]; // @[lsu_stbuf.scala 238:79] + wire _T_1108 = ld_addr_rhit_hi_hi & store_byteen_ext_r[6]; // @[lsu_stbuf.scala 238:79] + wire _T_1110 = ld_addr_rhit_hi_hi & store_byteen_ext_r[7]; // @[lsu_stbuf.scala 238:79] + wire [3:0] ld_byte_rhit_hi_hi = {_T_1110,_T_1108,_T_1106,_T_1104}; // @[Cat.scala 29:58] + wire _T_1116 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_stbuf.scala 240:79] + wire _T_1119 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_stbuf.scala 240:79] + wire _T_1122 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_stbuf.scala 240:79] + wire _T_1125 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_stbuf.scala 240:79] + wire [3:0] ld_byte_rhit_lo = {_T_1125,_T_1122,_T_1119,_T_1116}; // @[Cat.scala 29:58] + wire _T_1131 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_stbuf.scala 241:79] + wire _T_1134 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_stbuf.scala 241:79] + wire _T_1137 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_stbuf.scala 241:79] + wire _T_1140 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_stbuf.scala 241:79] + wire [3:0] ld_byte_rhit_hi = {_T_1140,_T_1137,_T_1134,_T_1131}; // @[Cat.scala 29:58] + wire [7:0] _T_1146 = ld_byte_rhit_lo_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1148 = _T_1146 & io_store_data_lo_r[7:0]; // @[lsu_stbuf.scala 243:53] + wire [7:0] _T_1151 = ld_byte_rhit_hi_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1153 = _T_1151 & io_store_data_hi_r[7:0]; // @[lsu_stbuf.scala 243:114] + wire [7:0] fwdpipe1_lo = _T_1148 | _T_1153; // @[lsu_stbuf.scala 243:80] + wire [7:0] _T_1156 = ld_byte_rhit_lo_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1158 = _T_1156 & io_store_data_lo_r[15:8]; // @[lsu_stbuf.scala 244:53] + wire [7:0] _T_1161 = ld_byte_rhit_hi_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1163 = _T_1161 & io_store_data_hi_r[15:8]; // @[lsu_stbuf.scala 244:115] + wire [7:0] fwdpipe2_lo = _T_1158 | _T_1163; // @[lsu_stbuf.scala 244:81] + wire [7:0] _T_1166 = ld_byte_rhit_lo_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1168 = _T_1166 & io_store_data_lo_r[23:16]; // @[lsu_stbuf.scala 245:53] + wire [7:0] _T_1171 = ld_byte_rhit_hi_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1173 = _T_1171 & io_store_data_hi_r[23:16]; // @[lsu_stbuf.scala 245:116] + wire [7:0] fwdpipe3_lo = _T_1168 | _T_1173; // @[lsu_stbuf.scala 245:82] + wire [7:0] _T_1176 = ld_byte_rhit_lo_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1178 = _T_1176 & io_store_data_lo_r[31:24]; // @[lsu_stbuf.scala 246:53] + wire [7:0] _T_1181 = ld_byte_rhit_hi_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1183 = _T_1181 & io_store_data_hi_r[31:24]; // @[lsu_stbuf.scala 246:116] + wire [7:0] fwdpipe4_lo = _T_1178 | _T_1183; // @[lsu_stbuf.scala 246:82] + wire [31:0] ld_fwddata_rpipe_lo = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58] + wire [7:0] _T_1189 = ld_byte_rhit_lo_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1191 = _T_1189 & io_store_data_lo_r[7:0]; // @[lsu_stbuf.scala 249:53] + wire [7:0] _T_1194 = ld_byte_rhit_hi_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1196 = _T_1194 & io_store_data_hi_r[7:0]; // @[lsu_stbuf.scala 249:114] + wire [7:0] fwdpipe1_hi = _T_1191 | _T_1196; // @[lsu_stbuf.scala 249:80] + wire [7:0] _T_1199 = ld_byte_rhit_lo_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1201 = _T_1199 & io_store_data_lo_r[15:8]; // @[lsu_stbuf.scala 250:53] + wire [7:0] _T_1204 = ld_byte_rhit_hi_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1206 = _T_1204 & io_store_data_hi_r[15:8]; // @[lsu_stbuf.scala 250:115] + wire [7:0] fwdpipe2_hi = _T_1201 | _T_1206; // @[lsu_stbuf.scala 250:81] + wire [7:0] _T_1209 = ld_byte_rhit_lo_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1211 = _T_1209 & io_store_data_lo_r[23:16]; // @[lsu_stbuf.scala 251:53] + wire [7:0] _T_1214 = ld_byte_rhit_hi_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1216 = _T_1214 & io_store_data_hi_r[23:16]; // @[lsu_stbuf.scala 251:116] + wire [7:0] fwdpipe3_hi = _T_1211 | _T_1216; // @[lsu_stbuf.scala 251:82] + wire [7:0] _T_1219 = ld_byte_rhit_lo_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1221 = _T_1219 & io_store_data_lo_r[31:24]; // @[lsu_stbuf.scala 252:53] + wire [7:0] _T_1224 = ld_byte_rhit_hi_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1226 = _T_1224 & io_store_data_hi_r[31:24]; // @[lsu_stbuf.scala 252:116] + wire [7:0] fwdpipe4_hi = _T_1221 | _T_1226; // @[lsu_stbuf.scala 252:82] + wire [31:0] ld_fwddata_rpipe_hi = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58] + wire _T_1261 = ld_byte_rhit_hi[0] | stbuf_fwdbyteen_hi_pre_m_0; // @[lsu_stbuf.scala 258:83] + wire _T_1263 = ld_byte_rhit_hi[1] | stbuf_fwdbyteen_hi_pre_m_1; // @[lsu_stbuf.scala 258:83] + wire _T_1265 = ld_byte_rhit_hi[2] | stbuf_fwdbyteen_hi_pre_m_2; // @[lsu_stbuf.scala 258:83] + wire _T_1267 = ld_byte_rhit_hi[3] | stbuf_fwdbyteen_hi_pre_m_3; // @[lsu_stbuf.scala 258:83] + wire [2:0] _T_1269 = {_T_1267,_T_1265,_T_1263}; // @[Cat.scala 29:58] + wire _T_1272 = ld_byte_rhit_lo[0] | stbuf_fwdbyteen_lo_pre_m_0; // @[lsu_stbuf.scala 259:83] + wire _T_1274 = ld_byte_rhit_lo[1] | stbuf_fwdbyteen_lo_pre_m_1; // @[lsu_stbuf.scala 259:83] + wire _T_1276 = ld_byte_rhit_lo[2] | stbuf_fwdbyteen_lo_pre_m_2; // @[lsu_stbuf.scala 259:83] + wire _T_1278 = ld_byte_rhit_lo[3] | stbuf_fwdbyteen_lo_pre_m_3; // @[lsu_stbuf.scala 259:83] + wire [2:0] _T_1280 = {_T_1278,_T_1276,_T_1274}; // @[Cat.scala 29:58] + wire [7:0] stbuf_fwdpipe1_lo = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : stbuf_fwddata_lo_pre_m[7:0]; // @[lsu_stbuf.scala 262:30] + wire [7:0] stbuf_fwdpipe2_lo = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : stbuf_fwddata_lo_pre_m[15:8]; // @[lsu_stbuf.scala 263:30] + wire [7:0] stbuf_fwdpipe3_lo = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : stbuf_fwddata_lo_pre_m[23:16]; // @[lsu_stbuf.scala 264:30] + wire [7:0] stbuf_fwdpipe4_lo = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : stbuf_fwddata_lo_pre_m[31:24]; // @[lsu_stbuf.scala 265:30] + wire [15:0] _T_1294 = {stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo}; // @[Cat.scala 29:58] + wire [15:0] _T_1295 = {stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo}; // @[Cat.scala 29:58] + wire [7:0] stbuf_fwdpipe1_hi = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : stbuf_fwddata_hi_pre_m[7:0]; // @[lsu_stbuf.scala 268:30] + wire [7:0] stbuf_fwdpipe2_hi = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : stbuf_fwddata_hi_pre_m[15:8]; // @[lsu_stbuf.scala 269:30] + wire [7:0] stbuf_fwdpipe3_hi = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : stbuf_fwddata_hi_pre_m[23:16]; // @[lsu_stbuf.scala 270:30] + wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[lsu_stbuf.scala 271:30] + wire [15:0] _T_1309 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58] + wire [15:0] _T_1310 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + assign io_stbuf_reqvld_any = _T_696 & _T_698; // @[lsu_stbuf.scala 51:47 lsu_stbuf.scala 184:24] + assign io_stbuf_reqvld_flushed_any = _T_686[0] & _T_688[0]; // @[lsu_stbuf.scala 52:35 lsu_stbuf.scala 183:31] + assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_10; // @[lsu_stbuf.scala 53:35 lsu_stbuf.scala 185:22] + assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_14; // @[lsu_stbuf.scala 54:35 lsu_stbuf.scala 186:22] + assign io_lsu_stbuf_full_any = _T_749 ? _T_751 : _T_752; // @[lsu_stbuf.scala 55:43 lsu_stbuf.scala 205:26] + assign io_ldst_stbuf_reqvld_r = _T_22 & io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 57:43 lsu_stbuf.scala 125:26] + assign io_stbuf_fwddata_hi_m = {_T_1310,_T_1309}; // @[lsu_stbuf.scala 58:43 lsu_stbuf.scala 272:25] + assign io_stbuf_fwddata_lo_m = {_T_1295,_T_1294}; // @[lsu_stbuf.scala 59:43 lsu_stbuf.scala 266:25] + assign io_stbuf_fwdbyteen_hi_m = {_T_1269,_T_1261}; // @[lsu_stbuf.scala 60:37 lsu_stbuf.scala 258:27] + assign io_stbuf_fwdbyteen_lo_m = {_T_1280,_T_1272}; // @[lsu_stbuf.scala 61:37 lsu_stbuf.scala 259:27] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + RdPtr = _RAND_0[1:0]; + _RAND_1 = {1{`RANDOM}}; + WrPtr = _RAND_1[1:0]; + _RAND_2 = {1{`RANDOM}}; + stbuf_addr_0 = _RAND_2[15:0]; + _RAND_3 = {1{`RANDOM}}; + _T_587 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_579 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_571 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_563 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_622 = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + _T_614 = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + _T_606 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + _T_598 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + stbuf_addr_1 = _RAND_11[15:0]; + _RAND_12 = {1{`RANDOM}}; + stbuf_addr_2 = _RAND_12[15:0]; + _RAND_13 = {1{`RANDOM}}; + stbuf_addr_3 = _RAND_13[15:0]; + _RAND_14 = {1{`RANDOM}}; + stbuf_byteen_0 = _RAND_14[3:0]; + _RAND_15 = {1{`RANDOM}}; + stbuf_byteen_1 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + stbuf_byteen_2 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + stbuf_byteen_3 = _RAND_17[3:0]; + _RAND_18 = {1{`RANDOM}}; + stbuf_data_0 = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + stbuf_data_1 = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + stbuf_data_2 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + stbuf_data_3 = _RAND_21[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + RdPtr = 2'h0; + end + if (reset) begin + WrPtr = 2'h0; + end + if (reset) begin + stbuf_addr_0 = 16'h0; + end + if (reset) begin + _T_587 = 1'h0; + end + if (reset) begin + _T_579 = 1'h0; + end + if (reset) begin + _T_571 = 1'h0; + end + if (reset) begin + _T_563 = 1'h0; + end + if (reset) begin + _T_622 = 1'h0; + end + if (reset) begin + _T_614 = 1'h0; + end + if (reset) begin + _T_606 = 1'h0; + end + if (reset) begin + _T_598 = 1'h0; + end + if (reset) begin + stbuf_addr_1 = 16'h0; + end + if (reset) begin + stbuf_addr_2 = 16'h0; + end + if (reset) begin + stbuf_addr_3 = 16'h0; + end + if (reset) begin + stbuf_byteen_0 = 4'h0; + end + if (reset) begin + stbuf_byteen_1 = 4'h0; + end + if (reset) begin + stbuf_byteen_2 = 4'h0; + end + if (reset) begin + stbuf_byteen_3 = 4'h0; + end + if (reset) begin + stbuf_data_0 = 32'h0; + end + if (reset) begin + stbuf_data_1 = 32'h0; + end + if (reset) begin + stbuf_data_2 = 32'h0; + end + if (reset) begin + stbuf_data_3 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + RdPtr <= 2'h0; + end else if (_T_211) begin + RdPtr <= RdPtrPlus1; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + WrPtr <= 2'h0; + end else if (WrPtrEn) begin + if (_T_713) begin + WrPtr <= WrPtrPlus2; + end else begin + WrPtr <= WrPtrPlus1; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_addr_0 <= 16'h0; + end else if (stbuf_wr_en[0]) begin + if (sel_lo[0]) begin + stbuf_addr_0 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_0 <= io_end_addr_r[15:0]; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_587 <= 1'h0; + end else begin + _T_587 <= _T_583 & _T_66; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_579 <= 1'h0; + end else begin + _T_579 <= _T_575 & _T_55; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_571 <= 1'h0; + end else begin + _T_571 <= _T_567 & _T_44; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_563 <= 1'h0; + end else begin + _T_563 <= _T_559 & _T_33; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_622 <= 1'h0; + end else begin + _T_622 <= _T_618 & _T_66; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_614 <= 1'h0; + end else begin + _T_614 <= _T_610 & _T_55; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_606 <= 1'h0; + end else begin + _T_606 <= _T_602 & _T_44; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_598 <= 1'h0; + end else begin + _T_598 <= _T_594 & _T_33; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_addr_1 <= 16'h0; + end else if (stbuf_wr_en[1]) begin + if (sel_lo[1]) begin + stbuf_addr_1 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_1 <= io_end_addr_r[15:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_addr_2 <= 16'h0; + end else if (stbuf_wr_en[2]) begin + if (sel_lo[2]) begin + stbuf_addr_2 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_2 <= io_end_addr_r[15:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_addr_3 <= 16'h0; + end else if (stbuf_wr_en[3]) begin + if (sel_lo[3]) begin + stbuf_addr_3 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_3 <= io_end_addr_r[15:0]; + end + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_0 <= 4'h0; + end else begin + stbuf_byteen_0 <= _T_628 & _T_632; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_1 <= 4'h0; + end else begin + stbuf_byteen_1 <= _T_637 & _T_641; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_2 <= 4'h0; + end else begin + stbuf_byteen_2 <= _T_646 & _T_650; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_3 <= 4'h0; + end else begin + stbuf_byteen_3 <= _T_655 & _T_659; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_data_0 <= 32'h0; + end else if (stbuf_wr_en[0]) begin + stbuf_data_0 <= stbuf_datain_0; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_data_1 <= 32'h0; + end else if (stbuf_wr_en[1]) begin + stbuf_data_1 <= stbuf_datain_1; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_data_2 <= 32'h0; + end else if (stbuf_wr_en[2]) begin + stbuf_data_2 <= stbuf_datain_2; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_data_3 <= 32'h0; + end else if (stbuf_wr_en[3]) begin + stbuf_data_3 <= stbuf_datain_3; + end + end +endmodule +module lsu_ecc( + input clock, + input reset, + input io_lsu_c2_r_clk, + input io_clk_override, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input [31:0] io_stbuf_data_any, + input io_dec_tlu_core_ecc_disable, + input [15:0] io_lsu_addr_m, + input [15:0] io_end_addr_m, + input [31:0] io_dccm_rdata_hi_m, + input [31:0] io_dccm_rdata_lo_m, + input [6:0] io_dccm_data_ecc_hi_m, + input [6:0] io_dccm_data_ecc_lo_m, + input io_ld_single_ecc_error_r, + input io_ld_single_ecc_error_r_ff, + input io_lsu_dccm_rden_m, + input io_addr_in_dccm_m, + input io_dma_dccm_wen, + input [31:0] io_dma_dccm_wdata_lo, + input [31:0] io_dma_dccm_wdata_hi, + output [31:0] io_sec_data_hi_r, + output [31:0] io_sec_data_lo_r, + output [31:0] io_sec_data_hi_m, + output [31:0] io_sec_data_lo_m, + output [31:0] io_sec_data_hi_r_ff, + output [31:0] io_sec_data_lo_r_ff, + output [6:0] io_dma_dccm_wdata_ecc_hi, + output [6:0] io_dma_dccm_wdata_ecc_lo, + output [6:0] io_stbuf_ecc_any, + output [6:0] io_sec_data_ecc_hi_r_ff, + output [6:0] io_sec_data_ecc_lo_r_ff, + output io_single_ecc_error_hi_r, + output io_single_ecc_error_lo_r, + output io_lsu_single_ecc_error_r, + output io_lsu_double_ecc_error_r, + output io_lsu_single_ecc_error_m, + output io_lsu_double_ecc_error_m +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire _T_96 = ^io_dccm_rdata_hi_m; // @[lib.scala 193:30] + wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[lib.scala 193:44] + wire _T_98 = _T_96 ^ _T_97; // @[lib.scala 193:35] + wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[lib.scala 193:76] + wire _T_107 = ^_T_106; // @[lib.scala 193:83] + wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[lib.scala 193:71] + wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[lib.scala 193:103] + wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[lib.scala 193:103] + wire _T_124 = ^_T_123; // @[lib.scala 193:110] + wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[lib.scala 193:98] + wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[lib.scala 193:130] + wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[lib.scala 193:130] + wire _T_141 = ^_T_140; // @[lib.scala 193:137] + wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[lib.scala 193:125] + wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[lib.scala 193:157] + wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[lib.scala 193:157] + wire _T_161 = ^_T_160; // @[lib.scala 193:164] + wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[lib.scala 193:152] + wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:184] + wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[lib.scala 193:184] + wire _T_181 = ^_T_180; // @[lib.scala 193:191] + wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[lib.scala 193:179] + wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:211] + wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[lib.scala 193:211] + wire _T_201 = ^_T_200; // @[lib.scala 193:218] + wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[lib.scala 193:206] + wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58] + wire _T_209 = _T_208 != 7'h0; // @[lib.scala 194:44] + wire _T_1130 = ~io_dec_tlu_core_ecc_disable; // @[lsu_ecc.scala 106:48] + wire _T_1137 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[lsu_ecc.scala 124:65] + wire _T_1138 = io_lsu_pkt_m_valid & _T_1137; // @[lsu_ecc.scala 124:39] + wire _T_1139 = _T_1138 & io_addr_in_dccm_m; // @[lsu_ecc.scala 124:92] + wire is_ldst_m = _T_1139 & io_lsu_dccm_rden_m; // @[lsu_ecc.scala 124:112] + wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[lsu_ecc.scala 123:39] + wire _T_1143 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[lsu_ecc.scala 126:48] + wire _T_1144 = is_ldst_m & _T_1143; // @[lsu_ecc.scala 126:33] + wire is_ldst_hi_m = _T_1144 & _T_1130; // @[lsu_ecc.scala 126:73] + wire _T_210 = is_ldst_hi_m & _T_209; // @[lib.scala 194:32] + wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[lib.scala 194:53] + wire _T_215 = ~_T_208[6]; // @[lib.scala 195:55] + wire double_ecc_error_hi_any = _T_210 & _T_215; // @[lib.scala 195:53] + wire _T_218 = _T_208[5:0] == 6'h1; // @[lib.scala 199:41] + wire _T_220 = _T_208[5:0] == 6'h2; // @[lib.scala 199:41] + wire _T_222 = _T_208[5:0] == 6'h3; // @[lib.scala 199:41] + wire _T_224 = _T_208[5:0] == 6'h4; // @[lib.scala 199:41] + wire _T_226 = _T_208[5:0] == 6'h5; // @[lib.scala 199:41] + wire _T_228 = _T_208[5:0] == 6'h6; // @[lib.scala 199:41] + wire _T_230 = _T_208[5:0] == 6'h7; // @[lib.scala 199:41] + wire _T_232 = _T_208[5:0] == 6'h8; // @[lib.scala 199:41] + wire _T_234 = _T_208[5:0] == 6'h9; // @[lib.scala 199:41] + wire _T_236 = _T_208[5:0] == 6'ha; // @[lib.scala 199:41] + wire _T_238 = _T_208[5:0] == 6'hb; // @[lib.scala 199:41] + wire _T_240 = _T_208[5:0] == 6'hc; // @[lib.scala 199:41] + wire _T_242 = _T_208[5:0] == 6'hd; // @[lib.scala 199:41] + wire _T_244 = _T_208[5:0] == 6'he; // @[lib.scala 199:41] + wire _T_246 = _T_208[5:0] == 6'hf; // @[lib.scala 199:41] + wire _T_248 = _T_208[5:0] == 6'h10; // @[lib.scala 199:41] + wire _T_250 = _T_208[5:0] == 6'h11; // @[lib.scala 199:41] + wire _T_252 = _T_208[5:0] == 6'h12; // @[lib.scala 199:41] + wire _T_254 = _T_208[5:0] == 6'h13; // @[lib.scala 199:41] + wire _T_256 = _T_208[5:0] == 6'h14; // @[lib.scala 199:41] + wire _T_258 = _T_208[5:0] == 6'h15; // @[lib.scala 199:41] + wire _T_260 = _T_208[5:0] == 6'h16; // @[lib.scala 199:41] + wire _T_262 = _T_208[5:0] == 6'h17; // @[lib.scala 199:41] + wire _T_264 = _T_208[5:0] == 6'h18; // @[lib.scala 199:41] + wire _T_266 = _T_208[5:0] == 6'h19; // @[lib.scala 199:41] + wire _T_268 = _T_208[5:0] == 6'h1a; // @[lib.scala 199:41] + wire _T_270 = _T_208[5:0] == 6'h1b; // @[lib.scala 199:41] + wire _T_272 = _T_208[5:0] == 6'h1c; // @[lib.scala 199:41] + wire _T_274 = _T_208[5:0] == 6'h1d; // @[lib.scala 199:41] + wire _T_276 = _T_208[5:0] == 6'h1e; // @[lib.scala 199:41] + wire _T_278 = _T_208[5:0] == 6'h1f; // @[lib.scala 199:41] + wire _T_280 = _T_208[5:0] == 6'h20; // @[lib.scala 199:41] + wire _T_282 = _T_208[5:0] == 6'h21; // @[lib.scala 199:41] + wire _T_284 = _T_208[5:0] == 6'h22; // @[lib.scala 199:41] + wire _T_286 = _T_208[5:0] == 6'h23; // @[lib.scala 199:41] + wire _T_288 = _T_208[5:0] == 6'h24; // @[lib.scala 199:41] + wire _T_290 = _T_208[5:0] == 6'h25; // @[lib.scala 199:41] + wire _T_292 = _T_208[5:0] == 6'h26; // @[lib.scala 199:41] + wire _T_294 = _T_208[5:0] == 6'h27; // @[lib.scala 199:41] + wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58] + wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[lib.scala 202:69] + wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[lib.scala 202:69] + wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[lib.scala 202:69] + wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[lib.scala 202:69] + wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[lib.scala 202:69] + wire [38:0] _T_355 = _T_354 ^ _T_315; // @[lib.scala 202:76] + wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[lib.scala 202:31] + wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58] + wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58] + wire _T_474 = ^io_dccm_rdata_lo_m; // @[lib.scala 193:30] + wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[lib.scala 193:44] + wire _T_476 = _T_474 ^ _T_475; // @[lib.scala 193:35] + wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[lib.scala 193:76] + wire _T_485 = ^_T_484; // @[lib.scala 193:83] + wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[lib.scala 193:71] + wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[lib.scala 193:103] + wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[lib.scala 193:103] + wire _T_502 = ^_T_501; // @[lib.scala 193:110] + wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[lib.scala 193:98] + wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[lib.scala 193:130] + wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[lib.scala 193:130] + wire _T_519 = ^_T_518; // @[lib.scala 193:137] + wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[lib.scala 193:125] + wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[lib.scala 193:157] + wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[lib.scala 193:157] + wire _T_539 = ^_T_538; // @[lib.scala 193:164] + wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[lib.scala 193:152] + wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:184] + wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[lib.scala 193:184] + wire _T_559 = ^_T_558; // @[lib.scala 193:191] + wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[lib.scala 193:179] + wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:211] + wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[lib.scala 193:211] + wire _T_579 = ^_T_578; // @[lib.scala 193:218] + wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[lib.scala 193:206] + wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58] + wire _T_587 = _T_586 != 7'h0; // @[lib.scala 194:44] + wire is_ldst_lo_m = is_ldst_m & _T_1130; // @[lsu_ecc.scala 125:33] + wire _T_588 = is_ldst_lo_m & _T_587; // @[lib.scala 194:32] + wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[lib.scala 194:53] + wire _T_593 = ~_T_586[6]; // @[lib.scala 195:55] + wire double_ecc_error_lo_any = _T_588 & _T_593; // @[lib.scala 195:53] + wire _T_596 = _T_586[5:0] == 6'h1; // @[lib.scala 199:41] + wire _T_598 = _T_586[5:0] == 6'h2; // @[lib.scala 199:41] + wire _T_600 = _T_586[5:0] == 6'h3; // @[lib.scala 199:41] + wire _T_602 = _T_586[5:0] == 6'h4; // @[lib.scala 199:41] + wire _T_604 = _T_586[5:0] == 6'h5; // @[lib.scala 199:41] + wire _T_606 = _T_586[5:0] == 6'h6; // @[lib.scala 199:41] + wire _T_608 = _T_586[5:0] == 6'h7; // @[lib.scala 199:41] + wire _T_610 = _T_586[5:0] == 6'h8; // @[lib.scala 199:41] + wire _T_612 = _T_586[5:0] == 6'h9; // @[lib.scala 199:41] + wire _T_614 = _T_586[5:0] == 6'ha; // @[lib.scala 199:41] + wire _T_616 = _T_586[5:0] == 6'hb; // @[lib.scala 199:41] + wire _T_618 = _T_586[5:0] == 6'hc; // @[lib.scala 199:41] + wire _T_620 = _T_586[5:0] == 6'hd; // @[lib.scala 199:41] + wire _T_622 = _T_586[5:0] == 6'he; // @[lib.scala 199:41] + wire _T_624 = _T_586[5:0] == 6'hf; // @[lib.scala 199:41] + wire _T_626 = _T_586[5:0] == 6'h10; // @[lib.scala 199:41] + wire _T_628 = _T_586[5:0] == 6'h11; // @[lib.scala 199:41] + wire _T_630 = _T_586[5:0] == 6'h12; // @[lib.scala 199:41] + wire _T_632 = _T_586[5:0] == 6'h13; // @[lib.scala 199:41] + wire _T_634 = _T_586[5:0] == 6'h14; // @[lib.scala 199:41] + wire _T_636 = _T_586[5:0] == 6'h15; // @[lib.scala 199:41] + wire _T_638 = _T_586[5:0] == 6'h16; // @[lib.scala 199:41] + wire _T_640 = _T_586[5:0] == 6'h17; // @[lib.scala 199:41] + wire _T_642 = _T_586[5:0] == 6'h18; // @[lib.scala 199:41] + wire _T_644 = _T_586[5:0] == 6'h19; // @[lib.scala 199:41] + wire _T_646 = _T_586[5:0] == 6'h1a; // @[lib.scala 199:41] + wire _T_648 = _T_586[5:0] == 6'h1b; // @[lib.scala 199:41] + wire _T_650 = _T_586[5:0] == 6'h1c; // @[lib.scala 199:41] + wire _T_652 = _T_586[5:0] == 6'h1d; // @[lib.scala 199:41] + wire _T_654 = _T_586[5:0] == 6'h1e; // @[lib.scala 199:41] + wire _T_656 = _T_586[5:0] == 6'h1f; // @[lib.scala 199:41] + wire _T_658 = _T_586[5:0] == 6'h20; // @[lib.scala 199:41] + wire _T_660 = _T_586[5:0] == 6'h21; // @[lib.scala 199:41] + wire _T_662 = _T_586[5:0] == 6'h22; // @[lib.scala 199:41] + wire _T_664 = _T_586[5:0] == 6'h23; // @[lib.scala 199:41] + wire _T_666 = _T_586[5:0] == 6'h24; // @[lib.scala 199:41] + wire _T_668 = _T_586[5:0] == 6'h25; // @[lib.scala 199:41] + wire _T_670 = _T_586[5:0] == 6'h26; // @[lib.scala 199:41] + wire _T_672 = _T_586[5:0] == 6'h27; // @[lib.scala 199:41] + wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58] + wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[lib.scala 202:69] + wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[lib.scala 202:69] + wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[lib.scala 202:69] + wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[lib.scala 202:69] + wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[lib.scala 202:69] + wire [38:0] _T_733 = _T_732 ^ _T_693; // @[lib.scala 202:76] + wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[lib.scala 202:31] + wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58] + wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_1159 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[lsu_ecc.scala 148:87] + wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1159; // @[lsu_ecc.scala 148:27] + wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[lib.scala 119:74] + wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[lib.scala 119:74] + wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[lib.scala 119:74] + wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[lib.scala 119:74] + wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74] + wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74] + wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74] + wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74] + wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74] + wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74] + wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74] + wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74] + wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74] + wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74] + wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74] + wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74] + wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74] + wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74] + wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74] + wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74] + wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58] + wire _T_935 = ^dccm_wdata_lo_any; // @[lib.scala 127:13] + wire _T_936 = ^_T_934; // @[lib.scala 127:23] + wire _T_937 = _T_935 ^ _T_936; // @[lib.scala 127:18] + wire [31:0] _T_1163 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : 32'h0; // @[lsu_ecc.scala 149:87] + wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1163; // @[lsu_ecc.scala 149:27] + wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[lib.scala 119:74] + wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[lib.scala 119:74] + wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[lib.scala 119:74] + wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[lib.scala 119:74] + wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74] + wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74] + wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74] + wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74] + wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74] + wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74] + wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74] + wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74] + wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74] + wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74] + wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74] + wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74] + wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74] + wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74] + wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74] + wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74] + wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58] + wire _T_1117 = ^dccm_wdata_hi_any; // @[lib.scala 127:13] + wire _T_1118 = ^_T_1116; // @[lib.scala 127:23] + wire _T_1119 = _T_1117 ^ _T_1118; // @[lib.scala 127:18] + reg _T_1149; // @[lsu_ecc.scala 140:72] + reg _T_1150; // @[lsu_ecc.scala 141:72] + reg _T_1151; // @[lsu_ecc.scala 142:72] + reg _T_1152; // @[lsu_ecc.scala 143:72] + wire _T_1153 = io_lsu_single_ecc_error_m | io_clk_override; // @[lsu_ecc.scala 144:87] + reg [31:0] _T_1154; // @[Reg.scala 27:20] + reg [31:0] _T_1156; // @[Reg.scala 27:20] + wire _T_1165 = io_ld_single_ecc_error_r | io_clk_override; // @[lsu_ecc.scala 156:75] + reg [31:0] _T_1166; // @[Reg.scala 27:20] + reg [31:0] _T_1168; // @[Reg.scala 27:20] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + assign io_sec_data_hi_r = _T_1154; // @[lsu_ecc.scala 113:22 lsu_ecc.scala 144:34] + assign io_sec_data_lo_r = _T_1156; // @[lsu_ecc.scala 116:25 lsu_ecc.scala 145:34] + assign io_sec_data_hi_m = {_T_364,_T_362}; // @[lsu_ecc.scala 89:32 lsu_ecc.scala 133:27] + assign io_sec_data_lo_m = {_T_742,_T_740}; // @[lsu_ecc.scala 90:32 lsu_ecc.scala 135:27] + assign io_sec_data_hi_r_ff = _T_1166; // @[lsu_ecc.scala 156:23] + assign io_sec_data_lo_r_ff = _T_1168; // @[lsu_ecc.scala 157:23] + assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[lsu_ecc.scala 153:28] + assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[lsu_ecc.scala 154:28] + assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[lsu_ecc.scala 152:28] + assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[lsu_ecc.scala 150:28] + assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[lsu_ecc.scala 151:28] + assign io_single_ecc_error_hi_r = _T_1152; // @[lsu_ecc.scala 114:31 lsu_ecc.scala 143:62] + assign io_single_ecc_error_lo_r = _T_1151; // @[lsu_ecc.scala 117:31 lsu_ecc.scala 142:62] + assign io_lsu_single_ecc_error_r = _T_1149; // @[lsu_ecc.scala 119:31 lsu_ecc.scala 140:62] + assign io_lsu_double_ecc_error_r = _T_1150; // @[lsu_ecc.scala 120:31 lsu_ecc.scala 141:62] + assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[lsu_ecc.scala 91:30 lsu_ecc.scala 137:33] + assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 92:30 lsu_ecc.scala 138:33] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_1149 = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_1150 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_1151 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_1152 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_1154 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + _T_1156 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + _T_1166 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + _T_1168 = _RAND_7[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_1149 = 1'h0; + end + if (reset) begin + _T_1150 = 1'h0; + end + if (reset) begin + _T_1151 = 1'h0; + end + if (reset) begin + _T_1152 = 1'h0; + end + if (reset) begin + _T_1154 = 32'h0; + end + if (reset) begin + _T_1156 = 32'h0; + end + if (reset) begin + _T_1166 = 32'h0; + end + if (reset) begin + _T_1168 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1149 <= 1'h0; + end else begin + _T_1149 <= io_lsu_single_ecc_error_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1150 <= 1'h0; + end else begin + _T_1150 <= io_lsu_double_ecc_error_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1151 <= 1'h0; + end else begin + _T_1151 <= _T_588 & _T_586[6]; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1152 <= 1'h0; + end else begin + _T_1152 <= _T_210 & _T_208[6]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1154 <= 32'h0; + end else if (_T_1153) begin + _T_1154 <= io_sec_data_hi_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1156 <= 32'h0; + end else if (_T_1153) begin + _T_1156 <= io_sec_data_lo_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1166 <= 32'h0; + end else if (_T_1165) begin + _T_1166 <= io_sec_data_hi_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1168 <= 32'h0; + end else if (_T_1165) begin + _T_1168 <= io_sec_data_lo_r; + end + end +endmodule +module lsu_trigger( + input io_trigger_pkt_any_0_select, + input io_trigger_pkt_any_0_match_pkt, + input io_trigger_pkt_any_0_store, + input io_trigger_pkt_any_0_load, + input io_trigger_pkt_any_0_m, + input [31:0] io_trigger_pkt_any_0_tdata2, + input io_trigger_pkt_any_1_select, + input io_trigger_pkt_any_1_match_pkt, + input io_trigger_pkt_any_1_store, + input io_trigger_pkt_any_1_load, + input io_trigger_pkt_any_1_m, + input [31:0] io_trigger_pkt_any_1_tdata2, + input io_trigger_pkt_any_2_select, + input io_trigger_pkt_any_2_match_pkt, + input io_trigger_pkt_any_2_store, + input io_trigger_pkt_any_2_load, + input io_trigger_pkt_any_2_m, + input [31:0] io_trigger_pkt_any_2_tdata2, + input io_trigger_pkt_any_3_select, + input io_trigger_pkt_any_3_match_pkt, + input io_trigger_pkt_any_3_store, + input io_trigger_pkt_any_3_load, + input io_trigger_pkt_any_3_m, + input [31:0] io_trigger_pkt_any_3_tdata2, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input [31:0] io_lsu_addr_m, + input [31:0] io_store_data_m, + output [3:0] io_lsu_trigger_match_m +); + wire _T = io_trigger_pkt_any_0_m | io_trigger_pkt_any_1_m; // @[lsu_trigger.scala 16:73] + wire _T_1 = _T | io_trigger_pkt_any_2_m; // @[lsu_trigger.scala 16:73] + wire trigger_enable = _T_1 | io_trigger_pkt_any_3_m; // @[lsu_trigger.scala 16:73] + wire [15:0] _T_4 = io_lsu_pkt_m_bits_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_6 = _T_4 & io_store_data_m[31:16]; // @[lsu_trigger.scala 17:66] + wire _T_7 = io_lsu_pkt_m_bits_half | io_lsu_pkt_m_bits_word; // @[lsu_trigger.scala 17:124] + wire [7:0] _T_9 = _T_7 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_11 = _T_9 & io_store_data_m[15:8]; // @[lsu_trigger.scala 17:151] + wire [31:0] store_data_trigger_m = {_T_6,_T_11,io_store_data_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_15 = trigger_enable ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] ldst_addr_trigger_m = io_lsu_addr_m & _T_15; // @[lsu_trigger.scala 18:43] + wire _T_17 = ~io_trigger_pkt_any_0_select; // @[lsu_trigger.scala 19:53] + wire _T_18 = io_trigger_pkt_any_0_select & io_trigger_pkt_any_0_store; // @[lsu_trigger.scala 19:143] + wire [31:0] _T_20 = _T_17 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_21 = _T_18 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_0 = _T_20 | _T_21; // @[Mux.scala 27:72] + wire _T_24 = ~io_trigger_pkt_any_1_select; // @[lsu_trigger.scala 19:53] + wire _T_25 = io_trigger_pkt_any_1_select & io_trigger_pkt_any_1_store; // @[lsu_trigger.scala 19:143] + wire [31:0] _T_27 = _T_24 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_28 = _T_25 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_1 = _T_27 | _T_28; // @[Mux.scala 27:72] + wire _T_31 = ~io_trigger_pkt_any_2_select; // @[lsu_trigger.scala 19:53] + wire _T_32 = io_trigger_pkt_any_2_select & io_trigger_pkt_any_2_store; // @[lsu_trigger.scala 19:143] + wire [31:0] _T_34 = _T_31 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_35 = _T_32 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_2 = _T_34 | _T_35; // @[Mux.scala 27:72] + wire _T_38 = ~io_trigger_pkt_any_3_select; // @[lsu_trigger.scala 19:53] + wire _T_39 = io_trigger_pkt_any_3_select & io_trigger_pkt_any_3_store; // @[lsu_trigger.scala 19:143] + wire [31:0] _T_41 = _T_38 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_42 = _T_39 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_3 = _T_41 | _T_42; // @[Mux.scala 27:72] + wire _T_44 = ~io_lsu_pkt_m_bits_dma; // @[lsu_trigger.scala 20:70] + wire _T_45 = io_lsu_pkt_m_valid & _T_44; // @[lsu_trigger.scala 20:68] + wire _T_46 = _T_45 & trigger_enable; // @[lsu_trigger.scala 20:93] + wire _T_47 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142] + wire _T_48 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33] + wire _T_50 = _T_48 & _T_17; // @[lsu_trigger.scala 21:58] + wire _T_51 = _T_47 | _T_50; // @[lsu_trigger.scala 20:168] + wire _T_52 = _T_46 & _T_51; // @[lsu_trigger.scala 20:110] + wire _T_55 = &io_trigger_pkt_any_0_tdata2; // @[lib.scala 101:45] + wire _T_56 = ~_T_55; // @[lib.scala 101:39] + wire _T_57 = io_trigger_pkt_any_0_match_pkt & _T_56; // @[lib.scala 101:37] + wire _T_60 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[lib.scala 102:52] + wire _T_61 = _T_57 | _T_60; // @[lib.scala 102:41] + wire _T_63 = &io_trigger_pkt_any_0_tdata2[0]; // @[lib.scala 104:36] + wire _T_64 = _T_63 & _T_57; // @[lib.scala 104:41] + wire _T_67 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[lib.scala 104:78] + wire _T_68 = _T_64 | _T_67; // @[lib.scala 104:23] + wire _T_70 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_71 = _T_70 & _T_57; // @[lib.scala 104:41] + wire _T_74 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[lib.scala 104:78] + wire _T_75 = _T_71 | _T_74; // @[lib.scala 104:23] + wire _T_77 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_78 = _T_77 & _T_57; // @[lib.scala 104:41] + wire _T_81 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[lib.scala 104:78] + wire _T_82 = _T_78 | _T_81; // @[lib.scala 104:23] + wire _T_84 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_85 = _T_84 & _T_57; // @[lib.scala 104:41] + wire _T_88 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[lib.scala 104:78] + wire _T_89 = _T_85 | _T_88; // @[lib.scala 104:23] + wire _T_91 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_92 = _T_91 & _T_57; // @[lib.scala 104:41] + wire _T_95 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[lib.scala 104:78] + wire _T_96 = _T_92 | _T_95; // @[lib.scala 104:23] + wire _T_98 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_99 = _T_98 & _T_57; // @[lib.scala 104:41] + wire _T_102 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[lib.scala 104:78] + wire _T_103 = _T_99 | _T_102; // @[lib.scala 104:23] + wire _T_105 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_106 = _T_105 & _T_57; // @[lib.scala 104:41] + wire _T_109 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[lib.scala 104:78] + wire _T_110 = _T_106 | _T_109; // @[lib.scala 104:23] + wire _T_112 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_113 = _T_112 & _T_57; // @[lib.scala 104:41] + wire _T_116 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[lib.scala 104:78] + wire _T_117 = _T_113 | _T_116; // @[lib.scala 104:23] + wire _T_119 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_120 = _T_119 & _T_57; // @[lib.scala 104:41] + wire _T_123 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[lib.scala 104:78] + wire _T_124 = _T_120 | _T_123; // @[lib.scala 104:23] + wire _T_126 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_127 = _T_126 & _T_57; // @[lib.scala 104:41] + wire _T_130 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[lib.scala 104:78] + wire _T_131 = _T_127 | _T_130; // @[lib.scala 104:23] + wire _T_133 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_134 = _T_133 & _T_57; // @[lib.scala 104:41] + wire _T_137 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[lib.scala 104:78] + wire _T_138 = _T_134 | _T_137; // @[lib.scala 104:23] + wire _T_140 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_141 = _T_140 & _T_57; // @[lib.scala 104:41] + wire _T_144 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[lib.scala 104:78] + wire _T_145 = _T_141 | _T_144; // @[lib.scala 104:23] + wire _T_147 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_148 = _T_147 & _T_57; // @[lib.scala 104:41] + wire _T_151 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[lib.scala 104:78] + wire _T_152 = _T_148 | _T_151; // @[lib.scala 104:23] + wire _T_154 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_155 = _T_154 & _T_57; // @[lib.scala 104:41] + wire _T_158 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[lib.scala 104:78] + wire _T_159 = _T_155 | _T_158; // @[lib.scala 104:23] + wire _T_161 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_162 = _T_161 & _T_57; // @[lib.scala 104:41] + wire _T_165 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[lib.scala 104:78] + wire _T_166 = _T_162 | _T_165; // @[lib.scala 104:23] + wire _T_168 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_169 = _T_168 & _T_57; // @[lib.scala 104:41] + wire _T_172 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[lib.scala 104:78] + wire _T_173 = _T_169 | _T_172; // @[lib.scala 104:23] + wire _T_175 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_176 = _T_175 & _T_57; // @[lib.scala 104:41] + wire _T_179 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[lib.scala 104:78] + wire _T_180 = _T_176 | _T_179; // @[lib.scala 104:23] + wire _T_182 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_183 = _T_182 & _T_57; // @[lib.scala 104:41] + wire _T_186 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[lib.scala 104:78] + wire _T_187 = _T_183 | _T_186; // @[lib.scala 104:23] + wire _T_189 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_190 = _T_189 & _T_57; // @[lib.scala 104:41] + wire _T_193 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[lib.scala 104:78] + wire _T_194 = _T_190 | _T_193; // @[lib.scala 104:23] + wire _T_196 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_197 = _T_196 & _T_57; // @[lib.scala 104:41] + wire _T_200 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[lib.scala 104:78] + wire _T_201 = _T_197 | _T_200; // @[lib.scala 104:23] + wire _T_203 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_204 = _T_203 & _T_57; // @[lib.scala 104:41] + wire _T_207 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[lib.scala 104:78] + wire _T_208 = _T_204 | _T_207; // @[lib.scala 104:23] + wire _T_210 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_211 = _T_210 & _T_57; // @[lib.scala 104:41] + wire _T_214 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[lib.scala 104:78] + wire _T_215 = _T_211 | _T_214; // @[lib.scala 104:23] + wire _T_217 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_218 = _T_217 & _T_57; // @[lib.scala 104:41] + wire _T_221 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[lib.scala 104:78] + wire _T_222 = _T_218 | _T_221; // @[lib.scala 104:23] + wire _T_224 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_225 = _T_224 & _T_57; // @[lib.scala 104:41] + wire _T_228 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[lib.scala 104:78] + wire _T_229 = _T_225 | _T_228; // @[lib.scala 104:23] + wire _T_231 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_232 = _T_231 & _T_57; // @[lib.scala 104:41] + wire _T_235 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[lib.scala 104:78] + wire _T_236 = _T_232 | _T_235; // @[lib.scala 104:23] + wire _T_238 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_239 = _T_238 & _T_57; // @[lib.scala 104:41] + wire _T_242 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[lib.scala 104:78] + wire _T_243 = _T_239 | _T_242; // @[lib.scala 104:23] + wire _T_245 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_246 = _T_245 & _T_57; // @[lib.scala 104:41] + wire _T_249 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[lib.scala 104:78] + wire _T_250 = _T_246 | _T_249; // @[lib.scala 104:23] + wire _T_252 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_253 = _T_252 & _T_57; // @[lib.scala 104:41] + wire _T_256 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[lib.scala 104:78] + wire _T_257 = _T_253 | _T_256; // @[lib.scala 104:23] + wire _T_259 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_260 = _T_259 & _T_57; // @[lib.scala 104:41] + wire _T_263 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[lib.scala 104:78] + wire _T_264 = _T_260 | _T_263; // @[lib.scala 104:23] + wire _T_266 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_267 = _T_266 & _T_57; // @[lib.scala 104:41] + wire _T_270 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[lib.scala 104:78] + wire _T_271 = _T_267 | _T_270; // @[lib.scala 104:23] + wire _T_273 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_274 = _T_273 & _T_57; // @[lib.scala 104:41] + wire _T_277 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[lib.scala 104:78] + wire _T_278 = _T_274 | _T_277; // @[lib.scala 104:23] + wire [7:0] _T_285 = {_T_110,_T_103,_T_96,_T_89,_T_82,_T_75,_T_68,_T_61}; // @[lib.scala 105:14] + wire [15:0] _T_293 = {_T_166,_T_159,_T_152,_T_145,_T_138,_T_131,_T_124,_T_117,_T_285}; // @[lib.scala 105:14] + wire [7:0] _T_300 = {_T_222,_T_215,_T_208,_T_201,_T_194,_T_187,_T_180,_T_173}; // @[lib.scala 105:14] + wire [31:0] _T_309 = {_T_278,_T_271,_T_264,_T_257,_T_250,_T_243,_T_236,_T_229,_T_300,_T_293}; // @[lib.scala 105:14] + wire _T_310 = &_T_309; // @[lib.scala 105:25] + wire _T_311 = _T_52 & _T_310; // @[lsu_trigger.scala 21:92] + wire _T_315 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142] + wire _T_316 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33] + wire _T_318 = _T_316 & _T_24; // @[lsu_trigger.scala 21:58] + wire _T_319 = _T_315 | _T_318; // @[lsu_trigger.scala 20:168] + wire _T_320 = _T_46 & _T_319; // @[lsu_trigger.scala 20:110] + wire _T_323 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 101:45] + wire _T_324 = ~_T_323; // @[lib.scala 101:39] + wire _T_325 = io_trigger_pkt_any_1_match_pkt & _T_324; // @[lib.scala 101:37] + wire _T_328 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 102:52] + wire _T_329 = _T_325 | _T_328; // @[lib.scala 102:41] + wire _T_331 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 104:36] + wire _T_332 = _T_331 & _T_325; // @[lib.scala 104:41] + wire _T_335 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 104:78] + wire _T_336 = _T_332 | _T_335; // @[lib.scala 104:23] + wire _T_338 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_339 = _T_338 & _T_325; // @[lib.scala 104:41] + wire _T_342 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 104:78] + wire _T_343 = _T_339 | _T_342; // @[lib.scala 104:23] + wire _T_345 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_346 = _T_345 & _T_325; // @[lib.scala 104:41] + wire _T_349 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 104:78] + wire _T_350 = _T_346 | _T_349; // @[lib.scala 104:23] + wire _T_352 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_353 = _T_352 & _T_325; // @[lib.scala 104:41] + wire _T_356 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 104:78] + wire _T_357 = _T_353 | _T_356; // @[lib.scala 104:23] + wire _T_359 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_360 = _T_359 & _T_325; // @[lib.scala 104:41] + wire _T_363 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 104:78] + wire _T_364 = _T_360 | _T_363; // @[lib.scala 104:23] + wire _T_366 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_367 = _T_366 & _T_325; // @[lib.scala 104:41] + wire _T_370 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 104:78] + wire _T_371 = _T_367 | _T_370; // @[lib.scala 104:23] + wire _T_373 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_374 = _T_373 & _T_325; // @[lib.scala 104:41] + wire _T_377 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 104:78] + wire _T_378 = _T_374 | _T_377; // @[lib.scala 104:23] + wire _T_380 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_381 = _T_380 & _T_325; // @[lib.scala 104:41] + wire _T_384 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 104:78] + wire _T_385 = _T_381 | _T_384; // @[lib.scala 104:23] + wire _T_387 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_388 = _T_387 & _T_325; // @[lib.scala 104:41] + wire _T_391 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 104:78] + wire _T_392 = _T_388 | _T_391; // @[lib.scala 104:23] + wire _T_394 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_395 = _T_394 & _T_325; // @[lib.scala 104:41] + wire _T_398 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 104:78] + wire _T_399 = _T_395 | _T_398; // @[lib.scala 104:23] + wire _T_401 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_402 = _T_401 & _T_325; // @[lib.scala 104:41] + wire _T_405 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 104:78] + wire _T_406 = _T_402 | _T_405; // @[lib.scala 104:23] + wire _T_408 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_409 = _T_408 & _T_325; // @[lib.scala 104:41] + wire _T_412 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 104:78] + wire _T_413 = _T_409 | _T_412; // @[lib.scala 104:23] + wire _T_415 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_416 = _T_415 & _T_325; // @[lib.scala 104:41] + wire _T_419 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 104:78] + wire _T_420 = _T_416 | _T_419; // @[lib.scala 104:23] + wire _T_422 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_423 = _T_422 & _T_325; // @[lib.scala 104:41] + wire _T_426 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 104:78] + wire _T_427 = _T_423 | _T_426; // @[lib.scala 104:23] + wire _T_429 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_430 = _T_429 & _T_325; // @[lib.scala 104:41] + wire _T_433 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 104:78] + wire _T_434 = _T_430 | _T_433; // @[lib.scala 104:23] + wire _T_436 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_437 = _T_436 & _T_325; // @[lib.scala 104:41] + wire _T_440 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 104:78] + wire _T_441 = _T_437 | _T_440; // @[lib.scala 104:23] + wire _T_443 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_444 = _T_443 & _T_325; // @[lib.scala 104:41] + wire _T_447 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 104:78] + wire _T_448 = _T_444 | _T_447; // @[lib.scala 104:23] + wire _T_450 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_451 = _T_450 & _T_325; // @[lib.scala 104:41] + wire _T_454 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 104:78] + wire _T_455 = _T_451 | _T_454; // @[lib.scala 104:23] + wire _T_457 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_458 = _T_457 & _T_325; // @[lib.scala 104:41] + wire _T_461 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 104:78] + wire _T_462 = _T_458 | _T_461; // @[lib.scala 104:23] + wire _T_464 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_465 = _T_464 & _T_325; // @[lib.scala 104:41] + wire _T_468 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 104:78] + wire _T_469 = _T_465 | _T_468; // @[lib.scala 104:23] + wire _T_471 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_472 = _T_471 & _T_325; // @[lib.scala 104:41] + wire _T_475 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 104:78] + wire _T_476 = _T_472 | _T_475; // @[lib.scala 104:23] + wire _T_478 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_479 = _T_478 & _T_325; // @[lib.scala 104:41] + wire _T_482 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 104:78] + wire _T_483 = _T_479 | _T_482; // @[lib.scala 104:23] + wire _T_485 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_486 = _T_485 & _T_325; // @[lib.scala 104:41] + wire _T_489 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 104:78] + wire _T_490 = _T_486 | _T_489; // @[lib.scala 104:23] + wire _T_492 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_493 = _T_492 & _T_325; // @[lib.scala 104:41] + wire _T_496 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 104:78] + wire _T_497 = _T_493 | _T_496; // @[lib.scala 104:23] + wire _T_499 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_500 = _T_499 & _T_325; // @[lib.scala 104:41] + wire _T_503 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 104:78] + wire _T_504 = _T_500 | _T_503; // @[lib.scala 104:23] + wire _T_506 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_507 = _T_506 & _T_325; // @[lib.scala 104:41] + wire _T_510 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 104:78] + wire _T_511 = _T_507 | _T_510; // @[lib.scala 104:23] + wire _T_513 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_514 = _T_513 & _T_325; // @[lib.scala 104:41] + wire _T_517 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 104:78] + wire _T_518 = _T_514 | _T_517; // @[lib.scala 104:23] + wire _T_520 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_521 = _T_520 & _T_325; // @[lib.scala 104:41] + wire _T_524 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 104:78] + wire _T_525 = _T_521 | _T_524; // @[lib.scala 104:23] + wire _T_527 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_528 = _T_527 & _T_325; // @[lib.scala 104:41] + wire _T_531 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 104:78] + wire _T_532 = _T_528 | _T_531; // @[lib.scala 104:23] + wire _T_534 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_535 = _T_534 & _T_325; // @[lib.scala 104:41] + wire _T_538 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 104:78] + wire _T_539 = _T_535 | _T_538; // @[lib.scala 104:23] + wire _T_541 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_542 = _T_541 & _T_325; // @[lib.scala 104:41] + wire _T_545 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 104:78] + wire _T_546 = _T_542 | _T_545; // @[lib.scala 104:23] + wire [7:0] _T_553 = {_T_378,_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329}; // @[lib.scala 105:14] + wire [15:0] _T_561 = {_T_434,_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_553}; // @[lib.scala 105:14] + wire [7:0] _T_568 = {_T_490,_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441}; // @[lib.scala 105:14] + wire [31:0] _T_577 = {_T_546,_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_568,_T_561}; // @[lib.scala 105:14] + wire _T_578 = &_T_577; // @[lib.scala 105:25] + wire _T_579 = _T_320 & _T_578; // @[lsu_trigger.scala 21:92] + wire _T_583 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142] + wire _T_584 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33] + wire _T_586 = _T_584 & _T_31; // @[lsu_trigger.scala 21:58] + wire _T_587 = _T_583 | _T_586; // @[lsu_trigger.scala 20:168] + wire _T_588 = _T_46 & _T_587; // @[lsu_trigger.scala 20:110] + wire _T_591 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 101:45] + wire _T_592 = ~_T_591; // @[lib.scala 101:39] + wire _T_593 = io_trigger_pkt_any_2_match_pkt & _T_592; // @[lib.scala 101:37] + wire _T_596 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 102:52] + wire _T_597 = _T_593 | _T_596; // @[lib.scala 102:41] + wire _T_599 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 104:36] + wire _T_600 = _T_599 & _T_593; // @[lib.scala 104:41] + wire _T_603 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 104:78] + wire _T_604 = _T_600 | _T_603; // @[lib.scala 104:23] + wire _T_606 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_607 = _T_606 & _T_593; // @[lib.scala 104:41] + wire _T_610 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 104:78] + wire _T_611 = _T_607 | _T_610; // @[lib.scala 104:23] + wire _T_613 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_614 = _T_613 & _T_593; // @[lib.scala 104:41] + wire _T_617 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 104:78] + wire _T_618 = _T_614 | _T_617; // @[lib.scala 104:23] + wire _T_620 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_621 = _T_620 & _T_593; // @[lib.scala 104:41] + wire _T_624 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 104:78] + wire _T_625 = _T_621 | _T_624; // @[lib.scala 104:23] + wire _T_627 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_628 = _T_627 & _T_593; // @[lib.scala 104:41] + wire _T_631 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 104:78] + wire _T_632 = _T_628 | _T_631; // @[lib.scala 104:23] + wire _T_634 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_635 = _T_634 & _T_593; // @[lib.scala 104:41] + wire _T_638 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 104:78] + wire _T_639 = _T_635 | _T_638; // @[lib.scala 104:23] + wire _T_641 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_642 = _T_641 & _T_593; // @[lib.scala 104:41] + wire _T_645 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 104:78] + wire _T_646 = _T_642 | _T_645; // @[lib.scala 104:23] + wire _T_648 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_649 = _T_648 & _T_593; // @[lib.scala 104:41] + wire _T_652 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 104:78] + wire _T_653 = _T_649 | _T_652; // @[lib.scala 104:23] + wire _T_655 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_656 = _T_655 & _T_593; // @[lib.scala 104:41] + wire _T_659 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 104:78] + wire _T_660 = _T_656 | _T_659; // @[lib.scala 104:23] + wire _T_662 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_663 = _T_662 & _T_593; // @[lib.scala 104:41] + wire _T_666 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 104:78] + wire _T_667 = _T_663 | _T_666; // @[lib.scala 104:23] + wire _T_669 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_670 = _T_669 & _T_593; // @[lib.scala 104:41] + wire _T_673 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 104:78] + wire _T_674 = _T_670 | _T_673; // @[lib.scala 104:23] + wire _T_676 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_677 = _T_676 & _T_593; // @[lib.scala 104:41] + wire _T_680 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 104:78] + wire _T_681 = _T_677 | _T_680; // @[lib.scala 104:23] + wire _T_683 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_684 = _T_683 & _T_593; // @[lib.scala 104:41] + wire _T_687 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 104:78] + wire _T_688 = _T_684 | _T_687; // @[lib.scala 104:23] + wire _T_690 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_691 = _T_690 & _T_593; // @[lib.scala 104:41] + wire _T_694 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 104:78] + wire _T_695 = _T_691 | _T_694; // @[lib.scala 104:23] + wire _T_697 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_698 = _T_697 & _T_593; // @[lib.scala 104:41] + wire _T_701 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 104:78] + wire _T_702 = _T_698 | _T_701; // @[lib.scala 104:23] + wire _T_704 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_705 = _T_704 & _T_593; // @[lib.scala 104:41] + wire _T_708 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 104:78] + wire _T_709 = _T_705 | _T_708; // @[lib.scala 104:23] + wire _T_711 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_712 = _T_711 & _T_593; // @[lib.scala 104:41] + wire _T_715 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 104:78] + wire _T_716 = _T_712 | _T_715; // @[lib.scala 104:23] + wire _T_718 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_719 = _T_718 & _T_593; // @[lib.scala 104:41] + wire _T_722 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 104:78] + wire _T_723 = _T_719 | _T_722; // @[lib.scala 104:23] + wire _T_725 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_726 = _T_725 & _T_593; // @[lib.scala 104:41] + wire _T_729 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 104:78] + wire _T_730 = _T_726 | _T_729; // @[lib.scala 104:23] + wire _T_732 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_733 = _T_732 & _T_593; // @[lib.scala 104:41] + wire _T_736 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 104:78] + wire _T_737 = _T_733 | _T_736; // @[lib.scala 104:23] + wire _T_739 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_740 = _T_739 & _T_593; // @[lib.scala 104:41] + wire _T_743 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 104:78] + wire _T_744 = _T_740 | _T_743; // @[lib.scala 104:23] + wire _T_746 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_747 = _T_746 & _T_593; // @[lib.scala 104:41] + wire _T_750 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 104:78] + wire _T_751 = _T_747 | _T_750; // @[lib.scala 104:23] + wire _T_753 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_754 = _T_753 & _T_593; // @[lib.scala 104:41] + wire _T_757 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 104:78] + wire _T_758 = _T_754 | _T_757; // @[lib.scala 104:23] + wire _T_760 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_761 = _T_760 & _T_593; // @[lib.scala 104:41] + wire _T_764 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 104:78] + wire _T_765 = _T_761 | _T_764; // @[lib.scala 104:23] + wire _T_767 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_768 = _T_767 & _T_593; // @[lib.scala 104:41] + wire _T_771 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 104:78] + wire _T_772 = _T_768 | _T_771; // @[lib.scala 104:23] + wire _T_774 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_775 = _T_774 & _T_593; // @[lib.scala 104:41] + wire _T_778 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 104:78] + wire _T_779 = _T_775 | _T_778; // @[lib.scala 104:23] + wire _T_781 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_782 = _T_781 & _T_593; // @[lib.scala 104:41] + wire _T_785 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 104:78] + wire _T_786 = _T_782 | _T_785; // @[lib.scala 104:23] + wire _T_788 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_789 = _T_788 & _T_593; // @[lib.scala 104:41] + wire _T_792 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 104:78] + wire _T_793 = _T_789 | _T_792; // @[lib.scala 104:23] + wire _T_795 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_796 = _T_795 & _T_593; // @[lib.scala 104:41] + wire _T_799 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 104:78] + wire _T_800 = _T_796 | _T_799; // @[lib.scala 104:23] + wire _T_802 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_803 = _T_802 & _T_593; // @[lib.scala 104:41] + wire _T_806 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 104:78] + wire _T_807 = _T_803 | _T_806; // @[lib.scala 104:23] + wire _T_809 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_810 = _T_809 & _T_593; // @[lib.scala 104:41] + wire _T_813 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 104:78] + wire _T_814 = _T_810 | _T_813; // @[lib.scala 104:23] + wire [7:0] _T_821 = {_T_646,_T_639,_T_632,_T_625,_T_618,_T_611,_T_604,_T_597}; // @[lib.scala 105:14] + wire [15:0] _T_829 = {_T_702,_T_695,_T_688,_T_681,_T_674,_T_667,_T_660,_T_653,_T_821}; // @[lib.scala 105:14] + wire [7:0] _T_836 = {_T_758,_T_751,_T_744,_T_737,_T_730,_T_723,_T_716,_T_709}; // @[lib.scala 105:14] + wire [31:0] _T_845 = {_T_814,_T_807,_T_800,_T_793,_T_786,_T_779,_T_772,_T_765,_T_836,_T_829}; // @[lib.scala 105:14] + wire _T_846 = &_T_845; // @[lib.scala 105:25] + wire _T_847 = _T_588 & _T_846; // @[lsu_trigger.scala 21:92] + wire _T_851 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142] + wire _T_852 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33] + wire _T_854 = _T_852 & _T_38; // @[lsu_trigger.scala 21:58] + wire _T_855 = _T_851 | _T_854; // @[lsu_trigger.scala 20:168] + wire _T_856 = _T_46 & _T_855; // @[lsu_trigger.scala 20:110] + wire _T_859 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 101:45] + wire _T_860 = ~_T_859; // @[lib.scala 101:39] + wire _T_861 = io_trigger_pkt_any_3_match_pkt & _T_860; // @[lib.scala 101:37] + wire _T_864 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 102:52] + wire _T_865 = _T_861 | _T_864; // @[lib.scala 102:41] + wire _T_867 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 104:36] + wire _T_868 = _T_867 & _T_861; // @[lib.scala 104:41] + wire _T_871 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 104:78] + wire _T_872 = _T_868 | _T_871; // @[lib.scala 104:23] + wire _T_874 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_875 = _T_874 & _T_861; // @[lib.scala 104:41] + wire _T_878 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 104:78] + wire _T_879 = _T_875 | _T_878; // @[lib.scala 104:23] + wire _T_881 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_882 = _T_881 & _T_861; // @[lib.scala 104:41] + wire _T_885 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 104:78] + wire _T_886 = _T_882 | _T_885; // @[lib.scala 104:23] + wire _T_888 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_889 = _T_888 & _T_861; // @[lib.scala 104:41] + wire _T_892 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 104:78] + wire _T_893 = _T_889 | _T_892; // @[lib.scala 104:23] + wire _T_895 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_896 = _T_895 & _T_861; // @[lib.scala 104:41] + wire _T_899 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 104:78] + wire _T_900 = _T_896 | _T_899; // @[lib.scala 104:23] + wire _T_902 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_903 = _T_902 & _T_861; // @[lib.scala 104:41] + wire _T_906 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 104:78] + wire _T_907 = _T_903 | _T_906; // @[lib.scala 104:23] + wire _T_909 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_910 = _T_909 & _T_861; // @[lib.scala 104:41] + wire _T_913 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 104:78] + wire _T_914 = _T_910 | _T_913; // @[lib.scala 104:23] + wire _T_916 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_917 = _T_916 & _T_861; // @[lib.scala 104:41] + wire _T_920 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 104:78] + wire _T_921 = _T_917 | _T_920; // @[lib.scala 104:23] + wire _T_923 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_924 = _T_923 & _T_861; // @[lib.scala 104:41] + wire _T_927 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 104:78] + wire _T_928 = _T_924 | _T_927; // @[lib.scala 104:23] + wire _T_930 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_931 = _T_930 & _T_861; // @[lib.scala 104:41] + wire _T_934 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 104:78] + wire _T_935 = _T_931 | _T_934; // @[lib.scala 104:23] + wire _T_937 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_938 = _T_937 & _T_861; // @[lib.scala 104:41] + wire _T_941 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 104:78] + wire _T_942 = _T_938 | _T_941; // @[lib.scala 104:23] + wire _T_944 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_945 = _T_944 & _T_861; // @[lib.scala 104:41] + wire _T_948 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 104:78] + wire _T_949 = _T_945 | _T_948; // @[lib.scala 104:23] + wire _T_951 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_952 = _T_951 & _T_861; // @[lib.scala 104:41] + wire _T_955 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 104:78] + wire _T_956 = _T_952 | _T_955; // @[lib.scala 104:23] + wire _T_958 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_959 = _T_958 & _T_861; // @[lib.scala 104:41] + wire _T_962 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 104:78] + wire _T_963 = _T_959 | _T_962; // @[lib.scala 104:23] + wire _T_965 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_966 = _T_965 & _T_861; // @[lib.scala 104:41] + wire _T_969 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 104:78] + wire _T_970 = _T_966 | _T_969; // @[lib.scala 104:23] + wire _T_972 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_973 = _T_972 & _T_861; // @[lib.scala 104:41] + wire _T_976 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 104:78] + wire _T_977 = _T_973 | _T_976; // @[lib.scala 104:23] + wire _T_979 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_980 = _T_979 & _T_861; // @[lib.scala 104:41] + wire _T_983 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 104:78] + wire _T_984 = _T_980 | _T_983; // @[lib.scala 104:23] + wire _T_986 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_987 = _T_986 & _T_861; // @[lib.scala 104:41] + wire _T_990 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 104:78] + wire _T_991 = _T_987 | _T_990; // @[lib.scala 104:23] + wire _T_993 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_994 = _T_993 & _T_861; // @[lib.scala 104:41] + wire _T_997 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 104:78] + wire _T_998 = _T_994 | _T_997; // @[lib.scala 104:23] + wire _T_1000 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_1001 = _T_1000 & _T_861; // @[lib.scala 104:41] + wire _T_1004 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 104:78] + wire _T_1005 = _T_1001 | _T_1004; // @[lib.scala 104:23] + wire _T_1007 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_1008 = _T_1007 & _T_861; // @[lib.scala 104:41] + wire _T_1011 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 104:78] + wire _T_1012 = _T_1008 | _T_1011; // @[lib.scala 104:23] + wire _T_1014 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_1015 = _T_1014 & _T_861; // @[lib.scala 104:41] + wire _T_1018 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 104:78] + wire _T_1019 = _T_1015 | _T_1018; // @[lib.scala 104:23] + wire _T_1021 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_1022 = _T_1021 & _T_861; // @[lib.scala 104:41] + wire _T_1025 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 104:78] + wire _T_1026 = _T_1022 | _T_1025; // @[lib.scala 104:23] + wire _T_1028 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_1029 = _T_1028 & _T_861; // @[lib.scala 104:41] + wire _T_1032 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 104:78] + wire _T_1033 = _T_1029 | _T_1032; // @[lib.scala 104:23] + wire _T_1035 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_1036 = _T_1035 & _T_861; // @[lib.scala 104:41] + wire _T_1039 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 104:78] + wire _T_1040 = _T_1036 | _T_1039; // @[lib.scala 104:23] + wire _T_1042 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_1043 = _T_1042 & _T_861; // @[lib.scala 104:41] + wire _T_1046 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 104:78] + wire _T_1047 = _T_1043 | _T_1046; // @[lib.scala 104:23] + wire _T_1049 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_1050 = _T_1049 & _T_861; // @[lib.scala 104:41] + wire _T_1053 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 104:78] + wire _T_1054 = _T_1050 | _T_1053; // @[lib.scala 104:23] + wire _T_1056 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_1057 = _T_1056 & _T_861; // @[lib.scala 104:41] + wire _T_1060 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 104:78] + wire _T_1061 = _T_1057 | _T_1060; // @[lib.scala 104:23] + wire _T_1063 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_1064 = _T_1063 & _T_861; // @[lib.scala 104:41] + wire _T_1067 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 104:78] + wire _T_1068 = _T_1064 | _T_1067; // @[lib.scala 104:23] + wire _T_1070 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_1071 = _T_1070 & _T_861; // @[lib.scala 104:41] + wire _T_1074 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 104:78] + wire _T_1075 = _T_1071 | _T_1074; // @[lib.scala 104:23] + wire _T_1077 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_1078 = _T_1077 & _T_861; // @[lib.scala 104:41] + wire _T_1081 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 104:78] + wire _T_1082 = _T_1078 | _T_1081; // @[lib.scala 104:23] + wire [7:0] _T_1089 = {_T_914,_T_907,_T_900,_T_893,_T_886,_T_879,_T_872,_T_865}; // @[lib.scala 105:14] + wire [15:0] _T_1097 = {_T_970,_T_963,_T_956,_T_949,_T_942,_T_935,_T_928,_T_921,_T_1089}; // @[lib.scala 105:14] + wire [7:0] _T_1104 = {_T_1026,_T_1019,_T_1012,_T_1005,_T_998,_T_991,_T_984,_T_977}; // @[lib.scala 105:14] + wire [31:0] _T_1113 = {_T_1082,_T_1075,_T_1068,_T_1061,_T_1054,_T_1047,_T_1040,_T_1033,_T_1104,_T_1097}; // @[lib.scala 105:14] + wire _T_1114 = &_T_1113; // @[lib.scala 105:25] + wire _T_1115 = _T_856 & _T_1114; // @[lsu_trigger.scala 21:92] + wire [2:0] _T_1117 = {_T_1115,_T_847,_T_579}; // @[Cat.scala 29:58] + assign io_lsu_trigger_match_m = {_T_1117,_T_311}; // @[lsu_trigger.scala 20:25] +endmodule +module lsu_clkdomain( + input clock, + input io_clk_override, + input io_lsu_busreq_r, + input io_lsu_bus_buffer_pend_any, + input io_lsu_bus_buffer_empty_any, + input io_lsu_bus_clk_en, + output io_lsu_bus_obuf_c1_clken, + output io_lsu_busm_clken, + output io_lsu_c1_m_clk, + output io_lsu_c1_r_clk, + output io_lsu_c2_m_clk, + output io_lsu_c2_r_clk, + output io_lsu_store_c1_m_clk, + output io_lsu_store_c1_r_clk, + output io_lsu_stbuf_c1_clk, + output io_lsu_bus_ibuf_c1_clk, + output io_lsu_bus_buf_c1_clk, + output io_lsu_free_c2_clk +); + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire _T_8 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[lsu_clkdomain.scala 74:62] + wire _T_9 = _T_8 | io_clk_override; // @[lsu_clkdomain.scala 74:80] + wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[lsu_clkdomain.scala 75:32] + wire _T_12 = _T_11 | io_lsu_busreq_r; // @[lsu_clkdomain.scala 75:61] + wire _T_24 = _T_12 | io_clk_override; // @[lsu_clkdomain.scala 79:72] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + assign io_lsu_bus_obuf_c1_clken = _T_9 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 74:30] + assign io_lsu_busm_clken = _T_24 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 79:21] + assign io_lsu_c1_m_clk = clock; // @[lsu_clkdomain.scala 87:26] + assign io_lsu_c1_r_clk = clock; // @[lsu_clkdomain.scala 88:26] + assign io_lsu_c2_m_clk = clock; // @[lsu_clkdomain.scala 89:26] + assign io_lsu_c2_r_clk = clock; // @[lsu_clkdomain.scala 90:26] + assign io_lsu_store_c1_m_clk = clock; // @[lsu_clkdomain.scala 91:26] + assign io_lsu_store_c1_r_clk = clock; // @[lsu_clkdomain.scala 92:26] + assign io_lsu_stbuf_c1_clk = clock; // @[lsu_clkdomain.scala 93:26] + assign io_lsu_bus_ibuf_c1_clk = clock; // @[lsu_clkdomain.scala 94:26] + assign io_lsu_bus_buf_c1_clk = clock; // @[lsu_clkdomain.scala 96:26] + assign io_lsu_free_c2_clk = clock; // @[lsu_clkdomain.scala 98:26] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_lsu_bus_obuf_c1_clken; // @[lib.scala 345:16] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_lsu_busm_clken; // @[lib.scala 345:16] +endmodule +module lsu_bus_buffer( + input clock, + input reset, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + input io_dec_tlu_force_halt, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_dec_lsu_valid_raw_d, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input [31:0] io_lsu_addr_m, + input [31:0] io_end_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_r, + input [31:0] io_store_data_r, + input io_no_word_merge_r, + input io_no_dword_merge_r, + input io_lsu_busreq_m, + input io_ld_full_hit_m, + input io_flush_m_up, + input io_flush_r, + input io_lsu_commit_r, + input io_is_sideeffects_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [7:0] io_ldst_byteen_ext_m, + input io_lsu_axi_aw_ready, + output io_lsu_axi_aw_valid, + output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, + input io_lsu_axi_w_ready, + output io_lsu_axi_w_valid, + output [63:0] io_lsu_axi_w_bits_data, + output io_lsu_axi_b_ready, + input io_lsu_axi_b_valid, + input [1:0] io_lsu_axi_b_bits_resp, + input [2:0] io_lsu_axi_b_bits_id, + input io_lsu_axi_ar_ready, + output io_lsu_axi_ar_valid, + output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, + output io_lsu_axi_r_ready, + input io_lsu_axi_r_valid, + input [2:0] io_lsu_axi_r_bits_id, + input [63:0] io_lsu_axi_r_bits_data, + input [1:0] io_lsu_axi_r_bits_resp, + input io_lsu_bus_clk_en, + input io_lsu_bus_clk_en_q, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [3:0] io_ld_byte_hit_buf_lo, + output [3:0] io_ld_byte_hit_buf_hi, + output [31:0] io_ld_fwddata_buf_lo, + output [31:0] io_ld_fwddata_buf_hi, + output [31:0] io_lsu_nonblock_load_data +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [63:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [31:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; + reg [31:0] _RAND_91; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_11_io_en; // @[lib.scala 404:23] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 77:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 78:46] + reg [31:0] buf_addr_0; // @[Reg.scala 27:20] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 80:74] + reg _T_4355; // @[Reg.scala 27:20] + reg _T_4352; // @[Reg.scala 27:20] + reg _T_4349; // @[Reg.scala 27:20] + reg _T_4346; // @[Reg.scala 27:20] + wire [3:0] buf_write = {_T_4355,_T_4352,_T_4349,_T_4346}; // @[Cat.scala 29:58] + wire _T_4 = _T_2 & buf_write[0]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_0; // @[Reg.scala 27:20] + wire _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_1; // @[Reg.scala 27:20] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_1; // @[Reg.scala 27:20] + wire _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_2; // @[Reg.scala 27:20] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_2; // @[Reg.scala 27:20] + wire _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_3; // @[Reg.scala 27:20] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_3; // @[Reg.scala 27:20] + wire _T_26 = buf_state_3 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_27 = _T_25 & _T_26; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_32 = _T_30 & buf_write[0]; // @[lsu_bus_buffer.scala 81:98] + wire _T_34 = _T_32 & _T_5; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_39 = _T_37 & buf_write[1]; // @[lsu_bus_buffer.scala 81:98] + wire _T_41 = _T_39 & _T_12; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_46 = _T_44 & buf_write[2]; // @[lsu_bus_buffer.scala 81:98] + wire _T_48 = _T_46 & _T_19; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_53 = _T_51 & buf_write[3]; // @[lsu_bus_buffer.scala 81:98] + wire _T_55 = _T_53 & _T_26; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] + reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 513:60] + wire _T_2590 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_4104 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4127 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4131 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] + reg obuf_valid; // @[lsu_bus_buffer.scala 349:54] + wire _T_4165 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4250 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4268 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4276 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_2594 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 417:132] + wire _T_2595 = buf_ageQ_3[3] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2583 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3913 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3936 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3940 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3974 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4059 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4077 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4085 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_2588 = buf_ageQ_3[2] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2576 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3722 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3745 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3749 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3783 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3868 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3886 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3894 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_2581 = buf_ageQ_3[1] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2569 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3531 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3554 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3558 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3592 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3677 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3695 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3703 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_2574 = buf_ageQ_3[0] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_3 = {_T_2595,_T_2588,_T_2581,_T_2574}; // @[Cat.scala 29:58] + wire _T_2694 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2696 = _T_2694 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2688 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2690 = _T_2688 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire _T_2682 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2684 = _T_2682 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_3 = {1'h0,_T_2696,_T_2690,_T_2684}; // @[Cat.scala 29:58] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 150:144] + wire _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 150:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 150:97] + reg [31:0] ibuf_addr; // @[Reg.scala 27:20] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 156:51] + reg ibuf_write; // @[Reg.scala 27:20] + wire _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 156:73] + reg ibuf_valid; // @[lsu_bus_buffer.scala 244:54] + wire _T_514 = _T_513 & ibuf_valid; // @[lsu_bus_buffer.scala 156:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 156:99] + wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[lsu_bus_buffer.scala 161:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 161:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 150:150] + wire _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 513:60] + wire _T_2564 = buf_ageQ_2[3] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2557 = buf_ageQ_2[2] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2550 = buf_ageQ_2[1] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2543 = buf_ageQ_2[0] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_2 = {_T_2564,_T_2557,_T_2550,_T_2543}; // @[Cat.scala 29:58] + wire _T_2673 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2675 = _T_2673 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2661 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2663 = _T_2661 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire _T_2655 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2657 = _T_2655 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_2 = {_T_2675,1'h0,_T_2663,_T_2657}; // @[Cat.scala 29:58] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_248 = |_T_247; // @[lsu_bus_buffer.scala 150:144] + wire _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 150:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 150:97] + wire _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 513:60] + wire _T_2533 = buf_ageQ_1[3] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2526 = buf_ageQ_1[2] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2519 = buf_ageQ_1[1] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2512 = buf_ageQ_1[0] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_1 = {_T_2533,_T_2526,_T_2519,_T_2512}; // @[Cat.scala 29:58] + wire _T_2646 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2648 = _T_2646 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2640 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2642 = _T_2640 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2628 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2630 = _T_2628 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_1 = {_T_2648,_T_2642,1'h0,_T_2630}; // @[Cat.scala 29:58] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_240 = |_T_239; // @[lsu_bus_buffer.scala 150:144] + wire _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 150:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 150:97] + wire _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 513:60] + wire _T_2502 = buf_ageQ_0[3] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2495 = buf_ageQ_0[2] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2488 = buf_ageQ_0[1] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2481 = buf_ageQ_0[0] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_0 = {_T_2502,_T_2495,_T_2488,_T_2481}; // @[Cat.scala 29:58] + wire _T_2619 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2621 = _T_2619 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2613 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2615 = _T_2613 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2607 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2609 = _T_2607 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_0 = {_T_2621,_T_2615,_T_2609,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_232 = |_T_231; // @[lsu_bus_buffer.scala 150:144] + wire _T_233 = ~_T_232; // @[lsu_bus_buffer.scala 150:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[lsu_bus_buffer.scala 150:97] + wire _T_237 = _T_234 & _T_260; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[lsu_bus_buffer.scala 142:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 142:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_291 = |_T_290; // @[lsu_bus_buffer.scala 150:144] + wire _T_292 = ~_T_291; // @[lsu_bus_buffer.scala 150:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[lsu_bus_buffer.scala 150:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 150:150] + wire _T_296 = _T_293 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_283 = |_T_282; // @[lsu_bus_buffer.scala 150:144] + wire _T_284 = ~_T_283; // @[lsu_bus_buffer.scala 150:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[lsu_bus_buffer.scala 150:97] + wire _T_288 = _T_285 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_275 = |_T_274; // @[lsu_bus_buffer.scala 150:144] + wire _T_276 = ~_T_275; // @[lsu_bus_buffer.scala 150:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[lsu_bus_buffer.scala 150:97] + wire _T_280 = _T_277 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_267 = |_T_266; // @[lsu_bus_buffer.scala 150:144] + wire _T_268 = ~_T_267; // @[lsu_bus_buffer.scala 150:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[lsu_bus_buffer.scala 150:97] + wire _T_272 = _T_269 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[lsu_bus_buffer.scala 142:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 142:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_326 = |_T_325; // @[lsu_bus_buffer.scala 150:144] + wire _T_327 = ~_T_326; // @[lsu_bus_buffer.scala 150:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[lsu_bus_buffer.scala 150:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 150:150] + wire _T_331 = _T_328 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_318 = |_T_317; // @[lsu_bus_buffer.scala 150:144] + wire _T_319 = ~_T_318; // @[lsu_bus_buffer.scala 150:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[lsu_bus_buffer.scala 150:97] + wire _T_323 = _T_320 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_310 = |_T_309; // @[lsu_bus_buffer.scala 150:144] + wire _T_311 = ~_T_310; // @[lsu_bus_buffer.scala 150:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[lsu_bus_buffer.scala 150:97] + wire _T_315 = _T_312 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_302 = |_T_301; // @[lsu_bus_buffer.scala 150:144] + wire _T_303 = ~_T_302; // @[lsu_bus_buffer.scala 150:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[lsu_bus_buffer.scala 150:97] + wire _T_307 = _T_304 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[lsu_bus_buffer.scala 142:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 142:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_361 = |_T_360; // @[lsu_bus_buffer.scala 150:144] + wire _T_362 = ~_T_361; // @[lsu_bus_buffer.scala 150:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[lsu_bus_buffer.scala 150:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 150:150] + wire _T_366 = _T_363 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_353 = |_T_352; // @[lsu_bus_buffer.scala 150:144] + wire _T_354 = ~_T_353; // @[lsu_bus_buffer.scala 150:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[lsu_bus_buffer.scala 150:97] + wire _T_358 = _T_355 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_345 = |_T_344; // @[lsu_bus_buffer.scala 150:144] + wire _T_346 = ~_T_345; // @[lsu_bus_buffer.scala 150:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[lsu_bus_buffer.scala 150:97] + wire _T_350 = _T_347 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_337 = |_T_336; // @[lsu_bus_buffer.scala 150:144] + wire _T_338 = ~_T_337; // @[lsu_bus_buffer.scala 150:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[lsu_bus_buffer.scala 150:97] + wire _T_342 = _T_339 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[lsu_bus_buffer.scala 142:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 142:77] + wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_396 = |_T_395; // @[lsu_bus_buffer.scala 151:144] + wire _T_397 = ~_T_396; // @[lsu_bus_buffer.scala 151:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[lsu_bus_buffer.scala 151:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 157:51] + wire _T_518 = _T_517 & ibuf_write; // @[lsu_bus_buffer.scala 157:73] + wire _T_519 = _T_518 & ibuf_valid; // @[lsu_bus_buffer.scala 157:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 157:99] + wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[lsu_bus_buffer.scala 162:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[lsu_bus_buffer.scala 162:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 151:150] + wire _T_401 = _T_398 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_388 = |_T_387; // @[lsu_bus_buffer.scala 151:144] + wire _T_389 = ~_T_388; // @[lsu_bus_buffer.scala 151:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[lsu_bus_buffer.scala 151:97] + wire _T_393 = _T_390 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_380 = |_T_379; // @[lsu_bus_buffer.scala 151:144] + wire _T_381 = ~_T_380; // @[lsu_bus_buffer.scala 151:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[lsu_bus_buffer.scala 151:97] + wire _T_385 = _T_382 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_372 = |_T_371; // @[lsu_bus_buffer.scala 151:144] + wire _T_373 = ~_T_372; // @[lsu_bus_buffer.scala 151:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[lsu_bus_buffer.scala 151:97] + wire _T_377 = _T_374 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[lsu_bus_buffer.scala 143:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 143:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_431 = |_T_430; // @[lsu_bus_buffer.scala 151:144] + wire _T_432 = ~_T_431; // @[lsu_bus_buffer.scala 151:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[lsu_bus_buffer.scala 151:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 151:150] + wire _T_436 = _T_433 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_423 = |_T_422; // @[lsu_bus_buffer.scala 151:144] + wire _T_424 = ~_T_423; // @[lsu_bus_buffer.scala 151:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[lsu_bus_buffer.scala 151:97] + wire _T_428 = _T_425 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_415 = |_T_414; // @[lsu_bus_buffer.scala 151:144] + wire _T_416 = ~_T_415; // @[lsu_bus_buffer.scala 151:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[lsu_bus_buffer.scala 151:97] + wire _T_420 = _T_417 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_407 = |_T_406; // @[lsu_bus_buffer.scala 151:144] + wire _T_408 = ~_T_407; // @[lsu_bus_buffer.scala 151:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[lsu_bus_buffer.scala 151:97] + wire _T_412 = _T_409 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[lsu_bus_buffer.scala 143:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 143:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_466 = |_T_465; // @[lsu_bus_buffer.scala 151:144] + wire _T_467 = ~_T_466; // @[lsu_bus_buffer.scala 151:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[lsu_bus_buffer.scala 151:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 151:150] + wire _T_471 = _T_468 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_458 = |_T_457; // @[lsu_bus_buffer.scala 151:144] + wire _T_459 = ~_T_458; // @[lsu_bus_buffer.scala 151:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[lsu_bus_buffer.scala 151:97] + wire _T_463 = _T_460 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_450 = |_T_449; // @[lsu_bus_buffer.scala 151:144] + wire _T_451 = ~_T_450; // @[lsu_bus_buffer.scala 151:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[lsu_bus_buffer.scala 151:97] + wire _T_455 = _T_452 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_442 = |_T_441; // @[lsu_bus_buffer.scala 151:144] + wire _T_443 = ~_T_442; // @[lsu_bus_buffer.scala 151:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[lsu_bus_buffer.scala 151:97] + wire _T_447 = _T_444 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[lsu_bus_buffer.scala 143:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 143:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_501 = |_T_500; // @[lsu_bus_buffer.scala 151:144] + wire _T_502 = ~_T_501; // @[lsu_bus_buffer.scala 151:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[lsu_bus_buffer.scala 151:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 151:150] + wire _T_506 = _T_503 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_493 = |_T_492; // @[lsu_bus_buffer.scala 151:144] + wire _T_494 = ~_T_493; // @[lsu_bus_buffer.scala 151:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[lsu_bus_buffer.scala 151:97] + wire _T_498 = _T_495 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_485 = |_T_484; // @[lsu_bus_buffer.scala 151:144] + wire _T_486 = ~_T_485; // @[lsu_bus_buffer.scala 151:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[lsu_bus_buffer.scala 151:97] + wire _T_490 = _T_487 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_477 = |_T_476; // @[lsu_bus_buffer.scala 151:144] + wire _T_478 = ~_T_477; // @[lsu_bus_buffer.scala 151:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[lsu_bus_buffer.scala 151:97] + wire _T_482 = _T_479 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[lsu_bus_buffer.scala 143:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 143:77] + wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] + wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58] + wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] + wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_0; // @[Reg.scala 27:20] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_1; // @[Reg.scala 27:20] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_2; // @[Reg.scala 27:20] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_3; // @[Reg.scala 27:20] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 172:97] + wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] + reg [31:0] ibuf_data; // @[Reg.scala 27:20] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 173:32] + wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[lsu_bus_buffer.scala 178:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[lsu_bus_buffer.scala 178:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[lsu_bus_buffer.scala 178:97] + wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[lsu_bus_buffer.scala 179:32] + wire [3:0] _T_750 = io_lsu_pkt_r_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_751 = io_lsu_pkt_r_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_752 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[lsu_bus_buffer.scala 186:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[lsu_bus_buffer.scala 187:24] + wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[lsu_bus_buffer.scala 188:24] + wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[lsu_bus_buffer.scala 189:24] + wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72] + wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72] + wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72] + wire [31:0] _T_802 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58] + wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58] + wire [31:0] _T_810 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72] + wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72] + wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] + wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] + wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[lsu_bus_buffer.scala 207:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[lsu_bus_buffer.scala 209:31] + wire _T_845 = io_lsu_pkt_r_bits_word & _T_756; // @[Mux.scala 27:72] + wire _T_846 = io_lsu_pkt_r_bits_half & _T_844; // @[Mux.scala 27:72] + wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] + wire is_aligned_r = _T_848 | io_lsu_pkt_r_bits_by; // @[Mux.scala 27:72] + wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[lsu_bus_buffer.scala 211:60] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[lsu_bus_buffer.scala 211:34] + wire _T_852 = ~ibuf_valid; // @[lsu_bus_buffer.scala 211:84] + wire ibuf_byp = _T_851 & _T_852; // @[lsu_bus_buffer.scala 211:82] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[lsu_bus_buffer.scala 212:36] + wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 212:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 212:54] + wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 214:36] + reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 257:55] + wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 220:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 220:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 239:54] + wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 239:80] + wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 239:93] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 239:129] + wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 239:106] + wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 239:152] + wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 239:150] + wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 239:175] + wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 239:173] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 240:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 220:98] + wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 220:82] + wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 220:80] + wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 221:5] + wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 215:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 215:42] + wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 215:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 215:120] + wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 215:100] + wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 215:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 221:16] + reg ibuf_sideeffect; // @[Reg.scala 27:20] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 221:35] + wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 221:55] + wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 221:53] + wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 221:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 220:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 214:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 214:49] + reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 627:49] + reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 626:49] + reg [1:0] ibuf_tag; // @[Reg.scala 27:20] + wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 230:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 234:46] + wire [31:0] ibuf_data_in = {_T_920,_T_911,_T_902,_T_893}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 237:60] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 237:95] + wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 241:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 241:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 241:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 241:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 241:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 241:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 241:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 241:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 241:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 241:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 242:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 244:58] + wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 244:93] + reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] + reg ibuf_dual; // @[Reg.scala 27:20] + reg ibuf_samedw; // @[Reg.scala 27:20] + reg ibuf_nomerge; // @[Reg.scala 27:20] + reg ibuf_unsign; // @[Reg.scala 27:20] + reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire _T_4441 = buf_write[3] & _T_2590; // @[lsu_bus_buffer.scala 533:64] + wire _T_4436 = buf_write[2] & _T_2583; // @[lsu_bus_buffer.scala 533:64] + wire [1:0] _T_4444 = _T_4441 + _T_4436; // @[lsu_bus_buffer.scala 533:142] + wire _T_4431 = buf_write[1] & _T_2576; // @[lsu_bus_buffer.scala 533:64] + wire [1:0] _GEN_376 = {{1'd0}, _T_4431}; // @[lsu_bus_buffer.scala 533:142] + wire [2:0] _T_4445 = _T_4444 + _GEN_376; // @[lsu_bus_buffer.scala 533:142] + wire _T_4426 = buf_write[0] & _T_2569; // @[lsu_bus_buffer.scala 533:64] + wire [2:0] _GEN_377 = {{2'd0}, _T_4426}; // @[lsu_bus_buffer.scala 533:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4445 + _GEN_377; // @[lsu_bus_buffer.scala 533:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 267:43] + wire [1:0] _T_4459 = _T_2590 + _T_2583; // @[lsu_bus_buffer.scala 534:126] + wire [1:0] _GEN_378 = {{1'd0}, _T_2576}; // @[lsu_bus_buffer.scala 534:126] + wire [2:0] _T_4460 = _T_4459 + _GEN_378; // @[lsu_bus_buffer.scala 534:126] + wire [2:0] _GEN_379 = {{2'd0}, _T_2569}; // @[lsu_bus_buffer.scala 534:126] + wire [3:0] buf_numvld_cmd_any = _T_4460 + _GEN_379; // @[lsu_bus_buffer.scala 534:126] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 267:72] + wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 267:51] + reg _T_1791; // @[Reg.scala 27:20] + wire [2:0] obuf_wr_timer = {{2'd0}, _T_1791}; // @[lsu_bus_buffer.scala 365:17] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 267:97] + wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 267:80] + wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 267:114] + wire _T_1918 = |buf_age_3; // @[lsu_bus_buffer.scala 383:58] + wire _T_1919 = ~_T_1918; // @[lsu_bus_buffer.scala 383:45] + wire _T_1921 = _T_1919 & _T_2590; // @[lsu_bus_buffer.scala 383:63] + wire _T_1912 = |buf_age_2; // @[lsu_bus_buffer.scala 383:58] + wire _T_1913 = ~_T_1912; // @[lsu_bus_buffer.scala 383:45] + wire _T_1915 = _T_1913 & _T_2583; // @[lsu_bus_buffer.scala 383:63] + wire _T_1906 = |buf_age_1; // @[lsu_bus_buffer.scala 383:58] + wire _T_1907 = ~_T_1906; // @[lsu_bus_buffer.scala 383:45] + wire _T_1909 = _T_1907 & _T_2576; // @[lsu_bus_buffer.scala 383:63] + wire _T_1900 = |buf_age_0; // @[lsu_bus_buffer.scala 383:58] + wire _T_1901 = ~_T_1900; // @[lsu_bus_buffer.scala 383:45] + wire _T_1903 = _T_1901 & _T_2569; // @[lsu_bus_buffer.scala 383:63] + wire [3:0] CmdPtr0Dec = {_T_1921,_T_1915,_T_1909,_T_1903}; // @[Cat.scala 29:58] + wire [7:0] _T_1993 = {4'h0,_T_1921,_T_1915,_T_1909,_T_1903}; // @[Cat.scala 29:58] + wire _T_1996 = _T_1993[4] | _T_1993[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_1998 = _T_1996 | _T_1993[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2000 = _T_1998 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2003 = _T_1993[2] | _T_1993[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2005 = _T_2003 | _T_1993[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2007 = _T_2005 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2010 = _T_1993[1] | _T_1993[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2012 = _T_2010 | _T_1993[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2014 = _T_2012 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2016 = {_T_2000,_T_2007,_T_2014}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr0 = _T_2016[1:0]; // @[lsu_bus_buffer.scala 396:11] + wire _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 268:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 268:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 268:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 268:114] + reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] + reg buf_nomerge_1; // @[Reg.scala 27:20] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] + reg buf_nomerge_2; // @[Reg.scala 27:20] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] + reg buf_nomerge_3; // @[Reg.scala 27:20] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 268:31] + wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 268:29] + reg _T_4325; // @[Reg.scala 27:20] + reg _T_4322; // @[Reg.scala 27:20] + reg _T_4319; // @[Reg.scala 27:20] + reg _T_4316; // @[Reg.scala 27:20] + wire [3:0] buf_sideeffect = {_T_4325,_T_4322,_T_4319,_T_4316}; // @[Cat.scala 29:58] + wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72] + wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72] + wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72] + wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72] + wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] + wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] + wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] + wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 269:5] + wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 268:140] + wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 271:58] + wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 271:72] + wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] + wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] + wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 271:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 271:101] + wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 269:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 269:117] + wire _T_4477 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4481 = _T_4477 | _T_2590; // @[lsu_bus_buffer.scala 535:74] + wire _T_4472 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4476 = _T_4472 | _T_2583; // @[lsu_bus_buffer.scala 535:74] + wire [1:0] _T_4482 = _T_4481 + _T_4476; // @[lsu_bus_buffer.scala 535:154] + wire _T_4467 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4471 = _T_4467 | _T_2576; // @[lsu_bus_buffer.scala 535:74] + wire [1:0] _GEN_380 = {{1'd0}, _T_4471}; // @[lsu_bus_buffer.scala 535:154] + wire [2:0] _T_4483 = _T_4482 + _GEN_380; // @[lsu_bus_buffer.scala 535:154] + wire _T_4462 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4466 = _T_4462 | _T_2569; // @[lsu_bus_buffer.scala 535:74] + wire [2:0] _GEN_381 = {{2'd0}, _T_4466}; // @[lsu_bus_buffer.scala 535:154] + wire [3:0] buf_numvld_pend_any = _T_4483 + _GEN_381; // @[lsu_bus_buffer.scala 535:154] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 273:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 273:31] + wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 273:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 273:89] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 273:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 289:32] + wire _T_4751 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4753 = _T_4751 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4754 = _T_4753 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4755 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4757 = _T_4755 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4758 = _T_4757 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4767 = _T_4754 | _T_4758; // @[lsu_bus_buffer.scala 563:153] + wire _T_4759 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4761 = _T_4759 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4762 = _T_4761 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4768 = _T_4767 | _T_4762; // @[lsu_bus_buffer.scala 563:153] + wire _T_4763 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4765 = _T_4763 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4766 = _T_4765 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire bus_sideeffect_pend = _T_4768 | _T_4766; // @[lsu_bus_buffer.scala 563:153] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 289:74] + wire _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 289:52] + wire _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 289:50] + wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] + wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] + wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] + wire _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 290:36] + wire found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 388:31] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 290:47] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 291:141] + wire _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 291:105] + wire _T_1148 = _T_1108 & _T_1147; // @[lsu_bus_buffer.scala 291:103] + reg buf_dual_3; // @[Reg.scala 27:20] + reg buf_dual_2; // @[Reg.scala 27:20] + reg buf_dual_1; // @[Reg.scala 27:20] + reg buf_dual_0; // @[Reg.scala 27:20] + wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58] + wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72] + wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72] + wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72] + wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72] + wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72] + reg buf_samedw_3; // @[Reg.scala 27:20] + reg buf_samedw_2; // @[Reg.scala 27:20] + reg buf_samedw_1; // @[Reg.scala 27:20] + reg buf_samedw_0; // @[Reg.scala 27:20] + wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58] + wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72] + wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72] + wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72] + wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72] + wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] + wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] + wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] + wire _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 292:77] + wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] + wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] + wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] + wire _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 292:150] + wire _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 292:148] + wire _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 292:8] + wire [3:0] _T_1959 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 384:62] + wire [3:0] _T_1960 = buf_age_3 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1961 = |_T_1960; // @[lsu_bus_buffer.scala 384:76] + wire _T_1962 = ~_T_1961; // @[lsu_bus_buffer.scala 384:45] + wire _T_1964 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1965 = _T_1962 & _T_1964; // @[lsu_bus_buffer.scala 384:81] + wire _T_1967 = _T_1965 & _T_2590; // @[lsu_bus_buffer.scala 384:98] + wire [3:0] _T_1949 = buf_age_2 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1950 = |_T_1949; // @[lsu_bus_buffer.scala 384:76] + wire _T_1951 = ~_T_1950; // @[lsu_bus_buffer.scala 384:45] + wire _T_1953 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1954 = _T_1951 & _T_1953; // @[lsu_bus_buffer.scala 384:81] + wire _T_1956 = _T_1954 & _T_2583; // @[lsu_bus_buffer.scala 384:98] + wire [3:0] _T_1938 = buf_age_1 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1939 = |_T_1938; // @[lsu_bus_buffer.scala 384:76] + wire _T_1940 = ~_T_1939; // @[lsu_bus_buffer.scala 384:45] + wire _T_1942 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1943 = _T_1940 & _T_1942; // @[lsu_bus_buffer.scala 384:81] + wire _T_1945 = _T_1943 & _T_2576; // @[lsu_bus_buffer.scala 384:98] + wire [3:0] _T_1927 = buf_age_0 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1928 = |_T_1927; // @[lsu_bus_buffer.scala 384:76] + wire _T_1929 = ~_T_1928; // @[lsu_bus_buffer.scala 384:45] + wire _T_1931 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1932 = _T_1929 & _T_1931; // @[lsu_bus_buffer.scala 384:81] + wire _T_1934 = _T_1932 & _T_2569; // @[lsu_bus_buffer.scala 384:98] + wire [3:0] CmdPtr1Dec = {_T_1967,_T_1956,_T_1945,_T_1934}; // @[Cat.scala 29:58] + wire found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 389:31] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 292:181] + wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] + wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] + wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] + wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72] + wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72] + wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] + wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] + wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] + wire _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 292:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 292:269] + wire _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 291:164] + wire _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 289:98] + wire _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 293:48] + wire _T_1232 = io_lsu_axi_ar_ready | _T_1231; // @[lsu_bus_buffer.scala 293:46] + reg obuf_nosend; // @[Reg.scala 27:20] + wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 293:60] + wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 293:29] + wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 293:77] + wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 293:75] + reg [31:0] obuf_addr; // @[Reg.scala 27:20] + wire _T_4787 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4788 = obuf_valid & _T_4787; // @[lsu_bus_buffer.scala 565:19] + wire _T_4818 = _T_4755 & _T_4788; // @[Mux.scala 27:72] + wire _T_4798 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4799 = obuf_valid & _T_4798; // @[lsu_bus_buffer.scala 565:19] + wire _T_4819 = _T_4759 & _T_4799; // @[Mux.scala 27:72] + wire _T_4822 = _T_4818 | _T_4819; // @[Mux.scala 27:72] + wire _T_4809 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4810 = obuf_valid & _T_4809; // @[lsu_bus_buffer.scala 565:19] + wire _T_4820 = _T_4763 & _T_4810; // @[Mux.scala 27:72] + wire bus_addr_match_pending = _T_4822 | _T_4820; // @[Mux.scala 27:72] + wire _T_1237 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 293:94] + wire _T_1238 = _T_1236 & _T_1237; // @[lsu_bus_buffer.scala 293:92] + wire obuf_wr_en = _T_1238 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 293:118] + wire _T_1240 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 296:47] + wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 568:40] + wire bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 569:40] + wire _T_4834 = bus_wcmd_sent & bus_wdata_sent; // @[lsu_bus_buffer.scala 570:52] + wire _T_4835 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 570:112] + wire bus_cmd_sent = _T_4834 | _T_4835; // @[lsu_bus_buffer.scala 570:89] + wire _T_1241 = bus_cmd_sent | _T_1240; // @[lsu_bus_buffer.scala 296:33] + wire _T_1242 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 296:65] + wire _T_1243 = _T_1241 & _T_1242; // @[lsu_bus_buffer.scala 296:63] + wire _T_1244 = _T_1243 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 296:77] + wire obuf_rst = _T_1244 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 296:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 297:26] + wire [31:0] _T_1281 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1282 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1283 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1284 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1285 = _T_1281 | _T_1282; // @[Mux.scala 27:72] + wire [31:0] _T_1286 = _T_1285 | _T_1283; // @[Mux.scala 27:72] + wire [31:0] _T_1287 = _T_1286 | _T_1284; // @[Mux.scala 27:72] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1287; // @[lsu_bus_buffer.scala 299:25] + reg [1:0] buf_sz_0; // @[Reg.scala 27:20] + wire [1:0] _T_1294 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire [1:0] _T_1295 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_2; // @[Reg.scala 27:20] + wire [1:0] _T_1296 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_3; // @[Reg.scala 27:20] + wire [1:0] _T_1297 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1298 = _T_1294 | _T_1295; // @[Mux.scala 27:72] + wire [1:0] _T_1299 = _T_1298 | _T_1296; // @[Mux.scala 27:72] + wire [1:0] _T_1300 = _T_1299 | _T_1297; // @[Mux.scala 27:72] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1300; // @[lsu_bus_buffer.scala 302:23] + wire [7:0] _T_2018 = {4'h0,_T_1967,_T_1956,_T_1945,_T_1934}; // @[Cat.scala 29:58] + wire _T_2021 = _T_2018[4] | _T_2018[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_2023 = _T_2021 | _T_2018[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2025 = _T_2023 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2028 = _T_2018[2] | _T_2018[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2030 = _T_2028 | _T_2018[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2032 = _T_2030 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2035 = _T_2018[1] | _T_2018[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2037 = _T_2035 | _T_2018[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2039 = _T_2037 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2041 = {_T_2025,_T_2032,_T_2039}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr1 = _T_2041[1:0]; // @[lsu_bus_buffer.scala 398:11] + wire _T_1302 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 310:39] + wire _T_1303 = ~_T_1302; // @[lsu_bus_buffer.scala 310:26] + wire obuf_data_done_in = _T_1303 & bus_wdata_sent; // @[lsu_bus_buffer.scala 313:52] + wire _T_1309 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 314:72] + wire _T_1312 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 314:98] + wire _T_1313 = obuf_sz_in[0] & _T_1312; // @[lsu_bus_buffer.scala 314:96] + wire _T_1314 = _T_1309 | _T_1313; // @[lsu_bus_buffer.scala 314:79] + wire _T_1317 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 314:153] + wire _T_1318 = ~_T_1317; // @[lsu_bus_buffer.scala 314:134] + wire _T_1319 = obuf_sz_in[1] & _T_1318; // @[lsu_bus_buffer.scala 314:132] + wire _T_1320 = _T_1314 | _T_1319; // @[lsu_bus_buffer.scala 314:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1320; // @[lsu_bus_buffer.scala 314:28] + wire _T_1337 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 328:40] + wire _T_1338 = _T_1337 & obuf_aligned_in; // @[lsu_bus_buffer.scala 328:60] + wire _T_1343 = ~obuf_write_in; // @[lsu_bus_buffer.scala 328:113] + wire _T_1344 = _T_1338 & _T_1343; // @[lsu_bus_buffer.scala 328:111] + wire _T_1345 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 328:130] + wire _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 328:128] + wire _T_1347 = ~obuf_nosend; // @[lsu_bus_buffer.scala 329:20] + wire _T_1348 = obuf_valid & _T_1347; // @[lsu_bus_buffer.scala 329:18] + reg obuf_rdrsp_pend; // @[Reg.scala 27:20] + wire bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 571:38] + wire _T_1349 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 329:90] + wire _T_1350 = bus_rsp_read & _T_1349; // @[lsu_bus_buffer.scala 329:70] + wire _T_1351 = ~_T_1350; // @[lsu_bus_buffer.scala 329:55] + wire _T_1352 = obuf_rdrsp_pend & _T_1351; // @[lsu_bus_buffer.scala 329:53] + wire _T_1353 = _T_1348 | _T_1352; // @[lsu_bus_buffer.scala 329:34] + wire obuf_nosend_in = _T_1346 & _T_1353; // @[lsu_bus_buffer.scala 328:177] + wire _T_1321 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 322:45] + wire _T_1322 = obuf_wr_en & _T_1321; // @[lsu_bus_buffer.scala 322:43] + wire _T_1323 = ~_T_1322; // @[lsu_bus_buffer.scala 322:30] + wire _T_1324 = _T_1323 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 322:62] + wire _T_1328 = _T_1324 & _T_1351; // @[lsu_bus_buffer.scala 322:80] + wire _T_1331 = _T_1328 | bus_cmd_sent; // @[lsu_bus_buffer.scala 322:139] + wire obuf_rdrsp_pend_in = _T_1331 & _T_2594; // @[lsu_bus_buffer.scala 322:171] + wire obuf_rdrsp_pend_en = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 323:47] + wire [7:0] _T_1401 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1402 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1403 = io_end_addr_r[2] ? _T_1401 : _T_1402; // @[lsu_bus_buffer.scala 332:46] + wire _T_1404 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 62:123] + wire _T_1405 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 62:123] + wire _T_1406 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 62:123] + wire _T_1407 = CmdPtr1 == 2'h3; // @[lsu_bus_buffer.scala 62:123] + wire [31:0] _T_1408 = _T_1404 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1409 = _T_1405 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1410 = _T_1406 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1411 = _T_1407 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1412 = _T_1408 | _T_1409; // @[Mux.scala 27:72] + wire [31:0] _T_1413 = _T_1412 | _T_1410; // @[Mux.scala 27:72] + wire [31:0] _T_1414 = _T_1413 | _T_1411; // @[Mux.scala 27:72] + wire [3:0] _T_1422 = _T_1404 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1423 = _T_1405 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1424 = _T_1406 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1425 = _T_1407 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1426 = _T_1422 | _T_1423; // @[Mux.scala 27:72] + wire [3:0] _T_1427 = _T_1426 | _T_1424; // @[Mux.scala 27:72] + wire [3:0] _T_1428 = _T_1427 | _T_1425; // @[Mux.scala 27:72] + wire [7:0] _T_1430 = {_T_1428,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1443 = {4'h0,_T_1428}; // @[Cat.scala 29:58] + wire [7:0] _T_1444 = _T_1414[2] ? _T_1430 : _T_1443; // @[lsu_bus_buffer.scala 333:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1403 : _T_1444; // @[lsu_bus_buffer.scala 332:28] + wire [63:0] _T_1446 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1447 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1448 = io_lsu_addr_r[2] ? _T_1446 : _T_1447; // @[lsu_bus_buffer.scala 335:44] + wire [31:0] _T_1467 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1468 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1469 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1470 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1471 = _T_1467 | _T_1468; // @[Mux.scala 27:72] + wire [31:0] _T_1472 = _T_1471 | _T_1469; // @[Mux.scala 27:72] + wire [31:0] _T_1473 = _T_1472 | _T_1470; // @[Mux.scala 27:72] + wire [63:0] _T_1475 = {_T_1473,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1488 = {32'h0,_T_1473}; // @[Cat.scala 29:58] + wire [63:0] _T_1489 = _T_1287[2] ? _T_1475 : _T_1488; // @[lsu_bus_buffer.scala 336:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1448 : _T_1489; // @[lsu_bus_buffer.scala 335:26] + wire [63:0] _T_1491 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1492 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1493 = io_end_addr_r[2] ? _T_1491 : _T_1492; // @[lsu_bus_buffer.scala 337:44] + wire [31:0] _T_1512 = _T_1404 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1513 = _T_1405 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1514 = _T_1406 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1515 = _T_1407 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1516 = _T_1512 | _T_1513; // @[Mux.scala 27:72] + wire [31:0] _T_1517 = _T_1516 | _T_1514; // @[Mux.scala 27:72] + wire [31:0] _T_1518 = _T_1517 | _T_1515; // @[Mux.scala 27:72] + wire [63:0] _T_1520 = {_T_1518,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1533 = {32'h0,_T_1518}; // @[Cat.scala 29:58] + wire [63:0] _T_1534 = _T_1414[2] ? _T_1520 : _T_1533; // @[lsu_bus_buffer.scala 338:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1493 : _T_1534; // @[lsu_bus_buffer.scala 337:26] + wire _T_1619 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 344:30] + wire _T_1620 = _T_1619 & found_cmdptr0; // @[lsu_bus_buffer.scala 344:43] + wire _T_1621 = _T_1620 & found_cmdptr1; // @[lsu_bus_buffer.scala 344:59] + wire _T_1635 = _T_1621 & _T_1107; // @[lsu_bus_buffer.scala 344:75] + wire [2:0] _T_1640 = _T_1404 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1641 = _T_1405 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1644 = _T_1640 | _T_1641; // @[Mux.scala 27:72] + wire [2:0] _T_1642 = _T_1406 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1645 = _T_1644 | _T_1642; // @[Mux.scala 27:72] + wire [2:0] _T_1643 = _T_1407 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1646 = _T_1645 | _T_1643; // @[Mux.scala 27:72] + wire _T_1648 = _T_1646 == 3'h2; // @[lsu_bus_buffer.scala 344:150] + wire _T_1649 = _T_1635 & _T_1648; // @[lsu_bus_buffer.scala 344:118] + wire _T_1688 = _T_1649 & _T_1053; // @[lsu_bus_buffer.scala 345:85] + wire _T_1725 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 346:36] + reg buf_dualhi_3; // @[Reg.scala 27:20] + reg buf_dualhi_2; // @[Reg.scala 27:20] + reg buf_dualhi_1; // @[Reg.scala 27:20] + reg buf_dualhi_0; // @[Reg.scala 27:20] + wire [3:0] _T_1728 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58] + wire _T_1737 = _T_1023 & _T_1728[0]; // @[Mux.scala 27:72] + wire _T_1738 = _T_1024 & _T_1728[1]; // @[Mux.scala 27:72] + wire _T_1741 = _T_1737 | _T_1738; // @[Mux.scala 27:72] + wire _T_1739 = _T_1025 & _T_1728[2]; // @[Mux.scala 27:72] + wire _T_1742 = _T_1741 | _T_1739; // @[Mux.scala 27:72] + wire _T_1740 = _T_1026 & _T_1728[3]; // @[Mux.scala 27:72] + wire _T_1743 = _T_1742 | _T_1740; // @[Mux.scala 27:72] + wire _T_1745 = ~_T_1743; // @[lsu_bus_buffer.scala 346:107] + wire _T_1746 = _T_1725 & _T_1745; // @[lsu_bus_buffer.scala 346:105] + wire _T_1766 = _T_1746 & _T_1185; // @[lsu_bus_buffer.scala 346:177] + wire _T_1767 = _T_1688 & _T_1766; // @[lsu_bus_buffer.scala 345:122] + wire _T_1768 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 347:19] + wire _T_1769 = _T_1768 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 347:35] + wire obuf_merge_en = _T_1767 | _T_1769; // @[lsu_bus_buffer.scala 346:250] + wire _T_1537 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1541 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1545 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1549 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1553 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1557 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1561 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1565 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 339:80] + wire [7:0] _T_1577 = _T_1537 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1582 = _T_1541 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1587 = _T_1545 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1592 = _T_1549 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1597 = _T_1553 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1602 = _T_1557 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1607 = _T_1561 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1612 = _T_1565 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 340:44] + wire [63:0] obuf_data_in = {_T_1612,_T_1607,_T_1602,_T_1597,_T_1592,_T_1587,_T_1582,_T_1577}; // @[Cat.scala 29:58] + wire _T_1771 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 349:58] + wire _T_1772 = ~obuf_rst; // @[lsu_bus_buffer.scala 349:93] + reg [63:0] obuf_data; // @[Reg.scala 27:20] + wire _T_1792 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1793 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 370:30] + wire _T_1794 = ibuf_valid & _T_1793; // @[lsu_bus_buffer.scala 370:19] + wire _T_1795 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 371:18] + wire _T_1796 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 371:57] + wire _T_1797 = io_ldst_dual_r & _T_1796; // @[lsu_bus_buffer.scala 371:45] + wire _T_1798 = _T_1795 | _T_1797; // @[lsu_bus_buffer.scala 371:27] + wire _T_1799 = io_lsu_busreq_r & _T_1798; // @[lsu_bus_buffer.scala 370:58] + wire _T_1800 = _T_1794 | _T_1799; // @[lsu_bus_buffer.scala 370:39] + wire _T_1801 = ~_T_1800; // @[lsu_bus_buffer.scala 370:5] + wire _T_1802 = _T_1792 & _T_1801; // @[lsu_bus_buffer.scala 369:76] + wire _T_1803 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1804 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 370:30] + wire _T_1805 = ibuf_valid & _T_1804; // @[lsu_bus_buffer.scala 370:19] + wire _T_1806 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 371:18] + wire _T_1807 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 371:57] + wire _T_1808 = io_ldst_dual_r & _T_1807; // @[lsu_bus_buffer.scala 371:45] + wire _T_1809 = _T_1806 | _T_1808; // @[lsu_bus_buffer.scala 371:27] + wire _T_1810 = io_lsu_busreq_r & _T_1809; // @[lsu_bus_buffer.scala 370:58] + wire _T_1811 = _T_1805 | _T_1810; // @[lsu_bus_buffer.scala 370:39] + wire _T_1812 = ~_T_1811; // @[lsu_bus_buffer.scala 370:5] + wire _T_1813 = _T_1803 & _T_1812; // @[lsu_bus_buffer.scala 369:76] + wire _T_1814 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1815 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 370:30] + wire _T_1816 = ibuf_valid & _T_1815; // @[lsu_bus_buffer.scala 370:19] + wire _T_1817 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 371:18] + wire _T_1818 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 371:57] + wire _T_1819 = io_ldst_dual_r & _T_1818; // @[lsu_bus_buffer.scala 371:45] + wire _T_1820 = _T_1817 | _T_1819; // @[lsu_bus_buffer.scala 371:27] + wire _T_1821 = io_lsu_busreq_r & _T_1820; // @[lsu_bus_buffer.scala 370:58] + wire _T_1822 = _T_1816 | _T_1821; // @[lsu_bus_buffer.scala 370:39] + wire _T_1823 = ~_T_1822; // @[lsu_bus_buffer.scala 370:5] + wire _T_1824 = _T_1814 & _T_1823; // @[lsu_bus_buffer.scala 369:76] + wire _T_1825 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1826 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 370:30] + wire _T_1828 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 371:18] + wire _T_1829 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 371:57] + wire [1:0] _T_1837 = _T_1824 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] + wire [1:0] _T_1838 = _T_1813 ? 2'h1 : _T_1837; // @[Mux.scala 98:16] + wire [1:0] WrPtr0_m = _T_1802 ? 2'h0 : _T_1838; // @[Mux.scala 98:16] + wire _T_1843 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 376:33] + wire _T_1844 = io_lsu_busreq_m & _T_1843; // @[lsu_bus_buffer.scala 376:22] + wire _T_1845 = _T_1794 | _T_1844; // @[lsu_bus_buffer.scala 375:112] + wire _T_1851 = _T_1845 | _T_1799; // @[lsu_bus_buffer.scala 376:42] + wire _T_1852 = ~_T_1851; // @[lsu_bus_buffer.scala 375:78] + wire _T_1853 = _T_1792 & _T_1852; // @[lsu_bus_buffer.scala 375:76] + wire _T_1857 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 376:33] + wire _T_1858 = io_lsu_busreq_m & _T_1857; // @[lsu_bus_buffer.scala 376:22] + wire _T_1859 = _T_1805 | _T_1858; // @[lsu_bus_buffer.scala 375:112] + wire _T_1865 = _T_1859 | _T_1810; // @[lsu_bus_buffer.scala 376:42] + wire _T_1866 = ~_T_1865; // @[lsu_bus_buffer.scala 375:78] + wire _T_1867 = _T_1803 & _T_1866; // @[lsu_bus_buffer.scala 375:76] + wire _T_1871 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 376:33] + wire _T_1872 = io_lsu_busreq_m & _T_1871; // @[lsu_bus_buffer.scala 376:22] + wire _T_1873 = _T_1816 | _T_1872; // @[lsu_bus_buffer.scala 375:112] + wire _T_1879 = _T_1873 | _T_1821; // @[lsu_bus_buffer.scala 376:42] + wire _T_1880 = ~_T_1879; // @[lsu_bus_buffer.scala 375:78] + wire _T_1881 = _T_1814 & _T_1880; // @[lsu_bus_buffer.scala 375:76] + reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 514:63] + wire _T_2717 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2718 = buf_rspageQ_0[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2714 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2715 = buf_rspageQ_0[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2711 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2712 = buf_rspageQ_0[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2708 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2709 = buf_rspageQ_0[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_0 = {_T_2718,_T_2715,_T_2712,_T_2709}; // @[Cat.scala 29:58] + wire _T_1972 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 387:65] + wire _T_1973 = ~_T_1972; // @[lsu_bus_buffer.scala 387:44] + wire _T_1975 = _T_1973 & _T_2708; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 514:63] + wire _T_2733 = buf_rspageQ_1[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2730 = buf_rspageQ_1[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2727 = buf_rspageQ_1[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2724 = buf_rspageQ_1[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_1 = {_T_2733,_T_2730,_T_2727,_T_2724}; // @[Cat.scala 29:58] + wire _T_1976 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 387:65] + wire _T_1977 = ~_T_1976; // @[lsu_bus_buffer.scala 387:44] + wire _T_1979 = _T_1977 & _T_2711; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 514:63] + wire _T_2748 = buf_rspageQ_2[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2745 = buf_rspageQ_2[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2742 = buf_rspageQ_2[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2739 = buf_rspageQ_2[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_2 = {_T_2748,_T_2745,_T_2742,_T_2739}; // @[Cat.scala 29:58] + wire _T_1980 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 387:65] + wire _T_1981 = ~_T_1980; // @[lsu_bus_buffer.scala 387:44] + wire _T_1983 = _T_1981 & _T_2714; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 514:63] + wire _T_2763 = buf_rspageQ_3[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2760 = buf_rspageQ_3[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2757 = buf_rspageQ_3[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2754 = buf_rspageQ_3[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_3 = {_T_2763,_T_2760,_T_2757,_T_2754}; // @[Cat.scala 29:58] + wire _T_1984 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 387:65] + wire _T_1985 = ~_T_1984; // @[lsu_bus_buffer.scala 387:44] + wire _T_1987 = _T_1985 & _T_2717; // @[lsu_bus_buffer.scala 387:70] + wire [7:0] _T_2043 = {4'h0,_T_1987,_T_1983,_T_1979,_T_1975}; // @[Cat.scala 29:58] + wire _T_2046 = _T_2043[4] | _T_2043[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_2048 = _T_2046 | _T_2043[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2050 = _T_2048 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2053 = _T_2043[2] | _T_2043[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2055 = _T_2053 | _T_2043[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2057 = _T_2055 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2060 = _T_2043[1] | _T_2043[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2062 = _T_2060 | _T_2043[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2064 = _T_2062 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2066 = {_T_2050,_T_2057,_T_2064}; // @[Cat.scala 29:58] + wire _T_3535 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 445:77] + wire _T_3536 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 445:97] + wire _T_3537 = _T_3535 & _T_3536; // @[lsu_bus_buffer.scala 445:95] + wire _T_3538 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 445:112] + wire _T_3540 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 445:144] + wire _T_3541 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3542 = _T_3540 & _T_3541; // @[lsu_bus_buffer.scala 445:161] + wire _T_3543 = _T_3539 | _T_3542; // @[lsu_bus_buffer.scala 445:132] + wire _T_3544 = _T_853 & _T_3543; // @[lsu_bus_buffer.scala 445:63] + wire _T_3545 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3546 = ibuf_drain_vld & _T_3545; // @[lsu_bus_buffer.scala 445:201] + wire _T_3547 = _T_3544 | _T_3546; // @[lsu_bus_buffer.scala 445:183] + wire bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 572:39] + wire _T_3636 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 475:73] + wire _T_3637 = bus_rsp_write & _T_3636; // @[lsu_bus_buffer.scala 475:52] + reg _T_4302; // @[Reg.scala 27:20] + reg _T_4300; // @[Reg.scala 27:20] + reg _T_4298; // @[Reg.scala 27:20] + reg _T_4296; // @[Reg.scala 27:20] + wire [3:0] buf_ldfwd = {_T_4302,_T_4300,_T_4298,_T_4296}; // @[Cat.scala 29:58] + wire _T_3641 = buf_ldfwd[0] & _T_1349; // @[lsu_bus_buffer.scala 477:27] + wire _T_3642 = _T_1349 | _T_3641; // @[lsu_bus_buffer.scala 476:77] + wire _T_3643 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 478:26] + wire _T_3645 = ~buf_write[0]; // @[lsu_bus_buffer.scala 478:44] + wire _T_3646 = _T_3643 & _T_3645; // @[lsu_bus_buffer.scala 478:42] + wire _T_3647 = _T_3646 & buf_samedw_0; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_382 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 478:94] + wire _T_3648 = io_lsu_axi_r_bits_id == _GEN_382; // @[lsu_bus_buffer.scala 478:94] + wire _T_3649 = _T_3647 & _T_3648; // @[lsu_bus_buffer.scala 478:74] + wire _T_3650 = _T_3642 | _T_3649; // @[lsu_bus_buffer.scala 477:71] + wire _T_3651 = bus_rsp_read & _T_3650; // @[lsu_bus_buffer.scala 476:25] + wire _T_3652 = _T_3637 | _T_3651; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_52 = _T_3592 & _T_3652; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_3558 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_3554 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire [3:0] _T_3687 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 492:21] + wire _T_3690 = _T_3687[0] & _T_1349; // @[lsu_bus_buffer.scala 492:38] + wire _T_3691 = _T_3648 | _T_3690; // @[lsu_bus_buffer.scala 491:95] + wire _T_3692 = bus_rsp_read & _T_3691; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_46 = _T_3677 & _T_3692; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_3592 ? buf_resp_state_bus_en_0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_3558 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_77 = _T_3554 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire buf_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58] + wire _T_3571 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3572 = _T_3571 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire [1:0] RspPtr = _T_2066[1:0]; // @[lsu_bus_buffer.scala 399:10] + wire _T_3698 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 499:37] + wire _T_3699 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_3700 = buf_dual_0 & _T_3699; // @[lsu_bus_buffer.scala 499:80] + wire _T_3701 = _T_3698 | _T_3700; // @[lsu_bus_buffer.scala 499:65] + wire _T_3702 = _T_3701 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_41 = _T_3695 ? _T_3702 : _T_3703; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_3677 ? _T_3572 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_3592 ? _T_3572 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_3558 ? _T_3572 : _GEN_54; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_3554 ? obuf_rdrsp_pend_en : _GEN_64; // @[Conditional.scala 39:67] + wire buf_state_en_0 = _T_3531 ? _T_3547 : _GEN_74; // @[Conditional.scala 40:58] + wire _T_2068 = _T_1792 & buf_state_en_0; // @[lsu_bus_buffer.scala 411:94] + wire _T_2074 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 413:23] + wire _T_2076 = _T_2074 & _T_3535; // @[lsu_bus_buffer.scala 413:41] + wire _T_2078 = _T_2076 & _T_1795; // @[lsu_bus_buffer.scala 413:71] + wire _T_2080 = _T_2078 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2081 = _T_4466 | _T_2080; // @[lsu_bus_buffer.scala 412:86] + wire _T_2082 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 414:17] + wire _T_2083 = _T_2082 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 414:35] + wire _T_2085 = _T_2083 & _T_1796; // @[lsu_bus_buffer.scala 414:52] + wire _T_2087 = _T_2085 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2088 = _T_2081 | _T_2087; // @[lsu_bus_buffer.scala 413:114] + wire _T_2089 = _T_2068 & _T_2088; // @[lsu_bus_buffer.scala 411:113] + wire _T_2091 = _T_2089 | buf_age_0[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2105 = _T_2078 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2106 = _T_4471 | _T_2105; // @[lsu_bus_buffer.scala 412:86] + wire _T_2112 = _T_2085 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2113 = _T_2106 | _T_2112; // @[lsu_bus_buffer.scala 413:114] + wire _T_2114 = _T_2068 & _T_2113; // @[lsu_bus_buffer.scala 411:113] + wire _T_2116 = _T_2114 | buf_age_0[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2130 = _T_2078 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2131 = _T_4476 | _T_2130; // @[lsu_bus_buffer.scala 412:86] + wire _T_2137 = _T_2085 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2138 = _T_2131 | _T_2137; // @[lsu_bus_buffer.scala 413:114] + wire _T_2139 = _T_2068 & _T_2138; // @[lsu_bus_buffer.scala 411:113] + wire _T_2141 = _T_2139 | buf_age_0[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2155 = _T_2078 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2156 = _T_4481 | _T_2155; // @[lsu_bus_buffer.scala 412:86] + wire _T_2162 = _T_2085 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2163 = _T_2156 | _T_2162; // @[lsu_bus_buffer.scala 413:114] + wire _T_2164 = _T_2068 & _T_2163; // @[lsu_bus_buffer.scala 411:113] + wire _T_2166 = _T_2164 | buf_age_0[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2168 = {_T_2166,_T_2141,_T_2116}; // @[Cat.scala 29:58] + wire _T_3729 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3730 = _T_3537 & _T_3729; // @[lsu_bus_buffer.scala 445:112] + wire _T_3732 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3733 = _T_3540 & _T_3732; // @[lsu_bus_buffer.scala 445:161] + wire _T_3734 = _T_3730 | _T_3733; // @[lsu_bus_buffer.scala 445:132] + wire _T_3735 = _T_853 & _T_3734; // @[lsu_bus_buffer.scala 445:63] + wire _T_3736 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3737 = ibuf_drain_vld & _T_3736; // @[lsu_bus_buffer.scala 445:201] + wire _T_3738 = _T_3735 | _T_3737; // @[lsu_bus_buffer.scala 445:183] + wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 475:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 475:52] + wire _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 476:46] + wire _T_3832 = buf_ldfwd[1] & _T_1349; // @[lsu_bus_buffer.scala 477:27] + wire _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 476:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 478:26] + wire _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 478:44] + wire _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 478:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] + wire [2:0] _GEN_384 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 478:94] + wire _T_3839 = io_lsu_axi_r_bits_id == _GEN_384; // @[lsu_bus_buffer.scala 478:94] + wire _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 478:74] + wire _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 477:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 476:25] + wire _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_128 = _T_3783 & _T_3843; // @[Conditional.scala 39:67] + wire _GEN_148 = _T_3749 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] + wire _GEN_160 = _T_3745 ? 1'h0 : _GEN_148; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_160; // @[Conditional.scala 40:58] + wire [3:0] _T_3878 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 492:21] + wire _T_3881 = _T_3878[0] & _T_1349; // @[lsu_bus_buffer.scala 492:38] + wire _T_3882 = _T_3839 | _T_3881; // @[lsu_bus_buffer.scala 491:95] + wire _T_3883 = bus_rsp_read & _T_3882; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_122 = _T_3868 & _T_3883; // @[Conditional.scala 39:67] + wire _GEN_129 = _T_3783 ? buf_resp_state_bus_en_1 : _GEN_122; // @[Conditional.scala 39:67] + wire _GEN_139 = _T_3749 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] + wire _GEN_153 = _T_3745 ? 1'h0 : _GEN_139; // @[Conditional.scala 39:67] + wire buf_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_153; // @[Conditional.scala 40:58] + wire _T_3762 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3763 = _T_3762 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_3889 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 499:37] + wire _T_3890 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_3891 = buf_dual_1 & _T_3890; // @[lsu_bus_buffer.scala 499:80] + wire _T_3892 = _T_3889 | _T_3891; // @[lsu_bus_buffer.scala 499:65] + wire _T_3893 = _T_3892 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_117 = _T_3886 ? _T_3893 : _T_3894; // @[Conditional.scala 39:67] + wire _GEN_123 = _T_3868 ? _T_3763 : _GEN_117; // @[Conditional.scala 39:67] + wire _GEN_130 = _T_3783 ? _T_3763 : _GEN_123; // @[Conditional.scala 39:67] + wire _GEN_140 = _T_3749 ? _T_3763 : _GEN_130; // @[Conditional.scala 39:67] + wire _GEN_150 = _T_3745 ? obuf_rdrsp_pend_en : _GEN_140; // @[Conditional.scala 39:67] + wire buf_state_en_1 = _T_3722 ? _T_3738 : _GEN_150; // @[Conditional.scala 40:58] + wire _T_2170 = _T_1803 & buf_state_en_1; // @[lsu_bus_buffer.scala 411:94] + wire _T_2180 = _T_2076 & _T_1806; // @[lsu_bus_buffer.scala 413:71] + wire _T_2182 = _T_2180 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2183 = _T_4466 | _T_2182; // @[lsu_bus_buffer.scala 412:86] + wire _T_2187 = _T_2083 & _T_1807; // @[lsu_bus_buffer.scala 414:52] + wire _T_2189 = _T_2187 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2190 = _T_2183 | _T_2189; // @[lsu_bus_buffer.scala 413:114] + wire _T_2191 = _T_2170 & _T_2190; // @[lsu_bus_buffer.scala 411:113] + wire _T_2193 = _T_2191 | buf_age_1[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2207 = _T_2180 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2208 = _T_4471 | _T_2207; // @[lsu_bus_buffer.scala 412:86] + wire _T_2214 = _T_2187 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2215 = _T_2208 | _T_2214; // @[lsu_bus_buffer.scala 413:114] + wire _T_2216 = _T_2170 & _T_2215; // @[lsu_bus_buffer.scala 411:113] + wire _T_2218 = _T_2216 | buf_age_1[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2232 = _T_2180 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2233 = _T_4476 | _T_2232; // @[lsu_bus_buffer.scala 412:86] + wire _T_2239 = _T_2187 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2240 = _T_2233 | _T_2239; // @[lsu_bus_buffer.scala 413:114] + wire _T_2241 = _T_2170 & _T_2240; // @[lsu_bus_buffer.scala 411:113] + wire _T_2243 = _T_2241 | buf_age_1[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2257 = _T_2180 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2258 = _T_4481 | _T_2257; // @[lsu_bus_buffer.scala 412:86] + wire _T_2264 = _T_2187 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2265 = _T_2258 | _T_2264; // @[lsu_bus_buffer.scala 413:114] + wire _T_2266 = _T_2170 & _T_2265; // @[lsu_bus_buffer.scala 411:113] + wire _T_2268 = _T_2266 | buf_age_1[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2270 = {_T_2268,_T_2243,_T_2218}; // @[Cat.scala 29:58] + wire _T_3920 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3921 = _T_3537 & _T_3920; // @[lsu_bus_buffer.scala 445:112] + wire _T_3923 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3924 = _T_3540 & _T_3923; // @[lsu_bus_buffer.scala 445:161] + wire _T_3925 = _T_3921 | _T_3924; // @[lsu_bus_buffer.scala 445:132] + wire _T_3926 = _T_853 & _T_3925; // @[lsu_bus_buffer.scala 445:63] + wire _T_3927 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3928 = ibuf_drain_vld & _T_3927; // @[lsu_bus_buffer.scala 445:201] + wire _T_3929 = _T_3926 | _T_3928; // @[lsu_bus_buffer.scala 445:183] + wire _T_4018 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 475:73] + wire _T_4019 = bus_rsp_write & _T_4018; // @[lsu_bus_buffer.scala 475:52] + wire _T_4020 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 476:46] + wire _T_4023 = buf_ldfwd[2] & _T_1349; // @[lsu_bus_buffer.scala 477:27] + wire _T_4024 = _T_4020 | _T_4023; // @[lsu_bus_buffer.scala 476:77] + wire _T_4025 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 478:26] + wire _T_4027 = ~buf_write[2]; // @[lsu_bus_buffer.scala 478:44] + wire _T_4028 = _T_4025 & _T_4027; // @[lsu_bus_buffer.scala 478:42] + wire _T_4029 = _T_4028 & buf_samedw_2; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] + wire [2:0] _GEN_386 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 478:94] + wire _T_4030 = io_lsu_axi_r_bits_id == _GEN_386; // @[lsu_bus_buffer.scala 478:94] + wire _T_4031 = _T_4029 & _T_4030; // @[lsu_bus_buffer.scala 478:74] + wire _T_4032 = _T_4024 | _T_4031; // @[lsu_bus_buffer.scala 477:71] + wire _T_4033 = bus_rsp_read & _T_4032; // @[lsu_bus_buffer.scala 476:25] + wire _T_4034 = _T_4019 | _T_4033; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_204 = _T_3974 & _T_4034; // @[Conditional.scala 39:67] + wire _GEN_224 = _T_3940 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] + wire _GEN_236 = _T_3936 ? 1'h0 : _GEN_224; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_236; // @[Conditional.scala 40:58] + wire [3:0] _T_4069 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 492:21] + wire _T_4072 = _T_4069[0] & _T_1349; // @[lsu_bus_buffer.scala 492:38] + wire _T_4073 = _T_4030 | _T_4072; // @[lsu_bus_buffer.scala 491:95] + wire _T_4074 = bus_rsp_read & _T_4073; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_198 = _T_4059 & _T_4074; // @[Conditional.scala 39:67] + wire _GEN_205 = _T_3974 ? buf_resp_state_bus_en_2 : _GEN_198; // @[Conditional.scala 39:67] + wire _GEN_215 = _T_3940 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67] + wire _GEN_229 = _T_3936 ? 1'h0 : _GEN_215; // @[Conditional.scala 39:67] + wire buf_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_229; // @[Conditional.scala 40:58] + wire _T_3953 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3954 = _T_3953 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_4080 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 499:37] + wire _T_4081 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_4082 = buf_dual_2 & _T_4081; // @[lsu_bus_buffer.scala 499:80] + wire _T_4083 = _T_4080 | _T_4082; // @[lsu_bus_buffer.scala 499:65] + wire _T_4084 = _T_4083 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_193 = _T_4077 ? _T_4084 : _T_4085; // @[Conditional.scala 39:67] + wire _GEN_199 = _T_4059 ? _T_3954 : _GEN_193; // @[Conditional.scala 39:67] + wire _GEN_206 = _T_3974 ? _T_3954 : _GEN_199; // @[Conditional.scala 39:67] + wire _GEN_216 = _T_3940 ? _T_3954 : _GEN_206; // @[Conditional.scala 39:67] + wire _GEN_226 = _T_3936 ? obuf_rdrsp_pend_en : _GEN_216; // @[Conditional.scala 39:67] + wire buf_state_en_2 = _T_3913 ? _T_3929 : _GEN_226; // @[Conditional.scala 40:58] + wire _T_2272 = _T_1814 & buf_state_en_2; // @[lsu_bus_buffer.scala 411:94] + wire _T_2282 = _T_2076 & _T_1817; // @[lsu_bus_buffer.scala 413:71] + wire _T_2284 = _T_2282 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2285 = _T_4466 | _T_2284; // @[lsu_bus_buffer.scala 412:86] + wire _T_2289 = _T_2083 & _T_1818; // @[lsu_bus_buffer.scala 414:52] + wire _T_2291 = _T_2289 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2292 = _T_2285 | _T_2291; // @[lsu_bus_buffer.scala 413:114] + wire _T_2293 = _T_2272 & _T_2292; // @[lsu_bus_buffer.scala 411:113] + wire _T_2295 = _T_2293 | buf_age_2[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2309 = _T_2282 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2310 = _T_4471 | _T_2309; // @[lsu_bus_buffer.scala 412:86] + wire _T_2316 = _T_2289 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2317 = _T_2310 | _T_2316; // @[lsu_bus_buffer.scala 413:114] + wire _T_2318 = _T_2272 & _T_2317; // @[lsu_bus_buffer.scala 411:113] + wire _T_2320 = _T_2318 | buf_age_2[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2334 = _T_2282 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2335 = _T_4476 | _T_2334; // @[lsu_bus_buffer.scala 412:86] + wire _T_2341 = _T_2289 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2342 = _T_2335 | _T_2341; // @[lsu_bus_buffer.scala 413:114] + wire _T_2343 = _T_2272 & _T_2342; // @[lsu_bus_buffer.scala 411:113] + wire _T_2345 = _T_2343 | buf_age_2[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2359 = _T_2282 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2360 = _T_4481 | _T_2359; // @[lsu_bus_buffer.scala 412:86] + wire _T_2366 = _T_2289 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2367 = _T_2360 | _T_2366; // @[lsu_bus_buffer.scala 413:114] + wire _T_2368 = _T_2272 & _T_2367; // @[lsu_bus_buffer.scala 411:113] + wire _T_2370 = _T_2368 | buf_age_2[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2372 = {_T_2370,_T_2345,_T_2320}; // @[Cat.scala 29:58] + wire _T_4111 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_4112 = _T_3537 & _T_4111; // @[lsu_bus_buffer.scala 445:112] + wire _T_4114 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_4115 = _T_3540 & _T_4114; // @[lsu_bus_buffer.scala 445:161] + wire _T_4116 = _T_4112 | _T_4115; // @[lsu_bus_buffer.scala 445:132] + wire _T_4117 = _T_853 & _T_4116; // @[lsu_bus_buffer.scala 445:63] + wire _T_4118 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_4119 = ibuf_drain_vld & _T_4118; // @[lsu_bus_buffer.scala 445:201] + wire _T_4120 = _T_4117 | _T_4119; // @[lsu_bus_buffer.scala 445:183] + wire _T_4209 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 475:73] + wire _T_4210 = bus_rsp_write & _T_4209; // @[lsu_bus_buffer.scala 475:52] + wire _T_4211 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 476:46] + wire _T_4214 = buf_ldfwd[3] & _T_1349; // @[lsu_bus_buffer.scala 477:27] + wire _T_4215 = _T_4211 | _T_4214; // @[lsu_bus_buffer.scala 476:77] + wire _T_4216 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 478:26] + wire _T_4218 = ~buf_write[3]; // @[lsu_bus_buffer.scala 478:44] + wire _T_4219 = _T_4216 & _T_4218; // @[lsu_bus_buffer.scala 478:42] + wire _T_4220 = _T_4219 & buf_samedw_3; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] + wire [2:0] _GEN_388 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 478:94] + wire _T_4221 = io_lsu_axi_r_bits_id == _GEN_388; // @[lsu_bus_buffer.scala 478:94] + wire _T_4222 = _T_4220 & _T_4221; // @[lsu_bus_buffer.scala 478:74] + wire _T_4223 = _T_4215 | _T_4222; // @[lsu_bus_buffer.scala 477:71] + wire _T_4224 = bus_rsp_read & _T_4223; // @[lsu_bus_buffer.scala 476:25] + wire _T_4225 = _T_4210 | _T_4224; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_280 = _T_4165 & _T_4225; // @[Conditional.scala 39:67] + wire _GEN_300 = _T_4131 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] + wire _GEN_312 = _T_4127 ? 1'h0 : _GEN_300; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_312; // @[Conditional.scala 40:58] + wire [3:0] _T_4260 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 492:21] + wire _T_4263 = _T_4260[0] & _T_1349; // @[lsu_bus_buffer.scala 492:38] + wire _T_4264 = _T_4221 | _T_4263; // @[lsu_bus_buffer.scala 491:95] + wire _T_4265 = bus_rsp_read & _T_4264; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_274 = _T_4250 & _T_4265; // @[Conditional.scala 39:67] + wire _GEN_281 = _T_4165 ? buf_resp_state_bus_en_3 : _GEN_274; // @[Conditional.scala 39:67] + wire _GEN_291 = _T_4131 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67] + wire _GEN_305 = _T_4127 ? 1'h0 : _GEN_291; // @[Conditional.scala 39:67] + wire buf_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_305; // @[Conditional.scala 40:58] + wire _T_4144 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_4145 = _T_4144 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_4271 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 499:37] + wire _T_4272 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_4273 = buf_dual_3 & _T_4272; // @[lsu_bus_buffer.scala 499:80] + wire _T_4274 = _T_4271 | _T_4273; // @[lsu_bus_buffer.scala 499:65] + wire _T_4275 = _T_4274 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_269 = _T_4268 ? _T_4275 : _T_4276; // @[Conditional.scala 39:67] + wire _GEN_275 = _T_4250 ? _T_4145 : _GEN_269; // @[Conditional.scala 39:67] + wire _GEN_282 = _T_4165 ? _T_4145 : _GEN_275; // @[Conditional.scala 39:67] + wire _GEN_292 = _T_4131 ? _T_4145 : _GEN_282; // @[Conditional.scala 39:67] + wire _GEN_302 = _T_4127 ? obuf_rdrsp_pend_en : _GEN_292; // @[Conditional.scala 39:67] + wire buf_state_en_3 = _T_4104 ? _T_4120 : _GEN_302; // @[Conditional.scala 40:58] + wire _T_2374 = _T_1825 & buf_state_en_3; // @[lsu_bus_buffer.scala 411:94] + wire _T_2384 = _T_2076 & _T_1828; // @[lsu_bus_buffer.scala 413:71] + wire _T_2386 = _T_2384 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2387 = _T_4466 | _T_2386; // @[lsu_bus_buffer.scala 412:86] + wire _T_2391 = _T_2083 & _T_1829; // @[lsu_bus_buffer.scala 414:52] + wire _T_2393 = _T_2391 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2394 = _T_2387 | _T_2393; // @[lsu_bus_buffer.scala 413:114] + wire _T_2395 = _T_2374 & _T_2394; // @[lsu_bus_buffer.scala 411:113] + wire _T_2397 = _T_2395 | buf_age_3[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2411 = _T_2384 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2412 = _T_4471 | _T_2411; // @[lsu_bus_buffer.scala 412:86] + wire _T_2418 = _T_2391 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2419 = _T_2412 | _T_2418; // @[lsu_bus_buffer.scala 413:114] + wire _T_2420 = _T_2374 & _T_2419; // @[lsu_bus_buffer.scala 411:113] + wire _T_2422 = _T_2420 | buf_age_3[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2436 = _T_2384 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2437 = _T_4476 | _T_2436; // @[lsu_bus_buffer.scala 412:86] + wire _T_2443 = _T_2391 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2444 = _T_2437 | _T_2443; // @[lsu_bus_buffer.scala 413:114] + wire _T_2445 = _T_2374 & _T_2444; // @[lsu_bus_buffer.scala 411:113] + wire _T_2447 = _T_2445 | buf_age_3[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2461 = _T_2384 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2462 = _T_4481 | _T_2461; // @[lsu_bus_buffer.scala 412:86] + wire _T_2468 = _T_2391 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2469 = _T_2462 | _T_2468; // @[lsu_bus_buffer.scala 413:114] + wire _T_2470 = _T_2374 & _T_2469; // @[lsu_bus_buffer.scala 411:113] + wire _T_2472 = _T_2470 | buf_age_3[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2474 = {_T_2472,_T_2447,_T_2422}; // @[Cat.scala 29:58] + wire _T_2770 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2771 = _T_1792 | _T_2770; // @[lsu_bus_buffer.scala 422:32] + wire _T_2772 = ~_T_2771; // @[lsu_bus_buffer.scala 422:6] + wire _T_2780 = _T_2772 | _T_2080; // @[lsu_bus_buffer.scala 422:59] + wire _T_2787 = _T_2780 | _T_2087; // @[lsu_bus_buffer.scala 423:110] + wire _T_2788 = _T_2068 & _T_2787; // @[lsu_bus_buffer.scala 421:112] + wire _T_2792 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2793 = _T_1803 | _T_2792; // @[lsu_bus_buffer.scala 422:32] + wire _T_2794 = ~_T_2793; // @[lsu_bus_buffer.scala 422:6] + wire _T_2802 = _T_2794 | _T_2105; // @[lsu_bus_buffer.scala 422:59] + wire _T_2809 = _T_2802 | _T_2112; // @[lsu_bus_buffer.scala 423:110] + wire _T_2810 = _T_2068 & _T_2809; // @[lsu_bus_buffer.scala 421:112] + wire _T_2814 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2815 = _T_1814 | _T_2814; // @[lsu_bus_buffer.scala 422:32] + wire _T_2816 = ~_T_2815; // @[lsu_bus_buffer.scala 422:6] + wire _T_2824 = _T_2816 | _T_2130; // @[lsu_bus_buffer.scala 422:59] + wire _T_2831 = _T_2824 | _T_2137; // @[lsu_bus_buffer.scala 423:110] + wire _T_2832 = _T_2068 & _T_2831; // @[lsu_bus_buffer.scala 421:112] + wire _T_2836 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2837 = _T_1825 | _T_2836; // @[lsu_bus_buffer.scala 422:32] + wire _T_2838 = ~_T_2837; // @[lsu_bus_buffer.scala 422:6] + wire _T_2846 = _T_2838 | _T_2155; // @[lsu_bus_buffer.scala 422:59] + wire _T_2853 = _T_2846 | _T_2162; // @[lsu_bus_buffer.scala 423:110] + wire _T_2854 = _T_2068 & _T_2853; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_0 = {_T_2854,_T_2832,_T_2810,_T_2788}; // @[Cat.scala 29:58] + wire _T_2871 = _T_2772 | _T_2182; // @[lsu_bus_buffer.scala 422:59] + wire _T_2878 = _T_2871 | _T_2189; // @[lsu_bus_buffer.scala 423:110] + wire _T_2879 = _T_2170 & _T_2878; // @[lsu_bus_buffer.scala 421:112] + wire _T_2893 = _T_2794 | _T_2207; // @[lsu_bus_buffer.scala 422:59] + wire _T_2900 = _T_2893 | _T_2214; // @[lsu_bus_buffer.scala 423:110] + wire _T_2901 = _T_2170 & _T_2900; // @[lsu_bus_buffer.scala 421:112] + wire _T_2915 = _T_2816 | _T_2232; // @[lsu_bus_buffer.scala 422:59] + wire _T_2922 = _T_2915 | _T_2239; // @[lsu_bus_buffer.scala 423:110] + wire _T_2923 = _T_2170 & _T_2922; // @[lsu_bus_buffer.scala 421:112] + wire _T_2937 = _T_2838 | _T_2257; // @[lsu_bus_buffer.scala 422:59] + wire _T_2944 = _T_2937 | _T_2264; // @[lsu_bus_buffer.scala 423:110] + wire _T_2945 = _T_2170 & _T_2944; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_1 = {_T_2945,_T_2923,_T_2901,_T_2879}; // @[Cat.scala 29:58] + wire _T_2962 = _T_2772 | _T_2284; // @[lsu_bus_buffer.scala 422:59] + wire _T_2969 = _T_2962 | _T_2291; // @[lsu_bus_buffer.scala 423:110] + wire _T_2970 = _T_2272 & _T_2969; // @[lsu_bus_buffer.scala 421:112] + wire _T_2984 = _T_2794 | _T_2309; // @[lsu_bus_buffer.scala 422:59] + wire _T_2991 = _T_2984 | _T_2316; // @[lsu_bus_buffer.scala 423:110] + wire _T_2992 = _T_2272 & _T_2991; // @[lsu_bus_buffer.scala 421:112] + wire _T_3006 = _T_2816 | _T_2334; // @[lsu_bus_buffer.scala 422:59] + wire _T_3013 = _T_3006 | _T_2341; // @[lsu_bus_buffer.scala 423:110] + wire _T_3014 = _T_2272 & _T_3013; // @[lsu_bus_buffer.scala 421:112] + wire _T_3028 = _T_2838 | _T_2359; // @[lsu_bus_buffer.scala 422:59] + wire _T_3035 = _T_3028 | _T_2366; // @[lsu_bus_buffer.scala 423:110] + wire _T_3036 = _T_2272 & _T_3035; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_2 = {_T_3036,_T_3014,_T_2992,_T_2970}; // @[Cat.scala 29:58] + wire _T_3053 = _T_2772 | _T_2386; // @[lsu_bus_buffer.scala 422:59] + wire _T_3060 = _T_3053 | _T_2393; // @[lsu_bus_buffer.scala 423:110] + wire _T_3061 = _T_2374 & _T_3060; // @[lsu_bus_buffer.scala 421:112] + wire _T_3075 = _T_2794 | _T_2411; // @[lsu_bus_buffer.scala 422:59] + wire _T_3082 = _T_3075 | _T_2418; // @[lsu_bus_buffer.scala 423:110] + wire _T_3083 = _T_2374 & _T_3082; // @[lsu_bus_buffer.scala 421:112] + wire _T_3097 = _T_2816 | _T_2436; // @[lsu_bus_buffer.scala 422:59] + wire _T_3104 = _T_3097 | _T_2443; // @[lsu_bus_buffer.scala 423:110] + wire _T_3105 = _T_2374 & _T_3104; // @[lsu_bus_buffer.scala 421:112] + wire _T_3119 = _T_2838 | _T_2461; // @[lsu_bus_buffer.scala 422:59] + wire _T_3126 = _T_3119 | _T_2468; // @[lsu_bus_buffer.scala 423:110] + wire _T_3127 = _T_2374 & _T_3126; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_3 = {_T_3127,_T_3105,_T_3083,_T_3061}; // @[Cat.scala 29:58] + wire _T_3218 = _T_2836 | _T_1825; // @[lsu_bus_buffer.scala 426:110] + wire _T_3219 = ~_T_3218; // @[lsu_bus_buffer.scala 426:84] + wire _T_3220 = buf_rspageQ_0[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3222 = _T_3220 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3210 = _T_2814 | _T_1814; // @[lsu_bus_buffer.scala 426:110] + wire _T_3211 = ~_T_3210; // @[lsu_bus_buffer.scala 426:84] + wire _T_3212 = buf_rspageQ_0[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3214 = _T_3212 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3202 = _T_2792 | _T_1803; // @[lsu_bus_buffer.scala 426:110] + wire _T_3203 = ~_T_3202; // @[lsu_bus_buffer.scala 426:84] + wire _T_3204 = buf_rspageQ_0[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3206 = _T_3204 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3194 = _T_2770 | _T_1792; // @[lsu_bus_buffer.scala 426:110] + wire _T_3195 = ~_T_3194; // @[lsu_bus_buffer.scala 426:84] + wire _T_3196 = buf_rspageQ_0[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3198 = _T_3196 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_0 = {_T_3222,_T_3214,_T_3206,_T_3198}; // @[Cat.scala 29:58] + wire _T_3133 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3136 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3139 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3142 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3144 = {_T_3142,_T_3139,_T_3136}; // @[Cat.scala 29:58] + wire _T_3255 = buf_rspageQ_1[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3257 = _T_3255 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3247 = buf_rspageQ_1[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3249 = _T_3247 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3239 = buf_rspageQ_1[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3241 = _T_3239 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3231 = buf_rspageQ_1[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3233 = _T_3231 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_1 = {_T_3257,_T_3249,_T_3241,_T_3233}; // @[Cat.scala 29:58] + wire _T_3148 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3151 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3154 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3157 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3159 = {_T_3157,_T_3154,_T_3151}; // @[Cat.scala 29:58] + wire _T_3290 = buf_rspageQ_2[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3292 = _T_3290 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3282 = buf_rspageQ_2[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3284 = _T_3282 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3274 = buf_rspageQ_2[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3276 = _T_3274 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3266 = buf_rspageQ_2[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3268 = _T_3266 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_2 = {_T_3292,_T_3284,_T_3276,_T_3268}; // @[Cat.scala 29:58] + wire _T_3163 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3166 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3169 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3172 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3174 = {_T_3172,_T_3169,_T_3166}; // @[Cat.scala 29:58] + wire _T_3325 = buf_rspageQ_3[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3327 = _T_3325 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3317 = buf_rspageQ_3[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3319 = _T_3317 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3309 = buf_rspageQ_3[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3311 = _T_3309 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3301 = buf_rspageQ_3[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3303 = _T_3301 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_3 = {_T_3327,_T_3319,_T_3311,_T_3303}; // @[Cat.scala 29:58] + wire _T_3178 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3181 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3184 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3187 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3189 = {_T_3187,_T_3184,_T_3181}; // @[Cat.scala 29:58] + wire _T_3332 = ibuf_drain_vld & _T_1793; // @[lsu_bus_buffer.scala 427:63] + wire _T_3334 = ibuf_drain_vld & _T_1804; // @[lsu_bus_buffer.scala 427:63] + wire _T_3336 = ibuf_drain_vld & _T_1815; // @[lsu_bus_buffer.scala 427:63] + wire _T_3338 = ibuf_drain_vld & _T_1826; // @[lsu_bus_buffer.scala 427:63] + wire [3:0] ibuf_drainvec_vld = {_T_3338,_T_3336,_T_3334,_T_3332}; // @[Cat.scala 29:58] + wire _T_3346 = _T_3540 & _T_1796; // @[lsu_bus_buffer.scala 429:35] + wire _T_3355 = _T_3540 & _T_1807; // @[lsu_bus_buffer.scala 429:35] + wire _T_3364 = _T_3540 & _T_1818; // @[lsu_bus_buffer.scala 429:35] + wire _T_3373 = _T_3540 & _T_1829; // @[lsu_bus_buffer.scala 429:35] + wire _T_3403 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3405 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3407 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3409 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire [3:0] buf_dual_in = {_T_3409,_T_3407,_T_3405,_T_3403}; // @[Cat.scala 29:58] + wire _T_3414 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3416 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3418 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3420 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire [3:0] buf_samedw_in = {_T_3420,_T_3418,_T_3416,_T_3414}; // @[Cat.scala 29:58] + wire _T_3425 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 433:84] + wire _T_3426 = ibuf_drainvec_vld[0] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3429 = ibuf_drainvec_vld[1] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3432 = ibuf_drainvec_vld[2] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3435 = ibuf_drainvec_vld[3] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire [3:0] buf_nomerge_in = {_T_3435,_T_3432,_T_3429,_T_3426}; // @[Cat.scala 29:58] + wire _T_3443 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3346; // @[lsu_bus_buffer.scala 434:47] + wire _T_3448 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3355; // @[lsu_bus_buffer.scala 434:47] + wire _T_3453 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3364; // @[lsu_bus_buffer.scala 434:47] + wire _T_3458 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3373; // @[lsu_bus_buffer.scala 434:47] + wire [3:0] buf_dualhi_in = {_T_3458,_T_3453,_T_3448,_T_3443}; // @[Cat.scala 29:58] + wire _T_3487 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3489 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3491 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3493 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire [3:0] buf_sideeffect_in = {_T_3493,_T_3491,_T_3489,_T_3487}; // @[Cat.scala 29:58] + wire _T_3498 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3500 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3502 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3504 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire [3:0] buf_unsign_in = {_T_3504,_T_3502,_T_3500,_T_3498}; // @[Cat.scala 29:58] + wire _T_3521 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3523 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3525 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3527 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire [3:0] buf_write_in = {_T_3527,_T_3525,_T_3523,_T_3521}; // @[Cat.scala 29:58] + wire _T_3560 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 459:89] + wire _T_3562 = _T_3560 & _T_1349; // @[lsu_bus_buffer.scala 459:104] + wire _T_3575 = buf_state_en_0 & _T_3645; // @[lsu_bus_buffer.scala 464:44] + wire _T_3576 = _T_3575 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3578 = _T_3576 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3581 = _T_3571 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3582 = _T_3581 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_4841 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 576:64] + wire bus_rsp_read_error = bus_rsp_read & _T_4841; // @[lsu_bus_buffer.scala 576:38] + wire _T_3585 = _T_3581 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_3659 = bus_rsp_read_error & _T_1349; // @[lsu_bus_buffer.scala 482:91] + wire _T_3661 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 483:31] + wire _T_3663 = _T_3661 & _T_1349; // @[lsu_bus_buffer.scala 483:46] + wire _T_3664 = _T_3659 | _T_3663; // @[lsu_bus_buffer.scala 482:143] + wire _T_4839 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 575:66] + wire bus_rsp_write_error = bus_rsp_write & _T_4839; // @[lsu_bus_buffer.scala 575:40] + wire _T_3666 = bus_rsp_write_error & _T_3636; // @[lsu_bus_buffer.scala 484:33] + wire _T_3667 = _T_3664 | _T_3666; // @[lsu_bus_buffer.scala 483:88] + wire _T_3668 = _T_3571 & _T_3667; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_56 = _T_3592 & _T_3668; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_3558 ? _T_3585 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_82 = _T_3554 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_error_en_0 = _T_3531 ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58] + wire _T_3594 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 472:75] + wire _T_3595 = buf_write[0] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3596 = io_dec_tlu_force_halt | _T_3595; // @[lsu_bus_buffer.scala 472:57] + wire _T_3598 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 473:30] + wire _T_3599 = buf_dual_0 & _T_3598; // @[lsu_bus_buffer.scala 473:28] + wire _T_3602 = _T_3599 & _T_3645; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_29 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_30 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_29; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_31 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_30; // @[lsu_bus_buffer.scala 473:90] + wire _T_3603 = _GEN_31 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3604 = _T_3602 & _T_3603; // @[lsu_bus_buffer.scala 473:61] + wire _T_4489 = _T_2717 | _T_2714; // @[lsu_bus_buffer.scala 536:93] + wire _T_4490 = _T_4489 | _T_2711; // @[lsu_bus_buffer.scala 536:93] + wire any_done_wait_state = _T_4490 | _T_2708; // @[lsu_bus_buffer.scala 536:93] + wire _T_3606 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3612 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3614 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3616 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_3618 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_3620 = _T_3612 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3621 = _T_3614 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3622 = _T_3616 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3623 = _T_3618 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3624 = _T_3620 | _T_3621; // @[Mux.scala 27:72] + wire _T_3625 = _T_3624 | _T_3622; // @[Mux.scala 27:72] + wire _T_3626 = _T_3625 | _T_3623; // @[Mux.scala 27:72] + wire _T_3628 = _T_3602 & _T_3626; // @[lsu_bus_buffer.scala 474:101] + wire _T_3629 = _GEN_31 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_3630 = _T_3628 & _T_3629; // @[lsu_bus_buffer.scala 474:138] + wire _T_3631 = _T_3630 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_3632 = _T_3606 | _T_3631; // @[lsu_bus_buffer.scala 474:53] + wire _T_3655 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_3656 = _T_3655 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_3669 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 485:50] + wire _T_3670 = buf_state_en_0 & _T_3669; // @[lsu_bus_buffer.scala 485:48] + wire _T_3682 = buf_ldfwd[0] | _T_3687[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_3683 = _T_3682 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_39 = _T_3703 ? buf_state_en_0 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_3695 ? io_dec_tlu_force_halt : _T_3703; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_3695 ? io_dec_tlu_force_halt : _GEN_39; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_3677 ? io_dec_tlu_force_halt : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_3677 ? io_dec_tlu_force_halt : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_3592 & _T_3656; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_3592 ? io_dec_tlu_force_halt : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_3592 ? io_dec_tlu_force_halt : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_3558 ? _T_3578 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_3558 ? _T_3582 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_3558 ? io_dec_tlu_force_halt : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_3554 ? io_dec_tlu_force_halt : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_3554 ? io_dec_tlu_force_halt : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_3554 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67] + wire buf_wr_en_0 = _T_3531 & buf_state_en_0; // @[Conditional.scala 40:58] + wire buf_data_en_0 = _T_3531 ? buf_state_en_0 : _GEN_81; // @[Conditional.scala 40:58] + wire buf_rst_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_76; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_79; // @[Conditional.scala 40:58] + wire _T_3766 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 464:44] + wire _T_3767 = _T_3766 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3769 = _T_3767 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3772 = _T_3762 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3773 = _T_3772 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_3776 = _T_3772 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 482:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 483:31] + wire _T_3854 = _T_3852 & _T_1349; // @[lsu_bus_buffer.scala 483:46] + wire _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 482:143] + wire _T_3857 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 484:33] + wire _T_3858 = _T_3855 | _T_3857; // @[lsu_bus_buffer.scala 483:88] + wire _T_3859 = _T_3762 & _T_3858; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_132 = _T_3783 & _T_3859; // @[Conditional.scala 39:67] + wire _GEN_145 = _T_3749 ? _T_3776 : _GEN_132; // @[Conditional.scala 39:67] + wire _GEN_158 = _T_3745 ? 1'h0 : _GEN_145; // @[Conditional.scala 39:67] + wire buf_error_en_1 = _T_3722 ? 1'h0 : _GEN_158; // @[Conditional.scala 40:58] + wire _T_3786 = buf_write[1] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 472:57] + wire _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 473:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 473:28] + wire _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_105 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_106 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_105; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_107 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_106; // @[lsu_bus_buffer.scala 473:90] + wire _T_3794 = _GEN_107 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 473:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_3809 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] + wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] + wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] + wire _T_3819 = _T_3793 & _T_3817; // @[lsu_bus_buffer.scala 474:101] + wire _T_3820 = _GEN_107 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 474:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 474:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_3860 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 485:50] + wire _T_3861 = buf_state_en_1 & _T_3860; // @[lsu_bus_buffer.scala 485:48] + wire _T_3873 = buf_ldfwd[1] | _T_3878[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_3874 = _T_3873 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_115 = _T_3894 ? buf_state_en_1 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_119 = _T_3886 ? io_dec_tlu_force_halt : _T_3894; // @[Conditional.scala 39:67] + wire _GEN_120 = _T_3886 ? io_dec_tlu_force_halt : _GEN_115; // @[Conditional.scala 39:67] + wire _GEN_125 = _T_3868 ? io_dec_tlu_force_halt : _GEN_119; // @[Conditional.scala 39:67] + wire _GEN_126 = _T_3868 ? io_dec_tlu_force_halt : _GEN_120; // @[Conditional.scala 39:67] + wire _GEN_131 = _T_3783 & _T_3847; // @[Conditional.scala 39:67] + wire _GEN_135 = _T_3783 ? io_dec_tlu_force_halt : _GEN_125; // @[Conditional.scala 39:67] + wire _GEN_136 = _T_3783 ? io_dec_tlu_force_halt : _GEN_126; // @[Conditional.scala 39:67] + wire _GEN_142 = _T_3749 ? _T_3769 : _GEN_136; // @[Conditional.scala 39:67] + wire _GEN_144 = _T_3749 ? _T_3773 : _GEN_131; // @[Conditional.scala 39:67] + wire _GEN_147 = _T_3749 ? io_dec_tlu_force_halt : _GEN_135; // @[Conditional.scala 39:67] + wire _GEN_152 = _T_3745 ? io_dec_tlu_force_halt : _GEN_147; // @[Conditional.scala 39:67] + wire _GEN_155 = _T_3745 ? io_dec_tlu_force_halt : _GEN_142; // @[Conditional.scala 39:67] + wire _GEN_157 = _T_3745 ? 1'h0 : _GEN_144; // @[Conditional.scala 39:67] + wire buf_wr_en_1 = _T_3722 & buf_state_en_1; // @[Conditional.scala 40:58] + wire buf_data_en_1 = _T_3722 ? buf_state_en_1 : _GEN_157; // @[Conditional.scala 40:58] + wire buf_rst_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_152; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_155; // @[Conditional.scala 40:58] + wire _T_3957 = buf_state_en_2 & _T_4027; // @[lsu_bus_buffer.scala 464:44] + wire _T_3958 = _T_3957 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3960 = _T_3958 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3963 = _T_3953 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3964 = _T_3963 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_3967 = _T_3963 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_4041 = bus_rsp_read_error & _T_4020; // @[lsu_bus_buffer.scala 482:91] + wire _T_4043 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 483:31] + wire _T_4045 = _T_4043 & _T_1349; // @[lsu_bus_buffer.scala 483:46] + wire _T_4046 = _T_4041 | _T_4045; // @[lsu_bus_buffer.scala 482:143] + wire _T_4048 = bus_rsp_write_error & _T_4018; // @[lsu_bus_buffer.scala 484:33] + wire _T_4049 = _T_4046 | _T_4048; // @[lsu_bus_buffer.scala 483:88] + wire _T_4050 = _T_3953 & _T_4049; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_208 = _T_3974 & _T_4050; // @[Conditional.scala 39:67] + wire _GEN_221 = _T_3940 ? _T_3967 : _GEN_208; // @[Conditional.scala 39:67] + wire _GEN_234 = _T_3936 ? 1'h0 : _GEN_221; // @[Conditional.scala 39:67] + wire buf_error_en_2 = _T_3913 ? 1'h0 : _GEN_234; // @[Conditional.scala 40:58] + wire _T_3977 = buf_write[2] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3978 = io_dec_tlu_force_halt | _T_3977; // @[lsu_bus_buffer.scala 472:57] + wire _T_3980 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 473:30] + wire _T_3981 = buf_dual_2 & _T_3980; // @[lsu_bus_buffer.scala 473:28] + wire _T_3984 = _T_3981 & _T_4027; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_181 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_182 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_181; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_183 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_182; // @[lsu_bus_buffer.scala 473:90] + wire _T_3985 = _GEN_183 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3986 = _T_3984 & _T_3985; // @[lsu_bus_buffer.scala 473:61] + wire _T_3988 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3994 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3996 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3998 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_4000 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_4002 = _T_3994 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4003 = _T_3996 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4004 = _T_3998 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4005 = _T_4000 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4006 = _T_4002 | _T_4003; // @[Mux.scala 27:72] + wire _T_4007 = _T_4006 | _T_4004; // @[Mux.scala 27:72] + wire _T_4008 = _T_4007 | _T_4005; // @[Mux.scala 27:72] + wire _T_4010 = _T_3984 & _T_4008; // @[lsu_bus_buffer.scala 474:101] + wire _T_4011 = _GEN_183 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_4012 = _T_4010 & _T_4011; // @[lsu_bus_buffer.scala 474:138] + wire _T_4013 = _T_4012 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_4014 = _T_3988 | _T_4013; // @[lsu_bus_buffer.scala 474:53] + wire _T_4037 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_4038 = _T_4037 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_4051 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 485:50] + wire _T_4052 = buf_state_en_2 & _T_4051; // @[lsu_bus_buffer.scala 485:48] + wire _T_4064 = buf_ldfwd[2] | _T_4069[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_4065 = _T_4064 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_191 = _T_4085 ? buf_state_en_2 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_195 = _T_4077 ? io_dec_tlu_force_halt : _T_4085; // @[Conditional.scala 39:67] + wire _GEN_196 = _T_4077 ? io_dec_tlu_force_halt : _GEN_191; // @[Conditional.scala 39:67] + wire _GEN_201 = _T_4059 ? io_dec_tlu_force_halt : _GEN_195; // @[Conditional.scala 39:67] + wire _GEN_202 = _T_4059 ? io_dec_tlu_force_halt : _GEN_196; // @[Conditional.scala 39:67] + wire _GEN_207 = _T_3974 & _T_4038; // @[Conditional.scala 39:67] + wire _GEN_211 = _T_3974 ? io_dec_tlu_force_halt : _GEN_201; // @[Conditional.scala 39:67] + wire _GEN_212 = _T_3974 ? io_dec_tlu_force_halt : _GEN_202; // @[Conditional.scala 39:67] + wire _GEN_218 = _T_3940 ? _T_3960 : _GEN_212; // @[Conditional.scala 39:67] + wire _GEN_220 = _T_3940 ? _T_3964 : _GEN_207; // @[Conditional.scala 39:67] + wire _GEN_223 = _T_3940 ? io_dec_tlu_force_halt : _GEN_211; // @[Conditional.scala 39:67] + wire _GEN_228 = _T_3936 ? io_dec_tlu_force_halt : _GEN_223; // @[Conditional.scala 39:67] + wire _GEN_231 = _T_3936 ? io_dec_tlu_force_halt : _GEN_218; // @[Conditional.scala 39:67] + wire _GEN_233 = _T_3936 ? 1'h0 : _GEN_220; // @[Conditional.scala 39:67] + wire buf_wr_en_2 = _T_3913 & buf_state_en_2; // @[Conditional.scala 40:58] + wire buf_data_en_2 = _T_3913 ? buf_state_en_2 : _GEN_233; // @[Conditional.scala 40:58] + wire buf_rst_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_228; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_231; // @[Conditional.scala 40:58] + wire _T_4148 = buf_state_en_3 & _T_4218; // @[lsu_bus_buffer.scala 464:44] + wire _T_4149 = _T_4148 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_4151 = _T_4149 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_4154 = _T_4144 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_4155 = _T_4154 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_4158 = _T_4154 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_4232 = bus_rsp_read_error & _T_4211; // @[lsu_bus_buffer.scala 482:91] + wire _T_4234 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 483:31] + wire _T_4236 = _T_4234 & _T_1349; // @[lsu_bus_buffer.scala 483:46] + wire _T_4237 = _T_4232 | _T_4236; // @[lsu_bus_buffer.scala 482:143] + wire _T_4239 = bus_rsp_write_error & _T_4209; // @[lsu_bus_buffer.scala 484:33] + wire _T_4240 = _T_4237 | _T_4239; // @[lsu_bus_buffer.scala 483:88] + wire _T_4241 = _T_4144 & _T_4240; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_284 = _T_4165 & _T_4241; // @[Conditional.scala 39:67] + wire _GEN_297 = _T_4131 ? _T_4158 : _GEN_284; // @[Conditional.scala 39:67] + wire _GEN_310 = _T_4127 ? 1'h0 : _GEN_297; // @[Conditional.scala 39:67] + wire buf_error_en_3 = _T_4104 ? 1'h0 : _GEN_310; // @[Conditional.scala 40:58] + wire _T_4168 = buf_write[3] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_4169 = io_dec_tlu_force_halt | _T_4168; // @[lsu_bus_buffer.scala 472:57] + wire _T_4171 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 473:30] + wire _T_4172 = buf_dual_3 & _T_4171; // @[lsu_bus_buffer.scala 473:28] + wire _T_4175 = _T_4172 & _T_4218; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_257 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_258 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_257; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_259 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_258; // @[lsu_bus_buffer.scala 473:90] + wire _T_4176 = _GEN_259 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_4177 = _T_4175 & _T_4176; // @[lsu_bus_buffer.scala 473:61] + wire _T_4179 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_4185 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_4187 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_4189 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_4191 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_4193 = _T_4185 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4194 = _T_4187 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4195 = _T_4189 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4196 = _T_4191 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4197 = _T_4193 | _T_4194; // @[Mux.scala 27:72] + wire _T_4198 = _T_4197 | _T_4195; // @[Mux.scala 27:72] + wire _T_4199 = _T_4198 | _T_4196; // @[Mux.scala 27:72] + wire _T_4201 = _T_4175 & _T_4199; // @[lsu_bus_buffer.scala 474:101] + wire _T_4202 = _GEN_259 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_4203 = _T_4201 & _T_4202; // @[lsu_bus_buffer.scala 474:138] + wire _T_4204 = _T_4203 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_4205 = _T_4179 | _T_4204; // @[lsu_bus_buffer.scala 474:53] + wire _T_4228 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_4229 = _T_4228 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_4242 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 485:50] + wire _T_4243 = buf_state_en_3 & _T_4242; // @[lsu_bus_buffer.scala 485:48] + wire _T_4255 = buf_ldfwd[3] | _T_4260[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_4256 = _T_4255 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_267 = _T_4276 ? buf_state_en_3 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_271 = _T_4268 ? io_dec_tlu_force_halt : _T_4276; // @[Conditional.scala 39:67] + wire _GEN_272 = _T_4268 ? io_dec_tlu_force_halt : _GEN_267; // @[Conditional.scala 39:67] + wire _GEN_277 = _T_4250 ? io_dec_tlu_force_halt : _GEN_271; // @[Conditional.scala 39:67] + wire _GEN_278 = _T_4250 ? io_dec_tlu_force_halt : _GEN_272; // @[Conditional.scala 39:67] + wire _GEN_283 = _T_4165 & _T_4229; // @[Conditional.scala 39:67] + wire _GEN_287 = _T_4165 ? io_dec_tlu_force_halt : _GEN_277; // @[Conditional.scala 39:67] + wire _GEN_288 = _T_4165 ? io_dec_tlu_force_halt : _GEN_278; // @[Conditional.scala 39:67] + wire _GEN_294 = _T_4131 ? _T_4151 : _GEN_288; // @[Conditional.scala 39:67] + wire _GEN_296 = _T_4131 ? _T_4155 : _GEN_283; // @[Conditional.scala 39:67] + wire _GEN_299 = _T_4131 ? io_dec_tlu_force_halt : _GEN_287; // @[Conditional.scala 39:67] + wire _GEN_304 = _T_4127 ? io_dec_tlu_force_halt : _GEN_299; // @[Conditional.scala 39:67] + wire _GEN_307 = _T_4127 ? io_dec_tlu_force_halt : _GEN_294; // @[Conditional.scala 39:67] + wire _GEN_309 = _T_4127 ? 1'h0 : _GEN_296; // @[Conditional.scala 39:67] + wire buf_wr_en_3 = _T_4104 & buf_state_en_3; // @[Conditional.scala 40:58] + wire buf_data_en_3 = _T_4104 ? buf_state_en_3 : _GEN_309; // @[Conditional.scala 40:58] + wire buf_rst_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_304; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_307; // @[Conditional.scala 40:58] + reg _T_4331; // @[Reg.scala 27:20] + reg _T_4334; // @[Reg.scala 27:20] + reg _T_4337; // @[Reg.scala 27:20] + reg _T_4340; // @[Reg.scala 27:20] + wire [3:0] buf_unsign = {_T_4340,_T_4337,_T_4334,_T_4331}; // @[Cat.scala 29:58] + wire _T_4387 = ~buf_rst_0; // @[lsu_bus_buffer.scala 531:81] + reg _T_4406; // @[lsu_bus_buffer.scala 531:80] + reg _T_4401; // @[lsu_bus_buffer.scala 531:80] + reg _T_4396; // @[lsu_bus_buffer.scala 531:80] + reg _T_4391; // @[lsu_bus_buffer.scala 531:80] + wire [3:0] buf_error = {_T_4406,_T_4401,_T_4396,_T_4391}; // @[Cat.scala 29:58] + wire _T_4389 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4392 = ~buf_rst_1; // @[lsu_bus_buffer.scala 531:81] + wire _T_4394 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4397 = ~buf_rst_2; // @[lsu_bus_buffer.scala 531:81] + wire _T_4399 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4402 = ~buf_rst_3; // @[lsu_bus_buffer.scala 531:81] + wire _T_4404 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 531:98] + wire [1:0] _T_4410 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4411 = io_ldst_dual_m ? _T_4410 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 532:28] + wire [1:0] _T_4412 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4413 = io_ldst_dual_r ? _T_4412 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 532:94] + wire [2:0] _T_4414 = _T_4411 + _T_4413; // @[lsu_bus_buffer.scala 532:88] + wire [2:0] _GEN_390 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 532:154] + wire [3:0] _T_4415 = _T_4414 + _GEN_390; // @[lsu_bus_buffer.scala 532:154] + wire [1:0] _T_4420 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 532:217] + wire [1:0] _GEN_391 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 532:217] + wire [2:0] _T_4421 = _T_4420 + _GEN_391; // @[lsu_bus_buffer.scala 532:217] + wire [2:0] _GEN_392 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 532:217] + wire [3:0] _T_4422 = _T_4421 + _GEN_392; // @[lsu_bus_buffer.scala 532:217] + wire [3:0] buf_numvld_any = _T_4415 + _T_4422; // @[lsu_bus_buffer.scala 532:169] + wire _T_4493 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 538:52] + wire _T_4494 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 538:92] + wire _T_4495 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 538:121] + wire _T_4497 = |buf_state_0; // @[lsu_bus_buffer.scala 539:52] + wire _T_4498 = |buf_state_1; // @[lsu_bus_buffer.scala 539:52] + wire _T_4499 = |buf_state_2; // @[lsu_bus_buffer.scala 539:52] + wire _T_4500 = |buf_state_3; // @[lsu_bus_buffer.scala 539:52] + wire _T_4501 = _T_4497 | _T_4498; // @[lsu_bus_buffer.scala 539:65] + wire _T_4502 = _T_4501 | _T_4499; // @[lsu_bus_buffer.scala 539:65] + wire _T_4503 = _T_4502 | _T_4500; // @[lsu_bus_buffer.scala 539:65] + wire _T_4504 = ~_T_4503; // @[lsu_bus_buffer.scala 539:34] + wire _T_4506 = _T_4504 & _T_852; // @[lsu_bus_buffer.scala 539:70] + wire _T_4509 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 541:64] + wire _T_4510 = _T_4509 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 541:85] + wire _T_4511 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 541:112] + wire _T_4512 = _T_4510 & _T_4511; // @[lsu_bus_buffer.scala 541:110] + wire _T_4513 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 541:129] + wire _T_4515 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 544:74] + reg lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 629:66] + wire _T_4529 = _T_2770 & _T_3645; // @[Mux.scala 27:72] + wire _T_4530 = _T_2792 & _T_3836; // @[Mux.scala 27:72] + wire _T_4531 = _T_2814 & _T_4027; // @[Mux.scala 27:72] + wire _T_4532 = _T_2836 & _T_4218; // @[Mux.scala 27:72] + wire _T_4533 = _T_4529 | _T_4530; // @[Mux.scala 27:72] + wire _T_4534 = _T_4533 | _T_4531; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4534 | _T_4532; // @[Mux.scala 27:72] + wire _T_4540 = buf_error[0] & _T_3645; // @[lsu_bus_buffer.scala 547:121] + wire _T_4545 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 547:121] + wire _T_4550 = buf_error[2] & _T_4027; // @[lsu_bus_buffer.scala 547:121] + wire _T_4555 = buf_error[3] & _T_4218; // @[lsu_bus_buffer.scala 547:121] + wire _T_4556 = _T_2770 & _T_4540; // @[Mux.scala 27:72] + wire _T_4557 = _T_2792 & _T_4545; // @[Mux.scala 27:72] + wire _T_4558 = _T_2814 & _T_4550; // @[Mux.scala 27:72] + wire _T_4559 = _T_2836 & _T_4555; // @[Mux.scala 27:72] + wire _T_4560 = _T_4556 | _T_4557; // @[Mux.scala 27:72] + wire _T_4561 = _T_4560 | _T_4558; // @[Mux.scala 27:72] + wire _T_4568 = ~buf_dual_0; // @[lsu_bus_buffer.scala 548:121] + wire _T_4569 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 548:136] + wire _T_4570 = _T_4568 | _T_4569; // @[lsu_bus_buffer.scala 548:134] + wire _T_4571 = _T_4529 & _T_4570; // @[lsu_bus_buffer.scala 548:118] + wire _T_4576 = ~buf_dual_1; // @[lsu_bus_buffer.scala 548:121] + wire _T_4577 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 548:136] + wire _T_4578 = _T_4576 | _T_4577; // @[lsu_bus_buffer.scala 548:134] + wire _T_4579 = _T_4530 & _T_4578; // @[lsu_bus_buffer.scala 548:118] + wire _T_4584 = ~buf_dual_2; // @[lsu_bus_buffer.scala 548:121] + wire _T_4585 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 548:136] + wire _T_4586 = _T_4584 | _T_4585; // @[lsu_bus_buffer.scala 548:134] + wire _T_4587 = _T_4531 & _T_4586; // @[lsu_bus_buffer.scala 548:118] + wire _T_4592 = ~buf_dual_3; // @[lsu_bus_buffer.scala 548:121] + wire _T_4593 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 548:136] + wire _T_4594 = _T_4592 | _T_4593; // @[lsu_bus_buffer.scala 548:134] + wire _T_4595 = _T_4532 & _T_4594; // @[lsu_bus_buffer.scala 548:118] + wire [1:0] _T_4598 = _T_4587 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4599 = _T_4595 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_393 = {{1'd0}, _T_4579}; // @[Mux.scala 27:72] + wire [1:0] _T_4601 = _GEN_393 | _T_4598; // @[Mux.scala 27:72] + wire [31:0] _T_4636 = _T_4571 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4637 = _T_4579 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4638 = _T_4587 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4639 = _T_4595 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4640 = _T_4636 | _T_4637; // @[Mux.scala 27:72] + wire [31:0] _T_4641 = _T_4640 | _T_4638; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_lo = _T_4641 | _T_4639; // @[Mux.scala 27:72] + wire _T_4648 = _T_4529 & _T_3643; // @[lsu_bus_buffer.scala 550:105] + wire _T_4654 = _T_4530 & _T_3834; // @[lsu_bus_buffer.scala 550:105] + wire _T_4660 = _T_4531 & _T_4025; // @[lsu_bus_buffer.scala 550:105] + wire _T_4666 = _T_4532 & _T_4216; // @[lsu_bus_buffer.scala 550:105] + wire [31:0] _T_4667 = _T_4648 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4668 = _T_4654 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4669 = _T_4660 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4670 = _T_4666 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4671 = _T_4667 | _T_4668; // @[Mux.scala 27:72] + wire [31:0] _T_4672 = _T_4671 | _T_4669; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_hi = _T_4672 | _T_4670; // @[Mux.scala 27:72] + wire _T_4674 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 62:123] + wire _T_4675 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 62:123] + wire _T_4676 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 62:123] + wire _T_4677 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 62:123] + wire [31:0] _T_4678 = _T_4674 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4679 = _T_4675 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4680 = _T_4676 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4681 = _T_4677 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4682 = _T_4678 | _T_4679; // @[Mux.scala 27:72] + wire [31:0] _T_4683 = _T_4682 | _T_4680; // @[Mux.scala 27:72] + wire [31:0] _T_4684 = _T_4683 | _T_4681; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_addr_offset = _T_4684[1:0]; // @[lsu_bus_buffer.scala 551:96] + wire [1:0] _T_4690 = _T_4674 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4691 = _T_4675 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4692 = _T_4676 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4693 = _T_4677 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4694 = _T_4690 | _T_4691; // @[Mux.scala 27:72] + wire [1:0] _T_4695 = _T_4694 | _T_4692; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_sz = _T_4695 | _T_4693; // @[Mux.scala 27:72] + wire _T_4705 = _T_4674 & buf_unsign[0]; // @[Mux.scala 27:72] + wire _T_4706 = _T_4675 & buf_unsign[1]; // @[Mux.scala 27:72] + wire _T_4707 = _T_4676 & buf_unsign[2]; // @[Mux.scala 27:72] + wire _T_4708 = _T_4677 & buf_unsign[3]; // @[Mux.scala 27:72] + wire _T_4709 = _T_4705 | _T_4706; // @[Mux.scala 27:72] + wire _T_4710 = _T_4709 | _T_4707; // @[Mux.scala 27:72] + wire lsu_nonblock_unsign = _T_4710 | _T_4708; // @[Mux.scala 27:72] + wire [63:0] _T_4712 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] + wire [3:0] _GEN_394 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 555:121] + wire [5:0] _T_4713 = _GEN_394 * 4'h8; // @[lsu_bus_buffer.scala 555:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4712 >> _T_4713; // @[lsu_bus_buffer.scala 555:92] + wire _T_4714 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 557:82] + wire _T_4716 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 558:81] + wire _T_4717 = lsu_nonblock_unsign & _T_4716; // @[lsu_bus_buffer.scala 558:63] + wire [31:0] _T_4719 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4720 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 559:45] + wire _T_4721 = lsu_nonblock_unsign & _T_4720; // @[lsu_bus_buffer.scala 559:26] + wire [31:0] _T_4723 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4724 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 560:6] + wire _T_4726 = _T_4724 & _T_4716; // @[lsu_bus_buffer.scala 560:27] + wire [23:0] _T_4729 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4731 = {_T_4729,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4734 = _T_4724 & _T_4720; // @[lsu_bus_buffer.scala 561:27] + wire [15:0] _T_4737 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4739 = {_T_4737,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4740 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 562:21] + wire [31:0] _T_4741 = _T_4717 ? _T_4719 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4742 = _T_4721 ? _T_4723 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4743 = _T_4726 ? _T_4731 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4744 = _T_4734 ? _T_4739 : 32'h0; // @[Mux.scala 27:72] + wire [63:0] _T_4745 = _T_4740 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4746 = _T_4741 | _T_4742; // @[Mux.scala 27:72] + wire [31:0] _T_4747 = _T_4746 | _T_4743; // @[Mux.scala 27:72] + wire [31:0] _T_4748 = _T_4747 | _T_4744; // @[Mux.scala 27:72] + wire [63:0] _GEN_395 = {{32'd0}, _T_4748}; // @[Mux.scala 27:72] + wire [63:0] _T_4749 = _GEN_395 | _T_4745; // @[Mux.scala 27:72] + wire _T_4878 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4880 = _T_4878 & buf_write[0]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4883 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4885 = _T_4883 & buf_write[1]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4888 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4890 = _T_4888 & buf_write[2]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4893 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4895 = _T_4893 & buf_write[3]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4896 = _T_2770 & _T_4880; // @[Mux.scala 27:72] + wire _T_4897 = _T_2792 & _T_4885; // @[Mux.scala 27:72] + wire _T_4898 = _T_2814 & _T_4890; // @[Mux.scala 27:72] + wire _T_4899 = _T_2836 & _T_4895; // @[Mux.scala 27:72] + wire _T_4900 = _T_4896 | _T_4897; // @[Mux.scala 27:72] + wire _T_4901 = _T_4900 | _T_4898; // @[Mux.scala 27:72] + wire _T_4911 = _T_2792 & buf_error[1]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4913 = _T_4911 & buf_write[1]; // @[lsu_bus_buffer.scala 611:108] + wire _T_4916 = _T_2814 & buf_error[2]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4918 = _T_4916 & buf_write[2]; // @[lsu_bus_buffer.scala 611:108] + wire _T_4921 = _T_2836 & buf_error[3]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4923 = _T_4921 & buf_write[3]; // @[lsu_bus_buffer.scala 611:108] + wire [1:0] _T_4926 = _T_4918 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4927 = _T_4923 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_396 = {{1'd0}, _T_4913}; // @[Mux.scala 27:72] + wire [1:0] _T_4929 = _GEN_396 | _T_4926; // @[Mux.scala 27:72] + wire [1:0] lsu_imprecise_error_store_tag = _T_4929 | _T_4927; // @[Mux.scala 27:72] + wire _T_4931 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 613:97] + wire [31:0] _GEN_369 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_370 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_369; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_371 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_370; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_373 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_374 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_373; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_375 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_374; // @[lsu_bus_buffer.scala 614:53] + wire _T_4936 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 620:82] + wire _T_4939 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 621:60] + wire _T_4942 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 624:61] + wire _T_4943 = io_lsu_axi_aw_valid & _T_4942; // @[lsu_bus_buffer.scala 624:59] + wire _T_4944 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 624:107] + wire _T_4945 = io_lsu_axi_w_valid & _T_4944; // @[lsu_bus_buffer.scala 624:105] + wire _T_4946 = _T_4943 | _T_4945; // @[lsu_bus_buffer.scala 624:83] + wire _T_4947 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 624:153] + wire _T_4948 = io_lsu_axi_ar_valid & _T_4947; // @[lsu_bus_buffer.scala 624:151] + wire _T_4952 = ~io_flush_r; // @[lsu_bus_buffer.scala 628:75] + wire _T_4953 = io_lsu_busreq_m & _T_4952; // @[lsu_bus_buffer.scala 628:73] + reg _T_4956; // @[lsu_bus_buffer.scala 628:56] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4936 | _T_4835; // @[lsu_bus_buffer.scala 620:35] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4939 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 621:41] + assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 622:36] + assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4946 | _T_4948; // @[lsu_bus_buffer.scala 624:35] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4931; // @[lsu_bus_buffer.scala 613:47] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4901 | _T_4899; // @[lsu_bus_buffer.scala 610:48] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_371 : _GEN_375; // @[lsu_bus_buffer.scala 614:47] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4512 & _T_4513; // @[lsu_bus_buffer.scala 541:45] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1802 ? 2'h0 : _T_1838; // @[lsu_bus_buffer.scala 542:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4515; // @[lsu_bus_buffer.scala 544:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 545:47] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4714; // @[lsu_bus_buffer.scala 557:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4561 | _T_4559; // @[lsu_bus_buffer.scala 547:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4601 | _T_4599; // @[lsu_bus_buffer.scala 548:45] + assign io_lsu_axi_aw_valid = 1'h0; // @[lsu_bus_buffer.scala 580:23] + assign io_lsu_axi_aw_bits_addr = {obuf_addr[31:3],3'h0}; // @[lsu_bus_buffer.scala 582:27] + assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 586:29] + assign io_lsu_axi_w_valid = 1'h0; // @[lsu_bus_buffer.scala 592:22] + assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 594:26] + assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 608:22] + assign io_lsu_axi_ar_valid = _T_1348 & _T_1237; // @[lsu_bus_buffer.scala 597:23] + assign io_lsu_axi_ar_bits_addr = {obuf_addr[31:3],3'h0}; // @[lsu_bus_buffer.scala 599:27] + assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 603:29] + assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 609:22] + assign io_lsu_busreq_r = _T_4956; // @[lsu_bus_buffer.scala 628:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 537:30] + assign io_lsu_bus_buffer_full_any = _T_4493 ? _T_4494 : _T_4495; // @[lsu_bus_buffer.scala 538:30] + assign io_lsu_bus_buffer_empty_any = _T_4506 & _T_1231; // @[lsu_bus_buffer.scala 539:31] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 142:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 143:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 169:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 175:24] + assign io_lsu_nonblock_load_data = _T_4749[31:0]; // @[lsu_bus_buffer.scala 558:29] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = _T_3531 & buf_state_en_0; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = _T_3722 & buf_state_en_1; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = _T_3913 & buf_state_en_2; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = _T_4104 & buf_state_en_3; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = _T_3531 ? buf_state_en_0 : _GEN_81; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = _T_3722 ? buf_state_en_1 : _GEN_157; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = _T_3913 ? buf_state_en_2 : _GEN_233; // @[lib.scala 407:17] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_11_io_en = _T_4104 ? buf_state_en_3 : _GEN_309; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_addr_0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_4355 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_4352 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_4349 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_4346 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + buf_state_0 = _RAND_5[2:0]; + _RAND_6 = {1{`RANDOM}}; + buf_addr_1 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + buf_state_1 = _RAND_7[2:0]; + _RAND_8 = {1{`RANDOM}}; + buf_addr_2 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + buf_state_2 = _RAND_9[2:0]; + _RAND_10 = {1{`RANDOM}}; + buf_addr_3 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + buf_state_3 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + buf_byteen_3 = _RAND_12[3:0]; + _RAND_13 = {1{`RANDOM}}; + buf_byteen_2 = _RAND_13[3:0]; + _RAND_14 = {1{`RANDOM}}; + buf_byteen_1 = _RAND_14[3:0]; + _RAND_15 = {1{`RANDOM}}; + buf_byteen_0 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + buf_ageQ_3 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + obuf_valid = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + ibuf_addr = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + ibuf_write = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + ibuf_valid = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + ibuf_byteen = _RAND_21[3:0]; + _RAND_22 = {1{`RANDOM}}; + buf_ageQ_2 = _RAND_22[3:0]; + _RAND_23 = {1{`RANDOM}}; + buf_ageQ_1 = _RAND_23[3:0]; + _RAND_24 = {1{`RANDOM}}; + buf_ageQ_0 = _RAND_24[3:0]; + _RAND_25 = {1{`RANDOM}}; + buf_data_0 = _RAND_25[31:0]; + _RAND_26 = {1{`RANDOM}}; + buf_data_1 = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + buf_data_2 = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + buf_data_3 = _RAND_28[31:0]; + _RAND_29 = {1{`RANDOM}}; + ibuf_data = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + ibuf_timer = _RAND_30[2:0]; + _RAND_31 = {1{`RANDOM}}; + ibuf_sideeffect = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + WrPtr1_r = _RAND_32[1:0]; + _RAND_33 = {1{`RANDOM}}; + WrPtr0_r = _RAND_33[1:0]; + _RAND_34 = {1{`RANDOM}}; + ibuf_tag = _RAND_34[1:0]; + _RAND_35 = {1{`RANDOM}}; + ibuf_dualtag = _RAND_35[1:0]; + _RAND_36 = {1{`RANDOM}}; + ibuf_dual = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + ibuf_samedw = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + ibuf_nomerge = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + ibuf_unsign = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + ibuf_sz = _RAND_40[1:0]; + _RAND_41 = {1{`RANDOM}}; + _T_1791 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + buf_nomerge_0 = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + buf_nomerge_1 = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + buf_nomerge_2 = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + buf_nomerge_3 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + _T_4325 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + _T_4322 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + _T_4319 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + _T_4316 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + buf_dual_3 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + buf_dual_2 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + buf_dual_1 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + buf_dual_0 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + buf_samedw_3 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + buf_samedw_2 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + buf_samedw_1 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + buf_samedw_0 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + obuf_nosend = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + obuf_addr = _RAND_59[31:0]; + _RAND_60 = {1{`RANDOM}}; + buf_sz_0 = _RAND_60[1:0]; + _RAND_61 = {1{`RANDOM}}; + buf_sz_1 = _RAND_61[1:0]; + _RAND_62 = {1{`RANDOM}}; + buf_sz_2 = _RAND_62[1:0]; + _RAND_63 = {1{`RANDOM}}; + buf_sz_3 = _RAND_63[1:0]; + _RAND_64 = {1{`RANDOM}}; + obuf_rdrsp_pend = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + buf_dualhi_3 = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + buf_dualhi_2 = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + buf_dualhi_1 = _RAND_67[0:0]; + _RAND_68 = {1{`RANDOM}}; + buf_dualhi_0 = _RAND_68[0:0]; + _RAND_69 = {2{`RANDOM}}; + obuf_data = _RAND_69[63:0]; + _RAND_70 = {1{`RANDOM}}; + buf_rspageQ_0 = _RAND_70[3:0]; + _RAND_71 = {1{`RANDOM}}; + buf_rspageQ_1 = _RAND_71[3:0]; + _RAND_72 = {1{`RANDOM}}; + buf_rspageQ_2 = _RAND_72[3:0]; + _RAND_73 = {1{`RANDOM}}; + buf_rspageQ_3 = _RAND_73[3:0]; + _RAND_74 = {1{`RANDOM}}; + _T_4302 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + _T_4300 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + _T_4298 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + _T_4296 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + buf_dualtag_0 = _RAND_78[1:0]; + _RAND_79 = {1{`RANDOM}}; + buf_dualtag_1 = _RAND_79[1:0]; + _RAND_80 = {1{`RANDOM}}; + buf_dualtag_2 = _RAND_80[1:0]; + _RAND_81 = {1{`RANDOM}}; + buf_dualtag_3 = _RAND_81[1:0]; + _RAND_82 = {1{`RANDOM}}; + _T_4331 = _RAND_82[0:0]; + _RAND_83 = {1{`RANDOM}}; + _T_4334 = _RAND_83[0:0]; + _RAND_84 = {1{`RANDOM}}; + _T_4337 = _RAND_84[0:0]; + _RAND_85 = {1{`RANDOM}}; + _T_4340 = _RAND_85[0:0]; + _RAND_86 = {1{`RANDOM}}; + _T_4406 = _RAND_86[0:0]; + _RAND_87 = {1{`RANDOM}}; + _T_4401 = _RAND_87[0:0]; + _RAND_88 = {1{`RANDOM}}; + _T_4396 = _RAND_88[0:0]; + _RAND_89 = {1{`RANDOM}}; + _T_4391 = _RAND_89[0:0]; + _RAND_90 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_90[0:0]; + _RAND_91 = {1{`RANDOM}}; + _T_4956 = _RAND_91[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_addr_0 = 32'h0; + end + if (reset) begin + _T_4355 = 1'h0; + end + if (reset) begin + _T_4352 = 1'h0; + end + if (reset) begin + _T_4349 = 1'h0; + end + if (reset) begin + _T_4346 = 1'h0; + end + if (reset) begin + buf_state_0 = 3'h0; + end + if (reset) begin + buf_addr_1 = 32'h0; + end + if (reset) begin + buf_state_1 = 3'h0; + end + if (reset) begin + buf_addr_2 = 32'h0; + end + if (reset) begin + buf_state_2 = 3'h0; + end + if (reset) begin + buf_addr_3 = 32'h0; + end + if (reset) begin + buf_state_3 = 3'h0; + end + if (reset) begin + buf_byteen_3 = 4'h0; + end + if (reset) begin + buf_byteen_2 = 4'h0; + end + if (reset) begin + buf_byteen_1 = 4'h0; + end + if (reset) begin + buf_byteen_0 = 4'h0; + end + if (reset) begin + buf_ageQ_3 = 4'h0; + end + if (reset) begin + obuf_valid = 1'h0; + end + if (reset) begin + ibuf_addr = 32'h0; + end + if (reset) begin + ibuf_write = 1'h0; + end + if (reset) begin + ibuf_valid = 1'h0; + end + if (reset) begin + ibuf_byteen = 4'h0; + end + if (reset) begin + buf_ageQ_2 = 4'h0; + end + if (reset) begin + buf_ageQ_1 = 4'h0; + end + if (reset) begin + buf_ageQ_0 = 4'h0; + end + if (reset) begin + buf_data_0 = 32'h0; + end + if (reset) begin + buf_data_1 = 32'h0; + end + if (reset) begin + buf_data_2 = 32'h0; + end + if (reset) begin + buf_data_3 = 32'h0; + end + if (reset) begin + ibuf_data = 32'h0; + end + if (reset) begin + ibuf_timer = 3'h0; + end + if (reset) begin + ibuf_sideeffect = 1'h0; + end + if (reset) begin + WrPtr1_r = 2'h0; + end + if (reset) begin + WrPtr0_r = 2'h0; + end + if (reset) begin + ibuf_tag = 2'h0; + end + if (reset) begin + ibuf_dualtag = 2'h0; + end + if (reset) begin + ibuf_dual = 1'h0; + end + if (reset) begin + ibuf_samedw = 1'h0; + end + if (reset) begin + ibuf_nomerge = 1'h0; + end + if (reset) begin + ibuf_unsign = 1'h0; + end + if (reset) begin + ibuf_sz = 2'h0; + end + if (reset) begin + _T_1791 = 1'h0; + end + if (reset) begin + buf_nomerge_0 = 1'h0; + end + if (reset) begin + buf_nomerge_1 = 1'h0; + end + if (reset) begin + buf_nomerge_2 = 1'h0; + end + if (reset) begin + buf_nomerge_3 = 1'h0; + end + if (reset) begin + _T_4325 = 1'h0; + end + if (reset) begin + _T_4322 = 1'h0; + end + if (reset) begin + _T_4319 = 1'h0; + end + if (reset) begin + _T_4316 = 1'h0; + end + if (reset) begin + buf_dual_3 = 1'h0; + end + if (reset) begin + buf_dual_2 = 1'h0; + end + if (reset) begin + buf_dual_1 = 1'h0; + end + if (reset) begin + buf_dual_0 = 1'h0; + end + if (reset) begin + buf_samedw_3 = 1'h0; + end + if (reset) begin + buf_samedw_2 = 1'h0; + end + if (reset) begin + buf_samedw_1 = 1'h0; + end + if (reset) begin + buf_samedw_0 = 1'h0; + end + if (reset) begin + obuf_nosend = 1'h0; + end + if (reset) begin + obuf_addr = 32'h0; + end + if (reset) begin + buf_sz_0 = 2'h0; + end + if (reset) begin + buf_sz_1 = 2'h0; + end + if (reset) begin + buf_sz_2 = 2'h0; + end + if (reset) begin + buf_sz_3 = 2'h0; + end + if (reset) begin + obuf_rdrsp_pend = 1'h0; + end + if (reset) begin + buf_dualhi_3 = 1'h0; + end + if (reset) begin + buf_dualhi_2 = 1'h0; + end + if (reset) begin + buf_dualhi_1 = 1'h0; + end + if (reset) begin + buf_dualhi_0 = 1'h0; + end + if (reset) begin + obuf_data = 64'h0; + end + if (reset) begin + buf_rspageQ_0 = 4'h0; + end + if (reset) begin + buf_rspageQ_1 = 4'h0; + end + if (reset) begin + buf_rspageQ_2 = 4'h0; + end + if (reset) begin + buf_rspageQ_3 = 4'h0; + end + if (reset) begin + _T_4302 = 1'h0; + end + if (reset) begin + _T_4300 = 1'h0; + end + if (reset) begin + _T_4298 = 1'h0; + end + if (reset) begin + _T_4296 = 1'h0; + end + if (reset) begin + buf_dualtag_0 = 2'h0; + end + if (reset) begin + buf_dualtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_2 = 2'h0; + end + if (reset) begin + buf_dualtag_3 = 2'h0; + end + if (reset) begin + _T_4331 = 1'h0; + end + if (reset) begin + _T_4334 = 1'h0; + end + if (reset) begin + _T_4337 = 1'h0; + end + if (reset) begin + _T_4340 = 1'h0; + end + if (reset) begin + _T_4406 = 1'h0; + end + if (reset) begin + _T_4401 = 1'h0; + end + if (reset) begin + _T_4396 = 1'h0; + end + if (reset) begin + _T_4391 = 1'h0; + end + if (reset) begin + lsu_nonblock_load_valid_r = 1'h0; + end + if (reset) begin + _T_4956 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_0 <= 32'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_addr_0 <= ibuf_addr; + end else if (_T_3346) begin + buf_addr_0 <= io_end_addr_r; + end else begin + buf_addr_0 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4355 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4355 <= buf_write_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4352 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4352 <= buf_write_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4349 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4349 <= buf_write_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4346 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4346 <= buf_write_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_0 <= 3'h0; + end else if (buf_state_en_0) begin + if (_T_3531) begin + if (io_lsu_bus_clk_en) begin + buf_state_0 <= 3'h2; + end else begin + buf_state_0 <= 3'h1; + end + end else if (_T_3554) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h2; + end + end else if (_T_3558) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3562) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h3; + end + end else if (_T_3592) begin + if (_T_3596) begin + buf_state_0 <= 3'h0; + end else if (_T_3604) begin + buf_state_0 <= 3'h4; + end else if (_T_3632) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3677) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3683) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3695) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h6; + end + end else begin + buf_state_0 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_1 <= 32'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_addr_1 <= ibuf_addr; + end else if (_T_3355) begin + buf_addr_1 <= io_end_addr_r; + end else begin + buf_addr_1 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_1 <= 3'h0; + end else if (buf_state_en_1) begin + if (_T_3722) begin + if (io_lsu_bus_clk_en) begin + buf_state_1 <= 3'h2; + end else begin + buf_state_1 <= 3'h1; + end + end else if (_T_3745) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h2; + end + end else if (_T_3749) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3562) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h3; + end + end else if (_T_3783) begin + if (_T_3787) begin + buf_state_1 <= 3'h0; + end else if (_T_3795) begin + buf_state_1 <= 3'h4; + end else if (_T_3823) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3868) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3874) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3886) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h6; + end + end else begin + buf_state_1 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_2 <= 32'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_addr_2 <= ibuf_addr; + end else if (_T_3364) begin + buf_addr_2 <= io_end_addr_r; + end else begin + buf_addr_2 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_2 <= 3'h0; + end else if (buf_state_en_2) begin + if (_T_3913) begin + if (io_lsu_bus_clk_en) begin + buf_state_2 <= 3'h2; + end else begin + buf_state_2 <= 3'h1; + end + end else if (_T_3936) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h2; + end + end else if (_T_3940) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3562) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h3; + end + end else if (_T_3974) begin + if (_T_3978) begin + buf_state_2 <= 3'h0; + end else if (_T_3986) begin + buf_state_2 <= 3'h4; + end else if (_T_4014) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4059) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_4065) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4077) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h6; + end + end else begin + buf_state_2 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_3 <= 32'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_addr_3 <= ibuf_addr; + end else if (_T_3373) begin + buf_addr_3 <= io_end_addr_r; + end else begin + buf_addr_3 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_3 <= 3'h0; + end else if (buf_state_en_3) begin + if (_T_4104) begin + if (io_lsu_bus_clk_en) begin + buf_state_3 <= 3'h2; + end else begin + buf_state_3 <= 3'h1; + end + end else if (_T_4127) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h2; + end + end else if (_T_4131) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_3562) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h3; + end + end else if (_T_4165) begin + if (_T_4169) begin + buf_state_3 <= 3'h0; + end else if (_T_4177) begin + buf_state_3 <= 3'h4; + end else if (_T_4205) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4250) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_4256) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4268) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h6; + end + end else begin + buf_state_3 <= 3'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_3 <= 4'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_byteen_3 <= ibuf_byteen_out; + end else if (_T_3373) begin + buf_byteen_3 <= ldst_byteen_hi_r; + end else begin + buf_byteen_3 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_2 <= 4'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_byteen_2 <= ibuf_byteen_out; + end else if (_T_3364) begin + buf_byteen_2 <= ldst_byteen_hi_r; + end else begin + buf_byteen_2 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_1 <= 4'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_byteen_1 <= ibuf_byteen_out; + end else if (_T_3355) begin + buf_byteen_1 <= ldst_byteen_hi_r; + end else begin + buf_byteen_1 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_0 <= 4'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_byteen_0 <= ibuf_byteen_out; + end else if (_T_3346) begin + buf_byteen_0 <= ldst_byteen_hi_r; + end else begin + buf_byteen_0 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_3 <= 4'h0; + end else begin + buf_ageQ_3 <= {_T_2474,_T_2397}; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_valid <= 1'h0; + end else begin + obuf_valid <= _T_1771 & _T_1772; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ibuf_addr <= 32'h0; + end else if (ibuf_wr_en) begin + if (io_ldst_dual_r) begin + ibuf_addr <= io_end_addr_r; + end else begin + ibuf_addr <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_write <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_write <= io_lsu_pkt_r_bits_store; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_valid <= 1'h0; + end else begin + ibuf_valid <= _T_1005 & _T_1006; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_byteen <= 4'h0; + end else if (ibuf_wr_en) begin + if (_T_866) begin + ibuf_byteen <= _T_881; + end else if (io_ldst_dual_r) begin + ibuf_byteen <= ldst_byteen_hi_r; + end else begin + ibuf_byteen <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_2 <= 4'h0; + end else begin + buf_ageQ_2 <= {_T_2372,_T_2295}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_1 <= 4'h0; + end else begin + buf_ageQ_1 <= {_T_2270,_T_2193}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_0 <= 4'h0; + end else begin + buf_ageQ_0 <= {_T_2168,_T_2091}; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_0 <= 32'h0; + end else if (buf_data_en_0) begin + if (_T_3531) begin + if (_T_3546) begin + buf_data_0 <= ibuf_data_out; + end else begin + buf_data_0 <= store_data_lo_r; + end + end else if (_T_3554) begin + buf_data_0 <= 32'h0; + end else if (_T_3558) begin + if (buf_error_en_0) begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3592) begin + if (_T_3670) begin + if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_1 <= 32'h0; + end else if (buf_data_en_1) begin + if (_T_3722) begin + if (_T_3737) begin + buf_data_1 <= ibuf_data_out; + end else begin + buf_data_1 <= store_data_lo_r; + end + end else if (_T_3745) begin + buf_data_1 <= 32'h0; + end else if (_T_3749) begin + if (buf_error_en_1) begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3783) begin + if (_T_3861) begin + if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_2 <= 32'h0; + end else if (buf_data_en_2) begin + if (_T_3913) begin + if (_T_3928) begin + buf_data_2 <= ibuf_data_out; + end else begin + buf_data_2 <= store_data_lo_r; + end + end else if (_T_3936) begin + buf_data_2 <= 32'h0; + end else if (_T_3940) begin + if (buf_error_en_2) begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3974) begin + if (_T_4052) begin + if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_3 <= 32'h0; + end else if (buf_data_en_3) begin + if (_T_4104) begin + if (_T_4119) begin + buf_data_3 <= ibuf_data_out; + end else begin + buf_data_3 <= store_data_lo_r; + end + end else if (_T_4127) begin + buf_data_3 <= 32'h0; + end else if (_T_4131) begin + if (buf_error_en_3) begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_4165) begin + if (_T_4243) begin + if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ibuf_data <= 32'h0; + end else if (ibuf_wr_en) begin + ibuf_data <= ibuf_data_in; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_923) begin + ibuf_timer <= _T_926; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sideeffect <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_sideeffect <= io_is_sideeffects_r; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr1_r <= 2'h0; + end else if (_T_1853) begin + WrPtr1_r <= 2'h0; + end else if (_T_1867) begin + WrPtr1_r <= 2'h1; + end else if (_T_1881) begin + WrPtr1_r <= 2'h2; + end else begin + WrPtr1_r <= 2'h3; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr0_r <= 2'h0; + end else if (_T_1802) begin + WrPtr0_r <= 2'h0; + end else if (_T_1813) begin + WrPtr0_r <= 2'h1; + end else if (_T_1824) begin + WrPtr0_r <= 2'h2; + end else begin + WrPtr0_r <= 2'h3; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_tag <= 2'h0; + end else if (ibuf_wr_en) begin + if (!(_T_866)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dualtag <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_dualtag <= WrPtr0_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dual <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_dual <= io_ldst_dual_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_samedw <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_samedw <= ldst_samedw_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_nomerge <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_nomerge <= io_no_dword_merge_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_unsign <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_unsign <= io_lsu_pkt_r_bits_unsign; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sz <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_sz <= ibuf_sz_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1791 <= 1'h0; + end else if (obuf_wr_en) begin + _T_1791 <= obuf_data_done_in; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_nomerge_0 <= buf_nomerge_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_nomerge_1 <= buf_nomerge_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_nomerge_2 <= buf_nomerge_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_nomerge_3 <= buf_nomerge_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4325 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4325 <= buf_sideeffect_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4322 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4322 <= buf_sideeffect_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4319 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4319 <= buf_sideeffect_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4316 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4316 <= buf_sideeffect_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dual_3 <= buf_dual_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dual_2 <= buf_dual_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dual_1 <= buf_dual_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dual_0 <= buf_dual_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_samedw_3 <= buf_samedw_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_samedw_2 <= buf_samedw_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_samedw_1 <= buf_samedw_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_samedw_0 <= buf_samedw_in[0]; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_nosend <= 1'h0; + end else if (obuf_wr_en) begin + obuf_nosend <= obuf_nosend_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_addr <= 32'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_addr <= io_lsu_addr_r; + end else begin + obuf_addr <= _T_1287; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_sz_0 <= ibuf_sz; + end else begin + buf_sz_0 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_sz_1 <= ibuf_sz; + end else begin + buf_sz_1 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_sz_2 <= ibuf_sz; + end else begin + buf_sz_2 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_sz_3 <= ibuf_sz; + end else begin + buf_sz_3 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_pend <= 1'h0; + end else if (obuf_rdrsp_pend_en) begin + obuf_rdrsp_pend <= obuf_rdrsp_pend_in; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dualhi_3 <= buf_dualhi_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dualhi_2 <= buf_dualhi_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dualhi_1 <= buf_dualhi_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dualhi_0 <= buf_dualhi_in[0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_data <= 64'h0; + end else if (obuf_wr_en) begin + obuf_data <= obuf_data_in; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_0 <= 4'h0; + end else begin + buf_rspageQ_0 <= {_T_3144,_T_3133}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_1 <= 4'h0; + end else begin + buf_rspageQ_1 <= {_T_3159,_T_3148}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_2 <= 4'h0; + end else begin + buf_rspageQ_2 <= {_T_3174,_T_3163}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_3 <= 4'h0; + end else begin + buf_rspageQ_3 <= {_T_3189,_T_3178}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4302 <= 1'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4104) begin + _T_4302 <= 1'h0; + end else if (_T_4127) begin + _T_4302 <= 1'h0; + end else begin + _T_4302 <= _T_4131; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4300 <= 1'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3913) begin + _T_4300 <= 1'h0; + end else if (_T_3936) begin + _T_4300 <= 1'h0; + end else begin + _T_4300 <= _T_3940; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4298 <= 1'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3722) begin + _T_4298 <= 1'h0; + end else if (_T_3745) begin + _T_4298 <= 1'h0; + end else begin + _T_4298 <= _T_3749; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4296 <= 1'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3531) begin + _T_4296 <= 1'h0; + end else if (_T_3554) begin + _T_4296 <= 1'h0; + end else begin + _T_4296 <= _T_3558; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_dualtag_0 <= ibuf_dualtag; + end else if (_T_3346) begin + buf_dualtag_0 <= WrPtr0_r; + end else begin + buf_dualtag_0 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_dualtag_1 <= ibuf_dualtag; + end else if (_T_3355) begin + buf_dualtag_1 <= WrPtr0_r; + end else begin + buf_dualtag_1 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_dualtag_2 <= ibuf_dualtag; + end else if (_T_3364) begin + buf_dualtag_2 <= WrPtr0_r; + end else begin + buf_dualtag_2 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_dualtag_3 <= ibuf_dualtag; + end else if (_T_3373) begin + buf_dualtag_3 <= WrPtr0_r; + end else begin + buf_dualtag_3 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4331 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4331 <= buf_unsign_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4334 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4334 <= buf_unsign_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4337 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4337 <= buf_unsign_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4340 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4340 <= buf_unsign_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4406 <= 1'h0; + end else begin + _T_4406 <= _T_4402 & _T_4404; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4401 <= 1'h0; + end else begin + _T_4401 <= _T_4397 & _T_4399; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4396 <= 1'h0; + end else begin + _T_4396 <= _T_4392 & _T_4394; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4391 <= 1'h0; + end else begin + _T_4391 <= _T_4387 & _T_4389; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_nonblock_load_valid_r <= 1'h0; + end else begin + lsu_nonblock_load_valid_r <= io_dctl_busbuff_lsu_nonblock_load_valid_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_4956 <= 1'h0; + end else begin + _T_4956 <= _T_4953 & _T_4513; + end + end +endmodule +module lsu_bus_intf( + input clock, + input reset, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + input io_lsu_c1_r_clk, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_active_clk, + input io_axi_aw_ready, + output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, + input io_axi_w_ready, + output [63:0] io_axi_w_bits_data, + input io_axi_b_valid, + input [1:0] io_axi_b_bits_resp, + input [2:0] io_axi_b_bits_id, + input io_axi_ar_ready, + output io_axi_ar_valid, + output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, + input io_axi_r_valid, + input [2:0] io_axi_r_bits_id, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + input io_dec_lsu_valid_raw_d, + input io_lsu_busreq_m, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input [31:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_m, + input [31:0] io_end_addr_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [31:0] io_store_data_r, + input io_dec_tlu_force_halt, + input io_lsu_commit_r, + input io_is_sideeffects_m, + input io_flush_m_up, + input io_flush_r, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [31:0] io_bus_read_data_m, + output [31:0] io_lsu_nonblock_load_data, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + input io_lsu_bus_clk_en +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire bus_buffer_clock; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_reset; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_store_data_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_word_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_dword_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ld_full_hit_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_m_up; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_commit_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_is_sideeffects_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 100:39] + wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 100:39] + wire [3:0] _T_3 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_4 = io_lsu_pkt_m_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_5 = io_lsu_pkt_m_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72] + wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[lsu_bus_intf.scala 155:51] + wire _T_14 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[lsu_bus_intf.scala 156:71] + wire _T_15 = ~_T_14; // @[lsu_bus_intf.scala 156:53] + wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_15; // @[lsu_bus_intf.scala 156:51] + wire _T_17 = ~io_ldst_dual_r; // @[lsu_bus_intf.scala 157:48] + wire _T_18 = io_lsu_busreq_r & _T_17; // @[lsu_bus_intf.scala 157:46] + wire _T_19 = _T_18 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 157:64] + wire _T_20 = ~addr_match_word_lo_r_m; // @[lsu_bus_intf.scala 157:110] + wire _T_21 = io_lsu_pkt_m_bits_load | _T_20; // @[lsu_bus_intf.scala 157:108] + wire _T_26 = ~addr_match_dw_lo_r_m; // @[lsu_bus_intf.scala 158:110] + wire _T_27 = io_lsu_pkt_m_bits_load | _T_26; // @[lsu_bus_intf.scala 158:108] + wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[lsu_bus_intf.scala 160:49] + wire [6:0] _T_31 = _GEN_0 << io_lsu_addr_m[1:0]; // @[lsu_bus_intf.scala 160:49] + reg [3:0] ldst_byteen_r; // @[lsu_bus_intf.scala 200:33] + wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[lsu_bus_intf.scala 161:49] + wire [6:0] _T_34 = _GEN_1 << io_lsu_addr_r[1:0]; // @[lsu_bus_intf.scala 161:49] + wire [4:0] _T_37 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58] + wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[lsu_bus_intf.scala 162:52] + wire [62:0] _T_38 = _GEN_2 << _T_37; // @[lsu_bus_intf.scala 162:52] + wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 160:27] + wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[lsu_bus_intf.scala 163:47] + wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[lsu_bus_intf.scala 164:47] + wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 161:27] + wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[lsu_bus_intf.scala 165:47] + wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[lsu_bus_intf.scala 166:47] + wire [63:0] store_data_ext_r = {{1'd0}, _T_38}; // @[lsu_bus_intf.scala 162:27] + wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[lsu_bus_intf.scala 168:46] + wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[lsu_bus_intf.scala 169:46] + wire _T_47 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 170:51] + wire _T_48 = _T_47 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 170:76] + wire _T_49 = _T_48 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 170:97] + wire ld_addr_rhit_lo_lo = _T_49 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 170:123] + wire _T_53 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 171:51] + wire _T_54 = _T_53 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 171:76] + wire _T_55 = _T_54 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 171:97] + wire ld_addr_rhit_lo_hi = _T_55 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 171:123] + wire _T_59 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 172:51] + wire _T_60 = _T_59 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 172:76] + wire _T_61 = _T_60 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 172:97] + wire ld_addr_rhit_hi_lo = _T_61 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 172:123] + wire _T_65 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 173:51] + wire _T_66 = _T_65 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 173:76] + wire _T_67 = _T_66 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 173:97] + wire ld_addr_rhit_hi_hi = _T_67 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 173:123] + wire _T_70 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 175:70] + wire _T_72 = _T_70 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 175:92] + wire _T_74 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 175:70] + wire _T_76 = _T_74 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 175:92] + wire _T_78 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 175:70] + wire _T_80 = _T_78 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 175:92] + wire _T_82 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 175:70] + wire _T_84 = _T_82 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 175:92] + wire [3:0] ld_byte_rhit_lo_lo = {_T_84,_T_80,_T_76,_T_72}; // @[Cat.scala 29:58] + wire _T_89 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 176:70] + wire _T_91 = _T_89 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 176:92] + wire _T_93 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 176:70] + wire _T_95 = _T_93 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 176:92] + wire _T_97 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 176:70] + wire _T_99 = _T_97 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 176:92] + wire _T_101 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 176:70] + wire _T_103 = _T_101 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 176:92] + wire [3:0] ld_byte_rhit_lo_hi = {_T_103,_T_99,_T_95,_T_91}; // @[Cat.scala 29:58] + wire _T_108 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 177:70] + wire _T_110 = _T_108 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 177:92] + wire _T_112 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 177:70] + wire _T_114 = _T_112 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 177:92] + wire _T_116 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 177:70] + wire _T_118 = _T_116 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 177:92] + wire _T_120 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 177:70] + wire _T_122 = _T_120 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 177:92] + wire [3:0] ld_byte_rhit_hi_lo = {_T_122,_T_118,_T_114,_T_110}; // @[Cat.scala 29:58] + wire _T_127 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 178:70] + wire _T_129 = _T_127 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 178:92] + wire _T_131 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 178:70] + wire _T_133 = _T_131 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 178:92] + wire _T_135 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 178:70] + wire _T_137 = _T_135 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 178:92] + wire _T_139 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 178:70] + wire _T_141 = _T_139 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 178:92] + wire [3:0] ld_byte_rhit_hi_hi = {_T_141,_T_137,_T_133,_T_129}; // @[Cat.scala 29:58] + wire _T_147 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_bus_intf.scala 180:73] + wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 139:38] + wire _T_149 = _T_147 | ld_byte_hit_buf_lo[0]; // @[lsu_bus_intf.scala 180:97] + wire _T_152 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_bus_intf.scala 180:73] + wire _T_154 = _T_152 | ld_byte_hit_buf_lo[1]; // @[lsu_bus_intf.scala 180:97] + wire _T_157 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_bus_intf.scala 180:73] + wire _T_159 = _T_157 | ld_byte_hit_buf_lo[2]; // @[lsu_bus_intf.scala 180:97] + wire _T_162 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_bus_intf.scala 180:73] + wire _T_164 = _T_162 | ld_byte_hit_buf_lo[3]; // @[lsu_bus_intf.scala 180:97] + wire [3:0] ld_byte_hit_lo = {_T_164,_T_159,_T_154,_T_149}; // @[Cat.scala 29:58] + wire _T_170 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_bus_intf.scala 181:73] + wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 140:38] + wire _T_172 = _T_170 | ld_byte_hit_buf_hi[0]; // @[lsu_bus_intf.scala 181:97] + wire _T_175 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_bus_intf.scala 181:73] + wire _T_177 = _T_175 | ld_byte_hit_buf_hi[1]; // @[lsu_bus_intf.scala 181:97] + wire _T_180 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_bus_intf.scala 181:73] + wire _T_182 = _T_180 | ld_byte_hit_buf_hi[2]; // @[lsu_bus_intf.scala 181:97] + wire _T_185 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_bus_intf.scala 181:73] + wire _T_187 = _T_185 | ld_byte_hit_buf_hi[3]; // @[lsu_bus_intf.scala 181:97] + wire [3:0] ld_byte_hit_hi = {_T_187,_T_182,_T_177,_T_172}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_lo = {_T_162,_T_157,_T_152,_T_147}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_hi = {_T_185,_T_180,_T_175,_T_170}; // @[Cat.scala 29:58] + wire [7:0] _T_225 = ld_byte_rhit_lo_lo[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_226 = ld_byte_rhit_hi_lo[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_227 = _T_225 | _T_226; // @[Mux.scala 27:72] + wire [7:0] _T_233 = ld_byte_rhit_lo_lo[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_234 = ld_byte_rhit_hi_lo[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_235 = _T_233 | _T_234; // @[Mux.scala 27:72] + wire [7:0] _T_241 = ld_byte_rhit_lo_lo[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_242 = ld_byte_rhit_hi_lo[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_243 = _T_241 | _T_242; // @[Mux.scala 27:72] + wire [7:0] _T_249 = ld_byte_rhit_lo_lo[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_250 = ld_byte_rhit_hi_lo[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_251 = _T_249 | _T_250; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_lo = {_T_251,_T_243,_T_235,_T_227}; // @[Cat.scala 29:58] + wire [7:0] _T_260 = ld_byte_rhit_lo_hi[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_261 = ld_byte_rhit_hi_hi[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_262 = _T_260 | _T_261; // @[Mux.scala 27:72] + wire [7:0] _T_268 = ld_byte_rhit_lo_hi[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_269 = ld_byte_rhit_hi_hi[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_270 = _T_268 | _T_269; // @[Mux.scala 27:72] + wire [7:0] _T_276 = ld_byte_rhit_lo_hi[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_277 = ld_byte_rhit_hi_hi[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_278 = _T_276 | _T_277; // @[Mux.scala 27:72] + wire [7:0] _T_284 = ld_byte_rhit_lo_hi[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_285 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_286 = _T_284 | _T_285; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_hi = {_T_286,_T_278,_T_270,_T_262}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 141:38] + wire [7:0] _T_294 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_298 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_302 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_306 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[lsu_bus_intf.scala 186:54] + wire [31:0] _T_309 = {_T_306,_T_302,_T_298,_T_294}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 142:38] + wire [7:0] _T_313 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_317 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_321 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_325 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[lsu_bus_intf.scala 187:54] + wire [31:0] _T_328 = {_T_325,_T_321,_T_317,_T_313}; // @[Cat.scala 29:58] + wire _T_331 = ~ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 188:72] + wire _T_332 = ld_byte_hit_lo[0] | _T_331; // @[lsu_bus_intf.scala 188:70] + wire _T_335 = ~ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 188:72] + wire _T_336 = ld_byte_hit_lo[1] | _T_335; // @[lsu_bus_intf.scala 188:70] + wire _T_339 = ~ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 188:72] + wire _T_340 = ld_byte_hit_lo[2] | _T_339; // @[lsu_bus_intf.scala 188:70] + wire _T_343 = ~ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 188:72] + wire _T_344 = ld_byte_hit_lo[3] | _T_343; // @[lsu_bus_intf.scala 188:70] + wire _T_345 = _T_332 & _T_336; // @[lsu_bus_intf.scala 188:111] + wire _T_346 = _T_345 & _T_340; // @[lsu_bus_intf.scala 188:111] + wire ld_full_hit_lo_m = _T_346 & _T_344; // @[lsu_bus_intf.scala 188:111] + wire _T_350 = ~ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 189:72] + wire _T_351 = ld_byte_hit_hi[0] | _T_350; // @[lsu_bus_intf.scala 189:70] + wire _T_354 = ~ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 189:72] + wire _T_355 = ld_byte_hit_hi[1] | _T_354; // @[lsu_bus_intf.scala 189:70] + wire _T_358 = ~ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 189:72] + wire _T_359 = ld_byte_hit_hi[2] | _T_358; // @[lsu_bus_intf.scala 189:70] + wire _T_362 = ~ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 189:72] + wire _T_363 = ld_byte_hit_hi[3] | _T_362; // @[lsu_bus_intf.scala 189:70] + wire _T_364 = _T_351 & _T_355; // @[lsu_bus_intf.scala 189:111] + wire _T_365 = _T_364 & _T_359; // @[lsu_bus_intf.scala 189:111] + wire ld_full_hit_hi_m = _T_365 & _T_363; // @[lsu_bus_intf.scala 189:111] + wire _T_367 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[lsu_bus_intf.scala 190:47] + wire _T_368 = _T_367 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 190:66] + wire _T_369 = _T_368 & io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 190:84] + wire _T_370 = ~io_is_sideeffects_m; // @[lsu_bus_intf.scala 190:111] + wire [63:0] ld_fwddata_hi = {{32'd0}, _T_328}; // @[lsu_bus_intf.scala 187:27] + wire [63:0] ld_fwddata_lo = {{32'd0}, _T_309}; // @[lsu_bus_intf.scala 186:27] + wire [63:0] _T_374 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58] + wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_bus_intf.scala 191:83] + wire [5:0] _T_376 = 4'h8 * _GEN_3; // @[lsu_bus_intf.scala 191:83] + wire [63:0] ld_fwddata_m = _T_374 >> _T_376; // @[lsu_bus_intf.scala 191:76] + reg lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 195:32] + reg is_sideeffects_r; // @[lsu_bus_intf.scala 199:33] + lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 100:39] + .clock(bus_buffer_clock), + .reset(bus_buffer_reset), + .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn), + .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned), + .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), + .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), + .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), + .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), + .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), + .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), + .io_tlu_busbuff_lsu_imprecise_error_addr_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any), + .io_dctl_busbuff_lsu_nonblock_load_valid_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m), + .io_dctl_busbuff_lsu_nonblock_load_tag_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m), + .io_dctl_busbuff_lsu_nonblock_load_inv_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r), + .io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r), + .io_dctl_busbuff_lsu_nonblock_load_data_valid(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid), + .io_dctl_busbuff_lsu_nonblock_load_data_error(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error), + .io_dctl_busbuff_lsu_nonblock_load_data_tag(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag), + .io_dec_tlu_force_halt(bus_buffer_io_dec_tlu_force_halt), + .io_lsu_c2_r_clk(bus_buffer_io_lsu_c2_r_clk), + .io_lsu_bus_ibuf_c1_clk(bus_buffer_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_buf_c1_clk(bus_buffer_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(bus_buffer_io_lsu_free_c2_clk), + .io_dec_lsu_valid_raw_d(bus_buffer_io_dec_lsu_valid_raw_d), + .io_lsu_pkt_m_valid(bus_buffer_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_load(bus_buffer_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_r_bits_by(bus_buffer_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(bus_buffer_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(bus_buffer_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(bus_buffer_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(bus_buffer_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(bus_buffer_io_lsu_pkt_r_bits_unsign), + .io_lsu_addr_m(bus_buffer_io_lsu_addr_m), + .io_end_addr_m(bus_buffer_io_end_addr_m), + .io_lsu_addr_r(bus_buffer_io_lsu_addr_r), + .io_end_addr_r(bus_buffer_io_end_addr_r), + .io_store_data_r(bus_buffer_io_store_data_r), + .io_no_word_merge_r(bus_buffer_io_no_word_merge_r), + .io_no_dword_merge_r(bus_buffer_io_no_dword_merge_r), + .io_lsu_busreq_m(bus_buffer_io_lsu_busreq_m), + .io_ld_full_hit_m(bus_buffer_io_ld_full_hit_m), + .io_flush_m_up(bus_buffer_io_flush_m_up), + .io_flush_r(bus_buffer_io_flush_r), + .io_lsu_commit_r(bus_buffer_io_lsu_commit_r), + .io_is_sideeffects_r(bus_buffer_io_is_sideeffects_r), + .io_ldst_dual_d(bus_buffer_io_ldst_dual_d), + .io_ldst_dual_m(bus_buffer_io_ldst_dual_m), + .io_ldst_dual_r(bus_buffer_io_ldst_dual_r), + .io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m), + .io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready), + .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), + .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region), + .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), + .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), + .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), + .io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready), + .io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid), + .io_lsu_axi_b_bits_resp(bus_buffer_io_lsu_axi_b_bits_resp), + .io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id), + .io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready), + .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), + .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region), + .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), + .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), + .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), + .io_lsu_axi_r_bits_data(bus_buffer_io_lsu_axi_r_bits_data), + .io_lsu_axi_r_bits_resp(bus_buffer_io_lsu_axi_r_bits_resp), + .io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en), + .io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q), + .io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(bus_buffer_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_full_any(bus_buffer_io_lsu_bus_buffer_full_any), + .io_lsu_bus_buffer_empty_any(bus_buffer_io_lsu_bus_buffer_empty_any), + .io_ld_byte_hit_buf_lo(bus_buffer_io_ld_byte_hit_buf_lo), + .io_ld_byte_hit_buf_hi(bus_buffer_io_ld_byte_hit_buf_hi), + .io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo), + .io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi), + .io_lsu_nonblock_load_data(bus_buffer_io_lsu_nonblock_load_data) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 103:18] + assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 131:51] + assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 131:51] + assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 134:38] + assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 135:38] + assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 136:38] + assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 137:38] + assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 192:27] + assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 133:29] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 143:19] + assign bus_buffer_clock = clock; + assign bus_buffer_reset = reset; + assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 107:51] + assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 108:51] + assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 109:51] + assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 111:51] + assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 112:51] + assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 114:51] + assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 117:27] + assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 117:27] + assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 121:51] + assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 122:51] + assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 123:51] + assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 124:51] + assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 125:51] + assign bus_buffer_io_no_word_merge_r = _T_19 & _T_21; // @[lsu_bus_intf.scala 144:51] + assign bus_buffer_io_no_dword_merge_r = _T_19 & _T_27; // @[lsu_bus_intf.scala 145:51] + assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 127:51] + assign bus_buffer_io_ld_full_hit_m = _T_369 & _T_370; // @[lsu_bus_intf.scala 151:51] + assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 128:51] + assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 129:51] + assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 130:51] + assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 146:51] + assign bus_buffer_io_ldst_dual_d = io_ldst_dual_d; // @[lsu_bus_intf.scala 147:51] + assign bus_buffer_io_ldst_dual_m = io_ldst_dual_m; // @[lsu_bus_intf.scala 148:51] + assign bus_buffer_io_ldst_dual_r = io_ldst_dual_r; // @[lsu_bus_intf.scala 149:51] + assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 150:51] + assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 132:51] + assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 152:51] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + ldst_byteen_r = _RAND_0[3:0]; + _RAND_1 = {1{`RANDOM}}; + lsu_bus_clk_en_q = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + is_sideeffects_r = _RAND_2[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + ldst_byteen_r = 4'h0; + end + if (reset) begin + lsu_bus_clk_en_q = 1'h0; + end + if (reset) begin + is_sideeffects_r = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + ldst_byteen_r <= 4'h0; + end else begin + ldst_byteen_r <= _T_6 | _T_5; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + lsu_bus_clk_en_q <= 1'h0; + end else begin + lsu_bus_clk_en_q <= io_lsu_bus_clk_en; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + is_sideeffects_r <= 1'h0; + end else begin + is_sideeffects_r <= io_is_sideeffects_m; + end + end +endmodule +module lsu( + input clock, + input reset, + input io_clk_override, + input io_lsu_dma_dma_lsc_ctl_dma_dccm_req, + input [31:0] io_lsu_dma_dma_lsc_ctl_dma_mem_addr, + input [2:0] io_lsu_dma_dma_lsc_ctl_dma_mem_sz, + input io_lsu_dma_dma_lsc_ctl_dma_mem_write, + input [63:0] io_lsu_dma_dma_lsc_ctl_dma_mem_wdata, + input [31:0] io_lsu_dma_dma_dccm_ctl_dma_mem_addr, + input [63:0] io_lsu_dma_dma_dccm_ctl_dma_mem_wdata, + output io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid, + output io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error, + output [2:0] io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag, + output [63:0] io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata, + output io_lsu_dma_dccm_ready, + input [2:0] io_lsu_dma_dma_mem_tag, + output io_lsu_pic_picm_wren, + output io_lsu_pic_picm_rden, + output io_lsu_pic_picm_mken, + output [31:0] io_lsu_pic_picm_rdaddr, + output [31:0] io_lsu_pic_picm_wraddr, + output [31:0] io_lsu_pic_picm_wr_data, + input [31:0] io_lsu_pic_picm_rd_data, + input [31:0] io_lsu_exu_exu_lsu_rs1_d, + input [31:0] io_lsu_exu_exu_lsu_rs2_d, + output [31:0] io_lsu_exu_lsu_result_m, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, + input io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, + output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag, + output io_dccm_wren, + output io_dccm_rden, + output [15:0] io_dccm_wr_addr_lo, + output [15:0] io_dccm_wr_addr_hi, + output [15:0] io_dccm_rd_addr_lo, + output [15:0] io_dccm_rd_addr_hi, + output [38:0] io_dccm_wr_data_lo, + output [38:0] io_dccm_wr_data_hi, + input [38:0] io_dccm_rd_data_lo, + input [38:0] io_dccm_rd_data_hi, + output io_lsu_tlu_lsu_pmu_load_external_m, + output io_lsu_tlu_lsu_pmu_store_external_m, + input io_axi_aw_ready, + output io_axi_aw_valid, + output [2:0] io_axi_aw_bits_id, + output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, + output [7:0] io_axi_aw_bits_len, + output [2:0] io_axi_aw_bits_size, + output [1:0] io_axi_aw_bits_burst, + output io_axi_aw_bits_lock, + output [3:0] io_axi_aw_bits_cache, + output [2:0] io_axi_aw_bits_prot, + output [3:0] io_axi_aw_bits_qos, + input io_axi_w_ready, + output io_axi_w_valid, + output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, + output io_axi_w_bits_last, + output io_axi_b_ready, + input io_axi_b_valid, + input [1:0] io_axi_b_bits_resp, + input [2:0] io_axi_b_bits_id, + input io_axi_ar_ready, + output io_axi_ar_valid, + output [2:0] io_axi_ar_bits_id, + output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, + output [7:0] io_axi_ar_bits_len, + output [2:0] io_axi_ar_bits_size, + output [1:0] io_axi_ar_bits_burst, + output io_axi_ar_bits_lock, + output [3:0] io_axi_ar_bits_cache, + output [2:0] io_axi_ar_bits_prot, + output [3:0] io_axi_ar_bits_qos, + output io_axi_r_ready, + input io_axi_r_valid, + input [2:0] io_axi_r_bits_id, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + input io_axi_r_bits_last, + input io_dec_tlu_flush_lower_r, + input io_dec_tlu_i0_kill_writeb_r, + input io_dec_tlu_force_halt, + input io_dec_tlu_core_ecc_disable, + input [11:0] io_dec_lsu_offset_d, + input io_lsu_p_valid, + input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_stack, + input io_lsu_p_bits_by, + input io_lsu_p_bits_half, + input io_lsu_p_bits_word, + input io_lsu_p_bits_dword, + input io_lsu_p_bits_load, + input io_lsu_p_bits_store, + input io_lsu_p_bits_unsign, + input io_lsu_p_bits_dma, + input io_lsu_p_bits_store_data_bypass_d, + input io_lsu_p_bits_load_ldst_bypass_d, + input io_lsu_p_bits_store_data_bypass_m, + input io_trigger_pkt_any_0_select, + input io_trigger_pkt_any_0_match_pkt, + input io_trigger_pkt_any_0_store, + input io_trigger_pkt_any_0_load, + input io_trigger_pkt_any_0_execute, + input io_trigger_pkt_any_0_m, + input [31:0] io_trigger_pkt_any_0_tdata2, + input io_trigger_pkt_any_1_select, + input io_trigger_pkt_any_1_match_pkt, + input io_trigger_pkt_any_1_store, + input io_trigger_pkt_any_1_load, + input io_trigger_pkt_any_1_execute, + input io_trigger_pkt_any_1_m, + input [31:0] io_trigger_pkt_any_1_tdata2, + input io_trigger_pkt_any_2_select, + input io_trigger_pkt_any_2_match_pkt, + input io_trigger_pkt_any_2_store, + input io_trigger_pkt_any_2_load, + input io_trigger_pkt_any_2_execute, + input io_trigger_pkt_any_2_m, + input [31:0] io_trigger_pkt_any_2_tdata2, + input io_trigger_pkt_any_3_select, + input io_trigger_pkt_any_3_match_pkt, + input io_trigger_pkt_any_3_store, + input io_trigger_pkt_any_3_load, + input io_trigger_pkt_any_3_execute, + input io_trigger_pkt_any_3_m, + input [31:0] io_trigger_pkt_any_3_tdata2, + input io_dec_lsu_valid_raw_d, + input [31:0] io_dec_tlu_mrac_ff, + output [31:0] io_lsu_result_corr_r, + output io_lsu_load_stall_any, + output io_lsu_store_stall_any, + output io_lsu_fastint_stall_any, + output io_lsu_idle_any, + output io_lsu_active, + output [30:0] io_lsu_fir_addr, + output [1:0] io_lsu_fir_error, + output io_lsu_single_ecc_error_incr, + output io_lsu_error_pkt_r_valid, + output io_lsu_error_pkt_r_bits_single_ecc_error, + output io_lsu_error_pkt_r_bits_inst_type, + output io_lsu_error_pkt_r_bits_exc_type, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, + output io_lsu_pmu_misaligned_m, + output [3:0] io_lsu_trigger_match_m, + input io_lsu_bus_clk_en, + input io_scan_mode, + input io_active_clk, + output [31:0] io_lsu_nonblock_load_data +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire lsu_lsc_ctl_clock; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_reset; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_clk_override; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_c1_m_clk; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_c1_r_clk; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_c2_m_clk; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_c2_r_clk; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_store_c1_m_clk; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_double_ecc_error_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_flush_m_up; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_flush_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_ldst_dual_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_exu_lsu_result_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_valid; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_fast_int; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_by; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_half; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_word; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_dword; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_load; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_store; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_unsign; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_dma; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_dec_lsu_valid_raw_d; // @[lsu.scala 72:30] + wire [11:0] lsu_lsc_ctl_io_dec_lsu_offset_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_picm_mask_data_m; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_bus_read_data_m; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_dec_tlu_mrac_ff; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 72:30] + wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 72:30] + wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 72:30] + wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 72:30] + wire [2:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 72:30] + wire [63:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_by; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_half; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_dword; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 72:30] + wire dccm_ctl_clock; // @[lsu.scala 76:30] + wire dccm_ctl_reset; // @[lsu.scala 76:30] + wire dccm_ctl_io_clk_override; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_c2_m_clk; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_free_c2_clk; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_store_c1_r_clk; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_dccm_d; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_dccm_m; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_dccm_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_pic_d; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_pic_m; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_pic_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_raw_fwd_lo_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_raw_fwd_hi_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_commit_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_ldst_dual_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_addr_d; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_lsu_addr_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_addr_r; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_end_addr_d; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_end_addr_m; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_end_addr_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_stbuf_reqvld_any; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_stbuf_addr_any; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_stbuf_data_any; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_stbuf_ecc_any; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_stbuf_fwddata_hi_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_stbuf_fwddata_lo_m; // @[lsu.scala 76:30] + wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 76:30] + wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_single_ecc_error_hi_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_single_ecc_error_lo_r; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_sec_data_hi_r_ff; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_sec_data_lo_r_ff; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_ld_data_m; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_double_ecc_error_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_sec_data_hi_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_sec_data_lo_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_data_m; // @[lsu.scala 76:30] + wire dccm_ctl_io_dma_dccm_wen; // @[lsu.scala 76:30] + wire dccm_ctl_io_dma_pic_wen; // @[lsu.scala 76:30] + wire [2:0] dccm_ctl_io_dma_mem_tag_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_dma_dccm_wdata_lo; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_dma_dccm_wdata_hi; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_data_hi_r; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_data_lo_r; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_data_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 76:30] + wire [63:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 76:30] + wire dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 76:30] + wire dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 76:30] + wire [2:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 76:30] + wire [63:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 76:30] + wire dccm_ctl_io_dccm_wren; // @[lsu.scala 76:30] + wire dccm_ctl_io_dccm_rden; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 76:30] + wire [38:0] dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 76:30] + wire [38:0] dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 76:30] + wire [38:0] dccm_ctl_io_dccm_rd_data_lo; // @[lsu.scala 76:30] + wire [38:0] dccm_ctl_io_dccm_rd_data_hi; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_rd_data; // @[lsu.scala 76:30] + wire stbuf_clock; // @[lsu.scala 77:30] + wire stbuf_reset; // @[lsu.scala 77:30] + wire stbuf_io_lsu_stbuf_c1_clk; // @[lsu.scala 77:30] + wire stbuf_io_lsu_free_c2_clk; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_m_valid; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_m_bits_store; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_m_bits_dma; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_valid; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_by; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_half; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_word; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_dword; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_store; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_dma; // @[lsu.scala 77:30] + wire stbuf_io_store_stbuf_reqvld_r; // @[lsu.scala 77:30] + wire stbuf_io_lsu_commit_r; // @[lsu.scala 77:30] + wire stbuf_io_dec_lsu_valid_raw_d; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_store_data_hi_r; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_store_data_lo_r; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_store_datafn_hi_r; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_store_datafn_lo_r; // @[lsu.scala 77:30] + wire stbuf_io_lsu_stbuf_commit_any; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_lsu_addr_m; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_lsu_addr_r; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_end_addr_m; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_end_addr_r; // @[lsu.scala 77:30] + wire stbuf_io_ldst_dual_d; // @[lsu.scala 77:30] + wire stbuf_io_ldst_dual_m; // @[lsu.scala 77:30] + wire stbuf_io_ldst_dual_r; // @[lsu.scala 77:30] + wire stbuf_io_addr_in_dccm_m; // @[lsu.scala 77:30] + wire stbuf_io_addr_in_dccm_r; // @[lsu.scala 77:30] + wire stbuf_io_stbuf_reqvld_any; // @[lsu.scala 77:30] + wire stbuf_io_stbuf_reqvld_flushed_any; // @[lsu.scala 77:30] + wire [15:0] stbuf_io_stbuf_addr_any; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_stbuf_data_any; // @[lsu.scala 77:30] + wire stbuf_io_lsu_stbuf_full_any; // @[lsu.scala 77:30] + wire stbuf_io_ldst_stbuf_reqvld_r; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 77:30] + wire [3:0] stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 77:30] + wire [3:0] stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 77:30] + wire ecc_clock; // @[lsu.scala 78:30] + wire ecc_reset; // @[lsu.scala 78:30] + wire ecc_io_lsu_c2_r_clk; // @[lsu.scala 78:30] + wire ecc_io_clk_override; // @[lsu.scala 78:30] + wire ecc_io_lsu_pkt_m_valid; // @[lsu.scala 78:30] + wire ecc_io_lsu_pkt_m_bits_load; // @[lsu.scala 78:30] + wire ecc_io_lsu_pkt_m_bits_store; // @[lsu.scala 78:30] + wire ecc_io_lsu_pkt_m_bits_dma; // @[lsu.scala 78:30] + wire [31:0] ecc_io_stbuf_data_any; // @[lsu.scala 78:30] + wire ecc_io_dec_tlu_core_ecc_disable; // @[lsu.scala 78:30] + wire [15:0] ecc_io_lsu_addr_m; // @[lsu.scala 78:30] + wire [15:0] ecc_io_end_addr_m; // @[lsu.scala 78:30] + wire [31:0] ecc_io_dccm_rdata_hi_m; // @[lsu.scala 78:30] + wire [31:0] ecc_io_dccm_rdata_lo_m; // @[lsu.scala 78:30] + wire [6:0] ecc_io_dccm_data_ecc_hi_m; // @[lsu.scala 78:30] + wire [6:0] ecc_io_dccm_data_ecc_lo_m; // @[lsu.scala 78:30] + wire ecc_io_ld_single_ecc_error_r; // @[lsu.scala 78:30] + wire ecc_io_ld_single_ecc_error_r_ff; // @[lsu.scala 78:30] + wire ecc_io_lsu_dccm_rden_m; // @[lsu.scala 78:30] + wire ecc_io_addr_in_dccm_m; // @[lsu.scala 78:30] + wire ecc_io_dma_dccm_wen; // @[lsu.scala 78:30] + wire [31:0] ecc_io_dma_dccm_wdata_lo; // @[lsu.scala 78:30] + wire [31:0] ecc_io_dma_dccm_wdata_hi; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_hi_r; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_lo_r; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_hi_m; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_lo_m; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_hi_r_ff; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_lo_r_ff; // @[lsu.scala 78:30] + wire [6:0] ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 78:30] + wire [6:0] ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 78:30] + wire [6:0] ecc_io_stbuf_ecc_any; // @[lsu.scala 78:30] + wire [6:0] ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 78:30] + wire [6:0] ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 78:30] + wire ecc_io_single_ecc_error_hi_r; // @[lsu.scala 78:30] + wire ecc_io_single_ecc_error_lo_r; // @[lsu.scala 78:30] + wire ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 78:30] + wire ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 78:30] + wire ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 78:30] + wire ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 78:30] + wire trigger_io_trigger_pkt_any_0_select; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_0_store; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_0_load; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_0_m; // @[lsu.scala 79:30] + wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_1_select; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_1_store; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_1_load; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_1_m; // @[lsu.scala 79:30] + wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_2_select; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_2_store; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_2_load; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_2_m; // @[lsu.scala 79:30] + wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_3_select; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_3_store; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_3_load; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_3_m; // @[lsu.scala 79:30] + wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_valid; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_bits_half; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_bits_word; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_bits_load; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_bits_store; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_bits_dma; // @[lsu.scala 79:30] + wire [31:0] trigger_io_lsu_addr_m; // @[lsu.scala 79:30] + wire [31:0] trigger_io_store_data_m; // @[lsu.scala 79:30] + wire [3:0] trigger_io_lsu_trigger_match_m; // @[lsu.scala 79:30] + wire clkdomain_clock; // @[lsu.scala 80:30] + wire clkdomain_io_clk_override; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_busreq_r; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_buffer_pend_any; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_buffer_empty_any; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_clk_en; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_obuf_c1_clken; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_busm_clken; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 80:30] + wire bus_intf_clock; // @[lsu.scala 81:30] + wire bus_intf_reset; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_c1_r_clk; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_c2_r_clk; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_buf_c1_clk; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_free_c2_clk; // @[lsu.scala 81:30] + wire bus_intf_io_active_clk; // @[lsu.scala 81:30] + wire bus_intf_io_axi_aw_ready; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 81:30] + wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 81:30] + wire bus_intf_io_axi_w_ready; // @[lsu.scala 81:30] + wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 81:30] + wire bus_intf_io_axi_b_valid; // @[lsu.scala 81:30] + wire [1:0] bus_intf_io_axi_b_bits_resp; // @[lsu.scala 81:30] + wire [2:0] bus_intf_io_axi_b_bits_id; // @[lsu.scala 81:30] + wire bus_intf_io_axi_ar_ready; // @[lsu.scala 81:30] + wire bus_intf_io_axi_ar_valid; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 81:30] + wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 81:30] + wire bus_intf_io_axi_r_valid; // @[lsu.scala 81:30] + wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 81:30] + wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 81:30] + wire [1:0] bus_intf_io_axi_r_bits_resp; // @[lsu.scala 81:30] + wire bus_intf_io_dec_lsu_valid_raw_d; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_busreq_m; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_m_valid; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_m_bits_by; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_m_bits_half; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_m_bits_word; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_m_bits_load; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_valid; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_by; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_half; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_word; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_load; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_store; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_lsu_addr_m; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_lsu_addr_r; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_end_addr_m; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_end_addr_r; // @[lsu.scala 81:30] + wire bus_intf_io_ldst_dual_d; // @[lsu.scala 81:30] + wire bus_intf_io_ldst_dual_m; // @[lsu.scala 81:30] + wire bus_intf_io_ldst_dual_r; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_store_data_r; // @[lsu.scala 81:30] + wire bus_intf_io_dec_tlu_force_halt; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_commit_r; // @[lsu.scala 81:30] + wire bus_intf_io_is_sideeffects_m; // @[lsu.scala 81:30] + wire bus_intf_io_flush_m_up; // @[lsu.scala 81:30] + wire bus_intf_io_flush_r; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_busreq_r; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_bus_read_data_m; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_lsu_nonblock_load_data; // @[lsu.scala 81:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 81:30] + wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 81:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 81:30] + wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 81:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 81:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 81:30] + wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_clk_en; // @[lsu.scala 81:30] + wire _T = stbuf_io_lsu_stbuf_full_any | bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 87:57] + wire _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 94:58] + wire _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[lsu.scala 94:56] + wire _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 94:126] + wire _T_6 = _T_4 & _T_5; // @[lsu.scala 94:93] + wire ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 94:158] + wire _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[lsu.scala 95:53] + wire _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 95:71] + wire _T_10 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 96:58] + wire _T_11 = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 96:97] + wire [5:0] _T_15 = {io_lsu_dma_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] + wire [63:0] dma_dccm_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata >> _T_15; // @[lsu.scala 98:58] + wire _T_21 = ~lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 109:130] + wire _T_22 = lsu_lsc_ctl_io_lsu_pkt_r_valid & _T_21; // @[lsu.scala 109:128] + wire _T_23 = _T_4 | _T_22; // @[lsu.scala 109:94] + wire _T_24 = ~_T_23; // @[lsu.scala 109:22] + wire _T_26 = lsu_lsc_ctl_io_lsu_pkt_m_valid | lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 110:53] + wire _T_27 = _T_26 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 110:86] + wire _T_28 = ~bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 110:128] + wire _T_30 = lsu_lsc_ctl_io_lsu_pkt_r_valid & lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 112:61] + wire _T_31 = _T_30 & lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 112:99] + wire _T_32 = ~io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 112:133] + wire _T_33 = _T_31 & _T_32; // @[lsu.scala 112:131] + wire _T_35 = lsu_lsc_ctl_io_lsu_pkt_r_bits_by | lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 112:217] + wire _T_36 = ~ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 112:257] + wire _T_37 = _T_35 & _T_36; // @[lsu.scala 112:255] + wire _T_38 = _T_21 | _T_37; // @[lsu.scala 112:180] + wire _T_39 = lsu_lsc_ctl_io_lsu_pkt_m_bits_load | lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 114:90] + wire _T_43 = _T_39 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 116:131] + wire _T_44 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_43; // @[lsu.scala 116:53] + wire _T_45 = ~io_dec_tlu_flush_lower_r; // @[lsu.scala 116:167] + wire _T_46 = _T_44 & _T_45; // @[lsu.scala 116:165] + wire _T_47 = ~lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 116:181] + wire _T_48 = _T_46 & _T_47; // @[lsu.scala 116:179] + wire _T_49 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 116:209] + wire _T_51 = lsu_lsc_ctl_io_lsu_pkt_m_bits_half & lsu_lsc_ctl_io_lsu_addr_m[0]; // @[lsu.scala 120:100] + wire _T_53 = |lsu_lsc_ctl_io_lsu_addr_m[1:0]; // @[lsu.scala 120:203] + wire _T_54 = lsu_lsc_ctl_io_lsu_pkt_m_bits_word & _T_53; // @[lsu.scala 120:170] + wire _T_55 = _T_51 | _T_54; // @[lsu.scala 120:132] + wire _T_57 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 121:73] + wire _T_59 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 122:73] + wire _T_98 = lsu_lsc_ctl_io_addr_external_m & lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 333:119] + wire [31:0] _T_100 = _T_98 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 348:16] + wire [31:0] _T_103 = lsu_busreq_r ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + reg [2:0] dma_mem_tag_m; // @[lsu.scala 352:67] + reg lsu_raw_fwd_hi_r; // @[lsu.scala 353:67] + reg lsu_raw_fwd_lo_r; // @[lsu.scala 354:67] + lsu_lsc_ctl lsu_lsc_ctl ( // @[lsu.scala 72:30] + .clock(lsu_lsc_ctl_clock), + .reset(lsu_lsc_ctl_reset), + .io_clk_override(lsu_lsc_ctl_io_clk_override), + .io_lsu_c1_m_clk(lsu_lsc_ctl_io_lsu_c1_m_clk), + .io_lsu_c1_r_clk(lsu_lsc_ctl_io_lsu_c1_r_clk), + .io_lsu_c2_m_clk(lsu_lsc_ctl_io_lsu_c2_m_clk), + .io_lsu_c2_r_clk(lsu_lsc_ctl_io_lsu_c2_r_clk), + .io_lsu_store_c1_m_clk(lsu_lsc_ctl_io_lsu_store_c1_m_clk), + .io_lsu_ld_data_corr_r(lsu_lsc_ctl_io_lsu_ld_data_corr_r), + .io_lsu_single_ecc_error_r(lsu_lsc_ctl_io_lsu_single_ecc_error_r), + .io_lsu_double_ecc_error_r(lsu_lsc_ctl_io_lsu_double_ecc_error_r), + .io_lsu_ld_data_m(lsu_lsc_ctl_io_lsu_ld_data_m), + .io_lsu_single_ecc_error_m(lsu_lsc_ctl_io_lsu_single_ecc_error_m), + .io_lsu_double_ecc_error_m(lsu_lsc_ctl_io_lsu_double_ecc_error_m), + .io_flush_m_up(lsu_lsc_ctl_io_flush_m_up), + .io_flush_r(lsu_lsc_ctl_io_flush_r), + .io_ldst_dual_d(lsu_lsc_ctl_io_ldst_dual_d), + .io_lsu_exu_exu_lsu_rs1_d(lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d), + .io_lsu_exu_exu_lsu_rs2_d(lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d), + .io_lsu_exu_lsu_result_m(lsu_lsc_ctl_io_lsu_exu_lsu_result_m), + .io_lsu_p_valid(lsu_lsc_ctl_io_lsu_p_valid), + .io_lsu_p_bits_fast_int(lsu_lsc_ctl_io_lsu_p_bits_fast_int), + .io_lsu_p_bits_by(lsu_lsc_ctl_io_lsu_p_bits_by), + .io_lsu_p_bits_half(lsu_lsc_ctl_io_lsu_p_bits_half), + .io_lsu_p_bits_word(lsu_lsc_ctl_io_lsu_p_bits_word), + .io_lsu_p_bits_dword(lsu_lsc_ctl_io_lsu_p_bits_dword), + .io_lsu_p_bits_load(lsu_lsc_ctl_io_lsu_p_bits_load), + .io_lsu_p_bits_store(lsu_lsc_ctl_io_lsu_p_bits_store), + .io_lsu_p_bits_unsign(lsu_lsc_ctl_io_lsu_p_bits_unsign), + .io_lsu_p_bits_dma(lsu_lsc_ctl_io_lsu_p_bits_dma), + .io_lsu_p_bits_store_data_bypass_d(lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d), + .io_lsu_p_bits_load_ldst_bypass_d(lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d), + .io_lsu_p_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m), + .io_dec_lsu_valid_raw_d(lsu_lsc_ctl_io_dec_lsu_valid_raw_d), + .io_dec_lsu_offset_d(lsu_lsc_ctl_io_dec_lsu_offset_d), + .io_picm_mask_data_m(lsu_lsc_ctl_io_picm_mask_data_m), + .io_bus_read_data_m(lsu_lsc_ctl_io_bus_read_data_m), + .io_lsu_result_corr_r(lsu_lsc_ctl_io_lsu_result_corr_r), + .io_lsu_addr_d(lsu_lsc_ctl_io_lsu_addr_d), + .io_lsu_addr_m(lsu_lsc_ctl_io_lsu_addr_m), + .io_lsu_addr_r(lsu_lsc_ctl_io_lsu_addr_r), + .io_end_addr_d(lsu_lsc_ctl_io_end_addr_d), + .io_end_addr_m(lsu_lsc_ctl_io_end_addr_m), + .io_end_addr_r(lsu_lsc_ctl_io_end_addr_r), + .io_store_data_m(lsu_lsc_ctl_io_store_data_m), + .io_dec_tlu_mrac_ff(lsu_lsc_ctl_io_dec_tlu_mrac_ff), + .io_lsu_exc_m(lsu_lsc_ctl_io_lsu_exc_m), + .io_is_sideeffects_m(lsu_lsc_ctl_io_is_sideeffects_m), + .io_lsu_commit_r(lsu_lsc_ctl_io_lsu_commit_r), + .io_lsu_single_ecc_error_incr(lsu_lsc_ctl_io_lsu_single_ecc_error_incr), + .io_lsu_error_pkt_r_valid(lsu_lsc_ctl_io_lsu_error_pkt_r_valid), + .io_lsu_error_pkt_r_bits_single_ecc_error(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error), + .io_lsu_error_pkt_r_bits_inst_type(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type), + .io_lsu_error_pkt_r_bits_exc_type(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type), + .io_lsu_error_pkt_r_bits_mscause(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause), + .io_lsu_error_pkt_r_bits_addr(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr), + .io_lsu_fir_addr(lsu_lsc_ctl_io_lsu_fir_addr), + .io_lsu_fir_error(lsu_lsc_ctl_io_lsu_fir_error), + .io_addr_in_dccm_d(lsu_lsc_ctl_io_addr_in_dccm_d), + .io_addr_in_dccm_m(lsu_lsc_ctl_io_addr_in_dccm_m), + .io_addr_in_dccm_r(lsu_lsc_ctl_io_addr_in_dccm_r), + .io_addr_in_pic_d(lsu_lsc_ctl_io_addr_in_pic_d), + .io_addr_in_pic_m(lsu_lsc_ctl_io_addr_in_pic_m), + .io_addr_in_pic_r(lsu_lsc_ctl_io_addr_in_pic_r), + .io_addr_external_m(lsu_lsc_ctl_io_addr_external_m), + .io_dma_lsc_ctl_dma_dccm_req(lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req), + .io_dma_lsc_ctl_dma_mem_addr(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr), + .io_dma_lsc_ctl_dma_mem_sz(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz), + .io_dma_lsc_ctl_dma_mem_write(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write), + .io_dma_lsc_ctl_dma_mem_wdata(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata), + .io_lsu_pkt_d_valid(lsu_lsc_ctl_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int), + .io_lsu_pkt_d_bits_by(lsu_lsc_ctl_io_lsu_pkt_d_bits_by), + .io_lsu_pkt_d_bits_half(lsu_lsc_ctl_io_lsu_pkt_d_bits_half), + .io_lsu_pkt_d_bits_word(lsu_lsc_ctl_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_dword(lsu_lsc_ctl_io_lsu_pkt_d_bits_dword), + .io_lsu_pkt_d_bits_load(lsu_lsc_ctl_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(lsu_lsc_ctl_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign), + .io_lsu_pkt_d_bits_dma(lsu_lsc_ctl_io_lsu_pkt_d_bits_dma), + .io_lsu_pkt_d_bits_store_data_bypass_d(lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d), + .io_lsu_pkt_d_bits_load_ldst_bypass_d(lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d), + .io_lsu_pkt_d_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m), + .io_lsu_pkt_m_valid(lsu_lsc_ctl_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int), + .io_lsu_pkt_m_bits_by(lsu_lsc_ctl_io_lsu_pkt_m_bits_by), + .io_lsu_pkt_m_bits_half(lsu_lsc_ctl_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(lsu_lsc_ctl_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_dword(lsu_lsc_ctl_io_lsu_pkt_m_bits_dword), + .io_lsu_pkt_m_bits_load(lsu_lsc_ctl_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(lsu_lsc_ctl_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign), + .io_lsu_pkt_m_bits_dma(lsu_lsc_ctl_io_lsu_pkt_m_bits_dma), + .io_lsu_pkt_m_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m), + .io_lsu_pkt_r_valid(lsu_lsc_ctl_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(lsu_lsc_ctl_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(lsu_lsc_ctl_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(lsu_lsc_ctl_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_dword(lsu_lsc_ctl_io_lsu_pkt_r_bits_dword), + .io_lsu_pkt_r_bits_load(lsu_lsc_ctl_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(lsu_lsc_ctl_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign), + .io_lsu_pkt_r_bits_dma(lsu_lsc_ctl_io_lsu_pkt_r_bits_dma) + ); + lsu_dccm_ctl dccm_ctl ( // @[lsu.scala 76:30] + .clock(dccm_ctl_clock), + .reset(dccm_ctl_reset), + .io_clk_override(dccm_ctl_io_clk_override), + .io_lsu_c2_m_clk(dccm_ctl_io_lsu_c2_m_clk), + .io_lsu_free_c2_clk(dccm_ctl_io_lsu_free_c2_clk), + .io_lsu_store_c1_r_clk(dccm_ctl_io_lsu_store_c1_r_clk), + .io_lsu_pkt_d_valid(dccm_ctl_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_word(dccm_ctl_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_dword(dccm_ctl_io_lsu_pkt_d_bits_dword), + .io_lsu_pkt_d_bits_load(dccm_ctl_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(dccm_ctl_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_dma(dccm_ctl_io_lsu_pkt_d_bits_dma), + .io_lsu_pkt_m_valid(dccm_ctl_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_by(dccm_ctl_io_lsu_pkt_m_bits_by), + .io_lsu_pkt_m_bits_half(dccm_ctl_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(dccm_ctl_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_load(dccm_ctl_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(dccm_ctl_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(dccm_ctl_io_lsu_pkt_m_bits_dma), + .io_lsu_pkt_r_valid(dccm_ctl_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(dccm_ctl_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(dccm_ctl_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(dccm_ctl_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(dccm_ctl_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(dccm_ctl_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_dma(dccm_ctl_io_lsu_pkt_r_bits_dma), + .io_addr_in_dccm_d(dccm_ctl_io_addr_in_dccm_d), + .io_addr_in_dccm_m(dccm_ctl_io_addr_in_dccm_m), + .io_addr_in_dccm_r(dccm_ctl_io_addr_in_dccm_r), + .io_addr_in_pic_d(dccm_ctl_io_addr_in_pic_d), + .io_addr_in_pic_m(dccm_ctl_io_addr_in_pic_m), + .io_addr_in_pic_r(dccm_ctl_io_addr_in_pic_r), + .io_lsu_raw_fwd_lo_r(dccm_ctl_io_lsu_raw_fwd_lo_r), + .io_lsu_raw_fwd_hi_r(dccm_ctl_io_lsu_raw_fwd_hi_r), + .io_lsu_commit_r(dccm_ctl_io_lsu_commit_r), + .io_ldst_dual_m(dccm_ctl_io_ldst_dual_m), + .io_lsu_addr_d(dccm_ctl_io_lsu_addr_d), + .io_lsu_addr_m(dccm_ctl_io_lsu_addr_m), + .io_lsu_addr_r(dccm_ctl_io_lsu_addr_r), + .io_end_addr_d(dccm_ctl_io_end_addr_d), + .io_end_addr_m(dccm_ctl_io_end_addr_m), + .io_end_addr_r(dccm_ctl_io_end_addr_r), + .io_stbuf_reqvld_any(dccm_ctl_io_stbuf_reqvld_any), + .io_stbuf_addr_any(dccm_ctl_io_stbuf_addr_any), + .io_stbuf_data_any(dccm_ctl_io_stbuf_data_any), + .io_stbuf_ecc_any(dccm_ctl_io_stbuf_ecc_any), + .io_stbuf_fwddata_hi_m(dccm_ctl_io_stbuf_fwddata_hi_m), + .io_stbuf_fwddata_lo_m(dccm_ctl_io_stbuf_fwddata_lo_m), + .io_stbuf_fwdbyteen_lo_m(dccm_ctl_io_stbuf_fwdbyteen_lo_m), + .io_stbuf_fwdbyteen_hi_m(dccm_ctl_io_stbuf_fwdbyteen_hi_m), + .io_lsu_ld_data_corr_r(dccm_ctl_io_lsu_ld_data_corr_r), + .io_lsu_double_ecc_error_r(dccm_ctl_io_lsu_double_ecc_error_r), + .io_single_ecc_error_hi_r(dccm_ctl_io_single_ecc_error_hi_r), + .io_single_ecc_error_lo_r(dccm_ctl_io_single_ecc_error_lo_r), + .io_sec_data_hi_r_ff(dccm_ctl_io_sec_data_hi_r_ff), + .io_sec_data_lo_r_ff(dccm_ctl_io_sec_data_lo_r_ff), + .io_sec_data_ecc_hi_r_ff(dccm_ctl_io_sec_data_ecc_hi_r_ff), + .io_sec_data_ecc_lo_r_ff(dccm_ctl_io_sec_data_ecc_lo_r_ff), + .io_dccm_rdata_hi_m(dccm_ctl_io_dccm_rdata_hi_m), + .io_dccm_rdata_lo_m(dccm_ctl_io_dccm_rdata_lo_m), + .io_dccm_data_ecc_hi_m(dccm_ctl_io_dccm_data_ecc_hi_m), + .io_dccm_data_ecc_lo_m(dccm_ctl_io_dccm_data_ecc_lo_m), + .io_lsu_ld_data_m(dccm_ctl_io_lsu_ld_data_m), + .io_lsu_double_ecc_error_m(dccm_ctl_io_lsu_double_ecc_error_m), + .io_sec_data_hi_m(dccm_ctl_io_sec_data_hi_m), + .io_sec_data_lo_m(dccm_ctl_io_sec_data_lo_m), + .io_store_data_m(dccm_ctl_io_store_data_m), + .io_dma_dccm_wen(dccm_ctl_io_dma_dccm_wen), + .io_dma_pic_wen(dccm_ctl_io_dma_pic_wen), + .io_dma_mem_tag_m(dccm_ctl_io_dma_mem_tag_m), + .io_dma_dccm_wdata_lo(dccm_ctl_io_dma_dccm_wdata_lo), + .io_dma_dccm_wdata_hi(dccm_ctl_io_dma_dccm_wdata_hi), + .io_dma_dccm_wdata_ecc_hi(dccm_ctl_io_dma_dccm_wdata_ecc_hi), + .io_dma_dccm_wdata_ecc_lo(dccm_ctl_io_dma_dccm_wdata_ecc_lo), + .io_store_data_hi_r(dccm_ctl_io_store_data_hi_r), + .io_store_data_lo_r(dccm_ctl_io_store_data_lo_r), + .io_store_datafn_hi_r(dccm_ctl_io_store_datafn_hi_r), + .io_store_datafn_lo_r(dccm_ctl_io_store_datafn_lo_r), + .io_store_data_r(dccm_ctl_io_store_data_r), + .io_ld_single_ecc_error_r(dccm_ctl_io_ld_single_ecc_error_r), + .io_ld_single_ecc_error_r_ff(dccm_ctl_io_ld_single_ecc_error_r_ff), + .io_picm_mask_data_m(dccm_ctl_io_picm_mask_data_m), + .io_lsu_stbuf_commit_any(dccm_ctl_io_lsu_stbuf_commit_any), + .io_lsu_dccm_rden_m(dccm_ctl_io_lsu_dccm_rden_m), + .io_dma_dccm_ctl_dma_mem_addr(dccm_ctl_io_dma_dccm_ctl_dma_mem_addr), + .io_dma_dccm_ctl_dma_mem_wdata(dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata), + .io_dma_dccm_ctl_dccm_dma_rvalid(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid), + .io_dma_dccm_ctl_dccm_dma_ecc_error(dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error), + .io_dma_dccm_ctl_dccm_dma_rtag(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag), + .io_dma_dccm_ctl_dccm_dma_rdata(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata), + .io_dccm_wren(dccm_ctl_io_dccm_wren), + .io_dccm_rden(dccm_ctl_io_dccm_rden), + .io_dccm_wr_addr_lo(dccm_ctl_io_dccm_wr_addr_lo), + .io_dccm_wr_addr_hi(dccm_ctl_io_dccm_wr_addr_hi), + .io_dccm_rd_addr_lo(dccm_ctl_io_dccm_rd_addr_lo), + .io_dccm_rd_addr_hi(dccm_ctl_io_dccm_rd_addr_hi), + .io_dccm_wr_data_lo(dccm_ctl_io_dccm_wr_data_lo), + .io_dccm_wr_data_hi(dccm_ctl_io_dccm_wr_data_hi), + .io_dccm_rd_data_lo(dccm_ctl_io_dccm_rd_data_lo), + .io_dccm_rd_data_hi(dccm_ctl_io_dccm_rd_data_hi), + .io_lsu_pic_picm_wren(dccm_ctl_io_lsu_pic_picm_wren), + .io_lsu_pic_picm_rden(dccm_ctl_io_lsu_pic_picm_rden), + .io_lsu_pic_picm_mken(dccm_ctl_io_lsu_pic_picm_mken), + .io_lsu_pic_picm_rdaddr(dccm_ctl_io_lsu_pic_picm_rdaddr), + .io_lsu_pic_picm_wraddr(dccm_ctl_io_lsu_pic_picm_wraddr), + .io_lsu_pic_picm_wr_data(dccm_ctl_io_lsu_pic_picm_wr_data), + .io_lsu_pic_picm_rd_data(dccm_ctl_io_lsu_pic_picm_rd_data) + ); + lsu_stbuf stbuf ( // @[lsu.scala 77:30] + .clock(stbuf_clock), + .reset(stbuf_reset), + .io_lsu_stbuf_c1_clk(stbuf_io_lsu_stbuf_c1_clk), + .io_lsu_free_c2_clk(stbuf_io_lsu_free_c2_clk), + .io_lsu_pkt_m_valid(stbuf_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_store(stbuf_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(stbuf_io_lsu_pkt_m_bits_dma), + .io_lsu_pkt_r_valid(stbuf_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(stbuf_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(stbuf_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(stbuf_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_dword(stbuf_io_lsu_pkt_r_bits_dword), + .io_lsu_pkt_r_bits_store(stbuf_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_dma(stbuf_io_lsu_pkt_r_bits_dma), + .io_store_stbuf_reqvld_r(stbuf_io_store_stbuf_reqvld_r), + .io_lsu_commit_r(stbuf_io_lsu_commit_r), + .io_dec_lsu_valid_raw_d(stbuf_io_dec_lsu_valid_raw_d), + .io_store_data_hi_r(stbuf_io_store_data_hi_r), + .io_store_data_lo_r(stbuf_io_store_data_lo_r), + .io_store_datafn_hi_r(stbuf_io_store_datafn_hi_r), + .io_store_datafn_lo_r(stbuf_io_store_datafn_lo_r), + .io_lsu_stbuf_commit_any(stbuf_io_lsu_stbuf_commit_any), + .io_lsu_addr_m(stbuf_io_lsu_addr_m), + .io_lsu_addr_r(stbuf_io_lsu_addr_r), + .io_end_addr_m(stbuf_io_end_addr_m), + .io_end_addr_r(stbuf_io_end_addr_r), + .io_ldst_dual_d(stbuf_io_ldst_dual_d), + .io_ldst_dual_m(stbuf_io_ldst_dual_m), + .io_ldst_dual_r(stbuf_io_ldst_dual_r), + .io_addr_in_dccm_m(stbuf_io_addr_in_dccm_m), + .io_addr_in_dccm_r(stbuf_io_addr_in_dccm_r), + .io_stbuf_reqvld_any(stbuf_io_stbuf_reqvld_any), + .io_stbuf_reqvld_flushed_any(stbuf_io_stbuf_reqvld_flushed_any), + .io_stbuf_addr_any(stbuf_io_stbuf_addr_any), + .io_stbuf_data_any(stbuf_io_stbuf_data_any), + .io_lsu_stbuf_full_any(stbuf_io_lsu_stbuf_full_any), + .io_ldst_stbuf_reqvld_r(stbuf_io_ldst_stbuf_reqvld_r), + .io_stbuf_fwddata_hi_m(stbuf_io_stbuf_fwddata_hi_m), + .io_stbuf_fwddata_lo_m(stbuf_io_stbuf_fwddata_lo_m), + .io_stbuf_fwdbyteen_hi_m(stbuf_io_stbuf_fwdbyteen_hi_m), + .io_stbuf_fwdbyteen_lo_m(stbuf_io_stbuf_fwdbyteen_lo_m) + ); + lsu_ecc ecc ( // @[lsu.scala 78:30] + .clock(ecc_clock), + .reset(ecc_reset), + .io_lsu_c2_r_clk(ecc_io_lsu_c2_r_clk), + .io_clk_override(ecc_io_clk_override), + .io_lsu_pkt_m_valid(ecc_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_load(ecc_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(ecc_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(ecc_io_lsu_pkt_m_bits_dma), + .io_stbuf_data_any(ecc_io_stbuf_data_any), + .io_dec_tlu_core_ecc_disable(ecc_io_dec_tlu_core_ecc_disable), + .io_lsu_addr_m(ecc_io_lsu_addr_m), + .io_end_addr_m(ecc_io_end_addr_m), + .io_dccm_rdata_hi_m(ecc_io_dccm_rdata_hi_m), + .io_dccm_rdata_lo_m(ecc_io_dccm_rdata_lo_m), + .io_dccm_data_ecc_hi_m(ecc_io_dccm_data_ecc_hi_m), + .io_dccm_data_ecc_lo_m(ecc_io_dccm_data_ecc_lo_m), + .io_ld_single_ecc_error_r(ecc_io_ld_single_ecc_error_r), + .io_ld_single_ecc_error_r_ff(ecc_io_ld_single_ecc_error_r_ff), + .io_lsu_dccm_rden_m(ecc_io_lsu_dccm_rden_m), + .io_addr_in_dccm_m(ecc_io_addr_in_dccm_m), + .io_dma_dccm_wen(ecc_io_dma_dccm_wen), + .io_dma_dccm_wdata_lo(ecc_io_dma_dccm_wdata_lo), + .io_dma_dccm_wdata_hi(ecc_io_dma_dccm_wdata_hi), + .io_sec_data_hi_r(ecc_io_sec_data_hi_r), + .io_sec_data_lo_r(ecc_io_sec_data_lo_r), + .io_sec_data_hi_m(ecc_io_sec_data_hi_m), + .io_sec_data_lo_m(ecc_io_sec_data_lo_m), + .io_sec_data_hi_r_ff(ecc_io_sec_data_hi_r_ff), + .io_sec_data_lo_r_ff(ecc_io_sec_data_lo_r_ff), + .io_dma_dccm_wdata_ecc_hi(ecc_io_dma_dccm_wdata_ecc_hi), + .io_dma_dccm_wdata_ecc_lo(ecc_io_dma_dccm_wdata_ecc_lo), + .io_stbuf_ecc_any(ecc_io_stbuf_ecc_any), + .io_sec_data_ecc_hi_r_ff(ecc_io_sec_data_ecc_hi_r_ff), + .io_sec_data_ecc_lo_r_ff(ecc_io_sec_data_ecc_lo_r_ff), + .io_single_ecc_error_hi_r(ecc_io_single_ecc_error_hi_r), + .io_single_ecc_error_lo_r(ecc_io_single_ecc_error_lo_r), + .io_lsu_single_ecc_error_r(ecc_io_lsu_single_ecc_error_r), + .io_lsu_double_ecc_error_r(ecc_io_lsu_double_ecc_error_r), + .io_lsu_single_ecc_error_m(ecc_io_lsu_single_ecc_error_m), + .io_lsu_double_ecc_error_m(ecc_io_lsu_double_ecc_error_m) + ); + lsu_trigger trigger ( // @[lsu.scala 79:30] + .io_trigger_pkt_any_0_select(trigger_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_pkt(trigger_io_trigger_pkt_any_0_match_pkt), + .io_trigger_pkt_any_0_store(trigger_io_trigger_pkt_any_0_store), + .io_trigger_pkt_any_0_load(trigger_io_trigger_pkt_any_0_load), + .io_trigger_pkt_any_0_m(trigger_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(trigger_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(trigger_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_pkt(trigger_io_trigger_pkt_any_1_match_pkt), + .io_trigger_pkt_any_1_store(trigger_io_trigger_pkt_any_1_store), + .io_trigger_pkt_any_1_load(trigger_io_trigger_pkt_any_1_load), + .io_trigger_pkt_any_1_m(trigger_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(trigger_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(trigger_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_pkt(trigger_io_trigger_pkt_any_2_match_pkt), + .io_trigger_pkt_any_2_store(trigger_io_trigger_pkt_any_2_store), + .io_trigger_pkt_any_2_load(trigger_io_trigger_pkt_any_2_load), + .io_trigger_pkt_any_2_m(trigger_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(trigger_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(trigger_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_pkt(trigger_io_trigger_pkt_any_3_match_pkt), + .io_trigger_pkt_any_3_store(trigger_io_trigger_pkt_any_3_store), + .io_trigger_pkt_any_3_load(trigger_io_trigger_pkt_any_3_load), + .io_trigger_pkt_any_3_m(trigger_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(trigger_io_trigger_pkt_any_3_tdata2), + .io_lsu_pkt_m_valid(trigger_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_half(trigger_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(trigger_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_load(trigger_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(trigger_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(trigger_io_lsu_pkt_m_bits_dma), + .io_lsu_addr_m(trigger_io_lsu_addr_m), + .io_store_data_m(trigger_io_store_data_m), + .io_lsu_trigger_match_m(trigger_io_lsu_trigger_match_m) + ); + lsu_clkdomain clkdomain ( // @[lsu.scala 80:30] + .clock(clkdomain_clock), + .io_clk_override(clkdomain_io_clk_override), + .io_lsu_busreq_r(clkdomain_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(clkdomain_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_empty_any(clkdomain_io_lsu_bus_buffer_empty_any), + .io_lsu_bus_clk_en(clkdomain_io_lsu_bus_clk_en), + .io_lsu_bus_obuf_c1_clken(clkdomain_io_lsu_bus_obuf_c1_clken), + .io_lsu_busm_clken(clkdomain_io_lsu_busm_clken), + .io_lsu_c1_m_clk(clkdomain_io_lsu_c1_m_clk), + .io_lsu_c1_r_clk(clkdomain_io_lsu_c1_r_clk), + .io_lsu_c2_m_clk(clkdomain_io_lsu_c2_m_clk), + .io_lsu_c2_r_clk(clkdomain_io_lsu_c2_r_clk), + .io_lsu_store_c1_m_clk(clkdomain_io_lsu_store_c1_m_clk), + .io_lsu_store_c1_r_clk(clkdomain_io_lsu_store_c1_r_clk), + .io_lsu_stbuf_c1_clk(clkdomain_io_lsu_stbuf_c1_clk), + .io_lsu_bus_ibuf_c1_clk(clkdomain_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_buf_c1_clk(clkdomain_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(clkdomain_io_lsu_free_c2_clk) + ); + lsu_bus_intf bus_intf ( // @[lsu.scala 81:30] + .clock(bus_intf_clock), + .reset(bus_intf_reset), + .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn), + .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned), + .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error), + .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy), + .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), + .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), + .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any), + .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any), + .io_tlu_busbuff_lsu_imprecise_error_addr_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any), + .io_lsu_c1_r_clk(bus_intf_io_lsu_c1_r_clk), + .io_lsu_c2_r_clk(bus_intf_io_lsu_c2_r_clk), + .io_lsu_bus_ibuf_c1_clk(bus_intf_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_buf_c1_clk(bus_intf_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(bus_intf_io_lsu_free_c2_clk), + .io_active_clk(bus_intf_io_active_clk), + .io_axi_aw_ready(bus_intf_io_axi_aw_ready), + .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr), + .io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region), + .io_axi_w_ready(bus_intf_io_axi_w_ready), + .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data), + .io_axi_b_valid(bus_intf_io_axi_b_valid), + .io_axi_b_bits_resp(bus_intf_io_axi_b_bits_resp), + .io_axi_b_bits_id(bus_intf_io_axi_b_bits_id), + .io_axi_ar_ready(bus_intf_io_axi_ar_ready), + .io_axi_ar_valid(bus_intf_io_axi_ar_valid), + .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr), + .io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region), + .io_axi_r_valid(bus_intf_io_axi_r_valid), + .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id), + .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data), + .io_axi_r_bits_resp(bus_intf_io_axi_r_bits_resp), + .io_dec_lsu_valid_raw_d(bus_intf_io_dec_lsu_valid_raw_d), + .io_lsu_busreq_m(bus_intf_io_lsu_busreq_m), + .io_lsu_pkt_m_valid(bus_intf_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_by(bus_intf_io_lsu_pkt_m_bits_by), + .io_lsu_pkt_m_bits_half(bus_intf_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(bus_intf_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_load(bus_intf_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_r_valid(bus_intf_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(bus_intf_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(bus_intf_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(bus_intf_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(bus_intf_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(bus_intf_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(bus_intf_io_lsu_pkt_r_bits_unsign), + .io_lsu_addr_m(bus_intf_io_lsu_addr_m), + .io_lsu_addr_r(bus_intf_io_lsu_addr_r), + .io_end_addr_m(bus_intf_io_end_addr_m), + .io_end_addr_r(bus_intf_io_end_addr_r), + .io_ldst_dual_d(bus_intf_io_ldst_dual_d), + .io_ldst_dual_m(bus_intf_io_ldst_dual_m), + .io_ldst_dual_r(bus_intf_io_ldst_dual_r), + .io_store_data_r(bus_intf_io_store_data_r), + .io_dec_tlu_force_halt(bus_intf_io_dec_tlu_force_halt), + .io_lsu_commit_r(bus_intf_io_lsu_commit_r), + .io_is_sideeffects_m(bus_intf_io_is_sideeffects_m), + .io_flush_m_up(bus_intf_io_flush_m_up), + .io_flush_r(bus_intf_io_flush_r), + .io_lsu_busreq_r(bus_intf_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(bus_intf_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_full_any(bus_intf_io_lsu_bus_buffer_full_any), + .io_lsu_bus_buffer_empty_any(bus_intf_io_lsu_bus_buffer_empty_any), + .io_bus_read_data_m(bus_intf_io_bus_read_data_m), + .io_lsu_nonblock_load_data(bus_intf_io_lsu_nonblock_load_data), + .io_dctl_busbuff_lsu_nonblock_load_valid_m(bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m), + .io_dctl_busbuff_lsu_nonblock_load_tag_m(bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m), + .io_dctl_busbuff_lsu_nonblock_load_inv_r(bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r), + .io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r), + .io_dctl_busbuff_lsu_nonblock_load_data_valid(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid), + .io_dctl_busbuff_lsu_nonblock_load_data_error(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error), + .io_dctl_busbuff_lsu_nonblock_load_data_tag(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag), + .io_lsu_bus_clk_en(bus_intf_io_lsu_bus_clk_en) + ); + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 222:27] + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 222:27] + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 222:27] + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 222:27] + assign io_lsu_dma_dccm_ready = ~_T_8; // @[lsu.scala 95:25] + assign io_lsu_pic_picm_wren = dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 224:14] + assign io_lsu_pic_picm_rden = dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 224:14] + assign io_lsu_pic_picm_mken = dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 224:14] + assign io_lsu_pic_picm_rdaddr = dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 224:14] + assign io_lsu_pic_picm_wraddr = dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 224:14] + assign io_lsu_pic_picm_wr_data = dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 224:14] + assign io_lsu_exu_lsu_result_m = lsu_lsc_ctl_io_lsu_exu_lsu_result_m; // @[lsu.scala 144:46] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 316:26] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 346:27] + assign io_dccm_wren = dccm_ctl_io_dccm_wren; // @[lsu.scala 223:11] + assign io_dccm_rden = dccm_ctl_io_dccm_rden; // @[lsu.scala 223:11] + assign io_dccm_wr_addr_lo = dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 223:11] + assign io_dccm_wr_addr_hi = dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 223:11] + assign io_dccm_rd_addr_lo = dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 223:11] + assign io_dccm_rd_addr_hi = dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 223:11] + assign io_dccm_wr_data_lo = dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 223:11] + assign io_dccm_wr_data_hi = dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 223:11] + assign io_lsu_tlu_lsu_pmu_load_external_m = _T_57 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 121:39] + assign io_lsu_tlu_lsu_pmu_store_external_m = _T_59 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 122:39] + assign io_axi_aw_valid = 1'h0; // @[lsu.scala 349:49] + assign io_axi_aw_bits_id = 3'h0; // @[lsu.scala 349:49] + assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 349:49] + assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 349:49] + assign io_axi_aw_bits_len = 8'h0; // @[lsu.scala 349:49] + assign io_axi_aw_bits_size = 3'h3; // @[lsu.scala 349:49] + assign io_axi_aw_bits_burst = 2'h1; // @[lsu.scala 349:49] + assign io_axi_aw_bits_lock = 1'h0; // @[lsu.scala 349:49] + assign io_axi_aw_bits_cache = 4'hf; // @[lsu.scala 349:49] + assign io_axi_aw_bits_prot = 3'h1; // @[lsu.scala 349:49] + assign io_axi_aw_bits_qos = 4'h0; // @[lsu.scala 349:49] + assign io_axi_w_valid = 1'h0; // @[lsu.scala 349:49] + assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 349:49] + assign io_axi_w_bits_strb = 8'h0; // @[lsu.scala 349:49] + assign io_axi_w_bits_last = 1'h1; // @[lsu.scala 349:49] + assign io_axi_b_ready = 1'h1; // @[lsu.scala 349:49] + assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 349:49] + assign io_axi_ar_bits_id = 3'h0; // @[lsu.scala 349:49] + assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 349:49] + assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 349:49] + assign io_axi_ar_bits_len = 8'h0; // @[lsu.scala 349:49] + assign io_axi_ar_bits_size = 3'h3; // @[lsu.scala 349:49] + assign io_axi_ar_bits_burst = 2'h1; // @[lsu.scala 349:49] + assign io_axi_ar_bits_lock = 1'h0; // @[lsu.scala 349:49] + assign io_axi_ar_bits_cache = 4'hf; // @[lsu.scala 349:49] + assign io_axi_ar_bits_prot = 3'h1; // @[lsu.scala 349:49] + assign io_axi_ar_bits_qos = 4'h0; // @[lsu.scala 349:49] + assign io_axi_r_ready = 1'h1; // @[lsu.scala 349:49] + assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 75:24] + assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 88:25] + assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 87:26] + assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 89:28] + assign io_lsu_idle_any = _T_24 & bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 109:19] + assign io_lsu_active = _T_27 | _T_28; // @[lsu.scala 110:18] + assign io_lsu_fir_addr = lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 162:49] + assign io_lsu_fir_error = lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 163:49] + assign io_lsu_single_ecc_error_incr = lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 160:49] + assign io_lsu_error_pkt_r_valid = lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 161:49] + assign io_lsu_error_pkt_r_bits_single_ecc_error = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 161:49] + assign io_lsu_error_pkt_r_bits_inst_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 161:49] + assign io_lsu_error_pkt_r_bits_exc_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 161:49] + assign io_lsu_error_pkt_r_bits_mscause = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 161:49] + assign io_lsu_error_pkt_r_bits_addr = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 161:49] + assign io_lsu_pmu_misaligned_m = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_55; // @[lsu.scala 120:27] + assign io_lsu_trigger_match_m = trigger_io_lsu_trigger_match_m; // @[lsu.scala 291:50] + assign io_lsu_nonblock_load_data = bus_intf_io_lsu_nonblock_load_data; // @[lsu.scala 347:29] + assign lsu_lsc_ctl_clock = clock; + assign lsu_lsc_ctl_reset = reset; + assign lsu_lsc_ctl_io_clk_override = io_clk_override; // @[lsu.scala 126:46] + assign lsu_lsc_ctl_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 127:46] + assign lsu_lsc_ctl_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 128:46] + assign lsu_lsc_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 129:46] + assign lsu_lsc_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 130:46] + assign lsu_lsc_ctl_io_lsu_store_c1_m_clk = clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 131:46] + assign lsu_lsc_ctl_io_lsu_ld_data_corr_r = dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 133:46] + assign lsu_lsc_ctl_io_lsu_single_ecc_error_r = ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 134:46] + assign lsu_lsc_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 135:46] + assign lsu_lsc_ctl_io_lsu_ld_data_m = dccm_ctl_io_lsu_ld_data_m; // @[lsu.scala 136:46] + assign lsu_lsc_ctl_io_lsu_single_ecc_error_m = ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 137:46] + assign lsu_lsc_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 138:46] + assign lsu_lsc_ctl_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 139:46] + assign lsu_lsc_ctl_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 140:46] + assign lsu_lsc_ctl_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 141:46] + assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d = io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 144:46] + assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d = io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 144:46] + assign lsu_lsc_ctl_io_lsu_p_valid = io_lsu_p_valid; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_fast_int = io_lsu_p_bits_fast_int; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_by = io_lsu_p_bits_by; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_half = io_lsu_p_bits_half; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_word = io_lsu_p_bits_word; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_dword = io_lsu_p_bits_dword; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_load = io_lsu_p_bits_load; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_store = io_lsu_p_bits_store; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_unsign = io_lsu_p_bits_unsign; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_dma = io_lsu_p_bits_dma; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d = io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d = io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m = io_lsu_p_bits_store_data_bypass_m; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 146:46] + assign lsu_lsc_ctl_io_dec_lsu_offset_d = io_dec_lsu_offset_d; // @[lsu.scala 147:46] + assign lsu_lsc_ctl_io_picm_mask_data_m = dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 148:46] + assign lsu_lsc_ctl_io_bus_read_data_m = bus_intf_io_bus_read_data_m; // @[lsu.scala 149:46] + assign lsu_lsc_ctl_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu.scala 151:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req = io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 150:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 150:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 150:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 150:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 150:46] + assign dccm_ctl_clock = clock; + assign dccm_ctl_reset = reset; + assign dccm_ctl_io_clk_override = io_clk_override; // @[lsu.scala 166:46] + assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 169:46] + assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 171:46] + assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 173:46] + assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_d_bits_word = lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_d_bits_dword = lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_d_bits_load = lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_d_bits_dma = lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 176:46] + assign dccm_ctl_io_addr_in_dccm_d = lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 177:46] + assign dccm_ctl_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 178:46] + assign dccm_ctl_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 179:46] + assign dccm_ctl_io_addr_in_pic_d = lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 180:46] + assign dccm_ctl_io_addr_in_pic_m = lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 181:46] + assign dccm_ctl_io_addr_in_pic_r = lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 182:46] + assign dccm_ctl_io_lsu_raw_fwd_lo_r = lsu_raw_fwd_lo_r; // @[lsu.scala 183:46] + assign dccm_ctl_io_lsu_raw_fwd_hi_r = lsu_raw_fwd_hi_r; // @[lsu.scala 184:46] + assign dccm_ctl_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 185:46] + assign dccm_ctl_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 167:46] + assign dccm_ctl_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 186:46] + assign dccm_ctl_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[lsu.scala 187:46] + assign dccm_ctl_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 188:46] + assign dccm_ctl_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[lsu.scala 189:46] + assign dccm_ctl_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[lsu.scala 190:46] + assign dccm_ctl_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r[15:0]; // @[lsu.scala 191:46] + assign dccm_ctl_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[lsu.scala 192:46] + assign dccm_ctl_io_stbuf_addr_any = stbuf_io_stbuf_addr_any; // @[lsu.scala 193:46] + assign dccm_ctl_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 194:46] + assign dccm_ctl_io_stbuf_ecc_any = ecc_io_stbuf_ecc_any; // @[lsu.scala 195:46] + assign dccm_ctl_io_stbuf_fwddata_hi_m = stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 196:46] + assign dccm_ctl_io_stbuf_fwddata_lo_m = stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 197:46] + assign dccm_ctl_io_stbuf_fwdbyteen_lo_m = stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 198:46] + assign dccm_ctl_io_stbuf_fwdbyteen_hi_m = stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 199:46] + assign dccm_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 200:46] + assign dccm_ctl_io_single_ecc_error_hi_r = ecc_io_single_ecc_error_hi_r; // @[lsu.scala 201:46] + assign dccm_ctl_io_single_ecc_error_lo_r = ecc_io_single_ecc_error_lo_r; // @[lsu.scala 202:46] + assign dccm_ctl_io_sec_data_hi_r_ff = ecc_io_sec_data_hi_r_ff; // @[lsu.scala 205:46] + assign dccm_ctl_io_sec_data_lo_r_ff = ecc_io_sec_data_lo_r_ff; // @[lsu.scala 206:46] + assign dccm_ctl_io_sec_data_ecc_hi_r_ff = ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 207:46] + assign dccm_ctl_io_sec_data_ecc_lo_r_ff = ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 208:46] + assign dccm_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 209:46] + assign dccm_ctl_io_sec_data_hi_m = ecc_io_sec_data_hi_m; // @[lsu.scala 210:46] + assign dccm_ctl_io_sec_data_lo_m = ecc_io_sec_data_lo_m; // @[lsu.scala 211:46] + assign dccm_ctl_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 212:46] + assign dccm_ctl_io_dma_dccm_wen = _T_11 & io_lsu_dma_dma_lsc_ctl_dma_mem_sz[1]; // @[lsu.scala 213:46] + assign dccm_ctl_io_dma_pic_wen = _T_10 & lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 214:46] + assign dccm_ctl_io_dma_mem_tag_m = dma_mem_tag_m; // @[lsu.scala 215:46] + assign dccm_ctl_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 216:46] + assign dccm_ctl_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 217:46] + assign dccm_ctl_io_dma_dccm_wdata_ecc_hi = ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 218:46] + assign dccm_ctl_io_dma_dccm_wdata_ecc_lo = ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 219:46] + assign dccm_ctl_io_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 222:27] + assign dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 222:27] + assign dccm_ctl_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[lsu.scala 223:11] + assign dccm_ctl_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[lsu.scala 223:11] + assign dccm_ctl_io_lsu_pic_picm_rd_data = io_lsu_pic_picm_rd_data; // @[lsu.scala 224:14] + assign stbuf_clock = clock; + assign stbuf_reset = reset; + assign stbuf_io_lsu_stbuf_c1_clk = clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 230:54] + assign stbuf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 231:54] + assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 232:48] + assign stbuf_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 232:48] + assign stbuf_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 232:48] + assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_dword = lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 233:48] + assign stbuf_io_store_stbuf_reqvld_r = _T_33 & _T_38; // @[lsu.scala 234:48] + assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 235:49] + assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 236:49] + assign stbuf_io_store_data_hi_r = dccm_ctl_io_store_data_hi_r; // @[lsu.scala 237:62] + assign stbuf_io_store_data_lo_r = dccm_ctl_io_store_data_lo_r; // @[lsu.scala 238:62] + assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 239:49] + assign stbuf_io_store_datafn_lo_r = dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 240:56] + assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 241:52] + assign stbuf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 243:64] + assign stbuf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 244:64] + assign stbuf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 246:64] + assign stbuf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 247:64] + assign stbuf_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 227:50] + assign stbuf_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 228:50] + assign stbuf_io_ldst_dual_r = lsu_lsc_ctl_io_lsu_addr_r[2] != lsu_lsc_ctl_io_end_addr_r[2]; // @[lsu.scala 229:50] + assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 248:49] + assign stbuf_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 249:56] + assign ecc_clock = clock; + assign ecc_reset = reset; + assign ecc_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 256:52] + assign ecc_io_clk_override = io_clk_override; // @[lsu.scala 255:50] + assign ecc_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 257:52] + assign ecc_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 257:52] + assign ecc_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 257:52] + assign ecc_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 257:52] + assign ecc_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 259:54] + assign ecc_io_dec_tlu_core_ecc_disable = io_dec_tlu_core_ecc_disable; // @[lsu.scala 260:50] + assign ecc_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[lsu.scala 265:58] + assign ecc_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[lsu.scala 266:58] + assign ecc_io_dccm_rdata_hi_m = dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 269:54] + assign ecc_io_dccm_rdata_lo_m = dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 270:54] + assign ecc_io_dccm_data_ecc_hi_m = dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 273:50] + assign ecc_io_dccm_data_ecc_lo_m = dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 274:50] + assign ecc_io_ld_single_ecc_error_r = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 275:50] + assign ecc_io_ld_single_ecc_error_r_ff = dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 276:50] + assign ecc_io_lsu_dccm_rden_m = dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 277:50] + assign ecc_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 278:50] + assign ecc_io_dma_dccm_wen = _T_11 & io_lsu_dma_dma_lsc_ctl_dma_mem_sz[1]; // @[lsu.scala 279:50] + assign ecc_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 280:50] + assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 281:50] + assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_0_match_pkt = io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_0_load = io_trigger_pkt_any_0_load; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_0_m = io_trigger_pkt_any_0_m; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_0_tdata2 = io_trigger_pkt_any_0_tdata2; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_select = io_trigger_pkt_any_1_select; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_match_pkt = io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_store = io_trigger_pkt_any_1_store; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_load = io_trigger_pkt_any_1_load; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_m = io_trigger_pkt_any_1_m; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_tdata2 = io_trigger_pkt_any_1_tdata2; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_select = io_trigger_pkt_any_2_select; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_match_pkt = io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_store = io_trigger_pkt_any_2_store; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_load = io_trigger_pkt_any_2_load; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_m = io_trigger_pkt_any_2_m; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_tdata2 = io_trigger_pkt_any_2_tdata2; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_select = io_trigger_pkt_any_3_select; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_match_pkt = io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_store = io_trigger_pkt_any_3_store; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_load = io_trigger_pkt_any_3_load; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_m = io_trigger_pkt_any_3_m; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_tdata2 = io_trigger_pkt_any_3_tdata2; // @[lsu.scala 286:50] + assign trigger_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 287:50] + assign trigger_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 287:50] + assign trigger_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 287:50] + assign trigger_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 287:50] + assign trigger_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 287:50] + assign trigger_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 287:50] + assign trigger_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 288:50] + assign trigger_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 289:50] + assign clkdomain_clock = clock; + assign clkdomain_io_clk_override = io_clk_override; // @[lsu.scala 296:50] + assign clkdomain_io_lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 302:50] + assign clkdomain_io_lsu_bus_buffer_pend_any = bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 303:50] + assign clkdomain_io_lsu_bus_buffer_empty_any = bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 304:50] + assign clkdomain_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 306:50] + assign bus_intf_clock = clock; + assign bus_intf_reset = reset; + assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 316:26] + assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 316:26] + assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 316:26] + assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 318:49] + assign bus_intf_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 319:49] + assign bus_intf_io_lsu_bus_ibuf_c1_clk = clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 322:49] + assign bus_intf_io_lsu_bus_buf_c1_clk = clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 324:49] + assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 325:49] + assign bus_intf_io_active_clk = io_active_clk; // @[lsu.scala 326:49] + assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 349:49] + assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 349:49] + assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 349:49] + assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 349:49] + assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 349:49] + assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 349:49] + assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 349:49] + assign bus_intf_io_axi_r_bits_id = io_axi_r_bits_id; // @[lsu.scala 349:49] + assign bus_intf_io_axi_r_bits_data = io_axi_r_bits_data; // @[lsu.scala 349:49] + assign bus_intf_io_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu.scala 349:49] + assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 328:49] + assign bus_intf_io_lsu_busreq_m = _T_48 & _T_49; // @[lsu.scala 329:49] + assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 338:49] + assign bus_intf_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 338:49] + assign bus_intf_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 338:49] + assign bus_intf_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 338:49] + assign bus_intf_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 338:49] + assign bus_intf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_unsign = lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m & _T_100; // @[lsu.scala 333:49] + assign bus_intf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r & _T_103; // @[lsu.scala 334:49] + assign bus_intf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m & _T_100; // @[lsu.scala 335:49] + assign bus_intf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r & _T_103; // @[lsu.scala 336:49] + assign bus_intf_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 330:49] + assign bus_intf_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 331:49] + assign bus_intf_io_ldst_dual_r = lsu_lsc_ctl_io_lsu_addr_r[2] != lsu_lsc_ctl_io_end_addr_r[2]; // @[lsu.scala 332:49] + assign bus_intf_io_store_data_r = dccm_ctl_io_store_data_r & _T_103; // @[lsu.scala 337:49] + assign bus_intf_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu.scala 340:49] + assign bus_intf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 341:49] + assign bus_intf_io_is_sideeffects_m = lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 342:49] + assign bus_intf_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 343:49] + assign bus_intf_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 344:49] + assign bus_intf_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 350:49] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dma_mem_tag_m = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + lsu_raw_fwd_hi_r = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + lsu_raw_fwd_lo_r = _RAND_2[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dma_mem_tag_m = 3'h0; + end + if (reset) begin + lsu_raw_fwd_hi_r = 1'h0; + end + if (reset) begin + lsu_raw_fwd_lo_r = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clkdomain_io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + dma_mem_tag_m <= 3'h0; + end else begin + dma_mem_tag_m <= io_lsu_dma_dma_mem_tag; + end + end + always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_raw_fwd_hi_r <= 1'h0; + end else begin + lsu_raw_fwd_hi_r <= |stbuf_io_stbuf_fwdbyteen_hi_m; + end + end + always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_raw_fwd_lo_r <= 1'h0; + end else begin + lsu_raw_fwd_lo_r <= |stbuf_io_stbuf_fwdbyteen_lo_m; + end + end +endmodule diff --git a/lsu_bus_intf.anno.json b/lsu_bus_intf.anno.json new file mode 100644 index 00000000..df7ef78c --- /dev/null +++ b/lsu_bus_intf.anno.json @@ -0,0 +1,113 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_misaligned", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r", + "~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_bus_read_data_m", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m", + "~lsu_bus_intf|lsu_bus_intf>io_end_addr_m", + "~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store", + "~lsu_bus_intf|lsu_bus_intf>io_store_data_r", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half", + "~lsu_bus_intf|lsu_bus_intf>io_end_addr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_valid_m", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_load", + "~lsu_bus_intf|lsu_bus_intf>io_flush_m_up", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_valid", + "~lsu_bus_intf|lsu_bus_intf>io_is_sideeffects_m", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m", + "~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt", + "~lsu_bus_intf|lsu_bus_intf>io_end_addr_m", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r", + "~lsu_bus_intf|lsu_bus_intf>io_end_addr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_busy", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready", + "~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready", + "~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_tag_m", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_lsu_bus_buffer_full_any", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_d", + "~lsu_bus_intf|lsu_bus_intf>io_dec_lsu_valid_raw_d", + "~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_m", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m", + "~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_inv_r", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_trxn", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready", + "~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready", + "~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"lsu_bus_intf.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"lsu_bus_intf" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/lsu_bus_intf.fir b/lsu_bus_intf.fir new file mode 100644 index 00000000..aecef0c5 --- /dev/null +++ b/lsu_bus_intf.fir @@ -0,0 +1,7199 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit lsu_bus_intf : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_bus_buffer : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_nonblock_load_data : UInt<32>} + + wire buf_addr : UInt<32>[4] @[lsu_bus_buffer.scala 71:22] + wire buf_state : UInt<3>[4] @[lsu_bus_buffer.scala 72:23] + wire buf_write : UInt<4> + buf_write <= UInt<1>("h00") + wire CmdPtr0 : UInt<2> + CmdPtr0 <= UInt<1>("h00") + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[lsu_bus_buffer.scala 77:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[lsu_bus_buffer.scala 78:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_2 = eq(_T, _T_1) @[lsu_bus_buffer.scala 80:74] + node _T_3 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 80:109] + node _T_4 = and(_T_2, _T_3) @[lsu_bus_buffer.scala 80:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_6 = and(_T_4, _T_5) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_9 = eq(_T_7, _T_8) @[lsu_bus_buffer.scala 80:74] + node _T_10 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 80:109] + node _T_11 = and(_T_9, _T_10) @[lsu_bus_buffer.scala 80:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_13 = and(_T_11, _T_12) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_16 = eq(_T_14, _T_15) @[lsu_bus_buffer.scala 80:74] + node _T_17 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 80:109] + node _T_18 = and(_T_16, _T_17) @[lsu_bus_buffer.scala 80:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_20 = and(_T_18, _T_19) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_23 = eq(_T_21, _T_22) @[lsu_bus_buffer.scala 80:74] + node _T_24 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 80:109] + node _T_25 = and(_T_23, _T_24) @[lsu_bus_buffer.scala 80:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_27 = and(_T_25, _T_26) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_30 = eq(_T_28, _T_29) @[lsu_bus_buffer.scala 81:74] + node _T_31 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 81:109] + node _T_32 = and(_T_30, _T_31) @[lsu_bus_buffer.scala 81:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_34 = and(_T_32, _T_33) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_37 = eq(_T_35, _T_36) @[lsu_bus_buffer.scala 81:74] + node _T_38 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 81:109] + node _T_39 = and(_T_37, _T_38) @[lsu_bus_buffer.scala 81:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_41 = and(_T_39, _T_40) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_44 = eq(_T_42, _T_43) @[lsu_bus_buffer.scala 81:74] + node _T_45 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 81:109] + node _T_46 = and(_T_44, _T_45) @[lsu_bus_buffer.scala 81:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_48 = and(_T_46, _T_47) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_51 = eq(_T_49, _T_50) @[lsu_bus_buffer.scala 81:74] + node _T_52 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 81:109] + node _T_53 = and(_T_51, _T_52) @[lsu_bus_buffer.scala 81:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_55 = and(_T_53, _T_54) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[lsu_bus_buffer.scala 82:33] + wire ld_byte_ibuf_hit_lo : UInt<4> + ld_byte_ibuf_hit_lo <= UInt<1>("h00") + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[lsu_bus_buffer.scala 84:33] + wire ld_byte_ibuf_hit_hi : UInt<4> + ld_byte_ibuf_hit_hi <= UInt<1>("h00") + wire buf_byteen : UInt<4>[4] @[lsu_bus_buffer.scala 86:24] + buf_byteen[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + wire buf_nxtstate : UInt<3>[4] @[lsu_bus_buffer.scala 88:26] + buf_nxtstate[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + wire buf_wr_en : UInt<1>[4] @[lsu_bus_buffer.scala 90:23] + buf_wr_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + wire buf_data_en : UInt<1>[4] @[lsu_bus_buffer.scala 92:25] + buf_data_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + wire buf_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 94:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + wire buf_ldfwd_in : UInt<1>[4] @[lsu_bus_buffer.scala 96:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + wire buf_ldfwd_en : UInt<1>[4] @[lsu_bus_buffer.scala 98:26] + buf_ldfwd_en[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + wire buf_data_in : UInt<32>[4] @[lsu_bus_buffer.scala 100:25] + buf_data_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 102:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + wire buf_error_en : UInt<1>[4] @[lsu_bus_buffer.scala 104:26] + buf_error_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + wire bus_rsp_read_error : UInt<1> + bus_rsp_read_error <= UInt<1>("h00") + wire bus_rsp_rdata : UInt<64> + bus_rsp_rdata <= UInt<1>("h00") + wire bus_rsp_write_error : UInt<1> + bus_rsp_write_error <= UInt<1>("h00") + wire buf_dualtag : UInt<2>[4] @[lsu_bus_buffer.scala 109:25] + buf_dualtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + wire buf_ldfwd : UInt<4> + buf_ldfwd <= UInt<1>("h00") + wire buf_resp_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 112:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + wire any_done_wait_state : UInt<1> + any_done_wait_state <= UInt<1>("h00") + wire bus_rsp_write : UInt<1> + bus_rsp_write <= UInt<1>("h00") + wire bus_rsp_write_tag : UInt<3> + bus_rsp_write_tag <= UInt<1>("h00") + wire buf_ldfwdtag : UInt<2>[4] @[lsu_bus_buffer.scala 117:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + wire buf_rst : UInt<1>[4] @[lsu_bus_buffer.scala 119:21] + buf_rst[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + wire ibuf_drainvec_vld : UInt<4> + ibuf_drainvec_vld <= UInt<1>("h00") + wire buf_byteen_in : UInt<4>[4] @[lsu_bus_buffer.scala 122:27] + buf_byteen_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + wire buf_addr_in : UInt<32>[4] @[lsu_bus_buffer.scala 124:25] + buf_addr_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + wire buf_dual_in : UInt<4> + buf_dual_in <= UInt<1>("h00") + wire buf_samedw_in : UInt<4> + buf_samedw_in <= UInt<1>("h00") + wire buf_nomerge_in : UInt<4> + buf_nomerge_in <= UInt<1>("h00") + wire buf_dualhi_in : UInt<4> + buf_dualhi_in <= UInt<1>("h00") + wire buf_dualtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 130:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + wire buf_sideeffect_in : UInt<4> + buf_sideeffect_in <= UInt<1>("h00") + wire buf_unsign_in : UInt<4> + buf_unsign_in <= UInt<1>("h00") + wire buf_sz_in : UInt<2>[4] @[lsu_bus_buffer.scala 134:23] + buf_sz_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + wire buf_write_in : UInt<4> + buf_write_in <= UInt<1>("h00") + wire buf_unsign : UInt<4> + buf_unsign <= UInt<1>("h00") + wire buf_error : UInt<4> + buf_error <= UInt<1>("h00") + wire CmdPtr1 : UInt<2> + CmdPtr1 <= UInt<1>("h00") + wire ibuf_data : UInt<32> + ibuf_data <= UInt<1>("h00") + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[lsu_bus_buffer.scala 142:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 142:98] + node _T_58 = or(_T_56, _T_57) @[lsu_bus_buffer.scala 142:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[lsu_bus_buffer.scala 142:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 142:98] + node _T_61 = or(_T_59, _T_60) @[lsu_bus_buffer.scala 142:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[lsu_bus_buffer.scala 142:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 142:98] + node _T_64 = or(_T_62, _T_63) @[lsu_bus_buffer.scala 142:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[lsu_bus_buffer.scala 142:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 142:98] + node _T_67 = or(_T_65, _T_66) @[lsu_bus_buffer.scala 142:77] + node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] + io.ld_byte_hit_buf_lo <= _T_70 @[lsu_bus_buffer.scala 142:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[lsu_bus_buffer.scala 143:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 143:98] + node _T_73 = or(_T_71, _T_72) @[lsu_bus_buffer.scala 143:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[lsu_bus_buffer.scala 143:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 143:98] + node _T_76 = or(_T_74, _T_75) @[lsu_bus_buffer.scala 143:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[lsu_bus_buffer.scala 143:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 143:98] + node _T_79 = or(_T_77, _T_78) @[lsu_bus_buffer.scala 143:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[lsu_bus_buffer.scala 143:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 143:98] + node _T_82 = or(_T_80, _T_81) @[lsu_bus_buffer.scala 143:77] + node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] + io.ld_byte_hit_buf_hi <= _T_85 @[lsu_bus_buffer.scala 143:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[lsu_bus_buffer.scala 145:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_89 = and(_T_87, _T_88) @[lsu_bus_buffer.scala 145:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[lsu_bus_buffer.scala 145:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_93 = and(_T_91, _T_92) @[lsu_bus_buffer.scala 145:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[lsu_bus_buffer.scala 145:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_97 = and(_T_95, _T_96) @[lsu_bus_buffer.scala 145:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[lsu_bus_buffer.scala 145:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_101 = and(_T_99, _T_100) @[lsu_bus_buffer.scala 145:114] + node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] + node _T_104 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[lsu_bus_buffer.scala 145:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_107 = and(_T_105, _T_106) @[lsu_bus_buffer.scala 145:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[lsu_bus_buffer.scala 145:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_111 = and(_T_109, _T_110) @[lsu_bus_buffer.scala 145:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[lsu_bus_buffer.scala 145:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_115 = and(_T_113, _T_114) @[lsu_bus_buffer.scala 145:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[lsu_bus_buffer.scala 145:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_119 = and(_T_117, _T_118) @[lsu_bus_buffer.scala 145:114] + node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] + node _T_122 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[lsu_bus_buffer.scala 145:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_125 = and(_T_123, _T_124) @[lsu_bus_buffer.scala 145:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[lsu_bus_buffer.scala 145:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_buffer.scala 145:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[lsu_bus_buffer.scala 145:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_buffer.scala 145:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[lsu_bus_buffer.scala 145:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_buffer.scala 145:114] + node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] + node _T_140 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[lsu_bus_buffer.scala 145:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_143 = and(_T_141, _T_142) @[lsu_bus_buffer.scala 145:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[lsu_bus_buffer.scala 145:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_147 = and(_T_145, _T_146) @[lsu_bus_buffer.scala 145:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[lsu_bus_buffer.scala 145:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_151 = and(_T_149, _T_150) @[lsu_bus_buffer.scala 145:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[lsu_bus_buffer.scala 145:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_155 = and(_T_153, _T_154) @[lsu_bus_buffer.scala 145:114] + node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] + node _T_158 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[lsu_bus_buffer.scala 146:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_161 = and(_T_159, _T_160) @[lsu_bus_buffer.scala 146:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[lsu_bus_buffer.scala 146:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_165 = and(_T_163, _T_164) @[lsu_bus_buffer.scala 146:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[lsu_bus_buffer.scala 146:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_169 = and(_T_167, _T_168) @[lsu_bus_buffer.scala 146:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[lsu_bus_buffer.scala 146:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_173 = and(_T_171, _T_172) @[lsu_bus_buffer.scala 146:114] + node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] + node _T_176 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[lsu_bus_buffer.scala 146:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_179 = and(_T_177, _T_178) @[lsu_bus_buffer.scala 146:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[lsu_bus_buffer.scala 146:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_183 = and(_T_181, _T_182) @[lsu_bus_buffer.scala 146:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[lsu_bus_buffer.scala 146:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_187 = and(_T_185, _T_186) @[lsu_bus_buffer.scala 146:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[lsu_bus_buffer.scala 146:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_191 = and(_T_189, _T_190) @[lsu_bus_buffer.scala 146:114] + node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] + node _T_194 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[lsu_bus_buffer.scala 146:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_197 = and(_T_195, _T_196) @[lsu_bus_buffer.scala 146:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[lsu_bus_buffer.scala 146:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_201 = and(_T_199, _T_200) @[lsu_bus_buffer.scala 146:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[lsu_bus_buffer.scala 146:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_205 = and(_T_203, _T_204) @[lsu_bus_buffer.scala 146:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[lsu_bus_buffer.scala 146:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_209 = and(_T_207, _T_208) @[lsu_bus_buffer.scala 146:114] + node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] + node _T_212 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[lsu_bus_buffer.scala 146:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_215 = and(_T_213, _T_214) @[lsu_bus_buffer.scala 146:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[lsu_bus_buffer.scala 146:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_219 = and(_T_217, _T_218) @[lsu_bus_buffer.scala 146:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[lsu_bus_buffer.scala 146:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_223 = and(_T_221, _T_222) @[lsu_bus_buffer.scala 146:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[lsu_bus_buffer.scala 146:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_227 = and(_T_225, _T_226) @[lsu_bus_buffer.scala 146:114] + node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] + node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] + wire buf_age_younger : UInt<4>[4] @[lsu_bus_buffer.scala 148:29] + buf_age_younger[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_232 = orr(_T_231) @[lsu_bus_buffer.scala 150:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_234 = and(_T_230, _T_233) @[lsu_bus_buffer.scala 150:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_237 = and(_T_234, _T_236) @[lsu_bus_buffer.scala 150:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_240 = orr(_T_239) @[lsu_bus_buffer.scala 150:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_242 = and(_T_238, _T_241) @[lsu_bus_buffer.scala 150:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_245 = and(_T_242, _T_244) @[lsu_bus_buffer.scala 150:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_248 = orr(_T_247) @[lsu_bus_buffer.scala 150:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_250 = and(_T_246, _T_249) @[lsu_bus_buffer.scala 150:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_253 = and(_T_250, _T_252) @[lsu_bus_buffer.scala 150:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_256 = orr(_T_255) @[lsu_bus_buffer.scala 150:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_258 = and(_T_254, _T_257) @[lsu_bus_buffer.scala 150:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_261 = and(_T_258, _T_260) @[lsu_bus_buffer.scala 150:148] + node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] + node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] + node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_267 = orr(_T_266) @[lsu_bus_buffer.scala 150:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_269 = and(_T_265, _T_268) @[lsu_bus_buffer.scala 150:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_272 = and(_T_269, _T_271) @[lsu_bus_buffer.scala 150:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_275 = orr(_T_274) @[lsu_bus_buffer.scala 150:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_277 = and(_T_273, _T_276) @[lsu_bus_buffer.scala 150:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_280 = and(_T_277, _T_279) @[lsu_bus_buffer.scala 150:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_283 = orr(_T_282) @[lsu_bus_buffer.scala 150:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_285 = and(_T_281, _T_284) @[lsu_bus_buffer.scala 150:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_288 = and(_T_285, _T_287) @[lsu_bus_buffer.scala 150:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_291 = orr(_T_290) @[lsu_bus_buffer.scala 150:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_293 = and(_T_289, _T_292) @[lsu_bus_buffer.scala 150:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_296 = and(_T_293, _T_295) @[lsu_bus_buffer.scala 150:148] + node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_302 = orr(_T_301) @[lsu_bus_buffer.scala 150:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_304 = and(_T_300, _T_303) @[lsu_bus_buffer.scala 150:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_307 = and(_T_304, _T_306) @[lsu_bus_buffer.scala 150:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_310 = orr(_T_309) @[lsu_bus_buffer.scala 150:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_312 = and(_T_308, _T_311) @[lsu_bus_buffer.scala 150:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_315 = and(_T_312, _T_314) @[lsu_bus_buffer.scala 150:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_318 = orr(_T_317) @[lsu_bus_buffer.scala 150:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_320 = and(_T_316, _T_319) @[lsu_bus_buffer.scala 150:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_323 = and(_T_320, _T_322) @[lsu_bus_buffer.scala 150:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_326 = orr(_T_325) @[lsu_bus_buffer.scala 150:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_328 = and(_T_324, _T_327) @[lsu_bus_buffer.scala 150:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_331 = and(_T_328, _T_330) @[lsu_bus_buffer.scala 150:148] + node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] + node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] + node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_337 = orr(_T_336) @[lsu_bus_buffer.scala 150:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_339 = and(_T_335, _T_338) @[lsu_bus_buffer.scala 150:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_342 = and(_T_339, _T_341) @[lsu_bus_buffer.scala 150:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_345 = orr(_T_344) @[lsu_bus_buffer.scala 150:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_347 = and(_T_343, _T_346) @[lsu_bus_buffer.scala 150:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_350 = and(_T_347, _T_349) @[lsu_bus_buffer.scala 150:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_353 = orr(_T_352) @[lsu_bus_buffer.scala 150:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_355 = and(_T_351, _T_354) @[lsu_bus_buffer.scala 150:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_358 = and(_T_355, _T_357) @[lsu_bus_buffer.scala 150:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_361 = orr(_T_360) @[lsu_bus_buffer.scala 150:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_363 = and(_T_359, _T_362) @[lsu_bus_buffer.scala 150:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_366 = and(_T_363, _T_365) @[lsu_bus_buffer.scala 150:148] + node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] + ld_byte_hitvecfn_lo[0] <= _T_264 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[lsu_bus_buffer.scala 150:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_372 = orr(_T_371) @[lsu_bus_buffer.scala 151:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_374 = and(_T_370, _T_373) @[lsu_bus_buffer.scala 151:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_377 = and(_T_374, _T_376) @[lsu_bus_buffer.scala 151:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_380 = orr(_T_379) @[lsu_bus_buffer.scala 151:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_382 = and(_T_378, _T_381) @[lsu_bus_buffer.scala 151:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_385 = and(_T_382, _T_384) @[lsu_bus_buffer.scala 151:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_388 = orr(_T_387) @[lsu_bus_buffer.scala 151:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_390 = and(_T_386, _T_389) @[lsu_bus_buffer.scala 151:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_393 = and(_T_390, _T_392) @[lsu_bus_buffer.scala 151:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_396 = orr(_T_395) @[lsu_bus_buffer.scala 151:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_398 = and(_T_394, _T_397) @[lsu_bus_buffer.scala 151:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_401 = and(_T_398, _T_400) @[lsu_bus_buffer.scala 151:148] + node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_407 = orr(_T_406) @[lsu_bus_buffer.scala 151:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_409 = and(_T_405, _T_408) @[lsu_bus_buffer.scala 151:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_412 = and(_T_409, _T_411) @[lsu_bus_buffer.scala 151:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_415 = orr(_T_414) @[lsu_bus_buffer.scala 151:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_417 = and(_T_413, _T_416) @[lsu_bus_buffer.scala 151:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_420 = and(_T_417, _T_419) @[lsu_bus_buffer.scala 151:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_423 = orr(_T_422) @[lsu_bus_buffer.scala 151:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_425 = and(_T_421, _T_424) @[lsu_bus_buffer.scala 151:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_428 = and(_T_425, _T_427) @[lsu_bus_buffer.scala 151:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_431 = orr(_T_430) @[lsu_bus_buffer.scala 151:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_433 = and(_T_429, _T_432) @[lsu_bus_buffer.scala 151:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_436 = and(_T_433, _T_435) @[lsu_bus_buffer.scala 151:148] + node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] + node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_442 = orr(_T_441) @[lsu_bus_buffer.scala 151:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_444 = and(_T_440, _T_443) @[lsu_bus_buffer.scala 151:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_447 = and(_T_444, _T_446) @[lsu_bus_buffer.scala 151:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_450 = orr(_T_449) @[lsu_bus_buffer.scala 151:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_452 = and(_T_448, _T_451) @[lsu_bus_buffer.scala 151:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_455 = and(_T_452, _T_454) @[lsu_bus_buffer.scala 151:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_458 = orr(_T_457) @[lsu_bus_buffer.scala 151:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_460 = and(_T_456, _T_459) @[lsu_bus_buffer.scala 151:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_463 = and(_T_460, _T_462) @[lsu_bus_buffer.scala 151:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_466 = orr(_T_465) @[lsu_bus_buffer.scala 151:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_468 = and(_T_464, _T_467) @[lsu_bus_buffer.scala 151:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_471 = and(_T_468, _T_470) @[lsu_bus_buffer.scala 151:148] + node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_477 = orr(_T_476) @[lsu_bus_buffer.scala 151:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_479 = and(_T_475, _T_478) @[lsu_bus_buffer.scala 151:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_482 = and(_T_479, _T_481) @[lsu_bus_buffer.scala 151:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_485 = orr(_T_484) @[lsu_bus_buffer.scala 151:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_487 = and(_T_483, _T_486) @[lsu_bus_buffer.scala 151:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_490 = and(_T_487, _T_489) @[lsu_bus_buffer.scala 151:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_493 = orr(_T_492) @[lsu_bus_buffer.scala 151:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_495 = and(_T_491, _T_494) @[lsu_bus_buffer.scala 151:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_498 = and(_T_495, _T_497) @[lsu_bus_buffer.scala 151:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_501 = orr(_T_500) @[lsu_bus_buffer.scala 151:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_503 = and(_T_499, _T_502) @[lsu_bus_buffer.scala 151:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_506 = and(_T_503, _T_505) @[lsu_bus_buffer.scala 151:148] + node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] + node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] + ld_byte_hitvecfn_hi[0] <= _T_404 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[lsu_bus_buffer.scala 151:23] + wire ibuf_addr : UInt<32> + ibuf_addr <= UInt<1>("h00") + wire ibuf_write : UInt<1> + ibuf_write <= UInt<1>("h00") + wire ibuf_valid : UInt<1> + ibuf_valid <= UInt<1>("h00") + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 156:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 156:64] + node _T_512 = eq(_T_510, _T_511) @[lsu_bus_buffer.scala 156:51] + node _T_513 = and(_T_512, ibuf_write) @[lsu_bus_buffer.scala 156:73] + node _T_514 = and(_T_513, ibuf_valid) @[lsu_bus_buffer.scala 156:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[lsu_bus_buffer.scala 156:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 157:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 157:64] + node _T_517 = eq(_T_515, _T_516) @[lsu_bus_buffer.scala 157:51] + node _T_518 = and(_T_517, ibuf_write) @[lsu_bus_buffer.scala 157:73] + node _T_519 = and(_T_518, ibuf_valid) @[lsu_bus_buffer.scala 157:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[lsu_bus_buffer.scala 157:99] + wire ibuf_byteen : UInt<4> + ibuf_byteen <= UInt<1>("h00") + node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] + node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_522 = and(_T_521, ibuf_byteen) @[lsu_bus_buffer.scala 161:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[lsu_bus_buffer.scala 161:69] + ld_byte_ibuf_hit_lo <= _T_523 @[lsu_bus_buffer.scala 161:23] + node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(_T_525, ibuf_byteen) @[lsu_bus_buffer.scala 162:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[lsu_bus_buffer.scala 162:69] + ld_byte_ibuf_hit_hi <= _T_527 @[lsu_bus_buffer.scala 162:23] + wire buf_data : UInt<32>[4] @[lsu_bus_buffer.scala 164:22] + buf_data[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + wire fwd_data : UInt<32> + fwd_data <= UInt<1>("h00") + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 167:81] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 167:81] + node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] + node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 167:81] + node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] + node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 167:81] + node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] + node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] + node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] + node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 168:81] + node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 168:81] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 168:81] + node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] + node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 168:81] + node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] + node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] + node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[lsu_bus_buffer.scala 169:86] + node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] + node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_559 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_560 = and(_T_558, _T_559) @[lsu_bus_buffer.scala 169:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[lsu_bus_buffer.scala 169:86] + node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] + node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_564 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_565 = and(_T_563, _T_564) @[lsu_bus_buffer.scala 169:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[lsu_bus_buffer.scala 169:86] + node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_569 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_570 = and(_T_568, _T_569) @[lsu_bus_buffer.scala 169:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[lsu_bus_buffer.scala 169:86] + node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] + node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_574 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_575 = and(_T_573, _T_574) @[lsu_bus_buffer.scala 169:91] + node _T_576 = or(_T_560, _T_565) @[lsu_bus_buffer.scala 169:123] + node _T_577 = or(_T_576, _T_570) @[lsu_bus_buffer.scala 169:123] + node _T_578 = or(_T_577, _T_575) @[lsu_bus_buffer.scala 169:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[lsu_bus_buffer.scala 170:60] + node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_583 = and(_T_581, _T_582) @[lsu_bus_buffer.scala 170:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[lsu_bus_buffer.scala 170:60] + node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] + node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_587 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_588 = and(_T_586, _T_587) @[lsu_bus_buffer.scala 170:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[lsu_bus_buffer.scala 170:60] + node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] + node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_592 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_593 = and(_T_591, _T_592) @[lsu_bus_buffer.scala 170:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[lsu_bus_buffer.scala 170:60] + node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] + node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_597 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_598 = and(_T_596, _T_597) @[lsu_bus_buffer.scala 170:65] + node _T_599 = or(_T_583, _T_588) @[lsu_bus_buffer.scala 170:97] + node _T_600 = or(_T_599, _T_593) @[lsu_bus_buffer.scala 170:97] + node _T_601 = or(_T_600, _T_598) @[lsu_bus_buffer.scala 170:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[lsu_bus_buffer.scala 171:60] + node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] + node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_605 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_606 = and(_T_604, _T_605) @[lsu_bus_buffer.scala 171:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[lsu_bus_buffer.scala 171:60] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_611 = and(_T_609, _T_610) @[lsu_bus_buffer.scala 171:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[lsu_bus_buffer.scala 171:60] + node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] + node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_615 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_616 = and(_T_614, _T_615) @[lsu_bus_buffer.scala 171:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[lsu_bus_buffer.scala 171:60] + node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_620 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_621 = and(_T_619, _T_620) @[lsu_bus_buffer.scala 171:65] + node _T_622 = or(_T_606, _T_611) @[lsu_bus_buffer.scala 171:97] + node _T_623 = or(_T_622, _T_616) @[lsu_bus_buffer.scala 171:97] + node _T_624 = or(_T_623, _T_621) @[lsu_bus_buffer.scala 171:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[lsu_bus_buffer.scala 172:60] + node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_629 = and(_T_627, _T_628) @[lsu_bus_buffer.scala 172:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[lsu_bus_buffer.scala 172:60] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_634 = and(_T_632, _T_633) @[lsu_bus_buffer.scala 172:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[lsu_bus_buffer.scala 172:60] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_639 = and(_T_637, _T_638) @[lsu_bus_buffer.scala 172:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[lsu_bus_buffer.scala 172:60] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_643 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_644 = and(_T_642, _T_643) @[lsu_bus_buffer.scala 172:65] + node _T_645 = or(_T_629, _T_634) @[lsu_bus_buffer.scala 172:97] + node _T_646 = or(_T_645, _T_639) @[lsu_bus_buffer.scala 172:97] + node _T_647 = or(_T_646, _T_644) @[lsu_bus_buffer.scala 172:97] + node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] + node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[lsu_bus_buffer.scala 173:32] + node _T_652 = or(_T_650, _T_651) @[lsu_bus_buffer.scala 172:103] + io.ld_fwddata_buf_lo <= _T_652 @[lsu_bus_buffer.scala 169:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[lsu_bus_buffer.scala 175:86] + node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] + node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_656 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_657 = and(_T_655, _T_656) @[lsu_bus_buffer.scala 175:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[lsu_bus_buffer.scala 175:86] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_662 = and(_T_660, _T_661) @[lsu_bus_buffer.scala 175:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[lsu_bus_buffer.scala 175:86] + node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] + node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_666 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_667 = and(_T_665, _T_666) @[lsu_bus_buffer.scala 175:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[lsu_bus_buffer.scala 175:86] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_672 = and(_T_670, _T_671) @[lsu_bus_buffer.scala 175:91] + node _T_673 = or(_T_657, _T_662) @[lsu_bus_buffer.scala 175:123] + node _T_674 = or(_T_673, _T_667) @[lsu_bus_buffer.scala 175:123] + node _T_675 = or(_T_674, _T_672) @[lsu_bus_buffer.scala 175:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[lsu_bus_buffer.scala 176:60] + node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] + node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_679 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_680 = and(_T_678, _T_679) @[lsu_bus_buffer.scala 176:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[lsu_bus_buffer.scala 176:60] + node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] + node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_684 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_685 = and(_T_683, _T_684) @[lsu_bus_buffer.scala 176:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[lsu_bus_buffer.scala 176:60] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] + node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_689 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_690 = and(_T_688, _T_689) @[lsu_bus_buffer.scala 176:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[lsu_bus_buffer.scala 176:60] + node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] + node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_694 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_695 = and(_T_693, _T_694) @[lsu_bus_buffer.scala 176:65] + node _T_696 = or(_T_680, _T_685) @[lsu_bus_buffer.scala 176:97] + node _T_697 = or(_T_696, _T_690) @[lsu_bus_buffer.scala 176:97] + node _T_698 = or(_T_697, _T_695) @[lsu_bus_buffer.scala 176:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[lsu_bus_buffer.scala 177:60] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] + node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_702 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_703 = and(_T_701, _T_702) @[lsu_bus_buffer.scala 177:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[lsu_bus_buffer.scala 177:60] + node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] + node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_707 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_708 = and(_T_706, _T_707) @[lsu_bus_buffer.scala 177:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[lsu_bus_buffer.scala 177:60] + node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_713 = and(_T_711, _T_712) @[lsu_bus_buffer.scala 177:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[lsu_bus_buffer.scala 177:60] + node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] + node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_717 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_718 = and(_T_716, _T_717) @[lsu_bus_buffer.scala 177:65] + node _T_719 = or(_T_703, _T_708) @[lsu_bus_buffer.scala 177:97] + node _T_720 = or(_T_719, _T_713) @[lsu_bus_buffer.scala 177:97] + node _T_721 = or(_T_720, _T_718) @[lsu_bus_buffer.scala 177:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[lsu_bus_buffer.scala 178:60] + node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] + node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_725 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_726 = and(_T_724, _T_725) @[lsu_bus_buffer.scala 178:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[lsu_bus_buffer.scala 178:60] + node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] + node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_730 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_731 = and(_T_729, _T_730) @[lsu_bus_buffer.scala 178:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[lsu_bus_buffer.scala 178:60] + node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] + node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_735 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_736 = and(_T_734, _T_735) @[lsu_bus_buffer.scala 178:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[lsu_bus_buffer.scala 178:60] + node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] + node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_740 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_741 = and(_T_739, _T_740) @[lsu_bus_buffer.scala 178:65] + node _T_742 = or(_T_726, _T_731) @[lsu_bus_buffer.scala 178:97] + node _T_743 = or(_T_742, _T_736) @[lsu_bus_buffer.scala 178:97] + node _T_744 = or(_T_743, _T_741) @[lsu_bus_buffer.scala 178:97] + node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] + node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 179:32] + node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 178:103] + io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 175:24] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 181:77] + node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = or(_T_750, _T_751) @[Mux.scala 27:72] + node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_r <= _T_754 @[Mux.scala 27:72] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 186:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[lsu_bus_buffer.scala 186:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 187:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[lsu_bus_buffer.scala 187:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[lsu_bus_buffer.scala 187:60] + node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 188:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[lsu_bus_buffer.scala 188:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[lsu_bus_buffer.scala 188:60] + node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 189:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[lsu_bus_buffer.scala 189:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[lsu_bus_buffer.scala 189:60] + node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] + node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_762, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_766, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = or(_T_769, _T_770) @[Mux.scala 27:72] + node _T_774 = or(_T_773, _T_771) @[Mux.scala 27:72] + node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] + wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 191:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[lsu_bus_buffer.scala 191:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 192:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[lsu_bus_buffer.scala 192:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[lsu_bus_buffer.scala 192:50] + node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 193:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[lsu_bus_buffer.scala 193:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[lsu_bus_buffer.scala 193:50] + node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 194:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[lsu_bus_buffer.scala 194:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[lsu_bus_buffer.scala 194:50] + node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_783, _T_785, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_787, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = or(_T_790, _T_791) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_792) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] + wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 196:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[lsu_bus_buffer.scala 196:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 197:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[lsu_bus_buffer.scala 197:24] + node _T_801 = bits(io.store_data_r, 31, 24) @[lsu_bus_buffer.scala 197:64] + node _T_802 = cat(UInt<24>("h00"), _T_801) @[Cat.scala 29:58] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 198:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[lsu_bus_buffer.scala 198:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[lsu_bus_buffer.scala 198:63] + node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 199:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[lsu_bus_buffer.scala 199:24] + node _T_809 = bits(io.store_data_r, 31, 8) @[lsu_bus_buffer.scala 199:62] + node _T_810 = cat(UInt<8>("h00"), _T_809) @[Cat.scala 29:58] + node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_804, _T_806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_808, _T_810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = or(_T_811, _T_812) @[Mux.scala 27:72] + node _T_816 = or(_T_815, _T_813) @[Mux.scala 27:72] + node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] + wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] + store_data_hi_r <= _T_817 @[Mux.scala 27:72] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 201:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[lsu_bus_buffer.scala 201:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 202:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[lsu_bus_buffer.scala 202:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[lsu_bus_buffer.scala 202:52] + node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 203:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[lsu_bus_buffer.scala 203:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[lsu_bus_buffer.scala 203:52] + node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 204:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[lsu_bus_buffer.scala 204:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[lsu_bus_buffer.scala 204:52] + node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] + node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_834 = mux(_T_825, _T_827, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_835 = mux(_T_829, _T_831, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_836 = or(_T_832, _T_833) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] + wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] + store_data_lo_r <= _T_838 @[Mux.scala 27:72] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[lsu_bus_buffer.scala 207:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[lsu_bus_buffer.scala 207:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[lsu_bus_buffer.scala 207:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 208:72] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[lsu_bus_buffer.scala 208:79] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[lsu_bus_buffer.scala 209:45] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[lsu_bus_buffer.scala 209:31] + node _T_845 = mux(io.lsu_pkt_r.bits.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = mux(io.lsu_pkt_r.bits.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_847 = mux(io.lsu_pkt_r.bits.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_848 = or(_T_845, _T_846) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] + wire is_aligned_r : UInt<1> @[Mux.scala 27:72] + is_aligned_r <= _T_849 @[Mux.scala 27:72] + node _T_850 = or(io.lsu_pkt_r.bits.load, io.no_word_merge_r) @[lsu_bus_buffer.scala 211:60] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[lsu_bus_buffer.scala 211:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 211:84] + node ibuf_byp = and(_T_851, _T_852) @[lsu_bus_buffer.scala 211:82] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 212:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[lsu_bus_buffer.scala 212:56] + node ibuf_wr_en = and(_T_853, _T_854) @[lsu_bus_buffer.scala 212:54] + wire ibuf_drain_vld : UInt<1> + ibuf_drain_vld <= UInt<1>("h00") + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 214:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[lsu_bus_buffer.scala 214:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 214:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 215:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[lsu_bus_buffer.scala 215:42] + node _T_859 = and(_T_858, ibuf_valid) @[lsu_bus_buffer.scala 215:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 215:112] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 215:137] + node _T_862 = neq(_T_860, _T_861) @[lsu_bus_buffer.scala 215:120] + node _T_863 = or(io.lsu_pkt_m.bits.load, _T_862) @[lsu_bus_buffer.scala 215:100] + node ibuf_force_drain = and(_T_859, _T_863) @[lsu_bus_buffer.scala 215:74] + wire ibuf_sideeffect : UInt<1> + ibuf_sideeffect <= UInt<1>("h00") + wire ibuf_timer : UInt<3> + ibuf_timer <= UInt<1>("h00") + wire ibuf_merge_en : UInt<1> + ibuf_merge_en <= UInt<1>("h00") + wire ibuf_merge_in : UInt<1> + ibuf_merge_in <= UInt<1>("h00") + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 220:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[lsu_bus_buffer.scala 220:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 220:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[lsu_bus_buffer.scala 220:82] + node _T_868 = and(_T_865, _T_867) @[lsu_bus_buffer.scala 220:80] + node _T_869 = or(_T_868, ibuf_byp) @[lsu_bus_buffer.scala 221:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[lsu_bus_buffer.scala 221:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[lsu_bus_buffer.scala 221:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 221:55] + node _T_873 = or(_T_871, _T_872) @[lsu_bus_buffer.scala 221:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[lsu_bus_buffer.scala 221:67] + node _T_875 = and(ibuf_valid, _T_874) @[lsu_bus_buffer.scala 220:32] + ibuf_drain_vld <= _T_875 @[lsu_bus_buffer.scala 220:18] + wire ibuf_tag : UInt<2> + ibuf_tag <= UInt<1>("h00") + wire WrPtr1_r : UInt<2> + WrPtr1_r <= UInt<1>("h00") + wire WrPtr0_r : UInt<2> + WrPtr0_r <= UInt<1>("h00") + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 226:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[lsu_bus_buffer.scala 226:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[lsu_bus_buffer.scala 226:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 229:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 230:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[lsu_bus_buffer.scala 230:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 230:95] + node _T_881 = or(_T_879, _T_880) @[lsu_bus_buffer.scala 230:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 231:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 231:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[lsu_bus_buffer.scala 231:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[lsu_bus_buffer.scala 230:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 235:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 235:45] + node _T_888 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 235:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[lsu_bus_buffer.scala 235:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[lsu_bus_buffer.scala 236:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 236:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[lsu_bus_buffer.scala 236:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[lsu_bus_buffer.scala 234:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 235:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 235:45] + node _T_897 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 235:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[lsu_bus_buffer.scala 235:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[lsu_bus_buffer.scala 236:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 236:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[lsu_bus_buffer.scala 236:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[lsu_bus_buffer.scala 234:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 235:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 235:45] + node _T_906 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 235:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[lsu_bus_buffer.scala 235:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[lsu_bus_buffer.scala 236:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 236:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[lsu_bus_buffer.scala 236:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[lsu_bus_buffer.scala 234:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 235:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 235:45] + node _T_915 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 235:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[lsu_bus_buffer.scala 235:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[lsu_bus_buffer.scala 236:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 236:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[lsu_bus_buffer.scala 236:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[lsu_bus_buffer.scala 234:46] + node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] + node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] + node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 237:60] + node _T_924 = bits(_T_923, 0, 0) @[lsu_bus_buffer.scala 237:81] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 237:95] + node _T_926 = tail(_T_925, 1) @[lsu_bus_buffer.scala 237:95] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[lsu_bus_buffer.scala 237:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[lsu_bus_buffer.scala 237:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 239:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 239:54] + node _T_930 = and(_T_929, ibuf_valid) @[lsu_bus_buffer.scala 239:80] + node _T_931 = and(_T_930, ibuf_write) @[lsu_bus_buffer.scala 239:93] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_buffer.scala 239:122] + node _T_933 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 239:142] + node _T_934 = eq(_T_932, _T_933) @[lsu_bus_buffer.scala 239:129] + node _T_935 = and(_T_931, _T_934) @[lsu_bus_buffer.scala 239:106] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 239:152] + node _T_937 = and(_T_935, _T_936) @[lsu_bus_buffer.scala 239:150] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 239:175] + node _T_939 = and(_T_937, _T_938) @[lsu_bus_buffer.scala 239:173] + ibuf_merge_en <= _T_939 @[lsu_bus_buffer.scala 239:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 240:20] + ibuf_merge_in <= _T_940 @[lsu_bus_buffer.scala 240:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[lsu_bus_buffer.scala 241:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 241:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 241:114] + node _T_945 = or(_T_943, _T_944) @[lsu_bus_buffer.scala 241:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 241:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[lsu_bus_buffer.scala 241:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[lsu_bus_buffer.scala 241:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 241:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 241:114] + node _T_952 = or(_T_950, _T_951) @[lsu_bus_buffer.scala 241:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 241:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[lsu_bus_buffer.scala 241:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[lsu_bus_buffer.scala 241:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 241:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 241:114] + node _T_959 = or(_T_957, _T_958) @[lsu_bus_buffer.scala 241:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 241:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[lsu_bus_buffer.scala 241:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[lsu_bus_buffer.scala 241:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 241:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 241:114] + node _T_966 = or(_T_964, _T_965) @[lsu_bus_buffer.scala 241:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 241:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[lsu_bus_buffer.scala 241:48] + node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] + node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] + node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[lsu_bus_buffer.scala 242:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 242:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 242:118] + node _T_975 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 242:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[lsu_bus_buffer.scala 242:81] + node _T_977 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 242:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[lsu_bus_buffer.scala 242:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[lsu_bus_buffer.scala 242:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 242:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 242:118] + node _T_983 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 242:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[lsu_bus_buffer.scala 242:81] + node _T_985 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 242:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[lsu_bus_buffer.scala 242:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[lsu_bus_buffer.scala 242:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 242:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 242:118] + node _T_991 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 242:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[lsu_bus_buffer.scala 242:81] + node _T_993 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 242:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[lsu_bus_buffer.scala 242:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[lsu_bus_buffer.scala 242:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 242:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 242:118] + node _T_999 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 242:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[lsu_bus_buffer.scala 242:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 242:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[lsu_bus_buffer.scala 242:45] + node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] + node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] + node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[lsu_bus_buffer.scala 244:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 244:93] + node _T_1007 = and(_T_1005, _T_1006) @[lsu_bus_buffer.scala 244:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 244:54] + _T_1008 <= _T_1007 @[lsu_bus_buffer.scala 244:54] + ibuf_valid <= _T_1008 @[lsu_bus_buffer.scala 244:14] + reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_tag <= _T_1009 @[lsu_bus_buffer.scala 245:12] + reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_dual : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dual <= io.ldst_dual_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_samedw : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_samedw <= ldst_samedw_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_nomerge : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_nomerge <= io.no_dword_merge_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1010 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_sideeffect <= _T_1010 @[lsu_bus_buffer.scala 250:19] + reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_unsign <= io.lsu_pkt_r.bits.unsign @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1011 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1011 <= io.lsu_pkt_r.bits.store @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_write <= _T_1011 @[lsu_bus_buffer.scala 252:14] + reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr of rvclkhdr @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1012 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1012 <= ibuf_addr_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 254:13] + reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 255:15] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1014 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1014 <= ibuf_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 256:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 257:55] + _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 257:55] + ibuf_timer <= _T_1015 @[lsu_bus_buffer.scala 257:14] + wire buf_numvld_wrcmd_any : UInt<4> + buf_numvld_wrcmd_any <= UInt<1>("h00") + wire buf_numvld_cmd_any : UInt<4> + buf_numvld_cmd_any <= UInt<1>("h00") + wire obuf_wr_timer : UInt<3> + obuf_wr_timer <= UInt<1>("h00") + wire buf_nomerge : UInt<1>[4] @[lsu_bus_buffer.scala 261:25] + buf_nomerge[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + wire buf_sideeffect : UInt<4> + buf_sideeffect <= UInt<1>("h00") + wire obuf_force_wr_en : UInt<1> + obuf_force_wr_en <= UInt<1>("h00") + wire obuf_wr_en : UInt<1> + obuf_wr_en <= UInt<1>("h00") + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 267:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 267:72] + node _T_1018 = and(_T_1016, _T_1017) @[lsu_bus_buffer.scala 267:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 267:97] + node _T_1020 = and(_T_1018, _T_1019) @[lsu_bus_buffer.scala 267:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:5] + node _T_1022 = and(_T_1020, _T_1021) @[lsu_bus_buffer.scala 267:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 268:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 268:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 268:114] + node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1030 = mux(_T_1026, buf_nomerge[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1031 = or(_T_1027, _T_1028) @[Mux.scala 27:72] + node _T_1032 = or(_T_1031, _T_1029) @[Mux.scala 27:72] + node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] + wire _T_1034 : UInt<1> @[Mux.scala 27:72] + _T_1034 <= _T_1033 @[Mux.scala 27:72] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:31] + node _T_1036 = and(_T_1022, _T_1035) @[lsu_bus_buffer.scala 268:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 269:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 269:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 269:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 269:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 269:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 269:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 269:111] + node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1048 = mux(_T_1043, _T_1044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1049 = or(_T_1045, _T_1046) @[Mux.scala 27:72] + node _T_1050 = or(_T_1049, _T_1047) @[Mux.scala 27:72] + node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] + wire _T_1052 : UInt<1> @[Mux.scala 27:72] + _T_1052 <= _T_1051 @[Mux.scala 27:72] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:5] + node _T_1054 = and(_T_1036, _T_1053) @[lsu_bus_buffer.scala 268:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[lsu_bus_buffer.scala 269:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[lsu_bus_buffer.scala 270:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 270:95] + node _T_1058 = and(_T_1056, _T_1057) @[lsu_bus_buffer.scala 270:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 270:123] + node _T_1060 = tail(_T_1059, 1) @[lsu_bus_buffer.scala 270:123] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[lsu_bus_buffer.scala 270:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[lsu_bus_buffer.scala 270:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[lsu_bus_buffer.scala 271:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:60] + node _T_1065 = and(_T_1063, _T_1064) @[lsu_bus_buffer.scala 271:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 271:93] + node _T_1067 = and(_T_1065, _T_1066) @[lsu_bus_buffer.scala 271:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 271:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 271:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 271:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 271:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = or(_T_1077, _T_1078) @[Mux.scala 27:72] + node _T_1082 = or(_T_1081, _T_1079) @[Mux.scala 27:72] + node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] + wire _T_1084 : UInt<30> @[Mux.scala 27:72] + _T_1084 <= _T_1083 @[Mux.scala 27:72] + node _T_1085 = neq(_T_1068, _T_1084) @[lsu_bus_buffer.scala 271:123] + node _T_1086 = and(_T_1067, _T_1085) @[lsu_bus_buffer.scala 271:101] + obuf_force_wr_en <= _T_1086 @[lsu_bus_buffer.scala 271:20] + wire buf_numvld_pend_any : UInt<4> + buf_numvld_pend_any <= UInt<1>("h00") + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 273:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[lsu_bus_buffer.scala 273:31] + node _T_1089 = eq(io.lsu_pkt_r.bits.store, UInt<1>("h00")) @[lsu_bus_buffer.scala 273:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[lsu_bus_buffer.scala 273:89] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[lsu_bus_buffer.scala 273:61] + wire bus_sideeffect_pend : UInt<1> + bus_sideeffect_pend <= UInt<1>("h00") + wire found_cmdptr0 : UInt<1> + found_cmdptr0 <= UInt<1>("h00") + wire buf_cmd_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 276:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + wire buf_dual : UInt<1>[4] @[lsu_bus_buffer.scala 278:22] + buf_dual[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + wire buf_samedw : UInt<1>[4] @[lsu_bus_buffer.scala 280:24] + buf_samedw[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + wire found_cmdptr1 : UInt<1> + found_cmdptr1 <= UInt<1>("h00") + wire bus_cmd_ready : UInt<1> + bus_cmd_ready <= UInt<1>("h00") + wire obuf_valid : UInt<1> + obuf_valid <= UInt<1>("h00") + wire obuf_nosend : UInt<1> + obuf_nosend <= UInt<1>("h00") + wire bus_addr_match_pending : UInt<1> + bus_addr_match_pending <= UInt<1>("h00") + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[lsu_bus_buffer.scala 289:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[lsu_bus_buffer.scala 289:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[lsu_bus_buffer.scala 289:52] + node _T_1094 = and(_T_1091, _T_1093) @[lsu_bus_buffer.scala 289:50] + node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1099 = mux(_T_1095, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_1096, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1097, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_1098, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = or(_T_1099, _T_1100) @[Mux.scala 27:72] + node _T_1104 = or(_T_1103, _T_1101) @[Mux.scala 27:72] + node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] + wire _T_1106 : UInt<3> @[Mux.scala 27:72] + _T_1106 <= _T_1105 @[Mux.scala 27:72] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[lsu_bus_buffer.scala 290:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[lsu_bus_buffer.scala 290:47] + node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1113 = bits(_T_1111, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1115 = bits(_T_1111, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1117 = bits(_T_1111, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1119 = bits(_T_1111, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1120 = mux(_T_1112, _T_1113, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1116, _T_1117, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1118, _T_1119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = or(_T_1120, _T_1121) @[Mux.scala 27:72] + node _T_1125 = or(_T_1124, _T_1122) @[Mux.scala 27:72] + node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] + wire _T_1127 : UInt<1> @[Mux.scala 27:72] + _T_1127 <= _T_1126 @[Mux.scala 27:72] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:23] + node _T_1129 = and(_T_1108, _T_1128) @[lsu_bus_buffer.scala 291:21] + node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1131 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1133 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1135 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1137 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1138 = mux(_T_1130, _T_1131, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1139 = mux(_T_1132, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1140 = mux(_T_1134, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1141 = mux(_T_1136, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1142 = or(_T_1138, _T_1139) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1140) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] + wire _T_1145 : UInt<1> @[Mux.scala 27:72] + _T_1145 <= _T_1144 @[Mux.scala 27:72] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[lsu_bus_buffer.scala 291:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:105] + node _T_1148 = and(_T_1129, _T_1147) @[lsu_bus_buffer.scala 291:103] + node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] + node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] + node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1153 = bits(_T_1151, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1155 = bits(_T_1151, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1157 = bits(_T_1151, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1159 = bits(_T_1151, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1160 = mux(_T_1152, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1161 = mux(_T_1154, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1162 = mux(_T_1156, _T_1157, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1163 = mux(_T_1158, _T_1159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1164 = or(_T_1160, _T_1161) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1162) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1163) @[Mux.scala 27:72] + wire _T_1167 : UInt<1> @[Mux.scala 27:72] + _T_1167 <= _T_1166 @[Mux.scala 27:72] + node _T_1168 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1170 = cat(_T_1169, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1172 = bits(_T_1170, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1174 = bits(_T_1170, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1176 = bits(_T_1170, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1178 = bits(_T_1170, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1179 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1180 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1181 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1182 = mux(_T_1177, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1183 = or(_T_1179, _T_1180) @[Mux.scala 27:72] + node _T_1184 = or(_T_1183, _T_1181) @[Mux.scala 27:72] + node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] + wire _T_1186 : UInt<1> @[Mux.scala 27:72] + _T_1186 <= _T_1185 @[Mux.scala 27:72] + node _T_1187 = and(_T_1167, _T_1186) @[lsu_bus_buffer.scala 292:77] + node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1189 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1191 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1193 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1195 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1194, _T_1195, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = or(_T_1196, _T_1197) @[Mux.scala 27:72] + node _T_1201 = or(_T_1200, _T_1198) @[Mux.scala 27:72] + node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] + wire _T_1203 : UInt<1> @[Mux.scala 27:72] + _T_1203 <= _T_1202 @[Mux.scala 27:72] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:150] + node _T_1205 = and(_T_1187, _T_1204) @[lsu_bus_buffer.scala 292:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[lsu_bus_buffer.scala 292:181] + node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] + node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] + node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] + node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1212 = bits(_T_1210, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1214 = bits(_T_1210, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1216 = bits(_T_1210, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1218 = bits(_T_1210, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1219 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = or(_T_1219, _T_1220) @[Mux.scala 27:72] + node _T_1224 = or(_T_1223, _T_1221) @[Mux.scala 27:72] + node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] + wire _T_1226 : UInt<1> @[Mux.scala 27:72] + _T_1226 <= _T_1225 @[Mux.scala 27:72] + node _T_1227 = or(_T_1207, _T_1226) @[lsu_bus_buffer.scala 292:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[lsu_bus_buffer.scala 292:269] + node _T_1229 = and(_T_1148, _T_1228) @[lsu_bus_buffer.scala 291:164] + node _T_1230 = or(_T_1094, _T_1229) @[lsu_bus_buffer.scala 289:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[lsu_bus_buffer.scala 293:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[lsu_bus_buffer.scala 293:60] + node _T_1234 = and(_T_1230, _T_1233) @[lsu_bus_buffer.scala 293:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:77] + node _T_1236 = and(_T_1234, _T_1235) @[lsu_bus_buffer.scala 293:75] + node _T_1237 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:94] + node _T_1238 = and(_T_1236, _T_1237) @[lsu_bus_buffer.scala 293:92] + node _T_1239 = and(_T_1238, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 293:118] + obuf_wr_en <= _T_1239 @[lsu_bus_buffer.scala 289:14] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_1240 = and(obuf_valid, obuf_nosend) @[lsu_bus_buffer.scala 296:47] + node _T_1241 = or(bus_cmd_sent, _T_1240) @[lsu_bus_buffer.scala 296:33] + node _T_1242 = eq(obuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 296:65] + node _T_1243 = and(_T_1241, _T_1242) @[lsu_bus_buffer.scala 296:63] + node _T_1244 = and(_T_1243, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 296:77] + node obuf_rst = or(_T_1244, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 296:98] + node _T_1245 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1246 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1247 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1248 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1249 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1250 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1251 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1252 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1253 = mux(_T_1245, _T_1246, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1254 = mux(_T_1247, _T_1248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1255 = mux(_T_1249, _T_1250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1256 = mux(_T_1251, _T_1252, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1257 = or(_T_1253, _T_1254) @[Mux.scala 27:72] + node _T_1258 = or(_T_1257, _T_1255) @[Mux.scala 27:72] + node _T_1259 = or(_T_1258, _T_1256) @[Mux.scala 27:72] + wire _T_1260 : UInt<1> @[Mux.scala 27:72] + _T_1260 <= _T_1259 @[Mux.scala 27:72] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1260) @[lsu_bus_buffer.scala 297:26] + node _T_1261 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1262 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1263 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1264 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1265 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1266 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1267 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1268 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1269 = mux(_T_1261, _T_1262, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1270 = mux(_T_1263, _T_1264, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1271 = mux(_T_1265, _T_1266, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1272 = mux(_T_1267, _T_1268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1273 = or(_T_1269, _T_1270) @[Mux.scala 27:72] + node _T_1274 = or(_T_1273, _T_1271) @[Mux.scala 27:72] + node _T_1275 = or(_T_1274, _T_1272) @[Mux.scala 27:72] + wire _T_1276 : UInt<1> @[Mux.scala 27:72] + _T_1276 <= _T_1275 @[Mux.scala 27:72] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1276) @[lsu_bus_buffer.scala 298:31] + node _T_1277 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1278 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1279 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1280 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1281 = mux(_T_1277, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1282 = mux(_T_1278, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1283 = mux(_T_1279, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1284 = mux(_T_1280, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1285 = or(_T_1281, _T_1282) @[Mux.scala 27:72] + node _T_1286 = or(_T_1285, _T_1283) @[Mux.scala 27:72] + node _T_1287 = or(_T_1286, _T_1284) @[Mux.scala 27:72] + wire _T_1288 : UInt<32> @[Mux.scala 27:72] + _T_1288 <= _T_1287 @[Mux.scala 27:72] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1288) @[lsu_bus_buffer.scala 299:25] + wire buf_sz : UInt<2>[4] @[lsu_bus_buffer.scala 300:20] + buf_sz[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + node _T_1289 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_1290 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1291 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1292 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1293 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1294 = mux(_T_1290, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1295 = mux(_T_1291, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1296 = mux(_T_1292, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1297 = mux(_T_1293, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1298 = or(_T_1294, _T_1295) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1296) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1297) @[Mux.scala 27:72] + wire _T_1301 : UInt<2> @[Mux.scala 27:72] + _T_1301 <= _T_1300 @[Mux.scala 27:72] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1289, _T_1301) @[lsu_bus_buffer.scala 302:23] + wire obuf_merge_en : UInt<1> + obuf_merge_en <= UInt<1>("h00") + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 305:25] + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 307:25] + wire obuf_cmd_done : UInt<1> + obuf_cmd_done <= UInt<1>("h00") + wire bus_wcmd_sent : UInt<1> + bus_wcmd_sent <= UInt<1>("h00") + node _T_1302 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 310:39] + node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[lsu_bus_buffer.scala 310:26] + node _T_1304 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 310:68] + node obuf_cmd_done_in = and(_T_1303, _T_1304) @[lsu_bus_buffer.scala 310:51] + wire obuf_data_done : UInt<1> + obuf_data_done <= UInt<1>("h00") + wire bus_wdata_sent : UInt<1> + bus_wdata_sent <= UInt<1>("h00") + node _T_1305 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 313:40] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[lsu_bus_buffer.scala 313:27] + node _T_1307 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 313:70] + node obuf_data_done_in = and(_T_1306, _T_1307) @[lsu_bus_buffer.scala 313:52] + node _T_1308 = bits(obuf_sz_in, 1, 0) @[lsu_bus_buffer.scala 314:67] + node _T_1309 = eq(_T_1308, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:72] + node _T_1310 = bits(obuf_sz_in, 0, 0) @[lsu_bus_buffer.scala 314:92] + node _T_1311 = bits(obuf_addr_in, 0, 0) @[lsu_bus_buffer.scala 314:111] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:98] + node _T_1313 = and(_T_1310, _T_1312) @[lsu_bus_buffer.scala 314:96] + node _T_1314 = or(_T_1309, _T_1313) @[lsu_bus_buffer.scala 314:79] + node _T_1315 = bits(obuf_sz_in, 1, 1) @[lsu_bus_buffer.scala 314:129] + node _T_1316 = bits(obuf_addr_in, 1, 0) @[lsu_bus_buffer.scala 314:147] + node _T_1317 = orr(_T_1316) @[lsu_bus_buffer.scala 314:153] + node _T_1318 = eq(_T_1317, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:134] + node _T_1319 = and(_T_1315, _T_1318) @[lsu_bus_buffer.scala 314:132] + node _T_1320 = or(_T_1314, _T_1319) @[lsu_bus_buffer.scala 314:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1320) @[lsu_bus_buffer.scala 314:28] + wire obuf_nosend_in : UInt<1> + obuf_nosend_in <= UInt<1>("h00") + wire obuf_rdrsp_pend : UInt<1> + obuf_rdrsp_pend <= UInt<1>("h00") + wire bus_rsp_read : UInt<1> + bus_rsp_read <= UInt<1>("h00") + wire bus_rsp_read_tag : UInt<3> + bus_rsp_read_tag <= UInt<1>("h00") + wire obuf_rdrsp_tag : UInt<3> + obuf_rdrsp_tag <= UInt<1>("h00") + wire obuf_write : UInt<1> + obuf_write <= UInt<1>("h00") + node _T_1321 = eq(obuf_nosend_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:45] + node _T_1322 = and(obuf_wr_en, _T_1321) @[lsu_bus_buffer.scala 322:43] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:30] + node _T_1324 = and(_T_1323, obuf_rdrsp_pend) @[lsu_bus_buffer.scala 322:62] + node _T_1325 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 322:117] + node _T_1326 = and(bus_rsp_read, _T_1325) @[lsu_bus_buffer.scala 322:97] + node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:82] + node _T_1328 = and(_T_1324, _T_1327) @[lsu_bus_buffer.scala 322:80] + node _T_1329 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:157] + node _T_1330 = and(bus_cmd_sent, _T_1329) @[lsu_bus_buffer.scala 322:155] + node _T_1331 = or(_T_1328, _T_1330) @[lsu_bus_buffer.scala 322:139] + node _T_1332 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:173] + node obuf_rdrsp_pend_in = and(_T_1331, _T_1332) @[lsu_bus_buffer.scala 322:171] + node obuf_rdrsp_pend_en = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 323:47] + wire obuf_tag0 : UInt<3> + obuf_tag0 <= UInt<1>("h00") + node _T_1333 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 325:46] + node _T_1334 = and(bus_cmd_sent, _T_1333) @[lsu_bus_buffer.scala 325:44] + node obuf_rdrsp_tag_in = mux(_T_1334, obuf_tag0, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 325:30] + wire obuf_addr : UInt<32> + obuf_addr <= UInt<1>("h00") + wire obuf_sideeffect : UInt<1> + obuf_sideeffect <= UInt<1>("h00") + node _T_1335 = bits(obuf_addr_in, 31, 3) @[lsu_bus_buffer.scala 328:34] + node _T_1336 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 328:52] + node _T_1337 = eq(_T_1335, _T_1336) @[lsu_bus_buffer.scala 328:40] + node _T_1338 = and(_T_1337, obuf_aligned_in) @[lsu_bus_buffer.scala 328:60] + node _T_1339 = eq(obuf_sideeffect, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:80] + node _T_1340 = and(_T_1338, _T_1339) @[lsu_bus_buffer.scala 328:78] + node _T_1341 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:99] + node _T_1342 = and(_T_1340, _T_1341) @[lsu_bus_buffer.scala 328:97] + node _T_1343 = eq(obuf_write_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:113] + node _T_1344 = and(_T_1342, _T_1343) @[lsu_bus_buffer.scala 328:111] + node _T_1345 = eq(io.tlu_busbuff.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:130] + node _T_1346 = and(_T_1344, _T_1345) @[lsu_bus_buffer.scala 328:128] + node _T_1347 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 329:20] + node _T_1348 = and(obuf_valid, _T_1347) @[lsu_bus_buffer.scala 329:18] + node _T_1349 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 329:90] + node _T_1350 = and(bus_rsp_read, _T_1349) @[lsu_bus_buffer.scala 329:70] + node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[lsu_bus_buffer.scala 329:55] + node _T_1352 = and(obuf_rdrsp_pend, _T_1351) @[lsu_bus_buffer.scala 329:53] + node _T_1353 = or(_T_1348, _T_1352) @[lsu_bus_buffer.scala 329:34] + node _T_1354 = and(_T_1346, _T_1353) @[lsu_bus_buffer.scala 328:177] + obuf_nosend_in <= _T_1354 @[lsu_bus_buffer.scala 328:18] + node _T_1355 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 330:60] + node _T_1356 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1357 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] + node _T_1358 = mux(_T_1355, _T_1356, _T_1357) @[lsu_bus_buffer.scala 330:46] + node _T_1359 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1360 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1361 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1362 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1363 = mux(_T_1359, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1364 = mux(_T_1360, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1365 = mux(_T_1361, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1362, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = or(_T_1363, _T_1364) @[Mux.scala 27:72] + node _T_1368 = or(_T_1367, _T_1365) @[Mux.scala 27:72] + node _T_1369 = or(_T_1368, _T_1366) @[Mux.scala 27:72] + wire _T_1370 : UInt<32> @[Mux.scala 27:72] + _T_1370 <= _T_1369 @[Mux.scala 27:72] + node _T_1371 = bits(_T_1370, 2, 2) @[lsu_bus_buffer.scala 331:36] + node _T_1372 = bits(_T_1371, 0, 0) @[lsu_bus_buffer.scala 331:46] + node _T_1373 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1374 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1375 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1376 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1377 = mux(_T_1373, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1378 = mux(_T_1374, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1379 = mux(_T_1375, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1376, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = or(_T_1377, _T_1378) @[Mux.scala 27:72] + node _T_1382 = or(_T_1381, _T_1379) @[Mux.scala 27:72] + node _T_1383 = or(_T_1382, _T_1380) @[Mux.scala 27:72] + wire _T_1384 : UInt<4> @[Mux.scala 27:72] + _T_1384 <= _T_1383 @[Mux.scala 27:72] + node _T_1385 = cat(_T_1384, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1386 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1387 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1388 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1389 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1390 = mux(_T_1386, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1391 = mux(_T_1387, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1392 = mux(_T_1388, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1393 = mux(_T_1389, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1394 = or(_T_1390, _T_1391) @[Mux.scala 27:72] + node _T_1395 = or(_T_1394, _T_1392) @[Mux.scala 27:72] + node _T_1396 = or(_T_1395, _T_1393) @[Mux.scala 27:72] + wire _T_1397 : UInt<4> @[Mux.scala 27:72] + _T_1397 <= _T_1396 @[Mux.scala 27:72] + node _T_1398 = cat(UInt<4>("h00"), _T_1397) @[Cat.scala 29:58] + node _T_1399 = mux(_T_1372, _T_1385, _T_1398) @[lsu_bus_buffer.scala 331:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1358, _T_1399) @[lsu_bus_buffer.scala 330:28] + node _T_1400 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 332:60] + node _T_1401 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1402 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] + node _T_1403 = mux(_T_1400, _T_1401, _T_1402) @[lsu_bus_buffer.scala 332:46] + node _T_1404 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1405 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1406 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1407 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1408 = mux(_T_1404, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1409 = mux(_T_1405, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1410 = mux(_T_1406, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1411 = mux(_T_1407, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1412 = or(_T_1408, _T_1409) @[Mux.scala 27:72] + node _T_1413 = or(_T_1412, _T_1410) @[Mux.scala 27:72] + node _T_1414 = or(_T_1413, _T_1411) @[Mux.scala 27:72] + wire _T_1415 : UInt<32> @[Mux.scala 27:72] + _T_1415 <= _T_1414 @[Mux.scala 27:72] + node _T_1416 = bits(_T_1415, 2, 2) @[lsu_bus_buffer.scala 333:36] + node _T_1417 = bits(_T_1416, 0, 0) @[lsu_bus_buffer.scala 333:46] + node _T_1418 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1419 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1420 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1421 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1422 = mux(_T_1418, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1423 = mux(_T_1419, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1424 = mux(_T_1420, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1425 = mux(_T_1421, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = or(_T_1422, _T_1423) @[Mux.scala 27:72] + node _T_1427 = or(_T_1426, _T_1424) @[Mux.scala 27:72] + node _T_1428 = or(_T_1427, _T_1425) @[Mux.scala 27:72] + wire _T_1429 : UInt<4> @[Mux.scala 27:72] + _T_1429 <= _T_1428 @[Mux.scala 27:72] + node _T_1430 = cat(_T_1429, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1431 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1432 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1433 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1434 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1435 = mux(_T_1431, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1436 = mux(_T_1432, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1437 = mux(_T_1433, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1438 = mux(_T_1434, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1439 = or(_T_1435, _T_1436) @[Mux.scala 27:72] + node _T_1440 = or(_T_1439, _T_1437) @[Mux.scala 27:72] + node _T_1441 = or(_T_1440, _T_1438) @[Mux.scala 27:72] + wire _T_1442 : UInt<4> @[Mux.scala 27:72] + _T_1442 <= _T_1441 @[Mux.scala 27:72] + node _T_1443 = cat(UInt<4>("h00"), _T_1442) @[Cat.scala 29:58] + node _T_1444 = mux(_T_1417, _T_1430, _T_1443) @[lsu_bus_buffer.scala 333:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1403, _T_1444) @[lsu_bus_buffer.scala 332:28] + node _T_1445 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 335:58] + node _T_1446 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1447 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] + node _T_1448 = mux(_T_1445, _T_1446, _T_1447) @[lsu_bus_buffer.scala 335:44] + node _T_1449 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1450 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1451 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1452 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1453 = mux(_T_1449, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1454 = mux(_T_1450, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1455 = mux(_T_1451, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = mux(_T_1452, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1457 = or(_T_1453, _T_1454) @[Mux.scala 27:72] + node _T_1458 = or(_T_1457, _T_1455) @[Mux.scala 27:72] + node _T_1459 = or(_T_1458, _T_1456) @[Mux.scala 27:72] + wire _T_1460 : UInt<32> @[Mux.scala 27:72] + _T_1460 <= _T_1459 @[Mux.scala 27:72] + node _T_1461 = bits(_T_1460, 2, 2) @[lsu_bus_buffer.scala 336:36] + node _T_1462 = bits(_T_1461, 0, 0) @[lsu_bus_buffer.scala 336:46] + node _T_1463 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1464 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1465 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1466 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1467 = mux(_T_1463, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1468 = mux(_T_1464, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1469 = mux(_T_1465, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1466, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = or(_T_1467, _T_1468) @[Mux.scala 27:72] + node _T_1472 = or(_T_1471, _T_1469) @[Mux.scala 27:72] + node _T_1473 = or(_T_1472, _T_1470) @[Mux.scala 27:72] + wire _T_1474 : UInt<32> @[Mux.scala 27:72] + _T_1474 <= _T_1473 @[Mux.scala 27:72] + node _T_1475 = cat(_T_1474, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1476 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1477 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1478 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1479 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1480 = mux(_T_1476, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1477, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1478, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1479, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = or(_T_1480, _T_1481) @[Mux.scala 27:72] + node _T_1485 = or(_T_1484, _T_1482) @[Mux.scala 27:72] + node _T_1486 = or(_T_1485, _T_1483) @[Mux.scala 27:72] + wire _T_1487 : UInt<32> @[Mux.scala 27:72] + _T_1487 <= _T_1486 @[Mux.scala 27:72] + node _T_1488 = cat(UInt<32>("h00"), _T_1487) @[Cat.scala 29:58] + node _T_1489 = mux(_T_1462, _T_1475, _T_1488) @[lsu_bus_buffer.scala 336:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1448, _T_1489) @[lsu_bus_buffer.scala 335:26] + node _T_1490 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 337:58] + node _T_1491 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1492 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] + node _T_1493 = mux(_T_1490, _T_1491, _T_1492) @[lsu_bus_buffer.scala 337:44] + node _T_1494 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1495 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1496 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1497 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1498 = mux(_T_1494, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1495, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1496, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1497, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = or(_T_1498, _T_1499) @[Mux.scala 27:72] + node _T_1503 = or(_T_1502, _T_1500) @[Mux.scala 27:72] + node _T_1504 = or(_T_1503, _T_1501) @[Mux.scala 27:72] + wire _T_1505 : UInt<32> @[Mux.scala 27:72] + _T_1505 <= _T_1504 @[Mux.scala 27:72] + node _T_1506 = bits(_T_1505, 2, 2) @[lsu_bus_buffer.scala 338:36] + node _T_1507 = bits(_T_1506, 0, 0) @[lsu_bus_buffer.scala 338:46] + node _T_1508 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1509 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1510 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1511 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1512 = mux(_T_1508, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1509, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1510, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1511, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = or(_T_1512, _T_1513) @[Mux.scala 27:72] + node _T_1517 = or(_T_1516, _T_1514) @[Mux.scala 27:72] + node _T_1518 = or(_T_1517, _T_1515) @[Mux.scala 27:72] + wire _T_1519 : UInt<32> @[Mux.scala 27:72] + _T_1519 <= _T_1518 @[Mux.scala 27:72] + node _T_1520 = cat(_T_1519, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1521 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1522 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1523 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1524 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1525 = mux(_T_1521, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1522, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1523, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1524, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = or(_T_1525, _T_1526) @[Mux.scala 27:72] + node _T_1530 = or(_T_1529, _T_1527) @[Mux.scala 27:72] + node _T_1531 = or(_T_1530, _T_1528) @[Mux.scala 27:72] + wire _T_1532 : UInt<32> @[Mux.scala 27:72] + _T_1532 <= _T_1531 @[Mux.scala 27:72] + node _T_1533 = cat(UInt<32>("h00"), _T_1532) @[Cat.scala 29:58] + node _T_1534 = mux(_T_1507, _T_1520, _T_1533) @[lsu_bus_buffer.scala 338:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1493, _T_1534) @[lsu_bus_buffer.scala 337:26] + node _T_1535 = bits(obuf_byteen0_in, 0, 0) @[lsu_bus_buffer.scala 339:59] + node _T_1536 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 339:97] + node _T_1537 = and(obuf_merge_en, _T_1536) @[lsu_bus_buffer.scala 339:80] + node _T_1538 = or(_T_1535, _T_1537) @[lsu_bus_buffer.scala 339:63] + node _T_1539 = bits(obuf_byteen0_in, 1, 1) @[lsu_bus_buffer.scala 339:59] + node _T_1540 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 339:97] + node _T_1541 = and(obuf_merge_en, _T_1540) @[lsu_bus_buffer.scala 339:80] + node _T_1542 = or(_T_1539, _T_1541) @[lsu_bus_buffer.scala 339:63] + node _T_1543 = bits(obuf_byteen0_in, 2, 2) @[lsu_bus_buffer.scala 339:59] + node _T_1544 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 339:97] + node _T_1545 = and(obuf_merge_en, _T_1544) @[lsu_bus_buffer.scala 339:80] + node _T_1546 = or(_T_1543, _T_1545) @[lsu_bus_buffer.scala 339:63] + node _T_1547 = bits(obuf_byteen0_in, 3, 3) @[lsu_bus_buffer.scala 339:59] + node _T_1548 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 339:97] + node _T_1549 = and(obuf_merge_en, _T_1548) @[lsu_bus_buffer.scala 339:80] + node _T_1550 = or(_T_1547, _T_1549) @[lsu_bus_buffer.scala 339:63] + node _T_1551 = bits(obuf_byteen0_in, 4, 4) @[lsu_bus_buffer.scala 339:59] + node _T_1552 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 339:97] + node _T_1553 = and(obuf_merge_en, _T_1552) @[lsu_bus_buffer.scala 339:80] + node _T_1554 = or(_T_1551, _T_1553) @[lsu_bus_buffer.scala 339:63] + node _T_1555 = bits(obuf_byteen0_in, 5, 5) @[lsu_bus_buffer.scala 339:59] + node _T_1556 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 339:97] + node _T_1557 = and(obuf_merge_en, _T_1556) @[lsu_bus_buffer.scala 339:80] + node _T_1558 = or(_T_1555, _T_1557) @[lsu_bus_buffer.scala 339:63] + node _T_1559 = bits(obuf_byteen0_in, 6, 6) @[lsu_bus_buffer.scala 339:59] + node _T_1560 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 339:97] + node _T_1561 = and(obuf_merge_en, _T_1560) @[lsu_bus_buffer.scala 339:80] + node _T_1562 = or(_T_1559, _T_1561) @[lsu_bus_buffer.scala 339:63] + node _T_1563 = bits(obuf_byteen0_in, 7, 7) @[lsu_bus_buffer.scala 339:59] + node _T_1564 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 339:97] + node _T_1565 = and(obuf_merge_en, _T_1564) @[lsu_bus_buffer.scala 339:80] + node _T_1566 = or(_T_1563, _T_1565) @[lsu_bus_buffer.scala 339:63] + node _T_1567 = cat(_T_1566, _T_1562) @[Cat.scala 29:58] + node _T_1568 = cat(_T_1567, _T_1558) @[Cat.scala 29:58] + node _T_1569 = cat(_T_1568, _T_1554) @[Cat.scala 29:58] + node _T_1570 = cat(_T_1569, _T_1550) @[Cat.scala 29:58] + node _T_1571 = cat(_T_1570, _T_1546) @[Cat.scala 29:58] + node _T_1572 = cat(_T_1571, _T_1542) @[Cat.scala 29:58] + node obuf_byteen_in = cat(_T_1572, _T_1538) @[Cat.scala 29:58] + node _T_1573 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 340:76] + node _T_1574 = and(obuf_merge_en, _T_1573) @[lsu_bus_buffer.scala 340:59] + node _T_1575 = bits(obuf_data1_in, 7, 0) @[lsu_bus_buffer.scala 340:94] + node _T_1576 = bits(obuf_data0_in, 7, 0) @[lsu_bus_buffer.scala 340:123] + node _T_1577 = mux(_T_1574, _T_1575, _T_1576) @[lsu_bus_buffer.scala 340:44] + node _T_1578 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 340:76] + node _T_1579 = and(obuf_merge_en, _T_1578) @[lsu_bus_buffer.scala 340:59] + node _T_1580 = bits(obuf_data1_in, 15, 8) @[lsu_bus_buffer.scala 340:94] + node _T_1581 = bits(obuf_data0_in, 15, 8) @[lsu_bus_buffer.scala 340:123] + node _T_1582 = mux(_T_1579, _T_1580, _T_1581) @[lsu_bus_buffer.scala 340:44] + node _T_1583 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 340:76] + node _T_1584 = and(obuf_merge_en, _T_1583) @[lsu_bus_buffer.scala 340:59] + node _T_1585 = bits(obuf_data1_in, 23, 16) @[lsu_bus_buffer.scala 340:94] + node _T_1586 = bits(obuf_data0_in, 23, 16) @[lsu_bus_buffer.scala 340:123] + node _T_1587 = mux(_T_1584, _T_1585, _T_1586) @[lsu_bus_buffer.scala 340:44] + node _T_1588 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 340:76] + node _T_1589 = and(obuf_merge_en, _T_1588) @[lsu_bus_buffer.scala 340:59] + node _T_1590 = bits(obuf_data1_in, 31, 24) @[lsu_bus_buffer.scala 340:94] + node _T_1591 = bits(obuf_data0_in, 31, 24) @[lsu_bus_buffer.scala 340:123] + node _T_1592 = mux(_T_1589, _T_1590, _T_1591) @[lsu_bus_buffer.scala 340:44] + node _T_1593 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 340:76] + node _T_1594 = and(obuf_merge_en, _T_1593) @[lsu_bus_buffer.scala 340:59] + node _T_1595 = bits(obuf_data1_in, 39, 32) @[lsu_bus_buffer.scala 340:94] + node _T_1596 = bits(obuf_data0_in, 39, 32) @[lsu_bus_buffer.scala 340:123] + node _T_1597 = mux(_T_1594, _T_1595, _T_1596) @[lsu_bus_buffer.scala 340:44] + node _T_1598 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 340:76] + node _T_1599 = and(obuf_merge_en, _T_1598) @[lsu_bus_buffer.scala 340:59] + node _T_1600 = bits(obuf_data1_in, 47, 40) @[lsu_bus_buffer.scala 340:94] + node _T_1601 = bits(obuf_data0_in, 47, 40) @[lsu_bus_buffer.scala 340:123] + node _T_1602 = mux(_T_1599, _T_1600, _T_1601) @[lsu_bus_buffer.scala 340:44] + node _T_1603 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 340:76] + node _T_1604 = and(obuf_merge_en, _T_1603) @[lsu_bus_buffer.scala 340:59] + node _T_1605 = bits(obuf_data1_in, 55, 48) @[lsu_bus_buffer.scala 340:94] + node _T_1606 = bits(obuf_data0_in, 55, 48) @[lsu_bus_buffer.scala 340:123] + node _T_1607 = mux(_T_1604, _T_1605, _T_1606) @[lsu_bus_buffer.scala 340:44] + node _T_1608 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 340:76] + node _T_1609 = and(obuf_merge_en, _T_1608) @[lsu_bus_buffer.scala 340:59] + node _T_1610 = bits(obuf_data1_in, 63, 56) @[lsu_bus_buffer.scala 340:94] + node _T_1611 = bits(obuf_data0_in, 63, 56) @[lsu_bus_buffer.scala 340:123] + node _T_1612 = mux(_T_1609, _T_1610, _T_1611) @[lsu_bus_buffer.scala 340:44] + node _T_1613 = cat(_T_1612, _T_1607) @[Cat.scala 29:58] + node _T_1614 = cat(_T_1613, _T_1602) @[Cat.scala 29:58] + node _T_1615 = cat(_T_1614, _T_1597) @[Cat.scala 29:58] + node _T_1616 = cat(_T_1615, _T_1592) @[Cat.scala 29:58] + node _T_1617 = cat(_T_1616, _T_1587) @[Cat.scala 29:58] + node _T_1618 = cat(_T_1617, _T_1582) @[Cat.scala 29:58] + node obuf_data_in = cat(_T_1618, _T_1577) @[Cat.scala 29:58] + wire buf_dualhi : UInt<1>[4] @[lsu_bus_buffer.scala 342:24] + buf_dualhi[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + node _T_1619 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 344:30] + node _T_1620 = and(_T_1619, found_cmdptr0) @[lsu_bus_buffer.scala 344:43] + node _T_1621 = and(_T_1620, found_cmdptr1) @[lsu_bus_buffer.scala 344:59] + node _T_1622 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1623 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1624 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1625 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1626 = mux(_T_1622, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1627 = mux(_T_1623, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1628 = mux(_T_1624, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1629 = mux(_T_1625, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1630 = or(_T_1626, _T_1627) @[Mux.scala 27:72] + node _T_1631 = or(_T_1630, _T_1628) @[Mux.scala 27:72] + node _T_1632 = or(_T_1631, _T_1629) @[Mux.scala 27:72] + wire _T_1633 : UInt<3> @[Mux.scala 27:72] + _T_1633 <= _T_1632 @[Mux.scala 27:72] + node _T_1634 = eq(_T_1633, UInt<3>("h02")) @[lsu_bus_buffer.scala 344:107] + node _T_1635 = and(_T_1621, _T_1634) @[lsu_bus_buffer.scala 344:75] + node _T_1636 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1637 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1638 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1639 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1640 = mux(_T_1636, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1641 = mux(_T_1637, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1642 = mux(_T_1638, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1643 = mux(_T_1639, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1644 = or(_T_1640, _T_1641) @[Mux.scala 27:72] + node _T_1645 = or(_T_1644, _T_1642) @[Mux.scala 27:72] + node _T_1646 = or(_T_1645, _T_1643) @[Mux.scala 27:72] + wire _T_1647 : UInt<3> @[Mux.scala 27:72] + _T_1647 <= _T_1646 @[Mux.scala 27:72] + node _T_1648 = eq(_T_1647, UInt<3>("h02")) @[lsu_bus_buffer.scala 344:150] + node _T_1649 = and(_T_1635, _T_1648) @[lsu_bus_buffer.scala 344:118] + node _T_1650 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1651 = cat(_T_1650, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1652 = cat(_T_1651, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1653 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1654 = bits(_T_1652, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1655 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1656 = bits(_T_1652, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1657 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1658 = bits(_T_1652, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1659 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1660 = bits(_T_1652, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1661 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1662 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1663 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1664 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1665 = or(_T_1661, _T_1662) @[Mux.scala 27:72] + node _T_1666 = or(_T_1665, _T_1663) @[Mux.scala 27:72] + node _T_1667 = or(_T_1666, _T_1664) @[Mux.scala 27:72] + wire _T_1668 : UInt<1> @[Mux.scala 27:72] + _T_1668 <= _T_1667 @[Mux.scala 27:72] + node _T_1669 = eq(_T_1668, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:5] + node _T_1670 = and(_T_1649, _T_1669) @[lsu_bus_buffer.scala 344:161] + node _T_1671 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1672 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1673 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1674 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1675 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1676 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1677 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1678 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1679 = mux(_T_1671, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1680 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1681 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1682 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1683 = or(_T_1679, _T_1680) @[Mux.scala 27:72] + node _T_1684 = or(_T_1683, _T_1681) @[Mux.scala 27:72] + node _T_1685 = or(_T_1684, _T_1682) @[Mux.scala 27:72] + wire _T_1686 : UInt<1> @[Mux.scala 27:72] + _T_1686 <= _T_1685 @[Mux.scala 27:72] + node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:87] + node _T_1688 = and(_T_1670, _T_1687) @[lsu_bus_buffer.scala 345:85] + node _T_1689 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1690 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1691 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1692 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1693 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1694 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1695 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1696 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1697 = mux(_T_1689, _T_1690, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1698 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1699 = mux(_T_1693, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1700 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1701 = or(_T_1697, _T_1698) @[Mux.scala 27:72] + node _T_1702 = or(_T_1701, _T_1699) @[Mux.scala 27:72] + node _T_1703 = or(_T_1702, _T_1700) @[Mux.scala 27:72] + wire _T_1704 : UInt<1> @[Mux.scala 27:72] + _T_1704 <= _T_1703 @[Mux.scala 27:72] + node _T_1705 = eq(_T_1704, UInt<1>("h00")) @[lsu_bus_buffer.scala 346:6] + node _T_1706 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1707 = cat(_T_1706, buf_dual[1]) @[Cat.scala 29:58] + node _T_1708 = cat(_T_1707, buf_dual[0]) @[Cat.scala 29:58] + node _T_1709 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1710 = bits(_T_1708, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1711 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1712 = bits(_T_1708, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1713 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1714 = bits(_T_1708, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1715 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1716 = bits(_T_1708, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1717 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1718 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1719 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1720 = mux(_T_1715, _T_1716, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1721 = or(_T_1717, _T_1718) @[Mux.scala 27:72] + node _T_1722 = or(_T_1721, _T_1719) @[Mux.scala 27:72] + node _T_1723 = or(_T_1722, _T_1720) @[Mux.scala 27:72] + wire _T_1724 : UInt<1> @[Mux.scala 27:72] + _T_1724 <= _T_1723 @[Mux.scala 27:72] + node _T_1725 = and(_T_1705, _T_1724) @[lsu_bus_buffer.scala 346:36] + node _T_1726 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] + node _T_1727 = cat(_T_1726, buf_dualhi[1]) @[Cat.scala 29:58] + node _T_1728 = cat(_T_1727, buf_dualhi[0]) @[Cat.scala 29:58] + node _T_1729 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1730 = bits(_T_1728, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1731 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1732 = bits(_T_1728, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1733 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1734 = bits(_T_1728, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1735 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1736 = bits(_T_1728, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1737 = mux(_T_1729, _T_1730, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1738 = mux(_T_1731, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1739 = mux(_T_1733, _T_1734, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1740 = mux(_T_1735, _T_1736, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1741 = or(_T_1737, _T_1738) @[Mux.scala 27:72] + node _T_1742 = or(_T_1741, _T_1739) @[Mux.scala 27:72] + node _T_1743 = or(_T_1742, _T_1740) @[Mux.scala 27:72] + wire _T_1744 : UInt<1> @[Mux.scala 27:72] + _T_1744 <= _T_1743 @[Mux.scala 27:72] + node _T_1745 = eq(_T_1744, UInt<1>("h00")) @[lsu_bus_buffer.scala 346:107] + node _T_1746 = and(_T_1725, _T_1745) @[lsu_bus_buffer.scala 346:105] + node _T_1747 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1748 = cat(_T_1747, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1749 = cat(_T_1748, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1750 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1751 = bits(_T_1749, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1752 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1753 = bits(_T_1749, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1754 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1755 = bits(_T_1749, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1756 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1757 = bits(_T_1749, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1758 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1759 = mux(_T_1752, _T_1753, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1760 = mux(_T_1754, _T_1755, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1761 = mux(_T_1756, _T_1757, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = or(_T_1758, _T_1759) @[Mux.scala 27:72] + node _T_1763 = or(_T_1762, _T_1760) @[Mux.scala 27:72] + node _T_1764 = or(_T_1763, _T_1761) @[Mux.scala 27:72] + wire _T_1765 : UInt<1> @[Mux.scala 27:72] + _T_1765 <= _T_1764 @[Mux.scala 27:72] + node _T_1766 = and(_T_1746, _T_1765) @[lsu_bus_buffer.scala 346:177] + node _T_1767 = and(_T_1688, _T_1766) @[lsu_bus_buffer.scala 345:122] + node _T_1768 = and(ibuf_buf_byp, ldst_samedw_r) @[lsu_bus_buffer.scala 347:19] + node _T_1769 = and(_T_1768, io.ldst_dual_r) @[lsu_bus_buffer.scala 347:35] + node _T_1770 = or(_T_1767, _T_1769) @[lsu_bus_buffer.scala 346:250] + obuf_merge_en <= _T_1770 @[lsu_bus_buffer.scala 344:17] + reg obuf_wr_enQ : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + obuf_wr_enQ <= obuf_wr_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1771 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 349:58] + node _T_1772 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 349:93] + node _T_1773 = and(_T_1771, _T_1772) @[lsu_bus_buffer.scala 349:91] + reg _T_1774 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 349:54] + _T_1774 <= _T_1773 @[lsu_bus_buffer.scala 349:54] + obuf_valid <= _T_1774 @[lsu_bus_buffer.scala 349:14] + reg _T_1775 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1775 <= obuf_nosend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_nosend <= _T_1775 @[lsu_bus_buffer.scala 350:15] + reg _T_1776 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_rdrsp_pend_en : @[Reg.scala 28:19] + _T_1776 <= obuf_rdrsp_pend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_rdrsp_pend <= _T_1776 @[lsu_bus_buffer.scala 351:19] + reg _T_1777 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1777 <= obuf_cmd_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_cmd_done <= _T_1777 @[lsu_bus_buffer.scala 352:17] + reg _T_1778 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1778 <= obuf_data_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_data_done <= _T_1778 @[lsu_bus_buffer.scala 353:18] + reg _T_1779 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1779 <= obuf_rdrsp_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_rdrsp_tag <= _T_1779 @[lsu_bus_buffer.scala 354:18] + node _T_1780 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1780 : @[Reg.scala 28:19] + _T_1781 <= obuf_tag0_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_tag0 <= _T_1781 @[lsu_bus_buffer.scala 356:13] + node _T_1782 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_tag1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1782 : @[Reg.scala 28:19] + obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1783 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_merge : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1783 : @[Reg.scala 28:19] + obuf_merge <= obuf_merge_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1784 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1785 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1784 : @[Reg.scala 28:19] + _T_1785 <= obuf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_write <= _T_1785 @[lsu_bus_buffer.scala 359:14] + node _T_1786 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1787 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1786 : @[Reg.scala 28:19] + _T_1787 <= obuf_sideeffect_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_sideeffect <= _T_1787 @[lsu_bus_buffer.scala 360:19] + node _T_1788 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_sz : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1788 : @[Reg.scala 28:19] + obuf_sz <= obuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1789 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_byteen : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1789 : @[Reg.scala 28:19] + obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1790 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1790 <= obuf_addr_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_addr <= _T_1790 @[lsu_bus_buffer.scala 363:13] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg obuf_data : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_data <= obuf_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1791 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1791 <= obuf_data_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_wr_timer <= _T_1791 @[lsu_bus_buffer.scala 365:17] + wire WrPtr0_m : UInt<2> + WrPtr0_m <= UInt<1>("h00") + node _T_1792 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1793 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:30] + node _T_1794 = and(ibuf_valid, _T_1793) @[lsu_bus_buffer.scala 370:19] + node _T_1795 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:18] + node _T_1796 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:57] + node _T_1797 = and(io.ldst_dual_r, _T_1796) @[lsu_bus_buffer.scala 371:45] + node _T_1798 = or(_T_1795, _T_1797) @[lsu_bus_buffer.scala 371:27] + node _T_1799 = and(io.lsu_busreq_r, _T_1798) @[lsu_bus_buffer.scala 370:58] + node _T_1800 = or(_T_1794, _T_1799) @[lsu_bus_buffer.scala 370:39] + node _T_1801 = eq(_T_1800, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1802 = and(_T_1792, _T_1801) @[lsu_bus_buffer.scala 369:76] + node _T_1803 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1804 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 370:30] + node _T_1805 = and(ibuf_valid, _T_1804) @[lsu_bus_buffer.scala 370:19] + node _T_1806 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:18] + node _T_1807 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:57] + node _T_1808 = and(io.ldst_dual_r, _T_1807) @[lsu_bus_buffer.scala 371:45] + node _T_1809 = or(_T_1806, _T_1808) @[lsu_bus_buffer.scala 371:27] + node _T_1810 = and(io.lsu_busreq_r, _T_1809) @[lsu_bus_buffer.scala 370:58] + node _T_1811 = or(_T_1805, _T_1810) @[lsu_bus_buffer.scala 370:39] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1813 = and(_T_1803, _T_1812) @[lsu_bus_buffer.scala 369:76] + node _T_1814 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1815 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 370:30] + node _T_1816 = and(ibuf_valid, _T_1815) @[lsu_bus_buffer.scala 370:19] + node _T_1817 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:18] + node _T_1818 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:57] + node _T_1819 = and(io.ldst_dual_r, _T_1818) @[lsu_bus_buffer.scala 371:45] + node _T_1820 = or(_T_1817, _T_1819) @[lsu_bus_buffer.scala 371:27] + node _T_1821 = and(io.lsu_busreq_r, _T_1820) @[lsu_bus_buffer.scala 370:58] + node _T_1822 = or(_T_1816, _T_1821) @[lsu_bus_buffer.scala 370:39] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1824 = and(_T_1814, _T_1823) @[lsu_bus_buffer.scala 369:76] + node _T_1825 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1826 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 370:30] + node _T_1827 = and(ibuf_valid, _T_1826) @[lsu_bus_buffer.scala 370:19] + node _T_1828 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:18] + node _T_1829 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:57] + node _T_1830 = and(io.ldst_dual_r, _T_1829) @[lsu_bus_buffer.scala 371:45] + node _T_1831 = or(_T_1828, _T_1830) @[lsu_bus_buffer.scala 371:27] + node _T_1832 = and(io.lsu_busreq_r, _T_1831) @[lsu_bus_buffer.scala 370:58] + node _T_1833 = or(_T_1827, _T_1832) @[lsu_bus_buffer.scala 370:39] + node _T_1834 = eq(_T_1833, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1835 = and(_T_1825, _T_1834) @[lsu_bus_buffer.scala 369:76] + node _T_1836 = mux(_T_1835, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1837 = mux(_T_1824, UInt<2>("h02"), _T_1836) @[Mux.scala 98:16] + node _T_1838 = mux(_T_1813, UInt<1>("h01"), _T_1837) @[Mux.scala 98:16] + node _T_1839 = mux(_T_1802, UInt<1>("h00"), _T_1838) @[Mux.scala 98:16] + WrPtr0_m <= _T_1839 @[lsu_bus_buffer.scala 369:12] + wire WrPtr1_m : UInt<2> + WrPtr1_m <= UInt<1>("h00") + node _T_1840 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1841 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:103] + node _T_1842 = and(ibuf_valid, _T_1841) @[lsu_bus_buffer.scala 375:92] + node _T_1843 = eq(WrPtr0_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 376:33] + node _T_1844 = and(io.lsu_busreq_m, _T_1843) @[lsu_bus_buffer.scala 376:22] + node _T_1845 = or(_T_1842, _T_1844) @[lsu_bus_buffer.scala 375:112] + node _T_1846 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:36] + node _T_1847 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:34] + node _T_1848 = and(io.ldst_dual_r, _T_1847) @[lsu_bus_buffer.scala 378:23] + node _T_1849 = or(_T_1846, _T_1848) @[lsu_bus_buffer.scala 377:46] + node _T_1850 = and(io.lsu_busreq_r, _T_1849) @[lsu_bus_buffer.scala 377:22] + node _T_1851 = or(_T_1845, _T_1850) @[lsu_bus_buffer.scala 376:42] + node _T_1852 = eq(_T_1851, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1853 = and(_T_1840, _T_1852) @[lsu_bus_buffer.scala 375:76] + node _T_1854 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1855 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 375:103] + node _T_1856 = and(ibuf_valid, _T_1855) @[lsu_bus_buffer.scala 375:92] + node _T_1857 = eq(WrPtr0_m, UInt<1>("h01")) @[lsu_bus_buffer.scala 376:33] + node _T_1858 = and(io.lsu_busreq_m, _T_1857) @[lsu_bus_buffer.scala 376:22] + node _T_1859 = or(_T_1856, _T_1858) @[lsu_bus_buffer.scala 375:112] + node _T_1860 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 377:36] + node _T_1861 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 378:34] + node _T_1862 = and(io.ldst_dual_r, _T_1861) @[lsu_bus_buffer.scala 378:23] + node _T_1863 = or(_T_1860, _T_1862) @[lsu_bus_buffer.scala 377:46] + node _T_1864 = and(io.lsu_busreq_r, _T_1863) @[lsu_bus_buffer.scala 377:22] + node _T_1865 = or(_T_1859, _T_1864) @[lsu_bus_buffer.scala 376:42] + node _T_1866 = eq(_T_1865, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1867 = and(_T_1854, _T_1866) @[lsu_bus_buffer.scala 375:76] + node _T_1868 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1869 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 375:103] + node _T_1870 = and(ibuf_valid, _T_1869) @[lsu_bus_buffer.scala 375:92] + node _T_1871 = eq(WrPtr0_m, UInt<2>("h02")) @[lsu_bus_buffer.scala 376:33] + node _T_1872 = and(io.lsu_busreq_m, _T_1871) @[lsu_bus_buffer.scala 376:22] + node _T_1873 = or(_T_1870, _T_1872) @[lsu_bus_buffer.scala 375:112] + node _T_1874 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 377:36] + node _T_1875 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 378:34] + node _T_1876 = and(io.ldst_dual_r, _T_1875) @[lsu_bus_buffer.scala 378:23] + node _T_1877 = or(_T_1874, _T_1876) @[lsu_bus_buffer.scala 377:46] + node _T_1878 = and(io.lsu_busreq_r, _T_1877) @[lsu_bus_buffer.scala 377:22] + node _T_1879 = or(_T_1873, _T_1878) @[lsu_bus_buffer.scala 376:42] + node _T_1880 = eq(_T_1879, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1881 = and(_T_1868, _T_1880) @[lsu_bus_buffer.scala 375:76] + node _T_1882 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1883 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 375:103] + node _T_1884 = and(ibuf_valid, _T_1883) @[lsu_bus_buffer.scala 375:92] + node _T_1885 = eq(WrPtr0_m, UInt<2>("h03")) @[lsu_bus_buffer.scala 376:33] + node _T_1886 = and(io.lsu_busreq_m, _T_1885) @[lsu_bus_buffer.scala 376:22] + node _T_1887 = or(_T_1884, _T_1886) @[lsu_bus_buffer.scala 375:112] + node _T_1888 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 377:36] + node _T_1889 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 378:34] + node _T_1890 = and(io.ldst_dual_r, _T_1889) @[lsu_bus_buffer.scala 378:23] + node _T_1891 = or(_T_1888, _T_1890) @[lsu_bus_buffer.scala 377:46] + node _T_1892 = and(io.lsu_busreq_r, _T_1891) @[lsu_bus_buffer.scala 377:22] + node _T_1893 = or(_T_1887, _T_1892) @[lsu_bus_buffer.scala 376:42] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1895 = and(_T_1882, _T_1894) @[lsu_bus_buffer.scala 375:76] + node _T_1896 = mux(_T_1895, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1897 = mux(_T_1881, UInt<2>("h02"), _T_1896) @[Mux.scala 98:16] + node _T_1898 = mux(_T_1867, UInt<1>("h01"), _T_1897) @[Mux.scala 98:16] + node _T_1899 = mux(_T_1853, UInt<1>("h00"), _T_1898) @[Mux.scala 98:16] + WrPtr1_m <= _T_1899 @[lsu_bus_buffer.scala 375:12] + wire buf_age : UInt<4>[4] @[lsu_bus_buffer.scala 380:21] + buf_age[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + node _T_1900 = orr(buf_age[0]) @[lsu_bus_buffer.scala 383:58] + node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1902 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1903 = and(_T_1901, _T_1902) @[lsu_bus_buffer.scala 383:63] + node _T_1904 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1905 = and(_T_1903, _T_1904) @[lsu_bus_buffer.scala 383:88] + node _T_1906 = orr(buf_age[1]) @[lsu_bus_buffer.scala 383:58] + node _T_1907 = eq(_T_1906, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1908 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1909 = and(_T_1907, _T_1908) @[lsu_bus_buffer.scala 383:63] + node _T_1910 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1911 = and(_T_1909, _T_1910) @[lsu_bus_buffer.scala 383:88] + node _T_1912 = orr(buf_age[2]) @[lsu_bus_buffer.scala 383:58] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1914 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1915 = and(_T_1913, _T_1914) @[lsu_bus_buffer.scala 383:63] + node _T_1916 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1917 = and(_T_1915, _T_1916) @[lsu_bus_buffer.scala 383:88] + node _T_1918 = orr(buf_age[3]) @[lsu_bus_buffer.scala 383:58] + node _T_1919 = eq(_T_1918, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1920 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1921 = and(_T_1919, _T_1920) @[lsu_bus_buffer.scala 383:63] + node _T_1922 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1923 = and(_T_1921, _T_1922) @[lsu_bus_buffer.scala 383:88] + node _T_1924 = cat(_T_1923, _T_1917) @[Cat.scala 29:58] + node _T_1925 = cat(_T_1924, _T_1911) @[Cat.scala 29:58] + node CmdPtr0Dec = cat(_T_1925, _T_1905) @[Cat.scala 29:58] + node _T_1926 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1927 = and(buf_age[0], _T_1926) @[lsu_bus_buffer.scala 384:59] + node _T_1928 = orr(_T_1927) @[lsu_bus_buffer.scala 384:76] + node _T_1929 = eq(_T_1928, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1930 = bits(CmdPtr0Dec, 0, 0) @[lsu_bus_buffer.scala 384:94] + node _T_1931 = eq(_T_1930, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1932 = and(_T_1929, _T_1931) @[lsu_bus_buffer.scala 384:81] + node _T_1933 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1934 = and(_T_1932, _T_1933) @[lsu_bus_buffer.scala 384:98] + node _T_1935 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1936 = and(_T_1934, _T_1935) @[lsu_bus_buffer.scala 384:123] + node _T_1937 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1938 = and(buf_age[1], _T_1937) @[lsu_bus_buffer.scala 384:59] + node _T_1939 = orr(_T_1938) @[lsu_bus_buffer.scala 384:76] + node _T_1940 = eq(_T_1939, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1941 = bits(CmdPtr0Dec, 1, 1) @[lsu_bus_buffer.scala 384:94] + node _T_1942 = eq(_T_1941, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1943 = and(_T_1940, _T_1942) @[lsu_bus_buffer.scala 384:81] + node _T_1944 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1945 = and(_T_1943, _T_1944) @[lsu_bus_buffer.scala 384:98] + node _T_1946 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1947 = and(_T_1945, _T_1946) @[lsu_bus_buffer.scala 384:123] + node _T_1948 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1949 = and(buf_age[2], _T_1948) @[lsu_bus_buffer.scala 384:59] + node _T_1950 = orr(_T_1949) @[lsu_bus_buffer.scala 384:76] + node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1952 = bits(CmdPtr0Dec, 2, 2) @[lsu_bus_buffer.scala 384:94] + node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1954 = and(_T_1951, _T_1953) @[lsu_bus_buffer.scala 384:81] + node _T_1955 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1956 = and(_T_1954, _T_1955) @[lsu_bus_buffer.scala 384:98] + node _T_1957 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1958 = and(_T_1956, _T_1957) @[lsu_bus_buffer.scala 384:123] + node _T_1959 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1960 = and(buf_age[3], _T_1959) @[lsu_bus_buffer.scala 384:59] + node _T_1961 = orr(_T_1960) @[lsu_bus_buffer.scala 384:76] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1963 = bits(CmdPtr0Dec, 3, 3) @[lsu_bus_buffer.scala 384:94] + node _T_1964 = eq(_T_1963, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1965 = and(_T_1962, _T_1964) @[lsu_bus_buffer.scala 384:81] + node _T_1966 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1967 = and(_T_1965, _T_1966) @[lsu_bus_buffer.scala 384:98] + node _T_1968 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1969 = and(_T_1967, _T_1968) @[lsu_bus_buffer.scala 384:123] + node _T_1970 = cat(_T_1969, _T_1958) @[Cat.scala 29:58] + node _T_1971 = cat(_T_1970, _T_1947) @[Cat.scala 29:58] + node CmdPtr1Dec = cat(_T_1971, _T_1936) @[Cat.scala 29:58] + wire buf_rsp_pickage : UInt<4>[4] @[lsu_bus_buffer.scala 385:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + node _T_1972 = orr(buf_rsp_pickage[0]) @[lsu_bus_buffer.scala 387:65] + node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1974 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1975 = and(_T_1973, _T_1974) @[lsu_bus_buffer.scala 387:70] + node _T_1976 = orr(buf_rsp_pickage[1]) @[lsu_bus_buffer.scala 387:65] + node _T_1977 = eq(_T_1976, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1978 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1979 = and(_T_1977, _T_1978) @[lsu_bus_buffer.scala 387:70] + node _T_1980 = orr(buf_rsp_pickage[2]) @[lsu_bus_buffer.scala 387:65] + node _T_1981 = eq(_T_1980, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1982 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1983 = and(_T_1981, _T_1982) @[lsu_bus_buffer.scala 387:70] + node _T_1984 = orr(buf_rsp_pickage[3]) @[lsu_bus_buffer.scala 387:65] + node _T_1985 = eq(_T_1984, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1986 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1987 = and(_T_1985, _T_1986) @[lsu_bus_buffer.scala 387:70] + node _T_1988 = cat(_T_1987, _T_1983) @[Cat.scala 29:58] + node _T_1989 = cat(_T_1988, _T_1979) @[Cat.scala 29:58] + node RspPtrDec = cat(_T_1989, _T_1975) @[Cat.scala 29:58] + node _T_1990 = orr(CmdPtr0Dec) @[lsu_bus_buffer.scala 388:31] + found_cmdptr0 <= _T_1990 @[lsu_bus_buffer.scala 388:17] + node _T_1991 = orr(CmdPtr1Dec) @[lsu_bus_buffer.scala 389:31] + found_cmdptr1 <= _T_1991 @[lsu_bus_buffer.scala 389:17] + wire RspPtr : UInt<2> + RspPtr <= UInt<1>("h00") + node _T_1992 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1993 = cat(_T_1992, CmdPtr0Dec) @[Cat.scala 29:58] + node _T_1994 = bits(_T_1993, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_1995 = bits(_T_1993, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_1996 = or(_T_1994, _T_1995) @[lsu_bus_buffer.scala 391:42] + node _T_1997 = bits(_T_1993, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_1998 = or(_T_1996, _T_1997) @[lsu_bus_buffer.scala 391:48] + node _T_1999 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2000 = or(_T_1998, _T_1999) @[lsu_bus_buffer.scala 391:54] + node _T_2001 = bits(_T_1993, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2002 = bits(_T_1993, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2003 = or(_T_2001, _T_2002) @[lsu_bus_buffer.scala 391:67] + node _T_2004 = bits(_T_1993, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2005 = or(_T_2003, _T_2004) @[lsu_bus_buffer.scala 391:73] + node _T_2006 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2007 = or(_T_2005, _T_2006) @[lsu_bus_buffer.scala 391:79] + node _T_2008 = bits(_T_1993, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2009 = bits(_T_1993, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2010 = or(_T_2008, _T_2009) @[lsu_bus_buffer.scala 391:92] + node _T_2011 = bits(_T_1993, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2012 = or(_T_2010, _T_2011) @[lsu_bus_buffer.scala 391:98] + node _T_2013 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2014 = or(_T_2012, _T_2013) @[lsu_bus_buffer.scala 391:104] + node _T_2015 = cat(_T_2000, _T_2007) @[Cat.scala 29:58] + node _T_2016 = cat(_T_2015, _T_2014) @[Cat.scala 29:58] + CmdPtr0 <= _T_2016 @[lsu_bus_buffer.scala 396:11] + node _T_2017 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2018 = cat(_T_2017, CmdPtr1Dec) @[Cat.scala 29:58] + node _T_2019 = bits(_T_2018, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_2020 = bits(_T_2018, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_2021 = or(_T_2019, _T_2020) @[lsu_bus_buffer.scala 391:42] + node _T_2022 = bits(_T_2018, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_2023 = or(_T_2021, _T_2022) @[lsu_bus_buffer.scala 391:48] + node _T_2024 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2025 = or(_T_2023, _T_2024) @[lsu_bus_buffer.scala 391:54] + node _T_2026 = bits(_T_2018, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2027 = bits(_T_2018, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2028 = or(_T_2026, _T_2027) @[lsu_bus_buffer.scala 391:67] + node _T_2029 = bits(_T_2018, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2030 = or(_T_2028, _T_2029) @[lsu_bus_buffer.scala 391:73] + node _T_2031 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2032 = or(_T_2030, _T_2031) @[lsu_bus_buffer.scala 391:79] + node _T_2033 = bits(_T_2018, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2034 = bits(_T_2018, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2035 = or(_T_2033, _T_2034) @[lsu_bus_buffer.scala 391:92] + node _T_2036 = bits(_T_2018, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2037 = or(_T_2035, _T_2036) @[lsu_bus_buffer.scala 391:98] + node _T_2038 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2039 = or(_T_2037, _T_2038) @[lsu_bus_buffer.scala 391:104] + node _T_2040 = cat(_T_2025, _T_2032) @[Cat.scala 29:58] + node _T_2041 = cat(_T_2040, _T_2039) @[Cat.scala 29:58] + CmdPtr1 <= _T_2041 @[lsu_bus_buffer.scala 398:11] + node _T_2042 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2043 = cat(_T_2042, RspPtrDec) @[Cat.scala 29:58] + node _T_2044 = bits(_T_2043, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_2045 = bits(_T_2043, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_2046 = or(_T_2044, _T_2045) @[lsu_bus_buffer.scala 391:42] + node _T_2047 = bits(_T_2043, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_2048 = or(_T_2046, _T_2047) @[lsu_bus_buffer.scala 391:48] + node _T_2049 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2050 = or(_T_2048, _T_2049) @[lsu_bus_buffer.scala 391:54] + node _T_2051 = bits(_T_2043, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2052 = bits(_T_2043, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2053 = or(_T_2051, _T_2052) @[lsu_bus_buffer.scala 391:67] + node _T_2054 = bits(_T_2043, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2055 = or(_T_2053, _T_2054) @[lsu_bus_buffer.scala 391:73] + node _T_2056 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2057 = or(_T_2055, _T_2056) @[lsu_bus_buffer.scala 391:79] + node _T_2058 = bits(_T_2043, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2059 = bits(_T_2043, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2060 = or(_T_2058, _T_2059) @[lsu_bus_buffer.scala 391:92] + node _T_2061 = bits(_T_2043, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2062 = or(_T_2060, _T_2061) @[lsu_bus_buffer.scala 391:98] + node _T_2063 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2064 = or(_T_2062, _T_2063) @[lsu_bus_buffer.scala 391:104] + node _T_2065 = cat(_T_2050, _T_2057) @[Cat.scala 29:58] + node _T_2066 = cat(_T_2065, _T_2064) @[Cat.scala 29:58] + RspPtr <= _T_2066 @[lsu_bus_buffer.scala 399:10] + wire buf_state_en : UInt<1>[4] @[lsu_bus_buffer.scala 400:26] + buf_state_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + wire buf_rspageQ : UInt<4>[4] @[lsu_bus_buffer.scala 402:25] + buf_rspageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + wire buf_rspage_set : UInt<4>[4] @[lsu_bus_buffer.scala 404:28] + buf_rspage_set[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + wire buf_rspage_in : UInt<4>[4] @[lsu_bus_buffer.scala 406:27] + buf_rspage_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + wire buf_rspage : UInt<4>[4] @[lsu_bus_buffer.scala 408:24] + buf_rspage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + node _T_2067 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2068 = and(_T_2067, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2069 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2070 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2071 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2072 = and(_T_2070, _T_2071) @[lsu_bus_buffer.scala 412:57] + node _T_2073 = or(_T_2069, _T_2072) @[lsu_bus_buffer.scala 412:31] + node _T_2074 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2075 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2076 = and(_T_2074, _T_2075) @[lsu_bus_buffer.scala 413:41] + node _T_2077 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2078 = and(_T_2076, _T_2077) @[lsu_bus_buffer.scala 413:71] + node _T_2079 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2080 = and(_T_2078, _T_2079) @[lsu_bus_buffer.scala 413:92] + node _T_2081 = or(_T_2073, _T_2080) @[lsu_bus_buffer.scala 412:86] + node _T_2082 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2083 = and(_T_2082, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2084 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2085 = and(_T_2083, _T_2084) @[lsu_bus_buffer.scala 414:52] + node _T_2086 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2087 = and(_T_2085, _T_2086) @[lsu_bus_buffer.scala 414:73] + node _T_2088 = or(_T_2081, _T_2087) @[lsu_bus_buffer.scala 413:114] + node _T_2089 = and(_T_2068, _T_2088) @[lsu_bus_buffer.scala 411:113] + node _T_2090 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2091 = or(_T_2089, _T_2090) @[lsu_bus_buffer.scala 414:97] + node _T_2092 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2093 = and(_T_2092, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2094 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2095 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2096 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2097 = and(_T_2095, _T_2096) @[lsu_bus_buffer.scala 412:57] + node _T_2098 = or(_T_2094, _T_2097) @[lsu_bus_buffer.scala 412:31] + node _T_2099 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2100 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2101 = and(_T_2099, _T_2100) @[lsu_bus_buffer.scala 413:41] + node _T_2102 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2103 = and(_T_2101, _T_2102) @[lsu_bus_buffer.scala 413:71] + node _T_2104 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2105 = and(_T_2103, _T_2104) @[lsu_bus_buffer.scala 413:92] + node _T_2106 = or(_T_2098, _T_2105) @[lsu_bus_buffer.scala 412:86] + node _T_2107 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2108 = and(_T_2107, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2109 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2110 = and(_T_2108, _T_2109) @[lsu_bus_buffer.scala 414:52] + node _T_2111 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2112 = and(_T_2110, _T_2111) @[lsu_bus_buffer.scala 414:73] + node _T_2113 = or(_T_2106, _T_2112) @[lsu_bus_buffer.scala 413:114] + node _T_2114 = and(_T_2093, _T_2113) @[lsu_bus_buffer.scala 411:113] + node _T_2115 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2116 = or(_T_2114, _T_2115) @[lsu_bus_buffer.scala 414:97] + node _T_2117 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2118 = and(_T_2117, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2119 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2120 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2121 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2122 = and(_T_2120, _T_2121) @[lsu_bus_buffer.scala 412:57] + node _T_2123 = or(_T_2119, _T_2122) @[lsu_bus_buffer.scala 412:31] + node _T_2124 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2125 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2126 = and(_T_2124, _T_2125) @[lsu_bus_buffer.scala 413:41] + node _T_2127 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2128 = and(_T_2126, _T_2127) @[lsu_bus_buffer.scala 413:71] + node _T_2129 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2130 = and(_T_2128, _T_2129) @[lsu_bus_buffer.scala 413:92] + node _T_2131 = or(_T_2123, _T_2130) @[lsu_bus_buffer.scala 412:86] + node _T_2132 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2133 = and(_T_2132, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2134 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2135 = and(_T_2133, _T_2134) @[lsu_bus_buffer.scala 414:52] + node _T_2136 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2137 = and(_T_2135, _T_2136) @[lsu_bus_buffer.scala 414:73] + node _T_2138 = or(_T_2131, _T_2137) @[lsu_bus_buffer.scala 413:114] + node _T_2139 = and(_T_2118, _T_2138) @[lsu_bus_buffer.scala 411:113] + node _T_2140 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2141 = or(_T_2139, _T_2140) @[lsu_bus_buffer.scala 414:97] + node _T_2142 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2143 = and(_T_2142, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2144 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2145 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2146 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2147 = and(_T_2145, _T_2146) @[lsu_bus_buffer.scala 412:57] + node _T_2148 = or(_T_2144, _T_2147) @[lsu_bus_buffer.scala 412:31] + node _T_2149 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2150 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2151 = and(_T_2149, _T_2150) @[lsu_bus_buffer.scala 413:41] + node _T_2152 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2153 = and(_T_2151, _T_2152) @[lsu_bus_buffer.scala 413:71] + node _T_2154 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2155 = and(_T_2153, _T_2154) @[lsu_bus_buffer.scala 413:92] + node _T_2156 = or(_T_2148, _T_2155) @[lsu_bus_buffer.scala 412:86] + node _T_2157 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2158 = and(_T_2157, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2159 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2160 = and(_T_2158, _T_2159) @[lsu_bus_buffer.scala 414:52] + node _T_2161 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2162 = and(_T_2160, _T_2161) @[lsu_bus_buffer.scala 414:73] + node _T_2163 = or(_T_2156, _T_2162) @[lsu_bus_buffer.scala 413:114] + node _T_2164 = and(_T_2143, _T_2163) @[lsu_bus_buffer.scala 411:113] + node _T_2165 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2166 = or(_T_2164, _T_2165) @[lsu_bus_buffer.scala 414:97] + node _T_2167 = cat(_T_2166, _T_2141) @[Cat.scala 29:58] + node _T_2168 = cat(_T_2167, _T_2116) @[Cat.scala 29:58] + node buf_age_in_0 = cat(_T_2168, _T_2091) @[Cat.scala 29:58] + node _T_2169 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2170 = and(_T_2169, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2171 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2172 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2173 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2174 = and(_T_2172, _T_2173) @[lsu_bus_buffer.scala 412:57] + node _T_2175 = or(_T_2171, _T_2174) @[lsu_bus_buffer.scala 412:31] + node _T_2176 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2177 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2178 = and(_T_2176, _T_2177) @[lsu_bus_buffer.scala 413:41] + node _T_2179 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2180 = and(_T_2178, _T_2179) @[lsu_bus_buffer.scala 413:71] + node _T_2181 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2182 = and(_T_2180, _T_2181) @[lsu_bus_buffer.scala 413:92] + node _T_2183 = or(_T_2175, _T_2182) @[lsu_bus_buffer.scala 412:86] + node _T_2184 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2185 = and(_T_2184, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2186 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2187 = and(_T_2185, _T_2186) @[lsu_bus_buffer.scala 414:52] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2189 = and(_T_2187, _T_2188) @[lsu_bus_buffer.scala 414:73] + node _T_2190 = or(_T_2183, _T_2189) @[lsu_bus_buffer.scala 413:114] + node _T_2191 = and(_T_2170, _T_2190) @[lsu_bus_buffer.scala 411:113] + node _T_2192 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2193 = or(_T_2191, _T_2192) @[lsu_bus_buffer.scala 414:97] + node _T_2194 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2195 = and(_T_2194, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2196 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2197 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2198 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2199 = and(_T_2197, _T_2198) @[lsu_bus_buffer.scala 412:57] + node _T_2200 = or(_T_2196, _T_2199) @[lsu_bus_buffer.scala 412:31] + node _T_2201 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2202 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2203 = and(_T_2201, _T_2202) @[lsu_bus_buffer.scala 413:41] + node _T_2204 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2205 = and(_T_2203, _T_2204) @[lsu_bus_buffer.scala 413:71] + node _T_2206 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2207 = and(_T_2205, _T_2206) @[lsu_bus_buffer.scala 413:92] + node _T_2208 = or(_T_2200, _T_2207) @[lsu_bus_buffer.scala 412:86] + node _T_2209 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2210 = and(_T_2209, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2211 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2212 = and(_T_2210, _T_2211) @[lsu_bus_buffer.scala 414:52] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2214 = and(_T_2212, _T_2213) @[lsu_bus_buffer.scala 414:73] + node _T_2215 = or(_T_2208, _T_2214) @[lsu_bus_buffer.scala 413:114] + node _T_2216 = and(_T_2195, _T_2215) @[lsu_bus_buffer.scala 411:113] + node _T_2217 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2218 = or(_T_2216, _T_2217) @[lsu_bus_buffer.scala 414:97] + node _T_2219 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2220 = and(_T_2219, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2221 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2222 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2223 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2224 = and(_T_2222, _T_2223) @[lsu_bus_buffer.scala 412:57] + node _T_2225 = or(_T_2221, _T_2224) @[lsu_bus_buffer.scala 412:31] + node _T_2226 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2227 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2228 = and(_T_2226, _T_2227) @[lsu_bus_buffer.scala 413:41] + node _T_2229 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2230 = and(_T_2228, _T_2229) @[lsu_bus_buffer.scala 413:71] + node _T_2231 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2232 = and(_T_2230, _T_2231) @[lsu_bus_buffer.scala 413:92] + node _T_2233 = or(_T_2225, _T_2232) @[lsu_bus_buffer.scala 412:86] + node _T_2234 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2235 = and(_T_2234, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2236 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2237 = and(_T_2235, _T_2236) @[lsu_bus_buffer.scala 414:52] + node _T_2238 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2239 = and(_T_2237, _T_2238) @[lsu_bus_buffer.scala 414:73] + node _T_2240 = or(_T_2233, _T_2239) @[lsu_bus_buffer.scala 413:114] + node _T_2241 = and(_T_2220, _T_2240) @[lsu_bus_buffer.scala 411:113] + node _T_2242 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2243 = or(_T_2241, _T_2242) @[lsu_bus_buffer.scala 414:97] + node _T_2244 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2245 = and(_T_2244, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2246 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2247 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2248 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2249 = and(_T_2247, _T_2248) @[lsu_bus_buffer.scala 412:57] + node _T_2250 = or(_T_2246, _T_2249) @[lsu_bus_buffer.scala 412:31] + node _T_2251 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2252 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2253 = and(_T_2251, _T_2252) @[lsu_bus_buffer.scala 413:41] + node _T_2254 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2255 = and(_T_2253, _T_2254) @[lsu_bus_buffer.scala 413:71] + node _T_2256 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2257 = and(_T_2255, _T_2256) @[lsu_bus_buffer.scala 413:92] + node _T_2258 = or(_T_2250, _T_2257) @[lsu_bus_buffer.scala 412:86] + node _T_2259 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2260 = and(_T_2259, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2261 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2262 = and(_T_2260, _T_2261) @[lsu_bus_buffer.scala 414:52] + node _T_2263 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2264 = and(_T_2262, _T_2263) @[lsu_bus_buffer.scala 414:73] + node _T_2265 = or(_T_2258, _T_2264) @[lsu_bus_buffer.scala 413:114] + node _T_2266 = and(_T_2245, _T_2265) @[lsu_bus_buffer.scala 411:113] + node _T_2267 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2268 = or(_T_2266, _T_2267) @[lsu_bus_buffer.scala 414:97] + node _T_2269 = cat(_T_2268, _T_2243) @[Cat.scala 29:58] + node _T_2270 = cat(_T_2269, _T_2218) @[Cat.scala 29:58] + node buf_age_in_1 = cat(_T_2270, _T_2193) @[Cat.scala 29:58] + node _T_2271 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2272 = and(_T_2271, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2273 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2274 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2275 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2276 = and(_T_2274, _T_2275) @[lsu_bus_buffer.scala 412:57] + node _T_2277 = or(_T_2273, _T_2276) @[lsu_bus_buffer.scala 412:31] + node _T_2278 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2279 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2280 = and(_T_2278, _T_2279) @[lsu_bus_buffer.scala 413:41] + node _T_2281 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2282 = and(_T_2280, _T_2281) @[lsu_bus_buffer.scala 413:71] + node _T_2283 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2284 = and(_T_2282, _T_2283) @[lsu_bus_buffer.scala 413:92] + node _T_2285 = or(_T_2277, _T_2284) @[lsu_bus_buffer.scala 412:86] + node _T_2286 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2287 = and(_T_2286, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2288 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2289 = and(_T_2287, _T_2288) @[lsu_bus_buffer.scala 414:52] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2291 = and(_T_2289, _T_2290) @[lsu_bus_buffer.scala 414:73] + node _T_2292 = or(_T_2285, _T_2291) @[lsu_bus_buffer.scala 413:114] + node _T_2293 = and(_T_2272, _T_2292) @[lsu_bus_buffer.scala 411:113] + node _T_2294 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2295 = or(_T_2293, _T_2294) @[lsu_bus_buffer.scala 414:97] + node _T_2296 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2297 = and(_T_2296, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2298 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2299 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2300 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2301 = and(_T_2299, _T_2300) @[lsu_bus_buffer.scala 412:57] + node _T_2302 = or(_T_2298, _T_2301) @[lsu_bus_buffer.scala 412:31] + node _T_2303 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2304 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2305 = and(_T_2303, _T_2304) @[lsu_bus_buffer.scala 413:41] + node _T_2306 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2307 = and(_T_2305, _T_2306) @[lsu_bus_buffer.scala 413:71] + node _T_2308 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2309 = and(_T_2307, _T_2308) @[lsu_bus_buffer.scala 413:92] + node _T_2310 = or(_T_2302, _T_2309) @[lsu_bus_buffer.scala 412:86] + node _T_2311 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2312 = and(_T_2311, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2313 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2314 = and(_T_2312, _T_2313) @[lsu_bus_buffer.scala 414:52] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2316 = and(_T_2314, _T_2315) @[lsu_bus_buffer.scala 414:73] + node _T_2317 = or(_T_2310, _T_2316) @[lsu_bus_buffer.scala 413:114] + node _T_2318 = and(_T_2297, _T_2317) @[lsu_bus_buffer.scala 411:113] + node _T_2319 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2320 = or(_T_2318, _T_2319) @[lsu_bus_buffer.scala 414:97] + node _T_2321 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2322 = and(_T_2321, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2323 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2324 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2325 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2326 = and(_T_2324, _T_2325) @[lsu_bus_buffer.scala 412:57] + node _T_2327 = or(_T_2323, _T_2326) @[lsu_bus_buffer.scala 412:31] + node _T_2328 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2329 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2330 = and(_T_2328, _T_2329) @[lsu_bus_buffer.scala 413:41] + node _T_2331 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2332 = and(_T_2330, _T_2331) @[lsu_bus_buffer.scala 413:71] + node _T_2333 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2334 = and(_T_2332, _T_2333) @[lsu_bus_buffer.scala 413:92] + node _T_2335 = or(_T_2327, _T_2334) @[lsu_bus_buffer.scala 412:86] + node _T_2336 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2337 = and(_T_2336, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2338 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2339 = and(_T_2337, _T_2338) @[lsu_bus_buffer.scala 414:52] + node _T_2340 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2341 = and(_T_2339, _T_2340) @[lsu_bus_buffer.scala 414:73] + node _T_2342 = or(_T_2335, _T_2341) @[lsu_bus_buffer.scala 413:114] + node _T_2343 = and(_T_2322, _T_2342) @[lsu_bus_buffer.scala 411:113] + node _T_2344 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2345 = or(_T_2343, _T_2344) @[lsu_bus_buffer.scala 414:97] + node _T_2346 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2347 = and(_T_2346, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2348 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2349 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2350 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2351 = and(_T_2349, _T_2350) @[lsu_bus_buffer.scala 412:57] + node _T_2352 = or(_T_2348, _T_2351) @[lsu_bus_buffer.scala 412:31] + node _T_2353 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2354 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2355 = and(_T_2353, _T_2354) @[lsu_bus_buffer.scala 413:41] + node _T_2356 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2357 = and(_T_2355, _T_2356) @[lsu_bus_buffer.scala 413:71] + node _T_2358 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2359 = and(_T_2357, _T_2358) @[lsu_bus_buffer.scala 413:92] + node _T_2360 = or(_T_2352, _T_2359) @[lsu_bus_buffer.scala 412:86] + node _T_2361 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2362 = and(_T_2361, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2363 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2364 = and(_T_2362, _T_2363) @[lsu_bus_buffer.scala 414:52] + node _T_2365 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2366 = and(_T_2364, _T_2365) @[lsu_bus_buffer.scala 414:73] + node _T_2367 = or(_T_2360, _T_2366) @[lsu_bus_buffer.scala 413:114] + node _T_2368 = and(_T_2347, _T_2367) @[lsu_bus_buffer.scala 411:113] + node _T_2369 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2370 = or(_T_2368, _T_2369) @[lsu_bus_buffer.scala 414:97] + node _T_2371 = cat(_T_2370, _T_2345) @[Cat.scala 29:58] + node _T_2372 = cat(_T_2371, _T_2320) @[Cat.scala 29:58] + node buf_age_in_2 = cat(_T_2372, _T_2295) @[Cat.scala 29:58] + node _T_2373 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2374 = and(_T_2373, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2375 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2376 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2377 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2378 = and(_T_2376, _T_2377) @[lsu_bus_buffer.scala 412:57] + node _T_2379 = or(_T_2375, _T_2378) @[lsu_bus_buffer.scala 412:31] + node _T_2380 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2381 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2382 = and(_T_2380, _T_2381) @[lsu_bus_buffer.scala 413:41] + node _T_2383 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2384 = and(_T_2382, _T_2383) @[lsu_bus_buffer.scala 413:71] + node _T_2385 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2386 = and(_T_2384, _T_2385) @[lsu_bus_buffer.scala 413:92] + node _T_2387 = or(_T_2379, _T_2386) @[lsu_bus_buffer.scala 412:86] + node _T_2388 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2389 = and(_T_2388, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2390 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2391 = and(_T_2389, _T_2390) @[lsu_bus_buffer.scala 414:52] + node _T_2392 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2393 = and(_T_2391, _T_2392) @[lsu_bus_buffer.scala 414:73] + node _T_2394 = or(_T_2387, _T_2393) @[lsu_bus_buffer.scala 413:114] + node _T_2395 = and(_T_2374, _T_2394) @[lsu_bus_buffer.scala 411:113] + node _T_2396 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2397 = or(_T_2395, _T_2396) @[lsu_bus_buffer.scala 414:97] + node _T_2398 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2399 = and(_T_2398, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2400 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2401 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2402 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2403 = and(_T_2401, _T_2402) @[lsu_bus_buffer.scala 412:57] + node _T_2404 = or(_T_2400, _T_2403) @[lsu_bus_buffer.scala 412:31] + node _T_2405 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2406 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2407 = and(_T_2405, _T_2406) @[lsu_bus_buffer.scala 413:41] + node _T_2408 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2409 = and(_T_2407, _T_2408) @[lsu_bus_buffer.scala 413:71] + node _T_2410 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2411 = and(_T_2409, _T_2410) @[lsu_bus_buffer.scala 413:92] + node _T_2412 = or(_T_2404, _T_2411) @[lsu_bus_buffer.scala 412:86] + node _T_2413 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2414 = and(_T_2413, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2415 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2416 = and(_T_2414, _T_2415) @[lsu_bus_buffer.scala 414:52] + node _T_2417 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2418 = and(_T_2416, _T_2417) @[lsu_bus_buffer.scala 414:73] + node _T_2419 = or(_T_2412, _T_2418) @[lsu_bus_buffer.scala 413:114] + node _T_2420 = and(_T_2399, _T_2419) @[lsu_bus_buffer.scala 411:113] + node _T_2421 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2422 = or(_T_2420, _T_2421) @[lsu_bus_buffer.scala 414:97] + node _T_2423 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2424 = and(_T_2423, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2425 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2426 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2427 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2428 = and(_T_2426, _T_2427) @[lsu_bus_buffer.scala 412:57] + node _T_2429 = or(_T_2425, _T_2428) @[lsu_bus_buffer.scala 412:31] + node _T_2430 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2431 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2432 = and(_T_2430, _T_2431) @[lsu_bus_buffer.scala 413:41] + node _T_2433 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2434 = and(_T_2432, _T_2433) @[lsu_bus_buffer.scala 413:71] + node _T_2435 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2436 = and(_T_2434, _T_2435) @[lsu_bus_buffer.scala 413:92] + node _T_2437 = or(_T_2429, _T_2436) @[lsu_bus_buffer.scala 412:86] + node _T_2438 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2439 = and(_T_2438, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2440 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2441 = and(_T_2439, _T_2440) @[lsu_bus_buffer.scala 414:52] + node _T_2442 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2443 = and(_T_2441, _T_2442) @[lsu_bus_buffer.scala 414:73] + node _T_2444 = or(_T_2437, _T_2443) @[lsu_bus_buffer.scala 413:114] + node _T_2445 = and(_T_2424, _T_2444) @[lsu_bus_buffer.scala 411:113] + node _T_2446 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2447 = or(_T_2445, _T_2446) @[lsu_bus_buffer.scala 414:97] + node _T_2448 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2449 = and(_T_2448, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2450 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2451 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2452 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2453 = and(_T_2451, _T_2452) @[lsu_bus_buffer.scala 412:57] + node _T_2454 = or(_T_2450, _T_2453) @[lsu_bus_buffer.scala 412:31] + node _T_2455 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2456 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2457 = and(_T_2455, _T_2456) @[lsu_bus_buffer.scala 413:41] + node _T_2458 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2459 = and(_T_2457, _T_2458) @[lsu_bus_buffer.scala 413:71] + node _T_2460 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2461 = and(_T_2459, _T_2460) @[lsu_bus_buffer.scala 413:92] + node _T_2462 = or(_T_2454, _T_2461) @[lsu_bus_buffer.scala 412:86] + node _T_2463 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2464 = and(_T_2463, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2465 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2466 = and(_T_2464, _T_2465) @[lsu_bus_buffer.scala 414:52] + node _T_2467 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2468 = and(_T_2466, _T_2467) @[lsu_bus_buffer.scala 414:73] + node _T_2469 = or(_T_2462, _T_2468) @[lsu_bus_buffer.scala 413:114] + node _T_2470 = and(_T_2449, _T_2469) @[lsu_bus_buffer.scala 411:113] + node _T_2471 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2472 = or(_T_2470, _T_2471) @[lsu_bus_buffer.scala 414:97] + node _T_2473 = cat(_T_2472, _T_2447) @[Cat.scala 29:58] + node _T_2474 = cat(_T_2473, _T_2422) @[Cat.scala 29:58] + node buf_age_in_3 = cat(_T_2474, _T_2397) @[Cat.scala 29:58] + wire buf_ageQ : UInt<4>[4] @[lsu_bus_buffer.scala 415:22] + buf_ageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + node _T_2475 = bits(buf_ageQ[0], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2476 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2477 = and(_T_2476, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2478 = eq(_T_2477, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2479 = and(_T_2475, _T_2478) @[lsu_bus_buffer.scala 417:76] + node _T_2480 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2481 = and(_T_2479, _T_2480) @[lsu_bus_buffer.scala 417:130] + node _T_2482 = bits(buf_ageQ[0], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2483 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2484 = and(_T_2483, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2485 = eq(_T_2484, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2486 = and(_T_2482, _T_2485) @[lsu_bus_buffer.scala 417:76] + node _T_2487 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2488 = and(_T_2486, _T_2487) @[lsu_bus_buffer.scala 417:130] + node _T_2489 = bits(buf_ageQ[0], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2490 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2491 = and(_T_2490, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2492 = eq(_T_2491, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2493 = and(_T_2489, _T_2492) @[lsu_bus_buffer.scala 417:76] + node _T_2494 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2495 = and(_T_2493, _T_2494) @[lsu_bus_buffer.scala 417:130] + node _T_2496 = bits(buf_ageQ[0], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2497 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2498 = and(_T_2497, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2499 = eq(_T_2498, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2500 = and(_T_2496, _T_2499) @[lsu_bus_buffer.scala 417:76] + node _T_2501 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2502 = and(_T_2500, _T_2501) @[lsu_bus_buffer.scala 417:130] + node _T_2503 = cat(_T_2502, _T_2495) @[Cat.scala 29:58] + node _T_2504 = cat(_T_2503, _T_2488) @[Cat.scala 29:58] + node _T_2505 = cat(_T_2504, _T_2481) @[Cat.scala 29:58] + node _T_2506 = bits(buf_ageQ[1], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2507 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2508 = and(_T_2507, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2509 = eq(_T_2508, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2510 = and(_T_2506, _T_2509) @[lsu_bus_buffer.scala 417:76] + node _T_2511 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2512 = and(_T_2510, _T_2511) @[lsu_bus_buffer.scala 417:130] + node _T_2513 = bits(buf_ageQ[1], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2514 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2515 = and(_T_2514, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2516 = eq(_T_2515, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2517 = and(_T_2513, _T_2516) @[lsu_bus_buffer.scala 417:76] + node _T_2518 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2519 = and(_T_2517, _T_2518) @[lsu_bus_buffer.scala 417:130] + node _T_2520 = bits(buf_ageQ[1], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2521 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2522 = and(_T_2521, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2523 = eq(_T_2522, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2524 = and(_T_2520, _T_2523) @[lsu_bus_buffer.scala 417:76] + node _T_2525 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2526 = and(_T_2524, _T_2525) @[lsu_bus_buffer.scala 417:130] + node _T_2527 = bits(buf_ageQ[1], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2528 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2529 = and(_T_2528, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2530 = eq(_T_2529, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2531 = and(_T_2527, _T_2530) @[lsu_bus_buffer.scala 417:76] + node _T_2532 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2533 = and(_T_2531, _T_2532) @[lsu_bus_buffer.scala 417:130] + node _T_2534 = cat(_T_2533, _T_2526) @[Cat.scala 29:58] + node _T_2535 = cat(_T_2534, _T_2519) @[Cat.scala 29:58] + node _T_2536 = cat(_T_2535, _T_2512) @[Cat.scala 29:58] + node _T_2537 = bits(buf_ageQ[2], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2538 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2539 = and(_T_2538, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2540 = eq(_T_2539, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2541 = and(_T_2537, _T_2540) @[lsu_bus_buffer.scala 417:76] + node _T_2542 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2543 = and(_T_2541, _T_2542) @[lsu_bus_buffer.scala 417:130] + node _T_2544 = bits(buf_ageQ[2], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2545 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2546 = and(_T_2545, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2547 = eq(_T_2546, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2548 = and(_T_2544, _T_2547) @[lsu_bus_buffer.scala 417:76] + node _T_2549 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2550 = and(_T_2548, _T_2549) @[lsu_bus_buffer.scala 417:130] + node _T_2551 = bits(buf_ageQ[2], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2552 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2555 = and(_T_2551, _T_2554) @[lsu_bus_buffer.scala 417:76] + node _T_2556 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2557 = and(_T_2555, _T_2556) @[lsu_bus_buffer.scala 417:130] + node _T_2558 = bits(buf_ageQ[2], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2559 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2560 = and(_T_2559, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2561 = eq(_T_2560, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2562 = and(_T_2558, _T_2561) @[lsu_bus_buffer.scala 417:76] + node _T_2563 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2564 = and(_T_2562, _T_2563) @[lsu_bus_buffer.scala 417:130] + node _T_2565 = cat(_T_2564, _T_2557) @[Cat.scala 29:58] + node _T_2566 = cat(_T_2565, _T_2550) @[Cat.scala 29:58] + node _T_2567 = cat(_T_2566, _T_2543) @[Cat.scala 29:58] + node _T_2568 = bits(buf_ageQ[3], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2569 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2570 = and(_T_2569, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2571 = eq(_T_2570, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2572 = and(_T_2568, _T_2571) @[lsu_bus_buffer.scala 417:76] + node _T_2573 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2574 = and(_T_2572, _T_2573) @[lsu_bus_buffer.scala 417:130] + node _T_2575 = bits(buf_ageQ[3], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2576 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2577 = and(_T_2576, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2578 = eq(_T_2577, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2579 = and(_T_2575, _T_2578) @[lsu_bus_buffer.scala 417:76] + node _T_2580 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2581 = and(_T_2579, _T_2580) @[lsu_bus_buffer.scala 417:130] + node _T_2582 = bits(buf_ageQ[3], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2583 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2586 = and(_T_2582, _T_2585) @[lsu_bus_buffer.scala 417:76] + node _T_2587 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2588 = and(_T_2586, _T_2587) @[lsu_bus_buffer.scala 417:130] + node _T_2589 = bits(buf_ageQ[3], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2590 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2591 = and(_T_2590, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2592 = eq(_T_2591, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2593 = and(_T_2589, _T_2592) @[lsu_bus_buffer.scala 417:76] + node _T_2594 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2595 = and(_T_2593, _T_2594) @[lsu_bus_buffer.scala 417:130] + node _T_2596 = cat(_T_2595, _T_2588) @[Cat.scala 29:58] + node _T_2597 = cat(_T_2596, _T_2581) @[Cat.scala 29:58] + node _T_2598 = cat(_T_2597, _T_2574) @[Cat.scala 29:58] + buf_age[0] <= _T_2505 @[lsu_bus_buffer.scala 417:11] + buf_age[1] <= _T_2536 @[lsu_bus_buffer.scala 417:11] + buf_age[2] <= _T_2567 @[lsu_bus_buffer.scala 417:11] + buf_age[3] <= _T_2598 @[lsu_bus_buffer.scala 417:11] + node _T_2599 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2600 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2601 = eq(_T_2600, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2602 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2603 = and(_T_2601, _T_2602) @[lsu_bus_buffer.scala 418:104] + node _T_2604 = mux(_T_2599, UInt<1>("h00"), _T_2603) @[lsu_bus_buffer.scala 418:72] + node _T_2605 = eq(UInt<1>("h00"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2606 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2607 = eq(_T_2606, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2608 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2609 = and(_T_2607, _T_2608) @[lsu_bus_buffer.scala 418:104] + node _T_2610 = mux(_T_2605, UInt<1>("h00"), _T_2609) @[lsu_bus_buffer.scala 418:72] + node _T_2611 = eq(UInt<1>("h00"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2612 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2614 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2615 = and(_T_2613, _T_2614) @[lsu_bus_buffer.scala 418:104] + node _T_2616 = mux(_T_2611, UInt<1>("h00"), _T_2615) @[lsu_bus_buffer.scala 418:72] + node _T_2617 = eq(UInt<1>("h00"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2618 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2619 = eq(_T_2618, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2620 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2621 = and(_T_2619, _T_2620) @[lsu_bus_buffer.scala 418:104] + node _T_2622 = mux(_T_2617, UInt<1>("h00"), _T_2621) @[lsu_bus_buffer.scala 418:72] + node _T_2623 = cat(_T_2622, _T_2616) @[Cat.scala 29:58] + node _T_2624 = cat(_T_2623, _T_2610) @[Cat.scala 29:58] + node _T_2625 = cat(_T_2624, _T_2604) @[Cat.scala 29:58] + node _T_2626 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2627 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2628 = eq(_T_2627, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2629 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2630 = and(_T_2628, _T_2629) @[lsu_bus_buffer.scala 418:104] + node _T_2631 = mux(_T_2626, UInt<1>("h00"), _T_2630) @[lsu_bus_buffer.scala 418:72] + node _T_2632 = eq(UInt<1>("h01"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2633 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2634 = eq(_T_2633, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2635 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2636 = and(_T_2634, _T_2635) @[lsu_bus_buffer.scala 418:104] + node _T_2637 = mux(_T_2632, UInt<1>("h00"), _T_2636) @[lsu_bus_buffer.scala 418:72] + node _T_2638 = eq(UInt<1>("h01"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2639 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2640 = eq(_T_2639, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2641 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2642 = and(_T_2640, _T_2641) @[lsu_bus_buffer.scala 418:104] + node _T_2643 = mux(_T_2638, UInt<1>("h00"), _T_2642) @[lsu_bus_buffer.scala 418:72] + node _T_2644 = eq(UInt<1>("h01"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2645 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2646 = eq(_T_2645, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2647 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2648 = and(_T_2646, _T_2647) @[lsu_bus_buffer.scala 418:104] + node _T_2649 = mux(_T_2644, UInt<1>("h00"), _T_2648) @[lsu_bus_buffer.scala 418:72] + node _T_2650 = cat(_T_2649, _T_2643) @[Cat.scala 29:58] + node _T_2651 = cat(_T_2650, _T_2637) @[Cat.scala 29:58] + node _T_2652 = cat(_T_2651, _T_2631) @[Cat.scala 29:58] + node _T_2653 = eq(UInt<2>("h02"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2654 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2655 = eq(_T_2654, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2656 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2657 = and(_T_2655, _T_2656) @[lsu_bus_buffer.scala 418:104] + node _T_2658 = mux(_T_2653, UInt<1>("h00"), _T_2657) @[lsu_bus_buffer.scala 418:72] + node _T_2659 = eq(UInt<2>("h02"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2660 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2661 = eq(_T_2660, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2662 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2663 = and(_T_2661, _T_2662) @[lsu_bus_buffer.scala 418:104] + node _T_2664 = mux(_T_2659, UInt<1>("h00"), _T_2663) @[lsu_bus_buffer.scala 418:72] + node _T_2665 = eq(UInt<2>("h02"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2666 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2667 = eq(_T_2666, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2668 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2669 = and(_T_2667, _T_2668) @[lsu_bus_buffer.scala 418:104] + node _T_2670 = mux(_T_2665, UInt<1>("h00"), _T_2669) @[lsu_bus_buffer.scala 418:72] + node _T_2671 = eq(UInt<2>("h02"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2672 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2673 = eq(_T_2672, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2674 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2675 = and(_T_2673, _T_2674) @[lsu_bus_buffer.scala 418:104] + node _T_2676 = mux(_T_2671, UInt<1>("h00"), _T_2675) @[lsu_bus_buffer.scala 418:72] + node _T_2677 = cat(_T_2676, _T_2670) @[Cat.scala 29:58] + node _T_2678 = cat(_T_2677, _T_2664) @[Cat.scala 29:58] + node _T_2679 = cat(_T_2678, _T_2658) @[Cat.scala 29:58] + node _T_2680 = eq(UInt<2>("h03"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2681 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2682 = eq(_T_2681, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2683 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2684 = and(_T_2682, _T_2683) @[lsu_bus_buffer.scala 418:104] + node _T_2685 = mux(_T_2680, UInt<1>("h00"), _T_2684) @[lsu_bus_buffer.scala 418:72] + node _T_2686 = eq(UInt<2>("h03"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2687 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2688 = eq(_T_2687, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2689 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2690 = and(_T_2688, _T_2689) @[lsu_bus_buffer.scala 418:104] + node _T_2691 = mux(_T_2686, UInt<1>("h00"), _T_2690) @[lsu_bus_buffer.scala 418:72] + node _T_2692 = eq(UInt<2>("h03"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2693 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2694 = eq(_T_2693, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2695 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2696 = and(_T_2694, _T_2695) @[lsu_bus_buffer.scala 418:104] + node _T_2697 = mux(_T_2692, UInt<1>("h00"), _T_2696) @[lsu_bus_buffer.scala 418:72] + node _T_2698 = eq(UInt<2>("h03"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2699 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2700 = eq(_T_2699, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2701 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2702 = and(_T_2700, _T_2701) @[lsu_bus_buffer.scala 418:104] + node _T_2703 = mux(_T_2698, UInt<1>("h00"), _T_2702) @[lsu_bus_buffer.scala 418:72] + node _T_2704 = cat(_T_2703, _T_2697) @[Cat.scala 29:58] + node _T_2705 = cat(_T_2704, _T_2691) @[Cat.scala 29:58] + node _T_2706 = cat(_T_2705, _T_2685) @[Cat.scala 29:58] + buf_age_younger[0] <= _T_2625 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[1] <= _T_2652 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[2] <= _T_2679 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[3] <= _T_2706 @[lsu_bus_buffer.scala 418:19] + node _T_2707 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2708 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2709 = and(_T_2707, _T_2708) @[lsu_bus_buffer.scala 419:87] + node _T_2710 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2711 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2712 = and(_T_2710, _T_2711) @[lsu_bus_buffer.scala 419:87] + node _T_2713 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2714 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2715 = and(_T_2713, _T_2714) @[lsu_bus_buffer.scala 419:87] + node _T_2716 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2717 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2718 = and(_T_2716, _T_2717) @[lsu_bus_buffer.scala 419:87] + node _T_2719 = cat(_T_2718, _T_2715) @[Cat.scala 29:58] + node _T_2720 = cat(_T_2719, _T_2712) @[Cat.scala 29:58] + node _T_2721 = cat(_T_2720, _T_2709) @[Cat.scala 29:58] + node _T_2722 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2723 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2724 = and(_T_2722, _T_2723) @[lsu_bus_buffer.scala 419:87] + node _T_2725 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2726 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2727 = and(_T_2725, _T_2726) @[lsu_bus_buffer.scala 419:87] + node _T_2728 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2729 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2730 = and(_T_2728, _T_2729) @[lsu_bus_buffer.scala 419:87] + node _T_2731 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2732 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2733 = and(_T_2731, _T_2732) @[lsu_bus_buffer.scala 419:87] + node _T_2734 = cat(_T_2733, _T_2730) @[Cat.scala 29:58] + node _T_2735 = cat(_T_2734, _T_2727) @[Cat.scala 29:58] + node _T_2736 = cat(_T_2735, _T_2724) @[Cat.scala 29:58] + node _T_2737 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2738 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2739 = and(_T_2737, _T_2738) @[lsu_bus_buffer.scala 419:87] + node _T_2740 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2741 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2742 = and(_T_2740, _T_2741) @[lsu_bus_buffer.scala 419:87] + node _T_2743 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2744 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2745 = and(_T_2743, _T_2744) @[lsu_bus_buffer.scala 419:87] + node _T_2746 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2747 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2748 = and(_T_2746, _T_2747) @[lsu_bus_buffer.scala 419:87] + node _T_2749 = cat(_T_2748, _T_2745) @[Cat.scala 29:58] + node _T_2750 = cat(_T_2749, _T_2742) @[Cat.scala 29:58] + node _T_2751 = cat(_T_2750, _T_2739) @[Cat.scala 29:58] + node _T_2752 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2753 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2754 = and(_T_2752, _T_2753) @[lsu_bus_buffer.scala 419:87] + node _T_2755 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2756 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2757 = and(_T_2755, _T_2756) @[lsu_bus_buffer.scala 419:87] + node _T_2758 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2759 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2760 = and(_T_2758, _T_2759) @[lsu_bus_buffer.scala 419:87] + node _T_2761 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2762 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2763 = and(_T_2761, _T_2762) @[lsu_bus_buffer.scala 419:87] + node _T_2764 = cat(_T_2763, _T_2760) @[Cat.scala 29:58] + node _T_2765 = cat(_T_2764, _T_2757) @[Cat.scala 29:58] + node _T_2766 = cat(_T_2765, _T_2754) @[Cat.scala 29:58] + buf_rsp_pickage[0] <= _T_2721 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[1] <= _T_2736 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[2] <= _T_2751 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[3] <= _T_2766 @[lsu_bus_buffer.scala 419:19] + node _T_2767 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2768 = and(_T_2767, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2769 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2770 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2771 = or(_T_2769, _T_2770) @[lsu_bus_buffer.scala 422:32] + node _T_2772 = eq(_T_2771, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2773 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2774 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2775 = and(_T_2773, _T_2774) @[lsu_bus_buffer.scala 423:41] + node _T_2776 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2777 = and(_T_2775, _T_2776) @[lsu_bus_buffer.scala 423:71] + node _T_2778 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2779 = and(_T_2777, _T_2778) @[lsu_bus_buffer.scala 423:90] + node _T_2780 = or(_T_2772, _T_2779) @[lsu_bus_buffer.scala 422:59] + node _T_2781 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2782 = and(_T_2781, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2783 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2784 = and(_T_2782, _T_2783) @[lsu_bus_buffer.scala 424:52] + node _T_2785 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2786 = and(_T_2784, _T_2785) @[lsu_bus_buffer.scala 424:71] + node _T_2787 = or(_T_2780, _T_2786) @[lsu_bus_buffer.scala 423:110] + node _T_2788 = and(_T_2768, _T_2787) @[lsu_bus_buffer.scala 421:112] + node _T_2789 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2790 = and(_T_2789, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2791 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2792 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2793 = or(_T_2791, _T_2792) @[lsu_bus_buffer.scala 422:32] + node _T_2794 = eq(_T_2793, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2795 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2796 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2797 = and(_T_2795, _T_2796) @[lsu_bus_buffer.scala 423:41] + node _T_2798 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2799 = and(_T_2797, _T_2798) @[lsu_bus_buffer.scala 423:71] + node _T_2800 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2801 = and(_T_2799, _T_2800) @[lsu_bus_buffer.scala 423:90] + node _T_2802 = or(_T_2794, _T_2801) @[lsu_bus_buffer.scala 422:59] + node _T_2803 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2804 = and(_T_2803, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2805 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2806 = and(_T_2804, _T_2805) @[lsu_bus_buffer.scala 424:52] + node _T_2807 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2808 = and(_T_2806, _T_2807) @[lsu_bus_buffer.scala 424:71] + node _T_2809 = or(_T_2802, _T_2808) @[lsu_bus_buffer.scala 423:110] + node _T_2810 = and(_T_2790, _T_2809) @[lsu_bus_buffer.scala 421:112] + node _T_2811 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2812 = and(_T_2811, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2813 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2814 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2815 = or(_T_2813, _T_2814) @[lsu_bus_buffer.scala 422:32] + node _T_2816 = eq(_T_2815, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2817 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2818 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2819 = and(_T_2817, _T_2818) @[lsu_bus_buffer.scala 423:41] + node _T_2820 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2821 = and(_T_2819, _T_2820) @[lsu_bus_buffer.scala 423:71] + node _T_2822 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_2823 = and(_T_2821, _T_2822) @[lsu_bus_buffer.scala 423:90] + node _T_2824 = or(_T_2816, _T_2823) @[lsu_bus_buffer.scala 422:59] + node _T_2825 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2826 = and(_T_2825, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2827 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2828 = and(_T_2826, _T_2827) @[lsu_bus_buffer.scala 424:52] + node _T_2829 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_2830 = and(_T_2828, _T_2829) @[lsu_bus_buffer.scala 424:71] + node _T_2831 = or(_T_2824, _T_2830) @[lsu_bus_buffer.scala 423:110] + node _T_2832 = and(_T_2812, _T_2831) @[lsu_bus_buffer.scala 421:112] + node _T_2833 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2834 = and(_T_2833, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2835 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2836 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2837 = or(_T_2835, _T_2836) @[lsu_bus_buffer.scala 422:32] + node _T_2838 = eq(_T_2837, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2839 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2840 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2841 = and(_T_2839, _T_2840) @[lsu_bus_buffer.scala 423:41] + node _T_2842 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2843 = and(_T_2841, _T_2842) @[lsu_bus_buffer.scala 423:71] + node _T_2844 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_2845 = and(_T_2843, _T_2844) @[lsu_bus_buffer.scala 423:90] + node _T_2846 = or(_T_2838, _T_2845) @[lsu_bus_buffer.scala 422:59] + node _T_2847 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2848 = and(_T_2847, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2849 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2850 = and(_T_2848, _T_2849) @[lsu_bus_buffer.scala 424:52] + node _T_2851 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_2852 = and(_T_2850, _T_2851) @[lsu_bus_buffer.scala 424:71] + node _T_2853 = or(_T_2846, _T_2852) @[lsu_bus_buffer.scala 423:110] + node _T_2854 = and(_T_2834, _T_2853) @[lsu_bus_buffer.scala 421:112] + node _T_2855 = cat(_T_2854, _T_2832) @[Cat.scala 29:58] + node _T_2856 = cat(_T_2855, _T_2810) @[Cat.scala 29:58] + node _T_2857 = cat(_T_2856, _T_2788) @[Cat.scala 29:58] + node _T_2858 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2859 = and(_T_2858, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2860 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2861 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2862 = or(_T_2860, _T_2861) @[lsu_bus_buffer.scala 422:32] + node _T_2863 = eq(_T_2862, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2864 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2865 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2866 = and(_T_2864, _T_2865) @[lsu_bus_buffer.scala 423:41] + node _T_2867 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2868 = and(_T_2866, _T_2867) @[lsu_bus_buffer.scala 423:71] + node _T_2869 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2870 = and(_T_2868, _T_2869) @[lsu_bus_buffer.scala 423:90] + node _T_2871 = or(_T_2863, _T_2870) @[lsu_bus_buffer.scala 422:59] + node _T_2872 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2873 = and(_T_2872, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2874 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2875 = and(_T_2873, _T_2874) @[lsu_bus_buffer.scala 424:52] + node _T_2876 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2877 = and(_T_2875, _T_2876) @[lsu_bus_buffer.scala 424:71] + node _T_2878 = or(_T_2871, _T_2877) @[lsu_bus_buffer.scala 423:110] + node _T_2879 = and(_T_2859, _T_2878) @[lsu_bus_buffer.scala 421:112] + node _T_2880 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2881 = and(_T_2880, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2882 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2883 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2884 = or(_T_2882, _T_2883) @[lsu_bus_buffer.scala 422:32] + node _T_2885 = eq(_T_2884, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2886 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2887 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2888 = and(_T_2886, _T_2887) @[lsu_bus_buffer.scala 423:41] + node _T_2889 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2890 = and(_T_2888, _T_2889) @[lsu_bus_buffer.scala 423:71] + node _T_2891 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2892 = and(_T_2890, _T_2891) @[lsu_bus_buffer.scala 423:90] + node _T_2893 = or(_T_2885, _T_2892) @[lsu_bus_buffer.scala 422:59] + node _T_2894 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2895 = and(_T_2894, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2896 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2897 = and(_T_2895, _T_2896) @[lsu_bus_buffer.scala 424:52] + node _T_2898 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2899 = and(_T_2897, _T_2898) @[lsu_bus_buffer.scala 424:71] + node _T_2900 = or(_T_2893, _T_2899) @[lsu_bus_buffer.scala 423:110] + node _T_2901 = and(_T_2881, _T_2900) @[lsu_bus_buffer.scala 421:112] + node _T_2902 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2903 = and(_T_2902, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2904 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2905 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2906 = or(_T_2904, _T_2905) @[lsu_bus_buffer.scala 422:32] + node _T_2907 = eq(_T_2906, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2908 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2909 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2910 = and(_T_2908, _T_2909) @[lsu_bus_buffer.scala 423:41] + node _T_2911 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2912 = and(_T_2910, _T_2911) @[lsu_bus_buffer.scala 423:71] + node _T_2913 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_2914 = and(_T_2912, _T_2913) @[lsu_bus_buffer.scala 423:90] + node _T_2915 = or(_T_2907, _T_2914) @[lsu_bus_buffer.scala 422:59] + node _T_2916 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2917 = and(_T_2916, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2918 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2919 = and(_T_2917, _T_2918) @[lsu_bus_buffer.scala 424:52] + node _T_2920 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_2921 = and(_T_2919, _T_2920) @[lsu_bus_buffer.scala 424:71] + node _T_2922 = or(_T_2915, _T_2921) @[lsu_bus_buffer.scala 423:110] + node _T_2923 = and(_T_2903, _T_2922) @[lsu_bus_buffer.scala 421:112] + node _T_2924 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2925 = and(_T_2924, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2926 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2927 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2928 = or(_T_2926, _T_2927) @[lsu_bus_buffer.scala 422:32] + node _T_2929 = eq(_T_2928, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2930 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2931 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2932 = and(_T_2930, _T_2931) @[lsu_bus_buffer.scala 423:41] + node _T_2933 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2934 = and(_T_2932, _T_2933) @[lsu_bus_buffer.scala 423:71] + node _T_2935 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_2936 = and(_T_2934, _T_2935) @[lsu_bus_buffer.scala 423:90] + node _T_2937 = or(_T_2929, _T_2936) @[lsu_bus_buffer.scala 422:59] + node _T_2938 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2939 = and(_T_2938, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2940 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2941 = and(_T_2939, _T_2940) @[lsu_bus_buffer.scala 424:52] + node _T_2942 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_2943 = and(_T_2941, _T_2942) @[lsu_bus_buffer.scala 424:71] + node _T_2944 = or(_T_2937, _T_2943) @[lsu_bus_buffer.scala 423:110] + node _T_2945 = and(_T_2925, _T_2944) @[lsu_bus_buffer.scala 421:112] + node _T_2946 = cat(_T_2945, _T_2923) @[Cat.scala 29:58] + node _T_2947 = cat(_T_2946, _T_2901) @[Cat.scala 29:58] + node _T_2948 = cat(_T_2947, _T_2879) @[Cat.scala 29:58] + node _T_2949 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2950 = and(_T_2949, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2951 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2952 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2953 = or(_T_2951, _T_2952) @[lsu_bus_buffer.scala 422:32] + node _T_2954 = eq(_T_2953, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2955 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2956 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2957 = and(_T_2955, _T_2956) @[lsu_bus_buffer.scala 423:41] + node _T_2958 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_2959 = and(_T_2957, _T_2958) @[lsu_bus_buffer.scala 423:71] + node _T_2960 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2961 = and(_T_2959, _T_2960) @[lsu_bus_buffer.scala 423:90] + node _T_2962 = or(_T_2954, _T_2961) @[lsu_bus_buffer.scala 422:59] + node _T_2963 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2964 = and(_T_2963, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2965 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_2966 = and(_T_2964, _T_2965) @[lsu_bus_buffer.scala 424:52] + node _T_2967 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2968 = and(_T_2966, _T_2967) @[lsu_bus_buffer.scala 424:71] + node _T_2969 = or(_T_2962, _T_2968) @[lsu_bus_buffer.scala 423:110] + node _T_2970 = and(_T_2950, _T_2969) @[lsu_bus_buffer.scala 421:112] + node _T_2971 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2972 = and(_T_2971, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2973 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2974 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2975 = or(_T_2973, _T_2974) @[lsu_bus_buffer.scala 422:32] + node _T_2976 = eq(_T_2975, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2977 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2978 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2979 = and(_T_2977, _T_2978) @[lsu_bus_buffer.scala 423:41] + node _T_2980 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_2981 = and(_T_2979, _T_2980) @[lsu_bus_buffer.scala 423:71] + node _T_2982 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2983 = and(_T_2981, _T_2982) @[lsu_bus_buffer.scala 423:90] + node _T_2984 = or(_T_2976, _T_2983) @[lsu_bus_buffer.scala 422:59] + node _T_2985 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2986 = and(_T_2985, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2987 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_2988 = and(_T_2986, _T_2987) @[lsu_bus_buffer.scala 424:52] + node _T_2989 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2990 = and(_T_2988, _T_2989) @[lsu_bus_buffer.scala 424:71] + node _T_2991 = or(_T_2984, _T_2990) @[lsu_bus_buffer.scala 423:110] + node _T_2992 = and(_T_2972, _T_2991) @[lsu_bus_buffer.scala 421:112] + node _T_2993 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2994 = and(_T_2993, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2995 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2996 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2997 = or(_T_2995, _T_2996) @[lsu_bus_buffer.scala 422:32] + node _T_2998 = eq(_T_2997, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2999 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3000 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3001 = and(_T_2999, _T_3000) @[lsu_bus_buffer.scala 423:41] + node _T_3002 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_3003 = and(_T_3001, _T_3002) @[lsu_bus_buffer.scala 423:71] + node _T_3004 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_3005 = and(_T_3003, _T_3004) @[lsu_bus_buffer.scala 423:90] + node _T_3006 = or(_T_2998, _T_3005) @[lsu_bus_buffer.scala 422:59] + node _T_3007 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3008 = and(_T_3007, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3009 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_3010 = and(_T_3008, _T_3009) @[lsu_bus_buffer.scala 424:52] + node _T_3011 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_3012 = and(_T_3010, _T_3011) @[lsu_bus_buffer.scala 424:71] + node _T_3013 = or(_T_3006, _T_3012) @[lsu_bus_buffer.scala 423:110] + node _T_3014 = and(_T_2994, _T_3013) @[lsu_bus_buffer.scala 421:112] + node _T_3015 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3016 = and(_T_3015, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_3017 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3018 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3019 = or(_T_3017, _T_3018) @[lsu_bus_buffer.scala 422:32] + node _T_3020 = eq(_T_3019, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3021 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3022 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3023 = and(_T_3021, _T_3022) @[lsu_bus_buffer.scala 423:41] + node _T_3024 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_3025 = and(_T_3023, _T_3024) @[lsu_bus_buffer.scala 423:71] + node _T_3026 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_3027 = and(_T_3025, _T_3026) @[lsu_bus_buffer.scala 423:90] + node _T_3028 = or(_T_3020, _T_3027) @[lsu_bus_buffer.scala 422:59] + node _T_3029 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3030 = and(_T_3029, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3031 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_3032 = and(_T_3030, _T_3031) @[lsu_bus_buffer.scala 424:52] + node _T_3033 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_3034 = and(_T_3032, _T_3033) @[lsu_bus_buffer.scala 424:71] + node _T_3035 = or(_T_3028, _T_3034) @[lsu_bus_buffer.scala 423:110] + node _T_3036 = and(_T_3016, _T_3035) @[lsu_bus_buffer.scala 421:112] + node _T_3037 = cat(_T_3036, _T_3014) @[Cat.scala 29:58] + node _T_3038 = cat(_T_3037, _T_2992) @[Cat.scala 29:58] + node _T_3039 = cat(_T_3038, _T_2970) @[Cat.scala 29:58] + node _T_3040 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3041 = and(_T_3040, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3042 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3043 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3044 = or(_T_3042, _T_3043) @[lsu_bus_buffer.scala 422:32] + node _T_3045 = eq(_T_3044, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3046 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3047 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3048 = and(_T_3046, _T_3047) @[lsu_bus_buffer.scala 423:41] + node _T_3049 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3050 = and(_T_3048, _T_3049) @[lsu_bus_buffer.scala 423:71] + node _T_3051 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_3052 = and(_T_3050, _T_3051) @[lsu_bus_buffer.scala 423:90] + node _T_3053 = or(_T_3045, _T_3052) @[lsu_bus_buffer.scala 422:59] + node _T_3054 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3055 = and(_T_3054, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3056 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3057 = and(_T_3055, _T_3056) @[lsu_bus_buffer.scala 424:52] + node _T_3058 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_3059 = and(_T_3057, _T_3058) @[lsu_bus_buffer.scala 424:71] + node _T_3060 = or(_T_3053, _T_3059) @[lsu_bus_buffer.scala 423:110] + node _T_3061 = and(_T_3041, _T_3060) @[lsu_bus_buffer.scala 421:112] + node _T_3062 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3063 = and(_T_3062, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3064 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3065 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3066 = or(_T_3064, _T_3065) @[lsu_bus_buffer.scala 422:32] + node _T_3067 = eq(_T_3066, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3068 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3069 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3070 = and(_T_3068, _T_3069) @[lsu_bus_buffer.scala 423:41] + node _T_3071 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3072 = and(_T_3070, _T_3071) @[lsu_bus_buffer.scala 423:71] + node _T_3073 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_3074 = and(_T_3072, _T_3073) @[lsu_bus_buffer.scala 423:90] + node _T_3075 = or(_T_3067, _T_3074) @[lsu_bus_buffer.scala 422:59] + node _T_3076 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3077 = and(_T_3076, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3078 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3079 = and(_T_3077, _T_3078) @[lsu_bus_buffer.scala 424:52] + node _T_3080 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_3081 = and(_T_3079, _T_3080) @[lsu_bus_buffer.scala 424:71] + node _T_3082 = or(_T_3075, _T_3081) @[lsu_bus_buffer.scala 423:110] + node _T_3083 = and(_T_3063, _T_3082) @[lsu_bus_buffer.scala 421:112] + node _T_3084 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3085 = and(_T_3084, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3086 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3087 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3088 = or(_T_3086, _T_3087) @[lsu_bus_buffer.scala 422:32] + node _T_3089 = eq(_T_3088, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3090 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3091 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3092 = and(_T_3090, _T_3091) @[lsu_bus_buffer.scala 423:41] + node _T_3093 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3094 = and(_T_3092, _T_3093) @[lsu_bus_buffer.scala 423:71] + node _T_3095 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_3096 = and(_T_3094, _T_3095) @[lsu_bus_buffer.scala 423:90] + node _T_3097 = or(_T_3089, _T_3096) @[lsu_bus_buffer.scala 422:59] + node _T_3098 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3099 = and(_T_3098, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3100 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3101 = and(_T_3099, _T_3100) @[lsu_bus_buffer.scala 424:52] + node _T_3102 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_3103 = and(_T_3101, _T_3102) @[lsu_bus_buffer.scala 424:71] + node _T_3104 = or(_T_3097, _T_3103) @[lsu_bus_buffer.scala 423:110] + node _T_3105 = and(_T_3085, _T_3104) @[lsu_bus_buffer.scala 421:112] + node _T_3106 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3107 = and(_T_3106, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3108 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3109 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3110 = or(_T_3108, _T_3109) @[lsu_bus_buffer.scala 422:32] + node _T_3111 = eq(_T_3110, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3112 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3113 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3114 = and(_T_3112, _T_3113) @[lsu_bus_buffer.scala 423:41] + node _T_3115 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3116 = and(_T_3114, _T_3115) @[lsu_bus_buffer.scala 423:71] + node _T_3117 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_3118 = and(_T_3116, _T_3117) @[lsu_bus_buffer.scala 423:90] + node _T_3119 = or(_T_3111, _T_3118) @[lsu_bus_buffer.scala 422:59] + node _T_3120 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3121 = and(_T_3120, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3122 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3123 = and(_T_3121, _T_3122) @[lsu_bus_buffer.scala 424:52] + node _T_3124 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_3125 = and(_T_3123, _T_3124) @[lsu_bus_buffer.scala 424:71] + node _T_3126 = or(_T_3119, _T_3125) @[lsu_bus_buffer.scala 423:110] + node _T_3127 = and(_T_3107, _T_3126) @[lsu_bus_buffer.scala 421:112] + node _T_3128 = cat(_T_3127, _T_3105) @[Cat.scala 29:58] + node _T_3129 = cat(_T_3128, _T_3083) @[Cat.scala 29:58] + node _T_3130 = cat(_T_3129, _T_3061) @[Cat.scala 29:58] + buf_rspage_set[0] <= _T_2857 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[1] <= _T_2948 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[2] <= _T_3039 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[3] <= _T_3130 @[lsu_bus_buffer.scala 421:18] + node _T_3131 = bits(buf_rspage_set[0], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3132 = bits(buf_rspage[0], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3133 = or(_T_3131, _T_3132) @[lsu_bus_buffer.scala 425:88] + node _T_3134 = bits(buf_rspage_set[0], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3135 = bits(buf_rspage[0], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3136 = or(_T_3134, _T_3135) @[lsu_bus_buffer.scala 425:88] + node _T_3137 = bits(buf_rspage_set[0], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3138 = bits(buf_rspage[0], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3139 = or(_T_3137, _T_3138) @[lsu_bus_buffer.scala 425:88] + node _T_3140 = bits(buf_rspage_set[0], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3141 = bits(buf_rspage[0], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3142 = or(_T_3140, _T_3141) @[lsu_bus_buffer.scala 425:88] + node _T_3143 = cat(_T_3142, _T_3139) @[Cat.scala 29:58] + node _T_3144 = cat(_T_3143, _T_3136) @[Cat.scala 29:58] + node _T_3145 = cat(_T_3144, _T_3133) @[Cat.scala 29:58] + node _T_3146 = bits(buf_rspage_set[1], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3147 = bits(buf_rspage[1], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3148 = or(_T_3146, _T_3147) @[lsu_bus_buffer.scala 425:88] + node _T_3149 = bits(buf_rspage_set[1], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3150 = bits(buf_rspage[1], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3151 = or(_T_3149, _T_3150) @[lsu_bus_buffer.scala 425:88] + node _T_3152 = bits(buf_rspage_set[1], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3153 = bits(buf_rspage[1], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3154 = or(_T_3152, _T_3153) @[lsu_bus_buffer.scala 425:88] + node _T_3155 = bits(buf_rspage_set[1], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3156 = bits(buf_rspage[1], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3157 = or(_T_3155, _T_3156) @[lsu_bus_buffer.scala 425:88] + node _T_3158 = cat(_T_3157, _T_3154) @[Cat.scala 29:58] + node _T_3159 = cat(_T_3158, _T_3151) @[Cat.scala 29:58] + node _T_3160 = cat(_T_3159, _T_3148) @[Cat.scala 29:58] + node _T_3161 = bits(buf_rspage_set[2], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3162 = bits(buf_rspage[2], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3163 = or(_T_3161, _T_3162) @[lsu_bus_buffer.scala 425:88] + node _T_3164 = bits(buf_rspage_set[2], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3165 = bits(buf_rspage[2], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3166 = or(_T_3164, _T_3165) @[lsu_bus_buffer.scala 425:88] + node _T_3167 = bits(buf_rspage_set[2], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3168 = bits(buf_rspage[2], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3169 = or(_T_3167, _T_3168) @[lsu_bus_buffer.scala 425:88] + node _T_3170 = bits(buf_rspage_set[2], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3171 = bits(buf_rspage[2], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3172 = or(_T_3170, _T_3171) @[lsu_bus_buffer.scala 425:88] + node _T_3173 = cat(_T_3172, _T_3169) @[Cat.scala 29:58] + node _T_3174 = cat(_T_3173, _T_3166) @[Cat.scala 29:58] + node _T_3175 = cat(_T_3174, _T_3163) @[Cat.scala 29:58] + node _T_3176 = bits(buf_rspage_set[3], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3177 = bits(buf_rspage[3], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3178 = or(_T_3176, _T_3177) @[lsu_bus_buffer.scala 425:88] + node _T_3179 = bits(buf_rspage_set[3], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3180 = bits(buf_rspage[3], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3181 = or(_T_3179, _T_3180) @[lsu_bus_buffer.scala 425:88] + node _T_3182 = bits(buf_rspage_set[3], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3183 = bits(buf_rspage[3], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3184 = or(_T_3182, _T_3183) @[lsu_bus_buffer.scala 425:88] + node _T_3185 = bits(buf_rspage_set[3], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3186 = bits(buf_rspage[3], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3187 = or(_T_3185, _T_3186) @[lsu_bus_buffer.scala 425:88] + node _T_3188 = cat(_T_3187, _T_3184) @[Cat.scala 29:58] + node _T_3189 = cat(_T_3188, _T_3181) @[Cat.scala 29:58] + node _T_3190 = cat(_T_3189, _T_3178) @[Cat.scala 29:58] + buf_rspage_in[0] <= _T_3145 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[1] <= _T_3160 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[2] <= _T_3175 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[3] <= _T_3190 @[lsu_bus_buffer.scala 425:17] + node _T_3191 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3192 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3193 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3194 = or(_T_3192, _T_3193) @[lsu_bus_buffer.scala 426:110] + node _T_3195 = eq(_T_3194, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3196 = and(_T_3191, _T_3195) @[lsu_bus_buffer.scala 426:82] + node _T_3197 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3198 = and(_T_3196, _T_3197) @[lsu_bus_buffer.scala 426:136] + node _T_3199 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3200 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3201 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3202 = or(_T_3200, _T_3201) @[lsu_bus_buffer.scala 426:110] + node _T_3203 = eq(_T_3202, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3204 = and(_T_3199, _T_3203) @[lsu_bus_buffer.scala 426:82] + node _T_3205 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3206 = and(_T_3204, _T_3205) @[lsu_bus_buffer.scala 426:136] + node _T_3207 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3208 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3209 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3210 = or(_T_3208, _T_3209) @[lsu_bus_buffer.scala 426:110] + node _T_3211 = eq(_T_3210, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3212 = and(_T_3207, _T_3211) @[lsu_bus_buffer.scala 426:82] + node _T_3213 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3214 = and(_T_3212, _T_3213) @[lsu_bus_buffer.scala 426:136] + node _T_3215 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3216 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3217 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3218 = or(_T_3216, _T_3217) @[lsu_bus_buffer.scala 426:110] + node _T_3219 = eq(_T_3218, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3220 = and(_T_3215, _T_3219) @[lsu_bus_buffer.scala 426:82] + node _T_3221 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3222 = and(_T_3220, _T_3221) @[lsu_bus_buffer.scala 426:136] + node _T_3223 = cat(_T_3222, _T_3214) @[Cat.scala 29:58] + node _T_3224 = cat(_T_3223, _T_3206) @[Cat.scala 29:58] + node _T_3225 = cat(_T_3224, _T_3198) @[Cat.scala 29:58] + node _T_3226 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3227 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3228 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3229 = or(_T_3227, _T_3228) @[lsu_bus_buffer.scala 426:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3231 = and(_T_3226, _T_3230) @[lsu_bus_buffer.scala 426:82] + node _T_3232 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3233 = and(_T_3231, _T_3232) @[lsu_bus_buffer.scala 426:136] + node _T_3234 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3235 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3236 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3237 = or(_T_3235, _T_3236) @[lsu_bus_buffer.scala 426:110] + node _T_3238 = eq(_T_3237, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3239 = and(_T_3234, _T_3238) @[lsu_bus_buffer.scala 426:82] + node _T_3240 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3241 = and(_T_3239, _T_3240) @[lsu_bus_buffer.scala 426:136] + node _T_3242 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3243 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3244 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3245 = or(_T_3243, _T_3244) @[lsu_bus_buffer.scala 426:110] + node _T_3246 = eq(_T_3245, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3247 = and(_T_3242, _T_3246) @[lsu_bus_buffer.scala 426:82] + node _T_3248 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3249 = and(_T_3247, _T_3248) @[lsu_bus_buffer.scala 426:136] + node _T_3250 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3251 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3252 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3253 = or(_T_3251, _T_3252) @[lsu_bus_buffer.scala 426:110] + node _T_3254 = eq(_T_3253, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3255 = and(_T_3250, _T_3254) @[lsu_bus_buffer.scala 426:82] + node _T_3256 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3257 = and(_T_3255, _T_3256) @[lsu_bus_buffer.scala 426:136] + node _T_3258 = cat(_T_3257, _T_3249) @[Cat.scala 29:58] + node _T_3259 = cat(_T_3258, _T_3241) @[Cat.scala 29:58] + node _T_3260 = cat(_T_3259, _T_3233) @[Cat.scala 29:58] + node _T_3261 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3262 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3263 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3264 = or(_T_3262, _T_3263) @[lsu_bus_buffer.scala 426:110] + node _T_3265 = eq(_T_3264, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3266 = and(_T_3261, _T_3265) @[lsu_bus_buffer.scala 426:82] + node _T_3267 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3268 = and(_T_3266, _T_3267) @[lsu_bus_buffer.scala 426:136] + node _T_3269 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3270 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3271 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3272 = or(_T_3270, _T_3271) @[lsu_bus_buffer.scala 426:110] + node _T_3273 = eq(_T_3272, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3274 = and(_T_3269, _T_3273) @[lsu_bus_buffer.scala 426:82] + node _T_3275 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3276 = and(_T_3274, _T_3275) @[lsu_bus_buffer.scala 426:136] + node _T_3277 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3278 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3279 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3280 = or(_T_3278, _T_3279) @[lsu_bus_buffer.scala 426:110] + node _T_3281 = eq(_T_3280, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3282 = and(_T_3277, _T_3281) @[lsu_bus_buffer.scala 426:82] + node _T_3283 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3284 = and(_T_3282, _T_3283) @[lsu_bus_buffer.scala 426:136] + node _T_3285 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3286 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3287 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3288 = or(_T_3286, _T_3287) @[lsu_bus_buffer.scala 426:110] + node _T_3289 = eq(_T_3288, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3290 = and(_T_3285, _T_3289) @[lsu_bus_buffer.scala 426:82] + node _T_3291 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3292 = and(_T_3290, _T_3291) @[lsu_bus_buffer.scala 426:136] + node _T_3293 = cat(_T_3292, _T_3284) @[Cat.scala 29:58] + node _T_3294 = cat(_T_3293, _T_3276) @[Cat.scala 29:58] + node _T_3295 = cat(_T_3294, _T_3268) @[Cat.scala 29:58] + node _T_3296 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3297 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3298 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3299 = or(_T_3297, _T_3298) @[lsu_bus_buffer.scala 426:110] + node _T_3300 = eq(_T_3299, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3301 = and(_T_3296, _T_3300) @[lsu_bus_buffer.scala 426:82] + node _T_3302 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3303 = and(_T_3301, _T_3302) @[lsu_bus_buffer.scala 426:136] + node _T_3304 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3305 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3306 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3307 = or(_T_3305, _T_3306) @[lsu_bus_buffer.scala 426:110] + node _T_3308 = eq(_T_3307, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3309 = and(_T_3304, _T_3308) @[lsu_bus_buffer.scala 426:82] + node _T_3310 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3311 = and(_T_3309, _T_3310) @[lsu_bus_buffer.scala 426:136] + node _T_3312 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3313 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3314 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3315 = or(_T_3313, _T_3314) @[lsu_bus_buffer.scala 426:110] + node _T_3316 = eq(_T_3315, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3317 = and(_T_3312, _T_3316) @[lsu_bus_buffer.scala 426:82] + node _T_3318 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3319 = and(_T_3317, _T_3318) @[lsu_bus_buffer.scala 426:136] + node _T_3320 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3321 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3322 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3323 = or(_T_3321, _T_3322) @[lsu_bus_buffer.scala 426:110] + node _T_3324 = eq(_T_3323, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3325 = and(_T_3320, _T_3324) @[lsu_bus_buffer.scala 426:82] + node _T_3326 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3327 = and(_T_3325, _T_3326) @[lsu_bus_buffer.scala 426:136] + node _T_3328 = cat(_T_3327, _T_3319) @[Cat.scala 29:58] + node _T_3329 = cat(_T_3328, _T_3311) @[Cat.scala 29:58] + node _T_3330 = cat(_T_3329, _T_3303) @[Cat.scala 29:58] + buf_rspage[0] <= _T_3225 @[lsu_bus_buffer.scala 426:14] + buf_rspage[1] <= _T_3260 @[lsu_bus_buffer.scala 426:14] + buf_rspage[2] <= _T_3295 @[lsu_bus_buffer.scala 426:14] + buf_rspage[3] <= _T_3330 @[lsu_bus_buffer.scala 426:14] + node _T_3331 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 427:75] + node _T_3332 = and(ibuf_drain_vld, _T_3331) @[lsu_bus_buffer.scala 427:63] + node _T_3333 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 427:75] + node _T_3334 = and(ibuf_drain_vld, _T_3333) @[lsu_bus_buffer.scala 427:63] + node _T_3335 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 427:75] + node _T_3336 = and(ibuf_drain_vld, _T_3335) @[lsu_bus_buffer.scala 427:63] + node _T_3337 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 427:75] + node _T_3338 = and(ibuf_drain_vld, _T_3337) @[lsu_bus_buffer.scala 427:63] + node _T_3339 = cat(_T_3338, _T_3336) @[Cat.scala 29:58] + node _T_3340 = cat(_T_3339, _T_3334) @[Cat.scala 29:58] + node _T_3341 = cat(_T_3340, _T_3332) @[Cat.scala 29:58] + ibuf_drainvec_vld <= _T_3341 @[lsu_bus_buffer.scala 427:21] + node _T_3342 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 428:64] + node _T_3343 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3344 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3345 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 429:46] + node _T_3346 = and(_T_3344, _T_3345) @[lsu_bus_buffer.scala 429:35] + node _T_3347 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3348 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3349 = mux(_T_3346, _T_3347, _T_3348) @[lsu_bus_buffer.scala 429:8] + node _T_3350 = mux(_T_3342, _T_3343, _T_3349) @[lsu_bus_buffer.scala 428:46] + node _T_3351 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 428:64] + node _T_3352 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3353 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3354 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 429:46] + node _T_3355 = and(_T_3353, _T_3354) @[lsu_bus_buffer.scala 429:35] + node _T_3356 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3357 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3358 = mux(_T_3355, _T_3356, _T_3357) @[lsu_bus_buffer.scala 429:8] + node _T_3359 = mux(_T_3351, _T_3352, _T_3358) @[lsu_bus_buffer.scala 428:46] + node _T_3360 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 428:64] + node _T_3361 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3362 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3363 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 429:46] + node _T_3364 = and(_T_3362, _T_3363) @[lsu_bus_buffer.scala 429:35] + node _T_3365 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3366 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3367 = mux(_T_3364, _T_3365, _T_3366) @[lsu_bus_buffer.scala 429:8] + node _T_3368 = mux(_T_3360, _T_3361, _T_3367) @[lsu_bus_buffer.scala 428:46] + node _T_3369 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 428:64] + node _T_3370 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3371 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3372 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 429:46] + node _T_3373 = and(_T_3371, _T_3372) @[lsu_bus_buffer.scala 429:35] + node _T_3374 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3375 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3376 = mux(_T_3373, _T_3374, _T_3375) @[lsu_bus_buffer.scala 429:8] + node _T_3377 = mux(_T_3369, _T_3370, _T_3376) @[lsu_bus_buffer.scala 428:46] + buf_byteen_in[0] <= _T_3350 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[1] <= _T_3359 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[2] <= _T_3368 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[3] <= _T_3377 @[lsu_bus_buffer.scala 428:17] + node _T_3378 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 430:62] + node _T_3379 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3380 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 430:119] + node _T_3381 = and(_T_3379, _T_3380) @[lsu_bus_buffer.scala 430:108] + node _T_3382 = mux(_T_3381, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3383 = mux(_T_3378, ibuf_addr, _T_3382) @[lsu_bus_buffer.scala 430:44] + node _T_3384 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 430:62] + node _T_3385 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3386 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 430:119] + node _T_3387 = and(_T_3385, _T_3386) @[lsu_bus_buffer.scala 430:108] + node _T_3388 = mux(_T_3387, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3389 = mux(_T_3384, ibuf_addr, _T_3388) @[lsu_bus_buffer.scala 430:44] + node _T_3390 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 430:62] + node _T_3391 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3392 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 430:119] + node _T_3393 = and(_T_3391, _T_3392) @[lsu_bus_buffer.scala 430:108] + node _T_3394 = mux(_T_3393, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3395 = mux(_T_3390, ibuf_addr, _T_3394) @[lsu_bus_buffer.scala 430:44] + node _T_3396 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 430:62] + node _T_3397 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3398 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 430:119] + node _T_3399 = and(_T_3397, _T_3398) @[lsu_bus_buffer.scala 430:108] + node _T_3400 = mux(_T_3399, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3401 = mux(_T_3396, ibuf_addr, _T_3400) @[lsu_bus_buffer.scala 430:44] + buf_addr_in[0] <= _T_3383 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[1] <= _T_3389 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[2] <= _T_3395 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[3] <= _T_3401 @[lsu_bus_buffer.scala 430:15] + node _T_3402 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 431:63] + node _T_3403 = mux(_T_3402, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3404 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 431:63] + node _T_3405 = mux(_T_3404, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3406 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 431:63] + node _T_3407 = mux(_T_3406, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3408 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 431:63] + node _T_3409 = mux(_T_3408, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3410 = cat(_T_3409, _T_3407) @[Cat.scala 29:58] + node _T_3411 = cat(_T_3410, _T_3405) @[Cat.scala 29:58] + node _T_3412 = cat(_T_3411, _T_3403) @[Cat.scala 29:58] + buf_dual_in <= _T_3412 @[lsu_bus_buffer.scala 431:15] + node _T_3413 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 432:65] + node _T_3414 = mux(_T_3413, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3415 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 432:65] + node _T_3416 = mux(_T_3415, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3417 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 432:65] + node _T_3418 = mux(_T_3417, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3419 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 432:65] + node _T_3420 = mux(_T_3419, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3421 = cat(_T_3420, _T_3418) @[Cat.scala 29:58] + node _T_3422 = cat(_T_3421, _T_3416) @[Cat.scala 29:58] + node _T_3423 = cat(_T_3422, _T_3414) @[Cat.scala 29:58] + buf_samedw_in <= _T_3423 @[lsu_bus_buffer.scala 432:17] + node _T_3424 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 433:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3427 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 433:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3430 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 433:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3433 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 433:66] + node _T_3434 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3435 = mux(_T_3433, _T_3434, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3436 = cat(_T_3435, _T_3432) @[Cat.scala 29:58] + node _T_3437 = cat(_T_3436, _T_3429) @[Cat.scala 29:58] + node _T_3438 = cat(_T_3437, _T_3426) @[Cat.scala 29:58] + buf_nomerge_in <= _T_3438 @[lsu_bus_buffer.scala 433:18] + node _T_3439 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 434:65] + node _T_3440 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3441 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 434:118] + node _T_3442 = and(_T_3440, _T_3441) @[lsu_bus_buffer.scala 434:107] + node _T_3443 = mux(_T_3439, ibuf_dual, _T_3442) @[lsu_bus_buffer.scala 434:47] + node _T_3444 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 434:65] + node _T_3445 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3446 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 434:118] + node _T_3447 = and(_T_3445, _T_3446) @[lsu_bus_buffer.scala 434:107] + node _T_3448 = mux(_T_3444, ibuf_dual, _T_3447) @[lsu_bus_buffer.scala 434:47] + node _T_3449 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 434:65] + node _T_3450 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3451 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 434:118] + node _T_3452 = and(_T_3450, _T_3451) @[lsu_bus_buffer.scala 434:107] + node _T_3453 = mux(_T_3449, ibuf_dual, _T_3452) @[lsu_bus_buffer.scala 434:47] + node _T_3454 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 434:65] + node _T_3455 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3456 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 434:118] + node _T_3457 = and(_T_3455, _T_3456) @[lsu_bus_buffer.scala 434:107] + node _T_3458 = mux(_T_3454, ibuf_dual, _T_3457) @[lsu_bus_buffer.scala 434:47] + node _T_3459 = cat(_T_3458, _T_3453) @[Cat.scala 29:58] + node _T_3460 = cat(_T_3459, _T_3448) @[Cat.scala 29:58] + node _T_3461 = cat(_T_3460, _T_3443) @[Cat.scala 29:58] + buf_dualhi_in <= _T_3461 @[lsu_bus_buffer.scala 434:17] + node _T_3462 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 435:65] + node _T_3463 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3464 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 435:125] + node _T_3465 = and(_T_3463, _T_3464) @[lsu_bus_buffer.scala 435:114] + node _T_3466 = mux(_T_3465, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3467 = mux(_T_3462, ibuf_dualtag, _T_3466) @[lsu_bus_buffer.scala 435:47] + node _T_3468 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 435:65] + node _T_3469 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3470 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 435:125] + node _T_3471 = and(_T_3469, _T_3470) @[lsu_bus_buffer.scala 435:114] + node _T_3472 = mux(_T_3471, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3473 = mux(_T_3468, ibuf_dualtag, _T_3472) @[lsu_bus_buffer.scala 435:47] + node _T_3474 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 435:65] + node _T_3475 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3476 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 435:125] + node _T_3477 = and(_T_3475, _T_3476) @[lsu_bus_buffer.scala 435:114] + node _T_3478 = mux(_T_3477, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3479 = mux(_T_3474, ibuf_dualtag, _T_3478) @[lsu_bus_buffer.scala 435:47] + node _T_3480 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 435:65] + node _T_3481 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3482 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 435:125] + node _T_3483 = and(_T_3481, _T_3482) @[lsu_bus_buffer.scala 435:114] + node _T_3484 = mux(_T_3483, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3485 = mux(_T_3480, ibuf_dualtag, _T_3484) @[lsu_bus_buffer.scala 435:47] + buf_dualtag_in[0] <= _T_3467 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[1] <= _T_3473 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[2] <= _T_3479 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[3] <= _T_3485 @[lsu_bus_buffer.scala 435:18] + node _T_3486 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 436:69] + node _T_3487 = mux(_T_3486, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3488 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 436:69] + node _T_3489 = mux(_T_3488, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3490 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 436:69] + node _T_3491 = mux(_T_3490, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3492 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 436:69] + node _T_3493 = mux(_T_3492, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3494 = cat(_T_3493, _T_3491) @[Cat.scala 29:58] + node _T_3495 = cat(_T_3494, _T_3489) @[Cat.scala 29:58] + node _T_3496 = cat(_T_3495, _T_3487) @[Cat.scala 29:58] + buf_sideeffect_in <= _T_3496 @[lsu_bus_buffer.scala 436:21] + node _T_3497 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 437:65] + node _T_3498 = mux(_T_3497, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3499 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 437:65] + node _T_3500 = mux(_T_3499, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3501 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 437:65] + node _T_3502 = mux(_T_3501, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3503 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 437:65] + node _T_3504 = mux(_T_3503, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3505 = cat(_T_3504, _T_3502) @[Cat.scala 29:58] + node _T_3506 = cat(_T_3505, _T_3500) @[Cat.scala 29:58] + node _T_3507 = cat(_T_3506, _T_3498) @[Cat.scala 29:58] + buf_unsign_in <= _T_3507 @[lsu_bus_buffer.scala 437:17] + node _T_3508 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 438:60] + node _T_3509 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[lsu_bus_buffer.scala 438:42] + node _T_3511 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 438:60] + node _T_3512 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[lsu_bus_buffer.scala 438:42] + node _T_3514 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 438:60] + node _T_3515 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[lsu_bus_buffer.scala 438:42] + node _T_3517 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 438:60] + node _T_3518 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3519 = mux(_T_3517, ibuf_sz, _T_3518) @[lsu_bus_buffer.scala 438:42] + buf_sz_in[0] <= _T_3510 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[1] <= _T_3513 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[2] <= _T_3516 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[3] <= _T_3519 @[lsu_bus_buffer.scala 438:13] + node _T_3520 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 439:64] + node _T_3521 = mux(_T_3520, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3522 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 439:64] + node _T_3523 = mux(_T_3522, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3524 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 439:64] + node _T_3525 = mux(_T_3524, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3526 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 439:64] + node _T_3527 = mux(_T_3526, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3528 = cat(_T_3527, _T_3525) @[Cat.scala 29:58] + node _T_3529 = cat(_T_3528, _T_3523) @[Cat.scala 29:58] + node _T_3530 = cat(_T_3529, _T_3521) @[Cat.scala 29:58] + buf_write_in <= _T_3530 @[lsu_bus_buffer.scala 439:16] + node _T_3531 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3531 : @[Conditional.scala 40:58] + node _T_3532 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3533 = mux(_T_3532, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[0] <= _T_3533 @[lsu_bus_buffer.scala 444:25] + node _T_3534 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3535 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3536 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3537 = and(_T_3535, _T_3536) @[lsu_bus_buffer.scala 445:95] + node _T_3538 = eq(UInt<1>("h00"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3539 = and(_T_3537, _T_3538) @[lsu_bus_buffer.scala 445:112] + node _T_3540 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3541 = eq(UInt<1>("h00"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3542 = and(_T_3540, _T_3541) @[lsu_bus_buffer.scala 445:161] + node _T_3543 = or(_T_3539, _T_3542) @[lsu_bus_buffer.scala 445:132] + node _T_3544 = and(_T_3534, _T_3543) @[lsu_bus_buffer.scala 445:63] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[lsu_bus_buffer.scala 445:201] + node _T_3547 = or(_T_3544, _T_3546) @[lsu_bus_buffer.scala 445:183] + buf_state_en[0] <= _T_3547 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 446:22] + buf_data_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 447:24] + node _T_3548 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3549 = and(ibuf_drain_vld, _T_3548) @[lsu_bus_buffer.scala 448:47] + node _T_3550 = bits(_T_3549, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3551 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3552 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3553 = mux(_T_3550, _T_3551, _T_3552) @[lsu_bus_buffer.scala 448:30] + buf_data_in[0] <= _T_3553 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3554 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3554 : @[Conditional.scala 39:67] + node _T_3555 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3556 = mux(_T_3555, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[0] <= _T_3556 @[lsu_bus_buffer.scala 453:25] + node _T_3557 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[0] <= _T_3557 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3558 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3558 : @[Conditional.scala 39:67] + node _T_3559 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3560 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3561 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3562 = and(_T_3560, _T_3561) @[lsu_bus_buffer.scala 459:104] + node _T_3563 = mux(_T_3562, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3564 = mux(_T_3559, UInt<3>("h00"), _T_3563) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[0] <= _T_3564 @[lsu_bus_buffer.scala 459:25] + node _T_3565 = eq(obuf_tag0, UInt<3>("h00")) @[lsu_bus_buffer.scala 460:48] + node _T_3566 = eq(obuf_tag1, UInt<3>("h00")) @[lsu_bus_buffer.scala 460:104] + node _T_3567 = and(obuf_merge, _T_3566) @[lsu_bus_buffer.scala 460:91] + node _T_3568 = or(_T_3565, _T_3567) @[lsu_bus_buffer.scala 460:77] + node _T_3569 = and(_T_3568, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3570 = and(_T_3569, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[0] <= _T_3570 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[lsu_bus_buffer.scala 461:29] + node _T_3571 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3572 = or(_T_3571, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[0] <= _T_3572 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3573 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 464:56] + node _T_3574 = eq(_T_3573, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3575 = and(buf_state_en[0], _T_3574) @[lsu_bus_buffer.scala 464:44] + node _T_3576 = and(_T_3575, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3577 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3578 = and(_T_3576, _T_3577) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[0] <= _T_3578 @[lsu_bus_buffer.scala 464:25] + node _T_3579 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[0] <= _T_3579 @[lsu_bus_buffer.scala 465:28] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3581 = and(_T_3580, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3582 = and(_T_3581, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[0] <= _T_3582 @[lsu_bus_buffer.scala 466:24] + node _T_3583 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3584 = and(_T_3583, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3585 = and(_T_3584, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[0] <= _T_3585 @[lsu_bus_buffer.scala 467:25] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3587 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3588 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3589 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3590 = mux(_T_3587, _T_3588, _T_3589) @[lsu_bus_buffer.scala 468:73] + node _T_3591 = mux(buf_error_en[0], _T_3586, _T_3590) @[lsu_bus_buffer.scala 468:30] + buf_data_in[0] <= _T_3591 @[lsu_bus_buffer.scala 468:24] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3592 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3592 : @[Conditional.scala 39:67] + node _T_3593 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 472:69] + node _T_3594 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3595 = and(_T_3593, _T_3594) @[lsu_bus_buffer.scala 472:73] + node _T_3596 = or(io.dec_tlu_force_halt, _T_3595) @[lsu_bus_buffer.scala 472:57] + node _T_3597 = bits(_T_3596, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3598 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3599 = and(buf_dual[0], _T_3598) @[lsu_bus_buffer.scala 473:28] + node _T_3600 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 473:57] + node _T_3601 = eq(_T_3600, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3602 = and(_T_3599, _T_3601) @[lsu_bus_buffer.scala 473:45] + node _T_3603 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3604 = and(_T_3602, _T_3603) @[lsu_bus_buffer.scala 473:61] + node _T_3605 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 474:27] + node _T_3606 = or(_T_3605, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3607 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3608 = and(buf_dual[0], _T_3607) @[lsu_bus_buffer.scala 474:68] + node _T_3609 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 474:97] + node _T_3610 = eq(_T_3609, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3611 = and(_T_3608, _T_3610) @[lsu_bus_buffer.scala 474:85] + node _T_3612 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3613 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3614 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3615 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3616 = eq(buf_dualtag[0], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3617 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_3618 = eq(buf_dualtag[0], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_3619 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_3620 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3621 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3622 = mux(_T_3616, _T_3617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3623 = mux(_T_3618, _T_3619, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3624 = or(_T_3620, _T_3621) @[Mux.scala 27:72] + node _T_3625 = or(_T_3624, _T_3622) @[Mux.scala 27:72] + node _T_3626 = or(_T_3625, _T_3623) @[Mux.scala 27:72] + wire _T_3627 : UInt<1> @[Mux.scala 27:72] + _T_3627 <= _T_3626 @[Mux.scala 27:72] + node _T_3628 = and(_T_3611, _T_3627) @[lsu_bus_buffer.scala 474:101] + node _T_3629 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_3630 = and(_T_3628, _T_3629) @[lsu_bus_buffer.scala 474:138] + node _T_3631 = and(_T_3630, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_3632 = or(_T_3606, _T_3631) @[lsu_bus_buffer.scala 474:53] + node _T_3633 = mux(_T_3632, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_3634 = mux(_T_3604, UInt<3>("h04"), _T_3633) @[lsu_bus_buffer.scala 473:14] + node _T_3635 = mux(_T_3597, UInt<3>("h00"), _T_3634) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[0] <= _T_3635 @[lsu_bus_buffer.scala 472:27] + node _T_3636 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 475:73] + node _T_3637 = and(bus_rsp_write, _T_3636) @[lsu_bus_buffer.scala 475:52] + node _T_3638 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 476:46] + node _T_3639 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 477:23] + node _T_3640 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 477:47] + node _T_3641 = and(_T_3639, _T_3640) @[lsu_bus_buffer.scala 477:27] + node _T_3642 = or(_T_3638, _T_3641) @[lsu_bus_buffer.scala 476:77] + node _T_3643 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 478:26] + node _T_3644 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 478:54] + node _T_3645 = not(_T_3644) @[lsu_bus_buffer.scala 478:44] + node _T_3646 = and(_T_3643, _T_3645) @[lsu_bus_buffer.scala 478:42] + node _T_3647 = and(_T_3646, buf_samedw[0]) @[lsu_bus_buffer.scala 478:58] + node _T_3648 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 478:94] + node _T_3649 = and(_T_3647, _T_3648) @[lsu_bus_buffer.scala 478:74] + node _T_3650 = or(_T_3642, _T_3649) @[lsu_bus_buffer.scala 477:71] + node _T_3651 = and(bus_rsp_read, _T_3650) @[lsu_bus_buffer.scala 476:25] + node _T_3652 = or(_T_3637, _T_3651) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[0] <= _T_3652 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[lsu_bus_buffer.scala 479:29] + node _T_3653 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_3654 = or(_T_3653, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[0] <= _T_3654 @[lsu_bus_buffer.scala 480:25] + node _T_3655 = and(buf_state_bus_en[0], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_3656 = and(_T_3655, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[0] <= _T_3656 @[lsu_bus_buffer.scala 481:24] + node _T_3657 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_3658 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 482:111] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[lsu_bus_buffer.scala 482:91] + node _T_3660 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 483:42] + node _T_3661 = and(bus_rsp_read_error, _T_3660) @[lsu_bus_buffer.scala 483:31] + node _T_3662 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 483:66] + node _T_3663 = and(_T_3661, _T_3662) @[lsu_bus_buffer.scala 483:46] + node _T_3664 = or(_T_3659, _T_3663) @[lsu_bus_buffer.scala 482:143] + node _T_3665 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 484:54] + node _T_3666 = and(bus_rsp_write_error, _T_3665) @[lsu_bus_buffer.scala 484:33] + node _T_3667 = or(_T_3664, _T_3666) @[lsu_bus_buffer.scala 483:88] + node _T_3668 = and(_T_3657, _T_3667) @[lsu_bus_buffer.scala 482:68] + buf_error_en[0] <= _T_3668 @[lsu_bus_buffer.scala 482:25] + node _T_3669 = eq(buf_error_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_3670 = and(buf_state_en[0], _T_3669) @[lsu_bus_buffer.scala 485:48] + node _T_3671 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_3672 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_3673 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_3674 = mux(_T_3671, _T_3672, _T_3673) @[lsu_bus_buffer.scala 485:72] + node _T_3675 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_3676 = mux(_T_3670, _T_3674, _T_3675) @[lsu_bus_buffer.scala 485:30] + buf_data_in[0] <= _T_3676 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3677 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3677 : @[Conditional.scala 39:67] + node _T_3678 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_3679 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 490:86] + node _T_3680 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 490:101] + node _T_3681 = bits(_T_3680, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_3682 = or(_T_3679, _T_3681) @[lsu_bus_buffer.scala 490:90] + node _T_3683 = or(_T_3682, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_3684 = mux(_T_3683, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_3685 = mux(_T_3678, UInt<3>("h00"), _T_3684) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[0] <= _T_3685 @[lsu_bus_buffer.scala 490:25] + node _T_3686 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 491:66] + node _T_3687 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 492:21] + node _T_3688 = bits(_T_3687, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_3689 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[lsu_bus_buffer.scala 492:58] + node _T_3690 = and(_T_3688, _T_3689) @[lsu_bus_buffer.scala 492:38] + node _T_3691 = or(_T_3686, _T_3690) @[lsu_bus_buffer.scala 491:95] + node _T_3692 = and(bus_rsp_read, _T_3691) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[0] <= _T_3692 @[lsu_bus_buffer.scala 491:29] + node _T_3693 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_3694 = or(_T_3693, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[0] <= _T_3694 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3695 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3695 : @[Conditional.scala 39:67] + node _T_3696 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_3697 = mux(_T_3696, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[0] <= _T_3697 @[lsu_bus_buffer.scala 498:25] + node _T_3698 = eq(RspPtr, UInt<2>("h00")) @[lsu_bus_buffer.scala 499:37] + node _T_3699 = eq(buf_dualtag[0], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_3700 = and(buf_dual[0], _T_3699) @[lsu_bus_buffer.scala 499:80] + node _T_3701 = or(_T_3698, _T_3700) @[lsu_bus_buffer.scala 499:65] + node _T_3702 = or(_T_3701, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[0] <= _T_3702 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3703 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3703 : @[Conditional.scala 39:67] + buf_nxtstate[0] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_3704 = bits(buf_state_en[0], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3704 : @[Reg.scala 28:19] + _T_3705 <= buf_nxtstate[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[0] <= _T_3705 @[lsu_bus_buffer.scala 512:18] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_3706 <= buf_age_in_0 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[0] <= _T_3706 @[lsu_bus_buffer.scala 513:17] + reg _T_3707 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_3707 <= buf_rspage_in[0] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[0] <= _T_3707 @[lsu_bus_buffer.scala 514:20] + node _T_3708 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_3709 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3708 : @[Reg.scala 28:19] + _T_3709 <= buf_dualtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[0] <= _T_3709 @[lsu_bus_buffer.scala 515:20] + node _T_3710 = bits(buf_dual_in, 0, 0) @[lsu_bus_buffer.scala 516:74] + node _T_3711 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_3712 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3711 : @[Reg.scala 28:19] + _T_3712 <= _T_3710 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[0] <= _T_3712 @[lsu_bus_buffer.scala 516:17] + node _T_3713 = bits(buf_samedw_in, 0, 0) @[lsu_bus_buffer.scala 517:78] + node _T_3714 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_3715 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3714 : @[Reg.scala 28:19] + _T_3715 <= _T_3713 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[0] <= _T_3715 @[lsu_bus_buffer.scala 517:19] + node _T_3716 = bits(buf_nomerge_in, 0, 0) @[lsu_bus_buffer.scala 518:80] + node _T_3717 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_3718 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3717 : @[Reg.scala 28:19] + _T_3718 <= _T_3716 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[0] <= _T_3718 @[lsu_bus_buffer.scala 518:20] + node _T_3719 = bits(buf_dualhi_in, 0, 0) @[lsu_bus_buffer.scala 519:78] + node _T_3720 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_3721 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3720 : @[Reg.scala 28:19] + _T_3721 <= _T_3719 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[0] <= _T_3721 @[lsu_bus_buffer.scala 519:19] + node _T_3722 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3722 : @[Conditional.scala 40:58] + node _T_3723 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3724 = mux(_T_3723, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[1] <= _T_3724 @[lsu_bus_buffer.scala 444:25] + node _T_3725 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3726 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3727 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3728 = and(_T_3726, _T_3727) @[lsu_bus_buffer.scala 445:95] + node _T_3729 = eq(UInt<1>("h01"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3730 = and(_T_3728, _T_3729) @[lsu_bus_buffer.scala 445:112] + node _T_3731 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3732 = eq(UInt<1>("h01"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3733 = and(_T_3731, _T_3732) @[lsu_bus_buffer.scala 445:161] + node _T_3734 = or(_T_3730, _T_3733) @[lsu_bus_buffer.scala 445:132] + node _T_3735 = and(_T_3725, _T_3734) @[lsu_bus_buffer.scala 445:63] + node _T_3736 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3737 = and(ibuf_drain_vld, _T_3736) @[lsu_bus_buffer.scala 445:201] + node _T_3738 = or(_T_3735, _T_3737) @[lsu_bus_buffer.scala 445:183] + buf_state_en[1] <= _T_3738 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 446:22] + buf_data_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 447:24] + node _T_3739 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3740 = and(ibuf_drain_vld, _T_3739) @[lsu_bus_buffer.scala 448:47] + node _T_3741 = bits(_T_3740, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3742 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3743 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3744 = mux(_T_3741, _T_3742, _T_3743) @[lsu_bus_buffer.scala 448:30] + buf_data_in[1] <= _T_3744 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3745 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3745 : @[Conditional.scala 39:67] + node _T_3746 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3747 = mux(_T_3746, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[1] <= _T_3747 @[lsu_bus_buffer.scala 453:25] + node _T_3748 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[1] <= _T_3748 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3749 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3749 : @[Conditional.scala 39:67] + node _T_3750 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3751 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3752 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3753 = and(_T_3751, _T_3752) @[lsu_bus_buffer.scala 459:104] + node _T_3754 = mux(_T_3753, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3755 = mux(_T_3750, UInt<3>("h00"), _T_3754) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[1] <= _T_3755 @[lsu_bus_buffer.scala 459:25] + node _T_3756 = eq(obuf_tag0, UInt<3>("h01")) @[lsu_bus_buffer.scala 460:48] + node _T_3757 = eq(obuf_tag1, UInt<3>("h01")) @[lsu_bus_buffer.scala 460:104] + node _T_3758 = and(obuf_merge, _T_3757) @[lsu_bus_buffer.scala 460:91] + node _T_3759 = or(_T_3756, _T_3758) @[lsu_bus_buffer.scala 460:77] + node _T_3760 = and(_T_3759, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3761 = and(_T_3760, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[1] <= _T_3761 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[lsu_bus_buffer.scala 461:29] + node _T_3762 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3763 = or(_T_3762, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[1] <= _T_3763 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3764 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 464:56] + node _T_3765 = eq(_T_3764, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3766 = and(buf_state_en[1], _T_3765) @[lsu_bus_buffer.scala 464:44] + node _T_3767 = and(_T_3766, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3768 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3769 = and(_T_3767, _T_3768) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[1] <= _T_3769 @[lsu_bus_buffer.scala 464:25] + node _T_3770 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[1] <= _T_3770 @[lsu_bus_buffer.scala 465:28] + node _T_3771 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3772 = and(_T_3771, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3773 = and(_T_3772, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[1] <= _T_3773 @[lsu_bus_buffer.scala 466:24] + node _T_3774 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3775 = and(_T_3774, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3776 = and(_T_3775, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[1] <= _T_3776 @[lsu_bus_buffer.scala 467:25] + node _T_3777 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3778 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3779 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3780 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3781 = mux(_T_3778, _T_3779, _T_3780) @[lsu_bus_buffer.scala 468:73] + node _T_3782 = mux(buf_error_en[1], _T_3777, _T_3781) @[lsu_bus_buffer.scala 468:30] + buf_data_in[1] <= _T_3782 @[lsu_bus_buffer.scala 468:24] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3783 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3783 : @[Conditional.scala 39:67] + node _T_3784 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 472:69] + node _T_3785 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3786 = and(_T_3784, _T_3785) @[lsu_bus_buffer.scala 472:73] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[lsu_bus_buffer.scala 472:57] + node _T_3788 = bits(_T_3787, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[lsu_bus_buffer.scala 473:28] + node _T_3791 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 473:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3793 = and(_T_3790, _T_3792) @[lsu_bus_buffer.scala 473:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3795 = and(_T_3793, _T_3794) @[lsu_bus_buffer.scala 473:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 474:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[lsu_bus_buffer.scala 474:68] + node _T_3800 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 474:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3802 = and(_T_3799, _T_3801) @[lsu_bus_buffer.scala 474:85] + node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3804 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3806 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3808 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_3810 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3814 = mux(_T_3809, _T_3810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3815 = or(_T_3811, _T_3812) @[Mux.scala 27:72] + node _T_3816 = or(_T_3815, _T_3813) @[Mux.scala 27:72] + node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] + wire _T_3818 : UInt<1> @[Mux.scala 27:72] + _T_3818 <= _T_3817 @[Mux.scala 27:72] + node _T_3819 = and(_T_3802, _T_3818) @[lsu_bus_buffer.scala 474:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_3821 = and(_T_3819, _T_3820) @[lsu_bus_buffer.scala 474:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_3823 = or(_T_3797, _T_3822) @[lsu_bus_buffer.scala 474:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[lsu_bus_buffer.scala 473:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[1] <= _T_3826 @[lsu_bus_buffer.scala 472:27] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 475:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[lsu_bus_buffer.scala 475:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 476:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 477:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 477:47] + node _T_3832 = and(_T_3830, _T_3831) @[lsu_bus_buffer.scala 477:27] + node _T_3833 = or(_T_3829, _T_3832) @[lsu_bus_buffer.scala 476:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 478:26] + node _T_3835 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 478:54] + node _T_3836 = not(_T_3835) @[lsu_bus_buffer.scala 478:44] + node _T_3837 = and(_T_3834, _T_3836) @[lsu_bus_buffer.scala 478:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[lsu_bus_buffer.scala 478:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 478:94] + node _T_3840 = and(_T_3838, _T_3839) @[lsu_bus_buffer.scala 478:74] + node _T_3841 = or(_T_3833, _T_3840) @[lsu_bus_buffer.scala 477:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[lsu_bus_buffer.scala 476:25] + node _T_3843 = or(_T_3828, _T_3842) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[1] <= _T_3843 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[lsu_bus_buffer.scala 479:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[1] <= _T_3845 @[lsu_bus_buffer.scala 480:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[1] <= _T_3847 @[lsu_bus_buffer.scala 481:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 482:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[lsu_bus_buffer.scala 482:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 483:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[lsu_bus_buffer.scala 483:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 483:66] + node _T_3854 = and(_T_3852, _T_3853) @[lsu_bus_buffer.scala 483:46] + node _T_3855 = or(_T_3850, _T_3854) @[lsu_bus_buffer.scala 482:143] + node _T_3856 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 484:54] + node _T_3857 = and(bus_rsp_write_error, _T_3856) @[lsu_bus_buffer.scala 484:33] + node _T_3858 = or(_T_3855, _T_3857) @[lsu_bus_buffer.scala 483:88] + node _T_3859 = and(_T_3848, _T_3858) @[lsu_bus_buffer.scala 482:68] + buf_error_en[1] <= _T_3859 @[lsu_bus_buffer.scala 482:25] + node _T_3860 = eq(buf_error_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_3861 = and(buf_state_en[1], _T_3860) @[lsu_bus_buffer.scala 485:48] + node _T_3862 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_3863 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_3864 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_3865 = mux(_T_3862, _T_3863, _T_3864) @[lsu_bus_buffer.scala 485:72] + node _T_3866 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_3867 = mux(_T_3861, _T_3865, _T_3866) @[lsu_bus_buffer.scala 485:30] + buf_data_in[1] <= _T_3867 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3868 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3868 : @[Conditional.scala 39:67] + node _T_3869 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_3870 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 490:86] + node _T_3871 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 490:101] + node _T_3872 = bits(_T_3871, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_3873 = or(_T_3870, _T_3872) @[lsu_bus_buffer.scala 490:90] + node _T_3874 = or(_T_3873, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_3875 = mux(_T_3874, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_3876 = mux(_T_3869, UInt<3>("h00"), _T_3875) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[1] <= _T_3876 @[lsu_bus_buffer.scala 490:25] + node _T_3877 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 491:66] + node _T_3878 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 492:21] + node _T_3879 = bits(_T_3878, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_3880 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[lsu_bus_buffer.scala 492:58] + node _T_3881 = and(_T_3879, _T_3880) @[lsu_bus_buffer.scala 492:38] + node _T_3882 = or(_T_3877, _T_3881) @[lsu_bus_buffer.scala 491:95] + node _T_3883 = and(bus_rsp_read, _T_3882) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[1] <= _T_3883 @[lsu_bus_buffer.scala 491:29] + node _T_3884 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_3885 = or(_T_3884, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[1] <= _T_3885 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3886 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3886 : @[Conditional.scala 39:67] + node _T_3887 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_3888 = mux(_T_3887, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[1] <= _T_3888 @[lsu_bus_buffer.scala 498:25] + node _T_3889 = eq(RspPtr, UInt<2>("h01")) @[lsu_bus_buffer.scala 499:37] + node _T_3890 = eq(buf_dualtag[1], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_3891 = and(buf_dual[1], _T_3890) @[lsu_bus_buffer.scala 499:80] + node _T_3892 = or(_T_3889, _T_3891) @[lsu_bus_buffer.scala 499:65] + node _T_3893 = or(_T_3892, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[1] <= _T_3893 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3894 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3894 : @[Conditional.scala 39:67] + buf_nxtstate[1] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_3895 = bits(buf_state_en[1], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_3896 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3895 : @[Reg.scala 28:19] + _T_3896 <= buf_nxtstate[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[1] <= _T_3896 @[lsu_bus_buffer.scala 512:18] + reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_3897 <= buf_age_in_1 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[1] <= _T_3897 @[lsu_bus_buffer.scala 513:17] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_3898 <= buf_rspage_in[1] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[1] <= _T_3898 @[lsu_bus_buffer.scala 514:20] + node _T_3899 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_3900 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3899 : @[Reg.scala 28:19] + _T_3900 <= buf_dualtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[1] <= _T_3900 @[lsu_bus_buffer.scala 515:20] + node _T_3901 = bits(buf_dual_in, 1, 1) @[lsu_bus_buffer.scala 516:74] + node _T_3902 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_3903 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3902 : @[Reg.scala 28:19] + _T_3903 <= _T_3901 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[1] <= _T_3903 @[lsu_bus_buffer.scala 516:17] + node _T_3904 = bits(buf_samedw_in, 1, 1) @[lsu_bus_buffer.scala 517:78] + node _T_3905 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_3906 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3905 : @[Reg.scala 28:19] + _T_3906 <= _T_3904 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[1] <= _T_3906 @[lsu_bus_buffer.scala 517:19] + node _T_3907 = bits(buf_nomerge_in, 1, 1) @[lsu_bus_buffer.scala 518:80] + node _T_3908 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_3909 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3908 : @[Reg.scala 28:19] + _T_3909 <= _T_3907 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[1] <= _T_3909 @[lsu_bus_buffer.scala 518:20] + node _T_3910 = bits(buf_dualhi_in, 1, 1) @[lsu_bus_buffer.scala 519:78] + node _T_3911 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_3912 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3911 : @[Reg.scala 28:19] + _T_3912 <= _T_3910 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[1] <= _T_3912 @[lsu_bus_buffer.scala 519:19] + node _T_3913 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3913 : @[Conditional.scala 40:58] + node _T_3914 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3915 = mux(_T_3914, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[2] <= _T_3915 @[lsu_bus_buffer.scala 444:25] + node _T_3916 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3917 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3918 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3919 = and(_T_3917, _T_3918) @[lsu_bus_buffer.scala 445:95] + node _T_3920 = eq(UInt<2>("h02"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3921 = and(_T_3919, _T_3920) @[lsu_bus_buffer.scala 445:112] + node _T_3922 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3923 = eq(UInt<2>("h02"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3924 = and(_T_3922, _T_3923) @[lsu_bus_buffer.scala 445:161] + node _T_3925 = or(_T_3921, _T_3924) @[lsu_bus_buffer.scala 445:132] + node _T_3926 = and(_T_3916, _T_3925) @[lsu_bus_buffer.scala 445:63] + node _T_3927 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3928 = and(ibuf_drain_vld, _T_3927) @[lsu_bus_buffer.scala 445:201] + node _T_3929 = or(_T_3926, _T_3928) @[lsu_bus_buffer.scala 445:183] + buf_state_en[2] <= _T_3929 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 446:22] + buf_data_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 447:24] + node _T_3930 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3931 = and(ibuf_drain_vld, _T_3930) @[lsu_bus_buffer.scala 448:47] + node _T_3932 = bits(_T_3931, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3933 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3934 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3935 = mux(_T_3932, _T_3933, _T_3934) @[lsu_bus_buffer.scala 448:30] + buf_data_in[2] <= _T_3935 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3936 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3936 : @[Conditional.scala 39:67] + node _T_3937 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3938 = mux(_T_3937, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[2] <= _T_3938 @[lsu_bus_buffer.scala 453:25] + node _T_3939 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[2] <= _T_3939 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3940 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3940 : @[Conditional.scala 39:67] + node _T_3941 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3942 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3943 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3944 = and(_T_3942, _T_3943) @[lsu_bus_buffer.scala 459:104] + node _T_3945 = mux(_T_3944, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3946 = mux(_T_3941, UInt<3>("h00"), _T_3945) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[2] <= _T_3946 @[lsu_bus_buffer.scala 459:25] + node _T_3947 = eq(obuf_tag0, UInt<3>("h02")) @[lsu_bus_buffer.scala 460:48] + node _T_3948 = eq(obuf_tag1, UInt<3>("h02")) @[lsu_bus_buffer.scala 460:104] + node _T_3949 = and(obuf_merge, _T_3948) @[lsu_bus_buffer.scala 460:91] + node _T_3950 = or(_T_3947, _T_3949) @[lsu_bus_buffer.scala 460:77] + node _T_3951 = and(_T_3950, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3952 = and(_T_3951, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[2] <= _T_3952 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[lsu_bus_buffer.scala 461:29] + node _T_3953 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3954 = or(_T_3953, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[2] <= _T_3954 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3955 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 464:56] + node _T_3956 = eq(_T_3955, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3957 = and(buf_state_en[2], _T_3956) @[lsu_bus_buffer.scala 464:44] + node _T_3958 = and(_T_3957, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3959 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3960 = and(_T_3958, _T_3959) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[2] <= _T_3960 @[lsu_bus_buffer.scala 464:25] + node _T_3961 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[2] <= _T_3961 @[lsu_bus_buffer.scala 465:28] + node _T_3962 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3963 = and(_T_3962, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3964 = and(_T_3963, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[2] <= _T_3964 @[lsu_bus_buffer.scala 466:24] + node _T_3965 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3966 = and(_T_3965, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3967 = and(_T_3966, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[2] <= _T_3967 @[lsu_bus_buffer.scala 467:25] + node _T_3968 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3969 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3970 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3971 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3972 = mux(_T_3969, _T_3970, _T_3971) @[lsu_bus_buffer.scala 468:73] + node _T_3973 = mux(buf_error_en[2], _T_3968, _T_3972) @[lsu_bus_buffer.scala 468:30] + buf_data_in[2] <= _T_3973 @[lsu_bus_buffer.scala 468:24] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3974 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3974 : @[Conditional.scala 39:67] + node _T_3975 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 472:69] + node _T_3976 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3977 = and(_T_3975, _T_3976) @[lsu_bus_buffer.scala 472:73] + node _T_3978 = or(io.dec_tlu_force_halt, _T_3977) @[lsu_bus_buffer.scala 472:57] + node _T_3979 = bits(_T_3978, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3980 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3981 = and(buf_dual[2], _T_3980) @[lsu_bus_buffer.scala 473:28] + node _T_3982 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 473:57] + node _T_3983 = eq(_T_3982, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3984 = and(_T_3981, _T_3983) @[lsu_bus_buffer.scala 473:45] + node _T_3985 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3986 = and(_T_3984, _T_3985) @[lsu_bus_buffer.scala 473:61] + node _T_3987 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 474:27] + node _T_3988 = or(_T_3987, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3989 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3990 = and(buf_dual[2], _T_3989) @[lsu_bus_buffer.scala 474:68] + node _T_3991 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 474:97] + node _T_3992 = eq(_T_3991, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3993 = and(_T_3990, _T_3992) @[lsu_bus_buffer.scala 474:85] + node _T_3994 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3995 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3996 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3997 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3998 = eq(buf_dualtag[2], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3999 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4000 = eq(buf_dualtag[2], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4001 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4002 = mux(_T_3994, _T_3995, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4003 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4004 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4005 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4006 = or(_T_4002, _T_4003) @[Mux.scala 27:72] + node _T_4007 = or(_T_4006, _T_4004) @[Mux.scala 27:72] + node _T_4008 = or(_T_4007, _T_4005) @[Mux.scala 27:72] + wire _T_4009 : UInt<1> @[Mux.scala 27:72] + _T_4009 <= _T_4008 @[Mux.scala 27:72] + node _T_4010 = and(_T_3993, _T_4009) @[lsu_bus_buffer.scala 474:101] + node _T_4011 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_4012 = and(_T_4010, _T_4011) @[lsu_bus_buffer.scala 474:138] + node _T_4013 = and(_T_4012, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_4014 = or(_T_3988, _T_4013) @[lsu_bus_buffer.scala 474:53] + node _T_4015 = mux(_T_4014, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_4016 = mux(_T_3986, UInt<3>("h04"), _T_4015) @[lsu_bus_buffer.scala 473:14] + node _T_4017 = mux(_T_3979, UInt<3>("h00"), _T_4016) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[2] <= _T_4017 @[lsu_bus_buffer.scala 472:27] + node _T_4018 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 475:73] + node _T_4019 = and(bus_rsp_write, _T_4018) @[lsu_bus_buffer.scala 475:52] + node _T_4020 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 476:46] + node _T_4021 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 477:23] + node _T_4022 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 477:47] + node _T_4023 = and(_T_4021, _T_4022) @[lsu_bus_buffer.scala 477:27] + node _T_4024 = or(_T_4020, _T_4023) @[lsu_bus_buffer.scala 476:77] + node _T_4025 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 478:26] + node _T_4026 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 478:54] + node _T_4027 = not(_T_4026) @[lsu_bus_buffer.scala 478:44] + node _T_4028 = and(_T_4025, _T_4027) @[lsu_bus_buffer.scala 478:42] + node _T_4029 = and(_T_4028, buf_samedw[2]) @[lsu_bus_buffer.scala 478:58] + node _T_4030 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 478:94] + node _T_4031 = and(_T_4029, _T_4030) @[lsu_bus_buffer.scala 478:74] + node _T_4032 = or(_T_4024, _T_4031) @[lsu_bus_buffer.scala 477:71] + node _T_4033 = and(bus_rsp_read, _T_4032) @[lsu_bus_buffer.scala 476:25] + node _T_4034 = or(_T_4019, _T_4033) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[2] <= _T_4034 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[lsu_bus_buffer.scala 479:29] + node _T_4035 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_4036 = or(_T_4035, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[2] <= _T_4036 @[lsu_bus_buffer.scala 480:25] + node _T_4037 = and(buf_state_bus_en[2], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_4038 = and(_T_4037, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[2] <= _T_4038 @[lsu_bus_buffer.scala 481:24] + node _T_4039 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_4040 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 482:111] + node _T_4041 = and(bus_rsp_read_error, _T_4040) @[lsu_bus_buffer.scala 482:91] + node _T_4042 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 483:42] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[lsu_bus_buffer.scala 483:31] + node _T_4044 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 483:66] + node _T_4045 = and(_T_4043, _T_4044) @[lsu_bus_buffer.scala 483:46] + node _T_4046 = or(_T_4041, _T_4045) @[lsu_bus_buffer.scala 482:143] + node _T_4047 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 484:54] + node _T_4048 = and(bus_rsp_write_error, _T_4047) @[lsu_bus_buffer.scala 484:33] + node _T_4049 = or(_T_4046, _T_4048) @[lsu_bus_buffer.scala 483:88] + node _T_4050 = and(_T_4039, _T_4049) @[lsu_bus_buffer.scala 482:68] + buf_error_en[2] <= _T_4050 @[lsu_bus_buffer.scala 482:25] + node _T_4051 = eq(buf_error_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_4052 = and(buf_state_en[2], _T_4051) @[lsu_bus_buffer.scala 485:48] + node _T_4053 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_4054 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_4055 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_4056 = mux(_T_4053, _T_4054, _T_4055) @[lsu_bus_buffer.scala 485:72] + node _T_4057 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_4058 = mux(_T_4052, _T_4056, _T_4057) @[lsu_bus_buffer.scala 485:30] + buf_data_in[2] <= _T_4058 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4059 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4059 : @[Conditional.scala 39:67] + node _T_4060 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_4061 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 490:86] + node _T_4062 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 490:101] + node _T_4063 = bits(_T_4062, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_4064 = or(_T_4061, _T_4063) @[lsu_bus_buffer.scala 490:90] + node _T_4065 = or(_T_4064, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_4066 = mux(_T_4065, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_4067 = mux(_T_4060, UInt<3>("h00"), _T_4066) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[2] <= _T_4067 @[lsu_bus_buffer.scala 490:25] + node _T_4068 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 491:66] + node _T_4069 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 492:21] + node _T_4070 = bits(_T_4069, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_4071 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[lsu_bus_buffer.scala 492:58] + node _T_4072 = and(_T_4070, _T_4071) @[lsu_bus_buffer.scala 492:38] + node _T_4073 = or(_T_4068, _T_4072) @[lsu_bus_buffer.scala 491:95] + node _T_4074 = and(bus_rsp_read, _T_4073) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[2] <= _T_4074 @[lsu_bus_buffer.scala 491:29] + node _T_4075 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_4076 = or(_T_4075, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[2] <= _T_4076 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4077 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4077 : @[Conditional.scala 39:67] + node _T_4078 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_4079 = mux(_T_4078, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[2] <= _T_4079 @[lsu_bus_buffer.scala 498:25] + node _T_4080 = eq(RspPtr, UInt<2>("h02")) @[lsu_bus_buffer.scala 499:37] + node _T_4081 = eq(buf_dualtag[2], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_4082 = and(buf_dual[2], _T_4081) @[lsu_bus_buffer.scala 499:80] + node _T_4083 = or(_T_4080, _T_4082) @[lsu_bus_buffer.scala 499:65] + node _T_4084 = or(_T_4083, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[2] <= _T_4084 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4085 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4085 : @[Conditional.scala 39:67] + buf_nxtstate[2] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_4086 = bits(buf_state_en[2], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_4087 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4086 : @[Reg.scala 28:19] + _T_4087 <= buf_nxtstate[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[2] <= _T_4087 @[lsu_bus_buffer.scala 512:18] + reg _T_4088 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_4088 <= buf_age_in_2 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[2] <= _T_4088 @[lsu_bus_buffer.scala 513:17] + reg _T_4089 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_4089 <= buf_rspage_in[2] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[2] <= _T_4089 @[lsu_bus_buffer.scala 514:20] + node _T_4090 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4090 : @[Reg.scala 28:19] + _T_4091 <= buf_dualtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[2] <= _T_4091 @[lsu_bus_buffer.scala 515:20] + node _T_4092 = bits(buf_dual_in, 2, 2) @[lsu_bus_buffer.scala 516:74] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_4094 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4093 : @[Reg.scala 28:19] + _T_4094 <= _T_4092 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[2] <= _T_4094 @[lsu_bus_buffer.scala 516:17] + node _T_4095 = bits(buf_samedw_in, 2, 2) @[lsu_bus_buffer.scala 517:78] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4096 : @[Reg.scala 28:19] + _T_4097 <= _T_4095 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[2] <= _T_4097 @[lsu_bus_buffer.scala 517:19] + node _T_4098 = bits(buf_nomerge_in, 2, 2) @[lsu_bus_buffer.scala 518:80] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4099 : @[Reg.scala 28:19] + _T_4100 <= _T_4098 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[2] <= _T_4100 @[lsu_bus_buffer.scala 518:20] + node _T_4101 = bits(buf_dualhi_in, 2, 2) @[lsu_bus_buffer.scala 519:78] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4102 : @[Reg.scala 28:19] + _T_4103 <= _T_4101 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[2] <= _T_4103 @[lsu_bus_buffer.scala 519:19] + node _T_4104 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4104 : @[Conditional.scala 40:58] + node _T_4105 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_4106 = mux(_T_4105, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[3] <= _T_4106 @[lsu_bus_buffer.scala 444:25] + node _T_4107 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_4108 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_4109 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_4110 = and(_T_4108, _T_4109) @[lsu_bus_buffer.scala 445:95] + node _T_4111 = eq(UInt<2>("h03"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_4112 = and(_T_4110, _T_4111) @[lsu_bus_buffer.scala 445:112] + node _T_4113 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_4114 = eq(UInt<2>("h03"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_4115 = and(_T_4113, _T_4114) @[lsu_bus_buffer.scala 445:161] + node _T_4116 = or(_T_4112, _T_4115) @[lsu_bus_buffer.scala 445:132] + node _T_4117 = and(_T_4107, _T_4116) @[lsu_bus_buffer.scala 445:63] + node _T_4118 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_4119 = and(ibuf_drain_vld, _T_4118) @[lsu_bus_buffer.scala 445:201] + node _T_4120 = or(_T_4117, _T_4119) @[lsu_bus_buffer.scala 445:183] + buf_state_en[3] <= _T_4120 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 446:22] + buf_data_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 447:24] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[lsu_bus_buffer.scala 448:47] + node _T_4123 = bits(_T_4122, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_4124 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_4125 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_4126 = mux(_T_4123, _T_4124, _T_4125) @[lsu_bus_buffer.scala 448:30] + buf_data_in[3] <= _T_4126 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_4127 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4127 : @[Conditional.scala 39:67] + node _T_4128 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_4129 = mux(_T_4128, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[3] <= _T_4129 @[lsu_bus_buffer.scala 453:25] + node _T_4130 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[3] <= _T_4130 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4131 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4131 : @[Conditional.scala 39:67] + node _T_4132 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_4133 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_4134 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_4135 = and(_T_4133, _T_4134) @[lsu_bus_buffer.scala 459:104] + node _T_4136 = mux(_T_4135, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_4137 = mux(_T_4132, UInt<3>("h00"), _T_4136) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[3] <= _T_4137 @[lsu_bus_buffer.scala 459:25] + node _T_4138 = eq(obuf_tag0, UInt<3>("h03")) @[lsu_bus_buffer.scala 460:48] + node _T_4139 = eq(obuf_tag1, UInt<3>("h03")) @[lsu_bus_buffer.scala 460:104] + node _T_4140 = and(obuf_merge, _T_4139) @[lsu_bus_buffer.scala 460:91] + node _T_4141 = or(_T_4138, _T_4140) @[lsu_bus_buffer.scala 460:77] + node _T_4142 = and(_T_4141, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_4143 = and(_T_4142, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[3] <= _T_4143 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[lsu_bus_buffer.scala 461:29] + node _T_4144 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_4145 = or(_T_4144, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[3] <= _T_4145 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_4146 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 464:56] + node _T_4147 = eq(_T_4146, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_4148 = and(buf_state_en[3], _T_4147) @[lsu_bus_buffer.scala 464:44] + node _T_4149 = and(_T_4148, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_4150 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_4151 = and(_T_4149, _T_4150) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[3] <= _T_4151 @[lsu_bus_buffer.scala 464:25] + node _T_4152 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[3] <= _T_4152 @[lsu_bus_buffer.scala 465:28] + node _T_4153 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_4154 = and(_T_4153, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_4155 = and(_T_4154, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[3] <= _T_4155 @[lsu_bus_buffer.scala 466:24] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_4157 = and(_T_4156, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_4158 = and(_T_4157, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[3] <= _T_4158 @[lsu_bus_buffer.scala 467:25] + node _T_4159 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_4160 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_4161 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_4163 = mux(_T_4160, _T_4161, _T_4162) @[lsu_bus_buffer.scala 468:73] + node _T_4164 = mux(buf_error_en[3], _T_4159, _T_4163) @[lsu_bus_buffer.scala 468:30] + buf_data_in[3] <= _T_4164 @[lsu_bus_buffer.scala 468:24] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4165 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4165 : @[Conditional.scala 39:67] + node _T_4166 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 472:69] + node _T_4167 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_4168 = and(_T_4166, _T_4167) @[lsu_bus_buffer.scala 472:73] + node _T_4169 = or(io.dec_tlu_force_halt, _T_4168) @[lsu_bus_buffer.scala 472:57] + node _T_4170 = bits(_T_4169, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_4171 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_4172 = and(buf_dual[3], _T_4171) @[lsu_bus_buffer.scala 473:28] + node _T_4173 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 473:57] + node _T_4174 = eq(_T_4173, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_4175 = and(_T_4172, _T_4174) @[lsu_bus_buffer.scala 473:45] + node _T_4176 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_4177 = and(_T_4175, _T_4176) @[lsu_bus_buffer.scala 473:61] + node _T_4178 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 474:27] + node _T_4179 = or(_T_4178, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_4180 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_4181 = and(buf_dual[3], _T_4180) @[lsu_bus_buffer.scala 474:68] + node _T_4182 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 474:97] + node _T_4183 = eq(_T_4182, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_4184 = and(_T_4181, _T_4183) @[lsu_bus_buffer.scala 474:85] + node _T_4185 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_4186 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_4187 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_4188 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_4189 = eq(buf_dualtag[3], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_4190 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4191 = eq(buf_dualtag[3], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4192 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4193 = mux(_T_4185, _T_4186, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4194 = mux(_T_4187, _T_4188, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4195 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4196 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4197 = or(_T_4193, _T_4194) @[Mux.scala 27:72] + node _T_4198 = or(_T_4197, _T_4195) @[Mux.scala 27:72] + node _T_4199 = or(_T_4198, _T_4196) @[Mux.scala 27:72] + wire _T_4200 : UInt<1> @[Mux.scala 27:72] + _T_4200 <= _T_4199 @[Mux.scala 27:72] + node _T_4201 = and(_T_4184, _T_4200) @[lsu_bus_buffer.scala 474:101] + node _T_4202 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_4203 = and(_T_4201, _T_4202) @[lsu_bus_buffer.scala 474:138] + node _T_4204 = and(_T_4203, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_4205 = or(_T_4179, _T_4204) @[lsu_bus_buffer.scala 474:53] + node _T_4206 = mux(_T_4205, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_4207 = mux(_T_4177, UInt<3>("h04"), _T_4206) @[lsu_bus_buffer.scala 473:14] + node _T_4208 = mux(_T_4170, UInt<3>("h00"), _T_4207) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[3] <= _T_4208 @[lsu_bus_buffer.scala 472:27] + node _T_4209 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 475:73] + node _T_4210 = and(bus_rsp_write, _T_4209) @[lsu_bus_buffer.scala 475:52] + node _T_4211 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 476:46] + node _T_4212 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 477:23] + node _T_4213 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 477:47] + node _T_4214 = and(_T_4212, _T_4213) @[lsu_bus_buffer.scala 477:27] + node _T_4215 = or(_T_4211, _T_4214) @[lsu_bus_buffer.scala 476:77] + node _T_4216 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 478:26] + node _T_4217 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 478:54] + node _T_4218 = not(_T_4217) @[lsu_bus_buffer.scala 478:44] + node _T_4219 = and(_T_4216, _T_4218) @[lsu_bus_buffer.scala 478:42] + node _T_4220 = and(_T_4219, buf_samedw[3]) @[lsu_bus_buffer.scala 478:58] + node _T_4221 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 478:94] + node _T_4222 = and(_T_4220, _T_4221) @[lsu_bus_buffer.scala 478:74] + node _T_4223 = or(_T_4215, _T_4222) @[lsu_bus_buffer.scala 477:71] + node _T_4224 = and(bus_rsp_read, _T_4223) @[lsu_bus_buffer.scala 476:25] + node _T_4225 = or(_T_4210, _T_4224) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[3] <= _T_4225 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[lsu_bus_buffer.scala 479:29] + node _T_4226 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_4227 = or(_T_4226, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[3] <= _T_4227 @[lsu_bus_buffer.scala 480:25] + node _T_4228 = and(buf_state_bus_en[3], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_4229 = and(_T_4228, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[3] <= _T_4229 @[lsu_bus_buffer.scala 481:24] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_4231 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 482:111] + node _T_4232 = and(bus_rsp_read_error, _T_4231) @[lsu_bus_buffer.scala 482:91] + node _T_4233 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 483:42] + node _T_4234 = and(bus_rsp_read_error, _T_4233) @[lsu_bus_buffer.scala 483:31] + node _T_4235 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 483:66] + node _T_4236 = and(_T_4234, _T_4235) @[lsu_bus_buffer.scala 483:46] + node _T_4237 = or(_T_4232, _T_4236) @[lsu_bus_buffer.scala 482:143] + node _T_4238 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 484:54] + node _T_4239 = and(bus_rsp_write_error, _T_4238) @[lsu_bus_buffer.scala 484:33] + node _T_4240 = or(_T_4237, _T_4239) @[lsu_bus_buffer.scala 483:88] + node _T_4241 = and(_T_4230, _T_4240) @[lsu_bus_buffer.scala 482:68] + buf_error_en[3] <= _T_4241 @[lsu_bus_buffer.scala 482:25] + node _T_4242 = eq(buf_error_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_4243 = and(buf_state_en[3], _T_4242) @[lsu_bus_buffer.scala 485:48] + node _T_4244 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_4245 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_4246 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_4247 = mux(_T_4244, _T_4245, _T_4246) @[lsu_bus_buffer.scala 485:72] + node _T_4248 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_4249 = mux(_T_4243, _T_4247, _T_4248) @[lsu_bus_buffer.scala 485:30] + buf_data_in[3] <= _T_4249 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4250 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4250 : @[Conditional.scala 39:67] + node _T_4251 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_4252 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 490:86] + node _T_4253 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 490:101] + node _T_4254 = bits(_T_4253, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_4255 = or(_T_4252, _T_4254) @[lsu_bus_buffer.scala 490:90] + node _T_4256 = or(_T_4255, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_4257 = mux(_T_4256, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_4258 = mux(_T_4251, UInt<3>("h00"), _T_4257) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[3] <= _T_4258 @[lsu_bus_buffer.scala 490:25] + node _T_4259 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 491:66] + node _T_4260 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 492:21] + node _T_4261 = bits(_T_4260, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_4262 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[lsu_bus_buffer.scala 492:58] + node _T_4263 = and(_T_4261, _T_4262) @[lsu_bus_buffer.scala 492:38] + node _T_4264 = or(_T_4259, _T_4263) @[lsu_bus_buffer.scala 491:95] + node _T_4265 = and(bus_rsp_read, _T_4264) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[3] <= _T_4265 @[lsu_bus_buffer.scala 491:29] + node _T_4266 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_4267 = or(_T_4266, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[3] <= _T_4267 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4268 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4268 : @[Conditional.scala 39:67] + node _T_4269 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_4270 = mux(_T_4269, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[3] <= _T_4270 @[lsu_bus_buffer.scala 498:25] + node _T_4271 = eq(RspPtr, UInt<2>("h03")) @[lsu_bus_buffer.scala 499:37] + node _T_4272 = eq(buf_dualtag[3], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_4273 = and(buf_dual[3], _T_4272) @[lsu_bus_buffer.scala 499:80] + node _T_4274 = or(_T_4271, _T_4273) @[lsu_bus_buffer.scala 499:65] + node _T_4275 = or(_T_4274, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[3] <= _T_4275 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4276 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4276 : @[Conditional.scala 39:67] + buf_nxtstate[3] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_4277 = bits(buf_state_en[3], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_4278 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4277 : @[Reg.scala 28:19] + _T_4278 <= buf_nxtstate[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[3] <= _T_4278 @[lsu_bus_buffer.scala 512:18] + reg _T_4279 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_4279 <= buf_age_in_3 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[3] <= _T_4279 @[lsu_bus_buffer.scala 513:17] + reg _T_4280 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_4280 <= buf_rspage_in[3] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[3] <= _T_4280 @[lsu_bus_buffer.scala 514:20] + node _T_4281 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_4282 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4281 : @[Reg.scala 28:19] + _T_4282 <= buf_dualtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[3] <= _T_4282 @[lsu_bus_buffer.scala 515:20] + node _T_4283 = bits(buf_dual_in, 3, 3) @[lsu_bus_buffer.scala 516:74] + node _T_4284 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_4285 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4284 : @[Reg.scala 28:19] + _T_4285 <= _T_4283 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[3] <= _T_4285 @[lsu_bus_buffer.scala 516:17] + node _T_4286 = bits(buf_samedw_in, 3, 3) @[lsu_bus_buffer.scala 517:78] + node _T_4287 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_4288 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4287 : @[Reg.scala 28:19] + _T_4288 <= _T_4286 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[3] <= _T_4288 @[lsu_bus_buffer.scala 517:19] + node _T_4289 = bits(buf_nomerge_in, 3, 3) @[lsu_bus_buffer.scala 518:80] + node _T_4290 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_4291 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4290 : @[Reg.scala 28:19] + _T_4291 <= _T_4289 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[3] <= _T_4291 @[lsu_bus_buffer.scala 518:20] + node _T_4292 = bits(buf_dualhi_in, 3, 3) @[lsu_bus_buffer.scala 519:78] + node _T_4293 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_4294 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4293 : @[Reg.scala 28:19] + _T_4294 <= _T_4292 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[3] <= _T_4294 @[lsu_bus_buffer.scala 519:19] + node _T_4295 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4295 : @[Reg.scala 28:19] + _T_4296 <= buf_ldfwd_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4297 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4298 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4297 : @[Reg.scala 28:19] + _T_4298 <= buf_ldfwd_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4299 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4300 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4299 : @[Reg.scala 28:19] + _T_4300 <= buf_ldfwd_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4301 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4302 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4301 : @[Reg.scala 28:19] + _T_4302 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4303 = cat(_T_4302, _T_4300) @[Cat.scala 29:58] + node _T_4304 = cat(_T_4303, _T_4298) @[Cat.scala 29:58] + node _T_4305 = cat(_T_4304, _T_4296) @[Cat.scala 29:58] + buf_ldfwd <= _T_4305 @[lsu_bus_buffer.scala 522:13] + node _T_4306 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4307 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4306 : @[Reg.scala 28:19] + _T_4307 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4308 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4309 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4308 : @[Reg.scala 28:19] + _T_4309 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4310 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4311 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4310 : @[Reg.scala 28:19] + _T_4311 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4312 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4313 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4312 : @[Reg.scala 28:19] + _T_4313 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_ldfwdtag[0] <= _T_4307 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[1] <= _T_4309 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[2] <= _T_4311 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[3] <= _T_4313 @[lsu_bus_buffer.scala 523:16] + node _T_4314 = bits(buf_sideeffect_in, 0, 0) @[lsu_bus_buffer.scala 524:105] + node _T_4315 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4316 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4315 : @[Reg.scala 28:19] + _T_4316 <= _T_4314 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4317 = bits(buf_sideeffect_in, 1, 1) @[lsu_bus_buffer.scala 524:105] + node _T_4318 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4319 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4318 : @[Reg.scala 28:19] + _T_4319 <= _T_4317 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4320 = bits(buf_sideeffect_in, 2, 2) @[lsu_bus_buffer.scala 524:105] + node _T_4321 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4322 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4321 : @[Reg.scala 28:19] + _T_4322 <= _T_4320 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4323 = bits(buf_sideeffect_in, 3, 3) @[lsu_bus_buffer.scala 524:105] + node _T_4324 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4325 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4324 : @[Reg.scala 28:19] + _T_4325 <= _T_4323 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4326 = cat(_T_4325, _T_4322) @[Cat.scala 29:58] + node _T_4327 = cat(_T_4326, _T_4319) @[Cat.scala 29:58] + node _T_4328 = cat(_T_4327, _T_4316) @[Cat.scala 29:58] + buf_sideeffect <= _T_4328 @[lsu_bus_buffer.scala 524:18] + node _T_4329 = bits(buf_unsign_in, 0, 0) @[lsu_bus_buffer.scala 525:97] + node _T_4330 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4331 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4330 : @[Reg.scala 28:19] + _T_4331 <= _T_4329 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4332 = bits(buf_unsign_in, 1, 1) @[lsu_bus_buffer.scala 525:97] + node _T_4333 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4334 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4333 : @[Reg.scala 28:19] + _T_4334 <= _T_4332 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4335 = bits(buf_unsign_in, 2, 2) @[lsu_bus_buffer.scala 525:97] + node _T_4336 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4337 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4336 : @[Reg.scala 28:19] + _T_4337 <= _T_4335 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4338 = bits(buf_unsign_in, 3, 3) @[lsu_bus_buffer.scala 525:97] + node _T_4339 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4340 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4339 : @[Reg.scala 28:19] + _T_4340 <= _T_4338 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4341 = cat(_T_4340, _T_4337) @[Cat.scala 29:58] + node _T_4342 = cat(_T_4341, _T_4334) @[Cat.scala 29:58] + node _T_4343 = cat(_T_4342, _T_4331) @[Cat.scala 29:58] + buf_unsign <= _T_4343 @[lsu_bus_buffer.scala 525:14] + node _T_4344 = bits(buf_write_in, 0, 0) @[lsu_bus_buffer.scala 526:95] + node _T_4345 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4346 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4345 : @[Reg.scala 28:19] + _T_4346 <= _T_4344 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4347 = bits(buf_write_in, 1, 1) @[lsu_bus_buffer.scala 526:95] + node _T_4348 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4349 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4348 : @[Reg.scala 28:19] + _T_4349 <= _T_4347 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4350 = bits(buf_write_in, 2, 2) @[lsu_bus_buffer.scala 526:95] + node _T_4351 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4352 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4351 : @[Reg.scala 28:19] + _T_4352 <= _T_4350 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4353 = bits(buf_write_in, 3, 3) @[lsu_bus_buffer.scala 526:95] + node _T_4354 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4355 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4354 : @[Reg.scala 28:19] + _T_4355 <= _T_4353 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4356 = cat(_T_4355, _T_4352) @[Cat.scala 29:58] + node _T_4357 = cat(_T_4356, _T_4349) @[Cat.scala 29:58] + node _T_4358 = cat(_T_4357, _T_4346) @[Cat.scala 29:58] + buf_write <= _T_4358 @[lsu_bus_buffer.scala 526:13] + node _T_4359 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4360 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4359 : @[Reg.scala 28:19] + _T_4360 <= buf_sz_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4361 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4362 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4361 : @[Reg.scala 28:19] + _T_4362 <= buf_sz_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4363 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4364 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4363 : @[Reg.scala 28:19] + _T_4364 <= buf_sz_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4365 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4366 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4365 : @[Reg.scala 28:19] + _T_4366 <= buf_sz_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_sz[0] <= _T_4360 @[lsu_bus_buffer.scala 527:10] + buf_sz[1] <= _T_4362 @[lsu_bus_buffer.scala 527:10] + buf_sz[2] <= _T_4364 @[lsu_bus_buffer.scala 527:10] + buf_sz[3] <= _T_4366 @[lsu_bus_buffer.scala 527:10] + node _T_4367 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_4367 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4368 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4367 : @[Reg.scala 28:19] + _T_4368 <= buf_addr_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4369 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_4369 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4370 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4369 : @[Reg.scala 28:19] + _T_4370 <= buf_addr_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4371 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_4371 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4372 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4371 : @[Reg.scala 28:19] + _T_4372 <= buf_addr_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4373 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_4373 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4374 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4373 : @[Reg.scala 28:19] + _T_4374 <= buf_addr_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_addr[0] <= _T_4368 @[lsu_bus_buffer.scala 528:12] + buf_addr[1] <= _T_4370 @[lsu_bus_buffer.scala 528:12] + buf_addr[2] <= _T_4372 @[lsu_bus_buffer.scala 528:12] + buf_addr[3] <= _T_4374 @[lsu_bus_buffer.scala 528:12] + node _T_4375 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4376 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4375 : @[Reg.scala 28:19] + _T_4376 <= buf_byteen_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4377 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4378 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4377 : @[Reg.scala 28:19] + _T_4378 <= buf_byteen_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4379 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4380 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4379 : @[Reg.scala 28:19] + _T_4380 <= buf_byteen_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4381 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4382 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4381 : @[Reg.scala 28:19] + _T_4382 <= buf_byteen_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen[0] <= _T_4376 @[lsu_bus_buffer.scala 529:14] + buf_byteen[1] <= _T_4378 @[lsu_bus_buffer.scala 529:14] + buf_byteen[2] <= _T_4380 @[lsu_bus_buffer.scala 529:14] + buf_byteen[3] <= _T_4382 @[lsu_bus_buffer.scala 529:14] + inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4383 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[0] : @[Reg.scala 28:19] + _T_4383 <= buf_data_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4384 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[1] : @[Reg.scala 28:19] + _T_4384 <= buf_data_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4385 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[2] : @[Reg.scala 28:19] + _T_4385 <= buf_data_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 404:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 407:17] + rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4386 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[3] : @[Reg.scala 28:19] + _T_4386 <= buf_data_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_data[0] <= _T_4383 @[lsu_bus_buffer.scala 530:12] + buf_data[1] <= _T_4384 @[lsu_bus_buffer.scala 530:12] + buf_data[2] <= _T_4385 @[lsu_bus_buffer.scala 530:12] + buf_data[3] <= _T_4386 @[lsu_bus_buffer.scala 530:12] + node _T_4387 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4388 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 531:133] + node _T_4389 = mux(buf_error_en[0], UInt<1>("h01"), _T_4388) @[lsu_bus_buffer.scala 531:98] + node _T_4390 = and(_T_4387, _T_4389) @[lsu_bus_buffer.scala 531:93] + reg _T_4391 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4391 <= _T_4390 @[lsu_bus_buffer.scala 531:80] + node _T_4392 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4393 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 531:133] + node _T_4394 = mux(buf_error_en[1], UInt<1>("h01"), _T_4393) @[lsu_bus_buffer.scala 531:98] + node _T_4395 = and(_T_4392, _T_4394) @[lsu_bus_buffer.scala 531:93] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4396 <= _T_4395 @[lsu_bus_buffer.scala 531:80] + node _T_4397 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4398 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 531:133] + node _T_4399 = mux(buf_error_en[2], UInt<1>("h01"), _T_4398) @[lsu_bus_buffer.scala 531:98] + node _T_4400 = and(_T_4397, _T_4399) @[lsu_bus_buffer.scala 531:93] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4401 <= _T_4400 @[lsu_bus_buffer.scala 531:80] + node _T_4402 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4403 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 531:133] + node _T_4404 = mux(buf_error_en[3], UInt<1>("h01"), _T_4403) @[lsu_bus_buffer.scala 531:98] + node _T_4405 = and(_T_4402, _T_4404) @[lsu_bus_buffer.scala 531:93] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4406 <= _T_4405 @[lsu_bus_buffer.scala 531:80] + node _T_4407 = cat(_T_4406, _T_4401) @[Cat.scala 29:58] + node _T_4408 = cat(_T_4407, _T_4396) @[Cat.scala 29:58] + node _T_4409 = cat(_T_4408, _T_4391) @[Cat.scala 29:58] + buf_error <= _T_4409 @[lsu_bus_buffer.scala 531:13] + node _T_4410 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4411 = mux(io.ldst_dual_m, _T_4410, io.lsu_busreq_m) @[lsu_bus_buffer.scala 532:28] + node _T_4412 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4413 = mux(io.ldst_dual_r, _T_4412, io.lsu_busreq_r) @[lsu_bus_buffer.scala 532:94] + node _T_4414 = add(_T_4411, _T_4413) @[lsu_bus_buffer.scala 532:88] + node _T_4415 = add(_T_4414, ibuf_valid) @[lsu_bus_buffer.scala 532:154] + node _T_4416 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4417 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4418 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4419 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4420 = add(_T_4416, _T_4417) @[lsu_bus_buffer.scala 532:217] + node _T_4421 = add(_T_4420, _T_4418) @[lsu_bus_buffer.scala 532:217] + node _T_4422 = add(_T_4421, _T_4419) @[lsu_bus_buffer.scala 532:217] + node _T_4423 = add(_T_4415, _T_4422) @[lsu_bus_buffer.scala 532:169] + node buf_numvld_any = tail(_T_4423, 1) @[lsu_bus_buffer.scala 532:169] + node _T_4424 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 533:60] + node _T_4425 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4426 = and(_T_4424, _T_4425) @[lsu_bus_buffer.scala 533:64] + node _T_4427 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4428 = and(_T_4426, _T_4427) @[lsu_bus_buffer.scala 533:89] + node _T_4429 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 533:60] + node _T_4430 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4431 = and(_T_4429, _T_4430) @[lsu_bus_buffer.scala 533:64] + node _T_4432 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4433 = and(_T_4431, _T_4432) @[lsu_bus_buffer.scala 533:89] + node _T_4434 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 533:60] + node _T_4435 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4436 = and(_T_4434, _T_4435) @[lsu_bus_buffer.scala 533:64] + node _T_4437 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4438 = and(_T_4436, _T_4437) @[lsu_bus_buffer.scala 533:89] + node _T_4439 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 533:60] + node _T_4440 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4441 = and(_T_4439, _T_4440) @[lsu_bus_buffer.scala 533:64] + node _T_4442 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4443 = and(_T_4441, _T_4442) @[lsu_bus_buffer.scala 533:89] + node _T_4444 = add(_T_4443, _T_4438) @[lsu_bus_buffer.scala 533:142] + node _T_4445 = add(_T_4444, _T_4433) @[lsu_bus_buffer.scala 533:142] + node _T_4446 = add(_T_4445, _T_4428) @[lsu_bus_buffer.scala 533:142] + buf_numvld_wrcmd_any <= _T_4446 @[lsu_bus_buffer.scala 533:24] + node _T_4447 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4448 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4449 = and(_T_4447, _T_4448) @[lsu_bus_buffer.scala 534:73] + node _T_4450 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4451 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4452 = and(_T_4450, _T_4451) @[lsu_bus_buffer.scala 534:73] + node _T_4453 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4454 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4455 = and(_T_4453, _T_4454) @[lsu_bus_buffer.scala 534:73] + node _T_4456 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4457 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4458 = and(_T_4456, _T_4457) @[lsu_bus_buffer.scala 534:73] + node _T_4459 = add(_T_4458, _T_4455) @[lsu_bus_buffer.scala 534:126] + node _T_4460 = add(_T_4459, _T_4452) @[lsu_bus_buffer.scala 534:126] + node _T_4461 = add(_T_4460, _T_4449) @[lsu_bus_buffer.scala 534:126] + buf_numvld_cmd_any <= _T_4461 @[lsu_bus_buffer.scala 534:22] + node _T_4462 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4463 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4464 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4465 = and(_T_4463, _T_4464) @[lsu_bus_buffer.scala 535:100] + node _T_4466 = or(_T_4462, _T_4465) @[lsu_bus_buffer.scala 535:74] + node _T_4467 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4468 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4469 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4470 = and(_T_4468, _T_4469) @[lsu_bus_buffer.scala 535:100] + node _T_4471 = or(_T_4467, _T_4470) @[lsu_bus_buffer.scala 535:74] + node _T_4472 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4473 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4474 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4475 = and(_T_4473, _T_4474) @[lsu_bus_buffer.scala 535:100] + node _T_4476 = or(_T_4472, _T_4475) @[lsu_bus_buffer.scala 535:74] + node _T_4477 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4478 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4479 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4480 = and(_T_4478, _T_4479) @[lsu_bus_buffer.scala 535:100] + node _T_4481 = or(_T_4477, _T_4480) @[lsu_bus_buffer.scala 535:74] + node _T_4482 = add(_T_4481, _T_4476) @[lsu_bus_buffer.scala 535:154] + node _T_4483 = add(_T_4482, _T_4471) @[lsu_bus_buffer.scala 535:154] + node _T_4484 = add(_T_4483, _T_4466) @[lsu_bus_buffer.scala 535:154] + buf_numvld_pend_any <= _T_4484 @[lsu_bus_buffer.scala 535:23] + node _T_4485 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4486 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4487 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4488 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4489 = or(_T_4488, _T_4487) @[lsu_bus_buffer.scala 536:93] + node _T_4490 = or(_T_4489, _T_4486) @[lsu_bus_buffer.scala 536:93] + node _T_4491 = or(_T_4490, _T_4485) @[lsu_bus_buffer.scala 536:93] + any_done_wait_state <= _T_4491 @[lsu_bus_buffer.scala 536:23] + node _T_4492 = orr(buf_numvld_pend_any) @[lsu_bus_buffer.scala 537:53] + io.lsu_bus_buffer_pend_any <= _T_4492 @[lsu_bus_buffer.scala 537:30] + node _T_4493 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[lsu_bus_buffer.scala 538:52] + node _T_4494 = geq(buf_numvld_any, UInt<2>("h03")) @[lsu_bus_buffer.scala 538:92] + node _T_4495 = eq(buf_numvld_any, UInt<3>("h04")) @[lsu_bus_buffer.scala 538:121] + node _T_4496 = mux(_T_4493, _T_4494, _T_4495) @[lsu_bus_buffer.scala 538:36] + io.lsu_bus_buffer_full_any <= _T_4496 @[lsu_bus_buffer.scala 538:30] + node _T_4497 = orr(buf_state[0]) @[lsu_bus_buffer.scala 539:52] + node _T_4498 = orr(buf_state[1]) @[lsu_bus_buffer.scala 539:52] + node _T_4499 = orr(buf_state[2]) @[lsu_bus_buffer.scala 539:52] + node _T_4500 = orr(buf_state[3]) @[lsu_bus_buffer.scala 539:52] + node _T_4501 = or(_T_4497, _T_4498) @[lsu_bus_buffer.scala 539:65] + node _T_4502 = or(_T_4501, _T_4499) @[lsu_bus_buffer.scala 539:65] + node _T_4503 = or(_T_4502, _T_4500) @[lsu_bus_buffer.scala 539:65] + node _T_4504 = eq(_T_4503, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:34] + node _T_4505 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:72] + node _T_4506 = and(_T_4504, _T_4505) @[lsu_bus_buffer.scala 539:70] + node _T_4507 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:86] + node _T_4508 = and(_T_4506, _T_4507) @[lsu_bus_buffer.scala 539:84] + io.lsu_bus_buffer_empty_any <= _T_4508 @[lsu_bus_buffer.scala 539:31] + node _T_4509 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[lsu_bus_buffer.scala 541:64] + node _T_4510 = and(_T_4509, io.lsu_pkt_m.bits.load) @[lsu_bus_buffer.scala 541:85] + node _T_4511 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_bus_buffer.scala 541:112] + node _T_4512 = and(_T_4510, _T_4511) @[lsu_bus_buffer.scala 541:110] + node _T_4513 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 541:129] + node _T_4514 = and(_T_4512, _T_4513) @[lsu_bus_buffer.scala 541:127] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= _T_4514 @[lsu_bus_buffer.scala 541:45] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= WrPtr0_m @[lsu_bus_buffer.scala 542:43] + wire lsu_nonblock_load_valid_r : UInt<1> + lsu_nonblock_load_valid_r <= UInt<1>("h00") + node _T_4515 = eq(io.lsu_commit_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:74] + node _T_4516 = and(lsu_nonblock_load_valid_r, _T_4515) @[lsu_bus_buffer.scala 544:72] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= _T_4516 @[lsu_bus_buffer.scala 544:43] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 545:47] + node _T_4517 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4518 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 546:106] + node _T_4519 = eq(_T_4518, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4520 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4521 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 546:106] + node _T_4522 = eq(_T_4521, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4523 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4524 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 546:106] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4526 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4527 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 546:106] + node _T_4528 = eq(_T_4527, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4529 = mux(_T_4517, _T_4519, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4530 = mux(_T_4520, _T_4522, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4531 = mux(_T_4523, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4532 = mux(_T_4526, _T_4528, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4533 = or(_T_4529, _T_4530) @[Mux.scala 27:72] + node _T_4534 = or(_T_4533, _T_4531) @[Mux.scala 27:72] + node _T_4535 = or(_T_4534, _T_4532) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_load_data_ready <= _T_4535 @[Mux.scala 27:72] + node _T_4536 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4537 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 547:117] + node _T_4538 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 547:133] + node _T_4539 = eq(_T_4538, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4540 = and(_T_4537, _T_4539) @[lsu_bus_buffer.scala 547:121] + node _T_4541 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4542 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 547:117] + node _T_4543 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 547:133] + node _T_4544 = eq(_T_4543, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4545 = and(_T_4542, _T_4544) @[lsu_bus_buffer.scala 547:121] + node _T_4546 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4547 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 547:117] + node _T_4548 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 547:133] + node _T_4549 = eq(_T_4548, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4550 = and(_T_4547, _T_4549) @[lsu_bus_buffer.scala 547:121] + node _T_4551 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4552 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 547:117] + node _T_4553 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 547:133] + node _T_4554 = eq(_T_4553, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4555 = and(_T_4552, _T_4554) @[lsu_bus_buffer.scala 547:121] + node _T_4556 = mux(_T_4536, _T_4540, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4557 = mux(_T_4541, _T_4545, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4558 = mux(_T_4546, _T_4550, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4559 = mux(_T_4551, _T_4555, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4560 = or(_T_4556, _T_4557) @[Mux.scala 27:72] + node _T_4561 = or(_T_4560, _T_4558) @[Mux.scala 27:72] + node _T_4562 = or(_T_4561, _T_4559) @[Mux.scala 27:72] + wire _T_4563 : UInt<1> @[Mux.scala 27:72] + _T_4563 <= _T_4562 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_error <= _T_4563 @[lsu_bus_buffer.scala 547:48] + node _T_4564 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4565 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 548:114] + node _T_4566 = eq(_T_4565, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4567 = and(_T_4564, _T_4566) @[lsu_bus_buffer.scala 548:102] + node _T_4568 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4569 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4570 = or(_T_4568, _T_4569) @[lsu_bus_buffer.scala 548:134] + node _T_4571 = and(_T_4567, _T_4570) @[lsu_bus_buffer.scala 548:118] + node _T_4572 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4573 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 548:114] + node _T_4574 = eq(_T_4573, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4575 = and(_T_4572, _T_4574) @[lsu_bus_buffer.scala 548:102] + node _T_4576 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4577 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4578 = or(_T_4576, _T_4577) @[lsu_bus_buffer.scala 548:134] + node _T_4579 = and(_T_4575, _T_4578) @[lsu_bus_buffer.scala 548:118] + node _T_4580 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4581 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 548:114] + node _T_4582 = eq(_T_4581, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4583 = and(_T_4580, _T_4582) @[lsu_bus_buffer.scala 548:102] + node _T_4584 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4585 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4586 = or(_T_4584, _T_4585) @[lsu_bus_buffer.scala 548:134] + node _T_4587 = and(_T_4583, _T_4586) @[lsu_bus_buffer.scala 548:118] + node _T_4588 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4589 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 548:114] + node _T_4590 = eq(_T_4589, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4591 = and(_T_4588, _T_4590) @[lsu_bus_buffer.scala 548:102] + node _T_4592 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4593 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4594 = or(_T_4592, _T_4593) @[lsu_bus_buffer.scala 548:134] + node _T_4595 = and(_T_4591, _T_4594) @[lsu_bus_buffer.scala 548:118] + node _T_4596 = mux(_T_4571, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4597 = mux(_T_4579, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4598 = mux(_T_4587, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4599 = mux(_T_4595, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4600 = or(_T_4596, _T_4597) @[Mux.scala 27:72] + node _T_4601 = or(_T_4600, _T_4598) @[Mux.scala 27:72] + node _T_4602 = or(_T_4601, _T_4599) @[Mux.scala 27:72] + wire _T_4603 : UInt<2> @[Mux.scala 27:72] + _T_4603 <= _T_4602 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= _T_4603 @[lsu_bus_buffer.scala 548:45] + node _T_4604 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4605 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 549:101] + node _T_4606 = eq(_T_4605, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4607 = and(_T_4604, _T_4606) @[lsu_bus_buffer.scala 549:89] + node _T_4608 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4609 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4610 = or(_T_4608, _T_4609) @[lsu_bus_buffer.scala 549:121] + node _T_4611 = and(_T_4607, _T_4610) @[lsu_bus_buffer.scala 549:105] + node _T_4612 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4613 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 549:101] + node _T_4614 = eq(_T_4613, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4615 = and(_T_4612, _T_4614) @[lsu_bus_buffer.scala 549:89] + node _T_4616 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4617 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4618 = or(_T_4616, _T_4617) @[lsu_bus_buffer.scala 549:121] + node _T_4619 = and(_T_4615, _T_4618) @[lsu_bus_buffer.scala 549:105] + node _T_4620 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4621 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 549:101] + node _T_4622 = eq(_T_4621, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4623 = and(_T_4620, _T_4622) @[lsu_bus_buffer.scala 549:89] + node _T_4624 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4625 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4626 = or(_T_4624, _T_4625) @[lsu_bus_buffer.scala 549:121] + node _T_4627 = and(_T_4623, _T_4626) @[lsu_bus_buffer.scala 549:105] + node _T_4628 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4629 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 549:101] + node _T_4630 = eq(_T_4629, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4631 = and(_T_4628, _T_4630) @[lsu_bus_buffer.scala 549:89] + node _T_4632 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4633 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4634 = or(_T_4632, _T_4633) @[lsu_bus_buffer.scala 549:121] + node _T_4635 = and(_T_4631, _T_4634) @[lsu_bus_buffer.scala 549:105] + node _T_4636 = mux(_T_4611, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4637 = mux(_T_4619, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4638 = mux(_T_4627, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4639 = mux(_T_4635, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4640 = or(_T_4636, _T_4637) @[Mux.scala 27:72] + node _T_4641 = or(_T_4640, _T_4638) @[Mux.scala 27:72] + node _T_4642 = or(_T_4641, _T_4639) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_lo <= _T_4642 @[Mux.scala 27:72] + node _T_4643 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4644 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 550:101] + node _T_4645 = eq(_T_4644, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4646 = and(_T_4643, _T_4645) @[lsu_bus_buffer.scala 550:89] + node _T_4647 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 550:120] + node _T_4648 = and(_T_4646, _T_4647) @[lsu_bus_buffer.scala 550:105] + node _T_4649 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4650 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 550:101] + node _T_4651 = eq(_T_4650, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4652 = and(_T_4649, _T_4651) @[lsu_bus_buffer.scala 550:89] + node _T_4653 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 550:120] + node _T_4654 = and(_T_4652, _T_4653) @[lsu_bus_buffer.scala 550:105] + node _T_4655 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4656 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 550:101] + node _T_4657 = eq(_T_4656, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4658 = and(_T_4655, _T_4657) @[lsu_bus_buffer.scala 550:89] + node _T_4659 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 550:120] + node _T_4660 = and(_T_4658, _T_4659) @[lsu_bus_buffer.scala 550:105] + node _T_4661 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4662 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 550:101] + node _T_4663 = eq(_T_4662, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4664 = and(_T_4661, _T_4663) @[lsu_bus_buffer.scala 550:89] + node _T_4665 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 550:120] + node _T_4666 = and(_T_4664, _T_4665) @[lsu_bus_buffer.scala 550:105] + node _T_4667 = mux(_T_4648, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4668 = mux(_T_4654, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4669 = mux(_T_4660, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4670 = mux(_T_4666, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4671 = or(_T_4667, _T_4668) @[Mux.scala 27:72] + node _T_4672 = or(_T_4671, _T_4669) @[Mux.scala 27:72] + node _T_4673 = or(_T_4672, _T_4670) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_hi <= _T_4673 @[Mux.scala 27:72] + node _T_4674 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_4675 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_4676 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_4677 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_4678 = mux(_T_4674, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4679 = mux(_T_4675, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4680 = mux(_T_4676, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4681 = mux(_T_4677, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4682 = or(_T_4678, _T_4679) @[Mux.scala 27:72] + node _T_4683 = or(_T_4682, _T_4680) @[Mux.scala 27:72] + node _T_4684 = or(_T_4683, _T_4681) @[Mux.scala 27:72] + wire _T_4685 : UInt<32> @[Mux.scala 27:72] + _T_4685 <= _T_4684 @[Mux.scala 27:72] + node lsu_nonblock_addr_offset = bits(_T_4685, 1, 0) @[lsu_bus_buffer.scala 551:96] + node _T_4686 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_4687 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_4688 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_4689 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_4690 = mux(_T_4686, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4691 = mux(_T_4687, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4692 = mux(_T_4688, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4693 = mux(_T_4689, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4694 = or(_T_4690, _T_4691) @[Mux.scala 27:72] + node _T_4695 = or(_T_4694, _T_4692) @[Mux.scala 27:72] + node _T_4696 = or(_T_4695, _T_4693) @[Mux.scala 27:72] + wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] + lsu_nonblock_sz <= _T_4696 @[Mux.scala 27:72] + node _T_4697 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_4698 = bits(buf_unsign, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_4699 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_4700 = bits(buf_unsign, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_4701 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_4702 = bits(buf_unsign, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4703 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4704 = bits(buf_unsign, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4705 = mux(_T_4697, _T_4698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4706 = mux(_T_4699, _T_4700, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4707 = mux(_T_4701, _T_4702, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4708 = mux(_T_4703, _T_4704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4709 = or(_T_4705, _T_4706) @[Mux.scala 27:72] + node _T_4710 = or(_T_4709, _T_4707) @[Mux.scala 27:72] + node _T_4711 = or(_T_4710, _T_4708) @[Mux.scala 27:72] + wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_unsign <= _T_4711 @[Mux.scala 27:72] + node _T_4712 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] + node _T_4713 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[lsu_bus_buffer.scala 555:121] + node lsu_nonblock_data_unalgn = dshr(_T_4712, _T_4713) @[lsu_bus_buffer.scala 555:92] + node _T_4714 = eq(io.dctl_busbuff.lsu_nonblock_load_data_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 557:82] + node _T_4715 = and(lsu_nonblock_load_data_ready, _T_4714) @[lsu_bus_buffer.scala 557:80] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= _T_4715 @[lsu_bus_buffer.scala 557:48] + node _T_4716 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 558:81] + node _T_4717 = and(lsu_nonblock_unsign, _T_4716) @[lsu_bus_buffer.scala 558:63] + node _T_4718 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 558:131] + node _T_4719 = cat(UInt<24>("h00"), _T_4718) @[Cat.scala 29:58] + node _T_4720 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 559:45] + node _T_4721 = and(lsu_nonblock_unsign, _T_4720) @[lsu_bus_buffer.scala 559:26] + node _T_4722 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 559:95] + node _T_4723 = cat(UInt<16>("h00"), _T_4722) @[Cat.scala 29:58] + node _T_4724 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 560:6] + node _T_4725 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 560:45] + node _T_4726 = and(_T_4724, _T_4725) @[lsu_bus_buffer.scala 560:27] + node _T_4727 = bits(lsu_nonblock_data_unalgn, 7, 7) @[lsu_bus_buffer.scala 560:93] + node _T_4728 = bits(_T_4727, 0, 0) @[Bitwise.scala 72:15] + node _T_4729 = mux(_T_4728, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_4730 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 560:123] + node _T_4731 = cat(_T_4729, _T_4730) @[Cat.scala 29:58] + node _T_4732 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 561:6] + node _T_4733 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 561:45] + node _T_4734 = and(_T_4732, _T_4733) @[lsu_bus_buffer.scala 561:27] + node _T_4735 = bits(lsu_nonblock_data_unalgn, 15, 15) @[lsu_bus_buffer.scala 561:93] + node _T_4736 = bits(_T_4735, 0, 0) @[Bitwise.scala 72:15] + node _T_4737 = mux(_T_4736, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_4738 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 561:124] + node _T_4739 = cat(_T_4737, _T_4738) @[Cat.scala 29:58] + node _T_4740 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[lsu_bus_buffer.scala 562:21] + node _T_4741 = mux(_T_4717, _T_4719, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4742 = mux(_T_4721, _T_4723, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4743 = mux(_T_4726, _T_4731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4744 = mux(_T_4734, _T_4739, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4745 = mux(_T_4740, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4746 = or(_T_4741, _T_4742) @[Mux.scala 27:72] + node _T_4747 = or(_T_4746, _T_4743) @[Mux.scala 27:72] + node _T_4748 = or(_T_4747, _T_4744) @[Mux.scala 27:72] + node _T_4749 = or(_T_4748, _T_4745) @[Mux.scala 27:72] + wire _T_4750 : UInt<64> @[Mux.scala 27:72] + _T_4750 <= _T_4749 @[Mux.scala 27:72] + io.lsu_nonblock_load_data <= _T_4750 @[lsu_bus_buffer.scala 558:29] + node _T_4751 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4752 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 563:89] + node _T_4753 = and(_T_4751, _T_4752) @[lsu_bus_buffer.scala 563:73] + node _T_4754 = and(_T_4753, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4755 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4756 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 563:89] + node _T_4757 = and(_T_4755, _T_4756) @[lsu_bus_buffer.scala 563:73] + node _T_4758 = and(_T_4757, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4759 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4760 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 563:89] + node _T_4761 = and(_T_4759, _T_4760) @[lsu_bus_buffer.scala 563:73] + node _T_4762 = and(_T_4761, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4763 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4764 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 563:89] + node _T_4765 = and(_T_4763, _T_4764) @[lsu_bus_buffer.scala 563:73] + node _T_4766 = and(_T_4765, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4767 = or(_T_4754, _T_4758) @[lsu_bus_buffer.scala 563:153] + node _T_4768 = or(_T_4767, _T_4762) @[lsu_bus_buffer.scala 563:153] + node _T_4769 = or(_T_4768, _T_4766) @[lsu_bus_buffer.scala 563:153] + node _T_4770 = and(obuf_valid, obuf_sideeffect) @[lsu_bus_buffer.scala 563:171] + node _T_4771 = and(_T_4770, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:189] + node _T_4772 = or(_T_4769, _T_4771) @[lsu_bus_buffer.scala 563:157] + bus_sideeffect_pend <= _T_4772 @[lsu_bus_buffer.scala 563:23] + node _T_4773 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4774 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4775 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4776 = eq(_T_4774, _T_4775) @[lsu_bus_buffer.scala 565:37] + node _T_4777 = and(obuf_valid, _T_4776) @[lsu_bus_buffer.scala 565:19] + node _T_4778 = eq(obuf_tag0, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:73] + node _T_4779 = eq(obuf_tag1, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:107] + node _T_4780 = and(obuf_merge, _T_4779) @[lsu_bus_buffer.scala 565:95] + node _T_4781 = or(_T_4778, _T_4780) @[lsu_bus_buffer.scala 565:81] + node _T_4782 = eq(_T_4781, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4783 = and(_T_4777, _T_4782) @[lsu_bus_buffer.scala 565:59] + node _T_4784 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4785 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4786 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4787 = eq(_T_4785, _T_4786) @[lsu_bus_buffer.scala 565:37] + node _T_4788 = and(obuf_valid, _T_4787) @[lsu_bus_buffer.scala 565:19] + node _T_4789 = eq(obuf_tag0, UInt<1>("h01")) @[lsu_bus_buffer.scala 565:73] + node _T_4790 = eq(obuf_tag1, UInt<1>("h01")) @[lsu_bus_buffer.scala 565:107] + node _T_4791 = and(obuf_merge, _T_4790) @[lsu_bus_buffer.scala 565:95] + node _T_4792 = or(_T_4789, _T_4791) @[lsu_bus_buffer.scala 565:81] + node _T_4793 = eq(_T_4792, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4794 = and(_T_4788, _T_4793) @[lsu_bus_buffer.scala 565:59] + node _T_4795 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4796 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4797 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4798 = eq(_T_4796, _T_4797) @[lsu_bus_buffer.scala 565:37] + node _T_4799 = and(obuf_valid, _T_4798) @[lsu_bus_buffer.scala 565:19] + node _T_4800 = eq(obuf_tag0, UInt<2>("h02")) @[lsu_bus_buffer.scala 565:73] + node _T_4801 = eq(obuf_tag1, UInt<2>("h02")) @[lsu_bus_buffer.scala 565:107] + node _T_4802 = and(obuf_merge, _T_4801) @[lsu_bus_buffer.scala 565:95] + node _T_4803 = or(_T_4800, _T_4802) @[lsu_bus_buffer.scala 565:81] + node _T_4804 = eq(_T_4803, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4805 = and(_T_4799, _T_4804) @[lsu_bus_buffer.scala 565:59] + node _T_4806 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4807 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4808 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4809 = eq(_T_4807, _T_4808) @[lsu_bus_buffer.scala 565:37] + node _T_4810 = and(obuf_valid, _T_4809) @[lsu_bus_buffer.scala 565:19] + node _T_4811 = eq(obuf_tag0, UInt<2>("h03")) @[lsu_bus_buffer.scala 565:73] + node _T_4812 = eq(obuf_tag1, UInt<2>("h03")) @[lsu_bus_buffer.scala 565:107] + node _T_4813 = and(obuf_merge, _T_4812) @[lsu_bus_buffer.scala 565:95] + node _T_4814 = or(_T_4811, _T_4813) @[lsu_bus_buffer.scala 565:81] + node _T_4815 = eq(_T_4814, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4816 = and(_T_4810, _T_4815) @[lsu_bus_buffer.scala 565:59] + node _T_4817 = mux(_T_4773, _T_4783, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4818 = mux(_T_4784, _T_4794, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4819 = mux(_T_4795, _T_4805, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4820 = mux(_T_4806, _T_4816, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4821 = or(_T_4817, _T_4818) @[Mux.scala 27:72] + node _T_4822 = or(_T_4821, _T_4819) @[Mux.scala 27:72] + node _T_4823 = or(_T_4822, _T_4820) @[Mux.scala 27:72] + wire _T_4824 : UInt<1> @[Mux.scala 27:72] + _T_4824 <= _T_4823 @[Mux.scala 27:72] + bus_addr_match_pending <= _T_4824 @[lsu_bus_buffer.scala 564:26] + node _T_4825 = or(obuf_cmd_done, obuf_data_done) @[lsu_bus_buffer.scala 567:54] + node _T_4826 = mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 567:75] + node _T_4827 = and(io.lsu_axi.aw.ready, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 567:153] + node _T_4828 = mux(_T_4825, _T_4826, _T_4827) @[lsu_bus_buffer.scala 567:39] + node _T_4829 = mux(obuf_write, _T_4828, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 567:23] + bus_cmd_ready <= _T_4829 @[lsu_bus_buffer.scala 567:17] + node _T_4830 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 568:40] + bus_wcmd_sent <= _T_4830 @[lsu_bus_buffer.scala 568:17] + node _T_4831 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 569:40] + bus_wdata_sent <= _T_4831 @[lsu_bus_buffer.scala 569:18] + node _T_4832 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 570:35] + node _T_4833 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 570:70] + node _T_4834 = and(_T_4832, _T_4833) @[lsu_bus_buffer.scala 570:52] + node _T_4835 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 570:112] + node _T_4836 = or(_T_4834, _T_4835) @[lsu_bus_buffer.scala 570:89] + bus_cmd_sent <= _T_4836 @[lsu_bus_buffer.scala 570:16] + node _T_4837 = and(io.lsu_axi.r.valid, io.lsu_axi.r.ready) @[lsu_bus_buffer.scala 571:38] + bus_rsp_read <= _T_4837 @[lsu_bus_buffer.scala 571:16] + node _T_4838 = and(io.lsu_axi.b.valid, io.lsu_axi.b.ready) @[lsu_bus_buffer.scala 572:39] + bus_rsp_write <= _T_4838 @[lsu_bus_buffer.scala 572:17] + bus_rsp_read_tag <= io.lsu_axi.r.bits.id @[lsu_bus_buffer.scala 573:20] + bus_rsp_write_tag <= io.lsu_axi.b.bits.id @[lsu_bus_buffer.scala 574:21] + node _T_4839 = neq(io.lsu_axi.b.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 575:66] + node _T_4840 = and(bus_rsp_write, _T_4839) @[lsu_bus_buffer.scala 575:40] + bus_rsp_write_error <= _T_4840 @[lsu_bus_buffer.scala 575:23] + node _T_4841 = neq(io.lsu_axi.r.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 576:64] + node _T_4842 = and(bus_rsp_read, _T_4841) @[lsu_bus_buffer.scala 576:38] + bus_rsp_read_error <= _T_4842 @[lsu_bus_buffer.scala 576:22] + bus_rsp_rdata <= io.lsu_axi.r.bits.data @[lsu_bus_buffer.scala 577:17] + node _T_4843 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 580:37] + node _T_4844 = eq(obuf_cmd_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:52] + node _T_4845 = and(_T_4843, _T_4844) @[lsu_bus_buffer.scala 580:50] + node _T_4846 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:69] + node _T_4847 = and(_T_4845, _T_4846) @[lsu_bus_buffer.scala 580:67] + io.lsu_axi.aw.valid <= _T_4847 @[lsu_bus_buffer.scala 580:23] + io.lsu_axi.aw.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 581:25] + node _T_4848 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 582:75] + node _T_4849 = cat(_T_4848, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4850 = mux(obuf_sideeffect, obuf_addr, _T_4849) @[lsu_bus_buffer.scala 582:33] + io.lsu_axi.aw.bits.addr <= _T_4850 @[lsu_bus_buffer.scala 582:27] + node _T_4851 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4852 = mux(obuf_sideeffect, _T_4851, UInt<3>("h03")) @[lsu_bus_buffer.scala 583:33] + io.lsu_axi.aw.bits.size <= _T_4852 @[lsu_bus_buffer.scala 583:27] + io.lsu_axi.aw.bits.prot <= UInt<3>("h01") @[lsu_bus_buffer.scala 584:27] + node _T_4853 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 585:34] + io.lsu_axi.aw.bits.cache <= _T_4853 @[lsu_bus_buffer.scala 585:28] + node _T_4854 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 586:41] + io.lsu_axi.aw.bits.region <= _T_4854 @[lsu_bus_buffer.scala 586:29] + io.lsu_axi.aw.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 587:26] + io.lsu_axi.aw.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 588:28] + io.lsu_axi.aw.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 589:26] + io.lsu_axi.aw.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 590:27] + node _T_4855 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 592:36] + node _T_4856 = eq(obuf_data_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 592:51] + node _T_4857 = and(_T_4855, _T_4856) @[lsu_bus_buffer.scala 592:49] + node _T_4858 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 592:69] + node _T_4859 = and(_T_4857, _T_4858) @[lsu_bus_buffer.scala 592:67] + io.lsu_axi.w.valid <= _T_4859 @[lsu_bus_buffer.scala 592:22] + node _T_4860 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] + node _T_4861 = mux(_T_4860, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_4862 = and(obuf_byteen, _T_4861) @[lsu_bus_buffer.scala 593:41] + io.lsu_axi.w.bits.strb <= _T_4862 @[lsu_bus_buffer.scala 593:26] + io.lsu_axi.w.bits.data <= obuf_data @[lsu_bus_buffer.scala 594:26] + io.lsu_axi.w.bits.last <= UInt<1>("h01") @[lsu_bus_buffer.scala 595:26] + node _T_4863 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:39] + node _T_4864 = and(obuf_valid, _T_4863) @[lsu_bus_buffer.scala 597:37] + node _T_4865 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:53] + node _T_4866 = and(_T_4864, _T_4865) @[lsu_bus_buffer.scala 597:51] + node _T_4867 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:68] + node _T_4868 = and(_T_4866, _T_4867) @[lsu_bus_buffer.scala 597:66] + io.lsu_axi.ar.valid <= _T_4868 @[lsu_bus_buffer.scala 597:23] + io.lsu_axi.ar.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 598:25] + node _T_4869 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 599:75] + node _T_4870 = cat(_T_4869, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4871 = mux(obuf_sideeffect, obuf_addr, _T_4870) @[lsu_bus_buffer.scala 599:33] + io.lsu_axi.ar.bits.addr <= _T_4871 @[lsu_bus_buffer.scala 599:27] + node _T_4872 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4873 = mux(obuf_sideeffect, _T_4872, UInt<3>("h03")) @[lsu_bus_buffer.scala 600:33] + io.lsu_axi.ar.bits.size <= _T_4873 @[lsu_bus_buffer.scala 600:27] + io.lsu_axi.ar.bits.prot <= UInt<3>("h01") @[lsu_bus_buffer.scala 601:27] + node _T_4874 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 602:34] + io.lsu_axi.ar.bits.cache <= _T_4874 @[lsu_bus_buffer.scala 602:28] + node _T_4875 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 603:41] + io.lsu_axi.ar.bits.region <= _T_4875 @[lsu_bus_buffer.scala 603:29] + io.lsu_axi.ar.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 604:26] + io.lsu_axi.ar.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 605:28] + io.lsu_axi.ar.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 606:26] + io.lsu_axi.ar.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 607:27] + io.lsu_axi.b.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 608:22] + io.lsu_axi.r.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 609:22] + node _T_4876 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4877 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 610:137] + node _T_4878 = and(io.lsu_bus_clk_en_q, _T_4877) @[lsu_bus_buffer.scala 610:126] + node _T_4879 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 610:152] + node _T_4880 = and(_T_4878, _T_4879) @[lsu_bus_buffer.scala 610:141] + node _T_4881 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4882 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 610:137] + node _T_4883 = and(io.lsu_bus_clk_en_q, _T_4882) @[lsu_bus_buffer.scala 610:126] + node _T_4884 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 610:152] + node _T_4885 = and(_T_4883, _T_4884) @[lsu_bus_buffer.scala 610:141] + node _T_4886 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4887 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 610:137] + node _T_4888 = and(io.lsu_bus_clk_en_q, _T_4887) @[lsu_bus_buffer.scala 610:126] + node _T_4889 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 610:152] + node _T_4890 = and(_T_4888, _T_4889) @[lsu_bus_buffer.scala 610:141] + node _T_4891 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4892 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 610:137] + node _T_4893 = and(io.lsu_bus_clk_en_q, _T_4892) @[lsu_bus_buffer.scala 610:126] + node _T_4894 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 610:152] + node _T_4895 = and(_T_4893, _T_4894) @[lsu_bus_buffer.scala 610:141] + node _T_4896 = mux(_T_4876, _T_4880, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4897 = mux(_T_4881, _T_4885, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4898 = mux(_T_4886, _T_4890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4899 = mux(_T_4891, _T_4895, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4900 = or(_T_4896, _T_4897) @[Mux.scala 27:72] + node _T_4901 = or(_T_4900, _T_4898) @[Mux.scala 27:72] + node _T_4902 = or(_T_4901, _T_4899) @[Mux.scala 27:72] + wire _T_4903 : UInt<1> @[Mux.scala 27:72] + _T_4903 <= _T_4902 @[Mux.scala 27:72] + io.tlu_busbuff.lsu_imprecise_error_store_any <= _T_4903 @[lsu_bus_buffer.scala 610:48] + node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4905 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 611:104] + node _T_4906 = and(_T_4904, _T_4905) @[lsu_bus_buffer.scala 611:93] + node _T_4907 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 611:119] + node _T_4908 = and(_T_4906, _T_4907) @[lsu_bus_buffer.scala 611:108] + node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4910 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 611:104] + node _T_4911 = and(_T_4909, _T_4910) @[lsu_bus_buffer.scala 611:93] + node _T_4912 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 611:119] + node _T_4913 = and(_T_4911, _T_4912) @[lsu_bus_buffer.scala 611:108] + node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4915 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 611:104] + node _T_4916 = and(_T_4914, _T_4915) @[lsu_bus_buffer.scala 611:93] + node _T_4917 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 611:119] + node _T_4918 = and(_T_4916, _T_4917) @[lsu_bus_buffer.scala 611:108] + node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4920 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 611:104] + node _T_4921 = and(_T_4919, _T_4920) @[lsu_bus_buffer.scala 611:93] + node _T_4922 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 611:119] + node _T_4923 = and(_T_4921, _T_4922) @[lsu_bus_buffer.scala 611:108] + node _T_4924 = mux(_T_4908, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4925 = mux(_T_4913, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4926 = mux(_T_4918, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4927 = mux(_T_4923, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4928 = or(_T_4924, _T_4925) @[Mux.scala 27:72] + node _T_4929 = or(_T_4928, _T_4926) @[Mux.scala 27:72] + node _T_4930 = or(_T_4929, _T_4927) @[Mux.scala 27:72] + wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72] + lsu_imprecise_error_store_tag <= _T_4930 @[Mux.scala 27:72] + node _T_4931 = eq(io.tlu_busbuff.lsu_imprecise_error_store_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 613:97] + node _T_4932 = and(io.dctl_busbuff.lsu_nonblock_load_data_error, _T_4931) @[lsu_bus_buffer.scala 613:95] + io.tlu_busbuff.lsu_imprecise_error_load_any <= _T_4932 @[lsu_bus_buffer.scala 613:47] + node _T_4933 = mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.dctl_busbuff.lsu_nonblock_load_data_tag]) @[lsu_bus_buffer.scala 614:53] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= _T_4933 @[lsu_bus_buffer.scala 614:47] + node _T_4934 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 620:59] + node _T_4935 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 620:104] + node _T_4936 = or(_T_4934, _T_4935) @[lsu_bus_buffer.scala 620:82] + node _T_4937 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 620:149] + node _T_4938 = or(_T_4936, _T_4937) @[lsu_bus_buffer.scala 620:126] + io.tlu_busbuff.lsu_pmu_bus_trxn <= _T_4938 @[lsu_bus_buffer.scala 620:35] + node _T_4939 = and(io.lsu_busreq_r, io.ldst_dual_r) @[lsu_bus_buffer.scala 621:60] + node _T_4940 = and(_T_4939, io.lsu_commit_r) @[lsu_bus_buffer.scala 621:77] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= _T_4940 @[lsu_bus_buffer.scala 621:41] + node _T_4941 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[lsu_bus_buffer.scala 622:83] + io.tlu_busbuff.lsu_pmu_bus_error <= _T_4941 @[lsu_bus_buffer.scala 622:36] + node _T_4942 = eq(io.lsu_axi.aw.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:61] + node _T_4943 = and(io.lsu_axi.aw.valid, _T_4942) @[lsu_bus_buffer.scala 624:59] + node _T_4944 = eq(io.lsu_axi.w.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:107] + node _T_4945 = and(io.lsu_axi.w.valid, _T_4944) @[lsu_bus_buffer.scala 624:105] + node _T_4946 = or(_T_4943, _T_4945) @[lsu_bus_buffer.scala 624:83] + node _T_4947 = eq(io.lsu_axi.ar.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:153] + node _T_4948 = and(io.lsu_axi.ar.valid, _T_4947) @[lsu_bus_buffer.scala 624:151] + node _T_4949 = or(_T_4946, _T_4948) @[lsu_bus_buffer.scala 624:128] + io.tlu_busbuff.lsu_pmu_bus_busy <= _T_4949 @[lsu_bus_buffer.scala 624:35] + reg _T_4950 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 626:49] + _T_4950 <= WrPtr0_m @[lsu_bus_buffer.scala 626:49] + WrPtr0_r <= _T_4950 @[lsu_bus_buffer.scala 626:12] + reg _T_4951 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 627:49] + _T_4951 <= WrPtr1_m @[lsu_bus_buffer.scala 627:49] + WrPtr1_r <= _T_4951 @[lsu_bus_buffer.scala 627:12] + node _T_4952 = eq(io.flush_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 628:75] + node _T_4953 = and(io.lsu_busreq_m, _T_4952) @[lsu_bus_buffer.scala 628:73] + node _T_4954 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 628:89] + node _T_4955 = and(_T_4953, _T_4954) @[lsu_bus_buffer.scala 628:87] + reg _T_4956 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 628:56] + _T_4956 <= _T_4955 @[lsu_bus_buffer.scala 628:56] + io.lsu_busreq_r <= _T_4956 @[lsu_bus_buffer.scala 628:19] + reg _T_4957 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 629:66] + _T_4957 <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_buffer.scala 629:66] + lsu_nonblock_load_valid_r <= _T_4957 @[lsu_bus_buffer.scala 629:29] + + module lsu_bus_intf : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip clk_override : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip active_clk : Clock, flip lsu_busm_clk : Clock, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, bus_read_data_m : UInt<32>, lsu_nonblock_load_data : UInt<32>, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, flip lsu_bus_clk_en : UInt<1>} + + wire lsu_bus_clk_en_q : UInt<1> + lsu_bus_clk_en_q <= UInt<1>("h00") + wire ldst_byteen_m : UInt<4> + ldst_byteen_m <= UInt<1>("h00") + wire ldst_byteen_r : UInt<4> + ldst_byteen_r <= UInt<1>("h00") + wire ldst_byteen_ext_m : UInt<8> + ldst_byteen_ext_m <= UInt<1>("h00") + wire ldst_byteen_ext_r : UInt<8> + ldst_byteen_ext_r <= UInt<1>("h00") + wire ldst_byteen_hi_m : UInt<4> + ldst_byteen_hi_m <= UInt<1>("h00") + wire ldst_byteen_hi_r : UInt<4> + ldst_byteen_hi_r <= UInt<1>("h00") + wire ldst_byteen_lo_m : UInt<4> + ldst_byteen_lo_m <= UInt<1>("h00") + wire ldst_byteen_lo_r : UInt<4> + ldst_byteen_lo_r <= UInt<1>("h00") + wire is_sideeffects_r : UInt<1> + is_sideeffects_r <= UInt<1>("h00") + wire store_data_ext_r : UInt<64> + store_data_ext_r <= UInt<1>("h00") + wire store_data_hi_r : UInt<32> + store_data_hi_r <= UInt<1>("h00") + wire store_data_lo_r : UInt<32> + store_data_lo_r <= UInt<1>("h00") + wire addr_match_dw_lo_r_m : UInt<1> + addr_match_dw_lo_r_m <= UInt<1>("h00") + wire addr_match_word_lo_r_m : UInt<1> + addr_match_word_lo_r_m <= UInt<1>("h00") + wire no_word_merge_r : UInt<1> + no_word_merge_r <= UInt<1>("h00") + wire no_dword_merge_r : UInt<1> + no_dword_merge_r <= UInt<1>("h00") + wire ld_addr_rhit_lo_lo : UInt<1> + ld_addr_rhit_lo_lo <= UInt<1>("h00") + wire ld_addr_rhit_hi_lo : UInt<1> + ld_addr_rhit_hi_lo <= UInt<1>("h00") + wire ld_addr_rhit_lo_hi : UInt<1> + ld_addr_rhit_lo_hi <= UInt<1>("h00") + wire ld_addr_rhit_hi_hi : UInt<1> + ld_addr_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_rhit_lo_lo : UInt<4> + ld_byte_rhit_lo_lo <= UInt<1>("h00") + wire ld_byte_rhit_hi_lo : UInt<4> + ld_byte_rhit_hi_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo_hi : UInt<4> + ld_byte_rhit_lo_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi_hi : UInt<4> + ld_byte_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_hit_lo : UInt<4> + ld_byte_hit_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo : UInt<4> + ld_byte_rhit_lo <= UInt<1>("h00") + wire ld_byte_hit_hi : UInt<4> + ld_byte_hit_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi : UInt<4> + ld_byte_rhit_hi <= UInt<1>("h00") + wire ld_fwddata_rpipe_lo : UInt<32> + ld_fwddata_rpipe_lo <= UInt<1>("h00") + wire ld_fwddata_rpipe_hi : UInt<32> + ld_fwddata_rpipe_hi <= UInt<1>("h00") + wire ld_byte_hit_buf_lo : UInt<4> + ld_byte_hit_buf_lo <= UInt<1>("h00") + wire ld_byte_hit_buf_hi : UInt<4> + ld_byte_hit_buf_hi <= UInt<1>("h00") + wire ld_fwddata_buf_lo : UInt<32> + ld_fwddata_buf_lo <= UInt<1>("h00") + wire ld_fwddata_buf_hi : UInt<32> + ld_fwddata_buf_hi <= UInt<1>("h00") + wire ld_fwddata_lo : UInt<64> + ld_fwddata_lo <= UInt<1>("h00") + wire ld_fwddata_hi : UInt<64> + ld_fwddata_hi <= UInt<1>("h00") + wire ld_fwddata_m : UInt<64> + ld_fwddata_m <= UInt<1>("h00") + wire ld_full_hit_hi_m : UInt<1> + ld_full_hit_hi_m <= UInt<1>("h01") + wire ld_full_hit_lo_m : UInt<1> + ld_full_hit_lo_m <= UInt<1>("h01") + wire ld_full_hit_m : UInt<1> + ld_full_hit_m <= UInt<1>("h00") + inst bus_buffer of lsu_bus_buffer @[lsu_bus_intf.scala 100:39] + bus_buffer.clock <= clock + bus_buffer.reset <= reset + bus_buffer.io.scan_mode <= io.scan_mode @[lsu_bus_intf.scala 102:29] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_store_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_load_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_busy <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_error <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_error @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_trxn <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu_bus_intf.scala 103:18] + bus_buffer.io.clk_override <= io.clk_override @[lsu_bus_intf.scala 104:51] + bus_buffer.io.lsu_bus_obuf_c1_clken <= io.lsu_bus_obuf_c1_clken @[lsu_bus_intf.scala 105:51] + bus_buffer.io.lsu_busm_clken <= io.lsu_busm_clken @[lsu_bus_intf.scala 106:51] + bus_buffer.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu_bus_intf.scala 107:51] + bus_buffer.io.lsu_c2_r_clk <= io.lsu_c2_r_clk @[lsu_bus_intf.scala 108:51] + bus_buffer.io.lsu_bus_ibuf_c1_clk <= io.lsu_bus_ibuf_c1_clk @[lsu_bus_intf.scala 109:51] + bus_buffer.io.lsu_bus_obuf_c1_clk <= io.lsu_bus_obuf_c1_clk @[lsu_bus_intf.scala 110:51] + bus_buffer.io.lsu_bus_buf_c1_clk <= io.lsu_bus_buf_c1_clk @[lsu_bus_intf.scala 111:51] + bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[lsu_bus_intf.scala 112:51] + bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[lsu_bus_intf.scala 113:51] + bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu_bus_intf.scala 114:51] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.store <= io.lsu_pkt_m.bits.store @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.load <= io.lsu_pkt_m.bits.load @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.word <= io.lsu_pkt_m.bits.word @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.half <= io.lsu_pkt_m.bits.half @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.by <= io.lsu_pkt_m.bits.by @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_m <= io.lsu_pkt_r.bits.store_data_bypass_m @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.load_ldst_bypass_d <= io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_d <= io.lsu_pkt_r.bits.store_data_bypass_d @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.dma <= io.lsu_pkt_r.bits.dma @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.unsign <= io.lsu_pkt_r.bits.unsign @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.store <= io.lsu_pkt_r.bits.store @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.load <= io.lsu_pkt_r.bits.load @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.dword <= io.lsu_pkt_r.bits.dword @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.word <= io.lsu_pkt_r.bits.word @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.half <= io.lsu_pkt_r.bits.half @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.by <= io.lsu_pkt_r.bits.by @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.stack <= io.lsu_pkt_r.bits.stack @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.fast_int <= io.lsu_pkt_r.bits.fast_int @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[lsu_bus_intf.scala 121:51] + bus_buffer.io.end_addr_m <= io.end_addr_m @[lsu_bus_intf.scala 122:51] + bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[lsu_bus_intf.scala 123:51] + bus_buffer.io.end_addr_r <= io.end_addr_r @[lsu_bus_intf.scala 124:51] + bus_buffer.io.store_data_r <= io.store_data_r @[lsu_bus_intf.scala 125:51] + bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[lsu_bus_intf.scala 127:51] + bus_buffer.io.flush_m_up <= io.flush_m_up @[lsu_bus_intf.scala 128:51] + bus_buffer.io.flush_r <= io.flush_r @[lsu_bus_intf.scala 129:51] + bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[lsu_bus_intf.scala 130:51] + bus_buffer.io.lsu_axi.r.bits.last <= io.axi.r.bits.last @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.resp <= io.axi.r.bits.resp @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.data <= io.axi.r.bits.data @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.id <= io.axi.r.bits.id @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.valid <= io.axi.r.valid @[lsu_bus_intf.scala 131:51] + io.axi.r.ready <= bus_buffer.io.lsu_axi.r.ready @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.qos <= bus_buffer.io.lsu_axi.ar.bits.qos @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.prot <= bus_buffer.io.lsu_axi.ar.bits.prot @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.cache <= bus_buffer.io.lsu_axi.ar.bits.cache @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.lock <= bus_buffer.io.lsu_axi.ar.bits.lock @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.burst <= bus_buffer.io.lsu_axi.ar.bits.burst @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.size <= bus_buffer.io.lsu_axi.ar.bits.size @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.len <= bus_buffer.io.lsu_axi.ar.bits.len @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.region <= bus_buffer.io.lsu_axi.ar.bits.region @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.addr <= bus_buffer.io.lsu_axi.ar.bits.addr @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.id <= bus_buffer.io.lsu_axi.ar.bits.id @[lsu_bus_intf.scala 131:51] + io.axi.ar.valid <= bus_buffer.io.lsu_axi.ar.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.ar.ready <= io.axi.ar.ready @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.bits.id <= io.axi.b.bits.id @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.bits.resp <= io.axi.b.bits.resp @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.valid <= io.axi.b.valid @[lsu_bus_intf.scala 131:51] + io.axi.b.ready <= bus_buffer.io.lsu_axi.b.ready @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.last <= bus_buffer.io.lsu_axi.w.bits.last @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.strb <= bus_buffer.io.lsu_axi.w.bits.strb @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.data <= bus_buffer.io.lsu_axi.w.bits.data @[lsu_bus_intf.scala 131:51] + io.axi.w.valid <= bus_buffer.io.lsu_axi.w.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.w.ready <= io.axi.w.ready @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.qos <= bus_buffer.io.lsu_axi.aw.bits.qos @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.prot <= bus_buffer.io.lsu_axi.aw.bits.prot @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.cache <= bus_buffer.io.lsu_axi.aw.bits.cache @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.lock <= bus_buffer.io.lsu_axi.aw.bits.lock @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.burst <= bus_buffer.io.lsu_axi.aw.bits.burst @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.size <= bus_buffer.io.lsu_axi.aw.bits.size @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.len <= bus_buffer.io.lsu_axi.aw.bits.len @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.region <= bus_buffer.io.lsu_axi.aw.bits.region @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.addr <= bus_buffer.io.lsu_axi.aw.bits.addr @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.id <= bus_buffer.io.lsu_axi.aw.bits.id @[lsu_bus_intf.scala 131:51] + io.axi.aw.valid <= bus_buffer.io.lsu_axi.aw.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.aw.ready <= io.axi.aw.ready @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 132:51] + io.lsu_nonblock_load_data <= bus_buffer.io.lsu_nonblock_load_data @[lsu_bus_intf.scala 133:29] + io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[lsu_bus_intf.scala 134:38] + io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[lsu_bus_intf.scala 135:38] + io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[lsu_bus_intf.scala 136:38] + io.lsu_bus_buffer_empty_any <= bus_buffer.io.lsu_bus_buffer_empty_any @[lsu_bus_intf.scala 137:38] + ld_byte_hit_buf_lo <= bus_buffer.io.ld_byte_hit_buf_lo @[lsu_bus_intf.scala 139:38] + ld_byte_hit_buf_hi <= bus_buffer.io.ld_byte_hit_buf_hi @[lsu_bus_intf.scala 140:38] + ld_fwddata_buf_lo <= bus_buffer.io.ld_fwddata_buf_lo @[lsu_bus_intf.scala 141:38] + ld_fwddata_buf_hi <= bus_buffer.io.ld_fwddata_buf_hi @[lsu_bus_intf.scala 142:38] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_data_error <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_intf.scala 143:19] + bus_buffer.io.no_word_merge_r <= no_word_merge_r @[lsu_bus_intf.scala 144:51] + bus_buffer.io.no_dword_merge_r <= no_dword_merge_r @[lsu_bus_intf.scala 145:51] + bus_buffer.io.is_sideeffects_r <= is_sideeffects_r @[lsu_bus_intf.scala 146:51] + bus_buffer.io.ldst_dual_d <= io.ldst_dual_d @[lsu_bus_intf.scala 147:51] + bus_buffer.io.ldst_dual_m <= io.ldst_dual_m @[lsu_bus_intf.scala 148:51] + bus_buffer.io.ldst_dual_r <= io.ldst_dual_r @[lsu_bus_intf.scala 149:51] + bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[lsu_bus_intf.scala 150:51] + bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[lsu_bus_intf.scala 151:51] + bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[lsu_bus_intf.scala 152:51] + node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[lsu_bus_intf.scala 154:63] + node _T_1 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[lsu_bus_intf.scala 154:107] + node _T_2 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[lsu_bus_intf.scala 154:148] + node _T_3 = mux(_T, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4 = mux(_T_1, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_2, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = or(_T_3, _T_4) @[Mux.scala 27:72] + node _T_7 = or(_T_6, _T_5) @[Mux.scala 27:72] + wire _T_8 : UInt<4> @[Mux.scala 27:72] + _T_8 <= _T_7 @[Mux.scala 27:72] + ldst_byteen_m <= _T_8 @[lsu_bus_intf.scala 154:27] + node _T_9 = bits(io.lsu_addr_r, 31, 3) @[lsu_bus_intf.scala 155:44] + node _T_10 = bits(io.lsu_addr_m, 31, 3) @[lsu_bus_intf.scala 155:68] + node _T_11 = eq(_T_9, _T_10) @[lsu_bus_intf.scala 155:51] + addr_match_dw_lo_r_m <= _T_11 @[lsu_bus_intf.scala 155:27] + node _T_12 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_intf.scala 156:68] + node _T_13 = bits(io.lsu_addr_m, 2, 2) @[lsu_bus_intf.scala 156:85] + node _T_14 = xor(_T_12, _T_13) @[lsu_bus_intf.scala 156:71] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[lsu_bus_intf.scala 156:53] + node _T_16 = and(addr_match_dw_lo_r_m, _T_15) @[lsu_bus_intf.scala 156:51] + addr_match_word_lo_r_m <= _T_16 @[lsu_bus_intf.scala 156:27] + node _T_17 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 157:48] + node _T_18 = and(io.lsu_busreq_r, _T_17) @[lsu_bus_intf.scala 157:46] + node _T_19 = and(_T_18, io.lsu_busreq_m) @[lsu_bus_intf.scala 157:64] + node _T_20 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 157:110] + node _T_21 = or(io.lsu_pkt_m.bits.load, _T_20) @[lsu_bus_intf.scala 157:108] + node _T_22 = and(_T_19, _T_21) @[lsu_bus_intf.scala 157:82] + no_word_merge_r <= _T_22 @[lsu_bus_intf.scala 157:27] + node _T_23 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 158:48] + node _T_24 = and(io.lsu_busreq_r, _T_23) @[lsu_bus_intf.scala 158:46] + node _T_25 = and(_T_24, io.lsu_busreq_m) @[lsu_bus_intf.scala 158:64] + node _T_26 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 158:110] + node _T_27 = or(io.lsu_pkt_m.bits.load, _T_26) @[lsu_bus_intf.scala 158:108] + node _T_28 = and(_T_25, _T_27) @[lsu_bus_intf.scala 158:82] + no_dword_merge_r <= _T_28 @[lsu_bus_intf.scala 158:27] + node _T_29 = bits(ldst_byteen_m, 3, 0) @[lsu_bus_intf.scala 160:43] + node _T_30 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 160:65] + node _T_31 = dshl(_T_29, _T_30) @[lsu_bus_intf.scala 160:49] + ldst_byteen_ext_m <= _T_31 @[lsu_bus_intf.scala 160:27] + node _T_32 = bits(ldst_byteen_r, 3, 0) @[lsu_bus_intf.scala 161:43] + node _T_33 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 161:65] + node _T_34 = dshl(_T_32, _T_33) @[lsu_bus_intf.scala 161:49] + ldst_byteen_ext_r <= _T_34 @[lsu_bus_intf.scala 161:27] + node _T_35 = bits(io.store_data_r, 31, 0) @[lsu_bus_intf.scala 162:45] + node _T_36 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 162:72] + node _T_37 = cat(_T_36, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_38 = dshl(_T_35, _T_37) @[lsu_bus_intf.scala 162:52] + store_data_ext_r <= _T_38 @[lsu_bus_intf.scala 162:27] + node _T_39 = bits(ldst_byteen_ext_m, 7, 4) @[lsu_bus_intf.scala 163:47] + ldst_byteen_hi_m <= _T_39 @[lsu_bus_intf.scala 163:27] + node _T_40 = bits(ldst_byteen_ext_m, 3, 0) @[lsu_bus_intf.scala 164:47] + ldst_byteen_lo_m <= _T_40 @[lsu_bus_intf.scala 164:27] + node _T_41 = bits(ldst_byteen_ext_r, 7, 4) @[lsu_bus_intf.scala 165:47] + ldst_byteen_hi_r <= _T_41 @[lsu_bus_intf.scala 165:27] + node _T_42 = bits(ldst_byteen_ext_r, 3, 0) @[lsu_bus_intf.scala 166:47] + ldst_byteen_lo_r <= _T_42 @[lsu_bus_intf.scala 166:27] + node _T_43 = bits(store_data_ext_r, 63, 32) @[lsu_bus_intf.scala 168:46] + store_data_hi_r <= _T_43 @[lsu_bus_intf.scala 168:27] + node _T_44 = bits(store_data_ext_r, 31, 0) @[lsu_bus_intf.scala 169:46] + store_data_lo_r <= _T_44 @[lsu_bus_intf.scala 169:27] + node _T_45 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 170:44] + node _T_46 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 170:68] + node _T_47 = eq(_T_45, _T_46) @[lsu_bus_intf.scala 170:51] + node _T_48 = and(_T_47, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 170:76] + node _T_49 = and(_T_48, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 170:97] + node _T_50 = and(_T_49, io.lsu_busreq_m) @[lsu_bus_intf.scala 170:123] + ld_addr_rhit_lo_lo <= _T_50 @[lsu_bus_intf.scala 170:27] + node _T_51 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 171:44] + node _T_52 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 171:68] + node _T_53 = eq(_T_51, _T_52) @[lsu_bus_intf.scala 171:51] + node _T_54 = and(_T_53, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 171:76] + node _T_55 = and(_T_54, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 171:97] + node _T_56 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_intf.scala 171:123] + ld_addr_rhit_lo_hi <= _T_56 @[lsu_bus_intf.scala 171:27] + node _T_57 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 172:44] + node _T_58 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 172:68] + node _T_59 = eq(_T_57, _T_58) @[lsu_bus_intf.scala 172:51] + node _T_60 = and(_T_59, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 172:76] + node _T_61 = and(_T_60, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 172:97] + node _T_62 = and(_T_61, io.lsu_busreq_m) @[lsu_bus_intf.scala 172:123] + ld_addr_rhit_hi_lo <= _T_62 @[lsu_bus_intf.scala 172:27] + node _T_63 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 173:44] + node _T_64 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 173:68] + node _T_65 = eq(_T_63, _T_64) @[lsu_bus_intf.scala 173:51] + node _T_66 = and(_T_65, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 173:76] + node _T_67 = and(_T_66, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 173:97] + node _T_68 = and(_T_67, io.lsu_busreq_m) @[lsu_bus_intf.scala 173:123] + ld_addr_rhit_hi_hi <= _T_68 @[lsu_bus_intf.scala 173:27] + node _T_69 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 175:88] + node _T_70 = and(ld_addr_rhit_lo_lo, _T_69) @[lsu_bus_intf.scala 175:70] + node _T_71 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 175:110] + node _T_72 = and(_T_70, _T_71) @[lsu_bus_intf.scala 175:92] + node _T_73 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 175:88] + node _T_74 = and(ld_addr_rhit_lo_lo, _T_73) @[lsu_bus_intf.scala 175:70] + node _T_75 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 175:110] + node _T_76 = and(_T_74, _T_75) @[lsu_bus_intf.scala 175:92] + node _T_77 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 175:88] + node _T_78 = and(ld_addr_rhit_lo_lo, _T_77) @[lsu_bus_intf.scala 175:70] + node _T_79 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 175:110] + node _T_80 = and(_T_78, _T_79) @[lsu_bus_intf.scala 175:92] + node _T_81 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 175:88] + node _T_82 = and(ld_addr_rhit_lo_lo, _T_81) @[lsu_bus_intf.scala 175:70] + node _T_83 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 175:110] + node _T_84 = and(_T_82, _T_83) @[lsu_bus_intf.scala 175:92] + node _T_85 = cat(_T_84, _T_80) @[Cat.scala 29:58] + node _T_86 = cat(_T_85, _T_76) @[Cat.scala 29:58] + node _T_87 = cat(_T_86, _T_72) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_87 @[lsu_bus_intf.scala 175:27] + node _T_88 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 176:88] + node _T_89 = and(ld_addr_rhit_lo_hi, _T_88) @[lsu_bus_intf.scala 176:70] + node _T_90 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 176:110] + node _T_91 = and(_T_89, _T_90) @[lsu_bus_intf.scala 176:92] + node _T_92 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 176:88] + node _T_93 = and(ld_addr_rhit_lo_hi, _T_92) @[lsu_bus_intf.scala 176:70] + node _T_94 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 176:110] + node _T_95 = and(_T_93, _T_94) @[lsu_bus_intf.scala 176:92] + node _T_96 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 176:88] + node _T_97 = and(ld_addr_rhit_lo_hi, _T_96) @[lsu_bus_intf.scala 176:70] + node _T_98 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 176:110] + node _T_99 = and(_T_97, _T_98) @[lsu_bus_intf.scala 176:92] + node _T_100 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 176:88] + node _T_101 = and(ld_addr_rhit_lo_hi, _T_100) @[lsu_bus_intf.scala 176:70] + node _T_102 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 176:110] + node _T_103 = and(_T_101, _T_102) @[lsu_bus_intf.scala 176:92] + node _T_104 = cat(_T_103, _T_99) @[Cat.scala 29:58] + node _T_105 = cat(_T_104, _T_95) @[Cat.scala 29:58] + node _T_106 = cat(_T_105, _T_91) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_106 @[lsu_bus_intf.scala 176:27] + node _T_107 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 177:88] + node _T_108 = and(ld_addr_rhit_hi_lo, _T_107) @[lsu_bus_intf.scala 177:70] + node _T_109 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 177:110] + node _T_110 = and(_T_108, _T_109) @[lsu_bus_intf.scala 177:92] + node _T_111 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 177:88] + node _T_112 = and(ld_addr_rhit_hi_lo, _T_111) @[lsu_bus_intf.scala 177:70] + node _T_113 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 177:110] + node _T_114 = and(_T_112, _T_113) @[lsu_bus_intf.scala 177:92] + node _T_115 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 177:88] + node _T_116 = and(ld_addr_rhit_hi_lo, _T_115) @[lsu_bus_intf.scala 177:70] + node _T_117 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 177:110] + node _T_118 = and(_T_116, _T_117) @[lsu_bus_intf.scala 177:92] + node _T_119 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 177:88] + node _T_120 = and(ld_addr_rhit_hi_lo, _T_119) @[lsu_bus_intf.scala 177:70] + node _T_121 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 177:110] + node _T_122 = and(_T_120, _T_121) @[lsu_bus_intf.scala 177:92] + node _T_123 = cat(_T_122, _T_118) @[Cat.scala 29:58] + node _T_124 = cat(_T_123, _T_114) @[Cat.scala 29:58] + node _T_125 = cat(_T_124, _T_110) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_125 @[lsu_bus_intf.scala 177:27] + node _T_126 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 178:88] + node _T_127 = and(ld_addr_rhit_hi_hi, _T_126) @[lsu_bus_intf.scala 178:70] + node _T_128 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 178:110] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_intf.scala 178:92] + node _T_130 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 178:88] + node _T_131 = and(ld_addr_rhit_hi_hi, _T_130) @[lsu_bus_intf.scala 178:70] + node _T_132 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 178:110] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_intf.scala 178:92] + node _T_134 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 178:88] + node _T_135 = and(ld_addr_rhit_hi_hi, _T_134) @[lsu_bus_intf.scala 178:70] + node _T_136 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 178:110] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_intf.scala 178:92] + node _T_138 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 178:88] + node _T_139 = and(ld_addr_rhit_hi_hi, _T_138) @[lsu_bus_intf.scala 178:70] + node _T_140 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 178:110] + node _T_141 = and(_T_139, _T_140) @[lsu_bus_intf.scala 178:92] + node _T_142 = cat(_T_141, _T_137) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_133) @[Cat.scala 29:58] + node _T_144 = cat(_T_143, _T_129) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_144 @[lsu_bus_intf.scala 178:27] + node _T_145 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 180:69] + node _T_146 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 180:93] + node _T_147 = or(_T_145, _T_146) @[lsu_bus_intf.scala 180:73] + node _T_148 = bits(ld_byte_hit_buf_lo, 0, 0) @[lsu_bus_intf.scala 180:117] + node _T_149 = or(_T_147, _T_148) @[lsu_bus_intf.scala 180:97] + node _T_150 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 180:69] + node _T_151 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 180:93] + node _T_152 = or(_T_150, _T_151) @[lsu_bus_intf.scala 180:73] + node _T_153 = bits(ld_byte_hit_buf_lo, 1, 1) @[lsu_bus_intf.scala 180:117] + node _T_154 = or(_T_152, _T_153) @[lsu_bus_intf.scala 180:97] + node _T_155 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 180:69] + node _T_156 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 180:93] + node _T_157 = or(_T_155, _T_156) @[lsu_bus_intf.scala 180:73] + node _T_158 = bits(ld_byte_hit_buf_lo, 2, 2) @[lsu_bus_intf.scala 180:117] + node _T_159 = or(_T_157, _T_158) @[lsu_bus_intf.scala 180:97] + node _T_160 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 180:69] + node _T_161 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 180:93] + node _T_162 = or(_T_160, _T_161) @[lsu_bus_intf.scala 180:73] + node _T_163 = bits(ld_byte_hit_buf_lo, 3, 3) @[lsu_bus_intf.scala 180:117] + node _T_164 = or(_T_162, _T_163) @[lsu_bus_intf.scala 180:97] + node _T_165 = cat(_T_164, _T_159) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, _T_154) @[Cat.scala 29:58] + node _T_167 = cat(_T_166, _T_149) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_167 @[lsu_bus_intf.scala 180:27] + node _T_168 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 181:69] + node _T_169 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 181:93] + node _T_170 = or(_T_168, _T_169) @[lsu_bus_intf.scala 181:73] + node _T_171 = bits(ld_byte_hit_buf_hi, 0, 0) @[lsu_bus_intf.scala 181:117] + node _T_172 = or(_T_170, _T_171) @[lsu_bus_intf.scala 181:97] + node _T_173 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 181:69] + node _T_174 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 181:93] + node _T_175 = or(_T_173, _T_174) @[lsu_bus_intf.scala 181:73] + node _T_176 = bits(ld_byte_hit_buf_hi, 1, 1) @[lsu_bus_intf.scala 181:117] + node _T_177 = or(_T_175, _T_176) @[lsu_bus_intf.scala 181:97] + node _T_178 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 181:69] + node _T_179 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 181:93] + node _T_180 = or(_T_178, _T_179) @[lsu_bus_intf.scala 181:73] + node _T_181 = bits(ld_byte_hit_buf_hi, 2, 2) @[lsu_bus_intf.scala 181:117] + node _T_182 = or(_T_180, _T_181) @[lsu_bus_intf.scala 181:97] + node _T_183 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 181:69] + node _T_184 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 181:93] + node _T_185 = or(_T_183, _T_184) @[lsu_bus_intf.scala 181:73] + node _T_186 = bits(ld_byte_hit_buf_hi, 3, 3) @[lsu_bus_intf.scala 181:117] + node _T_187 = or(_T_185, _T_186) @[lsu_bus_intf.scala 181:97] + node _T_188 = cat(_T_187, _T_182) @[Cat.scala 29:58] + node _T_189 = cat(_T_188, _T_177) @[Cat.scala 29:58] + node _T_190 = cat(_T_189, _T_172) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_190 @[lsu_bus_intf.scala 181:27] + node _T_191 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 182:69] + node _T_192 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 182:93] + node _T_193 = or(_T_191, _T_192) @[lsu_bus_intf.scala 182:73] + node _T_194 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 182:69] + node _T_195 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 182:93] + node _T_196 = or(_T_194, _T_195) @[lsu_bus_intf.scala 182:73] + node _T_197 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 182:69] + node _T_198 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 182:93] + node _T_199 = or(_T_197, _T_198) @[lsu_bus_intf.scala 182:73] + node _T_200 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 182:69] + node _T_201 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 182:93] + node _T_202 = or(_T_200, _T_201) @[lsu_bus_intf.scala 182:73] + node _T_203 = cat(_T_202, _T_199) @[Cat.scala 29:58] + node _T_204 = cat(_T_203, _T_196) @[Cat.scala 29:58] + node _T_205 = cat(_T_204, _T_193) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_205 @[lsu_bus_intf.scala 182:27] + node _T_206 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 183:69] + node _T_207 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 183:93] + node _T_208 = or(_T_206, _T_207) @[lsu_bus_intf.scala 183:73] + node _T_209 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 183:69] + node _T_210 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 183:93] + node _T_211 = or(_T_209, _T_210) @[lsu_bus_intf.scala 183:73] + node _T_212 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 183:69] + node _T_213 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 183:93] + node _T_214 = or(_T_212, _T_213) @[lsu_bus_intf.scala 183:73] + node _T_215 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 183:69] + node _T_216 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 183:93] + node _T_217 = or(_T_215, _T_216) @[lsu_bus_intf.scala 183:73] + node _T_218 = cat(_T_217, _T_214) @[Cat.scala 29:58] + node _T_219 = cat(_T_218, _T_211) @[Cat.scala 29:58] + node _T_220 = cat(_T_219, _T_208) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_220 @[lsu_bus_intf.scala 183:27] + node _T_221 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 184:79] + node _T_222 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 184:101] + node _T_223 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 184:136] + node _T_224 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 184:158] + node _T_225 = mux(_T_221, _T_222, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_226 = mux(_T_223, _T_224, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_227 = or(_T_225, _T_226) @[Mux.scala 27:72] + wire _T_228 : UInt<8> @[Mux.scala 27:72] + _T_228 <= _T_227 @[Mux.scala 27:72] + node _T_229 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 184:79] + node _T_230 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 184:101] + node _T_231 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 184:136] + node _T_232 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 184:158] + node _T_233 = mux(_T_229, _T_230, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_234 = mux(_T_231, _T_232, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_235 = or(_T_233, _T_234) @[Mux.scala 27:72] + wire _T_236 : UInt<8> @[Mux.scala 27:72] + _T_236 <= _T_235 @[Mux.scala 27:72] + node _T_237 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 184:79] + node _T_238 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 184:101] + node _T_239 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 184:136] + node _T_240 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 184:158] + node _T_241 = mux(_T_237, _T_238, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_242 = mux(_T_239, _T_240, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_243 = or(_T_241, _T_242) @[Mux.scala 27:72] + wire _T_244 : UInt<8> @[Mux.scala 27:72] + _T_244 <= _T_243 @[Mux.scala 27:72] + node _T_245 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 184:79] + node _T_246 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 184:101] + node _T_247 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 184:136] + node _T_248 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 184:158] + node _T_249 = mux(_T_245, _T_246, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_250 = mux(_T_247, _T_248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_251 = or(_T_249, _T_250) @[Mux.scala 27:72] + wire _T_252 : UInt<8> @[Mux.scala 27:72] + _T_252 <= _T_251 @[Mux.scala 27:72] + node _T_253 = cat(_T_252, _T_244) @[Cat.scala 29:58] + node _T_254 = cat(_T_253, _T_236) @[Cat.scala 29:58] + node _T_255 = cat(_T_254, _T_228) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_255 @[lsu_bus_intf.scala 184:27] + node _T_256 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 185:79] + node _T_257 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 185:101] + node _T_258 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 185:136] + node _T_259 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 185:158] + node _T_260 = mux(_T_256, _T_257, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = or(_T_260, _T_261) @[Mux.scala 27:72] + wire _T_263 : UInt<8> @[Mux.scala 27:72] + _T_263 <= _T_262 @[Mux.scala 27:72] + node _T_264 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 185:79] + node _T_265 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 185:101] + node _T_266 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 185:136] + node _T_267 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 185:158] + node _T_268 = mux(_T_264, _T_265, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_269 = mux(_T_266, _T_267, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_270 = or(_T_268, _T_269) @[Mux.scala 27:72] + wire _T_271 : UInt<8> @[Mux.scala 27:72] + _T_271 <= _T_270 @[Mux.scala 27:72] + node _T_272 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 185:79] + node _T_273 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 185:101] + node _T_274 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 185:136] + node _T_275 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 185:158] + node _T_276 = mux(_T_272, _T_273, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_277 = mux(_T_274, _T_275, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_278 = or(_T_276, _T_277) @[Mux.scala 27:72] + wire _T_279 : UInt<8> @[Mux.scala 27:72] + _T_279 <= _T_278 @[Mux.scala 27:72] + node _T_280 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 185:79] + node _T_281 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 185:101] + node _T_282 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 185:136] + node _T_283 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 185:158] + node _T_284 = mux(_T_280, _T_281, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_285 = mux(_T_282, _T_283, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_286 = or(_T_284, _T_285) @[Mux.scala 27:72] + wire _T_287 : UInt<8> @[Mux.scala 27:72] + _T_287 <= _T_286 @[Mux.scala 27:72] + node _T_288 = cat(_T_287, _T_279) @[Cat.scala 29:58] + node _T_289 = cat(_T_288, _T_271) @[Cat.scala 29:58] + node _T_290 = cat(_T_289, _T_263) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_290 @[lsu_bus_intf.scala 185:27] + node _T_291 = bits(ld_byte_rhit_lo, 0, 0) @[lsu_bus_intf.scala 186:70] + node _T_292 = bits(ld_fwddata_rpipe_lo, 7, 0) @[lsu_bus_intf.scala 186:94] + node _T_293 = bits(ld_fwddata_buf_lo, 7, 0) @[lsu_bus_intf.scala 186:128] + node _T_294 = mux(_T_291, _T_292, _T_293) @[lsu_bus_intf.scala 186:54] + node _T_295 = bits(ld_byte_rhit_lo, 1, 1) @[lsu_bus_intf.scala 186:70] + node _T_296 = bits(ld_fwddata_rpipe_lo, 15, 8) @[lsu_bus_intf.scala 186:94] + node _T_297 = bits(ld_fwddata_buf_lo, 15, 8) @[lsu_bus_intf.scala 186:128] + node _T_298 = mux(_T_295, _T_296, _T_297) @[lsu_bus_intf.scala 186:54] + node _T_299 = bits(ld_byte_rhit_lo, 2, 2) @[lsu_bus_intf.scala 186:70] + node _T_300 = bits(ld_fwddata_rpipe_lo, 23, 16) @[lsu_bus_intf.scala 186:94] + node _T_301 = bits(ld_fwddata_buf_lo, 23, 16) @[lsu_bus_intf.scala 186:128] + node _T_302 = mux(_T_299, _T_300, _T_301) @[lsu_bus_intf.scala 186:54] + node _T_303 = bits(ld_byte_rhit_lo, 3, 3) @[lsu_bus_intf.scala 186:70] + node _T_304 = bits(ld_fwddata_rpipe_lo, 31, 24) @[lsu_bus_intf.scala 186:94] + node _T_305 = bits(ld_fwddata_buf_lo, 31, 24) @[lsu_bus_intf.scala 186:128] + node _T_306 = mux(_T_303, _T_304, _T_305) @[lsu_bus_intf.scala 186:54] + node _T_307 = cat(_T_306, _T_302) @[Cat.scala 29:58] + node _T_308 = cat(_T_307, _T_298) @[Cat.scala 29:58] + node _T_309 = cat(_T_308, _T_294) @[Cat.scala 29:58] + ld_fwddata_lo <= _T_309 @[lsu_bus_intf.scala 186:27] + node _T_310 = bits(ld_byte_rhit_hi, 0, 0) @[lsu_bus_intf.scala 187:70] + node _T_311 = bits(ld_fwddata_rpipe_hi, 7, 0) @[lsu_bus_intf.scala 187:94] + node _T_312 = bits(ld_fwddata_buf_hi, 7, 0) @[lsu_bus_intf.scala 187:128] + node _T_313 = mux(_T_310, _T_311, _T_312) @[lsu_bus_intf.scala 187:54] + node _T_314 = bits(ld_byte_rhit_hi, 1, 1) @[lsu_bus_intf.scala 187:70] + node _T_315 = bits(ld_fwddata_rpipe_hi, 15, 8) @[lsu_bus_intf.scala 187:94] + node _T_316 = bits(ld_fwddata_buf_hi, 15, 8) @[lsu_bus_intf.scala 187:128] + node _T_317 = mux(_T_314, _T_315, _T_316) @[lsu_bus_intf.scala 187:54] + node _T_318 = bits(ld_byte_rhit_hi, 2, 2) @[lsu_bus_intf.scala 187:70] + node _T_319 = bits(ld_fwddata_rpipe_hi, 23, 16) @[lsu_bus_intf.scala 187:94] + node _T_320 = bits(ld_fwddata_buf_hi, 23, 16) @[lsu_bus_intf.scala 187:128] + node _T_321 = mux(_T_318, _T_319, _T_320) @[lsu_bus_intf.scala 187:54] + node _T_322 = bits(ld_byte_rhit_hi, 3, 3) @[lsu_bus_intf.scala 187:70] + node _T_323 = bits(ld_fwddata_rpipe_hi, 31, 24) @[lsu_bus_intf.scala 187:94] + node _T_324 = bits(ld_fwddata_buf_hi, 31, 24) @[lsu_bus_intf.scala 187:128] + node _T_325 = mux(_T_322, _T_323, _T_324) @[lsu_bus_intf.scala 187:54] + node _T_326 = cat(_T_325, _T_321) @[Cat.scala 29:58] + node _T_327 = cat(_T_326, _T_317) @[Cat.scala 29:58] + node _T_328 = cat(_T_327, _T_313) @[Cat.scala 29:58] + ld_fwddata_hi <= _T_328 @[lsu_bus_intf.scala 187:27] + node _T_329 = bits(ld_byte_hit_lo, 0, 0) @[lsu_bus_intf.scala 188:66] + node _T_330 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 188:89] + node _T_331 = eq(_T_330, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_332 = or(_T_329, _T_331) @[lsu_bus_intf.scala 188:70] + node _T_333 = bits(ld_byte_hit_lo, 1, 1) @[lsu_bus_intf.scala 188:66] + node _T_334 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 188:89] + node _T_335 = eq(_T_334, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_336 = or(_T_333, _T_335) @[lsu_bus_intf.scala 188:70] + node _T_337 = bits(ld_byte_hit_lo, 2, 2) @[lsu_bus_intf.scala 188:66] + node _T_338 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 188:89] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_340 = or(_T_337, _T_339) @[lsu_bus_intf.scala 188:70] + node _T_341 = bits(ld_byte_hit_lo, 3, 3) @[lsu_bus_intf.scala 188:66] + node _T_342 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 188:89] + node _T_343 = eq(_T_342, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_344 = or(_T_341, _T_343) @[lsu_bus_intf.scala 188:70] + node _T_345 = and(_T_332, _T_336) @[lsu_bus_intf.scala 188:111] + node _T_346 = and(_T_345, _T_340) @[lsu_bus_intf.scala 188:111] + node _T_347 = and(_T_346, _T_344) @[lsu_bus_intf.scala 188:111] + ld_full_hit_lo_m <= _T_347 @[lsu_bus_intf.scala 188:27] + node _T_348 = bits(ld_byte_hit_hi, 0, 0) @[lsu_bus_intf.scala 189:66] + node _T_349 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 189:89] + node _T_350 = eq(_T_349, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_351 = or(_T_348, _T_350) @[lsu_bus_intf.scala 189:70] + node _T_352 = bits(ld_byte_hit_hi, 1, 1) @[lsu_bus_intf.scala 189:66] + node _T_353 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 189:89] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_355 = or(_T_352, _T_354) @[lsu_bus_intf.scala 189:70] + node _T_356 = bits(ld_byte_hit_hi, 2, 2) @[lsu_bus_intf.scala 189:66] + node _T_357 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 189:89] + node _T_358 = eq(_T_357, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_359 = or(_T_356, _T_358) @[lsu_bus_intf.scala 189:70] + node _T_360 = bits(ld_byte_hit_hi, 3, 3) @[lsu_bus_intf.scala 189:66] + node _T_361 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 189:89] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_363 = or(_T_360, _T_362) @[lsu_bus_intf.scala 189:70] + node _T_364 = and(_T_351, _T_355) @[lsu_bus_intf.scala 189:111] + node _T_365 = and(_T_364, _T_359) @[lsu_bus_intf.scala 189:111] + node _T_366 = and(_T_365, _T_363) @[lsu_bus_intf.scala 189:111] + ld_full_hit_hi_m <= _T_366 @[lsu_bus_intf.scala 189:27] + node _T_367 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[lsu_bus_intf.scala 190:47] + node _T_368 = and(_T_367, io.lsu_busreq_m) @[lsu_bus_intf.scala 190:66] + node _T_369 = and(_T_368, io.lsu_pkt_m.bits.load) @[lsu_bus_intf.scala 190:84] + node _T_370 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[lsu_bus_intf.scala 190:111] + node _T_371 = and(_T_369, _T_370) @[lsu_bus_intf.scala 190:109] + ld_full_hit_m <= _T_371 @[lsu_bus_intf.scala 190:27] + node _T_372 = bits(ld_fwddata_hi, 31, 0) @[lsu_bus_intf.scala 191:47] + node _T_373 = bits(ld_fwddata_lo, 31, 0) @[lsu_bus_intf.scala 191:68] + node _T_374 = cat(_T_372, _T_373) @[Cat.scala 29:58] + node _T_375 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 191:97] + node _T_376 = mul(UInt<4>("h08"), _T_375) @[lsu_bus_intf.scala 191:83] + node _T_377 = dshr(_T_374, _T_376) @[lsu_bus_intf.scala 191:76] + ld_fwddata_m <= _T_377 @[lsu_bus_intf.scala 191:27] + node _T_378 = bits(ld_fwddata_m, 31, 0) @[lsu_bus_intf.scala 192:42] + io.bus_read_data_m <= _T_378 @[lsu_bus_intf.scala 192:27] + reg _T_379 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 195:32] + _T_379 <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 195:32] + lsu_bus_clk_en_q <= _T_379 @[lsu_bus_intf.scala 195:22] + reg _T_380 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 199:33] + _T_380 <= io.is_sideeffects_m @[lsu_bus_intf.scala 199:33] + is_sideeffects_r <= _T_380 @[lsu_bus_intf.scala 199:23] + reg _T_381 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<4>("h00"))) @[lsu_bus_intf.scala 200:33] + _T_381 <= ldst_byteen_m @[lsu_bus_intf.scala 200:33] + ldst_byteen_r <= _T_381 @[lsu_bus_intf.scala 200:23] + diff --git a/lsu_bus_intf.v b/lsu_bus_intf.v new file mode 100644 index 00000000..cbeea71a --- /dev/null +++ b/lsu_bus_intf.v @@ -0,0 +1,5244 @@ +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module lsu_bus_buffer( + input clock, + input reset, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + input io_dec_tlu_force_halt, + input io_lsu_bus_obuf_c1_clken, + input io_lsu_busm_clken, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_dec_lsu_valid_raw_d, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input [31:0] io_lsu_addr_m, + input [31:0] io_end_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_r, + input [31:0] io_store_data_r, + input io_no_word_merge_r, + input io_no_dword_merge_r, + input io_lsu_busreq_m, + input io_ld_full_hit_m, + input io_flush_m_up, + input io_flush_r, + input io_lsu_commit_r, + input io_is_sideeffects_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [7:0] io_ldst_byteen_ext_m, + input io_lsu_axi_aw_ready, + output io_lsu_axi_aw_valid, + output [2:0] io_lsu_axi_aw_bits_id, + output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, + output [2:0] io_lsu_axi_aw_bits_size, + output [3:0] io_lsu_axi_aw_bits_cache, + input io_lsu_axi_w_ready, + output io_lsu_axi_w_valid, + output [63:0] io_lsu_axi_w_bits_data, + output [7:0] io_lsu_axi_w_bits_strb, + output io_lsu_axi_b_ready, + input io_lsu_axi_b_valid, + input [1:0] io_lsu_axi_b_bits_resp, + input [2:0] io_lsu_axi_b_bits_id, + input io_lsu_axi_ar_ready, + output io_lsu_axi_ar_valid, + output [2:0] io_lsu_axi_ar_bits_id, + output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, + output [2:0] io_lsu_axi_ar_bits_size, + output [3:0] io_lsu_axi_ar_bits_cache, + output io_lsu_axi_r_ready, + input io_lsu_axi_r_valid, + input [2:0] io_lsu_axi_r_bits_id, + input [63:0] io_lsu_axi_r_bits_data, + input [1:0] io_lsu_axi_r_bits_resp, + input io_lsu_bus_clk_en, + input io_lsu_bus_clk_en_q, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [3:0] io_ld_byte_hit_buf_lo, + output [3:0] io_ld_byte_hit_buf_hi, + output [31:0] io_ld_fwddata_buf_lo, + output [31:0] io_ld_fwddata_buf_hi, + output [31:0] io_lsu_nonblock_load_data +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [63:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; + reg [31:0] _RAND_91; + reg [31:0] _RAND_92; + reg [31:0] _RAND_93; + reg [31:0] _RAND_94; + reg [31:0] _RAND_95; + reg [31:0] _RAND_96; + reg [31:0] _RAND_97; + reg [31:0] _RAND_98; + reg [31:0] _RAND_99; + reg [31:0] _RAND_100; + reg [31:0] _RAND_101; + reg [31:0] _RAND_102; + reg [31:0] _RAND_103; + reg [31:0] _RAND_104; + reg [31:0] _RAND_105; + reg [31:0] _RAND_106; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_11_io_en; // @[lib.scala 404:23] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 77:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 78:46] + reg [31:0] buf_addr_0; // @[Reg.scala 27:20] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 80:74] + reg _T_4355; // @[Reg.scala 27:20] + reg _T_4352; // @[Reg.scala 27:20] + reg _T_4349; // @[Reg.scala 27:20] + reg _T_4346; // @[Reg.scala 27:20] + wire [3:0] buf_write = {_T_4355,_T_4352,_T_4349,_T_4346}; // @[Cat.scala 29:58] + wire _T_4 = _T_2 & buf_write[0]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_0; // @[Reg.scala 27:20] + wire _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_1; // @[Reg.scala 27:20] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_1; // @[Reg.scala 27:20] + wire _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_2; // @[Reg.scala 27:20] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_2; // @[Reg.scala 27:20] + wire _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_3; // @[Reg.scala 27:20] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_3; // @[Reg.scala 27:20] + wire _T_26 = buf_state_3 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_27 = _T_25 & _T_26; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_32 = _T_30 & buf_write[0]; // @[lsu_bus_buffer.scala 81:98] + wire _T_34 = _T_32 & _T_5; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_39 = _T_37 & buf_write[1]; // @[lsu_bus_buffer.scala 81:98] + wire _T_41 = _T_39 & _T_12; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_46 = _T_44 & buf_write[2]; // @[lsu_bus_buffer.scala 81:98] + wire _T_48 = _T_46 & _T_19; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_53 = _T_51 & buf_write[3]; // @[lsu_bus_buffer.scala 81:98] + wire _T_55 = _T_53 & _T_26; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] + reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 513:60] + wire _T_2590 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_4104 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4127 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4131 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] + reg [1:0] _T_1781; // @[Reg.scala 27:20] + wire [2:0] obuf_tag0 = {{1'd0}, _T_1781}; // @[lsu_bus_buffer.scala 356:13] + wire _T_4138 = obuf_tag0 == 3'h3; // @[lsu_bus_buffer.scala 460:48] + reg obuf_merge; // @[Reg.scala 27:20] + reg [1:0] obuf_tag1; // @[Reg.scala 27:20] + wire [2:0] _GEN_376 = {{1'd0}, obuf_tag1}; // @[lsu_bus_buffer.scala 460:104] + wire _T_4139 = _GEN_376 == 3'h3; // @[lsu_bus_buffer.scala 460:104] + wire _T_4140 = obuf_merge & _T_4139; // @[lsu_bus_buffer.scala 460:91] + wire _T_4141 = _T_4138 | _T_4140; // @[lsu_bus_buffer.scala 460:77] + reg obuf_valid; // @[lsu_bus_buffer.scala 349:54] + wire _T_4142 = _T_4141 & obuf_valid; // @[lsu_bus_buffer.scala 460:135] + reg obuf_wr_enQ; // @[Reg.scala 27:20] + wire _T_4143 = _T_4142 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 460:148] + wire _T_4165 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4250 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4268 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4276 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] + wire _GEN_290 = _T_4131 & _T_4143; // @[Conditional.scala 39:67] + wire _GEN_303 = _T_4127 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_303; // @[Conditional.scala 40:58] + wire _T_2591 = _T_2590 & buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 417:103] + wire _T_2592 = ~_T_2591; // @[lsu_bus_buffer.scala 417:78] + wire _T_2593 = buf_ageQ_3[3] & _T_2592; // @[lsu_bus_buffer.scala 417:76] + wire _T_2594 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 417:132] + wire _T_2595 = _T_2593 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2583 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3913 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3936 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3940 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3947 = obuf_tag0 == 3'h2; // @[lsu_bus_buffer.scala 460:48] + wire _T_3948 = _GEN_376 == 3'h2; // @[lsu_bus_buffer.scala 460:104] + wire _T_3949 = obuf_merge & _T_3948; // @[lsu_bus_buffer.scala 460:91] + wire _T_3950 = _T_3947 | _T_3949; // @[lsu_bus_buffer.scala 460:77] + wire _T_3951 = _T_3950 & obuf_valid; // @[lsu_bus_buffer.scala 460:135] + wire _T_3952 = _T_3951 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 460:148] + wire _T_3974 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4059 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4077 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4085 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] + wire _GEN_214 = _T_3940 & _T_3952; // @[Conditional.scala 39:67] + wire _GEN_227 = _T_3936 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_227; // @[Conditional.scala 40:58] + wire _T_2584 = _T_2583 & buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 417:103] + wire _T_2585 = ~_T_2584; // @[lsu_bus_buffer.scala 417:78] + wire _T_2586 = buf_ageQ_3[2] & _T_2585; // @[lsu_bus_buffer.scala 417:76] + wire _T_2588 = _T_2586 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2576 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3722 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3745 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3749 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3756 = obuf_tag0 == 3'h1; // @[lsu_bus_buffer.scala 460:48] + wire _T_3757 = _GEN_376 == 3'h1; // @[lsu_bus_buffer.scala 460:104] + wire _T_3758 = obuf_merge & _T_3757; // @[lsu_bus_buffer.scala 460:91] + wire _T_3759 = _T_3756 | _T_3758; // @[lsu_bus_buffer.scala 460:77] + wire _T_3760 = _T_3759 & obuf_valid; // @[lsu_bus_buffer.scala 460:135] + wire _T_3761 = _T_3760 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 460:148] + wire _T_3783 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3868 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3886 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3894 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] + wire _GEN_138 = _T_3749 & _T_3761; // @[Conditional.scala 39:67] + wire _GEN_151 = _T_3745 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_151; // @[Conditional.scala 40:58] + wire _T_2577 = _T_2576 & buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 417:103] + wire _T_2578 = ~_T_2577; // @[lsu_bus_buffer.scala 417:78] + wire _T_2579 = buf_ageQ_3[1] & _T_2578; // @[lsu_bus_buffer.scala 417:76] + wire _T_2581 = _T_2579 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2569 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3531 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3554 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3558 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3565 = obuf_tag0 == 3'h0; // @[lsu_bus_buffer.scala 460:48] + wire _T_3566 = _GEN_376 == 3'h0; // @[lsu_bus_buffer.scala 460:104] + wire _T_3567 = obuf_merge & _T_3566; // @[lsu_bus_buffer.scala 460:91] + wire _T_3568 = _T_3565 | _T_3567; // @[lsu_bus_buffer.scala 460:77] + wire _T_3569 = _T_3568 & obuf_valid; // @[lsu_bus_buffer.scala 460:135] + wire _T_3570 = _T_3569 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 460:148] + wire _T_3592 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3677 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3695 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3703 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] + wire _GEN_62 = _T_3558 & _T_3570; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_3554 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_75; // @[Conditional.scala 40:58] + wire _T_2570 = _T_2569 & buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 417:103] + wire _T_2571 = ~_T_2570; // @[lsu_bus_buffer.scala 417:78] + wire _T_2572 = buf_ageQ_3[0] & _T_2571; // @[lsu_bus_buffer.scala 417:76] + wire _T_2574 = _T_2572 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_3 = {_T_2595,_T_2588,_T_2581,_T_2574}; // @[Cat.scala 29:58] + wire _T_2694 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2696 = _T_2694 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2688 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2690 = _T_2688 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire _T_2682 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2684 = _T_2682 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_3 = {1'h0,_T_2696,_T_2690,_T_2684}; // @[Cat.scala 29:58] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 150:144] + wire _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 150:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 150:97] + reg [31:0] ibuf_addr; // @[Reg.scala 27:20] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 156:51] + reg ibuf_write; // @[Reg.scala 27:20] + wire _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 156:73] + reg ibuf_valid; // @[lsu_bus_buffer.scala 244:54] + wire _T_514 = _T_513 & ibuf_valid; // @[lsu_bus_buffer.scala 156:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 156:99] + wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[lsu_bus_buffer.scala 161:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 161:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 150:150] + wire _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 513:60] + wire _T_2562 = buf_ageQ_2[3] & _T_2592; // @[lsu_bus_buffer.scala 417:76] + wire _T_2564 = _T_2562 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2555 = buf_ageQ_2[2] & _T_2585; // @[lsu_bus_buffer.scala 417:76] + wire _T_2557 = _T_2555 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2548 = buf_ageQ_2[1] & _T_2578; // @[lsu_bus_buffer.scala 417:76] + wire _T_2550 = _T_2548 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2541 = buf_ageQ_2[0] & _T_2571; // @[lsu_bus_buffer.scala 417:76] + wire _T_2543 = _T_2541 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_2 = {_T_2564,_T_2557,_T_2550,_T_2543}; // @[Cat.scala 29:58] + wire _T_2673 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2675 = _T_2673 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2661 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2663 = _T_2661 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire _T_2655 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2657 = _T_2655 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_2 = {_T_2675,1'h0,_T_2663,_T_2657}; // @[Cat.scala 29:58] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_248 = |_T_247; // @[lsu_bus_buffer.scala 150:144] + wire _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 150:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 150:97] + wire _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 513:60] + wire _T_2531 = buf_ageQ_1[3] & _T_2592; // @[lsu_bus_buffer.scala 417:76] + wire _T_2533 = _T_2531 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2524 = buf_ageQ_1[2] & _T_2585; // @[lsu_bus_buffer.scala 417:76] + wire _T_2526 = _T_2524 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2517 = buf_ageQ_1[1] & _T_2578; // @[lsu_bus_buffer.scala 417:76] + wire _T_2519 = _T_2517 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2510 = buf_ageQ_1[0] & _T_2571; // @[lsu_bus_buffer.scala 417:76] + wire _T_2512 = _T_2510 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_1 = {_T_2533,_T_2526,_T_2519,_T_2512}; // @[Cat.scala 29:58] + wire _T_2646 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2648 = _T_2646 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2640 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2642 = _T_2640 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2628 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2630 = _T_2628 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_1 = {_T_2648,_T_2642,1'h0,_T_2630}; // @[Cat.scala 29:58] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_240 = |_T_239; // @[lsu_bus_buffer.scala 150:144] + wire _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 150:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 150:97] + wire _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 513:60] + wire _T_2500 = buf_ageQ_0[3] & _T_2592; // @[lsu_bus_buffer.scala 417:76] + wire _T_2502 = _T_2500 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2493 = buf_ageQ_0[2] & _T_2585; // @[lsu_bus_buffer.scala 417:76] + wire _T_2495 = _T_2493 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2486 = buf_ageQ_0[1] & _T_2578; // @[lsu_bus_buffer.scala 417:76] + wire _T_2488 = _T_2486 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2479 = buf_ageQ_0[0] & _T_2571; // @[lsu_bus_buffer.scala 417:76] + wire _T_2481 = _T_2479 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_0 = {_T_2502,_T_2495,_T_2488,_T_2481}; // @[Cat.scala 29:58] + wire _T_2619 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2621 = _T_2619 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2613 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2615 = _T_2613 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2607 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2609 = _T_2607 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_0 = {_T_2621,_T_2615,_T_2609,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_232 = |_T_231; // @[lsu_bus_buffer.scala 150:144] + wire _T_233 = ~_T_232; // @[lsu_bus_buffer.scala 150:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[lsu_bus_buffer.scala 150:97] + wire _T_237 = _T_234 & _T_260; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[lsu_bus_buffer.scala 142:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 142:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_291 = |_T_290; // @[lsu_bus_buffer.scala 150:144] + wire _T_292 = ~_T_291; // @[lsu_bus_buffer.scala 150:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[lsu_bus_buffer.scala 150:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 150:150] + wire _T_296 = _T_293 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_283 = |_T_282; // @[lsu_bus_buffer.scala 150:144] + wire _T_284 = ~_T_283; // @[lsu_bus_buffer.scala 150:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[lsu_bus_buffer.scala 150:97] + wire _T_288 = _T_285 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_275 = |_T_274; // @[lsu_bus_buffer.scala 150:144] + wire _T_276 = ~_T_275; // @[lsu_bus_buffer.scala 150:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[lsu_bus_buffer.scala 150:97] + wire _T_280 = _T_277 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_267 = |_T_266; // @[lsu_bus_buffer.scala 150:144] + wire _T_268 = ~_T_267; // @[lsu_bus_buffer.scala 150:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[lsu_bus_buffer.scala 150:97] + wire _T_272 = _T_269 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[lsu_bus_buffer.scala 142:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 142:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_326 = |_T_325; // @[lsu_bus_buffer.scala 150:144] + wire _T_327 = ~_T_326; // @[lsu_bus_buffer.scala 150:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[lsu_bus_buffer.scala 150:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 150:150] + wire _T_331 = _T_328 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_318 = |_T_317; // @[lsu_bus_buffer.scala 150:144] + wire _T_319 = ~_T_318; // @[lsu_bus_buffer.scala 150:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[lsu_bus_buffer.scala 150:97] + wire _T_323 = _T_320 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_310 = |_T_309; // @[lsu_bus_buffer.scala 150:144] + wire _T_311 = ~_T_310; // @[lsu_bus_buffer.scala 150:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[lsu_bus_buffer.scala 150:97] + wire _T_315 = _T_312 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_302 = |_T_301; // @[lsu_bus_buffer.scala 150:144] + wire _T_303 = ~_T_302; // @[lsu_bus_buffer.scala 150:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[lsu_bus_buffer.scala 150:97] + wire _T_307 = _T_304 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[lsu_bus_buffer.scala 142:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 142:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_361 = |_T_360; // @[lsu_bus_buffer.scala 150:144] + wire _T_362 = ~_T_361; // @[lsu_bus_buffer.scala 150:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[lsu_bus_buffer.scala 150:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 150:150] + wire _T_366 = _T_363 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_353 = |_T_352; // @[lsu_bus_buffer.scala 150:144] + wire _T_354 = ~_T_353; // @[lsu_bus_buffer.scala 150:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[lsu_bus_buffer.scala 150:97] + wire _T_358 = _T_355 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_345 = |_T_344; // @[lsu_bus_buffer.scala 150:144] + wire _T_346 = ~_T_345; // @[lsu_bus_buffer.scala 150:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[lsu_bus_buffer.scala 150:97] + wire _T_350 = _T_347 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_337 = |_T_336; // @[lsu_bus_buffer.scala 150:144] + wire _T_338 = ~_T_337; // @[lsu_bus_buffer.scala 150:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[lsu_bus_buffer.scala 150:97] + wire _T_342 = _T_339 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[lsu_bus_buffer.scala 142:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 142:77] + wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_396 = |_T_395; // @[lsu_bus_buffer.scala 151:144] + wire _T_397 = ~_T_396; // @[lsu_bus_buffer.scala 151:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[lsu_bus_buffer.scala 151:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 157:51] + wire _T_518 = _T_517 & ibuf_write; // @[lsu_bus_buffer.scala 157:73] + wire _T_519 = _T_518 & ibuf_valid; // @[lsu_bus_buffer.scala 157:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 157:99] + wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[lsu_bus_buffer.scala 162:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[lsu_bus_buffer.scala 162:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 151:150] + wire _T_401 = _T_398 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_388 = |_T_387; // @[lsu_bus_buffer.scala 151:144] + wire _T_389 = ~_T_388; // @[lsu_bus_buffer.scala 151:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[lsu_bus_buffer.scala 151:97] + wire _T_393 = _T_390 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_380 = |_T_379; // @[lsu_bus_buffer.scala 151:144] + wire _T_381 = ~_T_380; // @[lsu_bus_buffer.scala 151:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[lsu_bus_buffer.scala 151:97] + wire _T_385 = _T_382 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_372 = |_T_371; // @[lsu_bus_buffer.scala 151:144] + wire _T_373 = ~_T_372; // @[lsu_bus_buffer.scala 151:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[lsu_bus_buffer.scala 151:97] + wire _T_377 = _T_374 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[lsu_bus_buffer.scala 143:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 143:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_431 = |_T_430; // @[lsu_bus_buffer.scala 151:144] + wire _T_432 = ~_T_431; // @[lsu_bus_buffer.scala 151:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[lsu_bus_buffer.scala 151:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 151:150] + wire _T_436 = _T_433 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_423 = |_T_422; // @[lsu_bus_buffer.scala 151:144] + wire _T_424 = ~_T_423; // @[lsu_bus_buffer.scala 151:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[lsu_bus_buffer.scala 151:97] + wire _T_428 = _T_425 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_415 = |_T_414; // @[lsu_bus_buffer.scala 151:144] + wire _T_416 = ~_T_415; // @[lsu_bus_buffer.scala 151:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[lsu_bus_buffer.scala 151:97] + wire _T_420 = _T_417 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_407 = |_T_406; // @[lsu_bus_buffer.scala 151:144] + wire _T_408 = ~_T_407; // @[lsu_bus_buffer.scala 151:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[lsu_bus_buffer.scala 151:97] + wire _T_412 = _T_409 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[lsu_bus_buffer.scala 143:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 143:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_466 = |_T_465; // @[lsu_bus_buffer.scala 151:144] + wire _T_467 = ~_T_466; // @[lsu_bus_buffer.scala 151:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[lsu_bus_buffer.scala 151:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 151:150] + wire _T_471 = _T_468 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_458 = |_T_457; // @[lsu_bus_buffer.scala 151:144] + wire _T_459 = ~_T_458; // @[lsu_bus_buffer.scala 151:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[lsu_bus_buffer.scala 151:97] + wire _T_463 = _T_460 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_450 = |_T_449; // @[lsu_bus_buffer.scala 151:144] + wire _T_451 = ~_T_450; // @[lsu_bus_buffer.scala 151:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[lsu_bus_buffer.scala 151:97] + wire _T_455 = _T_452 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_442 = |_T_441; // @[lsu_bus_buffer.scala 151:144] + wire _T_443 = ~_T_442; // @[lsu_bus_buffer.scala 151:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[lsu_bus_buffer.scala 151:97] + wire _T_447 = _T_444 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[lsu_bus_buffer.scala 143:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 143:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_501 = |_T_500; // @[lsu_bus_buffer.scala 151:144] + wire _T_502 = ~_T_501; // @[lsu_bus_buffer.scala 151:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[lsu_bus_buffer.scala 151:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 151:150] + wire _T_506 = _T_503 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_493 = |_T_492; // @[lsu_bus_buffer.scala 151:144] + wire _T_494 = ~_T_493; // @[lsu_bus_buffer.scala 151:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[lsu_bus_buffer.scala 151:97] + wire _T_498 = _T_495 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_485 = |_T_484; // @[lsu_bus_buffer.scala 151:144] + wire _T_486 = ~_T_485; // @[lsu_bus_buffer.scala 151:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[lsu_bus_buffer.scala 151:97] + wire _T_490 = _T_487 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_477 = |_T_476; // @[lsu_bus_buffer.scala 151:144] + wire _T_478 = ~_T_477; // @[lsu_bus_buffer.scala 151:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[lsu_bus_buffer.scala 151:97] + wire _T_482 = _T_479 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[lsu_bus_buffer.scala 143:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 143:77] + wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] + wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58] + wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] + wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_0; // @[Reg.scala 27:20] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_1; // @[Reg.scala 27:20] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_2; // @[Reg.scala 27:20] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_3; // @[Reg.scala 27:20] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 172:97] + wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] + reg [31:0] ibuf_data; // @[Reg.scala 27:20] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 173:32] + wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[lsu_bus_buffer.scala 178:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[lsu_bus_buffer.scala 178:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[lsu_bus_buffer.scala 178:97] + wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[lsu_bus_buffer.scala 179:32] + wire [3:0] _T_750 = io_lsu_pkt_r_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_751 = io_lsu_pkt_r_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_752 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[lsu_bus_buffer.scala 186:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[lsu_bus_buffer.scala 187:24] + wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[lsu_bus_buffer.scala 188:24] + wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[lsu_bus_buffer.scala 189:24] + wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72] + wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72] + wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72] + wire [31:0] _T_802 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58] + wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58] + wire [31:0] _T_810 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72] + wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72] + wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] + wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] + wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[lsu_bus_buffer.scala 207:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[lsu_bus_buffer.scala 209:31] + wire _T_845 = io_lsu_pkt_r_bits_word & _T_756; // @[Mux.scala 27:72] + wire _T_846 = io_lsu_pkt_r_bits_half & _T_844; // @[Mux.scala 27:72] + wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] + wire is_aligned_r = _T_848 | io_lsu_pkt_r_bits_by; // @[Mux.scala 27:72] + wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[lsu_bus_buffer.scala 211:60] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[lsu_bus_buffer.scala 211:34] + wire _T_852 = ~ibuf_valid; // @[lsu_bus_buffer.scala 211:84] + wire ibuf_byp = _T_851 & _T_852; // @[lsu_bus_buffer.scala 211:82] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[lsu_bus_buffer.scala 212:36] + wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 212:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 212:54] + wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 214:36] + reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 257:55] + wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 220:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 220:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 239:54] + wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 239:80] + wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 239:93] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 239:129] + wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 239:106] + wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 239:152] + wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 239:150] + wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 239:175] + wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 239:173] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 240:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 220:98] + wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 220:82] + wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 220:80] + wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 221:5] + wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 215:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 215:42] + wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 215:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 215:120] + wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 215:100] + wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 215:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 221:16] + reg ibuf_sideeffect; // @[Reg.scala 27:20] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 221:35] + wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 221:55] + wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 221:53] + wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 221:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 220:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 214:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 214:49] + reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 627:49] + reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 626:49] + reg [1:0] ibuf_tag; // @[Reg.scala 27:20] + wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 230:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 234:46] + wire [31:0] ibuf_data_in = {_T_920,_T_911,_T_902,_T_893}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 237:60] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 237:95] + wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 241:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 241:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 241:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 241:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 241:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 241:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 241:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 241:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 241:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 241:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 242:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 244:58] + wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 244:93] + reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] + reg ibuf_dual; // @[Reg.scala 27:20] + reg ibuf_samedw; // @[Reg.scala 27:20] + reg ibuf_nomerge; // @[Reg.scala 27:20] + reg ibuf_unsign; // @[Reg.scala 27:20] + reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire _T_4441 = buf_write[3] & _T_2590; // @[lsu_bus_buffer.scala 533:64] + wire _T_4442 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 533:91] + wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 533:89] + wire _T_4436 = buf_write[2] & _T_2583; // @[lsu_bus_buffer.scala 533:64] + wire _T_4437 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 533:91] + wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 533:89] + wire [1:0] _T_4444 = _T_4443 + _T_4438; // @[lsu_bus_buffer.scala 533:142] + wire _T_4431 = buf_write[1] & _T_2576; // @[lsu_bus_buffer.scala 533:64] + wire _T_4432 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 533:91] + wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 533:89] + wire [1:0] _GEN_380 = {{1'd0}, _T_4433}; // @[lsu_bus_buffer.scala 533:142] + wire [2:0] _T_4445 = _T_4444 + _GEN_380; // @[lsu_bus_buffer.scala 533:142] + wire _T_4426 = buf_write[0] & _T_2569; // @[lsu_bus_buffer.scala 533:64] + wire _T_4427 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 533:91] + wire _T_4428 = _T_4426 & _T_4427; // @[lsu_bus_buffer.scala 533:89] + wire [2:0] _GEN_381 = {{2'd0}, _T_4428}; // @[lsu_bus_buffer.scala 533:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4445 + _GEN_381; // @[lsu_bus_buffer.scala 533:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 267:43] + wire _T_4458 = _T_2590 & _T_4442; // @[lsu_bus_buffer.scala 534:73] + wire _T_4455 = _T_2583 & _T_4437; // @[lsu_bus_buffer.scala 534:73] + wire [1:0] _T_4459 = _T_4458 + _T_4455; // @[lsu_bus_buffer.scala 534:126] + wire _T_4452 = _T_2576 & _T_4432; // @[lsu_bus_buffer.scala 534:73] + wire [1:0] _GEN_382 = {{1'd0}, _T_4452}; // @[lsu_bus_buffer.scala 534:126] + wire [2:0] _T_4460 = _T_4459 + _GEN_382; // @[lsu_bus_buffer.scala 534:126] + wire _T_4449 = _T_2569 & _T_4427; // @[lsu_bus_buffer.scala 534:73] + wire [2:0] _GEN_383 = {{2'd0}, _T_4449}; // @[lsu_bus_buffer.scala 534:126] + wire [3:0] buf_numvld_cmd_any = _T_4460 + _GEN_383; // @[lsu_bus_buffer.scala 534:126] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 267:72] + wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 267:51] + reg _T_1791; // @[Reg.scala 27:20] + wire [2:0] obuf_wr_timer = {{2'd0}, _T_1791}; // @[lsu_bus_buffer.scala 365:17] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 267:97] + wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 267:80] + wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 267:114] + wire _T_1918 = |buf_age_3; // @[lsu_bus_buffer.scala 383:58] + wire _T_1919 = ~_T_1918; // @[lsu_bus_buffer.scala 383:45] + wire _T_1921 = _T_1919 & _T_2590; // @[lsu_bus_buffer.scala 383:63] + wire _T_1923 = _T_1921 & _T_4442; // @[lsu_bus_buffer.scala 383:88] + wire _T_1912 = |buf_age_2; // @[lsu_bus_buffer.scala 383:58] + wire _T_1913 = ~_T_1912; // @[lsu_bus_buffer.scala 383:45] + wire _T_1915 = _T_1913 & _T_2583; // @[lsu_bus_buffer.scala 383:63] + wire _T_1917 = _T_1915 & _T_4437; // @[lsu_bus_buffer.scala 383:88] + wire _T_1906 = |buf_age_1; // @[lsu_bus_buffer.scala 383:58] + wire _T_1907 = ~_T_1906; // @[lsu_bus_buffer.scala 383:45] + wire _T_1909 = _T_1907 & _T_2576; // @[lsu_bus_buffer.scala 383:63] + wire _T_1911 = _T_1909 & _T_4432; // @[lsu_bus_buffer.scala 383:88] + wire _T_1900 = |buf_age_0; // @[lsu_bus_buffer.scala 383:58] + wire _T_1901 = ~_T_1900; // @[lsu_bus_buffer.scala 383:45] + wire _T_1903 = _T_1901 & _T_2569; // @[lsu_bus_buffer.scala 383:63] + wire _T_1905 = _T_1903 & _T_4427; // @[lsu_bus_buffer.scala 383:88] + wire [3:0] CmdPtr0Dec = {_T_1923,_T_1917,_T_1911,_T_1905}; // @[Cat.scala 29:58] + wire [7:0] _T_1993 = {4'h0,_T_1923,_T_1917,_T_1911,_T_1905}; // @[Cat.scala 29:58] + wire _T_1996 = _T_1993[4] | _T_1993[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_1998 = _T_1996 | _T_1993[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2000 = _T_1998 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2003 = _T_1993[2] | _T_1993[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2005 = _T_2003 | _T_1993[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2007 = _T_2005 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2010 = _T_1993[1] | _T_1993[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2012 = _T_2010 | _T_1993[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2014 = _T_2012 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2016 = {_T_2000,_T_2007,_T_2014}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr0 = _T_2016[1:0]; // @[lsu_bus_buffer.scala 396:11] + wire _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 268:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 268:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 268:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 268:114] + reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] + reg buf_nomerge_1; // @[Reg.scala 27:20] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] + reg buf_nomerge_2; // @[Reg.scala 27:20] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] + reg buf_nomerge_3; // @[Reg.scala 27:20] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 268:31] + wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 268:29] + reg _T_4325; // @[Reg.scala 27:20] + reg _T_4322; // @[Reg.scala 27:20] + reg _T_4319; // @[Reg.scala 27:20] + reg _T_4316; // @[Reg.scala 27:20] + wire [3:0] buf_sideeffect = {_T_4325,_T_4322,_T_4319,_T_4316}; // @[Cat.scala 29:58] + wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72] + wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72] + wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72] + wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72] + wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] + wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] + wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] + wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 269:5] + wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 268:140] + wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 271:58] + wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 271:72] + wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] + wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] + wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 271:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 271:101] + wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 269:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 269:117] + wire _T_4477 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4481 = _T_4477 | _T_4458; // @[lsu_bus_buffer.scala 535:74] + wire _T_4472 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4476 = _T_4472 | _T_4455; // @[lsu_bus_buffer.scala 535:74] + wire [1:0] _T_4482 = _T_4481 + _T_4476; // @[lsu_bus_buffer.scala 535:154] + wire _T_4467 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4471 = _T_4467 | _T_4452; // @[lsu_bus_buffer.scala 535:74] + wire [1:0] _GEN_384 = {{1'd0}, _T_4471}; // @[lsu_bus_buffer.scala 535:154] + wire [2:0] _T_4483 = _T_4482 + _GEN_384; // @[lsu_bus_buffer.scala 535:154] + wire _T_4462 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4466 = _T_4462 | _T_4449; // @[lsu_bus_buffer.scala 535:74] + wire [2:0] _GEN_385 = {{2'd0}, _T_4466}; // @[lsu_bus_buffer.scala 535:154] + wire [3:0] buf_numvld_pend_any = _T_4483 + _GEN_385; // @[lsu_bus_buffer.scala 535:154] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 273:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 273:31] + wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 273:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 273:89] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 273:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 289:32] + wire _T_4751 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4753 = _T_4751 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4754 = _T_4753 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4755 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4757 = _T_4755 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4758 = _T_4757 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4767 = _T_4754 | _T_4758; // @[lsu_bus_buffer.scala 563:153] + wire _T_4759 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4761 = _T_4759 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4762 = _T_4761 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4768 = _T_4767 | _T_4762; // @[lsu_bus_buffer.scala 563:153] + wire _T_4763 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4765 = _T_4763 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4766 = _T_4765 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4769 = _T_4768 | _T_4766; // @[lsu_bus_buffer.scala 563:153] + reg obuf_sideeffect; // @[Reg.scala 27:20] + wire _T_4770 = obuf_valid & obuf_sideeffect; // @[lsu_bus_buffer.scala 563:171] + wire _T_4771 = _T_4770 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:189] + wire bus_sideeffect_pend = _T_4769 | _T_4771; // @[lsu_bus_buffer.scala 563:157] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 289:74] + wire _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 289:52] + wire _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 289:50] + wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] + wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] + wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] + wire _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 290:36] + wire found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 388:31] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 290:47] + wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58] + wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72] + wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72] + wire _T_1124 = _T_1120 | _T_1121; // @[Mux.scala 27:72] + wire _T_1122 = _T_1025 & _T_1111[2]; // @[Mux.scala 27:72] + wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72] + wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72] + wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72] + wire _T_1128 = ~_T_1126; // @[lsu_bus_buffer.scala 291:23] + wire _T_1129 = _T_1108 & _T_1128; // @[lsu_bus_buffer.scala 291:21] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 291:141] + wire _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 291:105] + wire _T_1148 = _T_1129 & _T_1147; // @[lsu_bus_buffer.scala 291:103] + reg buf_dual_3; // @[Reg.scala 27:20] + reg buf_dual_2; // @[Reg.scala 27:20] + reg buf_dual_1; // @[Reg.scala 27:20] + reg buf_dual_0; // @[Reg.scala 27:20] + wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58] + wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72] + wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72] + wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72] + wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72] + wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72] + reg buf_samedw_3; // @[Reg.scala 27:20] + reg buf_samedw_2; // @[Reg.scala 27:20] + reg buf_samedw_1; // @[Reg.scala 27:20] + reg buf_samedw_0; // @[Reg.scala 27:20] + wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58] + wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72] + wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72] + wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72] + wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72] + wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] + wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] + wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] + wire _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 292:77] + wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] + wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] + wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] + wire _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 292:150] + wire _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 292:148] + wire _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 292:8] + wire [3:0] _T_1959 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 384:62] + wire [3:0] _T_1960 = buf_age_3 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1961 = |_T_1960; // @[lsu_bus_buffer.scala 384:76] + wire _T_1962 = ~_T_1961; // @[lsu_bus_buffer.scala 384:45] + wire _T_1964 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1965 = _T_1962 & _T_1964; // @[lsu_bus_buffer.scala 384:81] + wire _T_1967 = _T_1965 & _T_2590; // @[lsu_bus_buffer.scala 384:98] + wire _T_1969 = _T_1967 & _T_4442; // @[lsu_bus_buffer.scala 384:123] + wire [3:0] _T_1949 = buf_age_2 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1950 = |_T_1949; // @[lsu_bus_buffer.scala 384:76] + wire _T_1951 = ~_T_1950; // @[lsu_bus_buffer.scala 384:45] + wire _T_1953 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1954 = _T_1951 & _T_1953; // @[lsu_bus_buffer.scala 384:81] + wire _T_1956 = _T_1954 & _T_2583; // @[lsu_bus_buffer.scala 384:98] + wire _T_1958 = _T_1956 & _T_4437; // @[lsu_bus_buffer.scala 384:123] + wire [3:0] _T_1938 = buf_age_1 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1939 = |_T_1938; // @[lsu_bus_buffer.scala 384:76] + wire _T_1940 = ~_T_1939; // @[lsu_bus_buffer.scala 384:45] + wire _T_1942 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1943 = _T_1940 & _T_1942; // @[lsu_bus_buffer.scala 384:81] + wire _T_1945 = _T_1943 & _T_2576; // @[lsu_bus_buffer.scala 384:98] + wire _T_1947 = _T_1945 & _T_4432; // @[lsu_bus_buffer.scala 384:123] + wire [3:0] _T_1927 = buf_age_0 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1928 = |_T_1927; // @[lsu_bus_buffer.scala 384:76] + wire _T_1929 = ~_T_1928; // @[lsu_bus_buffer.scala 384:45] + wire _T_1931 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1932 = _T_1929 & _T_1931; // @[lsu_bus_buffer.scala 384:81] + wire _T_1934 = _T_1932 & _T_2569; // @[lsu_bus_buffer.scala 384:98] + wire _T_1936 = _T_1934 & _T_4427; // @[lsu_bus_buffer.scala 384:123] + wire [3:0] CmdPtr1Dec = {_T_1969,_T_1958,_T_1947,_T_1936}; // @[Cat.scala 29:58] + wire found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 389:31] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 292:181] + wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] + wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] + wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] + wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72] + wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72] + wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] + wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] + wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] + wire _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 292:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 292:269] + wire _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 291:164] + wire _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 289:98] + reg obuf_write; // @[Reg.scala 27:20] + reg obuf_cmd_done; // @[Reg.scala 27:20] + reg obuf_data_done; // @[Reg.scala 27:20] + wire _T_4825 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 567:54] + wire _T_4826 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 567:75] + wire _T_4827 = io_lsu_axi_aw_ready & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 567:153] + wire _T_4828 = _T_4825 ? _T_4826 : _T_4827; // @[lsu_bus_buffer.scala 567:39] + wire bus_cmd_ready = obuf_write ? _T_4828 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 567:23] + wire _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 293:48] + wire _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 293:46] + reg obuf_nosend; // @[Reg.scala 27:20] + wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 293:60] + wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 293:29] + wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 293:77] + wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 293:75] + reg [31:0] obuf_addr; // @[Reg.scala 27:20] + wire _T_4776 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4777 = obuf_valid & _T_4776; // @[lsu_bus_buffer.scala 565:19] + wire _T_4779 = obuf_tag1 == 2'h0; // @[lsu_bus_buffer.scala 565:107] + wire _T_4780 = obuf_merge & _T_4779; // @[lsu_bus_buffer.scala 565:95] + wire _T_4781 = _T_3565 | _T_4780; // @[lsu_bus_buffer.scala 565:81] + wire _T_4782 = ~_T_4781; // @[lsu_bus_buffer.scala 565:61] + wire _T_4783 = _T_4777 & _T_4782; // @[lsu_bus_buffer.scala 565:59] + wire _T_4817 = _T_4751 & _T_4783; // @[Mux.scala 27:72] + wire _T_4787 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4788 = obuf_valid & _T_4787; // @[lsu_bus_buffer.scala 565:19] + wire _T_4790 = obuf_tag1 == 2'h1; // @[lsu_bus_buffer.scala 565:107] + wire _T_4791 = obuf_merge & _T_4790; // @[lsu_bus_buffer.scala 565:95] + wire _T_4792 = _T_3756 | _T_4791; // @[lsu_bus_buffer.scala 565:81] + wire _T_4793 = ~_T_4792; // @[lsu_bus_buffer.scala 565:61] + wire _T_4794 = _T_4788 & _T_4793; // @[lsu_bus_buffer.scala 565:59] + wire _T_4818 = _T_4755 & _T_4794; // @[Mux.scala 27:72] + wire _T_4821 = _T_4817 | _T_4818; // @[Mux.scala 27:72] + wire _T_4798 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4799 = obuf_valid & _T_4798; // @[lsu_bus_buffer.scala 565:19] + wire _T_4801 = obuf_tag1 == 2'h2; // @[lsu_bus_buffer.scala 565:107] + wire _T_4802 = obuf_merge & _T_4801; // @[lsu_bus_buffer.scala 565:95] + wire _T_4803 = _T_3947 | _T_4802; // @[lsu_bus_buffer.scala 565:81] + wire _T_4804 = ~_T_4803; // @[lsu_bus_buffer.scala 565:61] + wire _T_4805 = _T_4799 & _T_4804; // @[lsu_bus_buffer.scala 565:59] + wire _T_4819 = _T_4759 & _T_4805; // @[Mux.scala 27:72] + wire _T_4822 = _T_4821 | _T_4819; // @[Mux.scala 27:72] + wire _T_4809 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4810 = obuf_valid & _T_4809; // @[lsu_bus_buffer.scala 565:19] + wire _T_4812 = obuf_tag1 == 2'h3; // @[lsu_bus_buffer.scala 565:107] + wire _T_4813 = obuf_merge & _T_4812; // @[lsu_bus_buffer.scala 565:95] + wire _T_4814 = _T_4138 | _T_4813; // @[lsu_bus_buffer.scala 565:81] + wire _T_4815 = ~_T_4814; // @[lsu_bus_buffer.scala 565:61] + wire _T_4816 = _T_4810 & _T_4815; // @[lsu_bus_buffer.scala 565:59] + wire _T_4820 = _T_4763 & _T_4816; // @[Mux.scala 27:72] + wire bus_addr_match_pending = _T_4822 | _T_4820; // @[Mux.scala 27:72] + wire _T_1237 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 293:94] + wire _T_1238 = _T_1236 & _T_1237; // @[lsu_bus_buffer.scala 293:92] + wire obuf_wr_en = _T_1238 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 293:118] + wire _T_1240 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 296:47] + wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 568:40] + wire _T_4832 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 570:35] + wire bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 569:40] + wire _T_4833 = obuf_data_done | bus_wdata_sent; // @[lsu_bus_buffer.scala 570:70] + wire _T_4834 = _T_4832 & _T_4833; // @[lsu_bus_buffer.scala 570:52] + wire _T_4835 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 570:112] + wire bus_cmd_sent = _T_4834 | _T_4835; // @[lsu_bus_buffer.scala 570:89] + wire _T_1241 = bus_cmd_sent | _T_1240; // @[lsu_bus_buffer.scala 296:33] + wire _T_1242 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 296:65] + wire _T_1243 = _T_1241 & _T_1242; // @[lsu_bus_buffer.scala 296:63] + wire _T_1244 = _T_1243 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 296:77] + wire obuf_rst = _T_1244 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 296:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 297:26] + wire [31:0] _T_1281 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1282 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1283 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1284 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1285 = _T_1281 | _T_1282; // @[Mux.scala 27:72] + wire [31:0] _T_1286 = _T_1285 | _T_1283; // @[Mux.scala 27:72] + wire [31:0] _T_1287 = _T_1286 | _T_1284; // @[Mux.scala 27:72] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1287; // @[lsu_bus_buffer.scala 299:25] + reg [1:0] buf_sz_0; // @[Reg.scala 27:20] + wire [1:0] _T_1294 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire [1:0] _T_1295 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_2; // @[Reg.scala 27:20] + wire [1:0] _T_1296 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_3; // @[Reg.scala 27:20] + wire [1:0] _T_1297 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1298 = _T_1294 | _T_1295; // @[Mux.scala 27:72] + wire [1:0] _T_1299 = _T_1298 | _T_1296; // @[Mux.scala 27:72] + wire [1:0] _T_1300 = _T_1299 | _T_1297; // @[Mux.scala 27:72] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1300; // @[lsu_bus_buffer.scala 302:23] + wire [7:0] _T_2018 = {4'h0,_T_1969,_T_1958,_T_1947,_T_1936}; // @[Cat.scala 29:58] + wire _T_2021 = _T_2018[4] | _T_2018[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_2023 = _T_2021 | _T_2018[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2025 = _T_2023 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2028 = _T_2018[2] | _T_2018[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2030 = _T_2028 | _T_2018[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2032 = _T_2030 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2035 = _T_2018[1] | _T_2018[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2037 = _T_2035 | _T_2018[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2039 = _T_2037 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2041 = {_T_2025,_T_2032,_T_2039}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr1 = _T_2041[1:0]; // @[lsu_bus_buffer.scala 398:11] + wire _T_1302 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 310:39] + wire _T_1303 = ~_T_1302; // @[lsu_bus_buffer.scala 310:26] + wire obuf_cmd_done_in = _T_1303 & _T_4832; // @[lsu_bus_buffer.scala 310:51] + wire obuf_data_done_in = _T_1303 & _T_4833; // @[lsu_bus_buffer.scala 313:52] + wire _T_1309 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 314:72] + wire _T_1312 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 314:98] + wire _T_1313 = obuf_sz_in[0] & _T_1312; // @[lsu_bus_buffer.scala 314:96] + wire _T_1314 = _T_1309 | _T_1313; // @[lsu_bus_buffer.scala 314:79] + wire _T_1317 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 314:153] + wire _T_1318 = ~_T_1317; // @[lsu_bus_buffer.scala 314:134] + wire _T_1319 = obuf_sz_in[1] & _T_1318; // @[lsu_bus_buffer.scala 314:132] + wire _T_1320 = _T_1314 | _T_1319; // @[lsu_bus_buffer.scala 314:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1320; // @[lsu_bus_buffer.scala 314:28] + wire _T_1337 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 328:40] + wire _T_1338 = _T_1337 & obuf_aligned_in; // @[lsu_bus_buffer.scala 328:60] + wire _T_1339 = ~obuf_sideeffect; // @[lsu_bus_buffer.scala 328:80] + wire _T_1340 = _T_1338 & _T_1339; // @[lsu_bus_buffer.scala 328:78] + wire _T_1341 = ~obuf_write; // @[lsu_bus_buffer.scala 328:99] + wire _T_1342 = _T_1340 & _T_1341; // @[lsu_bus_buffer.scala 328:97] + wire _T_1343 = ~obuf_write_in; // @[lsu_bus_buffer.scala 328:113] + wire _T_1344 = _T_1342 & _T_1343; // @[lsu_bus_buffer.scala 328:111] + wire _T_1345 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 328:130] + wire _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 328:128] + wire _T_1347 = ~obuf_nosend; // @[lsu_bus_buffer.scala 329:20] + wire _T_1348 = obuf_valid & _T_1347; // @[lsu_bus_buffer.scala 329:18] + reg obuf_rdrsp_pend; // @[Reg.scala 27:20] + wire bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 571:38] + reg [2:0] obuf_rdrsp_tag; // @[Reg.scala 27:20] + wire _T_1349 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 329:90] + wire _T_1350 = bus_rsp_read & _T_1349; // @[lsu_bus_buffer.scala 329:70] + wire _T_1351 = ~_T_1350; // @[lsu_bus_buffer.scala 329:55] + wire _T_1352 = obuf_rdrsp_pend & _T_1351; // @[lsu_bus_buffer.scala 329:53] + wire _T_1353 = _T_1348 | _T_1352; // @[lsu_bus_buffer.scala 329:34] + wire obuf_nosend_in = _T_1346 & _T_1353; // @[lsu_bus_buffer.scala 328:177] + wire _T_1321 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 322:45] + wire _T_1322 = obuf_wr_en & _T_1321; // @[lsu_bus_buffer.scala 322:43] + wire _T_1323 = ~_T_1322; // @[lsu_bus_buffer.scala 322:30] + wire _T_1324 = _T_1323 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 322:62] + wire _T_1328 = _T_1324 & _T_1351; // @[lsu_bus_buffer.scala 322:80] + wire _T_1330 = bus_cmd_sent & _T_1341; // @[lsu_bus_buffer.scala 322:155] + wire _T_1331 = _T_1328 | _T_1330; // @[lsu_bus_buffer.scala 322:139] + wire obuf_rdrsp_pend_in = _T_1331 & _T_2594; // @[lsu_bus_buffer.scala 322:171] + wire obuf_rdrsp_pend_en = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 323:47] + wire [7:0] _T_1356 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1357 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1358 = io_lsu_addr_r[2] ? _T_1356 : _T_1357; // @[lsu_bus_buffer.scala 330:46] + wire [3:0] _T_1377 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1378 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1379 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1380 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1381 = _T_1377 | _T_1378; // @[Mux.scala 27:72] + wire [3:0] _T_1382 = _T_1381 | _T_1379; // @[Mux.scala 27:72] + wire [3:0] _T_1383 = _T_1382 | _T_1380; // @[Mux.scala 27:72] + wire [7:0] _T_1385 = {_T_1383,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1398 = {4'h0,_T_1383}; // @[Cat.scala 29:58] + wire [7:0] _T_1399 = _T_1287[2] ? _T_1385 : _T_1398; // @[lsu_bus_buffer.scala 331:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1358 : _T_1399; // @[lsu_bus_buffer.scala 330:28] + wire [7:0] _T_1401 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1402 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1403 = io_end_addr_r[2] ? _T_1401 : _T_1402; // @[lsu_bus_buffer.scala 332:46] + wire _T_1404 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 62:123] + wire _T_1405 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 62:123] + wire _T_1406 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 62:123] + wire _T_1407 = CmdPtr1 == 2'h3; // @[lsu_bus_buffer.scala 62:123] + wire [31:0] _T_1408 = _T_1404 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1409 = _T_1405 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1410 = _T_1406 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1411 = _T_1407 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1412 = _T_1408 | _T_1409; // @[Mux.scala 27:72] + wire [31:0] _T_1413 = _T_1412 | _T_1410; // @[Mux.scala 27:72] + wire [31:0] _T_1414 = _T_1413 | _T_1411; // @[Mux.scala 27:72] + wire [3:0] _T_1422 = _T_1404 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1423 = _T_1405 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1424 = _T_1406 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1425 = _T_1407 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1426 = _T_1422 | _T_1423; // @[Mux.scala 27:72] + wire [3:0] _T_1427 = _T_1426 | _T_1424; // @[Mux.scala 27:72] + wire [3:0] _T_1428 = _T_1427 | _T_1425; // @[Mux.scala 27:72] + wire [7:0] _T_1430 = {_T_1428,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1443 = {4'h0,_T_1428}; // @[Cat.scala 29:58] + wire [7:0] _T_1444 = _T_1414[2] ? _T_1430 : _T_1443; // @[lsu_bus_buffer.scala 333:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1403 : _T_1444; // @[lsu_bus_buffer.scala 332:28] + wire [63:0] _T_1446 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1447 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1448 = io_lsu_addr_r[2] ? _T_1446 : _T_1447; // @[lsu_bus_buffer.scala 335:44] + wire [31:0] _T_1467 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1468 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1469 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1470 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1471 = _T_1467 | _T_1468; // @[Mux.scala 27:72] + wire [31:0] _T_1472 = _T_1471 | _T_1469; // @[Mux.scala 27:72] + wire [31:0] _T_1473 = _T_1472 | _T_1470; // @[Mux.scala 27:72] + wire [63:0] _T_1475 = {_T_1473,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1488 = {32'h0,_T_1473}; // @[Cat.scala 29:58] + wire [63:0] _T_1489 = _T_1287[2] ? _T_1475 : _T_1488; // @[lsu_bus_buffer.scala 336:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1448 : _T_1489; // @[lsu_bus_buffer.scala 335:26] + wire [63:0] _T_1491 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1492 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1493 = io_end_addr_r[2] ? _T_1491 : _T_1492; // @[lsu_bus_buffer.scala 337:44] + wire [31:0] _T_1512 = _T_1404 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1513 = _T_1405 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1514 = _T_1406 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1515 = _T_1407 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1516 = _T_1512 | _T_1513; // @[Mux.scala 27:72] + wire [31:0] _T_1517 = _T_1516 | _T_1514; // @[Mux.scala 27:72] + wire [31:0] _T_1518 = _T_1517 | _T_1515; // @[Mux.scala 27:72] + wire [63:0] _T_1520 = {_T_1518,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1533 = {32'h0,_T_1518}; // @[Cat.scala 29:58] + wire [63:0] _T_1534 = _T_1414[2] ? _T_1520 : _T_1533; // @[lsu_bus_buffer.scala 338:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1493 : _T_1534; // @[lsu_bus_buffer.scala 337:26] + wire _T_1619 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 344:30] + wire _T_1620 = _T_1619 & found_cmdptr0; // @[lsu_bus_buffer.scala 344:43] + wire _T_1621 = _T_1620 & found_cmdptr1; // @[lsu_bus_buffer.scala 344:59] + wire _T_1635 = _T_1621 & _T_1107; // @[lsu_bus_buffer.scala 344:75] + wire [2:0] _T_1640 = _T_1404 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1641 = _T_1405 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1644 = _T_1640 | _T_1641; // @[Mux.scala 27:72] + wire [2:0] _T_1642 = _T_1406 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1645 = _T_1644 | _T_1642; // @[Mux.scala 27:72] + wire [2:0] _T_1643 = _T_1407 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1646 = _T_1645 | _T_1643; // @[Mux.scala 27:72] + wire _T_1648 = _T_1646 == 3'h2; // @[lsu_bus_buffer.scala 344:150] + wire _T_1649 = _T_1635 & _T_1648; // @[lsu_bus_buffer.scala 344:118] + wire _T_1670 = _T_1649 & _T_1128; // @[lsu_bus_buffer.scala 344:161] + wire _T_1688 = _T_1670 & _T_1053; // @[lsu_bus_buffer.scala 345:85] + wire _T_1725 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 346:36] + reg buf_dualhi_3; // @[Reg.scala 27:20] + reg buf_dualhi_2; // @[Reg.scala 27:20] + reg buf_dualhi_1; // @[Reg.scala 27:20] + reg buf_dualhi_0; // @[Reg.scala 27:20] + wire [3:0] _T_1728 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58] + wire _T_1737 = _T_1023 & _T_1728[0]; // @[Mux.scala 27:72] + wire _T_1738 = _T_1024 & _T_1728[1]; // @[Mux.scala 27:72] + wire _T_1741 = _T_1737 | _T_1738; // @[Mux.scala 27:72] + wire _T_1739 = _T_1025 & _T_1728[2]; // @[Mux.scala 27:72] + wire _T_1742 = _T_1741 | _T_1739; // @[Mux.scala 27:72] + wire _T_1740 = _T_1026 & _T_1728[3]; // @[Mux.scala 27:72] + wire _T_1743 = _T_1742 | _T_1740; // @[Mux.scala 27:72] + wire _T_1745 = ~_T_1743; // @[lsu_bus_buffer.scala 346:107] + wire _T_1746 = _T_1725 & _T_1745; // @[lsu_bus_buffer.scala 346:105] + wire _T_1766 = _T_1746 & _T_1185; // @[lsu_bus_buffer.scala 346:177] + wire _T_1767 = _T_1688 & _T_1766; // @[lsu_bus_buffer.scala 345:122] + wire _T_1768 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 347:19] + wire _T_1769 = _T_1768 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 347:35] + wire obuf_merge_en = _T_1767 | _T_1769; // @[lsu_bus_buffer.scala 346:250] + wire _T_1537 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1538 = obuf_byteen0_in[0] | _T_1537; // @[lsu_bus_buffer.scala 339:63] + wire _T_1541 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1542 = obuf_byteen0_in[1] | _T_1541; // @[lsu_bus_buffer.scala 339:63] + wire _T_1545 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1546 = obuf_byteen0_in[2] | _T_1545; // @[lsu_bus_buffer.scala 339:63] + wire _T_1549 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1550 = obuf_byteen0_in[3] | _T_1549; // @[lsu_bus_buffer.scala 339:63] + wire _T_1553 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1554 = obuf_byteen0_in[4] | _T_1553; // @[lsu_bus_buffer.scala 339:63] + wire _T_1557 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1558 = obuf_byteen0_in[5] | _T_1557; // @[lsu_bus_buffer.scala 339:63] + wire _T_1561 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1562 = obuf_byteen0_in[6] | _T_1561; // @[lsu_bus_buffer.scala 339:63] + wire _T_1565 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1566 = obuf_byteen0_in[7] | _T_1565; // @[lsu_bus_buffer.scala 339:63] + wire [7:0] obuf_byteen_in = {_T_1566,_T_1562,_T_1558,_T_1554,_T_1550,_T_1546,_T_1542,_T_1538}; // @[Cat.scala 29:58] + wire [7:0] _T_1577 = _T_1537 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1582 = _T_1541 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1587 = _T_1545 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1592 = _T_1549 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1597 = _T_1553 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1602 = _T_1557 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1607 = _T_1561 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1612 = _T_1565 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 340:44] + wire [63:0] obuf_data_in = {_T_1612,_T_1607,_T_1602,_T_1597,_T_1592,_T_1587,_T_1582,_T_1577}; // @[Cat.scala 29:58] + wire _T_1771 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 349:58] + wire _T_1772 = ~obuf_rst; // @[lsu_bus_buffer.scala 349:93] + wire _T_1780 = io_lsu_bus_obuf_c1_clken & obuf_wr_en; // @[lib.scala 388:57] + reg [1:0] obuf_sz; // @[Reg.scala 27:20] + reg [7:0] obuf_byteen; // @[Reg.scala 27:20] + reg [63:0] obuf_data; // @[Reg.scala 27:20] + wire _T_1792 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1793 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 370:30] + wire _T_1794 = ibuf_valid & _T_1793; // @[lsu_bus_buffer.scala 370:19] + wire _T_1795 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 371:18] + wire _T_1796 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 371:57] + wire _T_1797 = io_ldst_dual_r & _T_1796; // @[lsu_bus_buffer.scala 371:45] + wire _T_1798 = _T_1795 | _T_1797; // @[lsu_bus_buffer.scala 371:27] + wire _T_1799 = io_lsu_busreq_r & _T_1798; // @[lsu_bus_buffer.scala 370:58] + wire _T_1800 = _T_1794 | _T_1799; // @[lsu_bus_buffer.scala 370:39] + wire _T_1801 = ~_T_1800; // @[lsu_bus_buffer.scala 370:5] + wire _T_1802 = _T_1792 & _T_1801; // @[lsu_bus_buffer.scala 369:76] + wire _T_1803 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1804 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 370:30] + wire _T_1805 = ibuf_valid & _T_1804; // @[lsu_bus_buffer.scala 370:19] + wire _T_1806 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 371:18] + wire _T_1807 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 371:57] + wire _T_1808 = io_ldst_dual_r & _T_1807; // @[lsu_bus_buffer.scala 371:45] + wire _T_1809 = _T_1806 | _T_1808; // @[lsu_bus_buffer.scala 371:27] + wire _T_1810 = io_lsu_busreq_r & _T_1809; // @[lsu_bus_buffer.scala 370:58] + wire _T_1811 = _T_1805 | _T_1810; // @[lsu_bus_buffer.scala 370:39] + wire _T_1812 = ~_T_1811; // @[lsu_bus_buffer.scala 370:5] + wire _T_1813 = _T_1803 & _T_1812; // @[lsu_bus_buffer.scala 369:76] + wire _T_1814 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1815 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 370:30] + wire _T_1816 = ibuf_valid & _T_1815; // @[lsu_bus_buffer.scala 370:19] + wire _T_1817 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 371:18] + wire _T_1818 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 371:57] + wire _T_1819 = io_ldst_dual_r & _T_1818; // @[lsu_bus_buffer.scala 371:45] + wire _T_1820 = _T_1817 | _T_1819; // @[lsu_bus_buffer.scala 371:27] + wire _T_1821 = io_lsu_busreq_r & _T_1820; // @[lsu_bus_buffer.scala 370:58] + wire _T_1822 = _T_1816 | _T_1821; // @[lsu_bus_buffer.scala 370:39] + wire _T_1823 = ~_T_1822; // @[lsu_bus_buffer.scala 370:5] + wire _T_1824 = _T_1814 & _T_1823; // @[lsu_bus_buffer.scala 369:76] + wire _T_1825 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1826 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 370:30] + wire _T_1828 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 371:18] + wire _T_1829 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 371:57] + wire [1:0] _T_1837 = _T_1824 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] + wire [1:0] _T_1838 = _T_1813 ? 2'h1 : _T_1837; // @[Mux.scala 98:16] + wire [1:0] WrPtr0_m = _T_1802 ? 2'h0 : _T_1838; // @[Mux.scala 98:16] + wire _T_1843 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 376:33] + wire _T_1844 = io_lsu_busreq_m & _T_1843; // @[lsu_bus_buffer.scala 376:22] + wire _T_1845 = _T_1794 | _T_1844; // @[lsu_bus_buffer.scala 375:112] + wire _T_1851 = _T_1845 | _T_1799; // @[lsu_bus_buffer.scala 376:42] + wire _T_1852 = ~_T_1851; // @[lsu_bus_buffer.scala 375:78] + wire _T_1853 = _T_1792 & _T_1852; // @[lsu_bus_buffer.scala 375:76] + wire _T_1857 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 376:33] + wire _T_1858 = io_lsu_busreq_m & _T_1857; // @[lsu_bus_buffer.scala 376:22] + wire _T_1859 = _T_1805 | _T_1858; // @[lsu_bus_buffer.scala 375:112] + wire _T_1865 = _T_1859 | _T_1810; // @[lsu_bus_buffer.scala 376:42] + wire _T_1866 = ~_T_1865; // @[lsu_bus_buffer.scala 375:78] + wire _T_1867 = _T_1803 & _T_1866; // @[lsu_bus_buffer.scala 375:76] + wire _T_1871 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 376:33] + wire _T_1872 = io_lsu_busreq_m & _T_1871; // @[lsu_bus_buffer.scala 376:22] + wire _T_1873 = _T_1816 | _T_1872; // @[lsu_bus_buffer.scala 375:112] + wire _T_1879 = _T_1873 | _T_1821; // @[lsu_bus_buffer.scala 376:42] + wire _T_1880 = ~_T_1879; // @[lsu_bus_buffer.scala 375:78] + wire _T_1881 = _T_1814 & _T_1880; // @[lsu_bus_buffer.scala 375:76] + reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 514:63] + wire _T_2717 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2718 = buf_rspageQ_0[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2714 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2715 = buf_rspageQ_0[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2711 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2712 = buf_rspageQ_0[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2708 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2709 = buf_rspageQ_0[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_0 = {_T_2718,_T_2715,_T_2712,_T_2709}; // @[Cat.scala 29:58] + wire _T_1972 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 387:65] + wire _T_1973 = ~_T_1972; // @[lsu_bus_buffer.scala 387:44] + wire _T_1975 = _T_1973 & _T_2708; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 514:63] + wire _T_2733 = buf_rspageQ_1[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2730 = buf_rspageQ_1[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2727 = buf_rspageQ_1[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2724 = buf_rspageQ_1[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_1 = {_T_2733,_T_2730,_T_2727,_T_2724}; // @[Cat.scala 29:58] + wire _T_1976 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 387:65] + wire _T_1977 = ~_T_1976; // @[lsu_bus_buffer.scala 387:44] + wire _T_1979 = _T_1977 & _T_2711; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 514:63] + wire _T_2748 = buf_rspageQ_2[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2745 = buf_rspageQ_2[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2742 = buf_rspageQ_2[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2739 = buf_rspageQ_2[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_2 = {_T_2748,_T_2745,_T_2742,_T_2739}; // @[Cat.scala 29:58] + wire _T_1980 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 387:65] + wire _T_1981 = ~_T_1980; // @[lsu_bus_buffer.scala 387:44] + wire _T_1983 = _T_1981 & _T_2714; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 514:63] + wire _T_2763 = buf_rspageQ_3[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2760 = buf_rspageQ_3[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2757 = buf_rspageQ_3[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2754 = buf_rspageQ_3[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_3 = {_T_2763,_T_2760,_T_2757,_T_2754}; // @[Cat.scala 29:58] + wire _T_1984 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 387:65] + wire _T_1985 = ~_T_1984; // @[lsu_bus_buffer.scala 387:44] + wire _T_1987 = _T_1985 & _T_2717; // @[lsu_bus_buffer.scala 387:70] + wire [7:0] _T_2043 = {4'h0,_T_1987,_T_1983,_T_1979,_T_1975}; // @[Cat.scala 29:58] + wire _T_2046 = _T_2043[4] | _T_2043[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_2048 = _T_2046 | _T_2043[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2050 = _T_2048 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2053 = _T_2043[2] | _T_2043[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2055 = _T_2053 | _T_2043[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2057 = _T_2055 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2060 = _T_2043[1] | _T_2043[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2062 = _T_2060 | _T_2043[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2064 = _T_2062 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2066 = {_T_2050,_T_2057,_T_2064}; // @[Cat.scala 29:58] + wire _T_3535 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 445:77] + wire _T_3536 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 445:97] + wire _T_3537 = _T_3535 & _T_3536; // @[lsu_bus_buffer.scala 445:95] + wire _T_3538 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 445:112] + wire _T_3540 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 445:144] + wire _T_3541 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3542 = _T_3540 & _T_3541; // @[lsu_bus_buffer.scala 445:161] + wire _T_3543 = _T_3539 | _T_3542; // @[lsu_bus_buffer.scala 445:132] + wire _T_3544 = _T_853 & _T_3543; // @[lsu_bus_buffer.scala 445:63] + wire _T_3545 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3546 = ibuf_drain_vld & _T_3545; // @[lsu_bus_buffer.scala 445:201] + wire _T_3547 = _T_3544 | _T_3546; // @[lsu_bus_buffer.scala 445:183] + wire bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 572:39] + wire _T_3636 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 475:73] + wire _T_3637 = bus_rsp_write & _T_3636; // @[lsu_bus_buffer.scala 475:52] + wire _T_3638 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 476:46] + reg _T_4302; // @[Reg.scala 27:20] + reg _T_4300; // @[Reg.scala 27:20] + reg _T_4298; // @[Reg.scala 27:20] + reg _T_4296; // @[Reg.scala 27:20] + wire [3:0] buf_ldfwd = {_T_4302,_T_4300,_T_4298,_T_4296}; // @[Cat.scala 29:58] + reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_386 = {{1'd0}, buf_ldfwdtag_0}; // @[lsu_bus_buffer.scala 477:47] + wire _T_3640 = io_lsu_axi_r_bits_id == _GEN_386; // @[lsu_bus_buffer.scala 477:47] + wire _T_3641 = buf_ldfwd[0] & _T_3640; // @[lsu_bus_buffer.scala 477:27] + wire _T_3642 = _T_3638 | _T_3641; // @[lsu_bus_buffer.scala 476:77] + wire _T_3643 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 478:26] + wire _T_3645 = ~buf_write[0]; // @[lsu_bus_buffer.scala 478:44] + wire _T_3646 = _T_3643 & _T_3645; // @[lsu_bus_buffer.scala 478:42] + wire _T_3647 = _T_3646 & buf_samedw_0; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_387 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 478:94] + wire _T_3648 = io_lsu_axi_r_bits_id == _GEN_387; // @[lsu_bus_buffer.scala 478:94] + wire _T_3649 = _T_3647 & _T_3648; // @[lsu_bus_buffer.scala 478:74] + wire _T_3650 = _T_3642 | _T_3649; // @[lsu_bus_buffer.scala 477:71] + wire _T_3651 = bus_rsp_read & _T_3650; // @[lsu_bus_buffer.scala 476:25] + wire _T_3652 = _T_3637 | _T_3651; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_52 = _T_3592 & _T_3652; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_3558 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_3554 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire [3:0] _T_3687 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 492:21] + reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20] + wire [1:0] _GEN_33 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_34 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_33; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_35 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_34; // @[lsu_bus_buffer.scala 492:58] + wire [2:0] _GEN_389 = {{1'd0}, _GEN_35}; // @[lsu_bus_buffer.scala 492:58] + wire _T_3689 = io_lsu_axi_r_bits_id == _GEN_389; // @[lsu_bus_buffer.scala 492:58] + wire _T_3690 = _T_3687[0] & _T_3689; // @[lsu_bus_buffer.scala 492:38] + wire _T_3691 = _T_3648 | _T_3690; // @[lsu_bus_buffer.scala 491:95] + wire _T_3692 = bus_rsp_read & _T_3691; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_46 = _T_3677 & _T_3692; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_3592 ? buf_resp_state_bus_en_0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_3558 ? buf_cmd_state_bus_en_0 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_77 = _T_3554 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire buf_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58] + wire _T_3571 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3572 = _T_3571 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire [1:0] RspPtr = _T_2066[1:0]; // @[lsu_bus_buffer.scala 399:10] + wire _T_3698 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 499:37] + wire _T_3699 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_3700 = buf_dual_0 & _T_3699; // @[lsu_bus_buffer.scala 499:80] + wire _T_3701 = _T_3698 | _T_3700; // @[lsu_bus_buffer.scala 499:65] + wire _T_3702 = _T_3701 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_41 = _T_3695 ? _T_3702 : _T_3703; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_3677 ? _T_3572 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_3592 ? _T_3572 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_3558 ? _T_3572 : _GEN_54; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_3554 ? obuf_rdrsp_pend_en : _GEN_64; // @[Conditional.scala 39:67] + wire buf_state_en_0 = _T_3531 ? _T_3547 : _GEN_74; // @[Conditional.scala 40:58] + wire _T_2068 = _T_1792 & buf_state_en_0; // @[lsu_bus_buffer.scala 411:94] + wire _T_2074 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 413:23] + wire _T_2076 = _T_2074 & _T_3535; // @[lsu_bus_buffer.scala 413:41] + wire _T_2078 = _T_2076 & _T_1795; // @[lsu_bus_buffer.scala 413:71] + wire _T_2080 = _T_2078 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2081 = _T_4466 | _T_2080; // @[lsu_bus_buffer.scala 412:86] + wire _T_2082 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 414:17] + wire _T_2083 = _T_2082 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 414:35] + wire _T_2085 = _T_2083 & _T_1796; // @[lsu_bus_buffer.scala 414:52] + wire _T_2087 = _T_2085 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2088 = _T_2081 | _T_2087; // @[lsu_bus_buffer.scala 413:114] + wire _T_2089 = _T_2068 & _T_2088; // @[lsu_bus_buffer.scala 411:113] + wire _T_2091 = _T_2089 | buf_age_0[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2105 = _T_2078 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2106 = _T_4471 | _T_2105; // @[lsu_bus_buffer.scala 412:86] + wire _T_2112 = _T_2085 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2113 = _T_2106 | _T_2112; // @[lsu_bus_buffer.scala 413:114] + wire _T_2114 = _T_2068 & _T_2113; // @[lsu_bus_buffer.scala 411:113] + wire _T_2116 = _T_2114 | buf_age_0[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2130 = _T_2078 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2131 = _T_4476 | _T_2130; // @[lsu_bus_buffer.scala 412:86] + wire _T_2137 = _T_2085 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2138 = _T_2131 | _T_2137; // @[lsu_bus_buffer.scala 413:114] + wire _T_2139 = _T_2068 & _T_2138; // @[lsu_bus_buffer.scala 411:113] + wire _T_2141 = _T_2139 | buf_age_0[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2155 = _T_2078 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2156 = _T_4481 | _T_2155; // @[lsu_bus_buffer.scala 412:86] + wire _T_2162 = _T_2085 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2163 = _T_2156 | _T_2162; // @[lsu_bus_buffer.scala 413:114] + wire _T_2164 = _T_2068 & _T_2163; // @[lsu_bus_buffer.scala 411:113] + wire _T_2166 = _T_2164 | buf_age_0[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2168 = {_T_2166,_T_2141,_T_2116}; // @[Cat.scala 29:58] + wire _T_3729 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3730 = _T_3537 & _T_3729; // @[lsu_bus_buffer.scala 445:112] + wire _T_3732 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3733 = _T_3540 & _T_3732; // @[lsu_bus_buffer.scala 445:161] + wire _T_3734 = _T_3730 | _T_3733; // @[lsu_bus_buffer.scala 445:132] + wire _T_3735 = _T_853 & _T_3734; // @[lsu_bus_buffer.scala 445:63] + wire _T_3736 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3737 = ibuf_drain_vld & _T_3736; // @[lsu_bus_buffer.scala 445:201] + wire _T_3738 = _T_3735 | _T_3737; // @[lsu_bus_buffer.scala 445:183] + wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 475:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 475:52] + wire _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 476:46] + wire [2:0] _GEN_390 = {{1'd0}, buf_ldfwdtag_1}; // @[lsu_bus_buffer.scala 477:47] + wire _T_3831 = io_lsu_axi_r_bits_id == _GEN_390; // @[lsu_bus_buffer.scala 477:47] + wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[lsu_bus_buffer.scala 477:27] + wire _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 476:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 478:26] + wire _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 478:44] + wire _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 478:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] + wire [2:0] _GEN_391 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 478:94] + wire _T_3839 = io_lsu_axi_r_bits_id == _GEN_391; // @[lsu_bus_buffer.scala 478:94] + wire _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 478:74] + wire _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 477:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 476:25] + wire _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_128 = _T_3783 & _T_3843; // @[Conditional.scala 39:67] + wire _GEN_148 = _T_3749 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] + wire _GEN_160 = _T_3745 ? 1'h0 : _GEN_148; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_160; // @[Conditional.scala 40:58] + wire [3:0] _T_3878 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 492:21] + wire [1:0] _GEN_109 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_110 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_109; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_111 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_110; // @[lsu_bus_buffer.scala 492:58] + wire [2:0] _GEN_393 = {{1'd0}, _GEN_111}; // @[lsu_bus_buffer.scala 492:58] + wire _T_3880 = io_lsu_axi_r_bits_id == _GEN_393; // @[lsu_bus_buffer.scala 492:58] + wire _T_3881 = _T_3878[0] & _T_3880; // @[lsu_bus_buffer.scala 492:38] + wire _T_3882 = _T_3839 | _T_3881; // @[lsu_bus_buffer.scala 491:95] + wire _T_3883 = bus_rsp_read & _T_3882; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_122 = _T_3868 & _T_3883; // @[Conditional.scala 39:67] + wire _GEN_129 = _T_3783 ? buf_resp_state_bus_en_1 : _GEN_122; // @[Conditional.scala 39:67] + wire _GEN_139 = _T_3749 ? buf_cmd_state_bus_en_1 : _GEN_129; // @[Conditional.scala 39:67] + wire _GEN_153 = _T_3745 ? 1'h0 : _GEN_139; // @[Conditional.scala 39:67] + wire buf_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_153; // @[Conditional.scala 40:58] + wire _T_3762 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3763 = _T_3762 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_3889 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 499:37] + wire _T_3890 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_3891 = buf_dual_1 & _T_3890; // @[lsu_bus_buffer.scala 499:80] + wire _T_3892 = _T_3889 | _T_3891; // @[lsu_bus_buffer.scala 499:65] + wire _T_3893 = _T_3892 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_117 = _T_3886 ? _T_3893 : _T_3894; // @[Conditional.scala 39:67] + wire _GEN_123 = _T_3868 ? _T_3763 : _GEN_117; // @[Conditional.scala 39:67] + wire _GEN_130 = _T_3783 ? _T_3763 : _GEN_123; // @[Conditional.scala 39:67] + wire _GEN_140 = _T_3749 ? _T_3763 : _GEN_130; // @[Conditional.scala 39:67] + wire _GEN_150 = _T_3745 ? obuf_rdrsp_pend_en : _GEN_140; // @[Conditional.scala 39:67] + wire buf_state_en_1 = _T_3722 ? _T_3738 : _GEN_150; // @[Conditional.scala 40:58] + wire _T_2170 = _T_1803 & buf_state_en_1; // @[lsu_bus_buffer.scala 411:94] + wire _T_2180 = _T_2076 & _T_1806; // @[lsu_bus_buffer.scala 413:71] + wire _T_2182 = _T_2180 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2183 = _T_4466 | _T_2182; // @[lsu_bus_buffer.scala 412:86] + wire _T_2187 = _T_2083 & _T_1807; // @[lsu_bus_buffer.scala 414:52] + wire _T_2189 = _T_2187 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2190 = _T_2183 | _T_2189; // @[lsu_bus_buffer.scala 413:114] + wire _T_2191 = _T_2170 & _T_2190; // @[lsu_bus_buffer.scala 411:113] + wire _T_2193 = _T_2191 | buf_age_1[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2207 = _T_2180 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2208 = _T_4471 | _T_2207; // @[lsu_bus_buffer.scala 412:86] + wire _T_2214 = _T_2187 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2215 = _T_2208 | _T_2214; // @[lsu_bus_buffer.scala 413:114] + wire _T_2216 = _T_2170 & _T_2215; // @[lsu_bus_buffer.scala 411:113] + wire _T_2218 = _T_2216 | buf_age_1[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2232 = _T_2180 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2233 = _T_4476 | _T_2232; // @[lsu_bus_buffer.scala 412:86] + wire _T_2239 = _T_2187 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2240 = _T_2233 | _T_2239; // @[lsu_bus_buffer.scala 413:114] + wire _T_2241 = _T_2170 & _T_2240; // @[lsu_bus_buffer.scala 411:113] + wire _T_2243 = _T_2241 | buf_age_1[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2257 = _T_2180 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2258 = _T_4481 | _T_2257; // @[lsu_bus_buffer.scala 412:86] + wire _T_2264 = _T_2187 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2265 = _T_2258 | _T_2264; // @[lsu_bus_buffer.scala 413:114] + wire _T_2266 = _T_2170 & _T_2265; // @[lsu_bus_buffer.scala 411:113] + wire _T_2268 = _T_2266 | buf_age_1[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2270 = {_T_2268,_T_2243,_T_2218}; // @[Cat.scala 29:58] + wire _T_3920 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3921 = _T_3537 & _T_3920; // @[lsu_bus_buffer.scala 445:112] + wire _T_3923 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3924 = _T_3540 & _T_3923; // @[lsu_bus_buffer.scala 445:161] + wire _T_3925 = _T_3921 | _T_3924; // @[lsu_bus_buffer.scala 445:132] + wire _T_3926 = _T_853 & _T_3925; // @[lsu_bus_buffer.scala 445:63] + wire _T_3927 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3928 = ibuf_drain_vld & _T_3927; // @[lsu_bus_buffer.scala 445:201] + wire _T_3929 = _T_3926 | _T_3928; // @[lsu_bus_buffer.scala 445:183] + wire _T_4018 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 475:73] + wire _T_4019 = bus_rsp_write & _T_4018; // @[lsu_bus_buffer.scala 475:52] + wire _T_4020 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 476:46] + wire [2:0] _GEN_394 = {{1'd0}, buf_ldfwdtag_2}; // @[lsu_bus_buffer.scala 477:47] + wire _T_4022 = io_lsu_axi_r_bits_id == _GEN_394; // @[lsu_bus_buffer.scala 477:47] + wire _T_4023 = buf_ldfwd[2] & _T_4022; // @[lsu_bus_buffer.scala 477:27] + wire _T_4024 = _T_4020 | _T_4023; // @[lsu_bus_buffer.scala 476:77] + wire _T_4025 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 478:26] + wire _T_4027 = ~buf_write[2]; // @[lsu_bus_buffer.scala 478:44] + wire _T_4028 = _T_4025 & _T_4027; // @[lsu_bus_buffer.scala 478:42] + wire _T_4029 = _T_4028 & buf_samedw_2; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] + wire [2:0] _GEN_395 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 478:94] + wire _T_4030 = io_lsu_axi_r_bits_id == _GEN_395; // @[lsu_bus_buffer.scala 478:94] + wire _T_4031 = _T_4029 & _T_4030; // @[lsu_bus_buffer.scala 478:74] + wire _T_4032 = _T_4024 | _T_4031; // @[lsu_bus_buffer.scala 477:71] + wire _T_4033 = bus_rsp_read & _T_4032; // @[lsu_bus_buffer.scala 476:25] + wire _T_4034 = _T_4019 | _T_4033; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_204 = _T_3974 & _T_4034; // @[Conditional.scala 39:67] + wire _GEN_224 = _T_3940 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] + wire _GEN_236 = _T_3936 ? 1'h0 : _GEN_224; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_236; // @[Conditional.scala 40:58] + wire [3:0] _T_4069 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 492:21] + wire [1:0] _GEN_185 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_186 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_185; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_187 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_186; // @[lsu_bus_buffer.scala 492:58] + wire [2:0] _GEN_397 = {{1'd0}, _GEN_187}; // @[lsu_bus_buffer.scala 492:58] + wire _T_4071 = io_lsu_axi_r_bits_id == _GEN_397; // @[lsu_bus_buffer.scala 492:58] + wire _T_4072 = _T_4069[0] & _T_4071; // @[lsu_bus_buffer.scala 492:38] + wire _T_4073 = _T_4030 | _T_4072; // @[lsu_bus_buffer.scala 491:95] + wire _T_4074 = bus_rsp_read & _T_4073; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_198 = _T_4059 & _T_4074; // @[Conditional.scala 39:67] + wire _GEN_205 = _T_3974 ? buf_resp_state_bus_en_2 : _GEN_198; // @[Conditional.scala 39:67] + wire _GEN_215 = _T_3940 ? buf_cmd_state_bus_en_2 : _GEN_205; // @[Conditional.scala 39:67] + wire _GEN_229 = _T_3936 ? 1'h0 : _GEN_215; // @[Conditional.scala 39:67] + wire buf_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_229; // @[Conditional.scala 40:58] + wire _T_3953 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3954 = _T_3953 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_4080 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 499:37] + wire _T_4081 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_4082 = buf_dual_2 & _T_4081; // @[lsu_bus_buffer.scala 499:80] + wire _T_4083 = _T_4080 | _T_4082; // @[lsu_bus_buffer.scala 499:65] + wire _T_4084 = _T_4083 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_193 = _T_4077 ? _T_4084 : _T_4085; // @[Conditional.scala 39:67] + wire _GEN_199 = _T_4059 ? _T_3954 : _GEN_193; // @[Conditional.scala 39:67] + wire _GEN_206 = _T_3974 ? _T_3954 : _GEN_199; // @[Conditional.scala 39:67] + wire _GEN_216 = _T_3940 ? _T_3954 : _GEN_206; // @[Conditional.scala 39:67] + wire _GEN_226 = _T_3936 ? obuf_rdrsp_pend_en : _GEN_216; // @[Conditional.scala 39:67] + wire buf_state_en_2 = _T_3913 ? _T_3929 : _GEN_226; // @[Conditional.scala 40:58] + wire _T_2272 = _T_1814 & buf_state_en_2; // @[lsu_bus_buffer.scala 411:94] + wire _T_2282 = _T_2076 & _T_1817; // @[lsu_bus_buffer.scala 413:71] + wire _T_2284 = _T_2282 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2285 = _T_4466 | _T_2284; // @[lsu_bus_buffer.scala 412:86] + wire _T_2289 = _T_2083 & _T_1818; // @[lsu_bus_buffer.scala 414:52] + wire _T_2291 = _T_2289 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2292 = _T_2285 | _T_2291; // @[lsu_bus_buffer.scala 413:114] + wire _T_2293 = _T_2272 & _T_2292; // @[lsu_bus_buffer.scala 411:113] + wire _T_2295 = _T_2293 | buf_age_2[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2309 = _T_2282 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2310 = _T_4471 | _T_2309; // @[lsu_bus_buffer.scala 412:86] + wire _T_2316 = _T_2289 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2317 = _T_2310 | _T_2316; // @[lsu_bus_buffer.scala 413:114] + wire _T_2318 = _T_2272 & _T_2317; // @[lsu_bus_buffer.scala 411:113] + wire _T_2320 = _T_2318 | buf_age_2[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2334 = _T_2282 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2335 = _T_4476 | _T_2334; // @[lsu_bus_buffer.scala 412:86] + wire _T_2341 = _T_2289 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2342 = _T_2335 | _T_2341; // @[lsu_bus_buffer.scala 413:114] + wire _T_2343 = _T_2272 & _T_2342; // @[lsu_bus_buffer.scala 411:113] + wire _T_2345 = _T_2343 | buf_age_2[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2359 = _T_2282 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2360 = _T_4481 | _T_2359; // @[lsu_bus_buffer.scala 412:86] + wire _T_2366 = _T_2289 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2367 = _T_2360 | _T_2366; // @[lsu_bus_buffer.scala 413:114] + wire _T_2368 = _T_2272 & _T_2367; // @[lsu_bus_buffer.scala 411:113] + wire _T_2370 = _T_2368 | buf_age_2[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2372 = {_T_2370,_T_2345,_T_2320}; // @[Cat.scala 29:58] + wire _T_4111 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_4112 = _T_3537 & _T_4111; // @[lsu_bus_buffer.scala 445:112] + wire _T_4114 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_4115 = _T_3540 & _T_4114; // @[lsu_bus_buffer.scala 445:161] + wire _T_4116 = _T_4112 | _T_4115; // @[lsu_bus_buffer.scala 445:132] + wire _T_4117 = _T_853 & _T_4116; // @[lsu_bus_buffer.scala 445:63] + wire _T_4118 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_4119 = ibuf_drain_vld & _T_4118; // @[lsu_bus_buffer.scala 445:201] + wire _T_4120 = _T_4117 | _T_4119; // @[lsu_bus_buffer.scala 445:183] + wire _T_4209 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 475:73] + wire _T_4210 = bus_rsp_write & _T_4209; // @[lsu_bus_buffer.scala 475:52] + wire _T_4211 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 476:46] + wire [2:0] _GEN_398 = {{1'd0}, buf_ldfwdtag_3}; // @[lsu_bus_buffer.scala 477:47] + wire _T_4213 = io_lsu_axi_r_bits_id == _GEN_398; // @[lsu_bus_buffer.scala 477:47] + wire _T_4214 = buf_ldfwd[3] & _T_4213; // @[lsu_bus_buffer.scala 477:27] + wire _T_4215 = _T_4211 | _T_4214; // @[lsu_bus_buffer.scala 476:77] + wire _T_4216 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 478:26] + wire _T_4218 = ~buf_write[3]; // @[lsu_bus_buffer.scala 478:44] + wire _T_4219 = _T_4216 & _T_4218; // @[lsu_bus_buffer.scala 478:42] + wire _T_4220 = _T_4219 & buf_samedw_3; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] + wire [2:0] _GEN_399 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 478:94] + wire _T_4221 = io_lsu_axi_r_bits_id == _GEN_399; // @[lsu_bus_buffer.scala 478:94] + wire _T_4222 = _T_4220 & _T_4221; // @[lsu_bus_buffer.scala 478:74] + wire _T_4223 = _T_4215 | _T_4222; // @[lsu_bus_buffer.scala 477:71] + wire _T_4224 = bus_rsp_read & _T_4223; // @[lsu_bus_buffer.scala 476:25] + wire _T_4225 = _T_4210 | _T_4224; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_280 = _T_4165 & _T_4225; // @[Conditional.scala 39:67] + wire _GEN_300 = _T_4131 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] + wire _GEN_312 = _T_4127 ? 1'h0 : _GEN_300; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_312; // @[Conditional.scala 40:58] + wire [3:0] _T_4260 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 492:21] + wire [1:0] _GEN_261 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_262 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_261; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_263 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_262; // @[lsu_bus_buffer.scala 492:58] + wire [2:0] _GEN_401 = {{1'd0}, _GEN_263}; // @[lsu_bus_buffer.scala 492:58] + wire _T_4262 = io_lsu_axi_r_bits_id == _GEN_401; // @[lsu_bus_buffer.scala 492:58] + wire _T_4263 = _T_4260[0] & _T_4262; // @[lsu_bus_buffer.scala 492:38] + wire _T_4264 = _T_4221 | _T_4263; // @[lsu_bus_buffer.scala 491:95] + wire _T_4265 = bus_rsp_read & _T_4264; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_274 = _T_4250 & _T_4265; // @[Conditional.scala 39:67] + wire _GEN_281 = _T_4165 ? buf_resp_state_bus_en_3 : _GEN_274; // @[Conditional.scala 39:67] + wire _GEN_291 = _T_4131 ? buf_cmd_state_bus_en_3 : _GEN_281; // @[Conditional.scala 39:67] + wire _GEN_305 = _T_4127 ? 1'h0 : _GEN_291; // @[Conditional.scala 39:67] + wire buf_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_305; // @[Conditional.scala 40:58] + wire _T_4144 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_4145 = _T_4144 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_4271 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 499:37] + wire _T_4272 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_4273 = buf_dual_3 & _T_4272; // @[lsu_bus_buffer.scala 499:80] + wire _T_4274 = _T_4271 | _T_4273; // @[lsu_bus_buffer.scala 499:65] + wire _T_4275 = _T_4274 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_269 = _T_4268 ? _T_4275 : _T_4276; // @[Conditional.scala 39:67] + wire _GEN_275 = _T_4250 ? _T_4145 : _GEN_269; // @[Conditional.scala 39:67] + wire _GEN_282 = _T_4165 ? _T_4145 : _GEN_275; // @[Conditional.scala 39:67] + wire _GEN_292 = _T_4131 ? _T_4145 : _GEN_282; // @[Conditional.scala 39:67] + wire _GEN_302 = _T_4127 ? obuf_rdrsp_pend_en : _GEN_292; // @[Conditional.scala 39:67] + wire buf_state_en_3 = _T_4104 ? _T_4120 : _GEN_302; // @[Conditional.scala 40:58] + wire _T_2374 = _T_1825 & buf_state_en_3; // @[lsu_bus_buffer.scala 411:94] + wire _T_2384 = _T_2076 & _T_1828; // @[lsu_bus_buffer.scala 413:71] + wire _T_2386 = _T_2384 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2387 = _T_4466 | _T_2386; // @[lsu_bus_buffer.scala 412:86] + wire _T_2391 = _T_2083 & _T_1829; // @[lsu_bus_buffer.scala 414:52] + wire _T_2393 = _T_2391 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2394 = _T_2387 | _T_2393; // @[lsu_bus_buffer.scala 413:114] + wire _T_2395 = _T_2374 & _T_2394; // @[lsu_bus_buffer.scala 411:113] + wire _T_2397 = _T_2395 | buf_age_3[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2411 = _T_2384 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2412 = _T_4471 | _T_2411; // @[lsu_bus_buffer.scala 412:86] + wire _T_2418 = _T_2391 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2419 = _T_2412 | _T_2418; // @[lsu_bus_buffer.scala 413:114] + wire _T_2420 = _T_2374 & _T_2419; // @[lsu_bus_buffer.scala 411:113] + wire _T_2422 = _T_2420 | buf_age_3[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2436 = _T_2384 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2437 = _T_4476 | _T_2436; // @[lsu_bus_buffer.scala 412:86] + wire _T_2443 = _T_2391 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2444 = _T_2437 | _T_2443; // @[lsu_bus_buffer.scala 413:114] + wire _T_2445 = _T_2374 & _T_2444; // @[lsu_bus_buffer.scala 411:113] + wire _T_2447 = _T_2445 | buf_age_3[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2461 = _T_2384 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2462 = _T_4481 | _T_2461; // @[lsu_bus_buffer.scala 412:86] + wire _T_2468 = _T_2391 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2469 = _T_2462 | _T_2468; // @[lsu_bus_buffer.scala 413:114] + wire _T_2470 = _T_2374 & _T_2469; // @[lsu_bus_buffer.scala 411:113] + wire _T_2472 = _T_2470 | buf_age_3[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2474 = {_T_2472,_T_2447,_T_2422}; // @[Cat.scala 29:58] + wire _T_2770 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2771 = _T_1792 | _T_2770; // @[lsu_bus_buffer.scala 422:32] + wire _T_2772 = ~_T_2771; // @[lsu_bus_buffer.scala 422:6] + wire _T_2780 = _T_2772 | _T_2080; // @[lsu_bus_buffer.scala 422:59] + wire _T_2787 = _T_2780 | _T_2087; // @[lsu_bus_buffer.scala 423:110] + wire _T_2788 = _T_2068 & _T_2787; // @[lsu_bus_buffer.scala 421:112] + wire _T_2792 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2793 = _T_1803 | _T_2792; // @[lsu_bus_buffer.scala 422:32] + wire _T_2794 = ~_T_2793; // @[lsu_bus_buffer.scala 422:6] + wire _T_2802 = _T_2794 | _T_2105; // @[lsu_bus_buffer.scala 422:59] + wire _T_2809 = _T_2802 | _T_2112; // @[lsu_bus_buffer.scala 423:110] + wire _T_2810 = _T_2068 & _T_2809; // @[lsu_bus_buffer.scala 421:112] + wire _T_2814 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2815 = _T_1814 | _T_2814; // @[lsu_bus_buffer.scala 422:32] + wire _T_2816 = ~_T_2815; // @[lsu_bus_buffer.scala 422:6] + wire _T_2824 = _T_2816 | _T_2130; // @[lsu_bus_buffer.scala 422:59] + wire _T_2831 = _T_2824 | _T_2137; // @[lsu_bus_buffer.scala 423:110] + wire _T_2832 = _T_2068 & _T_2831; // @[lsu_bus_buffer.scala 421:112] + wire _T_2836 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2837 = _T_1825 | _T_2836; // @[lsu_bus_buffer.scala 422:32] + wire _T_2838 = ~_T_2837; // @[lsu_bus_buffer.scala 422:6] + wire _T_2846 = _T_2838 | _T_2155; // @[lsu_bus_buffer.scala 422:59] + wire _T_2853 = _T_2846 | _T_2162; // @[lsu_bus_buffer.scala 423:110] + wire _T_2854 = _T_2068 & _T_2853; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_0 = {_T_2854,_T_2832,_T_2810,_T_2788}; // @[Cat.scala 29:58] + wire _T_2871 = _T_2772 | _T_2182; // @[lsu_bus_buffer.scala 422:59] + wire _T_2878 = _T_2871 | _T_2189; // @[lsu_bus_buffer.scala 423:110] + wire _T_2879 = _T_2170 & _T_2878; // @[lsu_bus_buffer.scala 421:112] + wire _T_2893 = _T_2794 | _T_2207; // @[lsu_bus_buffer.scala 422:59] + wire _T_2900 = _T_2893 | _T_2214; // @[lsu_bus_buffer.scala 423:110] + wire _T_2901 = _T_2170 & _T_2900; // @[lsu_bus_buffer.scala 421:112] + wire _T_2915 = _T_2816 | _T_2232; // @[lsu_bus_buffer.scala 422:59] + wire _T_2922 = _T_2915 | _T_2239; // @[lsu_bus_buffer.scala 423:110] + wire _T_2923 = _T_2170 & _T_2922; // @[lsu_bus_buffer.scala 421:112] + wire _T_2937 = _T_2838 | _T_2257; // @[lsu_bus_buffer.scala 422:59] + wire _T_2944 = _T_2937 | _T_2264; // @[lsu_bus_buffer.scala 423:110] + wire _T_2945 = _T_2170 & _T_2944; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_1 = {_T_2945,_T_2923,_T_2901,_T_2879}; // @[Cat.scala 29:58] + wire _T_2962 = _T_2772 | _T_2284; // @[lsu_bus_buffer.scala 422:59] + wire _T_2969 = _T_2962 | _T_2291; // @[lsu_bus_buffer.scala 423:110] + wire _T_2970 = _T_2272 & _T_2969; // @[lsu_bus_buffer.scala 421:112] + wire _T_2984 = _T_2794 | _T_2309; // @[lsu_bus_buffer.scala 422:59] + wire _T_2991 = _T_2984 | _T_2316; // @[lsu_bus_buffer.scala 423:110] + wire _T_2992 = _T_2272 & _T_2991; // @[lsu_bus_buffer.scala 421:112] + wire _T_3006 = _T_2816 | _T_2334; // @[lsu_bus_buffer.scala 422:59] + wire _T_3013 = _T_3006 | _T_2341; // @[lsu_bus_buffer.scala 423:110] + wire _T_3014 = _T_2272 & _T_3013; // @[lsu_bus_buffer.scala 421:112] + wire _T_3028 = _T_2838 | _T_2359; // @[lsu_bus_buffer.scala 422:59] + wire _T_3035 = _T_3028 | _T_2366; // @[lsu_bus_buffer.scala 423:110] + wire _T_3036 = _T_2272 & _T_3035; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_2 = {_T_3036,_T_3014,_T_2992,_T_2970}; // @[Cat.scala 29:58] + wire _T_3053 = _T_2772 | _T_2386; // @[lsu_bus_buffer.scala 422:59] + wire _T_3060 = _T_3053 | _T_2393; // @[lsu_bus_buffer.scala 423:110] + wire _T_3061 = _T_2374 & _T_3060; // @[lsu_bus_buffer.scala 421:112] + wire _T_3075 = _T_2794 | _T_2411; // @[lsu_bus_buffer.scala 422:59] + wire _T_3082 = _T_3075 | _T_2418; // @[lsu_bus_buffer.scala 423:110] + wire _T_3083 = _T_2374 & _T_3082; // @[lsu_bus_buffer.scala 421:112] + wire _T_3097 = _T_2816 | _T_2436; // @[lsu_bus_buffer.scala 422:59] + wire _T_3104 = _T_3097 | _T_2443; // @[lsu_bus_buffer.scala 423:110] + wire _T_3105 = _T_2374 & _T_3104; // @[lsu_bus_buffer.scala 421:112] + wire _T_3119 = _T_2838 | _T_2461; // @[lsu_bus_buffer.scala 422:59] + wire _T_3126 = _T_3119 | _T_2468; // @[lsu_bus_buffer.scala 423:110] + wire _T_3127 = _T_2374 & _T_3126; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_3 = {_T_3127,_T_3105,_T_3083,_T_3061}; // @[Cat.scala 29:58] + wire _T_3218 = _T_2836 | _T_1825; // @[lsu_bus_buffer.scala 426:110] + wire _T_3219 = ~_T_3218; // @[lsu_bus_buffer.scala 426:84] + wire _T_3220 = buf_rspageQ_0[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3222 = _T_3220 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3210 = _T_2814 | _T_1814; // @[lsu_bus_buffer.scala 426:110] + wire _T_3211 = ~_T_3210; // @[lsu_bus_buffer.scala 426:84] + wire _T_3212 = buf_rspageQ_0[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3214 = _T_3212 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3202 = _T_2792 | _T_1803; // @[lsu_bus_buffer.scala 426:110] + wire _T_3203 = ~_T_3202; // @[lsu_bus_buffer.scala 426:84] + wire _T_3204 = buf_rspageQ_0[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3206 = _T_3204 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3194 = _T_2770 | _T_1792; // @[lsu_bus_buffer.scala 426:110] + wire _T_3195 = ~_T_3194; // @[lsu_bus_buffer.scala 426:84] + wire _T_3196 = buf_rspageQ_0[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3198 = _T_3196 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_0 = {_T_3222,_T_3214,_T_3206,_T_3198}; // @[Cat.scala 29:58] + wire _T_3133 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3136 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3139 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3142 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3144 = {_T_3142,_T_3139,_T_3136}; // @[Cat.scala 29:58] + wire _T_3255 = buf_rspageQ_1[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3257 = _T_3255 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3247 = buf_rspageQ_1[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3249 = _T_3247 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3239 = buf_rspageQ_1[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3241 = _T_3239 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3231 = buf_rspageQ_1[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3233 = _T_3231 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_1 = {_T_3257,_T_3249,_T_3241,_T_3233}; // @[Cat.scala 29:58] + wire _T_3148 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3151 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3154 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3157 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3159 = {_T_3157,_T_3154,_T_3151}; // @[Cat.scala 29:58] + wire _T_3290 = buf_rspageQ_2[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3292 = _T_3290 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3282 = buf_rspageQ_2[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3284 = _T_3282 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3274 = buf_rspageQ_2[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3276 = _T_3274 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3266 = buf_rspageQ_2[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3268 = _T_3266 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_2 = {_T_3292,_T_3284,_T_3276,_T_3268}; // @[Cat.scala 29:58] + wire _T_3163 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3166 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3169 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3172 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3174 = {_T_3172,_T_3169,_T_3166}; // @[Cat.scala 29:58] + wire _T_3325 = buf_rspageQ_3[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3327 = _T_3325 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3317 = buf_rspageQ_3[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3319 = _T_3317 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3309 = buf_rspageQ_3[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3311 = _T_3309 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3301 = buf_rspageQ_3[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3303 = _T_3301 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_3 = {_T_3327,_T_3319,_T_3311,_T_3303}; // @[Cat.scala 29:58] + wire _T_3178 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3181 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3184 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3187 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3189 = {_T_3187,_T_3184,_T_3181}; // @[Cat.scala 29:58] + wire _T_3332 = ibuf_drain_vld & _T_1793; // @[lsu_bus_buffer.scala 427:63] + wire _T_3334 = ibuf_drain_vld & _T_1804; // @[lsu_bus_buffer.scala 427:63] + wire _T_3336 = ibuf_drain_vld & _T_1815; // @[lsu_bus_buffer.scala 427:63] + wire _T_3338 = ibuf_drain_vld & _T_1826; // @[lsu_bus_buffer.scala 427:63] + wire [3:0] ibuf_drainvec_vld = {_T_3338,_T_3336,_T_3334,_T_3332}; // @[Cat.scala 29:58] + wire _T_3346 = _T_3540 & _T_1796; // @[lsu_bus_buffer.scala 429:35] + wire _T_3355 = _T_3540 & _T_1807; // @[lsu_bus_buffer.scala 429:35] + wire _T_3364 = _T_3540 & _T_1818; // @[lsu_bus_buffer.scala 429:35] + wire _T_3373 = _T_3540 & _T_1829; // @[lsu_bus_buffer.scala 429:35] + wire _T_3403 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3405 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3407 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3409 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire [3:0] buf_dual_in = {_T_3409,_T_3407,_T_3405,_T_3403}; // @[Cat.scala 29:58] + wire _T_3414 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3416 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3418 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3420 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire [3:0] buf_samedw_in = {_T_3420,_T_3418,_T_3416,_T_3414}; // @[Cat.scala 29:58] + wire _T_3425 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 433:84] + wire _T_3426 = ibuf_drainvec_vld[0] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3429 = ibuf_drainvec_vld[1] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3432 = ibuf_drainvec_vld[2] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3435 = ibuf_drainvec_vld[3] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire [3:0] buf_nomerge_in = {_T_3435,_T_3432,_T_3429,_T_3426}; // @[Cat.scala 29:58] + wire _T_3443 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3346; // @[lsu_bus_buffer.scala 434:47] + wire _T_3448 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3355; // @[lsu_bus_buffer.scala 434:47] + wire _T_3453 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3364; // @[lsu_bus_buffer.scala 434:47] + wire _T_3458 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3373; // @[lsu_bus_buffer.scala 434:47] + wire [3:0] buf_dualhi_in = {_T_3458,_T_3453,_T_3448,_T_3443}; // @[Cat.scala 29:58] + wire _T_3487 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3489 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3491 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3493 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire [3:0] buf_sideeffect_in = {_T_3493,_T_3491,_T_3489,_T_3487}; // @[Cat.scala 29:58] + wire _T_3498 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3500 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3502 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3504 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire [3:0] buf_unsign_in = {_T_3504,_T_3502,_T_3500,_T_3498}; // @[Cat.scala 29:58] + wire _T_3521 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3523 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3525 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3527 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire [3:0] buf_write_in = {_T_3527,_T_3525,_T_3523,_T_3521}; // @[Cat.scala 29:58] + wire _T_3560 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 459:89] + wire _T_3562 = _T_3560 & _T_1349; // @[lsu_bus_buffer.scala 459:104] + wire _T_3575 = buf_state_en_0 & _T_3645; // @[lsu_bus_buffer.scala 464:44] + wire _T_3576 = _T_3575 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3578 = _T_3576 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3581 = _T_3571 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3582 = _T_3581 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_4841 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 576:64] + wire bus_rsp_read_error = bus_rsp_read & _T_4841; // @[lsu_bus_buffer.scala 576:38] + wire _T_3585 = _T_3581 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_3659 = bus_rsp_read_error & _T_3638; // @[lsu_bus_buffer.scala 482:91] + wire _T_3661 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 483:31] + wire _T_3663 = _T_3661 & _T_3640; // @[lsu_bus_buffer.scala 483:46] + wire _T_3664 = _T_3659 | _T_3663; // @[lsu_bus_buffer.scala 482:143] + wire _T_4839 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 575:66] + wire bus_rsp_write_error = bus_rsp_write & _T_4839; // @[lsu_bus_buffer.scala 575:40] + wire _T_3666 = bus_rsp_write_error & _T_3636; // @[lsu_bus_buffer.scala 484:33] + wire _T_3667 = _T_3664 | _T_3666; // @[lsu_bus_buffer.scala 483:88] + wire _T_3668 = _T_3571 & _T_3667; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_56 = _T_3592 & _T_3668; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_3558 ? _T_3585 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_82 = _T_3554 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_error_en_0 = _T_3531 ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58] + wire _T_3594 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 472:75] + wire _T_3595 = buf_write[0] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3596 = io_dec_tlu_force_halt | _T_3595; // @[lsu_bus_buffer.scala 472:57] + wire _T_3598 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 473:30] + wire _T_3599 = buf_dual_0 & _T_3598; // @[lsu_bus_buffer.scala 473:28] + wire _T_3602 = _T_3599 & _T_3645; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_29 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_30 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_29; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_31 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_30; // @[lsu_bus_buffer.scala 473:90] + wire _T_3603 = _GEN_31 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3604 = _T_3602 & _T_3603; // @[lsu_bus_buffer.scala 473:61] + wire _T_4489 = _T_2717 | _T_2714; // @[lsu_bus_buffer.scala 536:93] + wire _T_4490 = _T_4489 | _T_2711; // @[lsu_bus_buffer.scala 536:93] + wire any_done_wait_state = _T_4490 | _T_2708; // @[lsu_bus_buffer.scala 536:93] + wire _T_3606 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3612 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3614 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3616 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_3618 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_3620 = _T_3612 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3621 = _T_3614 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3622 = _T_3616 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3623 = _T_3618 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3624 = _T_3620 | _T_3621; // @[Mux.scala 27:72] + wire _T_3625 = _T_3624 | _T_3622; // @[Mux.scala 27:72] + wire _T_3626 = _T_3625 | _T_3623; // @[Mux.scala 27:72] + wire _T_3628 = _T_3602 & _T_3626; // @[lsu_bus_buffer.scala 474:101] + wire _T_3629 = _GEN_31 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_3630 = _T_3628 & _T_3629; // @[lsu_bus_buffer.scala 474:138] + wire _T_3631 = _T_3630 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_3632 = _T_3606 | _T_3631; // @[lsu_bus_buffer.scala 474:53] + wire _T_3655 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_3656 = _T_3655 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_3669 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 485:50] + wire _T_3670 = buf_state_en_0 & _T_3669; // @[lsu_bus_buffer.scala 485:48] + wire _T_3682 = buf_ldfwd[0] | _T_3687[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_3683 = _T_3682 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_39 = _T_3703 ? buf_state_en_0 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_3695 ? io_dec_tlu_force_halt : _T_3703; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_3695 ? io_dec_tlu_force_halt : _GEN_39; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_3677 ? io_dec_tlu_force_halt : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_3677 ? io_dec_tlu_force_halt : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_3592 & _T_3656; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_3592 ? io_dec_tlu_force_halt : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_3592 ? io_dec_tlu_force_halt : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_3558 ? _T_3578 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_3558 ? _T_3582 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_3558 ? io_dec_tlu_force_halt : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_3554 ? io_dec_tlu_force_halt : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_3554 ? io_dec_tlu_force_halt : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_3554 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67] + wire buf_wr_en_0 = _T_3531 & buf_state_en_0; // @[Conditional.scala 40:58] + wire buf_data_en_0 = _T_3531 ? buf_state_en_0 : _GEN_81; // @[Conditional.scala 40:58] + wire buf_rst_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_76; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_79; // @[Conditional.scala 40:58] + wire _T_3766 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 464:44] + wire _T_3767 = _T_3766 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3769 = _T_3767 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3772 = _T_3762 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3773 = _T_3772 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_3776 = _T_3772 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 482:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 483:31] + wire _T_3854 = _T_3852 & _T_3831; // @[lsu_bus_buffer.scala 483:46] + wire _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 482:143] + wire _T_3857 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 484:33] + wire _T_3858 = _T_3855 | _T_3857; // @[lsu_bus_buffer.scala 483:88] + wire _T_3859 = _T_3762 & _T_3858; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_132 = _T_3783 & _T_3859; // @[Conditional.scala 39:67] + wire _GEN_145 = _T_3749 ? _T_3776 : _GEN_132; // @[Conditional.scala 39:67] + wire _GEN_158 = _T_3745 ? 1'h0 : _GEN_145; // @[Conditional.scala 39:67] + wire buf_error_en_1 = _T_3722 ? 1'h0 : _GEN_158; // @[Conditional.scala 40:58] + wire _T_3786 = buf_write[1] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 472:57] + wire _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 473:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 473:28] + wire _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_105 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_106 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_105; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_107 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_106; // @[lsu_bus_buffer.scala 473:90] + wire _T_3794 = _GEN_107 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 473:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_3809 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] + wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] + wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] + wire _T_3819 = _T_3793 & _T_3817; // @[lsu_bus_buffer.scala 474:101] + wire _T_3820 = _GEN_107 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 474:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 474:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_3860 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 485:50] + wire _T_3861 = buf_state_en_1 & _T_3860; // @[lsu_bus_buffer.scala 485:48] + wire _T_3873 = buf_ldfwd[1] | _T_3878[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_3874 = _T_3873 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_115 = _T_3894 ? buf_state_en_1 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_119 = _T_3886 ? io_dec_tlu_force_halt : _T_3894; // @[Conditional.scala 39:67] + wire _GEN_120 = _T_3886 ? io_dec_tlu_force_halt : _GEN_115; // @[Conditional.scala 39:67] + wire _GEN_125 = _T_3868 ? io_dec_tlu_force_halt : _GEN_119; // @[Conditional.scala 39:67] + wire _GEN_126 = _T_3868 ? io_dec_tlu_force_halt : _GEN_120; // @[Conditional.scala 39:67] + wire _GEN_131 = _T_3783 & _T_3847; // @[Conditional.scala 39:67] + wire _GEN_135 = _T_3783 ? io_dec_tlu_force_halt : _GEN_125; // @[Conditional.scala 39:67] + wire _GEN_136 = _T_3783 ? io_dec_tlu_force_halt : _GEN_126; // @[Conditional.scala 39:67] + wire _GEN_142 = _T_3749 ? _T_3769 : _GEN_136; // @[Conditional.scala 39:67] + wire _GEN_144 = _T_3749 ? _T_3773 : _GEN_131; // @[Conditional.scala 39:67] + wire _GEN_147 = _T_3749 ? io_dec_tlu_force_halt : _GEN_135; // @[Conditional.scala 39:67] + wire _GEN_152 = _T_3745 ? io_dec_tlu_force_halt : _GEN_147; // @[Conditional.scala 39:67] + wire _GEN_155 = _T_3745 ? io_dec_tlu_force_halt : _GEN_142; // @[Conditional.scala 39:67] + wire _GEN_157 = _T_3745 ? 1'h0 : _GEN_144; // @[Conditional.scala 39:67] + wire buf_wr_en_1 = _T_3722 & buf_state_en_1; // @[Conditional.scala 40:58] + wire buf_data_en_1 = _T_3722 ? buf_state_en_1 : _GEN_157; // @[Conditional.scala 40:58] + wire buf_rst_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_152; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_155; // @[Conditional.scala 40:58] + wire _T_3957 = buf_state_en_2 & _T_4027; // @[lsu_bus_buffer.scala 464:44] + wire _T_3958 = _T_3957 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3960 = _T_3958 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3963 = _T_3953 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3964 = _T_3963 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_3967 = _T_3963 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_4041 = bus_rsp_read_error & _T_4020; // @[lsu_bus_buffer.scala 482:91] + wire _T_4043 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 483:31] + wire _T_4045 = _T_4043 & _T_4022; // @[lsu_bus_buffer.scala 483:46] + wire _T_4046 = _T_4041 | _T_4045; // @[lsu_bus_buffer.scala 482:143] + wire _T_4048 = bus_rsp_write_error & _T_4018; // @[lsu_bus_buffer.scala 484:33] + wire _T_4049 = _T_4046 | _T_4048; // @[lsu_bus_buffer.scala 483:88] + wire _T_4050 = _T_3953 & _T_4049; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_208 = _T_3974 & _T_4050; // @[Conditional.scala 39:67] + wire _GEN_221 = _T_3940 ? _T_3967 : _GEN_208; // @[Conditional.scala 39:67] + wire _GEN_234 = _T_3936 ? 1'h0 : _GEN_221; // @[Conditional.scala 39:67] + wire buf_error_en_2 = _T_3913 ? 1'h0 : _GEN_234; // @[Conditional.scala 40:58] + wire _T_3977 = buf_write[2] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3978 = io_dec_tlu_force_halt | _T_3977; // @[lsu_bus_buffer.scala 472:57] + wire _T_3980 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 473:30] + wire _T_3981 = buf_dual_2 & _T_3980; // @[lsu_bus_buffer.scala 473:28] + wire _T_3984 = _T_3981 & _T_4027; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_181 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_182 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_181; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_183 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_182; // @[lsu_bus_buffer.scala 473:90] + wire _T_3985 = _GEN_183 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3986 = _T_3984 & _T_3985; // @[lsu_bus_buffer.scala 473:61] + wire _T_3988 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3994 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3996 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3998 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_4000 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_4002 = _T_3994 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4003 = _T_3996 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4004 = _T_3998 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4005 = _T_4000 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4006 = _T_4002 | _T_4003; // @[Mux.scala 27:72] + wire _T_4007 = _T_4006 | _T_4004; // @[Mux.scala 27:72] + wire _T_4008 = _T_4007 | _T_4005; // @[Mux.scala 27:72] + wire _T_4010 = _T_3984 & _T_4008; // @[lsu_bus_buffer.scala 474:101] + wire _T_4011 = _GEN_183 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_4012 = _T_4010 & _T_4011; // @[lsu_bus_buffer.scala 474:138] + wire _T_4013 = _T_4012 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_4014 = _T_3988 | _T_4013; // @[lsu_bus_buffer.scala 474:53] + wire _T_4037 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_4038 = _T_4037 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_4051 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 485:50] + wire _T_4052 = buf_state_en_2 & _T_4051; // @[lsu_bus_buffer.scala 485:48] + wire _T_4064 = buf_ldfwd[2] | _T_4069[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_4065 = _T_4064 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_191 = _T_4085 ? buf_state_en_2 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_195 = _T_4077 ? io_dec_tlu_force_halt : _T_4085; // @[Conditional.scala 39:67] + wire _GEN_196 = _T_4077 ? io_dec_tlu_force_halt : _GEN_191; // @[Conditional.scala 39:67] + wire _GEN_201 = _T_4059 ? io_dec_tlu_force_halt : _GEN_195; // @[Conditional.scala 39:67] + wire _GEN_202 = _T_4059 ? io_dec_tlu_force_halt : _GEN_196; // @[Conditional.scala 39:67] + wire _GEN_207 = _T_3974 & _T_4038; // @[Conditional.scala 39:67] + wire _GEN_211 = _T_3974 ? io_dec_tlu_force_halt : _GEN_201; // @[Conditional.scala 39:67] + wire _GEN_212 = _T_3974 ? io_dec_tlu_force_halt : _GEN_202; // @[Conditional.scala 39:67] + wire _GEN_218 = _T_3940 ? _T_3960 : _GEN_212; // @[Conditional.scala 39:67] + wire _GEN_220 = _T_3940 ? _T_3964 : _GEN_207; // @[Conditional.scala 39:67] + wire _GEN_223 = _T_3940 ? io_dec_tlu_force_halt : _GEN_211; // @[Conditional.scala 39:67] + wire _GEN_228 = _T_3936 ? io_dec_tlu_force_halt : _GEN_223; // @[Conditional.scala 39:67] + wire _GEN_231 = _T_3936 ? io_dec_tlu_force_halt : _GEN_218; // @[Conditional.scala 39:67] + wire _GEN_233 = _T_3936 ? 1'h0 : _GEN_220; // @[Conditional.scala 39:67] + wire buf_wr_en_2 = _T_3913 & buf_state_en_2; // @[Conditional.scala 40:58] + wire buf_data_en_2 = _T_3913 ? buf_state_en_2 : _GEN_233; // @[Conditional.scala 40:58] + wire buf_rst_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_228; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_231; // @[Conditional.scala 40:58] + wire _T_4148 = buf_state_en_3 & _T_4218; // @[lsu_bus_buffer.scala 464:44] + wire _T_4149 = _T_4148 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_4151 = _T_4149 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_4154 = _T_4144 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_4155 = _T_4154 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_4158 = _T_4154 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_4232 = bus_rsp_read_error & _T_4211; // @[lsu_bus_buffer.scala 482:91] + wire _T_4234 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 483:31] + wire _T_4236 = _T_4234 & _T_4213; // @[lsu_bus_buffer.scala 483:46] + wire _T_4237 = _T_4232 | _T_4236; // @[lsu_bus_buffer.scala 482:143] + wire _T_4239 = bus_rsp_write_error & _T_4209; // @[lsu_bus_buffer.scala 484:33] + wire _T_4240 = _T_4237 | _T_4239; // @[lsu_bus_buffer.scala 483:88] + wire _T_4241 = _T_4144 & _T_4240; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_284 = _T_4165 & _T_4241; // @[Conditional.scala 39:67] + wire _GEN_297 = _T_4131 ? _T_4158 : _GEN_284; // @[Conditional.scala 39:67] + wire _GEN_310 = _T_4127 ? 1'h0 : _GEN_297; // @[Conditional.scala 39:67] + wire buf_error_en_3 = _T_4104 ? 1'h0 : _GEN_310; // @[Conditional.scala 40:58] + wire _T_4168 = buf_write[3] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_4169 = io_dec_tlu_force_halt | _T_4168; // @[lsu_bus_buffer.scala 472:57] + wire _T_4171 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 473:30] + wire _T_4172 = buf_dual_3 & _T_4171; // @[lsu_bus_buffer.scala 473:28] + wire _T_4175 = _T_4172 & _T_4218; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_257 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_258 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_257; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_259 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_258; // @[lsu_bus_buffer.scala 473:90] + wire _T_4176 = _GEN_259 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_4177 = _T_4175 & _T_4176; // @[lsu_bus_buffer.scala 473:61] + wire _T_4179 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_4185 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_4187 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_4189 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_4191 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_4193 = _T_4185 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4194 = _T_4187 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4195 = _T_4189 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4196 = _T_4191 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4197 = _T_4193 | _T_4194; // @[Mux.scala 27:72] + wire _T_4198 = _T_4197 | _T_4195; // @[Mux.scala 27:72] + wire _T_4199 = _T_4198 | _T_4196; // @[Mux.scala 27:72] + wire _T_4201 = _T_4175 & _T_4199; // @[lsu_bus_buffer.scala 474:101] + wire _T_4202 = _GEN_259 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_4203 = _T_4201 & _T_4202; // @[lsu_bus_buffer.scala 474:138] + wire _T_4204 = _T_4203 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_4205 = _T_4179 | _T_4204; // @[lsu_bus_buffer.scala 474:53] + wire _T_4228 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_4229 = _T_4228 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_4242 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 485:50] + wire _T_4243 = buf_state_en_3 & _T_4242; // @[lsu_bus_buffer.scala 485:48] + wire _T_4255 = buf_ldfwd[3] | _T_4260[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_4256 = _T_4255 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_267 = _T_4276 ? buf_state_en_3 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_271 = _T_4268 ? io_dec_tlu_force_halt : _T_4276; // @[Conditional.scala 39:67] + wire _GEN_272 = _T_4268 ? io_dec_tlu_force_halt : _GEN_267; // @[Conditional.scala 39:67] + wire _GEN_277 = _T_4250 ? io_dec_tlu_force_halt : _GEN_271; // @[Conditional.scala 39:67] + wire _GEN_278 = _T_4250 ? io_dec_tlu_force_halt : _GEN_272; // @[Conditional.scala 39:67] + wire _GEN_283 = _T_4165 & _T_4229; // @[Conditional.scala 39:67] + wire _GEN_287 = _T_4165 ? io_dec_tlu_force_halt : _GEN_277; // @[Conditional.scala 39:67] + wire _GEN_288 = _T_4165 ? io_dec_tlu_force_halt : _GEN_278; // @[Conditional.scala 39:67] + wire _GEN_294 = _T_4131 ? _T_4151 : _GEN_288; // @[Conditional.scala 39:67] + wire _GEN_296 = _T_4131 ? _T_4155 : _GEN_283; // @[Conditional.scala 39:67] + wire _GEN_299 = _T_4131 ? io_dec_tlu_force_halt : _GEN_287; // @[Conditional.scala 39:67] + wire _GEN_304 = _T_4127 ? io_dec_tlu_force_halt : _GEN_299; // @[Conditional.scala 39:67] + wire _GEN_307 = _T_4127 ? io_dec_tlu_force_halt : _GEN_294; // @[Conditional.scala 39:67] + wire _GEN_309 = _T_4127 ? 1'h0 : _GEN_296; // @[Conditional.scala 39:67] + wire buf_wr_en_3 = _T_4104 & buf_state_en_3; // @[Conditional.scala 40:58] + wire buf_data_en_3 = _T_4104 ? buf_state_en_3 : _GEN_309; // @[Conditional.scala 40:58] + wire buf_rst_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_304; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_307; // @[Conditional.scala 40:58] + reg _T_4331; // @[Reg.scala 27:20] + reg _T_4334; // @[Reg.scala 27:20] + reg _T_4337; // @[Reg.scala 27:20] + reg _T_4340; // @[Reg.scala 27:20] + wire [3:0] buf_unsign = {_T_4340,_T_4337,_T_4334,_T_4331}; // @[Cat.scala 29:58] + wire _T_4387 = ~buf_rst_0; // @[lsu_bus_buffer.scala 531:81] + reg _T_4406; // @[lsu_bus_buffer.scala 531:80] + reg _T_4401; // @[lsu_bus_buffer.scala 531:80] + reg _T_4396; // @[lsu_bus_buffer.scala 531:80] + reg _T_4391; // @[lsu_bus_buffer.scala 531:80] + wire [3:0] buf_error = {_T_4406,_T_4401,_T_4396,_T_4391}; // @[Cat.scala 29:58] + wire _T_4389 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4392 = ~buf_rst_1; // @[lsu_bus_buffer.scala 531:81] + wire _T_4394 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4397 = ~buf_rst_2; // @[lsu_bus_buffer.scala 531:81] + wire _T_4399 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4402 = ~buf_rst_3; // @[lsu_bus_buffer.scala 531:81] + wire _T_4404 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 531:98] + wire [1:0] _T_4410 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4411 = io_ldst_dual_m ? _T_4410 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 532:28] + wire [1:0] _T_4412 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4413 = io_ldst_dual_r ? _T_4412 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 532:94] + wire [2:0] _T_4414 = _T_4411 + _T_4413; // @[lsu_bus_buffer.scala 532:88] + wire [2:0] _GEN_406 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 532:154] + wire [3:0] _T_4415 = _T_4414 + _GEN_406; // @[lsu_bus_buffer.scala 532:154] + wire [1:0] _T_4420 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 532:217] + wire [1:0] _GEN_407 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 532:217] + wire [2:0] _T_4421 = _T_4420 + _GEN_407; // @[lsu_bus_buffer.scala 532:217] + wire [2:0] _GEN_408 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 532:217] + wire [3:0] _T_4422 = _T_4421 + _GEN_408; // @[lsu_bus_buffer.scala 532:217] + wire [3:0] buf_numvld_any = _T_4415 + _T_4422; // @[lsu_bus_buffer.scala 532:169] + wire _T_4493 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 538:52] + wire _T_4494 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 538:92] + wire _T_4495 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 538:121] + wire _T_4497 = |buf_state_0; // @[lsu_bus_buffer.scala 539:52] + wire _T_4498 = |buf_state_1; // @[lsu_bus_buffer.scala 539:52] + wire _T_4499 = |buf_state_2; // @[lsu_bus_buffer.scala 539:52] + wire _T_4500 = |buf_state_3; // @[lsu_bus_buffer.scala 539:52] + wire _T_4501 = _T_4497 | _T_4498; // @[lsu_bus_buffer.scala 539:65] + wire _T_4502 = _T_4501 | _T_4499; // @[lsu_bus_buffer.scala 539:65] + wire _T_4503 = _T_4502 | _T_4500; // @[lsu_bus_buffer.scala 539:65] + wire _T_4504 = ~_T_4503; // @[lsu_bus_buffer.scala 539:34] + wire _T_4506 = _T_4504 & _T_852; // @[lsu_bus_buffer.scala 539:70] + wire _T_4509 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 541:64] + wire _T_4510 = _T_4509 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 541:85] + wire _T_4511 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 541:112] + wire _T_4512 = _T_4510 & _T_4511; // @[lsu_bus_buffer.scala 541:110] + wire _T_4513 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 541:129] + wire _T_4515 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 544:74] + reg lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 629:66] + wire _T_4529 = _T_2770 & _T_3645; // @[Mux.scala 27:72] + wire _T_4530 = _T_2792 & _T_3836; // @[Mux.scala 27:72] + wire _T_4531 = _T_2814 & _T_4027; // @[Mux.scala 27:72] + wire _T_4532 = _T_2836 & _T_4218; // @[Mux.scala 27:72] + wire _T_4533 = _T_4529 | _T_4530; // @[Mux.scala 27:72] + wire _T_4534 = _T_4533 | _T_4531; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4534 | _T_4532; // @[Mux.scala 27:72] + wire _T_4540 = buf_error[0] & _T_3645; // @[lsu_bus_buffer.scala 547:121] + wire _T_4545 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 547:121] + wire _T_4550 = buf_error[2] & _T_4027; // @[lsu_bus_buffer.scala 547:121] + wire _T_4555 = buf_error[3] & _T_4218; // @[lsu_bus_buffer.scala 547:121] + wire _T_4556 = _T_2770 & _T_4540; // @[Mux.scala 27:72] + wire _T_4557 = _T_2792 & _T_4545; // @[Mux.scala 27:72] + wire _T_4558 = _T_2814 & _T_4550; // @[Mux.scala 27:72] + wire _T_4559 = _T_2836 & _T_4555; // @[Mux.scala 27:72] + wire _T_4560 = _T_4556 | _T_4557; // @[Mux.scala 27:72] + wire _T_4561 = _T_4560 | _T_4558; // @[Mux.scala 27:72] + wire _T_4568 = ~buf_dual_0; // @[lsu_bus_buffer.scala 548:121] + wire _T_4569 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 548:136] + wire _T_4570 = _T_4568 | _T_4569; // @[lsu_bus_buffer.scala 548:134] + wire _T_4571 = _T_4529 & _T_4570; // @[lsu_bus_buffer.scala 548:118] + wire _T_4576 = ~buf_dual_1; // @[lsu_bus_buffer.scala 548:121] + wire _T_4577 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 548:136] + wire _T_4578 = _T_4576 | _T_4577; // @[lsu_bus_buffer.scala 548:134] + wire _T_4579 = _T_4530 & _T_4578; // @[lsu_bus_buffer.scala 548:118] + wire _T_4584 = ~buf_dual_2; // @[lsu_bus_buffer.scala 548:121] + wire _T_4585 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 548:136] + wire _T_4586 = _T_4584 | _T_4585; // @[lsu_bus_buffer.scala 548:134] + wire _T_4587 = _T_4531 & _T_4586; // @[lsu_bus_buffer.scala 548:118] + wire _T_4592 = ~buf_dual_3; // @[lsu_bus_buffer.scala 548:121] + wire _T_4593 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 548:136] + wire _T_4594 = _T_4592 | _T_4593; // @[lsu_bus_buffer.scala 548:134] + wire _T_4595 = _T_4532 & _T_4594; // @[lsu_bus_buffer.scala 548:118] + wire [1:0] _T_4598 = _T_4587 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4599 = _T_4595 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_409 = {{1'd0}, _T_4579}; // @[Mux.scala 27:72] + wire [1:0] _T_4601 = _GEN_409 | _T_4598; // @[Mux.scala 27:72] + wire [31:0] _T_4636 = _T_4571 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4637 = _T_4579 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4638 = _T_4587 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4639 = _T_4595 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4640 = _T_4636 | _T_4637; // @[Mux.scala 27:72] + wire [31:0] _T_4641 = _T_4640 | _T_4638; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_lo = _T_4641 | _T_4639; // @[Mux.scala 27:72] + wire _T_4648 = _T_4529 & _T_3643; // @[lsu_bus_buffer.scala 550:105] + wire _T_4654 = _T_4530 & _T_3834; // @[lsu_bus_buffer.scala 550:105] + wire _T_4660 = _T_4531 & _T_4025; // @[lsu_bus_buffer.scala 550:105] + wire _T_4666 = _T_4532 & _T_4216; // @[lsu_bus_buffer.scala 550:105] + wire [31:0] _T_4667 = _T_4648 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4668 = _T_4654 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4669 = _T_4660 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4670 = _T_4666 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4671 = _T_4667 | _T_4668; // @[Mux.scala 27:72] + wire [31:0] _T_4672 = _T_4671 | _T_4669; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_hi = _T_4672 | _T_4670; // @[Mux.scala 27:72] + wire _T_4674 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 62:123] + wire _T_4675 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 62:123] + wire _T_4676 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 62:123] + wire _T_4677 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 62:123] + wire [31:0] _T_4678 = _T_4674 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4679 = _T_4675 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4680 = _T_4676 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4681 = _T_4677 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4682 = _T_4678 | _T_4679; // @[Mux.scala 27:72] + wire [31:0] _T_4683 = _T_4682 | _T_4680; // @[Mux.scala 27:72] + wire [31:0] _T_4684 = _T_4683 | _T_4681; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_addr_offset = _T_4684[1:0]; // @[lsu_bus_buffer.scala 551:96] + wire [1:0] _T_4690 = _T_4674 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4691 = _T_4675 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4692 = _T_4676 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4693 = _T_4677 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4694 = _T_4690 | _T_4691; // @[Mux.scala 27:72] + wire [1:0] _T_4695 = _T_4694 | _T_4692; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_sz = _T_4695 | _T_4693; // @[Mux.scala 27:72] + wire _T_4705 = _T_4674 & buf_unsign[0]; // @[Mux.scala 27:72] + wire _T_4706 = _T_4675 & buf_unsign[1]; // @[Mux.scala 27:72] + wire _T_4707 = _T_4676 & buf_unsign[2]; // @[Mux.scala 27:72] + wire _T_4708 = _T_4677 & buf_unsign[3]; // @[Mux.scala 27:72] + wire _T_4709 = _T_4705 | _T_4706; // @[Mux.scala 27:72] + wire _T_4710 = _T_4709 | _T_4707; // @[Mux.scala 27:72] + wire lsu_nonblock_unsign = _T_4710 | _T_4708; // @[Mux.scala 27:72] + wire [63:0] _T_4712 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] + wire [3:0] _GEN_410 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 555:121] + wire [5:0] _T_4713 = _GEN_410 * 4'h8; // @[lsu_bus_buffer.scala 555:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4712 >> _T_4713; // @[lsu_bus_buffer.scala 555:92] + wire _T_4714 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 557:82] + wire _T_4716 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 558:81] + wire _T_4717 = lsu_nonblock_unsign & _T_4716; // @[lsu_bus_buffer.scala 558:63] + wire [31:0] _T_4719 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4720 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 559:45] + wire _T_4721 = lsu_nonblock_unsign & _T_4720; // @[lsu_bus_buffer.scala 559:26] + wire [31:0] _T_4723 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4724 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 560:6] + wire _T_4726 = _T_4724 & _T_4716; // @[lsu_bus_buffer.scala 560:27] + wire [23:0] _T_4729 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4731 = {_T_4729,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4734 = _T_4724 & _T_4720; // @[lsu_bus_buffer.scala 561:27] + wire [15:0] _T_4737 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4739 = {_T_4737,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4740 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 562:21] + wire [31:0] _T_4741 = _T_4717 ? _T_4719 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4742 = _T_4721 ? _T_4723 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4743 = _T_4726 ? _T_4731 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4744 = _T_4734 ? _T_4739 : 32'h0; // @[Mux.scala 27:72] + wire [63:0] _T_4745 = _T_4740 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4746 = _T_4741 | _T_4742; // @[Mux.scala 27:72] + wire [31:0] _T_4747 = _T_4746 | _T_4743; // @[Mux.scala 27:72] + wire [31:0] _T_4748 = _T_4747 | _T_4744; // @[Mux.scala 27:72] + wire [63:0] _GEN_411 = {{32'd0}, _T_4748}; // @[Mux.scala 27:72] + wire [63:0] _T_4749 = _GEN_411 | _T_4745; // @[Mux.scala 27:72] + wire _T_4843 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 580:37] + wire _T_4844 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 580:52] + wire _T_4845 = _T_4843 & _T_4844; // @[lsu_bus_buffer.scala 580:50] + wire [31:0] _T_4849 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] + wire [2:0] _T_4851 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] + wire _T_4856 = ~obuf_data_done; // @[lsu_bus_buffer.scala 592:51] + wire _T_4857 = _T_4843 & _T_4856; // @[lsu_bus_buffer.scala 592:49] + wire [7:0] _T_4861 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire _T_4864 = obuf_valid & _T_1341; // @[lsu_bus_buffer.scala 597:37] + wire _T_4866 = _T_4864 & _T_1347; // @[lsu_bus_buffer.scala 597:51] + wire _T_4878 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4880 = _T_4878 & buf_write[0]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4883 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4885 = _T_4883 & buf_write[1]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4888 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4890 = _T_4888 & buf_write[2]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4893 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4895 = _T_4893 & buf_write[3]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4896 = _T_2770 & _T_4880; // @[Mux.scala 27:72] + wire _T_4897 = _T_2792 & _T_4885; // @[Mux.scala 27:72] + wire _T_4898 = _T_2814 & _T_4890; // @[Mux.scala 27:72] + wire _T_4899 = _T_2836 & _T_4895; // @[Mux.scala 27:72] + wire _T_4900 = _T_4896 | _T_4897; // @[Mux.scala 27:72] + wire _T_4901 = _T_4900 | _T_4898; // @[Mux.scala 27:72] + wire _T_4911 = _T_2792 & buf_error[1]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4913 = _T_4911 & buf_write[1]; // @[lsu_bus_buffer.scala 611:108] + wire _T_4916 = _T_2814 & buf_error[2]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4918 = _T_4916 & buf_write[2]; // @[lsu_bus_buffer.scala 611:108] + wire _T_4921 = _T_2836 & buf_error[3]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4923 = _T_4921 & buf_write[3]; // @[lsu_bus_buffer.scala 611:108] + wire [1:0] _T_4926 = _T_4918 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4927 = _T_4923 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_412 = {{1'd0}, _T_4913}; // @[Mux.scala 27:72] + wire [1:0] _T_4929 = _GEN_412 | _T_4926; // @[Mux.scala 27:72] + wire [1:0] lsu_imprecise_error_store_tag = _T_4929 | _T_4927; // @[Mux.scala 27:72] + wire _T_4931 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 613:97] + wire [31:0] _GEN_369 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_370 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_369; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_371 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_370; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_373 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_374 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_373; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_375 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_374; // @[lsu_bus_buffer.scala 614:53] + wire _T_4936 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 620:82] + wire _T_4939 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 621:60] + wire _T_4942 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 624:61] + wire _T_4943 = io_lsu_axi_aw_valid & _T_4942; // @[lsu_bus_buffer.scala 624:59] + wire _T_4944 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 624:107] + wire _T_4945 = io_lsu_axi_w_valid & _T_4944; // @[lsu_bus_buffer.scala 624:105] + wire _T_4946 = _T_4943 | _T_4945; // @[lsu_bus_buffer.scala 624:83] + wire _T_4947 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 624:153] + wire _T_4948 = io_lsu_axi_ar_valid & _T_4947; // @[lsu_bus_buffer.scala 624:151] + wire _T_4952 = ~io_flush_r; // @[lsu_bus_buffer.scala 628:75] + wire _T_4953 = io_lsu_busreq_m & _T_4952; // @[lsu_bus_buffer.scala 628:73] + reg _T_4956; // @[lsu_bus_buffer.scala 628:56] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4936 | _T_4835; // @[lsu_bus_buffer.scala 620:35] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4939 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 621:41] + assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 622:36] + assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4946 | _T_4948; // @[lsu_bus_buffer.scala 624:35] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4931; // @[lsu_bus_buffer.scala 613:47] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4901 | _T_4899; // @[lsu_bus_buffer.scala 610:48] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_371 : _GEN_375; // @[lsu_bus_buffer.scala 614:47] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4512 & _T_4513; // @[lsu_bus_buffer.scala 541:45] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1802 ? 2'h0 : _T_1838; // @[lsu_bus_buffer.scala 542:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4515; // @[lsu_bus_buffer.scala 544:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 545:47] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4714; // @[lsu_bus_buffer.scala 557:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4561 | _T_4559; // @[lsu_bus_buffer.scala 547:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4601 | _T_4599; // @[lsu_bus_buffer.scala 548:45] + assign io_lsu_axi_aw_valid = _T_4845 & _T_1237; // @[lsu_bus_buffer.scala 580:23] + assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1781}; // @[lsu_bus_buffer.scala 581:25] + assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4849; // @[lsu_bus_buffer.scala 582:27] + assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 586:29] + assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4851 : 3'h3; // @[lsu_bus_buffer.scala 583:27] + assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 585:28] + assign io_lsu_axi_w_valid = _T_4857 & _T_1237; // @[lsu_bus_buffer.scala 592:22] + assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 594:26] + assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4861; // @[lsu_bus_buffer.scala 593:26] + assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 608:22] + assign io_lsu_axi_ar_valid = _T_4866 & _T_1237; // @[lsu_bus_buffer.scala 597:23] + assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1781}; // @[lsu_bus_buffer.scala 598:25] + assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4849; // @[lsu_bus_buffer.scala 599:27] + assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 603:29] + assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4851 : 3'h3; // @[lsu_bus_buffer.scala 600:27] + assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 602:28] + assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 609:22] + assign io_lsu_busreq_r = _T_4956; // @[lsu_bus_buffer.scala 628:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 537:30] + assign io_lsu_bus_buffer_full_any = _T_4493 ? _T_4494 : _T_4495; // @[lsu_bus_buffer.scala 538:30] + assign io_lsu_bus_buffer_empty_any = _T_4506 & _T_1231; // @[lsu_bus_buffer.scala 539:31] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 142:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 143:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 169:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 175:24] + assign io_lsu_nonblock_load_data = _T_4749[31:0]; // @[lsu_bus_buffer.scala 558:29] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = _T_3531 & buf_state_en_0; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = _T_3722 & buf_state_en_1; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = _T_3913 & buf_state_en_2; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = _T_4104 & buf_state_en_3; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = _T_3531 ? buf_state_en_0 : _GEN_81; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = _T_3722 ? buf_state_en_1 : _GEN_157; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = _T_3913 ? buf_state_en_2 : _GEN_233; // @[lib.scala 407:17] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_11_io_en = _T_4104 ? buf_state_en_3 : _GEN_309; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_addr_0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_4355 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_4352 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_4349 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_4346 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + buf_state_0 = _RAND_5[2:0]; + _RAND_6 = {1{`RANDOM}}; + buf_addr_1 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + buf_state_1 = _RAND_7[2:0]; + _RAND_8 = {1{`RANDOM}}; + buf_addr_2 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + buf_state_2 = _RAND_9[2:0]; + _RAND_10 = {1{`RANDOM}}; + buf_addr_3 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + buf_state_3 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + buf_byteen_3 = _RAND_12[3:0]; + _RAND_13 = {1{`RANDOM}}; + buf_byteen_2 = _RAND_13[3:0]; + _RAND_14 = {1{`RANDOM}}; + buf_byteen_1 = _RAND_14[3:0]; + _RAND_15 = {1{`RANDOM}}; + buf_byteen_0 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + buf_ageQ_3 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + _T_1781 = _RAND_17[1:0]; + _RAND_18 = {1{`RANDOM}}; + obuf_merge = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + obuf_tag1 = _RAND_19[1:0]; + _RAND_20 = {1{`RANDOM}}; + obuf_valid = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + obuf_wr_enQ = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ibuf_addr = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + ibuf_write = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + ibuf_valid = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + ibuf_byteen = _RAND_25[3:0]; + _RAND_26 = {1{`RANDOM}}; + buf_ageQ_2 = _RAND_26[3:0]; + _RAND_27 = {1{`RANDOM}}; + buf_ageQ_1 = _RAND_27[3:0]; + _RAND_28 = {1{`RANDOM}}; + buf_ageQ_0 = _RAND_28[3:0]; + _RAND_29 = {1{`RANDOM}}; + buf_data_0 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + buf_data_1 = _RAND_30[31:0]; + _RAND_31 = {1{`RANDOM}}; + buf_data_2 = _RAND_31[31:0]; + _RAND_32 = {1{`RANDOM}}; + buf_data_3 = _RAND_32[31:0]; + _RAND_33 = {1{`RANDOM}}; + ibuf_data = _RAND_33[31:0]; + _RAND_34 = {1{`RANDOM}}; + ibuf_timer = _RAND_34[2:0]; + _RAND_35 = {1{`RANDOM}}; + ibuf_sideeffect = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + WrPtr1_r = _RAND_36[1:0]; + _RAND_37 = {1{`RANDOM}}; + WrPtr0_r = _RAND_37[1:0]; + _RAND_38 = {1{`RANDOM}}; + ibuf_tag = _RAND_38[1:0]; + _RAND_39 = {1{`RANDOM}}; + ibuf_dualtag = _RAND_39[1:0]; + _RAND_40 = {1{`RANDOM}}; + ibuf_dual = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + ibuf_samedw = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + ibuf_nomerge = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + ibuf_unsign = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + ibuf_sz = _RAND_44[1:0]; + _RAND_45 = {1{`RANDOM}}; + _T_1791 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + buf_nomerge_0 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + buf_nomerge_1 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + buf_nomerge_2 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + buf_nomerge_3 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + _T_4325 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + _T_4322 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_4319 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + _T_4316 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + obuf_sideeffect = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + buf_dual_3 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + buf_dual_2 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + buf_dual_1 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + buf_dual_0 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + buf_samedw_3 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + buf_samedw_2 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + buf_samedw_1 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + buf_samedw_0 = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + obuf_write = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + obuf_cmd_done = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + obuf_data_done = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + obuf_nosend = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + obuf_addr = _RAND_67[31:0]; + _RAND_68 = {1{`RANDOM}}; + buf_sz_0 = _RAND_68[1:0]; + _RAND_69 = {1{`RANDOM}}; + buf_sz_1 = _RAND_69[1:0]; + _RAND_70 = {1{`RANDOM}}; + buf_sz_2 = _RAND_70[1:0]; + _RAND_71 = {1{`RANDOM}}; + buf_sz_3 = _RAND_71[1:0]; + _RAND_72 = {1{`RANDOM}}; + obuf_rdrsp_pend = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + obuf_rdrsp_tag = _RAND_73[2:0]; + _RAND_74 = {1{`RANDOM}}; + buf_dualhi_3 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + buf_dualhi_2 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + buf_dualhi_1 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + buf_dualhi_0 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + obuf_sz = _RAND_78[1:0]; + _RAND_79 = {1{`RANDOM}}; + obuf_byteen = _RAND_79[7:0]; + _RAND_80 = {2{`RANDOM}}; + obuf_data = _RAND_80[63:0]; + _RAND_81 = {1{`RANDOM}}; + buf_rspageQ_0 = _RAND_81[3:0]; + _RAND_82 = {1{`RANDOM}}; + buf_rspageQ_1 = _RAND_82[3:0]; + _RAND_83 = {1{`RANDOM}}; + buf_rspageQ_2 = _RAND_83[3:0]; + _RAND_84 = {1{`RANDOM}}; + buf_rspageQ_3 = _RAND_84[3:0]; + _RAND_85 = {1{`RANDOM}}; + _T_4302 = _RAND_85[0:0]; + _RAND_86 = {1{`RANDOM}}; + _T_4300 = _RAND_86[0:0]; + _RAND_87 = {1{`RANDOM}}; + _T_4298 = _RAND_87[0:0]; + _RAND_88 = {1{`RANDOM}}; + _T_4296 = _RAND_88[0:0]; + _RAND_89 = {1{`RANDOM}}; + buf_ldfwdtag_0 = _RAND_89[1:0]; + _RAND_90 = {1{`RANDOM}}; + buf_dualtag_0 = _RAND_90[1:0]; + _RAND_91 = {1{`RANDOM}}; + buf_ldfwdtag_3 = _RAND_91[1:0]; + _RAND_92 = {1{`RANDOM}}; + buf_ldfwdtag_2 = _RAND_92[1:0]; + _RAND_93 = {1{`RANDOM}}; + buf_ldfwdtag_1 = _RAND_93[1:0]; + _RAND_94 = {1{`RANDOM}}; + buf_dualtag_1 = _RAND_94[1:0]; + _RAND_95 = {1{`RANDOM}}; + buf_dualtag_2 = _RAND_95[1:0]; + _RAND_96 = {1{`RANDOM}}; + buf_dualtag_3 = _RAND_96[1:0]; + _RAND_97 = {1{`RANDOM}}; + _T_4331 = _RAND_97[0:0]; + _RAND_98 = {1{`RANDOM}}; + _T_4334 = _RAND_98[0:0]; + _RAND_99 = {1{`RANDOM}}; + _T_4337 = _RAND_99[0:0]; + _RAND_100 = {1{`RANDOM}}; + _T_4340 = _RAND_100[0:0]; + _RAND_101 = {1{`RANDOM}}; + _T_4406 = _RAND_101[0:0]; + _RAND_102 = {1{`RANDOM}}; + _T_4401 = _RAND_102[0:0]; + _RAND_103 = {1{`RANDOM}}; + _T_4396 = _RAND_103[0:0]; + _RAND_104 = {1{`RANDOM}}; + _T_4391 = _RAND_104[0:0]; + _RAND_105 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_105[0:0]; + _RAND_106 = {1{`RANDOM}}; + _T_4956 = _RAND_106[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_addr_0 = 32'h0; + end + if (reset) begin + _T_4355 = 1'h0; + end + if (reset) begin + _T_4352 = 1'h0; + end + if (reset) begin + _T_4349 = 1'h0; + end + if (reset) begin + _T_4346 = 1'h0; + end + if (reset) begin + buf_state_0 = 3'h0; + end + if (reset) begin + buf_addr_1 = 32'h0; + end + if (reset) begin + buf_state_1 = 3'h0; + end + if (reset) begin + buf_addr_2 = 32'h0; + end + if (reset) begin + buf_state_2 = 3'h0; + end + if (reset) begin + buf_addr_3 = 32'h0; + end + if (reset) begin + buf_state_3 = 3'h0; + end + if (reset) begin + buf_byteen_3 = 4'h0; + end + if (reset) begin + buf_byteen_2 = 4'h0; + end + if (reset) begin + buf_byteen_1 = 4'h0; + end + if (reset) begin + buf_byteen_0 = 4'h0; + end + if (reset) begin + buf_ageQ_3 = 4'h0; + end + if (reset) begin + _T_1781 = 2'h0; + end + if (reset) begin + obuf_merge = 1'h0; + end + if (reset) begin + obuf_tag1 = 2'h0; + end + if (reset) begin + obuf_valid = 1'h0; + end + if (reset) begin + obuf_wr_enQ = 1'h0; + end + if (reset) begin + ibuf_addr = 32'h0; + end + if (reset) begin + ibuf_write = 1'h0; + end + if (reset) begin + ibuf_valid = 1'h0; + end + if (reset) begin + ibuf_byteen = 4'h0; + end + if (reset) begin + buf_ageQ_2 = 4'h0; + end + if (reset) begin + buf_ageQ_1 = 4'h0; + end + if (reset) begin + buf_ageQ_0 = 4'h0; + end + if (reset) begin + buf_data_0 = 32'h0; + end + if (reset) begin + buf_data_1 = 32'h0; + end + if (reset) begin + buf_data_2 = 32'h0; + end + if (reset) begin + buf_data_3 = 32'h0; + end + if (reset) begin + ibuf_data = 32'h0; + end + if (reset) begin + ibuf_timer = 3'h0; + end + if (reset) begin + ibuf_sideeffect = 1'h0; + end + if (reset) begin + WrPtr1_r = 2'h0; + end + if (reset) begin + WrPtr0_r = 2'h0; + end + if (reset) begin + ibuf_tag = 2'h0; + end + if (reset) begin + ibuf_dualtag = 2'h0; + end + if (reset) begin + ibuf_dual = 1'h0; + end + if (reset) begin + ibuf_samedw = 1'h0; + end + if (reset) begin + ibuf_nomerge = 1'h0; + end + if (reset) begin + ibuf_unsign = 1'h0; + end + if (reset) begin + ibuf_sz = 2'h0; + end + if (reset) begin + _T_1791 = 1'h0; + end + if (reset) begin + buf_nomerge_0 = 1'h0; + end + if (reset) begin + buf_nomerge_1 = 1'h0; + end + if (reset) begin + buf_nomerge_2 = 1'h0; + end + if (reset) begin + buf_nomerge_3 = 1'h0; + end + if (reset) begin + _T_4325 = 1'h0; + end + if (reset) begin + _T_4322 = 1'h0; + end + if (reset) begin + _T_4319 = 1'h0; + end + if (reset) begin + _T_4316 = 1'h0; + end + if (reset) begin + obuf_sideeffect = 1'h0; + end + if (reset) begin + buf_dual_3 = 1'h0; + end + if (reset) begin + buf_dual_2 = 1'h0; + end + if (reset) begin + buf_dual_1 = 1'h0; + end + if (reset) begin + buf_dual_0 = 1'h0; + end + if (reset) begin + buf_samedw_3 = 1'h0; + end + if (reset) begin + buf_samedw_2 = 1'h0; + end + if (reset) begin + buf_samedw_1 = 1'h0; + end + if (reset) begin + buf_samedw_0 = 1'h0; + end + if (reset) begin + obuf_write = 1'h0; + end + if (reset) begin + obuf_cmd_done = 1'h0; + end + if (reset) begin + obuf_data_done = 1'h0; + end + if (reset) begin + obuf_nosend = 1'h0; + end + if (reset) begin + obuf_addr = 32'h0; + end + if (reset) begin + buf_sz_0 = 2'h0; + end + if (reset) begin + buf_sz_1 = 2'h0; + end + if (reset) begin + buf_sz_2 = 2'h0; + end + if (reset) begin + buf_sz_3 = 2'h0; + end + if (reset) begin + obuf_rdrsp_pend = 1'h0; + end + if (reset) begin + obuf_rdrsp_tag = 3'h0; + end + if (reset) begin + buf_dualhi_3 = 1'h0; + end + if (reset) begin + buf_dualhi_2 = 1'h0; + end + if (reset) begin + buf_dualhi_1 = 1'h0; + end + if (reset) begin + buf_dualhi_0 = 1'h0; + end + if (reset) begin + obuf_sz = 2'h0; + end + if (reset) begin + obuf_byteen = 8'h0; + end + if (reset) begin + obuf_data = 64'h0; + end + if (reset) begin + buf_rspageQ_0 = 4'h0; + end + if (reset) begin + buf_rspageQ_1 = 4'h0; + end + if (reset) begin + buf_rspageQ_2 = 4'h0; + end + if (reset) begin + buf_rspageQ_3 = 4'h0; + end + if (reset) begin + _T_4302 = 1'h0; + end + if (reset) begin + _T_4300 = 1'h0; + end + if (reset) begin + _T_4298 = 1'h0; + end + if (reset) begin + _T_4296 = 1'h0; + end + if (reset) begin + buf_ldfwdtag_0 = 2'h0; + end + if (reset) begin + buf_dualtag_0 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_3 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_2 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_2 = 2'h0; + end + if (reset) begin + buf_dualtag_3 = 2'h0; + end + if (reset) begin + _T_4331 = 1'h0; + end + if (reset) begin + _T_4334 = 1'h0; + end + if (reset) begin + _T_4337 = 1'h0; + end + if (reset) begin + _T_4340 = 1'h0; + end + if (reset) begin + _T_4406 = 1'h0; + end + if (reset) begin + _T_4401 = 1'h0; + end + if (reset) begin + _T_4396 = 1'h0; + end + if (reset) begin + _T_4391 = 1'h0; + end + if (reset) begin + lsu_nonblock_load_valid_r = 1'h0; + end + if (reset) begin + _T_4956 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_0 <= 32'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_addr_0 <= ibuf_addr; + end else if (_T_3346) begin + buf_addr_0 <= io_end_addr_r; + end else begin + buf_addr_0 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4355 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4355 <= buf_write_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4352 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4352 <= buf_write_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4349 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4349 <= buf_write_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4346 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4346 <= buf_write_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_0 <= 3'h0; + end else if (buf_state_en_0) begin + if (_T_3531) begin + if (io_lsu_bus_clk_en) begin + buf_state_0 <= 3'h2; + end else begin + buf_state_0 <= 3'h1; + end + end else if (_T_3554) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h2; + end + end else if (_T_3558) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3562) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h3; + end + end else if (_T_3592) begin + if (_T_3596) begin + buf_state_0 <= 3'h0; + end else if (_T_3604) begin + buf_state_0 <= 3'h4; + end else if (_T_3632) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3677) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3683) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3695) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h6; + end + end else begin + buf_state_0 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_1 <= 32'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_addr_1 <= ibuf_addr; + end else if (_T_3355) begin + buf_addr_1 <= io_end_addr_r; + end else begin + buf_addr_1 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_1 <= 3'h0; + end else if (buf_state_en_1) begin + if (_T_3722) begin + if (io_lsu_bus_clk_en) begin + buf_state_1 <= 3'h2; + end else begin + buf_state_1 <= 3'h1; + end + end else if (_T_3745) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h2; + end + end else if (_T_3749) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3562) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h3; + end + end else if (_T_3783) begin + if (_T_3787) begin + buf_state_1 <= 3'h0; + end else if (_T_3795) begin + buf_state_1 <= 3'h4; + end else if (_T_3823) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3868) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3874) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3886) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h6; + end + end else begin + buf_state_1 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_2 <= 32'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_addr_2 <= ibuf_addr; + end else if (_T_3364) begin + buf_addr_2 <= io_end_addr_r; + end else begin + buf_addr_2 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_2 <= 3'h0; + end else if (buf_state_en_2) begin + if (_T_3913) begin + if (io_lsu_bus_clk_en) begin + buf_state_2 <= 3'h2; + end else begin + buf_state_2 <= 3'h1; + end + end else if (_T_3936) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h2; + end + end else if (_T_3940) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3562) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h3; + end + end else if (_T_3974) begin + if (_T_3978) begin + buf_state_2 <= 3'h0; + end else if (_T_3986) begin + buf_state_2 <= 3'h4; + end else if (_T_4014) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4059) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_4065) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4077) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h6; + end + end else begin + buf_state_2 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_3 <= 32'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_addr_3 <= ibuf_addr; + end else if (_T_3373) begin + buf_addr_3 <= io_end_addr_r; + end else begin + buf_addr_3 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_3 <= 3'h0; + end else if (buf_state_en_3) begin + if (_T_4104) begin + if (io_lsu_bus_clk_en) begin + buf_state_3 <= 3'h2; + end else begin + buf_state_3 <= 3'h1; + end + end else if (_T_4127) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h2; + end + end else if (_T_4131) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_3562) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h3; + end + end else if (_T_4165) begin + if (_T_4169) begin + buf_state_3 <= 3'h0; + end else if (_T_4177) begin + buf_state_3 <= 3'h4; + end else if (_T_4205) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4250) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_4256) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4268) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h6; + end + end else begin + buf_state_3 <= 3'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_3 <= 4'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_byteen_3 <= ibuf_byteen_out; + end else if (_T_3373) begin + buf_byteen_3 <= ldst_byteen_hi_r; + end else begin + buf_byteen_3 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_2 <= 4'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_byteen_2 <= ibuf_byteen_out; + end else if (_T_3364) begin + buf_byteen_2 <= ldst_byteen_hi_r; + end else begin + buf_byteen_2 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_1 <= 4'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_byteen_1 <= ibuf_byteen_out; + end else if (_T_3355) begin + buf_byteen_1 <= ldst_byteen_hi_r; + end else begin + buf_byteen_1 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_0 <= 4'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_byteen_0 <= ibuf_byteen_out; + end else if (_T_3346) begin + buf_byteen_0 <= ldst_byteen_hi_r; + end else begin + buf_byteen_0 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_3 <= 4'h0; + end else begin + buf_ageQ_3 <= {_T_2474,_T_2397}; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1781 <= 2'h0; + end else if (_T_1780) begin + if (ibuf_buf_byp) begin + _T_1781 <= WrPtr0_r; + end else begin + _T_1781 <= CmdPtr0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_merge <= 1'h0; + end else if (_T_1780) begin + obuf_merge <= obuf_merge_en; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_tag1 <= 2'h0; + end else if (_T_1780) begin + if (ibuf_buf_byp) begin + obuf_tag1 <= WrPtr1_r; + end else begin + obuf_tag1 <= CmdPtr1; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_valid <= 1'h0; + end else begin + obuf_valid <= _T_1771 & _T_1772; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_wr_enQ <= 1'h0; + end else if (io_lsu_busm_clken) begin + obuf_wr_enQ <= obuf_wr_en; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ibuf_addr <= 32'h0; + end else if (ibuf_wr_en) begin + if (io_ldst_dual_r) begin + ibuf_addr <= io_end_addr_r; + end else begin + ibuf_addr <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_write <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_write <= io_lsu_pkt_r_bits_store; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_valid <= 1'h0; + end else begin + ibuf_valid <= _T_1005 & _T_1006; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_byteen <= 4'h0; + end else if (ibuf_wr_en) begin + if (_T_866) begin + ibuf_byteen <= _T_881; + end else if (io_ldst_dual_r) begin + ibuf_byteen <= ldst_byteen_hi_r; + end else begin + ibuf_byteen <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_2 <= 4'h0; + end else begin + buf_ageQ_2 <= {_T_2372,_T_2295}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_1 <= 4'h0; + end else begin + buf_ageQ_1 <= {_T_2270,_T_2193}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_0 <= 4'h0; + end else begin + buf_ageQ_0 <= {_T_2168,_T_2091}; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_0 <= 32'h0; + end else if (buf_data_en_0) begin + if (_T_3531) begin + if (_T_3546) begin + buf_data_0 <= ibuf_data_out; + end else begin + buf_data_0 <= store_data_lo_r; + end + end else if (_T_3554) begin + buf_data_0 <= 32'h0; + end else if (_T_3558) begin + if (buf_error_en_0) begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3592) begin + if (_T_3670) begin + if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_1 <= 32'h0; + end else if (buf_data_en_1) begin + if (_T_3722) begin + if (_T_3737) begin + buf_data_1 <= ibuf_data_out; + end else begin + buf_data_1 <= store_data_lo_r; + end + end else if (_T_3745) begin + buf_data_1 <= 32'h0; + end else if (_T_3749) begin + if (buf_error_en_1) begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3783) begin + if (_T_3861) begin + if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_2 <= 32'h0; + end else if (buf_data_en_2) begin + if (_T_3913) begin + if (_T_3928) begin + buf_data_2 <= ibuf_data_out; + end else begin + buf_data_2 <= store_data_lo_r; + end + end else if (_T_3936) begin + buf_data_2 <= 32'h0; + end else if (_T_3940) begin + if (buf_error_en_2) begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3974) begin + if (_T_4052) begin + if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_3 <= 32'h0; + end else if (buf_data_en_3) begin + if (_T_4104) begin + if (_T_4119) begin + buf_data_3 <= ibuf_data_out; + end else begin + buf_data_3 <= store_data_lo_r; + end + end else if (_T_4127) begin + buf_data_3 <= 32'h0; + end else if (_T_4131) begin + if (buf_error_en_3) begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_4165) begin + if (_T_4243) begin + if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ibuf_data <= 32'h0; + end else if (ibuf_wr_en) begin + ibuf_data <= ibuf_data_in; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_923) begin + ibuf_timer <= _T_926; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sideeffect <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_sideeffect <= io_is_sideeffects_r; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr1_r <= 2'h0; + end else if (_T_1853) begin + WrPtr1_r <= 2'h0; + end else if (_T_1867) begin + WrPtr1_r <= 2'h1; + end else if (_T_1881) begin + WrPtr1_r <= 2'h2; + end else begin + WrPtr1_r <= 2'h3; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr0_r <= 2'h0; + end else if (_T_1802) begin + WrPtr0_r <= 2'h0; + end else if (_T_1813) begin + WrPtr0_r <= 2'h1; + end else if (_T_1824) begin + WrPtr0_r <= 2'h2; + end else begin + WrPtr0_r <= 2'h3; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_tag <= 2'h0; + end else if (ibuf_wr_en) begin + if (!(_T_866)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dualtag <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_dualtag <= WrPtr0_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dual <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_dual <= io_ldst_dual_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_samedw <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_samedw <= ldst_samedw_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_nomerge <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_nomerge <= io_no_dword_merge_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_unsign <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_unsign <= io_lsu_pkt_r_bits_unsign; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sz <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_sz <= ibuf_sz_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1791 <= 1'h0; + end else if (obuf_wr_en) begin + _T_1791 <= obuf_data_done_in; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_nomerge_0 <= buf_nomerge_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_nomerge_1 <= buf_nomerge_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_nomerge_2 <= buf_nomerge_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_nomerge_3 <= buf_nomerge_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4325 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4325 <= buf_sideeffect_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4322 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4322 <= buf_sideeffect_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4319 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4319 <= buf_sideeffect_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4316 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4316 <= buf_sideeffect_in[0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_sideeffect <= 1'h0; + end else if (_T_1780) begin + if (ibuf_buf_byp) begin + obuf_sideeffect <= io_is_sideeffects_r; + end else begin + obuf_sideeffect <= _T_1051; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dual_3 <= buf_dual_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dual_2 <= buf_dual_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dual_1 <= buf_dual_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dual_0 <= buf_dual_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_samedw_3 <= buf_samedw_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_samedw_2 <= buf_samedw_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_samedw_1 <= buf_samedw_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_samedw_0 <= buf_samedw_in[0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_write <= 1'h0; + end else if (_T_1780) begin + if (ibuf_buf_byp) begin + obuf_write <= io_lsu_pkt_r_bits_store; + end else begin + obuf_write <= _T_1202; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_cmd_done <= 1'h0; + end else if (io_lsu_busm_clken) begin + obuf_cmd_done <= obuf_cmd_done_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_data_done <= 1'h0; + end else if (io_lsu_busm_clken) begin + obuf_data_done <= obuf_data_done_in; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_nosend <= 1'h0; + end else if (obuf_wr_en) begin + obuf_nosend <= obuf_nosend_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_addr <= 32'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_addr <= io_lsu_addr_r; + end else begin + obuf_addr <= _T_1287; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_sz_0 <= ibuf_sz; + end else begin + buf_sz_0 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_sz_1 <= ibuf_sz; + end else begin + buf_sz_1 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_sz_2 <= ibuf_sz; + end else begin + buf_sz_2 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_sz_3 <= ibuf_sz; + end else begin + buf_sz_3 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_pend <= 1'h0; + end else if (obuf_rdrsp_pend_en) begin + obuf_rdrsp_pend <= obuf_rdrsp_pend_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_rdrsp_tag <= 3'h0; + end else if (io_lsu_busm_clken) begin + if (_T_1330) begin + obuf_rdrsp_tag <= obuf_tag0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dualhi_3 <= buf_dualhi_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dualhi_2 <= buf_dualhi_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dualhi_1 <= buf_dualhi_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dualhi_0 <= buf_dualhi_in[0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_sz <= 2'h0; + end else if (_T_1780) begin + if (ibuf_buf_byp) begin + obuf_sz <= ibuf_sz_in; + end else begin + obuf_sz <= _T_1300; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_byteen <= 8'h0; + end else if (_T_1780) begin + obuf_byteen <= obuf_byteen_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_data <= 64'h0; + end else if (obuf_wr_en) begin + obuf_data <= obuf_data_in; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_0 <= 4'h0; + end else begin + buf_rspageQ_0 <= {_T_3144,_T_3133}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_1 <= 4'h0; + end else begin + buf_rspageQ_1 <= {_T_3159,_T_3148}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_2 <= 4'h0; + end else begin + buf_rspageQ_2 <= {_T_3174,_T_3163}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_3 <= 4'h0; + end else begin + buf_rspageQ_3 <= {_T_3189,_T_3178}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4302 <= 1'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4104) begin + _T_4302 <= 1'h0; + end else if (_T_4127) begin + _T_4302 <= 1'h0; + end else begin + _T_4302 <= _T_4131; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4300 <= 1'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3913) begin + _T_4300 <= 1'h0; + end else if (_T_3936) begin + _T_4300 <= 1'h0; + end else begin + _T_4300 <= _T_3940; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4298 <= 1'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3722) begin + _T_4298 <= 1'h0; + end else if (_T_3745) begin + _T_4298 <= 1'h0; + end else begin + _T_4298 <= _T_3749; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4296 <= 1'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3531) begin + _T_4296 <= 1'h0; + end else if (_T_3554) begin + _T_4296 <= 1'h0; + end else begin + _T_4296 <= _T_3558; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3531) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3554) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3558) begin + buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_0 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_dualtag_0 <= ibuf_dualtag; + end else if (_T_3346) begin + buf_dualtag_0 <= WrPtr0_r; + end else begin + buf_dualtag_0 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4104) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_4127) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_4131) begin + buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_3 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3913) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3936) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3940) begin + buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_2 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3722) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3745) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3749) begin + buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_1 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_dualtag_1 <= ibuf_dualtag; + end else if (_T_3355) begin + buf_dualtag_1 <= WrPtr0_r; + end else begin + buf_dualtag_1 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_dualtag_2 <= ibuf_dualtag; + end else if (_T_3364) begin + buf_dualtag_2 <= WrPtr0_r; + end else begin + buf_dualtag_2 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_dualtag_3 <= ibuf_dualtag; + end else if (_T_3373) begin + buf_dualtag_3 <= WrPtr0_r; + end else begin + buf_dualtag_3 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4331 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4331 <= buf_unsign_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4334 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4334 <= buf_unsign_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4337 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4337 <= buf_unsign_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4340 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4340 <= buf_unsign_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4406 <= 1'h0; + end else begin + _T_4406 <= _T_4402 & _T_4404; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4401 <= 1'h0; + end else begin + _T_4401 <= _T_4397 & _T_4399; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4396 <= 1'h0; + end else begin + _T_4396 <= _T_4392 & _T_4394; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4391 <= 1'h0; + end else begin + _T_4391 <= _T_4387 & _T_4389; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_nonblock_load_valid_r <= 1'h0; + end else begin + lsu_nonblock_load_valid_r <= io_dctl_busbuff_lsu_nonblock_load_valid_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_4956 <= 1'h0; + end else begin + _T_4956 <= _T_4953 & _T_4513; + end + end +endmodule +module lsu_bus_intf( + input clock, + input reset, + input io_scan_mode, + input io_clk_override, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + input io_lsu_bus_obuf_c1_clken, + input io_lsu_busm_clken, + input io_lsu_c1_r_clk, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_obuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_active_clk, + input io_lsu_busm_clk, + input io_axi_aw_ready, + output io_axi_aw_valid, + output [2:0] io_axi_aw_bits_id, + output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, + output [7:0] io_axi_aw_bits_len, + output [2:0] io_axi_aw_bits_size, + output [1:0] io_axi_aw_bits_burst, + output io_axi_aw_bits_lock, + output [3:0] io_axi_aw_bits_cache, + output [2:0] io_axi_aw_bits_prot, + output [3:0] io_axi_aw_bits_qos, + input io_axi_w_ready, + output io_axi_w_valid, + output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, + output io_axi_w_bits_last, + output io_axi_b_ready, + input io_axi_b_valid, + input [1:0] io_axi_b_bits_resp, + input [2:0] io_axi_b_bits_id, + input io_axi_ar_ready, + output io_axi_ar_valid, + output [2:0] io_axi_ar_bits_id, + output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, + output [7:0] io_axi_ar_bits_len, + output [2:0] io_axi_ar_bits_size, + output [1:0] io_axi_ar_bits_burst, + output io_axi_ar_bits_lock, + output [3:0] io_axi_ar_bits_cache, + output [2:0] io_axi_ar_bits_prot, + output [3:0] io_axi_ar_bits_qos, + output io_axi_r_ready, + input io_axi_r_valid, + input [2:0] io_axi_r_bits_id, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + input io_axi_r_bits_last, + input io_dec_lsu_valid_raw_d, + input io_lsu_busreq_m, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_fast_int, + input io_lsu_pkt_m_bits_stack, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_dword, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_unsign, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_m_bits_store_data_bypass_d, + input io_lsu_pkt_m_bits_load_ldst_bypass_d, + input io_lsu_pkt_m_bits_store_data_bypass_m, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_fast_int, + input io_lsu_pkt_r_bits_stack, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_dword, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input io_lsu_pkt_r_bits_dma, + input io_lsu_pkt_r_bits_store_data_bypass_d, + input io_lsu_pkt_r_bits_load_ldst_bypass_d, + input io_lsu_pkt_r_bits_store_data_bypass_m, + input [31:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_m, + input [31:0] io_end_addr_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [31:0] io_store_data_r, + input io_dec_tlu_force_halt, + input io_lsu_commit_r, + input io_is_sideeffects_m, + input io_flush_m_up, + input io_flush_r, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [31:0] io_bus_read_data_m, + output [31:0] io_lsu_nonblock_load_data, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + input io_lsu_bus_clk_en +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire bus_buffer_clock; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_reset; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_obuf_c1_clken; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busm_clken; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_store_data_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_word_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_dword_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ld_full_hit_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_m_up; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_commit_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_is_sideeffects_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 100:39] + wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39] + wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 100:39] + wire [3:0] _T_3 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_4 = io_lsu_pkt_m_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_5 = io_lsu_pkt_m_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72] + wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[lsu_bus_intf.scala 155:51] + wire _T_14 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[lsu_bus_intf.scala 156:71] + wire _T_15 = ~_T_14; // @[lsu_bus_intf.scala 156:53] + wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_15; // @[lsu_bus_intf.scala 156:51] + wire _T_17 = ~io_ldst_dual_r; // @[lsu_bus_intf.scala 157:48] + wire _T_18 = io_lsu_busreq_r & _T_17; // @[lsu_bus_intf.scala 157:46] + wire _T_19 = _T_18 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 157:64] + wire _T_20 = ~addr_match_word_lo_r_m; // @[lsu_bus_intf.scala 157:110] + wire _T_21 = io_lsu_pkt_m_bits_load | _T_20; // @[lsu_bus_intf.scala 157:108] + wire _T_26 = ~addr_match_dw_lo_r_m; // @[lsu_bus_intf.scala 158:110] + wire _T_27 = io_lsu_pkt_m_bits_load | _T_26; // @[lsu_bus_intf.scala 158:108] + wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[lsu_bus_intf.scala 160:49] + wire [6:0] _T_31 = _GEN_0 << io_lsu_addr_m[1:0]; // @[lsu_bus_intf.scala 160:49] + reg [3:0] ldst_byteen_r; // @[lsu_bus_intf.scala 200:33] + wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[lsu_bus_intf.scala 161:49] + wire [6:0] _T_34 = _GEN_1 << io_lsu_addr_r[1:0]; // @[lsu_bus_intf.scala 161:49] + wire [4:0] _T_37 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58] + wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[lsu_bus_intf.scala 162:52] + wire [62:0] _T_38 = _GEN_2 << _T_37; // @[lsu_bus_intf.scala 162:52] + wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 160:27] + wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[lsu_bus_intf.scala 163:47] + wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[lsu_bus_intf.scala 164:47] + wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 161:27] + wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[lsu_bus_intf.scala 165:47] + wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[lsu_bus_intf.scala 166:47] + wire [63:0] store_data_ext_r = {{1'd0}, _T_38}; // @[lsu_bus_intf.scala 162:27] + wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[lsu_bus_intf.scala 168:46] + wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[lsu_bus_intf.scala 169:46] + wire _T_47 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 170:51] + wire _T_48 = _T_47 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 170:76] + wire _T_49 = _T_48 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 170:97] + wire ld_addr_rhit_lo_lo = _T_49 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 170:123] + wire _T_53 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 171:51] + wire _T_54 = _T_53 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 171:76] + wire _T_55 = _T_54 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 171:97] + wire ld_addr_rhit_lo_hi = _T_55 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 171:123] + wire _T_59 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 172:51] + wire _T_60 = _T_59 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 172:76] + wire _T_61 = _T_60 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 172:97] + wire ld_addr_rhit_hi_lo = _T_61 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 172:123] + wire _T_65 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 173:51] + wire _T_66 = _T_65 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 173:76] + wire _T_67 = _T_66 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 173:97] + wire ld_addr_rhit_hi_hi = _T_67 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 173:123] + wire _T_70 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 175:70] + wire _T_72 = _T_70 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 175:92] + wire _T_74 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 175:70] + wire _T_76 = _T_74 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 175:92] + wire _T_78 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 175:70] + wire _T_80 = _T_78 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 175:92] + wire _T_82 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 175:70] + wire _T_84 = _T_82 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 175:92] + wire [3:0] ld_byte_rhit_lo_lo = {_T_84,_T_80,_T_76,_T_72}; // @[Cat.scala 29:58] + wire _T_89 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 176:70] + wire _T_91 = _T_89 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 176:92] + wire _T_93 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 176:70] + wire _T_95 = _T_93 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 176:92] + wire _T_97 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 176:70] + wire _T_99 = _T_97 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 176:92] + wire _T_101 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 176:70] + wire _T_103 = _T_101 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 176:92] + wire [3:0] ld_byte_rhit_lo_hi = {_T_103,_T_99,_T_95,_T_91}; // @[Cat.scala 29:58] + wire _T_108 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 177:70] + wire _T_110 = _T_108 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 177:92] + wire _T_112 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 177:70] + wire _T_114 = _T_112 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 177:92] + wire _T_116 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 177:70] + wire _T_118 = _T_116 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 177:92] + wire _T_120 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 177:70] + wire _T_122 = _T_120 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 177:92] + wire [3:0] ld_byte_rhit_hi_lo = {_T_122,_T_118,_T_114,_T_110}; // @[Cat.scala 29:58] + wire _T_127 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 178:70] + wire _T_129 = _T_127 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 178:92] + wire _T_131 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 178:70] + wire _T_133 = _T_131 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 178:92] + wire _T_135 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 178:70] + wire _T_137 = _T_135 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 178:92] + wire _T_139 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 178:70] + wire _T_141 = _T_139 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 178:92] + wire [3:0] ld_byte_rhit_hi_hi = {_T_141,_T_137,_T_133,_T_129}; // @[Cat.scala 29:58] + wire _T_147 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_bus_intf.scala 180:73] + wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 139:38] + wire _T_149 = _T_147 | ld_byte_hit_buf_lo[0]; // @[lsu_bus_intf.scala 180:97] + wire _T_152 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_bus_intf.scala 180:73] + wire _T_154 = _T_152 | ld_byte_hit_buf_lo[1]; // @[lsu_bus_intf.scala 180:97] + wire _T_157 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_bus_intf.scala 180:73] + wire _T_159 = _T_157 | ld_byte_hit_buf_lo[2]; // @[lsu_bus_intf.scala 180:97] + wire _T_162 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_bus_intf.scala 180:73] + wire _T_164 = _T_162 | ld_byte_hit_buf_lo[3]; // @[lsu_bus_intf.scala 180:97] + wire [3:0] ld_byte_hit_lo = {_T_164,_T_159,_T_154,_T_149}; // @[Cat.scala 29:58] + wire _T_170 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_bus_intf.scala 181:73] + wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 140:38] + wire _T_172 = _T_170 | ld_byte_hit_buf_hi[0]; // @[lsu_bus_intf.scala 181:97] + wire _T_175 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_bus_intf.scala 181:73] + wire _T_177 = _T_175 | ld_byte_hit_buf_hi[1]; // @[lsu_bus_intf.scala 181:97] + wire _T_180 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_bus_intf.scala 181:73] + wire _T_182 = _T_180 | ld_byte_hit_buf_hi[2]; // @[lsu_bus_intf.scala 181:97] + wire _T_185 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_bus_intf.scala 181:73] + wire _T_187 = _T_185 | ld_byte_hit_buf_hi[3]; // @[lsu_bus_intf.scala 181:97] + wire [3:0] ld_byte_hit_hi = {_T_187,_T_182,_T_177,_T_172}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_lo = {_T_162,_T_157,_T_152,_T_147}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_hi = {_T_185,_T_180,_T_175,_T_170}; // @[Cat.scala 29:58] + wire [7:0] _T_225 = ld_byte_rhit_lo_lo[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_226 = ld_byte_rhit_hi_lo[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_227 = _T_225 | _T_226; // @[Mux.scala 27:72] + wire [7:0] _T_233 = ld_byte_rhit_lo_lo[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_234 = ld_byte_rhit_hi_lo[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_235 = _T_233 | _T_234; // @[Mux.scala 27:72] + wire [7:0] _T_241 = ld_byte_rhit_lo_lo[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_242 = ld_byte_rhit_hi_lo[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_243 = _T_241 | _T_242; // @[Mux.scala 27:72] + wire [7:0] _T_249 = ld_byte_rhit_lo_lo[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_250 = ld_byte_rhit_hi_lo[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_251 = _T_249 | _T_250; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_lo = {_T_251,_T_243,_T_235,_T_227}; // @[Cat.scala 29:58] + wire [7:0] _T_260 = ld_byte_rhit_lo_hi[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_261 = ld_byte_rhit_hi_hi[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_262 = _T_260 | _T_261; // @[Mux.scala 27:72] + wire [7:0] _T_268 = ld_byte_rhit_lo_hi[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_269 = ld_byte_rhit_hi_hi[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_270 = _T_268 | _T_269; // @[Mux.scala 27:72] + wire [7:0] _T_276 = ld_byte_rhit_lo_hi[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_277 = ld_byte_rhit_hi_hi[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_278 = _T_276 | _T_277; // @[Mux.scala 27:72] + wire [7:0] _T_284 = ld_byte_rhit_lo_hi[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_285 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_286 = _T_284 | _T_285; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_hi = {_T_286,_T_278,_T_270,_T_262}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 141:38] + wire [7:0] _T_294 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_298 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_302 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_306 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[lsu_bus_intf.scala 186:54] + wire [31:0] _T_309 = {_T_306,_T_302,_T_298,_T_294}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 142:38] + wire [7:0] _T_313 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_317 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_321 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_325 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[lsu_bus_intf.scala 187:54] + wire [31:0] _T_328 = {_T_325,_T_321,_T_317,_T_313}; // @[Cat.scala 29:58] + wire _T_331 = ~ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 188:72] + wire _T_332 = ld_byte_hit_lo[0] | _T_331; // @[lsu_bus_intf.scala 188:70] + wire _T_335 = ~ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 188:72] + wire _T_336 = ld_byte_hit_lo[1] | _T_335; // @[lsu_bus_intf.scala 188:70] + wire _T_339 = ~ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 188:72] + wire _T_340 = ld_byte_hit_lo[2] | _T_339; // @[lsu_bus_intf.scala 188:70] + wire _T_343 = ~ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 188:72] + wire _T_344 = ld_byte_hit_lo[3] | _T_343; // @[lsu_bus_intf.scala 188:70] + wire _T_345 = _T_332 & _T_336; // @[lsu_bus_intf.scala 188:111] + wire _T_346 = _T_345 & _T_340; // @[lsu_bus_intf.scala 188:111] + wire ld_full_hit_lo_m = _T_346 & _T_344; // @[lsu_bus_intf.scala 188:111] + wire _T_350 = ~ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 189:72] + wire _T_351 = ld_byte_hit_hi[0] | _T_350; // @[lsu_bus_intf.scala 189:70] + wire _T_354 = ~ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 189:72] + wire _T_355 = ld_byte_hit_hi[1] | _T_354; // @[lsu_bus_intf.scala 189:70] + wire _T_358 = ~ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 189:72] + wire _T_359 = ld_byte_hit_hi[2] | _T_358; // @[lsu_bus_intf.scala 189:70] + wire _T_362 = ~ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 189:72] + wire _T_363 = ld_byte_hit_hi[3] | _T_362; // @[lsu_bus_intf.scala 189:70] + wire _T_364 = _T_351 & _T_355; // @[lsu_bus_intf.scala 189:111] + wire _T_365 = _T_364 & _T_359; // @[lsu_bus_intf.scala 189:111] + wire ld_full_hit_hi_m = _T_365 & _T_363; // @[lsu_bus_intf.scala 189:111] + wire _T_367 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[lsu_bus_intf.scala 190:47] + wire _T_368 = _T_367 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 190:66] + wire _T_369 = _T_368 & io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 190:84] + wire _T_370 = ~io_is_sideeffects_m; // @[lsu_bus_intf.scala 190:111] + wire [63:0] ld_fwddata_hi = {{32'd0}, _T_328}; // @[lsu_bus_intf.scala 187:27] + wire [63:0] ld_fwddata_lo = {{32'd0}, _T_309}; // @[lsu_bus_intf.scala 186:27] + wire [63:0] _T_374 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58] + wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_bus_intf.scala 191:83] + wire [5:0] _T_376 = 4'h8 * _GEN_3; // @[lsu_bus_intf.scala 191:83] + wire [63:0] ld_fwddata_m = _T_374 >> _T_376; // @[lsu_bus_intf.scala 191:76] + reg lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 195:32] + reg is_sideeffects_r; // @[lsu_bus_intf.scala 199:33] + lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 100:39] + .clock(bus_buffer_clock), + .reset(bus_buffer_reset), + .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn), + .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned), + .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), + .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), + .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), + .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), + .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), + .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), + .io_tlu_busbuff_lsu_imprecise_error_addr_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any), + .io_dctl_busbuff_lsu_nonblock_load_valid_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m), + .io_dctl_busbuff_lsu_nonblock_load_tag_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m), + .io_dctl_busbuff_lsu_nonblock_load_inv_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r), + .io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r), + .io_dctl_busbuff_lsu_nonblock_load_data_valid(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid), + .io_dctl_busbuff_lsu_nonblock_load_data_error(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error), + .io_dctl_busbuff_lsu_nonblock_load_data_tag(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag), + .io_dec_tlu_force_halt(bus_buffer_io_dec_tlu_force_halt), + .io_lsu_bus_obuf_c1_clken(bus_buffer_io_lsu_bus_obuf_c1_clken), + .io_lsu_busm_clken(bus_buffer_io_lsu_busm_clken), + .io_lsu_c2_r_clk(bus_buffer_io_lsu_c2_r_clk), + .io_lsu_bus_ibuf_c1_clk(bus_buffer_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_buf_c1_clk(bus_buffer_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(bus_buffer_io_lsu_free_c2_clk), + .io_dec_lsu_valid_raw_d(bus_buffer_io_dec_lsu_valid_raw_d), + .io_lsu_pkt_m_valid(bus_buffer_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_load(bus_buffer_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_r_bits_by(bus_buffer_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(bus_buffer_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(bus_buffer_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(bus_buffer_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(bus_buffer_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(bus_buffer_io_lsu_pkt_r_bits_unsign), + .io_lsu_addr_m(bus_buffer_io_lsu_addr_m), + .io_end_addr_m(bus_buffer_io_end_addr_m), + .io_lsu_addr_r(bus_buffer_io_lsu_addr_r), + .io_end_addr_r(bus_buffer_io_end_addr_r), + .io_store_data_r(bus_buffer_io_store_data_r), + .io_no_word_merge_r(bus_buffer_io_no_word_merge_r), + .io_no_dword_merge_r(bus_buffer_io_no_dword_merge_r), + .io_lsu_busreq_m(bus_buffer_io_lsu_busreq_m), + .io_ld_full_hit_m(bus_buffer_io_ld_full_hit_m), + .io_flush_m_up(bus_buffer_io_flush_m_up), + .io_flush_r(bus_buffer_io_flush_r), + .io_lsu_commit_r(bus_buffer_io_lsu_commit_r), + .io_is_sideeffects_r(bus_buffer_io_is_sideeffects_r), + .io_ldst_dual_d(bus_buffer_io_ldst_dual_d), + .io_ldst_dual_m(bus_buffer_io_ldst_dual_m), + .io_ldst_dual_r(bus_buffer_io_ldst_dual_r), + .io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m), + .io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready), + .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), + .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id), + .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region), + .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache), + .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), + .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), + .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), + .io_lsu_axi_w_bits_strb(bus_buffer_io_lsu_axi_w_bits_strb), + .io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready), + .io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid), + .io_lsu_axi_b_bits_resp(bus_buffer_io_lsu_axi_b_bits_resp), + .io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id), + .io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready), + .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), + .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id), + .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region), + .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache), + .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), + .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), + .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), + .io_lsu_axi_r_bits_data(bus_buffer_io_lsu_axi_r_bits_data), + .io_lsu_axi_r_bits_resp(bus_buffer_io_lsu_axi_r_bits_resp), + .io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en), + .io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q), + .io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(bus_buffer_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_full_any(bus_buffer_io_lsu_bus_buffer_full_any), + .io_lsu_bus_buffer_empty_any(bus_buffer_io_lsu_bus_buffer_empty_any), + .io_ld_byte_hit_buf_lo(bus_buffer_io_ld_byte_hit_buf_lo), + .io_ld_byte_hit_buf_hi(bus_buffer_io_ld_byte_hit_buf_hi), + .io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo), + .io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi), + .io_lsu_nonblock_load_data(bus_buffer_io_lsu_nonblock_load_data) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 103:18] + assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_len = 8'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_burst = 2'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_lock = 1'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_prot = 3'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_qos = 4'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 131:51] + assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 131:51] + assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 131:51] + assign io_axi_w_bits_last = 1'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_b_ready = 1'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_len = 8'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_burst = 2'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_lock = 1'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_prot = 3'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_qos = 4'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_r_ready = 1'h1; // @[lsu_bus_intf.scala 131:51] + assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 134:38] + assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 135:38] + assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 136:38] + assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 137:38] + assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 192:27] + assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 133:29] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 143:19] + assign bus_buffer_clock = clock; + assign bus_buffer_reset = reset; + assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 107:51] + assign bus_buffer_io_lsu_bus_obuf_c1_clken = io_lsu_bus_obuf_c1_clken; // @[lsu_bus_intf.scala 105:51] + assign bus_buffer_io_lsu_busm_clken = io_lsu_busm_clken; // @[lsu_bus_intf.scala 106:51] + assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 108:51] + assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 109:51] + assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 111:51] + assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 112:51] + assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 114:51] + assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 117:27] + assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 117:27] + assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 121:51] + assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 122:51] + assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 123:51] + assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 124:51] + assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 125:51] + assign bus_buffer_io_no_word_merge_r = _T_19 & _T_21; // @[lsu_bus_intf.scala 144:51] + assign bus_buffer_io_no_dword_merge_r = _T_19 & _T_27; // @[lsu_bus_intf.scala 145:51] + assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 127:51] + assign bus_buffer_io_ld_full_hit_m = _T_369 & _T_370; // @[lsu_bus_intf.scala 151:51] + assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 128:51] + assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 129:51] + assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 130:51] + assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 146:51] + assign bus_buffer_io_ldst_dual_d = io_ldst_dual_d; // @[lsu_bus_intf.scala 147:51] + assign bus_buffer_io_ldst_dual_m = io_ldst_dual_m; // @[lsu_bus_intf.scala 148:51] + assign bus_buffer_io_ldst_dual_r = io_ldst_dual_r; // @[lsu_bus_intf.scala 149:51] + assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 150:51] + assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 132:51] + assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 152:51] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + ldst_byteen_r = _RAND_0[3:0]; + _RAND_1 = {1{`RANDOM}}; + lsu_bus_clk_en_q = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + is_sideeffects_r = _RAND_2[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + ldst_byteen_r = 4'h0; + end + if (reset) begin + lsu_bus_clk_en_q = 1'h0; + end + if (reset) begin + is_sideeffects_r = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + ldst_byteen_r <= 4'h0; + end else begin + ldst_byteen_r <= _T_6 | _T_5; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + lsu_bus_clk_en_q <= 1'h0; + end else begin + lsu_bus_clk_en_q <= io_lsu_bus_clk_en; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + is_sideeffects_r <= 1'h0; + end else begin + is_sideeffects_r <= io_is_sideeffects_m; + end + end +endmodule diff --git a/lsu_lsc_ctl.anno.json b/lsu_lsc_ctl.anno.json new file mode 100644 index 00000000..0a7903d3 --- /dev/null +++ b/lsu_lsc_ctl.anno.json @@ -0,0 +1,331 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_addr", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_store_data_m", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_picm_mask_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dma", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dma", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_stack", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_valid", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_dccm_req", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_valid", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_m_up", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_unsign", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_incr", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_by", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_dccm_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_corr_r", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"lsu_lsc_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"lsu_lsc_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/lsu_lsc_ctl.fir b/lsu_lsc_ctl.fir new file mode 100644 index 00000000..76a95948 --- /dev/null +++ b/lsu_lsc_ctl.fir @@ -0,0 +1,987 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit lsu_lsc_ctl : + module lsu_addrcheck : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} + + node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 370:27] + node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 370:49] + wire start_addr_in_dccm_d : UInt<1> @[lib.scala 371:26] + node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 375:24] + node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 375:39] + start_addr_in_dccm_d <= _T_2 @[lib.scala 375:16] + node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 370:27] + node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 370:49] + wire end_addr_in_dccm_d : UInt<1> @[lib.scala 371:26] + node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 375:24] + node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 375:39] + end_addr_in_dccm_d <= _T_5 @[lib.scala 375:16] + wire addr_in_iccm : UInt<1> + addr_in_iccm <= UInt<1>("h00") + node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37] + node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45] + addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18] + node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89] + node _T_9 = bits(_T_8, 31, 28) @[lib.scala 370:27] + node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 370:49] + wire start_addr_in_pic_d : UInt<1> @[lib.scala 371:26] + node _T_10 = bits(_T_8, 31, 15) @[lib.scala 375:24] + node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 375:39] + start_addr_in_pic_d <= _T_11 @[lib.scala 375:16] + node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83] + node _T_13 = bits(_T_12, 31, 28) @[lib.scala 370:27] + node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 370:49] + wire end_addr_in_pic_d : UInt<1> @[lib.scala 371:26] + node _T_14 = bits(_T_12, 31, 15) @[lib.scala 375:24] + node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 375:39] + end_addr_in_pic_d <= _T_15 @[lib.scala 375:16] + node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60] + node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49] + node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55] + node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74] + node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109] + node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115] + node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91] + node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57] + io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32] + node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56] + io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32] + node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63] + node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33] + io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30] + node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51] + node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50] + node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50] + node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92] + node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62] + node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60] + node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137] + node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185] + node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158] + node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80] + node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56] + node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134] + node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138] + node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116] + node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90] + node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148] + node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58] + node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58] + node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58] + node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99] + node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33] + node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49] + node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56] + node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121] + node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88] + node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30] + node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49] + node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56] + node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121] + node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88] + node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30] + node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153] + node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49] + node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56] + node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121] + node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88] + node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30] + node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153] + node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49] + node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56] + node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121] + node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88] + node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30] + node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153] + node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49] + node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56] + node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121] + node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88] + node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30] + node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153] + node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49] + node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56] + node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121] + node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88] + node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30] + node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153] + node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49] + node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56] + node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121] + node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88] + node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30] + node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153] + node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49] + node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56] + node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121] + node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88] + node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30] + node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153] + node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48] + node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57] + node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122] + node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89] + node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31] + node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49] + node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58] + node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123] + node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90] + node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32] + node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154] + node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49] + node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58] + node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123] + node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90] + node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32] + node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155] + node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49] + node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58] + node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123] + node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90] + node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32] + node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155] + node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49] + node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58] + node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123] + node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90] + node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32] + node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155] + node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49] + node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58] + node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123] + node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90] + node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32] + node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155] + node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49] + node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58] + node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123] + node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90] + node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32] + node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155] + node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49] + node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58] + node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123] + node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90] + node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32] + node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155] + node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7] + node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104] + node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57] + node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70] + node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76] + node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92] + node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90] + node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51] + wire unmapped_access_fault_d : UInt<1> + unmapped_access_fault_d <= UInt<1>("h01") + wire mpu_access_fault_d : UInt<1> + mpu_access_fault_d <= UInt<1>("h01") + node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64] + node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62] + node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36] + node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34] + node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112] + node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29] + node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85] + node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29] + node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85] + unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29] + node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33] + node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64] + node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62] + mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29] + node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49] + node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70] + node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92] + node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118] + node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141] + node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139] + io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21] + node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60] + node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100] + node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144] + node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185] + node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164] + node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120] + node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80] + node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35] + node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53] + node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78] + node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61] + node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59] + node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57] + node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90] + node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57] + node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113] + node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136] + node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134] + io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25] + node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111] + node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80] + node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39] + node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50] + node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84] + node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113] + node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27] + io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21] + node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66] + node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64] + node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120] + node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118] + node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88] + node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142] + node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163] + io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31] + node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66] + node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36] + node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95] + node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116] + io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33] + reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60] + _T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60] + io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50] + + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_lsc_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} + + wire end_addr_pre_m : UInt<29> + end_addr_pre_m <= UInt<29>("h00") + wire end_addr_pre_r : UInt<29> + end_addr_pre_r <= UInt<29>("h00") + wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 93:29] + wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 94:29] + wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29] + wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 96:29] + wire _T : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 97:35] + _T.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + lsu_error_pkt_m.bits.addr <= _T.bits.addr @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.mscause <= _T.bits.mscause @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.exc_type <= _T.bits.exc_type @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.inst_type <= _T.bits.inst_type @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.single_ecc_error <= _T.bits.single_ecc_error @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.valid <= _T.valid @[lsu_lsc_ctl.scala 97:20] + node _T_1 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 99:52] + node lsu_rs1_d = mux(_T_1, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 99:28] + node _T_2 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 100:44] + node _T_3 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node lsu_offset_d = and(_T_2, _T_4) @[lsu_lsc_ctl.scala 100:51] + node _T_5 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 103:66] + node rs1_d = mux(_T_5, io.lsu_exu.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 103:28] + node _T_6 = bits(rs1_d, 11, 0) @[lib.scala 92:31] + node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58] + node _T_8 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60] + node _T_9 = cat(UInt<1>("h00"), _T_8) @[Cat.scala 29:58] + node _T_10 = add(_T_7, _T_9) @[lib.scala 92:39] + node _T_11 = tail(_T_10, 1) @[lib.scala 92:39] + node _T_12 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41] + node _T_13 = bits(_T_11, 12, 12) @[lib.scala 93:50] + node _T_14 = xor(_T_12, _T_13) @[lib.scala 93:46] + node _T_15 = not(_T_14) @[lib.scala 93:33] + node _T_16 = bits(_T_15, 0, 0) @[Bitwise.scala 72:15] + node _T_17 = mux(_T_16, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_18 = bits(rs1_d, 31, 12) @[lib.scala 93:63] + node _T_19 = and(_T_17, _T_18) @[lib.scala 93:58] + node _T_20 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25] + node _T_21 = not(_T_20) @[lib.scala 94:18] + node _T_22 = bits(_T_11, 12, 12) @[lib.scala 94:34] + node _T_23 = and(_T_21, _T_22) @[lib.scala 94:30] + node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15] + node _T_25 = mux(_T_24, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_26 = bits(rs1_d, 31, 12) @[lib.scala 94:47] + node _T_27 = add(_T_26, UInt<1>("h01")) @[lib.scala 94:54] + node _T_28 = tail(_T_27, 1) @[lib.scala 94:54] + node _T_29 = and(_T_25, _T_28) @[lib.scala 94:41] + node _T_30 = or(_T_19, _T_29) @[lib.scala 93:72] + node _T_31 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24] + node _T_32 = bits(_T_11, 12, 12) @[lib.scala 95:34] + node _T_33 = not(_T_32) @[lib.scala 95:31] + node _T_34 = and(_T_31, _T_33) @[lib.scala 95:29] + node _T_35 = bits(_T_34, 0, 0) @[Bitwise.scala 72:15] + node _T_36 = mux(_T_35, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_37 = bits(rs1_d, 31, 12) @[lib.scala 95:47] + node _T_38 = sub(_T_37, UInt<1>("h01")) @[lib.scala 95:54] + node _T_39 = tail(_T_38, 1) @[lib.scala 95:54] + node _T_40 = and(_T_36, _T_39) @[lib.scala 95:41] + node _T_41 = or(_T_30, _T_40) @[lib.scala 94:61] + node _T_42 = bits(_T_11, 11, 0) @[lib.scala 96:22] + node full_addr_d = cat(_T_41, _T_42) @[Cat.scala 29:58] + node _T_43 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_44 = mux(_T_43, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_45 = and(_T_44, UInt<3>("h01")) @[lsu_lsc_ctl.scala 108:58] + node _T_46 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_47 = mux(_T_46, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_48 = and(_T_47, UInt<3>("h03")) @[lsu_lsc_ctl.scala 109:40] + node _T_49 = or(_T_45, _T_48) @[lsu_lsc_ctl.scala 108:70] + node _T_50 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15] + node _T_51 = mux(_T_50, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_52 = and(_T_51, UInt<3>("h07")) @[lsu_lsc_ctl.scala 110:40] + node addr_offset_d = or(_T_49, _T_52) @[lsu_lsc_ctl.scala 109:52] + node _T_53 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 112:39] + node _T_54 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 112:52] + node _T_55 = cat(_T_53, _T_54) @[Cat.scala 29:58] + node _T_56 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_57 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 112:91] + node _T_58 = cat(_T_56, _T_57) @[Cat.scala 29:58] + node _T_59 = add(_T_55, _T_58) @[lsu_lsc_ctl.scala 112:60] + node end_addr_offset_d = tail(_T_59, 1) @[lsu_lsc_ctl.scala 112:60] + node _T_60 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 113:32] + node _T_61 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 113:70] + node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] + node _T_63 = mux(_T_62, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] + node _T_64 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 113:93] + node _T_65 = cat(_T_63, _T_64) @[Cat.scala 29:58] + node _T_66 = add(_T_60, _T_65) @[lsu_lsc_ctl.scala 113:39] + node full_end_addr_d = tail(_T_66, 1) @[lsu_lsc_ctl.scala 113:39] + io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 114:24] + inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 117:25] + addrcheck.clock <= clock + addrcheck.reset <= reset + addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 121:42] + addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 122:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 124:42] + node _T_67 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 125:50] + addrcheck.io.rs1_region_d <= _T_67 @[lsu_lsc_ctl.scala 125:42] + addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 126:42] + io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 127:42] + io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 128:42] + io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 129:42] + addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 136:42] + wire exc_mscause_r : UInt<4> + exc_mscause_r <= UInt<4>("h00") + wire fir_dccm_access_error_r : UInt<1> + fir_dccm_access_error_r <= UInt<1>("h00") + wire fir_nondccm_access_error_r : UInt<1> + fir_nondccm_access_error_r <= UInt<1>("h00") + wire access_fault_r : UInt<1> + access_fault_r <= UInt<1>("h00") + wire misaligned_fault_r : UInt<1> + misaligned_fault_r <= UInt<1>("h00") + wire lsu_fir_error_m : UInt<2> + lsu_fir_error_m <= UInt<2>("h00") + wire fir_dccm_access_error_m : UInt<1> + fir_dccm_access_error_m <= UInt<1>("h00") + wire fir_nondccm_access_error_m : UInt<1> + fir_nondccm_access_error_m <= UInt<1>("h00") + reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 148:75] + access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 148:75] + reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75] + misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 149:75] + reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75] + exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 150:75] + reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75] + _T_68 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 151:75] + fir_dccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 151:38] + reg _T_69 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75] + _T_69 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 152:75] + fir_nondccm_access_error_m <= _T_69 @[lsu_lsc_ctl.scala 152:38] + node _T_70 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 154:34] + io.lsu_exc_m <= _T_70 @[lsu_lsc_ctl.scala 154:16] + node _T_71 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 155:64] + node _T_72 = and(io.lsu_single_ecc_error_r, _T_71) @[lsu_lsc_ctl.scala 155:62] + node _T_73 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 155:111] + node _T_74 = and(_T_72, _T_73) @[lsu_lsc_ctl.scala 155:92] + node _T_75 = and(_T_74, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 155:136] + io.lsu_single_ecc_error_incr <= _T_75 @[lsu_lsc_ctl.scala 155:32] + node _T_76 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 177:46] + node _T_77 = or(_T_76, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 177:67] + node _T_78 = and(_T_77, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 177:96] + node _T_79 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:119] + node _T_80 = and(_T_78, _T_79) @[lsu_lsc_ctl.scala 177:117] + node _T_81 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:144] + node _T_82 = and(_T_80, _T_81) @[lsu_lsc_ctl.scala 177:142] + node _T_83 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:174] + node _T_84 = and(_T_82, _T_83) @[lsu_lsc_ctl.scala 177:172] + lsu_error_pkt_m.valid <= _T_84 @[lsu_lsc_ctl.scala 177:27] + node _T_85 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:75] + node _T_86 = and(io.lsu_single_ecc_error_m, _T_85) @[lsu_lsc_ctl.scala 178:73] + node _T_87 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:101] + node _T_88 = and(_T_86, _T_87) @[lsu_lsc_ctl.scala 178:99] + lsu_error_pkt_m.bits.single_ecc_error <= _T_88 @[lsu_lsc_ctl.scala 178:43] + lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 179:43] + node _T_89 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 180:46] + lsu_error_pkt_m.bits.exc_type <= _T_89 @[lsu_lsc_ctl.scala 180:43] + node _T_90 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:80] + node _T_91 = and(io.lsu_double_ecc_error_m, _T_90) @[lsu_lsc_ctl.scala 181:78] + node _T_92 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:102] + node _T_93 = and(_T_91, _T_92) @[lsu_lsc_ctl.scala 181:100] + node _T_94 = eq(_T_93, UInt<1>("h01")) @[lsu_lsc_ctl.scala 181:118] + node _T_95 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 181:149] + node _T_96 = mux(_T_94, UInt<4>("h01"), _T_95) @[lsu_lsc_ctl.scala 181:49] + lsu_error_pkt_m.bits.mscause <= _T_96 @[lsu_lsc_ctl.scala 181:43] + node _T_97 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 182:59] + lsu_error_pkt_m.bits.addr <= _T_97 @[lsu_lsc_ctl.scala 182:43] + node _T_98 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:72] + node _T_99 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:117] + node _T_100 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 183:166] + node _T_101 = bits(_T_100, 0, 0) @[lsu_lsc_ctl.scala 183:195] + node _T_102 = mux(_T_101, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 183:137] + node _T_103 = mux(_T_99, UInt<2>("h02"), _T_102) @[lsu_lsc_ctl.scala 183:92] + node _T_104 = mux(_T_98, UInt<2>("h03"), _T_103) @[lsu_lsc_ctl.scala 183:44] + lsu_fir_error_m <= _T_104 @[lsu_lsc_ctl.scala 183:38] + node _T_105 = or(lsu_error_pkt_m.valid, lsu_error_pkt_m.bits.single_ecc_error) @[lsu_lsc_ctl.scala 184:73] + node _T_106 = or(_T_105, io.clk_override) @[lsu_lsc_ctl.scala 184:113] + node _T_107 = bits(_T_106, 0, 0) @[lib.scala 8:44] + node _T_108 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr of rvclkhdr @[lib.scala 417:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 419:18] + rvclkhdr.io.en <= _T_107 @[lib.scala 420:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 421:24] + wire _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 423:50] + _T_109.bits.addr <= UInt<32>("h00") @[lib.scala 423:50] + _T_109.bits.mscause <= UInt<4>("h00") @[lib.scala 423:50] + _T_109.bits.exc_type <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.bits.inst_type <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.valid <= UInt<1>("h00") @[lib.scala 423:50] + reg _T_110 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, clock with : (reset => (reset, _T_109)) @[Reg.scala 27:20] + when _T_107 : @[Reg.scala 28:19] + _T_110.bits.addr <= lsu_error_pkt_m.bits.addr @[Reg.scala 28:23] + _T_110.bits.mscause <= lsu_error_pkt_m.bits.mscause @[Reg.scala 28:23] + _T_110.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[Reg.scala 28:23] + _T_110.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[Reg.scala 28:23] + _T_110.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[Reg.scala 28:23] + _T_110.valid <= lsu_error_pkt_m.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.lsu_error_pkt_r.bits.addr <= _T_110.bits.addr @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.mscause <= _T_110.bits.mscause @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.exc_type <= _T_110.bits.exc_type @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.inst_type <= _T_110.bits.inst_type @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.single_ecc_error <= _T_110.bits.single_ecc_error @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.valid <= _T_110.valid @[lsu_lsc_ctl.scala 184:24] + reg _T_111 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 185:83] + _T_111 <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 185:83] + io.lsu_error_pkt_r.bits.single_ecc_error <= _T_111 @[lsu_lsc_ctl.scala 185:46] + reg _T_112 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 186:67] + _T_112 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 186:67] + io.lsu_error_pkt_r.valid <= _T_112 @[lsu_lsc_ctl.scala 186:30] + reg _T_113 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:75] + _T_113 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 187:75] + io.lsu_fir_error <= _T_113 @[lsu_lsc_ctl.scala 187:38] + dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 189:27] + dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:26] + dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27] + dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22] + dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27] + dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27] + node _T_114 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30] + dma_pkt_d.bits.load <= _T_114 @[lsu_lsc_ctl.scala 195:27] + node _T_115 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56] + node _T_116 = eq(_T_115, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62] + dma_pkt_d.bits.by <= _T_116 @[lsu_lsc_ctl.scala 196:27] + node _T_117 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56] + node _T_118 = eq(_T_117, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62] + dma_pkt_d.bits.half <= _T_118 @[lsu_lsc_ctl.scala 197:27] + node _T_119 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56] + node _T_120 = eq(_T_119, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62] + dma_pkt_d.bits.word <= _T_120 @[lsu_lsc_ctl.scala 198:27] + node _T_121 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56] + node _T_122 = eq(_T_121, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62] + dma_pkt_d.bits.dword <= _T_122 @[lsu_lsc_ctl.scala 199:27] + dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39] + dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39] + dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39] + wire lsu_ld_datafn_r : UInt<32> + lsu_ld_datafn_r <= UInt<32>("h00") + wire lsu_ld_datafn_corr_r : UInt<32> + lsu_ld_datafn_corr_r <= UInt<32>("h00") + wire lsu_ld_datafn_m : UInt<32> + lsu_ld_datafn_m <= UInt<32>("h00") + node _T_123 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50] + node _T_124 = mux(_T_123, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26] + io.lsu_pkt_d.bits.store_data_bypass_m <= _T_124.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_124.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.store_data_bypass_d <= _T_124.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.dma <= _T_124.bits.dma @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.unsign <= _T_124.bits.unsign @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.store <= _T_124.bits.store @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.load <= _T_124.bits.load @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.dword <= _T_124.bits.dword @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.word <= _T_124.bits.word @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.half <= _T_124.bits.half @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.by <= _T_124.bits.by @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.stack <= _T_124.bits.stack @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.fast_int <= _T_124.bits.fast_int @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.valid <= _T_124.valid @[lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20] + node _T_125 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64] + node _T_126 = and(io.flush_m_up, _T_125) @[lsu_lsc_ctl.scala 212:61] + node _T_127 = eq(_T_126, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45] + node _T_128 = and(io.lsu_p.valid, _T_127) @[lsu_lsc_ctl.scala 212:43] + node _T_129 = or(_T_128, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90] + io.lsu_pkt_d.valid <= _T_129 @[lsu_lsc_ctl.scala 212:24] + node _T_130 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68] + node _T_131 = and(io.flush_m_up, _T_130) @[lsu_lsc_ctl.scala 213:65] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49] + node _T_133 = and(io.lsu_pkt_d.valid, _T_132) @[lsu_lsc_ctl.scala 213:47] + lsu_pkt_m_in.valid <= _T_133 @[lsu_lsc_ctl.scala 213:24] + node _T_134 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68] + node _T_135 = and(io.flush_m_up, _T_134) @[lsu_lsc_ctl.scala 214:65] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49] + node _T_137 = and(io.lsu_pkt_m.valid, _T_136) @[lsu_lsc_ctl.scala 214:47] + lsu_pkt_r_in.valid <= _T_137 @[lsu_lsc_ctl.scala 214:24] + wire _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + reg _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_138)) @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65] + _T_139.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65] + io.lsu_pkt_m.bits.store_data_bypass_m <= _T_139.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_139.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.store_data_bypass_d <= _T_139.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.dma <= _T_139.bits.dma @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.unsign <= _T_139.bits.unsign @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.store <= _T_139.bits.store @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.load <= _T_139.bits.load @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.dword <= _T_139.bits.dword @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.word <= _T_139.bits.word @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.half <= _T_139.bits.half @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.by <= _T_139.bits.by @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.stack <= _T_139.bits.stack @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.fast_int <= _T_139.bits.fast_int @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.valid <= _T_139.valid @[lsu_lsc_ctl.scala 216:28] + wire _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + reg _T_141 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_140)) @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65] + _T_141.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65] + io.lsu_pkt_r.bits.store_data_bypass_m <= _T_141.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_141.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.store_data_bypass_d <= _T_141.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.dma <= _T_141.bits.dma @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.unsign <= _T_141.bits.unsign @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.store <= _T_141.bits.store @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.load <= _T_141.bits.load @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.dword <= _T_141.bits.dword @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.word <= _T_141.bits.word @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.half <= _T_141.bits.half @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.by <= _T_141.bits.by @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.stack <= _T_141.bits.stack @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.fast_int <= _T_141.bits.fast_int @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.valid <= _T_141.valid @[lsu_lsc_ctl.scala 217:28] + reg _T_142 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65] + _T_142 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65] + io.lsu_pkt_m.valid <= _T_142 @[lsu_lsc_ctl.scala 218:28] + reg _T_143 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65] + _T_143 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65] + io.lsu_pkt_r.valid <= _T_143 @[lsu_lsc_ctl.scala 219:28] + node _T_144 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59] + node _T_145 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100] + node _T_146 = cat(_T_145, UInt<3>("h00")) @[Cat.scala 29:58] + node dma_mem_wdata_shifted = dshr(_T_144, _T_146) @[lsu_lsc_ctl.scala 221:66] + node _T_147 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63] + node _T_148 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91] + node _T_149 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122] + node store_data_d = mux(_T_147, _T_148, _T_149) @[lsu_lsc_ctl.scala 222:34] + node _T_150 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73] + node _T_151 = bits(io.lsu_exu.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:103] + node _T_152 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:122] + node store_data_m_in = mux(_T_150, _T_151, _T_152) @[lsu_lsc_ctl.scala 223:34] + node _T_153 = bits(io.lsu_addr_d, 2, 2) @[lsu_lsc_ctl.scala 225:61] + reg _T_154 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:47] + _T_154 <= _T_153 @[lsu_lsc_ctl.scala 225:47] + node _T_155 = bits(io.end_addr_d, 2, 2) @[lsu_lsc_ctl.scala 225:123] + reg _T_156 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:109] + _T_156 <= _T_155 @[lsu_lsc_ctl.scala 225:109] + node int = neq(_T_154, _T_156) @[lsu_lsc_ctl.scala 225:71] + node _T_157 = bits(io.lsu_addr_m, 2, 2) @[lsu_lsc_ctl.scala 226:62] + reg _T_158 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:48] + _T_158 <= _T_157 @[lsu_lsc_ctl.scala 226:48] + node _T_159 = bits(io.end_addr_m, 2, 2) @[lsu_lsc_ctl.scala 226:124] + reg _T_160 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:110] + _T_160 <= _T_159 @[lsu_lsc_ctl.scala 226:110] + node int1 = neq(_T_158, _T_160) @[lsu_lsc_ctl.scala 226:72] + reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:72] + store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 229:72] + reg _T_161 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:62] + _T_161 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 230:62] + io.lsu_addr_m <= _T_161 @[lsu_lsc_ctl.scala 230:24] + reg _T_162 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 231:62] + _T_162 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 231:62] + io.lsu_addr_r <= _T_162 @[lsu_lsc_ctl.scala 231:24] + node _T_163 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:60] + node _T_164 = mux(int, end_addr_pre_m, _T_163) @[lsu_lsc_ctl.scala 232:27] + node _T_165 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 232:117] + reg _T_166 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:103] + _T_166 <= _T_165 @[lsu_lsc_ctl.scala 232:103] + node _T_167 = cat(_T_164, _T_166) @[Cat.scala 29:58] + io.end_addr_m <= _T_167 @[lsu_lsc_ctl.scala 232:17] + node _T_168 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 233:61] + node _T_169 = mux(int1, end_addr_pre_r, _T_168) @[lsu_lsc_ctl.scala 233:27] + node _T_170 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 233:118] + reg _T_171 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:104] + _T_171 <= _T_170 @[lsu_lsc_ctl.scala 233:104] + node _T_172 = cat(_T_169, _T_171) @[Cat.scala 29:58] + io.end_addr_r <= _T_172 @[lsu_lsc_ctl.scala 233:17] + node _T_173 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 234:41] + node _T_174 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 234:69] + node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 234:87] + node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_175 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_175 : @[Reg.scala 28:19] + _T_177 <= _T_173 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + end_addr_pre_m <= _T_177 @[lsu_lsc_ctl.scala 234:18] + node _T_178 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 235:41] + node _T_179 = and(io.lsu_pkt_m.valid, int) @[lsu_lsc_ctl.scala 235:69] + node _T_180 = or(_T_179, io.clk_override) @[lsu_lsc_ctl.scala 235:76] + node _T_181 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_180 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_182 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_180 : @[Reg.scala 28:19] + _T_182 <= _T_178 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + end_addr_pre_r <= _T_182 @[lsu_lsc_ctl.scala 235:18] + reg _T_183 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62] + _T_183 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 236:62] + io.addr_in_dccm_m <= _T_183 @[lsu_lsc_ctl.scala 236:24] + reg _T_184 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62] + _T_184 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 237:62] + io.addr_in_dccm_r <= _T_184 @[lsu_lsc_ctl.scala 237:24] + reg _T_185 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:62] + _T_185 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 238:62] + io.addr_in_pic_m <= _T_185 @[lsu_lsc_ctl.scala 238:24] + reg _T_186 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 239:62] + _T_186 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 239:62] + io.addr_in_pic_r <= _T_186 @[lsu_lsc_ctl.scala 239:24] + reg _T_187 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 240:62] + _T_187 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 240:62] + io.addr_external_m <= _T_187 @[lsu_lsc_ctl.scala 240:24] + reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 241:66] + addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 241:66] + node _T_188 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 242:77] + node _T_189 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_188 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_188 : @[Reg.scala 28:19] + bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_190 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 245:52] + io.lsu_fir_addr <= _T_190 @[lsu_lsc_ctl.scala 245:28] + io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 247:28] + node _T_191 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 249:68] + node _T_192 = and(io.lsu_pkt_r.valid, _T_191) @[lsu_lsc_ctl.scala 249:41] + node _T_193 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 249:96] + node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 249:94] + node _T_195 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 249:110] + node _T_196 = and(_T_194, _T_195) @[lsu_lsc_ctl.scala 249:108] + io.lsu_commit_r <= _T_196 @[lsu_lsc_ctl.scala 249:19] + node _T_197 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 250:52] + node _T_198 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 250:69] + node _T_199 = bits(_T_198, 0, 0) @[Bitwise.scala 72:15] + node _T_200 = mux(_T_199, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_201 = or(_T_197, _T_200) @[lsu_lsc_ctl.scala 250:59] + node _T_202 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 250:133] + node _T_203 = mux(_T_202, io.lsu_exu.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 250:94] + node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 250:89] + io.store_data_m <= _T_204 @[lsu_lsc_ctl.scala 250:29] + node _T_205 = mux(io.addr_external_m, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 271:33] + lsu_ld_datafn_m <= _T_205 @[lsu_lsc_ctl.scala 271:27] + node _T_206 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 272:49] + node _T_207 = mux(_T_206, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 272:33] + lsu_ld_datafn_corr_r <= _T_207 @[lsu_lsc_ctl.scala 272:27] + node _T_208 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 273:74] + node _T_209 = bits(_T_208, 0, 0) @[Bitwise.scala 72:15] + node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_211 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 273:133] + node _T_212 = cat(UInt<24>("h00"), _T_211) @[Cat.scala 29:58] + node _T_213 = and(_T_210, _T_212) @[lsu_lsc_ctl.scala 273:102] + node _T_214 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 274:43] + node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15] + node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_217 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 274:102] + node _T_218 = cat(UInt<16>("h00"), _T_217) @[Cat.scala 29:58] + node _T_219 = and(_T_216, _T_218) @[lsu_lsc_ctl.scala 274:71] + node _T_220 = or(_T_213, _T_219) @[lsu_lsc_ctl.scala 273:141] + node _T_221 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 275:17] + node _T_222 = and(_T_221, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 275:43] + node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15] + node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_225 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 275:102] + node _T_226 = bits(_T_225, 0, 0) @[Bitwise.scala 72:15] + node _T_227 = mux(_T_226, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_228 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 275:125] + node _T_229 = cat(_T_227, _T_228) @[Cat.scala 29:58] + node _T_230 = and(_T_224, _T_229) @[lsu_lsc_ctl.scala 275:71] + node _T_231 = or(_T_220, _T_230) @[lsu_lsc_ctl.scala 274:114] + node _T_232 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 276:17] + node _T_233 = and(_T_232, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 276:43] + node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15] + node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_236 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 276:101] + node _T_237 = bits(_T_236, 0, 0) @[Bitwise.scala 72:15] + node _T_238 = mux(_T_237, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_239 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 276:125] + node _T_240 = cat(_T_238, _T_239) @[Cat.scala 29:58] + node _T_241 = and(_T_235, _T_240) @[lsu_lsc_ctl.scala 276:71] + node _T_242 = or(_T_231, _T_241) @[lsu_lsc_ctl.scala 275:134] + node _T_243 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_244 = mux(_T_243, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_245 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 277:60] + node _T_246 = and(_T_244, _T_245) @[lsu_lsc_ctl.scala 277:43] + node _T_247 = or(_T_242, _T_246) @[lsu_lsc_ctl.scala 276:134] + io.lsu_exu.lsu_result_m <= _T_247 @[lsu_lsc_ctl.scala 273:35] + node _T_248 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 278:66] + node _T_249 = bits(_T_248, 0, 0) @[Bitwise.scala 72:15] + node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_251 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 278:130] + node _T_252 = cat(UInt<24>("h00"), _T_251) @[Cat.scala 29:58] + node _T_253 = and(_T_250, _T_252) @[lsu_lsc_ctl.scala 278:94] + node _T_254 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 279:43] + node _T_255 = bits(_T_254, 0, 0) @[Bitwise.scala 72:15] + node _T_256 = mux(_T_255, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_257 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 279:107] + node _T_258 = cat(UInt<16>("h00"), _T_257) @[Cat.scala 29:58] + node _T_259 = and(_T_256, _T_258) @[lsu_lsc_ctl.scala 279:71] + node _T_260 = or(_T_253, _T_259) @[lsu_lsc_ctl.scala 278:138] + node _T_261 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 280:17] + node _T_262 = and(_T_261, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 280:43] + node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15] + node _T_264 = mux(_T_263, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 280:107] + node _T_266 = bits(_T_265, 0, 0) @[Bitwise.scala 72:15] + node _T_267 = mux(_T_266, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_268 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 280:135] + node _T_269 = cat(_T_267, _T_268) @[Cat.scala 29:58] + node _T_270 = and(_T_264, _T_269) @[lsu_lsc_ctl.scala 280:71] + node _T_271 = or(_T_260, _T_270) @[lsu_lsc_ctl.scala 279:119] + node _T_272 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 281:17] + node _T_273 = and(_T_272, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 281:43] + node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15] + node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 281:106] + node _T_277 = bits(_T_276, 0, 0) @[Bitwise.scala 72:15] + node _T_278 = mux(_T_277, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_279 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 281:135] + node _T_280 = cat(_T_278, _T_279) @[Cat.scala 29:58] + node _T_281 = and(_T_275, _T_280) @[lsu_lsc_ctl.scala 281:71] + node _T_282 = or(_T_271, _T_281) @[lsu_lsc_ctl.scala 280:144] + node _T_283 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_284 = mux(_T_283, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_285 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 282:65] + node _T_286 = and(_T_284, _T_285) @[lsu_lsc_ctl.scala 282:43] + node _T_287 = or(_T_282, _T_286) @[lsu_lsc_ctl.scala 281:144] + io.lsu_result_corr_r <= _T_287 @[lsu_lsc_ctl.scala 278:27] + diff --git a/lsu_lsc_ctl.v b/lsu_lsc_ctl.v new file mode 100644 index 00000000..528cdc60 --- /dev/null +++ b/lsu_lsc_ctl.v @@ -0,0 +1,1500 @@ +module lsu_addrcheck( + input reset, + input io_lsu_c2_m_clk, + input [31:0] io_start_addr_d, + input [31:0] io_end_addr_d, + input io_lsu_pkt_d_valid, + input io_lsu_pkt_d_bits_fast_int, + input io_lsu_pkt_d_bits_by, + input io_lsu_pkt_d_bits_half, + input io_lsu_pkt_d_bits_word, + input io_lsu_pkt_d_bits_load, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_d_bits_dma, + input [31:0] io_dec_tlu_mrac_ff, + input [3:0] io_rs1_region_d, + output io_is_sideeffects_m, + output io_addr_in_dccm_d, + output io_addr_in_pic_d, + output io_addr_external_d, + output io_access_fault_d, + output io_misaligned_fault_d, + output [3:0] io_exc_mscause_d, + output io_fir_dccm_access_error_d, + output io_fir_nondccm_access_error_d +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 370:49] + wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 375:39] + wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 370:49] + wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 375:39] + wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45] + wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 375:39] + wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 375:39] + wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60] + wire _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:55] + wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:91] + wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58] + wire [31:0] _T_26 = io_dec_tlu_mrac_ff >> csr_idx; // @[lsu_addrcheck.scala 61:50] + wire _T_29 = start_addr_dccm_or_pic | addr_in_iccm; // @[lsu_addrcheck.scala 61:121] + wire _T_30 = ~_T_29; // @[lsu_addrcheck.scala 61:62] + wire _T_31 = _T_26[0] & _T_30; // @[lsu_addrcheck.scala 61:60] + wire _T_32 = _T_31 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 61:137] + wire _T_33 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[lsu_addrcheck.scala 61:185] + wire is_sideeffects_d = _T_32 & _T_33; // @[lsu_addrcheck.scala 61:158] + wire _T_35 = io_start_addr_d[1:0] == 2'h0; // @[lsu_addrcheck.scala 62:80] + wire _T_36 = io_lsu_pkt_d_bits_word & _T_35; // @[lsu_addrcheck.scala 62:56] + wire _T_38 = ~io_start_addr_d[0]; // @[lsu_addrcheck.scala 62:138] + wire _T_39 = io_lsu_pkt_d_bits_half & _T_38; // @[lsu_addrcheck.scala 62:116] + wire _T_40 = _T_36 | _T_39; // @[lsu_addrcheck.scala 62:90] + wire is_aligned_d = _T_40 | io_lsu_pkt_d_bits_by; // @[lsu_addrcheck.scala 62:148] + wire [31:0] _T_51 = io_start_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 67:56] + wire _T_53 = _T_51 == 32'h7fffffff; // @[lsu_addrcheck.scala 67:88] + wire [31:0] _T_56 = io_start_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 68:56] + wire _T_58 = _T_56 == 32'hffffffff; // @[lsu_addrcheck.scala 68:88] + wire _T_60 = _T_53 | _T_58; // @[lsu_addrcheck.scala 67:153] + wire [31:0] _T_62 = io_start_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 69:56] + wire _T_64 = _T_62 == 32'hbfffffff; // @[lsu_addrcheck.scala 69:88] + wire _T_66 = _T_60 | _T_64; // @[lsu_addrcheck.scala 68:153] + wire [31:0] _T_68 = io_start_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 70:56] + wire _T_70 = _T_68 == 32'h8fffffff; // @[lsu_addrcheck.scala 70:88] + wire _T_72 = _T_66 | _T_70; // @[lsu_addrcheck.scala 69:153] + wire [31:0] _T_98 = io_end_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 76:57] + wire _T_100 = _T_98 == 32'h7fffffff; // @[lsu_addrcheck.scala 76:89] + wire [31:0] _T_103 = io_end_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 77:58] + wire _T_105 = _T_103 == 32'hffffffff; // @[lsu_addrcheck.scala 77:90] + wire _T_107 = _T_100 | _T_105; // @[lsu_addrcheck.scala 76:154] + wire [31:0] _T_109 = io_end_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 78:58] + wire _T_111 = _T_109 == 32'hbfffffff; // @[lsu_addrcheck.scala 78:90] + wire _T_113 = _T_107 | _T_111; // @[lsu_addrcheck.scala 77:155] + wire [31:0] _T_115 = io_end_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 79:58] + wire _T_117 = _T_115 == 32'h8fffffff; // @[lsu_addrcheck.scala 79:90] + wire _T_119 = _T_113 | _T_117; // @[lsu_addrcheck.scala 78:155] + wire non_dccm_access_ok = _T_72 & _T_119; // @[lsu_addrcheck.scala 75:7] + wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[lsu_addrcheck.scala 85:57] + wire _T_146 = io_start_addr_d[1:0] != 2'h0; // @[lsu_addrcheck.scala 86:76] + wire _T_147 = ~io_lsu_pkt_d_bits_word; // @[lsu_addrcheck.scala 86:92] + wire _T_148 = _T_146 | _T_147; // @[lsu_addrcheck.scala 86:90] + wire picm_access_fault_d = io_addr_in_pic_d & _T_148; // @[lsu_addrcheck.scala 86:51] + wire _T_149 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[lsu_addrcheck.scala 91:87] + wire _T_150 = ~_T_149; // @[lsu_addrcheck.scala 91:64] + wire _T_151 = start_addr_in_dccm_region_d & _T_150; // @[lsu_addrcheck.scala 91:62] + wire _T_152 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[lsu_addrcheck.scala 93:57] + wire _T_153 = ~_T_152; // @[lsu_addrcheck.scala 93:36] + wire _T_154 = end_addr_in_dccm_region_d & _T_153; // @[lsu_addrcheck.scala 93:34] + wire _T_155 = _T_151 | _T_154; // @[lsu_addrcheck.scala 91:112] + wire _T_156 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 95:29] + wire _T_157 = _T_155 | _T_156; // @[lsu_addrcheck.scala 93:85] + wire _T_158 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 97:29] + wire unmapped_access_fault_d = _T_157 | _T_158; // @[lsu_addrcheck.scala 95:85] + wire _T_160 = ~start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 99:33] + wire _T_161 = ~non_dccm_access_ok; // @[lsu_addrcheck.scala 99:64] + wire mpu_access_fault_d = _T_160 & _T_161; // @[lsu_addrcheck.scala 99:62] + wire _T_163 = unmapped_access_fault_d | mpu_access_fault_d; // @[lsu_addrcheck.scala 111:49] + wire _T_164 = _T_163 | picm_access_fault_d; // @[lsu_addrcheck.scala 111:70] + wire _T_165 = _T_164 | regpred_access_fault_d; // @[lsu_addrcheck.scala 111:92] + wire _T_166 = _T_165 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 111:118] + wire _T_167 = ~io_lsu_pkt_d_bits_dma; // @[lsu_addrcheck.scala 111:141] + wire [3:0] _T_173 = picm_access_fault_d ? 4'h6 : 4'h0; // @[lsu_addrcheck.scala 112:164] + wire [3:0] _T_174 = regpred_access_fault_d ? 4'h5 : _T_173; // @[lsu_addrcheck.scala 112:120] + wire [3:0] _T_175 = mpu_access_fault_d ? 4'h3 : _T_174; // @[lsu_addrcheck.scala 112:80] + wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_175; // @[lsu_addrcheck.scala 112:35] + wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[lsu_addrcheck.scala 113:61] + wire _T_178 = ~is_aligned_d; // @[lsu_addrcheck.scala 114:59] + wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_178; // @[lsu_addrcheck.scala 114:57] + wire _T_179 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[lsu_addrcheck.scala 115:90] + wire _T_180 = regcross_misaligned_fault_d | _T_179; // @[lsu_addrcheck.scala 115:57] + wire _T_181 = _T_180 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 115:113] + wire [3:0] _T_185 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[lsu_addrcheck.scala 116:80] + wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_185; // @[lsu_addrcheck.scala 116:39] + wire _T_190 = ~start_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:66] + wire _T_191 = start_addr_in_dccm_region_d & _T_190; // @[lsu_addrcheck.scala 118:64] + wire _T_192 = ~end_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:120] + wire _T_193 = end_addr_in_dccm_region_d & _T_192; // @[lsu_addrcheck.scala 118:118] + wire _T_194 = _T_191 | _T_193; // @[lsu_addrcheck.scala 118:88] + wire _T_195 = _T_194 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 118:142] + wire _T_197 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 119:66] + wire _T_198 = ~_T_197; // @[lsu_addrcheck.scala 119:36] + wire _T_199 = _T_198 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 119:95] + reg _T_201; // @[lsu_addrcheck.scala 121:60] + assign io_is_sideeffects_m = _T_201; // @[lsu_addrcheck.scala 121:50] + assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 56:32] + assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 57:32] + assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[lsu_addrcheck.scala 59:30] + assign io_access_fault_d = _T_166 & _T_167; // @[lsu_addrcheck.scala 111:21] + assign io_misaligned_fault_d = _T_181 & _T_167; // @[lsu_addrcheck.scala 115:25] + assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[lsu_addrcheck.scala 117:21] + assign io_fir_dccm_access_error_d = _T_195 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 118:31] + assign io_fir_nondccm_access_error_d = _T_199 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 119:33] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_201 = _RAND_0[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_201 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_201 <= 1'h0; + end else begin + _T_201 <= _T_32 & _T_33; + end + end +endmodule +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module lsu_lsc_ctl( + input clock, + input reset, + input io_clk_override, + input io_lsu_c1_m_clk, + input io_lsu_c1_r_clk, + input io_lsu_c2_m_clk, + input io_lsu_c2_r_clk, + input io_lsu_store_c1_m_clk, + input [31:0] io_lsu_ld_data_r, + input [31:0] io_lsu_ld_data_corr_r, + input io_lsu_single_ecc_error_r, + input io_lsu_double_ecc_error_r, + input [31:0] io_lsu_ld_data_m, + input io_lsu_single_ecc_error_m, + input io_lsu_double_ecc_error_m, + input io_flush_m_up, + input io_flush_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [31:0] io_lsu_exu_exu_lsu_rs1_d, + input [31:0] io_lsu_exu_exu_lsu_rs2_d, + output [31:0] io_lsu_exu_lsu_result_m, + input io_lsu_p_valid, + input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_stack, + input io_lsu_p_bits_by, + input io_lsu_p_bits_half, + input io_lsu_p_bits_word, + input io_lsu_p_bits_dword, + input io_lsu_p_bits_load, + input io_lsu_p_bits_store, + input io_lsu_p_bits_unsign, + input io_lsu_p_bits_dma, + input io_lsu_p_bits_store_data_bypass_d, + input io_lsu_p_bits_load_ldst_bypass_d, + input io_lsu_p_bits_store_data_bypass_m, + input io_dec_lsu_valid_raw_d, + input [11:0] io_dec_lsu_offset_d, + input [31:0] io_picm_mask_data_m, + input [31:0] io_bus_read_data_m, + output [31:0] io_lsu_result_corr_r, + output [31:0] io_lsu_addr_d, + output [31:0] io_lsu_addr_m, + output [31:0] io_lsu_addr_r, + output [31:0] io_end_addr_d, + output [31:0] io_end_addr_m, + output [31:0] io_end_addr_r, + output [31:0] io_store_data_m, + input [31:0] io_dec_tlu_mrac_ff, + output io_lsu_exc_m, + output io_is_sideeffects_m, + output io_lsu_commit_r, + output io_lsu_single_ecc_error_incr, + output io_lsu_error_pkt_r_valid, + output io_lsu_error_pkt_r_bits_single_ecc_error, + output io_lsu_error_pkt_r_bits_inst_type, + output io_lsu_error_pkt_r_bits_exc_type, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, + output [30:0] io_lsu_fir_addr, + output [1:0] io_lsu_fir_error, + output io_addr_in_dccm_d, + output io_addr_in_dccm_m, + output io_addr_in_dccm_r, + output io_addr_in_pic_d, + output io_addr_in_pic_m, + output io_addr_in_pic_r, + output io_addr_external_m, + input io_dma_lsc_ctl_dma_dccm_req, + input [31:0] io_dma_lsc_ctl_dma_mem_addr, + input [2:0] io_dma_lsc_ctl_dma_mem_sz, + input io_dma_lsc_ctl_dma_mem_write, + input [63:0] io_dma_lsc_ctl_dma_mem_wdata, + output io_lsu_pkt_d_valid, + output io_lsu_pkt_d_bits_fast_int, + output io_lsu_pkt_d_bits_stack, + output io_lsu_pkt_d_bits_by, + output io_lsu_pkt_d_bits_half, + output io_lsu_pkt_d_bits_word, + output io_lsu_pkt_d_bits_dword, + output io_lsu_pkt_d_bits_load, + output io_lsu_pkt_d_bits_store, + output io_lsu_pkt_d_bits_unsign, + output io_lsu_pkt_d_bits_dma, + output io_lsu_pkt_d_bits_store_data_bypass_d, + output io_lsu_pkt_d_bits_load_ldst_bypass_d, + output io_lsu_pkt_d_bits_store_data_bypass_m, + output io_lsu_pkt_m_valid, + output io_lsu_pkt_m_bits_fast_int, + output io_lsu_pkt_m_bits_stack, + output io_lsu_pkt_m_bits_by, + output io_lsu_pkt_m_bits_half, + output io_lsu_pkt_m_bits_word, + output io_lsu_pkt_m_bits_dword, + output io_lsu_pkt_m_bits_load, + output io_lsu_pkt_m_bits_store, + output io_lsu_pkt_m_bits_unsign, + output io_lsu_pkt_m_bits_dma, + output io_lsu_pkt_m_bits_store_data_bypass_d, + output io_lsu_pkt_m_bits_load_ldst_bypass_d, + output io_lsu_pkt_m_bits_store_data_bypass_m, + output io_lsu_pkt_r_valid, + output io_lsu_pkt_r_bits_fast_int, + output io_lsu_pkt_r_bits_stack, + output io_lsu_pkt_r_bits_by, + output io_lsu_pkt_r_bits_half, + output io_lsu_pkt_r_bits_word, + output io_lsu_pkt_r_bits_dword, + output io_lsu_pkt_r_bits_load, + output io_lsu_pkt_r_bits_store, + output io_lsu_pkt_r_bits_unsign, + output io_lsu_pkt_r_bits_dma, + output io_lsu_pkt_r_bits_store_data_bypass_d, + output io_lsu_pkt_r_bits_load_ldst_bypass_d, + output io_lsu_pkt_r_bits_store_data_bypass_m, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; +`endif // RANDOMIZE_REG_INIT + wire addrcheck_reset; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_start_addr_d; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_end_addr_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 117:25] + wire [3:0] addrcheck_io_rs1_region_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_external_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_access_fault_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_misaligned_fault_d; // @[lsu_lsc_ctl.scala 117:25] + wire [3:0] addrcheck_io_exc_mscause_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_fir_dccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_fir_nondccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25] + wire rvclkhdr_io_clk; // @[lib.scala 417:23] + wire rvclkhdr_io_en; // @[lib.scala 417:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_lsu_exu_exu_lsu_rs1_d : io_dma_lsc_ctl_dma_mem_addr; // @[lsu_lsc_ctl.scala 99:28] + wire [11:0] _T_4 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] + wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_4; // @[lsu_lsc_ctl.scala 100:51] + wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_exu_lsu_result_m : lsu_rs1_d; // @[lsu_lsc_ctl.scala 103:28] + wire [12:0] _T_7 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58] + wire [12:0] _T_9 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _T_11 = _T_7 + _T_9; // @[lib.scala 92:39] + wire _T_14 = lsu_offset_d[11] ^ _T_11[12]; // @[lib.scala 93:46] + wire _T_15 = ~_T_14; // @[lib.scala 93:33] + wire [19:0] _T_17 = _T_15 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_19 = _T_17 & rs1_d[31:12]; // @[lib.scala 93:58] + wire _T_21 = ~lsu_offset_d[11]; // @[lib.scala 94:18] + wire _T_23 = _T_21 & _T_11[12]; // @[lib.scala 94:30] + wire [19:0] _T_25 = _T_23 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_28 = rs1_d[31:12] + 20'h1; // @[lib.scala 94:54] + wire [19:0] _T_29 = _T_25 & _T_28; // @[lib.scala 94:41] + wire [19:0] _T_30 = _T_19 | _T_29; // @[lib.scala 93:72] + wire _T_33 = ~_T_11[12]; // @[lib.scala 95:31] + wire _T_34 = lsu_offset_d[11] & _T_33; // @[lib.scala 95:29] + wire [19:0] _T_36 = _T_34 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_39 = rs1_d[31:12] - 20'h1; // @[lib.scala 95:54] + wire [19:0] _T_40 = _T_36 & _T_39; // @[lib.scala 95:41] + wire [19:0] _T_41 = _T_30 | _T_40; // @[lib.scala 94:61] + wire [2:0] _T_44 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_45 = _T_44 & 3'h1; // @[lsu_lsc_ctl.scala 108:58] + wire [2:0] _T_47 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_48 = _T_47 & 3'h3; // @[lsu_lsc_ctl.scala 109:40] + wire [2:0] _T_49 = _T_45 | _T_48; // @[lsu_lsc_ctl.scala 108:70] + wire [2:0] _T_51 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] addr_offset_d = _T_49 | _T_51; // @[lsu_lsc_ctl.scala 109:52] + wire [12:0] _T_55 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58] + wire [11:0] _T_58 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _GEN_9 = {{1'd0}, _T_58}; // @[lsu_lsc_ctl.scala 112:60] + wire [12:0] end_addr_offset_d = _T_55 + _GEN_9; // @[lsu_lsc_ctl.scala 112:60] + wire [18:0] _T_63 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_65 = {_T_63,end_addr_offset_d}; // @[Cat.scala 29:58] + reg access_fault_m; // @[lsu_lsc_ctl.scala 148:75] + reg misaligned_fault_m; // @[lsu_lsc_ctl.scala 149:75] + reg [3:0] exc_mscause_m; // @[lsu_lsc_ctl.scala 150:75] + reg fir_dccm_access_error_m; // @[lsu_lsc_ctl.scala 151:75] + reg fir_nondccm_access_error_m; // @[lsu_lsc_ctl.scala 152:75] + wire _T_70 = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:34] + wire _T_71 = ~io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 155:64] + wire _T_72 = io_lsu_single_ecc_error_r & _T_71; // @[lsu_lsc_ctl.scala 155:62] + wire _T_73 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 155:111] + wire _T_74 = _T_72 & _T_73; // @[lsu_lsc_ctl.scala 155:92] + wire _T_77 = _T_70 | io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 177:67] + wire _T_78 = _T_77 & io_lsu_pkt_m_valid; // @[lsu_lsc_ctl.scala 177:96] + wire _T_79 = ~io_lsu_pkt_m_bits_dma; // @[lsu_lsc_ctl.scala 177:119] + wire _T_80 = _T_78 & _T_79; // @[lsu_lsc_ctl.scala 177:117] + wire _T_81 = ~io_lsu_pkt_m_bits_fast_int; // @[lsu_lsc_ctl.scala 177:144] + wire _T_82 = _T_80 & _T_81; // @[lsu_lsc_ctl.scala 177:142] + wire _T_83 = ~io_flush_m_up; // @[lsu_lsc_ctl.scala 177:174] + wire lsu_error_pkt_m_valid = _T_82 & _T_83; // @[lsu_lsc_ctl.scala 177:172] + wire _T_85 = ~lsu_error_pkt_m_valid; // @[lsu_lsc_ctl.scala 178:75] + wire _T_86 = io_lsu_single_ecc_error_m & _T_85; // @[lsu_lsc_ctl.scala 178:73] + wire lsu_error_pkt_m_bits_single_ecc_error = _T_86 & _T_79; // @[lsu_lsc_ctl.scala 178:99] + wire lsu_error_pkt_m_bits_exc_type = ~misaligned_fault_m; // @[lsu_lsc_ctl.scala 180:46] + wire _T_91 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[lsu_lsc_ctl.scala 181:78] + wire _T_92 = ~access_fault_m; // @[lsu_lsc_ctl.scala 181:102] + wire _T_93 = _T_91 & _T_92; // @[lsu_lsc_ctl.scala 181:100] + wire _T_100 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 183:166] + wire _T_105 = lsu_error_pkt_m_valid | lsu_error_pkt_m_bits_single_ecc_error; // @[lsu_lsc_ctl.scala 184:73] + wire _T_106 = _T_105 | io_clk_override; // @[lsu_lsc_ctl.scala 184:113] + reg _T_110_bits_inst_type; // @[Reg.scala 27:20] + reg _T_110_bits_exc_type; // @[Reg.scala 27:20] + reg [3:0] _T_110_bits_mscause; // @[Reg.scala 27:20] + reg [31:0] _T_110_bits_addr; // @[Reg.scala 27:20] + reg _T_111; // @[lsu_lsc_ctl.scala 185:83] + reg _T_112; // @[lsu_lsc_ctl.scala 186:67] + reg [1:0] _T_113; // @[lsu_lsc_ctl.scala 187:75] + wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 195:30] + wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 196:62] + wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 197:62] + wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 198:62] + wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 199:62] + wire _T_125 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 212:64] + wire _T_126 = io_flush_m_up & _T_125; // @[lsu_lsc_ctl.scala 212:61] + wire _T_127 = ~_T_126; // @[lsu_lsc_ctl.scala 212:45] + wire _T_128 = io_lsu_p_valid & _T_127; // @[lsu_lsc_ctl.scala 212:43] + wire _T_130 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 213:68] + wire _T_131 = io_flush_m_up & _T_130; // @[lsu_lsc_ctl.scala 213:65] + wire _T_132 = ~_T_131; // @[lsu_lsc_ctl.scala 213:49] + wire _T_135 = io_flush_m_up & _T_79; // @[lsu_lsc_ctl.scala 214:65] + wire _T_136 = ~_T_135; // @[lsu_lsc_ctl.scala 214:49] + reg _T_139_bits_fast_int; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_stack; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_by; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_half; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_word; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_dword; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_load; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_store; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_unsign; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_dma; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:65] + reg _T_141_bits_fast_int; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_stack; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_by; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_half; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_word; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_dword; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_load; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_store; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_unsign; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_dma; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:65] + reg _T_142; // @[lsu_lsc_ctl.scala 218:65] + reg _T_143; // @[lsu_lsc_ctl.scala 219:65] + wire [5:0] _T_146 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] + wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_146; // @[lsu_lsc_ctl.scala 221:66] + reg _T_154; // @[lsu_lsc_ctl.scala 225:47] + reg _T_156; // @[lsu_lsc_ctl.scala 225:109] + wire int_ = _T_154 != _T_156; // @[lsu_lsc_ctl.scala 225:71] + reg _T_158; // @[lsu_lsc_ctl.scala 226:48] + reg _T_160; // @[lsu_lsc_ctl.scala 226:110] + wire int1 = _T_158 != _T_160; // @[lsu_lsc_ctl.scala 226:72] + reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 229:72] + reg [31:0] _T_161; // @[lsu_lsc_ctl.scala 230:62] + reg [31:0] _T_162; // @[lsu_lsc_ctl.scala 231:62] + reg [28:0] end_addr_pre_m; // @[Reg.scala 27:20] + wire [28:0] _T_164 = int_ ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 232:27] + reg [2:0] _T_166; // @[lsu_lsc_ctl.scala 232:103] + reg [28:0] end_addr_pre_r; // @[Reg.scala 27:20] + wire [28:0] _T_169 = int1 ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 233:27] + reg [2:0] _T_171; // @[lsu_lsc_ctl.scala 233:104] + wire _T_174 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 234:69] + wire _T_175 = _T_174 | io_clk_override; // @[lsu_lsc_ctl.scala 234:87] + wire _T_179 = io_lsu_pkt_m_valid & int_; // @[lsu_lsc_ctl.scala 235:69] + wire _T_180 = _T_179 | io_clk_override; // @[lsu_lsc_ctl.scala 235:76] + reg _T_183; // @[lsu_lsc_ctl.scala 236:62] + reg _T_184; // @[lsu_lsc_ctl.scala 237:62] + reg _T_185; // @[lsu_lsc_ctl.scala 238:62] + reg _T_186; // @[lsu_lsc_ctl.scala 239:62] + reg _T_187; // @[lsu_lsc_ctl.scala 240:62] + reg addr_external_r; // @[lsu_lsc_ctl.scala 241:66] + wire _T_188 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 242:77] + reg [31:0] bus_read_data_r; // @[Reg.scala 27:20] + wire _T_191 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 249:68] + wire _T_192 = io_lsu_pkt_r_valid & _T_191; // @[lsu_lsc_ctl.scala 249:41] + wire _T_193 = ~io_flush_r; // @[lsu_lsc_ctl.scala 249:96] + wire _T_194 = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 249:94] + wire _T_195 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 249:110] + wire _T_198 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 250:69] + wire [31:0] _T_200 = _T_198 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_201 = io_picm_mask_data_m | _T_200; // @[lsu_lsc_ctl.scala 250:59] + wire [31:0] _T_203 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_exu_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 250:94] + wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 271:33] + wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 272:33] + wire _T_208 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 273:74] + wire [31:0] _T_210 = _T_208 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_213 = _T_210 & _T_212; // @[lsu_lsc_ctl.scala 273:102] + wire _T_214 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 274:43] + wire [31:0] _T_216 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_218 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_219 = _T_216 & _T_218; // @[lsu_lsc_ctl.scala 274:71] + wire [31:0] _T_220 = _T_213 | _T_219; // @[lsu_lsc_ctl.scala 273:141] + wire _T_221 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 275:17] + wire _T_222 = _T_221 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 275:43] + wire [31:0] _T_224 = _T_222 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_227 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = {_T_227,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_230 = _T_224 & _T_229; // @[lsu_lsc_ctl.scala 275:71] + wire [31:0] _T_231 = _T_220 | _T_230; // @[lsu_lsc_ctl.scala 274:114] + wire _T_233 = _T_221 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 276:43] + wire [31:0] _T_235 = _T_233 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_238 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_240 = {_T_238,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_241 = _T_235 & _T_240; // @[lsu_lsc_ctl.scala 276:71] + wire [31:0] _T_242 = _T_231 | _T_241; // @[lsu_lsc_ctl.scala 275:134] + wire [31:0] _T_244 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_244 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 277:43] + wire _T_248 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 278:66] + wire [31:0] _T_250 = _T_248 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_252 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_253 = _T_250 & _T_252; // @[lsu_lsc_ctl.scala 278:94] + wire _T_254 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 279:43] + wire [31:0] _T_256 = _T_254 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_258 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_259 = _T_256 & _T_258; // @[lsu_lsc_ctl.scala 279:71] + wire [31:0] _T_260 = _T_253 | _T_259; // @[lsu_lsc_ctl.scala 278:138] + wire _T_261 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 280:17] + wire _T_262 = _T_261 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 280:43] + wire [31:0] _T_264 = _T_262 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_267 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_269 = {_T_267,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_270 = _T_264 & _T_269; // @[lsu_lsc_ctl.scala 280:71] + wire [31:0] _T_271 = _T_260 | _T_270; // @[lsu_lsc_ctl.scala 279:119] + wire _T_273 = _T_261 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 281:43] + wire [31:0] _T_275 = _T_273 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_278 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = {_T_278,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_281 = _T_275 & _T_280; // @[lsu_lsc_ctl.scala 281:71] + wire [31:0] _T_282 = _T_271 | _T_281; // @[lsu_lsc_ctl.scala 280:144] + wire [31:0] _T_284 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_286 = _T_284 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 282:43] + lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 117:25] + .reset(addrcheck_reset), + .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk), + .io_start_addr_d(addrcheck_io_start_addr_d), + .io_end_addr_d(addrcheck_io_end_addr_d), + .io_lsu_pkt_d_valid(addrcheck_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_fast_int(addrcheck_io_lsu_pkt_d_bits_fast_int), + .io_lsu_pkt_d_bits_by(addrcheck_io_lsu_pkt_d_bits_by), + .io_lsu_pkt_d_bits_half(addrcheck_io_lsu_pkt_d_bits_half), + .io_lsu_pkt_d_bits_word(addrcheck_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_load(addrcheck_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(addrcheck_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_dma(addrcheck_io_lsu_pkt_d_bits_dma), + .io_dec_tlu_mrac_ff(addrcheck_io_dec_tlu_mrac_ff), + .io_rs1_region_d(addrcheck_io_rs1_region_d), + .io_is_sideeffects_m(addrcheck_io_is_sideeffects_m), + .io_addr_in_dccm_d(addrcheck_io_addr_in_dccm_d), + .io_addr_in_pic_d(addrcheck_io_addr_in_pic_d), + .io_addr_external_d(addrcheck_io_addr_external_d), + .io_access_fault_d(addrcheck_io_access_fault_d), + .io_misaligned_fault_d(addrcheck_io_misaligned_fault_d), + .io_exc_mscause_d(addrcheck_io_exc_mscause_d), + .io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d), + .io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d) + ); + rvclkhdr rvclkhdr ( // @[lib.scala 417:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + assign io_lsu_exu_lsu_result_m = _T_242 | _T_246; // @[lsu_lsc_ctl.scala 273:35] + assign io_lsu_result_corr_r = _T_282 | _T_286; // @[lsu_lsc_ctl.scala 278:27] + assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 247:28] + assign io_lsu_addr_m = _T_161; // @[lsu_lsc_ctl.scala 230:24] + assign io_lsu_addr_r = _T_162; // @[lsu_lsc_ctl.scala 231:24] + assign io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 114:24] + assign io_end_addr_m = {_T_164,_T_166}; // @[lsu_lsc_ctl.scala 232:17] + assign io_end_addr_r = {_T_169,_T_171}; // @[lsu_lsc_ctl.scala 233:17] + assign io_store_data_m = _T_201 & _T_203; // @[lsu_lsc_ctl.scala 250:29] + assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:16] + assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 127:42] + assign io_lsu_commit_r = _T_194 & _T_195; // @[lsu_lsc_ctl.scala 249:19] + assign io_lsu_single_ecc_error_incr = _T_74 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 155:32] + assign io_lsu_error_pkt_r_valid = _T_112; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 186:30] + assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_111; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 185:46] + assign io_lsu_error_pkt_r_bits_inst_type = _T_110_bits_inst_type; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_exc_type = _T_110_bits_exc_type; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_mscause = _T_110_bits_mscause; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_addr = _T_110_bits_addr; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 245:28] + assign io_lsu_fir_error = _T_113; // @[lsu_lsc_ctl.scala 187:38] + assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 128:42] + assign io_addr_in_dccm_m = _T_183; // @[lsu_lsc_ctl.scala 236:24] + assign io_addr_in_dccm_r = _T_184; // @[lsu_lsc_ctl.scala 237:24] + assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 129:42] + assign io_addr_in_pic_m = _T_185; // @[lsu_lsc_ctl.scala 238:24] + assign io_addr_in_pic_r = _T_186; // @[lsu_lsc_ctl.scala 239:24] + assign io_addr_external_m = _T_187; // @[lsu_lsc_ctl.scala 240:24] + assign io_lsu_pkt_d_valid = _T_128 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24] + assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_stack = io_dec_lsu_valid_raw_d & io_lsu_p_bits_stack; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_m_valid = _T_142; // @[lsu_lsc_ctl.scala 216:28 lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_m_bits_fast_int = _T_139_bits_fast_int; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_stack = _T_139_bits_stack; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_by = _T_139_bits_by; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_half = _T_139_bits_half; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_word = _T_139_bits_word; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_dword = _T_139_bits_dword; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_load = _T_139_bits_load; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store = _T_139_bits_store; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_unsign = _T_139_bits_unsign; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_dma = _T_139_bits_dma; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store_data_bypass_d = _T_139_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_load_ldst_bypass_d = _T_139_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_139_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_valid = _T_143; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28] + assign io_lsu_pkt_r_bits_fast_int = _T_141_bits_fast_int; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_stack = _T_141_bits_stack; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_by = _T_141_bits_by; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_half = _T_141_bits_half; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_word = _T_141_bits_word; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_dword = _T_141_bits_dword; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_load = _T_141_bits_load; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store = _T_141_bits_store; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_unsign = _T_141_bits_unsign; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_dma = _T_141_bits_dma; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store_data_bypass_d = _T_141_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_load_ldst_bypass_d = _T_141_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store_data_bypass_m = _T_141_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:28] + assign addrcheck_reset = reset; + assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_start_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 121:42] + assign addrcheck_io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 122:42] + assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 124:42] + assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[lsu_lsc_ctl.scala 125:42] + assign rvclkhdr_io_clk = clock; // @[lib.scala 419:18] + assign rvclkhdr_io_en = _T_105 | io_clk_override; // @[lib.scala 420:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_174 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_179 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + access_fault_m = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + misaligned_fault_m = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + exc_mscause_m = _RAND_2[3:0]; + _RAND_3 = {1{`RANDOM}}; + fir_dccm_access_error_m = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + fir_nondccm_access_error_m = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_110_bits_inst_type = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_110_bits_exc_type = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_110_bits_mscause = _RAND_7[3:0]; + _RAND_8 = {1{`RANDOM}}; + _T_110_bits_addr = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + _T_111 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + _T_112 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_113 = _RAND_11[1:0]; + _RAND_12 = {1{`RANDOM}}; + _T_139_bits_fast_int = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + _T_139_bits_stack = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + _T_139_bits_by = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + _T_139_bits_half = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + _T_139_bits_word = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + _T_139_bits_dword = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + _T_139_bits_load = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + _T_139_bits_store = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + _T_139_bits_unsign = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + _T_139_bits_dma = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + _T_139_bits_store_data_bypass_d = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + _T_139_bits_load_ldst_bypass_d = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + _T_139_bits_store_data_bypass_m = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + _T_141_bits_fast_int = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + _T_141_bits_stack = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + _T_141_bits_by = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + _T_141_bits_half = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + _T_141_bits_word = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + _T_141_bits_dword = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + _T_141_bits_load = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + _T_141_bits_store = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + _T_141_bits_unsign = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + _T_141_bits_dma = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + _T_141_bits_store_data_bypass_d = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + _T_141_bits_load_ldst_bypass_d = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + _T_141_bits_store_data_bypass_m = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + _T_142 = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + _T_143 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + _T_154 = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + _T_156 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + _T_158 = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + _T_160 = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + store_data_pre_m = _RAND_44[31:0]; + _RAND_45 = {1{`RANDOM}}; + _T_161 = _RAND_45[31:0]; + _RAND_46 = {1{`RANDOM}}; + _T_162 = _RAND_46[31:0]; + _RAND_47 = {1{`RANDOM}}; + end_addr_pre_m = _RAND_47[28:0]; + _RAND_48 = {1{`RANDOM}}; + _T_166 = _RAND_48[2:0]; + _RAND_49 = {1{`RANDOM}}; + end_addr_pre_r = _RAND_49[28:0]; + _RAND_50 = {1{`RANDOM}}; + _T_171 = _RAND_50[2:0]; + _RAND_51 = {1{`RANDOM}}; + _T_183 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_184 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + _T_185 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + _T_186 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + _T_187 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + addr_external_r = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + bus_read_data_r = _RAND_57[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + access_fault_m = 1'h0; + end + if (reset) begin + misaligned_fault_m = 1'h0; + end + if (reset) begin + exc_mscause_m = 4'h0; + end + if (reset) begin + fir_dccm_access_error_m = 1'h0; + end + if (reset) begin + fir_nondccm_access_error_m = 1'h0; + end + if (reset) begin + _T_110_bits_inst_type = 1'h0; + end + if (reset) begin + _T_110_bits_exc_type = 1'h0; + end + if (reset) begin + _T_110_bits_mscause = 4'h0; + end + if (reset) begin + _T_110_bits_addr = 32'h0; + end + if (reset) begin + _T_111 = 1'h0; + end + if (reset) begin + _T_112 = 1'h0; + end + if (reset) begin + _T_113 = 2'h0; + end + if (reset) begin + _T_139_bits_fast_int = 1'h0; + end + if (reset) begin + _T_139_bits_stack = 1'h0; + end + if (reset) begin + _T_139_bits_by = 1'h0; + end + if (reset) begin + _T_139_bits_half = 1'h0; + end + if (reset) begin + _T_139_bits_word = 1'h0; + end + if (reset) begin + _T_139_bits_dword = 1'h0; + end + if (reset) begin + _T_139_bits_load = 1'h0; + end + if (reset) begin + _T_139_bits_store = 1'h0; + end + if (reset) begin + _T_139_bits_unsign = 1'h0; + end + if (reset) begin + _T_139_bits_dma = 1'h0; + end + if (reset) begin + _T_139_bits_store_data_bypass_d = 1'h0; + end + if (reset) begin + _T_139_bits_load_ldst_bypass_d = 1'h0; + end + if (reset) begin + _T_139_bits_store_data_bypass_m = 1'h0; + end + if (reset) begin + _T_141_bits_fast_int = 1'h0; + end + if (reset) begin + _T_141_bits_stack = 1'h0; + end + if (reset) begin + _T_141_bits_by = 1'h0; + end + if (reset) begin + _T_141_bits_half = 1'h0; + end + if (reset) begin + _T_141_bits_word = 1'h0; + end + if (reset) begin + _T_141_bits_dword = 1'h0; + end + if (reset) begin + _T_141_bits_load = 1'h0; + end + if (reset) begin + _T_141_bits_store = 1'h0; + end + if (reset) begin + _T_141_bits_unsign = 1'h0; + end + if (reset) begin + _T_141_bits_dma = 1'h0; + end + if (reset) begin + _T_141_bits_store_data_bypass_d = 1'h0; + end + if (reset) begin + _T_141_bits_load_ldst_bypass_d = 1'h0; + end + if (reset) begin + _T_141_bits_store_data_bypass_m = 1'h0; + end + if (reset) begin + _T_142 = 1'h0; + end + if (reset) begin + _T_143 = 1'h0; + end + if (reset) begin + _T_154 = 1'h0; + end + if (reset) begin + _T_156 = 1'h0; + end + if (reset) begin + _T_158 = 1'h0; + end + if (reset) begin + _T_160 = 1'h0; + end + if (reset) begin + store_data_pre_m = 32'h0; + end + if (reset) begin + _T_161 = 32'h0; + end + if (reset) begin + _T_162 = 32'h0; + end + if (reset) begin + end_addr_pre_m = 29'h0; + end + if (reset) begin + _T_166 = 3'h0; + end + if (reset) begin + end_addr_pre_r = 29'h0; + end + if (reset) begin + _T_171 = 3'h0; + end + if (reset) begin + _T_183 = 1'h0; + end + if (reset) begin + _T_184 = 1'h0; + end + if (reset) begin + _T_185 = 1'h0; + end + if (reset) begin + _T_186 = 1'h0; + end + if (reset) begin + _T_187 = 1'h0; + end + if (reset) begin + addr_external_r = 1'h0; + end + if (reset) begin + bus_read_data_r = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + access_fault_m <= 1'h0; + end else begin + access_fault_m <= addrcheck_io_access_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + misaligned_fault_m <= 1'h0; + end else begin + misaligned_fault_m <= addrcheck_io_misaligned_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + exc_mscause_m <= 4'h0; + end else begin + exc_mscause_m <= addrcheck_io_exc_mscause_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_dccm_access_error_m <= 1'h0; + end else begin + fir_dccm_access_error_m <= addrcheck_io_fir_dccm_access_error_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_nondccm_access_error_m <= 1'h0; + end else begin + fir_nondccm_access_error_m <= addrcheck_io_fir_nondccm_access_error_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_inst_type <= 1'h0; + end else if (_T_106) begin + _T_110_bits_inst_type <= io_lsu_pkt_m_bits_store; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_exc_type <= 1'h0; + end else if (_T_106) begin + _T_110_bits_exc_type <= lsu_error_pkt_m_bits_exc_type; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_mscause <= 4'h0; + end else if (_T_106) begin + if (_T_93) begin + _T_110_bits_mscause <= 4'h1; + end else begin + _T_110_bits_mscause <= exc_mscause_m; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_addr <= 32'h0; + end else if (_T_106) begin + _T_110_bits_addr <= io_lsu_addr_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_111 <= 1'h0; + end else begin + _T_111 <= _T_86 & _T_79; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_112 <= 1'h0; + end else begin + _T_112 <= _T_82 & _T_83; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_113 <= 2'h0; + end else if (fir_nondccm_access_error_m) begin + _T_113 <= 2'h3; + end else if (fir_dccm_access_error_m) begin + _T_113 <= 2'h2; + end else if (_T_100) begin + _T_113 <= 2'h1; + end else begin + _T_113 <= 2'h0; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_fast_int <= 1'h0; + end else begin + _T_139_bits_fast_int <= io_lsu_pkt_d_bits_fast_int; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_stack <= 1'h0; + end else begin + _T_139_bits_stack <= io_lsu_pkt_d_bits_stack; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_by <= 1'h0; + end else begin + _T_139_bits_by <= io_lsu_pkt_d_bits_by; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_half <= 1'h0; + end else begin + _T_139_bits_half <= io_lsu_pkt_d_bits_half; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_word <= 1'h0; + end else begin + _T_139_bits_word <= io_lsu_pkt_d_bits_word; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_dword <= 1'h0; + end else begin + _T_139_bits_dword <= io_lsu_pkt_d_bits_dword; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_load <= 1'h0; + end else begin + _T_139_bits_load <= io_lsu_pkt_d_bits_load; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_store <= 1'h0; + end else begin + _T_139_bits_store <= io_lsu_pkt_d_bits_store; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_unsign <= 1'h0; + end else begin + _T_139_bits_unsign <= io_lsu_pkt_d_bits_unsign; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_dma <= 1'h0; + end else begin + _T_139_bits_dma <= io_lsu_pkt_d_bits_dma; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_store_data_bypass_d <= 1'h0; + end else begin + _T_139_bits_store_data_bypass_d <= io_lsu_pkt_d_bits_store_data_bypass_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_load_ldst_bypass_d <= 1'h0; + end else begin + _T_139_bits_load_ldst_bypass_d <= io_lsu_pkt_d_bits_load_ldst_bypass_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_store_data_bypass_m <= 1'h0; + end else begin + _T_139_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_fast_int <= 1'h0; + end else begin + _T_141_bits_fast_int <= io_lsu_pkt_m_bits_fast_int; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_stack <= 1'h0; + end else begin + _T_141_bits_stack <= io_lsu_pkt_m_bits_stack; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_by <= 1'h0; + end else begin + _T_141_bits_by <= io_lsu_pkt_m_bits_by; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_half <= 1'h0; + end else begin + _T_141_bits_half <= io_lsu_pkt_m_bits_half; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_word <= 1'h0; + end else begin + _T_141_bits_word <= io_lsu_pkt_m_bits_word; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_dword <= 1'h0; + end else begin + _T_141_bits_dword <= io_lsu_pkt_m_bits_dword; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_load <= 1'h0; + end else begin + _T_141_bits_load <= io_lsu_pkt_m_bits_load; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_store <= 1'h0; + end else begin + _T_141_bits_store <= io_lsu_pkt_m_bits_store; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_unsign <= 1'h0; + end else begin + _T_141_bits_unsign <= io_lsu_pkt_m_bits_unsign; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_dma <= 1'h0; + end else begin + _T_141_bits_dma <= io_lsu_pkt_m_bits_dma; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_store_data_bypass_d <= 1'h0; + end else begin + _T_141_bits_store_data_bypass_d <= io_lsu_pkt_m_bits_store_data_bypass_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_load_ldst_bypass_d <= 1'h0; + end else begin + _T_141_bits_load_ldst_bypass_d <= io_lsu_pkt_m_bits_load_ldst_bypass_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_store_data_bypass_m <= 1'h0; + end else begin + _T_141_bits_store_data_bypass_m <= io_lsu_pkt_m_bits_store_data_bypass_m; + end + end + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_142 <= 1'h0; + end else begin + _T_142 <= io_lsu_pkt_d_valid & _T_132; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_143 <= 1'h0; + end else begin + _T_143 <= io_lsu_pkt_m_valid & _T_136; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_154 <= 1'h0; + end else begin + _T_154 <= io_lsu_addr_d[2]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_156 <= 1'h0; + end else begin + _T_156 <= io_end_addr_d[2]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_158 <= 1'h0; + end else begin + _T_158 <= io_lsu_addr_m[2]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_160 <= 1'h0; + end else begin + _T_160 <= io_end_addr_m[2]; + end + end + always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin + if (reset) begin + store_data_pre_m <= 32'h0; + end else if (io_lsu_pkt_d_bits_store_data_bypass_d) begin + store_data_pre_m <= io_lsu_exu_lsu_result_m; + end else if (io_dma_lsc_ctl_dma_dccm_req) begin + store_data_pre_m <= dma_mem_wdata_shifted[31:0]; + end else begin + store_data_pre_m <= io_lsu_exu_exu_lsu_rs2_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_161 <= 32'h0; + end else begin + _T_161 <= io_lsu_addr_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_162 <= 32'h0; + end else begin + _T_162 <= io_lsu_addr_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + end_addr_pre_m <= 29'h0; + end else if (_T_175) begin + end_addr_pre_m <= io_end_addr_d[31:3]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_166 <= 3'h0; + end else begin + _T_166 <= io_end_addr_d[2:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + end_addr_pre_r <= 29'h0; + end else if (_T_180) begin + end_addr_pre_r <= io_end_addr_m[31:3]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_171 <= 3'h0; + end else begin + _T_171 <= io_end_addr_m[2:0]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_183 <= 1'h0; + end else begin + _T_183 <= io_addr_in_dccm_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_184 <= 1'h0; + end else begin + _T_184 <= io_addr_in_dccm_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_185 <= 1'h0; + end else begin + _T_185 <= io_addr_in_pic_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_186 <= 1'h0; + end else begin + _T_186 <= io_addr_in_pic_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_187 <= 1'h0; + end else begin + _T_187 <= addrcheck_io_addr_external_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + addr_external_r <= 1'h0; + end else begin + addr_external_r <= io_addr_external_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + bus_read_data_r <= 32'h0; + end else if (_T_188) begin + bus_read_data_r <= io_bus_read_data_m; + end + end +endmodule diff --git a/src/main/scala/exu/exu.scala b/src/main/scala/exu/exu.scala index 79f3afe7..3fa755db 100644 --- a/src/main/scala/exu/exu.scala +++ b/src/main/scala/exu/exu.scala @@ -22,6 +22,7 @@ class exu extends Module with lib with RequireAsyncReset{ //debug val dbg_cmd_wrdata = Input(UInt(32.W)) // Debug data to primary I0 RS1 val dec_csr_rddata_d = Input(UInt(32.W)) + val lsu_nonblock_load_data = Input(UInt(32.W)) //lsu val lsu_exu = Flipped(new lsu_exu()) //ifu_ifc @@ -86,13 +87,13 @@ class exu extends Module with lib with RequireAsyncReset{ io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_result_r, io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1).asBool -> io.lsu_exu.lsu_result_m, io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(2).asBool -> io.dec_exu.decode_exu.exu_i0_result_x, - io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(3).asBool -> io.lsu_exu.lsu_nonblock_load_data + io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(3).asBool -> io.lsu_nonblock_load_data )) val i0_rs2_bypass_data_d = Mux1H(Seq( io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_result_r, io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1).asBool -> io.lsu_exu.lsu_result_m, io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(2).asBool -> io.dec_exu.decode_exu.exu_i0_result_x, - io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(3).asBool -> io.lsu_exu.lsu_nonblock_load_data + io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(3).asBool -> io.lsu_nonblock_load_data )) val i0_rs1_d = Mux1H(Seq( diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala index 1599b4f6..ba5fab16 100644 --- a/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -176,8 +176,7 @@ class lsu_exu extends Bundle{ val exu_lsu_rs1_d = Input(UInt(32.W)) val exu_lsu_rs2_d = Input(UInt(32.W)) val lsu_result_m = Output(UInt(32.W)) - val lsu_nonblock_load_data = Output(UInt(32.W)) - + //val lsu_nonblock_load_data = Output(UInt(32.W)) } class lsu_dec extends Bundle { val tlu_busbuff = new tlu_busbuff diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala index 4963cca9..5ae6353e 100644 --- a/src/main/scala/lsu/lsu.scala +++ b/src/main/scala/lsu/lsu.scala @@ -1,358 +1,359 @@ -//package lsu -// -//import lib._ -//import chisel3._ -//import chisel3.util._ -//import include._ -//import mem._ -// -//class lsu extends Module with RequireAsyncReset with param with lib { -// val io = IO (new Bundle { -// val clk_override = Input(Bool()) -// val lsu_dma = new lsu_dma -// val lsu_pic = new lsu_pic -// val lsu_exu = new lsu_exu -// val lsu_dec = new lsu_dec -// val dccm = Flipped(new mem_lsu) -// val lsu_tlu = new lsu_tlu -// val axi = new axi_channels(LSU_BUS_TAG) -// -// val dec_tlu_flush_lower_r = Input(Bool()) -// val dec_tlu_i0_kill_writeb_r = Input(Bool()) -// val dec_tlu_force_halt = Input(Bool()) -// -// val dec_tlu_core_ecc_disable = Input(Bool()) -// -// val dec_lsu_offset_d = Input(UInt(12.W)) -// val lsu_p = Flipped(Valid(new lsu_pkt_t())) -// val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t())) -// -// val dec_lsu_valid_raw_d = Input(Bool()) -// val dec_tlu_mrac_ff = Input(UInt(32.W)) -// -// //Outputs -// val lsu_result_m = Output(UInt(32.W)) -// val lsu_result_corr_r = Output(UInt(32.W)) -// val lsu_load_stall_any = Output(Bool()) -// val lsu_store_stall_any = Output(Bool()) -// val lsu_fastint_stall_any = Output(Bool()) -// val lsu_idle_any = Output(Bool()) -// val lsu_active = Output(Bool()) -// val lsu_fir_addr = Output(UInt(31.W)) -// val lsu_fir_error = Output(UInt(2.W)) -// val lsu_single_ecc_error_incr = Output(Bool()) -// val lsu_error_pkt_r = Valid(new lsu_error_pkt_t()) -// val lsu_pmu_misaligned_m = Output(Bool()) -// val lsu_trigger_match_m = Output(UInt(4.W)) -// -// val lsu_bus_clk_en = Input(Bool()) -// -// val scan_mode = Input(Bool()) -// val active_clk = Input(Clock()) -// -// }) -// val dma_dccm_wdata = WireInit(0.U(64.W)) -// val dma_dccm_wdata_lo = WireInit(0.U(32.W)) -// val dma_dccm_wdata_hi = WireInit(0.U(32.W)) -// val dma_mem_tag_m = WireInit(0.U(3.W)) -// val lsu_raw_fwd_lo_r = WireInit(0.U(1.W)) -// val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) -// val lsu_busm_clken = WireInit(0.U(1.W)) -// val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W)) -// val lsu_addr_d = WireInit(0.U(32.W)) -// val lsu_addr_m = WireInit(0.U(32.W)) -// val lsu_addr_r = WireInit(0.U(32.W)) -// val end_addr_d = WireInit(0.U(32.W)) -// val end_addr_m = WireInit(0.U(32.W)) -// val end_addr_r = WireInit(0.U(32.W)) -// val lsu_busreq_r = WireInit(Bool(),false.B) -// -// val lsu_lsc_ctl = Module(new lsu_lsc_ctl()) -// io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m -// io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r -// val dccm_ctl = Module(new lsu_dccm_ctl()) -// val stbuf = Module(new lsu_stbuf()) -// val ecc = Module(new lsu_ecc()) -// val trigger = Module(new lsu_trigger()) -// val clkdomain = Module(new lsu_clkdomain()) -// val bus_intf = Module(new lsu_bus_intf()) -// -// val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR -// val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR -// -// // block stores in decode - for either bus or stbuf reasons -// io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff -// io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff -// io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage -// -// // Ready to accept dma trxns -// // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m -// val dma_mem_tag_d = io.lsu_dma.dma_mem_tag -// val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store -// io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff) -// val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1) -// val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d -// dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores -// dma_dccm_wdata_hi := dma_dccm_wdata(63,32) -// dma_dccm_wdata_lo := dma_dccm_wdata(31,0) -// -// val flush_m_up = io.dec_tlu_flush_lower_r -// val flush_r = io.dec_tlu_i0_kill_writeb_r -// -// // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence. -// // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error -// // Store buffer now have only non-dma dccm stores -// // stbuf_empty not needed since it has only dccm stores -// -// io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any -// io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock -// // Instantiate the store buffer -// val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r)) -// // Disable Forwarding for now -// val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) -// // Bus signals -// val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int -// // Dual signals -// val ldst_dual_d = lsu_addr_d(2) =/= end_addr_d(2) -// val ldst_dual_m = lsu_addr_m(2) =/= end_addr_m(2) -// val ldst_dual_r = lsu_addr_r(2) =/= end_addr_r(2) -// // PMU signals -// io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR)) -// io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m -// io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m -// -// //LSU_LSC_Control -// //Inputs -// lsu_lsc_ctl.io.clk_override := io.clk_override -// lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk -// lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk -// lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk -// lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk -// lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk -// lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r -// lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r -// lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r -// lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r -// lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m -// lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m -// lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m -// lsu_lsc_ctl.io.flush_m_up := flush_m_up -// lsu_lsc_ctl.io.flush_r := flush_r -// lsu_lsc_ctl.io.ldst_dual_d := ldst_dual_d -// lsu_lsc_ctl.io.ldst_dual_m := ldst_dual_m -// lsu_lsc_ctl.io.ldst_dual_r := ldst_dual_r -// lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu -// lsu_lsc_ctl.io.lsu_p <> io.lsu_p -// lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d -// lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d -// lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m -// lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m -// lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl -// lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff -// lsu_lsc_ctl.io.scan_mode := io.scan_mode -// //Outputs -// lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d -// lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m -// lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r -// end_addr_d := lsu_lsc_ctl.io.lsu_addr_d -// end_addr_m := lsu_lsc_ctl.io.lsu_addr_m -// end_addr_r := lsu_lsc_ctl.io.lsu_addr_r -// io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr -// io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r -// io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr -// io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error -// // DCCM Control -// //Inputs -// dccm_ctl.io.clk_override := io.clk_override -// dccm_ctl.io.ldst_dual_m := ldst_dual_m -// dccm_ctl.io.ldst_dual_r := ldst_dual_r -// dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk -// dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk -// dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk -// dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk -// dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk -// dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d -// dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r -// dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d -// dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m -// dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r -// dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d -// dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m -// dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r -// dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r -// dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r -// dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r -// dccm_ctl.io.lsu_addr_d := lsu_addr_d -// dccm_ctl.io.lsu_addr_m := lsu_addr_m(DCCM_BITS-1,0) -// dccm_ctl.io.lsu_addr_r := lsu_addr_r -// dccm_ctl.io.end_addr_d := end_addr_d(DCCM_BITS-1,0) -// dccm_ctl.io.end_addr_m := end_addr_m(DCCM_BITS-1,0) -// dccm_ctl.io.end_addr_r := end_addr_r(DCCM_BITS-1,0) -// dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any -// dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any -// dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any -// dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any -// dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m -// dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m -// dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m -// dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m -// dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r -// dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r -// dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r -// dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r -// dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r -// dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff -// dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff -// dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff -// dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff -// dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m -// dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m -// dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m -// dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m -// dccm_ctl.io.dma_dccm_wen := dma_dccm_wen -// dccm_ctl.io.dma_pic_wen := dma_pic_wen -// dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m -// dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo -// dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi -// dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi -// dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo -// dccm_ctl.io.scan_mode := io.scan_mode -// //Outputs -// io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl -// io.dccm <> dccm_ctl.io.dccm -// io.lsu_pic <> dccm_ctl.io.lsu_pic -// //Store Buffer -// //Inputs -// stbuf.io.ldst_dual_d := ldst_dual_d -// stbuf.io.ldst_dual_m := ldst_dual_m -// stbuf.io.ldst_dual_r := ldst_dual_r -// stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk -// stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk -// stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r -// stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r -// stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r -// stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d -// stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r -// stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r -// stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r -// stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r -// stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any -// stbuf.io.lsu_addr_d := lsu_addr_d -// stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m -// stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r -// stbuf.io.end_addr_d := end_addr_d -// stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m -// stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r -// stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m -// stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r -// stbuf.io.lsu_cmpen_m := lsu_cmpen_m -// stbuf.io.scan_mode := io.scan_mode -// -// // ECC -// //Inputs -// ecc.io.clk_override := io.clk_override -// ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk -// ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r -// ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any -// ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable -// ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r -// ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r -// ecc.io.lsu_addr_r := lsu_addr_r -// ecc.io.end_addr_r := end_addr_r -// ecc.io.lsu_addr_m := lsu_addr_m -// ecc.io.end_addr_m := end_addr_m -// ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r -// ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r -// ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m -// ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m -// ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r -// ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r -// ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m -// ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m -// ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r -// ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff -// ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m -// ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m -// ecc.io.dma_dccm_wen := dma_dccm_wen -// ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo -// ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi -// ecc.io.scan_mode := io.scan_mode -// -// //Trigger -// //Inputs -// trigger.io.trigger_pkt_any <> io.trigger_pkt_any -// trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m -// trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m -// //Outputs -// io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m -// -// //Clock Domain -// //Inputs -// clkdomain.io.active_clk := io.active_clk -// clkdomain.io.clk_override := io.clk_override -// clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt -// clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req -// clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r -// clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any -// clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any -// clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r -// clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any -// clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any -// clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any -// clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en -// clkdomain.io.lsu_p := io.lsu_p -// clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d -// clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r -// clkdomain.io.scan_mode := io.scan_mode -// -// //Bus Interface -// //Inputs -// bus_intf.io.scan_mode := io.scan_mode -// io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff -// bus_intf.io.clk_override := io.clk_override -// bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk -// bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk -// bus_intf.io.lsu_busm_clken := lsu_busm_clken -// bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken -// bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk -// bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk -// bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk -// bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk -// bus_intf.io.active_clk := io.active_clk -// bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk -// bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d -// bus_intf.io.lsu_busreq_m := lsu_busreq_m -// bus_intf.io.ldst_dual_d := ldst_dual_d -// bus_intf.io.ldst_dual_m := ldst_dual_m -// bus_intf.io.ldst_dual_r := ldst_dual_r -// bus_intf.io.lsu_addr_m := lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) -// bus_intf.io.lsu_addr_r := lsu_addr_r & Fill(32,lsu_busreq_r) -// bus_intf.io.end_addr_m := end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) -// bus_intf.io.end_addr_r := end_addr_r & Fill(32,lsu_busreq_r) -// bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r) -// bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r -// bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt -// bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r -// bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m -// bus_intf.io.flush_m_up := flush_m_up -// bus_intf.io.flush_r := flush_r -// //Outputs -// io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff -// lsu_busreq_r := bus_intf.io.lsu_busreq_r -// io.axi <> bus_intf.io.axi -// bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en -// -// withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)} -// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)} -// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)} -// -//} -//object lsu_main extends App { -// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu())) -//} \ No newline at end of file +package lsu + +import lib._ +import chisel3._ +import chisel3.util._ +import include._ +import mem._ + +class lsu extends Module with RequireAsyncReset with param with lib { + val io = IO (new Bundle { + val clk_override = Input(Bool()) + val lsu_dma = new lsu_dma + val lsu_pic = new lsu_pic + val lsu_exu = new lsu_exu + val lsu_dec = new lsu_dec + val dccm = Flipped(new mem_lsu) + val lsu_tlu = new lsu_tlu + val axi = new axi_channels(LSU_BUS_TAG) + + val dec_tlu_flush_lower_r = Input(Bool()) + val dec_tlu_i0_kill_writeb_r = Input(Bool()) + val dec_tlu_force_halt = Input(Bool()) + + val dec_tlu_core_ecc_disable = Input(Bool()) + + val dec_lsu_offset_d = Input(UInt(12.W)) + val lsu_p = Flipped(Valid(new lsu_pkt_t())) + val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t())) + + val dec_lsu_valid_raw_d = Input(Bool()) + val dec_tlu_mrac_ff = Input(UInt(32.W)) + + //Outputs + // val lsu_result_m = Output(UInt(32.W)) + val lsu_result_corr_r = Output(UInt(32.W)) + val lsu_load_stall_any = Output(Bool()) + val lsu_store_stall_any = Output(Bool()) + val lsu_fastint_stall_any = Output(Bool()) + val lsu_idle_any = Output(Bool()) + val lsu_active = Output(Bool()) + val lsu_fir_addr = Output(UInt(31.W)) + val lsu_fir_error = Output(UInt(2.W)) + val lsu_single_ecc_error_incr = Output(Bool()) + val lsu_error_pkt_r = Valid(new lsu_error_pkt_t()) + val lsu_pmu_misaligned_m = Output(Bool()) + val lsu_trigger_match_m = Output(UInt(4.W)) + + val lsu_bus_clk_en = Input(Bool()) + val scan_mode = Input(Bool()) + val active_clk = Input(Clock()) + val lsu_nonblock_load_data = Output(UInt(32.W)) + }) + val dma_dccm_wdata = WireInit(0.U(64.W)) + val dma_dccm_wdata_lo = WireInit(0.U(32.W)) + val dma_dccm_wdata_hi = WireInit(0.U(32.W)) + val dma_mem_tag_m = WireInit(0.U(3.W)) + val lsu_raw_fwd_lo_r = WireInit(0.U(1.W)) + val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) + val lsu_busm_clken = WireInit(0.U(1.W)) + val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W)) +// val lsu_addr_d = WireInit(0.U(32.W)) +// val lsu_addr_m = WireInit(0.U(32.W)) +// val lsu_addr_r = WireInit(0.U(32.W)) +// val end_addr_d = WireInit(0.U(32.W)) +// val end_addr_m = WireInit(0.U(32.W)) +// val end_addr_r = WireInit(0.U(32.W)) + val lsu_busreq_r = WireInit(Bool(),false.B) +// val ldst_dual_d = WireInit(Bool(),false.B) +// val ldst_dual_m = WireInit(Bool(),false.B) +// val ldst_dual_r = WireInit(Bool(),false.B) + + val lsu_lsc_ctl = Module(new lsu_lsc_ctl()) + // io.lsu_exu.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m + // io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data + io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r + val dccm_ctl = Module(new lsu_dccm_ctl()) + val stbuf = Module(new lsu_stbuf()) + val ecc = Module(new lsu_ecc()) + val trigger = Module(new lsu_trigger()) + val clkdomain = Module(new lsu_clkdomain()) + val bus_intf = Module(new lsu_bus_intf()) + + val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR + val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR + + // block stores in decode - for either bus or stbuf reasons + io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff + io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff + io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage + + // Ready to accept dma trxns + // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m + val dma_mem_tag_d = io.lsu_dma.dma_mem_tag + val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store + io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff) + val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1) + val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d + dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores + dma_dccm_wdata_hi := dma_dccm_wdata(63,32) + dma_dccm_wdata_lo := dma_dccm_wdata(31,0) + + val flush_m_up = io.dec_tlu_flush_lower_r + val flush_r = io.dec_tlu_i0_kill_writeb_r + + // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence. + // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error + // Store buffer now have only non-dma dccm stores + // stbuf_empty not needed since it has only dccm stores + io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any + io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock + // Instantiate the store buffer + val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r)) + // Disable Forwarding for now + val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) + // Bus signals + val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int + // Dual signals + + // PMU signals + io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR)) + io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m + io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m + + //LSU_LSC_Control + //Inputs + lsu_lsc_ctl.io.clk_override := io.clk_override + lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk + lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk + lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk + lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk + lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk + lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r + lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r + lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r + lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r + lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m + lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m + lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m + lsu_lsc_ctl.io.flush_m_up := flush_m_up + lsu_lsc_ctl.io.flush_r := flush_r + lsu_lsc_ctl.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2) + lsu_lsc_ctl.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) + lsu_lsc_ctl.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) + lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu + lsu_lsc_ctl.io.lsu_p <> io.lsu_p + lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d + lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d + lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m + lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m + lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl + lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff + lsu_lsc_ctl.io.scan_mode := io.scan_mode + //Outputs + + +// ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2) +// ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) +// ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) + + io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr + io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r + io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr + io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error + // DCCM Control + //Inputs + dccm_ctl.io.clk_override := io.clk_override + dccm_ctl.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) + dccm_ctl.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) + dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk + dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk + dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk + dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk + dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk + dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d + dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r + dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d + dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m + dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r + dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d + dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m + dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r + dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r + dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r + dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r + dccm_ctl.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d + dccm_ctl.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m(DCCM_BITS-1,0) + dccm_ctl.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r + dccm_ctl.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d(DCCM_BITS-1,0) + dccm_ctl.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m(DCCM_BITS-1,0) + dccm_ctl.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r(DCCM_BITS-1,0) + dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any + dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any + dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any + dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any + dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m + dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m + dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m + dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m + dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r + dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r + dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r + dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r + dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r + dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff + dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff + dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff + dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff + dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m + dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m + dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m + dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m + dccm_ctl.io.dma_dccm_wen := dma_dccm_wen + dccm_ctl.io.dma_pic_wen := dma_pic_wen + dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m + dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo + dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi + dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi + dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo + dccm_ctl.io.scan_mode := io.scan_mode + //Outputs + io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl + io.dccm <> dccm_ctl.io.dccm + io.lsu_pic <> dccm_ctl.io.lsu_pic + //Store Buffer + //Inputs + stbuf.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2) + stbuf.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) + stbuf.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) + stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk + stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk + stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r + stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r + stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r + stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d + stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r + stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r + stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r + stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r + stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any + stbuf.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d + stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m + stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r + stbuf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d + stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m + stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r + stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m + stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r + stbuf.io.lsu_cmpen_m := lsu_cmpen_m + stbuf.io.scan_mode := io.scan_mode + + // ECC + //Inputs + ecc.io.clk_override := io.clk_override + ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk + ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r + ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any + ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable + ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r + ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r + ecc.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r + ecc.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r + ecc.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m + ecc.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m + ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r + ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r + ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m + ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m + ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r + ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r + ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m + ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m + ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r + ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff + ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m + ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m + ecc.io.dma_dccm_wen := dma_dccm_wen + ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo + ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi + ecc.io.scan_mode := io.scan_mode + + //Trigger + //Inputs + trigger.io.trigger_pkt_any <> io.trigger_pkt_any + trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m + trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m + //Outputs + io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m + + //Clock Domain + //Inputs + clkdomain.io.active_clk := io.active_clk + clkdomain.io.clk_override := io.clk_override + clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt + clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req + clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r + clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any + clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any + clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r + clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any + clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any + clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any + clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en + clkdomain.io.lsu_p := io.lsu_p + clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d + clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r + clkdomain.io.scan_mode := io.scan_mode + + //Bus Interface + //Inputs + bus_intf.io.scan_mode := io.scan_mode + io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff + bus_intf.io.clk_override := io.clk_override + bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk + bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk + bus_intf.io.lsu_busm_clken := lsu_busm_clken + bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken + bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk + bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk + bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk + bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk + bus_intf.io.active_clk := io.active_clk + bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk + bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d + bus_intf.io.lsu_busreq_m := lsu_busreq_m + bus_intf.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2) + bus_intf.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) + bus_intf.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) + bus_intf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) + bus_intf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r & Fill(32,lsu_busreq_r) + bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) + bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r & Fill(32,lsu_busreq_r) + bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r) + bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r + bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt + bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r + bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m + bus_intf.io.flush_m_up := flush_m_up + bus_intf.io.flush_r := flush_r + //Outputs + io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff + io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data + lsu_busreq_r := bus_intf.io.lsu_busreq_r + io.axi <> bus_intf.io.axi + bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en + + withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)} + withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)} + withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)} + +} +object lsu_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new lsu())) +} \ No newline at end of file diff --git a/src/main/scala/lsu/lsu_bus_buffer.scala b/src/main/scala/lsu/lsu_bus_buffer.scala index 96d1b244..6ce06e2f 100644 --- a/src/main/scala/lsu/lsu_bus_buffer.scala +++ b/src/main/scala/lsu/lsu_bus_buffer.scala @@ -1,632 +1,633 @@ -//package lsu -//import chisel3._ -//import chisel3.util._ -//import lib._ -//import include._ -//import chisel3.experimental.{ChiselEnum, chiselName} -//import chisel3.util.ImplicitConversions.intToUInt -//import ifu._ -// -//@chiselName -//class lsu_bus_buffer extends Module with RequireAsyncReset with lib { -// val io = IO(new Bundle { -// val clk_override = Input(Bool()) -// val scan_mode = Input(Bool()) -// val tlu_busbuff = new tlu_busbuff() -// val dctl_busbuff = new dctl_busbuff() -// val dec_tlu_force_halt = Input(Bool()) -// val lsu_bus_obuf_c1_clken = Input(Bool()) -// val lsu_busm_clken = Input(Bool()) -// val lsu_c2_r_clk = Input(Clock()) -// val lsu_bus_ibuf_c1_clk = Input(Clock()) -// val lsu_bus_obuf_c1_clk = Input(Clock()) -// val lsu_bus_buf_c1_clk = Input(Clock()) -// val lsu_free_c2_clk = Input(Clock()) -// val lsu_busm_clk = Input(Clock()) -// val dec_lsu_valid_raw_d = Input(Bool()) -// val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) -// val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) -// val lsu_addr_m = Input(UInt(32.W)) -// val end_addr_m = Input(UInt(32.W)) -// val lsu_addr_r = Input(UInt(32.W)) -// val end_addr_r = Input(UInt(32.W)) -// val store_data_r = Input(UInt(32.W)) -// val no_word_merge_r = Input(Bool()) -// val no_dword_merge_r = Input(Bool()) -// val lsu_busreq_m = Input(Bool()) -// val ld_full_hit_m = Input(Bool()) -// val flush_m_up = Input(Bool()) -// val flush_r = Input(Bool()) -// val lsu_commit_r = Input(Bool()) -// val is_sideeffects_r = Input(Bool()) -// val ldst_dual_d = Input(Bool()) -// val ldst_dual_m = Input(Bool()) -// val ldst_dual_r = Input(Bool()) -// val ldst_byteen_ext_m = Input(UInt(8.W)) -// val lsu_axi = new axi_channels(LSU_BUS_TAG) -// val lsu_bus_clk_en = Input(Bool()) -// val lsu_bus_clk_en_q = Input(Bool()) -// -// val lsu_busreq_r = Output(Bool()) -// val lsu_bus_buffer_pend_any = Output(Bool()) -// val lsu_bus_buffer_full_any = Output(Bool()) -// val lsu_bus_buffer_empty_any = Output(Bool()) -// // val lsu_bus_idle_any = Output(Bool()) -// val ld_byte_hit_buf_lo = Output((UInt(4.W))) -// val ld_byte_hit_buf_hi = Output((UInt(4.W))) -// val ld_fwddata_buf_lo = Output((UInt(32.W))) -// val ld_fwddata_buf_hi = Output((UInt(32.W))) -// }) -// def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) -// def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) -// -// val DEPTH = LSU_NUM_NBLOAD -// val DEPTH_LOG2 = LSU_NUM_NBLOAD_WIDTH -// val TIMER = 8 -// val TIMER_MAX = TIMER - 1 -// val TIMER_LOG2 = if (TIMER < 2) 1 else log2Ceil(TIMER) -// -// val idle_C :: wait_C :: cmd_C :: resp_C :: done_partial_C :: done_wait_C :: done_C :: Nil = Enum(7) -// val buf_addr = Wire(Vec(DEPTH, UInt(32.W))) -// val buf_state = Wire(Vec(DEPTH, UInt(3.W))) -// val buf_write = WireInit(UInt(DEPTH.W), 0.U) -// val CmdPtr0 = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// -// -// val ldst_byteen_hi_m = io.ldst_byteen_ext_m(7, 4) -// val ldst_byteen_lo_m = io.ldst_byteen_ext_m(3, 0) -// -// val ld_addr_hitvec_lo = (0 until DEPTH).map(i => (io.lsu_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) -// val ld_addr_hitvec_hi = (0 until DEPTH).map(i => (io.end_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) -// val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W))) -// val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W), 0.U) -// val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W))) -// val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W), 0.U) -// val buf_byteen = Wire(Vec(DEPTH, UInt(4.W))) -// buf_byteen := buf_byteen.map(i=>0.U) -// val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W))) -// buf_nxtstate := buf_nxtstate.map(i=>0.U) -// val buf_wr_en = Wire(Vec(DEPTH, Bool())) -// buf_wr_en := buf_wr_en.map(i=> false.B) -// val buf_data_en = Wire(Vec(DEPTH, Bool())) -// buf_data_en := buf_data_en.map(i=> false.B) -// val buf_state_bus_en = Wire(Vec(DEPTH, Bool())) -// buf_state_bus_en := buf_state_bus_en.map(i=> false.B) -// val buf_ldfwd_in = Wire(Vec(DEPTH, Bool())) -// buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B) -// val buf_ldfwd_en = Wire(Vec(DEPTH, Bool())) -// buf_ldfwd_en := buf_ldfwd_en.map(i=> io.dec_tlu_force_halt) -// val buf_data_in = Wire(Vec(DEPTH, UInt(32.W))) -// buf_data_in := buf_data_in.map(i=> 0.U) -// val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) -// buf_ldfwdtag_in := buf_ldfwdtag_in.map(i=> 0.U) -// val buf_error_en = Wire(Vec(DEPTH, Bool())) -// buf_error_en := buf_error_en.map(i=> false.B) -// val bus_rsp_read_error = WireInit(Bool(), false.B) -// val bus_rsp_rdata = WireInit(UInt(64.W), 0.U) -// val bus_rsp_write_error = WireInit(Bool(), false.B) -// val buf_dualtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) -// buf_dualtag := buf_dualtag.map(i=> 0.U) -// val buf_ldfwd = WireInit(UInt(DEPTH.W), 0.U) -// val buf_resp_state_bus_en = Wire(Vec(DEPTH, Bool())) -// buf_resp_state_bus_en := buf_resp_state_bus_en.map(i=> false.B) -// val any_done_wait_state = WireInit(Bool(), false.B) -// val bus_rsp_write = WireInit(Bool(), false.B) -// val bus_rsp_write_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) -// val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) -// buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U) -// val buf_rst = Wire(Vec(DEPTH, Bool())) -// buf_rst := buf_rst.map(i=> false.B) -// val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U) -// val buf_byteen_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_byteen_in := buf_byteen_in.map(i=> 0.U) -// val buf_addr_in = Wire(Vec(DEPTH, UInt(32.W))) -// buf_addr_in := buf_addr_in.map(i=> 0.U) -// val buf_dual_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_samedw_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_nomerge_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_dualhi_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_dualtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) -// buf_dualtag_in := buf_dualtag_in.map(i=> 0.U) -// val buf_sideeffect_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_unsign_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_sz_in = Wire(Vec(DEPTH, UInt(2.W))) -// buf_sz_in := buf_sz_in.map(i=> 0.U) -// val buf_write_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_unsign = WireInit(UInt(DEPTH.W), 0.U) -// val buf_error = WireInit(UInt(DEPTH.W), 0.U) -// val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// -// val ibuf_data = WireInit(UInt(32.W), 0.U) -// io.ld_byte_hit_buf_lo := (0 until 4).map(i => (ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).asUInt).reverse.reduce(Cat(_, _)) -// io.ld_byte_hit_buf_hi := (0 until 4).map(i => (ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).asUInt).reverse.reduce(Cat(_, _)) -// -// val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).asUInt).reverse.reduce(Cat(_, _))) -// val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).asUInt).reverse.reduce(Cat(_, _))) -// -// val buf_age_younger = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_age_younger := buf_age_younger.map(i=> 0.U) -// ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).asUInt).reverse.reduce(Cat(_, _))) -// ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).asUInt).reverse.reduce(Cat(_, _))) -// -// val ibuf_addr = WireInit(UInt(32.W), 0.U) -// val ibuf_write = WireInit(Bool(), false.B) -// val ibuf_valid = WireInit(Bool(), false.B) -// val ld_addr_ibuf_hit_lo = (io.lsu_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m -// val ld_addr_ibuf_hit_hi = (io.end_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m -// -// val ibuf_byteen = WireInit(UInt(4.W), 0.U) -// -// ld_byte_ibuf_hit_lo := Fill(4, ld_addr_ibuf_hit_lo) & ibuf_byteen & ldst_byteen_lo_m -// ld_byte_ibuf_hit_hi := Fill(4, ld_addr_ibuf_hit_hi) & ibuf_byteen & ldst_byteen_hi_m -// -// val buf_data = Wire(Vec(DEPTH, UInt(32.W))) -// buf_data := buf_data.map(i=> 0.U) -// val fwd_data = WireInit(UInt(32.W), 0.U) -// val ld_fwddata_buf_lo_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_lo(i))).reverse.reduce(Cat(_,_)) -// val ld_fwddata_buf_hi_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_hi(i))).reverse.reduce(Cat(_,_)) -// io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | -// (ld_fwddata_buf_lo_initial & ibuf_data) -// -// io.ld_fwddata_buf_hi := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | -// (ld_fwddata_buf_hi_initial & ibuf_data) -// -// val bus_coalescing_disable = io.tlu_busbuff.dec_tlu_wb_coalescing_disable | BUILD_AHB_LITE.B -// val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.bits.by -> 1.U(4.W), -// io.lsu_pkt_r.bits.half -> 3.U(4.W), -// io.lsu_pkt_r.bits.word -> 15.U(4.W))) -// -// val ldst_byteen_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(4.W), -// (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)), -// (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)), -// (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1)))) -// -// val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r, -// (io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U), -// (io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)), -// (io.lsu_addr_r(1,0)===3.U)->Cat(ldst_byteen_r(0) , 0.U(3.W)))) -// -// val store_data_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(32.W), -// (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(24.W) , io.store_data_r(31,24)), -// (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(16.W), io.store_data_r(31,16)), -// (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(8.W), io.store_data_r(31,8)))) -// -// val store_data_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->io.store_data_r, -// (io.lsu_addr_r(1,0)===1.U)->Cat(io.store_data_r(23,0), 0.U(8.W)), -// (io.lsu_addr_r(1,0)===2.U)->Cat(io.store_data_r(15,0), 0.U(16.W)), -// (io.lsu_addr_r(1,0)===3.U)->Cat(io.store_data_r(7 ,0) , 0.U(24.W)))) -// -// -// val ldst_samedw_r = io.lsu_addr_r(3) === io.end_addr_r(3) -// val is_aligned_r = Mux1H(Seq(io.lsu_pkt_r.bits.word -> (io.lsu_addr_r(1, 0) === 0.U), -// io.lsu_pkt_r.bits.half -> !io.lsu_addr_r(0), -// io.lsu_pkt_r.bits.by -> 1.U)) -// val ibuf_byp = io.lsu_busreq_r & (io.lsu_pkt_r.bits.load | io.no_word_merge_r) & !ibuf_valid -// val ibuf_wr_en = io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp -// val ibuf_drain_vld = WireInit(Bool(), false.B) -// val ibuf_rst = (ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt -// val ibuf_force_drain = io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.bits.load | (ibuf_addr(31, 2) =/= io.lsu_addr_m(31, 2))) -// val ibuf_sideeffect = WireInit(Bool(), false.B) -// val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) -// val ibuf_merge_en = WireInit(Bool(), false.B) -// val ibuf_merge_in = WireInit(Bool(), false.B) -// ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in)) -// | ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable) -// val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// val WrPtr0_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// -// val ibuf_tag_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_tag, Mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r)) -// val ibuf_dualtag_in = WrPtr0_r -// val ibuf_sz_in = Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) -// val ibuf_addr_in = Mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) -// val ibuf_byteen_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3, 0) | ldst_byteen_lo_r(3, 0), -// Mux(io.ldst_dual_r, ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0))) -// -// -// val ibuf_data_in = (0 until 4).map(i => Mux(ibuf_merge_en & ibuf_merge_in, -// Mux(ldst_byteen_lo_r(i), store_data_lo_r((8 * i) + 7, 8 * i), ibuf_data((8 * i) + 7, 8 * i)), -// Mux(io.ldst_dual_r, store_data_hi_r((8 * i) + 7, 8 * i), store_data_lo_r((8 * i) + 7, 8 * i)))).reverse.reduce(Cat(_, _)) -// val ibuf_timer_in = Mux(ibuf_wr_en, 0.U, Mux((ibuf_timer < TIMER_MAX.U).asBool(), ibuf_timer+1.U, ibuf_timer)) -// -// ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.bits.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable -// ibuf_merge_in := !io.ldst_dual_r -// val ibuf_byteen_out = (0 until 4).map(i=>(Mux(ibuf_merge_en & !ibuf_merge_in, ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_)) -// val ibuf_data_out = (0 until 4).map(i=>Mux(ibuf_merge_en & !ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8*i)+7, 8*i), ibuf_data((8*i)+7, 8*i)), ibuf_data((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) -// -// ibuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(ibuf_wr_en, true.B, ibuf_valid) & !ibuf_rst, false.B)} -// ibuf_tag := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_tag_in, 0.U, ibuf_wr_en)} -// val ibuf_dualtag = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_dualtag_in, 0.U, ibuf_wr_en)} -// val ibuf_dual = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.ldst_dual_r, 0.U, ibuf_wr_en)} -// val ibuf_samedw = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en)} -// val ibuf_nomerge = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en)} -// ibuf_sideeffect := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en)} -// val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.unsign, 0.U, ibuf_wr_en)} -// ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.store, 0.U, ibuf_wr_en)} -// val ibuf_sz = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_sz_in, 0.U, ibuf_wr_en)} -// ibuf_addr := rvdffe(ibuf_addr_in, ibuf_wr_en, clock, io.scan_mode) -// ibuf_byteen := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_byteen_in, 0.U, ibuf_wr_en)} -// ibuf_data := rvdffe(ibuf_data_in, ibuf_wr_en, clock, io.scan_mode) -// ibuf_timer := withClock(io.lsu_free_c2_clk) {RegNext(ibuf_timer_in, 0.U)} -// val buf_numvld_wrcmd_any = WireInit(UInt(4.W), 0.U) -// val buf_numvld_cmd_any = WireInit(UInt(4.W), 0.U) -// val obuf_wr_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) -// val buf_nomerge = Wire(Vec(DEPTH, Bool())) -// buf_nomerge := buf_nomerge.map(i=> false.B) -// -// val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) -// val obuf_force_wr_en = WireInit(Bool(), false.B) -// val obuf_wr_en = WireInit(Bool(), false.B) -// val obuf_wr_wait = (buf_numvld_wrcmd_any===1.U) & (buf_numvld_cmd_any===1.U) & (obuf_wr_timer =/= TIMER_MAX.U) & -// !bus_coalescing_disable & !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_nomerge(i))) & -// !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_sideeffect(i))) & !obuf_force_wr_en -// val obuf_wr_timer_in = Mux(obuf_wr_en, 0.U(3.W), Mux(buf_numvld_cmd_any.orR & (obuf_wr_timer(CmdPtr0===i.U)->buf_addr(i)(31,2)))) -// val buf_numvld_pend_any = WireInit(UInt(4.W), 0.U) -// val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.bits.store | io.no_dword_merge_r) -// val bus_sideeffect_pend = WireInit(Bool(), false.B) -// val found_cmdptr0 = WireInit(Bool(), false.B) -// val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool())) -// buf_cmd_state_bus_en := buf_cmd_state_bus_en.map(i=> false.B) -// val buf_dual = Wire(Vec(DEPTH, Bool())) -// buf_dual := buf_dual.map(i=> false.B) -// val buf_samedw = Wire(Vec(DEPTH, Bool())) -// buf_samedw := buf_samedw.map(i=> false.B) -// val found_cmdptr1 = WireInit(Bool(), false.B) -// val bus_cmd_ready = WireInit(Bool(), false.B) -// val obuf_valid = WireInit(Bool(), false.B) -// val obuf_nosend = WireInit(Bool(), false.B) -// // val lsu_bus_cntr_overflow = WireInit(Bool(), false.B) -// val bus_addr_match_pending = WireInit(Bool(), false.B) -// -// obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) | -// ((indexing(buf_state, CmdPtr0) === cmd_C) & -// found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !(indexing(buf_sideeffect, CmdPtr0) & bus_sideeffect_pend) & -// (!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_write, CmdPtr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) | -// obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !bus_addr_match_pending & io.lsu_bus_clk_en -// -// val bus_cmd_sent = WireInit(Bool(), false.B) -// val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -// val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, indexing(buf_write, CmdPtr0)) -// val obuf_sideeffect_in = Mux(ibuf_buf_byp, io.is_sideeffects_r, indexing(buf_sideeffect, CmdPtr0)) -// val obuf_addr_in = Mux(ibuf_buf_byp, io.lsu_addr_r, indexing(buf_addr, CmdPtr0)) -// val buf_sz = Wire(Vec(DEPTH, UInt(2.W))) -// buf_sz := buf_sz.map(i=> 0.U) -// val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half), indexing(buf_sz, CmdPtr0)) -// val obuf_merge_en = WireInit(Bool(), false.B) -// val obuf_merge_in = obuf_merge_en -// val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) -// -// val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) -// val obuf_cmd_done = WireInit(Bool(), false.B) -// val bus_wcmd_sent = WireInit(Bool(), false.B) -// val obuf_cmd_done_in = !(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent) -// val obuf_data_done = WireInit(Bool(), false.B) -// val bus_wdata_sent = WireInit(Bool(), false.B) -// val obuf_data_done_in = !(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent) -// val obuf_aligned_in = Mux(ibuf_buf_byp, is_aligned_r, obuf_sz_in(1,0)===0.U | (obuf_sz_in(0) & !obuf_addr_in(0)) | (obuf_sz_in(1)&(!obuf_addr_in(1,0).orR))) -// -// val obuf_nosend_in = WireInit(Bool(), false.B) -// val obuf_rdrsp_pend = WireInit(Bool(), false.B) -// val bus_rsp_read = WireInit(Bool(), false.B) -// val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) -// val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) -// val obuf_write = WireInit(Bool(), false.B) -// val obuf_rdrsp_pend_in = ((!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | (bus_cmd_sent & !obuf_write)) & !io.dec_tlu_force_halt -// val obuf_rdrsp_pend_en = io.lsu_bus_clk_en | io.dec_tlu_force_halt -// val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U) -// val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag) -// val obuf_addr = WireInit(UInt(32.W), 0.U) -// val obuf_sideeffect = WireInit(Bool(), false.B) -// obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.tlu_busbuff.dec_tlu_external_ldfwd_disable & -// ((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) -// val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)), -// Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr0)))) -// val obuf_byteen1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_hi_r)), -// Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr1)))) -// -// val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)), -// Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_data, CmdPtr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr0)))) -// val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)), -// Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_data, CmdPtr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr1)))) -// val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) -// val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data0_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) -// -// val buf_dualhi = Wire(Vec(DEPTH, Bool())) -// buf_dualhi := buf_dualhi.map(i=> false.B) -// obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, CmdPtr1) === cmd_C) & -// !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_sideeffect, CmdPtr0) & -// (!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0))) | -// (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) -// val obuf_wr_enQ = rvdff_fpga (obuf_wr_en,io.lsu_busm_clk,io.lsu_busm_clken,clock) -// obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & !obuf_rst, false.B)} -// obuf_nosend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)} -// obuf_rdrsp_pend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_rdrsp_pend_in, false.B,obuf_rdrsp_pend_en)} -// obuf_cmd_done := rvdff_fpga (obuf_cmd_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) -// obuf_data_done := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) -// obuf_rdrsp_tag := rvdff_fpga (obuf_rdrsp_tag_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) -// -// obuf_tag0 := rvdffs_fpga (obuf_tag0_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// val obuf_tag1 = rvdffs_fpga (obuf_tag1_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// val obuf_merge = rvdffs_fpga (obuf_merge_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// obuf_write := rvdffs_fpga (obuf_write_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// obuf_sideeffect := rvdffs_fpga (obuf_sideeffect_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// val obuf_sz = rvdffs_fpga (obuf_sz_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode) -// val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode) -// obuf_wr_timer := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,obuf_wr_en,clock) -// val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// -// -// WrPtr0_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & -// !((ibuf_valid & (ibuf_tag===i.U)) | (io.lsu_busreq_r & -// ((WrPtr0_r === i.U) | (io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U)) -// -// -// val WrPtr1_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// WrPtr1_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | -// (io.lsu_busreq_m & (WrPtr0_m===i.U)) | -// (io.lsu_busreq_r & (((WrPtr0_r === i.U)) | -// (io.ldst_dual_r & (WrPtr1_r===i.U)))))) -> i.U)) -// -// val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_age := buf_age.map(i=> 0.U) -// -// val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) -// val CmdPtr1Dec = (0 until DEPTH).map(i=> (!((buf_age(i) & (~CmdPtr0Dec)).orR) & !CmdPtr0Dec(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) -// val buf_rsp_pickage = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_rsp_pickage := buf_rsp_pickage.map(i=> 0.U) -// val RspPtrDec = (0 until DEPTH).map(i=> (!(buf_rsp_pickage(i).orR) & (buf_state(i)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_)) -// found_cmdptr0 := CmdPtr0Dec.orR -// found_cmdptr1 := CmdPtr1Dec.orR -// -// def Enc8x3(in: UInt) : UInt = Cat(in(4)|in(5)|in(6)|in(7), in(2)|in(3)|in(6)|in(7), in(1)|in(3)|in(5)|in(7)) -// -// -// -// val RspPtr = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// CmdPtr0 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr0Dec)) -// -// CmdPtr1 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr1Dec)) -// RspPtr := Enc8x3(Cat(Fill(8-DEPTH, 0.U),RspPtrDec)) -// val buf_state_en = Wire(Vec(DEPTH, Bool())) -// buf_state_en := buf_state_en.map(i=> false.B) -// val buf_rspageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_rspageQ := buf_rspageQ.map(i=> 0.U) -// val buf_rspage_set = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_rspage_set := buf_rspage_set.map(i=> 0.U) -// val buf_rspage_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_rspage_in := buf_rspage_in.map(i=> 0.U) -// val buf_rspage = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_rspage := buf_rspage.map(i=> 0.U) -// -// val buf_age_in = (0 until DEPTH).map(i=>(0 until DEPTH).map(j=> ((((buf_state(i)===idle_C) & buf_state_en(i)) & -// (((buf_state(j)===wait_C) | ((buf_state(j)===cmd_C) & !buf_cmd_state_bus_en(j))) | -// (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r === i.U) & (ibuf_tag === j.U)) | -// (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_))) -// val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_ageQ := buf_ageQ.map(i=> 0.U) -// buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & !((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j)) & !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) -// buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_))) -// buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_))) -// -// buf_rspage_set := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(((buf_state(i)===idle_C) & buf_state_en(i)) & -// (!((buf_state(j)===idle_C) | (buf_state(j)===done_C)) | -// (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) | -// (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_))) -// buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_))) -// buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))& !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) -// ibuf_drainvec_vld := (0 until DEPTH).map(i=>(ibuf_drain_vld & (ibuf_tag === i.U)).asUInt).reverse.reduce(Cat(_,_)) -// buf_byteen_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), -// Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0)))) -// buf_addr_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_addr, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), io.end_addr_r, io.lsu_addr_r))) -// buf_dual_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r)).asUInt).reverse.reduce(Cat(_,_)) -// buf_samedw_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r)).asUInt).reverse.reduce(Cat(_,_)) -// buf_nomerge_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_nomerge | ibuf_force_drain, io.no_dword_merge_r)).asUInt).reverse.reduce(Cat(_,_)) -// buf_dualhi_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual ,ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U))).asUInt).reverse.reduce(Cat(_,_)) -// buf_dualtag_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), WrPtr0_r, WrPtr1_r))) -// buf_sideeffect_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)).asUInt).reverse.reduce(Cat(_,_)) -// buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.bits.unsign)).asUInt).reverse.reduce(Cat(_,_)) -// buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half))) -// buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.bits.store)).asUInt).reverse.reduce(Cat(_,_)) -// -// for(i<- 0 until DEPTH) { -// switch(buf_state(i)) { -// is(idle_C) { -// buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C) -// buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag)) -// buf_wr_en(i) := buf_state_en(i) -// buf_data_en(i) := buf_state_en(i) -// buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) -// buf_cmd_state_bus_en(i) := 0.U -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(wait_C) { -// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) -// buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt -// buf_cmd_state_bus_en(i) := 0.U -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(cmd_C) { -// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) -// buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ -// buf_state_bus_en(i) := buf_cmd_state_bus_en(i) -// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -// buf_ldfwd_in(i) := true.B -// buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt -// buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(LSU_BUS_TAG - 2, 0)).asUInt -// buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read -// buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error -// buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(resp_C) { -// buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !bus_rsp_write_error)).asBool(), idle_C, -// Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, -// Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) -// buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) | -// (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W))) | -// (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) | -// (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i)))))) -// buf_state_bus_en(i) := buf_resp_state_bus_en(i) -// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -// buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en -// buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) | -// (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | -// (bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) -// buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) -// buf_cmd_state_bus_en(i) := 0.U -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(done_partial_C) { // Other part of dual load hasn't returned -// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) -// buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | -// (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) -// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -// buf_cmd_state_bus_en(i) := 0.U -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns -// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) -// buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt -// buf_cmd_state_bus_en(i) := 0.U -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(done_C) { -// buf_nxtstate(i) := idle_C -// buf_rst(i) := true.B -// buf_state_en(i) := true.B -// buf_ldfwd_in(i) := false.B -// buf_ldfwd_en(i) := buf_state_en(i) -// buf_cmd_state_bus_en(i) := 0.U -// } -// } -// buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())} -// buf_ageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_age_in(i), 0.U)} -// buf_rspageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_rspage_in(i), 0.U)} -// buf_dualtag(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualtag_in(i), 0.U, buf_wr_en(i).asBool())} -// buf_dual(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dual_in(i), false.B, buf_wr_en(i).asBool())} -// buf_samedw(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_samedw_in(i), false.B, buf_wr_en(i).asBool())} -// buf_nomerge(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nomerge_in(i), false.B, buf_wr_en(i).asBool())} -// buf_dualhi(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualhi_in(i), false.B, buf_wr_en(i).asBool())} -// } -// -// buf_ldfwd := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwd_in(i), false.B, buf_ldfwd_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) -// buf_ldfwdtag := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwdtag_in(i), 0.U, buf_ldfwd_en(i).asBool())}) -// buf_sideeffect := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sideeffect_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) -// buf_unsign := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_unsign_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) -// buf_write := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_write_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) -// buf_sz := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sz_in(i), 0.U, buf_wr_en(i).asBool())}) -// buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode)) -// buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())}) -// buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode)) -// buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(!buf_rst(i) & Mux(buf_error_en(i), true.B, buf_error(i)), false.B)}).asUInt()).reverse.reduce(Cat(_,_)) -// val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_) -// buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) -// buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) -// buf_numvld_pend_any := (0 until DEPTH).map(i=>((buf_state(i)===wait_C) | ((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i))).asUInt).reverse.reduce(_ +& _) -// any_done_wait_state := (0 until DEPTH).map(i=>buf_state(i)===done_wait_C).reverse.reduce(_|_) -// io.lsu_bus_buffer_pend_any := buf_numvld_pend_any.orR -// io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U) -// io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid -// -// io.dctl_busbuff.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & !io.flush_m_up & !io.ld_full_hit_m -// io.dctl_busbuff.lsu_nonblock_load_tag_m := WrPtr0_m -// val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B) -// io.dctl_busbuff.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r -// io.dctl_busbuff.lsu_nonblock_load_inv_tag_r := WrPtr0_r -// val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(buf_write(i))))) -// io.dctl_busbuff.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i)))) -// io.dctl_busbuff.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U)) -// val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i))) -// val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) & buf_dualhi(i))) -> buf_data(i))) -// val lsu_nonblock_addr_offset = indexing(buf_addr, io.dctl_busbuff.lsu_nonblock_load_data_tag)(1,0) -// val lsu_nonblock_sz = indexing(buf_sz, io.dctl_busbuff.lsu_nonblock_load_data_tag) -// val lsu_nonblock_unsign = indexing(buf_unsign, io.dctl_busbuff.lsu_nonblock_load_data_tag) -// // val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.dctl_busbuff.lsu_nonblock_load_data_tag) -// val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U) -// -// io.dctl_busbuff.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.dctl_busbuff.lsu_nonblock_load_data_error -// io.dctl_busbuff.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)), -// (lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)), -// (!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)), -// (!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)), -// (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) -// bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) | (obuf_valid & obuf_sideeffect & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) -// bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> -// ( obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) -// -// bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.w.ready), io.lsu_axi.ar.ready) -// bus_wcmd_sent := io.lsu_axi.aw.valid & io.lsu_axi.aw.ready -// bus_wdata_sent := io.lsu_axi.w.valid & io.lsu_axi.w.ready -// bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) -// bus_rsp_read := io.lsu_axi.r.valid & io.lsu_axi.r.ready -// bus_rsp_write := io.lsu_axi.b.valid & io.lsu_axi.b.ready -// bus_rsp_read_tag := io.lsu_axi.r.bits.id -// bus_rsp_write_tag := io.lsu_axi.b.bits.id -// bus_rsp_write_error := bus_rsp_write & (io.lsu_axi.b.bits.resp =/= 0.U) -// bus_rsp_read_error := bus_rsp_read & (io.lsu_axi.r.bits.resp =/= 0.U) -// bus_rsp_rdata := io.lsu_axi.r.bits.data -// -// // AXI Command signals -// io.lsu_axi.aw.valid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending -// io.lsu_axi.aw.bits.id := obuf_tag0 -// io.lsu_axi.aw.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W))) -// io.lsu_axi.aw.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) -// io.lsu_axi.aw.bits.prot := 1.U(3.W) -// io.lsu_axi.aw.bits.cache := Mux(obuf_sideeffect, 0.U, 15.U) -// io.lsu_axi.aw.bits.region := obuf_addr(31,28) -// io.lsu_axi.aw.bits.len := 0.U -// io.lsu_axi.aw.bits.burst := 1.U(2.W) -// io.lsu_axi.aw.bits.qos := 0.U -// io.lsu_axi.aw.bits.lock := 0.U -// -// io.lsu_axi.w.valid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending -// io.lsu_axi.w.bits.strb := obuf_byteen & Fill(8, obuf_write) -// io.lsu_axi.w.bits.data := obuf_data -// io.lsu_axi.w.bits.last := 1.U -// -// io.lsu_axi.ar.valid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending -// io.lsu_axi.ar.bits.id := obuf_tag0 -// io.lsu_axi.ar.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W))) -// io.lsu_axi.ar.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) -// io.lsu_axi.ar.bits.prot := 1.U(3.W) -// io.lsu_axi.ar.bits.cache := Mux(obuf_sideeffect, 0.U(4.W), 15.U) -// io.lsu_axi.ar.bits.region := obuf_addr(31,28) -// io.lsu_axi.ar.bits.len := 0.U -// io.lsu_axi.ar.bits.burst := 1.U(2.W) -// io.lsu_axi.ar.bits.qos := 0.U -// io.lsu_axi.ar.bits.lock := 0.U -// io.lsu_axi.b.ready := 1.U -// io.lsu_axi.r.ready := 1.U -// io.tlu_busbuff.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i)))) -// val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U)) -// -// io.tlu_busbuff.lsu_imprecise_error_load_any := io.dctl_busbuff.lsu_nonblock_load_data_error & !io.tlu_busbuff.lsu_imprecise_error_store_any -// io.tlu_busbuff.lsu_imprecise_error_addr_any := Mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.dctl_busbuff.lsu_nonblock_load_data_tag)) -// //lsu_bus_cntr_overflow := 0.U -// -// // io.lsu_bus_idle_any := 1.U -// -// // PMU signals -// io.tlu_busbuff.lsu_pmu_bus_trxn := (io.lsu_axi.aw.valid & io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) -// io.tlu_busbuff.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r -// io.tlu_busbuff.lsu_pmu_bus_error := io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any -// -// io.tlu_busbuff.lsu_pmu_bus_busy := (io.lsu_axi.aw.valid & !io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & !io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & !io.lsu_axi.ar.ready) -// -// WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)} -// WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)} -// io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} -// lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)} -//} -//object buffer extends App { -// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer())) -//} +package lsu +import chisel3._ +import chisel3.util._ +import lib._ +import include._ +import chisel3.experimental.{ChiselEnum, chiselName} +import chisel3.util.ImplicitConversions.intToUInt +import ifu._ + +@chiselName +class lsu_bus_buffer extends Module with RequireAsyncReset with lib { + val io = IO(new Bundle { + val clk_override = Input(Bool()) + val scan_mode = Input(Bool()) + val tlu_busbuff = new tlu_busbuff() + val dctl_busbuff = new dctl_busbuff() + val dec_tlu_force_halt = Input(Bool()) + val lsu_bus_obuf_c1_clken = Input(Bool()) + val lsu_busm_clken = Input(Bool()) + val lsu_c2_r_clk = Input(Clock()) + val lsu_bus_ibuf_c1_clk = Input(Clock()) + val lsu_bus_obuf_c1_clk = Input(Clock()) + val lsu_bus_buf_c1_clk = Input(Clock()) + val lsu_free_c2_clk = Input(Clock()) + val lsu_busm_clk = Input(Clock()) + val dec_lsu_valid_raw_d = Input(Bool()) + val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) + val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) + val lsu_addr_m = Input(UInt(32.W)) + val end_addr_m = Input(UInt(32.W)) + val lsu_addr_r = Input(UInt(32.W)) + val end_addr_r = Input(UInt(32.W)) + val store_data_r = Input(UInt(32.W)) + val no_word_merge_r = Input(Bool()) + val no_dword_merge_r = Input(Bool()) + val lsu_busreq_m = Input(Bool()) + val ld_full_hit_m = Input(Bool()) + val flush_m_up = Input(Bool()) + val flush_r = Input(Bool()) + val lsu_commit_r = Input(Bool()) + val is_sideeffects_r = Input(Bool()) + val ldst_dual_d = Input(Bool()) + val ldst_dual_m = Input(Bool()) + val ldst_dual_r = Input(Bool()) + val ldst_byteen_ext_m = Input(UInt(8.W)) + val lsu_axi = new axi_channels(LSU_BUS_TAG) + val lsu_bus_clk_en = Input(Bool()) + val lsu_bus_clk_en_q = Input(Bool()) + + val lsu_busreq_r = Output(Bool()) + val lsu_bus_buffer_pend_any = Output(Bool()) + val lsu_bus_buffer_full_any = Output(Bool()) + val lsu_bus_buffer_empty_any = Output(Bool()) + // val lsu_bus_idle_any = Output(Bool()) + val ld_byte_hit_buf_lo = Output((UInt(4.W))) + val ld_byte_hit_buf_hi = Output((UInt(4.W))) + val ld_fwddata_buf_lo = Output((UInt(32.W))) + val ld_fwddata_buf_hi = Output((UInt(32.W))) + val lsu_nonblock_load_data = Output((UInt(32.W))) + }) + def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) + def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) + + val DEPTH = LSU_NUM_NBLOAD + val DEPTH_LOG2 = LSU_NUM_NBLOAD_WIDTH + val TIMER = 8 + val TIMER_MAX = TIMER - 1 + val TIMER_LOG2 = if (TIMER < 2) 1 else log2Ceil(TIMER) + + val idle_C :: wait_C :: cmd_C :: resp_C :: done_partial_C :: done_wait_C :: done_C :: Nil = Enum(7) + val buf_addr = Wire(Vec(DEPTH, UInt(32.W))) + val buf_state = Wire(Vec(DEPTH, UInt(3.W))) + val buf_write = WireInit(UInt(DEPTH.W), 0.U) + val CmdPtr0 = WireInit(UInt(DEPTH_LOG2.W), 0.U) + + + val ldst_byteen_hi_m = io.ldst_byteen_ext_m(7, 4) + val ldst_byteen_lo_m = io.ldst_byteen_ext_m(3, 0) + + val ld_addr_hitvec_lo = (0 until DEPTH).map(i => (io.lsu_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) + val ld_addr_hitvec_hi = (0 until DEPTH).map(i => (io.end_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) + val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W))) + val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W), 0.U) + val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W))) + val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W), 0.U) + val buf_byteen = Wire(Vec(DEPTH, UInt(4.W))) + buf_byteen := buf_byteen.map(i=>0.U) + val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W))) + buf_nxtstate := buf_nxtstate.map(i=>0.U) + val buf_wr_en = Wire(Vec(DEPTH, Bool())) + buf_wr_en := buf_wr_en.map(i=> false.B) + val buf_data_en = Wire(Vec(DEPTH, Bool())) + buf_data_en := buf_data_en.map(i=> false.B) + val buf_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_state_bus_en := buf_state_bus_en.map(i=> false.B) + val buf_ldfwd_in = Wire(Vec(DEPTH, Bool())) + buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B) + val buf_ldfwd_en = Wire(Vec(DEPTH, Bool())) + buf_ldfwd_en := buf_ldfwd_en.map(i=> io.dec_tlu_force_halt) + val buf_data_in = Wire(Vec(DEPTH, UInt(32.W))) + buf_data_in := buf_data_in.map(i=> 0.U) + val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_ldfwdtag_in := buf_ldfwdtag_in.map(i=> 0.U) + val buf_error_en = Wire(Vec(DEPTH, Bool())) + buf_error_en := buf_error_en.map(i=> false.B) + val bus_rsp_read_error = WireInit(Bool(), false.B) + val bus_rsp_rdata = WireInit(UInt(64.W), 0.U) + val bus_rsp_write_error = WireInit(Bool(), false.B) + val buf_dualtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_dualtag := buf_dualtag.map(i=> 0.U) + val buf_ldfwd = WireInit(UInt(DEPTH.W), 0.U) + val buf_resp_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_resp_state_bus_en := buf_resp_state_bus_en.map(i=> false.B) + val any_done_wait_state = WireInit(Bool(), false.B) + val bus_rsp_write = WireInit(Bool(), false.B) + val bus_rsp_write_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U) + val buf_rst = Wire(Vec(DEPTH, Bool())) + buf_rst := buf_rst.map(i=> false.B) + val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U) + val buf_byteen_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_byteen_in := buf_byteen_in.map(i=> 0.U) + val buf_addr_in = Wire(Vec(DEPTH, UInt(32.W))) + buf_addr_in := buf_addr_in.map(i=> 0.U) + val buf_dual_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_samedw_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_nomerge_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_dualhi_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_dualtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_dualtag_in := buf_dualtag_in.map(i=> 0.U) + val buf_sideeffect_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_unsign_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_sz_in = Wire(Vec(DEPTH, UInt(2.W))) + buf_sz_in := buf_sz_in.map(i=> 0.U) + val buf_write_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_unsign = WireInit(UInt(DEPTH.W), 0.U) + val buf_error = WireInit(UInt(DEPTH.W), 0.U) + val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) + + val ibuf_data = WireInit(UInt(32.W), 0.U) + io.ld_byte_hit_buf_lo := (0 until 4).map(i => (ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).asUInt).reverse.reduce(Cat(_, _)) + io.ld_byte_hit_buf_hi := (0 until 4).map(i => (ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).asUInt).reverse.reduce(Cat(_, _)) + + val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).asUInt).reverse.reduce(Cat(_, _))) + val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).asUInt).reverse.reduce(Cat(_, _))) + + val buf_age_younger = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_age_younger := buf_age_younger.map(i=> 0.U) + ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).asUInt).reverse.reduce(Cat(_, _))) + ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).asUInt).reverse.reduce(Cat(_, _))) + + val ibuf_addr = WireInit(UInt(32.W), 0.U) + val ibuf_write = WireInit(Bool(), false.B) + val ibuf_valid = WireInit(Bool(), false.B) + val ld_addr_ibuf_hit_lo = (io.lsu_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m + val ld_addr_ibuf_hit_hi = (io.end_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m + + val ibuf_byteen = WireInit(UInt(4.W), 0.U) + + ld_byte_ibuf_hit_lo := Fill(4, ld_addr_ibuf_hit_lo) & ibuf_byteen & ldst_byteen_lo_m + ld_byte_ibuf_hit_hi := Fill(4, ld_addr_ibuf_hit_hi) & ibuf_byteen & ldst_byteen_hi_m + + val buf_data = Wire(Vec(DEPTH, UInt(32.W))) + buf_data := buf_data.map(i=> 0.U) + val fwd_data = WireInit(UInt(32.W), 0.U) + val ld_fwddata_buf_lo_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_lo(i))).reverse.reduce(Cat(_,_)) + val ld_fwddata_buf_hi_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_hi(i))).reverse.reduce(Cat(_,_)) + io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | + (ld_fwddata_buf_lo_initial & ibuf_data) + + io.ld_fwddata_buf_hi := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | + (ld_fwddata_buf_hi_initial & ibuf_data) + + val bus_coalescing_disable = io.tlu_busbuff.dec_tlu_wb_coalescing_disable | BUILD_AHB_LITE.B + val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.bits.by -> 1.U(4.W), + io.lsu_pkt_r.bits.half -> 3.U(4.W), + io.lsu_pkt_r.bits.word -> 15.U(4.W))) + + val ldst_byteen_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(4.W), + (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)), + (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)), + (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1)))) + + val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r, + (io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U), + (io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)), + (io.lsu_addr_r(1,0)===3.U)->Cat(ldst_byteen_r(0) , 0.U(3.W)))) + + val store_data_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(32.W), + (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(24.W) , io.store_data_r(31,24)), + (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(16.W), io.store_data_r(31,16)), + (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(8.W), io.store_data_r(31,8)))) + + val store_data_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->io.store_data_r, + (io.lsu_addr_r(1,0)===1.U)->Cat(io.store_data_r(23,0), 0.U(8.W)), + (io.lsu_addr_r(1,0)===2.U)->Cat(io.store_data_r(15,0), 0.U(16.W)), + (io.lsu_addr_r(1,0)===3.U)->Cat(io.store_data_r(7 ,0) , 0.U(24.W)))) + + + val ldst_samedw_r = io.lsu_addr_r(3) === io.end_addr_r(3) + val is_aligned_r = Mux1H(Seq(io.lsu_pkt_r.bits.word -> (io.lsu_addr_r(1, 0) === 0.U), + io.lsu_pkt_r.bits.half -> !io.lsu_addr_r(0), + io.lsu_pkt_r.bits.by -> 1.U)) + val ibuf_byp = io.lsu_busreq_r & (io.lsu_pkt_r.bits.load | io.no_word_merge_r) & !ibuf_valid + val ibuf_wr_en = io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp + val ibuf_drain_vld = WireInit(Bool(), false.B) + val ibuf_rst = (ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt + val ibuf_force_drain = io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.bits.load | (ibuf_addr(31, 2) =/= io.lsu_addr_m(31, 2))) + val ibuf_sideeffect = WireInit(Bool(), false.B) + val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) + val ibuf_merge_en = WireInit(Bool(), false.B) + val ibuf_merge_in = WireInit(Bool(), false.B) + ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in)) + | ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable) + val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U) + val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) + val WrPtr0_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) + + val ibuf_tag_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_tag, Mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r)) + val ibuf_dualtag_in = WrPtr0_r + val ibuf_sz_in = Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) + val ibuf_addr_in = Mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) + val ibuf_byteen_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3, 0) | ldst_byteen_lo_r(3, 0), + Mux(io.ldst_dual_r, ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0))) + + + val ibuf_data_in = (0 until 4).map(i => Mux(ibuf_merge_en & ibuf_merge_in, + Mux(ldst_byteen_lo_r(i), store_data_lo_r((8 * i) + 7, 8 * i), ibuf_data((8 * i) + 7, 8 * i)), + Mux(io.ldst_dual_r, store_data_hi_r((8 * i) + 7, 8 * i), store_data_lo_r((8 * i) + 7, 8 * i)))).reverse.reduce(Cat(_, _)) + val ibuf_timer_in = Mux(ibuf_wr_en, 0.U, Mux((ibuf_timer < TIMER_MAX.U).asBool(), ibuf_timer+1.U, ibuf_timer)) + + ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.bits.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable + ibuf_merge_in := !io.ldst_dual_r + val ibuf_byteen_out = (0 until 4).map(i=>(Mux(ibuf_merge_en & !ibuf_merge_in, ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_)) + val ibuf_data_out = (0 until 4).map(i=>Mux(ibuf_merge_en & !ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8*i)+7, 8*i), ibuf_data((8*i)+7, 8*i)), ibuf_data((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) + + ibuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(ibuf_wr_en, true.B, ibuf_valid) & !ibuf_rst, false.B)} + ibuf_tag := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_tag_in, 0.U, ibuf_wr_en)} + val ibuf_dualtag = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_dualtag_in, 0.U, ibuf_wr_en)} + val ibuf_dual = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.ldst_dual_r, 0.U, ibuf_wr_en)} + val ibuf_samedw = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en)} + val ibuf_nomerge = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en)} + ibuf_sideeffect := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en)} + val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.unsign, 0.U, ibuf_wr_en)} + ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.store, 0.U, ibuf_wr_en)} + val ibuf_sz = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_sz_in, 0.U, ibuf_wr_en)} + ibuf_addr := rvdffe(ibuf_addr_in, ibuf_wr_en, clock, io.scan_mode) + ibuf_byteen := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_byteen_in, 0.U, ibuf_wr_en)} + ibuf_data := rvdffe(ibuf_data_in, ibuf_wr_en, clock, io.scan_mode) + ibuf_timer := withClock(io.lsu_free_c2_clk) {RegNext(ibuf_timer_in, 0.U)} + val buf_numvld_wrcmd_any = WireInit(UInt(4.W), 0.U) + val buf_numvld_cmd_any = WireInit(UInt(4.W), 0.U) + val obuf_wr_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) + val buf_nomerge = Wire(Vec(DEPTH, Bool())) + buf_nomerge := buf_nomerge.map(i=> false.B) + + val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) + val obuf_force_wr_en = WireInit(Bool(), false.B) + val obuf_wr_en = WireInit(Bool(), false.B) + val obuf_wr_wait = (buf_numvld_wrcmd_any===1.U) & (buf_numvld_cmd_any===1.U) & (obuf_wr_timer =/= TIMER_MAX.U) & + !bus_coalescing_disable & !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_nomerge(i))) & + !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_sideeffect(i))) & !obuf_force_wr_en + val obuf_wr_timer_in = Mux(obuf_wr_en, 0.U(3.W), Mux(buf_numvld_cmd_any.orR & (obuf_wr_timer(CmdPtr0===i.U)->buf_addr(i)(31,2)))) + val buf_numvld_pend_any = WireInit(UInt(4.W), 0.U) + val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.bits.store | io.no_dword_merge_r) + val bus_sideeffect_pend = WireInit(Bool(), false.B) + val found_cmdptr0 = WireInit(Bool(), false.B) + val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_cmd_state_bus_en := buf_cmd_state_bus_en.map(i=> false.B) + val buf_dual = Wire(Vec(DEPTH, Bool())) + buf_dual := buf_dual.map(i=> false.B) + val buf_samedw = Wire(Vec(DEPTH, Bool())) + buf_samedw := buf_samedw.map(i=> false.B) + val found_cmdptr1 = WireInit(Bool(), false.B) + val bus_cmd_ready = WireInit(Bool(), false.B) + val obuf_valid = WireInit(Bool(), false.B) + val obuf_nosend = WireInit(Bool(), false.B) + // val lsu_bus_cntr_overflow = WireInit(Bool(), false.B) + val bus_addr_match_pending = WireInit(Bool(), false.B) + + obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) | + ((indexing(buf_state, CmdPtr0) === cmd_C) & + found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !(indexing(buf_sideeffect, CmdPtr0) & bus_sideeffect_pend) & + (!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_write, CmdPtr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) | + obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !bus_addr_match_pending & io.lsu_bus_clk_en + + val bus_cmd_sent = WireInit(Bool(), false.B) + val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, indexing(buf_write, CmdPtr0)) + val obuf_sideeffect_in = Mux(ibuf_buf_byp, io.is_sideeffects_r, indexing(buf_sideeffect, CmdPtr0)) + val obuf_addr_in = Mux(ibuf_buf_byp, io.lsu_addr_r, indexing(buf_addr, CmdPtr0)) + val buf_sz = Wire(Vec(DEPTH, UInt(2.W))) + buf_sz := buf_sz.map(i=> 0.U) + val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half), indexing(buf_sz, CmdPtr0)) + val obuf_merge_en = WireInit(Bool(), false.B) + val obuf_merge_in = obuf_merge_en + val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) + + val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) + val obuf_cmd_done = WireInit(Bool(), false.B) + val bus_wcmd_sent = WireInit(Bool(), false.B) + val obuf_cmd_done_in = !(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent) + val obuf_data_done = WireInit(Bool(), false.B) + val bus_wdata_sent = WireInit(Bool(), false.B) + val obuf_data_done_in = !(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent) + val obuf_aligned_in = Mux(ibuf_buf_byp, is_aligned_r, obuf_sz_in(1,0)===0.U | (obuf_sz_in(0) & !obuf_addr_in(0)) | (obuf_sz_in(1)&(!obuf_addr_in(1,0).orR))) + + val obuf_nosend_in = WireInit(Bool(), false.B) + val obuf_rdrsp_pend = WireInit(Bool(), false.B) + val bus_rsp_read = WireInit(Bool(), false.B) + val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_write = WireInit(Bool(), false.B) + val obuf_rdrsp_pend_in = ((!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | (bus_cmd_sent & !obuf_write)) & !io.dec_tlu_force_halt + val obuf_rdrsp_pend_en = io.lsu_bus_clk_en | io.dec_tlu_force_halt + val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag) + val obuf_addr = WireInit(UInt(32.W), 0.U) + val obuf_sideeffect = WireInit(Bool(), false.B) + obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.tlu_busbuff.dec_tlu_external_ldfwd_disable & + ((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) + val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)), + Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr0)))) + val obuf_byteen1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_hi_r)), + Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr1)))) + + val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)), + Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_data, CmdPtr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr0)))) + val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)), + Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_data, CmdPtr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr1)))) + val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) + val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data0_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) + + val buf_dualhi = Wire(Vec(DEPTH, Bool())) + buf_dualhi := buf_dualhi.map(i=> false.B) + obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, CmdPtr1) === cmd_C) & + !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_sideeffect, CmdPtr0) & + (!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0))) | + (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) + val obuf_wr_enQ = rvdff_fpga (obuf_wr_en,io.lsu_busm_clk,io.lsu_busm_clken,clock) + obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & !obuf_rst, false.B)} + obuf_nosend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)} + obuf_rdrsp_pend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_rdrsp_pend_in, false.B,obuf_rdrsp_pend_en)} + obuf_cmd_done := rvdff_fpga (obuf_cmd_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) + obuf_data_done := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) + obuf_rdrsp_tag := rvdff_fpga (obuf_rdrsp_tag_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) + + obuf_tag0 := rvdffs_fpga (obuf_tag0_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + val obuf_tag1 = rvdffs_fpga (obuf_tag1_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + val obuf_merge = rvdffs_fpga (obuf_merge_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + obuf_write := rvdffs_fpga (obuf_write_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + obuf_sideeffect := rvdffs_fpga (obuf_sideeffect_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + val obuf_sz = rvdffs_fpga (obuf_sz_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode) + val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode) + obuf_wr_timer := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,obuf_wr_en,clock) + val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) + + + WrPtr0_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & + !((ibuf_valid & (ibuf_tag===i.U)) | (io.lsu_busreq_r & + ((WrPtr0_r === i.U) | (io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U)) + + + val WrPtr1_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) + WrPtr1_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | + (io.lsu_busreq_m & (WrPtr0_m===i.U)) | + (io.lsu_busreq_r & (((WrPtr0_r === i.U)) | + (io.ldst_dual_r & (WrPtr1_r===i.U)))))) -> i.U)) + + val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_age := buf_age.map(i=> 0.U) + + val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) + val CmdPtr1Dec = (0 until DEPTH).map(i=> (!((buf_age(i) & (~CmdPtr0Dec)).orR) & !CmdPtr0Dec(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) + val buf_rsp_pickage = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rsp_pickage := buf_rsp_pickage.map(i=> 0.U) + val RspPtrDec = (0 until DEPTH).map(i=> (!(buf_rsp_pickage(i).orR) & (buf_state(i)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_)) + found_cmdptr0 := CmdPtr0Dec.orR + found_cmdptr1 := CmdPtr1Dec.orR + + def Enc8x3(in: UInt) : UInt = Cat(in(4)|in(5)|in(6)|in(7), in(2)|in(3)|in(6)|in(7), in(1)|in(3)|in(5)|in(7)) + + + + val RspPtr = WireInit(UInt(DEPTH_LOG2.W), 0.U) + CmdPtr0 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr0Dec)) + + CmdPtr1 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr1Dec)) + RspPtr := Enc8x3(Cat(Fill(8-DEPTH, 0.U),RspPtrDec)) + val buf_state_en = Wire(Vec(DEPTH, Bool())) + buf_state_en := buf_state_en.map(i=> false.B) + val buf_rspageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspageQ := buf_rspageQ.map(i=> 0.U) + val buf_rspage_set = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage_set := buf_rspage_set.map(i=> 0.U) + val buf_rspage_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage_in := buf_rspage_in.map(i=> 0.U) + val buf_rspage = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage := buf_rspage.map(i=> 0.U) + + val buf_age_in = (0 until DEPTH).map(i=>(0 until DEPTH).map(j=> ((((buf_state(i)===idle_C) & buf_state_en(i)) & + (((buf_state(j)===wait_C) | ((buf_state(j)===cmd_C) & !buf_cmd_state_bus_en(j))) | + (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r === i.U) & (ibuf_tag === j.U)) | + (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_))) + val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_ageQ := buf_ageQ.map(i=> 0.U) + buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & !((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j)) & !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) + buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_))) + buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_))) + + buf_rspage_set := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(((buf_state(i)===idle_C) & buf_state_en(i)) & + (!((buf_state(j)===idle_C) | (buf_state(j)===done_C)) | + (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) | + (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_))) + buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_))) + buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))& !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) + ibuf_drainvec_vld := (0 until DEPTH).map(i=>(ibuf_drain_vld & (ibuf_tag === i.U)).asUInt).reverse.reduce(Cat(_,_)) + buf_byteen_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), + Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0)))) + buf_addr_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_addr, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), io.end_addr_r, io.lsu_addr_r))) + buf_dual_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_samedw_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_nomerge_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_nomerge | ibuf_force_drain, io.no_dword_merge_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_dualhi_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual ,ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U))).asUInt).reverse.reduce(Cat(_,_)) + buf_dualtag_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), WrPtr0_r, WrPtr1_r))) + buf_sideeffect_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.bits.unsign)).asUInt).reverse.reduce(Cat(_,_)) + buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half))) + buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.bits.store)).asUInt).reverse.reduce(Cat(_,_)) + + for(i<- 0 until DEPTH) { + switch(buf_state(i)) { + is(idle_C) { + buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C) + buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag)) + buf_wr_en(i) := buf_state_en(i) + buf_data_en(i) := buf_state_en(i) + buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) + buf_cmd_state_bus_en(i) := 0.U + buf_rst(i) := io.dec_tlu_force_halt + } + is(wait_C) { + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) + buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt + buf_cmd_state_bus_en(i) := 0.U + buf_rst(i) := io.dec_tlu_force_halt + } + is(cmd_C) { + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) + buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ + buf_state_bus_en(i) := buf_cmd_state_bus_en(i) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + buf_ldfwd_in(i) := true.B + buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt + buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(LSU_BUS_TAG - 2, 0)).asUInt + buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read + buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error + buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) + buf_rst(i) := io.dec_tlu_force_halt + } + is(resp_C) { + buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !bus_rsp_write_error)).asBool(), idle_C, + Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, + Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) + buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) | + (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W))) | + (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) | + (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i)))))) + buf_state_bus_en(i) := buf_resp_state_bus_en(i) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en + buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) | + (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | + (bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) + buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) + buf_cmd_state_bus_en(i) := 0.U + buf_rst(i) := io.dec_tlu_force_halt + } + is(done_partial_C) { // Other part of dual load hasn't returned + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) + buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | + (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + buf_cmd_state_bus_en(i) := 0.U + buf_rst(i) := io.dec_tlu_force_halt + } + is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) + buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt + buf_cmd_state_bus_en(i) := 0.U + buf_rst(i) := io.dec_tlu_force_halt + } + is(done_C) { + buf_nxtstate(i) := idle_C + buf_rst(i) := true.B + buf_state_en(i) := true.B + buf_ldfwd_in(i) := false.B + buf_ldfwd_en(i) := buf_state_en(i) + buf_cmd_state_bus_en(i) := 0.U + } + } + buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())} + buf_ageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_age_in(i), 0.U)} + buf_rspageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_rspage_in(i), 0.U)} + buf_dualtag(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualtag_in(i), 0.U, buf_wr_en(i).asBool())} + buf_dual(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dual_in(i), false.B, buf_wr_en(i).asBool())} + buf_samedw(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_samedw_in(i), false.B, buf_wr_en(i).asBool())} + buf_nomerge(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nomerge_in(i), false.B, buf_wr_en(i).asBool())} + buf_dualhi(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualhi_in(i), false.B, buf_wr_en(i).asBool())} + } + + buf_ldfwd := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwd_in(i), false.B, buf_ldfwd_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_ldfwdtag := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwdtag_in(i), 0.U, buf_ldfwd_en(i).asBool())}) + buf_sideeffect := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sideeffect_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_unsign := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_unsign_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_write := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_write_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_sz := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sz_in(i), 0.U, buf_wr_en(i).asBool())}) + buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode)) + buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())}) + buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode)) + buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(!buf_rst(i) & Mux(buf_error_en(i), true.B, buf_error(i)), false.B)}).asUInt()).reverse.reduce(Cat(_,_)) + val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_) + buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) + buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) + buf_numvld_pend_any := (0 until DEPTH).map(i=>((buf_state(i)===wait_C) | ((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i))).asUInt).reverse.reduce(_ +& _) + any_done_wait_state := (0 until DEPTH).map(i=>buf_state(i)===done_wait_C).reverse.reduce(_|_) + io.lsu_bus_buffer_pend_any := buf_numvld_pend_any.orR + io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U) + io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid + + io.dctl_busbuff.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & !io.flush_m_up & !io.ld_full_hit_m + io.dctl_busbuff.lsu_nonblock_load_tag_m := WrPtr0_m + val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B) + io.dctl_busbuff.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r := WrPtr0_r + val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(buf_write(i))))) + io.dctl_busbuff.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i)))) + io.dctl_busbuff.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U)) + val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i))) + val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) & buf_dualhi(i))) -> buf_data(i))) + val lsu_nonblock_addr_offset = indexing(buf_addr, io.dctl_busbuff.lsu_nonblock_load_data_tag)(1,0) + val lsu_nonblock_sz = indexing(buf_sz, io.dctl_busbuff.lsu_nonblock_load_data_tag) + val lsu_nonblock_unsign = indexing(buf_unsign, io.dctl_busbuff.lsu_nonblock_load_data_tag) + // val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.dctl_busbuff.lsu_nonblock_load_data_tag) + val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U) + + io.dctl_busbuff.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.dctl_busbuff.lsu_nonblock_load_data_error + io.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)), + (lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)), + (!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)), + (!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)), + (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) + bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) | (obuf_valid & obuf_sideeffect & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) + bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> + ( obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) + + bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.w.ready), io.lsu_axi.ar.ready) + bus_wcmd_sent := io.lsu_axi.aw.valid & io.lsu_axi.aw.ready + bus_wdata_sent := io.lsu_axi.w.valid & io.lsu_axi.w.ready + bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) + bus_rsp_read := io.lsu_axi.r.valid & io.lsu_axi.r.ready + bus_rsp_write := io.lsu_axi.b.valid & io.lsu_axi.b.ready + bus_rsp_read_tag := io.lsu_axi.r.bits.id + bus_rsp_write_tag := io.lsu_axi.b.bits.id + bus_rsp_write_error := bus_rsp_write & (io.lsu_axi.b.bits.resp =/= 0.U) + bus_rsp_read_error := bus_rsp_read & (io.lsu_axi.r.bits.resp =/= 0.U) + bus_rsp_rdata := io.lsu_axi.r.bits.data + + // AXI Command signals + io.lsu_axi.aw.valid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending + io.lsu_axi.aw.bits.id := obuf_tag0 + io.lsu_axi.aw.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W))) + io.lsu_axi.aw.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) + io.lsu_axi.aw.bits.prot := 1.U(3.W) + io.lsu_axi.aw.bits.cache := Mux(obuf_sideeffect, 0.U, 15.U) + io.lsu_axi.aw.bits.region := obuf_addr(31,28) + io.lsu_axi.aw.bits.len := 0.U + io.lsu_axi.aw.bits.burst := 1.U(2.W) + io.lsu_axi.aw.bits.qos := 0.U + io.lsu_axi.aw.bits.lock := 0.U + + io.lsu_axi.w.valid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending + io.lsu_axi.w.bits.strb := obuf_byteen & Fill(8, obuf_write) + io.lsu_axi.w.bits.data := obuf_data + io.lsu_axi.w.bits.last := 1.U + + io.lsu_axi.ar.valid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending + io.lsu_axi.ar.bits.id := obuf_tag0 + io.lsu_axi.ar.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W))) + io.lsu_axi.ar.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) + io.lsu_axi.ar.bits.prot := 1.U(3.W) + io.lsu_axi.ar.bits.cache := Mux(obuf_sideeffect, 0.U(4.W), 15.U) + io.lsu_axi.ar.bits.region := obuf_addr(31,28) + io.lsu_axi.ar.bits.len := 0.U + io.lsu_axi.ar.bits.burst := 1.U(2.W) + io.lsu_axi.ar.bits.qos := 0.U + io.lsu_axi.ar.bits.lock := 0.U + io.lsu_axi.b.ready := 1.U + io.lsu_axi.r.ready := 1.U + io.tlu_busbuff.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i)))) + val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U)) + + io.tlu_busbuff.lsu_imprecise_error_load_any := io.dctl_busbuff.lsu_nonblock_load_data_error & !io.tlu_busbuff.lsu_imprecise_error_store_any + io.tlu_busbuff.lsu_imprecise_error_addr_any := Mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.dctl_busbuff.lsu_nonblock_load_data_tag)) + //lsu_bus_cntr_overflow := 0.U + + // io.lsu_bus_idle_any := 1.U + + // PMU signals + io.tlu_busbuff.lsu_pmu_bus_trxn := (io.lsu_axi.aw.valid & io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) + io.tlu_busbuff.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r + io.tlu_busbuff.lsu_pmu_bus_error := io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any + + io.tlu_busbuff.lsu_pmu_bus_busy := (io.lsu_axi.aw.valid & !io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & !io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & !io.lsu_axi.ar.ready) + + WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)} + WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)} + io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} + lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)} +} +object buffer extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer())) +} diff --git a/src/main/scala/lsu/lsu_bus_intf.scala b/src/main/scala/lsu/lsu_bus_intf.scala index 4a246ab5..e800d75d 100644 --- a/src/main/scala/lsu/lsu_bus_intf.scala +++ b/src/main/scala/lsu/lsu_bus_intf.scala @@ -1,205 +1,205 @@ -//package lsu -//import chisel3._ -//import chisel3.util._ -//import lib._ -//import include._ -// -//class lsu_bus_intf extends Module with RequireAsyncReset with lib { -// val io = IO (new Bundle { -// val scan_mode = Input(Bool()) -// val clk_override = Input(Bool()) -// val tlu_busbuff = new tlu_busbuff() -// val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable -// val lsu_busm_clken = Input(Bool()) -// val lsu_c1_r_clk = Input(Clock()) -// val lsu_c2_r_clk = Input(Clock()) -// val lsu_bus_ibuf_c1_clk = Input(Clock()) -// val lsu_bus_obuf_c1_clk = Input(Clock()) -// val lsu_bus_buf_c1_clk = Input(Clock()) -// val lsu_free_c2_clk = Input(Clock()) -// val active_clk = Input(Clock()) -// val lsu_busm_clk = Input(Clock()) -// val axi = new axi_channels(LSU_BUS_TAG) -// val dec_lsu_valid_raw_d = Input(Bool()) -// val lsu_busreq_m = Input(Bool()) -// -// val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) -// val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) -// -// val lsu_addr_m = Input(UInt(32.W)) -// val lsu_addr_r = Input(UInt(32.W)) -// -// val end_addr_m = Input(UInt(32.W)) -// val end_addr_r = Input(UInt(32.W)) -// val ldst_dual_d = Input(Bool()) -// val ldst_dual_m = Input(Bool()) -// val ldst_dual_r = Input(Bool()) -// -// val store_data_r = Input(UInt(32.W)) -// val dec_tlu_force_halt = Input(Bool()) -// -// val lsu_commit_r = Input(Bool()) -// val is_sideeffects_m = Input(Bool()) -// val flush_m_up = Input(Bool()) -// val flush_r = Input(Bool()) -// -// val lsu_busreq_r = Output(Bool()) -// val lsu_bus_buffer_pend_any = Output(Bool()) -// val lsu_bus_buffer_full_any = Output(Bool()) -// val lsu_bus_buffer_empty_any = Output(Bool()) -// //val lsu_bus_idle_any = Output(Bool()) -// val bus_read_data_m = Output(UInt(32.W)) -// -// val dctl_busbuff = new dctl_busbuff() -// -// val lsu_bus_clk_en = Input(Bool()) -// }) -// -// val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B) -// val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U) -// val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) -// val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U) -// val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U) -// val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U) -// val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U) -// val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U) -// val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U) -// val is_sideeffects_r = WireInit(Bool(), init = false.B) -// val store_data_ext_r = WireInit(UInt(64.W), init = 0.U) -// val store_data_hi_r = WireInit(UInt(32.W), init = 0.U) -// val store_data_lo_r = WireInit(UInt(32.W), init = 0.U) -// val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B) -// val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B) -// val no_word_merge_r = WireInit(Bool(), init = false.B) -// val no_dword_merge_r = WireInit(Bool(), init = false.B) -// val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B) -// val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B) -// val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B) -// val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B) -// val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U) -// val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U) -// val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U) -// val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U) -// val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U) -// val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U) -// val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U) -// val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U) -// val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U) -// val ld_full_hit_hi_m = WireInit(Bool(), init = true.B) -// val ld_full_hit_lo_m = WireInit(Bool(), init = true.B) -// val ld_full_hit_m = WireInit(Bool(), init = false.B) -// -// val bus_buffer = Module(new lsu_bus_buffer) -// -// bus_buffer.io.scan_mode := io.scan_mode -// io.tlu_busbuff <> bus_buffer.io.tlu_busbuff -// bus_buffer.io.clk_override := io.clk_override -// bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken -// bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken -// bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt -// bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk -// bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk -// bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk -// bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk -// bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk -// bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk -// bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d -// -// // -// bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m -// bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r -// // -// -// bus_buffer.io.lsu_addr_m := io.lsu_addr_m -// bus_buffer.io.end_addr_m := io.end_addr_m -// bus_buffer.io.lsu_addr_r := io.lsu_addr_r -// bus_buffer.io.end_addr_r := io.end_addr_r -// bus_buffer.io.store_data_r := io.store_data_r -// -// bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m -// bus_buffer.io.flush_m_up := io.flush_m_up -// bus_buffer.io.flush_r := io.flush_r -// bus_buffer.io.lsu_commit_r := io.lsu_commit_r -// bus_buffer.io.lsu_axi <> io.axi -// bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en -// -// io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r -// io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any -// io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any -// io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any -// //io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any -// ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo -// ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi -// ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo -// ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi -// io.dctl_busbuff <> bus_buffer.io.dctl_busbuff -// bus_buffer.io.no_word_merge_r := no_word_merge_r -// bus_buffer.io.no_dword_merge_r := no_dword_merge_r -// bus_buffer.io.is_sideeffects_r := is_sideeffects_r -// bus_buffer.io.ldst_dual_d := io.ldst_dual_d -// bus_buffer.io.ldst_dual_m := io.ldst_dual_m -// bus_buffer.io.ldst_dual_r := io.ldst_dual_r -// bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m -// bus_buffer.io.ld_full_hit_m := ld_full_hit_m -// bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q -// -// ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W))) -// addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3)) -// addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2)) -// no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m) -// no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m) -// -// ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0) -// ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0) -// store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W)) -// ldst_byteen_hi_m := ldst_byteen_ext_m(7,4) -// ldst_byteen_lo_m := ldst_byteen_ext_m(3,0) -// ldst_byteen_hi_r := ldst_byteen_ext_r(7,4) -// ldst_byteen_lo_r := ldst_byteen_ext_r(3,0) -// -// store_data_hi_r := store_data_ext_r(63,32) -// store_data_lo_r := store_data_ext_r(31,0) -// ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m -// ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m -// ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m -// ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m -// -// ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) -// -// ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_)) -// ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) -// ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) -// ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) -// ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) -// ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_) -// ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_) -// ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m -// ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0)) -// io.bus_read_data_m := ld_fwddata_m(31,0) -// -// withClock(io.active_clk) { -// lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U) -// } -// -// withClock(io.lsu_c1_r_clk) { -// is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U) -// ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W)) -// } -//} -//object bus_intf extends App { -// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf())) -//} \ No newline at end of file +package lsu +import chisel3._ +import chisel3.util._ +import lib._ +import include._ + +class lsu_bus_intf extends Module with RequireAsyncReset with lib { + val io = IO (new Bundle { + val scan_mode = Input(Bool()) + val clk_override = Input(Bool()) + val tlu_busbuff = new tlu_busbuff() + val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable + val lsu_busm_clken = Input(Bool()) + val lsu_c1_r_clk = Input(Clock()) + val lsu_c2_r_clk = Input(Clock()) + val lsu_bus_ibuf_c1_clk = Input(Clock()) + val lsu_bus_obuf_c1_clk = Input(Clock()) + val lsu_bus_buf_c1_clk = Input(Clock()) + val lsu_free_c2_clk = Input(Clock()) + val active_clk = Input(Clock()) + val lsu_busm_clk = Input(Clock()) + val axi = new axi_channels(LSU_BUS_TAG) + val dec_lsu_valid_raw_d = Input(Bool()) + val lsu_busreq_m = Input(Bool()) + + val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) + val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) + + val lsu_addr_m = Input(UInt(32.W)) + val lsu_addr_r = Input(UInt(32.W)) + + val end_addr_m = Input(UInt(32.W)) + val end_addr_r = Input(UInt(32.W)) + val ldst_dual_d = Input(Bool()) + val ldst_dual_m = Input(Bool()) + val ldst_dual_r = Input(Bool()) + + val store_data_r = Input(UInt(32.W)) + val dec_tlu_force_halt = Input(Bool()) + + val lsu_commit_r = Input(Bool()) + val is_sideeffects_m = Input(Bool()) + val flush_m_up = Input(Bool()) + val flush_r = Input(Bool()) + + val lsu_busreq_r = Output(Bool()) + val lsu_bus_buffer_pend_any = Output(Bool()) + val lsu_bus_buffer_full_any = Output(Bool()) + val lsu_bus_buffer_empty_any = Output(Bool()) + //val lsu_bus_idle_any = Output(Bool()) + val bus_read_data_m = Output(UInt(32.W)) + val lsu_nonblock_load_data = Output((UInt(32.W))) + val dctl_busbuff = new dctl_busbuff() + + val lsu_bus_clk_en = Input(Bool()) + }) + + val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B) + val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U) + val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U) + val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U) + val is_sideeffects_r = WireInit(Bool(), init = false.B) + val store_data_ext_r = WireInit(UInt(64.W), init = 0.U) + val store_data_hi_r = WireInit(UInt(32.W), init = 0.U) + val store_data_lo_r = WireInit(UInt(32.W), init = 0.U) + val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B) + val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B) + val no_word_merge_r = WireInit(Bool(), init = false.B) + val no_dword_merge_r = WireInit(Bool(), init = false.B) + val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B) + val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B) + val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B) + val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B) + val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U) + val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U) + val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U) + val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U) + val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U) + val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U) + val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U) + val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U) + val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U) + val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U) + val ld_full_hit_hi_m = WireInit(Bool(), init = true.B) + val ld_full_hit_lo_m = WireInit(Bool(), init = true.B) + val ld_full_hit_m = WireInit(Bool(), init = false.B) + + val bus_buffer = Module(new lsu_bus_buffer) + + bus_buffer.io.scan_mode := io.scan_mode + io.tlu_busbuff <> bus_buffer.io.tlu_busbuff + bus_buffer.io.clk_override := io.clk_override + bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken + bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken + bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt + bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk + bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk + bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk + bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk + bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk + bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk + bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d + + // + bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m + bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r + // + + bus_buffer.io.lsu_addr_m := io.lsu_addr_m + bus_buffer.io.end_addr_m := io.end_addr_m + bus_buffer.io.lsu_addr_r := io.lsu_addr_r + bus_buffer.io.end_addr_r := io.end_addr_r + bus_buffer.io.store_data_r := io.store_data_r + + bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m + bus_buffer.io.flush_m_up := io.flush_m_up + bus_buffer.io.flush_r := io.flush_r + bus_buffer.io.lsu_commit_r := io.lsu_commit_r + bus_buffer.io.lsu_axi <> io.axi + bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en + io.lsu_nonblock_load_data := bus_buffer.io.lsu_nonblock_load_data + io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r + io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any + io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any + io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any + //io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any + ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo + ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi + ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo + ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi + io.dctl_busbuff <> bus_buffer.io.dctl_busbuff + bus_buffer.io.no_word_merge_r := no_word_merge_r + bus_buffer.io.no_dword_merge_r := no_dword_merge_r + bus_buffer.io.is_sideeffects_r := is_sideeffects_r + bus_buffer.io.ldst_dual_d := io.ldst_dual_d + bus_buffer.io.ldst_dual_m := io.ldst_dual_m + bus_buffer.io.ldst_dual_r := io.ldst_dual_r + bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m + bus_buffer.io.ld_full_hit_m := ld_full_hit_m + bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q + + ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W))) + addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3)) + addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2)) + no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m) + no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m) + + ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0) + ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0) + store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W)) + ldst_byteen_hi_m := ldst_byteen_ext_m(7,4) + ldst_byteen_lo_m := ldst_byteen_ext_m(3,0) + ldst_byteen_hi_r := ldst_byteen_ext_r(7,4) + ldst_byteen_lo_r := ldst_byteen_ext_r(3,0) + + store_data_hi_r := store_data_ext_r(63,32) + store_data_lo_r := store_data_ext_r(31,0) + ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m + ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m + ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m + ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m + + ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) + + ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) + ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_) + ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_) + ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m + ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0)) + io.bus_read_data_m := ld_fwddata_m(31,0) + + withClock(io.active_clk) { + lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U) + } + + withClock(io.lsu_c1_r_clk) { + is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U) + ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W)) + } +} +object bus_intf extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf())) +} \ No newline at end of file diff --git a/src/main/scala/lsu/lsu_lsc_ctl.scala b/src/main/scala/lsu/lsu_lsc_ctl.scala index 9c9ad2af..f7c80764 100644 --- a/src/main/scala/lsu/lsu_lsc_ctl.scala +++ b/src/main/scala/lsu/lsu_lsc_ctl.scala @@ -26,9 +26,9 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val flush_m_up = Input(UInt(1.W)) val flush_r = Input(UInt(1.W)) - val ldst_dual_d = Input(UInt(1.W)) - val ldst_dual_m = Input(UInt(1.W)) - val ldst_dual_r = Input(UInt(1.W)) + val ldst_dual_d = Input(Bool()) + val ldst_dual_m = Input(Bool()) + val ldst_dual_r = Input(Bool()) val lsu_exu = new lsu_exu() @@ -39,7 +39,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val picm_mask_data_m = Input(UInt(32.W)) val bus_read_data_m = Input(UInt(32.W)) //coming from bus interface - val lsu_result_m = Output(UInt(32.W)) + // val lsu_result_m = Output(UInt(32.W)) val lsu_result_corr_r = Output(UInt(32.W)) // This is the ECC corrected data going to RF // lsu address down the pipe @@ -100,7 +100,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d) val rs1_d_raw = lsu_rs1_d val offset_d = lsu_offset_d - val rs1_d = Mux(io.lsu_pkt_d.bits.load_ldst_bypass_d.asBool,io.lsu_result_m,rs1_d_raw) + val rs1_d = Mux(io.lsu_pkt_d.bits.load_ldst_bypass_d.asBool,io.lsu_exu.lsu_result_m,rs1_d_raw) // generate the ls address val full_addr_d = rvlsadder(rs1_d,offset_d) @@ -220,15 +220,16 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val dma_mem_wdata_shifted = io.dma_lsc_ctl.dma_mem_wdata(63,0) >> Cat(io.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores val store_data_d = Mux(io.dma_lsc_ctl.dma_dccm_req.asBool,dma_mem_wdata_shifted(31,0),io.lsu_exu.exu_lsu_rs2_d(31,0)) // Write to PIC still happens in r stage - val store_data_m_in = Mux(io.lsu_pkt_d.bits.store_data_bypass_d.asBool,io.lsu_result_m(31,0),store_data_d(31,0)) - + val store_data_m_in = Mux(io.lsu_pkt_d.bits.store_data_bypass_d.asBool,io.lsu_exu.lsu_result_m(31,0),store_data_d(31,0)) + val int = withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d(2),0.U)} =/= withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2),0.U)} + val int1 = withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m(2),0.U)} =/= withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2),0.U)} val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)} io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)} io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)} - io.end_addr_m := Cat(Mux(io.ldst_dual_m,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)}) - io.end_addr_r := Cat(Mux(io.ldst_dual_r,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2,0),0.U)}) + io.end_addr_m := Cat(Mux(int,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)}) + io.end_addr_r := Cat(Mux(int1,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2,0),0.U)}) end_addr_pre_m := rvdffe(io.end_addr_d(31,3),((io.lsu_pkt_d.valid & io.ldst_dual_d) | io.clk_override),clock,io.scan_mode) - end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & io.ldst_dual_m) | io.clk_override),clock,io.scan_mode) + end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & int) | io.clk_override),clock,io.scan_mode) io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)} io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)} io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)} @@ -243,14 +244,14 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib io.lsu_addr_d := full_addr_d // Interrupt as a flush source allows the WB to occur io.lsu_commit_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.bits.store | io.lsu_pkt_r.bits.load) & !io.flush_r & !io.lsu_pkt_r.bits.dma - io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,!io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.bits.store_data_bypass_m.asBool,io.lsu_result_m,store_data_pre_m) + io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,!io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.bits.store_data_bypass_m.asBool,io.lsu_exu.lsu_result_m,store_data_pre_m) if (LOAD_TO_USE_PLUS1 == 1){ //bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl lsu_ld_datafn_r := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_r) lsu_ld_datafn_corr_r := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_corr_r) // this is really R stage but don't want to make all the changes to support M,R buses - io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) | + io.lsu_exu.lsu_result_m := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) | ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_r(15,0))) | ((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat((Fill(24, lsu_ld_datafn_r(7))) ,lsu_ld_datafn_r(7,0))) | ((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat((Fill(16,lsu_ld_datafn_r(15))) ,lsu_ld_datafn_r(15,0))) | @@ -266,7 +267,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib else { lsu_ld_datafn_m := Mux(io.addr_external_m, io.bus_read_data_m,io.lsu_ld_data_m) lsu_ld_datafn_corr_r := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r) - io.lsu_result_m := ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) | + io.lsu_exu.lsu_result_m := ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) | ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_m(15,0))) | ((Fill(32,!io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat((Fill(24, lsu_ld_datafn_m(7))) ,lsu_ld_datafn_m(7,0))) | ((Fill(32,!io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat((Fill(16,lsu_ld_datafn_m(15))) ,lsu_ld_datafn_m(15,0))) | diff --git a/target/scala-2.12/classes/exu/exu$$anon$1.class b/target/scala-2.12/classes/exu/exu$$anon$1.class index c9dc09bd..f8d45123 100644 Binary files a/target/scala-2.12/classes/exu/exu$$anon$1.class and b/target/scala-2.12/classes/exu/exu$$anon$1.class differ diff --git a/target/scala-2.12/classes/exu/exu.class b/target/scala-2.12/classes/exu/exu.class index b1eec122..ffaeaa3e 100644 Binary files a/target/scala-2.12/classes/exu/exu.class and b/target/scala-2.12/classes/exu/exu.class differ diff --git a/target/scala-2.12/classes/exu/exu_main$.class b/target/scala-2.12/classes/exu/exu_main$.class index 0733df88..5c0e82c8 100644 Binary files a/target/scala-2.12/classes/exu/exu_main$.class and b/target/scala-2.12/classes/exu/exu_main$.class differ diff --git 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