From 9da7df3623b386473db0074a5379b38822e63148 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Thu, 28 Jan 2021 17:36:33 +0500 Subject: [PATCH] LSU Added --- exu.anno.json | 34 +- exu.fir | 782 +- exu.v | 540 +- lsu.anno.json | 547 + lsu.fir | 16090 ++++++++++++++++ lsu.v | 11116 +++++++++++ lsu_bus_intf.anno.json | 113 + lsu_bus_intf.fir | 7199 +++++++ lsu_bus_intf.v | 5244 +++++ lsu_lsc_ctl.anno.json | 331 + lsu_lsc_ctl.fir | 987 + lsu_lsc_ctl.v | 1500 ++ src/main/scala/exu/exu.scala | 5 +- src/main/scala/include/bundle.scala | 3 +- src/main/scala/lsu/lsu.scala | 717 +- src/main/scala/lsu/lsu_bus_buffer.scala | 1265 +- src/main/scala/lsu/lsu_bus_intf.scala | 410 +- src/main/scala/lsu/lsu_lsc_ctl.scala | 27 +- .../scala-2.12/classes/exu/exu$$anon$1.class | Bin 3113 -> 3262 bytes target/scala-2.12/classes/exu/exu.class | Bin 263720 -> 263741 bytes target/scala-2.12/classes/exu/exu_main$.class | Bin 3844 -> 3844 bytes .../exu/exu_main$delayedInit$body.class | Bin 730 -> 730 bytes .../scala-2.12/classes/include/aln_dec.class | Bin 1625 -> 1625 bytes .../scala-2.12/classes/include/aln_ib.class | Bin 55223 -> 55223 bytes .../classes/include/alu_pkt_t.class | Bin 8001 -> 8001 bytes .../scala-2.12/classes/include/br_pkt_t.class | Bin 2549 -> 2549 bytes .../classes/include/br_tlu_pkt_t.class | Bin 2108 -> 2108 bytes .../classes/include/cache_debug_pkt_t.class | Bin 2066 -> 2066 bytes .../classes/include/ccm_ext_in_pkt_t.class | Bin 2649 -> 2649 bytes .../classes/include/class_pkt_t.class | Bin 1751 -> 1751 bytes .../scala-2.12/classes/include/dbg_dctl.class | Bin 1632 -> 1632 bytes .../scala-2.12/classes/include/dbg_ib.class | Bin 2340 -> 2340 bytes .../classes/include/dccm_ext_in_pkt_t.class | Bin 2652 -> 2652 bytes .../classes/include/dctl_busbuff.class | Bin 54216 -> 54216 bytes .../scala-2.12/classes/include/dec_aln.class | Bin 52866 -> 52866 bytes .../scala-2.12/classes/include/dec_alu.class | Bin 2443 -> 2443 bytes .../scala-2.12/classes/include/dec_dbg.class | Bin 1349 -> 1349 bytes .../scala-2.12/classes/include/dec_div.class | Bin 2240 -> 2240 bytes .../scala-2.12/classes/include/dec_exu.class | Bin 53350 -> 53350 bytes .../classes/include/dec_pkt_t.class | Bin 14907 -> 14907 bytes .../classes/include/dec_tlu_csr_pkt.class | Bin 12983 -> 12983 bytes .../classes/include/decode_exu.class | Bin 57600 -> 57600 bytes .../classes/include/dest_pkt_t.class | Bin 2551 -> 2551 bytes .../classes/include/div_pkt_t.class | Bin 1605 -> 1605 bytes .../scala-2.12/classes/include/dma_ifc.class | Bin 1369 -> 1369 bytes .../classes/include/dma_mem_ctl.class | Bin 2728 -> 2728 bytes .../scala-2.12/classes/include/exu_bp.class | Bin 54407 -> 54407 bytes .../scala-2.12/classes/include/exu_ifu.class | Bin 1243 -> 1243 bytes .../scala-2.12/classes/include/gpr_exu.class | Bin 1814 -> 1814 bytes .../scala-2.12/classes/include/ib_exu.class | Bin 1836 -> 1836 bytes .../include/ic_data_ext_in_pkt_t.class | Bin 2662 -> 2662 bytes .../scala-2.12/classes/include/ic_mem.class | Bin 56735 -> 56735 bytes .../classes/include/ic_tag_ext_in_pkt_t.class | Bin 2659 -> 2659 bytes .../scala-2.12/classes/include/iccm_mem.class | Bin 54224 -> 54224 bytes .../scala-2.12/classes/include/ifu_dec.class | Bin 1860 -> 1860 bytes .../scala-2.12/classes/include/ifu_dma.class | Bin 1378 -> 1378 bytes .../classes/include/inst_pkt_t$.class | Bin 3015 -> 3015 bytes .../classes/include/load_cam_pkt_t.class | Bin 1750 -> 1750 bytes .../scala-2.12/classes/include/lsu_dec.class | Bin 1415 -> 1415 bytes .../classes/include/lsu_error_pkt_t.class | Bin 2148 -> 2148 bytes .../scala-2.12/classes/include/lsu_exu.class | Bin 2293 -> 2068 bytes .../classes/include/lsu_pkt_t.class | Bin 3016 -> 3016 bytes .../scala-2.12/classes/include/lsu_tlu.class | Bin 1608 -> 1608 bytes .../classes/include/mul_pkt_t.class | Bin 4251 -> 4251 bytes .../classes/include/predict_pkt_t.class | Bin 3328 -> 3328 bytes .../classes/include/reg_pkt_t.class | Bin 1738 -> 1738 bytes .../classes/include/rets_pkt_t.class | Bin 1787 -> 1787 bytes .../classes/include/tlu_busbuff.class | Bin 3899 -> 3899 bytes .../scala-2.12/classes/include/tlu_exu.class | Bin 55424 -> 55424 bytes .../classes/include/trace_pkt_t.class | Bin 2835 -> 2835 bytes .../classes/include/trap_pkt_t.class | Bin 3000 -> 3000 bytes .../classes/include/trigger_pkt_t.class | Bin 2395 -> 2395 bytes target/scala-2.12/classes/lsu/buffer$.class | Bin 0 -> 3869 bytes .../classes/lsu/buffer$delayedInit$body.class | Bin 0 -> 729 bytes target/scala-2.12/classes/lsu/buffer.class | Bin 0 -> 774 bytes target/scala-2.12/classes/lsu/bus_intf$.class | Bin 0 -> 3872 bytes .../lsu/bus_intf$delayedInit$body.class | Bin 0 -> 739 bytes target/scala-2.12/classes/lsu/bus_intf.class | Bin 0 -> 782 bytes target/scala-2.12/classes/lsu/lsc_ctl$.class | Bin 3864 -> 3864 bytes .../lsu/lsc_ctl$delayedInit$body.class | Bin 732 -> 732 bytes .../scala-2.12/classes/lsu/lsu$$anon$1.class | Bin 0 -> 7477 bytes target/scala-2.12/classes/lsu/lsu.class | Bin 0 -> 914395 bytes .../classes/lsu/lsu_bus_buffer$$anon$1.class | Bin 0 -> 8365 bytes .../classes/lsu/lsu_bus_buffer.class | Bin 0 -> 582805 bytes .../classes/lsu/lsu_bus_intf$$anon$1.class | Bin 0 -> 7501 bytes .../scala-2.12/classes/lsu/lsu_bus_intf.class | Bin 0 -> 187337 bytes .../classes/lsu/lsu_lsc_ctl$$anon$1.class | Bin 9634 -> 9465 bytes .../scala-2.12/classes/lsu/lsu_lsc_ctl.class | Bin 336909 -> 341453 bytes target/scala-2.12/classes/lsu/lsu_main$.class | Bin 0 -> 3844 bytes .../lsu/lsu_main$delayedInit$body.class | Bin 0 -> 730 bytes target/scala-2.12/classes/lsu/lsu_main.class | Bin 0 -> 773 bytes 91 files changed, 45020 insertions(+), 1890 deletions(-) create mode 100644 lsu.anno.json create mode 100644 lsu.fir create mode 100644 lsu.v create mode 100644 lsu_bus_intf.anno.json create mode 100644 lsu_bus_intf.fir create mode 100644 lsu_bus_intf.v create mode 100644 lsu_lsc_ctl.anno.json create mode 100644 lsu_lsc_ctl.fir create mode 100644 lsu_lsc_ctl.v create mode 100644 target/scala-2.12/classes/lsu/buffer$.class create mode 100644 target/scala-2.12/classes/lsu/buffer$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lsu/buffer.class create mode 100644 target/scala-2.12/classes/lsu/bus_intf$.class create mode 100644 target/scala-2.12/classes/lsu/bus_intf$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lsu/bus_intf.class create mode 100644 target/scala-2.12/classes/lsu/lsu$$anon$1.class create mode 100644 target/scala-2.12/classes/lsu/lsu.class create mode 100644 target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class create mode 100644 target/scala-2.12/classes/lsu/lsu_bus_buffer.class create mode 100644 target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class create mode 100644 target/scala-2.12/classes/lsu/lsu_bus_intf.class create mode 100644 target/scala-2.12/classes/lsu/lsu_main$.class create mode 100644 target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lsu/lsu_main.class diff --git a/exu.anno.json b/exu.anno.json index 3f5451bd..ad79e866 100644 --- a/exu.anno.json +++ b/exu.anno.json @@ -11,7 +11,7 @@ "sink":"~exu|exu>io_lsu_exu_exu_lsu_rs2_d", "sources":[ "~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs2_d", - "~exu|exu>io_dec_qual_lsu_d", + "~exu|exu>io_dec_exu_decode_exu_dec_qual_lsu_d", "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs2_en_d", "~exu|exu>io_lsu_exu_lsu_nonblock_load_data", "~exu|exu>io_dec_exu_decode_exu_dec_extint_stall", @@ -66,22 +66,6 @@ "~exu|exu>io_dec_exu_tlu_exu_exu_i0_br_index_r" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~exu|exu>io_lsu_exu_exu_lsu_rs1_d", - "sources":[ - "~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs1_d", - "~exu|exu>io_dec_exu_tlu_exu_dec_tlu_meihap", - "~exu|exu>io_dec_exu_decode_exu_dec_extint_stall", - "~exu|exu>io_dec_qual_lsu_d", - "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_en_d", - "~exu|exu>io_lsu_exu_lsu_nonblock_load_data", - "~exu|exu>io_dec_exu_decode_exu_exu_i0_result_x", - "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d", - "~exu|exu>io_dec_exu_decode_exu_dec_i0_result_r", - "~exu|exu>io_lsu_exu_lsu_result_m" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~exu|exu>io_exu_flush_final", @@ -132,6 +116,22 @@ "~exu|exu>io_dec_exu_dec_div_dec_div_cancel" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~exu|exu>io_lsu_exu_exu_lsu_rs1_d", + "sources":[ + "~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs1_d", + "~exu|exu>io_dec_exu_tlu_exu_dec_tlu_meihap", + "~exu|exu>io_dec_exu_decode_exu_dec_extint_stall", + "~exu|exu>io_dec_exu_decode_exu_dec_qual_lsu_d", + "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_en_d", + "~exu|exu>io_lsu_exu_lsu_nonblock_load_data", + "~exu|exu>io_dec_exu_decode_exu_exu_i0_result_x", + "~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d", + "~exu|exu>io_dec_exu_decode_exu_dec_i0_result_r", + "~exu|exu>io_lsu_exu_lsu_result_m" + ] + }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" diff --git a/exu.fir b/exu.fir index 4a9386ef..402ba9a9 100644 --- a/exu.fir +++ b/exu.fir @@ -219,7 +219,7 @@ circuit exu : module exu_alu_ctl : input clock : Clock input reset : AsyncReset - output io : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_i0_pc_d : UInt<31>, flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip enable : UInt<1>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}} + output io : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip csr_rddata_in : UInt<32>, flip dec_i0_pc_d : UInt<31>, flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip enable : UInt<1>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}} wire ap_clz : UInt<1> ap_clz <= UInt<1>("h00") @@ -429,7 +429,7 @@ circuit exu : node _T_92 = and(io.i0_ap.unsign, _T_91) @[exu_alu_ctl.scala 154:82] node lt = or(_T_90, _T_92) @[exu_alu_ctl.scala 154:61] node ge = eq(lt, UInt<1>("h00")) @[exu_alu_ctl.scala 155:29] - node _T_93 = asSInt(io.dec_alu.dec_csr_rddata_d) @[exu_alu_ctl.scala 159:73] + node _T_93 = asSInt(io.csr_rddata_in) @[exu_alu_ctl.scala 159:62] node _T_94 = eq(ap_zbb, UInt<1>("h00")) @[exu_alu_ctl.scala 160:22] node _T_95 = and(io.i0_ap.land, _T_94) @[exu_alu_ctl.scala 160:20] node _T_96 = bits(_T_95, 0, 0) @[exu_alu_ctl.scala 160:31] @@ -44537,49 +44537,49 @@ circuit exu : module exu : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}, exu_flush_final : UInt<1>, exu_div_result : UInt<32>, exu_div_wren : UInt<1>, flip dbg_cmd_wrdata : UInt<32>, flip lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>, lsu_nonblock_load_data : UInt<32>}, exu_flush_path_final : UInt<31>, flip dec_qual_lsu_d : UInt<1>} + output io : {flip scan_mode : UInt<1>, dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_qual_lsu_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}, exu_flush_final : UInt<1>, exu_div_result : UInt<32>, exu_div_wren : UInt<1>, flip dbg_cmd_wrdata : UInt<32>, flip dec_csr_rddata_d : UInt<32>, flip lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>, lsu_nonblock_load_data : UInt<32>}, exu_flush_path_final : UInt<31>} - wire ghr_x_ns : UInt<8> @[exu.scala 33:57] - wire ghr_d_ns : UInt<8> @[exu.scala 34:57] - wire ghr_d : UInt<8> @[exu.scala 35:67] - wire i0_taken_d : UInt<1> @[exu.scala 36:63] - wire mul_valid_x : UInt<1> @[exu.scala 37:63] - wire i0_valid_d : UInt<1> @[exu.scala 38:63] - wire i0_branch_x : UInt<1> @[exu.scala 39:39] - wire i0_predict_newp_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 40:51] - wire i0_flush_path_d : UInt<31> @[exu.scala 41:53] - wire i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 42:53] - wire i0_pp_r : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 43:65] - wire i0_predict_p_x : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 44:53] - wire final_predict_mp : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 45:45] - wire pred_correct_npc_r : UInt<32> @[exu.scala 46:51] - wire i0_pred_correct_upper_d : UInt<1> @[exu.scala 47:41] - wire i0_flush_upper_d : UInt<1> @[exu.scala 48:45] - io.exu_bp.exu_mp_pkt.bits.prett <= UInt<1>("h00") @[exu.scala 49:57] - io.exu_bp.exu_mp_pkt.bits.br_start_error <= UInt<1>("h00") @[exu.scala 50:44] - io.exu_bp.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[exu.scala 51:39] - io.exu_bp.exu_mp_pkt.valid <= UInt<1>("h00") @[exu.scala 52:53] - i0_pp_r.bits.toffset <= UInt<1>("h00") @[exu.scala 53:39] - node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 55:69] - node _T = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69] - node x_data_en_q1 = and(_T, io.dec_exu.dec_alu.dec_csr_ren_d) @[exu.scala 56:73] - node _T_1 = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 57:69] - node x_data_en_q2 = and(_T_1, io.dec_exu.decode_exu.dec_i0_branch_d) @[exu.scala 57:73] - node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 58:69] - node _T_2 = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 59:69] - node r_data_en_q2 = and(_T_2, i0_branch_x) @[exu.scala 59:73] - node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 60:68] - node r_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 0, 0) @[exu.scala 61:68] + wire ghr_x_ns : UInt<8> @[exu.scala 32:57] + wire ghr_d_ns : UInt<8> @[exu.scala 33:57] + wire ghr_d : UInt<8> @[exu.scala 34:67] + wire i0_taken_d : UInt<1> @[exu.scala 35:63] + wire mul_valid_x : UInt<1> @[exu.scala 36:63] + wire i0_valid_d : UInt<1> @[exu.scala 37:63] + wire i0_branch_x : UInt<1> @[exu.scala 38:39] + wire i0_predict_newp_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 39:51] + wire i0_flush_path_d : UInt<31> @[exu.scala 40:53] + wire i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 41:53] + wire i0_pp_r : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 42:65] + wire i0_predict_p_x : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 43:53] + wire final_predict_mp : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 44:45] + wire pred_correct_npc_r : UInt<32> @[exu.scala 45:51] + wire i0_pred_correct_upper_d : UInt<1> @[exu.scala 46:41] + wire i0_flush_upper_d : UInt<1> @[exu.scala 47:45] + io.exu_bp.exu_mp_pkt.bits.prett <= UInt<1>("h00") @[exu.scala 48:57] + io.exu_bp.exu_mp_pkt.bits.br_start_error <= UInt<1>("h00") @[exu.scala 49:44] + io.exu_bp.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[exu.scala 50:39] + io.exu_bp.exu_mp_pkt.valid <= UInt<1>("h00") @[exu.scala 51:53] + i0_pp_r.bits.toffset <= UInt<1>("h00") @[exu.scala 52:39] + node x_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 54:69] + node _T = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 55:69] + node x_data_en_q1 = and(_T, io.dec_exu.dec_alu.dec_csr_ren_d) @[exu.scala 55:73] + node _T_1 = bits(io.dec_exu.decode_exu.dec_data_en, 1, 1) @[exu.scala 56:69] + node x_data_en_q2 = and(_T_1, io.dec_exu.decode_exu.dec_i0_branch_d) @[exu.scala 56:73] + node r_data_en = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 57:69] + node _T_2 = bits(io.dec_exu.decode_exu.dec_data_en, 0, 0) @[exu.scala 58:69] + node r_data_en_q2 = and(_T_2, i0_branch_x) @[exu.scala 58:73] + node x_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 1, 1) @[exu.scala 59:68] + node r_ctl_en = bits(io.dec_exu.decode_exu.dec_ctl_en, 0, 0) @[exu.scala 60:68] node _T_3 = cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d) @[Cat.scala 29:58] node predpipe_d = cat(_T_3, io.dec_exu.decode_exu.i0_predict_btag_d) @[Cat.scala 29:58] - node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 64:68] + node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 63:68] wire _T_5 : UInt<31> @[lib.scala 648:38] _T_5 <= UInt<1>("h00") @[lib.scala 648:38] reg i0_flush_path_x : UInt, clock with : (reset => (reset, _T_5)) @[Reg.scala 27:20] when _T_4 : @[Reg.scala 28:19] i0_flush_path_x <= i0_flush_path_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 65:116] + node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 64:116] node _T_7 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] wire _T_8 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] _T_8.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] @@ -44613,21 +44613,21 @@ circuit exu : _T_9.bits.misp <= i0_predict_p_d.bits.misp @[Reg.scala 28:23] _T_9.valid <= i0_predict_p_d.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - i0_predict_p_x.bits.prett <= _T_9.bits.prett @[exu.scala 65:55] - i0_predict_p_x.bits.pret <= _T_9.bits.pret @[exu.scala 65:55] - i0_predict_p_x.bits.way <= _T_9.bits.way @[exu.scala 65:55] - i0_predict_p_x.bits.pja <= _T_9.bits.pja @[exu.scala 65:55] - i0_predict_p_x.bits.pcall <= _T_9.bits.pcall @[exu.scala 65:55] - i0_predict_p_x.bits.br_start_error <= _T_9.bits.br_start_error @[exu.scala 65:55] - i0_predict_p_x.bits.br_error <= _T_9.bits.br_error @[exu.scala 65:55] - i0_predict_p_x.bits.toffset <= _T_9.bits.toffset @[exu.scala 65:55] - i0_predict_p_x.bits.hist <= _T_9.bits.hist @[exu.scala 65:55] - i0_predict_p_x.bits.pc4 <= _T_9.bits.pc4 @[exu.scala 65:55] - i0_predict_p_x.bits.boffset <= _T_9.bits.boffset @[exu.scala 65:55] - i0_predict_p_x.bits.ataken <= _T_9.bits.ataken @[exu.scala 65:55] - i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 65:55] - i0_predict_p_x.valid <= _T_9.valid @[exu.scala 65:55] - node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 66:79] + i0_predict_p_x.bits.prett <= _T_9.bits.prett @[exu.scala 64:55] + i0_predict_p_x.bits.pret <= _T_9.bits.pret @[exu.scala 64:55] + i0_predict_p_x.bits.way <= _T_9.bits.way @[exu.scala 64:55] + i0_predict_p_x.bits.pja <= _T_9.bits.pja @[exu.scala 64:55] + i0_predict_p_x.bits.pcall <= _T_9.bits.pcall @[exu.scala 64:55] + i0_predict_p_x.bits.br_start_error <= _T_9.bits.br_start_error @[exu.scala 64:55] + i0_predict_p_x.bits.br_error <= _T_9.bits.br_error @[exu.scala 64:55] + i0_predict_p_x.bits.toffset <= _T_9.bits.toffset @[exu.scala 64:55] + i0_predict_p_x.bits.hist <= _T_9.bits.hist @[exu.scala 64:55] + i0_predict_p_x.bits.pc4 <= _T_9.bits.pc4 @[exu.scala 64:55] + i0_predict_p_x.bits.boffset <= _T_9.bits.boffset @[exu.scala 64:55] + i0_predict_p_x.bits.ataken <= _T_9.bits.ataken @[exu.scala 64:55] + i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 64:55] + i0_predict_p_x.valid <= _T_9.valid @[exu.scala 64:55] + node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 65:79] inst rvclkhdr of rvclkhdr @[lib.scala 404:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -44638,7 +44638,7 @@ circuit exu : when _T_10 : @[Reg.scala 28:19] predpipe_x <= predpipe_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 67:88] + node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 66:88] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -44649,7 +44649,7 @@ circuit exu : when _T_11 : @[Reg.scala 28:19] predpipe_r <= predpipe_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 68:86] + node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 67:86] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -44660,7 +44660,7 @@ circuit exu : when _T_12 : @[Reg.scala 28:19] ghr_x <= ghr_x_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 69:75] + node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 68:75] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -44671,7 +44671,7 @@ circuit exu : when _T_13 : @[Reg.scala 28:19] i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 70:66] + node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 69:66] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -44682,7 +44682,7 @@ circuit exu : when _T_14 : @[Reg.scala 28:19] i0_flush_upper_x <= i0_flush_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] + node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 70:84] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -44693,7 +44693,7 @@ circuit exu : when _T_15 : @[Reg.scala 28:19] i0_taken_x <= i0_taken_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 72:84] + node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -44704,7 +44704,7 @@ circuit exu : when _T_16 : @[Reg.scala 28:19] i0_valid_x <= i0_valid_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 73:93] + node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 72:93] node _T_18 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] wire _T_19 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] _T_19.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] @@ -44738,44 +44738,44 @@ circuit exu : _T_20.bits.misp <= i0_predict_p_x.bits.misp @[Reg.scala 28:23] _T_20.valid <= i0_predict_p_x.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - i0_pp_r.bits.prett <= _T_20.bits.prett @[exu.scala 73:31] - i0_pp_r.bits.pret <= _T_20.bits.pret @[exu.scala 73:31] - i0_pp_r.bits.way <= _T_20.bits.way @[exu.scala 73:31] - i0_pp_r.bits.pja <= _T_20.bits.pja @[exu.scala 73:31] - i0_pp_r.bits.pcall <= _T_20.bits.pcall @[exu.scala 73:31] - i0_pp_r.bits.br_start_error <= _T_20.bits.br_start_error @[exu.scala 73:31] - i0_pp_r.bits.br_error <= _T_20.bits.br_error @[exu.scala 73:31] - i0_pp_r.bits.toffset <= _T_20.bits.toffset @[exu.scala 73:31] - i0_pp_r.bits.hist <= _T_20.bits.hist @[exu.scala 73:31] - i0_pp_r.bits.pc4 <= _T_20.bits.pc4 @[exu.scala 73:31] - i0_pp_r.bits.boffset <= _T_20.bits.boffset @[exu.scala 73:31] - i0_pp_r.bits.ataken <= _T_20.bits.ataken @[exu.scala 73:31] - i0_pp_r.bits.misp <= _T_20.bits.misp @[exu.scala 73:31] - i0_pp_r.valid <= _T_20.valid @[exu.scala 73:31] - node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 74:94] - node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 74:111] + i0_pp_r.bits.prett <= _T_20.bits.prett @[exu.scala 72:31] + i0_pp_r.bits.pret <= _T_20.bits.pret @[exu.scala 72:31] + i0_pp_r.bits.way <= _T_20.bits.way @[exu.scala 72:31] + i0_pp_r.bits.pja <= _T_20.bits.pja @[exu.scala 72:31] + i0_pp_r.bits.pcall <= _T_20.bits.pcall @[exu.scala 72:31] + i0_pp_r.bits.br_start_error <= _T_20.bits.br_start_error @[exu.scala 72:31] + i0_pp_r.bits.br_error <= _T_20.bits.br_error @[exu.scala 72:31] + i0_pp_r.bits.toffset <= _T_20.bits.toffset @[exu.scala 72:31] + i0_pp_r.bits.hist <= _T_20.bits.hist @[exu.scala 72:31] + i0_pp_r.bits.pc4 <= _T_20.bits.pc4 @[exu.scala 72:31] + i0_pp_r.bits.boffset <= _T_20.bits.boffset @[exu.scala 72:31] + i0_pp_r.bits.ataken <= _T_20.bits.ataken @[exu.scala 72:31] + i0_pp_r.bits.misp <= _T_20.bits.misp @[exu.scala 72:31] + i0_pp_r.valid <= _T_20.valid @[exu.scala 72:31] + node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 73:94] + node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 73:111] wire _T_23 : UInt<6> @[lib.scala 648:38] _T_23 <= UInt<1>("h00") @[lib.scala 648:38] reg pred_temp1 : UInt, clock with : (reset => (reset, _T_23)) @[Reg.scala 27:20] when _T_22 : @[Reg.scala 28:19] pred_temp1 <= _T_21 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 75:109] + node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 74:109] wire _T_25 : UInt @[lib.scala 588:35] _T_25 <= UInt<1>("h00") @[lib.scala 588:35] reg i0_pred_correct_upper_r : UInt, clock with : (reset => (reset, _T_25)) @[Reg.scala 27:20] when _T_24 : @[Reg.scala 28:19] i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 76:73] + node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 75:73] wire _T_27 : UInt @[lib.scala 648:38] _T_27 <= UInt<1>("h00") @[lib.scala 648:38] reg i0_flush_path_upper_r : UInt, clock with : (reset => (reset, _T_27)) @[Reg.scala 27:20] when _T_26 : @[Reg.scala 28:19] i0_flush_path_upper_r <= i0_flush_path_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 77:106] - node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 77:124] + node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 76:106] + node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 76:124] wire _T_30 : UInt<25> @[lib.scala 648:38] _T_30 <= UInt<1>("h00") @[lib.scala 648:38] reg pred_temp2 : UInt, clock with : (reset => (reset, _T_30)) @[Reg.scala 27:20] @@ -44783,7 +44783,7 @@ circuit exu : pred_temp2 <= _T_28 @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_31 = cat(pred_temp2, pred_temp1) @[Cat.scala 29:58] - pred_correct_npc_r <= _T_31 @[exu.scala 78:45] + pred_correct_npc_r <= _T_31 @[exu.scala 77:45] wire _T_32 : UInt _T_32 <= UInt<1>("h00") node _T_33 = xor(ghr_d_ns, _T_32) @[lib.scala 448:21] @@ -44793,7 +44793,7 @@ circuit exu : _T_35 <= ghr_d_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_32 <= _T_35 @[lib.scala 451:16] - ghr_d <= _T_32 @[exu.scala 79:43] + ghr_d <= _T_32 @[exu.scala 78:43] wire _T_36 : UInt<1> _T_36 <= UInt<1>("h00") node _T_37 = xor(io.dec_exu.decode_exu.mul_p.valid, _T_36) @[lib.scala 470:21] @@ -44803,7 +44803,7 @@ circuit exu : _T_39 <= io.dec_exu.decode_exu.mul_p.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_36 <= _T_39 @[lib.scala 473:16] - mul_valid_x <= _T_36 @[exu.scala 80:39] + mul_valid_x <= _T_36 @[exu.scala 79:39] wire _T_40 : UInt _T_40 <= UInt<1>("h00") node _T_41 = xor(io.dec_exu.decode_exu.dec_i0_branch_d, _T_40) @[lib.scala 448:21] @@ -44813,29 +44813,29 @@ circuit exu : _T_43 <= io.dec_exu.decode_exu.dec_i0_branch_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_40 <= _T_43 @[lib.scala 451:16] - i0_branch_x <= _T_40 @[exu.scala 81:39] - node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 83:80] - node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 83:130] - node _T_46 = or(_T_44, _T_45) @[exu.scala 83:84] - node _T_47 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 83:180] - node _T_48 = or(_T_46, _T_47) @[exu.scala 83:134] - node _T_49 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 83:230] - node i0_rs1_bypass_en_d = or(_T_48, _T_49) @[exu.scala 83:184] - node _T_50 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 84:80] - node _T_51 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 84:130] - node _T_52 = or(_T_50, _T_51) @[exu.scala 84:84] - node _T_53 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 84:180] - node _T_54 = or(_T_52, _T_53) @[exu.scala 84:134] - node _T_55 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 84:230] - node i0_rs2_bypass_en_d = or(_T_54, _T_55) @[exu.scala 84:184] - node _T_56 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 87:49] - node _T_57 = bits(_T_56, 0, 0) @[exu.scala 87:53] - node _T_58 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 88:49] - node _T_59 = bits(_T_58, 0, 0) @[exu.scala 88:53] - node _T_60 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 89:49] - node _T_61 = bits(_T_60, 0, 0) @[exu.scala 89:53] - node _T_62 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 90:49] - node _T_63 = bits(_T_62, 0, 0) @[exu.scala 90:53] + i0_branch_x <= _T_40 @[exu.scala 80:39] + node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 82:80] + node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 82:130] + node _T_46 = or(_T_44, _T_45) @[exu.scala 82:84] + node _T_47 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 82:180] + node _T_48 = or(_T_46, _T_47) @[exu.scala 82:134] + node _T_49 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 82:230] + node i0_rs1_bypass_en_d = or(_T_48, _T_49) @[exu.scala 82:184] + node _T_50 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 83:80] + node _T_51 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 83:130] + node _T_52 = or(_T_50, _T_51) @[exu.scala 83:84] + node _T_53 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 83:180] + node _T_54 = or(_T_52, _T_53) @[exu.scala 83:134] + node _T_55 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 83:230] + node i0_rs2_bypass_en_d = or(_T_54, _T_55) @[exu.scala 83:184] + node _T_56 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 86:49] + node _T_57 = bits(_T_56, 0, 0) @[exu.scala 86:53] + node _T_58 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 87:49] + node _T_59 = bits(_T_58, 0, 0) @[exu.scala 87:53] + node _T_60 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 2, 2) @[exu.scala 88:49] + node _T_61 = bits(_T_60, 0, 0) @[exu.scala 88:53] + node _T_62 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 3, 3) @[exu.scala 89:49] + node _T_63 = bits(_T_62, 0, 0) @[exu.scala 89:53] node _T_64 = mux(_T_57, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_65 = mux(_T_59, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_66 = mux(_T_61, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44845,14 +44845,14 @@ circuit exu : node _T_70 = or(_T_69, _T_67) @[Mux.scala 27:72] wire i0_rs1_bypass_data_d : UInt<32> @[Mux.scala 27:72] i0_rs1_bypass_data_d <= _T_70 @[Mux.scala 27:72] - node _T_71 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 93:49] - node _T_72 = bits(_T_71, 0, 0) @[exu.scala 93:53] - node _T_73 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 94:49] - node _T_74 = bits(_T_73, 0, 0) @[exu.scala 94:53] - node _T_75 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 95:49] - node _T_76 = bits(_T_75, 0, 0) @[exu.scala 95:53] - node _T_77 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 96:49] - node _T_78 = bits(_T_77, 0, 0) @[exu.scala 96:53] + node _T_71 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 0, 0) @[exu.scala 92:49] + node _T_72 = bits(_T_71, 0, 0) @[exu.scala 92:53] + node _T_73 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 1, 1) @[exu.scala 93:49] + node _T_74 = bits(_T_73, 0, 0) @[exu.scala 93:53] + node _T_75 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 2, 2) @[exu.scala 94:49] + node _T_76 = bits(_T_75, 0, 0) @[exu.scala 94:53] + node _T_77 = bits(io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d, 3, 3) @[exu.scala 95:49] + node _T_78 = bits(_T_77, 0, 0) @[exu.scala 95:53] node _T_79 = mux(_T_72, io.dec_exu.decode_exu.dec_i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_80 = mux(_T_74, io.lsu_exu.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_81 = mux(_T_76, io.dec_exu.decode_exu.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44862,19 +44862,19 @@ circuit exu : node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72] wire i0_rs2_bypass_data_d : UInt<32> @[Mux.scala 27:72] i0_rs2_bypass_data_d <= _T_85 @[Mux.scala 27:72] - node _T_86 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 100:24] - node _T_87 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 101:6] - node _T_88 = and(_T_87, io.dec_exu.decode_exu.dec_i0_select_pc_d) @[exu.scala 101:26] - node _T_89 = bits(_T_88, 0, 0) @[exu.scala 101:71] + node _T_86 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 99:24] + node _T_87 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 100:6] + node _T_88 = and(_T_87, io.dec_exu.decode_exu.dec_i0_select_pc_d) @[exu.scala 100:26] + node _T_89 = bits(_T_88, 0, 0) @[exu.scala 100:71] node _T_90 = cat(io.dec_exu.ib_exu.dec_i0_pc_d, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_91 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 102:6] - node _T_92 = and(_T_91, io.dec_exu.ib_exu.dec_debug_wdata_rs1_d) @[exu.scala 102:26] - node _T_93 = bits(_T_92, 0, 0) @[exu.scala 102:70] - node _T_94 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 103:6] - node _T_95 = eq(io.dec_exu.ib_exu.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[exu.scala 103:28] - node _T_96 = and(_T_94, _T_95) @[exu.scala 103:26] - node _T_97 = and(_T_96, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 103:69] - node _T_98 = bits(_T_97, 0, 0) @[exu.scala 103:110] + node _T_91 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 101:6] + node _T_92 = and(_T_91, io.dec_exu.ib_exu.dec_debug_wdata_rs1_d) @[exu.scala 101:26] + node _T_93 = bits(_T_92, 0, 0) @[exu.scala 101:70] + node _T_94 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 102:6] + node _T_95 = eq(io.dec_exu.ib_exu.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[exu.scala 102:28] + node _T_96 = and(_T_94, _T_95) @[exu.scala 102:26] + node _T_97 = and(_T_96, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 102:69] + node _T_98 = bits(_T_97, 0, 0) @[exu.scala 102:110] node _T_99 = mux(_T_86, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_100 = mux(_T_89, _T_90, UInt<1>("h00")) @[Mux.scala 27:72] node _T_101 = mux(_T_93, io.dbg_cmd_wrdata, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44884,7 +44884,7 @@ circuit exu : node _T_105 = or(_T_104, _T_102) @[Mux.scala 27:72] wire i0_rs1_d : UInt<32> @[Mux.scala 27:72] i0_rs1_d <= _T_105 @[Mux.scala 27:72] - node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 105:88] + node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 104:88] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -44895,13 +44895,13 @@ circuit exu : when _T_106 : @[Reg.scala 28:19] _T_107 <= i0_rs1_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_107 @[exu.scala 105:57] - node _T_108 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 108:6] - node _T_109 = and(_T_108, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 108:26] - node _T_110 = bits(_T_109, 0, 0) @[exu.scala 108:67] - node _T_111 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 109:6] - node _T_112 = bits(_T_111, 0, 0) @[exu.scala 109:27] - node _T_113 = bits(i0_rs2_bypass_en_d, 0, 0) @[exu.scala 110:26] + io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_107 @[exu.scala 104:57] + node _T_108 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 107:6] + node _T_109 = and(_T_108, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 107:26] + node _T_110 = bits(_T_109, 0, 0) @[exu.scala 107:67] + node _T_111 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 108:6] + node _T_112 = bits(_T_111, 0, 0) @[exu.scala 108:27] + node _T_113 = bits(i0_rs2_bypass_en_d, 0, 0) @[exu.scala 109:26] node _T_114 = mux(_T_110, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_115 = mux(_T_112, io.dec_exu.decode_exu.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_116 = mux(_T_113, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44909,18 +44909,18 @@ circuit exu : node _T_118 = or(_T_117, _T_116) @[Mux.scala 27:72] wire i0_rs2_d : UInt<32> @[Mux.scala 27:72] i0_rs2_d <= _T_118 @[Mux.scala 27:72] - node _T_119 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 115:6] - node _T_120 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 115:28] - node _T_121 = and(_T_119, _T_120) @[exu.scala 115:26] - node _T_122 = and(_T_121, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 115:68] - node _T_123 = and(_T_122, io.dec_qual_lsu_d) @[exu.scala 115:108] - node _T_124 = bits(_T_123, 0, 0) @[exu.scala 115:129] - node _T_125 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 116:27] - node _T_126 = and(i0_rs1_bypass_en_d, _T_125) @[exu.scala 116:25] - node _T_127 = and(_T_126, io.dec_qual_lsu_d) @[exu.scala 116:67] - node _T_128 = bits(_T_127, 0, 0) @[exu.scala 116:88] - node _T_129 = and(io.dec_exu.decode_exu.dec_extint_stall, io.dec_qual_lsu_d) @[exu.scala 117:45] - node _T_130 = bits(_T_129, 0, 0) @[exu.scala 117:66] + node _T_119 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 114:6] + node _T_120 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 114:28] + node _T_121 = and(_T_119, _T_120) @[exu.scala 114:26] + node _T_122 = and(_T_121, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 114:68] + node _T_123 = and(_T_122, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 114:108] + node _T_124 = bits(_T_123, 0, 0) @[exu.scala 114:148] + node _T_125 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 115:27] + node _T_126 = and(i0_rs1_bypass_en_d, _T_125) @[exu.scala 115:25] + node _T_127 = and(_T_126, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 115:67] + node _T_128 = bits(_T_127, 0, 0) @[exu.scala 115:107] + node _T_129 = and(io.dec_exu.decode_exu.dec_extint_stall, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 116:45] + node _T_130 = bits(_T_129, 0, 0) @[exu.scala 116:85] node _T_131 = cat(io.dec_exu.tlu_exu.dec_tlu_meihap, UInt<2>("h00")) @[Cat.scala 29:58] node _T_132 = mux(_T_124, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_133 = mux(_T_128, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] @@ -44929,40 +44929,39 @@ circuit exu : node _T_136 = or(_T_135, _T_134) @[Mux.scala 27:72] wire _T_137 : UInt<32> @[Mux.scala 27:72] _T_137 <= _T_136 @[Mux.scala 27:72] - io.lsu_exu.exu_lsu_rs1_d <= _T_137 @[exu.scala 114:27] - node _T_138 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 121:6] - node _T_139 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 121:28] - node _T_140 = and(_T_138, _T_139) @[exu.scala 121:26] - node _T_141 = and(_T_140, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 121:68] - node _T_142 = and(_T_141, io.dec_qual_lsu_d) @[exu.scala 121:108] - node _T_143 = bits(_T_142, 0, 0) @[exu.scala 121:129] - node _T_144 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 122:27] - node _T_145 = and(i0_rs2_bypass_en_d, _T_144) @[exu.scala 122:25] - node _T_146 = and(_T_145, io.dec_qual_lsu_d) @[exu.scala 122:67] - node _T_147 = bits(_T_146, 0, 0) @[exu.scala 122:88] + io.lsu_exu.exu_lsu_rs1_d <= _T_137 @[exu.scala 113:27] + node _T_138 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[exu.scala 120:6] + node _T_139 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 120:28] + node _T_140 = and(_T_138, _T_139) @[exu.scala 120:26] + node _T_141 = and(_T_140, io.dec_exu.decode_exu.dec_i0_rs2_en_d) @[exu.scala 120:68] + node _T_142 = and(_T_141, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 120:108] + node _T_143 = bits(_T_142, 0, 0) @[exu.scala 120:148] + node _T_144 = eq(io.dec_exu.decode_exu.dec_extint_stall, UInt<1>("h00")) @[exu.scala 121:27] + node _T_145 = and(i0_rs2_bypass_en_d, _T_144) @[exu.scala 121:25] + node _T_146 = and(_T_145, io.dec_exu.decode_exu.dec_qual_lsu_d) @[exu.scala 121:67] + node _T_147 = bits(_T_146, 0, 0) @[exu.scala 121:107] node _T_148 = mux(_T_143, io.dec_exu.gpr_exu.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_149 = mux(_T_147, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_150 = or(_T_148, _T_149) @[Mux.scala 27:72] wire _T_151 : UInt<32> @[Mux.scala 27:72] _T_151 <= _T_150 @[Mux.scala 27:72] - io.lsu_exu.exu_lsu_rs2_d <= _T_151 @[exu.scala 120:27] - node _T_152 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 126:6] - node _T_153 = and(_T_152, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 126:26] - node _T_154 = bits(_T_153, 0, 0) @[exu.scala 126:67] - node _T_155 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 127:26] + io.lsu_exu.exu_lsu_rs2_d <= _T_151 @[exu.scala 119:27] + node _T_152 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[exu.scala 125:6] + node _T_153 = and(_T_152, io.dec_exu.decode_exu.dec_i0_rs1_en_d) @[exu.scala 125:26] + node _T_154 = bits(_T_153, 0, 0) @[exu.scala 125:67] + node _T_155 = bits(i0_rs1_bypass_en_d, 0, 0) @[exu.scala 126:26] node _T_156 = mux(_T_154, io.dec_exu.gpr_exu.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_157 = mux(_T_155, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_158 = or(_T_156, _T_157) @[Mux.scala 27:72] wire muldiv_rs1_d : UInt<32> @[Mux.scala 27:72] muldiv_rs1_d <= _T_158 @[Mux.scala 27:72] - inst i_alu of exu_alu_ctl @[exu.scala 130:19] + inst i_alu of exu_alu_ctl @[exu.scala 129:19] i_alu.clock <= clock i_alu.reset <= reset - io.dec_exu.dec_alu.exu_i0_pc_x <= i_alu.io.dec_alu.exu_i0_pc_x @[exu.scala 131:20] - i_alu.io.dec_alu.dec_i0_br_immed_d <= io.dec_exu.dec_alu.dec_i0_br_immed_d @[exu.scala 131:20] - i_alu.io.dec_alu.dec_csr_rddata_d <= io.dec_exu.dec_alu.dec_csr_rddata_d @[exu.scala 131:20] - i_alu.io.dec_alu.dec_csr_ren_d <= io.dec_exu.dec_alu.dec_csr_ren_d @[exu.scala 131:20] - i_alu.io.dec_alu.dec_i0_alu_decode_d <= io.dec_exu.dec_alu.dec_i0_alu_decode_d @[exu.scala 131:20] + io.dec_exu.dec_alu.exu_i0_pc_x <= i_alu.io.dec_alu.exu_i0_pc_x @[exu.scala 130:20] + i_alu.io.dec_alu.dec_i0_br_immed_d <= io.dec_exu.dec_alu.dec_i0_br_immed_d @[exu.scala 130:20] + i_alu.io.dec_alu.dec_csr_ren_d <= io.dec_exu.dec_alu.dec_csr_ren_d @[exu.scala 130:20] + i_alu.io.dec_alu.dec_i0_alu_decode_d <= io.dec_exu.dec_alu.dec_i0_alu_decode_d @[exu.scala 130:20] i_alu.io.scan_mode <= io.scan_mode @[exu.scala 132:35] i_alu.io.enable <= x_data_en @[exu.scala 133:45] i_alu.io.pp_in.bits.prett <= i0_predict_newp_d.bits.prett @[exu.scala 134:45] @@ -44980,155 +44979,156 @@ circuit exu : i_alu.io.pp_in.bits.misp <= i0_predict_newp_d.bits.misp @[exu.scala 134:45] i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[exu.scala 134:45] i_alu.io.flush_upper_x <= i0_flush_upper_x @[exu.scala 135:33] - i_alu.io.dec_tlu_flush_lower_r <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[exu.scala 136:41] - node _T_159 = asSInt(i0_rs1_d) @[exu.scala 137:50] - i_alu.io.a_in <= _T_159 @[exu.scala 137:39] - i_alu.io.b_in <= i0_rs2_d @[exu.scala 138:39] - i_alu.io.dec_i0_pc_d <= io.dec_exu.ib_exu.dec_i0_pc_d @[exu.scala 139:33] - i_alu.io.i0_ap.csr_imm <= io.dec_exu.decode_exu.i0_ap.csr_imm @[exu.scala 140:51] - i_alu.io.i0_ap.csr_write <= io.dec_exu.decode_exu.i0_ap.csr_write @[exu.scala 140:51] - i_alu.io.i0_ap.predict_nt <= io.dec_exu.decode_exu.i0_ap.predict_nt @[exu.scala 140:51] - i_alu.io.i0_ap.predict_t <= io.dec_exu.decode_exu.i0_ap.predict_t @[exu.scala 140:51] - i_alu.io.i0_ap.jal <= io.dec_exu.decode_exu.i0_ap.jal @[exu.scala 140:51] - i_alu.io.i0_ap.unsign <= io.dec_exu.decode_exu.i0_ap.unsign @[exu.scala 140:51] - i_alu.io.i0_ap.slt <= io.dec_exu.decode_exu.i0_ap.slt @[exu.scala 140:51] - i_alu.io.i0_ap.sub <= io.dec_exu.decode_exu.i0_ap.sub @[exu.scala 140:51] - i_alu.io.i0_ap.add <= io.dec_exu.decode_exu.i0_ap.add @[exu.scala 140:51] - i_alu.io.i0_ap.bge <= io.dec_exu.decode_exu.i0_ap.bge @[exu.scala 140:51] - i_alu.io.i0_ap.blt <= io.dec_exu.decode_exu.i0_ap.blt @[exu.scala 140:51] - i_alu.io.i0_ap.bne <= io.dec_exu.decode_exu.i0_ap.bne @[exu.scala 140:51] - i_alu.io.i0_ap.beq <= io.dec_exu.decode_exu.i0_ap.beq @[exu.scala 140:51] - i_alu.io.i0_ap.sra <= io.dec_exu.decode_exu.i0_ap.sra @[exu.scala 140:51] - i_alu.io.i0_ap.srl <= io.dec_exu.decode_exu.i0_ap.srl @[exu.scala 140:51] - i_alu.io.i0_ap.sll <= io.dec_exu.decode_exu.i0_ap.sll @[exu.scala 140:51] - i_alu.io.i0_ap.lxor <= io.dec_exu.decode_exu.i0_ap.lxor @[exu.scala 140:51] - i_alu.io.i0_ap.lor <= io.dec_exu.decode_exu.i0_ap.lor @[exu.scala 140:51] - i_alu.io.i0_ap.land <= io.dec_exu.decode_exu.i0_ap.land @[exu.scala 140:51] - i_alu.io.i0_ap.zba <= io.dec_exu.decode_exu.i0_ap.zba @[exu.scala 140:51] - i_alu.io.i0_ap.sh3add <= io.dec_exu.decode_exu.i0_ap.sh3add @[exu.scala 140:51] - i_alu.io.i0_ap.sh2add <= io.dec_exu.decode_exu.i0_ap.sh2add @[exu.scala 140:51] - i_alu.io.i0_ap.sh1add <= io.dec_exu.decode_exu.i0_ap.sh1add @[exu.scala 140:51] - i_alu.io.i0_ap.sbext <= io.dec_exu.decode_exu.i0_ap.sbext @[exu.scala 140:51] - i_alu.io.i0_ap.sbinv <= io.dec_exu.decode_exu.i0_ap.sbinv @[exu.scala 140:51] - i_alu.io.i0_ap.sbclr <= io.dec_exu.decode_exu.i0_ap.sbclr @[exu.scala 140:51] - i_alu.io.i0_ap.sbset <= io.dec_exu.decode_exu.i0_ap.sbset @[exu.scala 140:51] - i_alu.io.i0_ap.zbb <= io.dec_exu.decode_exu.i0_ap.zbb @[exu.scala 140:51] - i_alu.io.i0_ap.gorc <= io.dec_exu.decode_exu.i0_ap.gorc @[exu.scala 140:51] - i_alu.io.i0_ap.grev <= io.dec_exu.decode_exu.i0_ap.grev @[exu.scala 140:51] - i_alu.io.i0_ap.ror <= io.dec_exu.decode_exu.i0_ap.ror @[exu.scala 140:51] - i_alu.io.i0_ap.rol <= io.dec_exu.decode_exu.i0_ap.rol @[exu.scala 140:51] - i_alu.io.i0_ap.packh <= io.dec_exu.decode_exu.i0_ap.packh @[exu.scala 140:51] - i_alu.io.i0_ap.packu <= io.dec_exu.decode_exu.i0_ap.packu @[exu.scala 140:51] - i_alu.io.i0_ap.pack <= io.dec_exu.decode_exu.i0_ap.pack @[exu.scala 140:51] - i_alu.io.i0_ap.max <= io.dec_exu.decode_exu.i0_ap.max @[exu.scala 140:51] - i_alu.io.i0_ap.min <= io.dec_exu.decode_exu.i0_ap.min @[exu.scala 140:51] - i_alu.io.i0_ap.sro <= io.dec_exu.decode_exu.i0_ap.sro @[exu.scala 140:51] - i_alu.io.i0_ap.slo <= io.dec_exu.decode_exu.i0_ap.slo @[exu.scala 140:51] - i_alu.io.i0_ap.sext_h <= io.dec_exu.decode_exu.i0_ap.sext_h @[exu.scala 140:51] - i_alu.io.i0_ap.sext_b <= io.dec_exu.decode_exu.i0_ap.sext_b @[exu.scala 140:51] - i_alu.io.i0_ap.pcnt <= io.dec_exu.decode_exu.i0_ap.pcnt @[exu.scala 140:51] - i_alu.io.i0_ap.ctz <= io.dec_exu.decode_exu.i0_ap.ctz @[exu.scala 140:51] - i_alu.io.i0_ap.clz <= io.dec_exu.decode_exu.i0_ap.clz @[exu.scala 140:51] - i0_flush_upper_d <= i_alu.io.flush_upper_out @[exu.scala 142:35] - i0_flush_path_d <= i_alu.io.flush_path_out @[exu.scala 143:45] - io.exu_flush_final <= i_alu.io.flush_final_out @[exu.scala 144:27] - i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[exu.scala 145:45] - i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[exu.scala 145:45] - i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[exu.scala 145:45] - i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[exu.scala 145:45] - i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[exu.scala 145:45] - i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[exu.scala 145:45] - i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[exu.scala 145:45] - i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[exu.scala 145:45] - i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[exu.scala 145:45] - i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[exu.scala 145:45] - i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[exu.scala 145:45] - i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[exu.scala 145:45] - i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 145:45] - i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 145:45] - i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 146:27] - inst i_mul of exu_mul_ctl @[exu.scala 148:21] + i_alu.io.csr_rddata_in <= io.dec_csr_rddata_d @[exu.scala 136:33] + i_alu.io.dec_tlu_flush_lower_r <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[exu.scala 137:41] + node _T_159 = asSInt(i0_rs1_d) @[exu.scala 138:50] + i_alu.io.a_in <= _T_159 @[exu.scala 138:39] + i_alu.io.b_in <= i0_rs2_d @[exu.scala 139:39] + i_alu.io.dec_i0_pc_d <= io.dec_exu.ib_exu.dec_i0_pc_d @[exu.scala 140:33] + i_alu.io.i0_ap.csr_imm <= io.dec_exu.decode_exu.i0_ap.csr_imm @[exu.scala 141:51] + i_alu.io.i0_ap.csr_write <= io.dec_exu.decode_exu.i0_ap.csr_write @[exu.scala 141:51] + i_alu.io.i0_ap.predict_nt <= io.dec_exu.decode_exu.i0_ap.predict_nt @[exu.scala 141:51] + i_alu.io.i0_ap.predict_t <= io.dec_exu.decode_exu.i0_ap.predict_t @[exu.scala 141:51] + i_alu.io.i0_ap.jal <= io.dec_exu.decode_exu.i0_ap.jal @[exu.scala 141:51] + i_alu.io.i0_ap.unsign <= io.dec_exu.decode_exu.i0_ap.unsign @[exu.scala 141:51] + i_alu.io.i0_ap.slt <= io.dec_exu.decode_exu.i0_ap.slt @[exu.scala 141:51] + i_alu.io.i0_ap.sub <= io.dec_exu.decode_exu.i0_ap.sub @[exu.scala 141:51] + i_alu.io.i0_ap.add <= io.dec_exu.decode_exu.i0_ap.add @[exu.scala 141:51] + i_alu.io.i0_ap.bge <= io.dec_exu.decode_exu.i0_ap.bge @[exu.scala 141:51] + i_alu.io.i0_ap.blt <= io.dec_exu.decode_exu.i0_ap.blt @[exu.scala 141:51] + i_alu.io.i0_ap.bne <= io.dec_exu.decode_exu.i0_ap.bne @[exu.scala 141:51] + i_alu.io.i0_ap.beq <= io.dec_exu.decode_exu.i0_ap.beq @[exu.scala 141:51] + i_alu.io.i0_ap.sra <= io.dec_exu.decode_exu.i0_ap.sra @[exu.scala 141:51] + i_alu.io.i0_ap.srl <= io.dec_exu.decode_exu.i0_ap.srl @[exu.scala 141:51] + i_alu.io.i0_ap.sll <= io.dec_exu.decode_exu.i0_ap.sll @[exu.scala 141:51] + i_alu.io.i0_ap.lxor <= io.dec_exu.decode_exu.i0_ap.lxor @[exu.scala 141:51] + i_alu.io.i0_ap.lor <= io.dec_exu.decode_exu.i0_ap.lor @[exu.scala 141:51] + i_alu.io.i0_ap.land <= io.dec_exu.decode_exu.i0_ap.land @[exu.scala 141:51] + i_alu.io.i0_ap.zba <= io.dec_exu.decode_exu.i0_ap.zba @[exu.scala 141:51] + i_alu.io.i0_ap.sh3add <= io.dec_exu.decode_exu.i0_ap.sh3add @[exu.scala 141:51] + i_alu.io.i0_ap.sh2add <= io.dec_exu.decode_exu.i0_ap.sh2add @[exu.scala 141:51] + i_alu.io.i0_ap.sh1add <= io.dec_exu.decode_exu.i0_ap.sh1add @[exu.scala 141:51] + i_alu.io.i0_ap.sbext <= io.dec_exu.decode_exu.i0_ap.sbext @[exu.scala 141:51] + i_alu.io.i0_ap.sbinv <= io.dec_exu.decode_exu.i0_ap.sbinv @[exu.scala 141:51] + i_alu.io.i0_ap.sbclr <= io.dec_exu.decode_exu.i0_ap.sbclr @[exu.scala 141:51] + i_alu.io.i0_ap.sbset <= io.dec_exu.decode_exu.i0_ap.sbset @[exu.scala 141:51] + i_alu.io.i0_ap.zbb <= io.dec_exu.decode_exu.i0_ap.zbb @[exu.scala 141:51] + i_alu.io.i0_ap.gorc <= io.dec_exu.decode_exu.i0_ap.gorc @[exu.scala 141:51] + i_alu.io.i0_ap.grev <= io.dec_exu.decode_exu.i0_ap.grev @[exu.scala 141:51] + i_alu.io.i0_ap.ror <= io.dec_exu.decode_exu.i0_ap.ror @[exu.scala 141:51] + i_alu.io.i0_ap.rol <= io.dec_exu.decode_exu.i0_ap.rol @[exu.scala 141:51] + i_alu.io.i0_ap.packh <= io.dec_exu.decode_exu.i0_ap.packh @[exu.scala 141:51] + i_alu.io.i0_ap.packu <= io.dec_exu.decode_exu.i0_ap.packu @[exu.scala 141:51] + i_alu.io.i0_ap.pack <= io.dec_exu.decode_exu.i0_ap.pack @[exu.scala 141:51] + i_alu.io.i0_ap.max <= io.dec_exu.decode_exu.i0_ap.max @[exu.scala 141:51] + i_alu.io.i0_ap.min <= io.dec_exu.decode_exu.i0_ap.min @[exu.scala 141:51] + i_alu.io.i0_ap.sro <= io.dec_exu.decode_exu.i0_ap.sro @[exu.scala 141:51] + i_alu.io.i0_ap.slo <= io.dec_exu.decode_exu.i0_ap.slo @[exu.scala 141:51] + i_alu.io.i0_ap.sext_h <= io.dec_exu.decode_exu.i0_ap.sext_h @[exu.scala 141:51] + i_alu.io.i0_ap.sext_b <= io.dec_exu.decode_exu.i0_ap.sext_b @[exu.scala 141:51] + i_alu.io.i0_ap.pcnt <= io.dec_exu.decode_exu.i0_ap.pcnt @[exu.scala 141:51] + i_alu.io.i0_ap.ctz <= io.dec_exu.decode_exu.i0_ap.ctz @[exu.scala 141:51] + i_alu.io.i0_ap.clz <= io.dec_exu.decode_exu.i0_ap.clz @[exu.scala 141:51] + i0_flush_upper_d <= i_alu.io.flush_upper_out @[exu.scala 143:35] + i0_flush_path_d <= i_alu.io.flush_path_out @[exu.scala 144:45] + io.exu_flush_final <= i_alu.io.flush_final_out @[exu.scala 145:27] + i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[exu.scala 146:45] + i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[exu.scala 146:45] + i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[exu.scala 146:45] + i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[exu.scala 146:45] + i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[exu.scala 146:45] + i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[exu.scala 146:45] + i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[exu.scala 146:45] + i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[exu.scala 146:45] + i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[exu.scala 146:45] + i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[exu.scala 146:45] + i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[exu.scala 146:45] + i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[exu.scala 146:45] + i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[exu.scala 146:45] + i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[exu.scala 146:45] + i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[exu.scala 147:27] + inst i_mul of exu_mul_ctl @[exu.scala 149:21] i_mul.clock <= clock i_mul.reset <= reset - i_mul.io.scan_mode <= io.scan_mode @[exu.scala 149:25] - i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 150:23] - i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 150:23] - i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 150:23] - i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 150:23] - i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 150:23] - i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 150:23] - i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 150:23] - i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 150:23] - i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 150:23] - i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 150:23] - i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 150:23] - i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 150:23] - i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 150:23] - i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 150:23] - i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 150:23] + i_mul.io.scan_mode <= io.scan_mode @[exu.scala 150:25] + i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 151:23] + i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 151:23] + i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 151:23] + i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 151:23] + i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 151:23] + i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 151:23] + i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 151:23] + i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 151:23] + i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 151:23] + i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 151:23] + i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 151:23] + i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 151:23] + i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 151:23] + i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 151:23] + i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 151:23] node _T_160 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] node _T_161 = mux(_T_160, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_162 = and(muldiv_rs1_d, _T_161) @[exu.scala 152:57] - i_mul.io.rs1_in <= _T_162 @[exu.scala 152:41] + node _T_162 = and(muldiv_rs1_d, _T_161) @[exu.scala 153:57] + i_mul.io.rs1_in <= _T_162 @[exu.scala 153:41] node _T_163 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15] node _T_164 = mux(_T_163, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_165 = and(i0_rs2_d, _T_164) @[exu.scala 153:54] - i_mul.io.rs2_in <= _T_165 @[exu.scala 153:41] - inst i_div of exu_div_ctl @[exu.scala 156:21] + node _T_165 = and(i0_rs2_d, _T_164) @[exu.scala 154:54] + i_mul.io.rs2_in <= _T_165 @[exu.scala 154:41] + inst i_div of exu_div_ctl @[exu.scala 157:21] i_div.clock <= clock i_div.reset <= reset - i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 157:20] - i_div.io.dec_div.div_p.bits.rem <= io.dec_exu.dec_div.div_p.bits.rem @[exu.scala 157:20] - i_div.io.dec_div.div_p.bits.unsign <= io.dec_exu.dec_div.div_p.bits.unsign @[exu.scala 157:20] - i_div.io.dec_div.div_p.valid <= io.dec_exu.dec_div.div_p.valid @[exu.scala 157:20] - i_div.io.scan_mode <= io.scan_mode @[exu.scala 158:25] - i_div.io.dividend <= muldiv_rs1_d @[exu.scala 159:33] - i_div.io.divisor <= i0_rs2_d @[exu.scala 160:33] - io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 161:41] - io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 162:33] - node _T_166 = bits(mul_valid_x, 0, 0) @[exu.scala 164:76] - node _T_167 = mux(_T_166, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 164:63] - io.dec_exu.decode_exu.exu_i0_result_x <= _T_167 @[exu.scala 164:57] - i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 165:47] - i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 165:47] - i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 165:47] - i0_predict_newp_d.bits.pja <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[exu.scala 165:47] - i0_predict_newp_d.bits.pcall <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[exu.scala 165:47] - i0_predict_newp_d.bits.br_start_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[exu.scala 165:47] - i0_predict_newp_d.bits.br_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[exu.scala 165:47] - i0_predict_newp_d.bits.toffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[exu.scala 165:47] - i0_predict_newp_d.bits.hist <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[exu.scala 165:47] - i0_predict_newp_d.bits.pc4 <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[exu.scala 165:47] - i0_predict_newp_d.bits.boffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[exu.scala 165:47] - i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 165:47] - i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 165:47] - i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 165:47] - node _T_168 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 166:80] - i0_predict_newp_d.bits.boffset <= _T_168 @[exu.scala 166:47] - io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 168:47] - io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 169:47] - io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 170:47] - node _T_169 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 173:54] - node _T_170 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 173:97] - node _T_171 = and(_T_169, _T_170) @[exu.scala 173:95] - i0_valid_d <= _T_171 @[exu.scala 173:28] - node _T_172 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 174:59] - i0_taken_d <= _T_172 @[exu.scala 174:28] - node _T_173 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 180:8] - node _T_174 = and(_T_173, i0_valid_d) @[exu.scala 180:50] - node _T_175 = bits(_T_174, 0, 0) @[exu.scala 180:64] - node _T_176 = bits(ghr_d, 6, 0) @[exu.scala 180:85] + i_div.io.dec_div.dec_div_cancel <= io.dec_exu.dec_div.dec_div_cancel @[exu.scala 158:20] + i_div.io.dec_div.div_p.bits.rem <= io.dec_exu.dec_div.div_p.bits.rem @[exu.scala 158:20] + i_div.io.dec_div.div_p.bits.unsign <= io.dec_exu.dec_div.div_p.bits.unsign @[exu.scala 158:20] + i_div.io.dec_div.div_p.valid <= io.dec_exu.dec_div.div_p.valid @[exu.scala 158:20] + i_div.io.scan_mode <= io.scan_mode @[exu.scala 159:25] + i_div.io.dividend <= muldiv_rs1_d @[exu.scala 160:33] + i_div.io.divisor <= i0_rs2_d @[exu.scala 161:33] + io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 162:41] + io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 163:33] + node _T_166 = bits(mul_valid_x, 0, 0) @[exu.scala 165:76] + node _T_167 = mux(_T_166, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 165:63] + io.dec_exu.decode_exu.exu_i0_result_x <= _T_167 @[exu.scala 165:57] + i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 166:47] + i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 166:47] + i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 166:47] + i0_predict_newp_d.bits.pja <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[exu.scala 166:47] + i0_predict_newp_d.bits.pcall <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[exu.scala 166:47] + i0_predict_newp_d.bits.br_start_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[exu.scala 166:47] + i0_predict_newp_d.bits.br_error <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[exu.scala 166:47] + i0_predict_newp_d.bits.toffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[exu.scala 166:47] + i0_predict_newp_d.bits.hist <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[exu.scala 166:47] + i0_predict_newp_d.bits.pc4 <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[exu.scala 166:47] + i0_predict_newp_d.bits.boffset <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[exu.scala 166:47] + i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 166:47] + i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 166:47] + i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 166:47] + node _T_168 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 167:80] + i0_predict_newp_d.bits.boffset <= _T_168 @[exu.scala 167:47] + io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 169:47] + io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 170:47] + io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 171:47] + node _T_169 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 174:54] + node _T_170 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 174:97] + node _T_171 = and(_T_169, _T_170) @[exu.scala 174:95] + i0_valid_d <= _T_171 @[exu.scala 174:28] + node _T_172 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 175:59] + i0_taken_d <= _T_172 @[exu.scala 175:28] + node _T_173 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 181:8] + node _T_174 = and(_T_173, i0_valid_d) @[exu.scala 181:50] + node _T_175 = bits(_T_174, 0, 0) @[exu.scala 181:64] + node _T_176 = bits(ghr_d, 6, 0) @[exu.scala 181:85] node _T_177 = cat(_T_176, i0_taken_d) @[Cat.scala 29:58] - node _T_178 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 181:8] - node _T_179 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 181:52] - node _T_180 = and(_T_178, _T_179) @[exu.scala 181:50] - node _T_181 = bits(_T_180, 0, 0) @[exu.scala 181:65] - node _T_182 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 182:50] + node _T_178 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 182:8] + node _T_179 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 182:52] + node _T_180 = and(_T_178, _T_179) @[exu.scala 182:50] + node _T_181 = bits(_T_180, 0, 0) @[exu.scala 182:65] + node _T_182 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 183:50] node _T_183 = mux(_T_175, _T_177, UInt<1>("h00")) @[Mux.scala 27:72] node _T_184 = mux(_T_181, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_185 = mux(_T_182, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -45136,97 +45136,97 @@ circuit exu : node _T_187 = or(_T_186, _T_185) @[Mux.scala 27:72] wire _T_188 : UInt @[Mux.scala 27:72] _T_188 <= _T_187 @[Mux.scala 27:72] - ghr_d_ns <= _T_188 @[exu.scala 179:14] - node _T_189 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 186:32] - node _T_190 = bits(ghr_x, 6, 0) @[exu.scala 186:50] + ghr_d_ns <= _T_188 @[exu.scala 180:14] + node _T_189 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 187:32] + node _T_190 = bits(ghr_x, 6, 0) @[exu.scala 187:50] node _T_191 = cat(_T_190, i0_taken_x) @[Cat.scala 29:58] - node _T_192 = mux(_T_189, _T_191, ghr_x) @[exu.scala 186:20] - ghr_x_ns <= _T_192 @[exu.scala 186:14] - io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 188:43] - io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 189:43] - io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 190:43] + node _T_192 = mux(_T_189, _T_191, ghr_x) @[exu.scala 187:20] + ghr_x_ns <= _T_192 @[exu.scala 187:14] + io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 189:43] + io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 190:43] + io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 191:43] node _T_193 = bits(i0_pp_r.valid, 0, 0) @[Bitwise.scala 72:15] node _T_194 = mux(_T_193, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_195 = and(_T_194, i0_pp_r.bits.hist) @[exu.scala 191:69] - io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_195 @[exu.scala 191:43] - io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 192:43] - node _T_196 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 193:63] - io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_196 @[exu.scala 193:43] - io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 194:48] - node _T_197 = bits(predpipe_r, 20, 13) @[exu.scala 195:56] - io.exu_bp.exu_i0_br_fghr_r <= _T_197 @[exu.scala 195:43] - node _T_198 = bits(predpipe_r, 12, 5) @[exu.scala 196:56] - io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_198 @[exu.scala 196:43] - io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 197:43] - node _T_199 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 198:67] - wire _T_200 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 198:104] - _T_200.bits.prett <= UInt<31>("h00") @[exu.scala 198:104] - _T_200.bits.pret <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.way <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.pja <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.pcall <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.br_start_error <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.br_error <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.toffset <= UInt<12>("h00") @[exu.scala 198:104] - _T_200.bits.hist <= UInt<2>("h00") @[exu.scala 198:104] - _T_200.bits.pc4 <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.boffset <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.ataken <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.bits.misp <= UInt<1>("h00") @[exu.scala 198:104] - _T_200.valid <= UInt<1>("h00") @[exu.scala 198:104] - node _T_201 = mux(_T_199, i0_predict_p_x, _T_200) @[exu.scala 198:49] - final_predict_mp.bits.prett <= _T_201.bits.prett @[exu.scala 198:43] - final_predict_mp.bits.pret <= _T_201.bits.pret @[exu.scala 198:43] - final_predict_mp.bits.way <= _T_201.bits.way @[exu.scala 198:43] - final_predict_mp.bits.pja <= _T_201.bits.pja @[exu.scala 198:43] - final_predict_mp.bits.pcall <= _T_201.bits.pcall @[exu.scala 198:43] - final_predict_mp.bits.br_start_error <= _T_201.bits.br_start_error @[exu.scala 198:43] - final_predict_mp.bits.br_error <= _T_201.bits.br_error @[exu.scala 198:43] - final_predict_mp.bits.toffset <= _T_201.bits.toffset @[exu.scala 198:43] - final_predict_mp.bits.hist <= _T_201.bits.hist @[exu.scala 198:43] - final_predict_mp.bits.pc4 <= _T_201.bits.pc4 @[exu.scala 198:43] - final_predict_mp.bits.boffset <= _T_201.bits.boffset @[exu.scala 198:43] - final_predict_mp.bits.ataken <= _T_201.bits.ataken @[exu.scala 198:43] - final_predict_mp.bits.misp <= _T_201.bits.misp @[exu.scala 198:43] - final_predict_mp.valid <= _T_201.valid @[exu.scala 198:43] - node _T_202 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:66] - node final_predpipe_mp = mux(_T_202, predpipe_x, UInt<1>("h00")) @[exu.scala 199:48] - node _T_203 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 201:67] - node _T_204 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 201:120] - node _T_205 = eq(_T_204, UInt<1>("h00")) @[exu.scala 201:77] - node _T_206 = and(_T_203, _T_205) @[exu.scala 201:75] - node after_flush_eghr = mux(_T_206, ghr_d, ghr_x) @[exu.scala 201:48] - io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 203:39] - io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 204:39] - io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 205:39] - io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 206:39] - io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 207:39] - io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 208:39] - io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 209:39] - io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 210:39] - io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 211:39] - node _T_207 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 212:68] - io.exu_bp.exu_mp_pkt.bits.hist <= _T_207 @[exu.scala 212:39] - node _T_208 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 213:71] - io.exu_bp.exu_mp_pkt.bits.toffset <= _T_208 @[exu.scala 213:39] - io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 214:39] - node _T_209 = bits(final_predpipe_mp, 12, 5) @[exu.scala 215:59] - io.exu_bp.exu_mp_index <= _T_209 @[exu.scala 215:39] - node _T_210 = bits(final_predpipe_mp, 4, 0) @[exu.scala 216:59] - io.exu_bp.exu_mp_btag <= _T_210 @[exu.scala 216:39] - node _T_211 = bits(final_predpipe_mp, 20, 13) @[exu.scala 217:59] - io.exu_bp.exu_mp_eghr <= _T_211 @[exu.scala 217:39] - node _T_212 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 239:46] - node _T_213 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 240:6] - node _T_214 = and(_T_213, i0_flush_upper_d) @[exu.scala 240:48] - node _T_215 = bits(_T_214, 0, 0) @[exu.scala 240:68] + node _T_195 = and(_T_194, i0_pp_r.bits.hist) @[exu.scala 192:69] + io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_195 @[exu.scala 192:43] + io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 193:43] + node _T_196 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 194:63] + io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_196 @[exu.scala 194:43] + io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 195:48] + node _T_197 = bits(predpipe_r, 20, 13) @[exu.scala 196:56] + io.exu_bp.exu_i0_br_fghr_r <= _T_197 @[exu.scala 196:43] + node _T_198 = bits(predpipe_r, 12, 5) @[exu.scala 197:56] + io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_198 @[exu.scala 197:43] + io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 198:43] + node _T_199 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:67] + wire _T_200 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 199:104] + _T_200.bits.prett <= UInt<31>("h00") @[exu.scala 199:104] + _T_200.bits.pret <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.way <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.pja <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.pcall <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.br_start_error <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.br_error <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.toffset <= UInt<12>("h00") @[exu.scala 199:104] + _T_200.bits.hist <= UInt<2>("h00") @[exu.scala 199:104] + _T_200.bits.pc4 <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.boffset <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.ataken <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.bits.misp <= UInt<1>("h00") @[exu.scala 199:104] + _T_200.valid <= UInt<1>("h00") @[exu.scala 199:104] + node _T_201 = mux(_T_199, i0_predict_p_x, _T_200) @[exu.scala 199:49] + final_predict_mp.bits.prett <= _T_201.bits.prett @[exu.scala 199:43] + final_predict_mp.bits.pret <= _T_201.bits.pret @[exu.scala 199:43] + final_predict_mp.bits.way <= _T_201.bits.way @[exu.scala 199:43] + final_predict_mp.bits.pja <= _T_201.bits.pja @[exu.scala 199:43] + final_predict_mp.bits.pcall <= _T_201.bits.pcall @[exu.scala 199:43] + final_predict_mp.bits.br_start_error <= _T_201.bits.br_start_error @[exu.scala 199:43] + final_predict_mp.bits.br_error <= _T_201.bits.br_error @[exu.scala 199:43] + final_predict_mp.bits.toffset <= _T_201.bits.toffset @[exu.scala 199:43] + final_predict_mp.bits.hist <= _T_201.bits.hist @[exu.scala 199:43] + final_predict_mp.bits.pc4 <= _T_201.bits.pc4 @[exu.scala 199:43] + final_predict_mp.bits.boffset <= _T_201.bits.boffset @[exu.scala 199:43] + final_predict_mp.bits.ataken <= _T_201.bits.ataken @[exu.scala 199:43] + final_predict_mp.bits.misp <= _T_201.bits.misp @[exu.scala 199:43] + final_predict_mp.valid <= _T_201.valid @[exu.scala 199:43] + node _T_202 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 200:66] + node final_predpipe_mp = mux(_T_202, predpipe_x, UInt<1>("h00")) @[exu.scala 200:48] + node _T_203 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 202:67] + node _T_204 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 202:120] + node _T_205 = eq(_T_204, UInt<1>("h00")) @[exu.scala 202:77] + node _T_206 = and(_T_203, _T_205) @[exu.scala 202:75] + node after_flush_eghr = mux(_T_206, ghr_d, ghr_x) @[exu.scala 202:48] + io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 204:39] + io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 205:39] + io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 206:39] + io.exu_bp.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[exu.scala 207:39] + io.exu_bp.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[exu.scala 208:39] + io.exu_bp.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[exu.scala 209:39] + io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 210:39] + io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 211:39] + io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 212:39] + node _T_207 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 213:68] + io.exu_bp.exu_mp_pkt.bits.hist <= _T_207 @[exu.scala 213:39] + node _T_208 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 214:71] + io.exu_bp.exu_mp_pkt.bits.toffset <= _T_208 @[exu.scala 214:39] + io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 215:39] + node _T_209 = bits(final_predpipe_mp, 12, 5) @[exu.scala 216:59] + io.exu_bp.exu_mp_index <= _T_209 @[exu.scala 216:39] + node _T_210 = bits(final_predpipe_mp, 4, 0) @[exu.scala 217:59] + io.exu_bp.exu_mp_btag <= _T_210 @[exu.scala 217:39] + node _T_211 = bits(final_predpipe_mp, 20, 13) @[exu.scala 218:59] + io.exu_bp.exu_mp_eghr <= _T_211 @[exu.scala 218:39] + node _T_212 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 240:46] + node _T_213 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 241:6] + node _T_214 = and(_T_213, i0_flush_upper_d) @[exu.scala 241:48] + node _T_215 = bits(_T_214, 0, 0) @[exu.scala 241:68] node _T_216 = mux(_T_212, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_217 = mux(_T_215, i0_flush_path_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72] wire _T_219 : UInt<31> @[Mux.scala 27:72] _T_219 <= _T_218 @[Mux.scala 27:72] - io.exu_flush_path_final <= _T_219 @[exu.scala 238:33] - node _T_220 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 242:79] - node _T_221 = mux(_T_220, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 242:55] - io.dec_exu.tlu_exu.exu_npc_r <= _T_221 @[exu.scala 242:49] + io.exu_flush_path_final <= _T_219 @[exu.scala 239:33] + node _T_220 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 243:79] + node _T_221 = mux(_T_220, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 243:55] + io.dec_exu.tlu_exu.exu_npc_r <= _T_221 @[exu.scala 243:49] diff --git a/exu.v b/exu.v index 4662915c..aef37fe1 100644 --- a/exu.v +++ b/exu.v @@ -21,9 +21,9 @@ module exu_alu_ctl( input reset, input io_dec_alu_dec_i0_alu_decode_d, input io_dec_alu_dec_csr_ren_d, - input [31:0] io_dec_alu_dec_csr_rddata_d, input [11:0] io_dec_alu_dec_i0_br_immed_d, output [30:0] io_dec_alu_exu_i0_pc_x, + input [31:0] io_csr_rddata_in, input [30:0] io_dec_i0_pc_d, input io_flush_upper_x, input io_dec_tlu_flush_lower_r, @@ -116,7 +116,7 @@ module exu_alu_ctl( reg [30:0] _T_14; // @[Reg.scala 27:20] wire _T_15 = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[exu_alu_ctl.scala 135:43] reg [31:0] _T_18; // @[Reg.scala 27:20] - wire [31:0] _T_153 = io_dec_alu_dec_csr_rddata_d; // @[Mux.scala 27:72] + wire [31:0] _T_153 = io_csr_rddata_in; // @[Mux.scala 27:72] wire [32:0] _T_151 = {{1{_T_153[31]}},_T_153}; // @[Mux.scala 27:72 Mux.scala 27:72] wire [32:0] _T_172 = io_dec_alu_dec_csr_ren_d ? $signed(_T_151) : $signed(33'sh0); // @[Mux.scala 27:72] wire _T_94 = ~io_i0_ap_zbb; // @[exu_alu_ctl.scala 160:22] @@ -1952,7 +1952,6 @@ module exu( input io_scan_mode, input io_dec_exu_dec_alu_dec_i0_alu_decode_d, input io_dec_exu_dec_alu_dec_csr_ren_d, - input [31:0] io_dec_exu_dec_alu_dec_csr_rddata_d, input [11:0] io_dec_exu_dec_alu_dec_i0_br_immed_d, output [30:0] io_dec_exu_dec_alu_exu_i0_pc_x, input io_dec_exu_dec_div_div_p_valid, @@ -2027,6 +2026,7 @@ module exu( input io_dec_exu_decode_exu_dec_i0_rs2_en_d, input [31:0] io_dec_exu_decode_exu_dec_i0_immed_d, input [31:0] io_dec_exu_decode_exu_dec_i0_result_r, + input io_dec_exu_decode_exu_dec_qual_lsu_d, input io_dec_exu_decode_exu_dec_i0_select_pc_d, input [3:0] io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d, input [3:0] io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d, @@ -2097,12 +2097,12 @@ module exu( output [31:0] io_exu_div_result, output io_exu_div_wren, input [31:0] io_dbg_cmd_wrdata, + input [31:0] io_dec_csr_rddata_d, output [31:0] io_lsu_exu_exu_lsu_rs1_d, output [31:0] io_lsu_exu_exu_lsu_rs2_d, input [31:0] io_lsu_exu_lsu_result_m, input [31:0] io_lsu_exu_lsu_nonblock_load_data, - output [30:0] io_exu_flush_path_final, - input io_dec_qual_lsu_d + output [30:0] io_exu_flush_path_final ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -2160,117 +2160,117 @@ module exu( wire rvclkhdr_6_io_en; // @[lib.scala 404:23] wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] wire rvclkhdr_7_io_en; // @[lib.scala 404:23] - wire i_alu_clock; // @[exu.scala 130:19] - wire i_alu_reset; // @[exu.scala 130:19] - wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:19] - wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 130:19] - wire [31:0] i_alu_io_dec_alu_dec_csr_rddata_d; // @[exu.scala 130:19] - wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:19] - wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:19] - wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 130:19] - wire i_alu_io_flush_upper_x; // @[exu.scala 130:19] - wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 130:19] - wire i_alu_io_enable; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_clz; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_ctz; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_pcnt; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sext_b; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sext_h; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_min; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_max; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_pack; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_packu; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_packh; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_rol; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_ror; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_grev; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_gorc; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_zbb; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sbset; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sbclr; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sbinv; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sbext; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_land; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_lor; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_lxor; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sll; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_srl; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sra; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_beq; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_bne; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_blt; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_bge; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_add; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_sub; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_slt; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_unsign; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_jal; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_predict_t; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_csr_write; // @[exu.scala 130:19] - wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 130:19] - wire [31:0] i_alu_io_a_in; // @[exu.scala 130:19] - wire [31:0] i_alu_io_b_in; // @[exu.scala 130:19] - wire i_alu_io_pp_in_valid; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 130:19] - wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 130:19] - wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_pja; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_way; // @[exu.scala 130:19] - wire i_alu_io_pp_in_bits_pret; // @[exu.scala 130:19] - wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 130:19] - wire [31:0] i_alu_io_result_ff; // @[exu.scala 130:19] - wire i_alu_io_flush_upper_out; // @[exu.scala 130:19] - wire i_alu_io_flush_final_out; // @[exu.scala 130:19] - wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 130:19] - wire i_alu_io_pred_correct_out; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_valid; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 130:19] - wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 130:19] - wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 130:19] - wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 130:19] - wire i_mul_clock; // @[exu.scala 148:21] - wire i_mul_reset; // @[exu.scala 148:21] - wire i_mul_io_mul_p_valid; // @[exu.scala 148:21] - wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 148:21] - wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 148:21] - wire i_mul_io_mul_p_bits_low; // @[exu.scala 148:21] - wire [31:0] i_mul_io_rs1_in; // @[exu.scala 148:21] - wire [31:0] i_mul_io_rs2_in; // @[exu.scala 148:21] - wire [31:0] i_mul_io_result_x; // @[exu.scala 148:21] - wire i_div_clock; // @[exu.scala 156:21] - wire i_div_reset; // @[exu.scala 156:21] - wire [31:0] i_div_io_dividend; // @[exu.scala 156:21] - wire [31:0] i_div_io_divisor; // @[exu.scala 156:21] - wire [31:0] i_div_io_exu_div_result; // @[exu.scala 156:21] - wire i_div_io_exu_div_wren; // @[exu.scala 156:21] - wire i_div_io_dec_div_div_p_valid; // @[exu.scala 156:21] - wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 156:21] - wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 156:21] - wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 156:21] - wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 55:69] - wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 56:73] - wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 57:73] - wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 58:69] + wire i_alu_clock; // @[exu.scala 129:19] + wire i_alu_reset; // @[exu.scala 129:19] + wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 129:19] + wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 129:19] + wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 129:19] + wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 129:19] + wire [31:0] i_alu_io_csr_rddata_in; // @[exu.scala 129:19] + wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 129:19] + wire i_alu_io_flush_upper_x; // @[exu.scala 129:19] + wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 129:19] + wire i_alu_io_enable; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_clz; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_ctz; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_pcnt; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sext_b; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sext_h; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_min; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_max; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_pack; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_packu; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_packh; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_rol; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_ror; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_grev; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_gorc; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_zbb; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sbset; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sbclr; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sbinv; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sbext; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_land; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_lor; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_lxor; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sll; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_srl; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sra; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_beq; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_bne; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_blt; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_bge; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_add; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_sub; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_slt; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_unsign; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_jal; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_predict_t; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_csr_write; // @[exu.scala 129:19] + wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 129:19] + wire [31:0] i_alu_io_a_in; // @[exu.scala 129:19] + wire [31:0] i_alu_io_b_in; // @[exu.scala 129:19] + wire i_alu_io_pp_in_valid; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 129:19] + wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 129:19] + wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_pja; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_way; // @[exu.scala 129:19] + wire i_alu_io_pp_in_bits_pret; // @[exu.scala 129:19] + wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 129:19] + wire [31:0] i_alu_io_result_ff; // @[exu.scala 129:19] + wire i_alu_io_flush_upper_out; // @[exu.scala 129:19] + wire i_alu_io_flush_final_out; // @[exu.scala 129:19] + wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 129:19] + wire i_alu_io_pred_correct_out; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_valid; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 129:19] + wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 129:19] + wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 129:19] + wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 129:19] + wire i_mul_clock; // @[exu.scala 149:21] + wire i_mul_reset; // @[exu.scala 149:21] + wire i_mul_io_mul_p_valid; // @[exu.scala 149:21] + wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 149:21] + wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 149:21] + wire i_mul_io_mul_p_bits_low; // @[exu.scala 149:21] + wire [31:0] i_mul_io_rs1_in; // @[exu.scala 149:21] + wire [31:0] i_mul_io_rs2_in; // @[exu.scala 149:21] + wire [31:0] i_mul_io_result_x; // @[exu.scala 149:21] + wire i_div_clock; // @[exu.scala 157:21] + wire i_div_reset; // @[exu.scala 157:21] + wire [31:0] i_div_io_dividend; // @[exu.scala 157:21] + wire [31:0] i_div_io_divisor; // @[exu.scala 157:21] + wire [31:0] i_div_io_exu_div_result; // @[exu.scala 157:21] + wire i_div_io_exu_div_wren; // @[exu.scala 157:21] + wire i_div_io_dec_div_div_p_valid; // @[exu.scala 157:21] + wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 157:21] + wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 157:21] + wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 157:21] + wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 54:69] + wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 55:73] + wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 56:73] + wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 57:69] reg i0_branch_x; // @[Reg.scala 27:20] - wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 59:73] - wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 60:68] - wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 61:68] + wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 58:73] + wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 59:68] + wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 60:68] wire [20:0] predpipe_d = {io_dec_exu_decode_exu_i0_predict_fghr_d,io_dec_exu_decode_exu_i0_predict_index_d,io_dec_exu_decode_exu_i0_predict_btag_d}; // @[Cat.scala 29:58] reg [30:0] i0_flush_path_x; // @[Reg.scala 27:20] - wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 41:53 exu.scala 143:45] + wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 40:53 exu.scala 144:45] reg i0_predict_p_x_valid; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_misp; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_ataken; // @[Reg.scala 27:20] @@ -2284,19 +2284,19 @@ module exu( reg i0_predict_p_x_bits_pja; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_way; // @[Reg.scala 27:20] reg i0_predict_p_x_bits_pret; // @[Reg.scala 27:20] - wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 42:53 exu.scala 145:45] - wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 42:53 exu.scala 145:45] - wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 42:53 exu.scala 145:45] - wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 42:53 exu.scala 145:45] + wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 41:53 exu.scala 146:45] + wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 41:53 exu.scala 146:45] + wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 41:53 exu.scala 146:45] + wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 41:53 exu.scala 146:45] reg [20:0] predpipe_x; // @[Reg.scala 27:20] reg [20:0] predpipe_r; // @[Reg.scala 27:20] reg [7:0] ghr_x; // @[Reg.scala 27:20] @@ -2304,13 +2304,13 @@ module exu( reg i0_taken_x; // @[Reg.scala 27:20] wire [7:0] _T_191 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58] reg i0_pred_correct_upper_x; // @[Reg.scala 27:20] - wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 47:41 exu.scala 146:27] + wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 46:41 exu.scala 147:27] reg i0_flush_upper_x; // @[Reg.scala 27:20] - wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 48:45 exu.scala 142:35] - wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 174:59] - wire _T_169 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 173:54] - wire _T_170 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 173:97] - wire i0_valid_d = _T_169 & _T_170; // @[exu.scala 173:95] + wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 47:45 exu.scala 143:35] + wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 175:59] + wire _T_169 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 174:54] + wire _T_170 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 174:97] + wire i0_valid_d = _T_169 & _T_170; // @[exu.scala 174:95] reg i0_pp_r_valid; // @[Reg.scala 27:20] reg i0_pp_r_bits_misp; // @[Reg.scala 27:20] reg i0_pp_r_bits_ataken; // @[Reg.scala 27:20] @@ -2325,12 +2325,12 @@ module exu( reg [30:0] i0_flush_path_upper_r; // @[Reg.scala 27:20] reg [24:0] pred_temp2; // @[Reg.scala 27:20] wire [30:0] _T_31 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58] - wire _T_174 = _T_170 & i0_valid_d; // @[exu.scala 180:50] + wire _T_174 = _T_170 & i0_valid_d; // @[exu.scala 181:50] reg [7:0] ghr_d; // @[Reg.scala 27:20] wire [7:0] _T_177 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58] wire [7:0] _T_183 = _T_174 ? _T_177 : 8'h0; // @[Mux.scala 27:72] - wire _T_179 = ~i0_valid_d; // @[exu.scala 181:52] - wire _T_180 = _T_170 & _T_179; // @[exu.scala 181:50] + wire _T_179 = ~i0_valid_d; // @[exu.scala 182:52] + wire _T_180 = _T_170 & _T_179; // @[exu.scala 182:50] wire [7:0] _T_184 = _T_180 ? ghr_d : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_186 = _T_183 | _T_184; // @[Mux.scala 27:72] wire [7:0] _T_185 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] @@ -2342,12 +2342,12 @@ module exu( wire _T_38 = |_T_37; // @[lib.scala 470:29] wire _T_41 = io_dec_exu_decode_exu_dec_i0_branch_d ^ i0_branch_x; // @[lib.scala 448:21] wire _T_42 = |_T_41; // @[lib.scala 448:29] - wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 83:84] - wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 83:134] - wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 83:184] - wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 84:84] - wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 84:134] - wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 84:184] + wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 82:84] + wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 82:134] + wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 82:184] + wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 83:84] + wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 83:134] + wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 83:184] wire [31:0] _T_64 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] ? io_dec_exu_decode_exu_dec_i0_result_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_65 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1] ? io_lsu_exu_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_66 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2] ? io_dec_exu_decode_exu_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] @@ -2362,13 +2362,13 @@ module exu( wire [31:0] _T_83 = _T_79 | _T_80; // @[Mux.scala 27:72] wire [31:0] _T_84 = _T_83 | _T_81; // @[Mux.scala 27:72] wire [31:0] i0_rs2_bypass_data_d = _T_84 | _T_82; // @[Mux.scala 27:72] - wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 101:6] - wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 101:26] + wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 100:6] + wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 100:26] wire [31:0] _T_90 = {io_dec_exu_ib_exu_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58] - wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:26] - wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 103:28] - wire _T_96 = _T_87 & _T_95; // @[exu.scala 103:26] - wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 103:69] + wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 101:26] + wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:28] + wire _T_96 = _T_87 & _T_95; // @[exu.scala 102:26] + wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 102:69] wire [31:0] _T_99 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_100 = _T_88 ? _T_90 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_101 = _T_92 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72] @@ -2377,45 +2377,45 @@ module exu( wire [31:0] _T_104 = _T_103 | _T_101; // @[Mux.scala 27:72] wire [31:0] i0_rs1_d = _T_104 | _T_102; // @[Mux.scala 27:72] reg [31:0] _T_107; // @[Reg.scala 27:20] - wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 108:6] - wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 108:26] + wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 107:6] + wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 107:26] wire [31:0] _T_114 = _T_109 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_115 = _T_108 ? io_dec_exu_decode_exu_dec_i0_immed_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_116 = i0_rs2_bypass_en_d ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_117 = _T_114 | _T_115; // @[Mux.scala 27:72] wire [31:0] _T_118 = _T_117 | _T_116; // @[Mux.scala 27:72] - wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 115:28] - wire _T_121 = _T_87 & _T_120; // @[exu.scala 115:26] - wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 115:68] - wire _T_123 = _T_122 & io_dec_qual_lsu_d; // @[exu.scala 115:108] - wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 116:25] - wire _T_127 = _T_126 & io_dec_qual_lsu_d; // @[exu.scala 116:67] - wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_qual_lsu_d; // @[exu.scala 117:45] + wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 114:28] + wire _T_121 = _T_87 & _T_120; // @[exu.scala 114:26] + wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 114:68] + wire _T_123 = _T_122 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 114:108] + wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 115:25] + wire _T_127 = _T_126 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 115:67] + wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 116:45] wire [31:0] _T_131 = {io_dec_exu_tlu_exu_dec_tlu_meihap,2'h0}; // @[Cat.scala 29:58] wire [31:0] _T_132 = _T_123 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_133 = _T_127 ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_134 = _T_129 ? _T_131 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_135 = _T_132 | _T_133; // @[Mux.scala 27:72] - wire _T_140 = _T_108 & _T_120; // @[exu.scala 121:26] - wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 121:68] - wire _T_142 = _T_141 & io_dec_qual_lsu_d; // @[exu.scala 121:108] - wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 122:25] - wire _T_146 = _T_145 & io_dec_qual_lsu_d; // @[exu.scala 122:67] + wire _T_140 = _T_108 & _T_120; // @[exu.scala 120:26] + wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 120:68] + wire _T_142 = _T_141 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 120:108] + wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 121:25] + wire _T_146 = _T_145 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 121:67] wire [31:0] _T_148 = _T_142 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_149 = _T_146 ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] - wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 126:26] + wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 125:26] wire [31:0] _T_156 = _T_153 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] wire [31:0] muldiv_rs1_d = _T_156 | _T_99; // @[Mux.scala 27:72] wire [31:0] _T_161 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] i0_rs2_d = _T_118; // @[Mux.scala 27:72 Mux.scala 27:72] wire [1:0] _T_194 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 199:48] - wire _T_206 = i0_flush_upper_x & _T_170; // @[exu.scala 201:75] - wire _T_214 = _T_170 & i0_flush_upper_d; // @[exu.scala 240:48] + wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 200:48] + wire _T_206 = i0_flush_upper_x & _T_170; // @[exu.scala 202:75] + wire _T_214 = _T_170 & i0_flush_upper_d; // @[exu.scala 241:48] wire [30:0] _T_216 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_217 = _T_214 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72] - wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 46:51 exu.scala 78:45] - wire [31:0] _T_221 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 242:55] + wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 45:51 exu.scala 77:45] + wire [31:0] _T_221 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 243:55] rvclkhdr rvclkhdr ( // @[lib.scala 404:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) @@ -2448,14 +2448,14 @@ module exu( .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en) ); - exu_alu_ctl i_alu ( // @[exu.scala 130:19] + exu_alu_ctl i_alu ( // @[exu.scala 129:19] .clock(i_alu_clock), .reset(i_alu_reset), .io_dec_alu_dec_i0_alu_decode_d(i_alu_io_dec_alu_dec_i0_alu_decode_d), .io_dec_alu_dec_csr_ren_d(i_alu_io_dec_alu_dec_csr_ren_d), - .io_dec_alu_dec_csr_rddata_d(i_alu_io_dec_alu_dec_csr_rddata_d), .io_dec_alu_dec_i0_br_immed_d(i_alu_io_dec_alu_dec_i0_br_immed_d), .io_dec_alu_exu_i0_pc_x(i_alu_io_dec_alu_exu_i0_pc_x), + .io_csr_rddata_in(i_alu_io_csr_rddata_in), .io_dec_i0_pc_d(i_alu_io_dec_i0_pc_d), .io_flush_upper_x(i_alu_io_flush_upper_x), .io_dec_tlu_flush_lower_r(i_alu_io_dec_tlu_flush_lower_r), @@ -2531,7 +2531,7 @@ module exu( .io_predict_p_out_bits_way(i_alu_io_predict_p_out_bits_way), .io_predict_p_out_bits_pret(i_alu_io_predict_p_out_bits_pret) ); - exu_mul_ctl i_mul ( // @[exu.scala 148:21] + exu_mul_ctl i_mul ( // @[exu.scala 149:21] .clock(i_mul_clock), .reset(i_mul_reset), .io_mul_p_valid(i_mul_io_mul_p_valid), @@ -2542,7 +2542,7 @@ module exu( .io_rs2_in(i_mul_io_rs2_in), .io_result_x(i_mul_io_result_x) ); - exu_div_ctl i_div ( // @[exu.scala 156:21] + exu_div_ctl i_div ( // @[exu.scala 157:21] .clock(i_div_clock), .reset(i_div_reset), .io_dividend(i_div_io_dividend), @@ -2554,47 +2554,47 @@ module exu( .io_dec_div_div_p_bits_rem(i_div_io_dec_div_div_p_bits_rem), .io_dec_div_dec_div_cancel(i_div_io_dec_div_dec_div_cancel) ); - assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 131:20] - assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 164:57] - assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 105:57] - assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_194 & i0_pp_r_bits_hist; // @[exu.scala 191:43] - assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 192:43] - assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 194:48] - assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 196:43] - assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 188:43] - assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 189:43] - assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 193:43] - assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 168:47] - assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 169:47] - assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 170:47] - assign io_dec_exu_tlu_exu_exu_npc_r = _T_221[30:0]; // @[exu.scala 242:49] - assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 197:43] - assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 195:43] - assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 190:43] - assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 52:53 exu.scala 203:39] - assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 205:39] - assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 209:39] - assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 210:39] - assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 211:39] - assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 212:39] - assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 213:39] - assign io_exu_bp_exu_mp_pkt_bits_br_error = 1'h0; // @[exu.scala 51:39] - assign io_exu_bp_exu_mp_pkt_bits_br_start_error = 1'h0; // @[exu.scala 50:44] - assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 206:39] - assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 207:39] - assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 204:39] - assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 208:39] - assign io_exu_bp_exu_mp_pkt_bits_prett = 31'h0; // @[exu.scala 49:57] - assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 217:39] - assign io_exu_bp_exu_mp_fghr = _T_206 ? ghr_d : ghr_x; // @[exu.scala 214:39] - assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 215:39] - assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 216:39] - assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 144:27] - assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 162:33] - assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 161:41] - assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 114:27] - assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 120:27] - assign io_exu_flush_path_final = _T_216 | _T_217; // @[exu.scala 238:33] + assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:20] + assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 165:57] + assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 104:57] + assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_194 & i0_pp_r_bits_hist; // @[exu.scala 192:43] + assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 193:43] + assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 195:48] + assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 197:43] + assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 189:43] + assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 190:43] + assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 194:43] + assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 169:47] + assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 170:47] + assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 171:47] + assign io_dec_exu_tlu_exu_exu_npc_r = _T_221[30:0]; // @[exu.scala 243:49] + assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 198:43] + assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 196:43] + assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 191:43] + assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 51:53 exu.scala 204:39] + assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 206:39] + assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 210:39] + assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 211:39] + assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 212:39] + assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 213:39] + assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 214:39] + assign io_exu_bp_exu_mp_pkt_bits_br_error = 1'h0; // @[exu.scala 50:39] + assign io_exu_bp_exu_mp_pkt_bits_br_start_error = 1'h0; // @[exu.scala 49:44] + assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 207:39] + assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 208:39] + assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 205:39] + assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 209:39] + assign io_exu_bp_exu_mp_pkt_bits_prett = 31'h0; // @[exu.scala 48:57] + assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 218:39] + assign io_exu_bp_exu_mp_fghr = _T_206 ? ghr_d : ghr_x; // @[exu.scala 215:39] + assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 216:39] + assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 217:39] + assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 145:27] + assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 163:33] + assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 162:41] + assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 113:27] + assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 119:27] + assign io_exu_flush_path_final = _T_216 | _T_217; // @[exu.scala 239:33] assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_io_en = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[lib.scala 407:17] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] @@ -2613,54 +2613,54 @@ module exu( assign rvclkhdr_7_io_en = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[lib.scala 407:17] assign i_alu_clock = clock; assign i_alu_reset = reset; - assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 131:20] - assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 131:20] - assign i_alu_io_dec_alu_dec_csr_rddata_d = io_dec_exu_dec_alu_dec_csr_rddata_d; // @[exu.scala 131:20] - assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 131:20] - assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 139:33] + assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:20] + assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 130:20] + assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:20] + assign i_alu_io_csr_rddata_in = io_dec_csr_rddata_d; // @[exu.scala 136:33] + assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 140:33] assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[exu.scala 135:33] - assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 136:41] + assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 137:41] assign i_alu_io_enable = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 133:45] - assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 140:51] - assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 140:51] - assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 137:39] - assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 138:39] + assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 141:51] + assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 141:51] + assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 138:39] + assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 139:39] assign i_alu_io_pp_in_valid = io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[exu.scala 134:45] assign i_alu_io_pp_in_bits_boffset = io_dec_exu_ib_exu_dec_i0_pc_d[0]; // @[exu.scala 134:45] assign i_alu_io_pp_in_bits_pc4 = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[exu.scala 134:45] @@ -2675,20 +2675,20 @@ module exu( assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 134:45] assign i_mul_clock = clock; assign i_mul_reset = reset; - assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 150:23] - assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 150:23] - assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 150:23] - assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 150:23] - assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 152:41] - assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 153:41] + assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 151:23] + assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 151:23] + assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 151:23] + assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 151:23] + assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 153:41] + assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 154:41] assign i_div_clock = clock; assign i_div_reset = reset; - assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 159:33] - assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 160:33] - assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 157:20] - assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 157:20] - assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 157:20] - assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 157:20] + assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 160:33] + assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 161:33] + assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 158:20] + assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 158:20] + assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 158:20] + assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 158:20] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif diff --git a/lsu.anno.json b/lsu.anno.json new file mode 100644 index 00000000..7e37459a --- /dev/null +++ b/lsu.anno.json @@ -0,0 +1,547 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn", + "sources":[ + "~lsu|lsu>io_axi_ar_ready", + "~lsu|lsu>io_axi_aw_ready", + "~lsu|lsu>io_axi_w_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_mken", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_single_ecc_error_incr", + "sources":[ + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dma_dccm_ready", + "sources":[ + "~lsu|lsu>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_trigger_match_m", + "sources":[ + "~lsu|lsu>io_trigger_pkt_any_0_store", + "~lsu|lsu>io_trigger_pkt_any_1_store", + "~lsu|lsu>io_trigger_pkt_any_3_m", + "~lsu|lsu>io_trigger_pkt_any_0_load", + "~lsu|lsu>io_trigger_pkt_any_0_select", + "~lsu|lsu>io_trigger_pkt_any_3_store", + "~lsu|lsu>io_trigger_pkt_any_2_store", + "~lsu|lsu>io_trigger_pkt_any_1_load", + "~lsu|lsu>io_trigger_pkt_any_1_select", + "~lsu|lsu>io_trigger_pkt_any_2_m", + "~lsu|lsu>io_trigger_pkt_any_3_load", + "~lsu|lsu>io_trigger_pkt_any_3_select", + "~lsu|lsu>io_trigger_pkt_any_2_load", + "~lsu|lsu>io_trigger_pkt_any_2_select", + "~lsu|lsu>io_trigger_pkt_any_0_m", + "~lsu|lsu>io_trigger_pkt_any_1_m", + "~lsu|lsu>io_trigger_pkt_any_0_tdata2", + "~lsu|lsu>io_trigger_pkt_any_0_match_pkt", + "~lsu|lsu>io_trigger_pkt_any_1_tdata2", + "~lsu|lsu>io_trigger_pkt_any_1_match_pkt", + "~lsu|lsu>io_trigger_pkt_any_3_tdata2", + "~lsu|lsu>io_trigger_pkt_any_3_match_pkt", + "~lsu|lsu>io_trigger_pkt_any_2_tdata2", + "~lsu|lsu>io_trigger_pkt_any_2_match_pkt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wren", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy", + "sources":[ + "~lsu|lsu>io_axi_ar_ready", + "~lsu|lsu>io_axi_aw_ready", + "~lsu|lsu>io_axi_w_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_data_hi", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_addr_lo", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_store_stall_any", + "sources":[ + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata", + "sources":[ + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_addr_hi", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_fastint_stall_any", + "sources":[ + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_exu_lsu_result_m", + "sources":[ + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_rd_addr_hi", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_data_lo", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned", + "sources":[ + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_wren", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error", + "sources":[ + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_rden", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r", + "sources":[ + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_load_stall_any", + "sources":[ + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_rden", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_rd_addr_lo", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_wr_data", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_wraddr", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_tlu_force_halt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "sources":[ + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_force_halt" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"lsu.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"lsu" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/lsu.fir b/lsu.fir new file mode 100644 index 00000000..31e690e4 --- /dev/null +++ b/lsu.fir @@ -0,0 +1,16090 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit lsu : + module lsu_addrcheck : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} + + node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 370:27] + node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 370:49] + wire start_addr_in_dccm_d : UInt<1> @[lib.scala 371:26] + node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 375:24] + node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 375:39] + start_addr_in_dccm_d <= _T_2 @[lib.scala 375:16] + node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 370:27] + node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 370:49] + wire end_addr_in_dccm_d : UInt<1> @[lib.scala 371:26] + node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 375:24] + node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 375:39] + end_addr_in_dccm_d <= _T_5 @[lib.scala 375:16] + wire addr_in_iccm : UInt<1> + addr_in_iccm <= UInt<1>("h00") + node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37] + node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45] + addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18] + node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89] + node _T_9 = bits(_T_8, 31, 28) @[lib.scala 370:27] + node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 370:49] + wire start_addr_in_pic_d : UInt<1> @[lib.scala 371:26] + node _T_10 = bits(_T_8, 31, 15) @[lib.scala 375:24] + node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 375:39] + start_addr_in_pic_d <= _T_11 @[lib.scala 375:16] + node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83] + node _T_13 = bits(_T_12, 31, 28) @[lib.scala 370:27] + node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 370:49] + wire end_addr_in_pic_d : UInt<1> @[lib.scala 371:26] + node _T_14 = bits(_T_12, 31, 15) @[lib.scala 375:24] + node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 375:39] + end_addr_in_pic_d <= _T_15 @[lib.scala 375:16] + node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60] + node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49] + node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55] + node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74] + node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109] + node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115] + node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91] + node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57] + io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32] + node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56] + io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32] + node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63] + node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33] + io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30] + node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51] + node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50] + node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50] + node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92] + node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62] + node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60] + node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137] + node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185] + node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158] + node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80] + node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56] + node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134] + node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138] + node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116] + node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90] + node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148] + node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58] + node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58] + node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58] + node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99] + node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33] + node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49] + node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56] + node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121] + node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88] + node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30] + node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49] + node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56] + node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121] + node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88] + node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30] + node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153] + node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49] + node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56] + node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121] + node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88] + node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30] + node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153] + node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49] + node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56] + node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121] + node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88] + node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30] + node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153] + node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49] + node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56] + node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121] + node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88] + node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30] + node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153] + node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49] + node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56] + node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121] + node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88] + node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30] + node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153] + node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49] + node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56] + node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121] + node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88] + node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30] + node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153] + node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49] + node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56] + node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121] + node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88] + node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30] + node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153] + node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48] + node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57] + node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122] + node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89] + node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31] + node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49] + node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58] + node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123] + node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90] + node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32] + node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154] + node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49] + node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58] + node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123] + node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90] + node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32] + node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155] + node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49] + node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58] + node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123] + node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90] + node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32] + node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155] + node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49] + node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58] + node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123] + node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90] + node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32] + node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155] + node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49] + node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58] + node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123] + node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90] + node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32] + node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155] + node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49] + node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58] + node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123] + node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90] + node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32] + node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155] + node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49] + node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58] + node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123] + node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90] + node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32] + node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155] + node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7] + node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104] + node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57] + node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70] + node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76] + node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92] + node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90] + node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51] + wire unmapped_access_fault_d : UInt<1> + unmapped_access_fault_d <= UInt<1>("h01") + wire mpu_access_fault_d : UInt<1> + mpu_access_fault_d <= UInt<1>("h01") + node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64] + node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62] + node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36] + node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34] + node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112] + node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29] + node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85] + node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29] + node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85] + unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29] + node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33] + node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64] + node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62] + mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29] + node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49] + node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70] + node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92] + node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118] + node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141] + node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139] + io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21] + node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60] + node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100] + node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144] + node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185] + node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164] + node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120] + node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80] + node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35] + node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53] + node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78] + node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61] + node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59] + node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57] + node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90] + node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57] + node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113] + node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136] + node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134] + io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25] + node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111] + node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80] + node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39] + node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50] + node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84] + node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113] + node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27] + io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21] + node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66] + node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64] + node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120] + node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118] + node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88] + node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142] + node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163] + io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31] + node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66] + node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36] + node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95] + node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116] + io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33] + reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60] + _T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60] + io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50] + + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_lsc_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} + + wire end_addr_pre_m : UInt<29> + end_addr_pre_m <= UInt<29>("h00") + wire end_addr_pre_r : UInt<29> + end_addr_pre_r <= UInt<29>("h00") + wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 93:29] + wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 94:29] + wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29] + wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 96:29] + wire _T : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 97:35] + _T.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + lsu_error_pkt_m.bits.addr <= _T.bits.addr @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.mscause <= _T.bits.mscause @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.exc_type <= _T.bits.exc_type @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.inst_type <= _T.bits.inst_type @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.single_ecc_error <= _T.bits.single_ecc_error @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.valid <= _T.valid @[lsu_lsc_ctl.scala 97:20] + node _T_1 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 99:52] + node lsu_rs1_d = mux(_T_1, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 99:28] + node _T_2 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 100:44] + node _T_3 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node lsu_offset_d = and(_T_2, _T_4) @[lsu_lsc_ctl.scala 100:51] + node _T_5 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 103:66] + node rs1_d = mux(_T_5, io.lsu_exu.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 103:28] + node _T_6 = bits(rs1_d, 11, 0) @[lib.scala 92:31] + node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58] + node _T_8 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60] + node _T_9 = cat(UInt<1>("h00"), _T_8) @[Cat.scala 29:58] + node _T_10 = add(_T_7, _T_9) @[lib.scala 92:39] + node _T_11 = tail(_T_10, 1) @[lib.scala 92:39] + node _T_12 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41] + node _T_13 = bits(_T_11, 12, 12) @[lib.scala 93:50] + node _T_14 = xor(_T_12, _T_13) @[lib.scala 93:46] + node _T_15 = not(_T_14) @[lib.scala 93:33] + node _T_16 = bits(_T_15, 0, 0) @[Bitwise.scala 72:15] + node _T_17 = mux(_T_16, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_18 = bits(rs1_d, 31, 12) @[lib.scala 93:63] + node _T_19 = and(_T_17, _T_18) @[lib.scala 93:58] + node _T_20 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25] + node _T_21 = not(_T_20) @[lib.scala 94:18] + node _T_22 = bits(_T_11, 12, 12) @[lib.scala 94:34] + node _T_23 = and(_T_21, _T_22) @[lib.scala 94:30] + node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15] + node _T_25 = mux(_T_24, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_26 = bits(rs1_d, 31, 12) @[lib.scala 94:47] + node _T_27 = add(_T_26, UInt<1>("h01")) @[lib.scala 94:54] + node _T_28 = tail(_T_27, 1) @[lib.scala 94:54] + node _T_29 = and(_T_25, _T_28) @[lib.scala 94:41] + node _T_30 = or(_T_19, _T_29) @[lib.scala 93:72] + node _T_31 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24] + node _T_32 = bits(_T_11, 12, 12) @[lib.scala 95:34] + node _T_33 = not(_T_32) @[lib.scala 95:31] + node _T_34 = and(_T_31, _T_33) @[lib.scala 95:29] + node _T_35 = bits(_T_34, 0, 0) @[Bitwise.scala 72:15] + node _T_36 = mux(_T_35, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_37 = bits(rs1_d, 31, 12) @[lib.scala 95:47] + node _T_38 = sub(_T_37, UInt<1>("h01")) @[lib.scala 95:54] + node _T_39 = tail(_T_38, 1) @[lib.scala 95:54] + node _T_40 = and(_T_36, _T_39) @[lib.scala 95:41] + node _T_41 = or(_T_30, _T_40) @[lib.scala 94:61] + node _T_42 = bits(_T_11, 11, 0) @[lib.scala 96:22] + node full_addr_d = cat(_T_41, _T_42) @[Cat.scala 29:58] + node _T_43 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_44 = mux(_T_43, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_45 = and(_T_44, UInt<3>("h01")) @[lsu_lsc_ctl.scala 108:58] + node _T_46 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_47 = mux(_T_46, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_48 = and(_T_47, UInt<3>("h03")) @[lsu_lsc_ctl.scala 109:40] + node _T_49 = or(_T_45, _T_48) @[lsu_lsc_ctl.scala 108:70] + node _T_50 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15] + node _T_51 = mux(_T_50, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_52 = and(_T_51, UInt<3>("h07")) @[lsu_lsc_ctl.scala 110:40] + node addr_offset_d = or(_T_49, _T_52) @[lsu_lsc_ctl.scala 109:52] + node _T_53 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 112:39] + node _T_54 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 112:52] + node _T_55 = cat(_T_53, _T_54) @[Cat.scala 29:58] + node _T_56 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_57 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 112:91] + node _T_58 = cat(_T_56, _T_57) @[Cat.scala 29:58] + node _T_59 = add(_T_55, _T_58) @[lsu_lsc_ctl.scala 112:60] + node end_addr_offset_d = tail(_T_59, 1) @[lsu_lsc_ctl.scala 112:60] + node _T_60 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 113:32] + node _T_61 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 113:70] + node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] + node _T_63 = mux(_T_62, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] + node _T_64 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 113:93] + node _T_65 = cat(_T_63, _T_64) @[Cat.scala 29:58] + node _T_66 = add(_T_60, _T_65) @[lsu_lsc_ctl.scala 113:39] + node full_end_addr_d = tail(_T_66, 1) @[lsu_lsc_ctl.scala 113:39] + io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 114:24] + inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 117:25] + addrcheck.clock <= clock + addrcheck.reset <= reset + addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 121:42] + addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 122:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 124:42] + node _T_67 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 125:50] + addrcheck.io.rs1_region_d <= _T_67 @[lsu_lsc_ctl.scala 125:42] + addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 126:42] + io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 127:42] + io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 128:42] + io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 129:42] + addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 136:42] + wire exc_mscause_r : UInt<4> + exc_mscause_r <= UInt<4>("h00") + wire fir_dccm_access_error_r : UInt<1> + fir_dccm_access_error_r <= UInt<1>("h00") + wire fir_nondccm_access_error_r : UInt<1> + fir_nondccm_access_error_r <= UInt<1>("h00") + wire access_fault_r : UInt<1> + access_fault_r <= UInt<1>("h00") + wire misaligned_fault_r : UInt<1> + misaligned_fault_r <= UInt<1>("h00") + wire lsu_fir_error_m : UInt<2> + lsu_fir_error_m <= UInt<2>("h00") + wire fir_dccm_access_error_m : UInt<1> + fir_dccm_access_error_m <= UInt<1>("h00") + wire fir_nondccm_access_error_m : UInt<1> + fir_nondccm_access_error_m <= UInt<1>("h00") + reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 148:75] + access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 148:75] + reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75] + misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 149:75] + reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75] + exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 150:75] + reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75] + _T_68 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 151:75] + fir_dccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 151:38] + reg _T_69 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75] + _T_69 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 152:75] + fir_nondccm_access_error_m <= _T_69 @[lsu_lsc_ctl.scala 152:38] + node _T_70 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 154:34] + io.lsu_exc_m <= _T_70 @[lsu_lsc_ctl.scala 154:16] + node _T_71 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 155:64] + node _T_72 = and(io.lsu_single_ecc_error_r, _T_71) @[lsu_lsc_ctl.scala 155:62] + node _T_73 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 155:111] + node _T_74 = and(_T_72, _T_73) @[lsu_lsc_ctl.scala 155:92] + node _T_75 = and(_T_74, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 155:136] + io.lsu_single_ecc_error_incr <= _T_75 @[lsu_lsc_ctl.scala 155:32] + node _T_76 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 177:46] + node _T_77 = or(_T_76, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 177:67] + node _T_78 = and(_T_77, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 177:96] + node _T_79 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:119] + node _T_80 = and(_T_78, _T_79) @[lsu_lsc_ctl.scala 177:117] + node _T_81 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:144] + node _T_82 = and(_T_80, _T_81) @[lsu_lsc_ctl.scala 177:142] + node _T_83 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:174] + node _T_84 = and(_T_82, _T_83) @[lsu_lsc_ctl.scala 177:172] + lsu_error_pkt_m.valid <= _T_84 @[lsu_lsc_ctl.scala 177:27] + node _T_85 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:75] + node _T_86 = and(io.lsu_single_ecc_error_m, _T_85) @[lsu_lsc_ctl.scala 178:73] + node _T_87 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:101] + node _T_88 = and(_T_86, _T_87) @[lsu_lsc_ctl.scala 178:99] + lsu_error_pkt_m.bits.single_ecc_error <= _T_88 @[lsu_lsc_ctl.scala 178:43] + lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 179:43] + node _T_89 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 180:46] + lsu_error_pkt_m.bits.exc_type <= _T_89 @[lsu_lsc_ctl.scala 180:43] + node _T_90 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:80] + node _T_91 = and(io.lsu_double_ecc_error_m, _T_90) @[lsu_lsc_ctl.scala 181:78] + node _T_92 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:102] + node _T_93 = and(_T_91, _T_92) @[lsu_lsc_ctl.scala 181:100] + node _T_94 = eq(_T_93, UInt<1>("h01")) @[lsu_lsc_ctl.scala 181:118] + node _T_95 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 181:149] + node _T_96 = mux(_T_94, UInt<4>("h01"), _T_95) @[lsu_lsc_ctl.scala 181:49] + lsu_error_pkt_m.bits.mscause <= _T_96 @[lsu_lsc_ctl.scala 181:43] + node _T_97 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 182:59] + lsu_error_pkt_m.bits.addr <= _T_97 @[lsu_lsc_ctl.scala 182:43] + node _T_98 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:72] + node _T_99 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:117] + node _T_100 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 183:166] + node _T_101 = bits(_T_100, 0, 0) @[lsu_lsc_ctl.scala 183:195] + node _T_102 = mux(_T_101, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 183:137] + node _T_103 = mux(_T_99, UInt<2>("h02"), _T_102) @[lsu_lsc_ctl.scala 183:92] + node _T_104 = mux(_T_98, UInt<2>("h03"), _T_103) @[lsu_lsc_ctl.scala 183:44] + lsu_fir_error_m <= _T_104 @[lsu_lsc_ctl.scala 183:38] + node _T_105 = or(lsu_error_pkt_m.valid, lsu_error_pkt_m.bits.single_ecc_error) @[lsu_lsc_ctl.scala 184:73] + node _T_106 = or(_T_105, io.clk_override) @[lsu_lsc_ctl.scala 184:113] + node _T_107 = bits(_T_106, 0, 0) @[lib.scala 8:44] + node _T_108 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr of rvclkhdr @[lib.scala 417:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 419:18] + rvclkhdr.io.en <= _T_107 @[lib.scala 420:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 421:24] + wire _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 423:50] + _T_109.bits.addr <= UInt<32>("h00") @[lib.scala 423:50] + _T_109.bits.mscause <= UInt<4>("h00") @[lib.scala 423:50] + _T_109.bits.exc_type <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.bits.inst_type <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.valid <= UInt<1>("h00") @[lib.scala 423:50] + reg _T_110 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, clock with : (reset => (reset, _T_109)) @[Reg.scala 27:20] + when _T_107 : @[Reg.scala 28:19] + _T_110.bits.addr <= lsu_error_pkt_m.bits.addr @[Reg.scala 28:23] + _T_110.bits.mscause <= lsu_error_pkt_m.bits.mscause @[Reg.scala 28:23] + _T_110.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[Reg.scala 28:23] + _T_110.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[Reg.scala 28:23] + _T_110.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[Reg.scala 28:23] + _T_110.valid <= lsu_error_pkt_m.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.lsu_error_pkt_r.bits.addr <= _T_110.bits.addr @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.mscause <= _T_110.bits.mscause @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.exc_type <= _T_110.bits.exc_type @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.inst_type <= _T_110.bits.inst_type @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.single_ecc_error <= _T_110.bits.single_ecc_error @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.valid <= _T_110.valid @[lsu_lsc_ctl.scala 184:24] + reg _T_111 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 185:83] + _T_111 <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 185:83] + io.lsu_error_pkt_r.bits.single_ecc_error <= _T_111 @[lsu_lsc_ctl.scala 185:46] + reg _T_112 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 186:67] + _T_112 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 186:67] + io.lsu_error_pkt_r.valid <= _T_112 @[lsu_lsc_ctl.scala 186:30] + reg _T_113 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:75] + _T_113 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 187:75] + io.lsu_fir_error <= _T_113 @[lsu_lsc_ctl.scala 187:38] + dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 189:27] + dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:26] + dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27] + dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22] + dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27] + dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27] + node _T_114 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30] + dma_pkt_d.bits.load <= _T_114 @[lsu_lsc_ctl.scala 195:27] + node _T_115 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56] + node _T_116 = eq(_T_115, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62] + dma_pkt_d.bits.by <= _T_116 @[lsu_lsc_ctl.scala 196:27] + node _T_117 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56] + node _T_118 = eq(_T_117, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62] + dma_pkt_d.bits.half <= _T_118 @[lsu_lsc_ctl.scala 197:27] + node _T_119 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56] + node _T_120 = eq(_T_119, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62] + dma_pkt_d.bits.word <= _T_120 @[lsu_lsc_ctl.scala 198:27] + node _T_121 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56] + node _T_122 = eq(_T_121, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62] + dma_pkt_d.bits.dword <= _T_122 @[lsu_lsc_ctl.scala 199:27] + dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39] + dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39] + dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39] + wire lsu_ld_datafn_r : UInt<32> + lsu_ld_datafn_r <= UInt<32>("h00") + wire lsu_ld_datafn_corr_r : UInt<32> + lsu_ld_datafn_corr_r <= UInt<32>("h00") + wire lsu_ld_datafn_m : UInt<32> + lsu_ld_datafn_m <= UInt<32>("h00") + node _T_123 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50] + node _T_124 = mux(_T_123, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26] + io.lsu_pkt_d.bits.store_data_bypass_m <= _T_124.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_124.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.store_data_bypass_d <= _T_124.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.dma <= _T_124.bits.dma @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.unsign <= _T_124.bits.unsign @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.store <= _T_124.bits.store @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.load <= _T_124.bits.load @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.dword <= _T_124.bits.dword @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.word <= _T_124.bits.word @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.half <= _T_124.bits.half @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.by <= _T_124.bits.by @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.stack <= _T_124.bits.stack @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.fast_int <= _T_124.bits.fast_int @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.valid <= _T_124.valid @[lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20] + node _T_125 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64] + node _T_126 = and(io.flush_m_up, _T_125) @[lsu_lsc_ctl.scala 212:61] + node _T_127 = eq(_T_126, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45] + node _T_128 = and(io.lsu_p.valid, _T_127) @[lsu_lsc_ctl.scala 212:43] + node _T_129 = or(_T_128, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90] + io.lsu_pkt_d.valid <= _T_129 @[lsu_lsc_ctl.scala 212:24] + node _T_130 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68] + node _T_131 = and(io.flush_m_up, _T_130) @[lsu_lsc_ctl.scala 213:65] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49] + node _T_133 = and(io.lsu_pkt_d.valid, _T_132) @[lsu_lsc_ctl.scala 213:47] + lsu_pkt_m_in.valid <= _T_133 @[lsu_lsc_ctl.scala 213:24] + node _T_134 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68] + node _T_135 = and(io.flush_m_up, _T_134) @[lsu_lsc_ctl.scala 214:65] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49] + node _T_137 = and(io.lsu_pkt_m.valid, _T_136) @[lsu_lsc_ctl.scala 214:47] + lsu_pkt_r_in.valid <= _T_137 @[lsu_lsc_ctl.scala 214:24] + wire _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + reg _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_138)) @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65] + _T_139.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65] + io.lsu_pkt_m.bits.store_data_bypass_m <= _T_139.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_139.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.store_data_bypass_d <= _T_139.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.dma <= _T_139.bits.dma @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.unsign <= _T_139.bits.unsign @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.store <= _T_139.bits.store @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.load <= _T_139.bits.load @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.dword <= _T_139.bits.dword @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.word <= _T_139.bits.word @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.half <= _T_139.bits.half @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.by <= _T_139.bits.by @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.stack <= _T_139.bits.stack @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.fast_int <= _T_139.bits.fast_int @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.valid <= _T_139.valid @[lsu_lsc_ctl.scala 216:28] + wire _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + reg _T_141 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_140)) @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65] + _T_141.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65] + io.lsu_pkt_r.bits.store_data_bypass_m <= _T_141.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_141.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.store_data_bypass_d <= _T_141.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.dma <= _T_141.bits.dma @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.unsign <= _T_141.bits.unsign @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.store <= _T_141.bits.store @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.load <= _T_141.bits.load @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.dword <= _T_141.bits.dword @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.word <= _T_141.bits.word @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.half <= _T_141.bits.half @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.by <= _T_141.bits.by @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.stack <= _T_141.bits.stack @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.fast_int <= _T_141.bits.fast_int @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.valid <= _T_141.valid @[lsu_lsc_ctl.scala 217:28] + reg _T_142 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65] + _T_142 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65] + io.lsu_pkt_m.valid <= _T_142 @[lsu_lsc_ctl.scala 218:28] + reg _T_143 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65] + _T_143 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65] + io.lsu_pkt_r.valid <= _T_143 @[lsu_lsc_ctl.scala 219:28] + node _T_144 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59] + node _T_145 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100] + node _T_146 = cat(_T_145, UInt<3>("h00")) @[Cat.scala 29:58] + node dma_mem_wdata_shifted = dshr(_T_144, _T_146) @[lsu_lsc_ctl.scala 221:66] + node _T_147 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63] + node _T_148 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91] + node _T_149 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122] + node store_data_d = mux(_T_147, _T_148, _T_149) @[lsu_lsc_ctl.scala 222:34] + node _T_150 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73] + node _T_151 = bits(io.lsu_exu.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:103] + node _T_152 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:122] + node store_data_m_in = mux(_T_150, _T_151, _T_152) @[lsu_lsc_ctl.scala 223:34] + node _T_153 = bits(io.lsu_addr_d, 2, 2) @[lsu_lsc_ctl.scala 224:62] + reg _T_154 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:48] + _T_154 <= _T_153 @[lsu_lsc_ctl.scala 224:48] + node _T_155 = bits(io.end_addr_d, 2, 2) @[lsu_lsc_ctl.scala 224:124] + reg _T_156 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:110] + _T_156 <= _T_155 @[lsu_lsc_ctl.scala 224:110] + node int = neq(_T_154, _T_156) @[lsu_lsc_ctl.scala 224:72] + node _T_157 = bits(io.lsu_addr_m, 2, 2) @[lsu_lsc_ctl.scala 225:62] + reg _T_158 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:48] + _T_158 <= _T_157 @[lsu_lsc_ctl.scala 225:48] + node _T_159 = bits(io.end_addr_m, 2, 2) @[lsu_lsc_ctl.scala 225:124] + reg _T_160 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:110] + _T_160 <= _T_159 @[lsu_lsc_ctl.scala 225:110] + node int1 = neq(_T_158, _T_160) @[lsu_lsc_ctl.scala 225:72] + reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:72] + store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 226:72] + reg _T_161 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62] + _T_161 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 227:62] + io.lsu_addr_m <= _T_161 @[lsu_lsc_ctl.scala 227:24] + reg _T_162 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:62] + _T_162 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 228:62] + io.lsu_addr_r <= _T_162 @[lsu_lsc_ctl.scala 228:24] + node _T_163 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:60] + node _T_164 = mux(int, end_addr_pre_m, _T_163) @[lsu_lsc_ctl.scala 229:27] + node _T_165 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:117] + reg _T_166 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:103] + _T_166 <= _T_165 @[lsu_lsc_ctl.scala 229:103] + node _T_167 = cat(_T_164, _T_166) @[Cat.scala 29:58] + io.end_addr_m <= _T_167 @[lsu_lsc_ctl.scala 229:17] + node _T_168 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:61] + node _T_169 = mux(int1, end_addr_pre_r, _T_168) @[lsu_lsc_ctl.scala 230:27] + node _T_170 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:118] + reg _T_171 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:104] + _T_171 <= _T_170 @[lsu_lsc_ctl.scala 230:104] + node _T_172 = cat(_T_169, _T_171) @[Cat.scala 29:58] + io.end_addr_r <= _T_172 @[lsu_lsc_ctl.scala 230:17] + node _T_173 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 231:41] + node _T_174 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 231:69] + node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 231:87] + node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_175 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_175 : @[Reg.scala 28:19] + _T_177 <= _T_173 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + end_addr_pre_m <= _T_177 @[lsu_lsc_ctl.scala 231:18] + node _T_178 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:41] + node _T_179 = and(io.lsu_pkt_m.valid, int) @[lsu_lsc_ctl.scala 232:69] + node _T_180 = or(_T_179, io.clk_override) @[lsu_lsc_ctl.scala 232:76] + node _T_181 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_180 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_182 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_180 : @[Reg.scala 28:19] + _T_182 <= _T_178 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + end_addr_pre_r <= _T_182 @[lsu_lsc_ctl.scala 232:18] + reg _T_183 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62] + _T_183 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 233:62] + io.addr_in_dccm_m <= _T_183 @[lsu_lsc_ctl.scala 233:24] + reg _T_184 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62] + _T_184 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 234:62] + io.addr_in_dccm_r <= _T_184 @[lsu_lsc_ctl.scala 234:24] + reg _T_185 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62] + _T_185 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 235:62] + io.addr_in_pic_m <= _T_185 @[lsu_lsc_ctl.scala 235:24] + reg _T_186 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62] + _T_186 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 236:62] + io.addr_in_pic_r <= _T_186 @[lsu_lsc_ctl.scala 236:24] + reg _T_187 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62] + _T_187 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 237:62] + io.addr_external_m <= _T_187 @[lsu_lsc_ctl.scala 237:24] + reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:66] + addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 238:66] + node _T_188 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 239:77] + node _T_189 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_188 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_188 : @[Reg.scala 28:19] + bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_190 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 242:52] + io.lsu_fir_addr <= _T_190 @[lsu_lsc_ctl.scala 242:28] + io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 244:28] + node _T_191 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 246:68] + node _T_192 = and(io.lsu_pkt_r.valid, _T_191) @[lsu_lsc_ctl.scala 246:41] + node _T_193 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:96] + node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 246:94] + node _T_195 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:110] + node _T_196 = and(_T_194, _T_195) @[lsu_lsc_ctl.scala 246:108] + io.lsu_commit_r <= _T_196 @[lsu_lsc_ctl.scala 246:19] + node _T_197 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 247:52] + node _T_198 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 247:69] + node _T_199 = bits(_T_198, 0, 0) @[Bitwise.scala 72:15] + node _T_200 = mux(_T_199, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_201 = or(_T_197, _T_200) @[lsu_lsc_ctl.scala 247:59] + node _T_202 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 247:133] + node _T_203 = mux(_T_202, io.lsu_exu.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 247:94] + node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 247:89] + io.store_data_m <= _T_204 @[lsu_lsc_ctl.scala 247:29] + node _T_205 = mux(io.addr_external_m, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 268:33] + lsu_ld_datafn_m <= _T_205 @[lsu_lsc_ctl.scala 268:27] + node _T_206 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 269:49] + node _T_207 = mux(_T_206, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 269:33] + lsu_ld_datafn_corr_r <= _T_207 @[lsu_lsc_ctl.scala 269:27] + node _T_208 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 270:74] + node _T_209 = bits(_T_208, 0, 0) @[Bitwise.scala 72:15] + node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_211 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 270:133] + node _T_212 = cat(UInt<24>("h00"), _T_211) @[Cat.scala 29:58] + node _T_213 = and(_T_210, _T_212) @[lsu_lsc_ctl.scala 270:102] + node _T_214 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 271:43] + node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15] + node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_217 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 271:102] + node _T_218 = cat(UInt<16>("h00"), _T_217) @[Cat.scala 29:58] + node _T_219 = and(_T_216, _T_218) @[lsu_lsc_ctl.scala 271:71] + node _T_220 = or(_T_213, _T_219) @[lsu_lsc_ctl.scala 270:141] + node _T_221 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17] + node _T_222 = and(_T_221, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 272:43] + node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15] + node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_225 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 272:102] + node _T_226 = bits(_T_225, 0, 0) @[Bitwise.scala 72:15] + node _T_227 = mux(_T_226, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_228 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 272:125] + node _T_229 = cat(_T_227, _T_228) @[Cat.scala 29:58] + node _T_230 = and(_T_224, _T_229) @[lsu_lsc_ctl.scala 272:71] + node _T_231 = or(_T_220, _T_230) @[lsu_lsc_ctl.scala 271:114] + node _T_232 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 273:17] + node _T_233 = and(_T_232, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 273:43] + node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15] + node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_236 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 273:101] + node _T_237 = bits(_T_236, 0, 0) @[Bitwise.scala 72:15] + node _T_238 = mux(_T_237, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_239 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 273:125] + node _T_240 = cat(_T_238, _T_239) @[Cat.scala 29:58] + node _T_241 = and(_T_235, _T_240) @[lsu_lsc_ctl.scala 273:71] + node _T_242 = or(_T_231, _T_241) @[lsu_lsc_ctl.scala 272:134] + node _T_243 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_244 = mux(_T_243, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_245 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 274:60] + node _T_246 = and(_T_244, _T_245) @[lsu_lsc_ctl.scala 274:43] + node _T_247 = or(_T_242, _T_246) @[lsu_lsc_ctl.scala 273:134] + io.lsu_exu.lsu_result_m <= _T_247 @[lsu_lsc_ctl.scala 270:35] + node _T_248 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 275:66] + node _T_249 = bits(_T_248, 0, 0) @[Bitwise.scala 72:15] + node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_251 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 275:130] + node _T_252 = cat(UInt<24>("h00"), _T_251) @[Cat.scala 29:58] + node _T_253 = and(_T_250, _T_252) @[lsu_lsc_ctl.scala 275:94] + node _T_254 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 276:43] + node _T_255 = bits(_T_254, 0, 0) @[Bitwise.scala 72:15] + node _T_256 = mux(_T_255, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_257 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 276:107] + node _T_258 = cat(UInt<16>("h00"), _T_257) @[Cat.scala 29:58] + node _T_259 = and(_T_256, _T_258) @[lsu_lsc_ctl.scala 276:71] + node _T_260 = or(_T_253, _T_259) @[lsu_lsc_ctl.scala 275:138] + node _T_261 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17] + node _T_262 = and(_T_261, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 277:43] + node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15] + node _T_264 = mux(_T_263, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 277:107] + node _T_266 = bits(_T_265, 0, 0) @[Bitwise.scala 72:15] + node _T_267 = mux(_T_266, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_268 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 277:135] + node _T_269 = cat(_T_267, _T_268) @[Cat.scala 29:58] + node _T_270 = and(_T_264, _T_269) @[lsu_lsc_ctl.scala 277:71] + node _T_271 = or(_T_260, _T_270) @[lsu_lsc_ctl.scala 276:119] + node _T_272 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 278:17] + node _T_273 = and(_T_272, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 278:43] + node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15] + node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 278:106] + node _T_277 = bits(_T_276, 0, 0) @[Bitwise.scala 72:15] + node _T_278 = mux(_T_277, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_279 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 278:135] + node _T_280 = cat(_T_278, _T_279) @[Cat.scala 29:58] + node _T_281 = and(_T_275, _T_280) @[lsu_lsc_ctl.scala 278:71] + node _T_282 = or(_T_271, _T_281) @[lsu_lsc_ctl.scala 277:144] + node _T_283 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_284 = mux(_T_283, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_285 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 279:65] + node _T_286 = and(_T_284, _T_285) @[lsu_lsc_ctl.scala 279:43] + node _T_287 = or(_T_282, _T_286) @[lsu_lsc_ctl.scala 278:144] + io.lsu_result_corr_r <= _T_287 @[lsu_lsc_ctl.scala 275:27] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_dccm_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, flip scan_mode : UInt<1>} + + node picm_rd_data_m = cat(io.lsu_pic.picm_rd_data, io.lsu_pic.picm_rd_data) @[Cat.scala 29:58] + node dccm_rdata_corr_r = cat(io.sec_data_hi_r, io.sec_data_lo_r) @[Cat.scala 29:58] + node dccm_rdata_corr_m = cat(io.sec_data_hi_m, io.sec_data_lo_m) @[Cat.scala 29:58] + node dccm_rdata_r = cat(io.dccm_rdata_hi_r, io.dccm_rdata_lo_r) @[Cat.scala 29:58] + node dccm_rdata_m = cat(io.dccm_rdata_hi_m, io.dccm_rdata_lo_m) @[Cat.scala 29:58] + wire lsu_rdata_r : UInt<64> + lsu_rdata_r <= UInt<1>("h00") + wire lsu_rdata_m : UInt<64> + lsu_rdata_m <= UInt<1>("h00") + wire lsu_rdata_corr_r : UInt<64> + lsu_rdata_corr_r <= UInt<1>("h00") + wire lsu_rdata_corr_m : UInt<64> + lsu_rdata_corr_m <= UInt<1>("h00") + wire stbuf_fwddata_r : UInt<64> + stbuf_fwddata_r <= UInt<1>("h00") + wire stbuf_fwdbyteen_r : UInt<64> + stbuf_fwdbyteen_r <= UInt<1>("h00") + wire picm_rd_data_r_32 : UInt<32> + picm_rd_data_r_32 <= UInt<1>("h00") + wire picm_rd_data_r : UInt<64> + picm_rd_data_r <= UInt<1>("h00") + wire lsu_ld_data_corr_m : UInt<64> + lsu_ld_data_corr_m <= UInt<1>("h00") + wire stbuf_fwddata_en : UInt<1> + stbuf_fwddata_en <= UInt<1>("h00") + wire lsu_double_ecc_error_r_ff : UInt<1> + lsu_double_ecc_error_r_ff <= UInt<1>("h00") + wire ld_single_ecc_error_hi_r_ff : UInt<1> + ld_single_ecc_error_hi_r_ff <= UInt<1>("h00") + wire ld_single_ecc_error_lo_r_ff : UInt<1> + ld_single_ecc_error_lo_r_ff <= UInt<1>("h00") + wire ld_sec_addr_hi_r_ff : UInt<16> + ld_sec_addr_hi_r_ff <= UInt<1>("h00") + wire ld_sec_addr_lo_r_ff : UInt<16> + ld_sec_addr_lo_r_ff <= UInt<1>("h00") + io.lsu_ld_data_m <= UInt<1>("h00") @[lsu_dccm_ctl.scala 121:20] + node _T = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.load) @[lsu_dccm_ctl.scala 145:63] + node _T_1 = and(_T, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 145:88] + io.dma_dccm_ctl.dccm_dma_rvalid <= _T_1 @[lsu_dccm_ctl.scala 145:41] + io.dma_dccm_ctl.dccm_dma_ecc_error <= io.lsu_double_ecc_error_m @[lsu_dccm_ctl.scala 146:41] + node _T_2 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44] + node _T_3 = bits(lsu_rdata_corr_m, 31, 0) @[lsu_dccm_ctl.scala 147:104] + node _T_4 = cat(_T_3, _T_3) @[Cat.scala 29:58] + node _T_5 = mux(_T_2, lsu_rdata_corr_m, _T_4) @[lsu_dccm_ctl.scala 147:47] + io.dma_dccm_ctl.dccm_dma_rdata <= _T_5 @[lsu_dccm_ctl.scala 147:41] + io.dma_dccm_ctl.dccm_dma_rtag <= io.dma_mem_tag_m @[lsu_dccm_ctl.scala 148:41] + io.dccm_rdata_lo_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 149:28] + io.dccm_rdata_hi_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 150:28] + io.dccm_data_ecc_hi_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 151:28] + io.dccm_data_ecc_lo_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 152:28] + io.lsu_ld_data_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 153:28] + node _T_6 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_7 = bits(_T_6, 0, 0) @[lsu_dccm_ctl.scala 155:134] + node _T_8 = bits(_T_7, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_9 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_10 = bits(_T_9, 7, 0) @[lsu_dccm_ctl.scala 155:196] + node _T_11 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_12 = bits(picm_rd_data_m, 7, 0) @[lsu_dccm_ctl.scala 155:253] + node _T_13 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_14 = mux(_T_13, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_15 = bits(dccm_rdata_corr_m, 7, 0) @[lsu_dccm_ctl.scala 155:313] + node _T_16 = and(_T_14, _T_15) @[lsu_dccm_ctl.scala 155:294] + node _T_17 = mux(_T_11, _T_12, _T_16) @[lsu_dccm_ctl.scala 155:214] + node _T_18 = mux(_T_8, _T_10, _T_17) @[lsu_dccm_ctl.scala 155:78] + node _T_19 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_20 = xor(UInt<8>("h0ff"), _T_19) @[Bitwise.scala 102:21] + node _T_21 = shr(_T_18, 4) @[Bitwise.scala 103:21] + node _T_22 = and(_T_21, _T_20) @[Bitwise.scala 103:31] + node _T_23 = bits(_T_18, 3, 0) @[Bitwise.scala 103:46] + node _T_24 = shl(_T_23, 4) @[Bitwise.scala 103:65] + node _T_25 = not(_T_20) @[Bitwise.scala 103:77] + node _T_26 = and(_T_24, _T_25) @[Bitwise.scala 103:75] + node _T_27 = or(_T_22, _T_26) @[Bitwise.scala 103:39] + node _T_28 = bits(_T_20, 5, 0) @[Bitwise.scala 102:28] + node _T_29 = shl(_T_28, 2) @[Bitwise.scala 102:47] + node _T_30 = xor(_T_20, _T_29) @[Bitwise.scala 102:21] + node _T_31 = shr(_T_27, 2) @[Bitwise.scala 103:21] + node _T_32 = and(_T_31, _T_30) @[Bitwise.scala 103:31] + node _T_33 = bits(_T_27, 5, 0) @[Bitwise.scala 103:46] + node _T_34 = shl(_T_33, 2) @[Bitwise.scala 103:65] + node _T_35 = not(_T_30) @[Bitwise.scala 103:77] + node _T_36 = and(_T_34, _T_35) @[Bitwise.scala 103:75] + node _T_37 = or(_T_32, _T_36) @[Bitwise.scala 103:39] + node _T_38 = bits(_T_30, 6, 0) @[Bitwise.scala 102:28] + node _T_39 = shl(_T_38, 1) @[Bitwise.scala 102:47] + node _T_40 = xor(_T_30, _T_39) @[Bitwise.scala 102:21] + node _T_41 = shr(_T_37, 1) @[Bitwise.scala 103:21] + node _T_42 = and(_T_41, _T_40) @[Bitwise.scala 103:31] + node _T_43 = bits(_T_37, 6, 0) @[Bitwise.scala 103:46] + node _T_44 = shl(_T_43, 1) @[Bitwise.scala 103:65] + node _T_45 = not(_T_40) @[Bitwise.scala 103:77] + node _T_46 = and(_T_44, _T_45) @[Bitwise.scala 103:75] + node _T_47 = or(_T_42, _T_46) @[Bitwise.scala 103:39] + node _T_48 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_49 = bits(_T_48, 1, 1) @[lsu_dccm_ctl.scala 155:134] + node _T_50 = bits(_T_49, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_51 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_52 = bits(_T_51, 15, 8) @[lsu_dccm_ctl.scala 155:196] + node _T_53 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_54 = bits(picm_rd_data_m, 15, 8) @[lsu_dccm_ctl.scala 155:253] + node _T_55 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_56 = mux(_T_55, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_57 = bits(dccm_rdata_corr_m, 15, 8) @[lsu_dccm_ctl.scala 155:313] + node _T_58 = and(_T_56, _T_57) @[lsu_dccm_ctl.scala 155:294] + node _T_59 = mux(_T_53, _T_54, _T_58) @[lsu_dccm_ctl.scala 155:214] + node _T_60 = mux(_T_50, _T_52, _T_59) @[lsu_dccm_ctl.scala 155:78] + node _T_61 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_62 = xor(UInt<8>("h0ff"), _T_61) @[Bitwise.scala 102:21] + node _T_63 = shr(_T_60, 4) @[Bitwise.scala 103:21] + node _T_64 = and(_T_63, _T_62) @[Bitwise.scala 103:31] + node _T_65 = bits(_T_60, 3, 0) @[Bitwise.scala 103:46] + node _T_66 = shl(_T_65, 4) @[Bitwise.scala 103:65] + node _T_67 = not(_T_62) @[Bitwise.scala 103:77] + node _T_68 = and(_T_66, _T_67) @[Bitwise.scala 103:75] + node _T_69 = or(_T_64, _T_68) @[Bitwise.scala 103:39] + node _T_70 = bits(_T_62, 5, 0) @[Bitwise.scala 102:28] + node _T_71 = shl(_T_70, 2) @[Bitwise.scala 102:47] + node _T_72 = xor(_T_62, _T_71) @[Bitwise.scala 102:21] + node _T_73 = shr(_T_69, 2) @[Bitwise.scala 103:21] + node _T_74 = and(_T_73, _T_72) @[Bitwise.scala 103:31] + node _T_75 = bits(_T_69, 5, 0) @[Bitwise.scala 103:46] + node _T_76 = shl(_T_75, 2) @[Bitwise.scala 103:65] + node _T_77 = not(_T_72) @[Bitwise.scala 103:77] + node _T_78 = and(_T_76, _T_77) @[Bitwise.scala 103:75] + node _T_79 = or(_T_74, _T_78) @[Bitwise.scala 103:39] + node _T_80 = bits(_T_72, 6, 0) @[Bitwise.scala 102:28] + node _T_81 = shl(_T_80, 1) @[Bitwise.scala 102:47] + node _T_82 = xor(_T_72, _T_81) @[Bitwise.scala 102:21] + node _T_83 = shr(_T_79, 1) @[Bitwise.scala 103:21] + node _T_84 = and(_T_83, _T_82) @[Bitwise.scala 103:31] + node _T_85 = bits(_T_79, 6, 0) @[Bitwise.scala 103:46] + node _T_86 = shl(_T_85, 1) @[Bitwise.scala 103:65] + node _T_87 = not(_T_82) @[Bitwise.scala 103:77] + node _T_88 = and(_T_86, _T_87) @[Bitwise.scala 103:75] + node _T_89 = or(_T_84, _T_88) @[Bitwise.scala 103:39] + node _T_90 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_91 = bits(_T_90, 2, 2) @[lsu_dccm_ctl.scala 155:134] + node _T_92 = bits(_T_91, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_93 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_94 = bits(_T_93, 23, 16) @[lsu_dccm_ctl.scala 155:196] + node _T_95 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_96 = bits(picm_rd_data_m, 23, 16) @[lsu_dccm_ctl.scala 155:253] + node _T_97 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_98 = mux(_T_97, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_99 = bits(dccm_rdata_corr_m, 23, 16) @[lsu_dccm_ctl.scala 155:313] + node _T_100 = and(_T_98, _T_99) @[lsu_dccm_ctl.scala 155:294] + node _T_101 = mux(_T_95, _T_96, _T_100) @[lsu_dccm_ctl.scala 155:214] + node _T_102 = mux(_T_92, _T_94, _T_101) @[lsu_dccm_ctl.scala 155:78] + node _T_103 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_104 = xor(UInt<8>("h0ff"), _T_103) @[Bitwise.scala 102:21] + node _T_105 = shr(_T_102, 4) @[Bitwise.scala 103:21] + node _T_106 = and(_T_105, _T_104) @[Bitwise.scala 103:31] + node _T_107 = bits(_T_102, 3, 0) @[Bitwise.scala 103:46] + node _T_108 = shl(_T_107, 4) @[Bitwise.scala 103:65] + node _T_109 = not(_T_104) @[Bitwise.scala 103:77] + node _T_110 = and(_T_108, _T_109) @[Bitwise.scala 103:75] + node _T_111 = or(_T_106, _T_110) @[Bitwise.scala 103:39] + node _T_112 = bits(_T_104, 5, 0) @[Bitwise.scala 102:28] + node _T_113 = shl(_T_112, 2) @[Bitwise.scala 102:47] + node _T_114 = xor(_T_104, _T_113) @[Bitwise.scala 102:21] + node _T_115 = shr(_T_111, 2) @[Bitwise.scala 103:21] + node _T_116 = and(_T_115, _T_114) @[Bitwise.scala 103:31] + node _T_117 = bits(_T_111, 5, 0) @[Bitwise.scala 103:46] + node _T_118 = shl(_T_117, 2) @[Bitwise.scala 103:65] + node _T_119 = not(_T_114) @[Bitwise.scala 103:77] + node _T_120 = and(_T_118, _T_119) @[Bitwise.scala 103:75] + node _T_121 = or(_T_116, _T_120) @[Bitwise.scala 103:39] + node _T_122 = bits(_T_114, 6, 0) @[Bitwise.scala 102:28] + node _T_123 = shl(_T_122, 1) @[Bitwise.scala 102:47] + node _T_124 = xor(_T_114, _T_123) @[Bitwise.scala 102:21] + node _T_125 = shr(_T_121, 1) @[Bitwise.scala 103:21] + node _T_126 = and(_T_125, _T_124) @[Bitwise.scala 103:31] + node _T_127 = bits(_T_121, 6, 0) @[Bitwise.scala 103:46] + node _T_128 = shl(_T_127, 1) @[Bitwise.scala 103:65] + node _T_129 = not(_T_124) @[Bitwise.scala 103:77] + node _T_130 = and(_T_128, _T_129) @[Bitwise.scala 103:75] + node _T_131 = or(_T_126, _T_130) @[Bitwise.scala 103:39] + node _T_132 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_133 = bits(_T_132, 3, 3) @[lsu_dccm_ctl.scala 155:134] + node _T_134 = bits(_T_133, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_135 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_136 = bits(_T_135, 31, 24) @[lsu_dccm_ctl.scala 155:196] + node _T_137 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_138 = bits(picm_rd_data_m, 31, 24) @[lsu_dccm_ctl.scala 155:253] + node _T_139 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_140 = mux(_T_139, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_141 = bits(dccm_rdata_corr_m, 31, 24) @[lsu_dccm_ctl.scala 155:313] + node _T_142 = and(_T_140, _T_141) @[lsu_dccm_ctl.scala 155:294] + node _T_143 = mux(_T_137, _T_138, _T_142) @[lsu_dccm_ctl.scala 155:214] + node _T_144 = mux(_T_134, _T_136, _T_143) @[lsu_dccm_ctl.scala 155:78] + node _T_145 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_146 = xor(UInt<8>("h0ff"), _T_145) @[Bitwise.scala 102:21] + node _T_147 = shr(_T_144, 4) @[Bitwise.scala 103:21] + node _T_148 = and(_T_147, _T_146) @[Bitwise.scala 103:31] + node _T_149 = bits(_T_144, 3, 0) @[Bitwise.scala 103:46] + node _T_150 = shl(_T_149, 4) @[Bitwise.scala 103:65] + node _T_151 = not(_T_146) @[Bitwise.scala 103:77] + node _T_152 = and(_T_150, _T_151) @[Bitwise.scala 103:75] + node _T_153 = or(_T_148, _T_152) @[Bitwise.scala 103:39] + node _T_154 = bits(_T_146, 5, 0) @[Bitwise.scala 102:28] + node _T_155 = shl(_T_154, 2) @[Bitwise.scala 102:47] + node _T_156 = xor(_T_146, _T_155) @[Bitwise.scala 102:21] + node _T_157 = shr(_T_153, 2) @[Bitwise.scala 103:21] + node _T_158 = and(_T_157, _T_156) @[Bitwise.scala 103:31] + node _T_159 = bits(_T_153, 5, 0) @[Bitwise.scala 103:46] + node _T_160 = shl(_T_159, 2) @[Bitwise.scala 103:65] + node _T_161 = not(_T_156) @[Bitwise.scala 103:77] + node _T_162 = and(_T_160, _T_161) @[Bitwise.scala 103:75] + node _T_163 = or(_T_158, _T_162) @[Bitwise.scala 103:39] + node _T_164 = bits(_T_156, 6, 0) @[Bitwise.scala 102:28] + node _T_165 = shl(_T_164, 1) @[Bitwise.scala 102:47] + node _T_166 = xor(_T_156, _T_165) @[Bitwise.scala 102:21] + node _T_167 = shr(_T_163, 1) @[Bitwise.scala 103:21] + node _T_168 = and(_T_167, _T_166) @[Bitwise.scala 103:31] + node _T_169 = bits(_T_163, 6, 0) @[Bitwise.scala 103:46] + node _T_170 = shl(_T_169, 1) @[Bitwise.scala 103:65] + node _T_171 = not(_T_166) @[Bitwise.scala 103:77] + node _T_172 = and(_T_170, _T_171) @[Bitwise.scala 103:75] + node _T_173 = or(_T_168, _T_172) @[Bitwise.scala 103:39] + node _T_174 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_175 = bits(_T_174, 4, 4) @[lsu_dccm_ctl.scala 155:134] + node _T_176 = bits(_T_175, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_177 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_178 = bits(_T_177, 39, 32) @[lsu_dccm_ctl.scala 155:196] + node _T_179 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_180 = bits(picm_rd_data_m, 39, 32) @[lsu_dccm_ctl.scala 155:253] + node _T_181 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_182 = mux(_T_181, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_183 = bits(dccm_rdata_corr_m, 39, 32) @[lsu_dccm_ctl.scala 155:313] + node _T_184 = and(_T_182, _T_183) @[lsu_dccm_ctl.scala 155:294] + node _T_185 = mux(_T_179, _T_180, _T_184) @[lsu_dccm_ctl.scala 155:214] + node _T_186 = mux(_T_176, _T_178, _T_185) @[lsu_dccm_ctl.scala 155:78] + node _T_187 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_188 = xor(UInt<8>("h0ff"), _T_187) @[Bitwise.scala 102:21] + node _T_189 = shr(_T_186, 4) @[Bitwise.scala 103:21] + node _T_190 = and(_T_189, _T_188) @[Bitwise.scala 103:31] + node _T_191 = bits(_T_186, 3, 0) @[Bitwise.scala 103:46] + node _T_192 = shl(_T_191, 4) @[Bitwise.scala 103:65] + node _T_193 = not(_T_188) @[Bitwise.scala 103:77] + node _T_194 = and(_T_192, _T_193) @[Bitwise.scala 103:75] + node _T_195 = or(_T_190, _T_194) @[Bitwise.scala 103:39] + node _T_196 = bits(_T_188, 5, 0) @[Bitwise.scala 102:28] + node _T_197 = shl(_T_196, 2) @[Bitwise.scala 102:47] + node _T_198 = xor(_T_188, _T_197) @[Bitwise.scala 102:21] + node _T_199 = shr(_T_195, 2) @[Bitwise.scala 103:21] + node _T_200 = and(_T_199, _T_198) @[Bitwise.scala 103:31] + node _T_201 = bits(_T_195, 5, 0) @[Bitwise.scala 103:46] + node _T_202 = shl(_T_201, 2) @[Bitwise.scala 103:65] + node _T_203 = not(_T_198) @[Bitwise.scala 103:77] + node _T_204 = and(_T_202, _T_203) @[Bitwise.scala 103:75] + node _T_205 = or(_T_200, _T_204) @[Bitwise.scala 103:39] + node _T_206 = bits(_T_198, 6, 0) @[Bitwise.scala 102:28] + node _T_207 = shl(_T_206, 1) @[Bitwise.scala 102:47] + node _T_208 = xor(_T_198, _T_207) @[Bitwise.scala 102:21] + node _T_209 = shr(_T_205, 1) @[Bitwise.scala 103:21] + node _T_210 = and(_T_209, _T_208) @[Bitwise.scala 103:31] + node _T_211 = bits(_T_205, 6, 0) @[Bitwise.scala 103:46] + node _T_212 = shl(_T_211, 1) @[Bitwise.scala 103:65] + node _T_213 = not(_T_208) @[Bitwise.scala 103:77] + node _T_214 = and(_T_212, _T_213) @[Bitwise.scala 103:75] + node _T_215 = or(_T_210, _T_214) @[Bitwise.scala 103:39] + node _T_216 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_217 = bits(_T_216, 5, 5) @[lsu_dccm_ctl.scala 155:134] + node _T_218 = bits(_T_217, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_219 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_220 = bits(_T_219, 47, 40) @[lsu_dccm_ctl.scala 155:196] + node _T_221 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_222 = bits(picm_rd_data_m, 47, 40) @[lsu_dccm_ctl.scala 155:253] + node _T_223 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_224 = mux(_T_223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_225 = bits(dccm_rdata_corr_m, 47, 40) @[lsu_dccm_ctl.scala 155:313] + node _T_226 = and(_T_224, _T_225) @[lsu_dccm_ctl.scala 155:294] + node _T_227 = mux(_T_221, _T_222, _T_226) @[lsu_dccm_ctl.scala 155:214] + node _T_228 = mux(_T_218, _T_220, _T_227) @[lsu_dccm_ctl.scala 155:78] + node _T_229 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_230 = xor(UInt<8>("h0ff"), _T_229) @[Bitwise.scala 102:21] + node _T_231 = shr(_T_228, 4) @[Bitwise.scala 103:21] + node _T_232 = and(_T_231, _T_230) @[Bitwise.scala 103:31] + node _T_233 = bits(_T_228, 3, 0) @[Bitwise.scala 103:46] + node _T_234 = shl(_T_233, 4) @[Bitwise.scala 103:65] + node _T_235 = not(_T_230) @[Bitwise.scala 103:77] + node _T_236 = and(_T_234, _T_235) @[Bitwise.scala 103:75] + node _T_237 = or(_T_232, _T_236) @[Bitwise.scala 103:39] + node _T_238 = bits(_T_230, 5, 0) @[Bitwise.scala 102:28] + node _T_239 = shl(_T_238, 2) @[Bitwise.scala 102:47] + node _T_240 = xor(_T_230, _T_239) @[Bitwise.scala 102:21] + node _T_241 = shr(_T_237, 2) @[Bitwise.scala 103:21] + node _T_242 = and(_T_241, _T_240) @[Bitwise.scala 103:31] + node _T_243 = bits(_T_237, 5, 0) @[Bitwise.scala 103:46] + node _T_244 = shl(_T_243, 2) @[Bitwise.scala 103:65] + node _T_245 = not(_T_240) @[Bitwise.scala 103:77] + node _T_246 = and(_T_244, _T_245) @[Bitwise.scala 103:75] + node _T_247 = or(_T_242, _T_246) @[Bitwise.scala 103:39] + node _T_248 = bits(_T_240, 6, 0) @[Bitwise.scala 102:28] + node _T_249 = shl(_T_248, 1) @[Bitwise.scala 102:47] + node _T_250 = xor(_T_240, _T_249) @[Bitwise.scala 102:21] + node _T_251 = shr(_T_247, 1) @[Bitwise.scala 103:21] + node _T_252 = and(_T_251, _T_250) @[Bitwise.scala 103:31] + node _T_253 = bits(_T_247, 6, 0) @[Bitwise.scala 103:46] + node _T_254 = shl(_T_253, 1) @[Bitwise.scala 103:65] + node _T_255 = not(_T_250) @[Bitwise.scala 103:77] + node _T_256 = and(_T_254, _T_255) @[Bitwise.scala 103:75] + node _T_257 = or(_T_252, _T_256) @[Bitwise.scala 103:39] + node _T_258 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_259 = bits(_T_258, 6, 6) @[lsu_dccm_ctl.scala 155:134] + node _T_260 = bits(_T_259, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_261 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_262 = bits(_T_261, 55, 48) @[lsu_dccm_ctl.scala 155:196] + node _T_263 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_264 = bits(picm_rd_data_m, 55, 48) @[lsu_dccm_ctl.scala 155:253] + node _T_265 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_266 = mux(_T_265, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_267 = bits(dccm_rdata_corr_m, 55, 48) @[lsu_dccm_ctl.scala 155:313] + node _T_268 = and(_T_266, _T_267) @[lsu_dccm_ctl.scala 155:294] + node _T_269 = mux(_T_263, _T_264, _T_268) @[lsu_dccm_ctl.scala 155:214] + node _T_270 = mux(_T_260, _T_262, _T_269) @[lsu_dccm_ctl.scala 155:78] + node _T_271 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_272 = xor(UInt<8>("h0ff"), _T_271) @[Bitwise.scala 102:21] + node _T_273 = shr(_T_270, 4) @[Bitwise.scala 103:21] + node _T_274 = and(_T_273, _T_272) @[Bitwise.scala 103:31] + node _T_275 = bits(_T_270, 3, 0) @[Bitwise.scala 103:46] + node _T_276 = shl(_T_275, 4) @[Bitwise.scala 103:65] + node _T_277 = not(_T_272) @[Bitwise.scala 103:77] + node _T_278 = and(_T_276, _T_277) @[Bitwise.scala 103:75] + node _T_279 = or(_T_274, _T_278) @[Bitwise.scala 103:39] + node _T_280 = bits(_T_272, 5, 0) @[Bitwise.scala 102:28] + node _T_281 = shl(_T_280, 2) @[Bitwise.scala 102:47] + node _T_282 = xor(_T_272, _T_281) @[Bitwise.scala 102:21] + node _T_283 = shr(_T_279, 2) @[Bitwise.scala 103:21] + node _T_284 = and(_T_283, _T_282) @[Bitwise.scala 103:31] + node _T_285 = bits(_T_279, 5, 0) @[Bitwise.scala 103:46] + node _T_286 = shl(_T_285, 2) @[Bitwise.scala 103:65] + node _T_287 = not(_T_282) @[Bitwise.scala 103:77] + node _T_288 = and(_T_286, _T_287) @[Bitwise.scala 103:75] + node _T_289 = or(_T_284, _T_288) @[Bitwise.scala 103:39] + node _T_290 = bits(_T_282, 6, 0) @[Bitwise.scala 102:28] + node _T_291 = shl(_T_290, 1) @[Bitwise.scala 102:47] + node _T_292 = xor(_T_282, _T_291) @[Bitwise.scala 102:21] + node _T_293 = shr(_T_289, 1) @[Bitwise.scala 103:21] + node _T_294 = and(_T_293, _T_292) @[Bitwise.scala 103:31] + node _T_295 = bits(_T_289, 6, 0) @[Bitwise.scala 103:46] + node _T_296 = shl(_T_295, 1) @[Bitwise.scala 103:65] + node _T_297 = not(_T_292) @[Bitwise.scala 103:77] + node _T_298 = and(_T_296, _T_297) @[Bitwise.scala 103:75] + node _T_299 = or(_T_294, _T_298) @[Bitwise.scala 103:39] + node _T_300 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_301 = bits(_T_300, 7, 7) @[lsu_dccm_ctl.scala 155:134] + node _T_302 = bits(_T_301, 0, 0) @[lsu_dccm_ctl.scala 155:139] + node _T_303 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_304 = bits(_T_303, 63, 56) @[lsu_dccm_ctl.scala 155:196] + node _T_305 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232] + node _T_306 = bits(picm_rd_data_m, 63, 56) @[lsu_dccm_ctl.scala 155:253] + node _T_307 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_308 = mux(_T_307, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_309 = bits(dccm_rdata_corr_m, 63, 56) @[lsu_dccm_ctl.scala 155:313] + node _T_310 = and(_T_308, _T_309) @[lsu_dccm_ctl.scala 155:294] + node _T_311 = mux(_T_305, _T_306, _T_310) @[lsu_dccm_ctl.scala 155:214] + node _T_312 = mux(_T_302, _T_304, _T_311) @[lsu_dccm_ctl.scala 155:78] + node _T_313 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_314 = xor(UInt<8>("h0ff"), _T_313) @[Bitwise.scala 102:21] + node _T_315 = shr(_T_312, 4) @[Bitwise.scala 103:21] + node _T_316 = and(_T_315, _T_314) @[Bitwise.scala 103:31] + node _T_317 = bits(_T_312, 3, 0) @[Bitwise.scala 103:46] + node _T_318 = shl(_T_317, 4) @[Bitwise.scala 103:65] + node _T_319 = not(_T_314) @[Bitwise.scala 103:77] + node _T_320 = and(_T_318, _T_319) @[Bitwise.scala 103:75] + node _T_321 = or(_T_316, _T_320) @[Bitwise.scala 103:39] + node _T_322 = bits(_T_314, 5, 0) @[Bitwise.scala 102:28] + node _T_323 = shl(_T_322, 2) @[Bitwise.scala 102:47] + node _T_324 = xor(_T_314, _T_323) @[Bitwise.scala 102:21] + node _T_325 = shr(_T_321, 2) @[Bitwise.scala 103:21] + node _T_326 = and(_T_325, _T_324) @[Bitwise.scala 103:31] + node _T_327 = bits(_T_321, 5, 0) @[Bitwise.scala 103:46] + node _T_328 = shl(_T_327, 2) @[Bitwise.scala 103:65] + node _T_329 = not(_T_324) @[Bitwise.scala 103:77] + node _T_330 = and(_T_328, _T_329) @[Bitwise.scala 103:75] + node _T_331 = or(_T_326, _T_330) @[Bitwise.scala 103:39] + node _T_332 = bits(_T_324, 6, 0) @[Bitwise.scala 102:28] + node _T_333 = shl(_T_332, 1) @[Bitwise.scala 102:47] + node _T_334 = xor(_T_324, _T_333) @[Bitwise.scala 102:21] + node _T_335 = shr(_T_331, 1) @[Bitwise.scala 103:21] + node _T_336 = and(_T_335, _T_334) @[Bitwise.scala 103:31] + node _T_337 = bits(_T_331, 6, 0) @[Bitwise.scala 103:46] + node _T_338 = shl(_T_337, 1) @[Bitwise.scala 103:65] + node _T_339 = not(_T_334) @[Bitwise.scala 103:77] + node _T_340 = and(_T_338, _T_339) @[Bitwise.scala 103:75] + node _T_341 = or(_T_336, _T_340) @[Bitwise.scala 103:39] + wire _T_342 : UInt<8>[8] @[lsu_dccm_ctl.scala 155:62] + _T_342[0] <= _T_47 @[lsu_dccm_ctl.scala 155:62] + _T_342[1] <= _T_89 @[lsu_dccm_ctl.scala 155:62] + _T_342[2] <= _T_131 @[lsu_dccm_ctl.scala 155:62] + _T_342[3] <= _T_173 @[lsu_dccm_ctl.scala 155:62] + _T_342[4] <= _T_215 @[lsu_dccm_ctl.scala 155:62] + _T_342[5] <= _T_257 @[lsu_dccm_ctl.scala 155:62] + _T_342[6] <= _T_299 @[lsu_dccm_ctl.scala 155:62] + _T_342[7] <= _T_341 @[lsu_dccm_ctl.scala 155:62] + node _T_343 = cat(_T_342[6], _T_342[7]) @[Cat.scala 29:58] + node _T_344 = cat(_T_342[4], _T_342[5]) @[Cat.scala 29:58] + node _T_345 = cat(_T_344, _T_343) @[Cat.scala 29:58] + node _T_346 = cat(_T_342[2], _T_342[3]) @[Cat.scala 29:58] + node _T_347 = cat(_T_342[0], _T_342[1]) @[Cat.scala 29:58] + node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] + node _T_349 = cat(_T_348, _T_345) @[Cat.scala 29:58] + node _T_350 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47] + node _T_351 = xor(UInt<64>("h0ffffffffffffffff"), _T_350) @[Bitwise.scala 102:21] + node _T_352 = shr(_T_349, 32) @[Bitwise.scala 103:21] + node _T_353 = and(_T_352, _T_351) @[Bitwise.scala 103:31] + node _T_354 = bits(_T_349, 31, 0) @[Bitwise.scala 103:46] + node _T_355 = shl(_T_354, 32) @[Bitwise.scala 103:65] + node _T_356 = not(_T_351) @[Bitwise.scala 103:77] + node _T_357 = and(_T_355, _T_356) @[Bitwise.scala 103:75] + node _T_358 = or(_T_353, _T_357) @[Bitwise.scala 103:39] + node _T_359 = bits(_T_351, 47, 0) @[Bitwise.scala 102:28] + node _T_360 = shl(_T_359, 16) @[Bitwise.scala 102:47] + node _T_361 = xor(_T_351, _T_360) @[Bitwise.scala 102:21] + node _T_362 = shr(_T_358, 16) @[Bitwise.scala 103:21] + node _T_363 = and(_T_362, _T_361) @[Bitwise.scala 103:31] + node _T_364 = bits(_T_358, 47, 0) @[Bitwise.scala 103:46] + node _T_365 = shl(_T_364, 16) @[Bitwise.scala 103:65] + node _T_366 = not(_T_361) @[Bitwise.scala 103:77] + node _T_367 = and(_T_365, _T_366) @[Bitwise.scala 103:75] + node _T_368 = or(_T_363, _T_367) @[Bitwise.scala 103:39] + node _T_369 = bits(_T_361, 55, 0) @[Bitwise.scala 102:28] + node _T_370 = shl(_T_369, 8) @[Bitwise.scala 102:47] + node _T_371 = xor(_T_361, _T_370) @[Bitwise.scala 102:21] + node _T_372 = shr(_T_368, 8) @[Bitwise.scala 103:21] + node _T_373 = and(_T_372, _T_371) @[Bitwise.scala 103:31] + node _T_374 = bits(_T_368, 55, 0) @[Bitwise.scala 103:46] + node _T_375 = shl(_T_374, 8) @[Bitwise.scala 103:65] + node _T_376 = not(_T_371) @[Bitwise.scala 103:77] + node _T_377 = and(_T_375, _T_376) @[Bitwise.scala 103:75] + node _T_378 = or(_T_373, _T_377) @[Bitwise.scala 103:39] + node _T_379 = bits(_T_371, 59, 0) @[Bitwise.scala 102:28] + node _T_380 = shl(_T_379, 4) @[Bitwise.scala 102:47] + node _T_381 = xor(_T_371, _T_380) @[Bitwise.scala 102:21] + node _T_382 = shr(_T_378, 4) @[Bitwise.scala 103:21] + node _T_383 = and(_T_382, _T_381) @[Bitwise.scala 103:31] + node _T_384 = bits(_T_378, 59, 0) @[Bitwise.scala 103:46] + node _T_385 = shl(_T_384, 4) @[Bitwise.scala 103:65] + node _T_386 = not(_T_381) @[Bitwise.scala 103:77] + node _T_387 = and(_T_385, _T_386) @[Bitwise.scala 103:75] + node _T_388 = or(_T_383, _T_387) @[Bitwise.scala 103:39] + node _T_389 = bits(_T_381, 61, 0) @[Bitwise.scala 102:28] + node _T_390 = shl(_T_389, 2) @[Bitwise.scala 102:47] + node _T_391 = xor(_T_381, _T_390) @[Bitwise.scala 102:21] + node _T_392 = shr(_T_388, 2) @[Bitwise.scala 103:21] + node _T_393 = and(_T_392, _T_391) @[Bitwise.scala 103:31] + node _T_394 = bits(_T_388, 61, 0) @[Bitwise.scala 103:46] + node _T_395 = shl(_T_394, 2) @[Bitwise.scala 103:65] + node _T_396 = not(_T_391) @[Bitwise.scala 103:77] + node _T_397 = and(_T_395, _T_396) @[Bitwise.scala 103:75] + node _T_398 = or(_T_393, _T_397) @[Bitwise.scala 103:39] + node _T_399 = bits(_T_391, 62, 0) @[Bitwise.scala 102:28] + node _T_400 = shl(_T_399, 1) @[Bitwise.scala 102:47] + node _T_401 = xor(_T_391, _T_400) @[Bitwise.scala 102:21] + node _T_402 = shr(_T_398, 1) @[Bitwise.scala 103:21] + node _T_403 = and(_T_402, _T_401) @[Bitwise.scala 103:31] + node _T_404 = bits(_T_398, 62, 0) @[Bitwise.scala 103:46] + node _T_405 = shl(_T_404, 1) @[Bitwise.scala 103:65] + node _T_406 = not(_T_401) @[Bitwise.scala 103:77] + node _T_407 = and(_T_405, _T_406) @[Bitwise.scala 103:75] + node _T_408 = or(_T_403, _T_407) @[Bitwise.scala 103:39] + lsu_rdata_corr_m <= _T_408 @[lsu_dccm_ctl.scala 155:28] + node _T_409 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_410 = bits(_T_409, 0, 0) @[lsu_dccm_ctl.scala 156:134] + node _T_411 = bits(_T_410, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_412 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_413 = bits(_T_412, 7, 0) @[lsu_dccm_ctl.scala 156:196] + node _T_414 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_415 = bits(picm_rd_data_m, 7, 0) @[lsu_dccm_ctl.scala 156:253] + node _T_416 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_417 = mux(_T_416, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_418 = bits(dccm_rdata_m, 7, 0) @[lsu_dccm_ctl.scala 156:308] + node _T_419 = and(_T_417, _T_418) @[lsu_dccm_ctl.scala 156:294] + node _T_420 = mux(_T_414, _T_415, _T_419) @[lsu_dccm_ctl.scala 156:214] + node _T_421 = mux(_T_411, _T_413, _T_420) @[lsu_dccm_ctl.scala 156:78] + node _T_422 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_423 = xor(UInt<8>("h0ff"), _T_422) @[Bitwise.scala 102:21] + node _T_424 = shr(_T_421, 4) @[Bitwise.scala 103:21] + node _T_425 = and(_T_424, _T_423) @[Bitwise.scala 103:31] + node _T_426 = bits(_T_421, 3, 0) @[Bitwise.scala 103:46] + node _T_427 = shl(_T_426, 4) @[Bitwise.scala 103:65] + node _T_428 = not(_T_423) @[Bitwise.scala 103:77] + node _T_429 = and(_T_427, _T_428) @[Bitwise.scala 103:75] + node _T_430 = or(_T_425, _T_429) @[Bitwise.scala 103:39] + node _T_431 = bits(_T_423, 5, 0) @[Bitwise.scala 102:28] + node _T_432 = shl(_T_431, 2) @[Bitwise.scala 102:47] + node _T_433 = xor(_T_423, _T_432) @[Bitwise.scala 102:21] + node _T_434 = shr(_T_430, 2) @[Bitwise.scala 103:21] + node _T_435 = and(_T_434, _T_433) @[Bitwise.scala 103:31] + node _T_436 = bits(_T_430, 5, 0) @[Bitwise.scala 103:46] + node _T_437 = shl(_T_436, 2) @[Bitwise.scala 103:65] + node _T_438 = not(_T_433) @[Bitwise.scala 103:77] + node _T_439 = and(_T_437, _T_438) @[Bitwise.scala 103:75] + node _T_440 = or(_T_435, _T_439) @[Bitwise.scala 103:39] + node _T_441 = bits(_T_433, 6, 0) @[Bitwise.scala 102:28] + node _T_442 = shl(_T_441, 1) @[Bitwise.scala 102:47] + node _T_443 = xor(_T_433, _T_442) @[Bitwise.scala 102:21] + node _T_444 = shr(_T_440, 1) @[Bitwise.scala 103:21] + node _T_445 = and(_T_444, _T_443) @[Bitwise.scala 103:31] + node _T_446 = bits(_T_440, 6, 0) @[Bitwise.scala 103:46] + node _T_447 = shl(_T_446, 1) @[Bitwise.scala 103:65] + node _T_448 = not(_T_443) @[Bitwise.scala 103:77] + node _T_449 = and(_T_447, _T_448) @[Bitwise.scala 103:75] + node _T_450 = or(_T_445, _T_449) @[Bitwise.scala 103:39] + node _T_451 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_452 = bits(_T_451, 1, 1) @[lsu_dccm_ctl.scala 156:134] + node _T_453 = bits(_T_452, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_454 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_455 = bits(_T_454, 15, 8) @[lsu_dccm_ctl.scala 156:196] + node _T_456 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_457 = bits(picm_rd_data_m, 15, 8) @[lsu_dccm_ctl.scala 156:253] + node _T_458 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_459 = mux(_T_458, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_460 = bits(dccm_rdata_m, 15, 8) @[lsu_dccm_ctl.scala 156:308] + node _T_461 = and(_T_459, _T_460) @[lsu_dccm_ctl.scala 156:294] + node _T_462 = mux(_T_456, _T_457, _T_461) @[lsu_dccm_ctl.scala 156:214] + node _T_463 = mux(_T_453, _T_455, _T_462) @[lsu_dccm_ctl.scala 156:78] + node _T_464 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_465 = xor(UInt<8>("h0ff"), _T_464) @[Bitwise.scala 102:21] + node _T_466 = shr(_T_463, 4) @[Bitwise.scala 103:21] + node _T_467 = and(_T_466, _T_465) @[Bitwise.scala 103:31] + node _T_468 = bits(_T_463, 3, 0) @[Bitwise.scala 103:46] + node _T_469 = shl(_T_468, 4) @[Bitwise.scala 103:65] + node _T_470 = not(_T_465) @[Bitwise.scala 103:77] + node _T_471 = and(_T_469, _T_470) @[Bitwise.scala 103:75] + node _T_472 = or(_T_467, _T_471) @[Bitwise.scala 103:39] + node _T_473 = bits(_T_465, 5, 0) @[Bitwise.scala 102:28] + node _T_474 = shl(_T_473, 2) @[Bitwise.scala 102:47] + node _T_475 = xor(_T_465, _T_474) @[Bitwise.scala 102:21] + node _T_476 = shr(_T_472, 2) @[Bitwise.scala 103:21] + node _T_477 = and(_T_476, _T_475) @[Bitwise.scala 103:31] + node _T_478 = bits(_T_472, 5, 0) @[Bitwise.scala 103:46] + node _T_479 = shl(_T_478, 2) @[Bitwise.scala 103:65] + node _T_480 = not(_T_475) @[Bitwise.scala 103:77] + node _T_481 = and(_T_479, _T_480) @[Bitwise.scala 103:75] + node _T_482 = or(_T_477, _T_481) @[Bitwise.scala 103:39] + node _T_483 = bits(_T_475, 6, 0) @[Bitwise.scala 102:28] + node _T_484 = shl(_T_483, 1) @[Bitwise.scala 102:47] + node _T_485 = xor(_T_475, _T_484) @[Bitwise.scala 102:21] + node _T_486 = shr(_T_482, 1) @[Bitwise.scala 103:21] + node _T_487 = and(_T_486, _T_485) @[Bitwise.scala 103:31] + node _T_488 = bits(_T_482, 6, 0) @[Bitwise.scala 103:46] + node _T_489 = shl(_T_488, 1) @[Bitwise.scala 103:65] + node _T_490 = not(_T_485) @[Bitwise.scala 103:77] + node _T_491 = and(_T_489, _T_490) @[Bitwise.scala 103:75] + node _T_492 = or(_T_487, _T_491) @[Bitwise.scala 103:39] + node _T_493 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_494 = bits(_T_493, 2, 2) @[lsu_dccm_ctl.scala 156:134] + node _T_495 = bits(_T_494, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_496 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_497 = bits(_T_496, 23, 16) @[lsu_dccm_ctl.scala 156:196] + node _T_498 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_499 = bits(picm_rd_data_m, 23, 16) @[lsu_dccm_ctl.scala 156:253] + node _T_500 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_501 = mux(_T_500, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_502 = bits(dccm_rdata_m, 23, 16) @[lsu_dccm_ctl.scala 156:308] + node _T_503 = and(_T_501, _T_502) @[lsu_dccm_ctl.scala 156:294] + node _T_504 = mux(_T_498, _T_499, _T_503) @[lsu_dccm_ctl.scala 156:214] + node _T_505 = mux(_T_495, _T_497, _T_504) @[lsu_dccm_ctl.scala 156:78] + node _T_506 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_507 = xor(UInt<8>("h0ff"), _T_506) @[Bitwise.scala 102:21] + node _T_508 = shr(_T_505, 4) @[Bitwise.scala 103:21] + node _T_509 = and(_T_508, _T_507) @[Bitwise.scala 103:31] + node _T_510 = bits(_T_505, 3, 0) @[Bitwise.scala 103:46] + node _T_511 = shl(_T_510, 4) @[Bitwise.scala 103:65] + node _T_512 = not(_T_507) @[Bitwise.scala 103:77] + node _T_513 = and(_T_511, _T_512) @[Bitwise.scala 103:75] + node _T_514 = or(_T_509, _T_513) @[Bitwise.scala 103:39] + node _T_515 = bits(_T_507, 5, 0) @[Bitwise.scala 102:28] + node _T_516 = shl(_T_515, 2) @[Bitwise.scala 102:47] + node _T_517 = xor(_T_507, _T_516) @[Bitwise.scala 102:21] + node _T_518 = shr(_T_514, 2) @[Bitwise.scala 103:21] + node _T_519 = and(_T_518, _T_517) @[Bitwise.scala 103:31] + node _T_520 = bits(_T_514, 5, 0) @[Bitwise.scala 103:46] + node _T_521 = shl(_T_520, 2) @[Bitwise.scala 103:65] + node _T_522 = not(_T_517) @[Bitwise.scala 103:77] + node _T_523 = and(_T_521, _T_522) @[Bitwise.scala 103:75] + node _T_524 = or(_T_519, _T_523) @[Bitwise.scala 103:39] + node _T_525 = bits(_T_517, 6, 0) @[Bitwise.scala 102:28] + node _T_526 = shl(_T_525, 1) @[Bitwise.scala 102:47] + node _T_527 = xor(_T_517, _T_526) @[Bitwise.scala 102:21] + node _T_528 = shr(_T_524, 1) @[Bitwise.scala 103:21] + node _T_529 = and(_T_528, _T_527) @[Bitwise.scala 103:31] + node _T_530 = bits(_T_524, 6, 0) @[Bitwise.scala 103:46] + node _T_531 = shl(_T_530, 1) @[Bitwise.scala 103:65] + node _T_532 = not(_T_527) @[Bitwise.scala 103:77] + node _T_533 = and(_T_531, _T_532) @[Bitwise.scala 103:75] + node _T_534 = or(_T_529, _T_533) @[Bitwise.scala 103:39] + node _T_535 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_536 = bits(_T_535, 3, 3) @[lsu_dccm_ctl.scala 156:134] + node _T_537 = bits(_T_536, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_538 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_539 = bits(_T_538, 31, 24) @[lsu_dccm_ctl.scala 156:196] + node _T_540 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_541 = bits(picm_rd_data_m, 31, 24) @[lsu_dccm_ctl.scala 156:253] + node _T_542 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_543 = mux(_T_542, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_544 = bits(dccm_rdata_m, 31, 24) @[lsu_dccm_ctl.scala 156:308] + node _T_545 = and(_T_543, _T_544) @[lsu_dccm_ctl.scala 156:294] + node _T_546 = mux(_T_540, _T_541, _T_545) @[lsu_dccm_ctl.scala 156:214] + node _T_547 = mux(_T_537, _T_539, _T_546) @[lsu_dccm_ctl.scala 156:78] + node _T_548 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_549 = xor(UInt<8>("h0ff"), _T_548) @[Bitwise.scala 102:21] + node _T_550 = shr(_T_547, 4) @[Bitwise.scala 103:21] + node _T_551 = and(_T_550, _T_549) @[Bitwise.scala 103:31] + node _T_552 = bits(_T_547, 3, 0) @[Bitwise.scala 103:46] + node _T_553 = shl(_T_552, 4) @[Bitwise.scala 103:65] + node _T_554 = not(_T_549) @[Bitwise.scala 103:77] + node _T_555 = and(_T_553, _T_554) @[Bitwise.scala 103:75] + node _T_556 = or(_T_551, _T_555) @[Bitwise.scala 103:39] + node _T_557 = bits(_T_549, 5, 0) @[Bitwise.scala 102:28] + node _T_558 = shl(_T_557, 2) @[Bitwise.scala 102:47] + node _T_559 = xor(_T_549, _T_558) @[Bitwise.scala 102:21] + node _T_560 = shr(_T_556, 2) @[Bitwise.scala 103:21] + node _T_561 = and(_T_560, _T_559) @[Bitwise.scala 103:31] + node _T_562 = bits(_T_556, 5, 0) @[Bitwise.scala 103:46] + node _T_563 = shl(_T_562, 2) @[Bitwise.scala 103:65] + node _T_564 = not(_T_559) @[Bitwise.scala 103:77] + node _T_565 = and(_T_563, _T_564) @[Bitwise.scala 103:75] + node _T_566 = or(_T_561, _T_565) @[Bitwise.scala 103:39] + node _T_567 = bits(_T_559, 6, 0) @[Bitwise.scala 102:28] + node _T_568 = shl(_T_567, 1) @[Bitwise.scala 102:47] + node _T_569 = xor(_T_559, _T_568) @[Bitwise.scala 102:21] + node _T_570 = shr(_T_566, 1) @[Bitwise.scala 103:21] + node _T_571 = and(_T_570, _T_569) @[Bitwise.scala 103:31] + node _T_572 = bits(_T_566, 6, 0) @[Bitwise.scala 103:46] + node _T_573 = shl(_T_572, 1) @[Bitwise.scala 103:65] + node _T_574 = not(_T_569) @[Bitwise.scala 103:77] + node _T_575 = and(_T_573, _T_574) @[Bitwise.scala 103:75] + node _T_576 = or(_T_571, _T_575) @[Bitwise.scala 103:39] + node _T_577 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_578 = bits(_T_577, 4, 4) @[lsu_dccm_ctl.scala 156:134] + node _T_579 = bits(_T_578, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_580 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_581 = bits(_T_580, 39, 32) @[lsu_dccm_ctl.scala 156:196] + node _T_582 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_583 = bits(picm_rd_data_m, 39, 32) @[lsu_dccm_ctl.scala 156:253] + node _T_584 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_585 = mux(_T_584, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_586 = bits(dccm_rdata_m, 39, 32) @[lsu_dccm_ctl.scala 156:308] + node _T_587 = and(_T_585, _T_586) @[lsu_dccm_ctl.scala 156:294] + node _T_588 = mux(_T_582, _T_583, _T_587) @[lsu_dccm_ctl.scala 156:214] + node _T_589 = mux(_T_579, _T_581, _T_588) @[lsu_dccm_ctl.scala 156:78] + node _T_590 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_591 = xor(UInt<8>("h0ff"), _T_590) @[Bitwise.scala 102:21] + node _T_592 = shr(_T_589, 4) @[Bitwise.scala 103:21] + node _T_593 = and(_T_592, _T_591) @[Bitwise.scala 103:31] + node _T_594 = bits(_T_589, 3, 0) @[Bitwise.scala 103:46] + node _T_595 = shl(_T_594, 4) @[Bitwise.scala 103:65] + node _T_596 = not(_T_591) @[Bitwise.scala 103:77] + node _T_597 = and(_T_595, _T_596) @[Bitwise.scala 103:75] + node _T_598 = or(_T_593, _T_597) @[Bitwise.scala 103:39] + node _T_599 = bits(_T_591, 5, 0) @[Bitwise.scala 102:28] + node _T_600 = shl(_T_599, 2) @[Bitwise.scala 102:47] + node _T_601 = xor(_T_591, _T_600) @[Bitwise.scala 102:21] + node _T_602 = shr(_T_598, 2) @[Bitwise.scala 103:21] + node _T_603 = and(_T_602, _T_601) @[Bitwise.scala 103:31] + node _T_604 = bits(_T_598, 5, 0) @[Bitwise.scala 103:46] + node _T_605 = shl(_T_604, 2) @[Bitwise.scala 103:65] + node _T_606 = not(_T_601) @[Bitwise.scala 103:77] + node _T_607 = and(_T_605, _T_606) @[Bitwise.scala 103:75] + node _T_608 = or(_T_603, _T_607) @[Bitwise.scala 103:39] + node _T_609 = bits(_T_601, 6, 0) @[Bitwise.scala 102:28] + node _T_610 = shl(_T_609, 1) @[Bitwise.scala 102:47] + node _T_611 = xor(_T_601, _T_610) @[Bitwise.scala 102:21] + node _T_612 = shr(_T_608, 1) @[Bitwise.scala 103:21] + node _T_613 = and(_T_612, _T_611) @[Bitwise.scala 103:31] + node _T_614 = bits(_T_608, 6, 0) @[Bitwise.scala 103:46] + node _T_615 = shl(_T_614, 1) @[Bitwise.scala 103:65] + node _T_616 = not(_T_611) @[Bitwise.scala 103:77] + node _T_617 = and(_T_615, _T_616) @[Bitwise.scala 103:75] + node _T_618 = or(_T_613, _T_617) @[Bitwise.scala 103:39] + node _T_619 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_620 = bits(_T_619, 5, 5) @[lsu_dccm_ctl.scala 156:134] + node _T_621 = bits(_T_620, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_622 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_623 = bits(_T_622, 47, 40) @[lsu_dccm_ctl.scala 156:196] + node _T_624 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_625 = bits(picm_rd_data_m, 47, 40) @[lsu_dccm_ctl.scala 156:253] + node _T_626 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(dccm_rdata_m, 47, 40) @[lsu_dccm_ctl.scala 156:308] + node _T_629 = and(_T_627, _T_628) @[lsu_dccm_ctl.scala 156:294] + node _T_630 = mux(_T_624, _T_625, _T_629) @[lsu_dccm_ctl.scala 156:214] + node _T_631 = mux(_T_621, _T_623, _T_630) @[lsu_dccm_ctl.scala 156:78] + node _T_632 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_633 = xor(UInt<8>("h0ff"), _T_632) @[Bitwise.scala 102:21] + node _T_634 = shr(_T_631, 4) @[Bitwise.scala 103:21] + node _T_635 = and(_T_634, _T_633) @[Bitwise.scala 103:31] + node _T_636 = bits(_T_631, 3, 0) @[Bitwise.scala 103:46] + node _T_637 = shl(_T_636, 4) @[Bitwise.scala 103:65] + node _T_638 = not(_T_633) @[Bitwise.scala 103:77] + node _T_639 = and(_T_637, _T_638) @[Bitwise.scala 103:75] + node _T_640 = or(_T_635, _T_639) @[Bitwise.scala 103:39] + node _T_641 = bits(_T_633, 5, 0) @[Bitwise.scala 102:28] + node _T_642 = shl(_T_641, 2) @[Bitwise.scala 102:47] + node _T_643 = xor(_T_633, _T_642) @[Bitwise.scala 102:21] + node _T_644 = shr(_T_640, 2) @[Bitwise.scala 103:21] + node _T_645 = and(_T_644, _T_643) @[Bitwise.scala 103:31] + node _T_646 = bits(_T_640, 5, 0) @[Bitwise.scala 103:46] + node _T_647 = shl(_T_646, 2) @[Bitwise.scala 103:65] + node _T_648 = not(_T_643) @[Bitwise.scala 103:77] + node _T_649 = and(_T_647, _T_648) @[Bitwise.scala 103:75] + node _T_650 = or(_T_645, _T_649) @[Bitwise.scala 103:39] + node _T_651 = bits(_T_643, 6, 0) @[Bitwise.scala 102:28] + node _T_652 = shl(_T_651, 1) @[Bitwise.scala 102:47] + node _T_653 = xor(_T_643, _T_652) @[Bitwise.scala 102:21] + node _T_654 = shr(_T_650, 1) @[Bitwise.scala 103:21] + node _T_655 = and(_T_654, _T_653) @[Bitwise.scala 103:31] + node _T_656 = bits(_T_650, 6, 0) @[Bitwise.scala 103:46] + node _T_657 = shl(_T_656, 1) @[Bitwise.scala 103:65] + node _T_658 = not(_T_653) @[Bitwise.scala 103:77] + node _T_659 = and(_T_657, _T_658) @[Bitwise.scala 103:75] + node _T_660 = or(_T_655, _T_659) @[Bitwise.scala 103:39] + node _T_661 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_662 = bits(_T_661, 6, 6) @[lsu_dccm_ctl.scala 156:134] + node _T_663 = bits(_T_662, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_664 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_665 = bits(_T_664, 55, 48) @[lsu_dccm_ctl.scala 156:196] + node _T_666 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_667 = bits(picm_rd_data_m, 55, 48) @[lsu_dccm_ctl.scala 156:253] + node _T_668 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_669 = mux(_T_668, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_670 = bits(dccm_rdata_m, 55, 48) @[lsu_dccm_ctl.scala 156:308] + node _T_671 = and(_T_669, _T_670) @[lsu_dccm_ctl.scala 156:294] + node _T_672 = mux(_T_666, _T_667, _T_671) @[lsu_dccm_ctl.scala 156:214] + node _T_673 = mux(_T_663, _T_665, _T_672) @[lsu_dccm_ctl.scala 156:78] + node _T_674 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_675 = xor(UInt<8>("h0ff"), _T_674) @[Bitwise.scala 102:21] + node _T_676 = shr(_T_673, 4) @[Bitwise.scala 103:21] + node _T_677 = and(_T_676, _T_675) @[Bitwise.scala 103:31] + node _T_678 = bits(_T_673, 3, 0) @[Bitwise.scala 103:46] + node _T_679 = shl(_T_678, 4) @[Bitwise.scala 103:65] + node _T_680 = not(_T_675) @[Bitwise.scala 103:77] + node _T_681 = and(_T_679, _T_680) @[Bitwise.scala 103:75] + node _T_682 = or(_T_677, _T_681) @[Bitwise.scala 103:39] + node _T_683 = bits(_T_675, 5, 0) @[Bitwise.scala 102:28] + node _T_684 = shl(_T_683, 2) @[Bitwise.scala 102:47] + node _T_685 = xor(_T_675, _T_684) @[Bitwise.scala 102:21] + node _T_686 = shr(_T_682, 2) @[Bitwise.scala 103:21] + node _T_687 = and(_T_686, _T_685) @[Bitwise.scala 103:31] + node _T_688 = bits(_T_682, 5, 0) @[Bitwise.scala 103:46] + node _T_689 = shl(_T_688, 2) @[Bitwise.scala 103:65] + node _T_690 = not(_T_685) @[Bitwise.scala 103:77] + node _T_691 = and(_T_689, _T_690) @[Bitwise.scala 103:75] + node _T_692 = or(_T_687, _T_691) @[Bitwise.scala 103:39] + node _T_693 = bits(_T_685, 6, 0) @[Bitwise.scala 102:28] + node _T_694 = shl(_T_693, 1) @[Bitwise.scala 102:47] + node _T_695 = xor(_T_685, _T_694) @[Bitwise.scala 102:21] + node _T_696 = shr(_T_692, 1) @[Bitwise.scala 103:21] + node _T_697 = and(_T_696, _T_695) @[Bitwise.scala 103:31] + node _T_698 = bits(_T_692, 6, 0) @[Bitwise.scala 103:46] + node _T_699 = shl(_T_698, 1) @[Bitwise.scala 103:65] + node _T_700 = not(_T_695) @[Bitwise.scala 103:77] + node _T_701 = and(_T_699, _T_700) @[Bitwise.scala 103:75] + node _T_702 = or(_T_697, _T_701) @[Bitwise.scala 103:39] + node _T_703 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_704 = bits(_T_703, 7, 7) @[lsu_dccm_ctl.scala 156:134] + node _T_705 = bits(_T_704, 0, 0) @[lsu_dccm_ctl.scala 156:139] + node _T_706 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_707 = bits(_T_706, 63, 56) @[lsu_dccm_ctl.scala 156:196] + node _T_708 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232] + node _T_709 = bits(picm_rd_data_m, 63, 56) @[lsu_dccm_ctl.scala 156:253] + node _T_710 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(dccm_rdata_m, 63, 56) @[lsu_dccm_ctl.scala 156:308] + node _T_713 = and(_T_711, _T_712) @[lsu_dccm_ctl.scala 156:294] + node _T_714 = mux(_T_708, _T_709, _T_713) @[lsu_dccm_ctl.scala 156:214] + node _T_715 = mux(_T_705, _T_707, _T_714) @[lsu_dccm_ctl.scala 156:78] + node _T_716 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_717 = xor(UInt<8>("h0ff"), _T_716) @[Bitwise.scala 102:21] + node _T_718 = shr(_T_715, 4) @[Bitwise.scala 103:21] + node _T_719 = and(_T_718, _T_717) @[Bitwise.scala 103:31] + node _T_720 = bits(_T_715, 3, 0) @[Bitwise.scala 103:46] + node _T_721 = shl(_T_720, 4) @[Bitwise.scala 103:65] + node _T_722 = not(_T_717) @[Bitwise.scala 103:77] + node _T_723 = and(_T_721, _T_722) @[Bitwise.scala 103:75] + node _T_724 = or(_T_719, _T_723) @[Bitwise.scala 103:39] + node _T_725 = bits(_T_717, 5, 0) @[Bitwise.scala 102:28] + node _T_726 = shl(_T_725, 2) @[Bitwise.scala 102:47] + node _T_727 = xor(_T_717, _T_726) @[Bitwise.scala 102:21] + node _T_728 = shr(_T_724, 2) @[Bitwise.scala 103:21] + node _T_729 = and(_T_728, _T_727) @[Bitwise.scala 103:31] + node _T_730 = bits(_T_724, 5, 0) @[Bitwise.scala 103:46] + node _T_731 = shl(_T_730, 2) @[Bitwise.scala 103:65] + node _T_732 = not(_T_727) @[Bitwise.scala 103:77] + node _T_733 = and(_T_731, _T_732) @[Bitwise.scala 103:75] + node _T_734 = or(_T_729, _T_733) @[Bitwise.scala 103:39] + node _T_735 = bits(_T_727, 6, 0) @[Bitwise.scala 102:28] + node _T_736 = shl(_T_735, 1) @[Bitwise.scala 102:47] + node _T_737 = xor(_T_727, _T_736) @[Bitwise.scala 102:21] + node _T_738 = shr(_T_734, 1) @[Bitwise.scala 103:21] + node _T_739 = and(_T_738, _T_737) @[Bitwise.scala 103:31] + node _T_740 = bits(_T_734, 6, 0) @[Bitwise.scala 103:46] + node _T_741 = shl(_T_740, 1) @[Bitwise.scala 103:65] + node _T_742 = not(_T_737) @[Bitwise.scala 103:77] + node _T_743 = and(_T_741, _T_742) @[Bitwise.scala 103:75] + node _T_744 = or(_T_739, _T_743) @[Bitwise.scala 103:39] + wire _T_745 : UInt<8>[8] @[lsu_dccm_ctl.scala 156:62] + _T_745[0] <= _T_450 @[lsu_dccm_ctl.scala 156:62] + _T_745[1] <= _T_492 @[lsu_dccm_ctl.scala 156:62] + _T_745[2] <= _T_534 @[lsu_dccm_ctl.scala 156:62] + _T_745[3] <= _T_576 @[lsu_dccm_ctl.scala 156:62] + _T_745[4] <= _T_618 @[lsu_dccm_ctl.scala 156:62] + _T_745[5] <= _T_660 @[lsu_dccm_ctl.scala 156:62] + _T_745[6] <= _T_702 @[lsu_dccm_ctl.scala 156:62] + _T_745[7] <= _T_744 @[lsu_dccm_ctl.scala 156:62] + node _T_746 = cat(_T_745[6], _T_745[7]) @[Cat.scala 29:58] + node _T_747 = cat(_T_745[4], _T_745[5]) @[Cat.scala 29:58] + node _T_748 = cat(_T_747, _T_746) @[Cat.scala 29:58] + node _T_749 = cat(_T_745[2], _T_745[3]) @[Cat.scala 29:58] + node _T_750 = cat(_T_745[0], _T_745[1]) @[Cat.scala 29:58] + node _T_751 = cat(_T_750, _T_749) @[Cat.scala 29:58] + node _T_752 = cat(_T_751, _T_748) @[Cat.scala 29:58] + node _T_753 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47] + node _T_754 = xor(UInt<64>("h0ffffffffffffffff"), _T_753) @[Bitwise.scala 102:21] + node _T_755 = shr(_T_752, 32) @[Bitwise.scala 103:21] + node _T_756 = and(_T_755, _T_754) @[Bitwise.scala 103:31] + node _T_757 = bits(_T_752, 31, 0) @[Bitwise.scala 103:46] + node _T_758 = shl(_T_757, 32) @[Bitwise.scala 103:65] + node _T_759 = not(_T_754) @[Bitwise.scala 103:77] + node _T_760 = and(_T_758, _T_759) @[Bitwise.scala 103:75] + node _T_761 = or(_T_756, _T_760) @[Bitwise.scala 103:39] + node _T_762 = bits(_T_754, 47, 0) @[Bitwise.scala 102:28] + node _T_763 = shl(_T_762, 16) @[Bitwise.scala 102:47] + node _T_764 = xor(_T_754, _T_763) @[Bitwise.scala 102:21] + node _T_765 = shr(_T_761, 16) @[Bitwise.scala 103:21] + node _T_766 = and(_T_765, _T_764) @[Bitwise.scala 103:31] + node _T_767 = bits(_T_761, 47, 0) @[Bitwise.scala 103:46] + node _T_768 = shl(_T_767, 16) @[Bitwise.scala 103:65] + node _T_769 = not(_T_764) @[Bitwise.scala 103:77] + node _T_770 = and(_T_768, _T_769) @[Bitwise.scala 103:75] + node _T_771 = or(_T_766, _T_770) @[Bitwise.scala 103:39] + node _T_772 = bits(_T_764, 55, 0) @[Bitwise.scala 102:28] + node _T_773 = shl(_T_772, 8) @[Bitwise.scala 102:47] + node _T_774 = xor(_T_764, _T_773) @[Bitwise.scala 102:21] + node _T_775 = shr(_T_771, 8) @[Bitwise.scala 103:21] + node _T_776 = and(_T_775, _T_774) @[Bitwise.scala 103:31] + node _T_777 = bits(_T_771, 55, 0) @[Bitwise.scala 103:46] + node _T_778 = shl(_T_777, 8) @[Bitwise.scala 103:65] + node _T_779 = not(_T_774) @[Bitwise.scala 103:77] + node _T_780 = and(_T_778, _T_779) @[Bitwise.scala 103:75] + node _T_781 = or(_T_776, _T_780) @[Bitwise.scala 103:39] + node _T_782 = bits(_T_774, 59, 0) @[Bitwise.scala 102:28] + node _T_783 = shl(_T_782, 4) @[Bitwise.scala 102:47] + node _T_784 = xor(_T_774, _T_783) @[Bitwise.scala 102:21] + node _T_785 = shr(_T_781, 4) @[Bitwise.scala 103:21] + node _T_786 = and(_T_785, _T_784) @[Bitwise.scala 103:31] + node _T_787 = bits(_T_781, 59, 0) @[Bitwise.scala 103:46] + node _T_788 = shl(_T_787, 4) @[Bitwise.scala 103:65] + node _T_789 = not(_T_784) @[Bitwise.scala 103:77] + node _T_790 = and(_T_788, _T_789) @[Bitwise.scala 103:75] + node _T_791 = or(_T_786, _T_790) @[Bitwise.scala 103:39] + node _T_792 = bits(_T_784, 61, 0) @[Bitwise.scala 102:28] + node _T_793 = shl(_T_792, 2) @[Bitwise.scala 102:47] + node _T_794 = xor(_T_784, _T_793) @[Bitwise.scala 102:21] + node _T_795 = shr(_T_791, 2) @[Bitwise.scala 103:21] + node _T_796 = and(_T_795, _T_794) @[Bitwise.scala 103:31] + node _T_797 = bits(_T_791, 61, 0) @[Bitwise.scala 103:46] + node _T_798 = shl(_T_797, 2) @[Bitwise.scala 103:65] + node _T_799 = not(_T_794) @[Bitwise.scala 103:77] + node _T_800 = and(_T_798, _T_799) @[Bitwise.scala 103:75] + node _T_801 = or(_T_796, _T_800) @[Bitwise.scala 103:39] + node _T_802 = bits(_T_794, 62, 0) @[Bitwise.scala 102:28] + node _T_803 = shl(_T_802, 1) @[Bitwise.scala 102:47] + node _T_804 = xor(_T_794, _T_803) @[Bitwise.scala 102:21] + node _T_805 = shr(_T_801, 1) @[Bitwise.scala 103:21] + node _T_806 = and(_T_805, _T_804) @[Bitwise.scala 103:31] + node _T_807 = bits(_T_801, 62, 0) @[Bitwise.scala 103:46] + node _T_808 = shl(_T_807, 1) @[Bitwise.scala 103:65] + node _T_809 = not(_T_804) @[Bitwise.scala 103:77] + node _T_810 = and(_T_808, _T_809) @[Bitwise.scala 103:75] + node _T_811 = or(_T_806, _T_810) @[Bitwise.scala 103:39] + lsu_rdata_m <= _T_811 @[lsu_dccm_ctl.scala 156:28] + node _T_812 = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.load) @[lsu_dccm_ctl.scala 157:78] + node _T_813 = or(io.addr_in_pic_m, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 157:123] + node _T_814 = and(_T_812, _T_813) @[lsu_dccm_ctl.scala 157:103] + node _T_815 = or(_T_814, io.clk_override) @[lsu_dccm_ctl.scala 157:145] + node _T_816 = bits(_T_815, 0, 0) @[lib.scala 8:44] + node _T_817 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr of rvclkhdr_4 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_816 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_818 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_816 : @[Reg.scala 28:19] + _T_818 <= lsu_ld_data_corr_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.lsu_ld_data_corr_r <= _T_818 @[lsu_dccm_ctl.scala 157:28] + node _T_819 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 158:63] + node _T_820 = mul(UInt<4>("h08"), _T_819) @[lsu_dccm_ctl.scala 158:49] + node _T_821 = dshr(lsu_rdata_m, _T_820) @[lsu_dccm_ctl.scala 158:43] + io.lsu_ld_data_m <= _T_821 @[lsu_dccm_ctl.scala 158:28] + node _T_822 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 159:68] + node _T_823 = mul(UInt<4>("h08"), _T_822) @[lsu_dccm_ctl.scala 159:54] + node _T_824 = dshr(lsu_rdata_corr_m, _T_823) @[lsu_dccm_ctl.scala 159:48] + lsu_ld_data_corr_m <= _T_824 @[lsu_dccm_ctl.scala 159:28] + node _T_825 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 163:44] + node _T_826 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 163:77] + node _T_827 = eq(_T_825, _T_826) @[lsu_dccm_ctl.scala 163:60] + node _T_828 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 163:117] + node _T_829 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 163:150] + node _T_830 = eq(_T_828, _T_829) @[lsu_dccm_ctl.scala 163:133] + node _T_831 = or(_T_827, _T_830) @[lsu_dccm_ctl.scala 163:101] + node _T_832 = and(_T_831, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 163:175] + node _T_833 = and(_T_832, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 163:196] + node _T_834 = and(_T_833, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 163:222] + node _T_835 = and(_T_834, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 163:246] + node _T_836 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 164:21] + node _T_837 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 164:54] + node _T_838 = eq(_T_836, _T_837) @[lsu_dccm_ctl.scala 164:37] + node _T_839 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 164:94] + node _T_840 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 164:127] + node _T_841 = eq(_T_839, _T_840) @[lsu_dccm_ctl.scala 164:110] + node _T_842 = or(_T_838, _T_841) @[lsu_dccm_ctl.scala 164:78] + node _T_843 = and(_T_842, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 164:152] + node _T_844 = and(_T_843, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 164:173] + node _T_845 = and(_T_844, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 164:199] + node _T_846 = and(_T_845, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 164:223] + node kill_ecc_corr_lo_r = or(_T_835, _T_846) @[lsu_dccm_ctl.scala 163:267] + node _T_847 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 166:44] + node _T_848 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 166:77] + node _T_849 = eq(_T_847, _T_848) @[lsu_dccm_ctl.scala 166:60] + node _T_850 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 166:117] + node _T_851 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 166:150] + node _T_852 = eq(_T_850, _T_851) @[lsu_dccm_ctl.scala 166:133] + node _T_853 = or(_T_849, _T_852) @[lsu_dccm_ctl.scala 166:101] + node _T_854 = and(_T_853, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 166:175] + node _T_855 = and(_T_854, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 166:196] + node _T_856 = and(_T_855, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 166:222] + node _T_857 = and(_T_856, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 166:246] + node _T_858 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 167:21] + node _T_859 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 167:54] + node _T_860 = eq(_T_858, _T_859) @[lsu_dccm_ctl.scala 167:37] + node _T_861 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 167:94] + node _T_862 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 167:127] + node _T_863 = eq(_T_861, _T_862) @[lsu_dccm_ctl.scala 167:110] + node _T_864 = or(_T_860, _T_863) @[lsu_dccm_ctl.scala 167:78] + node _T_865 = and(_T_864, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 167:152] + node _T_866 = and(_T_865, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 167:173] + node _T_867 = and(_T_866, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 167:199] + node _T_868 = and(_T_867, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 167:223] + node kill_ecc_corr_hi_r = or(_T_857, _T_868) @[lsu_dccm_ctl.scala 166:267] + node _T_869 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_lo_r) @[lsu_dccm_ctl.scala 169:60] + node _T_870 = eq(io.lsu_raw_fwd_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 169:89] + node ld_single_ecc_error_lo_r = and(_T_869, _T_870) @[lsu_dccm_ctl.scala 169:87] + node _T_871 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 170:60] + node _T_872 = eq(io.lsu_raw_fwd_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 170:89] + node ld_single_ecc_error_hi_r = and(_T_871, _T_872) @[lsu_dccm_ctl.scala 170:87] + node _T_873 = or(ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 171:63] + node _T_874 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 171:93] + node _T_875 = and(_T_873, _T_874) @[lsu_dccm_ctl.scala 171:91] + io.ld_single_ecc_error_r <= _T_875 @[lsu_dccm_ctl.scala 171:34] + node _T_876 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 172:81] + node _T_877 = and(ld_single_ecc_error_lo_r, _T_876) @[lsu_dccm_ctl.scala 172:62] + node _T_878 = eq(kill_ecc_corr_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 172:108] + node ld_single_ecc_error_lo_r_ns = and(_T_877, _T_878) @[lsu_dccm_ctl.scala 172:106] + node _T_879 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 173:81] + node _T_880 = and(ld_single_ecc_error_hi_r, _T_879) @[lsu_dccm_ctl.scala 173:62] + node _T_881 = eq(kill_ecc_corr_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 173:108] + node ld_single_ecc_error_hi_r_ns = and(_T_880, _T_881) @[lsu_dccm_ctl.scala 173:106] + node _T_882 = or(io.lsu_pkt_d.bits.word, io.lsu_pkt_d.bits.dword) @[lsu_dccm_ctl.scala 175:125] + node _T_883 = eq(_T_882, UInt<1>("h00")) @[lsu_dccm_ctl.scala 175:100] + node _T_884 = bits(io.lsu_addr_d, 1, 0) @[lsu_dccm_ctl.scala 175:168] + node _T_885 = neq(_T_884, UInt<2>("h00")) @[lsu_dccm_ctl.scala 175:174] + node _T_886 = or(_T_883, _T_885) @[lsu_dccm_ctl.scala 175:152] + node _T_887 = and(io.lsu_pkt_d.bits.store, _T_886) @[lsu_dccm_ctl.scala 175:97] + node _T_888 = or(io.lsu_pkt_d.bits.load, _T_887) @[lsu_dccm_ctl.scala 175:70] + node _T_889 = and(io.lsu_pkt_d.valid, _T_888) @[lsu_dccm_ctl.scala 175:44] + node lsu_dccm_rden_d = and(_T_889, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 175:191] + node _T_890 = or(ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff) @[lsu_dccm_ctl.scala 178:63] + node _T_891 = eq(lsu_double_ecc_error_r_ff, UInt<1>("h00")) @[lsu_dccm_ctl.scala 178:96] + node _T_892 = and(_T_890, _T_891) @[lsu_dccm_ctl.scala 178:94] + io.ld_single_ecc_error_r_ff <= _T_892 @[lsu_dccm_ctl.scala 178:31] + node _T_893 = or(lsu_dccm_rden_d, io.dma_dccm_wen) @[lsu_dccm_ctl.scala 179:75] + node _T_894 = or(_T_893, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 179:93] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[lsu_dccm_ctl.scala 179:57] + node _T_896 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 180:44] + node _T_897 = bits(io.lsu_addr_d, 3, 2) @[lsu_dccm_ctl.scala 180:112] + node _T_898 = eq(_T_896, _T_897) @[lsu_dccm_ctl.scala 180:95] + node _T_899 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 181:25] + node _T_900 = bits(io.end_addr_d, 3, 2) @[lsu_dccm_ctl.scala 181:93] + node _T_901 = eq(_T_899, _T_900) @[lsu_dccm_ctl.scala 181:76] + node _T_902 = or(_T_898, _T_901) @[lsu_dccm_ctl.scala 180:171] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[lsu_dccm_ctl.scala 180:24] + node _T_904 = and(lsu_dccm_rden_d, _T_903) @[lsu_dccm_ctl.scala 180:22] + node _T_905 = or(_T_895, _T_904) @[lsu_dccm_ctl.scala 179:124] + node _T_906 = and(io.stbuf_reqvld_any, _T_905) @[lsu_dccm_ctl.scala 179:54] + io.lsu_stbuf_commit_any <= _T_906 @[lsu_dccm_ctl.scala 179:31] + node _T_907 = or(io.dma_dccm_wen, io.lsu_stbuf_commit_any) @[lsu_dccm_ctl.scala 185:41] + node _T_908 = or(_T_907, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 185:67] + io.dccm.wren <= _T_908 @[lsu_dccm_ctl.scala 185:22] + node _T_909 = and(lsu_dccm_rden_d, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 186:41] + io.dccm.rden <= _T_909 @[lsu_dccm_ctl.scala 186:22] + node _T_910 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 188:57] + node _T_911 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 189:36] + node _T_912 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 189:62] + node _T_913 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 189:97] + node _T_914 = mux(_T_911, _T_912, _T_913) @[lsu_dccm_ctl.scala 189:8] + node _T_915 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 190:25] + node _T_916 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 190:45] + node _T_917 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 190:78] + node _T_918 = mux(_T_915, _T_916, _T_917) @[lsu_dccm_ctl.scala 190:8] + node _T_919 = mux(_T_910, _T_914, _T_918) @[lsu_dccm_ctl.scala 188:28] + io.dccm.wr_addr_lo <= _T_919 @[lsu_dccm_ctl.scala 188:22] + node _T_920 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 192:57] + node _T_921 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 193:36] + node _T_922 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 193:63] + node _T_923 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 193:99] + node _T_924 = mux(_T_921, _T_922, _T_923) @[lsu_dccm_ctl.scala 193:8] + node _T_925 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 194:25] + node _T_926 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 194:46] + node _T_927 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 194:79] + node _T_928 = mux(_T_925, _T_926, _T_927) @[lsu_dccm_ctl.scala 194:8] + node _T_929 = mux(_T_920, _T_924, _T_928) @[lsu_dccm_ctl.scala 192:28] + io.dccm.wr_addr_hi <= _T_929 @[lsu_dccm_ctl.scala 192:22] + node _T_930 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 196:38] + io.dccm.rd_addr_lo <= _T_930 @[lsu_dccm_ctl.scala 196:22] + node _T_931 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 197:38] + io.dccm.rd_addr_hi <= _T_931 @[lsu_dccm_ctl.scala 197:22] + node _T_932 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 199:57] + node _T_933 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 200:36] + node _T_934 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 200:70] + node _T_935 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 200:110] + node _T_936 = cat(_T_934, _T_935) @[Cat.scala 29:58] + node _T_937 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 201:34] + node _T_938 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 201:74] + node _T_939 = cat(_T_937, _T_938) @[Cat.scala 29:58] + node _T_940 = mux(_T_933, _T_936, _T_939) @[lsu_dccm_ctl.scala 200:8] + node _T_941 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 202:25] + node _T_942 = bits(io.dma_dccm_wdata_ecc_lo, 6, 0) @[lsu_dccm_ctl.scala 202:60] + node _T_943 = bits(io.dma_dccm_wdata_lo, 31, 0) @[lsu_dccm_ctl.scala 202:101] + node _T_944 = cat(_T_942, _T_943) @[Cat.scala 29:58] + node _T_945 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 203:27] + node _T_946 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 203:65] + node _T_947 = cat(_T_945, _T_946) @[Cat.scala 29:58] + node _T_948 = mux(_T_941, _T_944, _T_947) @[lsu_dccm_ctl.scala 202:8] + node _T_949 = mux(_T_932, _T_940, _T_948) @[lsu_dccm_ctl.scala 199:28] + io.dccm.wr_data_lo <= _T_949 @[lsu_dccm_ctl.scala 199:22] + node _T_950 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 205:57] + node _T_951 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 206:36] + node _T_952 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 206:71] + node _T_953 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 206:111] + node _T_954 = cat(_T_952, _T_953) @[Cat.scala 29:58] + node _T_955 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 207:34] + node _T_956 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 207:74] + node _T_957 = cat(_T_955, _T_956) @[Cat.scala 29:58] + node _T_958 = mux(_T_951, _T_954, _T_957) @[lsu_dccm_ctl.scala 206:8] + node _T_959 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 208:25] + node _T_960 = bits(io.dma_dccm_wdata_ecc_hi, 6, 0) @[lsu_dccm_ctl.scala 208:61] + node _T_961 = bits(io.dma_dccm_wdata_hi, 31, 0) @[lsu_dccm_ctl.scala 208:102] + node _T_962 = cat(_T_960, _T_961) @[Cat.scala 29:58] + node _T_963 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 209:27] + node _T_964 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 209:65] + node _T_965 = cat(_T_963, _T_964) @[Cat.scala 29:58] + node _T_966 = mux(_T_959, _T_962, _T_965) @[lsu_dccm_ctl.scala 208:8] + node _T_967 = mux(_T_950, _T_958, _T_966) @[lsu_dccm_ctl.scala 205:28] + io.dccm.wr_data_hi <= _T_967 @[lsu_dccm_ctl.scala 205:22] + node _T_968 = bits(io.lsu_pkt_m.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_969 = mux(_T_968, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_970 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[Bitwise.scala 72:15] + node _T_971 = mux(_T_970, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_972 = and(_T_971, UInt<4>("h01")) @[lsu_dccm_ctl.scala 212:94] + node _T_973 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_974 = mux(_T_973, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_975 = and(_T_974, UInt<4>("h03")) @[lsu_dccm_ctl.scala 213:38] + node _T_976 = or(_T_972, _T_975) @[lsu_dccm_ctl.scala 212:107] + node _T_977 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_978 = mux(_T_977, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_979 = and(_T_978, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 214:38] + node _T_980 = or(_T_976, _T_979) @[lsu_dccm_ctl.scala 213:51] + node store_byteen_m = and(_T_969, _T_980) @[lsu_dccm_ctl.scala 212:58] + node _T_981 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_982 = mux(_T_981, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_983 = bits(io.lsu_pkt_r.bits.by, 0, 0) @[Bitwise.scala 72:15] + node _T_984 = mux(_T_983, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_985 = and(_T_984, UInt<4>("h01")) @[lsu_dccm_ctl.scala 216:94] + node _T_986 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_987 = mux(_T_986, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_988 = and(_T_987, UInt<4>("h03")) @[lsu_dccm_ctl.scala 217:38] + node _T_989 = or(_T_985, _T_988) @[lsu_dccm_ctl.scala 216:107] + node _T_990 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_991 = mux(_T_990, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_992 = and(_T_991, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 218:38] + node _T_993 = or(_T_989, _T_992) @[lsu_dccm_ctl.scala 217:51] + node store_byteen_r = and(_T_982, _T_993) @[lsu_dccm_ctl.scala 216:58] + wire store_byteen_ext_m : UInt<8> + store_byteen_ext_m <= UInt<1>("h00") + node _T_994 = bits(store_byteen_m, 3, 0) @[lsu_dccm_ctl.scala 220:39] + node _T_995 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 220:61] + node _T_996 = dshl(_T_994, _T_995) @[lsu_dccm_ctl.scala 220:45] + store_byteen_ext_m <= _T_996 @[lsu_dccm_ctl.scala 220:22] + wire store_byteen_ext_r : UInt<8> + store_byteen_ext_r <= UInt<1>("h00") + node _T_997 = bits(store_byteen_r, 3, 0) @[lsu_dccm_ctl.scala 222:39] + node _T_998 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 222:61] + node _T_999 = dshl(_T_997, _T_998) @[lsu_dccm_ctl.scala 222:45] + store_byteen_ext_r <= _T_999 @[lsu_dccm_ctl.scala 222:22] + node _T_1000 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 225:51] + node _T_1001 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 225:84] + node _T_1002 = eq(_T_1000, _T_1001) @[lsu_dccm_ctl.scala 225:67] + node dccm_wr_bypass_d_m_lo = and(_T_1002, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 225:101] + node _T_1003 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 226:51] + node _T_1004 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 226:84] + node _T_1005 = eq(_T_1003, _T_1004) @[lsu_dccm_ctl.scala 226:67] + node dccm_wr_bypass_d_m_hi = and(_T_1005, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 226:101] + node _T_1006 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 228:51] + node _T_1007 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 228:84] + node _T_1008 = eq(_T_1006, _T_1007) @[lsu_dccm_ctl.scala 228:67] + node dccm_wr_bypass_d_r_lo = and(_T_1008, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 228:101] + node _T_1009 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 229:51] + node _T_1010 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 229:84] + node _T_1011 = eq(_T_1009, _T_1010) @[lsu_dccm_ctl.scala 229:67] + node dccm_wr_bypass_d_r_hi = and(_T_1011, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 229:101] + wire dccm_wr_bypass_d_m_hi_Q : UInt<1> + dccm_wr_bypass_d_m_hi_Q <= UInt<1>("h00") + wire dccm_wr_bypass_d_m_lo_Q : UInt<1> + dccm_wr_bypass_d_m_lo_Q <= UInt<1>("h00") + wire dccm_wren_Q : UInt<1> + dccm_wren_Q <= UInt<1>("h00") + wire dccm_wr_data_Q : UInt<32> + dccm_wr_data_Q <= UInt<32>("h00") + wire store_data_pre_r : UInt<64> + store_data_pre_r <= UInt<64>("h00") + wire store_data_pre_hi_r : UInt<32> + store_data_pre_hi_r <= UInt<32>("h00") + wire store_data_pre_lo_r : UInt<32> + store_data_pre_lo_r <= UInt<32>("h00") + wire store_data_pre_m : UInt<64> + store_data_pre_m <= UInt<64>("h00") + wire store_data_hi_m : UInt<32> + store_data_hi_m <= UInt<32>("h00") + wire store_data_lo_m : UInt<32> + store_data_lo_m <= UInt<32>("h00") + node _T_1012 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1013 = bits(io.store_data_m, 31, 0) @[lsu_dccm_ctl.scala 258:64] + node _T_1014 = cat(_T_1012, _T_1013) @[Cat.scala 29:58] + node _T_1015 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 258:92] + node _T_1016 = mul(UInt<4>("h08"), _T_1015) @[lsu_dccm_ctl.scala 258:78] + node _T_1017 = dshl(_T_1014, _T_1016) @[lsu_dccm_ctl.scala 258:72] + store_data_pre_m <= _T_1017 @[lsu_dccm_ctl.scala 258:29] + node _T_1018 = bits(store_data_pre_m, 63, 32) @[lsu_dccm_ctl.scala 259:48] + store_data_hi_m <= _T_1018 @[lsu_dccm_ctl.scala 259:29] + node _T_1019 = bits(store_data_pre_m, 31, 0) @[lsu_dccm_ctl.scala 260:48] + store_data_lo_m <= _T_1019 @[lsu_dccm_ctl.scala 260:29] + node _T_1020 = bits(store_byteen_ext_m, 0, 0) @[lsu_dccm_ctl.scala 261:139] + node _T_1021 = bits(_T_1020, 0, 0) @[lsu_dccm_ctl.scala 261:143] + node _T_1022 = bits(store_data_lo_m, 7, 0) @[lsu_dccm_ctl.scala 261:167] + node _T_1023 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211] + node _T_1024 = bits(_T_1023, 0, 0) @[lsu_dccm_ctl.scala 261:237] + node _T_1025 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 261:262] + node _T_1026 = bits(io.sec_data_lo_m, 7, 0) @[lsu_dccm_ctl.scala 261:292] + node _T_1027 = mux(_T_1024, _T_1025, _T_1026) @[lsu_dccm_ctl.scala 261:185] + node _T_1028 = mux(_T_1021, _T_1022, _T_1027) @[lsu_dccm_ctl.scala 261:120] + node _T_1029 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1030 = xor(UInt<8>("h0ff"), _T_1029) @[Bitwise.scala 102:21] + node _T_1031 = shr(_T_1028, 4) @[Bitwise.scala 103:21] + node _T_1032 = and(_T_1031, _T_1030) @[Bitwise.scala 103:31] + node _T_1033 = bits(_T_1028, 3, 0) @[Bitwise.scala 103:46] + node _T_1034 = shl(_T_1033, 4) @[Bitwise.scala 103:65] + node _T_1035 = not(_T_1030) @[Bitwise.scala 103:77] + node _T_1036 = and(_T_1034, _T_1035) @[Bitwise.scala 103:75] + node _T_1037 = or(_T_1032, _T_1036) @[Bitwise.scala 103:39] + node _T_1038 = bits(_T_1030, 5, 0) @[Bitwise.scala 102:28] + node _T_1039 = shl(_T_1038, 2) @[Bitwise.scala 102:47] + node _T_1040 = xor(_T_1030, _T_1039) @[Bitwise.scala 102:21] + node _T_1041 = shr(_T_1037, 2) @[Bitwise.scala 103:21] + node _T_1042 = and(_T_1041, _T_1040) @[Bitwise.scala 103:31] + node _T_1043 = bits(_T_1037, 5, 0) @[Bitwise.scala 103:46] + node _T_1044 = shl(_T_1043, 2) @[Bitwise.scala 103:65] + node _T_1045 = not(_T_1040) @[Bitwise.scala 103:77] + node _T_1046 = and(_T_1044, _T_1045) @[Bitwise.scala 103:75] + node _T_1047 = or(_T_1042, _T_1046) @[Bitwise.scala 103:39] + node _T_1048 = bits(_T_1040, 6, 0) @[Bitwise.scala 102:28] + node _T_1049 = shl(_T_1048, 1) @[Bitwise.scala 102:47] + node _T_1050 = xor(_T_1040, _T_1049) @[Bitwise.scala 102:21] + node _T_1051 = shr(_T_1047, 1) @[Bitwise.scala 103:21] + node _T_1052 = and(_T_1051, _T_1050) @[Bitwise.scala 103:31] + node _T_1053 = bits(_T_1047, 6, 0) @[Bitwise.scala 103:46] + node _T_1054 = shl(_T_1053, 1) @[Bitwise.scala 103:65] + node _T_1055 = not(_T_1050) @[Bitwise.scala 103:77] + node _T_1056 = and(_T_1054, _T_1055) @[Bitwise.scala 103:75] + node _T_1057 = or(_T_1052, _T_1056) @[Bitwise.scala 103:39] + node _T_1058 = bits(store_byteen_ext_m, 1, 1) @[lsu_dccm_ctl.scala 261:139] + node _T_1059 = bits(_T_1058, 0, 0) @[lsu_dccm_ctl.scala 261:143] + node _T_1060 = bits(store_data_lo_m, 15, 8) @[lsu_dccm_ctl.scala 261:167] + node _T_1061 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211] + node _T_1062 = bits(_T_1061, 0, 0) @[lsu_dccm_ctl.scala 261:237] + node _T_1063 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 261:262] + node _T_1064 = bits(io.sec_data_lo_m, 15, 8) @[lsu_dccm_ctl.scala 261:292] + node _T_1065 = mux(_T_1062, _T_1063, _T_1064) @[lsu_dccm_ctl.scala 261:185] + node _T_1066 = mux(_T_1059, _T_1060, _T_1065) @[lsu_dccm_ctl.scala 261:120] + node _T_1067 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1068 = xor(UInt<8>("h0ff"), _T_1067) @[Bitwise.scala 102:21] + node _T_1069 = shr(_T_1066, 4) @[Bitwise.scala 103:21] + node _T_1070 = and(_T_1069, _T_1068) @[Bitwise.scala 103:31] + node _T_1071 = bits(_T_1066, 3, 0) @[Bitwise.scala 103:46] + node _T_1072 = shl(_T_1071, 4) @[Bitwise.scala 103:65] + node _T_1073 = not(_T_1068) @[Bitwise.scala 103:77] + node _T_1074 = and(_T_1072, _T_1073) @[Bitwise.scala 103:75] + node _T_1075 = or(_T_1070, _T_1074) @[Bitwise.scala 103:39] + node _T_1076 = bits(_T_1068, 5, 0) @[Bitwise.scala 102:28] + node _T_1077 = shl(_T_1076, 2) @[Bitwise.scala 102:47] + node _T_1078 = xor(_T_1068, _T_1077) @[Bitwise.scala 102:21] + node _T_1079 = shr(_T_1075, 2) @[Bitwise.scala 103:21] + node _T_1080 = and(_T_1079, _T_1078) @[Bitwise.scala 103:31] + node _T_1081 = bits(_T_1075, 5, 0) @[Bitwise.scala 103:46] + node _T_1082 = shl(_T_1081, 2) @[Bitwise.scala 103:65] + node _T_1083 = not(_T_1078) @[Bitwise.scala 103:77] + node _T_1084 = and(_T_1082, _T_1083) @[Bitwise.scala 103:75] + node _T_1085 = or(_T_1080, _T_1084) @[Bitwise.scala 103:39] + node _T_1086 = bits(_T_1078, 6, 0) @[Bitwise.scala 102:28] + node _T_1087 = shl(_T_1086, 1) @[Bitwise.scala 102:47] + node _T_1088 = xor(_T_1078, _T_1087) @[Bitwise.scala 102:21] + node _T_1089 = shr(_T_1085, 1) @[Bitwise.scala 103:21] + node _T_1090 = and(_T_1089, _T_1088) @[Bitwise.scala 103:31] + node _T_1091 = bits(_T_1085, 6, 0) @[Bitwise.scala 103:46] + node _T_1092 = shl(_T_1091, 1) @[Bitwise.scala 103:65] + node _T_1093 = not(_T_1088) @[Bitwise.scala 103:77] + node _T_1094 = and(_T_1092, _T_1093) @[Bitwise.scala 103:75] + node _T_1095 = or(_T_1090, _T_1094) @[Bitwise.scala 103:39] + node _T_1096 = bits(store_byteen_ext_m, 2, 2) @[lsu_dccm_ctl.scala 261:139] + node _T_1097 = bits(_T_1096, 0, 0) @[lsu_dccm_ctl.scala 261:143] + node _T_1098 = bits(store_data_lo_m, 23, 16) @[lsu_dccm_ctl.scala 261:167] + node _T_1099 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211] + node _T_1100 = bits(_T_1099, 0, 0) @[lsu_dccm_ctl.scala 261:237] + node _T_1101 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 261:262] + node _T_1102 = bits(io.sec_data_lo_m, 23, 16) @[lsu_dccm_ctl.scala 261:292] + node _T_1103 = mux(_T_1100, _T_1101, _T_1102) @[lsu_dccm_ctl.scala 261:185] + node _T_1104 = mux(_T_1097, _T_1098, _T_1103) @[lsu_dccm_ctl.scala 261:120] + node _T_1105 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1106 = xor(UInt<8>("h0ff"), _T_1105) @[Bitwise.scala 102:21] + node _T_1107 = shr(_T_1104, 4) @[Bitwise.scala 103:21] + node _T_1108 = and(_T_1107, _T_1106) @[Bitwise.scala 103:31] + node _T_1109 = bits(_T_1104, 3, 0) @[Bitwise.scala 103:46] + node _T_1110 = shl(_T_1109, 4) @[Bitwise.scala 103:65] + node _T_1111 = not(_T_1106) @[Bitwise.scala 103:77] + node _T_1112 = and(_T_1110, _T_1111) @[Bitwise.scala 103:75] + node _T_1113 = or(_T_1108, _T_1112) @[Bitwise.scala 103:39] + node _T_1114 = bits(_T_1106, 5, 0) @[Bitwise.scala 102:28] + node _T_1115 = shl(_T_1114, 2) @[Bitwise.scala 102:47] + node _T_1116 = xor(_T_1106, _T_1115) @[Bitwise.scala 102:21] + node _T_1117 = shr(_T_1113, 2) @[Bitwise.scala 103:21] + node _T_1118 = and(_T_1117, _T_1116) @[Bitwise.scala 103:31] + node _T_1119 = bits(_T_1113, 5, 0) @[Bitwise.scala 103:46] + node _T_1120 = shl(_T_1119, 2) @[Bitwise.scala 103:65] + node _T_1121 = not(_T_1116) @[Bitwise.scala 103:77] + node _T_1122 = and(_T_1120, _T_1121) @[Bitwise.scala 103:75] + node _T_1123 = or(_T_1118, _T_1122) @[Bitwise.scala 103:39] + node _T_1124 = bits(_T_1116, 6, 0) @[Bitwise.scala 102:28] + node _T_1125 = shl(_T_1124, 1) @[Bitwise.scala 102:47] + node _T_1126 = xor(_T_1116, _T_1125) @[Bitwise.scala 102:21] + node _T_1127 = shr(_T_1123, 1) @[Bitwise.scala 103:21] + node _T_1128 = and(_T_1127, _T_1126) @[Bitwise.scala 103:31] + node _T_1129 = bits(_T_1123, 6, 0) @[Bitwise.scala 103:46] + node _T_1130 = shl(_T_1129, 1) @[Bitwise.scala 103:65] + node _T_1131 = not(_T_1126) @[Bitwise.scala 103:77] + node _T_1132 = and(_T_1130, _T_1131) @[Bitwise.scala 103:75] + node _T_1133 = or(_T_1128, _T_1132) @[Bitwise.scala 103:39] + node _T_1134 = bits(store_byteen_ext_m, 3, 3) @[lsu_dccm_ctl.scala 261:139] + node _T_1135 = bits(_T_1134, 0, 0) @[lsu_dccm_ctl.scala 261:143] + node _T_1136 = bits(store_data_lo_m, 31, 24) @[lsu_dccm_ctl.scala 261:167] + node _T_1137 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211] + node _T_1138 = bits(_T_1137, 0, 0) @[lsu_dccm_ctl.scala 261:237] + node _T_1139 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 261:262] + node _T_1140 = bits(io.sec_data_lo_m, 31, 24) @[lsu_dccm_ctl.scala 261:292] + node _T_1141 = mux(_T_1138, _T_1139, _T_1140) @[lsu_dccm_ctl.scala 261:185] + node _T_1142 = mux(_T_1135, _T_1136, _T_1141) @[lsu_dccm_ctl.scala 261:120] + node _T_1143 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1144 = xor(UInt<8>("h0ff"), _T_1143) @[Bitwise.scala 102:21] + node _T_1145 = shr(_T_1142, 4) @[Bitwise.scala 103:21] + node _T_1146 = and(_T_1145, _T_1144) @[Bitwise.scala 103:31] + node _T_1147 = bits(_T_1142, 3, 0) @[Bitwise.scala 103:46] + node _T_1148 = shl(_T_1147, 4) @[Bitwise.scala 103:65] + node _T_1149 = not(_T_1144) @[Bitwise.scala 103:77] + node _T_1150 = and(_T_1148, _T_1149) @[Bitwise.scala 103:75] + node _T_1151 = or(_T_1146, _T_1150) @[Bitwise.scala 103:39] + node _T_1152 = bits(_T_1144, 5, 0) @[Bitwise.scala 102:28] + node _T_1153 = shl(_T_1152, 2) @[Bitwise.scala 102:47] + node _T_1154 = xor(_T_1144, _T_1153) @[Bitwise.scala 102:21] + node _T_1155 = shr(_T_1151, 2) @[Bitwise.scala 103:21] + node _T_1156 = and(_T_1155, _T_1154) @[Bitwise.scala 103:31] + node _T_1157 = bits(_T_1151, 5, 0) @[Bitwise.scala 103:46] + node _T_1158 = shl(_T_1157, 2) @[Bitwise.scala 103:65] + node _T_1159 = not(_T_1154) @[Bitwise.scala 103:77] + node _T_1160 = and(_T_1158, _T_1159) @[Bitwise.scala 103:75] + node _T_1161 = or(_T_1156, _T_1160) @[Bitwise.scala 103:39] + node _T_1162 = bits(_T_1154, 6, 0) @[Bitwise.scala 102:28] + node _T_1163 = shl(_T_1162, 1) @[Bitwise.scala 102:47] + node _T_1164 = xor(_T_1154, _T_1163) @[Bitwise.scala 102:21] + node _T_1165 = shr(_T_1161, 1) @[Bitwise.scala 103:21] + node _T_1166 = and(_T_1165, _T_1164) @[Bitwise.scala 103:31] + node _T_1167 = bits(_T_1161, 6, 0) @[Bitwise.scala 103:46] + node _T_1168 = shl(_T_1167, 1) @[Bitwise.scala 103:65] + node _T_1169 = not(_T_1164) @[Bitwise.scala 103:77] + node _T_1170 = and(_T_1168, _T_1169) @[Bitwise.scala 103:75] + node _T_1171 = or(_T_1166, _T_1170) @[Bitwise.scala 103:39] + wire _T_1172 : UInt<8>[4] @[lsu_dccm_ctl.scala 261:104] + _T_1172[0] <= _T_1057 @[lsu_dccm_ctl.scala 261:104] + _T_1172[1] <= _T_1095 @[lsu_dccm_ctl.scala 261:104] + _T_1172[2] <= _T_1133 @[lsu_dccm_ctl.scala 261:104] + _T_1172[3] <= _T_1171 @[lsu_dccm_ctl.scala 261:104] + node _T_1173 = cat(_T_1172[2], _T_1172[3]) @[Cat.scala 29:58] + node _T_1174 = cat(_T_1172[0], _T_1172[1]) @[Cat.scala 29:58] + node _T_1175 = cat(_T_1174, _T_1173) @[Cat.scala 29:58] + node _T_1176 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1177 = xor(UInt<32>("h0ffffffff"), _T_1176) @[Bitwise.scala 102:21] + node _T_1178 = shr(_T_1175, 16) @[Bitwise.scala 103:21] + node _T_1179 = and(_T_1178, _T_1177) @[Bitwise.scala 103:31] + node _T_1180 = bits(_T_1175, 15, 0) @[Bitwise.scala 103:46] + node _T_1181 = shl(_T_1180, 16) @[Bitwise.scala 103:65] + node _T_1182 = not(_T_1177) @[Bitwise.scala 103:77] + node _T_1183 = and(_T_1181, _T_1182) @[Bitwise.scala 103:75] + node _T_1184 = or(_T_1179, _T_1183) @[Bitwise.scala 103:39] + node _T_1185 = bits(_T_1177, 23, 0) @[Bitwise.scala 102:28] + node _T_1186 = shl(_T_1185, 8) @[Bitwise.scala 102:47] + node _T_1187 = xor(_T_1177, _T_1186) @[Bitwise.scala 102:21] + node _T_1188 = shr(_T_1184, 8) @[Bitwise.scala 103:21] + node _T_1189 = and(_T_1188, _T_1187) @[Bitwise.scala 103:31] + node _T_1190 = bits(_T_1184, 23, 0) @[Bitwise.scala 103:46] + node _T_1191 = shl(_T_1190, 8) @[Bitwise.scala 103:65] + node _T_1192 = not(_T_1187) @[Bitwise.scala 103:77] + node _T_1193 = and(_T_1191, _T_1192) @[Bitwise.scala 103:75] + node _T_1194 = or(_T_1189, _T_1193) @[Bitwise.scala 103:39] + node _T_1195 = bits(_T_1187, 27, 0) @[Bitwise.scala 102:28] + node _T_1196 = shl(_T_1195, 4) @[Bitwise.scala 102:47] + node _T_1197 = xor(_T_1187, _T_1196) @[Bitwise.scala 102:21] + node _T_1198 = shr(_T_1194, 4) @[Bitwise.scala 103:21] + node _T_1199 = and(_T_1198, _T_1197) @[Bitwise.scala 103:31] + node _T_1200 = bits(_T_1194, 27, 0) @[Bitwise.scala 103:46] + node _T_1201 = shl(_T_1200, 4) @[Bitwise.scala 103:65] + node _T_1202 = not(_T_1197) @[Bitwise.scala 103:77] + node _T_1203 = and(_T_1201, _T_1202) @[Bitwise.scala 103:75] + node _T_1204 = or(_T_1199, _T_1203) @[Bitwise.scala 103:39] + node _T_1205 = bits(_T_1197, 29, 0) @[Bitwise.scala 102:28] + node _T_1206 = shl(_T_1205, 2) @[Bitwise.scala 102:47] + node _T_1207 = xor(_T_1197, _T_1206) @[Bitwise.scala 102:21] + node _T_1208 = shr(_T_1204, 2) @[Bitwise.scala 103:21] + node _T_1209 = and(_T_1208, _T_1207) @[Bitwise.scala 103:31] + node _T_1210 = bits(_T_1204, 29, 0) @[Bitwise.scala 103:46] + node _T_1211 = shl(_T_1210, 2) @[Bitwise.scala 103:65] + node _T_1212 = not(_T_1207) @[Bitwise.scala 103:77] + node _T_1213 = and(_T_1211, _T_1212) @[Bitwise.scala 103:75] + node _T_1214 = or(_T_1209, _T_1213) @[Bitwise.scala 103:39] + node _T_1215 = bits(_T_1207, 30, 0) @[Bitwise.scala 102:28] + node _T_1216 = shl(_T_1215, 1) @[Bitwise.scala 102:47] + node _T_1217 = xor(_T_1207, _T_1216) @[Bitwise.scala 102:21] + node _T_1218 = shr(_T_1214, 1) @[Bitwise.scala 103:21] + node _T_1219 = and(_T_1218, _T_1217) @[Bitwise.scala 103:31] + node _T_1220 = bits(_T_1214, 30, 0) @[Bitwise.scala 103:46] + node _T_1221 = shl(_T_1220, 1) @[Bitwise.scala 103:65] + node _T_1222 = not(_T_1217) @[Bitwise.scala 103:77] + node _T_1223 = and(_T_1221, _T_1222) @[Bitwise.scala 103:75] + node _T_1224 = or(_T_1219, _T_1223) @[Bitwise.scala 103:39] + reg _T_1225 : UInt, io.lsu_store_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 261:72] + _T_1225 <= _T_1224 @[lsu_dccm_ctl.scala 261:72] + io.store_data_lo_r <= _T_1225 @[lsu_dccm_ctl.scala 261:29] + node _T_1226 = bits(store_byteen_ext_m, 4, 4) @[lsu_dccm_ctl.scala 262:105] + node _T_1227 = bits(_T_1226, 0, 0) @[lsu_dccm_ctl.scala 262:111] + node _T_1228 = bits(store_data_hi_m, 7, 0) @[lsu_dccm_ctl.scala 262:133] + node _T_1229 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177] + node _T_1230 = bits(_T_1229, 0, 0) @[lsu_dccm_ctl.scala 262:203] + node _T_1231 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 262:228] + node _T_1232 = bits(io.sec_data_hi_m, 7, 0) @[lsu_dccm_ctl.scala 262:258] + node _T_1233 = mux(_T_1230, _T_1231, _T_1232) @[lsu_dccm_ctl.scala 262:151] + node _T_1234 = mux(_T_1227, _T_1228, _T_1233) @[lsu_dccm_ctl.scala 262:86] + node _T_1235 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1236 = xor(UInt<8>("h0ff"), _T_1235) @[Bitwise.scala 102:21] + node _T_1237 = shr(_T_1234, 4) @[Bitwise.scala 103:21] + node _T_1238 = and(_T_1237, _T_1236) @[Bitwise.scala 103:31] + node _T_1239 = bits(_T_1234, 3, 0) @[Bitwise.scala 103:46] + node _T_1240 = shl(_T_1239, 4) @[Bitwise.scala 103:65] + node _T_1241 = not(_T_1236) @[Bitwise.scala 103:77] + node _T_1242 = and(_T_1240, _T_1241) @[Bitwise.scala 103:75] + node _T_1243 = or(_T_1238, _T_1242) @[Bitwise.scala 103:39] + node _T_1244 = bits(_T_1236, 5, 0) @[Bitwise.scala 102:28] + node _T_1245 = shl(_T_1244, 2) @[Bitwise.scala 102:47] + node _T_1246 = xor(_T_1236, _T_1245) @[Bitwise.scala 102:21] + node _T_1247 = shr(_T_1243, 2) @[Bitwise.scala 103:21] + node _T_1248 = and(_T_1247, _T_1246) @[Bitwise.scala 103:31] + node _T_1249 = bits(_T_1243, 5, 0) @[Bitwise.scala 103:46] + node _T_1250 = shl(_T_1249, 2) @[Bitwise.scala 103:65] + node _T_1251 = not(_T_1246) @[Bitwise.scala 103:77] + node _T_1252 = and(_T_1250, _T_1251) @[Bitwise.scala 103:75] + node _T_1253 = or(_T_1248, _T_1252) @[Bitwise.scala 103:39] + node _T_1254 = bits(_T_1246, 6, 0) @[Bitwise.scala 102:28] + node _T_1255 = shl(_T_1254, 1) @[Bitwise.scala 102:47] + node _T_1256 = xor(_T_1246, _T_1255) @[Bitwise.scala 102:21] + node _T_1257 = shr(_T_1253, 1) @[Bitwise.scala 103:21] + node _T_1258 = and(_T_1257, _T_1256) @[Bitwise.scala 103:31] + node _T_1259 = bits(_T_1253, 6, 0) @[Bitwise.scala 103:46] + node _T_1260 = shl(_T_1259, 1) @[Bitwise.scala 103:65] + node _T_1261 = not(_T_1256) @[Bitwise.scala 103:77] + node _T_1262 = and(_T_1260, _T_1261) @[Bitwise.scala 103:75] + node _T_1263 = or(_T_1258, _T_1262) @[Bitwise.scala 103:39] + node _T_1264 = bits(store_byteen_ext_m, 5, 5) @[lsu_dccm_ctl.scala 262:105] + node _T_1265 = bits(_T_1264, 0, 0) @[lsu_dccm_ctl.scala 262:111] + node _T_1266 = bits(store_data_hi_m, 15, 8) @[lsu_dccm_ctl.scala 262:133] + node _T_1267 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177] + node _T_1268 = bits(_T_1267, 0, 0) @[lsu_dccm_ctl.scala 262:203] + node _T_1269 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 262:228] + node _T_1270 = bits(io.sec_data_hi_m, 15, 8) @[lsu_dccm_ctl.scala 262:258] + node _T_1271 = mux(_T_1268, _T_1269, _T_1270) @[lsu_dccm_ctl.scala 262:151] + node _T_1272 = mux(_T_1265, _T_1266, _T_1271) @[lsu_dccm_ctl.scala 262:86] + node _T_1273 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1274 = xor(UInt<8>("h0ff"), _T_1273) @[Bitwise.scala 102:21] + node _T_1275 = shr(_T_1272, 4) @[Bitwise.scala 103:21] + node _T_1276 = and(_T_1275, _T_1274) @[Bitwise.scala 103:31] + node _T_1277 = bits(_T_1272, 3, 0) @[Bitwise.scala 103:46] + node _T_1278 = shl(_T_1277, 4) @[Bitwise.scala 103:65] + node _T_1279 = not(_T_1274) @[Bitwise.scala 103:77] + node _T_1280 = and(_T_1278, _T_1279) @[Bitwise.scala 103:75] + node _T_1281 = or(_T_1276, _T_1280) @[Bitwise.scala 103:39] + node _T_1282 = bits(_T_1274, 5, 0) @[Bitwise.scala 102:28] + node _T_1283 = shl(_T_1282, 2) @[Bitwise.scala 102:47] + node _T_1284 = xor(_T_1274, _T_1283) @[Bitwise.scala 102:21] + node _T_1285 = shr(_T_1281, 2) @[Bitwise.scala 103:21] + node _T_1286 = and(_T_1285, _T_1284) @[Bitwise.scala 103:31] + node _T_1287 = bits(_T_1281, 5, 0) @[Bitwise.scala 103:46] + node _T_1288 = shl(_T_1287, 2) @[Bitwise.scala 103:65] + node _T_1289 = not(_T_1284) @[Bitwise.scala 103:77] + node _T_1290 = and(_T_1288, _T_1289) @[Bitwise.scala 103:75] + node _T_1291 = or(_T_1286, _T_1290) @[Bitwise.scala 103:39] + node _T_1292 = bits(_T_1284, 6, 0) @[Bitwise.scala 102:28] + node _T_1293 = shl(_T_1292, 1) @[Bitwise.scala 102:47] + node _T_1294 = xor(_T_1284, _T_1293) @[Bitwise.scala 102:21] + node _T_1295 = shr(_T_1291, 1) @[Bitwise.scala 103:21] + node _T_1296 = and(_T_1295, _T_1294) @[Bitwise.scala 103:31] + node _T_1297 = bits(_T_1291, 6, 0) @[Bitwise.scala 103:46] + node _T_1298 = shl(_T_1297, 1) @[Bitwise.scala 103:65] + node _T_1299 = not(_T_1294) @[Bitwise.scala 103:77] + node _T_1300 = and(_T_1298, _T_1299) @[Bitwise.scala 103:75] + node _T_1301 = or(_T_1296, _T_1300) @[Bitwise.scala 103:39] + node _T_1302 = bits(store_byteen_ext_m, 6, 6) @[lsu_dccm_ctl.scala 262:105] + node _T_1303 = bits(_T_1302, 0, 0) @[lsu_dccm_ctl.scala 262:111] + node _T_1304 = bits(store_data_hi_m, 23, 16) @[lsu_dccm_ctl.scala 262:133] + node _T_1305 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177] + node _T_1306 = bits(_T_1305, 0, 0) @[lsu_dccm_ctl.scala 262:203] + node _T_1307 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 262:228] + node _T_1308 = bits(io.sec_data_hi_m, 23, 16) @[lsu_dccm_ctl.scala 262:258] + node _T_1309 = mux(_T_1306, _T_1307, _T_1308) @[lsu_dccm_ctl.scala 262:151] + node _T_1310 = mux(_T_1303, _T_1304, _T_1309) @[lsu_dccm_ctl.scala 262:86] + node _T_1311 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1312 = xor(UInt<8>("h0ff"), _T_1311) @[Bitwise.scala 102:21] + node _T_1313 = shr(_T_1310, 4) @[Bitwise.scala 103:21] + node _T_1314 = and(_T_1313, _T_1312) @[Bitwise.scala 103:31] + node _T_1315 = bits(_T_1310, 3, 0) @[Bitwise.scala 103:46] + node _T_1316 = shl(_T_1315, 4) @[Bitwise.scala 103:65] + node _T_1317 = not(_T_1312) @[Bitwise.scala 103:77] + node _T_1318 = and(_T_1316, _T_1317) @[Bitwise.scala 103:75] + node _T_1319 = or(_T_1314, _T_1318) @[Bitwise.scala 103:39] + node _T_1320 = bits(_T_1312, 5, 0) @[Bitwise.scala 102:28] + node _T_1321 = shl(_T_1320, 2) @[Bitwise.scala 102:47] + node _T_1322 = xor(_T_1312, _T_1321) @[Bitwise.scala 102:21] + node _T_1323 = shr(_T_1319, 2) @[Bitwise.scala 103:21] + node _T_1324 = and(_T_1323, _T_1322) @[Bitwise.scala 103:31] + node _T_1325 = bits(_T_1319, 5, 0) @[Bitwise.scala 103:46] + node _T_1326 = shl(_T_1325, 2) @[Bitwise.scala 103:65] + node _T_1327 = not(_T_1322) @[Bitwise.scala 103:77] + node _T_1328 = and(_T_1326, _T_1327) @[Bitwise.scala 103:75] + node _T_1329 = or(_T_1324, _T_1328) @[Bitwise.scala 103:39] + node _T_1330 = bits(_T_1322, 6, 0) @[Bitwise.scala 102:28] + node _T_1331 = shl(_T_1330, 1) @[Bitwise.scala 102:47] + node _T_1332 = xor(_T_1322, _T_1331) @[Bitwise.scala 102:21] + node _T_1333 = shr(_T_1329, 1) @[Bitwise.scala 103:21] + node _T_1334 = and(_T_1333, _T_1332) @[Bitwise.scala 103:31] + node _T_1335 = bits(_T_1329, 6, 0) @[Bitwise.scala 103:46] + node _T_1336 = shl(_T_1335, 1) @[Bitwise.scala 103:65] + node _T_1337 = not(_T_1332) @[Bitwise.scala 103:77] + node _T_1338 = and(_T_1336, _T_1337) @[Bitwise.scala 103:75] + node _T_1339 = or(_T_1334, _T_1338) @[Bitwise.scala 103:39] + node _T_1340 = bits(store_byteen_ext_m, 7, 7) @[lsu_dccm_ctl.scala 262:105] + node _T_1341 = bits(_T_1340, 0, 0) @[lsu_dccm_ctl.scala 262:111] + node _T_1342 = bits(store_data_hi_m, 31, 24) @[lsu_dccm_ctl.scala 262:133] + node _T_1343 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177] + node _T_1344 = bits(_T_1343, 0, 0) @[lsu_dccm_ctl.scala 262:203] + node _T_1345 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 262:228] + node _T_1346 = bits(io.sec_data_hi_m, 31, 24) @[lsu_dccm_ctl.scala 262:258] + node _T_1347 = mux(_T_1344, _T_1345, _T_1346) @[lsu_dccm_ctl.scala 262:151] + node _T_1348 = mux(_T_1341, _T_1342, _T_1347) @[lsu_dccm_ctl.scala 262:86] + node _T_1349 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1350 = xor(UInt<8>("h0ff"), _T_1349) @[Bitwise.scala 102:21] + node _T_1351 = shr(_T_1348, 4) @[Bitwise.scala 103:21] + node _T_1352 = and(_T_1351, _T_1350) @[Bitwise.scala 103:31] + node _T_1353 = bits(_T_1348, 3, 0) @[Bitwise.scala 103:46] + node _T_1354 = shl(_T_1353, 4) @[Bitwise.scala 103:65] + node _T_1355 = not(_T_1350) @[Bitwise.scala 103:77] + node _T_1356 = and(_T_1354, _T_1355) @[Bitwise.scala 103:75] + node _T_1357 = or(_T_1352, _T_1356) @[Bitwise.scala 103:39] + node _T_1358 = bits(_T_1350, 5, 0) @[Bitwise.scala 102:28] + node _T_1359 = shl(_T_1358, 2) @[Bitwise.scala 102:47] + node _T_1360 = xor(_T_1350, _T_1359) @[Bitwise.scala 102:21] + node _T_1361 = shr(_T_1357, 2) @[Bitwise.scala 103:21] + node _T_1362 = and(_T_1361, _T_1360) @[Bitwise.scala 103:31] + node _T_1363 = bits(_T_1357, 5, 0) @[Bitwise.scala 103:46] + node _T_1364 = shl(_T_1363, 2) @[Bitwise.scala 103:65] + node _T_1365 = not(_T_1360) @[Bitwise.scala 103:77] + node _T_1366 = and(_T_1364, _T_1365) @[Bitwise.scala 103:75] + node _T_1367 = or(_T_1362, _T_1366) @[Bitwise.scala 103:39] + node _T_1368 = bits(_T_1360, 6, 0) @[Bitwise.scala 102:28] + node _T_1369 = shl(_T_1368, 1) @[Bitwise.scala 102:47] + node _T_1370 = xor(_T_1360, _T_1369) @[Bitwise.scala 102:21] + node _T_1371 = shr(_T_1367, 1) @[Bitwise.scala 103:21] + node _T_1372 = and(_T_1371, _T_1370) @[Bitwise.scala 103:31] + node _T_1373 = bits(_T_1367, 6, 0) @[Bitwise.scala 103:46] + node _T_1374 = shl(_T_1373, 1) @[Bitwise.scala 103:65] + node _T_1375 = not(_T_1370) @[Bitwise.scala 103:77] + node _T_1376 = and(_T_1374, _T_1375) @[Bitwise.scala 103:75] + node _T_1377 = or(_T_1372, _T_1376) @[Bitwise.scala 103:39] + wire _T_1378 : UInt<8>[4] @[lsu_dccm_ctl.scala 262:70] + _T_1378[0] <= _T_1263 @[lsu_dccm_ctl.scala 262:70] + _T_1378[1] <= _T_1301 @[lsu_dccm_ctl.scala 262:70] + _T_1378[2] <= _T_1339 @[lsu_dccm_ctl.scala 262:70] + _T_1378[3] <= _T_1377 @[lsu_dccm_ctl.scala 262:70] + node _T_1379 = cat(_T_1378[2], _T_1378[3]) @[Cat.scala 29:58] + node _T_1380 = cat(_T_1378[0], _T_1378[1]) @[Cat.scala 29:58] + node _T_1381 = cat(_T_1380, _T_1379) @[Cat.scala 29:58] + node _T_1382 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1383 = xor(UInt<32>("h0ffffffff"), _T_1382) @[Bitwise.scala 102:21] + node _T_1384 = shr(_T_1381, 16) @[Bitwise.scala 103:21] + node _T_1385 = and(_T_1384, _T_1383) @[Bitwise.scala 103:31] + node _T_1386 = bits(_T_1381, 15, 0) @[Bitwise.scala 103:46] + node _T_1387 = shl(_T_1386, 16) @[Bitwise.scala 103:65] + node _T_1388 = not(_T_1383) @[Bitwise.scala 103:77] + node _T_1389 = and(_T_1387, _T_1388) @[Bitwise.scala 103:75] + node _T_1390 = or(_T_1385, _T_1389) @[Bitwise.scala 103:39] + node _T_1391 = bits(_T_1383, 23, 0) @[Bitwise.scala 102:28] + node _T_1392 = shl(_T_1391, 8) @[Bitwise.scala 102:47] + node _T_1393 = xor(_T_1383, _T_1392) @[Bitwise.scala 102:21] + node _T_1394 = shr(_T_1390, 8) @[Bitwise.scala 103:21] + node _T_1395 = and(_T_1394, _T_1393) @[Bitwise.scala 103:31] + node _T_1396 = bits(_T_1390, 23, 0) @[Bitwise.scala 103:46] + node _T_1397 = shl(_T_1396, 8) @[Bitwise.scala 103:65] + node _T_1398 = not(_T_1393) @[Bitwise.scala 103:77] + node _T_1399 = and(_T_1397, _T_1398) @[Bitwise.scala 103:75] + node _T_1400 = or(_T_1395, _T_1399) @[Bitwise.scala 103:39] + node _T_1401 = bits(_T_1393, 27, 0) @[Bitwise.scala 102:28] + node _T_1402 = shl(_T_1401, 4) @[Bitwise.scala 102:47] + node _T_1403 = xor(_T_1393, _T_1402) @[Bitwise.scala 102:21] + node _T_1404 = shr(_T_1400, 4) @[Bitwise.scala 103:21] + node _T_1405 = and(_T_1404, _T_1403) @[Bitwise.scala 103:31] + node _T_1406 = bits(_T_1400, 27, 0) @[Bitwise.scala 103:46] + node _T_1407 = shl(_T_1406, 4) @[Bitwise.scala 103:65] + node _T_1408 = not(_T_1403) @[Bitwise.scala 103:77] + node _T_1409 = and(_T_1407, _T_1408) @[Bitwise.scala 103:75] + node _T_1410 = or(_T_1405, _T_1409) @[Bitwise.scala 103:39] + node _T_1411 = bits(_T_1403, 29, 0) @[Bitwise.scala 102:28] + node _T_1412 = shl(_T_1411, 2) @[Bitwise.scala 102:47] + node _T_1413 = xor(_T_1403, _T_1412) @[Bitwise.scala 102:21] + node _T_1414 = shr(_T_1410, 2) @[Bitwise.scala 103:21] + node _T_1415 = and(_T_1414, _T_1413) @[Bitwise.scala 103:31] + node _T_1416 = bits(_T_1410, 29, 0) @[Bitwise.scala 103:46] + node _T_1417 = shl(_T_1416, 2) @[Bitwise.scala 103:65] + node _T_1418 = not(_T_1413) @[Bitwise.scala 103:77] + node _T_1419 = and(_T_1417, _T_1418) @[Bitwise.scala 103:75] + node _T_1420 = or(_T_1415, _T_1419) @[Bitwise.scala 103:39] + node _T_1421 = bits(_T_1413, 30, 0) @[Bitwise.scala 102:28] + node _T_1422 = shl(_T_1421, 1) @[Bitwise.scala 102:47] + node _T_1423 = xor(_T_1413, _T_1422) @[Bitwise.scala 102:21] + node _T_1424 = shr(_T_1420, 1) @[Bitwise.scala 103:21] + node _T_1425 = and(_T_1424, _T_1423) @[Bitwise.scala 103:31] + node _T_1426 = bits(_T_1420, 30, 0) @[Bitwise.scala 103:46] + node _T_1427 = shl(_T_1426, 1) @[Bitwise.scala 103:65] + node _T_1428 = not(_T_1423) @[Bitwise.scala 103:77] + node _T_1429 = and(_T_1427, _T_1428) @[Bitwise.scala 103:75] + node _T_1430 = or(_T_1425, _T_1429) @[Bitwise.scala 103:39] + node _T_1431 = and(io.ldst_dual_m, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 262:295] + node _T_1432 = and(_T_1431, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 262:316] + node _T_1433 = or(_T_1432, io.clk_override) @[lsu_dccm_ctl.scala 262:343] + node _T_1434 = bits(_T_1433, 0, 0) @[lib.scala 8:44] + node _T_1435 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_1 of rvclkhdr_5 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_1434 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1436 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1434 : @[Reg.scala 28:19] + _T_1436 <= _T_1430 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.store_data_hi_r <= _T_1436 @[lsu_dccm_ctl.scala 262:29] + node _T_1437 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105] + node _T_1438 = bits(store_byteen_ext_r, 0, 0) @[lsu_dccm_ctl.scala 263:150] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131] + node _T_1440 = and(_T_1437, _T_1439) @[lsu_dccm_ctl.scala 263:129] + node _T_1441 = bits(_T_1440, 0, 0) @[lsu_dccm_ctl.scala 263:155] + node _T_1442 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 263:179] + node _T_1443 = bits(io.store_data_lo_r, 7, 0) @[lsu_dccm_ctl.scala 263:211] + node _T_1444 = mux(_T_1441, _T_1442, _T_1443) @[lsu_dccm_ctl.scala 263:79] + node _T_1445 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1446 = xor(UInt<8>("h0ff"), _T_1445) @[Bitwise.scala 102:21] + node _T_1447 = shr(_T_1444, 4) @[Bitwise.scala 103:21] + node _T_1448 = and(_T_1447, _T_1446) @[Bitwise.scala 103:31] + node _T_1449 = bits(_T_1444, 3, 0) @[Bitwise.scala 103:46] + node _T_1450 = shl(_T_1449, 4) @[Bitwise.scala 103:65] + node _T_1451 = not(_T_1446) @[Bitwise.scala 103:77] + node _T_1452 = and(_T_1450, _T_1451) @[Bitwise.scala 103:75] + node _T_1453 = or(_T_1448, _T_1452) @[Bitwise.scala 103:39] + node _T_1454 = bits(_T_1446, 5, 0) @[Bitwise.scala 102:28] + node _T_1455 = shl(_T_1454, 2) @[Bitwise.scala 102:47] + node _T_1456 = xor(_T_1446, _T_1455) @[Bitwise.scala 102:21] + node _T_1457 = shr(_T_1453, 2) @[Bitwise.scala 103:21] + node _T_1458 = and(_T_1457, _T_1456) @[Bitwise.scala 103:31] + node _T_1459 = bits(_T_1453, 5, 0) @[Bitwise.scala 103:46] + node _T_1460 = shl(_T_1459, 2) @[Bitwise.scala 103:65] + node _T_1461 = not(_T_1456) @[Bitwise.scala 103:77] + node _T_1462 = and(_T_1460, _T_1461) @[Bitwise.scala 103:75] + node _T_1463 = or(_T_1458, _T_1462) @[Bitwise.scala 103:39] + node _T_1464 = bits(_T_1456, 6, 0) @[Bitwise.scala 102:28] + node _T_1465 = shl(_T_1464, 1) @[Bitwise.scala 102:47] + node _T_1466 = xor(_T_1456, _T_1465) @[Bitwise.scala 102:21] + node _T_1467 = shr(_T_1463, 1) @[Bitwise.scala 103:21] + node _T_1468 = and(_T_1467, _T_1466) @[Bitwise.scala 103:31] + node _T_1469 = bits(_T_1463, 6, 0) @[Bitwise.scala 103:46] + node _T_1470 = shl(_T_1469, 1) @[Bitwise.scala 103:65] + node _T_1471 = not(_T_1466) @[Bitwise.scala 103:77] + node _T_1472 = and(_T_1470, _T_1471) @[Bitwise.scala 103:75] + node _T_1473 = or(_T_1468, _T_1472) @[Bitwise.scala 103:39] + node _T_1474 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105] + node _T_1475 = bits(store_byteen_ext_r, 1, 1) @[lsu_dccm_ctl.scala 263:150] + node _T_1476 = eq(_T_1475, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131] + node _T_1477 = and(_T_1474, _T_1476) @[lsu_dccm_ctl.scala 263:129] + node _T_1478 = bits(_T_1477, 0, 0) @[lsu_dccm_ctl.scala 263:155] + node _T_1479 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 263:179] + node _T_1480 = bits(io.store_data_lo_r, 15, 8) @[lsu_dccm_ctl.scala 263:211] + node _T_1481 = mux(_T_1478, _T_1479, _T_1480) @[lsu_dccm_ctl.scala 263:79] + node _T_1482 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1483 = xor(UInt<8>("h0ff"), _T_1482) @[Bitwise.scala 102:21] + node _T_1484 = shr(_T_1481, 4) @[Bitwise.scala 103:21] + node _T_1485 = and(_T_1484, _T_1483) @[Bitwise.scala 103:31] + node _T_1486 = bits(_T_1481, 3, 0) @[Bitwise.scala 103:46] + node _T_1487 = shl(_T_1486, 4) @[Bitwise.scala 103:65] + node _T_1488 = not(_T_1483) @[Bitwise.scala 103:77] + node _T_1489 = and(_T_1487, _T_1488) @[Bitwise.scala 103:75] + node _T_1490 = or(_T_1485, _T_1489) @[Bitwise.scala 103:39] + node _T_1491 = bits(_T_1483, 5, 0) @[Bitwise.scala 102:28] + node _T_1492 = shl(_T_1491, 2) @[Bitwise.scala 102:47] + node _T_1493 = xor(_T_1483, _T_1492) @[Bitwise.scala 102:21] + node _T_1494 = shr(_T_1490, 2) @[Bitwise.scala 103:21] + node _T_1495 = and(_T_1494, _T_1493) @[Bitwise.scala 103:31] + node _T_1496 = bits(_T_1490, 5, 0) @[Bitwise.scala 103:46] + node _T_1497 = shl(_T_1496, 2) @[Bitwise.scala 103:65] + node _T_1498 = not(_T_1493) @[Bitwise.scala 103:77] + node _T_1499 = and(_T_1497, _T_1498) @[Bitwise.scala 103:75] + node _T_1500 = or(_T_1495, _T_1499) @[Bitwise.scala 103:39] + node _T_1501 = bits(_T_1493, 6, 0) @[Bitwise.scala 102:28] + node _T_1502 = shl(_T_1501, 1) @[Bitwise.scala 102:47] + node _T_1503 = xor(_T_1493, _T_1502) @[Bitwise.scala 102:21] + node _T_1504 = shr(_T_1500, 1) @[Bitwise.scala 103:21] + node _T_1505 = and(_T_1504, _T_1503) @[Bitwise.scala 103:31] + node _T_1506 = bits(_T_1500, 6, 0) @[Bitwise.scala 103:46] + node _T_1507 = shl(_T_1506, 1) @[Bitwise.scala 103:65] + node _T_1508 = not(_T_1503) @[Bitwise.scala 103:77] + node _T_1509 = and(_T_1507, _T_1508) @[Bitwise.scala 103:75] + node _T_1510 = or(_T_1505, _T_1509) @[Bitwise.scala 103:39] + node _T_1511 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105] + node _T_1512 = bits(store_byteen_ext_r, 2, 2) @[lsu_dccm_ctl.scala 263:150] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131] + node _T_1514 = and(_T_1511, _T_1513) @[lsu_dccm_ctl.scala 263:129] + node _T_1515 = bits(_T_1514, 0, 0) @[lsu_dccm_ctl.scala 263:155] + node _T_1516 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 263:179] + node _T_1517 = bits(io.store_data_lo_r, 23, 16) @[lsu_dccm_ctl.scala 263:211] + node _T_1518 = mux(_T_1515, _T_1516, _T_1517) @[lsu_dccm_ctl.scala 263:79] + node _T_1519 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1520 = xor(UInt<8>("h0ff"), _T_1519) @[Bitwise.scala 102:21] + node _T_1521 = shr(_T_1518, 4) @[Bitwise.scala 103:21] + node _T_1522 = and(_T_1521, _T_1520) @[Bitwise.scala 103:31] + node _T_1523 = bits(_T_1518, 3, 0) @[Bitwise.scala 103:46] + node _T_1524 = shl(_T_1523, 4) @[Bitwise.scala 103:65] + node _T_1525 = not(_T_1520) @[Bitwise.scala 103:77] + node _T_1526 = and(_T_1524, _T_1525) @[Bitwise.scala 103:75] + node _T_1527 = or(_T_1522, _T_1526) @[Bitwise.scala 103:39] + node _T_1528 = bits(_T_1520, 5, 0) @[Bitwise.scala 102:28] + node _T_1529 = shl(_T_1528, 2) @[Bitwise.scala 102:47] + node _T_1530 = xor(_T_1520, _T_1529) @[Bitwise.scala 102:21] + node _T_1531 = shr(_T_1527, 2) @[Bitwise.scala 103:21] + node _T_1532 = and(_T_1531, _T_1530) @[Bitwise.scala 103:31] + node _T_1533 = bits(_T_1527, 5, 0) @[Bitwise.scala 103:46] + node _T_1534 = shl(_T_1533, 2) @[Bitwise.scala 103:65] + node _T_1535 = not(_T_1530) @[Bitwise.scala 103:77] + node _T_1536 = and(_T_1534, _T_1535) @[Bitwise.scala 103:75] + node _T_1537 = or(_T_1532, _T_1536) @[Bitwise.scala 103:39] + node _T_1538 = bits(_T_1530, 6, 0) @[Bitwise.scala 102:28] + node _T_1539 = shl(_T_1538, 1) @[Bitwise.scala 102:47] + node _T_1540 = xor(_T_1530, _T_1539) @[Bitwise.scala 102:21] + node _T_1541 = shr(_T_1537, 1) @[Bitwise.scala 103:21] + node _T_1542 = and(_T_1541, _T_1540) @[Bitwise.scala 103:31] + node _T_1543 = bits(_T_1537, 6, 0) @[Bitwise.scala 103:46] + node _T_1544 = shl(_T_1543, 1) @[Bitwise.scala 103:65] + node _T_1545 = not(_T_1540) @[Bitwise.scala 103:77] + node _T_1546 = and(_T_1544, _T_1545) @[Bitwise.scala 103:75] + node _T_1547 = or(_T_1542, _T_1546) @[Bitwise.scala 103:39] + node _T_1548 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105] + node _T_1549 = bits(store_byteen_ext_r, 3, 3) @[lsu_dccm_ctl.scala 263:150] + node _T_1550 = eq(_T_1549, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131] + node _T_1551 = and(_T_1548, _T_1550) @[lsu_dccm_ctl.scala 263:129] + node _T_1552 = bits(_T_1551, 0, 0) @[lsu_dccm_ctl.scala 263:155] + node _T_1553 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 263:179] + node _T_1554 = bits(io.store_data_lo_r, 31, 24) @[lsu_dccm_ctl.scala 263:211] + node _T_1555 = mux(_T_1552, _T_1553, _T_1554) @[lsu_dccm_ctl.scala 263:79] + node _T_1556 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1557 = xor(UInt<8>("h0ff"), _T_1556) @[Bitwise.scala 102:21] + node _T_1558 = shr(_T_1555, 4) @[Bitwise.scala 103:21] + node _T_1559 = and(_T_1558, _T_1557) @[Bitwise.scala 103:31] + node _T_1560 = bits(_T_1555, 3, 0) @[Bitwise.scala 103:46] + node _T_1561 = shl(_T_1560, 4) @[Bitwise.scala 103:65] + node _T_1562 = not(_T_1557) @[Bitwise.scala 103:77] + node _T_1563 = and(_T_1561, _T_1562) @[Bitwise.scala 103:75] + node _T_1564 = or(_T_1559, _T_1563) @[Bitwise.scala 103:39] + node _T_1565 = bits(_T_1557, 5, 0) @[Bitwise.scala 102:28] + node _T_1566 = shl(_T_1565, 2) @[Bitwise.scala 102:47] + node _T_1567 = xor(_T_1557, _T_1566) @[Bitwise.scala 102:21] + node _T_1568 = shr(_T_1564, 2) @[Bitwise.scala 103:21] + node _T_1569 = and(_T_1568, _T_1567) @[Bitwise.scala 103:31] + node _T_1570 = bits(_T_1564, 5, 0) @[Bitwise.scala 103:46] + node _T_1571 = shl(_T_1570, 2) @[Bitwise.scala 103:65] + node _T_1572 = not(_T_1567) @[Bitwise.scala 103:77] + node _T_1573 = and(_T_1571, _T_1572) @[Bitwise.scala 103:75] + node _T_1574 = or(_T_1569, _T_1573) @[Bitwise.scala 103:39] + node _T_1575 = bits(_T_1567, 6, 0) @[Bitwise.scala 102:28] + node _T_1576 = shl(_T_1575, 1) @[Bitwise.scala 102:47] + node _T_1577 = xor(_T_1567, _T_1576) @[Bitwise.scala 102:21] + node _T_1578 = shr(_T_1574, 1) @[Bitwise.scala 103:21] + node _T_1579 = and(_T_1578, _T_1577) @[Bitwise.scala 103:31] + node _T_1580 = bits(_T_1574, 6, 0) @[Bitwise.scala 103:46] + node _T_1581 = shl(_T_1580, 1) @[Bitwise.scala 103:65] + node _T_1582 = not(_T_1577) @[Bitwise.scala 103:77] + node _T_1583 = and(_T_1581, _T_1582) @[Bitwise.scala 103:75] + node _T_1584 = or(_T_1579, _T_1583) @[Bitwise.scala 103:39] + wire _T_1585 : UInt<8>[4] @[lsu_dccm_ctl.scala 263:63] + _T_1585[0] <= _T_1473 @[lsu_dccm_ctl.scala 263:63] + _T_1585[1] <= _T_1510 @[lsu_dccm_ctl.scala 263:63] + _T_1585[2] <= _T_1547 @[lsu_dccm_ctl.scala 263:63] + _T_1585[3] <= _T_1584 @[lsu_dccm_ctl.scala 263:63] + node _T_1586 = cat(_T_1585[2], _T_1585[3]) @[Cat.scala 29:58] + node _T_1587 = cat(_T_1585[0], _T_1585[1]) @[Cat.scala 29:58] + node _T_1588 = cat(_T_1587, _T_1586) @[Cat.scala 29:58] + node _T_1589 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1590 = xor(UInt<32>("h0ffffffff"), _T_1589) @[Bitwise.scala 102:21] + node _T_1591 = shr(_T_1588, 16) @[Bitwise.scala 103:21] + node _T_1592 = and(_T_1591, _T_1590) @[Bitwise.scala 103:31] + node _T_1593 = bits(_T_1588, 15, 0) @[Bitwise.scala 103:46] + node _T_1594 = shl(_T_1593, 16) @[Bitwise.scala 103:65] + node _T_1595 = not(_T_1590) @[Bitwise.scala 103:77] + node _T_1596 = and(_T_1594, _T_1595) @[Bitwise.scala 103:75] + node _T_1597 = or(_T_1592, _T_1596) @[Bitwise.scala 103:39] + node _T_1598 = bits(_T_1590, 23, 0) @[Bitwise.scala 102:28] + node _T_1599 = shl(_T_1598, 8) @[Bitwise.scala 102:47] + node _T_1600 = xor(_T_1590, _T_1599) @[Bitwise.scala 102:21] + node _T_1601 = shr(_T_1597, 8) @[Bitwise.scala 103:21] + node _T_1602 = and(_T_1601, _T_1600) @[Bitwise.scala 103:31] + node _T_1603 = bits(_T_1597, 23, 0) @[Bitwise.scala 103:46] + node _T_1604 = shl(_T_1603, 8) @[Bitwise.scala 103:65] + node _T_1605 = not(_T_1600) @[Bitwise.scala 103:77] + node _T_1606 = and(_T_1604, _T_1605) @[Bitwise.scala 103:75] + node _T_1607 = or(_T_1602, _T_1606) @[Bitwise.scala 103:39] + node _T_1608 = bits(_T_1600, 27, 0) @[Bitwise.scala 102:28] + node _T_1609 = shl(_T_1608, 4) @[Bitwise.scala 102:47] + node _T_1610 = xor(_T_1600, _T_1609) @[Bitwise.scala 102:21] + node _T_1611 = shr(_T_1607, 4) @[Bitwise.scala 103:21] + node _T_1612 = and(_T_1611, _T_1610) @[Bitwise.scala 103:31] + node _T_1613 = bits(_T_1607, 27, 0) @[Bitwise.scala 103:46] + node _T_1614 = shl(_T_1613, 4) @[Bitwise.scala 103:65] + node _T_1615 = not(_T_1610) @[Bitwise.scala 103:77] + node _T_1616 = and(_T_1614, _T_1615) @[Bitwise.scala 103:75] + node _T_1617 = or(_T_1612, _T_1616) @[Bitwise.scala 103:39] + node _T_1618 = bits(_T_1610, 29, 0) @[Bitwise.scala 102:28] + node _T_1619 = shl(_T_1618, 2) @[Bitwise.scala 102:47] + node _T_1620 = xor(_T_1610, _T_1619) @[Bitwise.scala 102:21] + node _T_1621 = shr(_T_1617, 2) @[Bitwise.scala 103:21] + node _T_1622 = and(_T_1621, _T_1620) @[Bitwise.scala 103:31] + node _T_1623 = bits(_T_1617, 29, 0) @[Bitwise.scala 103:46] + node _T_1624 = shl(_T_1623, 2) @[Bitwise.scala 103:65] + node _T_1625 = not(_T_1620) @[Bitwise.scala 103:77] + node _T_1626 = and(_T_1624, _T_1625) @[Bitwise.scala 103:75] + node _T_1627 = or(_T_1622, _T_1626) @[Bitwise.scala 103:39] + node _T_1628 = bits(_T_1620, 30, 0) @[Bitwise.scala 102:28] + node _T_1629 = shl(_T_1628, 1) @[Bitwise.scala 102:47] + node _T_1630 = xor(_T_1620, _T_1629) @[Bitwise.scala 102:21] + node _T_1631 = shr(_T_1627, 1) @[Bitwise.scala 103:21] + node _T_1632 = and(_T_1631, _T_1630) @[Bitwise.scala 103:31] + node _T_1633 = bits(_T_1627, 30, 0) @[Bitwise.scala 103:46] + node _T_1634 = shl(_T_1633, 1) @[Bitwise.scala 103:65] + node _T_1635 = not(_T_1630) @[Bitwise.scala 103:77] + node _T_1636 = and(_T_1634, _T_1635) @[Bitwise.scala 103:75] + node _T_1637 = or(_T_1632, _T_1636) @[Bitwise.scala 103:39] + io.store_datafn_lo_r <= _T_1637 @[lsu_dccm_ctl.scala 263:29] + node _T_1638 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105] + node _T_1639 = bits(store_byteen_ext_r, 4, 4) @[lsu_dccm_ctl.scala 264:150] + node _T_1640 = eq(_T_1639, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131] + node _T_1641 = and(_T_1638, _T_1640) @[lsu_dccm_ctl.scala 264:129] + node _T_1642 = bits(_T_1641, 0, 0) @[lsu_dccm_ctl.scala 264:157] + node _T_1643 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 264:181] + node _T_1644 = bits(io.store_data_hi_r, 7, 0) @[lsu_dccm_ctl.scala 264:213] + node _T_1645 = mux(_T_1642, _T_1643, _T_1644) @[lsu_dccm_ctl.scala 264:79] + node _T_1646 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1647 = xor(UInt<8>("h0ff"), _T_1646) @[Bitwise.scala 102:21] + node _T_1648 = shr(_T_1645, 4) @[Bitwise.scala 103:21] + node _T_1649 = and(_T_1648, _T_1647) @[Bitwise.scala 103:31] + node _T_1650 = bits(_T_1645, 3, 0) @[Bitwise.scala 103:46] + node _T_1651 = shl(_T_1650, 4) @[Bitwise.scala 103:65] + node _T_1652 = not(_T_1647) @[Bitwise.scala 103:77] + node _T_1653 = and(_T_1651, _T_1652) @[Bitwise.scala 103:75] + node _T_1654 = or(_T_1649, _T_1653) @[Bitwise.scala 103:39] + node _T_1655 = bits(_T_1647, 5, 0) @[Bitwise.scala 102:28] + node _T_1656 = shl(_T_1655, 2) @[Bitwise.scala 102:47] + node _T_1657 = xor(_T_1647, _T_1656) @[Bitwise.scala 102:21] + node _T_1658 = shr(_T_1654, 2) @[Bitwise.scala 103:21] + node _T_1659 = and(_T_1658, _T_1657) @[Bitwise.scala 103:31] + node _T_1660 = bits(_T_1654, 5, 0) @[Bitwise.scala 103:46] + node _T_1661 = shl(_T_1660, 2) @[Bitwise.scala 103:65] + node _T_1662 = not(_T_1657) @[Bitwise.scala 103:77] + node _T_1663 = and(_T_1661, _T_1662) @[Bitwise.scala 103:75] + node _T_1664 = or(_T_1659, _T_1663) @[Bitwise.scala 103:39] + node _T_1665 = bits(_T_1657, 6, 0) @[Bitwise.scala 102:28] + node _T_1666 = shl(_T_1665, 1) @[Bitwise.scala 102:47] + node _T_1667 = xor(_T_1657, _T_1666) @[Bitwise.scala 102:21] + node _T_1668 = shr(_T_1664, 1) @[Bitwise.scala 103:21] + node _T_1669 = and(_T_1668, _T_1667) @[Bitwise.scala 103:31] + node _T_1670 = bits(_T_1664, 6, 0) @[Bitwise.scala 103:46] + node _T_1671 = shl(_T_1670, 1) @[Bitwise.scala 103:65] + node _T_1672 = not(_T_1667) @[Bitwise.scala 103:77] + node _T_1673 = and(_T_1671, _T_1672) @[Bitwise.scala 103:75] + node _T_1674 = or(_T_1669, _T_1673) @[Bitwise.scala 103:39] + node _T_1675 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105] + node _T_1676 = bits(store_byteen_ext_r, 5, 5) @[lsu_dccm_ctl.scala 264:150] + node _T_1677 = eq(_T_1676, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131] + node _T_1678 = and(_T_1675, _T_1677) @[lsu_dccm_ctl.scala 264:129] + node _T_1679 = bits(_T_1678, 0, 0) @[lsu_dccm_ctl.scala 264:157] + node _T_1680 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 264:181] + node _T_1681 = bits(io.store_data_hi_r, 15, 8) @[lsu_dccm_ctl.scala 264:213] + node _T_1682 = mux(_T_1679, _T_1680, _T_1681) @[lsu_dccm_ctl.scala 264:79] + node _T_1683 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1684 = xor(UInt<8>("h0ff"), _T_1683) @[Bitwise.scala 102:21] + node _T_1685 = shr(_T_1682, 4) @[Bitwise.scala 103:21] + node _T_1686 = and(_T_1685, _T_1684) @[Bitwise.scala 103:31] + node _T_1687 = bits(_T_1682, 3, 0) @[Bitwise.scala 103:46] + node _T_1688 = shl(_T_1687, 4) @[Bitwise.scala 103:65] + node _T_1689 = not(_T_1684) @[Bitwise.scala 103:77] + node _T_1690 = and(_T_1688, _T_1689) @[Bitwise.scala 103:75] + node _T_1691 = or(_T_1686, _T_1690) @[Bitwise.scala 103:39] + node _T_1692 = bits(_T_1684, 5, 0) @[Bitwise.scala 102:28] + node _T_1693 = shl(_T_1692, 2) @[Bitwise.scala 102:47] + node _T_1694 = xor(_T_1684, _T_1693) @[Bitwise.scala 102:21] + node _T_1695 = shr(_T_1691, 2) @[Bitwise.scala 103:21] + node _T_1696 = and(_T_1695, _T_1694) @[Bitwise.scala 103:31] + node _T_1697 = bits(_T_1691, 5, 0) @[Bitwise.scala 103:46] + node _T_1698 = shl(_T_1697, 2) @[Bitwise.scala 103:65] + node _T_1699 = not(_T_1694) @[Bitwise.scala 103:77] + node _T_1700 = and(_T_1698, _T_1699) @[Bitwise.scala 103:75] + node _T_1701 = or(_T_1696, _T_1700) @[Bitwise.scala 103:39] + node _T_1702 = bits(_T_1694, 6, 0) @[Bitwise.scala 102:28] + node _T_1703 = shl(_T_1702, 1) @[Bitwise.scala 102:47] + node _T_1704 = xor(_T_1694, _T_1703) @[Bitwise.scala 102:21] + node _T_1705 = shr(_T_1701, 1) @[Bitwise.scala 103:21] + node _T_1706 = and(_T_1705, _T_1704) @[Bitwise.scala 103:31] + node _T_1707 = bits(_T_1701, 6, 0) @[Bitwise.scala 103:46] + node _T_1708 = shl(_T_1707, 1) @[Bitwise.scala 103:65] + node _T_1709 = not(_T_1704) @[Bitwise.scala 103:77] + node _T_1710 = and(_T_1708, _T_1709) @[Bitwise.scala 103:75] + node _T_1711 = or(_T_1706, _T_1710) @[Bitwise.scala 103:39] + node _T_1712 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105] + node _T_1713 = bits(store_byteen_ext_r, 6, 6) @[lsu_dccm_ctl.scala 264:150] + node _T_1714 = eq(_T_1713, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131] + node _T_1715 = and(_T_1712, _T_1714) @[lsu_dccm_ctl.scala 264:129] + node _T_1716 = bits(_T_1715, 0, 0) @[lsu_dccm_ctl.scala 264:157] + node _T_1717 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 264:181] + node _T_1718 = bits(io.store_data_hi_r, 23, 16) @[lsu_dccm_ctl.scala 264:213] + node _T_1719 = mux(_T_1716, _T_1717, _T_1718) @[lsu_dccm_ctl.scala 264:79] + node _T_1720 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1721 = xor(UInt<8>("h0ff"), _T_1720) @[Bitwise.scala 102:21] + node _T_1722 = shr(_T_1719, 4) @[Bitwise.scala 103:21] + node _T_1723 = and(_T_1722, _T_1721) @[Bitwise.scala 103:31] + node _T_1724 = bits(_T_1719, 3, 0) @[Bitwise.scala 103:46] + node _T_1725 = shl(_T_1724, 4) @[Bitwise.scala 103:65] + node _T_1726 = not(_T_1721) @[Bitwise.scala 103:77] + node _T_1727 = and(_T_1725, _T_1726) @[Bitwise.scala 103:75] + node _T_1728 = or(_T_1723, _T_1727) @[Bitwise.scala 103:39] + node _T_1729 = bits(_T_1721, 5, 0) @[Bitwise.scala 102:28] + node _T_1730 = shl(_T_1729, 2) @[Bitwise.scala 102:47] + node _T_1731 = xor(_T_1721, _T_1730) @[Bitwise.scala 102:21] + node _T_1732 = shr(_T_1728, 2) @[Bitwise.scala 103:21] + node _T_1733 = and(_T_1732, _T_1731) @[Bitwise.scala 103:31] + node _T_1734 = bits(_T_1728, 5, 0) @[Bitwise.scala 103:46] + node _T_1735 = shl(_T_1734, 2) @[Bitwise.scala 103:65] + node _T_1736 = not(_T_1731) @[Bitwise.scala 103:77] + node _T_1737 = and(_T_1735, _T_1736) @[Bitwise.scala 103:75] + node _T_1738 = or(_T_1733, _T_1737) @[Bitwise.scala 103:39] + node _T_1739 = bits(_T_1731, 6, 0) @[Bitwise.scala 102:28] + node _T_1740 = shl(_T_1739, 1) @[Bitwise.scala 102:47] + node _T_1741 = xor(_T_1731, _T_1740) @[Bitwise.scala 102:21] + node _T_1742 = shr(_T_1738, 1) @[Bitwise.scala 103:21] + node _T_1743 = and(_T_1742, _T_1741) @[Bitwise.scala 103:31] + node _T_1744 = bits(_T_1738, 6, 0) @[Bitwise.scala 103:46] + node _T_1745 = shl(_T_1744, 1) @[Bitwise.scala 103:65] + node _T_1746 = not(_T_1741) @[Bitwise.scala 103:77] + node _T_1747 = and(_T_1745, _T_1746) @[Bitwise.scala 103:75] + node _T_1748 = or(_T_1743, _T_1747) @[Bitwise.scala 103:39] + node _T_1749 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105] + node _T_1750 = bits(store_byteen_ext_r, 7, 7) @[lsu_dccm_ctl.scala 264:150] + node _T_1751 = eq(_T_1750, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131] + node _T_1752 = and(_T_1749, _T_1751) @[lsu_dccm_ctl.scala 264:129] + node _T_1753 = bits(_T_1752, 0, 0) @[lsu_dccm_ctl.scala 264:157] + node _T_1754 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 264:181] + node _T_1755 = bits(io.store_data_hi_r, 31, 24) @[lsu_dccm_ctl.scala 264:213] + node _T_1756 = mux(_T_1753, _T_1754, _T_1755) @[lsu_dccm_ctl.scala 264:79] + node _T_1757 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1758 = xor(UInt<8>("h0ff"), _T_1757) @[Bitwise.scala 102:21] + node _T_1759 = shr(_T_1756, 4) @[Bitwise.scala 103:21] + node _T_1760 = and(_T_1759, _T_1758) @[Bitwise.scala 103:31] + node _T_1761 = bits(_T_1756, 3, 0) @[Bitwise.scala 103:46] + node _T_1762 = shl(_T_1761, 4) @[Bitwise.scala 103:65] + node _T_1763 = not(_T_1758) @[Bitwise.scala 103:77] + node _T_1764 = and(_T_1762, _T_1763) @[Bitwise.scala 103:75] + node _T_1765 = or(_T_1760, _T_1764) @[Bitwise.scala 103:39] + node _T_1766 = bits(_T_1758, 5, 0) @[Bitwise.scala 102:28] + node _T_1767 = shl(_T_1766, 2) @[Bitwise.scala 102:47] + node _T_1768 = xor(_T_1758, _T_1767) @[Bitwise.scala 102:21] + node _T_1769 = shr(_T_1765, 2) @[Bitwise.scala 103:21] + node _T_1770 = and(_T_1769, _T_1768) @[Bitwise.scala 103:31] + node _T_1771 = bits(_T_1765, 5, 0) @[Bitwise.scala 103:46] + node _T_1772 = shl(_T_1771, 2) @[Bitwise.scala 103:65] + node _T_1773 = not(_T_1768) @[Bitwise.scala 103:77] + node _T_1774 = and(_T_1772, _T_1773) @[Bitwise.scala 103:75] + node _T_1775 = or(_T_1770, _T_1774) @[Bitwise.scala 103:39] + node _T_1776 = bits(_T_1768, 6, 0) @[Bitwise.scala 102:28] + node _T_1777 = shl(_T_1776, 1) @[Bitwise.scala 102:47] + node _T_1778 = xor(_T_1768, _T_1777) @[Bitwise.scala 102:21] + node _T_1779 = shr(_T_1775, 1) @[Bitwise.scala 103:21] + node _T_1780 = and(_T_1779, _T_1778) @[Bitwise.scala 103:31] + node _T_1781 = bits(_T_1775, 6, 0) @[Bitwise.scala 103:46] + node _T_1782 = shl(_T_1781, 1) @[Bitwise.scala 103:65] + node _T_1783 = not(_T_1778) @[Bitwise.scala 103:77] + node _T_1784 = and(_T_1782, _T_1783) @[Bitwise.scala 103:75] + node _T_1785 = or(_T_1780, _T_1784) @[Bitwise.scala 103:39] + wire _T_1786 : UInt<8>[4] @[lsu_dccm_ctl.scala 264:63] + _T_1786[0] <= _T_1674 @[lsu_dccm_ctl.scala 264:63] + _T_1786[1] <= _T_1711 @[lsu_dccm_ctl.scala 264:63] + _T_1786[2] <= _T_1748 @[lsu_dccm_ctl.scala 264:63] + _T_1786[3] <= _T_1785 @[lsu_dccm_ctl.scala 264:63] + node _T_1787 = cat(_T_1786[2], _T_1786[3]) @[Cat.scala 29:58] + node _T_1788 = cat(_T_1786[0], _T_1786[1]) @[Cat.scala 29:58] + node _T_1789 = cat(_T_1788, _T_1787) @[Cat.scala 29:58] + node _T_1790 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1791 = xor(UInt<32>("h0ffffffff"), _T_1790) @[Bitwise.scala 102:21] + node _T_1792 = shr(_T_1789, 16) @[Bitwise.scala 103:21] + node _T_1793 = and(_T_1792, _T_1791) @[Bitwise.scala 103:31] + node _T_1794 = bits(_T_1789, 15, 0) @[Bitwise.scala 103:46] + node _T_1795 = shl(_T_1794, 16) @[Bitwise.scala 103:65] + node _T_1796 = not(_T_1791) @[Bitwise.scala 103:77] + node _T_1797 = and(_T_1795, _T_1796) @[Bitwise.scala 103:75] + node _T_1798 = or(_T_1793, _T_1797) @[Bitwise.scala 103:39] + node _T_1799 = bits(_T_1791, 23, 0) @[Bitwise.scala 102:28] + node _T_1800 = shl(_T_1799, 8) @[Bitwise.scala 102:47] + node _T_1801 = xor(_T_1791, _T_1800) @[Bitwise.scala 102:21] + node _T_1802 = shr(_T_1798, 8) @[Bitwise.scala 103:21] + node _T_1803 = and(_T_1802, _T_1801) @[Bitwise.scala 103:31] + node _T_1804 = bits(_T_1798, 23, 0) @[Bitwise.scala 103:46] + node _T_1805 = shl(_T_1804, 8) @[Bitwise.scala 103:65] + node _T_1806 = not(_T_1801) @[Bitwise.scala 103:77] + node _T_1807 = and(_T_1805, _T_1806) @[Bitwise.scala 103:75] + node _T_1808 = or(_T_1803, _T_1807) @[Bitwise.scala 103:39] + node _T_1809 = bits(_T_1801, 27, 0) @[Bitwise.scala 102:28] + node _T_1810 = shl(_T_1809, 4) @[Bitwise.scala 102:47] + node _T_1811 = xor(_T_1801, _T_1810) @[Bitwise.scala 102:21] + node _T_1812 = shr(_T_1808, 4) @[Bitwise.scala 103:21] + node _T_1813 = and(_T_1812, _T_1811) @[Bitwise.scala 103:31] + node _T_1814 = bits(_T_1808, 27, 0) @[Bitwise.scala 103:46] + node _T_1815 = shl(_T_1814, 4) @[Bitwise.scala 103:65] + node _T_1816 = not(_T_1811) @[Bitwise.scala 103:77] + node _T_1817 = and(_T_1815, _T_1816) @[Bitwise.scala 103:75] + node _T_1818 = or(_T_1813, _T_1817) @[Bitwise.scala 103:39] + node _T_1819 = bits(_T_1811, 29, 0) @[Bitwise.scala 102:28] + node _T_1820 = shl(_T_1819, 2) @[Bitwise.scala 102:47] + node _T_1821 = xor(_T_1811, _T_1820) @[Bitwise.scala 102:21] + node _T_1822 = shr(_T_1818, 2) @[Bitwise.scala 103:21] + node _T_1823 = and(_T_1822, _T_1821) @[Bitwise.scala 103:31] + node _T_1824 = bits(_T_1818, 29, 0) @[Bitwise.scala 103:46] + node _T_1825 = shl(_T_1824, 2) @[Bitwise.scala 103:65] + node _T_1826 = not(_T_1821) @[Bitwise.scala 103:77] + node _T_1827 = and(_T_1825, _T_1826) @[Bitwise.scala 103:75] + node _T_1828 = or(_T_1823, _T_1827) @[Bitwise.scala 103:39] + node _T_1829 = bits(_T_1821, 30, 0) @[Bitwise.scala 102:28] + node _T_1830 = shl(_T_1829, 1) @[Bitwise.scala 102:47] + node _T_1831 = xor(_T_1821, _T_1830) @[Bitwise.scala 102:21] + node _T_1832 = shr(_T_1828, 1) @[Bitwise.scala 103:21] + node _T_1833 = and(_T_1832, _T_1831) @[Bitwise.scala 103:31] + node _T_1834 = bits(_T_1828, 30, 0) @[Bitwise.scala 103:46] + node _T_1835 = shl(_T_1834, 1) @[Bitwise.scala 103:65] + node _T_1836 = not(_T_1831) @[Bitwise.scala 103:77] + node _T_1837 = and(_T_1835, _T_1836) @[Bitwise.scala 103:75] + node _T_1838 = or(_T_1833, _T_1837) @[Bitwise.scala 103:39] + io.store_datafn_hi_r <= _T_1838 @[lsu_dccm_ctl.scala 264:29] + node _T_1839 = bits(io.store_data_hi_r, 31, 0) @[lsu_dccm_ctl.scala 265:55] + node _T_1840 = bits(io.store_data_lo_r, 31, 0) @[lsu_dccm_ctl.scala 265:80] + node _T_1841 = cat(_T_1839, _T_1840) @[Cat.scala 29:58] + node _T_1842 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 265:108] + node _T_1843 = mul(UInt<4>("h08"), _T_1842) @[lsu_dccm_ctl.scala 265:94] + node _T_1844 = dshr(_T_1841, _T_1843) @[lsu_dccm_ctl.scala 265:88] + node _T_1845 = bits(store_byteen_r, 0, 0) @[lsu_dccm_ctl.scala 265:174] + node _T_1846 = bits(_T_1845, 0, 0) @[Bitwise.scala 72:15] + node _T_1847 = mux(_T_1846, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1848 = bits(store_byteen_r, 1, 1) @[lsu_dccm_ctl.scala 265:174] + node _T_1849 = bits(_T_1848, 0, 0) @[Bitwise.scala 72:15] + node _T_1850 = mux(_T_1849, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1851 = bits(store_byteen_r, 2, 2) @[lsu_dccm_ctl.scala 265:174] + node _T_1852 = bits(_T_1851, 0, 0) @[Bitwise.scala 72:15] + node _T_1853 = mux(_T_1852, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1854 = bits(store_byteen_r, 3, 3) @[lsu_dccm_ctl.scala 265:174] + node _T_1855 = bits(_T_1854, 0, 0) @[Bitwise.scala 72:15] + node _T_1856 = mux(_T_1855, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + wire _T_1857 : UInt<8>[4] @[lsu_dccm_ctl.scala 265:148] + _T_1857[0] <= _T_1847 @[lsu_dccm_ctl.scala 265:148] + _T_1857[1] <= _T_1850 @[lsu_dccm_ctl.scala 265:148] + _T_1857[2] <= _T_1853 @[lsu_dccm_ctl.scala 265:148] + _T_1857[3] <= _T_1856 @[lsu_dccm_ctl.scala 265:148] + node _T_1858 = cat(_T_1857[2], _T_1857[3]) @[Cat.scala 29:58] + node _T_1859 = cat(_T_1857[0], _T_1857[1]) @[Cat.scala 29:58] + node _T_1860 = cat(_T_1859, _T_1858) @[Cat.scala 29:58] + node _T_1861 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1862 = xor(UInt<32>("h0ffffffff"), _T_1861) @[Bitwise.scala 102:21] + node _T_1863 = shr(_T_1860, 16) @[Bitwise.scala 103:21] + node _T_1864 = and(_T_1863, _T_1862) @[Bitwise.scala 103:31] + node _T_1865 = bits(_T_1860, 15, 0) @[Bitwise.scala 103:46] + node _T_1866 = shl(_T_1865, 16) @[Bitwise.scala 103:65] + node _T_1867 = not(_T_1862) @[Bitwise.scala 103:77] + node _T_1868 = and(_T_1866, _T_1867) @[Bitwise.scala 103:75] + node _T_1869 = or(_T_1864, _T_1868) @[Bitwise.scala 103:39] + node _T_1870 = bits(_T_1862, 23, 0) @[Bitwise.scala 102:28] + node _T_1871 = shl(_T_1870, 8) @[Bitwise.scala 102:47] + node _T_1872 = xor(_T_1862, _T_1871) @[Bitwise.scala 102:21] + node _T_1873 = shr(_T_1869, 8) @[Bitwise.scala 103:21] + node _T_1874 = and(_T_1873, _T_1872) @[Bitwise.scala 103:31] + node _T_1875 = bits(_T_1869, 23, 0) @[Bitwise.scala 103:46] + node _T_1876 = shl(_T_1875, 8) @[Bitwise.scala 103:65] + node _T_1877 = not(_T_1872) @[Bitwise.scala 103:77] + node _T_1878 = and(_T_1876, _T_1877) @[Bitwise.scala 103:75] + node _T_1879 = or(_T_1874, _T_1878) @[Bitwise.scala 103:39] + node _T_1880 = bits(_T_1872, 27, 0) @[Bitwise.scala 102:28] + node _T_1881 = shl(_T_1880, 4) @[Bitwise.scala 102:47] + node _T_1882 = xor(_T_1872, _T_1881) @[Bitwise.scala 102:21] + node _T_1883 = shr(_T_1879, 4) @[Bitwise.scala 103:21] + node _T_1884 = and(_T_1883, _T_1882) @[Bitwise.scala 103:31] + node _T_1885 = bits(_T_1879, 27, 0) @[Bitwise.scala 103:46] + node _T_1886 = shl(_T_1885, 4) @[Bitwise.scala 103:65] + node _T_1887 = not(_T_1882) @[Bitwise.scala 103:77] + node _T_1888 = and(_T_1886, _T_1887) @[Bitwise.scala 103:75] + node _T_1889 = or(_T_1884, _T_1888) @[Bitwise.scala 103:39] + node _T_1890 = bits(_T_1882, 29, 0) @[Bitwise.scala 102:28] + node _T_1891 = shl(_T_1890, 2) @[Bitwise.scala 102:47] + node _T_1892 = xor(_T_1882, _T_1891) @[Bitwise.scala 102:21] + node _T_1893 = shr(_T_1889, 2) @[Bitwise.scala 103:21] + node _T_1894 = and(_T_1893, _T_1892) @[Bitwise.scala 103:31] + node _T_1895 = bits(_T_1889, 29, 0) @[Bitwise.scala 103:46] + node _T_1896 = shl(_T_1895, 2) @[Bitwise.scala 103:65] + node _T_1897 = not(_T_1892) @[Bitwise.scala 103:77] + node _T_1898 = and(_T_1896, _T_1897) @[Bitwise.scala 103:75] + node _T_1899 = or(_T_1894, _T_1898) @[Bitwise.scala 103:39] + node _T_1900 = bits(_T_1892, 30, 0) @[Bitwise.scala 102:28] + node _T_1901 = shl(_T_1900, 1) @[Bitwise.scala 102:47] + node _T_1902 = xor(_T_1892, _T_1901) @[Bitwise.scala 102:21] + node _T_1903 = shr(_T_1899, 1) @[Bitwise.scala 103:21] + node _T_1904 = and(_T_1903, _T_1902) @[Bitwise.scala 103:31] + node _T_1905 = bits(_T_1899, 30, 0) @[Bitwise.scala 103:46] + node _T_1906 = shl(_T_1905, 1) @[Bitwise.scala 103:65] + node _T_1907 = not(_T_1902) @[Bitwise.scala 103:77] + node _T_1908 = and(_T_1906, _T_1907) @[Bitwise.scala 103:75] + node _T_1909 = or(_T_1904, _T_1908) @[Bitwise.scala 103:39] + node _T_1910 = and(_T_1844, _T_1909) @[lsu_dccm_ctl.scala 265:115] + io.store_data_r <= _T_1910 @[lsu_dccm_ctl.scala 265:29] + node _T_1911 = bits(io.dccm.rd_data_lo, 31, 0) @[lsu_dccm_ctl.scala 267:48] + io.dccm_rdata_lo_m <= _T_1911 @[lsu_dccm_ctl.scala 267:27] + node _T_1912 = bits(io.dccm.rd_data_hi, 31, 0) @[lsu_dccm_ctl.scala 268:48] + io.dccm_rdata_hi_m <= _T_1912 @[lsu_dccm_ctl.scala 268:27] + node _T_1913 = bits(io.dccm.rd_data_lo, 38, 32) @[lsu_dccm_ctl.scala 269:48] + io.dccm_data_ecc_lo_m <= _T_1913 @[lsu_dccm_ctl.scala 269:27] + node _T_1914 = bits(io.dccm.rd_data_hi, 38, 32) @[lsu_dccm_ctl.scala 270:48] + io.dccm_data_ecc_hi_m <= _T_1914 @[lsu_dccm_ctl.scala 270:27] + node _T_1915 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[lsu_dccm_ctl.scala 272:58] + node _T_1916 = and(_T_1915, io.addr_in_pic_r) @[lsu_dccm_ctl.scala 272:84] + node _T_1917 = and(_T_1916, io.lsu_commit_r) @[lsu_dccm_ctl.scala 272:103] + node _T_1918 = or(_T_1917, io.dma_pic_wen) @[lsu_dccm_ctl.scala 272:122] + io.lsu_pic.picm_wren <= _T_1918 @[lsu_dccm_ctl.scala 272:35] + node _T_1919 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.load) @[lsu_dccm_ctl.scala 273:58] + node _T_1920 = and(_T_1919, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 273:84] + io.lsu_pic.picm_rden <= _T_1920 @[lsu_dccm_ctl.scala 273:35] + node _T_1921 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 274:58] + node _T_1922 = and(_T_1921, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 274:84] + io.lsu_pic.picm_mken <= _T_1922 @[lsu_dccm_ctl.scala 274:35] + node _T_1923 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] + node _T_1924 = bits(io.lsu_addr_d, 14, 0) @[lsu_dccm_ctl.scala 275:103] + node _T_1925 = cat(_T_1923, _T_1924) @[Cat.scala 29:58] + node _T_1926 = or(UInt<32>("h0f00c0000"), _T_1925) @[lsu_dccm_ctl.scala 275:62] + io.lsu_pic.picm_rdaddr <= _T_1926 @[lsu_dccm_ctl.scala 275:35] + node _T_1927 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] + node _T_1928 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 276:109] + node _T_1929 = bits(io.dma_dccm_ctl.dma_mem_addr, 14, 0) @[lsu_dccm_ctl.scala 276:144] + node _T_1930 = bits(io.lsu_addr_r, 14, 0) @[lsu_dccm_ctl.scala 276:172] + node _T_1931 = mux(_T_1928, _T_1929, _T_1930) @[lsu_dccm_ctl.scala 276:93] + node _T_1932 = cat(_T_1927, _T_1931) @[Cat.scala 29:58] + node _T_1933 = or(UInt<32>("h0f00c0000"), _T_1932) @[lsu_dccm_ctl.scala 276:62] + io.lsu_pic.picm_wraddr <= _T_1933 @[lsu_dccm_ctl.scala 276:35] + node _T_1934 = bits(picm_rd_data_m, 31, 0) @[lsu_dccm_ctl.scala 277:44] + io.picm_mask_data_m <= _T_1934 @[lsu_dccm_ctl.scala 277:27] + node _T_1935 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 278:57] + node _T_1936 = bits(io.dma_dccm_ctl.dma_mem_wdata, 31, 0) @[lsu_dccm_ctl.scala 278:93] + node _T_1937 = bits(io.store_datafn_lo_r, 31, 0) @[lsu_dccm_ctl.scala 278:120] + node _T_1938 = mux(_T_1935, _T_1936, _T_1937) @[lsu_dccm_ctl.scala 278:41] + io.lsu_pic.picm_wr_data <= _T_1938 @[lsu_dccm_ctl.scala 278:35] + reg _T_1939 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 280:61] + _T_1939 <= lsu_dccm_rden_d @[lsu_dccm_ctl.scala 280:61] + io.lsu_dccm_rden_m <= _T_1939 @[lsu_dccm_ctl.scala 280:24] + reg _T_1940 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 281:61] + _T_1940 <= io.lsu_dccm_rden_m @[lsu_dccm_ctl.scala 281:61] + io.lsu_dccm_rden_r <= _T_1940 @[lsu_dccm_ctl.scala 281:24] + reg _T_1941 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 282:73] + _T_1941 <= io.lsu_double_ecc_error_r @[lsu_dccm_ctl.scala 282:73] + lsu_double_ecc_error_r_ff <= _T_1941 @[lsu_dccm_ctl.scala 282:33] + reg _T_1942 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 283:73] + _T_1942 <= ld_single_ecc_error_hi_r_ns @[lsu_dccm_ctl.scala 283:73] + ld_single_ecc_error_hi_r_ff <= _T_1942 @[lsu_dccm_ctl.scala 283:33] + reg _T_1943 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 284:73] + _T_1943 <= ld_single_ecc_error_lo_r_ns @[lsu_dccm_ctl.scala 284:73] + ld_single_ecc_error_lo_r_ff <= _T_1943 @[lsu_dccm_ctl.scala 284:33] + node _T_1944 = bits(io.end_addr_r, 15, 0) @[lsu_dccm_ctl.scala 285:48] + node _T_1945 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 285:90] + node _T_1946 = bits(_T_1945, 0, 0) @[lib.scala 8:44] + node _T_1947 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 285:128] + inst rvclkhdr_2 of rvclkhdr_6 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_1946 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1948 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1946 : @[Reg.scala 28:19] + _T_1948 <= _T_1944 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ld_sec_addr_hi_r_ff <= _T_1948 @[lsu_dccm_ctl.scala 285:25] + node _T_1949 = bits(io.lsu_addr_r, 15, 0) @[lsu_dccm_ctl.scala 286:48] + node _T_1950 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 286:90] + node _T_1951 = bits(_T_1950, 0, 0) @[lib.scala 8:44] + node _T_1952 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 286:128] + inst rvclkhdr_3 of rvclkhdr_7 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_1951 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1953 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1951 : @[Reg.scala 28:19] + _T_1953 <= _T_1949 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ld_sec_addr_lo_r_ff <= _T_1953 @[lsu_dccm_ctl.scala 286:25] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_stbuf : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_stbuf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip store_stbuf_reqvld_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip dec_lsu_valid_raw_d : UInt<1>, flip store_data_hi_r : UInt<32>, flip store_data_lo_r : UInt<32>, flip store_datafn_hi_r : UInt<32>, flip store_datafn_lo_r : UInt<32>, flip lsu_stbuf_commit_any : UInt<1>, flip lsu_addr_d : UInt<16>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_cmpen_m : UInt<1>, flip scan_mode : UInt<1>, stbuf_reqvld_any : UInt<1>, stbuf_reqvld_flushed_any : UInt<1>, stbuf_addr_any : UInt<16>, stbuf_data_any : UInt<32>, lsu_stbuf_full_any : UInt<1>, lsu_stbuf_empty_any : UInt<1>, ldst_stbuf_reqvld_r : UInt<1>, stbuf_fwddata_hi_m : UInt<32>, stbuf_fwddata_lo_m : UInt<32>, stbuf_fwdbyteen_hi_m : UInt<4>, stbuf_fwdbyteen_lo_m : UInt<4>} + + io.stbuf_reqvld_any <= UInt<1>("h00") @[lsu_stbuf.scala 51:47] + io.stbuf_reqvld_flushed_any <= UInt<1>("h00") @[lsu_stbuf.scala 52:35] + io.stbuf_addr_any <= UInt<1>("h00") @[lsu_stbuf.scala 53:35] + io.stbuf_data_any <= UInt<1>("h00") @[lsu_stbuf.scala 54:35] + io.lsu_stbuf_full_any <= UInt<1>("h00") @[lsu_stbuf.scala 55:43] + io.lsu_stbuf_empty_any <= UInt<1>("h00") @[lsu_stbuf.scala 56:43] + io.ldst_stbuf_reqvld_r <= UInt<1>("h00") @[lsu_stbuf.scala 57:43] + io.stbuf_fwddata_hi_m <= UInt<1>("h00") @[lsu_stbuf.scala 58:43] + io.stbuf_fwddata_lo_m <= UInt<1>("h00") @[lsu_stbuf.scala 59:43] + io.stbuf_fwdbyteen_hi_m <= UInt<1>("h00") @[lsu_stbuf.scala 60:37] + io.stbuf_fwdbyteen_lo_m <= UInt<1>("h00") @[lsu_stbuf.scala 61:37] + wire stbuf_vld : UInt<4> + stbuf_vld <= UInt<1>("h00") + wire stbuf_wr_en : UInt<4> + stbuf_wr_en <= UInt<1>("h00") + wire stbuf_dma_kill_en : UInt<4> + stbuf_dma_kill_en <= UInt<1>("h00") + wire stbuf_dma_kill : UInt<4> + stbuf_dma_kill <= UInt<1>("h00") + wire stbuf_reset : UInt<4> + stbuf_reset <= UInt<1>("h00") + wire store_byteen_ext_r : UInt<8> + store_byteen_ext_r <= UInt<1>("h00") + wire stbuf_addr : UInt<16>[4] @[lsu_stbuf.scala 70:38] + stbuf_addr[0] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + stbuf_addr[1] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + stbuf_addr[2] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + stbuf_addr[3] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + wire stbuf_byteen : UInt<4>[4] @[lsu_stbuf.scala 72:38] + stbuf_byteen[0] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + stbuf_byteen[1] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + stbuf_byteen[2] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + stbuf_byteen[3] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + wire stbuf_data : UInt<32>[4] @[lsu_stbuf.scala 74:38] + stbuf_data[0] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + stbuf_data[1] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + stbuf_data[2] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + stbuf_data[3] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + wire stbuf_addrin : UInt<16>[4] @[lsu_stbuf.scala 76:38] + stbuf_addrin[0] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + stbuf_addrin[1] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + stbuf_addrin[2] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + stbuf_addrin[3] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + wire stbuf_datain : UInt<32>[4] @[lsu_stbuf.scala 78:38] + stbuf_datain[0] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + stbuf_datain[1] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + stbuf_datain[2] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + stbuf_datain[3] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + wire stbuf_byteenin : UInt<4>[4] @[lsu_stbuf.scala 80:38] + stbuf_byteenin[0] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + stbuf_byteenin[1] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + stbuf_byteenin[2] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + stbuf_byteenin[3] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + wire WrPtr : UInt<2> + WrPtr <= UInt<1>("h00") + wire RdPtr : UInt<2> + RdPtr <= UInt<1>("h00") + wire cmpaddr_hi_m : UInt<16> + cmpaddr_hi_m <= UInt<16>("h00") + wire stbuf_specvld_m : UInt<2> + stbuf_specvld_m <= UInt<2>("h00") + wire stbuf_specvld_r : UInt<2> + stbuf_specvld_r <= UInt<2>("h00") + wire cmpaddr_lo_m : UInt<16> + cmpaddr_lo_m <= UInt<16>("h00") + wire stbuf_fwdata_hi_pre_m : UInt<32> + stbuf_fwdata_hi_pre_m <= UInt<1>("h00") + wire stbuf_fwdata_lo_pre_m : UInt<32> + stbuf_fwdata_lo_pre_m <= UInt<1>("h00") + wire ld_byte_rhit_lo_lo : UInt<4> + ld_byte_rhit_lo_lo <= UInt<1>("h00") + wire ld_byte_rhit_hi_lo : UInt<4> + ld_byte_rhit_hi_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo_hi : UInt<4> + ld_byte_rhit_lo_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi_hi : UInt<4> + ld_byte_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_hit_lo : UInt<4> + ld_byte_hit_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo : UInt<4> + ld_byte_rhit_lo <= UInt<1>("h00") + wire ld_byte_hit_hi : UInt<4> + ld_byte_hit_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi : UInt<4> + ld_byte_rhit_hi <= UInt<1>("h00") + wire ldst_byteen_ext_r : UInt<8> + ldst_byteen_ext_r <= UInt<1>("h00") + wire ld_fwddata_rpipe_lo : UInt<32> + ld_fwddata_rpipe_lo <= UInt<1>("h00") + wire ld_fwddata_rpipe_hi : UInt<32> + ld_fwddata_rpipe_hi <= UInt<1>("h00") + wire datain1 : UInt<8>[4] @[lsu_stbuf.scala 103:33] + wire datain2 : UInt<8>[4] @[lsu_stbuf.scala 104:33] + wire datain3 : UInt<8>[4] @[lsu_stbuf.scala 105:33] + wire datain4 : UInt<8>[4] @[lsu_stbuf.scala 106:33] + node _T = bits(io.lsu_pkt_r.bits.by, 0, 0) @[lsu_stbuf.scala 110:26] + node _T_1 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[lsu_stbuf.scala 111:28] + node _T_2 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[lsu_stbuf.scala 112:28] + node _T_3 = bits(io.lsu_pkt_r.bits.dword, 0, 0) @[lsu_stbuf.scala 113:29] + node _T_4 = mux(_T, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_1, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = mux(_T_2, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_7 = mux(_T_3, UInt<8>("h0ff"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_8 = or(_T_4, _T_5) @[Mux.scala 27:72] + node _T_9 = or(_T_8, _T_6) @[Mux.scala 27:72] + node _T_10 = or(_T_9, _T_7) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<8> @[Mux.scala 27:72] + ldst_byteen_r <= _T_10 @[Mux.scala 27:72] + node dual_stbuf_write_r = and(io.ldst_dual_r, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 115:43] + node _T_11 = bits(io.lsu_addr_r, 1, 0) @[lsu_stbuf.scala 117:55] + node _T_12 = dshl(ldst_byteen_r, _T_11) @[lsu_stbuf.scala 117:39] + store_byteen_ext_r <= _T_12 @[lsu_stbuf.scala 117:22] + node _T_13 = bits(store_byteen_ext_r, 7, 4) @[lsu_stbuf.scala 118:46] + node _T_14 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_15 = mux(_T_14, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node store_byteen_hi_r = and(_T_13, _T_15) @[lsu_stbuf.scala 118:52] + node _T_16 = bits(store_byteen_ext_r, 3, 0) @[lsu_stbuf.scala 119:46] + node _T_17 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_18 = mux(_T_17, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node store_byteen_lo_r = and(_T_16, _T_18) @[lsu_stbuf.scala 119:52] + node _T_19 = add(RdPtr, UInt<1>("h01")) @[lsu_stbuf.scala 121:26] + node RdPtrPlus1 = tail(_T_19, 1) @[lsu_stbuf.scala 121:26] + node _T_20 = add(WrPtr, UInt<1>("h01")) @[lsu_stbuf.scala 122:26] + node WrPtrPlus1 = tail(_T_20, 1) @[lsu_stbuf.scala 122:26] + node _T_21 = add(WrPtr, UInt<2>("h02")) @[lsu_stbuf.scala 123:26] + node WrPtrPlus2 = tail(_T_21, 1) @[lsu_stbuf.scala 123:26] + node _T_22 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_stbuf.scala 125:46] + node _T_23 = and(_T_22, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 125:71] + io.ldst_stbuf_reqvld_r <= _T_23 @[lsu_stbuf.scala 125:26] + node _T_24 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 127:78] + node _T_25 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 127:137] + node _T_26 = eq(_T_24, _T_25) @[lsu_stbuf.scala 127:120] + node _T_27 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 127:191] + node _T_28 = and(_T_26, _T_27) @[lsu_stbuf.scala 127:179] + node _T_29 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 127:212] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_stbuf.scala 127:197] + node _T_31 = and(_T_28, _T_30) @[lsu_stbuf.scala 127:195] + node _T_32 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 127:230] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[lsu_stbuf.scala 127:218] + node _T_34 = and(_T_31, _T_33) @[lsu_stbuf.scala 127:216] + node _T_35 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 127:78] + node _T_36 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 127:137] + node _T_37 = eq(_T_35, _T_36) @[lsu_stbuf.scala 127:120] + node _T_38 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 127:191] + node _T_39 = and(_T_37, _T_38) @[lsu_stbuf.scala 127:179] + node _T_40 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 127:212] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[lsu_stbuf.scala 127:197] + node _T_42 = and(_T_39, _T_41) @[lsu_stbuf.scala 127:195] + node _T_43 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 127:230] + node _T_44 = eq(_T_43, UInt<1>("h00")) @[lsu_stbuf.scala 127:218] + node _T_45 = and(_T_42, _T_44) @[lsu_stbuf.scala 127:216] + node _T_46 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 127:78] + node _T_47 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 127:137] + node _T_48 = eq(_T_46, _T_47) @[lsu_stbuf.scala 127:120] + node _T_49 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 127:191] + node _T_50 = and(_T_48, _T_49) @[lsu_stbuf.scala 127:179] + node _T_51 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 127:212] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[lsu_stbuf.scala 127:197] + node _T_53 = and(_T_50, _T_52) @[lsu_stbuf.scala 127:195] + node _T_54 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 127:230] + node _T_55 = eq(_T_54, UInt<1>("h00")) @[lsu_stbuf.scala 127:218] + node _T_56 = and(_T_53, _T_55) @[lsu_stbuf.scala 127:216] + node _T_57 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 127:78] + node _T_58 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 127:137] + node _T_59 = eq(_T_57, _T_58) @[lsu_stbuf.scala 127:120] + node _T_60 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 127:191] + node _T_61 = and(_T_59, _T_60) @[lsu_stbuf.scala 127:179] + node _T_62 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 127:212] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[lsu_stbuf.scala 127:197] + node _T_64 = and(_T_61, _T_63) @[lsu_stbuf.scala 127:195] + node _T_65 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 127:230] + node _T_66 = eq(_T_65, UInt<1>("h00")) @[lsu_stbuf.scala 127:218] + node _T_67 = and(_T_64, _T_66) @[lsu_stbuf.scala 127:216] + node _T_68 = cat(_T_67, _T_56) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_45) @[Cat.scala 29:58] + node store_matchvec_lo_r = cat(_T_69, _T_34) @[Cat.scala 29:58] + node _T_70 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 128:78] + node _T_71 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 128:137] + node _T_72 = eq(_T_70, _T_71) @[lsu_stbuf.scala 128:120] + node _T_73 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 128:190] + node _T_74 = and(_T_72, _T_73) @[lsu_stbuf.scala 128:179] + node _T_75 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 128:211] + node _T_76 = eq(_T_75, UInt<1>("h00")) @[lsu_stbuf.scala 128:196] + node _T_77 = and(_T_74, _T_76) @[lsu_stbuf.scala 128:194] + node _T_78 = and(_T_77, dual_stbuf_write_r) @[lsu_stbuf.scala 128:215] + node _T_79 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 128:250] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[lsu_stbuf.scala 128:238] + node _T_81 = and(_T_78, _T_80) @[lsu_stbuf.scala 128:236] + node _T_82 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 128:78] + node _T_83 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 128:137] + node _T_84 = eq(_T_82, _T_83) @[lsu_stbuf.scala 128:120] + node _T_85 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 128:190] + node _T_86 = and(_T_84, _T_85) @[lsu_stbuf.scala 128:179] + node _T_87 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 128:211] + node _T_88 = eq(_T_87, UInt<1>("h00")) @[lsu_stbuf.scala 128:196] + node _T_89 = and(_T_86, _T_88) @[lsu_stbuf.scala 128:194] + node _T_90 = and(_T_89, dual_stbuf_write_r) @[lsu_stbuf.scala 128:215] + node _T_91 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 128:250] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[lsu_stbuf.scala 128:238] + node _T_93 = and(_T_90, _T_92) @[lsu_stbuf.scala 128:236] + node _T_94 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 128:78] + node _T_95 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 128:137] + node _T_96 = eq(_T_94, _T_95) @[lsu_stbuf.scala 128:120] + node _T_97 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 128:190] + node _T_98 = and(_T_96, _T_97) @[lsu_stbuf.scala 128:179] + node _T_99 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 128:211] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[lsu_stbuf.scala 128:196] + node _T_101 = and(_T_98, _T_100) @[lsu_stbuf.scala 128:194] + node _T_102 = and(_T_101, dual_stbuf_write_r) @[lsu_stbuf.scala 128:215] + node _T_103 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 128:250] + node _T_104 = eq(_T_103, UInt<1>("h00")) @[lsu_stbuf.scala 128:238] + node _T_105 = and(_T_102, _T_104) @[lsu_stbuf.scala 128:236] + node _T_106 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 128:78] + node _T_107 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 128:137] + node _T_108 = eq(_T_106, _T_107) @[lsu_stbuf.scala 128:120] + node _T_109 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 128:190] + node _T_110 = and(_T_108, _T_109) @[lsu_stbuf.scala 128:179] + node _T_111 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 128:211] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[lsu_stbuf.scala 128:196] + node _T_113 = and(_T_110, _T_112) @[lsu_stbuf.scala 128:194] + node _T_114 = and(_T_113, dual_stbuf_write_r) @[lsu_stbuf.scala 128:215] + node _T_115 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 128:250] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[lsu_stbuf.scala 128:238] + node _T_117 = and(_T_114, _T_116) @[lsu_stbuf.scala 128:236] + node _T_118 = cat(_T_117, _T_105) @[Cat.scala 29:58] + node _T_119 = cat(_T_118, _T_93) @[Cat.scala 29:58] + node store_matchvec_hi_r = cat(_T_119, _T_81) @[Cat.scala 29:58] + node store_coalesce_lo_r = orr(store_matchvec_lo_r) @[lsu_stbuf.scala 130:49] + node store_coalesce_hi_r = orr(store_matchvec_hi_r) @[lsu_stbuf.scala 131:49] + node _T_120 = eq(UInt<1>("h00"), WrPtr) @[lsu_stbuf.scala 134:18] + node _T_121 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 134:31] + node _T_122 = and(_T_120, _T_121) @[lsu_stbuf.scala 134:29] + node _T_123 = eq(UInt<1>("h00"), WrPtr) @[lsu_stbuf.scala 135:20] + node _T_124 = and(_T_123, dual_stbuf_write_r) @[lsu_stbuf.scala 135:31] + node _T_125 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 135:54] + node _T_126 = and(_T_124, _T_125) @[lsu_stbuf.scala 135:52] + node _T_127 = or(_T_122, _T_126) @[lsu_stbuf.scala 134:53] + node _T_128 = eq(UInt<1>("h00"), WrPtrPlus1) @[lsu_stbuf.scala 136:20] + node _T_129 = and(_T_128, dual_stbuf_write_r) @[lsu_stbuf.scala 136:36] + node _T_130 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 136:81] + node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_stbuf.scala 136:59] + node _T_132 = and(_T_129, _T_131) @[lsu_stbuf.scala 136:57] + node _T_133 = or(_T_127, _T_132) @[lsu_stbuf.scala 135:76] + node _T_134 = bits(store_matchvec_lo_r, 0, 0) @[lsu_stbuf.scala 137:28] + node _T_135 = or(_T_133, _T_134) @[lsu_stbuf.scala 136:105] + node _T_136 = bits(store_matchvec_hi_r, 0, 0) @[lsu_stbuf.scala 137:53] + node _T_137 = or(_T_135, _T_136) @[lsu_stbuf.scala 137:32] + node _T_138 = and(io.ldst_stbuf_reqvld_r, _T_137) @[lsu_stbuf.scala 133:79] + node _T_139 = eq(UInt<1>("h01"), WrPtr) @[lsu_stbuf.scala 134:18] + node _T_140 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 134:31] + node _T_141 = and(_T_139, _T_140) @[lsu_stbuf.scala 134:29] + node _T_142 = eq(UInt<1>("h01"), WrPtr) @[lsu_stbuf.scala 135:20] + node _T_143 = and(_T_142, dual_stbuf_write_r) @[lsu_stbuf.scala 135:31] + node _T_144 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 135:54] + node _T_145 = and(_T_143, _T_144) @[lsu_stbuf.scala 135:52] + node _T_146 = or(_T_141, _T_145) @[lsu_stbuf.scala 134:53] + node _T_147 = eq(UInt<1>("h01"), WrPtrPlus1) @[lsu_stbuf.scala 136:20] + node _T_148 = and(_T_147, dual_stbuf_write_r) @[lsu_stbuf.scala 136:36] + node _T_149 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 136:81] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_stbuf.scala 136:59] + node _T_151 = and(_T_148, _T_150) @[lsu_stbuf.scala 136:57] + node _T_152 = or(_T_146, _T_151) @[lsu_stbuf.scala 135:76] + node _T_153 = bits(store_matchvec_lo_r, 1, 1) @[lsu_stbuf.scala 137:28] + node _T_154 = or(_T_152, _T_153) @[lsu_stbuf.scala 136:105] + node _T_155 = bits(store_matchvec_hi_r, 1, 1) @[lsu_stbuf.scala 137:53] + node _T_156 = or(_T_154, _T_155) @[lsu_stbuf.scala 137:32] + node _T_157 = and(io.ldst_stbuf_reqvld_r, _T_156) @[lsu_stbuf.scala 133:79] + node _T_158 = eq(UInt<2>("h02"), WrPtr) @[lsu_stbuf.scala 134:18] + node _T_159 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 134:31] + node _T_160 = and(_T_158, _T_159) @[lsu_stbuf.scala 134:29] + node _T_161 = eq(UInt<2>("h02"), WrPtr) @[lsu_stbuf.scala 135:20] + node _T_162 = and(_T_161, dual_stbuf_write_r) @[lsu_stbuf.scala 135:31] + node _T_163 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 135:54] + node _T_164 = and(_T_162, _T_163) @[lsu_stbuf.scala 135:52] + node _T_165 = or(_T_160, _T_164) @[lsu_stbuf.scala 134:53] + node _T_166 = eq(UInt<2>("h02"), WrPtrPlus1) @[lsu_stbuf.scala 136:20] + node _T_167 = and(_T_166, dual_stbuf_write_r) @[lsu_stbuf.scala 136:36] + node _T_168 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 136:81] + node _T_169 = eq(_T_168, UInt<1>("h00")) @[lsu_stbuf.scala 136:59] + node _T_170 = and(_T_167, _T_169) @[lsu_stbuf.scala 136:57] + node _T_171 = or(_T_165, _T_170) @[lsu_stbuf.scala 135:76] + node _T_172 = bits(store_matchvec_lo_r, 2, 2) @[lsu_stbuf.scala 137:28] + node _T_173 = or(_T_171, _T_172) @[lsu_stbuf.scala 136:105] + node _T_174 = bits(store_matchvec_hi_r, 2, 2) @[lsu_stbuf.scala 137:53] + node _T_175 = or(_T_173, _T_174) @[lsu_stbuf.scala 137:32] + node _T_176 = and(io.ldst_stbuf_reqvld_r, _T_175) @[lsu_stbuf.scala 133:79] + node _T_177 = eq(UInt<2>("h03"), WrPtr) @[lsu_stbuf.scala 134:18] + node _T_178 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 134:31] + node _T_179 = and(_T_177, _T_178) @[lsu_stbuf.scala 134:29] + node _T_180 = eq(UInt<2>("h03"), WrPtr) @[lsu_stbuf.scala 135:20] + node _T_181 = and(_T_180, dual_stbuf_write_r) @[lsu_stbuf.scala 135:31] + node _T_182 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 135:54] + node _T_183 = and(_T_181, _T_182) @[lsu_stbuf.scala 135:52] + node _T_184 = or(_T_179, _T_183) @[lsu_stbuf.scala 134:53] + node _T_185 = eq(UInt<2>("h03"), WrPtrPlus1) @[lsu_stbuf.scala 136:20] + node _T_186 = and(_T_185, dual_stbuf_write_r) @[lsu_stbuf.scala 136:36] + node _T_187 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 136:81] + node _T_188 = eq(_T_187, UInt<1>("h00")) @[lsu_stbuf.scala 136:59] + node _T_189 = and(_T_186, _T_188) @[lsu_stbuf.scala 136:57] + node _T_190 = or(_T_184, _T_189) @[lsu_stbuf.scala 135:76] + node _T_191 = bits(store_matchvec_lo_r, 3, 3) @[lsu_stbuf.scala 137:28] + node _T_192 = or(_T_190, _T_191) @[lsu_stbuf.scala 136:105] + node _T_193 = bits(store_matchvec_hi_r, 3, 3) @[lsu_stbuf.scala 137:53] + node _T_194 = or(_T_192, _T_193) @[lsu_stbuf.scala 137:32] + node _T_195 = and(io.ldst_stbuf_reqvld_r, _T_194) @[lsu_stbuf.scala 133:79] + node _T_196 = cat(_T_195, _T_176) @[Cat.scala 29:58] + node _T_197 = cat(_T_196, _T_157) @[Cat.scala 29:58] + node _T_198 = cat(_T_197, _T_138) @[Cat.scala 29:58] + stbuf_wr_en <= _T_198 @[lsu_stbuf.scala 133:17] + node _T_199 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 138:81] + node _T_200 = eq(UInt<1>("h00"), RdPtr) @[lsu_stbuf.scala 138:124] + node _T_201 = bits(_T_200, 0, 0) @[lsu_stbuf.scala 138:135] + node _T_202 = and(_T_199, _T_201) @[lsu_stbuf.scala 138:112] + node _T_203 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 138:81] + node _T_204 = eq(UInt<1>("h01"), RdPtr) @[lsu_stbuf.scala 138:124] + node _T_205 = bits(_T_204, 0, 0) @[lsu_stbuf.scala 138:135] + node _T_206 = and(_T_203, _T_205) @[lsu_stbuf.scala 138:112] + node _T_207 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 138:81] + node _T_208 = eq(UInt<2>("h02"), RdPtr) @[lsu_stbuf.scala 138:124] + node _T_209 = bits(_T_208, 0, 0) @[lsu_stbuf.scala 138:135] + node _T_210 = and(_T_207, _T_209) @[lsu_stbuf.scala 138:112] + node _T_211 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 138:81] + node _T_212 = eq(UInt<2>("h03"), RdPtr) @[lsu_stbuf.scala 138:124] + node _T_213 = bits(_T_212, 0, 0) @[lsu_stbuf.scala 138:135] + node _T_214 = and(_T_211, _T_213) @[lsu_stbuf.scala 138:112] + node _T_215 = cat(_T_214, _T_210) @[Cat.scala 29:58] + node _T_216 = cat(_T_215, _T_206) @[Cat.scala 29:58] + node _T_217 = cat(_T_216, _T_202) @[Cat.scala 29:58] + stbuf_reset <= _T_217 @[lsu_stbuf.scala 138:17] + node _T_218 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:56] + node _T_219 = or(_T_218, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 139:72] + node _T_220 = eq(UInt<1>("h00"), WrPtr) @[lsu_stbuf.scala 139:111] + node _T_221 = bits(_T_220, 0, 0) @[lsu_stbuf.scala 139:122] + node _T_222 = and(_T_219, _T_221) @[lsu_stbuf.scala 139:99] + node _T_223 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:131] + node _T_224 = and(_T_222, _T_223) @[lsu_stbuf.scala 139:129] + node _T_225 = bits(store_matchvec_lo_r, 0, 0) @[lsu_stbuf.scala 139:174] + node _T_226 = or(_T_224, _T_225) @[lsu_stbuf.scala 139:153] + node _T_227 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:56] + node _T_228 = or(_T_227, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 139:72] + node _T_229 = eq(UInt<1>("h01"), WrPtr) @[lsu_stbuf.scala 139:111] + node _T_230 = bits(_T_229, 0, 0) @[lsu_stbuf.scala 139:122] + node _T_231 = and(_T_228, _T_230) @[lsu_stbuf.scala 139:99] + node _T_232 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:131] + node _T_233 = and(_T_231, _T_232) @[lsu_stbuf.scala 139:129] + node _T_234 = bits(store_matchvec_lo_r, 1, 1) @[lsu_stbuf.scala 139:174] + node _T_235 = or(_T_233, _T_234) @[lsu_stbuf.scala 139:153] + node _T_236 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:56] + node _T_237 = or(_T_236, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 139:72] + node _T_238 = eq(UInt<2>("h02"), WrPtr) @[lsu_stbuf.scala 139:111] + node _T_239 = bits(_T_238, 0, 0) @[lsu_stbuf.scala 139:122] + node _T_240 = and(_T_237, _T_239) @[lsu_stbuf.scala 139:99] + node _T_241 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:131] + node _T_242 = and(_T_240, _T_241) @[lsu_stbuf.scala 139:129] + node _T_243 = bits(store_matchvec_lo_r, 2, 2) @[lsu_stbuf.scala 139:174] + node _T_244 = or(_T_242, _T_243) @[lsu_stbuf.scala 139:153] + node _T_245 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:56] + node _T_246 = or(_T_245, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 139:72] + node _T_247 = eq(UInt<2>("h03"), WrPtr) @[lsu_stbuf.scala 139:111] + node _T_248 = bits(_T_247, 0, 0) @[lsu_stbuf.scala 139:122] + node _T_249 = and(_T_246, _T_248) @[lsu_stbuf.scala 139:99] + node _T_250 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 139:131] + node _T_251 = and(_T_249, _T_250) @[lsu_stbuf.scala 139:129] + node _T_252 = bits(store_matchvec_lo_r, 3, 3) @[lsu_stbuf.scala 139:174] + node _T_253 = or(_T_251, _T_252) @[lsu_stbuf.scala 139:153] + node _T_254 = cat(_T_253, _T_244) @[Cat.scala 29:58] + node _T_255 = cat(_T_254, _T_235) @[Cat.scala 29:58] + node sel_lo = cat(_T_255, _T_226) @[Cat.scala 29:58] + node _T_256 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 141:66] + node _T_257 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 141:84] + node _T_258 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 141:119] + node _T_259 = mux(_T_256, _T_257, _T_258) @[lsu_stbuf.scala 141:59] + node _T_260 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 141:66] + node _T_261 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 141:84] + node _T_262 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 141:119] + node _T_263 = mux(_T_260, _T_261, _T_262) @[lsu_stbuf.scala 141:59] + node _T_264 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 141:66] + node _T_265 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 141:84] + node _T_266 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 141:119] + node _T_267 = mux(_T_264, _T_265, _T_266) @[lsu_stbuf.scala 141:59] + node _T_268 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 141:66] + node _T_269 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 141:84] + node _T_270 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 141:119] + node _T_271 = mux(_T_268, _T_269, _T_270) @[lsu_stbuf.scala 141:59] + stbuf_addrin[0] <= _T_259 @[lsu_stbuf.scala 141:18] + stbuf_addrin[1] <= _T_263 @[lsu_stbuf.scala 141:18] + stbuf_addrin[2] <= _T_267 @[lsu_stbuf.scala 141:18] + stbuf_addrin[3] <= _T_271 @[lsu_stbuf.scala 141:18] + node _T_272 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 142:68] + node _T_273 = or(stbuf_byteen[0], store_byteen_lo_r) @[lsu_stbuf.scala 142:89] + node _T_274 = or(stbuf_byteen[0], store_byteen_hi_r) @[lsu_stbuf.scala 142:126] + node _T_275 = mux(_T_272, _T_273, _T_274) @[lsu_stbuf.scala 142:61] + node _T_276 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 142:68] + node _T_277 = or(stbuf_byteen[1], store_byteen_lo_r) @[lsu_stbuf.scala 142:89] + node _T_278 = or(stbuf_byteen[1], store_byteen_hi_r) @[lsu_stbuf.scala 142:126] + node _T_279 = mux(_T_276, _T_277, _T_278) @[lsu_stbuf.scala 142:61] + node _T_280 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 142:68] + node _T_281 = or(stbuf_byteen[2], store_byteen_lo_r) @[lsu_stbuf.scala 142:89] + node _T_282 = or(stbuf_byteen[2], store_byteen_hi_r) @[lsu_stbuf.scala 142:126] + node _T_283 = mux(_T_280, _T_281, _T_282) @[lsu_stbuf.scala 142:61] + node _T_284 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 142:68] + node _T_285 = or(stbuf_byteen[3], store_byteen_lo_r) @[lsu_stbuf.scala 142:89] + node _T_286 = or(stbuf_byteen[3], store_byteen_hi_r) @[lsu_stbuf.scala 142:126] + node _T_287 = mux(_T_284, _T_285, _T_286) @[lsu_stbuf.scala 142:61] + stbuf_byteenin[0] <= _T_275 @[lsu_stbuf.scala 142:20] + stbuf_byteenin[1] <= _T_279 @[lsu_stbuf.scala 142:20] + stbuf_byteenin[2] <= _T_283 @[lsu_stbuf.scala 142:20] + stbuf_byteenin[3] <= _T_287 @[lsu_stbuf.scala 142:20] + node _T_288 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 144:61] + node _T_289 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 144:86] + node _T_290 = eq(_T_289, UInt<1>("h00")) @[lsu_stbuf.scala 144:70] + node _T_291 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 144:109] + node _T_292 = or(_T_290, _T_291) @[lsu_stbuf.scala 144:90] + node _T_293 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 144:134] + node _T_294 = bits(stbuf_data[0], 7, 0) @[lsu_stbuf.scala 144:155] + node _T_295 = mux(_T_292, _T_293, _T_294) @[lsu_stbuf.scala 144:69] + node _T_296 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 145:27] + node _T_297 = eq(_T_296, UInt<1>("h00")) @[lsu_stbuf.scala 145:11] + node _T_298 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 145:50] + node _T_299 = or(_T_297, _T_298) @[lsu_stbuf.scala 145:31] + node _T_300 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 145:75] + node _T_301 = bits(stbuf_data[0], 7, 0) @[lsu_stbuf.scala 145:96] + node _T_302 = mux(_T_299, _T_300, _T_301) @[lsu_stbuf.scala 145:10] + node _T_303 = mux(_T_288, _T_295, _T_302) @[lsu_stbuf.scala 144:54] + node _T_304 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 144:61] + node _T_305 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 144:86] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[lsu_stbuf.scala 144:70] + node _T_307 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 144:109] + node _T_308 = or(_T_306, _T_307) @[lsu_stbuf.scala 144:90] + node _T_309 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 144:134] + node _T_310 = bits(stbuf_data[1], 7, 0) @[lsu_stbuf.scala 144:155] + node _T_311 = mux(_T_308, _T_309, _T_310) @[lsu_stbuf.scala 144:69] + node _T_312 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 145:27] + node _T_313 = eq(_T_312, UInt<1>("h00")) @[lsu_stbuf.scala 145:11] + node _T_314 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 145:50] + node _T_315 = or(_T_313, _T_314) @[lsu_stbuf.scala 145:31] + node _T_316 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 145:75] + node _T_317 = bits(stbuf_data[1], 7, 0) @[lsu_stbuf.scala 145:96] + node _T_318 = mux(_T_315, _T_316, _T_317) @[lsu_stbuf.scala 145:10] + node _T_319 = mux(_T_304, _T_311, _T_318) @[lsu_stbuf.scala 144:54] + node _T_320 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 144:61] + node _T_321 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 144:86] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[lsu_stbuf.scala 144:70] + node _T_323 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 144:109] + node _T_324 = or(_T_322, _T_323) @[lsu_stbuf.scala 144:90] + node _T_325 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 144:134] + node _T_326 = bits(stbuf_data[2], 7, 0) @[lsu_stbuf.scala 144:155] + node _T_327 = mux(_T_324, _T_325, _T_326) @[lsu_stbuf.scala 144:69] + node _T_328 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 145:27] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[lsu_stbuf.scala 145:11] + node _T_330 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 145:50] + node _T_331 = or(_T_329, _T_330) @[lsu_stbuf.scala 145:31] + node _T_332 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 145:75] + node _T_333 = bits(stbuf_data[2], 7, 0) @[lsu_stbuf.scala 145:96] + node _T_334 = mux(_T_331, _T_332, _T_333) @[lsu_stbuf.scala 145:10] + node _T_335 = mux(_T_320, _T_327, _T_334) @[lsu_stbuf.scala 144:54] + node _T_336 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 144:61] + node _T_337 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 144:86] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_stbuf.scala 144:70] + node _T_339 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 144:109] + node _T_340 = or(_T_338, _T_339) @[lsu_stbuf.scala 144:90] + node _T_341 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 144:134] + node _T_342 = bits(stbuf_data[3], 7, 0) @[lsu_stbuf.scala 144:155] + node _T_343 = mux(_T_340, _T_341, _T_342) @[lsu_stbuf.scala 144:69] + node _T_344 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 145:27] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[lsu_stbuf.scala 145:11] + node _T_346 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 145:50] + node _T_347 = or(_T_345, _T_346) @[lsu_stbuf.scala 145:31] + node _T_348 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 145:75] + node _T_349 = bits(stbuf_data[3], 7, 0) @[lsu_stbuf.scala 145:96] + node _T_350 = mux(_T_347, _T_348, _T_349) @[lsu_stbuf.scala 145:10] + node _T_351 = mux(_T_336, _T_343, _T_350) @[lsu_stbuf.scala 144:54] + datain1[0] <= _T_303 @[lsu_stbuf.scala 144:13] + datain1[1] <= _T_319 @[lsu_stbuf.scala 144:13] + datain1[2] <= _T_335 @[lsu_stbuf.scala 144:13] + datain1[3] <= _T_351 @[lsu_stbuf.scala 144:13] + node _T_352 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 147:61] + node _T_353 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 147:86] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_stbuf.scala 147:70] + node _T_355 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 147:109] + node _T_356 = or(_T_354, _T_355) @[lsu_stbuf.scala 147:90] + node _T_357 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 147:134] + node _T_358 = bits(stbuf_data[0], 15, 8) @[lsu_stbuf.scala 147:156] + node _T_359 = mux(_T_356, _T_357, _T_358) @[lsu_stbuf.scala 147:69] + node _T_360 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 148:27] + node _T_361 = eq(_T_360, UInt<1>("h00")) @[lsu_stbuf.scala 148:11] + node _T_362 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 148:50] + node _T_363 = or(_T_361, _T_362) @[lsu_stbuf.scala 148:31] + node _T_364 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 148:75] + node _T_365 = bits(stbuf_data[0], 15, 8) @[lsu_stbuf.scala 148:97] + node _T_366 = mux(_T_363, _T_364, _T_365) @[lsu_stbuf.scala 148:10] + node _T_367 = mux(_T_352, _T_359, _T_366) @[lsu_stbuf.scala 147:54] + node _T_368 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 147:61] + node _T_369 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 147:86] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[lsu_stbuf.scala 147:70] + node _T_371 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 147:109] + node _T_372 = or(_T_370, _T_371) @[lsu_stbuf.scala 147:90] + node _T_373 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 147:134] + node _T_374 = bits(stbuf_data[1], 15, 8) @[lsu_stbuf.scala 147:156] + node _T_375 = mux(_T_372, _T_373, _T_374) @[lsu_stbuf.scala 147:69] + node _T_376 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 148:27] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[lsu_stbuf.scala 148:11] + node _T_378 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 148:50] + node _T_379 = or(_T_377, _T_378) @[lsu_stbuf.scala 148:31] + node _T_380 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 148:75] + node _T_381 = bits(stbuf_data[1], 15, 8) @[lsu_stbuf.scala 148:97] + node _T_382 = mux(_T_379, _T_380, _T_381) @[lsu_stbuf.scala 148:10] + node _T_383 = mux(_T_368, _T_375, _T_382) @[lsu_stbuf.scala 147:54] + node _T_384 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 147:61] + node _T_385 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 147:86] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[lsu_stbuf.scala 147:70] + node _T_387 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 147:109] + node _T_388 = or(_T_386, _T_387) @[lsu_stbuf.scala 147:90] + node _T_389 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 147:134] + node _T_390 = bits(stbuf_data[2], 15, 8) @[lsu_stbuf.scala 147:156] + node _T_391 = mux(_T_388, _T_389, _T_390) @[lsu_stbuf.scala 147:69] + node _T_392 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 148:27] + node _T_393 = eq(_T_392, UInt<1>("h00")) @[lsu_stbuf.scala 148:11] + node _T_394 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 148:50] + node _T_395 = or(_T_393, _T_394) @[lsu_stbuf.scala 148:31] + node _T_396 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 148:75] + node _T_397 = bits(stbuf_data[2], 15, 8) @[lsu_stbuf.scala 148:97] + node _T_398 = mux(_T_395, _T_396, _T_397) @[lsu_stbuf.scala 148:10] + node _T_399 = mux(_T_384, _T_391, _T_398) @[lsu_stbuf.scala 147:54] + node _T_400 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 147:61] + node _T_401 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 147:86] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[lsu_stbuf.scala 147:70] + node _T_403 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 147:109] + node _T_404 = or(_T_402, _T_403) @[lsu_stbuf.scala 147:90] + node _T_405 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 147:134] + node _T_406 = bits(stbuf_data[3], 15, 8) @[lsu_stbuf.scala 147:156] + node _T_407 = mux(_T_404, _T_405, _T_406) @[lsu_stbuf.scala 147:69] + node _T_408 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 148:27] + node _T_409 = eq(_T_408, UInt<1>("h00")) @[lsu_stbuf.scala 148:11] + node _T_410 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 148:50] + node _T_411 = or(_T_409, _T_410) @[lsu_stbuf.scala 148:31] + node _T_412 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 148:75] + node _T_413 = bits(stbuf_data[3], 15, 8) @[lsu_stbuf.scala 148:97] + node _T_414 = mux(_T_411, _T_412, _T_413) @[lsu_stbuf.scala 148:10] + node _T_415 = mux(_T_400, _T_407, _T_414) @[lsu_stbuf.scala 147:54] + datain2[0] <= _T_367 @[lsu_stbuf.scala 147:13] + datain2[1] <= _T_383 @[lsu_stbuf.scala 147:13] + datain2[2] <= _T_399 @[lsu_stbuf.scala 147:13] + datain2[3] <= _T_415 @[lsu_stbuf.scala 147:13] + node _T_416 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 150:61] + node _T_417 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 150:86] + node _T_418 = eq(_T_417, UInt<1>("h00")) @[lsu_stbuf.scala 150:70] + node _T_419 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 150:109] + node _T_420 = or(_T_418, _T_419) @[lsu_stbuf.scala 150:90] + node _T_421 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 150:134] + node _T_422 = bits(stbuf_data[0], 23, 16) @[lsu_stbuf.scala 150:157] + node _T_423 = mux(_T_420, _T_421, _T_422) @[lsu_stbuf.scala 150:69] + node _T_424 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 151:27] + node _T_425 = eq(_T_424, UInt<1>("h00")) @[lsu_stbuf.scala 151:11] + node _T_426 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 151:50] + node _T_427 = or(_T_425, _T_426) @[lsu_stbuf.scala 151:31] + node _T_428 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 151:75] + node _T_429 = bits(stbuf_data[0], 23, 16) @[lsu_stbuf.scala 151:98] + node _T_430 = mux(_T_427, _T_428, _T_429) @[lsu_stbuf.scala 151:10] + node _T_431 = mux(_T_416, _T_423, _T_430) @[lsu_stbuf.scala 150:54] + node _T_432 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 150:61] + node _T_433 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 150:86] + node _T_434 = eq(_T_433, UInt<1>("h00")) @[lsu_stbuf.scala 150:70] + node _T_435 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 150:109] + node _T_436 = or(_T_434, _T_435) @[lsu_stbuf.scala 150:90] + node _T_437 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 150:134] + node _T_438 = bits(stbuf_data[1], 23, 16) @[lsu_stbuf.scala 150:157] + node _T_439 = mux(_T_436, _T_437, _T_438) @[lsu_stbuf.scala 150:69] + node _T_440 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 151:27] + node _T_441 = eq(_T_440, UInt<1>("h00")) @[lsu_stbuf.scala 151:11] + node _T_442 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 151:50] + node _T_443 = or(_T_441, _T_442) @[lsu_stbuf.scala 151:31] + node _T_444 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 151:75] + node _T_445 = bits(stbuf_data[1], 23, 16) @[lsu_stbuf.scala 151:98] + node _T_446 = mux(_T_443, _T_444, _T_445) @[lsu_stbuf.scala 151:10] + node _T_447 = mux(_T_432, _T_439, _T_446) @[lsu_stbuf.scala 150:54] + node _T_448 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 150:61] + node _T_449 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 150:86] + node _T_450 = eq(_T_449, UInt<1>("h00")) @[lsu_stbuf.scala 150:70] + node _T_451 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 150:109] + node _T_452 = or(_T_450, _T_451) @[lsu_stbuf.scala 150:90] + node _T_453 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 150:134] + node _T_454 = bits(stbuf_data[2], 23, 16) @[lsu_stbuf.scala 150:157] + node _T_455 = mux(_T_452, _T_453, _T_454) @[lsu_stbuf.scala 150:69] + node _T_456 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 151:27] + node _T_457 = eq(_T_456, UInt<1>("h00")) @[lsu_stbuf.scala 151:11] + node _T_458 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 151:50] + node _T_459 = or(_T_457, _T_458) @[lsu_stbuf.scala 151:31] + node _T_460 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 151:75] + node _T_461 = bits(stbuf_data[2], 23, 16) @[lsu_stbuf.scala 151:98] + node _T_462 = mux(_T_459, _T_460, _T_461) @[lsu_stbuf.scala 151:10] + node _T_463 = mux(_T_448, _T_455, _T_462) @[lsu_stbuf.scala 150:54] + node _T_464 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 150:61] + node _T_465 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 150:86] + node _T_466 = eq(_T_465, UInt<1>("h00")) @[lsu_stbuf.scala 150:70] + node _T_467 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 150:109] + node _T_468 = or(_T_466, _T_467) @[lsu_stbuf.scala 150:90] + node _T_469 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 150:134] + node _T_470 = bits(stbuf_data[3], 23, 16) @[lsu_stbuf.scala 150:157] + node _T_471 = mux(_T_468, _T_469, _T_470) @[lsu_stbuf.scala 150:69] + node _T_472 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 151:27] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[lsu_stbuf.scala 151:11] + node _T_474 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 151:50] + node _T_475 = or(_T_473, _T_474) @[lsu_stbuf.scala 151:31] + node _T_476 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 151:75] + node _T_477 = bits(stbuf_data[3], 23, 16) @[lsu_stbuf.scala 151:98] + node _T_478 = mux(_T_475, _T_476, _T_477) @[lsu_stbuf.scala 151:10] + node _T_479 = mux(_T_464, _T_471, _T_478) @[lsu_stbuf.scala 150:54] + datain3[0] <= _T_431 @[lsu_stbuf.scala 150:13] + datain3[1] <= _T_447 @[lsu_stbuf.scala 150:13] + datain3[2] <= _T_463 @[lsu_stbuf.scala 150:13] + datain3[3] <= _T_479 @[lsu_stbuf.scala 150:13] + node _T_480 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 153:61] + node _T_481 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 153:86] + node _T_482 = eq(_T_481, UInt<1>("h00")) @[lsu_stbuf.scala 153:70] + node _T_483 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 153:109] + node _T_484 = or(_T_482, _T_483) @[lsu_stbuf.scala 153:90] + node _T_485 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 153:134] + node _T_486 = bits(stbuf_data[0], 31, 24) @[lsu_stbuf.scala 153:157] + node _T_487 = mux(_T_484, _T_485, _T_486) @[lsu_stbuf.scala 153:69] + node _T_488 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 154:27] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[lsu_stbuf.scala 154:11] + node _T_490 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 154:50] + node _T_491 = or(_T_489, _T_490) @[lsu_stbuf.scala 154:31] + node _T_492 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 154:75] + node _T_493 = bits(stbuf_data[0], 31, 24) @[lsu_stbuf.scala 154:98] + node _T_494 = mux(_T_491, _T_492, _T_493) @[lsu_stbuf.scala 154:10] + node _T_495 = mux(_T_480, _T_487, _T_494) @[lsu_stbuf.scala 153:54] + node _T_496 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 153:61] + node _T_497 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 153:86] + node _T_498 = eq(_T_497, UInt<1>("h00")) @[lsu_stbuf.scala 153:70] + node _T_499 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 153:109] + node _T_500 = or(_T_498, _T_499) @[lsu_stbuf.scala 153:90] + node _T_501 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 153:134] + node _T_502 = bits(stbuf_data[1], 31, 24) @[lsu_stbuf.scala 153:157] + node _T_503 = mux(_T_500, _T_501, _T_502) @[lsu_stbuf.scala 153:69] + node _T_504 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 154:27] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[lsu_stbuf.scala 154:11] + node _T_506 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 154:50] + node _T_507 = or(_T_505, _T_506) @[lsu_stbuf.scala 154:31] + node _T_508 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 154:75] + node _T_509 = bits(stbuf_data[1], 31, 24) @[lsu_stbuf.scala 154:98] + node _T_510 = mux(_T_507, _T_508, _T_509) @[lsu_stbuf.scala 154:10] + node _T_511 = mux(_T_496, _T_503, _T_510) @[lsu_stbuf.scala 153:54] + node _T_512 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 153:61] + node _T_513 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 153:86] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[lsu_stbuf.scala 153:70] + node _T_515 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 153:109] + node _T_516 = or(_T_514, _T_515) @[lsu_stbuf.scala 153:90] + node _T_517 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 153:134] + node _T_518 = bits(stbuf_data[2], 31, 24) @[lsu_stbuf.scala 153:157] + node _T_519 = mux(_T_516, _T_517, _T_518) @[lsu_stbuf.scala 153:69] + node _T_520 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 154:27] + node _T_521 = eq(_T_520, UInt<1>("h00")) @[lsu_stbuf.scala 154:11] + node _T_522 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 154:50] + node _T_523 = or(_T_521, _T_522) @[lsu_stbuf.scala 154:31] + node _T_524 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 154:75] + node _T_525 = bits(stbuf_data[2], 31, 24) @[lsu_stbuf.scala 154:98] + node _T_526 = mux(_T_523, _T_524, _T_525) @[lsu_stbuf.scala 154:10] + node _T_527 = mux(_T_512, _T_519, _T_526) @[lsu_stbuf.scala 153:54] + node _T_528 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 153:61] + node _T_529 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 153:86] + node _T_530 = eq(_T_529, UInt<1>("h00")) @[lsu_stbuf.scala 153:70] + node _T_531 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 153:109] + node _T_532 = or(_T_530, _T_531) @[lsu_stbuf.scala 153:90] + node _T_533 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 153:134] + node _T_534 = bits(stbuf_data[3], 31, 24) @[lsu_stbuf.scala 153:157] + node _T_535 = mux(_T_532, _T_533, _T_534) @[lsu_stbuf.scala 153:69] + node _T_536 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 154:27] + node _T_537 = eq(_T_536, UInt<1>("h00")) @[lsu_stbuf.scala 154:11] + node _T_538 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 154:50] + node _T_539 = or(_T_537, _T_538) @[lsu_stbuf.scala 154:31] + node _T_540 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 154:75] + node _T_541 = bits(stbuf_data[3], 31, 24) @[lsu_stbuf.scala 154:98] + node _T_542 = mux(_T_539, _T_540, _T_541) @[lsu_stbuf.scala 154:10] + node _T_543 = mux(_T_528, _T_535, _T_542) @[lsu_stbuf.scala 153:54] + datain4[0] <= _T_495 @[lsu_stbuf.scala 153:13] + datain4[1] <= _T_511 @[lsu_stbuf.scala 153:13] + datain4[2] <= _T_527 @[lsu_stbuf.scala 153:13] + datain4[3] <= _T_543 @[lsu_stbuf.scala 153:13] + node _T_544 = cat(datain2[0], datain1[0]) @[Cat.scala 29:58] + node _T_545 = cat(datain4[0], datain3[0]) @[Cat.scala 29:58] + node _T_546 = cat(_T_545, _T_544) @[Cat.scala 29:58] + node _T_547 = cat(datain2[1], datain1[1]) @[Cat.scala 29:58] + node _T_548 = cat(datain4[1], datain3[1]) @[Cat.scala 29:58] + node _T_549 = cat(_T_548, _T_547) @[Cat.scala 29:58] + node _T_550 = cat(datain2[2], datain1[2]) @[Cat.scala 29:58] + node _T_551 = cat(datain4[2], datain3[2]) @[Cat.scala 29:58] + node _T_552 = cat(_T_551, _T_550) @[Cat.scala 29:58] + node _T_553 = cat(datain2[3], datain1[3]) @[Cat.scala 29:58] + node _T_554 = cat(datain4[3], datain3[3]) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_553) @[Cat.scala 29:58] + stbuf_datain[0] <= _T_546 @[lsu_stbuf.scala 156:18] + stbuf_datain[1] <= _T_549 @[lsu_stbuf.scala 156:18] + stbuf_datain[2] <= _T_552 @[lsu_stbuf.scala 156:18] + stbuf_datain[3] <= _T_555 @[lsu_stbuf.scala 156:18] + node _T_556 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 160:30] + node _T_557 = bits(_T_556, 0, 0) @[lsu_stbuf.scala 160:40] + node _T_558 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 160:58] + node _T_559 = mux(_T_557, UInt<1>("h01"), _T_558) @[lsu_stbuf.scala 160:18] + node _T_560 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 160:77] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[lsu_stbuf.scala 160:65] + node _T_562 = and(_T_559, _T_561) @[lsu_stbuf.scala 160:63] + reg _T_563 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 160:14] + _T_563 <= _T_562 @[lsu_stbuf.scala 160:14] + node _T_564 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 160:30] + node _T_565 = bits(_T_564, 0, 0) @[lsu_stbuf.scala 160:40] + node _T_566 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 160:58] + node _T_567 = mux(_T_565, UInt<1>("h01"), _T_566) @[lsu_stbuf.scala 160:18] + node _T_568 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 160:77] + node _T_569 = eq(_T_568, UInt<1>("h00")) @[lsu_stbuf.scala 160:65] + node _T_570 = and(_T_567, _T_569) @[lsu_stbuf.scala 160:63] + reg _T_571 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 160:14] + _T_571 <= _T_570 @[lsu_stbuf.scala 160:14] + node _T_572 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 160:30] + node _T_573 = bits(_T_572, 0, 0) @[lsu_stbuf.scala 160:40] + node _T_574 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 160:58] + node _T_575 = mux(_T_573, UInt<1>("h01"), _T_574) @[lsu_stbuf.scala 160:18] + node _T_576 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 160:77] + node _T_577 = eq(_T_576, UInt<1>("h00")) @[lsu_stbuf.scala 160:65] + node _T_578 = and(_T_575, _T_577) @[lsu_stbuf.scala 160:63] + reg _T_579 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 160:14] + _T_579 <= _T_578 @[lsu_stbuf.scala 160:14] + node _T_580 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 160:30] + node _T_581 = bits(_T_580, 0, 0) @[lsu_stbuf.scala 160:40] + node _T_582 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 160:58] + node _T_583 = mux(_T_581, UInt<1>("h01"), _T_582) @[lsu_stbuf.scala 160:18] + node _T_584 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 160:77] + node _T_585 = eq(_T_584, UInt<1>("h00")) @[lsu_stbuf.scala 160:65] + node _T_586 = and(_T_583, _T_585) @[lsu_stbuf.scala 160:63] + reg _T_587 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 160:14] + _T_587 <= _T_586 @[lsu_stbuf.scala 160:14] + node _T_588 = cat(_T_587, _T_579) @[Cat.scala 29:58] + node _T_589 = cat(_T_588, _T_571) @[Cat.scala 29:58] + node _T_590 = cat(_T_589, _T_563) @[Cat.scala 29:58] + stbuf_vld <= _T_590 @[lsu_stbuf.scala 159:15] + node _T_591 = bits(stbuf_dma_kill_en, 0, 0) @[lsu_stbuf.scala 163:36] + node _T_592 = bits(_T_591, 0, 0) @[lsu_stbuf.scala 163:40] + node _T_593 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 163:67] + node _T_594 = mux(_T_592, UInt<1>("h01"), _T_593) @[lsu_stbuf.scala 163:18] + node _T_595 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 163:86] + node _T_596 = eq(_T_595, UInt<1>("h00")) @[lsu_stbuf.scala 163:74] + node _T_597 = and(_T_594, _T_596) @[lsu_stbuf.scala 163:72] + reg _T_598 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:14] + _T_598 <= _T_597 @[lsu_stbuf.scala 163:14] + node _T_599 = bits(stbuf_dma_kill_en, 1, 1) @[lsu_stbuf.scala 163:36] + node _T_600 = bits(_T_599, 0, 0) @[lsu_stbuf.scala 163:40] + node _T_601 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 163:67] + node _T_602 = mux(_T_600, UInt<1>("h01"), _T_601) @[lsu_stbuf.scala 163:18] + node _T_603 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 163:86] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[lsu_stbuf.scala 163:74] + node _T_605 = and(_T_602, _T_604) @[lsu_stbuf.scala 163:72] + reg _T_606 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:14] + _T_606 <= _T_605 @[lsu_stbuf.scala 163:14] + node _T_607 = bits(stbuf_dma_kill_en, 2, 2) @[lsu_stbuf.scala 163:36] + node _T_608 = bits(_T_607, 0, 0) @[lsu_stbuf.scala 163:40] + node _T_609 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 163:67] + node _T_610 = mux(_T_608, UInt<1>("h01"), _T_609) @[lsu_stbuf.scala 163:18] + node _T_611 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 163:86] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[lsu_stbuf.scala 163:74] + node _T_613 = and(_T_610, _T_612) @[lsu_stbuf.scala 163:72] + reg _T_614 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:14] + _T_614 <= _T_613 @[lsu_stbuf.scala 163:14] + node _T_615 = bits(stbuf_dma_kill_en, 3, 3) @[lsu_stbuf.scala 163:36] + node _T_616 = bits(_T_615, 0, 0) @[lsu_stbuf.scala 163:40] + node _T_617 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 163:67] + node _T_618 = mux(_T_616, UInt<1>("h01"), _T_617) @[lsu_stbuf.scala 163:18] + node _T_619 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 163:86] + node _T_620 = eq(_T_619, UInt<1>("h00")) @[lsu_stbuf.scala 163:74] + node _T_621 = and(_T_618, _T_620) @[lsu_stbuf.scala 163:72] + reg _T_622 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:14] + _T_622 <= _T_621 @[lsu_stbuf.scala 163:14] + node _T_623 = cat(_T_622, _T_614) @[Cat.scala 29:58] + node _T_624 = cat(_T_623, _T_606) @[Cat.scala 29:58] + node _T_625 = cat(_T_624, _T_598) @[Cat.scala 29:58] + stbuf_dma_kill <= _T_625 @[lsu_stbuf.scala 162:20] + node _T_626 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 166:30] + node _T_627 = bits(_T_626, 0, 0) @[lsu_stbuf.scala 166:40] + node _T_628 = mux(_T_627, stbuf_byteenin[0], stbuf_byteen[0]) @[lsu_stbuf.scala 166:18] + node _T_629 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 166:127] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[lsu_stbuf.scala 166:115] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_633 = and(_T_628, _T_632) @[lsu_stbuf.scala 166:80] + reg _T_634 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 166:14] + _T_634 <= _T_633 @[lsu_stbuf.scala 166:14] + node _T_635 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 166:30] + node _T_636 = bits(_T_635, 0, 0) @[lsu_stbuf.scala 166:40] + node _T_637 = mux(_T_636, stbuf_byteenin[1], stbuf_byteen[1]) @[lsu_stbuf.scala 166:18] + node _T_638 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 166:127] + node _T_639 = eq(_T_638, UInt<1>("h00")) @[lsu_stbuf.scala 166:115] + node _T_640 = bits(_T_639, 0, 0) @[Bitwise.scala 72:15] + node _T_641 = mux(_T_640, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_642 = and(_T_637, _T_641) @[lsu_stbuf.scala 166:80] + reg _T_643 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 166:14] + _T_643 <= _T_642 @[lsu_stbuf.scala 166:14] + node _T_644 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 166:30] + node _T_645 = bits(_T_644, 0, 0) @[lsu_stbuf.scala 166:40] + node _T_646 = mux(_T_645, stbuf_byteenin[2], stbuf_byteen[2]) @[lsu_stbuf.scala 166:18] + node _T_647 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 166:127] + node _T_648 = eq(_T_647, UInt<1>("h00")) @[lsu_stbuf.scala 166:115] + node _T_649 = bits(_T_648, 0, 0) @[Bitwise.scala 72:15] + node _T_650 = mux(_T_649, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_651 = and(_T_646, _T_650) @[lsu_stbuf.scala 166:80] + reg _T_652 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 166:14] + _T_652 <= _T_651 @[lsu_stbuf.scala 166:14] + node _T_653 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 166:30] + node _T_654 = bits(_T_653, 0, 0) @[lsu_stbuf.scala 166:40] + node _T_655 = mux(_T_654, stbuf_byteenin[3], stbuf_byteen[3]) @[lsu_stbuf.scala 166:18] + node _T_656 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 166:127] + node _T_657 = eq(_T_656, UInt<1>("h00")) @[lsu_stbuf.scala 166:115] + node _T_658 = bits(_T_657, 0, 0) @[Bitwise.scala 72:15] + node _T_659 = mux(_T_658, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_660 = and(_T_655, _T_659) @[lsu_stbuf.scala 166:80] + reg _T_661 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 166:14] + _T_661 <= _T_660 @[lsu_stbuf.scala 166:14] + stbuf_byteen[0] <= _T_634 @[lsu_stbuf.scala 165:18] + stbuf_byteen[1] <= _T_643 @[lsu_stbuf.scala 165:18] + stbuf_byteen[2] <= _T_652 @[lsu_stbuf.scala 165:18] + stbuf_byteen[3] <= _T_661 @[lsu_stbuf.scala 165:18] + node _T_662 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 169:59] + node _T_663 = bits(_T_662, 0, 0) @[lsu_stbuf.scala 169:69] + inst rvclkhdr of rvclkhdr_8 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_663 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_664 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_663 : @[Reg.scala 28:19] + _T_664 <= stbuf_addrin[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_addr[0] <= _T_664 @[lsu_stbuf.scala 169:21] + node _T_665 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 170:59] + node _T_666 = bits(_T_665, 0, 0) @[lsu_stbuf.scala 170:69] + inst rvclkhdr_1 of rvclkhdr_9 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_666 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_667 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_666 : @[Reg.scala 28:19] + _T_667 <= stbuf_datain[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_data[0] <= _T_667 @[lsu_stbuf.scala 170:21] + node _T_668 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 169:59] + node _T_669 = bits(_T_668, 0, 0) @[lsu_stbuf.scala 169:69] + inst rvclkhdr_2 of rvclkhdr_10 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_669 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_670 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_669 : @[Reg.scala 28:19] + _T_670 <= stbuf_addrin[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_addr[1] <= _T_670 @[lsu_stbuf.scala 169:21] + node _T_671 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 170:59] + node _T_672 = bits(_T_671, 0, 0) @[lsu_stbuf.scala 170:69] + inst rvclkhdr_3 of rvclkhdr_11 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_672 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_673 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_672 : @[Reg.scala 28:19] + _T_673 <= stbuf_datain[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_data[1] <= _T_673 @[lsu_stbuf.scala 170:21] + node _T_674 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 169:59] + node _T_675 = bits(_T_674, 0, 0) @[lsu_stbuf.scala 169:69] + inst rvclkhdr_4 of rvclkhdr_12 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_675 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_676 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_675 : @[Reg.scala 28:19] + _T_676 <= stbuf_addrin[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_addr[2] <= _T_676 @[lsu_stbuf.scala 169:21] + node _T_677 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 170:59] + node _T_678 = bits(_T_677, 0, 0) @[lsu_stbuf.scala 170:69] + inst rvclkhdr_5 of rvclkhdr_13 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_678 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_679 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_678 : @[Reg.scala 28:19] + _T_679 <= stbuf_datain[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_data[2] <= _T_679 @[lsu_stbuf.scala 170:21] + node _T_680 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 169:59] + node _T_681 = bits(_T_680, 0, 0) @[lsu_stbuf.scala 169:69] + inst rvclkhdr_6 of rvclkhdr_14 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_681 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_682 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_681 : @[Reg.scala 28:19] + _T_682 <= stbuf_addrin[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_addr[3] <= _T_682 @[lsu_stbuf.scala 169:21] + node _T_683 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 170:59] + node _T_684 = bits(_T_683, 0, 0) @[lsu_stbuf.scala 170:69] + inst rvclkhdr_7 of rvclkhdr_15 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_684 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_685 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_684 : @[Reg.scala 28:19] + _T_685 <= stbuf_datain[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + stbuf_data[3] <= _T_685 @[lsu_stbuf.scala 170:21] + node _T_686 = dshr(stbuf_vld, RdPtr) @[lsu_stbuf.scala 183:43] + node _T_687 = bits(_T_686, 0, 0) @[lsu_stbuf.scala 183:43] + node _T_688 = dshr(stbuf_dma_kill, RdPtr) @[lsu_stbuf.scala 183:67] + node _T_689 = bits(_T_688, 0, 0) @[lsu_stbuf.scala 183:67] + node _T_690 = and(_T_687, _T_689) @[lsu_stbuf.scala 183:51] + io.stbuf_reqvld_flushed_any <= _T_690 @[lsu_stbuf.scala 183:31] + node _T_691 = dshr(stbuf_vld, RdPtr) @[lsu_stbuf.scala 184:36] + node _T_692 = bits(_T_691, 0, 0) @[lsu_stbuf.scala 184:36] + node _T_693 = dshr(stbuf_dma_kill, RdPtr) @[lsu_stbuf.scala 184:61] + node _T_694 = bits(_T_693, 0, 0) @[lsu_stbuf.scala 184:61] + node _T_695 = eq(_T_694, UInt<1>("h00")) @[lsu_stbuf.scala 184:46] + node _T_696 = and(_T_692, _T_695) @[lsu_stbuf.scala 184:44] + node _T_697 = orr(stbuf_dma_kill_en) @[lsu_stbuf.scala 184:91] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[lsu_stbuf.scala 184:71] + node _T_699 = and(_T_696, _T_698) @[lsu_stbuf.scala 184:69] + io.stbuf_reqvld_any <= _T_699 @[lsu_stbuf.scala 184:24] + io.stbuf_addr_any <= stbuf_addr[RdPtr] @[lsu_stbuf.scala 185:22] + io.stbuf_data_any <= stbuf_data[RdPtr] @[lsu_stbuf.scala 186:22] + node _T_700 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[lsu_stbuf.scala 188:44] + node _T_701 = and(io.ldst_stbuf_reqvld_r, _T_700) @[lsu_stbuf.scala 188:42] + node _T_702 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[lsu_stbuf.scala 188:88] + node _T_703 = eq(_T_702, UInt<1>("h00")) @[lsu_stbuf.scala 188:66] + node _T_704 = and(_T_701, _T_703) @[lsu_stbuf.scala 188:64] + node _T_705 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[lsu_stbuf.scala 189:30] + node _T_706 = and(store_coalesce_hi_r, store_coalesce_lo_r) @[lsu_stbuf.scala 189:76] + node _T_707 = eq(_T_706, UInt<1>("h00")) @[lsu_stbuf.scala 189:54] + node _T_708 = and(_T_705, _T_707) @[lsu_stbuf.scala 189:52] + node _T_709 = or(_T_704, _T_708) @[lsu_stbuf.scala 188:113] + node WrPtrEn = bits(_T_709, 0, 0) @[lsu_stbuf.scala 189:101] + node _T_710 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[lsu_stbuf.scala 190:46] + node _T_711 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[lsu_stbuf.scala 190:91] + node _T_712 = eq(_T_711, UInt<1>("h00")) @[lsu_stbuf.scala 190:69] + node _T_713 = and(_T_710, _T_712) @[lsu_stbuf.scala 190:67] + node _T_714 = bits(_T_713, 0, 0) @[lsu_stbuf.scala 190:115] + node NxtWrPtr = mux(_T_714, WrPtrPlus2, WrPtrPlus1) @[lsu_stbuf.scala 190:21] + node RdPtrEn = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 191:42] + reg _T_715 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when WrPtrEn : @[Reg.scala 28:19] + _T_715 <= NxtWrPtr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + WrPtr <= _T_715 @[lsu_stbuf.scala 194:41] + reg _T_716 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when RdPtrEn : @[Reg.scala 28:19] + _T_716 <= RdPtrPlus1 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + RdPtr <= _T_716 @[lsu_stbuf.scala 195:41] + node _T_717 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 197:86] + node _T_718 = cat(UInt<3>("h00"), _T_717) @[Cat.scala 29:58] + node _T_719 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 197:86] + node _T_720 = cat(UInt<3>("h00"), _T_719) @[Cat.scala 29:58] + node _T_721 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 197:86] + node _T_722 = cat(UInt<3>("h00"), _T_721) @[Cat.scala 29:58] + node _T_723 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 197:86] + node _T_724 = cat(UInt<3>("h00"), _T_723) @[Cat.scala 29:58] + wire _T_725 : UInt<4>[4] @[lsu_stbuf.scala 197:59] + _T_725[0] <= _T_718 @[lsu_stbuf.scala 197:59] + _T_725[1] <= _T_720 @[lsu_stbuf.scala 197:59] + _T_725[2] <= _T_722 @[lsu_stbuf.scala 197:59] + _T_725[3] <= _T_724 @[lsu_stbuf.scala 197:59] + node _T_726 = add(_T_725[0], _T_725[1]) @[lsu_stbuf.scala 197:101] + node _T_727 = tail(_T_726, 1) @[lsu_stbuf.scala 197:101] + node _T_728 = add(_T_727, _T_725[2]) @[lsu_stbuf.scala 197:101] + node _T_729 = tail(_T_728, 1) @[lsu_stbuf.scala 197:101] + node _T_730 = add(_T_729, _T_725[3]) @[lsu_stbuf.scala 197:101] + node stbuf_numvld_any = tail(_T_730, 1) @[lsu_stbuf.scala 197:101] + node _T_731 = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 198:39] + node _T_732 = and(_T_731, io.addr_in_dccm_m) @[lsu_stbuf.scala 198:65] + node _T_733 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 198:87] + node isdccmst_m = and(_T_732, _T_733) @[lsu_stbuf.scala 198:85] + node _T_734 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 199:39] + node _T_735 = and(_T_734, io.addr_in_dccm_r) @[lsu_stbuf.scala 199:65] + node _T_736 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 199:87] + node isdccmst_r = and(_T_735, _T_736) @[lsu_stbuf.scala 199:85] + node _T_737 = cat(UInt<1>("h00"), isdccmst_m) @[Cat.scala 29:58] + node _T_738 = and(isdccmst_m, io.ldst_dual_m) @[lsu_stbuf.scala 201:62] + node _T_739 = dshl(_T_737, _T_738) @[lsu_stbuf.scala 201:47] + stbuf_specvld_m <= _T_739 @[lsu_stbuf.scala 201:19] + node _T_740 = cat(UInt<1>("h00"), isdccmst_r) @[Cat.scala 29:58] + node _T_741 = and(isdccmst_r, io.ldst_dual_r) @[lsu_stbuf.scala 202:62] + node _T_742 = dshl(_T_740, _T_741) @[lsu_stbuf.scala 202:47] + stbuf_specvld_r <= _T_742 @[lsu_stbuf.scala 202:19] + node _T_743 = cat(UInt<2>("h00"), stbuf_specvld_m) @[Cat.scala 29:58] + node _T_744 = add(stbuf_numvld_any, _T_743) @[lsu_stbuf.scala 203:44] + node _T_745 = tail(_T_744, 1) @[lsu_stbuf.scala 203:44] + node _T_746 = cat(UInt<2>("h00"), stbuf_specvld_r) @[Cat.scala 29:58] + node _T_747 = add(_T_745, _T_746) @[lsu_stbuf.scala 203:78] + node stbuf_specvld_any = tail(_T_747, 1) @[lsu_stbuf.scala 203:78] + node _T_748 = eq(io.ldst_dual_d, UInt<1>("h00")) @[lsu_stbuf.scala 205:34] + node _T_749 = and(_T_748, io.dec_lsu_valid_raw_d) @[lsu_stbuf.scala 205:50] + node _T_750 = bits(_T_749, 0, 0) @[lsu_stbuf.scala 205:76] + node _T_751 = geq(stbuf_specvld_any, UInt<3>("h04")) @[lsu_stbuf.scala 205:102] + node _T_752 = geq(stbuf_specvld_any, UInt<2>("h03")) @[lsu_stbuf.scala 205:143] + node _T_753 = mux(_T_750, _T_751, _T_752) @[lsu_stbuf.scala 205:32] + io.lsu_stbuf_full_any <= _T_753 @[lsu_stbuf.scala 205:26] + node _T_754 = eq(stbuf_numvld_any, UInt<1>("h00")) @[lsu_stbuf.scala 206:46] + io.lsu_stbuf_empty_any <= _T_754 @[lsu_stbuf.scala 206:26] + node _T_755 = bits(io.end_addr_m, 15, 2) @[lsu_stbuf.scala 208:32] + cmpaddr_hi_m <= _T_755 @[lsu_stbuf.scala 208:16] + node _T_756 = bits(io.lsu_addr_m, 15, 2) @[lsu_stbuf.scala 209:33] + cmpaddr_lo_m <= _T_756 @[lsu_stbuf.scala 209:17] + node _T_757 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 212:73] + node _T_758 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 212:131] + node _T_759 = eq(_T_757, _T_758) @[lsu_stbuf.scala 212:115] + node _T_760 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 212:150] + node _T_761 = and(_T_759, _T_760) @[lsu_stbuf.scala 212:139] + node _T_762 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 212:171] + node _T_763 = eq(_T_762, UInt<1>("h00")) @[lsu_stbuf.scala 212:156] + node _T_764 = and(_T_761, _T_763) @[lsu_stbuf.scala 212:154] + node _T_765 = and(_T_764, io.addr_in_dccm_m) @[lsu_stbuf.scala 212:175] + node _T_766 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 212:73] + node _T_767 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 212:131] + node _T_768 = eq(_T_766, _T_767) @[lsu_stbuf.scala 212:115] + node _T_769 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 212:150] + node _T_770 = and(_T_768, _T_769) @[lsu_stbuf.scala 212:139] + node _T_771 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 212:171] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[lsu_stbuf.scala 212:156] + node _T_773 = and(_T_770, _T_772) @[lsu_stbuf.scala 212:154] + node _T_774 = and(_T_773, io.addr_in_dccm_m) @[lsu_stbuf.scala 212:175] + node _T_775 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 212:73] + node _T_776 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 212:131] + node _T_777 = eq(_T_775, _T_776) @[lsu_stbuf.scala 212:115] + node _T_778 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 212:150] + node _T_779 = and(_T_777, _T_778) @[lsu_stbuf.scala 212:139] + node _T_780 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 212:171] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[lsu_stbuf.scala 212:156] + node _T_782 = and(_T_779, _T_781) @[lsu_stbuf.scala 212:154] + node _T_783 = and(_T_782, io.addr_in_dccm_m) @[lsu_stbuf.scala 212:175] + node _T_784 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 212:73] + node _T_785 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 212:131] + node _T_786 = eq(_T_784, _T_785) @[lsu_stbuf.scala 212:115] + node _T_787 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 212:150] + node _T_788 = and(_T_786, _T_787) @[lsu_stbuf.scala 212:139] + node _T_789 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 212:171] + node _T_790 = eq(_T_789, UInt<1>("h00")) @[lsu_stbuf.scala 212:156] + node _T_791 = and(_T_788, _T_790) @[lsu_stbuf.scala 212:154] + node _T_792 = and(_T_791, io.addr_in_dccm_m) @[lsu_stbuf.scala 212:175] + node _T_793 = cat(_T_792, _T_783) @[Cat.scala 29:58] + node _T_794 = cat(_T_793, _T_774) @[Cat.scala 29:58] + node stbuf_match_hi = cat(_T_794, _T_765) @[Cat.scala 29:58] + node _T_795 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 213:73] + node _T_796 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 213:131] + node _T_797 = eq(_T_795, _T_796) @[lsu_stbuf.scala 213:115] + node _T_798 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 213:150] + node _T_799 = and(_T_797, _T_798) @[lsu_stbuf.scala 213:139] + node _T_800 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 213:171] + node _T_801 = eq(_T_800, UInt<1>("h00")) @[lsu_stbuf.scala 213:156] + node _T_802 = and(_T_799, _T_801) @[lsu_stbuf.scala 213:154] + node _T_803 = and(_T_802, io.addr_in_dccm_m) @[lsu_stbuf.scala 213:175] + node _T_804 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 213:73] + node _T_805 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 213:131] + node _T_806 = eq(_T_804, _T_805) @[lsu_stbuf.scala 213:115] + node _T_807 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 213:150] + node _T_808 = and(_T_806, _T_807) @[lsu_stbuf.scala 213:139] + node _T_809 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 213:171] + node _T_810 = eq(_T_809, UInt<1>("h00")) @[lsu_stbuf.scala 213:156] + node _T_811 = and(_T_808, _T_810) @[lsu_stbuf.scala 213:154] + node _T_812 = and(_T_811, io.addr_in_dccm_m) @[lsu_stbuf.scala 213:175] + node _T_813 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 213:73] + node _T_814 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 213:131] + node _T_815 = eq(_T_813, _T_814) @[lsu_stbuf.scala 213:115] + node _T_816 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 213:150] + node _T_817 = and(_T_815, _T_816) @[lsu_stbuf.scala 213:139] + node _T_818 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 213:171] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[lsu_stbuf.scala 213:156] + node _T_820 = and(_T_817, _T_819) @[lsu_stbuf.scala 213:154] + node _T_821 = and(_T_820, io.addr_in_dccm_m) @[lsu_stbuf.scala 213:175] + node _T_822 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 213:73] + node _T_823 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 213:131] + node _T_824 = eq(_T_822, _T_823) @[lsu_stbuf.scala 213:115] + node _T_825 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 213:150] + node _T_826 = and(_T_824, _T_825) @[lsu_stbuf.scala 213:139] + node _T_827 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 213:171] + node _T_828 = eq(_T_827, UInt<1>("h00")) @[lsu_stbuf.scala 213:156] + node _T_829 = and(_T_826, _T_828) @[lsu_stbuf.scala 213:154] + node _T_830 = and(_T_829, io.addr_in_dccm_m) @[lsu_stbuf.scala 213:175] + node _T_831 = cat(_T_830, _T_821) @[Cat.scala 29:58] + node _T_832 = cat(_T_831, _T_812) @[Cat.scala 29:58] + node stbuf_match_lo = cat(_T_832, _T_803) @[Cat.scala 29:58] + node _T_833 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 214:74] + node _T_834 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 214:94] + node _T_835 = or(_T_833, _T_834) @[lsu_stbuf.scala 214:78] + node _T_836 = and(_T_835, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 214:99] + node _T_837 = and(_T_836, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 214:120] + node _T_838 = and(_T_837, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 214:144] + node _T_839 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 214:74] + node _T_840 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 214:94] + node _T_841 = or(_T_839, _T_840) @[lsu_stbuf.scala 214:78] + node _T_842 = and(_T_841, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 214:99] + node _T_843 = and(_T_842, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 214:120] + node _T_844 = and(_T_843, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 214:144] + node _T_845 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 214:74] + node _T_846 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 214:94] + node _T_847 = or(_T_845, _T_846) @[lsu_stbuf.scala 214:78] + node _T_848 = and(_T_847, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 214:99] + node _T_849 = and(_T_848, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 214:120] + node _T_850 = and(_T_849, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 214:144] + node _T_851 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 214:74] + node _T_852 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 214:94] + node _T_853 = or(_T_851, _T_852) @[lsu_stbuf.scala 214:78] + node _T_854 = and(_T_853, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 214:99] + node _T_855 = and(_T_854, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 214:120] + node _T_856 = and(_T_855, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 214:144] + node _T_857 = cat(_T_856, _T_850) @[Cat.scala 29:58] + node _T_858 = cat(_T_857, _T_844) @[Cat.scala 29:58] + node _T_859 = cat(_T_858, _T_838) @[Cat.scala 29:58] + stbuf_dma_kill_en <= _T_859 @[lsu_stbuf.scala 214:21] + node _T_860 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 217:112] + node _T_861 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 217:133] + node _T_862 = and(_T_860, _T_861) @[lsu_stbuf.scala 217:116] + node _T_863 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_0 = and(_T_862, _T_863) @[lsu_stbuf.scala 217:137] + node _T_864 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 217:112] + node _T_865 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 217:133] + node _T_866 = and(_T_864, _T_865) @[lsu_stbuf.scala 217:116] + node _T_867 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_1 = and(_T_866, _T_867) @[lsu_stbuf.scala 217:137] + node _T_868 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 217:112] + node _T_869 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 217:133] + node _T_870 = and(_T_868, _T_869) @[lsu_stbuf.scala 217:116] + node _T_871 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_2 = and(_T_870, _T_871) @[lsu_stbuf.scala 217:137] + node _T_872 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 217:112] + node _T_873 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 217:133] + node _T_874 = and(_T_872, _T_873) @[lsu_stbuf.scala 217:116] + node _T_875 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_3 = and(_T_874, _T_875) @[lsu_stbuf.scala 217:137] + node _T_876 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 217:112] + node _T_877 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 217:133] + node _T_878 = and(_T_876, _T_877) @[lsu_stbuf.scala 217:116] + node _T_879 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_0 = and(_T_878, _T_879) @[lsu_stbuf.scala 217:137] + node _T_880 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 217:112] + node _T_881 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 217:133] + node _T_882 = and(_T_880, _T_881) @[lsu_stbuf.scala 217:116] + node _T_883 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_1 = and(_T_882, _T_883) @[lsu_stbuf.scala 217:137] + node _T_884 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 217:112] + node _T_885 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 217:133] + node _T_886 = and(_T_884, _T_885) @[lsu_stbuf.scala 217:116] + node _T_887 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_2 = and(_T_886, _T_887) @[lsu_stbuf.scala 217:137] + node _T_888 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 217:112] + node _T_889 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 217:133] + node _T_890 = and(_T_888, _T_889) @[lsu_stbuf.scala 217:116] + node _T_891 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_3 = and(_T_890, _T_891) @[lsu_stbuf.scala 217:137] + node _T_892 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 217:112] + node _T_893 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 217:133] + node _T_894 = and(_T_892, _T_893) @[lsu_stbuf.scala 217:116] + node _T_895 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_0 = and(_T_894, _T_895) @[lsu_stbuf.scala 217:137] + node _T_896 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 217:112] + node _T_897 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 217:133] + node _T_898 = and(_T_896, _T_897) @[lsu_stbuf.scala 217:116] + node _T_899 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_1 = and(_T_898, _T_899) @[lsu_stbuf.scala 217:137] + node _T_900 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 217:112] + node _T_901 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 217:133] + node _T_902 = and(_T_900, _T_901) @[lsu_stbuf.scala 217:116] + node _T_903 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_2 = and(_T_902, _T_903) @[lsu_stbuf.scala 217:137] + node _T_904 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 217:112] + node _T_905 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 217:133] + node _T_906 = and(_T_904, _T_905) @[lsu_stbuf.scala 217:116] + node _T_907 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_3 = and(_T_906, _T_907) @[lsu_stbuf.scala 217:137] + node _T_908 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 217:112] + node _T_909 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 217:133] + node _T_910 = and(_T_908, _T_909) @[lsu_stbuf.scala 217:116] + node _T_911 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_0 = and(_T_910, _T_911) @[lsu_stbuf.scala 217:137] + node _T_912 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 217:112] + node _T_913 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 217:133] + node _T_914 = and(_T_912, _T_913) @[lsu_stbuf.scala 217:116] + node _T_915 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_1 = and(_T_914, _T_915) @[lsu_stbuf.scala 217:137] + node _T_916 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 217:112] + node _T_917 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 217:133] + node _T_918 = and(_T_916, _T_917) @[lsu_stbuf.scala 217:116] + node _T_919 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_2 = and(_T_918, _T_919) @[lsu_stbuf.scala 217:137] + node _T_920 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 217:112] + node _T_921 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 217:133] + node _T_922 = and(_T_920, _T_921) @[lsu_stbuf.scala 217:116] + node _T_923 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_3 = and(_T_922, _T_923) @[lsu_stbuf.scala 217:137] + node _T_924 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 218:112] + node _T_925 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 218:133] + node _T_926 = and(_T_924, _T_925) @[lsu_stbuf.scala 218:116] + node _T_927 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_0 = and(_T_926, _T_927) @[lsu_stbuf.scala 218:137] + node _T_928 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 218:112] + node _T_929 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 218:133] + node _T_930 = and(_T_928, _T_929) @[lsu_stbuf.scala 218:116] + node _T_931 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_1 = and(_T_930, _T_931) @[lsu_stbuf.scala 218:137] + node _T_932 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 218:112] + node _T_933 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 218:133] + node _T_934 = and(_T_932, _T_933) @[lsu_stbuf.scala 218:116] + node _T_935 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_2 = and(_T_934, _T_935) @[lsu_stbuf.scala 218:137] + node _T_936 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 218:112] + node _T_937 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 218:133] + node _T_938 = and(_T_936, _T_937) @[lsu_stbuf.scala 218:116] + node _T_939 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_3 = and(_T_938, _T_939) @[lsu_stbuf.scala 218:137] + node _T_940 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 218:112] + node _T_941 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 218:133] + node _T_942 = and(_T_940, _T_941) @[lsu_stbuf.scala 218:116] + node _T_943 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_0 = and(_T_942, _T_943) @[lsu_stbuf.scala 218:137] + node _T_944 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 218:112] + node _T_945 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 218:133] + node _T_946 = and(_T_944, _T_945) @[lsu_stbuf.scala 218:116] + node _T_947 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_1 = and(_T_946, _T_947) @[lsu_stbuf.scala 218:137] + node _T_948 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 218:112] + node _T_949 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 218:133] + node _T_950 = and(_T_948, _T_949) @[lsu_stbuf.scala 218:116] + node _T_951 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_2 = and(_T_950, _T_951) @[lsu_stbuf.scala 218:137] + node _T_952 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 218:112] + node _T_953 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 218:133] + node _T_954 = and(_T_952, _T_953) @[lsu_stbuf.scala 218:116] + node _T_955 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_3 = and(_T_954, _T_955) @[lsu_stbuf.scala 218:137] + node _T_956 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 218:112] + node _T_957 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 218:133] + node _T_958 = and(_T_956, _T_957) @[lsu_stbuf.scala 218:116] + node _T_959 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_0 = and(_T_958, _T_959) @[lsu_stbuf.scala 218:137] + node _T_960 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 218:112] + node _T_961 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 218:133] + node _T_962 = and(_T_960, _T_961) @[lsu_stbuf.scala 218:116] + node _T_963 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_1 = and(_T_962, _T_963) @[lsu_stbuf.scala 218:137] + node _T_964 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 218:112] + node _T_965 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 218:133] + node _T_966 = and(_T_964, _T_965) @[lsu_stbuf.scala 218:116] + node _T_967 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_2 = and(_T_966, _T_967) @[lsu_stbuf.scala 218:137] + node _T_968 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 218:112] + node _T_969 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 218:133] + node _T_970 = and(_T_968, _T_969) @[lsu_stbuf.scala 218:116] + node _T_971 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_3 = and(_T_970, _T_971) @[lsu_stbuf.scala 218:137] + node _T_972 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 218:112] + node _T_973 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 218:133] + node _T_974 = and(_T_972, _T_973) @[lsu_stbuf.scala 218:116] + node _T_975 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_0 = and(_T_974, _T_975) @[lsu_stbuf.scala 218:137] + node _T_976 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 218:112] + node _T_977 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 218:133] + node _T_978 = and(_T_976, _T_977) @[lsu_stbuf.scala 218:116] + node _T_979 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_1 = and(_T_978, _T_979) @[lsu_stbuf.scala 218:137] + node _T_980 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 218:112] + node _T_981 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 218:133] + node _T_982 = and(_T_980, _T_981) @[lsu_stbuf.scala 218:116] + node _T_983 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_2 = and(_T_982, _T_983) @[lsu_stbuf.scala 218:137] + node _T_984 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 218:112] + node _T_985 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 218:133] + node _T_986 = and(_T_984, _T_985) @[lsu_stbuf.scala 218:116] + node _T_987 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_3 = and(_T_986, _T_987) @[lsu_stbuf.scala 218:137] + node _T_988 = or(stbuf_fwdbyteenvec_hi_0_0, stbuf_fwdbyteenvec_hi_1_0) @[lsu_stbuf.scala 219:147] + node _T_989 = or(_T_988, stbuf_fwdbyteenvec_hi_2_0) @[lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_0 = or(_T_989, stbuf_fwdbyteenvec_hi_3_0) @[lsu_stbuf.scala 219:147] + node _T_990 = or(stbuf_fwdbyteenvec_hi_0_1, stbuf_fwdbyteenvec_hi_1_1) @[lsu_stbuf.scala 219:147] + node _T_991 = or(_T_990, stbuf_fwdbyteenvec_hi_2_1) @[lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_1 = or(_T_991, stbuf_fwdbyteenvec_hi_3_1) @[lsu_stbuf.scala 219:147] + node _T_992 = or(stbuf_fwdbyteenvec_hi_0_2, stbuf_fwdbyteenvec_hi_1_2) @[lsu_stbuf.scala 219:147] + node _T_993 = or(_T_992, stbuf_fwdbyteenvec_hi_2_2) @[lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_2 = or(_T_993, stbuf_fwdbyteenvec_hi_3_2) @[lsu_stbuf.scala 219:147] + node _T_994 = or(stbuf_fwdbyteenvec_hi_0_3, stbuf_fwdbyteenvec_hi_1_3) @[lsu_stbuf.scala 219:147] + node _T_995 = or(_T_994, stbuf_fwdbyteenvec_hi_2_3) @[lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_3 = or(_T_995, stbuf_fwdbyteenvec_hi_3_3) @[lsu_stbuf.scala 219:147] + node _T_996 = or(stbuf_fwdbyteenvec_lo_0_0, stbuf_fwdbyteenvec_lo_1_0) @[lsu_stbuf.scala 220:147] + node _T_997 = or(_T_996, stbuf_fwdbyteenvec_lo_2_0) @[lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_0 = or(_T_997, stbuf_fwdbyteenvec_lo_3_0) @[lsu_stbuf.scala 220:147] + node _T_998 = or(stbuf_fwdbyteenvec_lo_0_1, stbuf_fwdbyteenvec_lo_1_1) @[lsu_stbuf.scala 220:147] + node _T_999 = or(_T_998, stbuf_fwdbyteenvec_lo_2_1) @[lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_1 = or(_T_999, stbuf_fwdbyteenvec_lo_3_1) @[lsu_stbuf.scala 220:147] + node _T_1000 = or(stbuf_fwdbyteenvec_lo_0_2, stbuf_fwdbyteenvec_lo_1_2) @[lsu_stbuf.scala 220:147] + node _T_1001 = or(_T_1000, stbuf_fwdbyteenvec_lo_2_2) @[lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_2 = or(_T_1001, stbuf_fwdbyteenvec_lo_3_2) @[lsu_stbuf.scala 220:147] + node _T_1002 = or(stbuf_fwdbyteenvec_lo_0_3, stbuf_fwdbyteenvec_lo_1_3) @[lsu_stbuf.scala 220:147] + node _T_1003 = or(_T_1002, stbuf_fwdbyteenvec_lo_2_3) @[lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_3 = or(_T_1003, stbuf_fwdbyteenvec_lo_3_3) @[lsu_stbuf.scala 220:147] + node _T_1004 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 222:92] + node _T_1005 = bits(_T_1004, 0, 0) @[Bitwise.scala 72:15] + node _T_1006 = mux(_T_1005, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1007 = and(_T_1006, stbuf_data[0]) @[lsu_stbuf.scala 222:97] + node _T_1008 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 222:92] + node _T_1009 = bits(_T_1008, 0, 0) @[Bitwise.scala 72:15] + node _T_1010 = mux(_T_1009, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1011 = and(_T_1010, stbuf_data[1]) @[lsu_stbuf.scala 222:97] + node _T_1012 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 222:92] + node _T_1013 = bits(_T_1012, 0, 0) @[Bitwise.scala 72:15] + node _T_1014 = mux(_T_1013, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1015 = and(_T_1014, stbuf_data[2]) @[lsu_stbuf.scala 222:97] + node _T_1016 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 222:92] + node _T_1017 = bits(_T_1016, 0, 0) @[Bitwise.scala 72:15] + node _T_1018 = mux(_T_1017, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1019 = and(_T_1018, stbuf_data[3]) @[lsu_stbuf.scala 222:97] + wire _T_1020 : UInt<32>[4] @[lsu_stbuf.scala 222:65] + _T_1020[0] <= _T_1007 @[lsu_stbuf.scala 222:65] + _T_1020[1] <= _T_1011 @[lsu_stbuf.scala 222:65] + _T_1020[2] <= _T_1015 @[lsu_stbuf.scala 222:65] + _T_1020[3] <= _T_1019 @[lsu_stbuf.scala 222:65] + node _T_1021 = or(_T_1020[3], _T_1020[2]) @[lsu_stbuf.scala 222:130] + node _T_1022 = or(_T_1021, _T_1020[1]) @[lsu_stbuf.scala 222:130] + node stbuf_fwddata_hi_pre_m = or(_T_1022, _T_1020[0]) @[lsu_stbuf.scala 222:130] + node _T_1023 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 223:92] + node _T_1024 = bits(_T_1023, 0, 0) @[Bitwise.scala 72:15] + node _T_1025 = mux(_T_1024, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1026 = and(_T_1025, stbuf_data[0]) @[lsu_stbuf.scala 223:97] + node _T_1027 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 223:92] + node _T_1028 = bits(_T_1027, 0, 0) @[Bitwise.scala 72:15] + node _T_1029 = mux(_T_1028, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1030 = and(_T_1029, stbuf_data[1]) @[lsu_stbuf.scala 223:97] + node _T_1031 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 223:92] + node _T_1032 = bits(_T_1031, 0, 0) @[Bitwise.scala 72:15] + node _T_1033 = mux(_T_1032, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1034 = and(_T_1033, stbuf_data[2]) @[lsu_stbuf.scala 223:97] + node _T_1035 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 223:92] + node _T_1036 = bits(_T_1035, 0, 0) @[Bitwise.scala 72:15] + node _T_1037 = mux(_T_1036, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1038 = and(_T_1037, stbuf_data[3]) @[lsu_stbuf.scala 223:97] + wire _T_1039 : UInt<32>[4] @[lsu_stbuf.scala 223:65] + _T_1039[0] <= _T_1026 @[lsu_stbuf.scala 223:65] + _T_1039[1] <= _T_1030 @[lsu_stbuf.scala 223:65] + _T_1039[2] <= _T_1034 @[lsu_stbuf.scala 223:65] + _T_1039[3] <= _T_1038 @[lsu_stbuf.scala 223:65] + node _T_1040 = or(_T_1039[3], _T_1039[2]) @[lsu_stbuf.scala 223:130] + node _T_1041 = or(_T_1040, _T_1039[1]) @[lsu_stbuf.scala 223:130] + node stbuf_fwddata_lo_pre_m = or(_T_1041, _T_1039[0]) @[lsu_stbuf.scala 223:130] + node _T_1042 = bits(io.lsu_addr_r, 1, 0) @[lsu_stbuf.scala 226:54] + node _T_1043 = dshl(ldst_byteen_r, _T_1042) @[lsu_stbuf.scala 226:38] + ldst_byteen_ext_r <= _T_1043 @[lsu_stbuf.scala 226:21] + node ldst_byteen_hi_r = bits(ldst_byteen_ext_r, 7, 4) @[lsu_stbuf.scala 227:43] + node ldst_byteen_lo_r = bits(ldst_byteen_ext_r, 3, 0) @[lsu_stbuf.scala 228:43] + node _T_1044 = bits(io.lsu_addr_m, 31, 2) @[lsu_stbuf.scala 230:42] + node _T_1045 = bits(io.lsu_addr_r, 31, 2) @[lsu_stbuf.scala 230:66] + node _T_1046 = eq(_T_1044, _T_1045) @[lsu_stbuf.scala 230:49] + node _T_1047 = and(_T_1046, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 230:74] + node _T_1048 = and(_T_1047, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 230:95] + node _T_1049 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 230:123] + node ld_addr_rhit_lo_lo = and(_T_1048, _T_1049) @[lsu_stbuf.scala 230:121] + node _T_1050 = bits(io.end_addr_m, 31, 2) @[lsu_stbuf.scala 231:42] + node _T_1051 = bits(io.lsu_addr_r, 31, 2) @[lsu_stbuf.scala 231:66] + node _T_1052 = eq(_T_1050, _T_1051) @[lsu_stbuf.scala 231:49] + node _T_1053 = and(_T_1052, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 231:74] + node _T_1054 = and(_T_1053, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 231:95] + node _T_1055 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 231:123] + node ld_addr_rhit_lo_hi = and(_T_1054, _T_1055) @[lsu_stbuf.scala 231:121] + node _T_1056 = bits(io.lsu_addr_m, 31, 2) @[lsu_stbuf.scala 232:42] + node _T_1057 = bits(io.end_addr_r, 31, 2) @[lsu_stbuf.scala 232:66] + node _T_1058 = eq(_T_1056, _T_1057) @[lsu_stbuf.scala 232:49] + node _T_1059 = and(_T_1058, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 232:74] + node _T_1060 = and(_T_1059, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 232:95] + node _T_1061 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 232:123] + node _T_1062 = and(_T_1060, _T_1061) @[lsu_stbuf.scala 232:121] + node ld_addr_rhit_hi_lo = and(_T_1062, dual_stbuf_write_r) @[lsu_stbuf.scala 232:146] + node _T_1063 = bits(io.end_addr_m, 31, 2) @[lsu_stbuf.scala 233:42] + node _T_1064 = bits(io.end_addr_r, 31, 2) @[lsu_stbuf.scala 233:66] + node _T_1065 = eq(_T_1063, _T_1064) @[lsu_stbuf.scala 233:49] + node _T_1066 = and(_T_1065, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 233:74] + node _T_1067 = and(_T_1066, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 233:95] + node _T_1068 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 233:123] + node _T_1069 = and(_T_1067, _T_1068) @[lsu_stbuf.scala 233:121] + node ld_addr_rhit_hi_hi = and(_T_1069, dual_stbuf_write_r) @[lsu_stbuf.scala 233:146] + node _T_1070 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 235:97] + node _T_1071 = and(ld_addr_rhit_lo_lo, _T_1070) @[lsu_stbuf.scala 235:79] + node _T_1072 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 235:97] + node _T_1073 = and(ld_addr_rhit_lo_lo, _T_1072) @[lsu_stbuf.scala 235:79] + node _T_1074 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 235:97] + node _T_1075 = and(ld_addr_rhit_lo_lo, _T_1074) @[lsu_stbuf.scala 235:79] + node _T_1076 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 235:97] + node _T_1077 = and(ld_addr_rhit_lo_lo, _T_1076) @[lsu_stbuf.scala 235:79] + node _T_1078 = cat(_T_1077, _T_1075) @[Cat.scala 29:58] + node _T_1079 = cat(_T_1078, _T_1073) @[Cat.scala 29:58] + node _T_1080 = cat(_T_1079, _T_1071) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_1080 @[lsu_stbuf.scala 235:22] + node _T_1081 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 236:97] + node _T_1082 = and(ld_addr_rhit_lo_hi, _T_1081) @[lsu_stbuf.scala 236:79] + node _T_1083 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 236:97] + node _T_1084 = and(ld_addr_rhit_lo_hi, _T_1083) @[lsu_stbuf.scala 236:79] + node _T_1085 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 236:97] + node _T_1086 = and(ld_addr_rhit_lo_hi, _T_1085) @[lsu_stbuf.scala 236:79] + node _T_1087 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 236:97] + node _T_1088 = and(ld_addr_rhit_lo_hi, _T_1087) @[lsu_stbuf.scala 236:79] + node _T_1089 = cat(_T_1088, _T_1086) @[Cat.scala 29:58] + node _T_1090 = cat(_T_1089, _T_1084) @[Cat.scala 29:58] + node _T_1091 = cat(_T_1090, _T_1082) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_1091 @[lsu_stbuf.scala 236:22] + node _T_1092 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 237:97] + node _T_1093 = and(ld_addr_rhit_hi_lo, _T_1092) @[lsu_stbuf.scala 237:79] + node _T_1094 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 237:97] + node _T_1095 = and(ld_addr_rhit_hi_lo, _T_1094) @[lsu_stbuf.scala 237:79] + node _T_1096 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 237:97] + node _T_1097 = and(ld_addr_rhit_hi_lo, _T_1096) @[lsu_stbuf.scala 237:79] + node _T_1098 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 237:97] + node _T_1099 = and(ld_addr_rhit_hi_lo, _T_1098) @[lsu_stbuf.scala 237:79] + node _T_1100 = cat(_T_1099, _T_1097) @[Cat.scala 29:58] + node _T_1101 = cat(_T_1100, _T_1095) @[Cat.scala 29:58] + node _T_1102 = cat(_T_1101, _T_1093) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_1102 @[lsu_stbuf.scala 237:22] + node _T_1103 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 238:97] + node _T_1104 = and(ld_addr_rhit_hi_hi, _T_1103) @[lsu_stbuf.scala 238:79] + node _T_1105 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 238:97] + node _T_1106 = and(ld_addr_rhit_hi_hi, _T_1105) @[lsu_stbuf.scala 238:79] + node _T_1107 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 238:97] + node _T_1108 = and(ld_addr_rhit_hi_hi, _T_1107) @[lsu_stbuf.scala 238:79] + node _T_1109 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 238:97] + node _T_1110 = and(ld_addr_rhit_hi_hi, _T_1109) @[lsu_stbuf.scala 238:79] + node _T_1111 = cat(_T_1110, _T_1108) @[Cat.scala 29:58] + node _T_1112 = cat(_T_1111, _T_1106) @[Cat.scala 29:58] + node _T_1113 = cat(_T_1112, _T_1104) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_1113 @[lsu_stbuf.scala 238:22] + node _T_1114 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_stbuf.scala 240:75] + node _T_1115 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_stbuf.scala 240:99] + node _T_1116 = or(_T_1114, _T_1115) @[lsu_stbuf.scala 240:79] + node _T_1117 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_stbuf.scala 240:75] + node _T_1118 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_stbuf.scala 240:99] + node _T_1119 = or(_T_1117, _T_1118) @[lsu_stbuf.scala 240:79] + node _T_1120 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_stbuf.scala 240:75] + node _T_1121 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_stbuf.scala 240:99] + node _T_1122 = or(_T_1120, _T_1121) @[lsu_stbuf.scala 240:79] + node _T_1123 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_stbuf.scala 240:75] + node _T_1124 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_stbuf.scala 240:99] + node _T_1125 = or(_T_1123, _T_1124) @[lsu_stbuf.scala 240:79] + node _T_1126 = cat(_T_1125, _T_1122) @[Cat.scala 29:58] + node _T_1127 = cat(_T_1126, _T_1119) @[Cat.scala 29:58] + node _T_1128 = cat(_T_1127, _T_1116) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_1128 @[lsu_stbuf.scala 240:19] + node _T_1129 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_stbuf.scala 241:75] + node _T_1130 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_stbuf.scala 241:99] + node _T_1131 = or(_T_1129, _T_1130) @[lsu_stbuf.scala 241:79] + node _T_1132 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_stbuf.scala 241:75] + node _T_1133 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_stbuf.scala 241:99] + node _T_1134 = or(_T_1132, _T_1133) @[lsu_stbuf.scala 241:79] + node _T_1135 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_stbuf.scala 241:75] + node _T_1136 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_stbuf.scala 241:99] + node _T_1137 = or(_T_1135, _T_1136) @[lsu_stbuf.scala 241:79] + node _T_1138 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_stbuf.scala 241:75] + node _T_1139 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_stbuf.scala 241:99] + node _T_1140 = or(_T_1138, _T_1139) @[lsu_stbuf.scala 241:79] + node _T_1141 = cat(_T_1140, _T_1137) @[Cat.scala 29:58] + node _T_1142 = cat(_T_1141, _T_1134) @[Cat.scala 29:58] + node _T_1143 = cat(_T_1142, _T_1131) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_1143 @[lsu_stbuf.scala 241:19] + node _T_1144 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_stbuf.scala 243:48] + node _T_1145 = bits(_T_1144, 0, 0) @[Bitwise.scala 72:15] + node _T_1146 = mux(_T_1145, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1147 = bits(io.store_data_lo_r, 7, 0) @[lsu_stbuf.scala 243:73] + node _T_1148 = and(_T_1146, _T_1147) @[lsu_stbuf.scala 243:53] + node _T_1149 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_stbuf.scala 243:109] + node _T_1150 = bits(_T_1149, 0, 0) @[Bitwise.scala 72:15] + node _T_1151 = mux(_T_1150, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1152 = bits(io.store_data_hi_r, 7, 0) @[lsu_stbuf.scala 243:134] + node _T_1153 = and(_T_1151, _T_1152) @[lsu_stbuf.scala 243:114] + node fwdpipe1_lo = or(_T_1148, _T_1153) @[lsu_stbuf.scala 243:80] + node _T_1154 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_stbuf.scala 244:48] + node _T_1155 = bits(_T_1154, 0, 0) @[Bitwise.scala 72:15] + node _T_1156 = mux(_T_1155, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1157 = bits(io.store_data_lo_r, 15, 8) @[lsu_stbuf.scala 244:73] + node _T_1158 = and(_T_1156, _T_1157) @[lsu_stbuf.scala 244:53] + node _T_1159 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_stbuf.scala 244:110] + node _T_1160 = bits(_T_1159, 0, 0) @[Bitwise.scala 72:15] + node _T_1161 = mux(_T_1160, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1162 = bits(io.store_data_hi_r, 15, 8) @[lsu_stbuf.scala 244:135] + node _T_1163 = and(_T_1161, _T_1162) @[lsu_stbuf.scala 244:115] + node fwdpipe2_lo = or(_T_1158, _T_1163) @[lsu_stbuf.scala 244:81] + node _T_1164 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_stbuf.scala 245:48] + node _T_1165 = bits(_T_1164, 0, 0) @[Bitwise.scala 72:15] + node _T_1166 = mux(_T_1165, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1167 = bits(io.store_data_lo_r, 23, 16) @[lsu_stbuf.scala 245:73] + node _T_1168 = and(_T_1166, _T_1167) @[lsu_stbuf.scala 245:53] + node _T_1169 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_stbuf.scala 245:111] + node _T_1170 = bits(_T_1169, 0, 0) @[Bitwise.scala 72:15] + node _T_1171 = mux(_T_1170, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1172 = bits(io.store_data_hi_r, 23, 16) @[lsu_stbuf.scala 245:136] + node _T_1173 = and(_T_1171, _T_1172) @[lsu_stbuf.scala 245:116] + node fwdpipe3_lo = or(_T_1168, _T_1173) @[lsu_stbuf.scala 245:82] + node _T_1174 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_stbuf.scala 246:48] + node _T_1175 = bits(_T_1174, 0, 0) @[Bitwise.scala 72:15] + node _T_1176 = mux(_T_1175, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1177 = bits(io.store_data_lo_r, 31, 24) @[lsu_stbuf.scala 246:73] + node _T_1178 = and(_T_1176, _T_1177) @[lsu_stbuf.scala 246:53] + node _T_1179 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_stbuf.scala 246:111] + node _T_1180 = bits(_T_1179, 0, 0) @[Bitwise.scala 72:15] + node _T_1181 = mux(_T_1180, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1182 = bits(io.store_data_hi_r, 31, 24) @[lsu_stbuf.scala 246:136] + node _T_1183 = and(_T_1181, _T_1182) @[lsu_stbuf.scala 246:116] + node fwdpipe4_lo = or(_T_1178, _T_1183) @[lsu_stbuf.scala 246:82] + node _T_1184 = cat(fwdpipe2_lo, fwdpipe1_lo) @[Cat.scala 29:58] + node _T_1185 = cat(fwdpipe4_lo, fwdpipe3_lo) @[Cat.scala 29:58] + node _T_1186 = cat(_T_1185, _T_1184) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_1186 @[lsu_stbuf.scala 247:23] + node _T_1187 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_stbuf.scala 249:48] + node _T_1188 = bits(_T_1187, 0, 0) @[Bitwise.scala 72:15] + node _T_1189 = mux(_T_1188, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1190 = bits(io.store_data_lo_r, 7, 0) @[lsu_stbuf.scala 249:73] + node _T_1191 = and(_T_1189, _T_1190) @[lsu_stbuf.scala 249:53] + node _T_1192 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_stbuf.scala 249:109] + node _T_1193 = bits(_T_1192, 0, 0) @[Bitwise.scala 72:15] + node _T_1194 = mux(_T_1193, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1195 = bits(io.store_data_hi_r, 7, 0) @[lsu_stbuf.scala 249:134] + node _T_1196 = and(_T_1194, _T_1195) @[lsu_stbuf.scala 249:114] + node fwdpipe1_hi = or(_T_1191, _T_1196) @[lsu_stbuf.scala 249:80] + node _T_1197 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_stbuf.scala 250:48] + node _T_1198 = bits(_T_1197, 0, 0) @[Bitwise.scala 72:15] + node _T_1199 = mux(_T_1198, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1200 = bits(io.store_data_lo_r, 15, 8) @[lsu_stbuf.scala 250:73] + node _T_1201 = and(_T_1199, _T_1200) @[lsu_stbuf.scala 250:53] + node _T_1202 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_stbuf.scala 250:110] + node _T_1203 = bits(_T_1202, 0, 0) @[Bitwise.scala 72:15] + node _T_1204 = mux(_T_1203, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1205 = bits(io.store_data_hi_r, 15, 8) @[lsu_stbuf.scala 250:135] + node _T_1206 = and(_T_1204, _T_1205) @[lsu_stbuf.scala 250:115] + node fwdpipe2_hi = or(_T_1201, _T_1206) @[lsu_stbuf.scala 250:81] + node _T_1207 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_stbuf.scala 251:48] + node _T_1208 = bits(_T_1207, 0, 0) @[Bitwise.scala 72:15] + node _T_1209 = mux(_T_1208, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1210 = bits(io.store_data_lo_r, 23, 16) @[lsu_stbuf.scala 251:73] + node _T_1211 = and(_T_1209, _T_1210) @[lsu_stbuf.scala 251:53] + node _T_1212 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_stbuf.scala 251:111] + node _T_1213 = bits(_T_1212, 0, 0) @[Bitwise.scala 72:15] + node _T_1214 = mux(_T_1213, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1215 = bits(io.store_data_hi_r, 23, 16) @[lsu_stbuf.scala 251:136] + node _T_1216 = and(_T_1214, _T_1215) @[lsu_stbuf.scala 251:116] + node fwdpipe3_hi = or(_T_1211, _T_1216) @[lsu_stbuf.scala 251:82] + node _T_1217 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_stbuf.scala 252:48] + node _T_1218 = bits(_T_1217, 0, 0) @[Bitwise.scala 72:15] + node _T_1219 = mux(_T_1218, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1220 = bits(io.store_data_lo_r, 31, 24) @[lsu_stbuf.scala 252:73] + node _T_1221 = and(_T_1219, _T_1220) @[lsu_stbuf.scala 252:53] + node _T_1222 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_stbuf.scala 252:111] + node _T_1223 = bits(_T_1222, 0, 0) @[Bitwise.scala 72:15] + node _T_1224 = mux(_T_1223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1225 = bits(io.store_data_hi_r, 31, 24) @[lsu_stbuf.scala 252:136] + node _T_1226 = and(_T_1224, _T_1225) @[lsu_stbuf.scala 252:116] + node fwdpipe4_hi = or(_T_1221, _T_1226) @[lsu_stbuf.scala 252:82] + node _T_1227 = cat(fwdpipe2_hi, fwdpipe1_hi) @[Cat.scala 29:58] + node _T_1228 = cat(fwdpipe4_hi, fwdpipe3_hi) @[Cat.scala 29:58] + node _T_1229 = cat(_T_1228, _T_1227) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_1229 @[lsu_stbuf.scala 253:23] + node _T_1230 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_stbuf.scala 255:74] + node _T_1231 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_stbuf.scala 255:98] + node _T_1232 = or(_T_1230, _T_1231) @[lsu_stbuf.scala 255:78] + node _T_1233 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_stbuf.scala 255:74] + node _T_1234 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_stbuf.scala 255:98] + node _T_1235 = or(_T_1233, _T_1234) @[lsu_stbuf.scala 255:78] + node _T_1236 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_stbuf.scala 255:74] + node _T_1237 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_stbuf.scala 255:98] + node _T_1238 = or(_T_1236, _T_1237) @[lsu_stbuf.scala 255:78] + node _T_1239 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_stbuf.scala 255:74] + node _T_1240 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_stbuf.scala 255:98] + node _T_1241 = or(_T_1239, _T_1240) @[lsu_stbuf.scala 255:78] + node _T_1242 = cat(_T_1241, _T_1238) @[Cat.scala 29:58] + node _T_1243 = cat(_T_1242, _T_1235) @[Cat.scala 29:58] + node _T_1244 = cat(_T_1243, _T_1232) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_1244 @[lsu_stbuf.scala 255:18] + node _T_1245 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_stbuf.scala 256:74] + node _T_1246 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_stbuf.scala 256:98] + node _T_1247 = or(_T_1245, _T_1246) @[lsu_stbuf.scala 256:78] + node _T_1248 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_stbuf.scala 256:74] + node _T_1249 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_stbuf.scala 256:98] + node _T_1250 = or(_T_1248, _T_1249) @[lsu_stbuf.scala 256:78] + node _T_1251 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_stbuf.scala 256:74] + node _T_1252 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_stbuf.scala 256:98] + node _T_1253 = or(_T_1251, _T_1252) @[lsu_stbuf.scala 256:78] + node _T_1254 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_stbuf.scala 256:74] + node _T_1255 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_stbuf.scala 256:98] + node _T_1256 = or(_T_1254, _T_1255) @[lsu_stbuf.scala 256:78] + node _T_1257 = cat(_T_1256, _T_1253) @[Cat.scala 29:58] + node _T_1258 = cat(_T_1257, _T_1250) @[Cat.scala 29:58] + node _T_1259 = cat(_T_1258, _T_1247) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_1259 @[lsu_stbuf.scala 256:18] + node _T_1260 = bits(ld_byte_hit_hi, 0, 0) @[lsu_stbuf.scala 258:79] + node _T_1261 = or(_T_1260, stbuf_fwdbyteen_hi_pre_m_0) @[lsu_stbuf.scala 258:83] + node _T_1262 = bits(ld_byte_hit_hi, 1, 1) @[lsu_stbuf.scala 258:79] + node _T_1263 = or(_T_1262, stbuf_fwdbyteen_hi_pre_m_1) @[lsu_stbuf.scala 258:83] + node _T_1264 = bits(ld_byte_hit_hi, 2, 2) @[lsu_stbuf.scala 258:79] + node _T_1265 = or(_T_1264, stbuf_fwdbyteen_hi_pre_m_2) @[lsu_stbuf.scala 258:83] + node _T_1266 = bits(ld_byte_hit_hi, 3, 3) @[lsu_stbuf.scala 258:79] + node _T_1267 = or(_T_1266, stbuf_fwdbyteen_hi_pre_m_3) @[lsu_stbuf.scala 258:83] + node _T_1268 = cat(_T_1267, _T_1265) @[Cat.scala 29:58] + node _T_1269 = cat(_T_1268, _T_1263) @[Cat.scala 29:58] + node _T_1270 = cat(_T_1269, _T_1261) @[Cat.scala 29:58] + io.stbuf_fwdbyteen_hi_m <= _T_1270 @[lsu_stbuf.scala 258:27] + node _T_1271 = bits(ld_byte_hit_lo, 0, 0) @[lsu_stbuf.scala 259:79] + node _T_1272 = or(_T_1271, stbuf_fwdbyteen_lo_pre_m_0) @[lsu_stbuf.scala 259:83] + node _T_1273 = bits(ld_byte_hit_lo, 1, 1) @[lsu_stbuf.scala 259:79] + node _T_1274 = or(_T_1273, stbuf_fwdbyteen_lo_pre_m_1) @[lsu_stbuf.scala 259:83] + node _T_1275 = bits(ld_byte_hit_lo, 2, 2) @[lsu_stbuf.scala 259:79] + node _T_1276 = or(_T_1275, stbuf_fwdbyteen_lo_pre_m_2) @[lsu_stbuf.scala 259:83] + node _T_1277 = bits(ld_byte_hit_lo, 3, 3) @[lsu_stbuf.scala 259:79] + node _T_1278 = or(_T_1277, stbuf_fwdbyteen_lo_pre_m_3) @[lsu_stbuf.scala 259:83] + node _T_1279 = cat(_T_1278, _T_1276) @[Cat.scala 29:58] + node _T_1280 = cat(_T_1279, _T_1274) @[Cat.scala 29:58] + node _T_1281 = cat(_T_1280, _T_1272) @[Cat.scala 29:58] + io.stbuf_fwdbyteen_lo_m <= _T_1281 @[lsu_stbuf.scala 259:27] + node _T_1282 = bits(ld_byte_rhit_lo, 0, 0) @[lsu_stbuf.scala 262:46] + node _T_1283 = bits(ld_fwddata_rpipe_lo, 7, 0) @[lsu_stbuf.scala 262:69] + node _T_1284 = bits(stbuf_fwddata_lo_pre_m, 7, 0) @[lsu_stbuf.scala 262:97] + node stbuf_fwdpipe1_lo = mux(_T_1282, _T_1283, _T_1284) @[lsu_stbuf.scala 262:30] + node _T_1285 = bits(ld_byte_rhit_lo, 1, 1) @[lsu_stbuf.scala 263:46] + node _T_1286 = bits(ld_fwddata_rpipe_lo, 15, 8) @[lsu_stbuf.scala 263:69] + node _T_1287 = bits(stbuf_fwddata_lo_pre_m, 15, 8) @[lsu_stbuf.scala 263:98] + node stbuf_fwdpipe2_lo = mux(_T_1285, _T_1286, _T_1287) @[lsu_stbuf.scala 263:30] + node _T_1288 = bits(ld_byte_rhit_lo, 2, 2) @[lsu_stbuf.scala 264:46] + node _T_1289 = bits(ld_fwddata_rpipe_lo, 23, 16) @[lsu_stbuf.scala 264:69] + node _T_1290 = bits(stbuf_fwddata_lo_pre_m, 23, 16) @[lsu_stbuf.scala 264:99] + node stbuf_fwdpipe3_lo = mux(_T_1288, _T_1289, _T_1290) @[lsu_stbuf.scala 264:30] + node _T_1291 = bits(ld_byte_rhit_lo, 3, 3) @[lsu_stbuf.scala 265:46] + node _T_1292 = bits(ld_fwddata_rpipe_lo, 31, 24) @[lsu_stbuf.scala 265:69] + node _T_1293 = bits(stbuf_fwddata_lo_pre_m, 31, 24) @[lsu_stbuf.scala 265:99] + node stbuf_fwdpipe4_lo = mux(_T_1291, _T_1292, _T_1293) @[lsu_stbuf.scala 265:30] + node _T_1294 = cat(stbuf_fwdpipe2_lo, stbuf_fwdpipe1_lo) @[Cat.scala 29:58] + node _T_1295 = cat(stbuf_fwdpipe4_lo, stbuf_fwdpipe3_lo) @[Cat.scala 29:58] + node _T_1296 = cat(_T_1295, _T_1294) @[Cat.scala 29:58] + io.stbuf_fwddata_lo_m <= _T_1296 @[lsu_stbuf.scala 266:25] + node _T_1297 = bits(ld_byte_rhit_hi, 0, 0) @[lsu_stbuf.scala 268:46] + node _T_1298 = bits(ld_fwddata_rpipe_hi, 7, 0) @[lsu_stbuf.scala 268:69] + node _T_1299 = bits(stbuf_fwddata_hi_pre_m, 7, 0) @[lsu_stbuf.scala 268:97] + node stbuf_fwdpipe1_hi = mux(_T_1297, _T_1298, _T_1299) @[lsu_stbuf.scala 268:30] + node _T_1300 = bits(ld_byte_rhit_hi, 1, 1) @[lsu_stbuf.scala 269:46] + node _T_1301 = bits(ld_fwddata_rpipe_hi, 15, 8) @[lsu_stbuf.scala 269:69] + node _T_1302 = bits(stbuf_fwddata_hi_pre_m, 15, 8) @[lsu_stbuf.scala 269:98] + node stbuf_fwdpipe2_hi = mux(_T_1300, _T_1301, _T_1302) @[lsu_stbuf.scala 269:30] + node _T_1303 = bits(ld_byte_rhit_hi, 2, 2) @[lsu_stbuf.scala 270:46] + node _T_1304 = bits(ld_fwddata_rpipe_hi, 23, 16) @[lsu_stbuf.scala 270:69] + node _T_1305 = bits(stbuf_fwddata_hi_pre_m, 23, 16) @[lsu_stbuf.scala 270:99] + node stbuf_fwdpipe3_hi = mux(_T_1303, _T_1304, _T_1305) @[lsu_stbuf.scala 270:30] + node _T_1306 = bits(ld_byte_rhit_hi, 3, 3) @[lsu_stbuf.scala 271:46] + node _T_1307 = bits(ld_fwddata_rpipe_hi, 31, 24) @[lsu_stbuf.scala 271:69] + node _T_1308 = bits(stbuf_fwddata_hi_pre_m, 31, 24) @[lsu_stbuf.scala 271:99] + node stbuf_fwdpipe4_hi = mux(_T_1306, _T_1307, _T_1308) @[lsu_stbuf.scala 271:30] + node _T_1309 = cat(stbuf_fwdpipe2_hi, stbuf_fwdpipe1_hi) @[Cat.scala 29:58] + node _T_1310 = cat(stbuf_fwdpipe4_hi, stbuf_fwdpipe3_hi) @[Cat.scala 29:58] + node _T_1311 = cat(_T_1310, _T_1309) @[Cat.scala 29:58] + io.stbuf_fwddata_hi_m <= _T_1311 @[lsu_stbuf.scala 272:25] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_ecc : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c2_r_clk : Clock, flip clk_override : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip stbuf_data_any : UInt<32>, flip dec_tlu_core_ecc_disable : UInt<1>, flip lsu_dccm_rden_r : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_addr_r : UInt<16>, flip end_addr_r : UInt<16>, flip lsu_addr_m : UInt<16>, flip end_addr_m : UInt<16>, flip dccm_rdata_hi_r : UInt<32>, flip dccm_rdata_lo_r : UInt<32>, flip dccm_rdata_hi_m : UInt<32>, flip dccm_rdata_lo_m : UInt<32>, flip dccm_data_ecc_hi_r : UInt<7>, flip dccm_data_ecc_lo_r : UInt<7>, flip dccm_data_ecc_hi_m : UInt<7>, flip dccm_data_ecc_lo_m : UInt<7>, flip ld_single_ecc_error_r : UInt<1>, flip ld_single_ecc_error_r_ff : UInt<1>, flip lsu_dccm_rden_m : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_wen : UInt<1>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip scan_mode : UInt<1>, sec_data_hi_r : UInt<32>, sec_data_lo_r : UInt<32>, sec_data_hi_m : UInt<32>, sec_data_lo_m : UInt<32>, sec_data_hi_r_ff : UInt<32>, sec_data_lo_r_ff : UInt<32>, dma_dccm_wdata_ecc_hi : UInt<7>, dma_dccm_wdata_ecc_lo : UInt<7>, stbuf_ecc_any : UInt<7>, sec_data_ecc_hi_r_ff : UInt<7>, sec_data_ecc_lo_r_ff : UInt<7>, single_ecc_error_hi_r : UInt<1>, single_ecc_error_lo_r : UInt<1>, lsu_single_ecc_error_r : UInt<1>, lsu_double_ecc_error_r : UInt<1>, lsu_single_ecc_error_m : UInt<1>, lsu_double_ecc_error_m : UInt<1>} + + wire is_ldst_r : UInt<1> + is_ldst_r <= UInt<1>("h00") + wire is_ldst_hi_any : UInt<1> + is_ldst_hi_any <= UInt<1>("h00") + wire is_ldst_lo_any : UInt<1> + is_ldst_lo_any <= UInt<1>("h00") + wire dccm_wdata_hi_any : UInt<32> + dccm_wdata_hi_any <= UInt<32>("h00") + wire dccm_wdata_lo_any : UInt<32> + dccm_wdata_lo_any <= UInt<32>("h00") + wire dccm_rdata_hi_any : UInt<32> + dccm_rdata_hi_any <= UInt<32>("h00") + wire dccm_rdata_lo_any : UInt<32> + dccm_rdata_lo_any <= UInt<32>("h00") + wire dccm_data_ecc_hi_any : UInt<7> + dccm_data_ecc_hi_any <= UInt<7>("h00") + wire dccm_data_ecc_lo_any : UInt<7> + dccm_data_ecc_lo_any <= UInt<7>("h00") + wire double_ecc_error_hi_m : UInt<1> + double_ecc_error_hi_m <= UInt<1>("h00") + wire double_ecc_error_lo_m : UInt<1> + double_ecc_error_lo_m <= UInt<1>("h00") + wire double_ecc_error_hi_r : UInt<1> + double_ecc_error_hi_r <= UInt<1>("h00") + wire double_ecc_error_lo_r : UInt<1> + double_ecc_error_lo_r <= UInt<1>("h00") + wire ldst_dual_m : UInt<1> + ldst_dual_m <= UInt<1>("h00") + wire ldst_dual_r : UInt<1> + ldst_dual_r <= UInt<1>("h00") + wire is_ldst_m : UInt<1> + is_ldst_m <= UInt<1>("h00") + wire is_ldst_hi_m : UInt<1> + is_ldst_hi_m <= UInt<1>("h00") + wire is_ldst_lo_m : UInt<1> + is_ldst_lo_m <= UInt<1>("h00") + wire is_ldst_hi_r : UInt<1> + is_ldst_hi_r <= UInt<1>("h00") + wire is_ldst_lo_r : UInt<1> + is_ldst_lo_r <= UInt<1>("h00") + io.sec_data_hi_m <= UInt<1>("h00") @[lsu_ecc.scala 89:32] + io.sec_data_lo_m <= UInt<1>("h00") @[lsu_ecc.scala 90:32] + io.lsu_single_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 91:30] + io.lsu_double_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 92:30] + wire _T : UInt<1>[18] @[lib.scala 173:18] + wire _T_1 : UInt<1>[18] @[lib.scala 174:18] + wire _T_2 : UInt<1>[18] @[lib.scala 175:18] + wire _T_3 : UInt<1>[15] @[lib.scala 176:18] + wire _T_4 : UInt<1>[15] @[lib.scala 177:18] + wire _T_5 : UInt<1>[6] @[lib.scala 178:18] + node _T_6 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 185:36] + _T[0] <= _T_6 @[lib.scala 185:30] + node _T_7 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 186:36] + _T_1[0] <= _T_7 @[lib.scala 186:30] + node _T_8 = bits(dccm_rdata_hi_any, 1, 1) @[lib.scala 185:36] + _T[1] <= _T_8 @[lib.scala 185:30] + node _T_9 = bits(dccm_rdata_hi_any, 1, 1) @[lib.scala 187:36] + _T_2[0] <= _T_9 @[lib.scala 187:30] + node _T_10 = bits(dccm_rdata_hi_any, 2, 2) @[lib.scala 186:36] + _T_1[1] <= _T_10 @[lib.scala 186:30] + node _T_11 = bits(dccm_rdata_hi_any, 2, 2) @[lib.scala 187:36] + _T_2[1] <= _T_11 @[lib.scala 187:30] + node _T_12 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 185:36] + _T[2] <= _T_12 @[lib.scala 185:30] + node _T_13 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 186:36] + _T_1[2] <= _T_13 @[lib.scala 186:30] + node _T_14 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 187:36] + _T_2[2] <= _T_14 @[lib.scala 187:30] + node _T_15 = bits(dccm_rdata_hi_any, 4, 4) @[lib.scala 185:36] + _T[3] <= _T_15 @[lib.scala 185:30] + node _T_16 = bits(dccm_rdata_hi_any, 4, 4) @[lib.scala 188:36] + _T_3[0] <= _T_16 @[lib.scala 188:30] + node _T_17 = bits(dccm_rdata_hi_any, 5, 5) @[lib.scala 186:36] + _T_1[3] <= _T_17 @[lib.scala 186:30] + node _T_18 = bits(dccm_rdata_hi_any, 5, 5) @[lib.scala 188:36] + _T_3[1] <= _T_18 @[lib.scala 188:30] + node _T_19 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 185:36] + _T[4] <= _T_19 @[lib.scala 185:30] + node _T_20 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 186:36] + _T_1[4] <= _T_20 @[lib.scala 186:30] + node _T_21 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 188:36] + _T_3[2] <= _T_21 @[lib.scala 188:30] + node _T_22 = bits(dccm_rdata_hi_any, 7, 7) @[lib.scala 187:36] + _T_2[3] <= _T_22 @[lib.scala 187:30] + node _T_23 = bits(dccm_rdata_hi_any, 7, 7) @[lib.scala 188:36] + _T_3[3] <= _T_23 @[lib.scala 188:30] + node _T_24 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 185:36] + _T[5] <= _T_24 @[lib.scala 185:30] + node _T_25 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 187:36] + _T_2[4] <= _T_25 @[lib.scala 187:30] + node _T_26 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 188:36] + _T_3[4] <= _T_26 @[lib.scala 188:30] + node _T_27 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 186:36] + _T_1[5] <= _T_27 @[lib.scala 186:30] + node _T_28 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 187:36] + _T_2[5] <= _T_28 @[lib.scala 187:30] + node _T_29 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 188:36] + _T_3[5] <= _T_29 @[lib.scala 188:30] + node _T_30 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 185:36] + _T[6] <= _T_30 @[lib.scala 185:30] + node _T_31 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 186:36] + _T_1[6] <= _T_31 @[lib.scala 186:30] + node _T_32 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 187:36] + _T_2[6] <= _T_32 @[lib.scala 187:30] + node _T_33 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 188:36] + _T_3[6] <= _T_33 @[lib.scala 188:30] + node _T_34 = bits(dccm_rdata_hi_any, 11, 11) @[lib.scala 185:36] + _T[7] <= _T_34 @[lib.scala 185:30] + node _T_35 = bits(dccm_rdata_hi_any, 11, 11) @[lib.scala 189:36] + _T_4[0] <= _T_35 @[lib.scala 189:30] + node _T_36 = bits(dccm_rdata_hi_any, 12, 12) @[lib.scala 186:36] + _T_1[7] <= _T_36 @[lib.scala 186:30] + node _T_37 = bits(dccm_rdata_hi_any, 12, 12) @[lib.scala 189:36] + _T_4[1] <= _T_37 @[lib.scala 189:30] + node _T_38 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 185:36] + _T[8] <= _T_38 @[lib.scala 185:30] + node _T_39 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 186:36] + _T_1[8] <= _T_39 @[lib.scala 186:30] + node _T_40 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 189:36] + _T_4[2] <= _T_40 @[lib.scala 189:30] + node _T_41 = bits(dccm_rdata_hi_any, 14, 14) @[lib.scala 187:36] + _T_2[7] <= _T_41 @[lib.scala 187:30] + node _T_42 = bits(dccm_rdata_hi_any, 14, 14) @[lib.scala 189:36] + _T_4[3] <= _T_42 @[lib.scala 189:30] + node _T_43 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 185:36] + _T[9] <= _T_43 @[lib.scala 185:30] + node _T_44 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 187:36] + _T_2[8] <= _T_44 @[lib.scala 187:30] + node _T_45 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 189:36] + _T_4[4] <= _T_45 @[lib.scala 189:30] + node _T_46 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 186:36] + _T_1[9] <= _T_46 @[lib.scala 186:30] + node _T_47 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 187:36] + _T_2[9] <= _T_47 @[lib.scala 187:30] + node _T_48 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 189:36] + _T_4[5] <= _T_48 @[lib.scala 189:30] + node _T_49 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 185:36] + _T[10] <= _T_49 @[lib.scala 185:30] + node _T_50 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 186:36] + _T_1[10] <= _T_50 @[lib.scala 186:30] + node _T_51 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 187:36] + _T_2[10] <= _T_51 @[lib.scala 187:30] + node _T_52 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 189:36] + _T_4[6] <= _T_52 @[lib.scala 189:30] + node _T_53 = bits(dccm_rdata_hi_any, 18, 18) @[lib.scala 188:36] + _T_3[7] <= _T_53 @[lib.scala 188:30] + node _T_54 = bits(dccm_rdata_hi_any, 18, 18) @[lib.scala 189:36] + _T_4[7] <= _T_54 @[lib.scala 189:30] + node _T_55 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 185:36] + _T[11] <= _T_55 @[lib.scala 185:30] + node _T_56 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 188:36] + _T_3[8] <= _T_56 @[lib.scala 188:30] + node _T_57 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 189:36] + _T_4[8] <= _T_57 @[lib.scala 189:30] + node _T_58 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 186:36] + _T_1[11] <= _T_58 @[lib.scala 186:30] + node _T_59 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 188:36] + _T_3[9] <= _T_59 @[lib.scala 188:30] + node _T_60 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 189:36] + _T_4[9] <= _T_60 @[lib.scala 189:30] + node _T_61 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 185:36] + _T[12] <= _T_61 @[lib.scala 185:30] + node _T_62 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 186:36] + _T_1[12] <= _T_62 @[lib.scala 186:30] + node _T_63 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 188:36] + _T_3[10] <= _T_63 @[lib.scala 188:30] + node _T_64 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 189:36] + _T_4[10] <= _T_64 @[lib.scala 189:30] + node _T_65 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 187:36] + _T_2[11] <= _T_65 @[lib.scala 187:30] + node _T_66 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 188:36] + _T_3[11] <= _T_66 @[lib.scala 188:30] + node _T_67 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 189:36] + _T_4[11] <= _T_67 @[lib.scala 189:30] + node _T_68 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 185:36] + _T[13] <= _T_68 @[lib.scala 185:30] + node _T_69 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 187:36] + _T_2[12] <= _T_69 @[lib.scala 187:30] + node _T_70 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 188:36] + _T_3[12] <= _T_70 @[lib.scala 188:30] + node _T_71 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 189:36] + _T_4[12] <= _T_71 @[lib.scala 189:30] + node _T_72 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 186:36] + _T_1[13] <= _T_72 @[lib.scala 186:30] + node _T_73 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 187:36] + _T_2[13] <= _T_73 @[lib.scala 187:30] + node _T_74 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 188:36] + _T_3[13] <= _T_74 @[lib.scala 188:30] + node _T_75 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 189:36] + _T_4[13] <= _T_75 @[lib.scala 189:30] + node _T_76 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 185:36] + _T[14] <= _T_76 @[lib.scala 185:30] + node _T_77 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 186:36] + _T_1[14] <= _T_77 @[lib.scala 186:30] + node _T_78 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 187:36] + _T_2[14] <= _T_78 @[lib.scala 187:30] + node _T_79 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 188:36] + _T_3[14] <= _T_79 @[lib.scala 188:30] + node _T_80 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 189:36] + _T_4[14] <= _T_80 @[lib.scala 189:30] + node _T_81 = bits(dccm_rdata_hi_any, 26, 26) @[lib.scala 185:36] + _T[15] <= _T_81 @[lib.scala 185:30] + node _T_82 = bits(dccm_rdata_hi_any, 26, 26) @[lib.scala 190:36] + _T_5[0] <= _T_82 @[lib.scala 190:30] + node _T_83 = bits(dccm_rdata_hi_any, 27, 27) @[lib.scala 186:36] + _T_1[15] <= _T_83 @[lib.scala 186:30] + node _T_84 = bits(dccm_rdata_hi_any, 27, 27) @[lib.scala 190:36] + _T_5[1] <= _T_84 @[lib.scala 190:30] + node _T_85 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 185:36] + _T[16] <= _T_85 @[lib.scala 185:30] + node _T_86 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 186:36] + _T_1[16] <= _T_86 @[lib.scala 186:30] + node _T_87 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 190:36] + _T_5[2] <= _T_87 @[lib.scala 190:30] + node _T_88 = bits(dccm_rdata_hi_any, 29, 29) @[lib.scala 187:36] + _T_2[15] <= _T_88 @[lib.scala 187:30] + node _T_89 = bits(dccm_rdata_hi_any, 29, 29) @[lib.scala 190:36] + _T_5[3] <= _T_89 @[lib.scala 190:30] + node _T_90 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 185:36] + _T[17] <= _T_90 @[lib.scala 185:30] + node _T_91 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 187:36] + _T_2[16] <= _T_91 @[lib.scala 187:30] + node _T_92 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 190:36] + _T_5[4] <= _T_92 @[lib.scala 190:30] + node _T_93 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 186:36] + _T_1[17] <= _T_93 @[lib.scala 186:30] + node _T_94 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 187:36] + _T_2[17] <= _T_94 @[lib.scala 187:30] + node _T_95 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 190:36] + _T_5[5] <= _T_95 @[lib.scala 190:30] + node _T_96 = xorr(dccm_rdata_hi_any) @[lib.scala 193:30] + node _T_97 = xorr(dccm_data_ecc_hi_any) @[lib.scala 193:44] + node _T_98 = xor(_T_96, _T_97) @[lib.scala 193:35] + node _T_99 = not(UInt<1>("h00")) @[lib.scala 193:52] + node _T_100 = and(_T_98, _T_99) @[lib.scala 193:50] + node _T_101 = bits(dccm_data_ecc_hi_any, 5, 5) @[lib.scala 193:68] + node _T_102 = cat(_T_5[2], _T_5[1]) @[lib.scala 193:76] + node _T_103 = cat(_T_102, _T_5[0]) @[lib.scala 193:76] + node _T_104 = cat(_T_5[5], _T_5[4]) @[lib.scala 193:76] + node _T_105 = cat(_T_104, _T_5[3]) @[lib.scala 193:76] + node _T_106 = cat(_T_105, _T_103) @[lib.scala 193:76] + node _T_107 = xorr(_T_106) @[lib.scala 193:83] + node _T_108 = xor(_T_101, _T_107) @[lib.scala 193:71] + node _T_109 = bits(dccm_data_ecc_hi_any, 4, 4) @[lib.scala 193:95] + node _T_110 = cat(_T_4[2], _T_4[1]) @[lib.scala 193:103] + node _T_111 = cat(_T_110, _T_4[0]) @[lib.scala 193:103] + node _T_112 = cat(_T_4[4], _T_4[3]) @[lib.scala 193:103] + node _T_113 = cat(_T_4[6], _T_4[5]) @[lib.scala 193:103] + node _T_114 = cat(_T_113, _T_112) @[lib.scala 193:103] + node _T_115 = cat(_T_114, _T_111) @[lib.scala 193:103] + node _T_116 = cat(_T_4[8], _T_4[7]) @[lib.scala 193:103] + node _T_117 = cat(_T_4[10], _T_4[9]) @[lib.scala 193:103] + node _T_118 = cat(_T_117, _T_116) @[lib.scala 193:103] + node _T_119 = cat(_T_4[12], _T_4[11]) @[lib.scala 193:103] + node _T_120 = cat(_T_4[14], _T_4[13]) @[lib.scala 193:103] + node _T_121 = cat(_T_120, _T_119) @[lib.scala 193:103] + node _T_122 = cat(_T_121, _T_118) @[lib.scala 193:103] + node _T_123 = cat(_T_122, _T_115) @[lib.scala 193:103] + node _T_124 = xorr(_T_123) @[lib.scala 193:110] + node _T_125 = xor(_T_109, _T_124) @[lib.scala 193:98] + node _T_126 = bits(dccm_data_ecc_hi_any, 3, 3) @[lib.scala 193:122] + node _T_127 = cat(_T_3[2], _T_3[1]) @[lib.scala 193:130] + node _T_128 = cat(_T_127, _T_3[0]) @[lib.scala 193:130] + node _T_129 = cat(_T_3[4], _T_3[3]) @[lib.scala 193:130] + node _T_130 = cat(_T_3[6], _T_3[5]) @[lib.scala 193:130] + node _T_131 = cat(_T_130, _T_129) @[lib.scala 193:130] + node _T_132 = cat(_T_131, _T_128) @[lib.scala 193:130] + node _T_133 = cat(_T_3[8], _T_3[7]) @[lib.scala 193:130] + node _T_134 = cat(_T_3[10], _T_3[9]) @[lib.scala 193:130] + node _T_135 = cat(_T_134, _T_133) @[lib.scala 193:130] + node _T_136 = cat(_T_3[12], _T_3[11]) @[lib.scala 193:130] + node _T_137 = cat(_T_3[14], _T_3[13]) @[lib.scala 193:130] + node _T_138 = cat(_T_137, _T_136) @[lib.scala 193:130] + node _T_139 = cat(_T_138, _T_135) @[lib.scala 193:130] + node _T_140 = cat(_T_139, _T_132) @[lib.scala 193:130] + node _T_141 = xorr(_T_140) @[lib.scala 193:137] + node _T_142 = xor(_T_126, _T_141) @[lib.scala 193:125] + node _T_143 = bits(dccm_data_ecc_hi_any, 2, 2) @[lib.scala 193:149] + node _T_144 = cat(_T_2[1], _T_2[0]) @[lib.scala 193:157] + node _T_145 = cat(_T_2[3], _T_2[2]) @[lib.scala 193:157] + node _T_146 = cat(_T_145, _T_144) @[lib.scala 193:157] + node _T_147 = cat(_T_2[5], _T_2[4]) @[lib.scala 193:157] + node _T_148 = cat(_T_2[8], _T_2[7]) @[lib.scala 193:157] + node _T_149 = cat(_T_148, _T_2[6]) @[lib.scala 193:157] + node _T_150 = cat(_T_149, _T_147) @[lib.scala 193:157] + node _T_151 = cat(_T_150, _T_146) @[lib.scala 193:157] + node _T_152 = cat(_T_2[10], _T_2[9]) @[lib.scala 193:157] + node _T_153 = cat(_T_2[12], _T_2[11]) @[lib.scala 193:157] + node _T_154 = cat(_T_153, _T_152) @[lib.scala 193:157] + node _T_155 = cat(_T_2[14], _T_2[13]) @[lib.scala 193:157] + node _T_156 = cat(_T_2[17], _T_2[16]) @[lib.scala 193:157] + node _T_157 = cat(_T_156, _T_2[15]) @[lib.scala 193:157] + node _T_158 = cat(_T_157, _T_155) @[lib.scala 193:157] + node _T_159 = cat(_T_158, _T_154) @[lib.scala 193:157] + node _T_160 = cat(_T_159, _T_151) @[lib.scala 193:157] + node _T_161 = xorr(_T_160) @[lib.scala 193:164] + node _T_162 = xor(_T_143, _T_161) @[lib.scala 193:152] + node _T_163 = bits(dccm_data_ecc_hi_any, 1, 1) @[lib.scala 193:176] + node _T_164 = cat(_T_1[1], _T_1[0]) @[lib.scala 193:184] + node _T_165 = cat(_T_1[3], _T_1[2]) @[lib.scala 193:184] + node _T_166 = cat(_T_165, _T_164) @[lib.scala 193:184] + node _T_167 = cat(_T_1[5], _T_1[4]) @[lib.scala 193:184] + node _T_168 = cat(_T_1[8], _T_1[7]) @[lib.scala 193:184] + node _T_169 = cat(_T_168, _T_1[6]) @[lib.scala 193:184] + node _T_170 = cat(_T_169, _T_167) @[lib.scala 193:184] + node _T_171 = cat(_T_170, _T_166) @[lib.scala 193:184] + node _T_172 = cat(_T_1[10], _T_1[9]) @[lib.scala 193:184] + node _T_173 = cat(_T_1[12], _T_1[11]) @[lib.scala 193:184] + node _T_174 = cat(_T_173, _T_172) @[lib.scala 193:184] + node _T_175 = cat(_T_1[14], _T_1[13]) @[lib.scala 193:184] + node _T_176 = cat(_T_1[17], _T_1[16]) @[lib.scala 193:184] + node _T_177 = cat(_T_176, _T_1[15]) @[lib.scala 193:184] + node _T_178 = cat(_T_177, _T_175) @[lib.scala 193:184] + node _T_179 = cat(_T_178, _T_174) @[lib.scala 193:184] + node _T_180 = cat(_T_179, _T_171) @[lib.scala 193:184] + node _T_181 = xorr(_T_180) @[lib.scala 193:191] + node _T_182 = xor(_T_163, _T_181) @[lib.scala 193:179] + node _T_183 = bits(dccm_data_ecc_hi_any, 0, 0) @[lib.scala 193:203] + node _T_184 = cat(_T[1], _T[0]) @[lib.scala 193:211] + node _T_185 = cat(_T[3], _T[2]) @[lib.scala 193:211] + node _T_186 = cat(_T_185, _T_184) @[lib.scala 193:211] + node _T_187 = cat(_T[5], _T[4]) @[lib.scala 193:211] + node _T_188 = cat(_T[8], _T[7]) @[lib.scala 193:211] + node _T_189 = cat(_T_188, _T[6]) @[lib.scala 193:211] + node _T_190 = cat(_T_189, _T_187) @[lib.scala 193:211] + node _T_191 = cat(_T_190, _T_186) @[lib.scala 193:211] + node _T_192 = cat(_T[10], _T[9]) @[lib.scala 193:211] + node _T_193 = cat(_T[12], _T[11]) @[lib.scala 193:211] + node _T_194 = cat(_T_193, _T_192) @[lib.scala 193:211] + node _T_195 = cat(_T[14], _T[13]) @[lib.scala 193:211] + node _T_196 = cat(_T[17], _T[16]) @[lib.scala 193:211] + node _T_197 = cat(_T_196, _T[15]) @[lib.scala 193:211] + node _T_198 = cat(_T_197, _T_195) @[lib.scala 193:211] + node _T_199 = cat(_T_198, _T_194) @[lib.scala 193:211] + node _T_200 = cat(_T_199, _T_191) @[lib.scala 193:211] + node _T_201 = xorr(_T_200) @[lib.scala 193:218] + node _T_202 = xor(_T_183, _T_201) @[lib.scala 193:206] + node _T_203 = cat(_T_162, _T_182) @[Cat.scala 29:58] + node _T_204 = cat(_T_203, _T_202) @[Cat.scala 29:58] + node _T_205 = cat(_T_125, _T_142) @[Cat.scala 29:58] + node _T_206 = cat(_T_100, _T_108) @[Cat.scala 29:58] + node _T_207 = cat(_T_206, _T_205) @[Cat.scala 29:58] + node _T_208 = cat(_T_207, _T_204) @[Cat.scala 29:58] + node _T_209 = neq(_T_208, UInt<1>("h00")) @[lib.scala 194:44] + node _T_210 = and(is_ldst_hi_any, _T_209) @[lib.scala 194:32] + node _T_211 = bits(_T_208, 6, 6) @[lib.scala 194:64] + node single_ecc_error_hi_any = and(_T_210, _T_211) @[lib.scala 194:53] + node _T_212 = neq(_T_208, UInt<1>("h00")) @[lib.scala 195:44] + node _T_213 = and(is_ldst_hi_any, _T_212) @[lib.scala 195:32] + node _T_214 = bits(_T_208, 6, 6) @[lib.scala 195:65] + node _T_215 = not(_T_214) @[lib.scala 195:55] + node double_ecc_error_hi_any = and(_T_213, _T_215) @[lib.scala 195:53] + wire _T_216 : UInt<1>[39] @[lib.scala 196:26] + node _T_217 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_218 = eq(_T_217, UInt<1>("h01")) @[lib.scala 199:41] + _T_216[0] <= _T_218 @[lib.scala 199:23] + node _T_219 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_220 = eq(_T_219, UInt<2>("h02")) @[lib.scala 199:41] + _T_216[1] <= _T_220 @[lib.scala 199:23] + node _T_221 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_222 = eq(_T_221, UInt<2>("h03")) @[lib.scala 199:41] + _T_216[2] <= _T_222 @[lib.scala 199:23] + node _T_223 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_224 = eq(_T_223, UInt<3>("h04")) @[lib.scala 199:41] + _T_216[3] <= _T_224 @[lib.scala 199:23] + node _T_225 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_226 = eq(_T_225, UInt<3>("h05")) @[lib.scala 199:41] + _T_216[4] <= _T_226 @[lib.scala 199:23] + node _T_227 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_228 = eq(_T_227, UInt<3>("h06")) @[lib.scala 199:41] + _T_216[5] <= _T_228 @[lib.scala 199:23] + node _T_229 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_230 = eq(_T_229, UInt<3>("h07")) @[lib.scala 199:41] + _T_216[6] <= _T_230 @[lib.scala 199:23] + node _T_231 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_232 = eq(_T_231, UInt<4>("h08")) @[lib.scala 199:41] + _T_216[7] <= _T_232 @[lib.scala 199:23] + node _T_233 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_234 = eq(_T_233, UInt<4>("h09")) @[lib.scala 199:41] + _T_216[8] <= _T_234 @[lib.scala 199:23] + node _T_235 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_236 = eq(_T_235, UInt<4>("h0a")) @[lib.scala 199:41] + _T_216[9] <= _T_236 @[lib.scala 199:23] + node _T_237 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_238 = eq(_T_237, UInt<4>("h0b")) @[lib.scala 199:41] + _T_216[10] <= _T_238 @[lib.scala 199:23] + node _T_239 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_240 = eq(_T_239, UInt<4>("h0c")) @[lib.scala 199:41] + _T_216[11] <= _T_240 @[lib.scala 199:23] + node _T_241 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_242 = eq(_T_241, UInt<4>("h0d")) @[lib.scala 199:41] + _T_216[12] <= _T_242 @[lib.scala 199:23] + node _T_243 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_244 = eq(_T_243, UInt<4>("h0e")) @[lib.scala 199:41] + _T_216[13] <= _T_244 @[lib.scala 199:23] + node _T_245 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_246 = eq(_T_245, UInt<4>("h0f")) @[lib.scala 199:41] + _T_216[14] <= _T_246 @[lib.scala 199:23] + node _T_247 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_248 = eq(_T_247, UInt<5>("h010")) @[lib.scala 199:41] + _T_216[15] <= _T_248 @[lib.scala 199:23] + node _T_249 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_250 = eq(_T_249, UInt<5>("h011")) @[lib.scala 199:41] + _T_216[16] <= _T_250 @[lib.scala 199:23] + node _T_251 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_252 = eq(_T_251, UInt<5>("h012")) @[lib.scala 199:41] + _T_216[17] <= _T_252 @[lib.scala 199:23] + node _T_253 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_254 = eq(_T_253, UInt<5>("h013")) @[lib.scala 199:41] + _T_216[18] <= _T_254 @[lib.scala 199:23] + node _T_255 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_256 = eq(_T_255, UInt<5>("h014")) @[lib.scala 199:41] + _T_216[19] <= _T_256 @[lib.scala 199:23] + node _T_257 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_258 = eq(_T_257, UInt<5>("h015")) @[lib.scala 199:41] + _T_216[20] <= _T_258 @[lib.scala 199:23] + node _T_259 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_260 = eq(_T_259, UInt<5>("h016")) @[lib.scala 199:41] + _T_216[21] <= _T_260 @[lib.scala 199:23] + node _T_261 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_262 = eq(_T_261, UInt<5>("h017")) @[lib.scala 199:41] + _T_216[22] <= _T_262 @[lib.scala 199:23] + node _T_263 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_264 = eq(_T_263, UInt<5>("h018")) @[lib.scala 199:41] + _T_216[23] <= _T_264 @[lib.scala 199:23] + node _T_265 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_266 = eq(_T_265, UInt<5>("h019")) @[lib.scala 199:41] + _T_216[24] <= _T_266 @[lib.scala 199:23] + node _T_267 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_268 = eq(_T_267, UInt<5>("h01a")) @[lib.scala 199:41] + _T_216[25] <= _T_268 @[lib.scala 199:23] + node _T_269 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_270 = eq(_T_269, UInt<5>("h01b")) @[lib.scala 199:41] + _T_216[26] <= _T_270 @[lib.scala 199:23] + node _T_271 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_272 = eq(_T_271, UInt<5>("h01c")) @[lib.scala 199:41] + _T_216[27] <= _T_272 @[lib.scala 199:23] + node _T_273 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_274 = eq(_T_273, UInt<5>("h01d")) @[lib.scala 199:41] + _T_216[28] <= _T_274 @[lib.scala 199:23] + node _T_275 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_276 = eq(_T_275, UInt<5>("h01e")) @[lib.scala 199:41] + _T_216[29] <= _T_276 @[lib.scala 199:23] + node _T_277 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_278 = eq(_T_277, UInt<5>("h01f")) @[lib.scala 199:41] + _T_216[30] <= _T_278 @[lib.scala 199:23] + node _T_279 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_280 = eq(_T_279, UInt<6>("h020")) @[lib.scala 199:41] + _T_216[31] <= _T_280 @[lib.scala 199:23] + node _T_281 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_282 = eq(_T_281, UInt<6>("h021")) @[lib.scala 199:41] + _T_216[32] <= _T_282 @[lib.scala 199:23] + node _T_283 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_284 = eq(_T_283, UInt<6>("h022")) @[lib.scala 199:41] + _T_216[33] <= _T_284 @[lib.scala 199:23] + node _T_285 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_286 = eq(_T_285, UInt<6>("h023")) @[lib.scala 199:41] + _T_216[34] <= _T_286 @[lib.scala 199:23] + node _T_287 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_288 = eq(_T_287, UInt<6>("h024")) @[lib.scala 199:41] + _T_216[35] <= _T_288 @[lib.scala 199:23] + node _T_289 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_290 = eq(_T_289, UInt<6>("h025")) @[lib.scala 199:41] + _T_216[36] <= _T_290 @[lib.scala 199:23] + node _T_291 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_292 = eq(_T_291, UInt<6>("h026")) @[lib.scala 199:41] + _T_216[37] <= _T_292 @[lib.scala 199:23] + node _T_293 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_294 = eq(_T_293, UInt<6>("h027")) @[lib.scala 199:41] + _T_216[38] <= _T_294 @[lib.scala 199:23] + node _T_295 = bits(dccm_data_ecc_hi_any, 6, 6) @[lib.scala 201:37] + node _T_296 = bits(dccm_rdata_hi_any, 31, 26) @[lib.scala 201:45] + node _T_297 = bits(dccm_data_ecc_hi_any, 5, 5) @[lib.scala 201:60] + node _T_298 = bits(dccm_rdata_hi_any, 25, 11) @[lib.scala 201:68] + node _T_299 = bits(dccm_data_ecc_hi_any, 4, 4) @[lib.scala 201:83] + node _T_300 = bits(dccm_rdata_hi_any, 10, 4) @[lib.scala 201:91] + node _T_301 = bits(dccm_data_ecc_hi_any, 3, 3) @[lib.scala 201:105] + node _T_302 = bits(dccm_rdata_hi_any, 3, 1) @[lib.scala 201:113] + node _T_303 = bits(dccm_data_ecc_hi_any, 2, 2) @[lib.scala 201:126] + node _T_304 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 201:134] + node _T_305 = bits(dccm_data_ecc_hi_any, 1, 0) @[lib.scala 201:145] + node _T_306 = cat(_T_304, _T_305) @[Cat.scala 29:58] + node _T_307 = cat(_T_301, _T_302) @[Cat.scala 29:58] + node _T_308 = cat(_T_307, _T_303) @[Cat.scala 29:58] + node _T_309 = cat(_T_308, _T_306) @[Cat.scala 29:58] + node _T_310 = cat(_T_298, _T_299) @[Cat.scala 29:58] + node _T_311 = cat(_T_310, _T_300) @[Cat.scala 29:58] + node _T_312 = cat(_T_295, _T_296) @[Cat.scala 29:58] + node _T_313 = cat(_T_312, _T_297) @[Cat.scala 29:58] + node _T_314 = cat(_T_313, _T_311) @[Cat.scala 29:58] + node _T_315 = cat(_T_314, _T_309) @[Cat.scala 29:58] + node _T_316 = bits(single_ecc_error_hi_any, 0, 0) @[lib.scala 202:49] + node _T_317 = cat(_T_216[1], _T_216[0]) @[lib.scala 202:69] + node _T_318 = cat(_T_216[3], _T_216[2]) @[lib.scala 202:69] + node _T_319 = cat(_T_318, _T_317) @[lib.scala 202:69] + node _T_320 = cat(_T_216[5], _T_216[4]) @[lib.scala 202:69] + node _T_321 = cat(_T_216[8], _T_216[7]) @[lib.scala 202:69] + node _T_322 = cat(_T_321, _T_216[6]) @[lib.scala 202:69] + node _T_323 = cat(_T_322, _T_320) @[lib.scala 202:69] + node _T_324 = cat(_T_323, _T_319) @[lib.scala 202:69] + node _T_325 = cat(_T_216[10], _T_216[9]) @[lib.scala 202:69] + node _T_326 = cat(_T_216[13], _T_216[12]) @[lib.scala 202:69] + node _T_327 = cat(_T_326, _T_216[11]) @[lib.scala 202:69] + node _T_328 = cat(_T_327, _T_325) @[lib.scala 202:69] + node _T_329 = cat(_T_216[15], _T_216[14]) @[lib.scala 202:69] + node _T_330 = cat(_T_216[18], _T_216[17]) @[lib.scala 202:69] + node _T_331 = cat(_T_330, _T_216[16]) @[lib.scala 202:69] + node _T_332 = cat(_T_331, _T_329) @[lib.scala 202:69] + node _T_333 = cat(_T_332, _T_328) @[lib.scala 202:69] + node _T_334 = cat(_T_333, _T_324) @[lib.scala 202:69] + node _T_335 = cat(_T_216[20], _T_216[19]) @[lib.scala 202:69] + node _T_336 = cat(_T_216[23], _T_216[22]) @[lib.scala 202:69] + node _T_337 = cat(_T_336, _T_216[21]) @[lib.scala 202:69] + node _T_338 = cat(_T_337, _T_335) @[lib.scala 202:69] + node _T_339 = cat(_T_216[25], _T_216[24]) @[lib.scala 202:69] + node _T_340 = cat(_T_216[28], _T_216[27]) @[lib.scala 202:69] + node _T_341 = cat(_T_340, _T_216[26]) @[lib.scala 202:69] + node _T_342 = cat(_T_341, _T_339) @[lib.scala 202:69] + node _T_343 = cat(_T_342, _T_338) @[lib.scala 202:69] + node _T_344 = cat(_T_216[30], _T_216[29]) @[lib.scala 202:69] + node _T_345 = cat(_T_216[33], _T_216[32]) @[lib.scala 202:69] + node _T_346 = cat(_T_345, _T_216[31]) @[lib.scala 202:69] + node _T_347 = cat(_T_346, _T_344) @[lib.scala 202:69] + node _T_348 = cat(_T_216[35], _T_216[34]) @[lib.scala 202:69] + node _T_349 = cat(_T_216[38], _T_216[37]) @[lib.scala 202:69] + node _T_350 = cat(_T_349, _T_216[36]) @[lib.scala 202:69] + node _T_351 = cat(_T_350, _T_348) @[lib.scala 202:69] + node _T_352 = cat(_T_351, _T_347) @[lib.scala 202:69] + node _T_353 = cat(_T_352, _T_343) @[lib.scala 202:69] + node _T_354 = cat(_T_353, _T_334) @[lib.scala 202:69] + node _T_355 = xor(_T_354, _T_315) @[lib.scala 202:76] + node _T_356 = mux(_T_316, _T_355, _T_315) @[lib.scala 202:31] + node _T_357 = bits(_T_356, 37, 32) @[lib.scala 204:37] + node _T_358 = bits(_T_356, 30, 16) @[lib.scala 204:61] + node _T_359 = bits(_T_356, 14, 8) @[lib.scala 204:86] + node _T_360 = bits(_T_356, 6, 4) @[lib.scala 204:110] + node _T_361 = bits(_T_356, 2, 2) @[lib.scala 204:133] + node _T_362 = cat(_T_360, _T_361) @[Cat.scala 29:58] + node _T_363 = cat(_T_357, _T_358) @[Cat.scala 29:58] + node _T_364 = cat(_T_363, _T_359) @[Cat.scala 29:58] + node sec_data_hi_any = cat(_T_364, _T_362) @[Cat.scala 29:58] + node _T_365 = bits(_T_356, 38, 38) @[lib.scala 205:39] + node _T_366 = bits(_T_208, 6, 0) @[lib.scala 205:56] + node _T_367 = eq(_T_366, UInt<7>("h040")) @[lib.scala 205:62] + node _T_368 = xor(_T_365, _T_367) @[lib.scala 205:44] + node _T_369 = bits(_T_356, 31, 31) @[lib.scala 205:102] + node _T_370 = bits(_T_356, 15, 15) @[lib.scala 205:124] + node _T_371 = bits(_T_356, 7, 7) @[lib.scala 205:146] + node _T_372 = bits(_T_356, 3, 3) @[lib.scala 205:167] + node _T_373 = bits(_T_356, 1, 0) @[lib.scala 205:188] + node _T_374 = cat(_T_371, _T_372) @[Cat.scala 29:58] + node _T_375 = cat(_T_374, _T_373) @[Cat.scala 29:58] + node _T_376 = cat(_T_368, _T_369) @[Cat.scala 29:58] + node _T_377 = cat(_T_376, _T_370) @[Cat.scala 29:58] + node ecc_out_hi_nc = cat(_T_377, _T_375) @[Cat.scala 29:58] + wire _T_378 : UInt<1>[18] @[lib.scala 173:18] + wire _T_379 : UInt<1>[18] @[lib.scala 174:18] + wire _T_380 : UInt<1>[18] @[lib.scala 175:18] + wire _T_381 : UInt<1>[15] @[lib.scala 176:18] + wire _T_382 : UInt<1>[15] @[lib.scala 177:18] + wire _T_383 : UInt<1>[6] @[lib.scala 178:18] + node _T_384 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 185:36] + _T_378[0] <= _T_384 @[lib.scala 185:30] + node _T_385 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 186:36] + _T_379[0] <= _T_385 @[lib.scala 186:30] + node _T_386 = bits(dccm_rdata_lo_any, 1, 1) @[lib.scala 185:36] + _T_378[1] <= _T_386 @[lib.scala 185:30] + node _T_387 = bits(dccm_rdata_lo_any, 1, 1) @[lib.scala 187:36] + _T_380[0] <= _T_387 @[lib.scala 187:30] + node _T_388 = bits(dccm_rdata_lo_any, 2, 2) @[lib.scala 186:36] + _T_379[1] <= _T_388 @[lib.scala 186:30] + node _T_389 = bits(dccm_rdata_lo_any, 2, 2) @[lib.scala 187:36] + _T_380[1] <= _T_389 @[lib.scala 187:30] + node _T_390 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 185:36] + _T_378[2] <= _T_390 @[lib.scala 185:30] + node _T_391 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 186:36] + _T_379[2] <= _T_391 @[lib.scala 186:30] + node _T_392 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 187:36] + _T_380[2] <= _T_392 @[lib.scala 187:30] + node _T_393 = bits(dccm_rdata_lo_any, 4, 4) @[lib.scala 185:36] + _T_378[3] <= _T_393 @[lib.scala 185:30] + node _T_394 = bits(dccm_rdata_lo_any, 4, 4) @[lib.scala 188:36] + _T_381[0] <= _T_394 @[lib.scala 188:30] + node _T_395 = bits(dccm_rdata_lo_any, 5, 5) @[lib.scala 186:36] + _T_379[3] <= _T_395 @[lib.scala 186:30] + node _T_396 = bits(dccm_rdata_lo_any, 5, 5) @[lib.scala 188:36] + _T_381[1] <= _T_396 @[lib.scala 188:30] + node _T_397 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 185:36] + _T_378[4] <= _T_397 @[lib.scala 185:30] + node _T_398 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 186:36] + _T_379[4] <= _T_398 @[lib.scala 186:30] + node _T_399 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 188:36] + _T_381[2] <= _T_399 @[lib.scala 188:30] + node _T_400 = bits(dccm_rdata_lo_any, 7, 7) @[lib.scala 187:36] + _T_380[3] <= _T_400 @[lib.scala 187:30] + node _T_401 = bits(dccm_rdata_lo_any, 7, 7) @[lib.scala 188:36] + _T_381[3] <= _T_401 @[lib.scala 188:30] + node _T_402 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 185:36] + _T_378[5] <= _T_402 @[lib.scala 185:30] + node _T_403 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 187:36] + _T_380[4] <= _T_403 @[lib.scala 187:30] + node _T_404 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 188:36] + _T_381[4] <= _T_404 @[lib.scala 188:30] + node _T_405 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 186:36] + _T_379[5] <= _T_405 @[lib.scala 186:30] + node _T_406 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 187:36] + _T_380[5] <= _T_406 @[lib.scala 187:30] + node _T_407 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 188:36] + _T_381[5] <= _T_407 @[lib.scala 188:30] + node _T_408 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 185:36] + _T_378[6] <= _T_408 @[lib.scala 185:30] + node _T_409 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 186:36] + _T_379[6] <= _T_409 @[lib.scala 186:30] + node _T_410 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 187:36] + _T_380[6] <= _T_410 @[lib.scala 187:30] + node _T_411 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 188:36] + _T_381[6] <= _T_411 @[lib.scala 188:30] + node _T_412 = bits(dccm_rdata_lo_any, 11, 11) @[lib.scala 185:36] + _T_378[7] <= _T_412 @[lib.scala 185:30] + node _T_413 = bits(dccm_rdata_lo_any, 11, 11) @[lib.scala 189:36] + _T_382[0] <= _T_413 @[lib.scala 189:30] + node _T_414 = bits(dccm_rdata_lo_any, 12, 12) @[lib.scala 186:36] + _T_379[7] <= _T_414 @[lib.scala 186:30] + node _T_415 = bits(dccm_rdata_lo_any, 12, 12) @[lib.scala 189:36] + _T_382[1] <= _T_415 @[lib.scala 189:30] + node _T_416 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 185:36] + _T_378[8] <= _T_416 @[lib.scala 185:30] + node _T_417 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 186:36] + _T_379[8] <= _T_417 @[lib.scala 186:30] + node _T_418 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 189:36] + _T_382[2] <= _T_418 @[lib.scala 189:30] + node _T_419 = bits(dccm_rdata_lo_any, 14, 14) @[lib.scala 187:36] + _T_380[7] <= _T_419 @[lib.scala 187:30] + node _T_420 = bits(dccm_rdata_lo_any, 14, 14) @[lib.scala 189:36] + _T_382[3] <= _T_420 @[lib.scala 189:30] + node _T_421 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 185:36] + _T_378[9] <= _T_421 @[lib.scala 185:30] + node _T_422 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 187:36] + _T_380[8] <= _T_422 @[lib.scala 187:30] + node _T_423 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 189:36] + _T_382[4] <= _T_423 @[lib.scala 189:30] + node _T_424 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 186:36] + _T_379[9] <= _T_424 @[lib.scala 186:30] + node _T_425 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 187:36] + _T_380[9] <= _T_425 @[lib.scala 187:30] + node _T_426 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 189:36] + _T_382[5] <= _T_426 @[lib.scala 189:30] + node _T_427 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 185:36] + _T_378[10] <= _T_427 @[lib.scala 185:30] + node _T_428 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 186:36] + _T_379[10] <= _T_428 @[lib.scala 186:30] + node _T_429 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 187:36] + _T_380[10] <= _T_429 @[lib.scala 187:30] + node _T_430 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 189:36] + _T_382[6] <= _T_430 @[lib.scala 189:30] + node _T_431 = bits(dccm_rdata_lo_any, 18, 18) @[lib.scala 188:36] + _T_381[7] <= _T_431 @[lib.scala 188:30] + node _T_432 = bits(dccm_rdata_lo_any, 18, 18) @[lib.scala 189:36] + _T_382[7] <= _T_432 @[lib.scala 189:30] + node _T_433 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 185:36] + _T_378[11] <= _T_433 @[lib.scala 185:30] + node _T_434 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 188:36] + _T_381[8] <= _T_434 @[lib.scala 188:30] + node _T_435 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 189:36] + _T_382[8] <= _T_435 @[lib.scala 189:30] + node _T_436 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 186:36] + _T_379[11] <= _T_436 @[lib.scala 186:30] + node _T_437 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 188:36] + _T_381[9] <= _T_437 @[lib.scala 188:30] + node _T_438 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 189:36] + _T_382[9] <= _T_438 @[lib.scala 189:30] + node _T_439 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 185:36] + _T_378[12] <= _T_439 @[lib.scala 185:30] + node _T_440 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 186:36] + _T_379[12] <= _T_440 @[lib.scala 186:30] + node _T_441 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 188:36] + _T_381[10] <= _T_441 @[lib.scala 188:30] + node _T_442 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 189:36] + _T_382[10] <= _T_442 @[lib.scala 189:30] + node _T_443 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 187:36] + _T_380[11] <= _T_443 @[lib.scala 187:30] + node _T_444 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 188:36] + _T_381[11] <= _T_444 @[lib.scala 188:30] + node _T_445 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 189:36] + _T_382[11] <= _T_445 @[lib.scala 189:30] + node _T_446 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 185:36] + _T_378[13] <= _T_446 @[lib.scala 185:30] + node _T_447 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 187:36] + _T_380[12] <= _T_447 @[lib.scala 187:30] + node _T_448 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 188:36] + _T_381[12] <= _T_448 @[lib.scala 188:30] + node _T_449 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 189:36] + _T_382[12] <= _T_449 @[lib.scala 189:30] + node _T_450 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 186:36] + _T_379[13] <= _T_450 @[lib.scala 186:30] + node _T_451 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 187:36] + _T_380[13] <= _T_451 @[lib.scala 187:30] + node _T_452 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 188:36] + _T_381[13] <= _T_452 @[lib.scala 188:30] + node _T_453 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 189:36] + _T_382[13] <= _T_453 @[lib.scala 189:30] + node _T_454 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 185:36] + _T_378[14] <= _T_454 @[lib.scala 185:30] + node _T_455 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 186:36] + _T_379[14] <= _T_455 @[lib.scala 186:30] + node _T_456 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 187:36] + _T_380[14] <= _T_456 @[lib.scala 187:30] + node _T_457 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 188:36] + _T_381[14] <= _T_457 @[lib.scala 188:30] + node _T_458 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 189:36] + _T_382[14] <= _T_458 @[lib.scala 189:30] + node _T_459 = bits(dccm_rdata_lo_any, 26, 26) @[lib.scala 185:36] + _T_378[15] <= _T_459 @[lib.scala 185:30] + node _T_460 = bits(dccm_rdata_lo_any, 26, 26) @[lib.scala 190:36] + _T_383[0] <= _T_460 @[lib.scala 190:30] + node _T_461 = bits(dccm_rdata_lo_any, 27, 27) @[lib.scala 186:36] + _T_379[15] <= _T_461 @[lib.scala 186:30] + node _T_462 = bits(dccm_rdata_lo_any, 27, 27) @[lib.scala 190:36] + _T_383[1] <= _T_462 @[lib.scala 190:30] + node _T_463 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 185:36] + _T_378[16] <= _T_463 @[lib.scala 185:30] + node _T_464 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 186:36] + _T_379[16] <= _T_464 @[lib.scala 186:30] + node _T_465 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 190:36] + _T_383[2] <= _T_465 @[lib.scala 190:30] + node _T_466 = bits(dccm_rdata_lo_any, 29, 29) @[lib.scala 187:36] + _T_380[15] <= _T_466 @[lib.scala 187:30] + node _T_467 = bits(dccm_rdata_lo_any, 29, 29) @[lib.scala 190:36] + _T_383[3] <= _T_467 @[lib.scala 190:30] + node _T_468 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 185:36] + _T_378[17] <= _T_468 @[lib.scala 185:30] + node _T_469 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 187:36] + _T_380[16] <= _T_469 @[lib.scala 187:30] + node _T_470 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 190:36] + _T_383[4] <= _T_470 @[lib.scala 190:30] + node _T_471 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 186:36] + _T_379[17] <= _T_471 @[lib.scala 186:30] + node _T_472 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 187:36] + _T_380[17] <= _T_472 @[lib.scala 187:30] + node _T_473 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 190:36] + _T_383[5] <= _T_473 @[lib.scala 190:30] + node _T_474 = xorr(dccm_rdata_lo_any) @[lib.scala 193:30] + node _T_475 = xorr(dccm_data_ecc_lo_any) @[lib.scala 193:44] + node _T_476 = xor(_T_474, _T_475) @[lib.scala 193:35] + node _T_477 = not(UInt<1>("h00")) @[lib.scala 193:52] + node _T_478 = and(_T_476, _T_477) @[lib.scala 193:50] + node _T_479 = bits(dccm_data_ecc_lo_any, 5, 5) @[lib.scala 193:68] + node _T_480 = cat(_T_383[2], _T_383[1]) @[lib.scala 193:76] + node _T_481 = cat(_T_480, _T_383[0]) @[lib.scala 193:76] + node _T_482 = cat(_T_383[5], _T_383[4]) @[lib.scala 193:76] + node _T_483 = cat(_T_482, _T_383[3]) @[lib.scala 193:76] + node _T_484 = cat(_T_483, _T_481) @[lib.scala 193:76] + node _T_485 = xorr(_T_484) @[lib.scala 193:83] + node _T_486 = xor(_T_479, _T_485) @[lib.scala 193:71] + node _T_487 = bits(dccm_data_ecc_lo_any, 4, 4) @[lib.scala 193:95] + node _T_488 = cat(_T_382[2], _T_382[1]) @[lib.scala 193:103] + node _T_489 = cat(_T_488, _T_382[0]) @[lib.scala 193:103] + node _T_490 = cat(_T_382[4], _T_382[3]) @[lib.scala 193:103] + node _T_491 = cat(_T_382[6], _T_382[5]) @[lib.scala 193:103] + node _T_492 = cat(_T_491, _T_490) @[lib.scala 193:103] + node _T_493 = cat(_T_492, _T_489) @[lib.scala 193:103] + node _T_494 = cat(_T_382[8], _T_382[7]) @[lib.scala 193:103] + node _T_495 = cat(_T_382[10], _T_382[9]) @[lib.scala 193:103] + node _T_496 = cat(_T_495, _T_494) @[lib.scala 193:103] + node _T_497 = cat(_T_382[12], _T_382[11]) @[lib.scala 193:103] + node _T_498 = cat(_T_382[14], _T_382[13]) @[lib.scala 193:103] + node _T_499 = cat(_T_498, _T_497) @[lib.scala 193:103] + node _T_500 = cat(_T_499, _T_496) @[lib.scala 193:103] + node _T_501 = cat(_T_500, _T_493) @[lib.scala 193:103] + node _T_502 = xorr(_T_501) @[lib.scala 193:110] + node _T_503 = xor(_T_487, _T_502) @[lib.scala 193:98] + node _T_504 = bits(dccm_data_ecc_lo_any, 3, 3) @[lib.scala 193:122] + node _T_505 = cat(_T_381[2], _T_381[1]) @[lib.scala 193:130] + node _T_506 = cat(_T_505, _T_381[0]) @[lib.scala 193:130] + node _T_507 = cat(_T_381[4], _T_381[3]) @[lib.scala 193:130] + node _T_508 = cat(_T_381[6], _T_381[5]) @[lib.scala 193:130] + node _T_509 = cat(_T_508, _T_507) @[lib.scala 193:130] + node _T_510 = cat(_T_509, _T_506) @[lib.scala 193:130] + node _T_511 = cat(_T_381[8], _T_381[7]) @[lib.scala 193:130] + node _T_512 = cat(_T_381[10], _T_381[9]) @[lib.scala 193:130] + node _T_513 = cat(_T_512, _T_511) @[lib.scala 193:130] + node _T_514 = cat(_T_381[12], _T_381[11]) @[lib.scala 193:130] + node _T_515 = cat(_T_381[14], _T_381[13]) @[lib.scala 193:130] + node _T_516 = cat(_T_515, _T_514) @[lib.scala 193:130] + node _T_517 = cat(_T_516, _T_513) @[lib.scala 193:130] + node _T_518 = cat(_T_517, _T_510) @[lib.scala 193:130] + node _T_519 = xorr(_T_518) @[lib.scala 193:137] + node _T_520 = xor(_T_504, _T_519) @[lib.scala 193:125] + node _T_521 = bits(dccm_data_ecc_lo_any, 2, 2) @[lib.scala 193:149] + node _T_522 = cat(_T_380[1], _T_380[0]) @[lib.scala 193:157] + node _T_523 = cat(_T_380[3], _T_380[2]) @[lib.scala 193:157] + node _T_524 = cat(_T_523, _T_522) @[lib.scala 193:157] + node _T_525 = cat(_T_380[5], _T_380[4]) @[lib.scala 193:157] + node _T_526 = cat(_T_380[8], _T_380[7]) @[lib.scala 193:157] + node _T_527 = cat(_T_526, _T_380[6]) @[lib.scala 193:157] + node _T_528 = cat(_T_527, _T_525) @[lib.scala 193:157] + node _T_529 = cat(_T_528, _T_524) @[lib.scala 193:157] + node _T_530 = cat(_T_380[10], _T_380[9]) @[lib.scala 193:157] + node _T_531 = cat(_T_380[12], _T_380[11]) @[lib.scala 193:157] + node _T_532 = cat(_T_531, _T_530) @[lib.scala 193:157] + node _T_533 = cat(_T_380[14], _T_380[13]) @[lib.scala 193:157] + node _T_534 = cat(_T_380[17], _T_380[16]) @[lib.scala 193:157] + node _T_535 = cat(_T_534, _T_380[15]) @[lib.scala 193:157] + node _T_536 = cat(_T_535, _T_533) @[lib.scala 193:157] + node _T_537 = cat(_T_536, _T_532) @[lib.scala 193:157] + node _T_538 = cat(_T_537, _T_529) @[lib.scala 193:157] + node _T_539 = xorr(_T_538) @[lib.scala 193:164] + node _T_540 = xor(_T_521, _T_539) @[lib.scala 193:152] + node _T_541 = bits(dccm_data_ecc_lo_any, 1, 1) @[lib.scala 193:176] + node _T_542 = cat(_T_379[1], _T_379[0]) @[lib.scala 193:184] + node _T_543 = cat(_T_379[3], _T_379[2]) @[lib.scala 193:184] + node _T_544 = cat(_T_543, _T_542) @[lib.scala 193:184] + node _T_545 = cat(_T_379[5], _T_379[4]) @[lib.scala 193:184] + node _T_546 = cat(_T_379[8], _T_379[7]) @[lib.scala 193:184] + node _T_547 = cat(_T_546, _T_379[6]) @[lib.scala 193:184] + node _T_548 = cat(_T_547, _T_545) @[lib.scala 193:184] + node _T_549 = cat(_T_548, _T_544) @[lib.scala 193:184] + node _T_550 = cat(_T_379[10], _T_379[9]) @[lib.scala 193:184] + node _T_551 = cat(_T_379[12], _T_379[11]) @[lib.scala 193:184] + node _T_552 = cat(_T_551, _T_550) @[lib.scala 193:184] + node _T_553 = cat(_T_379[14], _T_379[13]) @[lib.scala 193:184] + node _T_554 = cat(_T_379[17], _T_379[16]) @[lib.scala 193:184] + node _T_555 = cat(_T_554, _T_379[15]) @[lib.scala 193:184] + node _T_556 = cat(_T_555, _T_553) @[lib.scala 193:184] + node _T_557 = cat(_T_556, _T_552) @[lib.scala 193:184] + node _T_558 = cat(_T_557, _T_549) @[lib.scala 193:184] + node _T_559 = xorr(_T_558) @[lib.scala 193:191] + node _T_560 = xor(_T_541, _T_559) @[lib.scala 193:179] + node _T_561 = bits(dccm_data_ecc_lo_any, 0, 0) @[lib.scala 193:203] + node _T_562 = cat(_T_378[1], _T_378[0]) @[lib.scala 193:211] + node _T_563 = cat(_T_378[3], _T_378[2]) @[lib.scala 193:211] + node _T_564 = cat(_T_563, _T_562) @[lib.scala 193:211] + node _T_565 = cat(_T_378[5], _T_378[4]) @[lib.scala 193:211] + node _T_566 = cat(_T_378[8], _T_378[7]) @[lib.scala 193:211] + node _T_567 = cat(_T_566, _T_378[6]) @[lib.scala 193:211] + node _T_568 = cat(_T_567, _T_565) @[lib.scala 193:211] + node _T_569 = cat(_T_568, _T_564) @[lib.scala 193:211] + node _T_570 = cat(_T_378[10], _T_378[9]) @[lib.scala 193:211] + node _T_571 = cat(_T_378[12], _T_378[11]) @[lib.scala 193:211] + node _T_572 = cat(_T_571, _T_570) @[lib.scala 193:211] + node _T_573 = cat(_T_378[14], _T_378[13]) @[lib.scala 193:211] + node _T_574 = cat(_T_378[17], _T_378[16]) @[lib.scala 193:211] + node _T_575 = cat(_T_574, _T_378[15]) @[lib.scala 193:211] + node _T_576 = cat(_T_575, _T_573) @[lib.scala 193:211] + node _T_577 = cat(_T_576, _T_572) @[lib.scala 193:211] + node _T_578 = cat(_T_577, _T_569) @[lib.scala 193:211] + node _T_579 = xorr(_T_578) @[lib.scala 193:218] + node _T_580 = xor(_T_561, _T_579) @[lib.scala 193:206] + node _T_581 = cat(_T_540, _T_560) @[Cat.scala 29:58] + node _T_582 = cat(_T_581, _T_580) @[Cat.scala 29:58] + node _T_583 = cat(_T_503, _T_520) @[Cat.scala 29:58] + node _T_584 = cat(_T_478, _T_486) @[Cat.scala 29:58] + node _T_585 = cat(_T_584, _T_583) @[Cat.scala 29:58] + node _T_586 = cat(_T_585, _T_582) @[Cat.scala 29:58] + node _T_587 = neq(_T_586, UInt<1>("h00")) @[lib.scala 194:44] + node _T_588 = and(is_ldst_lo_any, _T_587) @[lib.scala 194:32] + node _T_589 = bits(_T_586, 6, 6) @[lib.scala 194:64] + node single_ecc_error_lo_any = and(_T_588, _T_589) @[lib.scala 194:53] + node _T_590 = neq(_T_586, UInt<1>("h00")) @[lib.scala 195:44] + node _T_591 = and(is_ldst_lo_any, _T_590) @[lib.scala 195:32] + node _T_592 = bits(_T_586, 6, 6) @[lib.scala 195:65] + node _T_593 = not(_T_592) @[lib.scala 195:55] + node double_ecc_error_lo_any = and(_T_591, _T_593) @[lib.scala 195:53] + wire _T_594 : UInt<1>[39] @[lib.scala 196:26] + node _T_595 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_596 = eq(_T_595, UInt<1>("h01")) @[lib.scala 199:41] + _T_594[0] <= _T_596 @[lib.scala 199:23] + node _T_597 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_598 = eq(_T_597, UInt<2>("h02")) @[lib.scala 199:41] + _T_594[1] <= _T_598 @[lib.scala 199:23] + node _T_599 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_600 = eq(_T_599, UInt<2>("h03")) @[lib.scala 199:41] + _T_594[2] <= _T_600 @[lib.scala 199:23] + node _T_601 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_602 = eq(_T_601, UInt<3>("h04")) @[lib.scala 199:41] + _T_594[3] <= _T_602 @[lib.scala 199:23] + node _T_603 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_604 = eq(_T_603, UInt<3>("h05")) @[lib.scala 199:41] + _T_594[4] <= _T_604 @[lib.scala 199:23] + node _T_605 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_606 = eq(_T_605, UInt<3>("h06")) @[lib.scala 199:41] + _T_594[5] <= _T_606 @[lib.scala 199:23] + node _T_607 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_608 = eq(_T_607, UInt<3>("h07")) @[lib.scala 199:41] + _T_594[6] <= _T_608 @[lib.scala 199:23] + node _T_609 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_610 = eq(_T_609, UInt<4>("h08")) @[lib.scala 199:41] + _T_594[7] <= _T_610 @[lib.scala 199:23] + node _T_611 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_612 = eq(_T_611, UInt<4>("h09")) @[lib.scala 199:41] + _T_594[8] <= _T_612 @[lib.scala 199:23] + node _T_613 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_614 = eq(_T_613, UInt<4>("h0a")) @[lib.scala 199:41] + _T_594[9] <= _T_614 @[lib.scala 199:23] + node _T_615 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_616 = eq(_T_615, UInt<4>("h0b")) @[lib.scala 199:41] + _T_594[10] <= _T_616 @[lib.scala 199:23] + node _T_617 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_618 = eq(_T_617, UInt<4>("h0c")) @[lib.scala 199:41] + _T_594[11] <= _T_618 @[lib.scala 199:23] + node _T_619 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_620 = eq(_T_619, UInt<4>("h0d")) @[lib.scala 199:41] + _T_594[12] <= _T_620 @[lib.scala 199:23] + node _T_621 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_622 = eq(_T_621, UInt<4>("h0e")) @[lib.scala 199:41] + _T_594[13] <= _T_622 @[lib.scala 199:23] + node _T_623 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_624 = eq(_T_623, UInt<4>("h0f")) @[lib.scala 199:41] + _T_594[14] <= _T_624 @[lib.scala 199:23] + node _T_625 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_626 = eq(_T_625, UInt<5>("h010")) @[lib.scala 199:41] + _T_594[15] <= _T_626 @[lib.scala 199:23] + node _T_627 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_628 = eq(_T_627, UInt<5>("h011")) @[lib.scala 199:41] + _T_594[16] <= _T_628 @[lib.scala 199:23] + node _T_629 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_630 = eq(_T_629, UInt<5>("h012")) @[lib.scala 199:41] + _T_594[17] <= _T_630 @[lib.scala 199:23] + node _T_631 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_632 = eq(_T_631, UInt<5>("h013")) @[lib.scala 199:41] + _T_594[18] <= _T_632 @[lib.scala 199:23] + node _T_633 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_634 = eq(_T_633, UInt<5>("h014")) @[lib.scala 199:41] + _T_594[19] <= _T_634 @[lib.scala 199:23] + node _T_635 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_636 = eq(_T_635, UInt<5>("h015")) @[lib.scala 199:41] + _T_594[20] <= _T_636 @[lib.scala 199:23] + node _T_637 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_638 = eq(_T_637, UInt<5>("h016")) @[lib.scala 199:41] + _T_594[21] <= _T_638 @[lib.scala 199:23] + node _T_639 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_640 = eq(_T_639, UInt<5>("h017")) @[lib.scala 199:41] + _T_594[22] <= _T_640 @[lib.scala 199:23] + node _T_641 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_642 = eq(_T_641, UInt<5>("h018")) @[lib.scala 199:41] + _T_594[23] <= _T_642 @[lib.scala 199:23] + node _T_643 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_644 = eq(_T_643, UInt<5>("h019")) @[lib.scala 199:41] + _T_594[24] <= _T_644 @[lib.scala 199:23] + node _T_645 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_646 = eq(_T_645, UInt<5>("h01a")) @[lib.scala 199:41] + _T_594[25] <= _T_646 @[lib.scala 199:23] + node _T_647 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_648 = eq(_T_647, UInt<5>("h01b")) @[lib.scala 199:41] + _T_594[26] <= _T_648 @[lib.scala 199:23] + node _T_649 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_650 = eq(_T_649, UInt<5>("h01c")) @[lib.scala 199:41] + _T_594[27] <= _T_650 @[lib.scala 199:23] + node _T_651 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_652 = eq(_T_651, UInt<5>("h01d")) @[lib.scala 199:41] + _T_594[28] <= _T_652 @[lib.scala 199:23] + node _T_653 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_654 = eq(_T_653, UInt<5>("h01e")) @[lib.scala 199:41] + _T_594[29] <= _T_654 @[lib.scala 199:23] + node _T_655 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_656 = eq(_T_655, UInt<5>("h01f")) @[lib.scala 199:41] + _T_594[30] <= _T_656 @[lib.scala 199:23] + node _T_657 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_658 = eq(_T_657, UInt<6>("h020")) @[lib.scala 199:41] + _T_594[31] <= _T_658 @[lib.scala 199:23] + node _T_659 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_660 = eq(_T_659, UInt<6>("h021")) @[lib.scala 199:41] + _T_594[32] <= _T_660 @[lib.scala 199:23] + node _T_661 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_662 = eq(_T_661, UInt<6>("h022")) @[lib.scala 199:41] + _T_594[33] <= _T_662 @[lib.scala 199:23] + node _T_663 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_664 = eq(_T_663, UInt<6>("h023")) @[lib.scala 199:41] + _T_594[34] <= _T_664 @[lib.scala 199:23] + node _T_665 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_666 = eq(_T_665, UInt<6>("h024")) @[lib.scala 199:41] + _T_594[35] <= _T_666 @[lib.scala 199:23] + node _T_667 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_668 = eq(_T_667, UInt<6>("h025")) @[lib.scala 199:41] + _T_594[36] <= _T_668 @[lib.scala 199:23] + node _T_669 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_670 = eq(_T_669, UInt<6>("h026")) @[lib.scala 199:41] + _T_594[37] <= _T_670 @[lib.scala 199:23] + node _T_671 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_672 = eq(_T_671, UInt<6>("h027")) @[lib.scala 199:41] + _T_594[38] <= _T_672 @[lib.scala 199:23] + node _T_673 = bits(dccm_data_ecc_lo_any, 6, 6) @[lib.scala 201:37] + node _T_674 = bits(dccm_rdata_lo_any, 31, 26) @[lib.scala 201:45] + node _T_675 = bits(dccm_data_ecc_lo_any, 5, 5) @[lib.scala 201:60] + node _T_676 = bits(dccm_rdata_lo_any, 25, 11) @[lib.scala 201:68] + node _T_677 = bits(dccm_data_ecc_lo_any, 4, 4) @[lib.scala 201:83] + node _T_678 = bits(dccm_rdata_lo_any, 10, 4) @[lib.scala 201:91] + node _T_679 = bits(dccm_data_ecc_lo_any, 3, 3) @[lib.scala 201:105] + node _T_680 = bits(dccm_rdata_lo_any, 3, 1) @[lib.scala 201:113] + node _T_681 = bits(dccm_data_ecc_lo_any, 2, 2) @[lib.scala 201:126] + node _T_682 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 201:134] + node _T_683 = bits(dccm_data_ecc_lo_any, 1, 0) @[lib.scala 201:145] + node _T_684 = cat(_T_682, _T_683) @[Cat.scala 29:58] + node _T_685 = cat(_T_679, _T_680) @[Cat.scala 29:58] + node _T_686 = cat(_T_685, _T_681) @[Cat.scala 29:58] + node _T_687 = cat(_T_686, _T_684) @[Cat.scala 29:58] + node _T_688 = cat(_T_676, _T_677) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_678) @[Cat.scala 29:58] + node _T_690 = cat(_T_673, _T_674) @[Cat.scala 29:58] + node _T_691 = cat(_T_690, _T_675) @[Cat.scala 29:58] + node _T_692 = cat(_T_691, _T_689) @[Cat.scala 29:58] + node _T_693 = cat(_T_692, _T_687) @[Cat.scala 29:58] + node _T_694 = bits(single_ecc_error_lo_any, 0, 0) @[lib.scala 202:49] + node _T_695 = cat(_T_594[1], _T_594[0]) @[lib.scala 202:69] + node _T_696 = cat(_T_594[3], _T_594[2]) @[lib.scala 202:69] + node _T_697 = cat(_T_696, _T_695) @[lib.scala 202:69] + node _T_698 = cat(_T_594[5], _T_594[4]) @[lib.scala 202:69] + node _T_699 = cat(_T_594[8], _T_594[7]) @[lib.scala 202:69] + node _T_700 = cat(_T_699, _T_594[6]) @[lib.scala 202:69] + node _T_701 = cat(_T_700, _T_698) @[lib.scala 202:69] + node _T_702 = cat(_T_701, _T_697) @[lib.scala 202:69] + node _T_703 = cat(_T_594[10], _T_594[9]) @[lib.scala 202:69] + node _T_704 = cat(_T_594[13], _T_594[12]) @[lib.scala 202:69] + node _T_705 = cat(_T_704, _T_594[11]) @[lib.scala 202:69] + node _T_706 = cat(_T_705, _T_703) @[lib.scala 202:69] + node _T_707 = cat(_T_594[15], _T_594[14]) @[lib.scala 202:69] + node _T_708 = cat(_T_594[18], _T_594[17]) @[lib.scala 202:69] + node _T_709 = cat(_T_708, _T_594[16]) @[lib.scala 202:69] + node _T_710 = cat(_T_709, _T_707) @[lib.scala 202:69] + node _T_711 = cat(_T_710, _T_706) @[lib.scala 202:69] + node _T_712 = cat(_T_711, _T_702) @[lib.scala 202:69] + node _T_713 = cat(_T_594[20], _T_594[19]) @[lib.scala 202:69] + node _T_714 = cat(_T_594[23], _T_594[22]) @[lib.scala 202:69] + node _T_715 = cat(_T_714, _T_594[21]) @[lib.scala 202:69] + node _T_716 = cat(_T_715, _T_713) @[lib.scala 202:69] + node _T_717 = cat(_T_594[25], _T_594[24]) @[lib.scala 202:69] + node _T_718 = cat(_T_594[28], _T_594[27]) @[lib.scala 202:69] + node _T_719 = cat(_T_718, _T_594[26]) @[lib.scala 202:69] + node _T_720 = cat(_T_719, _T_717) @[lib.scala 202:69] + node _T_721 = cat(_T_720, _T_716) @[lib.scala 202:69] + node _T_722 = cat(_T_594[30], _T_594[29]) @[lib.scala 202:69] + node _T_723 = cat(_T_594[33], _T_594[32]) @[lib.scala 202:69] + node _T_724 = cat(_T_723, _T_594[31]) @[lib.scala 202:69] + node _T_725 = cat(_T_724, _T_722) @[lib.scala 202:69] + node _T_726 = cat(_T_594[35], _T_594[34]) @[lib.scala 202:69] + node _T_727 = cat(_T_594[38], _T_594[37]) @[lib.scala 202:69] + node _T_728 = cat(_T_727, _T_594[36]) @[lib.scala 202:69] + node _T_729 = cat(_T_728, _T_726) @[lib.scala 202:69] + node _T_730 = cat(_T_729, _T_725) @[lib.scala 202:69] + node _T_731 = cat(_T_730, _T_721) @[lib.scala 202:69] + node _T_732 = cat(_T_731, _T_712) @[lib.scala 202:69] + node _T_733 = xor(_T_732, _T_693) @[lib.scala 202:76] + node _T_734 = mux(_T_694, _T_733, _T_693) @[lib.scala 202:31] + node _T_735 = bits(_T_734, 37, 32) @[lib.scala 204:37] + node _T_736 = bits(_T_734, 30, 16) @[lib.scala 204:61] + node _T_737 = bits(_T_734, 14, 8) @[lib.scala 204:86] + node _T_738 = bits(_T_734, 6, 4) @[lib.scala 204:110] + node _T_739 = bits(_T_734, 2, 2) @[lib.scala 204:133] + node _T_740 = cat(_T_738, _T_739) @[Cat.scala 29:58] + node _T_741 = cat(_T_735, _T_736) @[Cat.scala 29:58] + node _T_742 = cat(_T_741, _T_737) @[Cat.scala 29:58] + node sec_data_lo_any = cat(_T_742, _T_740) @[Cat.scala 29:58] + node _T_743 = bits(_T_734, 38, 38) @[lib.scala 205:39] + node _T_744 = bits(_T_586, 6, 0) @[lib.scala 205:56] + node _T_745 = eq(_T_744, UInt<7>("h040")) @[lib.scala 205:62] + node _T_746 = xor(_T_743, _T_745) @[lib.scala 205:44] + node _T_747 = bits(_T_734, 31, 31) @[lib.scala 205:102] + node _T_748 = bits(_T_734, 15, 15) @[lib.scala 205:124] + node _T_749 = bits(_T_734, 7, 7) @[lib.scala 205:146] + node _T_750 = bits(_T_734, 3, 3) @[lib.scala 205:167] + node _T_751 = bits(_T_734, 1, 0) @[lib.scala 205:188] + node _T_752 = cat(_T_749, _T_750) @[Cat.scala 29:58] + node _T_753 = cat(_T_752, _T_751) @[Cat.scala 29:58] + node _T_754 = cat(_T_746, _T_747) @[Cat.scala 29:58] + node _T_755 = cat(_T_754, _T_748) @[Cat.scala 29:58] + node ecc_out_lo_nc = cat(_T_755, _T_753) @[Cat.scala 29:58] + node _T_756 = bits(dccm_wdata_lo_any, 0, 0) @[lib.scala 119:58] + node _T_757 = bits(dccm_wdata_lo_any, 1, 1) @[lib.scala 119:58] + node _T_758 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_759 = bits(dccm_wdata_lo_any, 4, 4) @[lib.scala 119:58] + node _T_760 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_761 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_762 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_763 = bits(dccm_wdata_lo_any, 11, 11) @[lib.scala 119:58] + node _T_764 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_765 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_766 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_767 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_768 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_769 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_770 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_771 = bits(dccm_wdata_lo_any, 26, 26) @[lib.scala 119:58] + node _T_772 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_773 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_774 = xor(_T_756, _T_757) @[lib.scala 119:74] + node _T_775 = xor(_T_774, _T_758) @[lib.scala 119:74] + node _T_776 = xor(_T_775, _T_759) @[lib.scala 119:74] + node _T_777 = xor(_T_776, _T_760) @[lib.scala 119:74] + node _T_778 = xor(_T_777, _T_761) @[lib.scala 119:74] + node _T_779 = xor(_T_778, _T_762) @[lib.scala 119:74] + node _T_780 = xor(_T_779, _T_763) @[lib.scala 119:74] + node _T_781 = xor(_T_780, _T_764) @[lib.scala 119:74] + node _T_782 = xor(_T_781, _T_765) @[lib.scala 119:74] + node _T_783 = xor(_T_782, _T_766) @[lib.scala 119:74] + node _T_784 = xor(_T_783, _T_767) @[lib.scala 119:74] + node _T_785 = xor(_T_784, _T_768) @[lib.scala 119:74] + node _T_786 = xor(_T_785, _T_769) @[lib.scala 119:74] + node _T_787 = xor(_T_786, _T_770) @[lib.scala 119:74] + node _T_788 = xor(_T_787, _T_771) @[lib.scala 119:74] + node _T_789 = xor(_T_788, _T_772) @[lib.scala 119:74] + node _T_790 = xor(_T_789, _T_773) @[lib.scala 119:74] + node _T_791 = bits(dccm_wdata_lo_any, 0, 0) @[lib.scala 119:58] + node _T_792 = bits(dccm_wdata_lo_any, 2, 2) @[lib.scala 119:58] + node _T_793 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_794 = bits(dccm_wdata_lo_any, 5, 5) @[lib.scala 119:58] + node _T_795 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_796 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_797 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_798 = bits(dccm_wdata_lo_any, 12, 12) @[lib.scala 119:58] + node _T_799 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_800 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_801 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_802 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_803 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_804 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_805 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_806 = bits(dccm_wdata_lo_any, 27, 27) @[lib.scala 119:58] + node _T_807 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_808 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_809 = xor(_T_791, _T_792) @[lib.scala 119:74] + node _T_810 = xor(_T_809, _T_793) @[lib.scala 119:74] + node _T_811 = xor(_T_810, _T_794) @[lib.scala 119:74] + node _T_812 = xor(_T_811, _T_795) @[lib.scala 119:74] + node _T_813 = xor(_T_812, _T_796) @[lib.scala 119:74] + node _T_814 = xor(_T_813, _T_797) @[lib.scala 119:74] + node _T_815 = xor(_T_814, _T_798) @[lib.scala 119:74] + node _T_816 = xor(_T_815, _T_799) @[lib.scala 119:74] + node _T_817 = xor(_T_816, _T_800) @[lib.scala 119:74] + node _T_818 = xor(_T_817, _T_801) @[lib.scala 119:74] + node _T_819 = xor(_T_818, _T_802) @[lib.scala 119:74] + node _T_820 = xor(_T_819, _T_803) @[lib.scala 119:74] + node _T_821 = xor(_T_820, _T_804) @[lib.scala 119:74] + node _T_822 = xor(_T_821, _T_805) @[lib.scala 119:74] + node _T_823 = xor(_T_822, _T_806) @[lib.scala 119:74] + node _T_824 = xor(_T_823, _T_807) @[lib.scala 119:74] + node _T_825 = xor(_T_824, _T_808) @[lib.scala 119:74] + node _T_826 = bits(dccm_wdata_lo_any, 1, 1) @[lib.scala 119:58] + node _T_827 = bits(dccm_wdata_lo_any, 2, 2) @[lib.scala 119:58] + node _T_828 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_829 = bits(dccm_wdata_lo_any, 7, 7) @[lib.scala 119:58] + node _T_830 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_831 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_832 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_833 = bits(dccm_wdata_lo_any, 14, 14) @[lib.scala 119:58] + node _T_834 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_835 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_836 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_837 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_838 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_839 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_840 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_841 = bits(dccm_wdata_lo_any, 29, 29) @[lib.scala 119:58] + node _T_842 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_843 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_844 = xor(_T_826, _T_827) @[lib.scala 119:74] + node _T_845 = xor(_T_844, _T_828) @[lib.scala 119:74] + node _T_846 = xor(_T_845, _T_829) @[lib.scala 119:74] + node _T_847 = xor(_T_846, _T_830) @[lib.scala 119:74] + node _T_848 = xor(_T_847, _T_831) @[lib.scala 119:74] + node _T_849 = xor(_T_848, _T_832) @[lib.scala 119:74] + node _T_850 = xor(_T_849, _T_833) @[lib.scala 119:74] + node _T_851 = xor(_T_850, _T_834) @[lib.scala 119:74] + node _T_852 = xor(_T_851, _T_835) @[lib.scala 119:74] + node _T_853 = xor(_T_852, _T_836) @[lib.scala 119:74] + node _T_854 = xor(_T_853, _T_837) @[lib.scala 119:74] + node _T_855 = xor(_T_854, _T_838) @[lib.scala 119:74] + node _T_856 = xor(_T_855, _T_839) @[lib.scala 119:74] + node _T_857 = xor(_T_856, _T_840) @[lib.scala 119:74] + node _T_858 = xor(_T_857, _T_841) @[lib.scala 119:74] + node _T_859 = xor(_T_858, _T_842) @[lib.scala 119:74] + node _T_860 = xor(_T_859, _T_843) @[lib.scala 119:74] + node _T_861 = bits(dccm_wdata_lo_any, 4, 4) @[lib.scala 119:58] + node _T_862 = bits(dccm_wdata_lo_any, 5, 5) @[lib.scala 119:58] + node _T_863 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_864 = bits(dccm_wdata_lo_any, 7, 7) @[lib.scala 119:58] + node _T_865 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_866 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_867 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_868 = bits(dccm_wdata_lo_any, 18, 18) @[lib.scala 119:58] + node _T_869 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_870 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_871 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_872 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_873 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_874 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_875 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_876 = xor(_T_861, _T_862) @[lib.scala 119:74] + node _T_877 = xor(_T_876, _T_863) @[lib.scala 119:74] + node _T_878 = xor(_T_877, _T_864) @[lib.scala 119:74] + node _T_879 = xor(_T_878, _T_865) @[lib.scala 119:74] + node _T_880 = xor(_T_879, _T_866) @[lib.scala 119:74] + node _T_881 = xor(_T_880, _T_867) @[lib.scala 119:74] + node _T_882 = xor(_T_881, _T_868) @[lib.scala 119:74] + node _T_883 = xor(_T_882, _T_869) @[lib.scala 119:74] + node _T_884 = xor(_T_883, _T_870) @[lib.scala 119:74] + node _T_885 = xor(_T_884, _T_871) @[lib.scala 119:74] + node _T_886 = xor(_T_885, _T_872) @[lib.scala 119:74] + node _T_887 = xor(_T_886, _T_873) @[lib.scala 119:74] + node _T_888 = xor(_T_887, _T_874) @[lib.scala 119:74] + node _T_889 = xor(_T_888, _T_875) @[lib.scala 119:74] + node _T_890 = bits(dccm_wdata_lo_any, 11, 11) @[lib.scala 119:58] + node _T_891 = bits(dccm_wdata_lo_any, 12, 12) @[lib.scala 119:58] + node _T_892 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_893 = bits(dccm_wdata_lo_any, 14, 14) @[lib.scala 119:58] + node _T_894 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_895 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_896 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_897 = bits(dccm_wdata_lo_any, 18, 18) @[lib.scala 119:58] + node _T_898 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_899 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_900 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_901 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_902 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_903 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_904 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_905 = xor(_T_890, _T_891) @[lib.scala 119:74] + node _T_906 = xor(_T_905, _T_892) @[lib.scala 119:74] + node _T_907 = xor(_T_906, _T_893) @[lib.scala 119:74] + node _T_908 = xor(_T_907, _T_894) @[lib.scala 119:74] + node _T_909 = xor(_T_908, _T_895) @[lib.scala 119:74] + node _T_910 = xor(_T_909, _T_896) @[lib.scala 119:74] + node _T_911 = xor(_T_910, _T_897) @[lib.scala 119:74] + node _T_912 = xor(_T_911, _T_898) @[lib.scala 119:74] + node _T_913 = xor(_T_912, _T_899) @[lib.scala 119:74] + node _T_914 = xor(_T_913, _T_900) @[lib.scala 119:74] + node _T_915 = xor(_T_914, _T_901) @[lib.scala 119:74] + node _T_916 = xor(_T_915, _T_902) @[lib.scala 119:74] + node _T_917 = xor(_T_916, _T_903) @[lib.scala 119:74] + node _T_918 = xor(_T_917, _T_904) @[lib.scala 119:74] + node _T_919 = bits(dccm_wdata_lo_any, 26, 26) @[lib.scala 119:58] + node _T_920 = bits(dccm_wdata_lo_any, 27, 27) @[lib.scala 119:58] + node _T_921 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_922 = bits(dccm_wdata_lo_any, 29, 29) @[lib.scala 119:58] + node _T_923 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_924 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_925 = xor(_T_919, _T_920) @[lib.scala 119:74] + node _T_926 = xor(_T_925, _T_921) @[lib.scala 119:74] + node _T_927 = xor(_T_926, _T_922) @[lib.scala 119:74] + node _T_928 = xor(_T_927, _T_923) @[lib.scala 119:74] + node _T_929 = xor(_T_928, _T_924) @[lib.scala 119:74] + node _T_930 = cat(_T_860, _T_825) @[Cat.scala 29:58] + node _T_931 = cat(_T_930, _T_790) @[Cat.scala 29:58] + node _T_932 = cat(_T_929, _T_918) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, _T_889) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] + node _T_935 = xorr(dccm_wdata_lo_any) @[lib.scala 127:13] + node _T_936 = xorr(_T_934) @[lib.scala 127:23] + node _T_937 = xor(_T_935, _T_936) @[lib.scala 127:18] + node dccm_wdata_ecc_lo_any = cat(_T_937, _T_934) @[Cat.scala 29:58] + node _T_938 = bits(dccm_wdata_hi_any, 0, 0) @[lib.scala 119:58] + node _T_939 = bits(dccm_wdata_hi_any, 1, 1) @[lib.scala 119:58] + node _T_940 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_941 = bits(dccm_wdata_hi_any, 4, 4) @[lib.scala 119:58] + node _T_942 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_943 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_944 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_945 = bits(dccm_wdata_hi_any, 11, 11) @[lib.scala 119:58] + node _T_946 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_947 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_948 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_949 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_950 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_951 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_952 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_953 = bits(dccm_wdata_hi_any, 26, 26) @[lib.scala 119:58] + node _T_954 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_955 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_956 = xor(_T_938, _T_939) @[lib.scala 119:74] + node _T_957 = xor(_T_956, _T_940) @[lib.scala 119:74] + node _T_958 = xor(_T_957, _T_941) @[lib.scala 119:74] + node _T_959 = xor(_T_958, _T_942) @[lib.scala 119:74] + node _T_960 = xor(_T_959, _T_943) @[lib.scala 119:74] + node _T_961 = xor(_T_960, _T_944) @[lib.scala 119:74] + node _T_962 = xor(_T_961, _T_945) @[lib.scala 119:74] + node _T_963 = xor(_T_962, _T_946) @[lib.scala 119:74] + node _T_964 = xor(_T_963, _T_947) @[lib.scala 119:74] + node _T_965 = xor(_T_964, _T_948) @[lib.scala 119:74] + node _T_966 = xor(_T_965, _T_949) @[lib.scala 119:74] + node _T_967 = xor(_T_966, _T_950) @[lib.scala 119:74] + node _T_968 = xor(_T_967, _T_951) @[lib.scala 119:74] + node _T_969 = xor(_T_968, _T_952) @[lib.scala 119:74] + node _T_970 = xor(_T_969, _T_953) @[lib.scala 119:74] + node _T_971 = xor(_T_970, _T_954) @[lib.scala 119:74] + node _T_972 = xor(_T_971, _T_955) @[lib.scala 119:74] + node _T_973 = bits(dccm_wdata_hi_any, 0, 0) @[lib.scala 119:58] + node _T_974 = bits(dccm_wdata_hi_any, 2, 2) @[lib.scala 119:58] + node _T_975 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_976 = bits(dccm_wdata_hi_any, 5, 5) @[lib.scala 119:58] + node _T_977 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_978 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_979 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_980 = bits(dccm_wdata_hi_any, 12, 12) @[lib.scala 119:58] + node _T_981 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_982 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_983 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_984 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_985 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_986 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_987 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_988 = bits(dccm_wdata_hi_any, 27, 27) @[lib.scala 119:58] + node _T_989 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_990 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_991 = xor(_T_973, _T_974) @[lib.scala 119:74] + node _T_992 = xor(_T_991, _T_975) @[lib.scala 119:74] + node _T_993 = xor(_T_992, _T_976) @[lib.scala 119:74] + node _T_994 = xor(_T_993, _T_977) @[lib.scala 119:74] + node _T_995 = xor(_T_994, _T_978) @[lib.scala 119:74] + node _T_996 = xor(_T_995, _T_979) @[lib.scala 119:74] + node _T_997 = xor(_T_996, _T_980) @[lib.scala 119:74] + node _T_998 = xor(_T_997, _T_981) @[lib.scala 119:74] + node _T_999 = xor(_T_998, _T_982) @[lib.scala 119:74] + node _T_1000 = xor(_T_999, _T_983) @[lib.scala 119:74] + node _T_1001 = xor(_T_1000, _T_984) @[lib.scala 119:74] + node _T_1002 = xor(_T_1001, _T_985) @[lib.scala 119:74] + node _T_1003 = xor(_T_1002, _T_986) @[lib.scala 119:74] + node _T_1004 = xor(_T_1003, _T_987) @[lib.scala 119:74] + node _T_1005 = xor(_T_1004, _T_988) @[lib.scala 119:74] + node _T_1006 = xor(_T_1005, _T_989) @[lib.scala 119:74] + node _T_1007 = xor(_T_1006, _T_990) @[lib.scala 119:74] + node _T_1008 = bits(dccm_wdata_hi_any, 1, 1) @[lib.scala 119:58] + node _T_1009 = bits(dccm_wdata_hi_any, 2, 2) @[lib.scala 119:58] + node _T_1010 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_1011 = bits(dccm_wdata_hi_any, 7, 7) @[lib.scala 119:58] + node _T_1012 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_1013 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_1014 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_1015 = bits(dccm_wdata_hi_any, 14, 14) @[lib.scala 119:58] + node _T_1016 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_1017 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_1018 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_1019 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1020 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1021 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1022 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1023 = bits(dccm_wdata_hi_any, 29, 29) @[lib.scala 119:58] + node _T_1024 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_1025 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_1026 = xor(_T_1008, _T_1009) @[lib.scala 119:74] + node _T_1027 = xor(_T_1026, _T_1010) @[lib.scala 119:74] + node _T_1028 = xor(_T_1027, _T_1011) @[lib.scala 119:74] + node _T_1029 = xor(_T_1028, _T_1012) @[lib.scala 119:74] + node _T_1030 = xor(_T_1029, _T_1013) @[lib.scala 119:74] + node _T_1031 = xor(_T_1030, _T_1014) @[lib.scala 119:74] + node _T_1032 = xor(_T_1031, _T_1015) @[lib.scala 119:74] + node _T_1033 = xor(_T_1032, _T_1016) @[lib.scala 119:74] + node _T_1034 = xor(_T_1033, _T_1017) @[lib.scala 119:74] + node _T_1035 = xor(_T_1034, _T_1018) @[lib.scala 119:74] + node _T_1036 = xor(_T_1035, _T_1019) @[lib.scala 119:74] + node _T_1037 = xor(_T_1036, _T_1020) @[lib.scala 119:74] + node _T_1038 = xor(_T_1037, _T_1021) @[lib.scala 119:74] + node _T_1039 = xor(_T_1038, _T_1022) @[lib.scala 119:74] + node _T_1040 = xor(_T_1039, _T_1023) @[lib.scala 119:74] + node _T_1041 = xor(_T_1040, _T_1024) @[lib.scala 119:74] + node _T_1042 = xor(_T_1041, _T_1025) @[lib.scala 119:74] + node _T_1043 = bits(dccm_wdata_hi_any, 4, 4) @[lib.scala 119:58] + node _T_1044 = bits(dccm_wdata_hi_any, 5, 5) @[lib.scala 119:58] + node _T_1045 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_1046 = bits(dccm_wdata_hi_any, 7, 7) @[lib.scala 119:58] + node _T_1047 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_1048 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_1049 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_1050 = bits(dccm_wdata_hi_any, 18, 18) @[lib.scala 119:58] + node _T_1051 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_1052 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_1053 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_1054 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1055 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1056 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1057 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1058 = xor(_T_1043, _T_1044) @[lib.scala 119:74] + node _T_1059 = xor(_T_1058, _T_1045) @[lib.scala 119:74] + node _T_1060 = xor(_T_1059, _T_1046) @[lib.scala 119:74] + node _T_1061 = xor(_T_1060, _T_1047) @[lib.scala 119:74] + node _T_1062 = xor(_T_1061, _T_1048) @[lib.scala 119:74] + node _T_1063 = xor(_T_1062, _T_1049) @[lib.scala 119:74] + node _T_1064 = xor(_T_1063, _T_1050) @[lib.scala 119:74] + node _T_1065 = xor(_T_1064, _T_1051) @[lib.scala 119:74] + node _T_1066 = xor(_T_1065, _T_1052) @[lib.scala 119:74] + node _T_1067 = xor(_T_1066, _T_1053) @[lib.scala 119:74] + node _T_1068 = xor(_T_1067, _T_1054) @[lib.scala 119:74] + node _T_1069 = xor(_T_1068, _T_1055) @[lib.scala 119:74] + node _T_1070 = xor(_T_1069, _T_1056) @[lib.scala 119:74] + node _T_1071 = xor(_T_1070, _T_1057) @[lib.scala 119:74] + node _T_1072 = bits(dccm_wdata_hi_any, 11, 11) @[lib.scala 119:58] + node _T_1073 = bits(dccm_wdata_hi_any, 12, 12) @[lib.scala 119:58] + node _T_1074 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_1075 = bits(dccm_wdata_hi_any, 14, 14) @[lib.scala 119:58] + node _T_1076 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_1077 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_1078 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_1079 = bits(dccm_wdata_hi_any, 18, 18) @[lib.scala 119:58] + node _T_1080 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_1081 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_1082 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_1083 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1084 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1085 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1086 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1087 = xor(_T_1072, _T_1073) @[lib.scala 119:74] + node _T_1088 = xor(_T_1087, _T_1074) @[lib.scala 119:74] + node _T_1089 = xor(_T_1088, _T_1075) @[lib.scala 119:74] + node _T_1090 = xor(_T_1089, _T_1076) @[lib.scala 119:74] + node _T_1091 = xor(_T_1090, _T_1077) @[lib.scala 119:74] + node _T_1092 = xor(_T_1091, _T_1078) @[lib.scala 119:74] + node _T_1093 = xor(_T_1092, _T_1079) @[lib.scala 119:74] + node _T_1094 = xor(_T_1093, _T_1080) @[lib.scala 119:74] + node _T_1095 = xor(_T_1094, _T_1081) @[lib.scala 119:74] + node _T_1096 = xor(_T_1095, _T_1082) @[lib.scala 119:74] + node _T_1097 = xor(_T_1096, _T_1083) @[lib.scala 119:74] + node _T_1098 = xor(_T_1097, _T_1084) @[lib.scala 119:74] + node _T_1099 = xor(_T_1098, _T_1085) @[lib.scala 119:74] + node _T_1100 = xor(_T_1099, _T_1086) @[lib.scala 119:74] + node _T_1101 = bits(dccm_wdata_hi_any, 26, 26) @[lib.scala 119:58] + node _T_1102 = bits(dccm_wdata_hi_any, 27, 27) @[lib.scala 119:58] + node _T_1103 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_1104 = bits(dccm_wdata_hi_any, 29, 29) @[lib.scala 119:58] + node _T_1105 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_1106 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_1107 = xor(_T_1101, _T_1102) @[lib.scala 119:74] + node _T_1108 = xor(_T_1107, _T_1103) @[lib.scala 119:74] + node _T_1109 = xor(_T_1108, _T_1104) @[lib.scala 119:74] + node _T_1110 = xor(_T_1109, _T_1105) @[lib.scala 119:74] + node _T_1111 = xor(_T_1110, _T_1106) @[lib.scala 119:74] + node _T_1112 = cat(_T_1042, _T_1007) @[Cat.scala 29:58] + node _T_1113 = cat(_T_1112, _T_972) @[Cat.scala 29:58] + node _T_1114 = cat(_T_1111, _T_1100) @[Cat.scala 29:58] + node _T_1115 = cat(_T_1114, _T_1071) @[Cat.scala 29:58] + node _T_1116 = cat(_T_1115, _T_1113) @[Cat.scala 29:58] + node _T_1117 = xorr(dccm_wdata_hi_any) @[lib.scala 127:13] + node _T_1118 = xorr(_T_1116) @[lib.scala 127:23] + node _T_1119 = xor(_T_1117, _T_1118) @[lib.scala 127:18] + node dccm_wdata_ecc_hi_any = cat(_T_1119, _T_1116) @[Cat.scala 29:58] + when UInt<1>("h00") : @[lsu_ecc.scala 102:30] + node _T_1120 = bits(io.lsu_addr_r, 2, 2) @[lsu_ecc.scala 103:33] + node _T_1121 = bits(io.end_addr_r, 2, 2) @[lsu_ecc.scala 103:54] + node _T_1122 = neq(_T_1120, _T_1121) @[lsu_ecc.scala 103:37] + ldst_dual_r <= _T_1122 @[lsu_ecc.scala 103:17] + node _T_1123 = or(io.lsu_pkt_r.bits.load, io.lsu_pkt_r.bits.store) @[lsu_ecc.scala 104:63] + node _T_1124 = and(io.lsu_pkt_r.valid, _T_1123) @[lsu_ecc.scala 104:37] + node _T_1125 = and(_T_1124, io.addr_in_dccm_r) @[lsu_ecc.scala 104:90] + node _T_1126 = and(_T_1125, io.lsu_dccm_rden_r) @[lsu_ecc.scala 104:110] + is_ldst_r <= _T_1126 @[lsu_ecc.scala 104:15] + node _T_1127 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 105:33] + node _T_1128 = and(is_ldst_r, _T_1127) @[lsu_ecc.scala 105:31] + is_ldst_lo_r <= _T_1128 @[lsu_ecc.scala 105:18] + node _T_1129 = and(is_ldst_r, ldst_dual_r) @[lsu_ecc.scala 106:31] + node _T_1130 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 106:48] + node _T_1131 = and(_T_1129, _T_1130) @[lsu_ecc.scala 106:46] + is_ldst_hi_r <= _T_1131 @[lsu_ecc.scala 106:18] + is_ldst_hi_any <= is_ldst_hi_r @[lsu_ecc.scala 107:21] + dccm_rdata_hi_any <= io.dccm_rdata_hi_r @[lsu_ecc.scala 108:24] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_r @[lsu_ecc.scala 109:26] + is_ldst_lo_any <= is_ldst_lo_r @[lsu_ecc.scala 110:20] + dccm_rdata_lo_any <= io.dccm_rdata_lo_r @[lsu_ecc.scala 111:25] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_r @[lsu_ecc.scala 112:26] + io.sec_data_hi_r <= sec_data_hi_any @[lsu_ecc.scala 113:22] + io.single_ecc_error_hi_r <= single_ecc_error_hi_any @[lsu_ecc.scala 114:31] + double_ecc_error_hi_r <= double_ecc_error_hi_any @[lsu_ecc.scala 115:28] + io.sec_data_lo_r <= sec_data_lo_any @[lsu_ecc.scala 116:25] + io.single_ecc_error_lo_r <= single_ecc_error_lo_any @[lsu_ecc.scala 117:31] + double_ecc_error_lo_r <= double_ecc_error_lo_any @[lsu_ecc.scala 118:28] + node _T_1132 = or(io.single_ecc_error_hi_r, io.single_ecc_error_lo_r) @[lsu_ecc.scala 119:59] + io.lsu_single_ecc_error_r <= _T_1132 @[lsu_ecc.scala 119:31] + node _T_1133 = or(double_ecc_error_hi_r, double_ecc_error_lo_r) @[lsu_ecc.scala 120:56] + io.lsu_double_ecc_error_r <= _T_1133 @[lsu_ecc.scala 120:31] + skip @[lsu_ecc.scala 102:30] + else : @[lsu_ecc.scala 122:16] + node _T_1134 = bits(io.lsu_addr_m, 2, 2) @[lsu_ecc.scala 123:35] + node _T_1135 = bits(io.end_addr_m, 2, 2) @[lsu_ecc.scala 123:56] + node _T_1136 = neq(_T_1134, _T_1135) @[lsu_ecc.scala 123:39] + ldst_dual_m <= _T_1136 @[lsu_ecc.scala 123:19] + node _T_1137 = or(io.lsu_pkt_m.bits.load, io.lsu_pkt_m.bits.store) @[lsu_ecc.scala 124:65] + node _T_1138 = and(io.lsu_pkt_m.valid, _T_1137) @[lsu_ecc.scala 124:39] + node _T_1139 = and(_T_1138, io.addr_in_dccm_m) @[lsu_ecc.scala 124:92] + node _T_1140 = and(_T_1139, io.lsu_dccm_rden_m) @[lsu_ecc.scala 124:112] + is_ldst_m <= _T_1140 @[lsu_ecc.scala 124:17] + node _T_1141 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 125:35] + node _T_1142 = and(is_ldst_m, _T_1141) @[lsu_ecc.scala 125:33] + is_ldst_lo_m <= _T_1142 @[lsu_ecc.scala 125:20] + node _T_1143 = or(ldst_dual_m, io.lsu_pkt_m.bits.dma) @[lsu_ecc.scala 126:48] + node _T_1144 = and(is_ldst_m, _T_1143) @[lsu_ecc.scala 126:33] + node _T_1145 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 126:75] + node _T_1146 = and(_T_1144, _T_1145) @[lsu_ecc.scala 126:73] + is_ldst_hi_m <= _T_1146 @[lsu_ecc.scala 126:20] + is_ldst_hi_any <= is_ldst_hi_m @[lsu_ecc.scala 127:23] + dccm_rdata_hi_any <= io.dccm_rdata_hi_m @[lsu_ecc.scala 128:26] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_m @[lsu_ecc.scala 129:28] + is_ldst_lo_any <= is_ldst_lo_m @[lsu_ecc.scala 130:22] + dccm_rdata_lo_any <= io.dccm_rdata_lo_m @[lsu_ecc.scala 131:27] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_m @[lsu_ecc.scala 132:28] + io.sec_data_hi_m <= sec_data_hi_any @[lsu_ecc.scala 133:27] + double_ecc_error_hi_m <= double_ecc_error_hi_any @[lsu_ecc.scala 134:30] + io.sec_data_lo_m <= sec_data_lo_any @[lsu_ecc.scala 135:27] + double_ecc_error_lo_m <= double_ecc_error_lo_any @[lsu_ecc.scala 136:30] + node _T_1147 = or(single_ecc_error_hi_any, single_ecc_error_lo_any) @[lsu_ecc.scala 137:60] + io.lsu_single_ecc_error_m <= _T_1147 @[lsu_ecc.scala 137:33] + node _T_1148 = or(double_ecc_error_hi_m, double_ecc_error_lo_m) @[lsu_ecc.scala 138:58] + io.lsu_double_ecc_error_m <= _T_1148 @[lsu_ecc.scala 138:33] + reg _T_1149 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 140:72] + _T_1149 <= io.lsu_single_ecc_error_m @[lsu_ecc.scala 140:72] + io.lsu_single_ecc_error_r <= _T_1149 @[lsu_ecc.scala 140:62] + reg _T_1150 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 141:72] + _T_1150 <= io.lsu_double_ecc_error_m @[lsu_ecc.scala 141:72] + io.lsu_double_ecc_error_r <= _T_1150 @[lsu_ecc.scala 141:62] + reg _T_1151 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 142:72] + _T_1151 <= single_ecc_error_lo_any @[lsu_ecc.scala 142:72] + io.single_ecc_error_lo_r <= _T_1151 @[lsu_ecc.scala 142:62] + reg _T_1152 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 143:72] + _T_1152 <= single_ecc_error_hi_any @[lsu_ecc.scala 143:72] + io.single_ecc_error_hi_r <= _T_1152 @[lsu_ecc.scala 143:62] + node _T_1153 = or(io.lsu_single_ecc_error_m, io.clk_override) @[lsu_ecc.scala 144:87] + inst rvclkhdr of rvclkhdr_16 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_1153 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1154 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1153 : @[Reg.scala 28:19] + _T_1154 <= io.sec_data_hi_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.sec_data_hi_r <= _T_1154 @[lsu_ecc.scala 144:34] + node _T_1155 = or(io.lsu_single_ecc_error_m, io.clk_override) @[lsu_ecc.scala 145:87] + inst rvclkhdr_1 of rvclkhdr_17 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_1155 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1156 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1155 : @[Reg.scala 28:19] + _T_1156 <= io.sec_data_lo_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.sec_data_lo_r <= _T_1156 @[lsu_ecc.scala 145:34] + skip @[lsu_ecc.scala 122:16] + node _T_1157 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 148:56] + node _T_1158 = bits(io.dma_dccm_wen, 0, 0) @[lsu_ecc.scala 148:104] + node _T_1159 = mux(_T_1158, io.dma_dccm_wdata_lo, io.stbuf_data_any) @[lsu_ecc.scala 148:87] + node _T_1160 = mux(_T_1157, io.sec_data_lo_r_ff, _T_1159) @[lsu_ecc.scala 148:27] + dccm_wdata_lo_any <= _T_1160 @[lsu_ecc.scala 148:21] + node _T_1161 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 149:56] + node _T_1162 = bits(io.dma_dccm_wen, 0, 0) @[lsu_ecc.scala 149:104] + node _T_1163 = mux(_T_1162, io.dma_dccm_wdata_hi, UInt<1>("h00")) @[lsu_ecc.scala 149:87] + node _T_1164 = mux(_T_1161, io.sec_data_hi_r_ff, _T_1163) @[lsu_ecc.scala 149:27] + dccm_wdata_hi_any <= _T_1164 @[lsu_ecc.scala 149:21] + io.sec_data_ecc_hi_r_ff <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 150:28] + io.sec_data_ecc_lo_r_ff <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 151:28] + io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 152:28] + io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 153:28] + io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 154:28] + node _T_1165 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_ecc.scala 156:75] + inst rvclkhdr_2 of rvclkhdr_18 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_1165 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1165 : @[Reg.scala 28:19] + _T_1166 <= io.sec_data_hi_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.sec_data_hi_r_ff <= _T_1166 @[lsu_ecc.scala 156:23] + node _T_1167 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_ecc.scala 157:75] + inst rvclkhdr_3 of rvclkhdr_19 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_1167 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1167 : @[Reg.scala 28:19] + _T_1168 <= io.sec_data_lo_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.sec_data_lo_r_ff <= _T_1168 @[lsu_ecc.scala 157:23] + + module lsu_trigger : + input clock : Clock + input reset : AsyncReset + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} + + wire trigger_enable : UInt<1> + trigger_enable <= UInt<1>("h00") + node _T = or(io.trigger_pkt_any[0].m, io.trigger_pkt_any[1].m) @[lsu_trigger.scala 16:73] + node _T_1 = or(_T, io.trigger_pkt_any[2].m) @[lsu_trigger.scala 16:73] + node _T_2 = or(_T_1, io.trigger_pkt_any[3].m) @[lsu_trigger.scala 16:73] + trigger_enable <= _T_2 @[lsu_trigger.scala 16:18] + node _T_3 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_5 = bits(io.store_data_m, 31, 16) @[lsu_trigger.scala 17:83] + node _T_6 = and(_T_4, _T_5) @[lsu_trigger.scala 17:66] + node _T_7 = or(io.lsu_pkt_m.bits.half, io.lsu_pkt_m.bits.word) @[lsu_trigger.scala 17:124] + node _T_8 = bits(_T_7, 0, 0) @[Bitwise.scala 72:15] + node _T_9 = mux(_T_8, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_10 = bits(io.store_data_m, 15, 8) @[lsu_trigger.scala 17:168] + node _T_11 = and(_T_9, _T_10) @[lsu_trigger.scala 17:151] + node _T_12 = bits(io.store_data_m, 7, 0) @[lsu_trigger.scala 17:192] + node _T_13 = cat(_T_6, _T_11) @[Cat.scala 29:58] + node store_data_trigger_m = cat(_T_13, _T_12) @[Cat.scala 29:58] + node _T_14 = bits(trigger_enable, 0, 0) @[Bitwise.scala 72:15] + node _T_15 = mux(_T_14, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node ldst_addr_trigger_m = and(io.lsu_addr_m, _T_15) @[lsu_trigger.scala 18:43] + node _T_16 = bits(io.trigger_pkt_any[0].select, 0, 0) @[lsu_trigger.scala 19:83] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[lsu_trigger.scala 19:53] + node _T_18 = and(io.trigger_pkt_any[0].select, io.trigger_pkt_any[0].store) @[lsu_trigger.scala 19:143] + node _T_19 = bits(_T_18, 0, 0) @[lsu_trigger.scala 19:174] + node _T_20 = mux(_T_17, ldst_addr_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = mux(_T_19, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72] + wire lsu_match_data_0 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_0 <= _T_22 @[Mux.scala 27:72] + node _T_23 = bits(io.trigger_pkt_any[1].select, 0, 0) @[lsu_trigger.scala 19:83] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[lsu_trigger.scala 19:53] + node _T_25 = and(io.trigger_pkt_any[1].select, io.trigger_pkt_any[1].store) @[lsu_trigger.scala 19:143] + node _T_26 = bits(_T_25, 0, 0) @[lsu_trigger.scala 19:174] + node _T_27 = mux(_T_24, ldst_addr_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_28 = mux(_T_26, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_29 = or(_T_27, _T_28) @[Mux.scala 27:72] + wire lsu_match_data_1 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_1 <= _T_29 @[Mux.scala 27:72] + node _T_30 = bits(io.trigger_pkt_any[2].select, 0, 0) @[lsu_trigger.scala 19:83] + node _T_31 = eq(_T_30, UInt<1>("h00")) @[lsu_trigger.scala 19:53] + node _T_32 = and(io.trigger_pkt_any[2].select, io.trigger_pkt_any[2].store) @[lsu_trigger.scala 19:143] + node _T_33 = bits(_T_32, 0, 0) @[lsu_trigger.scala 19:174] + node _T_34 = mux(_T_31, ldst_addr_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_35 = mux(_T_33, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_36 = or(_T_34, _T_35) @[Mux.scala 27:72] + wire lsu_match_data_2 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_2 <= _T_36 @[Mux.scala 27:72] + node _T_37 = bits(io.trigger_pkt_any[3].select, 0, 0) @[lsu_trigger.scala 19:83] + node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_trigger.scala 19:53] + node _T_39 = and(io.trigger_pkt_any[3].select, io.trigger_pkt_any[3].store) @[lsu_trigger.scala 19:143] + node _T_40 = bits(_T_39, 0, 0) @[lsu_trigger.scala 19:174] + node _T_41 = mux(_T_38, ldst_addr_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_42 = mux(_T_40, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_43 = or(_T_41, _T_42) @[Mux.scala 27:72] + wire lsu_match_data_3 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_3 <= _T_43 @[Mux.scala 27:72] + node _T_44 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 20:70] + node _T_45 = and(io.lsu_pkt_m.valid, _T_44) @[lsu_trigger.scala 20:68] + node _T_46 = and(_T_45, trigger_enable) @[lsu_trigger.scala 20:93] + node _T_47 = and(io.trigger_pkt_any[0].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 20:142] + node _T_48 = and(io.trigger_pkt_any[0].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 21:33] + node _T_49 = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[lsu_trigger.scala 21:60] + node _T_50 = and(_T_48, _T_49) @[lsu_trigger.scala 21:58] + node _T_51 = or(_T_47, _T_50) @[lsu_trigger.scala 20:168] + node _T_52 = and(_T_46, _T_51) @[lsu_trigger.scala 20:110] + node _T_53 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[lsu_trigger.scala 22:107] + wire _T_54 : UInt<1>[32] @[lib.scala 100:24] + node _T_55 = andr(io.trigger_pkt_any[0].tdata2) @[lib.scala 101:45] + node _T_56 = not(_T_55) @[lib.scala 101:39] + node _T_57 = and(_T_53, _T_56) @[lib.scala 101:37] + node _T_58 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 102:48] + node _T_59 = bits(lsu_match_data_0, 0, 0) @[lib.scala 102:60] + node _T_60 = eq(_T_58, _T_59) @[lib.scala 102:52] + node _T_61 = or(_T_57, _T_60) @[lib.scala 102:41] + _T_54[0] <= _T_61 @[lib.scala 102:18] + node _T_62 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 104:28] + node _T_63 = andr(_T_62) @[lib.scala 104:36] + node _T_64 = and(_T_63, _T_57) @[lib.scala 104:41] + node _T_65 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[lib.scala 104:74] + node _T_66 = bits(lsu_match_data_0, 1, 1) @[lib.scala 104:86] + node _T_67 = eq(_T_65, _T_66) @[lib.scala 104:78] + node _T_68 = mux(_T_64, UInt<1>("h01"), _T_67) @[lib.scala 104:23] + _T_54[1] <= _T_68 @[lib.scala 104:17] + node _T_69 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[lib.scala 104:28] + node _T_70 = andr(_T_69) @[lib.scala 104:36] + node _T_71 = and(_T_70, _T_57) @[lib.scala 104:41] + node _T_72 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[lib.scala 104:74] + node _T_73 = bits(lsu_match_data_0, 2, 2) @[lib.scala 104:86] + node _T_74 = eq(_T_72, _T_73) @[lib.scala 104:78] + node _T_75 = mux(_T_71, UInt<1>("h01"), _T_74) @[lib.scala 104:23] + _T_54[2] <= _T_75 @[lib.scala 104:17] + node _T_76 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[lib.scala 104:28] + node _T_77 = andr(_T_76) @[lib.scala 104:36] + node _T_78 = and(_T_77, _T_57) @[lib.scala 104:41] + node _T_79 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[lib.scala 104:74] + node _T_80 = bits(lsu_match_data_0, 3, 3) @[lib.scala 104:86] + node _T_81 = eq(_T_79, _T_80) @[lib.scala 104:78] + node _T_82 = mux(_T_78, UInt<1>("h01"), _T_81) @[lib.scala 104:23] + _T_54[3] <= _T_82 @[lib.scala 104:17] + node _T_83 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[lib.scala 104:28] + node _T_84 = andr(_T_83) @[lib.scala 104:36] + node _T_85 = and(_T_84, _T_57) @[lib.scala 104:41] + node _T_86 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[lib.scala 104:74] + node _T_87 = bits(lsu_match_data_0, 4, 4) @[lib.scala 104:86] + node _T_88 = eq(_T_86, _T_87) @[lib.scala 104:78] + node _T_89 = mux(_T_85, UInt<1>("h01"), _T_88) @[lib.scala 104:23] + _T_54[4] <= _T_89 @[lib.scala 104:17] + node _T_90 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[lib.scala 104:28] + node _T_91 = andr(_T_90) @[lib.scala 104:36] + node _T_92 = and(_T_91, _T_57) @[lib.scala 104:41] + node _T_93 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[lib.scala 104:74] + node _T_94 = bits(lsu_match_data_0, 5, 5) @[lib.scala 104:86] + node _T_95 = eq(_T_93, _T_94) @[lib.scala 104:78] + node _T_96 = mux(_T_92, UInt<1>("h01"), _T_95) @[lib.scala 104:23] + _T_54[5] <= _T_96 @[lib.scala 104:17] + node _T_97 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[lib.scala 104:28] + node _T_98 = andr(_T_97) @[lib.scala 104:36] + node _T_99 = and(_T_98, _T_57) @[lib.scala 104:41] + node _T_100 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[lib.scala 104:74] + node _T_101 = bits(lsu_match_data_0, 6, 6) @[lib.scala 104:86] + node _T_102 = eq(_T_100, _T_101) @[lib.scala 104:78] + node _T_103 = mux(_T_99, UInt<1>("h01"), _T_102) @[lib.scala 104:23] + _T_54[6] <= _T_103 @[lib.scala 104:17] + node _T_104 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[lib.scala 104:28] + node _T_105 = andr(_T_104) @[lib.scala 104:36] + node _T_106 = and(_T_105, _T_57) @[lib.scala 104:41] + node _T_107 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[lib.scala 104:74] + node _T_108 = bits(lsu_match_data_0, 7, 7) @[lib.scala 104:86] + node _T_109 = eq(_T_107, _T_108) @[lib.scala 104:78] + node _T_110 = mux(_T_106, UInt<1>("h01"), _T_109) @[lib.scala 104:23] + _T_54[7] <= _T_110 @[lib.scala 104:17] + node _T_111 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[lib.scala 104:28] + node _T_112 = andr(_T_111) @[lib.scala 104:36] + node _T_113 = and(_T_112, _T_57) @[lib.scala 104:41] + node _T_114 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[lib.scala 104:74] + node _T_115 = bits(lsu_match_data_0, 8, 8) @[lib.scala 104:86] + node _T_116 = eq(_T_114, _T_115) @[lib.scala 104:78] + node _T_117 = mux(_T_113, UInt<1>("h01"), _T_116) @[lib.scala 104:23] + _T_54[8] <= _T_117 @[lib.scala 104:17] + node _T_118 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[lib.scala 104:28] + node _T_119 = andr(_T_118) @[lib.scala 104:36] + node _T_120 = and(_T_119, _T_57) @[lib.scala 104:41] + node _T_121 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[lib.scala 104:74] + node _T_122 = bits(lsu_match_data_0, 9, 9) @[lib.scala 104:86] + node _T_123 = eq(_T_121, _T_122) @[lib.scala 104:78] + node _T_124 = mux(_T_120, UInt<1>("h01"), _T_123) @[lib.scala 104:23] + _T_54[9] <= _T_124 @[lib.scala 104:17] + node _T_125 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[lib.scala 104:28] + node _T_126 = andr(_T_125) @[lib.scala 104:36] + node _T_127 = and(_T_126, _T_57) @[lib.scala 104:41] + node _T_128 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[lib.scala 104:74] + node _T_129 = bits(lsu_match_data_0, 10, 10) @[lib.scala 104:86] + node _T_130 = eq(_T_128, _T_129) @[lib.scala 104:78] + node _T_131 = mux(_T_127, UInt<1>("h01"), _T_130) @[lib.scala 104:23] + _T_54[10] <= _T_131 @[lib.scala 104:17] + node _T_132 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[lib.scala 104:28] + node _T_133 = andr(_T_132) @[lib.scala 104:36] + node _T_134 = and(_T_133, _T_57) @[lib.scala 104:41] + node _T_135 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[lib.scala 104:74] + node _T_136 = bits(lsu_match_data_0, 11, 11) @[lib.scala 104:86] + node _T_137 = eq(_T_135, _T_136) @[lib.scala 104:78] + node _T_138 = mux(_T_134, UInt<1>("h01"), _T_137) @[lib.scala 104:23] + _T_54[11] <= _T_138 @[lib.scala 104:17] + node _T_139 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[lib.scala 104:28] + node _T_140 = andr(_T_139) @[lib.scala 104:36] + node _T_141 = and(_T_140, _T_57) @[lib.scala 104:41] + node _T_142 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[lib.scala 104:74] + node _T_143 = bits(lsu_match_data_0, 12, 12) @[lib.scala 104:86] + node _T_144 = eq(_T_142, _T_143) @[lib.scala 104:78] + node _T_145 = mux(_T_141, UInt<1>("h01"), _T_144) @[lib.scala 104:23] + _T_54[12] <= _T_145 @[lib.scala 104:17] + node _T_146 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[lib.scala 104:28] + node _T_147 = andr(_T_146) @[lib.scala 104:36] + node _T_148 = and(_T_147, _T_57) @[lib.scala 104:41] + node _T_149 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[lib.scala 104:74] + node _T_150 = bits(lsu_match_data_0, 13, 13) @[lib.scala 104:86] + node _T_151 = eq(_T_149, _T_150) @[lib.scala 104:78] + node _T_152 = mux(_T_148, UInt<1>("h01"), _T_151) @[lib.scala 104:23] + _T_54[13] <= _T_152 @[lib.scala 104:17] + node _T_153 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[lib.scala 104:28] + node _T_154 = andr(_T_153) @[lib.scala 104:36] + node _T_155 = and(_T_154, _T_57) @[lib.scala 104:41] + node _T_156 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[lib.scala 104:74] + node _T_157 = bits(lsu_match_data_0, 14, 14) @[lib.scala 104:86] + node _T_158 = eq(_T_156, _T_157) @[lib.scala 104:78] + node _T_159 = mux(_T_155, UInt<1>("h01"), _T_158) @[lib.scala 104:23] + _T_54[14] <= _T_159 @[lib.scala 104:17] + node _T_160 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[lib.scala 104:28] + node _T_161 = andr(_T_160) @[lib.scala 104:36] + node _T_162 = and(_T_161, _T_57) @[lib.scala 104:41] + node _T_163 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[lib.scala 104:74] + node _T_164 = bits(lsu_match_data_0, 15, 15) @[lib.scala 104:86] + node _T_165 = eq(_T_163, _T_164) @[lib.scala 104:78] + node _T_166 = mux(_T_162, UInt<1>("h01"), _T_165) @[lib.scala 104:23] + _T_54[15] <= _T_166 @[lib.scala 104:17] + node _T_167 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[lib.scala 104:28] + node _T_168 = andr(_T_167) @[lib.scala 104:36] + node _T_169 = and(_T_168, _T_57) @[lib.scala 104:41] + node _T_170 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[lib.scala 104:74] + node _T_171 = bits(lsu_match_data_0, 16, 16) @[lib.scala 104:86] + node _T_172 = eq(_T_170, _T_171) @[lib.scala 104:78] + node _T_173 = mux(_T_169, UInt<1>("h01"), _T_172) @[lib.scala 104:23] + _T_54[16] <= _T_173 @[lib.scala 104:17] + node _T_174 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[lib.scala 104:28] + node _T_175 = andr(_T_174) @[lib.scala 104:36] + node _T_176 = and(_T_175, _T_57) @[lib.scala 104:41] + node _T_177 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[lib.scala 104:74] + node _T_178 = bits(lsu_match_data_0, 17, 17) @[lib.scala 104:86] + node _T_179 = eq(_T_177, _T_178) @[lib.scala 104:78] + node _T_180 = mux(_T_176, UInt<1>("h01"), _T_179) @[lib.scala 104:23] + _T_54[17] <= _T_180 @[lib.scala 104:17] + node _T_181 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[lib.scala 104:28] + node _T_182 = andr(_T_181) @[lib.scala 104:36] + node _T_183 = and(_T_182, _T_57) @[lib.scala 104:41] + node _T_184 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[lib.scala 104:74] + node _T_185 = bits(lsu_match_data_0, 18, 18) @[lib.scala 104:86] + node _T_186 = eq(_T_184, _T_185) @[lib.scala 104:78] + node _T_187 = mux(_T_183, UInt<1>("h01"), _T_186) @[lib.scala 104:23] + _T_54[18] <= _T_187 @[lib.scala 104:17] + node _T_188 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[lib.scala 104:28] + node _T_189 = andr(_T_188) @[lib.scala 104:36] + node _T_190 = and(_T_189, _T_57) @[lib.scala 104:41] + node _T_191 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[lib.scala 104:74] + node _T_192 = bits(lsu_match_data_0, 19, 19) @[lib.scala 104:86] + node _T_193 = eq(_T_191, _T_192) @[lib.scala 104:78] + node _T_194 = mux(_T_190, UInt<1>("h01"), _T_193) @[lib.scala 104:23] + _T_54[19] <= _T_194 @[lib.scala 104:17] + node _T_195 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[lib.scala 104:28] + node _T_196 = andr(_T_195) @[lib.scala 104:36] + node _T_197 = and(_T_196, _T_57) @[lib.scala 104:41] + node _T_198 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[lib.scala 104:74] + node _T_199 = bits(lsu_match_data_0, 20, 20) @[lib.scala 104:86] + node _T_200 = eq(_T_198, _T_199) @[lib.scala 104:78] + node _T_201 = mux(_T_197, UInt<1>("h01"), _T_200) @[lib.scala 104:23] + _T_54[20] <= _T_201 @[lib.scala 104:17] + node _T_202 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[lib.scala 104:28] + node _T_203 = andr(_T_202) @[lib.scala 104:36] + node _T_204 = and(_T_203, _T_57) @[lib.scala 104:41] + node _T_205 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[lib.scala 104:74] + node _T_206 = bits(lsu_match_data_0, 21, 21) @[lib.scala 104:86] + node _T_207 = eq(_T_205, _T_206) @[lib.scala 104:78] + node _T_208 = mux(_T_204, UInt<1>("h01"), _T_207) @[lib.scala 104:23] + _T_54[21] <= _T_208 @[lib.scala 104:17] + node _T_209 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[lib.scala 104:28] + node _T_210 = andr(_T_209) @[lib.scala 104:36] + node _T_211 = and(_T_210, _T_57) @[lib.scala 104:41] + node _T_212 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[lib.scala 104:74] + node _T_213 = bits(lsu_match_data_0, 22, 22) @[lib.scala 104:86] + node _T_214 = eq(_T_212, _T_213) @[lib.scala 104:78] + node _T_215 = mux(_T_211, UInt<1>("h01"), _T_214) @[lib.scala 104:23] + _T_54[22] <= _T_215 @[lib.scala 104:17] + node _T_216 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[lib.scala 104:28] + node _T_217 = andr(_T_216) @[lib.scala 104:36] + node _T_218 = and(_T_217, _T_57) @[lib.scala 104:41] + node _T_219 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[lib.scala 104:74] + node _T_220 = bits(lsu_match_data_0, 23, 23) @[lib.scala 104:86] + node _T_221 = eq(_T_219, _T_220) @[lib.scala 104:78] + node _T_222 = mux(_T_218, UInt<1>("h01"), _T_221) @[lib.scala 104:23] + _T_54[23] <= _T_222 @[lib.scala 104:17] + node _T_223 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[lib.scala 104:28] + node _T_224 = andr(_T_223) @[lib.scala 104:36] + node _T_225 = and(_T_224, _T_57) @[lib.scala 104:41] + node _T_226 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[lib.scala 104:74] + node _T_227 = bits(lsu_match_data_0, 24, 24) @[lib.scala 104:86] + node _T_228 = eq(_T_226, _T_227) @[lib.scala 104:78] + node _T_229 = mux(_T_225, UInt<1>("h01"), _T_228) @[lib.scala 104:23] + _T_54[24] <= _T_229 @[lib.scala 104:17] + node _T_230 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[lib.scala 104:28] + node _T_231 = andr(_T_230) @[lib.scala 104:36] + node _T_232 = and(_T_231, _T_57) @[lib.scala 104:41] + node _T_233 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[lib.scala 104:74] + node _T_234 = bits(lsu_match_data_0, 25, 25) @[lib.scala 104:86] + node _T_235 = eq(_T_233, _T_234) @[lib.scala 104:78] + node _T_236 = mux(_T_232, UInt<1>("h01"), _T_235) @[lib.scala 104:23] + _T_54[25] <= _T_236 @[lib.scala 104:17] + node _T_237 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[lib.scala 104:28] + node _T_238 = andr(_T_237) @[lib.scala 104:36] + node _T_239 = and(_T_238, _T_57) @[lib.scala 104:41] + node _T_240 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[lib.scala 104:74] + node _T_241 = bits(lsu_match_data_0, 26, 26) @[lib.scala 104:86] + node _T_242 = eq(_T_240, _T_241) @[lib.scala 104:78] + node _T_243 = mux(_T_239, UInt<1>("h01"), _T_242) @[lib.scala 104:23] + _T_54[26] <= _T_243 @[lib.scala 104:17] + node _T_244 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[lib.scala 104:28] + node _T_245 = andr(_T_244) @[lib.scala 104:36] + node _T_246 = and(_T_245, _T_57) @[lib.scala 104:41] + node _T_247 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[lib.scala 104:74] + node _T_248 = bits(lsu_match_data_0, 27, 27) @[lib.scala 104:86] + node _T_249 = eq(_T_247, _T_248) @[lib.scala 104:78] + node _T_250 = mux(_T_246, UInt<1>("h01"), _T_249) @[lib.scala 104:23] + _T_54[27] <= _T_250 @[lib.scala 104:17] + node _T_251 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[lib.scala 104:28] + node _T_252 = andr(_T_251) @[lib.scala 104:36] + node _T_253 = and(_T_252, _T_57) @[lib.scala 104:41] + node _T_254 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[lib.scala 104:74] + node _T_255 = bits(lsu_match_data_0, 28, 28) @[lib.scala 104:86] + node _T_256 = eq(_T_254, _T_255) @[lib.scala 104:78] + node _T_257 = mux(_T_253, UInt<1>("h01"), _T_256) @[lib.scala 104:23] + _T_54[28] <= _T_257 @[lib.scala 104:17] + node _T_258 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[lib.scala 104:28] + node _T_259 = andr(_T_258) @[lib.scala 104:36] + node _T_260 = and(_T_259, _T_57) @[lib.scala 104:41] + node _T_261 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[lib.scala 104:74] + node _T_262 = bits(lsu_match_data_0, 29, 29) @[lib.scala 104:86] + node _T_263 = eq(_T_261, _T_262) @[lib.scala 104:78] + node _T_264 = mux(_T_260, UInt<1>("h01"), _T_263) @[lib.scala 104:23] + _T_54[29] <= _T_264 @[lib.scala 104:17] + node _T_265 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[lib.scala 104:28] + node _T_266 = andr(_T_265) @[lib.scala 104:36] + node _T_267 = and(_T_266, _T_57) @[lib.scala 104:41] + node _T_268 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[lib.scala 104:74] + node _T_269 = bits(lsu_match_data_0, 30, 30) @[lib.scala 104:86] + node _T_270 = eq(_T_268, _T_269) @[lib.scala 104:78] + node _T_271 = mux(_T_267, UInt<1>("h01"), _T_270) @[lib.scala 104:23] + _T_54[30] <= _T_271 @[lib.scala 104:17] + node _T_272 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[lib.scala 104:28] + node _T_273 = andr(_T_272) @[lib.scala 104:36] + node _T_274 = and(_T_273, _T_57) @[lib.scala 104:41] + node _T_275 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[lib.scala 104:74] + node _T_276 = bits(lsu_match_data_0, 31, 31) @[lib.scala 104:86] + node _T_277 = eq(_T_275, _T_276) @[lib.scala 104:78] + node _T_278 = mux(_T_274, UInt<1>("h01"), _T_277) @[lib.scala 104:23] + _T_54[31] <= _T_278 @[lib.scala 104:17] + node _T_279 = cat(_T_54[1], _T_54[0]) @[lib.scala 105:14] + node _T_280 = cat(_T_54[3], _T_54[2]) @[lib.scala 105:14] + node _T_281 = cat(_T_280, _T_279) @[lib.scala 105:14] + node _T_282 = cat(_T_54[5], _T_54[4]) @[lib.scala 105:14] + node _T_283 = cat(_T_54[7], _T_54[6]) @[lib.scala 105:14] + node _T_284 = cat(_T_283, _T_282) @[lib.scala 105:14] + node _T_285 = cat(_T_284, _T_281) @[lib.scala 105:14] + node _T_286 = cat(_T_54[9], _T_54[8]) @[lib.scala 105:14] + node _T_287 = cat(_T_54[11], _T_54[10]) @[lib.scala 105:14] + node _T_288 = cat(_T_287, _T_286) @[lib.scala 105:14] + node _T_289 = cat(_T_54[13], _T_54[12]) @[lib.scala 105:14] + node _T_290 = cat(_T_54[15], _T_54[14]) @[lib.scala 105:14] + node _T_291 = cat(_T_290, _T_289) @[lib.scala 105:14] + node _T_292 = cat(_T_291, _T_288) @[lib.scala 105:14] + node _T_293 = cat(_T_292, _T_285) @[lib.scala 105:14] + node _T_294 = cat(_T_54[17], _T_54[16]) @[lib.scala 105:14] + node _T_295 = cat(_T_54[19], _T_54[18]) @[lib.scala 105:14] + node _T_296 = cat(_T_295, _T_294) @[lib.scala 105:14] + node _T_297 = cat(_T_54[21], _T_54[20]) @[lib.scala 105:14] + node _T_298 = cat(_T_54[23], _T_54[22]) @[lib.scala 105:14] + node _T_299 = cat(_T_298, _T_297) @[lib.scala 105:14] + node _T_300 = cat(_T_299, _T_296) @[lib.scala 105:14] + node _T_301 = cat(_T_54[25], _T_54[24]) @[lib.scala 105:14] + node _T_302 = cat(_T_54[27], _T_54[26]) @[lib.scala 105:14] + node _T_303 = cat(_T_302, _T_301) @[lib.scala 105:14] + node _T_304 = cat(_T_54[29], _T_54[28]) @[lib.scala 105:14] + node _T_305 = cat(_T_54[31], _T_54[30]) @[lib.scala 105:14] + node _T_306 = cat(_T_305, _T_304) @[lib.scala 105:14] + node _T_307 = cat(_T_306, _T_303) @[lib.scala 105:14] + node _T_308 = cat(_T_307, _T_300) @[lib.scala 105:14] + node _T_309 = cat(_T_308, _T_293) @[lib.scala 105:14] + node _T_310 = andr(_T_309) @[lib.scala 105:25] + node _T_311 = and(_T_52, _T_310) @[lsu_trigger.scala 21:92] + node _T_312 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 20:70] + node _T_313 = and(io.lsu_pkt_m.valid, _T_312) @[lsu_trigger.scala 20:68] + node _T_314 = and(_T_313, trigger_enable) @[lsu_trigger.scala 20:93] + node _T_315 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 20:142] + node _T_316 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 21:33] + node _T_317 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[lsu_trigger.scala 21:60] + node _T_318 = and(_T_316, _T_317) @[lsu_trigger.scala 21:58] + node _T_319 = or(_T_315, _T_318) @[lsu_trigger.scala 20:168] + node _T_320 = and(_T_314, _T_319) @[lsu_trigger.scala 20:110] + node _T_321 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[lsu_trigger.scala 22:107] + wire _T_322 : UInt<1>[32] @[lib.scala 100:24] + node _T_323 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 101:45] + node _T_324 = not(_T_323) @[lib.scala 101:39] + node _T_325 = and(_T_321, _T_324) @[lib.scala 101:37] + node _T_326 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 102:48] + node _T_327 = bits(lsu_match_data_1, 0, 0) @[lib.scala 102:60] + node _T_328 = eq(_T_326, _T_327) @[lib.scala 102:52] + node _T_329 = or(_T_325, _T_328) @[lib.scala 102:41] + _T_322[0] <= _T_329 @[lib.scala 102:18] + node _T_330 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 104:28] + node _T_331 = andr(_T_330) @[lib.scala 104:36] + node _T_332 = and(_T_331, _T_325) @[lib.scala 104:41] + node _T_333 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 104:74] + node _T_334 = bits(lsu_match_data_1, 1, 1) @[lib.scala 104:86] + node _T_335 = eq(_T_333, _T_334) @[lib.scala 104:78] + node _T_336 = mux(_T_332, UInt<1>("h01"), _T_335) @[lib.scala 104:23] + _T_322[1] <= _T_336 @[lib.scala 104:17] + node _T_337 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 104:28] + node _T_338 = andr(_T_337) @[lib.scala 104:36] + node _T_339 = and(_T_338, _T_325) @[lib.scala 104:41] + node _T_340 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 104:74] + node _T_341 = bits(lsu_match_data_1, 2, 2) @[lib.scala 104:86] + node _T_342 = eq(_T_340, _T_341) @[lib.scala 104:78] + node _T_343 = mux(_T_339, UInt<1>("h01"), _T_342) @[lib.scala 104:23] + _T_322[2] <= _T_343 @[lib.scala 104:17] + node _T_344 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 104:28] + node _T_345 = andr(_T_344) @[lib.scala 104:36] + node _T_346 = and(_T_345, _T_325) @[lib.scala 104:41] + node _T_347 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 104:74] + node _T_348 = bits(lsu_match_data_1, 3, 3) @[lib.scala 104:86] + node _T_349 = eq(_T_347, _T_348) @[lib.scala 104:78] + node _T_350 = mux(_T_346, UInt<1>("h01"), _T_349) @[lib.scala 104:23] + _T_322[3] <= _T_350 @[lib.scala 104:17] + node _T_351 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 104:28] + node _T_352 = andr(_T_351) @[lib.scala 104:36] + node _T_353 = and(_T_352, _T_325) @[lib.scala 104:41] + node _T_354 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 104:74] + node _T_355 = bits(lsu_match_data_1, 4, 4) @[lib.scala 104:86] + node _T_356 = eq(_T_354, _T_355) @[lib.scala 104:78] + node _T_357 = mux(_T_353, UInt<1>("h01"), _T_356) @[lib.scala 104:23] + _T_322[4] <= _T_357 @[lib.scala 104:17] + node _T_358 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 104:28] + node _T_359 = andr(_T_358) @[lib.scala 104:36] + node _T_360 = and(_T_359, _T_325) @[lib.scala 104:41] + node _T_361 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 104:74] + node _T_362 = bits(lsu_match_data_1, 5, 5) @[lib.scala 104:86] + node _T_363 = eq(_T_361, _T_362) @[lib.scala 104:78] + node _T_364 = mux(_T_360, UInt<1>("h01"), _T_363) @[lib.scala 104:23] + _T_322[5] <= _T_364 @[lib.scala 104:17] + node _T_365 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 104:28] + node _T_366 = andr(_T_365) @[lib.scala 104:36] + node _T_367 = and(_T_366, _T_325) @[lib.scala 104:41] + node _T_368 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 104:74] + node _T_369 = bits(lsu_match_data_1, 6, 6) @[lib.scala 104:86] + node _T_370 = eq(_T_368, _T_369) @[lib.scala 104:78] + node _T_371 = mux(_T_367, UInt<1>("h01"), _T_370) @[lib.scala 104:23] + _T_322[6] <= _T_371 @[lib.scala 104:17] + node _T_372 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 104:28] + node _T_373 = andr(_T_372) @[lib.scala 104:36] + node _T_374 = and(_T_373, _T_325) @[lib.scala 104:41] + node _T_375 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 104:74] + node _T_376 = bits(lsu_match_data_1, 7, 7) @[lib.scala 104:86] + node _T_377 = eq(_T_375, _T_376) @[lib.scala 104:78] + node _T_378 = mux(_T_374, UInt<1>("h01"), _T_377) @[lib.scala 104:23] + _T_322[7] <= _T_378 @[lib.scala 104:17] + node _T_379 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 104:28] + node _T_380 = andr(_T_379) @[lib.scala 104:36] + node _T_381 = and(_T_380, _T_325) @[lib.scala 104:41] + node _T_382 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 104:74] + node _T_383 = bits(lsu_match_data_1, 8, 8) @[lib.scala 104:86] + node _T_384 = eq(_T_382, _T_383) @[lib.scala 104:78] + node _T_385 = mux(_T_381, UInt<1>("h01"), _T_384) @[lib.scala 104:23] + _T_322[8] <= _T_385 @[lib.scala 104:17] + node _T_386 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 104:28] + node _T_387 = andr(_T_386) @[lib.scala 104:36] + node _T_388 = and(_T_387, _T_325) @[lib.scala 104:41] + node _T_389 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 104:74] + node _T_390 = bits(lsu_match_data_1, 9, 9) @[lib.scala 104:86] + node _T_391 = eq(_T_389, _T_390) @[lib.scala 104:78] + node _T_392 = mux(_T_388, UInt<1>("h01"), _T_391) @[lib.scala 104:23] + _T_322[9] <= _T_392 @[lib.scala 104:17] + node _T_393 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 104:28] + node _T_394 = andr(_T_393) @[lib.scala 104:36] + node _T_395 = and(_T_394, _T_325) @[lib.scala 104:41] + node _T_396 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 104:74] + node _T_397 = bits(lsu_match_data_1, 10, 10) @[lib.scala 104:86] + node _T_398 = eq(_T_396, _T_397) @[lib.scala 104:78] + node _T_399 = mux(_T_395, UInt<1>("h01"), _T_398) @[lib.scala 104:23] + _T_322[10] <= _T_399 @[lib.scala 104:17] + node _T_400 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 104:28] + node _T_401 = andr(_T_400) @[lib.scala 104:36] + node _T_402 = and(_T_401, _T_325) @[lib.scala 104:41] + node _T_403 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 104:74] + node _T_404 = bits(lsu_match_data_1, 11, 11) @[lib.scala 104:86] + node _T_405 = eq(_T_403, _T_404) @[lib.scala 104:78] + node _T_406 = mux(_T_402, UInt<1>("h01"), _T_405) @[lib.scala 104:23] + _T_322[11] <= _T_406 @[lib.scala 104:17] + node _T_407 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 104:28] + node _T_408 = andr(_T_407) @[lib.scala 104:36] + node _T_409 = and(_T_408, _T_325) @[lib.scala 104:41] + node _T_410 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 104:74] + node _T_411 = bits(lsu_match_data_1, 12, 12) @[lib.scala 104:86] + node _T_412 = eq(_T_410, _T_411) @[lib.scala 104:78] + node _T_413 = mux(_T_409, UInt<1>("h01"), _T_412) @[lib.scala 104:23] + _T_322[12] <= _T_413 @[lib.scala 104:17] + node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 104:28] + node _T_415 = andr(_T_414) @[lib.scala 104:36] + node _T_416 = and(_T_415, _T_325) @[lib.scala 104:41] + node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 104:74] + node _T_418 = bits(lsu_match_data_1, 13, 13) @[lib.scala 104:86] + node _T_419 = eq(_T_417, _T_418) @[lib.scala 104:78] + node _T_420 = mux(_T_416, UInt<1>("h01"), _T_419) @[lib.scala 104:23] + _T_322[13] <= _T_420 @[lib.scala 104:17] + node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 104:28] + node _T_422 = andr(_T_421) @[lib.scala 104:36] + node _T_423 = and(_T_422, _T_325) @[lib.scala 104:41] + node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 104:74] + node _T_425 = bits(lsu_match_data_1, 14, 14) @[lib.scala 104:86] + node _T_426 = eq(_T_424, _T_425) @[lib.scala 104:78] + node _T_427 = mux(_T_423, UInt<1>("h01"), _T_426) @[lib.scala 104:23] + _T_322[14] <= _T_427 @[lib.scala 104:17] + node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 104:28] + node _T_429 = andr(_T_428) @[lib.scala 104:36] + node _T_430 = and(_T_429, _T_325) @[lib.scala 104:41] + node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 104:74] + node _T_432 = bits(lsu_match_data_1, 15, 15) @[lib.scala 104:86] + node _T_433 = eq(_T_431, _T_432) @[lib.scala 104:78] + node _T_434 = mux(_T_430, UInt<1>("h01"), _T_433) @[lib.scala 104:23] + _T_322[15] <= _T_434 @[lib.scala 104:17] + node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 104:28] + node _T_436 = andr(_T_435) @[lib.scala 104:36] + node _T_437 = and(_T_436, _T_325) @[lib.scala 104:41] + node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 104:74] + node _T_439 = bits(lsu_match_data_1, 16, 16) @[lib.scala 104:86] + node _T_440 = eq(_T_438, _T_439) @[lib.scala 104:78] + node _T_441 = mux(_T_437, UInt<1>("h01"), _T_440) @[lib.scala 104:23] + _T_322[16] <= _T_441 @[lib.scala 104:17] + node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 104:28] + node _T_443 = andr(_T_442) @[lib.scala 104:36] + node _T_444 = and(_T_443, _T_325) @[lib.scala 104:41] + node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 104:74] + node _T_446 = bits(lsu_match_data_1, 17, 17) @[lib.scala 104:86] + node _T_447 = eq(_T_445, _T_446) @[lib.scala 104:78] + node _T_448 = mux(_T_444, UInt<1>("h01"), _T_447) @[lib.scala 104:23] + _T_322[17] <= _T_448 @[lib.scala 104:17] + node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 104:28] + node _T_450 = andr(_T_449) @[lib.scala 104:36] + node _T_451 = and(_T_450, _T_325) @[lib.scala 104:41] + node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 104:74] + node _T_453 = bits(lsu_match_data_1, 18, 18) @[lib.scala 104:86] + node _T_454 = eq(_T_452, _T_453) @[lib.scala 104:78] + node _T_455 = mux(_T_451, UInt<1>("h01"), _T_454) @[lib.scala 104:23] + _T_322[18] <= _T_455 @[lib.scala 104:17] + node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 104:28] + node _T_457 = andr(_T_456) @[lib.scala 104:36] + node _T_458 = and(_T_457, _T_325) @[lib.scala 104:41] + node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 104:74] + node _T_460 = bits(lsu_match_data_1, 19, 19) @[lib.scala 104:86] + node _T_461 = eq(_T_459, _T_460) @[lib.scala 104:78] + node _T_462 = mux(_T_458, UInt<1>("h01"), _T_461) @[lib.scala 104:23] + _T_322[19] <= _T_462 @[lib.scala 104:17] + node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 104:28] + node _T_464 = andr(_T_463) @[lib.scala 104:36] + node _T_465 = and(_T_464, _T_325) @[lib.scala 104:41] + node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 104:74] + node _T_467 = bits(lsu_match_data_1, 20, 20) @[lib.scala 104:86] + node _T_468 = eq(_T_466, _T_467) @[lib.scala 104:78] + node _T_469 = mux(_T_465, UInt<1>("h01"), _T_468) @[lib.scala 104:23] + _T_322[20] <= _T_469 @[lib.scala 104:17] + node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 104:28] + node _T_471 = andr(_T_470) @[lib.scala 104:36] + node _T_472 = and(_T_471, _T_325) @[lib.scala 104:41] + node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 104:74] + node _T_474 = bits(lsu_match_data_1, 21, 21) @[lib.scala 104:86] + node _T_475 = eq(_T_473, _T_474) @[lib.scala 104:78] + node _T_476 = mux(_T_472, UInt<1>("h01"), _T_475) @[lib.scala 104:23] + _T_322[21] <= _T_476 @[lib.scala 104:17] + node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 104:28] + node _T_478 = andr(_T_477) @[lib.scala 104:36] + node _T_479 = and(_T_478, _T_325) @[lib.scala 104:41] + node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 104:74] + node _T_481 = bits(lsu_match_data_1, 22, 22) @[lib.scala 104:86] + node _T_482 = eq(_T_480, _T_481) @[lib.scala 104:78] + node _T_483 = mux(_T_479, UInt<1>("h01"), _T_482) @[lib.scala 104:23] + _T_322[22] <= _T_483 @[lib.scala 104:17] + node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 104:28] + node _T_485 = andr(_T_484) @[lib.scala 104:36] + node _T_486 = and(_T_485, _T_325) @[lib.scala 104:41] + node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 104:74] + node _T_488 = bits(lsu_match_data_1, 23, 23) @[lib.scala 104:86] + node _T_489 = eq(_T_487, _T_488) @[lib.scala 104:78] + node _T_490 = mux(_T_486, UInt<1>("h01"), _T_489) @[lib.scala 104:23] + _T_322[23] <= _T_490 @[lib.scala 104:17] + node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 104:28] + node _T_492 = andr(_T_491) @[lib.scala 104:36] + node _T_493 = and(_T_492, _T_325) @[lib.scala 104:41] + node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 104:74] + node _T_495 = bits(lsu_match_data_1, 24, 24) @[lib.scala 104:86] + node _T_496 = eq(_T_494, _T_495) @[lib.scala 104:78] + node _T_497 = mux(_T_493, UInt<1>("h01"), _T_496) @[lib.scala 104:23] + _T_322[24] <= _T_497 @[lib.scala 104:17] + node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 104:28] + node _T_499 = andr(_T_498) @[lib.scala 104:36] + node _T_500 = and(_T_499, _T_325) @[lib.scala 104:41] + node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 104:74] + node _T_502 = bits(lsu_match_data_1, 25, 25) @[lib.scala 104:86] + node _T_503 = eq(_T_501, _T_502) @[lib.scala 104:78] + node _T_504 = mux(_T_500, UInt<1>("h01"), _T_503) @[lib.scala 104:23] + _T_322[25] <= _T_504 @[lib.scala 104:17] + node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 104:28] + node _T_506 = andr(_T_505) @[lib.scala 104:36] + node _T_507 = and(_T_506, _T_325) @[lib.scala 104:41] + node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 104:74] + node _T_509 = bits(lsu_match_data_1, 26, 26) @[lib.scala 104:86] + node _T_510 = eq(_T_508, _T_509) @[lib.scala 104:78] + node _T_511 = mux(_T_507, UInt<1>("h01"), _T_510) @[lib.scala 104:23] + _T_322[26] <= _T_511 @[lib.scala 104:17] + node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 104:28] + node _T_513 = andr(_T_512) @[lib.scala 104:36] + node _T_514 = and(_T_513, _T_325) @[lib.scala 104:41] + node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 104:74] + node _T_516 = bits(lsu_match_data_1, 27, 27) @[lib.scala 104:86] + node _T_517 = eq(_T_515, _T_516) @[lib.scala 104:78] + node _T_518 = mux(_T_514, UInt<1>("h01"), _T_517) @[lib.scala 104:23] + _T_322[27] <= _T_518 @[lib.scala 104:17] + node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 104:28] + node _T_520 = andr(_T_519) @[lib.scala 104:36] + node _T_521 = and(_T_520, _T_325) @[lib.scala 104:41] + node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 104:74] + node _T_523 = bits(lsu_match_data_1, 28, 28) @[lib.scala 104:86] + node _T_524 = eq(_T_522, _T_523) @[lib.scala 104:78] + node _T_525 = mux(_T_521, UInt<1>("h01"), _T_524) @[lib.scala 104:23] + _T_322[28] <= _T_525 @[lib.scala 104:17] + node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 104:28] + node _T_527 = andr(_T_526) @[lib.scala 104:36] + node _T_528 = and(_T_527, _T_325) @[lib.scala 104:41] + node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 104:74] + node _T_530 = bits(lsu_match_data_1, 29, 29) @[lib.scala 104:86] + node _T_531 = eq(_T_529, _T_530) @[lib.scala 104:78] + node _T_532 = mux(_T_528, UInt<1>("h01"), _T_531) @[lib.scala 104:23] + _T_322[29] <= _T_532 @[lib.scala 104:17] + node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 104:28] + node _T_534 = andr(_T_533) @[lib.scala 104:36] + node _T_535 = and(_T_534, _T_325) @[lib.scala 104:41] + node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 104:74] + node _T_537 = bits(lsu_match_data_1, 30, 30) @[lib.scala 104:86] + node _T_538 = eq(_T_536, _T_537) @[lib.scala 104:78] + node _T_539 = mux(_T_535, UInt<1>("h01"), _T_538) @[lib.scala 104:23] + _T_322[30] <= _T_539 @[lib.scala 104:17] + node _T_540 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 104:28] + node _T_541 = andr(_T_540) @[lib.scala 104:36] + node _T_542 = and(_T_541, _T_325) @[lib.scala 104:41] + node _T_543 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 104:74] + node _T_544 = bits(lsu_match_data_1, 31, 31) @[lib.scala 104:86] + node _T_545 = eq(_T_543, _T_544) @[lib.scala 104:78] + node _T_546 = mux(_T_542, UInt<1>("h01"), _T_545) @[lib.scala 104:23] + _T_322[31] <= _T_546 @[lib.scala 104:17] + node _T_547 = cat(_T_322[1], _T_322[0]) @[lib.scala 105:14] + node _T_548 = cat(_T_322[3], _T_322[2]) @[lib.scala 105:14] + node _T_549 = cat(_T_548, _T_547) @[lib.scala 105:14] + node _T_550 = cat(_T_322[5], _T_322[4]) @[lib.scala 105:14] + node _T_551 = cat(_T_322[7], _T_322[6]) @[lib.scala 105:14] + node _T_552 = cat(_T_551, _T_550) @[lib.scala 105:14] + node _T_553 = cat(_T_552, _T_549) @[lib.scala 105:14] + node _T_554 = cat(_T_322[9], _T_322[8]) @[lib.scala 105:14] + node _T_555 = cat(_T_322[11], _T_322[10]) @[lib.scala 105:14] + node _T_556 = cat(_T_555, _T_554) @[lib.scala 105:14] + node _T_557 = cat(_T_322[13], _T_322[12]) @[lib.scala 105:14] + node _T_558 = cat(_T_322[15], _T_322[14]) @[lib.scala 105:14] + node _T_559 = cat(_T_558, _T_557) @[lib.scala 105:14] + node _T_560 = cat(_T_559, _T_556) @[lib.scala 105:14] + node _T_561 = cat(_T_560, _T_553) @[lib.scala 105:14] + node _T_562 = cat(_T_322[17], _T_322[16]) @[lib.scala 105:14] + node _T_563 = cat(_T_322[19], _T_322[18]) @[lib.scala 105:14] + node _T_564 = cat(_T_563, _T_562) @[lib.scala 105:14] + node _T_565 = cat(_T_322[21], _T_322[20]) @[lib.scala 105:14] + node _T_566 = cat(_T_322[23], _T_322[22]) @[lib.scala 105:14] + node _T_567 = cat(_T_566, _T_565) @[lib.scala 105:14] + node _T_568 = cat(_T_567, _T_564) @[lib.scala 105:14] + node _T_569 = cat(_T_322[25], _T_322[24]) @[lib.scala 105:14] + node _T_570 = cat(_T_322[27], _T_322[26]) @[lib.scala 105:14] + node _T_571 = cat(_T_570, _T_569) @[lib.scala 105:14] + node _T_572 = cat(_T_322[29], _T_322[28]) @[lib.scala 105:14] + node _T_573 = cat(_T_322[31], _T_322[30]) @[lib.scala 105:14] + node _T_574 = cat(_T_573, _T_572) @[lib.scala 105:14] + node _T_575 = cat(_T_574, _T_571) @[lib.scala 105:14] + node _T_576 = cat(_T_575, _T_568) @[lib.scala 105:14] + node _T_577 = cat(_T_576, _T_561) @[lib.scala 105:14] + node _T_578 = andr(_T_577) @[lib.scala 105:25] + node _T_579 = and(_T_320, _T_578) @[lsu_trigger.scala 21:92] + node _T_580 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 20:70] + node _T_581 = and(io.lsu_pkt_m.valid, _T_580) @[lsu_trigger.scala 20:68] + node _T_582 = and(_T_581, trigger_enable) @[lsu_trigger.scala 20:93] + node _T_583 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 20:142] + node _T_584 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 21:33] + node _T_585 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[lsu_trigger.scala 21:60] + node _T_586 = and(_T_584, _T_585) @[lsu_trigger.scala 21:58] + node _T_587 = or(_T_583, _T_586) @[lsu_trigger.scala 20:168] + node _T_588 = and(_T_582, _T_587) @[lsu_trigger.scala 20:110] + node _T_589 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[lsu_trigger.scala 22:107] + wire _T_590 : UInt<1>[32] @[lib.scala 100:24] + node _T_591 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 101:45] + node _T_592 = not(_T_591) @[lib.scala 101:39] + node _T_593 = and(_T_589, _T_592) @[lib.scala 101:37] + node _T_594 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 102:48] + node _T_595 = bits(lsu_match_data_2, 0, 0) @[lib.scala 102:60] + node _T_596 = eq(_T_594, _T_595) @[lib.scala 102:52] + node _T_597 = or(_T_593, _T_596) @[lib.scala 102:41] + _T_590[0] <= _T_597 @[lib.scala 102:18] + node _T_598 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 104:28] + node _T_599 = andr(_T_598) @[lib.scala 104:36] + node _T_600 = and(_T_599, _T_593) @[lib.scala 104:41] + node _T_601 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 104:74] + node _T_602 = bits(lsu_match_data_2, 1, 1) @[lib.scala 104:86] + node _T_603 = eq(_T_601, _T_602) @[lib.scala 104:78] + node _T_604 = mux(_T_600, UInt<1>("h01"), _T_603) @[lib.scala 104:23] + _T_590[1] <= _T_604 @[lib.scala 104:17] + node _T_605 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 104:28] + node _T_606 = andr(_T_605) @[lib.scala 104:36] + node _T_607 = and(_T_606, _T_593) @[lib.scala 104:41] + node _T_608 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 104:74] + node _T_609 = bits(lsu_match_data_2, 2, 2) @[lib.scala 104:86] + node _T_610 = eq(_T_608, _T_609) @[lib.scala 104:78] + node _T_611 = mux(_T_607, UInt<1>("h01"), _T_610) @[lib.scala 104:23] + _T_590[2] <= _T_611 @[lib.scala 104:17] + node _T_612 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 104:28] + node _T_613 = andr(_T_612) @[lib.scala 104:36] + node _T_614 = and(_T_613, _T_593) @[lib.scala 104:41] + node _T_615 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 104:74] + node _T_616 = bits(lsu_match_data_2, 3, 3) @[lib.scala 104:86] + node _T_617 = eq(_T_615, _T_616) @[lib.scala 104:78] + node _T_618 = mux(_T_614, UInt<1>("h01"), _T_617) @[lib.scala 104:23] + _T_590[3] <= _T_618 @[lib.scala 104:17] + node _T_619 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 104:28] + node _T_620 = andr(_T_619) @[lib.scala 104:36] + node _T_621 = and(_T_620, _T_593) @[lib.scala 104:41] + node _T_622 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 104:74] + node _T_623 = bits(lsu_match_data_2, 4, 4) @[lib.scala 104:86] + node _T_624 = eq(_T_622, _T_623) @[lib.scala 104:78] + node _T_625 = mux(_T_621, UInt<1>("h01"), _T_624) @[lib.scala 104:23] + _T_590[4] <= _T_625 @[lib.scala 104:17] + node _T_626 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 104:28] + node _T_627 = andr(_T_626) @[lib.scala 104:36] + node _T_628 = and(_T_627, _T_593) @[lib.scala 104:41] + node _T_629 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 104:74] + node _T_630 = bits(lsu_match_data_2, 5, 5) @[lib.scala 104:86] + node _T_631 = eq(_T_629, _T_630) @[lib.scala 104:78] + node _T_632 = mux(_T_628, UInt<1>("h01"), _T_631) @[lib.scala 104:23] + _T_590[5] <= _T_632 @[lib.scala 104:17] + node _T_633 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 104:28] + node _T_634 = andr(_T_633) @[lib.scala 104:36] + node _T_635 = and(_T_634, _T_593) @[lib.scala 104:41] + node _T_636 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 104:74] + node _T_637 = bits(lsu_match_data_2, 6, 6) @[lib.scala 104:86] + node _T_638 = eq(_T_636, _T_637) @[lib.scala 104:78] + node _T_639 = mux(_T_635, UInt<1>("h01"), _T_638) @[lib.scala 104:23] + _T_590[6] <= _T_639 @[lib.scala 104:17] + node _T_640 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 104:28] + node _T_641 = andr(_T_640) @[lib.scala 104:36] + node _T_642 = and(_T_641, _T_593) @[lib.scala 104:41] + node _T_643 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 104:74] + node _T_644 = bits(lsu_match_data_2, 7, 7) @[lib.scala 104:86] + node _T_645 = eq(_T_643, _T_644) @[lib.scala 104:78] + node _T_646 = mux(_T_642, UInt<1>("h01"), _T_645) @[lib.scala 104:23] + _T_590[7] <= _T_646 @[lib.scala 104:17] + node _T_647 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 104:28] + node _T_648 = andr(_T_647) @[lib.scala 104:36] + node _T_649 = and(_T_648, _T_593) @[lib.scala 104:41] + node _T_650 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 104:74] + node _T_651 = bits(lsu_match_data_2, 8, 8) @[lib.scala 104:86] + node _T_652 = eq(_T_650, _T_651) @[lib.scala 104:78] + node _T_653 = mux(_T_649, UInt<1>("h01"), _T_652) @[lib.scala 104:23] + _T_590[8] <= _T_653 @[lib.scala 104:17] + node _T_654 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 104:28] + node _T_655 = andr(_T_654) @[lib.scala 104:36] + node _T_656 = and(_T_655, _T_593) @[lib.scala 104:41] + node _T_657 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 104:74] + node _T_658 = bits(lsu_match_data_2, 9, 9) @[lib.scala 104:86] + node _T_659 = eq(_T_657, _T_658) @[lib.scala 104:78] + node _T_660 = mux(_T_656, UInt<1>("h01"), _T_659) @[lib.scala 104:23] + _T_590[9] <= _T_660 @[lib.scala 104:17] + node _T_661 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 104:28] + node _T_662 = andr(_T_661) @[lib.scala 104:36] + node _T_663 = and(_T_662, _T_593) @[lib.scala 104:41] + node _T_664 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 104:74] + node _T_665 = bits(lsu_match_data_2, 10, 10) @[lib.scala 104:86] + node _T_666 = eq(_T_664, _T_665) @[lib.scala 104:78] + node _T_667 = mux(_T_663, UInt<1>("h01"), _T_666) @[lib.scala 104:23] + _T_590[10] <= _T_667 @[lib.scala 104:17] + node _T_668 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 104:28] + node _T_669 = andr(_T_668) @[lib.scala 104:36] + node _T_670 = and(_T_669, _T_593) @[lib.scala 104:41] + node _T_671 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 104:74] + node _T_672 = bits(lsu_match_data_2, 11, 11) @[lib.scala 104:86] + node _T_673 = eq(_T_671, _T_672) @[lib.scala 104:78] + node _T_674 = mux(_T_670, UInt<1>("h01"), _T_673) @[lib.scala 104:23] + _T_590[11] <= _T_674 @[lib.scala 104:17] + node _T_675 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 104:28] + node _T_676 = andr(_T_675) @[lib.scala 104:36] + node _T_677 = and(_T_676, _T_593) @[lib.scala 104:41] + node _T_678 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 104:74] + node _T_679 = bits(lsu_match_data_2, 12, 12) @[lib.scala 104:86] + node _T_680 = eq(_T_678, _T_679) @[lib.scala 104:78] + node _T_681 = mux(_T_677, UInt<1>("h01"), _T_680) @[lib.scala 104:23] + _T_590[12] <= _T_681 @[lib.scala 104:17] + node _T_682 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 104:28] + node _T_683 = andr(_T_682) @[lib.scala 104:36] + node _T_684 = and(_T_683, _T_593) @[lib.scala 104:41] + node _T_685 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 104:74] + node _T_686 = bits(lsu_match_data_2, 13, 13) @[lib.scala 104:86] + node _T_687 = eq(_T_685, _T_686) @[lib.scala 104:78] + node _T_688 = mux(_T_684, UInt<1>("h01"), _T_687) @[lib.scala 104:23] + _T_590[13] <= _T_688 @[lib.scala 104:17] + node _T_689 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 104:28] + node _T_690 = andr(_T_689) @[lib.scala 104:36] + node _T_691 = and(_T_690, _T_593) @[lib.scala 104:41] + node _T_692 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 104:74] + node _T_693 = bits(lsu_match_data_2, 14, 14) @[lib.scala 104:86] + node _T_694 = eq(_T_692, _T_693) @[lib.scala 104:78] + node _T_695 = mux(_T_691, UInt<1>("h01"), _T_694) @[lib.scala 104:23] + _T_590[14] <= _T_695 @[lib.scala 104:17] + node _T_696 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 104:28] + node _T_697 = andr(_T_696) @[lib.scala 104:36] + node _T_698 = and(_T_697, _T_593) @[lib.scala 104:41] + node _T_699 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 104:74] + node _T_700 = bits(lsu_match_data_2, 15, 15) @[lib.scala 104:86] + node _T_701 = eq(_T_699, _T_700) @[lib.scala 104:78] + node _T_702 = mux(_T_698, UInt<1>("h01"), _T_701) @[lib.scala 104:23] + _T_590[15] <= _T_702 @[lib.scala 104:17] + node _T_703 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 104:28] + node _T_704 = andr(_T_703) @[lib.scala 104:36] + node _T_705 = and(_T_704, _T_593) @[lib.scala 104:41] + node _T_706 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 104:74] + node _T_707 = bits(lsu_match_data_2, 16, 16) @[lib.scala 104:86] + node _T_708 = eq(_T_706, _T_707) @[lib.scala 104:78] + node _T_709 = mux(_T_705, UInt<1>("h01"), _T_708) @[lib.scala 104:23] + _T_590[16] <= _T_709 @[lib.scala 104:17] + node _T_710 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 104:28] + node _T_711 = andr(_T_710) @[lib.scala 104:36] + node _T_712 = and(_T_711, _T_593) @[lib.scala 104:41] + node _T_713 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 104:74] + node _T_714 = bits(lsu_match_data_2, 17, 17) @[lib.scala 104:86] + node _T_715 = eq(_T_713, _T_714) @[lib.scala 104:78] + node _T_716 = mux(_T_712, UInt<1>("h01"), _T_715) @[lib.scala 104:23] + _T_590[17] <= _T_716 @[lib.scala 104:17] + node _T_717 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 104:28] + node _T_718 = andr(_T_717) @[lib.scala 104:36] + node _T_719 = and(_T_718, _T_593) @[lib.scala 104:41] + node _T_720 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 104:74] + node _T_721 = bits(lsu_match_data_2, 18, 18) @[lib.scala 104:86] + node _T_722 = eq(_T_720, _T_721) @[lib.scala 104:78] + node _T_723 = mux(_T_719, UInt<1>("h01"), _T_722) @[lib.scala 104:23] + _T_590[18] <= _T_723 @[lib.scala 104:17] + node _T_724 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 104:28] + node _T_725 = andr(_T_724) @[lib.scala 104:36] + node _T_726 = and(_T_725, _T_593) @[lib.scala 104:41] + node _T_727 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 104:74] + node _T_728 = bits(lsu_match_data_2, 19, 19) @[lib.scala 104:86] + node _T_729 = eq(_T_727, _T_728) @[lib.scala 104:78] + node _T_730 = mux(_T_726, UInt<1>("h01"), _T_729) @[lib.scala 104:23] + _T_590[19] <= _T_730 @[lib.scala 104:17] + node _T_731 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 104:28] + node _T_732 = andr(_T_731) @[lib.scala 104:36] + node _T_733 = and(_T_732, _T_593) @[lib.scala 104:41] + node _T_734 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 104:74] + node _T_735 = bits(lsu_match_data_2, 20, 20) @[lib.scala 104:86] + node _T_736 = eq(_T_734, _T_735) @[lib.scala 104:78] + node _T_737 = mux(_T_733, UInt<1>("h01"), _T_736) @[lib.scala 104:23] + _T_590[20] <= _T_737 @[lib.scala 104:17] + node _T_738 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 104:28] + node _T_739 = andr(_T_738) @[lib.scala 104:36] + node _T_740 = and(_T_739, _T_593) @[lib.scala 104:41] + node _T_741 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 104:74] + node _T_742 = bits(lsu_match_data_2, 21, 21) @[lib.scala 104:86] + node _T_743 = eq(_T_741, _T_742) @[lib.scala 104:78] + node _T_744 = mux(_T_740, UInt<1>("h01"), _T_743) @[lib.scala 104:23] + _T_590[21] <= _T_744 @[lib.scala 104:17] + node _T_745 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 104:28] + node _T_746 = andr(_T_745) @[lib.scala 104:36] + node _T_747 = and(_T_746, _T_593) @[lib.scala 104:41] + node _T_748 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 104:74] + node _T_749 = bits(lsu_match_data_2, 22, 22) @[lib.scala 104:86] + node _T_750 = eq(_T_748, _T_749) @[lib.scala 104:78] + node _T_751 = mux(_T_747, UInt<1>("h01"), _T_750) @[lib.scala 104:23] + _T_590[22] <= _T_751 @[lib.scala 104:17] + node _T_752 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 104:28] + node _T_753 = andr(_T_752) @[lib.scala 104:36] + node _T_754 = and(_T_753, _T_593) @[lib.scala 104:41] + node _T_755 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 104:74] + node _T_756 = bits(lsu_match_data_2, 23, 23) @[lib.scala 104:86] + node _T_757 = eq(_T_755, _T_756) @[lib.scala 104:78] + node _T_758 = mux(_T_754, UInt<1>("h01"), _T_757) @[lib.scala 104:23] + _T_590[23] <= _T_758 @[lib.scala 104:17] + node _T_759 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 104:28] + node _T_760 = andr(_T_759) @[lib.scala 104:36] + node _T_761 = and(_T_760, _T_593) @[lib.scala 104:41] + node _T_762 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 104:74] + node _T_763 = bits(lsu_match_data_2, 24, 24) @[lib.scala 104:86] + node _T_764 = eq(_T_762, _T_763) @[lib.scala 104:78] + node _T_765 = mux(_T_761, UInt<1>("h01"), _T_764) @[lib.scala 104:23] + _T_590[24] <= _T_765 @[lib.scala 104:17] + node _T_766 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 104:28] + node _T_767 = andr(_T_766) @[lib.scala 104:36] + node _T_768 = and(_T_767, _T_593) @[lib.scala 104:41] + node _T_769 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 104:74] + node _T_770 = bits(lsu_match_data_2, 25, 25) @[lib.scala 104:86] + node _T_771 = eq(_T_769, _T_770) @[lib.scala 104:78] + node _T_772 = mux(_T_768, UInt<1>("h01"), _T_771) @[lib.scala 104:23] + _T_590[25] <= _T_772 @[lib.scala 104:17] + node _T_773 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 104:28] + node _T_774 = andr(_T_773) @[lib.scala 104:36] + node _T_775 = and(_T_774, _T_593) @[lib.scala 104:41] + node _T_776 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 104:74] + node _T_777 = bits(lsu_match_data_2, 26, 26) @[lib.scala 104:86] + node _T_778 = eq(_T_776, _T_777) @[lib.scala 104:78] + node _T_779 = mux(_T_775, UInt<1>("h01"), _T_778) @[lib.scala 104:23] + _T_590[26] <= _T_779 @[lib.scala 104:17] + node _T_780 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 104:28] + node _T_781 = andr(_T_780) @[lib.scala 104:36] + node _T_782 = and(_T_781, _T_593) @[lib.scala 104:41] + node _T_783 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 104:74] + node _T_784 = bits(lsu_match_data_2, 27, 27) @[lib.scala 104:86] + node _T_785 = eq(_T_783, _T_784) @[lib.scala 104:78] + node _T_786 = mux(_T_782, UInt<1>("h01"), _T_785) @[lib.scala 104:23] + _T_590[27] <= _T_786 @[lib.scala 104:17] + node _T_787 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 104:28] + node _T_788 = andr(_T_787) @[lib.scala 104:36] + node _T_789 = and(_T_788, _T_593) @[lib.scala 104:41] + node _T_790 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 104:74] + node _T_791 = bits(lsu_match_data_2, 28, 28) @[lib.scala 104:86] + node _T_792 = eq(_T_790, _T_791) @[lib.scala 104:78] + node _T_793 = mux(_T_789, UInt<1>("h01"), _T_792) @[lib.scala 104:23] + _T_590[28] <= _T_793 @[lib.scala 104:17] + node _T_794 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 104:28] + node _T_795 = andr(_T_794) @[lib.scala 104:36] + node _T_796 = and(_T_795, _T_593) @[lib.scala 104:41] + node _T_797 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 104:74] + node _T_798 = bits(lsu_match_data_2, 29, 29) @[lib.scala 104:86] + node _T_799 = eq(_T_797, _T_798) @[lib.scala 104:78] + node _T_800 = mux(_T_796, UInt<1>("h01"), _T_799) @[lib.scala 104:23] + _T_590[29] <= _T_800 @[lib.scala 104:17] + node _T_801 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 104:28] + node _T_802 = andr(_T_801) @[lib.scala 104:36] + node _T_803 = and(_T_802, _T_593) @[lib.scala 104:41] + node _T_804 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 104:74] + node _T_805 = bits(lsu_match_data_2, 30, 30) @[lib.scala 104:86] + node _T_806 = eq(_T_804, _T_805) @[lib.scala 104:78] + node _T_807 = mux(_T_803, UInt<1>("h01"), _T_806) @[lib.scala 104:23] + _T_590[30] <= _T_807 @[lib.scala 104:17] + node _T_808 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 104:28] + node _T_809 = andr(_T_808) @[lib.scala 104:36] + node _T_810 = and(_T_809, _T_593) @[lib.scala 104:41] + node _T_811 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 104:74] + node _T_812 = bits(lsu_match_data_2, 31, 31) @[lib.scala 104:86] + node _T_813 = eq(_T_811, _T_812) @[lib.scala 104:78] + node _T_814 = mux(_T_810, UInt<1>("h01"), _T_813) @[lib.scala 104:23] + _T_590[31] <= _T_814 @[lib.scala 104:17] + node _T_815 = cat(_T_590[1], _T_590[0]) @[lib.scala 105:14] + node _T_816 = cat(_T_590[3], _T_590[2]) @[lib.scala 105:14] + node _T_817 = cat(_T_816, _T_815) @[lib.scala 105:14] + node _T_818 = cat(_T_590[5], _T_590[4]) @[lib.scala 105:14] + node _T_819 = cat(_T_590[7], _T_590[6]) @[lib.scala 105:14] + node _T_820 = cat(_T_819, _T_818) @[lib.scala 105:14] + node _T_821 = cat(_T_820, _T_817) @[lib.scala 105:14] + node _T_822 = cat(_T_590[9], _T_590[8]) @[lib.scala 105:14] + node _T_823 = cat(_T_590[11], _T_590[10]) @[lib.scala 105:14] + node _T_824 = cat(_T_823, _T_822) @[lib.scala 105:14] + node _T_825 = cat(_T_590[13], _T_590[12]) @[lib.scala 105:14] + node _T_826 = cat(_T_590[15], _T_590[14]) @[lib.scala 105:14] + node _T_827 = cat(_T_826, _T_825) @[lib.scala 105:14] + node _T_828 = cat(_T_827, _T_824) @[lib.scala 105:14] + node _T_829 = cat(_T_828, _T_821) @[lib.scala 105:14] + node _T_830 = cat(_T_590[17], _T_590[16]) @[lib.scala 105:14] + node _T_831 = cat(_T_590[19], _T_590[18]) @[lib.scala 105:14] + node _T_832 = cat(_T_831, _T_830) @[lib.scala 105:14] + node _T_833 = cat(_T_590[21], _T_590[20]) @[lib.scala 105:14] + node _T_834 = cat(_T_590[23], _T_590[22]) @[lib.scala 105:14] + node _T_835 = cat(_T_834, _T_833) @[lib.scala 105:14] + node _T_836 = cat(_T_835, _T_832) @[lib.scala 105:14] + node _T_837 = cat(_T_590[25], _T_590[24]) @[lib.scala 105:14] + node _T_838 = cat(_T_590[27], _T_590[26]) @[lib.scala 105:14] + node _T_839 = cat(_T_838, _T_837) @[lib.scala 105:14] + node _T_840 = cat(_T_590[29], _T_590[28]) @[lib.scala 105:14] + node _T_841 = cat(_T_590[31], _T_590[30]) @[lib.scala 105:14] + node _T_842 = cat(_T_841, _T_840) @[lib.scala 105:14] + node _T_843 = cat(_T_842, _T_839) @[lib.scala 105:14] + node _T_844 = cat(_T_843, _T_836) @[lib.scala 105:14] + node _T_845 = cat(_T_844, _T_829) @[lib.scala 105:14] + node _T_846 = andr(_T_845) @[lib.scala 105:25] + node _T_847 = and(_T_588, _T_846) @[lsu_trigger.scala 21:92] + node _T_848 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 20:70] + node _T_849 = and(io.lsu_pkt_m.valid, _T_848) @[lsu_trigger.scala 20:68] + node _T_850 = and(_T_849, trigger_enable) @[lsu_trigger.scala 20:93] + node _T_851 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 20:142] + node _T_852 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 21:33] + node _T_853 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[lsu_trigger.scala 21:60] + node _T_854 = and(_T_852, _T_853) @[lsu_trigger.scala 21:58] + node _T_855 = or(_T_851, _T_854) @[lsu_trigger.scala 20:168] + node _T_856 = and(_T_850, _T_855) @[lsu_trigger.scala 20:110] + node _T_857 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[lsu_trigger.scala 22:107] + wire _T_858 : UInt<1>[32] @[lib.scala 100:24] + node _T_859 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 101:45] + node _T_860 = not(_T_859) @[lib.scala 101:39] + node _T_861 = and(_T_857, _T_860) @[lib.scala 101:37] + node _T_862 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 102:48] + node _T_863 = bits(lsu_match_data_3, 0, 0) @[lib.scala 102:60] + node _T_864 = eq(_T_862, _T_863) @[lib.scala 102:52] + node _T_865 = or(_T_861, _T_864) @[lib.scala 102:41] + _T_858[0] <= _T_865 @[lib.scala 102:18] + node _T_866 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 104:28] + node _T_867 = andr(_T_866) @[lib.scala 104:36] + node _T_868 = and(_T_867, _T_861) @[lib.scala 104:41] + node _T_869 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 104:74] + node _T_870 = bits(lsu_match_data_3, 1, 1) @[lib.scala 104:86] + node _T_871 = eq(_T_869, _T_870) @[lib.scala 104:78] + node _T_872 = mux(_T_868, UInt<1>("h01"), _T_871) @[lib.scala 104:23] + _T_858[1] <= _T_872 @[lib.scala 104:17] + node _T_873 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 104:28] + node _T_874 = andr(_T_873) @[lib.scala 104:36] + node _T_875 = and(_T_874, _T_861) @[lib.scala 104:41] + node _T_876 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 104:74] + node _T_877 = bits(lsu_match_data_3, 2, 2) @[lib.scala 104:86] + node _T_878 = eq(_T_876, _T_877) @[lib.scala 104:78] + node _T_879 = mux(_T_875, UInt<1>("h01"), _T_878) @[lib.scala 104:23] + _T_858[2] <= _T_879 @[lib.scala 104:17] + node _T_880 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 104:28] + node _T_881 = andr(_T_880) @[lib.scala 104:36] + node _T_882 = and(_T_881, _T_861) @[lib.scala 104:41] + node _T_883 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 104:74] + node _T_884 = bits(lsu_match_data_3, 3, 3) @[lib.scala 104:86] + node _T_885 = eq(_T_883, _T_884) @[lib.scala 104:78] + node _T_886 = mux(_T_882, UInt<1>("h01"), _T_885) @[lib.scala 104:23] + _T_858[3] <= _T_886 @[lib.scala 104:17] + node _T_887 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 104:28] + node _T_888 = andr(_T_887) @[lib.scala 104:36] + node _T_889 = and(_T_888, _T_861) @[lib.scala 104:41] + node _T_890 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 104:74] + node _T_891 = bits(lsu_match_data_3, 4, 4) @[lib.scala 104:86] + node _T_892 = eq(_T_890, _T_891) @[lib.scala 104:78] + node _T_893 = mux(_T_889, UInt<1>("h01"), _T_892) @[lib.scala 104:23] + _T_858[4] <= _T_893 @[lib.scala 104:17] + node _T_894 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 104:28] + node _T_895 = andr(_T_894) @[lib.scala 104:36] + node _T_896 = and(_T_895, _T_861) @[lib.scala 104:41] + node _T_897 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 104:74] + node _T_898 = bits(lsu_match_data_3, 5, 5) @[lib.scala 104:86] + node _T_899 = eq(_T_897, _T_898) @[lib.scala 104:78] + node _T_900 = mux(_T_896, UInt<1>("h01"), _T_899) @[lib.scala 104:23] + _T_858[5] <= _T_900 @[lib.scala 104:17] + node _T_901 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 104:28] + node _T_902 = andr(_T_901) @[lib.scala 104:36] + node _T_903 = and(_T_902, _T_861) @[lib.scala 104:41] + node _T_904 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 104:74] + node _T_905 = bits(lsu_match_data_3, 6, 6) @[lib.scala 104:86] + node _T_906 = eq(_T_904, _T_905) @[lib.scala 104:78] + node _T_907 = mux(_T_903, UInt<1>("h01"), _T_906) @[lib.scala 104:23] + _T_858[6] <= _T_907 @[lib.scala 104:17] + node _T_908 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 104:28] + node _T_909 = andr(_T_908) @[lib.scala 104:36] + node _T_910 = and(_T_909, _T_861) @[lib.scala 104:41] + node _T_911 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 104:74] + node _T_912 = bits(lsu_match_data_3, 7, 7) @[lib.scala 104:86] + node _T_913 = eq(_T_911, _T_912) @[lib.scala 104:78] + node _T_914 = mux(_T_910, UInt<1>("h01"), _T_913) @[lib.scala 104:23] + _T_858[7] <= _T_914 @[lib.scala 104:17] + node _T_915 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 104:28] + node _T_916 = andr(_T_915) @[lib.scala 104:36] + node _T_917 = and(_T_916, _T_861) @[lib.scala 104:41] + node _T_918 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 104:74] + node _T_919 = bits(lsu_match_data_3, 8, 8) @[lib.scala 104:86] + node _T_920 = eq(_T_918, _T_919) @[lib.scala 104:78] + node _T_921 = mux(_T_917, UInt<1>("h01"), _T_920) @[lib.scala 104:23] + _T_858[8] <= _T_921 @[lib.scala 104:17] + node _T_922 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 104:28] + node _T_923 = andr(_T_922) @[lib.scala 104:36] + node _T_924 = and(_T_923, _T_861) @[lib.scala 104:41] + node _T_925 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 104:74] + node _T_926 = bits(lsu_match_data_3, 9, 9) @[lib.scala 104:86] + node _T_927 = eq(_T_925, _T_926) @[lib.scala 104:78] + node _T_928 = mux(_T_924, UInt<1>("h01"), _T_927) @[lib.scala 104:23] + _T_858[9] <= _T_928 @[lib.scala 104:17] + node _T_929 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 104:28] + node _T_930 = andr(_T_929) @[lib.scala 104:36] + node _T_931 = and(_T_930, _T_861) @[lib.scala 104:41] + node _T_932 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 104:74] + node _T_933 = bits(lsu_match_data_3, 10, 10) @[lib.scala 104:86] + node _T_934 = eq(_T_932, _T_933) @[lib.scala 104:78] + node _T_935 = mux(_T_931, UInt<1>("h01"), _T_934) @[lib.scala 104:23] + _T_858[10] <= _T_935 @[lib.scala 104:17] + node _T_936 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 104:28] + node _T_937 = andr(_T_936) @[lib.scala 104:36] + node _T_938 = and(_T_937, _T_861) @[lib.scala 104:41] + node _T_939 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 104:74] + node _T_940 = bits(lsu_match_data_3, 11, 11) @[lib.scala 104:86] + node _T_941 = eq(_T_939, _T_940) @[lib.scala 104:78] + node _T_942 = mux(_T_938, UInt<1>("h01"), _T_941) @[lib.scala 104:23] + _T_858[11] <= _T_942 @[lib.scala 104:17] + node _T_943 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 104:28] + node _T_944 = andr(_T_943) @[lib.scala 104:36] + node _T_945 = and(_T_944, _T_861) @[lib.scala 104:41] + node _T_946 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 104:74] + node _T_947 = bits(lsu_match_data_3, 12, 12) @[lib.scala 104:86] + node _T_948 = eq(_T_946, _T_947) @[lib.scala 104:78] + node _T_949 = mux(_T_945, UInt<1>("h01"), _T_948) @[lib.scala 104:23] + _T_858[12] <= _T_949 @[lib.scala 104:17] + node _T_950 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 104:28] + node _T_951 = andr(_T_950) @[lib.scala 104:36] + node _T_952 = and(_T_951, _T_861) @[lib.scala 104:41] + node _T_953 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 104:74] + node _T_954 = bits(lsu_match_data_3, 13, 13) @[lib.scala 104:86] + node _T_955 = eq(_T_953, _T_954) @[lib.scala 104:78] + node _T_956 = mux(_T_952, UInt<1>("h01"), _T_955) @[lib.scala 104:23] + _T_858[13] <= _T_956 @[lib.scala 104:17] + node _T_957 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 104:28] + node _T_958 = andr(_T_957) @[lib.scala 104:36] + node _T_959 = and(_T_958, _T_861) @[lib.scala 104:41] + node _T_960 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 104:74] + node _T_961 = bits(lsu_match_data_3, 14, 14) @[lib.scala 104:86] + node _T_962 = eq(_T_960, _T_961) @[lib.scala 104:78] + node _T_963 = mux(_T_959, UInt<1>("h01"), _T_962) @[lib.scala 104:23] + _T_858[14] <= _T_963 @[lib.scala 104:17] + node _T_964 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 104:28] + node _T_965 = andr(_T_964) @[lib.scala 104:36] + node _T_966 = and(_T_965, _T_861) @[lib.scala 104:41] + node _T_967 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 104:74] + node _T_968 = bits(lsu_match_data_3, 15, 15) @[lib.scala 104:86] + node _T_969 = eq(_T_967, _T_968) @[lib.scala 104:78] + node _T_970 = mux(_T_966, UInt<1>("h01"), _T_969) @[lib.scala 104:23] + _T_858[15] <= _T_970 @[lib.scala 104:17] + node _T_971 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 104:28] + node _T_972 = andr(_T_971) @[lib.scala 104:36] + node _T_973 = and(_T_972, _T_861) @[lib.scala 104:41] + node _T_974 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 104:74] + node _T_975 = bits(lsu_match_data_3, 16, 16) @[lib.scala 104:86] + node _T_976 = eq(_T_974, _T_975) @[lib.scala 104:78] + node _T_977 = mux(_T_973, UInt<1>("h01"), _T_976) @[lib.scala 104:23] + _T_858[16] <= _T_977 @[lib.scala 104:17] + node _T_978 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 104:28] + node _T_979 = andr(_T_978) @[lib.scala 104:36] + node _T_980 = and(_T_979, _T_861) @[lib.scala 104:41] + node _T_981 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 104:74] + node _T_982 = bits(lsu_match_data_3, 17, 17) @[lib.scala 104:86] + node _T_983 = eq(_T_981, _T_982) @[lib.scala 104:78] + node _T_984 = mux(_T_980, UInt<1>("h01"), _T_983) @[lib.scala 104:23] + _T_858[17] <= _T_984 @[lib.scala 104:17] + node _T_985 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 104:28] + node _T_986 = andr(_T_985) @[lib.scala 104:36] + node _T_987 = and(_T_986, _T_861) @[lib.scala 104:41] + node _T_988 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 104:74] + node _T_989 = bits(lsu_match_data_3, 18, 18) @[lib.scala 104:86] + node _T_990 = eq(_T_988, _T_989) @[lib.scala 104:78] + node _T_991 = mux(_T_987, UInt<1>("h01"), _T_990) @[lib.scala 104:23] + _T_858[18] <= _T_991 @[lib.scala 104:17] + node _T_992 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 104:28] + node _T_993 = andr(_T_992) @[lib.scala 104:36] + node _T_994 = and(_T_993, _T_861) @[lib.scala 104:41] + node _T_995 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 104:74] + node _T_996 = bits(lsu_match_data_3, 19, 19) @[lib.scala 104:86] + node _T_997 = eq(_T_995, _T_996) @[lib.scala 104:78] + node _T_998 = mux(_T_994, UInt<1>("h01"), _T_997) @[lib.scala 104:23] + _T_858[19] <= _T_998 @[lib.scala 104:17] + node _T_999 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 104:28] + node _T_1000 = andr(_T_999) @[lib.scala 104:36] + node _T_1001 = and(_T_1000, _T_861) @[lib.scala 104:41] + node _T_1002 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 104:74] + node _T_1003 = bits(lsu_match_data_3, 20, 20) @[lib.scala 104:86] + node _T_1004 = eq(_T_1002, _T_1003) @[lib.scala 104:78] + node _T_1005 = mux(_T_1001, UInt<1>("h01"), _T_1004) @[lib.scala 104:23] + _T_858[20] <= _T_1005 @[lib.scala 104:17] + node _T_1006 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 104:28] + node _T_1007 = andr(_T_1006) @[lib.scala 104:36] + node _T_1008 = and(_T_1007, _T_861) @[lib.scala 104:41] + node _T_1009 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 104:74] + node _T_1010 = bits(lsu_match_data_3, 21, 21) @[lib.scala 104:86] + node _T_1011 = eq(_T_1009, _T_1010) @[lib.scala 104:78] + node _T_1012 = mux(_T_1008, UInt<1>("h01"), _T_1011) @[lib.scala 104:23] + _T_858[21] <= _T_1012 @[lib.scala 104:17] + node _T_1013 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 104:28] + node _T_1014 = andr(_T_1013) @[lib.scala 104:36] + node _T_1015 = and(_T_1014, _T_861) @[lib.scala 104:41] + node _T_1016 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 104:74] + node _T_1017 = bits(lsu_match_data_3, 22, 22) @[lib.scala 104:86] + node _T_1018 = eq(_T_1016, _T_1017) @[lib.scala 104:78] + node _T_1019 = mux(_T_1015, UInt<1>("h01"), _T_1018) @[lib.scala 104:23] + _T_858[22] <= _T_1019 @[lib.scala 104:17] + node _T_1020 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 104:28] + node _T_1021 = andr(_T_1020) @[lib.scala 104:36] + node _T_1022 = and(_T_1021, _T_861) @[lib.scala 104:41] + node _T_1023 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 104:74] + node _T_1024 = bits(lsu_match_data_3, 23, 23) @[lib.scala 104:86] + node _T_1025 = eq(_T_1023, _T_1024) @[lib.scala 104:78] + node _T_1026 = mux(_T_1022, UInt<1>("h01"), _T_1025) @[lib.scala 104:23] + _T_858[23] <= _T_1026 @[lib.scala 104:17] + node _T_1027 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 104:28] + node _T_1028 = andr(_T_1027) @[lib.scala 104:36] + node _T_1029 = and(_T_1028, _T_861) @[lib.scala 104:41] + node _T_1030 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 104:74] + node _T_1031 = bits(lsu_match_data_3, 24, 24) @[lib.scala 104:86] + node _T_1032 = eq(_T_1030, _T_1031) @[lib.scala 104:78] + node _T_1033 = mux(_T_1029, UInt<1>("h01"), _T_1032) @[lib.scala 104:23] + _T_858[24] <= _T_1033 @[lib.scala 104:17] + node _T_1034 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 104:28] + node _T_1035 = andr(_T_1034) @[lib.scala 104:36] + node _T_1036 = and(_T_1035, _T_861) @[lib.scala 104:41] + node _T_1037 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 104:74] + node _T_1038 = bits(lsu_match_data_3, 25, 25) @[lib.scala 104:86] + node _T_1039 = eq(_T_1037, _T_1038) @[lib.scala 104:78] + node _T_1040 = mux(_T_1036, UInt<1>("h01"), _T_1039) @[lib.scala 104:23] + _T_858[25] <= _T_1040 @[lib.scala 104:17] + node _T_1041 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 104:28] + node _T_1042 = andr(_T_1041) @[lib.scala 104:36] + node _T_1043 = and(_T_1042, _T_861) @[lib.scala 104:41] + node _T_1044 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 104:74] + node _T_1045 = bits(lsu_match_data_3, 26, 26) @[lib.scala 104:86] + node _T_1046 = eq(_T_1044, _T_1045) @[lib.scala 104:78] + node _T_1047 = mux(_T_1043, UInt<1>("h01"), _T_1046) @[lib.scala 104:23] + _T_858[26] <= _T_1047 @[lib.scala 104:17] + node _T_1048 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 104:28] + node _T_1049 = andr(_T_1048) @[lib.scala 104:36] + node _T_1050 = and(_T_1049, _T_861) @[lib.scala 104:41] + node _T_1051 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 104:74] + node _T_1052 = bits(lsu_match_data_3, 27, 27) @[lib.scala 104:86] + node _T_1053 = eq(_T_1051, _T_1052) @[lib.scala 104:78] + node _T_1054 = mux(_T_1050, UInt<1>("h01"), _T_1053) @[lib.scala 104:23] + _T_858[27] <= _T_1054 @[lib.scala 104:17] + node _T_1055 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 104:28] + node _T_1056 = andr(_T_1055) @[lib.scala 104:36] + node _T_1057 = and(_T_1056, _T_861) @[lib.scala 104:41] + node _T_1058 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 104:74] + node _T_1059 = bits(lsu_match_data_3, 28, 28) @[lib.scala 104:86] + node _T_1060 = eq(_T_1058, _T_1059) @[lib.scala 104:78] + node _T_1061 = mux(_T_1057, UInt<1>("h01"), _T_1060) @[lib.scala 104:23] + _T_858[28] <= _T_1061 @[lib.scala 104:17] + node _T_1062 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 104:28] + node _T_1063 = andr(_T_1062) @[lib.scala 104:36] + node _T_1064 = and(_T_1063, _T_861) @[lib.scala 104:41] + node _T_1065 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 104:74] + node _T_1066 = bits(lsu_match_data_3, 29, 29) @[lib.scala 104:86] + node _T_1067 = eq(_T_1065, _T_1066) @[lib.scala 104:78] + node _T_1068 = mux(_T_1064, UInt<1>("h01"), _T_1067) @[lib.scala 104:23] + _T_858[29] <= _T_1068 @[lib.scala 104:17] + node _T_1069 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 104:28] + node _T_1070 = andr(_T_1069) @[lib.scala 104:36] + node _T_1071 = and(_T_1070, _T_861) @[lib.scala 104:41] + node _T_1072 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 104:74] + node _T_1073 = bits(lsu_match_data_3, 30, 30) @[lib.scala 104:86] + node _T_1074 = eq(_T_1072, _T_1073) @[lib.scala 104:78] + node _T_1075 = mux(_T_1071, UInt<1>("h01"), _T_1074) @[lib.scala 104:23] + _T_858[30] <= _T_1075 @[lib.scala 104:17] + node _T_1076 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 104:28] + node _T_1077 = andr(_T_1076) @[lib.scala 104:36] + node _T_1078 = and(_T_1077, _T_861) @[lib.scala 104:41] + node _T_1079 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 104:74] + node _T_1080 = bits(lsu_match_data_3, 31, 31) @[lib.scala 104:86] + node _T_1081 = eq(_T_1079, _T_1080) @[lib.scala 104:78] + node _T_1082 = mux(_T_1078, UInt<1>("h01"), _T_1081) @[lib.scala 104:23] + _T_858[31] <= _T_1082 @[lib.scala 104:17] + node _T_1083 = cat(_T_858[1], _T_858[0]) @[lib.scala 105:14] + node _T_1084 = cat(_T_858[3], _T_858[2]) @[lib.scala 105:14] + node _T_1085 = cat(_T_1084, _T_1083) @[lib.scala 105:14] + node _T_1086 = cat(_T_858[5], _T_858[4]) @[lib.scala 105:14] + node _T_1087 = cat(_T_858[7], _T_858[6]) @[lib.scala 105:14] + node _T_1088 = cat(_T_1087, _T_1086) @[lib.scala 105:14] + node _T_1089 = cat(_T_1088, _T_1085) @[lib.scala 105:14] + node _T_1090 = cat(_T_858[9], _T_858[8]) @[lib.scala 105:14] + node _T_1091 = cat(_T_858[11], _T_858[10]) @[lib.scala 105:14] + node _T_1092 = cat(_T_1091, _T_1090) @[lib.scala 105:14] + node _T_1093 = cat(_T_858[13], _T_858[12]) @[lib.scala 105:14] + node _T_1094 = cat(_T_858[15], _T_858[14]) @[lib.scala 105:14] + node _T_1095 = cat(_T_1094, _T_1093) @[lib.scala 105:14] + node _T_1096 = cat(_T_1095, _T_1092) @[lib.scala 105:14] + node _T_1097 = cat(_T_1096, _T_1089) @[lib.scala 105:14] + node _T_1098 = cat(_T_858[17], _T_858[16]) @[lib.scala 105:14] + node _T_1099 = cat(_T_858[19], _T_858[18]) @[lib.scala 105:14] + node _T_1100 = cat(_T_1099, _T_1098) @[lib.scala 105:14] + node _T_1101 = cat(_T_858[21], _T_858[20]) @[lib.scala 105:14] + node _T_1102 = cat(_T_858[23], _T_858[22]) @[lib.scala 105:14] + node _T_1103 = cat(_T_1102, _T_1101) @[lib.scala 105:14] + node _T_1104 = cat(_T_1103, _T_1100) @[lib.scala 105:14] + node _T_1105 = cat(_T_858[25], _T_858[24]) @[lib.scala 105:14] + node _T_1106 = cat(_T_858[27], _T_858[26]) @[lib.scala 105:14] + node _T_1107 = cat(_T_1106, _T_1105) @[lib.scala 105:14] + node _T_1108 = cat(_T_858[29], _T_858[28]) @[lib.scala 105:14] + node _T_1109 = cat(_T_858[31], _T_858[30]) @[lib.scala 105:14] + node _T_1110 = cat(_T_1109, _T_1108) @[lib.scala 105:14] + node _T_1111 = cat(_T_1110, _T_1107) @[lib.scala 105:14] + node _T_1112 = cat(_T_1111, _T_1104) @[lib.scala 105:14] + node _T_1113 = cat(_T_1112, _T_1097) @[lib.scala 105:14] + node _T_1114 = andr(_T_1113) @[lib.scala 105:25] + node _T_1115 = and(_T_856, _T_1114) @[lsu_trigger.scala 21:92] + node _T_1116 = cat(_T_1115, _T_847) @[Cat.scala 29:58] + node _T_1117 = cat(_T_1116, _T_579) @[Cat.scala 29:58] + node _T_1118 = cat(_T_1117, _T_311) @[Cat.scala 29:58] + io.lsu_trigger_match_m <= _T_1118 @[lsu_trigger.scala 20:25] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_clkdomain : + input clock : Clock + input reset : AsyncReset + output io : {flip active_clk : Clock, flip clk_override : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_bus_obuf_c1_clken : UInt<1>, lsu_busm_clken : UInt<1>, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>} + + wire lsu_c1_m_clken_q : UInt<1> @[lsu_clkdomain.scala 60:36] + wire lsu_c1_r_clken_q : UInt<1> @[lsu_clkdomain.scala 61:36] + wire lsu_free_c1_clken_q : UInt<1> @[lsu_clkdomain.scala 62:36] + node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[lsu_clkdomain.scala 64:47] + node lsu_c1_m_clken = or(_T, io.clk_override) @[lsu_clkdomain.scala 64:65] + node _T_1 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 65:51] + node lsu_c1_r_clken = or(_T_1, io.clk_override) @[lsu_clkdomain.scala 65:70] + node _T_2 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 67:47] + node lsu_c2_m_clken = or(_T_2, io.clk_override) @[lsu_clkdomain.scala 67:66] + node _T_3 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[lsu_clkdomain.scala 68:47] + node lsu_c2_r_clken = or(_T_3, io.clk_override) @[lsu_clkdomain.scala 68:66] + node _T_4 = and(lsu_c1_m_clken, io.lsu_pkt_d.bits.store) @[lsu_clkdomain.scala 70:49] + node lsu_store_c1_m_clken = or(_T_4, io.clk_override) @[lsu_clkdomain.scala 70:76] + node _T_5 = and(lsu_c1_r_clken, io.lsu_pkt_m.bits.store) @[lsu_clkdomain.scala 71:49] + node lsu_store_c1_r_clken = or(_T_5, io.clk_override) @[lsu_clkdomain.scala 71:76] + node _T_6 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[lsu_clkdomain.scala 72:55] + node _T_7 = or(_T_6, io.stbuf_reqvld_flushed_any) @[lsu_clkdomain.scala 72:77] + node lsu_stbuf_c1_clken = or(_T_7, io.clk_override) @[lsu_clkdomain.scala 72:107] + node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[lsu_clkdomain.scala 73:49] + node _T_8 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[lsu_clkdomain.scala 74:62] + node _T_9 = or(_T_8, io.clk_override) @[lsu_clkdomain.scala 74:80] + node _T_10 = and(_T_9, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 74:99] + io.lsu_bus_obuf_c1_clken <= _T_10 @[lsu_clkdomain.scala 74:30] + node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 75:32] + node _T_12 = or(_T_11, io.lsu_busreq_r) @[lsu_clkdomain.scala 75:61] + node _T_13 = or(_T_12, io.dec_tlu_force_halt) @[lsu_clkdomain.scala 75:79] + node lsu_bus_buf_c1_clken = or(_T_13, io.clk_override) @[lsu_clkdomain.scala 75:103] + node _T_14 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[lsu_clkdomain.scala 77:48] + node _T_15 = or(_T_14, io.lsu_pkt_m.valid) @[lsu_clkdomain.scala 77:69] + node _T_16 = or(_T_15, io.lsu_pkt_r.valid) @[lsu_clkdomain.scala 77:90] + node _T_17 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:114] + node _T_18 = or(_T_16, _T_17) @[lsu_clkdomain.scala 77:112] + node _T_19 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:145] + node _T_20 = or(_T_18, _T_19) @[lsu_clkdomain.scala 77:143] + node lsu_free_c1_clken = or(_T_20, io.clk_override) @[lsu_clkdomain.scala 77:169] + node _T_21 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[lsu_clkdomain.scala 78:50] + node lsu_free_c2_clken = or(_T_21, io.clk_override) @[lsu_clkdomain.scala 78:72] + node _T_22 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 79:25] + node _T_23 = or(_T_22, io.lsu_busreq_r) @[lsu_clkdomain.scala 79:54] + node _T_24 = or(_T_23, io.clk_override) @[lsu_clkdomain.scala 79:72] + node _T_25 = and(_T_24, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 79:91] + io.lsu_busm_clken <= _T_25 @[lsu_clkdomain.scala 79:21] + reg _T_26 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 82:62] + _T_26 <= lsu_free_c1_clken @[lsu_clkdomain.scala 82:62] + lsu_free_c1_clken_q <= _T_26 @[lsu_clkdomain.scala 82:26] + reg _T_27 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 84:67] + _T_27 <= lsu_c1_m_clken @[lsu_clkdomain.scala 84:67] + lsu_c1_m_clken_q <= _T_27 @[lsu_clkdomain.scala 84:26] + reg _T_28 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 85:67] + _T_28 <= lsu_c1_r_clken @[lsu_clkdomain.scala 85:67] + lsu_c1_r_clken_q <= _T_28 @[lsu_clkdomain.scala 85:26] + node _T_29 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 87:60] + io.lsu_c1_m_clk <= clock @[lsu_clkdomain.scala 87:26] + node _T_30 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 88:60] + io.lsu_c1_r_clk <= clock @[lsu_clkdomain.scala 88:26] + node _T_31 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 89:60] + io.lsu_c2_m_clk <= clock @[lsu_clkdomain.scala 89:26] + node _T_32 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 90:60] + io.lsu_c2_r_clk <= clock @[lsu_clkdomain.scala 90:26] + node _T_33 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 91:66] + io.lsu_store_c1_m_clk <= clock @[lsu_clkdomain.scala 91:26] + node _T_34 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 92:66] + io.lsu_store_c1_r_clk <= clock @[lsu_clkdomain.scala 92:26] + node _T_35 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:64] + io.lsu_stbuf_c1_clk <= clock @[lsu_clkdomain.scala 93:26] + node _T_36 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:67] + io.lsu_bus_ibuf_c1_clk <= clock @[lsu_clkdomain.scala 94:26] + node _T_37 = bits(io.lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 95:69] + inst rvclkhdr of rvclkhdr_20 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= _T_37 @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] + io.lsu_bus_obuf_c1_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 95:26] + node _T_38 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 96:66] + io.lsu_bus_buf_c1_clk <= clock @[lsu_clkdomain.scala 96:26] + node _T_39 = bits(io.lsu_busm_clken, 0, 0) @[lsu_clkdomain.scala 97:62] + inst rvclkhdr_1 of rvclkhdr_21 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_39 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] + io.lsu_busm_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 97:26] + node _T_40 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 98:63] + io.lsu_free_c2_clk <= clock @[lsu_clkdomain.scala 98:26] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_27 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_28 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_29 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_30 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_31 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_31 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_31 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_32 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_32 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_32 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_33 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_33 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_33 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_bus_buffer : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_nonblock_load_data : UInt<32>} + + wire buf_addr : UInt<32>[4] @[lsu_bus_buffer.scala 71:22] + wire buf_state : UInt<3>[4] @[lsu_bus_buffer.scala 72:23] + wire buf_write : UInt<4> + buf_write <= UInt<1>("h00") + wire CmdPtr0 : UInt<2> + CmdPtr0 <= UInt<1>("h00") + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[lsu_bus_buffer.scala 77:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[lsu_bus_buffer.scala 78:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_2 = eq(_T, _T_1) @[lsu_bus_buffer.scala 80:74] + node _T_3 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 80:109] + node _T_4 = and(_T_2, _T_3) @[lsu_bus_buffer.scala 80:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_6 = and(_T_4, _T_5) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_9 = eq(_T_7, _T_8) @[lsu_bus_buffer.scala 80:74] + node _T_10 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 80:109] + node _T_11 = and(_T_9, _T_10) @[lsu_bus_buffer.scala 80:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_13 = and(_T_11, _T_12) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_16 = eq(_T_14, _T_15) @[lsu_bus_buffer.scala 80:74] + node _T_17 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 80:109] + node _T_18 = and(_T_16, _T_17) @[lsu_bus_buffer.scala 80:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_20 = and(_T_18, _T_19) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_23 = eq(_T_21, _T_22) @[lsu_bus_buffer.scala 80:74] + node _T_24 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 80:109] + node _T_25 = and(_T_23, _T_24) @[lsu_bus_buffer.scala 80:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_27 = and(_T_25, _T_26) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_30 = eq(_T_28, _T_29) @[lsu_bus_buffer.scala 81:74] + node _T_31 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 81:109] + node _T_32 = and(_T_30, _T_31) @[lsu_bus_buffer.scala 81:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_34 = and(_T_32, _T_33) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_37 = eq(_T_35, _T_36) @[lsu_bus_buffer.scala 81:74] + node _T_38 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 81:109] + node _T_39 = and(_T_37, _T_38) @[lsu_bus_buffer.scala 81:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_41 = and(_T_39, _T_40) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_44 = eq(_T_42, _T_43) @[lsu_bus_buffer.scala 81:74] + node _T_45 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 81:109] + node _T_46 = and(_T_44, _T_45) @[lsu_bus_buffer.scala 81:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_48 = and(_T_46, _T_47) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_51 = eq(_T_49, _T_50) @[lsu_bus_buffer.scala 81:74] + node _T_52 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 81:109] + node _T_53 = and(_T_51, _T_52) @[lsu_bus_buffer.scala 81:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_55 = and(_T_53, _T_54) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[lsu_bus_buffer.scala 82:33] + wire ld_byte_ibuf_hit_lo : UInt<4> + ld_byte_ibuf_hit_lo <= UInt<1>("h00") + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[lsu_bus_buffer.scala 84:33] + wire ld_byte_ibuf_hit_hi : UInt<4> + ld_byte_ibuf_hit_hi <= UInt<1>("h00") + wire buf_byteen : UInt<4>[4] @[lsu_bus_buffer.scala 86:24] + buf_byteen[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + wire buf_nxtstate : UInt<3>[4] @[lsu_bus_buffer.scala 88:26] + buf_nxtstate[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + wire buf_wr_en : UInt<1>[4] @[lsu_bus_buffer.scala 90:23] + buf_wr_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + wire buf_data_en : UInt<1>[4] @[lsu_bus_buffer.scala 92:25] + buf_data_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + wire buf_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 94:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + wire buf_ldfwd_in : UInt<1>[4] @[lsu_bus_buffer.scala 96:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + wire buf_ldfwd_en : UInt<1>[4] @[lsu_bus_buffer.scala 98:26] + buf_ldfwd_en[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + wire buf_data_in : UInt<32>[4] @[lsu_bus_buffer.scala 100:25] + buf_data_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 102:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + wire buf_error_en : UInt<1>[4] @[lsu_bus_buffer.scala 104:26] + buf_error_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + wire bus_rsp_read_error : UInt<1> + bus_rsp_read_error <= UInt<1>("h00") + wire bus_rsp_rdata : UInt<64> + bus_rsp_rdata <= UInt<1>("h00") + wire bus_rsp_write_error : UInt<1> + bus_rsp_write_error <= UInt<1>("h00") + wire buf_dualtag : UInt<2>[4] @[lsu_bus_buffer.scala 109:25] + buf_dualtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + wire buf_ldfwd : UInt<4> + buf_ldfwd <= UInt<1>("h00") + wire buf_resp_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 112:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + wire any_done_wait_state : UInt<1> + any_done_wait_state <= UInt<1>("h00") + wire bus_rsp_write : UInt<1> + bus_rsp_write <= UInt<1>("h00") + wire bus_rsp_write_tag : UInt<3> + bus_rsp_write_tag <= UInt<1>("h00") + wire buf_ldfwdtag : UInt<2>[4] @[lsu_bus_buffer.scala 117:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + wire buf_rst : UInt<1>[4] @[lsu_bus_buffer.scala 119:21] + buf_rst[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + wire ibuf_drainvec_vld : UInt<4> + ibuf_drainvec_vld <= UInt<1>("h00") + wire buf_byteen_in : UInt<4>[4] @[lsu_bus_buffer.scala 122:27] + buf_byteen_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + wire buf_addr_in : UInt<32>[4] @[lsu_bus_buffer.scala 124:25] + buf_addr_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + wire buf_dual_in : UInt<4> + buf_dual_in <= UInt<1>("h00") + wire buf_samedw_in : UInt<4> + buf_samedw_in <= UInt<1>("h00") + wire buf_nomerge_in : UInt<4> + buf_nomerge_in <= UInt<1>("h00") + wire buf_dualhi_in : UInt<4> + buf_dualhi_in <= UInt<1>("h00") + wire buf_dualtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 130:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + wire buf_sideeffect_in : UInt<4> + buf_sideeffect_in <= UInt<1>("h00") + wire buf_unsign_in : UInt<4> + buf_unsign_in <= UInt<1>("h00") + wire buf_sz_in : UInt<2>[4] @[lsu_bus_buffer.scala 134:23] + buf_sz_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + wire buf_write_in : UInt<4> + buf_write_in <= UInt<1>("h00") + wire buf_unsign : UInt<4> + buf_unsign <= UInt<1>("h00") + wire buf_error : UInt<4> + buf_error <= UInt<1>("h00") + wire CmdPtr1 : UInt<2> + CmdPtr1 <= UInt<1>("h00") + wire ibuf_data : UInt<32> + ibuf_data <= UInt<1>("h00") + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[lsu_bus_buffer.scala 142:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 142:98] + node _T_58 = or(_T_56, _T_57) @[lsu_bus_buffer.scala 142:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[lsu_bus_buffer.scala 142:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 142:98] + node _T_61 = or(_T_59, _T_60) @[lsu_bus_buffer.scala 142:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[lsu_bus_buffer.scala 142:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 142:98] + node _T_64 = or(_T_62, _T_63) @[lsu_bus_buffer.scala 142:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[lsu_bus_buffer.scala 142:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 142:98] + node _T_67 = or(_T_65, _T_66) @[lsu_bus_buffer.scala 142:77] + node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] + io.ld_byte_hit_buf_lo <= _T_70 @[lsu_bus_buffer.scala 142:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[lsu_bus_buffer.scala 143:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 143:98] + node _T_73 = or(_T_71, _T_72) @[lsu_bus_buffer.scala 143:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[lsu_bus_buffer.scala 143:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 143:98] + node _T_76 = or(_T_74, _T_75) @[lsu_bus_buffer.scala 143:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[lsu_bus_buffer.scala 143:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 143:98] + node _T_79 = or(_T_77, _T_78) @[lsu_bus_buffer.scala 143:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[lsu_bus_buffer.scala 143:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 143:98] + node _T_82 = or(_T_80, _T_81) @[lsu_bus_buffer.scala 143:77] + node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] + io.ld_byte_hit_buf_hi <= _T_85 @[lsu_bus_buffer.scala 143:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[lsu_bus_buffer.scala 145:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_89 = and(_T_87, _T_88) @[lsu_bus_buffer.scala 145:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[lsu_bus_buffer.scala 145:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_93 = and(_T_91, _T_92) @[lsu_bus_buffer.scala 145:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[lsu_bus_buffer.scala 145:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_97 = and(_T_95, _T_96) @[lsu_bus_buffer.scala 145:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[lsu_bus_buffer.scala 145:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_101 = and(_T_99, _T_100) @[lsu_bus_buffer.scala 145:114] + node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] + node _T_104 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[lsu_bus_buffer.scala 145:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_107 = and(_T_105, _T_106) @[lsu_bus_buffer.scala 145:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[lsu_bus_buffer.scala 145:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_111 = and(_T_109, _T_110) @[lsu_bus_buffer.scala 145:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[lsu_bus_buffer.scala 145:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_115 = and(_T_113, _T_114) @[lsu_bus_buffer.scala 145:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[lsu_bus_buffer.scala 145:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_119 = and(_T_117, _T_118) @[lsu_bus_buffer.scala 145:114] + node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] + node _T_122 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[lsu_bus_buffer.scala 145:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_125 = and(_T_123, _T_124) @[lsu_bus_buffer.scala 145:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[lsu_bus_buffer.scala 145:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_buffer.scala 145:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[lsu_bus_buffer.scala 145:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_buffer.scala 145:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[lsu_bus_buffer.scala 145:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_buffer.scala 145:114] + node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] + node _T_140 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[lsu_bus_buffer.scala 145:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_143 = and(_T_141, _T_142) @[lsu_bus_buffer.scala 145:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[lsu_bus_buffer.scala 145:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_147 = and(_T_145, _T_146) @[lsu_bus_buffer.scala 145:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[lsu_bus_buffer.scala 145:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_151 = and(_T_149, _T_150) @[lsu_bus_buffer.scala 145:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[lsu_bus_buffer.scala 145:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_155 = and(_T_153, _T_154) @[lsu_bus_buffer.scala 145:114] + node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] + node _T_158 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[lsu_bus_buffer.scala 146:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_161 = and(_T_159, _T_160) @[lsu_bus_buffer.scala 146:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[lsu_bus_buffer.scala 146:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_165 = and(_T_163, _T_164) @[lsu_bus_buffer.scala 146:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[lsu_bus_buffer.scala 146:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_169 = and(_T_167, _T_168) @[lsu_bus_buffer.scala 146:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[lsu_bus_buffer.scala 146:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_173 = and(_T_171, _T_172) @[lsu_bus_buffer.scala 146:114] + node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] + node _T_176 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[lsu_bus_buffer.scala 146:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_179 = and(_T_177, _T_178) @[lsu_bus_buffer.scala 146:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[lsu_bus_buffer.scala 146:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_183 = and(_T_181, _T_182) @[lsu_bus_buffer.scala 146:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[lsu_bus_buffer.scala 146:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_187 = and(_T_185, _T_186) @[lsu_bus_buffer.scala 146:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[lsu_bus_buffer.scala 146:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_191 = and(_T_189, _T_190) @[lsu_bus_buffer.scala 146:114] + node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] + node _T_194 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[lsu_bus_buffer.scala 146:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_197 = and(_T_195, _T_196) @[lsu_bus_buffer.scala 146:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[lsu_bus_buffer.scala 146:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_201 = and(_T_199, _T_200) @[lsu_bus_buffer.scala 146:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[lsu_bus_buffer.scala 146:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_205 = and(_T_203, _T_204) @[lsu_bus_buffer.scala 146:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[lsu_bus_buffer.scala 146:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_209 = and(_T_207, _T_208) @[lsu_bus_buffer.scala 146:114] + node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] + node _T_212 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[lsu_bus_buffer.scala 146:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_215 = and(_T_213, _T_214) @[lsu_bus_buffer.scala 146:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[lsu_bus_buffer.scala 146:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_219 = and(_T_217, _T_218) @[lsu_bus_buffer.scala 146:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[lsu_bus_buffer.scala 146:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_223 = and(_T_221, _T_222) @[lsu_bus_buffer.scala 146:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[lsu_bus_buffer.scala 146:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_227 = and(_T_225, _T_226) @[lsu_bus_buffer.scala 146:114] + node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] + node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] + wire buf_age_younger : UInt<4>[4] @[lsu_bus_buffer.scala 148:29] + buf_age_younger[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_232 = orr(_T_231) @[lsu_bus_buffer.scala 150:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_234 = and(_T_230, _T_233) @[lsu_bus_buffer.scala 150:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_237 = and(_T_234, _T_236) @[lsu_bus_buffer.scala 150:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_240 = orr(_T_239) @[lsu_bus_buffer.scala 150:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_242 = and(_T_238, _T_241) @[lsu_bus_buffer.scala 150:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_245 = and(_T_242, _T_244) @[lsu_bus_buffer.scala 150:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_248 = orr(_T_247) @[lsu_bus_buffer.scala 150:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_250 = and(_T_246, _T_249) @[lsu_bus_buffer.scala 150:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_253 = and(_T_250, _T_252) @[lsu_bus_buffer.scala 150:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_256 = orr(_T_255) @[lsu_bus_buffer.scala 150:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_258 = and(_T_254, _T_257) @[lsu_bus_buffer.scala 150:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_261 = and(_T_258, _T_260) @[lsu_bus_buffer.scala 150:148] + node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] + node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] + node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_267 = orr(_T_266) @[lsu_bus_buffer.scala 150:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_269 = and(_T_265, _T_268) @[lsu_bus_buffer.scala 150:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_272 = and(_T_269, _T_271) @[lsu_bus_buffer.scala 150:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_275 = orr(_T_274) @[lsu_bus_buffer.scala 150:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_277 = and(_T_273, _T_276) @[lsu_bus_buffer.scala 150:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_280 = and(_T_277, _T_279) @[lsu_bus_buffer.scala 150:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_283 = orr(_T_282) @[lsu_bus_buffer.scala 150:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_285 = and(_T_281, _T_284) @[lsu_bus_buffer.scala 150:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_288 = and(_T_285, _T_287) @[lsu_bus_buffer.scala 150:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_291 = orr(_T_290) @[lsu_bus_buffer.scala 150:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_293 = and(_T_289, _T_292) @[lsu_bus_buffer.scala 150:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_296 = and(_T_293, _T_295) @[lsu_bus_buffer.scala 150:148] + node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_302 = orr(_T_301) @[lsu_bus_buffer.scala 150:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_304 = and(_T_300, _T_303) @[lsu_bus_buffer.scala 150:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_307 = and(_T_304, _T_306) @[lsu_bus_buffer.scala 150:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_310 = orr(_T_309) @[lsu_bus_buffer.scala 150:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_312 = and(_T_308, _T_311) @[lsu_bus_buffer.scala 150:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_315 = and(_T_312, _T_314) @[lsu_bus_buffer.scala 150:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_318 = orr(_T_317) @[lsu_bus_buffer.scala 150:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_320 = and(_T_316, _T_319) @[lsu_bus_buffer.scala 150:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_323 = and(_T_320, _T_322) @[lsu_bus_buffer.scala 150:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_326 = orr(_T_325) @[lsu_bus_buffer.scala 150:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_328 = and(_T_324, _T_327) @[lsu_bus_buffer.scala 150:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_331 = and(_T_328, _T_330) @[lsu_bus_buffer.scala 150:148] + node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] + node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] + node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_337 = orr(_T_336) @[lsu_bus_buffer.scala 150:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_339 = and(_T_335, _T_338) @[lsu_bus_buffer.scala 150:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_342 = and(_T_339, _T_341) @[lsu_bus_buffer.scala 150:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_345 = orr(_T_344) @[lsu_bus_buffer.scala 150:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_347 = and(_T_343, _T_346) @[lsu_bus_buffer.scala 150:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_350 = and(_T_347, _T_349) @[lsu_bus_buffer.scala 150:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_353 = orr(_T_352) @[lsu_bus_buffer.scala 150:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_355 = and(_T_351, _T_354) @[lsu_bus_buffer.scala 150:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_358 = and(_T_355, _T_357) @[lsu_bus_buffer.scala 150:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_361 = orr(_T_360) @[lsu_bus_buffer.scala 150:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_363 = and(_T_359, _T_362) @[lsu_bus_buffer.scala 150:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_366 = and(_T_363, _T_365) @[lsu_bus_buffer.scala 150:148] + node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] + ld_byte_hitvecfn_lo[0] <= _T_264 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[lsu_bus_buffer.scala 150:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_372 = orr(_T_371) @[lsu_bus_buffer.scala 151:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_374 = and(_T_370, _T_373) @[lsu_bus_buffer.scala 151:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_377 = and(_T_374, _T_376) @[lsu_bus_buffer.scala 151:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_380 = orr(_T_379) @[lsu_bus_buffer.scala 151:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_382 = and(_T_378, _T_381) @[lsu_bus_buffer.scala 151:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_385 = and(_T_382, _T_384) @[lsu_bus_buffer.scala 151:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_388 = orr(_T_387) @[lsu_bus_buffer.scala 151:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_390 = and(_T_386, _T_389) @[lsu_bus_buffer.scala 151:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_393 = and(_T_390, _T_392) @[lsu_bus_buffer.scala 151:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_396 = orr(_T_395) @[lsu_bus_buffer.scala 151:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_398 = and(_T_394, _T_397) @[lsu_bus_buffer.scala 151:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_401 = and(_T_398, _T_400) @[lsu_bus_buffer.scala 151:148] + node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_407 = orr(_T_406) @[lsu_bus_buffer.scala 151:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_409 = and(_T_405, _T_408) @[lsu_bus_buffer.scala 151:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_412 = and(_T_409, _T_411) @[lsu_bus_buffer.scala 151:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_415 = orr(_T_414) @[lsu_bus_buffer.scala 151:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_417 = and(_T_413, _T_416) @[lsu_bus_buffer.scala 151:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_420 = and(_T_417, _T_419) @[lsu_bus_buffer.scala 151:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_423 = orr(_T_422) @[lsu_bus_buffer.scala 151:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_425 = and(_T_421, _T_424) @[lsu_bus_buffer.scala 151:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_428 = and(_T_425, _T_427) @[lsu_bus_buffer.scala 151:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_431 = orr(_T_430) @[lsu_bus_buffer.scala 151:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_433 = and(_T_429, _T_432) @[lsu_bus_buffer.scala 151:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_436 = and(_T_433, _T_435) @[lsu_bus_buffer.scala 151:148] + node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] + node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_442 = orr(_T_441) @[lsu_bus_buffer.scala 151:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_444 = and(_T_440, _T_443) @[lsu_bus_buffer.scala 151:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_447 = and(_T_444, _T_446) @[lsu_bus_buffer.scala 151:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_450 = orr(_T_449) @[lsu_bus_buffer.scala 151:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_452 = and(_T_448, _T_451) @[lsu_bus_buffer.scala 151:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_455 = and(_T_452, _T_454) @[lsu_bus_buffer.scala 151:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_458 = orr(_T_457) @[lsu_bus_buffer.scala 151:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_460 = and(_T_456, _T_459) @[lsu_bus_buffer.scala 151:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_463 = and(_T_460, _T_462) @[lsu_bus_buffer.scala 151:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_466 = orr(_T_465) @[lsu_bus_buffer.scala 151:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_468 = and(_T_464, _T_467) @[lsu_bus_buffer.scala 151:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_471 = and(_T_468, _T_470) @[lsu_bus_buffer.scala 151:148] + node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_477 = orr(_T_476) @[lsu_bus_buffer.scala 151:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_479 = and(_T_475, _T_478) @[lsu_bus_buffer.scala 151:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_482 = and(_T_479, _T_481) @[lsu_bus_buffer.scala 151:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_485 = orr(_T_484) @[lsu_bus_buffer.scala 151:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_487 = and(_T_483, _T_486) @[lsu_bus_buffer.scala 151:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_490 = and(_T_487, _T_489) @[lsu_bus_buffer.scala 151:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_493 = orr(_T_492) @[lsu_bus_buffer.scala 151:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_495 = and(_T_491, _T_494) @[lsu_bus_buffer.scala 151:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_498 = and(_T_495, _T_497) @[lsu_bus_buffer.scala 151:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_501 = orr(_T_500) @[lsu_bus_buffer.scala 151:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_503 = and(_T_499, _T_502) @[lsu_bus_buffer.scala 151:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_506 = and(_T_503, _T_505) @[lsu_bus_buffer.scala 151:148] + node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] + node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] + ld_byte_hitvecfn_hi[0] <= _T_404 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[lsu_bus_buffer.scala 151:23] + wire ibuf_addr : UInt<32> + ibuf_addr <= UInt<1>("h00") + wire ibuf_write : UInt<1> + ibuf_write <= UInt<1>("h00") + wire ibuf_valid : UInt<1> + ibuf_valid <= UInt<1>("h00") + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 156:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 156:64] + node _T_512 = eq(_T_510, _T_511) @[lsu_bus_buffer.scala 156:51] + node _T_513 = and(_T_512, ibuf_write) @[lsu_bus_buffer.scala 156:73] + node _T_514 = and(_T_513, ibuf_valid) @[lsu_bus_buffer.scala 156:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[lsu_bus_buffer.scala 156:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 157:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 157:64] + node _T_517 = eq(_T_515, _T_516) @[lsu_bus_buffer.scala 157:51] + node _T_518 = and(_T_517, ibuf_write) @[lsu_bus_buffer.scala 157:73] + node _T_519 = and(_T_518, ibuf_valid) @[lsu_bus_buffer.scala 157:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[lsu_bus_buffer.scala 157:99] + wire ibuf_byteen : UInt<4> + ibuf_byteen <= UInt<1>("h00") + node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] + node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_522 = and(_T_521, ibuf_byteen) @[lsu_bus_buffer.scala 161:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[lsu_bus_buffer.scala 161:69] + ld_byte_ibuf_hit_lo <= _T_523 @[lsu_bus_buffer.scala 161:23] + node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(_T_525, ibuf_byteen) @[lsu_bus_buffer.scala 162:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[lsu_bus_buffer.scala 162:69] + ld_byte_ibuf_hit_hi <= _T_527 @[lsu_bus_buffer.scala 162:23] + wire buf_data : UInt<32>[4] @[lsu_bus_buffer.scala 164:22] + buf_data[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + wire fwd_data : UInt<32> + fwd_data <= UInt<1>("h00") + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 167:81] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 167:81] + node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] + node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 167:81] + node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] + node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 167:81] + node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] + node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] + node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] + node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 168:81] + node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 168:81] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 168:81] + node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] + node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 168:81] + node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] + node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] + node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[lsu_bus_buffer.scala 169:86] + node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] + node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_559 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_560 = and(_T_558, _T_559) @[lsu_bus_buffer.scala 169:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[lsu_bus_buffer.scala 169:86] + node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] + node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_564 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_565 = and(_T_563, _T_564) @[lsu_bus_buffer.scala 169:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[lsu_bus_buffer.scala 169:86] + node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_569 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_570 = and(_T_568, _T_569) @[lsu_bus_buffer.scala 169:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[lsu_bus_buffer.scala 169:86] + node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] + node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_574 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_575 = and(_T_573, _T_574) @[lsu_bus_buffer.scala 169:91] + node _T_576 = or(_T_560, _T_565) @[lsu_bus_buffer.scala 169:123] + node _T_577 = or(_T_576, _T_570) @[lsu_bus_buffer.scala 169:123] + node _T_578 = or(_T_577, _T_575) @[lsu_bus_buffer.scala 169:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[lsu_bus_buffer.scala 170:60] + node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_583 = and(_T_581, _T_582) @[lsu_bus_buffer.scala 170:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[lsu_bus_buffer.scala 170:60] + node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] + node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_587 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_588 = and(_T_586, _T_587) @[lsu_bus_buffer.scala 170:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[lsu_bus_buffer.scala 170:60] + node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] + node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_592 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_593 = and(_T_591, _T_592) @[lsu_bus_buffer.scala 170:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[lsu_bus_buffer.scala 170:60] + node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] + node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_597 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_598 = and(_T_596, _T_597) @[lsu_bus_buffer.scala 170:65] + node _T_599 = or(_T_583, _T_588) @[lsu_bus_buffer.scala 170:97] + node _T_600 = or(_T_599, _T_593) @[lsu_bus_buffer.scala 170:97] + node _T_601 = or(_T_600, _T_598) @[lsu_bus_buffer.scala 170:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[lsu_bus_buffer.scala 171:60] + node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] + node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_605 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_606 = and(_T_604, _T_605) @[lsu_bus_buffer.scala 171:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[lsu_bus_buffer.scala 171:60] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_611 = and(_T_609, _T_610) @[lsu_bus_buffer.scala 171:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[lsu_bus_buffer.scala 171:60] + node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] + node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_615 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_616 = and(_T_614, _T_615) @[lsu_bus_buffer.scala 171:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[lsu_bus_buffer.scala 171:60] + node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_620 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_621 = and(_T_619, _T_620) @[lsu_bus_buffer.scala 171:65] + node _T_622 = or(_T_606, _T_611) @[lsu_bus_buffer.scala 171:97] + node _T_623 = or(_T_622, _T_616) @[lsu_bus_buffer.scala 171:97] + node _T_624 = or(_T_623, _T_621) @[lsu_bus_buffer.scala 171:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[lsu_bus_buffer.scala 172:60] + node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_629 = and(_T_627, _T_628) @[lsu_bus_buffer.scala 172:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[lsu_bus_buffer.scala 172:60] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_634 = and(_T_632, _T_633) @[lsu_bus_buffer.scala 172:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[lsu_bus_buffer.scala 172:60] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_639 = and(_T_637, _T_638) @[lsu_bus_buffer.scala 172:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[lsu_bus_buffer.scala 172:60] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_643 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_644 = and(_T_642, _T_643) @[lsu_bus_buffer.scala 172:65] + node _T_645 = or(_T_629, _T_634) @[lsu_bus_buffer.scala 172:97] + node _T_646 = or(_T_645, _T_639) @[lsu_bus_buffer.scala 172:97] + node _T_647 = or(_T_646, _T_644) @[lsu_bus_buffer.scala 172:97] + node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] + node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[lsu_bus_buffer.scala 173:32] + node _T_652 = or(_T_650, _T_651) @[lsu_bus_buffer.scala 172:103] + io.ld_fwddata_buf_lo <= _T_652 @[lsu_bus_buffer.scala 169:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[lsu_bus_buffer.scala 175:86] + node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] + node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_656 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_657 = and(_T_655, _T_656) @[lsu_bus_buffer.scala 175:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[lsu_bus_buffer.scala 175:86] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_662 = and(_T_660, _T_661) @[lsu_bus_buffer.scala 175:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[lsu_bus_buffer.scala 175:86] + node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] + node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_666 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_667 = and(_T_665, _T_666) @[lsu_bus_buffer.scala 175:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[lsu_bus_buffer.scala 175:86] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_672 = and(_T_670, _T_671) @[lsu_bus_buffer.scala 175:91] + node _T_673 = or(_T_657, _T_662) @[lsu_bus_buffer.scala 175:123] + node _T_674 = or(_T_673, _T_667) @[lsu_bus_buffer.scala 175:123] + node _T_675 = or(_T_674, _T_672) @[lsu_bus_buffer.scala 175:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[lsu_bus_buffer.scala 176:60] + node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] + node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_679 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_680 = and(_T_678, _T_679) @[lsu_bus_buffer.scala 176:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[lsu_bus_buffer.scala 176:60] + node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] + node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_684 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_685 = and(_T_683, _T_684) @[lsu_bus_buffer.scala 176:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[lsu_bus_buffer.scala 176:60] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] + node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_689 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_690 = and(_T_688, _T_689) @[lsu_bus_buffer.scala 176:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[lsu_bus_buffer.scala 176:60] + node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] + node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_694 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_695 = and(_T_693, _T_694) @[lsu_bus_buffer.scala 176:65] + node _T_696 = or(_T_680, _T_685) @[lsu_bus_buffer.scala 176:97] + node _T_697 = or(_T_696, _T_690) @[lsu_bus_buffer.scala 176:97] + node _T_698 = or(_T_697, _T_695) @[lsu_bus_buffer.scala 176:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[lsu_bus_buffer.scala 177:60] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] + node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_702 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_703 = and(_T_701, _T_702) @[lsu_bus_buffer.scala 177:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[lsu_bus_buffer.scala 177:60] + node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] + node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_707 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_708 = and(_T_706, _T_707) @[lsu_bus_buffer.scala 177:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[lsu_bus_buffer.scala 177:60] + node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_713 = and(_T_711, _T_712) @[lsu_bus_buffer.scala 177:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[lsu_bus_buffer.scala 177:60] + node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] + node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_717 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_718 = and(_T_716, _T_717) @[lsu_bus_buffer.scala 177:65] + node _T_719 = or(_T_703, _T_708) @[lsu_bus_buffer.scala 177:97] + node _T_720 = or(_T_719, _T_713) @[lsu_bus_buffer.scala 177:97] + node _T_721 = or(_T_720, _T_718) @[lsu_bus_buffer.scala 177:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[lsu_bus_buffer.scala 178:60] + node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] + node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_725 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_726 = and(_T_724, _T_725) @[lsu_bus_buffer.scala 178:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[lsu_bus_buffer.scala 178:60] + node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] + node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_730 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_731 = and(_T_729, _T_730) @[lsu_bus_buffer.scala 178:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[lsu_bus_buffer.scala 178:60] + node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] + node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_735 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_736 = and(_T_734, _T_735) @[lsu_bus_buffer.scala 178:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[lsu_bus_buffer.scala 178:60] + node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] + node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_740 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_741 = and(_T_739, _T_740) @[lsu_bus_buffer.scala 178:65] + node _T_742 = or(_T_726, _T_731) @[lsu_bus_buffer.scala 178:97] + node _T_743 = or(_T_742, _T_736) @[lsu_bus_buffer.scala 178:97] + node _T_744 = or(_T_743, _T_741) @[lsu_bus_buffer.scala 178:97] + node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] + node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 179:32] + node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 178:103] + io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 175:24] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 181:77] + node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = or(_T_750, _T_751) @[Mux.scala 27:72] + node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_r <= _T_754 @[Mux.scala 27:72] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 186:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[lsu_bus_buffer.scala 186:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 187:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[lsu_bus_buffer.scala 187:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[lsu_bus_buffer.scala 187:60] + node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 188:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[lsu_bus_buffer.scala 188:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[lsu_bus_buffer.scala 188:60] + node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 189:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[lsu_bus_buffer.scala 189:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[lsu_bus_buffer.scala 189:60] + node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] + node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_762, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_766, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = or(_T_769, _T_770) @[Mux.scala 27:72] + node _T_774 = or(_T_773, _T_771) @[Mux.scala 27:72] + node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] + wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 191:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[lsu_bus_buffer.scala 191:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 192:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[lsu_bus_buffer.scala 192:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[lsu_bus_buffer.scala 192:50] + node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 193:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[lsu_bus_buffer.scala 193:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[lsu_bus_buffer.scala 193:50] + node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 194:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[lsu_bus_buffer.scala 194:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[lsu_bus_buffer.scala 194:50] + node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_783, _T_785, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_787, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = or(_T_790, _T_791) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_792) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] + wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 196:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[lsu_bus_buffer.scala 196:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 197:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[lsu_bus_buffer.scala 197:24] + node _T_801 = bits(io.store_data_r, 31, 24) @[lsu_bus_buffer.scala 197:64] + node _T_802 = cat(UInt<24>("h00"), _T_801) @[Cat.scala 29:58] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 198:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[lsu_bus_buffer.scala 198:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[lsu_bus_buffer.scala 198:63] + node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 199:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[lsu_bus_buffer.scala 199:24] + node _T_809 = bits(io.store_data_r, 31, 8) @[lsu_bus_buffer.scala 199:62] + node _T_810 = cat(UInt<8>("h00"), _T_809) @[Cat.scala 29:58] + node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_804, _T_806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_808, _T_810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = or(_T_811, _T_812) @[Mux.scala 27:72] + node _T_816 = or(_T_815, _T_813) @[Mux.scala 27:72] + node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] + wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] + store_data_hi_r <= _T_817 @[Mux.scala 27:72] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 201:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[lsu_bus_buffer.scala 201:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 202:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[lsu_bus_buffer.scala 202:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[lsu_bus_buffer.scala 202:52] + node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 203:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[lsu_bus_buffer.scala 203:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[lsu_bus_buffer.scala 203:52] + node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 204:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[lsu_bus_buffer.scala 204:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[lsu_bus_buffer.scala 204:52] + node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] + node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_834 = mux(_T_825, _T_827, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_835 = mux(_T_829, _T_831, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_836 = or(_T_832, _T_833) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] + wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] + store_data_lo_r <= _T_838 @[Mux.scala 27:72] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[lsu_bus_buffer.scala 207:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[lsu_bus_buffer.scala 207:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[lsu_bus_buffer.scala 207:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 208:72] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[lsu_bus_buffer.scala 208:79] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[lsu_bus_buffer.scala 209:45] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[lsu_bus_buffer.scala 209:31] + node _T_845 = mux(io.lsu_pkt_r.bits.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = mux(io.lsu_pkt_r.bits.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_847 = mux(io.lsu_pkt_r.bits.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_848 = or(_T_845, _T_846) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] + wire is_aligned_r : UInt<1> @[Mux.scala 27:72] + is_aligned_r <= _T_849 @[Mux.scala 27:72] + node _T_850 = or(io.lsu_pkt_r.bits.load, io.no_word_merge_r) @[lsu_bus_buffer.scala 211:60] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[lsu_bus_buffer.scala 211:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 211:84] + node ibuf_byp = and(_T_851, _T_852) @[lsu_bus_buffer.scala 211:82] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 212:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[lsu_bus_buffer.scala 212:56] + node ibuf_wr_en = and(_T_853, _T_854) @[lsu_bus_buffer.scala 212:54] + wire ibuf_drain_vld : UInt<1> + ibuf_drain_vld <= UInt<1>("h00") + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 214:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[lsu_bus_buffer.scala 214:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 214:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 215:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[lsu_bus_buffer.scala 215:42] + node _T_859 = and(_T_858, ibuf_valid) @[lsu_bus_buffer.scala 215:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 215:112] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 215:137] + node _T_862 = neq(_T_860, _T_861) @[lsu_bus_buffer.scala 215:120] + node _T_863 = or(io.lsu_pkt_m.bits.load, _T_862) @[lsu_bus_buffer.scala 215:100] + node ibuf_force_drain = and(_T_859, _T_863) @[lsu_bus_buffer.scala 215:74] + wire ibuf_sideeffect : UInt<1> + ibuf_sideeffect <= UInt<1>("h00") + wire ibuf_timer : UInt<3> + ibuf_timer <= UInt<1>("h00") + wire ibuf_merge_en : UInt<1> + ibuf_merge_en <= UInt<1>("h00") + wire ibuf_merge_in : UInt<1> + ibuf_merge_in <= UInt<1>("h00") + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 220:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[lsu_bus_buffer.scala 220:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 220:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[lsu_bus_buffer.scala 220:82] + node _T_868 = and(_T_865, _T_867) @[lsu_bus_buffer.scala 220:80] + node _T_869 = or(_T_868, ibuf_byp) @[lsu_bus_buffer.scala 221:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[lsu_bus_buffer.scala 221:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[lsu_bus_buffer.scala 221:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 221:55] + node _T_873 = or(_T_871, _T_872) @[lsu_bus_buffer.scala 221:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[lsu_bus_buffer.scala 221:67] + node _T_875 = and(ibuf_valid, _T_874) @[lsu_bus_buffer.scala 220:32] + ibuf_drain_vld <= _T_875 @[lsu_bus_buffer.scala 220:18] + wire ibuf_tag : UInt<2> + ibuf_tag <= UInt<1>("h00") + wire WrPtr1_r : UInt<2> + WrPtr1_r <= UInt<1>("h00") + wire WrPtr0_r : UInt<2> + WrPtr0_r <= UInt<1>("h00") + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 226:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[lsu_bus_buffer.scala 226:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[lsu_bus_buffer.scala 226:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 229:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 230:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[lsu_bus_buffer.scala 230:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 230:95] + node _T_881 = or(_T_879, _T_880) @[lsu_bus_buffer.scala 230:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 231:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 231:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[lsu_bus_buffer.scala 231:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[lsu_bus_buffer.scala 230:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 235:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 235:45] + node _T_888 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 235:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[lsu_bus_buffer.scala 235:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[lsu_bus_buffer.scala 236:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 236:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[lsu_bus_buffer.scala 236:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[lsu_bus_buffer.scala 234:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 235:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 235:45] + node _T_897 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 235:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[lsu_bus_buffer.scala 235:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[lsu_bus_buffer.scala 236:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 236:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[lsu_bus_buffer.scala 236:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[lsu_bus_buffer.scala 234:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 235:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 235:45] + node _T_906 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 235:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[lsu_bus_buffer.scala 235:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[lsu_bus_buffer.scala 236:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 236:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[lsu_bus_buffer.scala 236:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[lsu_bus_buffer.scala 234:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 235:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 235:45] + node _T_915 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 235:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[lsu_bus_buffer.scala 235:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[lsu_bus_buffer.scala 236:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 236:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[lsu_bus_buffer.scala 236:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[lsu_bus_buffer.scala 234:46] + node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] + node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] + node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 237:60] + node _T_924 = bits(_T_923, 0, 0) @[lsu_bus_buffer.scala 237:81] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 237:95] + node _T_926 = tail(_T_925, 1) @[lsu_bus_buffer.scala 237:95] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[lsu_bus_buffer.scala 237:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[lsu_bus_buffer.scala 237:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 239:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 239:54] + node _T_930 = and(_T_929, ibuf_valid) @[lsu_bus_buffer.scala 239:80] + node _T_931 = and(_T_930, ibuf_write) @[lsu_bus_buffer.scala 239:93] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_buffer.scala 239:122] + node _T_933 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 239:142] + node _T_934 = eq(_T_932, _T_933) @[lsu_bus_buffer.scala 239:129] + node _T_935 = and(_T_931, _T_934) @[lsu_bus_buffer.scala 239:106] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 239:152] + node _T_937 = and(_T_935, _T_936) @[lsu_bus_buffer.scala 239:150] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 239:175] + node _T_939 = and(_T_937, _T_938) @[lsu_bus_buffer.scala 239:173] + ibuf_merge_en <= _T_939 @[lsu_bus_buffer.scala 239:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 240:20] + ibuf_merge_in <= _T_940 @[lsu_bus_buffer.scala 240:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[lsu_bus_buffer.scala 241:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 241:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 241:114] + node _T_945 = or(_T_943, _T_944) @[lsu_bus_buffer.scala 241:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 241:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[lsu_bus_buffer.scala 241:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[lsu_bus_buffer.scala 241:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 241:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 241:114] + node _T_952 = or(_T_950, _T_951) @[lsu_bus_buffer.scala 241:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 241:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[lsu_bus_buffer.scala 241:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[lsu_bus_buffer.scala 241:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 241:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 241:114] + node _T_959 = or(_T_957, _T_958) @[lsu_bus_buffer.scala 241:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 241:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[lsu_bus_buffer.scala 241:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[lsu_bus_buffer.scala 241:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 241:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 241:114] + node _T_966 = or(_T_964, _T_965) @[lsu_bus_buffer.scala 241:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 241:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[lsu_bus_buffer.scala 241:48] + node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] + node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] + node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[lsu_bus_buffer.scala 242:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 242:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 242:118] + node _T_975 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 242:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[lsu_bus_buffer.scala 242:81] + node _T_977 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 242:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[lsu_bus_buffer.scala 242:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[lsu_bus_buffer.scala 242:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 242:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 242:118] + node _T_983 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 242:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[lsu_bus_buffer.scala 242:81] + node _T_985 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 242:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[lsu_bus_buffer.scala 242:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[lsu_bus_buffer.scala 242:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 242:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 242:118] + node _T_991 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 242:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[lsu_bus_buffer.scala 242:81] + node _T_993 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 242:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[lsu_bus_buffer.scala 242:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[lsu_bus_buffer.scala 242:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 242:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 242:118] + node _T_999 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 242:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[lsu_bus_buffer.scala 242:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 242:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[lsu_bus_buffer.scala 242:45] + node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] + node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] + node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[lsu_bus_buffer.scala 244:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 244:93] + node _T_1007 = and(_T_1005, _T_1006) @[lsu_bus_buffer.scala 244:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 244:54] + _T_1008 <= _T_1007 @[lsu_bus_buffer.scala 244:54] + ibuf_valid <= _T_1008 @[lsu_bus_buffer.scala 244:14] + reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_tag <= _T_1009 @[lsu_bus_buffer.scala 245:12] + reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_dual : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dual <= io.ldst_dual_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_samedw : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_samedw <= ldst_samedw_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_nomerge : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_nomerge <= io.no_dword_merge_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1010 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_sideeffect <= _T_1010 @[lsu_bus_buffer.scala 250:19] + reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_unsign <= io.lsu_pkt_r.bits.unsign @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1011 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1011 <= io.lsu_pkt_r.bits.store @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_write <= _T_1011 @[lsu_bus_buffer.scala 252:14] + reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr of rvclkhdr_22 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1012 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1012 <= ibuf_addr_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 254:13] + reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 255:15] + inst rvclkhdr_1 of rvclkhdr_23 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1014 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1014 <= ibuf_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 256:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 257:55] + _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 257:55] + ibuf_timer <= _T_1015 @[lsu_bus_buffer.scala 257:14] + wire buf_numvld_wrcmd_any : UInt<4> + buf_numvld_wrcmd_any <= UInt<1>("h00") + wire buf_numvld_cmd_any : UInt<4> + buf_numvld_cmd_any <= UInt<1>("h00") + wire obuf_wr_timer : UInt<3> + obuf_wr_timer <= UInt<1>("h00") + wire buf_nomerge : UInt<1>[4] @[lsu_bus_buffer.scala 261:25] + buf_nomerge[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + wire buf_sideeffect : UInt<4> + buf_sideeffect <= UInt<1>("h00") + wire obuf_force_wr_en : UInt<1> + obuf_force_wr_en <= UInt<1>("h00") + wire obuf_wr_en : UInt<1> + obuf_wr_en <= UInt<1>("h00") + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 267:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 267:72] + node _T_1018 = and(_T_1016, _T_1017) @[lsu_bus_buffer.scala 267:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 267:97] + node _T_1020 = and(_T_1018, _T_1019) @[lsu_bus_buffer.scala 267:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:5] + node _T_1022 = and(_T_1020, _T_1021) @[lsu_bus_buffer.scala 267:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 268:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 268:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 268:114] + node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1030 = mux(_T_1026, buf_nomerge[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1031 = or(_T_1027, _T_1028) @[Mux.scala 27:72] + node _T_1032 = or(_T_1031, _T_1029) @[Mux.scala 27:72] + node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] + wire _T_1034 : UInt<1> @[Mux.scala 27:72] + _T_1034 <= _T_1033 @[Mux.scala 27:72] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:31] + node _T_1036 = and(_T_1022, _T_1035) @[lsu_bus_buffer.scala 268:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 269:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 269:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 269:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 269:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 269:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 269:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 269:111] + node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1048 = mux(_T_1043, _T_1044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1049 = or(_T_1045, _T_1046) @[Mux.scala 27:72] + node _T_1050 = or(_T_1049, _T_1047) @[Mux.scala 27:72] + node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] + wire _T_1052 : UInt<1> @[Mux.scala 27:72] + _T_1052 <= _T_1051 @[Mux.scala 27:72] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:5] + node _T_1054 = and(_T_1036, _T_1053) @[lsu_bus_buffer.scala 268:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[lsu_bus_buffer.scala 269:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[lsu_bus_buffer.scala 270:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 270:95] + node _T_1058 = and(_T_1056, _T_1057) @[lsu_bus_buffer.scala 270:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 270:123] + node _T_1060 = tail(_T_1059, 1) @[lsu_bus_buffer.scala 270:123] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[lsu_bus_buffer.scala 270:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[lsu_bus_buffer.scala 270:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[lsu_bus_buffer.scala 271:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:60] + node _T_1065 = and(_T_1063, _T_1064) @[lsu_bus_buffer.scala 271:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 271:93] + node _T_1067 = and(_T_1065, _T_1066) @[lsu_bus_buffer.scala 271:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 271:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 271:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 271:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 271:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = or(_T_1077, _T_1078) @[Mux.scala 27:72] + node _T_1082 = or(_T_1081, _T_1079) @[Mux.scala 27:72] + node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] + wire _T_1084 : UInt<30> @[Mux.scala 27:72] + _T_1084 <= _T_1083 @[Mux.scala 27:72] + node _T_1085 = neq(_T_1068, _T_1084) @[lsu_bus_buffer.scala 271:123] + node _T_1086 = and(_T_1067, _T_1085) @[lsu_bus_buffer.scala 271:101] + obuf_force_wr_en <= _T_1086 @[lsu_bus_buffer.scala 271:20] + wire buf_numvld_pend_any : UInt<4> + buf_numvld_pend_any <= UInt<1>("h00") + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 273:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[lsu_bus_buffer.scala 273:31] + node _T_1089 = eq(io.lsu_pkt_r.bits.store, UInt<1>("h00")) @[lsu_bus_buffer.scala 273:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[lsu_bus_buffer.scala 273:89] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[lsu_bus_buffer.scala 273:61] + wire bus_sideeffect_pend : UInt<1> + bus_sideeffect_pend <= UInt<1>("h00") + wire found_cmdptr0 : UInt<1> + found_cmdptr0 <= UInt<1>("h00") + wire buf_cmd_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 276:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + wire buf_dual : UInt<1>[4] @[lsu_bus_buffer.scala 278:22] + buf_dual[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + wire buf_samedw : UInt<1>[4] @[lsu_bus_buffer.scala 280:24] + buf_samedw[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + wire found_cmdptr1 : UInt<1> + found_cmdptr1 <= UInt<1>("h00") + wire bus_cmd_ready : UInt<1> + bus_cmd_ready <= UInt<1>("h00") + wire obuf_valid : UInt<1> + obuf_valid <= UInt<1>("h00") + wire obuf_nosend : UInt<1> + obuf_nosend <= UInt<1>("h00") + wire bus_addr_match_pending : UInt<1> + bus_addr_match_pending <= UInt<1>("h00") + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[lsu_bus_buffer.scala 289:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[lsu_bus_buffer.scala 289:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[lsu_bus_buffer.scala 289:52] + node _T_1094 = and(_T_1091, _T_1093) @[lsu_bus_buffer.scala 289:50] + node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1099 = mux(_T_1095, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_1096, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1097, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_1098, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = or(_T_1099, _T_1100) @[Mux.scala 27:72] + node _T_1104 = or(_T_1103, _T_1101) @[Mux.scala 27:72] + node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] + wire _T_1106 : UInt<3> @[Mux.scala 27:72] + _T_1106 <= _T_1105 @[Mux.scala 27:72] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[lsu_bus_buffer.scala 290:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[lsu_bus_buffer.scala 290:47] + node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1113 = bits(_T_1111, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1115 = bits(_T_1111, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1117 = bits(_T_1111, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1119 = bits(_T_1111, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1120 = mux(_T_1112, _T_1113, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1116, _T_1117, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1118, _T_1119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = or(_T_1120, _T_1121) @[Mux.scala 27:72] + node _T_1125 = or(_T_1124, _T_1122) @[Mux.scala 27:72] + node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] + wire _T_1127 : UInt<1> @[Mux.scala 27:72] + _T_1127 <= _T_1126 @[Mux.scala 27:72] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:23] + node _T_1129 = and(_T_1108, _T_1128) @[lsu_bus_buffer.scala 291:21] + node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1131 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1133 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1135 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1137 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1138 = mux(_T_1130, _T_1131, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1139 = mux(_T_1132, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1140 = mux(_T_1134, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1141 = mux(_T_1136, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1142 = or(_T_1138, _T_1139) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1140) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] + wire _T_1145 : UInt<1> @[Mux.scala 27:72] + _T_1145 <= _T_1144 @[Mux.scala 27:72] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[lsu_bus_buffer.scala 291:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:105] + node _T_1148 = and(_T_1129, _T_1147) @[lsu_bus_buffer.scala 291:103] + node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] + node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] + node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1153 = bits(_T_1151, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1155 = bits(_T_1151, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1157 = bits(_T_1151, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1159 = bits(_T_1151, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1160 = mux(_T_1152, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1161 = mux(_T_1154, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1162 = mux(_T_1156, _T_1157, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1163 = mux(_T_1158, _T_1159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1164 = or(_T_1160, _T_1161) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1162) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1163) @[Mux.scala 27:72] + wire _T_1167 : UInt<1> @[Mux.scala 27:72] + _T_1167 <= _T_1166 @[Mux.scala 27:72] + node _T_1168 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1170 = cat(_T_1169, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1172 = bits(_T_1170, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1174 = bits(_T_1170, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1176 = bits(_T_1170, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1178 = bits(_T_1170, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1179 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1180 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1181 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1182 = mux(_T_1177, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1183 = or(_T_1179, _T_1180) @[Mux.scala 27:72] + node _T_1184 = or(_T_1183, _T_1181) @[Mux.scala 27:72] + node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] + wire _T_1186 : UInt<1> @[Mux.scala 27:72] + _T_1186 <= _T_1185 @[Mux.scala 27:72] + node _T_1187 = and(_T_1167, _T_1186) @[lsu_bus_buffer.scala 292:77] + node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1189 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1191 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1193 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1195 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1194, _T_1195, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = or(_T_1196, _T_1197) @[Mux.scala 27:72] + node _T_1201 = or(_T_1200, _T_1198) @[Mux.scala 27:72] + node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] + wire _T_1203 : UInt<1> @[Mux.scala 27:72] + _T_1203 <= _T_1202 @[Mux.scala 27:72] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:150] + node _T_1205 = and(_T_1187, _T_1204) @[lsu_bus_buffer.scala 292:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[lsu_bus_buffer.scala 292:181] + node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] + node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] + node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] + node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1212 = bits(_T_1210, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1214 = bits(_T_1210, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1216 = bits(_T_1210, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1218 = bits(_T_1210, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1219 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = or(_T_1219, _T_1220) @[Mux.scala 27:72] + node _T_1224 = or(_T_1223, _T_1221) @[Mux.scala 27:72] + node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] + wire _T_1226 : UInt<1> @[Mux.scala 27:72] + _T_1226 <= _T_1225 @[Mux.scala 27:72] + node _T_1227 = or(_T_1207, _T_1226) @[lsu_bus_buffer.scala 292:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[lsu_bus_buffer.scala 292:269] + node _T_1229 = and(_T_1148, _T_1228) @[lsu_bus_buffer.scala 291:164] + node _T_1230 = or(_T_1094, _T_1229) @[lsu_bus_buffer.scala 289:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[lsu_bus_buffer.scala 293:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[lsu_bus_buffer.scala 293:60] + node _T_1234 = and(_T_1230, _T_1233) @[lsu_bus_buffer.scala 293:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:77] + node _T_1236 = and(_T_1234, _T_1235) @[lsu_bus_buffer.scala 293:75] + node _T_1237 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:94] + node _T_1238 = and(_T_1236, _T_1237) @[lsu_bus_buffer.scala 293:92] + node _T_1239 = and(_T_1238, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 293:118] + obuf_wr_en <= _T_1239 @[lsu_bus_buffer.scala 289:14] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_1240 = and(obuf_valid, obuf_nosend) @[lsu_bus_buffer.scala 296:47] + node _T_1241 = or(bus_cmd_sent, _T_1240) @[lsu_bus_buffer.scala 296:33] + node _T_1242 = eq(obuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 296:65] + node _T_1243 = and(_T_1241, _T_1242) @[lsu_bus_buffer.scala 296:63] + node _T_1244 = and(_T_1243, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 296:77] + node obuf_rst = or(_T_1244, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 296:98] + node _T_1245 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1246 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1247 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1248 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1249 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1250 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1251 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1252 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1253 = mux(_T_1245, _T_1246, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1254 = mux(_T_1247, _T_1248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1255 = mux(_T_1249, _T_1250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1256 = mux(_T_1251, _T_1252, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1257 = or(_T_1253, _T_1254) @[Mux.scala 27:72] + node _T_1258 = or(_T_1257, _T_1255) @[Mux.scala 27:72] + node _T_1259 = or(_T_1258, _T_1256) @[Mux.scala 27:72] + wire _T_1260 : UInt<1> @[Mux.scala 27:72] + _T_1260 <= _T_1259 @[Mux.scala 27:72] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1260) @[lsu_bus_buffer.scala 297:26] + node _T_1261 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1262 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1263 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1264 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1265 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1266 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1267 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1268 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1269 = mux(_T_1261, _T_1262, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1270 = mux(_T_1263, _T_1264, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1271 = mux(_T_1265, _T_1266, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1272 = mux(_T_1267, _T_1268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1273 = or(_T_1269, _T_1270) @[Mux.scala 27:72] + node _T_1274 = or(_T_1273, _T_1271) @[Mux.scala 27:72] + node _T_1275 = or(_T_1274, _T_1272) @[Mux.scala 27:72] + wire _T_1276 : UInt<1> @[Mux.scala 27:72] + _T_1276 <= _T_1275 @[Mux.scala 27:72] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1276) @[lsu_bus_buffer.scala 298:31] + node _T_1277 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1278 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1279 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1280 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1281 = mux(_T_1277, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1282 = mux(_T_1278, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1283 = mux(_T_1279, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1284 = mux(_T_1280, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1285 = or(_T_1281, _T_1282) @[Mux.scala 27:72] + node _T_1286 = or(_T_1285, _T_1283) @[Mux.scala 27:72] + node _T_1287 = or(_T_1286, _T_1284) @[Mux.scala 27:72] + wire _T_1288 : UInt<32> @[Mux.scala 27:72] + _T_1288 <= _T_1287 @[Mux.scala 27:72] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1288) @[lsu_bus_buffer.scala 299:25] + wire buf_sz : UInt<2>[4] @[lsu_bus_buffer.scala 300:20] + buf_sz[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + node _T_1289 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_1290 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1291 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1292 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1293 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1294 = mux(_T_1290, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1295 = mux(_T_1291, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1296 = mux(_T_1292, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1297 = mux(_T_1293, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1298 = or(_T_1294, _T_1295) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1296) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1297) @[Mux.scala 27:72] + wire _T_1301 : UInt<2> @[Mux.scala 27:72] + _T_1301 <= _T_1300 @[Mux.scala 27:72] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1289, _T_1301) @[lsu_bus_buffer.scala 302:23] + wire obuf_merge_en : UInt<1> + obuf_merge_en <= UInt<1>("h00") + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 305:25] + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 307:25] + wire obuf_cmd_done : UInt<1> + obuf_cmd_done <= UInt<1>("h00") + wire bus_wcmd_sent : UInt<1> + bus_wcmd_sent <= UInt<1>("h00") + node _T_1302 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 310:39] + node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[lsu_bus_buffer.scala 310:26] + node _T_1304 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 310:68] + node obuf_cmd_done_in = and(_T_1303, _T_1304) @[lsu_bus_buffer.scala 310:51] + wire obuf_data_done : UInt<1> + obuf_data_done <= UInt<1>("h00") + wire bus_wdata_sent : UInt<1> + bus_wdata_sent <= UInt<1>("h00") + node _T_1305 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 313:40] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[lsu_bus_buffer.scala 313:27] + node _T_1307 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 313:70] + node obuf_data_done_in = and(_T_1306, _T_1307) @[lsu_bus_buffer.scala 313:52] + node _T_1308 = bits(obuf_sz_in, 1, 0) @[lsu_bus_buffer.scala 314:67] + node _T_1309 = eq(_T_1308, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:72] + node _T_1310 = bits(obuf_sz_in, 0, 0) @[lsu_bus_buffer.scala 314:92] + node _T_1311 = bits(obuf_addr_in, 0, 0) @[lsu_bus_buffer.scala 314:111] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:98] + node _T_1313 = and(_T_1310, _T_1312) @[lsu_bus_buffer.scala 314:96] + node _T_1314 = or(_T_1309, _T_1313) @[lsu_bus_buffer.scala 314:79] + node _T_1315 = bits(obuf_sz_in, 1, 1) @[lsu_bus_buffer.scala 314:129] + node _T_1316 = bits(obuf_addr_in, 1, 0) @[lsu_bus_buffer.scala 314:147] + node _T_1317 = orr(_T_1316) @[lsu_bus_buffer.scala 314:153] + node _T_1318 = eq(_T_1317, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:134] + node _T_1319 = and(_T_1315, _T_1318) @[lsu_bus_buffer.scala 314:132] + node _T_1320 = or(_T_1314, _T_1319) @[lsu_bus_buffer.scala 314:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1320) @[lsu_bus_buffer.scala 314:28] + wire obuf_nosend_in : UInt<1> + obuf_nosend_in <= UInt<1>("h00") + wire obuf_rdrsp_pend : UInt<1> + obuf_rdrsp_pend <= UInt<1>("h00") + wire bus_rsp_read : UInt<1> + bus_rsp_read <= UInt<1>("h00") + wire bus_rsp_read_tag : UInt<3> + bus_rsp_read_tag <= UInt<1>("h00") + wire obuf_rdrsp_tag : UInt<3> + obuf_rdrsp_tag <= UInt<1>("h00") + wire obuf_write : UInt<1> + obuf_write <= UInt<1>("h00") + node _T_1321 = eq(obuf_nosend_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:45] + node _T_1322 = and(obuf_wr_en, _T_1321) @[lsu_bus_buffer.scala 322:43] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:30] + node _T_1324 = and(_T_1323, obuf_rdrsp_pend) @[lsu_bus_buffer.scala 322:62] + node _T_1325 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 322:117] + node _T_1326 = and(bus_rsp_read, _T_1325) @[lsu_bus_buffer.scala 322:97] + node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:82] + node _T_1328 = and(_T_1324, _T_1327) @[lsu_bus_buffer.scala 322:80] + node _T_1329 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:157] + node _T_1330 = and(bus_cmd_sent, _T_1329) @[lsu_bus_buffer.scala 322:155] + node _T_1331 = or(_T_1328, _T_1330) @[lsu_bus_buffer.scala 322:139] + node _T_1332 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:173] + node obuf_rdrsp_pend_in = and(_T_1331, _T_1332) @[lsu_bus_buffer.scala 322:171] + node obuf_rdrsp_pend_en = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 323:47] + wire obuf_tag0 : UInt<3> + obuf_tag0 <= UInt<1>("h00") + node _T_1333 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 325:46] + node _T_1334 = and(bus_cmd_sent, _T_1333) @[lsu_bus_buffer.scala 325:44] + node obuf_rdrsp_tag_in = mux(_T_1334, obuf_tag0, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 325:30] + wire obuf_addr : UInt<32> + obuf_addr <= UInt<1>("h00") + wire obuf_sideeffect : UInt<1> + obuf_sideeffect <= UInt<1>("h00") + node _T_1335 = bits(obuf_addr_in, 31, 3) @[lsu_bus_buffer.scala 328:34] + node _T_1336 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 328:52] + node _T_1337 = eq(_T_1335, _T_1336) @[lsu_bus_buffer.scala 328:40] + node _T_1338 = and(_T_1337, obuf_aligned_in) @[lsu_bus_buffer.scala 328:60] + node _T_1339 = eq(obuf_sideeffect, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:80] + node _T_1340 = and(_T_1338, _T_1339) @[lsu_bus_buffer.scala 328:78] + node _T_1341 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:99] + node _T_1342 = and(_T_1340, _T_1341) @[lsu_bus_buffer.scala 328:97] + node _T_1343 = eq(obuf_write_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:113] + node _T_1344 = and(_T_1342, _T_1343) @[lsu_bus_buffer.scala 328:111] + node _T_1345 = eq(io.tlu_busbuff.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:130] + node _T_1346 = and(_T_1344, _T_1345) @[lsu_bus_buffer.scala 328:128] + node _T_1347 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 329:20] + node _T_1348 = and(obuf_valid, _T_1347) @[lsu_bus_buffer.scala 329:18] + node _T_1349 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 329:90] + node _T_1350 = and(bus_rsp_read, _T_1349) @[lsu_bus_buffer.scala 329:70] + node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[lsu_bus_buffer.scala 329:55] + node _T_1352 = and(obuf_rdrsp_pend, _T_1351) @[lsu_bus_buffer.scala 329:53] + node _T_1353 = or(_T_1348, _T_1352) @[lsu_bus_buffer.scala 329:34] + node _T_1354 = and(_T_1346, _T_1353) @[lsu_bus_buffer.scala 328:177] + obuf_nosend_in <= _T_1354 @[lsu_bus_buffer.scala 328:18] + node _T_1355 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 330:60] + node _T_1356 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1357 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] + node _T_1358 = mux(_T_1355, _T_1356, _T_1357) @[lsu_bus_buffer.scala 330:46] + node _T_1359 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1360 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1361 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1362 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1363 = mux(_T_1359, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1364 = mux(_T_1360, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1365 = mux(_T_1361, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1362, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = or(_T_1363, _T_1364) @[Mux.scala 27:72] + node _T_1368 = or(_T_1367, _T_1365) @[Mux.scala 27:72] + node _T_1369 = or(_T_1368, _T_1366) @[Mux.scala 27:72] + wire _T_1370 : UInt<32> @[Mux.scala 27:72] + _T_1370 <= _T_1369 @[Mux.scala 27:72] + node _T_1371 = bits(_T_1370, 2, 2) @[lsu_bus_buffer.scala 331:36] + node _T_1372 = bits(_T_1371, 0, 0) @[lsu_bus_buffer.scala 331:46] + node _T_1373 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1374 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1375 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1376 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1377 = mux(_T_1373, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1378 = mux(_T_1374, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1379 = mux(_T_1375, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1376, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = or(_T_1377, _T_1378) @[Mux.scala 27:72] + node _T_1382 = or(_T_1381, _T_1379) @[Mux.scala 27:72] + node _T_1383 = or(_T_1382, _T_1380) @[Mux.scala 27:72] + wire _T_1384 : UInt<4> @[Mux.scala 27:72] + _T_1384 <= _T_1383 @[Mux.scala 27:72] + node _T_1385 = cat(_T_1384, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1386 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1387 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1388 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1389 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1390 = mux(_T_1386, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1391 = mux(_T_1387, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1392 = mux(_T_1388, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1393 = mux(_T_1389, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1394 = or(_T_1390, _T_1391) @[Mux.scala 27:72] + node _T_1395 = or(_T_1394, _T_1392) @[Mux.scala 27:72] + node _T_1396 = or(_T_1395, _T_1393) @[Mux.scala 27:72] + wire _T_1397 : UInt<4> @[Mux.scala 27:72] + _T_1397 <= _T_1396 @[Mux.scala 27:72] + node _T_1398 = cat(UInt<4>("h00"), _T_1397) @[Cat.scala 29:58] + node _T_1399 = mux(_T_1372, _T_1385, _T_1398) @[lsu_bus_buffer.scala 331:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1358, _T_1399) @[lsu_bus_buffer.scala 330:28] + node _T_1400 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 332:60] + node _T_1401 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1402 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] + node _T_1403 = mux(_T_1400, _T_1401, _T_1402) @[lsu_bus_buffer.scala 332:46] + node _T_1404 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1405 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1406 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1407 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1408 = mux(_T_1404, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1409 = mux(_T_1405, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1410 = mux(_T_1406, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1411 = mux(_T_1407, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1412 = or(_T_1408, _T_1409) @[Mux.scala 27:72] + node _T_1413 = or(_T_1412, _T_1410) @[Mux.scala 27:72] + node _T_1414 = or(_T_1413, _T_1411) @[Mux.scala 27:72] + wire _T_1415 : UInt<32> @[Mux.scala 27:72] + _T_1415 <= _T_1414 @[Mux.scala 27:72] + node _T_1416 = bits(_T_1415, 2, 2) @[lsu_bus_buffer.scala 333:36] + node _T_1417 = bits(_T_1416, 0, 0) @[lsu_bus_buffer.scala 333:46] + node _T_1418 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1419 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1420 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1421 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1422 = mux(_T_1418, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1423 = mux(_T_1419, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1424 = mux(_T_1420, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1425 = mux(_T_1421, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = or(_T_1422, _T_1423) @[Mux.scala 27:72] + node _T_1427 = or(_T_1426, _T_1424) @[Mux.scala 27:72] + node _T_1428 = or(_T_1427, _T_1425) @[Mux.scala 27:72] + wire _T_1429 : UInt<4> @[Mux.scala 27:72] + _T_1429 <= _T_1428 @[Mux.scala 27:72] + node _T_1430 = cat(_T_1429, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1431 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1432 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1433 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1434 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1435 = mux(_T_1431, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1436 = mux(_T_1432, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1437 = mux(_T_1433, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1438 = mux(_T_1434, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1439 = or(_T_1435, _T_1436) @[Mux.scala 27:72] + node _T_1440 = or(_T_1439, _T_1437) @[Mux.scala 27:72] + node _T_1441 = or(_T_1440, _T_1438) @[Mux.scala 27:72] + wire _T_1442 : UInt<4> @[Mux.scala 27:72] + _T_1442 <= _T_1441 @[Mux.scala 27:72] + node _T_1443 = cat(UInt<4>("h00"), _T_1442) @[Cat.scala 29:58] + node _T_1444 = mux(_T_1417, _T_1430, _T_1443) @[lsu_bus_buffer.scala 333:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1403, _T_1444) @[lsu_bus_buffer.scala 332:28] + node _T_1445 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 335:58] + node _T_1446 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1447 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] + node _T_1448 = mux(_T_1445, _T_1446, _T_1447) @[lsu_bus_buffer.scala 335:44] + node _T_1449 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1450 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1451 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1452 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1453 = mux(_T_1449, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1454 = mux(_T_1450, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1455 = mux(_T_1451, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = mux(_T_1452, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1457 = or(_T_1453, _T_1454) @[Mux.scala 27:72] + node _T_1458 = or(_T_1457, _T_1455) @[Mux.scala 27:72] + node _T_1459 = or(_T_1458, _T_1456) @[Mux.scala 27:72] + wire _T_1460 : UInt<32> @[Mux.scala 27:72] + _T_1460 <= _T_1459 @[Mux.scala 27:72] + node _T_1461 = bits(_T_1460, 2, 2) @[lsu_bus_buffer.scala 336:36] + node _T_1462 = bits(_T_1461, 0, 0) @[lsu_bus_buffer.scala 336:46] + node _T_1463 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1464 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1465 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1466 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1467 = mux(_T_1463, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1468 = mux(_T_1464, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1469 = mux(_T_1465, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1466, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = or(_T_1467, _T_1468) @[Mux.scala 27:72] + node _T_1472 = or(_T_1471, _T_1469) @[Mux.scala 27:72] + node _T_1473 = or(_T_1472, _T_1470) @[Mux.scala 27:72] + wire _T_1474 : UInt<32> @[Mux.scala 27:72] + _T_1474 <= _T_1473 @[Mux.scala 27:72] + node _T_1475 = cat(_T_1474, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1476 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1477 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1478 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1479 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1480 = mux(_T_1476, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1477, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1478, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1479, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = or(_T_1480, _T_1481) @[Mux.scala 27:72] + node _T_1485 = or(_T_1484, _T_1482) @[Mux.scala 27:72] + node _T_1486 = or(_T_1485, _T_1483) @[Mux.scala 27:72] + wire _T_1487 : UInt<32> @[Mux.scala 27:72] + _T_1487 <= _T_1486 @[Mux.scala 27:72] + node _T_1488 = cat(UInt<32>("h00"), _T_1487) @[Cat.scala 29:58] + node _T_1489 = mux(_T_1462, _T_1475, _T_1488) @[lsu_bus_buffer.scala 336:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1448, _T_1489) @[lsu_bus_buffer.scala 335:26] + node _T_1490 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 337:58] + node _T_1491 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1492 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] + node _T_1493 = mux(_T_1490, _T_1491, _T_1492) @[lsu_bus_buffer.scala 337:44] + node _T_1494 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1495 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1496 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1497 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1498 = mux(_T_1494, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1495, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1496, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1497, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = or(_T_1498, _T_1499) @[Mux.scala 27:72] + node _T_1503 = or(_T_1502, _T_1500) @[Mux.scala 27:72] + node _T_1504 = or(_T_1503, _T_1501) @[Mux.scala 27:72] + wire _T_1505 : UInt<32> @[Mux.scala 27:72] + _T_1505 <= _T_1504 @[Mux.scala 27:72] + node _T_1506 = bits(_T_1505, 2, 2) @[lsu_bus_buffer.scala 338:36] + node _T_1507 = bits(_T_1506, 0, 0) @[lsu_bus_buffer.scala 338:46] + node _T_1508 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1509 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1510 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1511 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1512 = mux(_T_1508, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1509, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1510, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1511, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = or(_T_1512, _T_1513) @[Mux.scala 27:72] + node _T_1517 = or(_T_1516, _T_1514) @[Mux.scala 27:72] + node _T_1518 = or(_T_1517, _T_1515) @[Mux.scala 27:72] + wire _T_1519 : UInt<32> @[Mux.scala 27:72] + _T_1519 <= _T_1518 @[Mux.scala 27:72] + node _T_1520 = cat(_T_1519, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1521 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1522 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1523 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1524 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1525 = mux(_T_1521, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1522, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1523, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1524, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = or(_T_1525, _T_1526) @[Mux.scala 27:72] + node _T_1530 = or(_T_1529, _T_1527) @[Mux.scala 27:72] + node _T_1531 = or(_T_1530, _T_1528) @[Mux.scala 27:72] + wire _T_1532 : UInt<32> @[Mux.scala 27:72] + _T_1532 <= _T_1531 @[Mux.scala 27:72] + node _T_1533 = cat(UInt<32>("h00"), _T_1532) @[Cat.scala 29:58] + node _T_1534 = mux(_T_1507, _T_1520, _T_1533) @[lsu_bus_buffer.scala 338:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1493, _T_1534) @[lsu_bus_buffer.scala 337:26] + node _T_1535 = bits(obuf_byteen0_in, 0, 0) @[lsu_bus_buffer.scala 339:59] + node _T_1536 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 339:97] + node _T_1537 = and(obuf_merge_en, _T_1536) @[lsu_bus_buffer.scala 339:80] + node _T_1538 = or(_T_1535, _T_1537) @[lsu_bus_buffer.scala 339:63] + node _T_1539 = bits(obuf_byteen0_in, 1, 1) @[lsu_bus_buffer.scala 339:59] + node _T_1540 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 339:97] + node _T_1541 = and(obuf_merge_en, _T_1540) @[lsu_bus_buffer.scala 339:80] + node _T_1542 = or(_T_1539, _T_1541) @[lsu_bus_buffer.scala 339:63] + node _T_1543 = bits(obuf_byteen0_in, 2, 2) @[lsu_bus_buffer.scala 339:59] + node _T_1544 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 339:97] + node _T_1545 = and(obuf_merge_en, _T_1544) @[lsu_bus_buffer.scala 339:80] + node _T_1546 = or(_T_1543, _T_1545) @[lsu_bus_buffer.scala 339:63] + node _T_1547 = bits(obuf_byteen0_in, 3, 3) @[lsu_bus_buffer.scala 339:59] + node _T_1548 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 339:97] + node _T_1549 = and(obuf_merge_en, _T_1548) @[lsu_bus_buffer.scala 339:80] + node _T_1550 = or(_T_1547, _T_1549) @[lsu_bus_buffer.scala 339:63] + node _T_1551 = bits(obuf_byteen0_in, 4, 4) @[lsu_bus_buffer.scala 339:59] + node _T_1552 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 339:97] + node _T_1553 = and(obuf_merge_en, _T_1552) @[lsu_bus_buffer.scala 339:80] + node _T_1554 = or(_T_1551, _T_1553) @[lsu_bus_buffer.scala 339:63] + node _T_1555 = bits(obuf_byteen0_in, 5, 5) @[lsu_bus_buffer.scala 339:59] + node _T_1556 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 339:97] + node _T_1557 = and(obuf_merge_en, _T_1556) @[lsu_bus_buffer.scala 339:80] + node _T_1558 = or(_T_1555, _T_1557) @[lsu_bus_buffer.scala 339:63] + node _T_1559 = bits(obuf_byteen0_in, 6, 6) @[lsu_bus_buffer.scala 339:59] + node _T_1560 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 339:97] + node _T_1561 = and(obuf_merge_en, _T_1560) @[lsu_bus_buffer.scala 339:80] + node _T_1562 = or(_T_1559, _T_1561) @[lsu_bus_buffer.scala 339:63] + node _T_1563 = bits(obuf_byteen0_in, 7, 7) @[lsu_bus_buffer.scala 339:59] + node _T_1564 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 339:97] + node _T_1565 = and(obuf_merge_en, _T_1564) @[lsu_bus_buffer.scala 339:80] + node _T_1566 = or(_T_1563, _T_1565) @[lsu_bus_buffer.scala 339:63] + node _T_1567 = cat(_T_1566, _T_1562) @[Cat.scala 29:58] + node _T_1568 = cat(_T_1567, _T_1558) @[Cat.scala 29:58] + node _T_1569 = cat(_T_1568, _T_1554) @[Cat.scala 29:58] + node _T_1570 = cat(_T_1569, _T_1550) @[Cat.scala 29:58] + node _T_1571 = cat(_T_1570, _T_1546) @[Cat.scala 29:58] + node _T_1572 = cat(_T_1571, _T_1542) @[Cat.scala 29:58] + node obuf_byteen_in = cat(_T_1572, _T_1538) @[Cat.scala 29:58] + node _T_1573 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 340:76] + node _T_1574 = and(obuf_merge_en, _T_1573) @[lsu_bus_buffer.scala 340:59] + node _T_1575 = bits(obuf_data1_in, 7, 0) @[lsu_bus_buffer.scala 340:94] + node _T_1576 = bits(obuf_data0_in, 7, 0) @[lsu_bus_buffer.scala 340:123] + node _T_1577 = mux(_T_1574, _T_1575, _T_1576) @[lsu_bus_buffer.scala 340:44] + node _T_1578 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 340:76] + node _T_1579 = and(obuf_merge_en, _T_1578) @[lsu_bus_buffer.scala 340:59] + node _T_1580 = bits(obuf_data1_in, 15, 8) @[lsu_bus_buffer.scala 340:94] + node _T_1581 = bits(obuf_data0_in, 15, 8) @[lsu_bus_buffer.scala 340:123] + node _T_1582 = mux(_T_1579, _T_1580, _T_1581) @[lsu_bus_buffer.scala 340:44] + node _T_1583 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 340:76] + node _T_1584 = and(obuf_merge_en, _T_1583) @[lsu_bus_buffer.scala 340:59] + node _T_1585 = bits(obuf_data1_in, 23, 16) @[lsu_bus_buffer.scala 340:94] + node _T_1586 = bits(obuf_data0_in, 23, 16) @[lsu_bus_buffer.scala 340:123] + node _T_1587 = mux(_T_1584, _T_1585, _T_1586) @[lsu_bus_buffer.scala 340:44] + node _T_1588 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 340:76] + node _T_1589 = and(obuf_merge_en, _T_1588) @[lsu_bus_buffer.scala 340:59] + node _T_1590 = bits(obuf_data1_in, 31, 24) @[lsu_bus_buffer.scala 340:94] + node _T_1591 = bits(obuf_data0_in, 31, 24) @[lsu_bus_buffer.scala 340:123] + node _T_1592 = mux(_T_1589, _T_1590, _T_1591) @[lsu_bus_buffer.scala 340:44] + node _T_1593 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 340:76] + node _T_1594 = and(obuf_merge_en, _T_1593) @[lsu_bus_buffer.scala 340:59] + node _T_1595 = bits(obuf_data1_in, 39, 32) @[lsu_bus_buffer.scala 340:94] + node _T_1596 = bits(obuf_data0_in, 39, 32) @[lsu_bus_buffer.scala 340:123] + node _T_1597 = mux(_T_1594, _T_1595, _T_1596) @[lsu_bus_buffer.scala 340:44] + node _T_1598 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 340:76] + node _T_1599 = and(obuf_merge_en, _T_1598) @[lsu_bus_buffer.scala 340:59] + node _T_1600 = bits(obuf_data1_in, 47, 40) @[lsu_bus_buffer.scala 340:94] + node _T_1601 = bits(obuf_data0_in, 47, 40) @[lsu_bus_buffer.scala 340:123] + node _T_1602 = mux(_T_1599, _T_1600, _T_1601) @[lsu_bus_buffer.scala 340:44] + node _T_1603 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 340:76] + node _T_1604 = and(obuf_merge_en, _T_1603) @[lsu_bus_buffer.scala 340:59] + node _T_1605 = bits(obuf_data1_in, 55, 48) @[lsu_bus_buffer.scala 340:94] + node _T_1606 = bits(obuf_data0_in, 55, 48) @[lsu_bus_buffer.scala 340:123] + node _T_1607 = mux(_T_1604, _T_1605, _T_1606) @[lsu_bus_buffer.scala 340:44] + node _T_1608 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 340:76] + node _T_1609 = and(obuf_merge_en, _T_1608) @[lsu_bus_buffer.scala 340:59] + node _T_1610 = bits(obuf_data1_in, 63, 56) @[lsu_bus_buffer.scala 340:94] + node _T_1611 = bits(obuf_data0_in, 63, 56) @[lsu_bus_buffer.scala 340:123] + node _T_1612 = mux(_T_1609, _T_1610, _T_1611) @[lsu_bus_buffer.scala 340:44] + node _T_1613 = cat(_T_1612, _T_1607) @[Cat.scala 29:58] + node _T_1614 = cat(_T_1613, _T_1602) @[Cat.scala 29:58] + node _T_1615 = cat(_T_1614, _T_1597) @[Cat.scala 29:58] + node _T_1616 = cat(_T_1615, _T_1592) @[Cat.scala 29:58] + node _T_1617 = cat(_T_1616, _T_1587) @[Cat.scala 29:58] + node _T_1618 = cat(_T_1617, _T_1582) @[Cat.scala 29:58] + node obuf_data_in = cat(_T_1618, _T_1577) @[Cat.scala 29:58] + wire buf_dualhi : UInt<1>[4] @[lsu_bus_buffer.scala 342:24] + buf_dualhi[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + node _T_1619 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 344:30] + node _T_1620 = and(_T_1619, found_cmdptr0) @[lsu_bus_buffer.scala 344:43] + node _T_1621 = and(_T_1620, found_cmdptr1) @[lsu_bus_buffer.scala 344:59] + node _T_1622 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1623 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1624 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1625 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1626 = mux(_T_1622, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1627 = mux(_T_1623, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1628 = mux(_T_1624, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1629 = mux(_T_1625, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1630 = or(_T_1626, _T_1627) @[Mux.scala 27:72] + node _T_1631 = or(_T_1630, _T_1628) @[Mux.scala 27:72] + node _T_1632 = or(_T_1631, _T_1629) @[Mux.scala 27:72] + wire _T_1633 : UInt<3> @[Mux.scala 27:72] + _T_1633 <= _T_1632 @[Mux.scala 27:72] + node _T_1634 = eq(_T_1633, UInt<3>("h02")) @[lsu_bus_buffer.scala 344:107] + node _T_1635 = and(_T_1621, _T_1634) @[lsu_bus_buffer.scala 344:75] + node _T_1636 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1637 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1638 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1639 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1640 = mux(_T_1636, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1641 = mux(_T_1637, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1642 = mux(_T_1638, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1643 = mux(_T_1639, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1644 = or(_T_1640, _T_1641) @[Mux.scala 27:72] + node _T_1645 = or(_T_1644, _T_1642) @[Mux.scala 27:72] + node _T_1646 = or(_T_1645, _T_1643) @[Mux.scala 27:72] + wire _T_1647 : UInt<3> @[Mux.scala 27:72] + _T_1647 <= _T_1646 @[Mux.scala 27:72] + node _T_1648 = eq(_T_1647, UInt<3>("h02")) @[lsu_bus_buffer.scala 344:150] + node _T_1649 = and(_T_1635, _T_1648) @[lsu_bus_buffer.scala 344:118] + node _T_1650 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1651 = cat(_T_1650, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1652 = cat(_T_1651, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1653 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1654 = bits(_T_1652, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1655 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1656 = bits(_T_1652, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1657 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1658 = bits(_T_1652, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1659 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1660 = bits(_T_1652, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1661 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1662 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1663 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1664 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1665 = or(_T_1661, _T_1662) @[Mux.scala 27:72] + node _T_1666 = or(_T_1665, _T_1663) @[Mux.scala 27:72] + node _T_1667 = or(_T_1666, _T_1664) @[Mux.scala 27:72] + wire _T_1668 : UInt<1> @[Mux.scala 27:72] + _T_1668 <= _T_1667 @[Mux.scala 27:72] + node _T_1669 = eq(_T_1668, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:5] + node _T_1670 = and(_T_1649, _T_1669) @[lsu_bus_buffer.scala 344:161] + node _T_1671 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1672 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1673 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1674 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1675 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1676 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1677 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1678 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1679 = mux(_T_1671, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1680 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1681 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1682 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1683 = or(_T_1679, _T_1680) @[Mux.scala 27:72] + node _T_1684 = or(_T_1683, _T_1681) @[Mux.scala 27:72] + node _T_1685 = or(_T_1684, _T_1682) @[Mux.scala 27:72] + wire _T_1686 : UInt<1> @[Mux.scala 27:72] + _T_1686 <= _T_1685 @[Mux.scala 27:72] + node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:87] + node _T_1688 = and(_T_1670, _T_1687) @[lsu_bus_buffer.scala 345:85] + node _T_1689 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1690 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1691 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1692 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1693 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1694 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1695 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1696 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1697 = mux(_T_1689, _T_1690, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1698 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1699 = mux(_T_1693, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1700 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1701 = or(_T_1697, _T_1698) @[Mux.scala 27:72] + node _T_1702 = or(_T_1701, _T_1699) @[Mux.scala 27:72] + node _T_1703 = or(_T_1702, _T_1700) @[Mux.scala 27:72] + wire _T_1704 : UInt<1> @[Mux.scala 27:72] + _T_1704 <= _T_1703 @[Mux.scala 27:72] + node _T_1705 = eq(_T_1704, UInt<1>("h00")) @[lsu_bus_buffer.scala 346:6] + node _T_1706 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1707 = cat(_T_1706, buf_dual[1]) @[Cat.scala 29:58] + node _T_1708 = cat(_T_1707, buf_dual[0]) @[Cat.scala 29:58] + node _T_1709 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1710 = bits(_T_1708, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1711 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1712 = bits(_T_1708, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1713 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1714 = bits(_T_1708, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1715 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1716 = bits(_T_1708, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1717 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1718 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1719 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1720 = mux(_T_1715, _T_1716, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1721 = or(_T_1717, _T_1718) @[Mux.scala 27:72] + node _T_1722 = or(_T_1721, _T_1719) @[Mux.scala 27:72] + node _T_1723 = or(_T_1722, _T_1720) @[Mux.scala 27:72] + wire _T_1724 : UInt<1> @[Mux.scala 27:72] + _T_1724 <= _T_1723 @[Mux.scala 27:72] + node _T_1725 = and(_T_1705, _T_1724) @[lsu_bus_buffer.scala 346:36] + node _T_1726 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] + node _T_1727 = cat(_T_1726, buf_dualhi[1]) @[Cat.scala 29:58] + node _T_1728 = cat(_T_1727, buf_dualhi[0]) @[Cat.scala 29:58] + node _T_1729 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1730 = bits(_T_1728, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1731 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1732 = bits(_T_1728, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1733 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1734 = bits(_T_1728, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1735 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1736 = bits(_T_1728, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1737 = mux(_T_1729, _T_1730, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1738 = mux(_T_1731, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1739 = mux(_T_1733, _T_1734, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1740 = mux(_T_1735, _T_1736, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1741 = or(_T_1737, _T_1738) @[Mux.scala 27:72] + node _T_1742 = or(_T_1741, _T_1739) @[Mux.scala 27:72] + node _T_1743 = or(_T_1742, _T_1740) @[Mux.scala 27:72] + wire _T_1744 : UInt<1> @[Mux.scala 27:72] + _T_1744 <= _T_1743 @[Mux.scala 27:72] + node _T_1745 = eq(_T_1744, UInt<1>("h00")) @[lsu_bus_buffer.scala 346:107] + node _T_1746 = and(_T_1725, _T_1745) @[lsu_bus_buffer.scala 346:105] + node _T_1747 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1748 = cat(_T_1747, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1749 = cat(_T_1748, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1750 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1751 = bits(_T_1749, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1752 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1753 = bits(_T_1749, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1754 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1755 = bits(_T_1749, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1756 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1757 = bits(_T_1749, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1758 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1759 = mux(_T_1752, _T_1753, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1760 = mux(_T_1754, _T_1755, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1761 = mux(_T_1756, _T_1757, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = or(_T_1758, _T_1759) @[Mux.scala 27:72] + node _T_1763 = or(_T_1762, _T_1760) @[Mux.scala 27:72] + node _T_1764 = or(_T_1763, _T_1761) @[Mux.scala 27:72] + wire _T_1765 : UInt<1> @[Mux.scala 27:72] + _T_1765 <= _T_1764 @[Mux.scala 27:72] + node _T_1766 = and(_T_1746, _T_1765) @[lsu_bus_buffer.scala 346:177] + node _T_1767 = and(_T_1688, _T_1766) @[lsu_bus_buffer.scala 345:122] + node _T_1768 = and(ibuf_buf_byp, ldst_samedw_r) @[lsu_bus_buffer.scala 347:19] + node _T_1769 = and(_T_1768, io.ldst_dual_r) @[lsu_bus_buffer.scala 347:35] + node _T_1770 = or(_T_1767, _T_1769) @[lsu_bus_buffer.scala 346:250] + obuf_merge_en <= _T_1770 @[lsu_bus_buffer.scala 344:17] + reg obuf_wr_enQ : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + obuf_wr_enQ <= obuf_wr_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1771 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 349:58] + node _T_1772 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 349:93] + node _T_1773 = and(_T_1771, _T_1772) @[lsu_bus_buffer.scala 349:91] + reg _T_1774 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 349:54] + _T_1774 <= _T_1773 @[lsu_bus_buffer.scala 349:54] + obuf_valid <= _T_1774 @[lsu_bus_buffer.scala 349:14] + reg _T_1775 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1775 <= obuf_nosend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_nosend <= _T_1775 @[lsu_bus_buffer.scala 350:15] + reg _T_1776 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_rdrsp_pend_en : @[Reg.scala 28:19] + _T_1776 <= obuf_rdrsp_pend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_rdrsp_pend <= _T_1776 @[lsu_bus_buffer.scala 351:19] + reg _T_1777 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1777 <= obuf_cmd_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_cmd_done <= _T_1777 @[lsu_bus_buffer.scala 352:17] + reg _T_1778 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1778 <= obuf_data_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_data_done <= _T_1778 @[lsu_bus_buffer.scala 353:18] + reg _T_1779 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1779 <= obuf_rdrsp_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_rdrsp_tag <= _T_1779 @[lsu_bus_buffer.scala 354:18] + node _T_1780 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1780 : @[Reg.scala 28:19] + _T_1781 <= obuf_tag0_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_tag0 <= _T_1781 @[lsu_bus_buffer.scala 356:13] + node _T_1782 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_tag1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1782 : @[Reg.scala 28:19] + obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1783 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_merge : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1783 : @[Reg.scala 28:19] + obuf_merge <= obuf_merge_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1784 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1785 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1784 : @[Reg.scala 28:19] + _T_1785 <= obuf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_write <= _T_1785 @[lsu_bus_buffer.scala 359:14] + node _T_1786 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1787 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1786 : @[Reg.scala 28:19] + _T_1787 <= obuf_sideeffect_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_sideeffect <= _T_1787 @[lsu_bus_buffer.scala 360:19] + node _T_1788 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_sz : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1788 : @[Reg.scala 28:19] + obuf_sz <= obuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1789 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_byteen : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1789 : @[Reg.scala 28:19] + obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_2 of rvclkhdr_24 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1790 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1790 <= obuf_addr_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_addr <= _T_1790 @[lsu_bus_buffer.scala 363:13] + inst rvclkhdr_3 of rvclkhdr_25 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg obuf_data : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_data <= obuf_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1791 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1791 <= obuf_data_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_wr_timer <= _T_1791 @[lsu_bus_buffer.scala 365:17] + wire WrPtr0_m : UInt<2> + WrPtr0_m <= UInt<1>("h00") + node _T_1792 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1793 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:30] + node _T_1794 = and(ibuf_valid, _T_1793) @[lsu_bus_buffer.scala 370:19] + node _T_1795 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:18] + node _T_1796 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:57] + node _T_1797 = and(io.ldst_dual_r, _T_1796) @[lsu_bus_buffer.scala 371:45] + node _T_1798 = or(_T_1795, _T_1797) @[lsu_bus_buffer.scala 371:27] + node _T_1799 = and(io.lsu_busreq_r, _T_1798) @[lsu_bus_buffer.scala 370:58] + node _T_1800 = or(_T_1794, _T_1799) @[lsu_bus_buffer.scala 370:39] + node _T_1801 = eq(_T_1800, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1802 = and(_T_1792, _T_1801) @[lsu_bus_buffer.scala 369:76] + node _T_1803 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1804 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 370:30] + node _T_1805 = and(ibuf_valid, _T_1804) @[lsu_bus_buffer.scala 370:19] + node _T_1806 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:18] + node _T_1807 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:57] + node _T_1808 = and(io.ldst_dual_r, _T_1807) @[lsu_bus_buffer.scala 371:45] + node _T_1809 = or(_T_1806, _T_1808) @[lsu_bus_buffer.scala 371:27] + node _T_1810 = and(io.lsu_busreq_r, _T_1809) @[lsu_bus_buffer.scala 370:58] + node _T_1811 = or(_T_1805, _T_1810) @[lsu_bus_buffer.scala 370:39] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1813 = and(_T_1803, _T_1812) @[lsu_bus_buffer.scala 369:76] + node _T_1814 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1815 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 370:30] + node _T_1816 = and(ibuf_valid, _T_1815) @[lsu_bus_buffer.scala 370:19] + node _T_1817 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:18] + node _T_1818 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:57] + node _T_1819 = and(io.ldst_dual_r, _T_1818) @[lsu_bus_buffer.scala 371:45] + node _T_1820 = or(_T_1817, _T_1819) @[lsu_bus_buffer.scala 371:27] + node _T_1821 = and(io.lsu_busreq_r, _T_1820) @[lsu_bus_buffer.scala 370:58] + node _T_1822 = or(_T_1816, _T_1821) @[lsu_bus_buffer.scala 370:39] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1824 = and(_T_1814, _T_1823) @[lsu_bus_buffer.scala 369:76] + node _T_1825 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1826 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 370:30] + node _T_1827 = and(ibuf_valid, _T_1826) @[lsu_bus_buffer.scala 370:19] + node _T_1828 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:18] + node _T_1829 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:57] + node _T_1830 = and(io.ldst_dual_r, _T_1829) @[lsu_bus_buffer.scala 371:45] + node _T_1831 = or(_T_1828, _T_1830) @[lsu_bus_buffer.scala 371:27] + node _T_1832 = and(io.lsu_busreq_r, _T_1831) @[lsu_bus_buffer.scala 370:58] + node _T_1833 = or(_T_1827, _T_1832) @[lsu_bus_buffer.scala 370:39] + node _T_1834 = eq(_T_1833, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1835 = and(_T_1825, _T_1834) @[lsu_bus_buffer.scala 369:76] + node _T_1836 = mux(_T_1835, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1837 = mux(_T_1824, UInt<2>("h02"), _T_1836) @[Mux.scala 98:16] + node _T_1838 = mux(_T_1813, UInt<1>("h01"), _T_1837) @[Mux.scala 98:16] + node _T_1839 = mux(_T_1802, UInt<1>("h00"), _T_1838) @[Mux.scala 98:16] + WrPtr0_m <= _T_1839 @[lsu_bus_buffer.scala 369:12] + wire WrPtr1_m : UInt<2> + WrPtr1_m <= UInt<1>("h00") + node _T_1840 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1841 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:103] + node _T_1842 = and(ibuf_valid, _T_1841) @[lsu_bus_buffer.scala 375:92] + node _T_1843 = eq(WrPtr0_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 376:33] + node _T_1844 = and(io.lsu_busreq_m, _T_1843) @[lsu_bus_buffer.scala 376:22] + node _T_1845 = or(_T_1842, _T_1844) @[lsu_bus_buffer.scala 375:112] + node _T_1846 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:36] + node _T_1847 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:34] + node _T_1848 = and(io.ldst_dual_r, _T_1847) @[lsu_bus_buffer.scala 378:23] + node _T_1849 = or(_T_1846, _T_1848) @[lsu_bus_buffer.scala 377:46] + node _T_1850 = and(io.lsu_busreq_r, _T_1849) @[lsu_bus_buffer.scala 377:22] + node _T_1851 = or(_T_1845, _T_1850) @[lsu_bus_buffer.scala 376:42] + node _T_1852 = eq(_T_1851, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1853 = and(_T_1840, _T_1852) @[lsu_bus_buffer.scala 375:76] + node _T_1854 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1855 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 375:103] + node _T_1856 = and(ibuf_valid, _T_1855) @[lsu_bus_buffer.scala 375:92] + node _T_1857 = eq(WrPtr0_m, UInt<1>("h01")) @[lsu_bus_buffer.scala 376:33] + node _T_1858 = and(io.lsu_busreq_m, _T_1857) @[lsu_bus_buffer.scala 376:22] + node _T_1859 = or(_T_1856, _T_1858) @[lsu_bus_buffer.scala 375:112] + node _T_1860 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 377:36] + node _T_1861 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 378:34] + node _T_1862 = and(io.ldst_dual_r, _T_1861) @[lsu_bus_buffer.scala 378:23] + node _T_1863 = or(_T_1860, _T_1862) @[lsu_bus_buffer.scala 377:46] + node _T_1864 = and(io.lsu_busreq_r, _T_1863) @[lsu_bus_buffer.scala 377:22] + node _T_1865 = or(_T_1859, _T_1864) @[lsu_bus_buffer.scala 376:42] + node _T_1866 = eq(_T_1865, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1867 = and(_T_1854, _T_1866) @[lsu_bus_buffer.scala 375:76] + node _T_1868 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1869 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 375:103] + node _T_1870 = and(ibuf_valid, _T_1869) @[lsu_bus_buffer.scala 375:92] + node _T_1871 = eq(WrPtr0_m, UInt<2>("h02")) @[lsu_bus_buffer.scala 376:33] + node _T_1872 = and(io.lsu_busreq_m, _T_1871) @[lsu_bus_buffer.scala 376:22] + node _T_1873 = or(_T_1870, _T_1872) @[lsu_bus_buffer.scala 375:112] + node _T_1874 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 377:36] + node _T_1875 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 378:34] + node _T_1876 = and(io.ldst_dual_r, _T_1875) @[lsu_bus_buffer.scala 378:23] + node _T_1877 = or(_T_1874, _T_1876) @[lsu_bus_buffer.scala 377:46] + node _T_1878 = and(io.lsu_busreq_r, _T_1877) @[lsu_bus_buffer.scala 377:22] + node _T_1879 = or(_T_1873, _T_1878) @[lsu_bus_buffer.scala 376:42] + node _T_1880 = eq(_T_1879, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1881 = and(_T_1868, _T_1880) @[lsu_bus_buffer.scala 375:76] + node _T_1882 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1883 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 375:103] + node _T_1884 = and(ibuf_valid, _T_1883) @[lsu_bus_buffer.scala 375:92] + node _T_1885 = eq(WrPtr0_m, UInt<2>("h03")) @[lsu_bus_buffer.scala 376:33] + node _T_1886 = and(io.lsu_busreq_m, _T_1885) @[lsu_bus_buffer.scala 376:22] + node _T_1887 = or(_T_1884, _T_1886) @[lsu_bus_buffer.scala 375:112] + node _T_1888 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 377:36] + node _T_1889 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 378:34] + node _T_1890 = and(io.ldst_dual_r, _T_1889) @[lsu_bus_buffer.scala 378:23] + node _T_1891 = or(_T_1888, _T_1890) @[lsu_bus_buffer.scala 377:46] + node _T_1892 = and(io.lsu_busreq_r, _T_1891) @[lsu_bus_buffer.scala 377:22] + node _T_1893 = or(_T_1887, _T_1892) @[lsu_bus_buffer.scala 376:42] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1895 = and(_T_1882, _T_1894) @[lsu_bus_buffer.scala 375:76] + node _T_1896 = mux(_T_1895, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1897 = mux(_T_1881, UInt<2>("h02"), _T_1896) @[Mux.scala 98:16] + node _T_1898 = mux(_T_1867, UInt<1>("h01"), _T_1897) @[Mux.scala 98:16] + node _T_1899 = mux(_T_1853, UInt<1>("h00"), _T_1898) @[Mux.scala 98:16] + WrPtr1_m <= _T_1899 @[lsu_bus_buffer.scala 375:12] + wire buf_age : UInt<4>[4] @[lsu_bus_buffer.scala 380:21] + buf_age[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + node _T_1900 = orr(buf_age[0]) @[lsu_bus_buffer.scala 383:58] + node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1902 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1903 = and(_T_1901, _T_1902) @[lsu_bus_buffer.scala 383:63] + node _T_1904 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1905 = and(_T_1903, _T_1904) @[lsu_bus_buffer.scala 383:88] + node _T_1906 = orr(buf_age[1]) @[lsu_bus_buffer.scala 383:58] + node _T_1907 = eq(_T_1906, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1908 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1909 = and(_T_1907, _T_1908) @[lsu_bus_buffer.scala 383:63] + node _T_1910 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1911 = and(_T_1909, _T_1910) @[lsu_bus_buffer.scala 383:88] + node _T_1912 = orr(buf_age[2]) @[lsu_bus_buffer.scala 383:58] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1914 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1915 = and(_T_1913, _T_1914) @[lsu_bus_buffer.scala 383:63] + node _T_1916 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1917 = and(_T_1915, _T_1916) @[lsu_bus_buffer.scala 383:88] + node _T_1918 = orr(buf_age[3]) @[lsu_bus_buffer.scala 383:58] + node _T_1919 = eq(_T_1918, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1920 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1921 = and(_T_1919, _T_1920) @[lsu_bus_buffer.scala 383:63] + node _T_1922 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1923 = and(_T_1921, _T_1922) @[lsu_bus_buffer.scala 383:88] + node _T_1924 = cat(_T_1923, _T_1917) @[Cat.scala 29:58] + node _T_1925 = cat(_T_1924, _T_1911) @[Cat.scala 29:58] + node CmdPtr0Dec = cat(_T_1925, _T_1905) @[Cat.scala 29:58] + node _T_1926 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1927 = and(buf_age[0], _T_1926) @[lsu_bus_buffer.scala 384:59] + node _T_1928 = orr(_T_1927) @[lsu_bus_buffer.scala 384:76] + node _T_1929 = eq(_T_1928, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1930 = bits(CmdPtr0Dec, 0, 0) @[lsu_bus_buffer.scala 384:94] + node _T_1931 = eq(_T_1930, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1932 = and(_T_1929, _T_1931) @[lsu_bus_buffer.scala 384:81] + node _T_1933 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1934 = and(_T_1932, _T_1933) @[lsu_bus_buffer.scala 384:98] + node _T_1935 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1936 = and(_T_1934, _T_1935) @[lsu_bus_buffer.scala 384:123] + node _T_1937 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1938 = and(buf_age[1], _T_1937) @[lsu_bus_buffer.scala 384:59] + node _T_1939 = orr(_T_1938) @[lsu_bus_buffer.scala 384:76] + node _T_1940 = eq(_T_1939, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1941 = bits(CmdPtr0Dec, 1, 1) @[lsu_bus_buffer.scala 384:94] + node _T_1942 = eq(_T_1941, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1943 = and(_T_1940, _T_1942) @[lsu_bus_buffer.scala 384:81] + node _T_1944 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1945 = and(_T_1943, _T_1944) @[lsu_bus_buffer.scala 384:98] + node _T_1946 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1947 = and(_T_1945, _T_1946) @[lsu_bus_buffer.scala 384:123] + node _T_1948 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1949 = and(buf_age[2], _T_1948) @[lsu_bus_buffer.scala 384:59] + node _T_1950 = orr(_T_1949) @[lsu_bus_buffer.scala 384:76] + node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1952 = bits(CmdPtr0Dec, 2, 2) @[lsu_bus_buffer.scala 384:94] + node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1954 = and(_T_1951, _T_1953) @[lsu_bus_buffer.scala 384:81] + node _T_1955 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1956 = and(_T_1954, _T_1955) @[lsu_bus_buffer.scala 384:98] + node _T_1957 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1958 = and(_T_1956, _T_1957) @[lsu_bus_buffer.scala 384:123] + node _T_1959 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1960 = and(buf_age[3], _T_1959) @[lsu_bus_buffer.scala 384:59] + node _T_1961 = orr(_T_1960) @[lsu_bus_buffer.scala 384:76] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1963 = bits(CmdPtr0Dec, 3, 3) @[lsu_bus_buffer.scala 384:94] + node _T_1964 = eq(_T_1963, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1965 = and(_T_1962, _T_1964) @[lsu_bus_buffer.scala 384:81] + node _T_1966 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1967 = and(_T_1965, _T_1966) @[lsu_bus_buffer.scala 384:98] + node _T_1968 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1969 = and(_T_1967, _T_1968) @[lsu_bus_buffer.scala 384:123] + node _T_1970 = cat(_T_1969, _T_1958) @[Cat.scala 29:58] + node _T_1971 = cat(_T_1970, _T_1947) @[Cat.scala 29:58] + node CmdPtr1Dec = cat(_T_1971, _T_1936) @[Cat.scala 29:58] + wire buf_rsp_pickage : UInt<4>[4] @[lsu_bus_buffer.scala 385:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + node _T_1972 = orr(buf_rsp_pickage[0]) @[lsu_bus_buffer.scala 387:65] + node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1974 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1975 = and(_T_1973, _T_1974) @[lsu_bus_buffer.scala 387:70] + node _T_1976 = orr(buf_rsp_pickage[1]) @[lsu_bus_buffer.scala 387:65] + node _T_1977 = eq(_T_1976, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1978 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1979 = and(_T_1977, _T_1978) @[lsu_bus_buffer.scala 387:70] + node _T_1980 = orr(buf_rsp_pickage[2]) @[lsu_bus_buffer.scala 387:65] + node _T_1981 = eq(_T_1980, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1982 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1983 = and(_T_1981, _T_1982) @[lsu_bus_buffer.scala 387:70] + node _T_1984 = orr(buf_rsp_pickage[3]) @[lsu_bus_buffer.scala 387:65] + node _T_1985 = eq(_T_1984, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1986 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1987 = and(_T_1985, _T_1986) @[lsu_bus_buffer.scala 387:70] + node _T_1988 = cat(_T_1987, _T_1983) @[Cat.scala 29:58] + node _T_1989 = cat(_T_1988, _T_1979) @[Cat.scala 29:58] + node RspPtrDec = cat(_T_1989, _T_1975) @[Cat.scala 29:58] + node _T_1990 = orr(CmdPtr0Dec) @[lsu_bus_buffer.scala 388:31] + found_cmdptr0 <= _T_1990 @[lsu_bus_buffer.scala 388:17] + node _T_1991 = orr(CmdPtr1Dec) @[lsu_bus_buffer.scala 389:31] + found_cmdptr1 <= _T_1991 @[lsu_bus_buffer.scala 389:17] + wire RspPtr : UInt<2> + RspPtr <= UInt<1>("h00") + node _T_1992 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1993 = cat(_T_1992, CmdPtr0Dec) @[Cat.scala 29:58] + node _T_1994 = bits(_T_1993, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_1995 = bits(_T_1993, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_1996 = or(_T_1994, _T_1995) @[lsu_bus_buffer.scala 391:42] + node _T_1997 = bits(_T_1993, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_1998 = or(_T_1996, _T_1997) @[lsu_bus_buffer.scala 391:48] + node _T_1999 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2000 = or(_T_1998, _T_1999) @[lsu_bus_buffer.scala 391:54] + node _T_2001 = bits(_T_1993, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2002 = bits(_T_1993, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2003 = or(_T_2001, _T_2002) @[lsu_bus_buffer.scala 391:67] + node _T_2004 = bits(_T_1993, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2005 = or(_T_2003, _T_2004) @[lsu_bus_buffer.scala 391:73] + node _T_2006 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2007 = or(_T_2005, _T_2006) @[lsu_bus_buffer.scala 391:79] + node _T_2008 = bits(_T_1993, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2009 = bits(_T_1993, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2010 = or(_T_2008, _T_2009) @[lsu_bus_buffer.scala 391:92] + node _T_2011 = bits(_T_1993, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2012 = or(_T_2010, _T_2011) @[lsu_bus_buffer.scala 391:98] + node _T_2013 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2014 = or(_T_2012, _T_2013) @[lsu_bus_buffer.scala 391:104] + node _T_2015 = cat(_T_2000, _T_2007) @[Cat.scala 29:58] + node _T_2016 = cat(_T_2015, _T_2014) @[Cat.scala 29:58] + CmdPtr0 <= _T_2016 @[lsu_bus_buffer.scala 396:11] + node _T_2017 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2018 = cat(_T_2017, CmdPtr1Dec) @[Cat.scala 29:58] + node _T_2019 = bits(_T_2018, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_2020 = bits(_T_2018, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_2021 = or(_T_2019, _T_2020) @[lsu_bus_buffer.scala 391:42] + node _T_2022 = bits(_T_2018, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_2023 = or(_T_2021, _T_2022) @[lsu_bus_buffer.scala 391:48] + node _T_2024 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2025 = or(_T_2023, _T_2024) @[lsu_bus_buffer.scala 391:54] + node _T_2026 = bits(_T_2018, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2027 = bits(_T_2018, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2028 = or(_T_2026, _T_2027) @[lsu_bus_buffer.scala 391:67] + node _T_2029 = bits(_T_2018, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2030 = or(_T_2028, _T_2029) @[lsu_bus_buffer.scala 391:73] + node _T_2031 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2032 = or(_T_2030, _T_2031) @[lsu_bus_buffer.scala 391:79] + node _T_2033 = bits(_T_2018, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2034 = bits(_T_2018, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2035 = or(_T_2033, _T_2034) @[lsu_bus_buffer.scala 391:92] + node _T_2036 = bits(_T_2018, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2037 = or(_T_2035, _T_2036) @[lsu_bus_buffer.scala 391:98] + node _T_2038 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2039 = or(_T_2037, _T_2038) @[lsu_bus_buffer.scala 391:104] + node _T_2040 = cat(_T_2025, _T_2032) @[Cat.scala 29:58] + node _T_2041 = cat(_T_2040, _T_2039) @[Cat.scala 29:58] + CmdPtr1 <= _T_2041 @[lsu_bus_buffer.scala 398:11] + node _T_2042 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2043 = cat(_T_2042, RspPtrDec) @[Cat.scala 29:58] + node _T_2044 = bits(_T_2043, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_2045 = bits(_T_2043, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_2046 = or(_T_2044, _T_2045) @[lsu_bus_buffer.scala 391:42] + node _T_2047 = bits(_T_2043, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_2048 = or(_T_2046, _T_2047) @[lsu_bus_buffer.scala 391:48] + node _T_2049 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2050 = or(_T_2048, _T_2049) @[lsu_bus_buffer.scala 391:54] + node _T_2051 = bits(_T_2043, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2052 = bits(_T_2043, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2053 = or(_T_2051, _T_2052) @[lsu_bus_buffer.scala 391:67] + node _T_2054 = bits(_T_2043, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2055 = or(_T_2053, _T_2054) @[lsu_bus_buffer.scala 391:73] + node _T_2056 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2057 = or(_T_2055, _T_2056) @[lsu_bus_buffer.scala 391:79] + node _T_2058 = bits(_T_2043, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2059 = bits(_T_2043, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2060 = or(_T_2058, _T_2059) @[lsu_bus_buffer.scala 391:92] + node _T_2061 = bits(_T_2043, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2062 = or(_T_2060, _T_2061) @[lsu_bus_buffer.scala 391:98] + node _T_2063 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2064 = or(_T_2062, _T_2063) @[lsu_bus_buffer.scala 391:104] + node _T_2065 = cat(_T_2050, _T_2057) @[Cat.scala 29:58] + node _T_2066 = cat(_T_2065, _T_2064) @[Cat.scala 29:58] + RspPtr <= _T_2066 @[lsu_bus_buffer.scala 399:10] + wire buf_state_en : UInt<1>[4] @[lsu_bus_buffer.scala 400:26] + buf_state_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + wire buf_rspageQ : UInt<4>[4] @[lsu_bus_buffer.scala 402:25] + buf_rspageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + wire buf_rspage_set : UInt<4>[4] @[lsu_bus_buffer.scala 404:28] + buf_rspage_set[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + wire buf_rspage_in : UInt<4>[4] @[lsu_bus_buffer.scala 406:27] + buf_rspage_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + wire buf_rspage : UInt<4>[4] @[lsu_bus_buffer.scala 408:24] + buf_rspage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + node _T_2067 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2068 = and(_T_2067, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2069 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2070 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2071 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2072 = and(_T_2070, _T_2071) @[lsu_bus_buffer.scala 412:57] + node _T_2073 = or(_T_2069, _T_2072) @[lsu_bus_buffer.scala 412:31] + node _T_2074 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2075 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2076 = and(_T_2074, _T_2075) @[lsu_bus_buffer.scala 413:41] + node _T_2077 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2078 = and(_T_2076, _T_2077) @[lsu_bus_buffer.scala 413:71] + node _T_2079 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2080 = and(_T_2078, _T_2079) @[lsu_bus_buffer.scala 413:92] + node _T_2081 = or(_T_2073, _T_2080) @[lsu_bus_buffer.scala 412:86] + node _T_2082 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2083 = and(_T_2082, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2084 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2085 = and(_T_2083, _T_2084) @[lsu_bus_buffer.scala 414:52] + node _T_2086 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2087 = and(_T_2085, _T_2086) @[lsu_bus_buffer.scala 414:73] + node _T_2088 = or(_T_2081, _T_2087) @[lsu_bus_buffer.scala 413:114] + node _T_2089 = and(_T_2068, _T_2088) @[lsu_bus_buffer.scala 411:113] + node _T_2090 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2091 = or(_T_2089, _T_2090) @[lsu_bus_buffer.scala 414:97] + node _T_2092 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2093 = and(_T_2092, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2094 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2095 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2096 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2097 = and(_T_2095, _T_2096) @[lsu_bus_buffer.scala 412:57] + node _T_2098 = or(_T_2094, _T_2097) @[lsu_bus_buffer.scala 412:31] + node _T_2099 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2100 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2101 = and(_T_2099, _T_2100) @[lsu_bus_buffer.scala 413:41] + node _T_2102 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2103 = and(_T_2101, _T_2102) @[lsu_bus_buffer.scala 413:71] + node _T_2104 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2105 = and(_T_2103, _T_2104) @[lsu_bus_buffer.scala 413:92] + node _T_2106 = or(_T_2098, _T_2105) @[lsu_bus_buffer.scala 412:86] + node _T_2107 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2108 = and(_T_2107, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2109 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2110 = and(_T_2108, _T_2109) @[lsu_bus_buffer.scala 414:52] + node _T_2111 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2112 = and(_T_2110, _T_2111) @[lsu_bus_buffer.scala 414:73] + node _T_2113 = or(_T_2106, _T_2112) @[lsu_bus_buffer.scala 413:114] + node _T_2114 = and(_T_2093, _T_2113) @[lsu_bus_buffer.scala 411:113] + node _T_2115 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2116 = or(_T_2114, _T_2115) @[lsu_bus_buffer.scala 414:97] + node _T_2117 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2118 = and(_T_2117, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2119 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2120 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2121 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2122 = and(_T_2120, _T_2121) @[lsu_bus_buffer.scala 412:57] + node _T_2123 = or(_T_2119, _T_2122) @[lsu_bus_buffer.scala 412:31] + node _T_2124 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2125 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2126 = and(_T_2124, _T_2125) @[lsu_bus_buffer.scala 413:41] + node _T_2127 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2128 = and(_T_2126, _T_2127) @[lsu_bus_buffer.scala 413:71] + node _T_2129 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2130 = and(_T_2128, _T_2129) @[lsu_bus_buffer.scala 413:92] + node _T_2131 = or(_T_2123, _T_2130) @[lsu_bus_buffer.scala 412:86] + node _T_2132 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2133 = and(_T_2132, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2134 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2135 = and(_T_2133, _T_2134) @[lsu_bus_buffer.scala 414:52] + node _T_2136 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2137 = and(_T_2135, _T_2136) @[lsu_bus_buffer.scala 414:73] + node _T_2138 = or(_T_2131, _T_2137) @[lsu_bus_buffer.scala 413:114] + node _T_2139 = and(_T_2118, _T_2138) @[lsu_bus_buffer.scala 411:113] + node _T_2140 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2141 = or(_T_2139, _T_2140) @[lsu_bus_buffer.scala 414:97] + node _T_2142 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2143 = and(_T_2142, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2144 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2145 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2146 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2147 = and(_T_2145, _T_2146) @[lsu_bus_buffer.scala 412:57] + node _T_2148 = or(_T_2144, _T_2147) @[lsu_bus_buffer.scala 412:31] + node _T_2149 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2150 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2151 = and(_T_2149, _T_2150) @[lsu_bus_buffer.scala 413:41] + node _T_2152 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2153 = and(_T_2151, _T_2152) @[lsu_bus_buffer.scala 413:71] + node _T_2154 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2155 = and(_T_2153, _T_2154) @[lsu_bus_buffer.scala 413:92] + node _T_2156 = or(_T_2148, _T_2155) @[lsu_bus_buffer.scala 412:86] + node _T_2157 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2158 = and(_T_2157, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2159 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2160 = and(_T_2158, _T_2159) @[lsu_bus_buffer.scala 414:52] + node _T_2161 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2162 = and(_T_2160, _T_2161) @[lsu_bus_buffer.scala 414:73] + node _T_2163 = or(_T_2156, _T_2162) @[lsu_bus_buffer.scala 413:114] + node _T_2164 = and(_T_2143, _T_2163) @[lsu_bus_buffer.scala 411:113] + node _T_2165 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2166 = or(_T_2164, _T_2165) @[lsu_bus_buffer.scala 414:97] + node _T_2167 = cat(_T_2166, _T_2141) @[Cat.scala 29:58] + node _T_2168 = cat(_T_2167, _T_2116) @[Cat.scala 29:58] + node buf_age_in_0 = cat(_T_2168, _T_2091) @[Cat.scala 29:58] + node _T_2169 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2170 = and(_T_2169, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2171 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2172 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2173 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2174 = and(_T_2172, _T_2173) @[lsu_bus_buffer.scala 412:57] + node _T_2175 = or(_T_2171, _T_2174) @[lsu_bus_buffer.scala 412:31] + node _T_2176 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2177 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2178 = and(_T_2176, _T_2177) @[lsu_bus_buffer.scala 413:41] + node _T_2179 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2180 = and(_T_2178, _T_2179) @[lsu_bus_buffer.scala 413:71] + node _T_2181 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2182 = and(_T_2180, _T_2181) @[lsu_bus_buffer.scala 413:92] + node _T_2183 = or(_T_2175, _T_2182) @[lsu_bus_buffer.scala 412:86] + node _T_2184 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2185 = and(_T_2184, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2186 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2187 = and(_T_2185, _T_2186) @[lsu_bus_buffer.scala 414:52] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2189 = and(_T_2187, _T_2188) @[lsu_bus_buffer.scala 414:73] + node _T_2190 = or(_T_2183, _T_2189) @[lsu_bus_buffer.scala 413:114] + node _T_2191 = and(_T_2170, _T_2190) @[lsu_bus_buffer.scala 411:113] + node _T_2192 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2193 = or(_T_2191, _T_2192) @[lsu_bus_buffer.scala 414:97] + node _T_2194 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2195 = and(_T_2194, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2196 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2197 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2198 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2199 = and(_T_2197, _T_2198) @[lsu_bus_buffer.scala 412:57] + node _T_2200 = or(_T_2196, _T_2199) @[lsu_bus_buffer.scala 412:31] + node _T_2201 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2202 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2203 = and(_T_2201, _T_2202) @[lsu_bus_buffer.scala 413:41] + node _T_2204 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2205 = and(_T_2203, _T_2204) @[lsu_bus_buffer.scala 413:71] + node _T_2206 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2207 = and(_T_2205, _T_2206) @[lsu_bus_buffer.scala 413:92] + node _T_2208 = or(_T_2200, _T_2207) @[lsu_bus_buffer.scala 412:86] + node _T_2209 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2210 = and(_T_2209, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2211 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2212 = and(_T_2210, _T_2211) @[lsu_bus_buffer.scala 414:52] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2214 = and(_T_2212, _T_2213) @[lsu_bus_buffer.scala 414:73] + node _T_2215 = or(_T_2208, _T_2214) @[lsu_bus_buffer.scala 413:114] + node _T_2216 = and(_T_2195, _T_2215) @[lsu_bus_buffer.scala 411:113] + node _T_2217 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2218 = or(_T_2216, _T_2217) @[lsu_bus_buffer.scala 414:97] + node _T_2219 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2220 = and(_T_2219, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2221 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2222 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2223 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2224 = and(_T_2222, _T_2223) @[lsu_bus_buffer.scala 412:57] + node _T_2225 = or(_T_2221, _T_2224) @[lsu_bus_buffer.scala 412:31] + node _T_2226 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2227 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2228 = and(_T_2226, _T_2227) @[lsu_bus_buffer.scala 413:41] + node _T_2229 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2230 = and(_T_2228, _T_2229) @[lsu_bus_buffer.scala 413:71] + node _T_2231 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2232 = and(_T_2230, _T_2231) @[lsu_bus_buffer.scala 413:92] + node _T_2233 = or(_T_2225, _T_2232) @[lsu_bus_buffer.scala 412:86] + node _T_2234 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2235 = and(_T_2234, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2236 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2237 = and(_T_2235, _T_2236) @[lsu_bus_buffer.scala 414:52] + node _T_2238 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2239 = and(_T_2237, _T_2238) @[lsu_bus_buffer.scala 414:73] + node _T_2240 = or(_T_2233, _T_2239) @[lsu_bus_buffer.scala 413:114] + node _T_2241 = and(_T_2220, _T_2240) @[lsu_bus_buffer.scala 411:113] + node _T_2242 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2243 = or(_T_2241, _T_2242) @[lsu_bus_buffer.scala 414:97] + node _T_2244 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2245 = and(_T_2244, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2246 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2247 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2248 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2249 = and(_T_2247, _T_2248) @[lsu_bus_buffer.scala 412:57] + node _T_2250 = or(_T_2246, _T_2249) @[lsu_bus_buffer.scala 412:31] + node _T_2251 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2252 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2253 = and(_T_2251, _T_2252) @[lsu_bus_buffer.scala 413:41] + node _T_2254 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2255 = and(_T_2253, _T_2254) @[lsu_bus_buffer.scala 413:71] + node _T_2256 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2257 = and(_T_2255, _T_2256) @[lsu_bus_buffer.scala 413:92] + node _T_2258 = or(_T_2250, _T_2257) @[lsu_bus_buffer.scala 412:86] + node _T_2259 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2260 = and(_T_2259, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2261 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2262 = and(_T_2260, _T_2261) @[lsu_bus_buffer.scala 414:52] + node _T_2263 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2264 = and(_T_2262, _T_2263) @[lsu_bus_buffer.scala 414:73] + node _T_2265 = or(_T_2258, _T_2264) @[lsu_bus_buffer.scala 413:114] + node _T_2266 = and(_T_2245, _T_2265) @[lsu_bus_buffer.scala 411:113] + node _T_2267 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2268 = or(_T_2266, _T_2267) @[lsu_bus_buffer.scala 414:97] + node _T_2269 = cat(_T_2268, _T_2243) @[Cat.scala 29:58] + node _T_2270 = cat(_T_2269, _T_2218) @[Cat.scala 29:58] + node buf_age_in_1 = cat(_T_2270, _T_2193) @[Cat.scala 29:58] + node _T_2271 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2272 = and(_T_2271, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2273 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2274 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2275 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2276 = and(_T_2274, _T_2275) @[lsu_bus_buffer.scala 412:57] + node _T_2277 = or(_T_2273, _T_2276) @[lsu_bus_buffer.scala 412:31] + node _T_2278 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2279 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2280 = and(_T_2278, _T_2279) @[lsu_bus_buffer.scala 413:41] + node _T_2281 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2282 = and(_T_2280, _T_2281) @[lsu_bus_buffer.scala 413:71] + node _T_2283 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2284 = and(_T_2282, _T_2283) @[lsu_bus_buffer.scala 413:92] + node _T_2285 = or(_T_2277, _T_2284) @[lsu_bus_buffer.scala 412:86] + node _T_2286 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2287 = and(_T_2286, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2288 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2289 = and(_T_2287, _T_2288) @[lsu_bus_buffer.scala 414:52] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2291 = and(_T_2289, _T_2290) @[lsu_bus_buffer.scala 414:73] + node _T_2292 = or(_T_2285, _T_2291) @[lsu_bus_buffer.scala 413:114] + node _T_2293 = and(_T_2272, _T_2292) @[lsu_bus_buffer.scala 411:113] + node _T_2294 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2295 = or(_T_2293, _T_2294) @[lsu_bus_buffer.scala 414:97] + node _T_2296 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2297 = and(_T_2296, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2298 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2299 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2300 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2301 = and(_T_2299, _T_2300) @[lsu_bus_buffer.scala 412:57] + node _T_2302 = or(_T_2298, _T_2301) @[lsu_bus_buffer.scala 412:31] + node _T_2303 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2304 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2305 = and(_T_2303, _T_2304) @[lsu_bus_buffer.scala 413:41] + node _T_2306 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2307 = and(_T_2305, _T_2306) @[lsu_bus_buffer.scala 413:71] + node _T_2308 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2309 = and(_T_2307, _T_2308) @[lsu_bus_buffer.scala 413:92] + node _T_2310 = or(_T_2302, _T_2309) @[lsu_bus_buffer.scala 412:86] + node _T_2311 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2312 = and(_T_2311, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2313 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2314 = and(_T_2312, _T_2313) @[lsu_bus_buffer.scala 414:52] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2316 = and(_T_2314, _T_2315) @[lsu_bus_buffer.scala 414:73] + node _T_2317 = or(_T_2310, _T_2316) @[lsu_bus_buffer.scala 413:114] + node _T_2318 = and(_T_2297, _T_2317) @[lsu_bus_buffer.scala 411:113] + node _T_2319 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2320 = or(_T_2318, _T_2319) @[lsu_bus_buffer.scala 414:97] + node _T_2321 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2322 = and(_T_2321, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2323 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2324 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2325 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2326 = and(_T_2324, _T_2325) @[lsu_bus_buffer.scala 412:57] + node _T_2327 = or(_T_2323, _T_2326) @[lsu_bus_buffer.scala 412:31] + node _T_2328 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2329 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2330 = and(_T_2328, _T_2329) @[lsu_bus_buffer.scala 413:41] + node _T_2331 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2332 = and(_T_2330, _T_2331) @[lsu_bus_buffer.scala 413:71] + node _T_2333 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2334 = and(_T_2332, _T_2333) @[lsu_bus_buffer.scala 413:92] + node _T_2335 = or(_T_2327, _T_2334) @[lsu_bus_buffer.scala 412:86] + node _T_2336 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2337 = and(_T_2336, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2338 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2339 = and(_T_2337, _T_2338) @[lsu_bus_buffer.scala 414:52] + node _T_2340 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2341 = and(_T_2339, _T_2340) @[lsu_bus_buffer.scala 414:73] + node _T_2342 = or(_T_2335, _T_2341) @[lsu_bus_buffer.scala 413:114] + node _T_2343 = and(_T_2322, _T_2342) @[lsu_bus_buffer.scala 411:113] + node _T_2344 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2345 = or(_T_2343, _T_2344) @[lsu_bus_buffer.scala 414:97] + node _T_2346 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2347 = and(_T_2346, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2348 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2349 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2350 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2351 = and(_T_2349, _T_2350) @[lsu_bus_buffer.scala 412:57] + node _T_2352 = or(_T_2348, _T_2351) @[lsu_bus_buffer.scala 412:31] + node _T_2353 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2354 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2355 = and(_T_2353, _T_2354) @[lsu_bus_buffer.scala 413:41] + node _T_2356 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2357 = and(_T_2355, _T_2356) @[lsu_bus_buffer.scala 413:71] + node _T_2358 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2359 = and(_T_2357, _T_2358) @[lsu_bus_buffer.scala 413:92] + node _T_2360 = or(_T_2352, _T_2359) @[lsu_bus_buffer.scala 412:86] + node _T_2361 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2362 = and(_T_2361, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2363 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2364 = and(_T_2362, _T_2363) @[lsu_bus_buffer.scala 414:52] + node _T_2365 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2366 = and(_T_2364, _T_2365) @[lsu_bus_buffer.scala 414:73] + node _T_2367 = or(_T_2360, _T_2366) @[lsu_bus_buffer.scala 413:114] + node _T_2368 = and(_T_2347, _T_2367) @[lsu_bus_buffer.scala 411:113] + node _T_2369 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2370 = or(_T_2368, _T_2369) @[lsu_bus_buffer.scala 414:97] + node _T_2371 = cat(_T_2370, _T_2345) @[Cat.scala 29:58] + node _T_2372 = cat(_T_2371, _T_2320) @[Cat.scala 29:58] + node buf_age_in_2 = cat(_T_2372, _T_2295) @[Cat.scala 29:58] + node _T_2373 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2374 = and(_T_2373, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2375 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2376 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2377 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2378 = and(_T_2376, _T_2377) @[lsu_bus_buffer.scala 412:57] + node _T_2379 = or(_T_2375, _T_2378) @[lsu_bus_buffer.scala 412:31] + node _T_2380 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2381 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2382 = and(_T_2380, _T_2381) @[lsu_bus_buffer.scala 413:41] + node _T_2383 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2384 = and(_T_2382, _T_2383) @[lsu_bus_buffer.scala 413:71] + node _T_2385 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2386 = and(_T_2384, _T_2385) @[lsu_bus_buffer.scala 413:92] + node _T_2387 = or(_T_2379, _T_2386) @[lsu_bus_buffer.scala 412:86] + node _T_2388 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2389 = and(_T_2388, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2390 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2391 = and(_T_2389, _T_2390) @[lsu_bus_buffer.scala 414:52] + node _T_2392 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2393 = and(_T_2391, _T_2392) @[lsu_bus_buffer.scala 414:73] + node _T_2394 = or(_T_2387, _T_2393) @[lsu_bus_buffer.scala 413:114] + node _T_2395 = and(_T_2374, _T_2394) @[lsu_bus_buffer.scala 411:113] + node _T_2396 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2397 = or(_T_2395, _T_2396) @[lsu_bus_buffer.scala 414:97] + node _T_2398 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2399 = and(_T_2398, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2400 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2401 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2402 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2403 = and(_T_2401, _T_2402) @[lsu_bus_buffer.scala 412:57] + node _T_2404 = or(_T_2400, _T_2403) @[lsu_bus_buffer.scala 412:31] + node _T_2405 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2406 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2407 = and(_T_2405, _T_2406) @[lsu_bus_buffer.scala 413:41] + node _T_2408 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2409 = and(_T_2407, _T_2408) @[lsu_bus_buffer.scala 413:71] + node _T_2410 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2411 = and(_T_2409, _T_2410) @[lsu_bus_buffer.scala 413:92] + node _T_2412 = or(_T_2404, _T_2411) @[lsu_bus_buffer.scala 412:86] + node _T_2413 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2414 = and(_T_2413, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2415 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2416 = and(_T_2414, _T_2415) @[lsu_bus_buffer.scala 414:52] + node _T_2417 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2418 = and(_T_2416, _T_2417) @[lsu_bus_buffer.scala 414:73] + node _T_2419 = or(_T_2412, _T_2418) @[lsu_bus_buffer.scala 413:114] + node _T_2420 = and(_T_2399, _T_2419) @[lsu_bus_buffer.scala 411:113] + node _T_2421 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2422 = or(_T_2420, _T_2421) @[lsu_bus_buffer.scala 414:97] + node _T_2423 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2424 = and(_T_2423, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2425 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2426 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2427 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2428 = and(_T_2426, _T_2427) @[lsu_bus_buffer.scala 412:57] + node _T_2429 = or(_T_2425, _T_2428) @[lsu_bus_buffer.scala 412:31] + node _T_2430 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2431 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2432 = and(_T_2430, _T_2431) @[lsu_bus_buffer.scala 413:41] + node _T_2433 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2434 = and(_T_2432, _T_2433) @[lsu_bus_buffer.scala 413:71] + node _T_2435 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2436 = and(_T_2434, _T_2435) @[lsu_bus_buffer.scala 413:92] + node _T_2437 = or(_T_2429, _T_2436) @[lsu_bus_buffer.scala 412:86] + node _T_2438 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2439 = and(_T_2438, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2440 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2441 = and(_T_2439, _T_2440) @[lsu_bus_buffer.scala 414:52] + node _T_2442 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2443 = and(_T_2441, _T_2442) @[lsu_bus_buffer.scala 414:73] + node _T_2444 = or(_T_2437, _T_2443) @[lsu_bus_buffer.scala 413:114] + node _T_2445 = and(_T_2424, _T_2444) @[lsu_bus_buffer.scala 411:113] + node _T_2446 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2447 = or(_T_2445, _T_2446) @[lsu_bus_buffer.scala 414:97] + node _T_2448 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2449 = and(_T_2448, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2450 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2451 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2452 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2453 = and(_T_2451, _T_2452) @[lsu_bus_buffer.scala 412:57] + node _T_2454 = or(_T_2450, _T_2453) @[lsu_bus_buffer.scala 412:31] + node _T_2455 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2456 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2457 = and(_T_2455, _T_2456) @[lsu_bus_buffer.scala 413:41] + node _T_2458 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2459 = and(_T_2457, _T_2458) @[lsu_bus_buffer.scala 413:71] + node _T_2460 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2461 = and(_T_2459, _T_2460) @[lsu_bus_buffer.scala 413:92] + node _T_2462 = or(_T_2454, _T_2461) @[lsu_bus_buffer.scala 412:86] + node _T_2463 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2464 = and(_T_2463, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2465 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2466 = and(_T_2464, _T_2465) @[lsu_bus_buffer.scala 414:52] + node _T_2467 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2468 = and(_T_2466, _T_2467) @[lsu_bus_buffer.scala 414:73] + node _T_2469 = or(_T_2462, _T_2468) @[lsu_bus_buffer.scala 413:114] + node _T_2470 = and(_T_2449, _T_2469) @[lsu_bus_buffer.scala 411:113] + node _T_2471 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2472 = or(_T_2470, _T_2471) @[lsu_bus_buffer.scala 414:97] + node _T_2473 = cat(_T_2472, _T_2447) @[Cat.scala 29:58] + node _T_2474 = cat(_T_2473, _T_2422) @[Cat.scala 29:58] + node buf_age_in_3 = cat(_T_2474, _T_2397) @[Cat.scala 29:58] + wire buf_ageQ : UInt<4>[4] @[lsu_bus_buffer.scala 415:22] + buf_ageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + node _T_2475 = bits(buf_ageQ[0], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2476 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2477 = and(_T_2476, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2478 = eq(_T_2477, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2479 = and(_T_2475, _T_2478) @[lsu_bus_buffer.scala 417:76] + node _T_2480 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2481 = and(_T_2479, _T_2480) @[lsu_bus_buffer.scala 417:130] + node _T_2482 = bits(buf_ageQ[0], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2483 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2484 = and(_T_2483, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2485 = eq(_T_2484, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2486 = and(_T_2482, _T_2485) @[lsu_bus_buffer.scala 417:76] + node _T_2487 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2488 = and(_T_2486, _T_2487) @[lsu_bus_buffer.scala 417:130] + node _T_2489 = bits(buf_ageQ[0], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2490 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2491 = and(_T_2490, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2492 = eq(_T_2491, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2493 = and(_T_2489, _T_2492) @[lsu_bus_buffer.scala 417:76] + node _T_2494 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2495 = and(_T_2493, _T_2494) @[lsu_bus_buffer.scala 417:130] + node _T_2496 = bits(buf_ageQ[0], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2497 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2498 = and(_T_2497, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2499 = eq(_T_2498, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2500 = and(_T_2496, _T_2499) @[lsu_bus_buffer.scala 417:76] + node _T_2501 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2502 = and(_T_2500, _T_2501) @[lsu_bus_buffer.scala 417:130] + node _T_2503 = cat(_T_2502, _T_2495) @[Cat.scala 29:58] + node _T_2504 = cat(_T_2503, _T_2488) @[Cat.scala 29:58] + node _T_2505 = cat(_T_2504, _T_2481) @[Cat.scala 29:58] + node _T_2506 = bits(buf_ageQ[1], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2507 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2508 = and(_T_2507, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2509 = eq(_T_2508, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2510 = and(_T_2506, _T_2509) @[lsu_bus_buffer.scala 417:76] + node _T_2511 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2512 = and(_T_2510, _T_2511) @[lsu_bus_buffer.scala 417:130] + node _T_2513 = bits(buf_ageQ[1], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2514 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2515 = and(_T_2514, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2516 = eq(_T_2515, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2517 = and(_T_2513, _T_2516) @[lsu_bus_buffer.scala 417:76] + node _T_2518 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2519 = and(_T_2517, _T_2518) @[lsu_bus_buffer.scala 417:130] + node _T_2520 = bits(buf_ageQ[1], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2521 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2522 = and(_T_2521, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2523 = eq(_T_2522, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2524 = and(_T_2520, _T_2523) @[lsu_bus_buffer.scala 417:76] + node _T_2525 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2526 = and(_T_2524, _T_2525) @[lsu_bus_buffer.scala 417:130] + node _T_2527 = bits(buf_ageQ[1], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2528 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2529 = and(_T_2528, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2530 = eq(_T_2529, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2531 = and(_T_2527, _T_2530) @[lsu_bus_buffer.scala 417:76] + node _T_2532 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2533 = and(_T_2531, _T_2532) @[lsu_bus_buffer.scala 417:130] + node _T_2534 = cat(_T_2533, _T_2526) @[Cat.scala 29:58] + node _T_2535 = cat(_T_2534, _T_2519) @[Cat.scala 29:58] + node _T_2536 = cat(_T_2535, _T_2512) @[Cat.scala 29:58] + node _T_2537 = bits(buf_ageQ[2], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2538 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2539 = and(_T_2538, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2540 = eq(_T_2539, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2541 = and(_T_2537, _T_2540) @[lsu_bus_buffer.scala 417:76] + node _T_2542 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2543 = and(_T_2541, _T_2542) @[lsu_bus_buffer.scala 417:130] + node _T_2544 = bits(buf_ageQ[2], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2545 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2546 = and(_T_2545, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2547 = eq(_T_2546, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2548 = and(_T_2544, _T_2547) @[lsu_bus_buffer.scala 417:76] + node _T_2549 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2550 = and(_T_2548, _T_2549) @[lsu_bus_buffer.scala 417:130] + node _T_2551 = bits(buf_ageQ[2], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2552 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2555 = and(_T_2551, _T_2554) @[lsu_bus_buffer.scala 417:76] + node _T_2556 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2557 = and(_T_2555, _T_2556) @[lsu_bus_buffer.scala 417:130] + node _T_2558 = bits(buf_ageQ[2], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2559 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2560 = and(_T_2559, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2561 = eq(_T_2560, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2562 = and(_T_2558, _T_2561) @[lsu_bus_buffer.scala 417:76] + node _T_2563 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2564 = and(_T_2562, _T_2563) @[lsu_bus_buffer.scala 417:130] + node _T_2565 = cat(_T_2564, _T_2557) @[Cat.scala 29:58] + node _T_2566 = cat(_T_2565, _T_2550) @[Cat.scala 29:58] + node _T_2567 = cat(_T_2566, _T_2543) @[Cat.scala 29:58] + node _T_2568 = bits(buf_ageQ[3], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2569 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2570 = and(_T_2569, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2571 = eq(_T_2570, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2572 = and(_T_2568, _T_2571) @[lsu_bus_buffer.scala 417:76] + node _T_2573 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2574 = and(_T_2572, _T_2573) @[lsu_bus_buffer.scala 417:130] + node _T_2575 = bits(buf_ageQ[3], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2576 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2577 = and(_T_2576, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2578 = eq(_T_2577, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2579 = and(_T_2575, _T_2578) @[lsu_bus_buffer.scala 417:76] + node _T_2580 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2581 = and(_T_2579, _T_2580) @[lsu_bus_buffer.scala 417:130] + node _T_2582 = bits(buf_ageQ[3], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2583 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2586 = and(_T_2582, _T_2585) @[lsu_bus_buffer.scala 417:76] + node _T_2587 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2588 = and(_T_2586, _T_2587) @[lsu_bus_buffer.scala 417:130] + node _T_2589 = bits(buf_ageQ[3], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2590 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2591 = and(_T_2590, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2592 = eq(_T_2591, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2593 = and(_T_2589, _T_2592) @[lsu_bus_buffer.scala 417:76] + node _T_2594 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2595 = and(_T_2593, _T_2594) @[lsu_bus_buffer.scala 417:130] + node _T_2596 = cat(_T_2595, _T_2588) @[Cat.scala 29:58] + node _T_2597 = cat(_T_2596, _T_2581) @[Cat.scala 29:58] + node _T_2598 = cat(_T_2597, _T_2574) @[Cat.scala 29:58] + buf_age[0] <= _T_2505 @[lsu_bus_buffer.scala 417:11] + buf_age[1] <= _T_2536 @[lsu_bus_buffer.scala 417:11] + buf_age[2] <= _T_2567 @[lsu_bus_buffer.scala 417:11] + buf_age[3] <= _T_2598 @[lsu_bus_buffer.scala 417:11] + node _T_2599 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2600 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2601 = eq(_T_2600, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2602 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2603 = and(_T_2601, _T_2602) @[lsu_bus_buffer.scala 418:104] + node _T_2604 = mux(_T_2599, UInt<1>("h00"), _T_2603) @[lsu_bus_buffer.scala 418:72] + node _T_2605 = eq(UInt<1>("h00"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2606 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2607 = eq(_T_2606, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2608 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2609 = and(_T_2607, _T_2608) @[lsu_bus_buffer.scala 418:104] + node _T_2610 = mux(_T_2605, UInt<1>("h00"), _T_2609) @[lsu_bus_buffer.scala 418:72] + node _T_2611 = eq(UInt<1>("h00"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2612 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2614 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2615 = and(_T_2613, _T_2614) @[lsu_bus_buffer.scala 418:104] + node _T_2616 = mux(_T_2611, UInt<1>("h00"), _T_2615) @[lsu_bus_buffer.scala 418:72] + node _T_2617 = eq(UInt<1>("h00"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2618 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2619 = eq(_T_2618, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2620 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2621 = and(_T_2619, _T_2620) @[lsu_bus_buffer.scala 418:104] + node _T_2622 = mux(_T_2617, UInt<1>("h00"), _T_2621) @[lsu_bus_buffer.scala 418:72] + node _T_2623 = cat(_T_2622, _T_2616) @[Cat.scala 29:58] + node _T_2624 = cat(_T_2623, _T_2610) @[Cat.scala 29:58] + node _T_2625 = cat(_T_2624, _T_2604) @[Cat.scala 29:58] + node _T_2626 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2627 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2628 = eq(_T_2627, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2629 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2630 = and(_T_2628, _T_2629) @[lsu_bus_buffer.scala 418:104] + node _T_2631 = mux(_T_2626, UInt<1>("h00"), _T_2630) @[lsu_bus_buffer.scala 418:72] + node _T_2632 = eq(UInt<1>("h01"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2633 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2634 = eq(_T_2633, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2635 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2636 = and(_T_2634, _T_2635) @[lsu_bus_buffer.scala 418:104] + node _T_2637 = mux(_T_2632, UInt<1>("h00"), _T_2636) @[lsu_bus_buffer.scala 418:72] + node _T_2638 = eq(UInt<1>("h01"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2639 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2640 = eq(_T_2639, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2641 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2642 = and(_T_2640, _T_2641) @[lsu_bus_buffer.scala 418:104] + node _T_2643 = mux(_T_2638, UInt<1>("h00"), _T_2642) @[lsu_bus_buffer.scala 418:72] + node _T_2644 = eq(UInt<1>("h01"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2645 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2646 = eq(_T_2645, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2647 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2648 = and(_T_2646, _T_2647) @[lsu_bus_buffer.scala 418:104] + node _T_2649 = mux(_T_2644, UInt<1>("h00"), _T_2648) @[lsu_bus_buffer.scala 418:72] + node _T_2650 = cat(_T_2649, _T_2643) @[Cat.scala 29:58] + node _T_2651 = cat(_T_2650, _T_2637) @[Cat.scala 29:58] + node _T_2652 = cat(_T_2651, _T_2631) @[Cat.scala 29:58] + node _T_2653 = eq(UInt<2>("h02"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2654 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2655 = eq(_T_2654, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2656 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2657 = and(_T_2655, _T_2656) @[lsu_bus_buffer.scala 418:104] + node _T_2658 = mux(_T_2653, UInt<1>("h00"), _T_2657) @[lsu_bus_buffer.scala 418:72] + node _T_2659 = eq(UInt<2>("h02"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2660 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2661 = eq(_T_2660, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2662 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2663 = and(_T_2661, _T_2662) @[lsu_bus_buffer.scala 418:104] + node _T_2664 = mux(_T_2659, UInt<1>("h00"), _T_2663) @[lsu_bus_buffer.scala 418:72] + node _T_2665 = eq(UInt<2>("h02"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2666 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2667 = eq(_T_2666, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2668 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2669 = and(_T_2667, _T_2668) @[lsu_bus_buffer.scala 418:104] + node _T_2670 = mux(_T_2665, UInt<1>("h00"), _T_2669) @[lsu_bus_buffer.scala 418:72] + node _T_2671 = eq(UInt<2>("h02"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2672 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2673 = eq(_T_2672, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2674 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2675 = and(_T_2673, _T_2674) @[lsu_bus_buffer.scala 418:104] + node _T_2676 = mux(_T_2671, UInt<1>("h00"), _T_2675) @[lsu_bus_buffer.scala 418:72] + node _T_2677 = cat(_T_2676, _T_2670) @[Cat.scala 29:58] + node _T_2678 = cat(_T_2677, _T_2664) @[Cat.scala 29:58] + node _T_2679 = cat(_T_2678, _T_2658) @[Cat.scala 29:58] + node _T_2680 = eq(UInt<2>("h03"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2681 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2682 = eq(_T_2681, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2683 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2684 = and(_T_2682, _T_2683) @[lsu_bus_buffer.scala 418:104] + node _T_2685 = mux(_T_2680, UInt<1>("h00"), _T_2684) @[lsu_bus_buffer.scala 418:72] + node _T_2686 = eq(UInt<2>("h03"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2687 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2688 = eq(_T_2687, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2689 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2690 = and(_T_2688, _T_2689) @[lsu_bus_buffer.scala 418:104] + node _T_2691 = mux(_T_2686, UInt<1>("h00"), _T_2690) @[lsu_bus_buffer.scala 418:72] + node _T_2692 = eq(UInt<2>("h03"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2693 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2694 = eq(_T_2693, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2695 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2696 = and(_T_2694, _T_2695) @[lsu_bus_buffer.scala 418:104] + node _T_2697 = mux(_T_2692, UInt<1>("h00"), _T_2696) @[lsu_bus_buffer.scala 418:72] + node _T_2698 = eq(UInt<2>("h03"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2699 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2700 = eq(_T_2699, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2701 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2702 = and(_T_2700, _T_2701) @[lsu_bus_buffer.scala 418:104] + node _T_2703 = mux(_T_2698, UInt<1>("h00"), _T_2702) @[lsu_bus_buffer.scala 418:72] + node _T_2704 = cat(_T_2703, _T_2697) @[Cat.scala 29:58] + node _T_2705 = cat(_T_2704, _T_2691) @[Cat.scala 29:58] + node _T_2706 = cat(_T_2705, _T_2685) @[Cat.scala 29:58] + buf_age_younger[0] <= _T_2625 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[1] <= _T_2652 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[2] <= _T_2679 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[3] <= _T_2706 @[lsu_bus_buffer.scala 418:19] + node _T_2707 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2708 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2709 = and(_T_2707, _T_2708) @[lsu_bus_buffer.scala 419:87] + node _T_2710 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2711 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2712 = and(_T_2710, _T_2711) @[lsu_bus_buffer.scala 419:87] + node _T_2713 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2714 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2715 = and(_T_2713, _T_2714) @[lsu_bus_buffer.scala 419:87] + node _T_2716 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2717 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2718 = and(_T_2716, _T_2717) @[lsu_bus_buffer.scala 419:87] + node _T_2719 = cat(_T_2718, _T_2715) @[Cat.scala 29:58] + node _T_2720 = cat(_T_2719, _T_2712) @[Cat.scala 29:58] + node _T_2721 = cat(_T_2720, _T_2709) @[Cat.scala 29:58] + node _T_2722 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2723 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2724 = and(_T_2722, _T_2723) @[lsu_bus_buffer.scala 419:87] + node _T_2725 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2726 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2727 = and(_T_2725, _T_2726) @[lsu_bus_buffer.scala 419:87] + node _T_2728 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2729 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2730 = and(_T_2728, _T_2729) @[lsu_bus_buffer.scala 419:87] + node _T_2731 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2732 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2733 = and(_T_2731, _T_2732) @[lsu_bus_buffer.scala 419:87] + node _T_2734 = cat(_T_2733, _T_2730) @[Cat.scala 29:58] + node _T_2735 = cat(_T_2734, _T_2727) @[Cat.scala 29:58] + node _T_2736 = cat(_T_2735, _T_2724) @[Cat.scala 29:58] + node _T_2737 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2738 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2739 = and(_T_2737, _T_2738) @[lsu_bus_buffer.scala 419:87] + node _T_2740 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2741 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2742 = and(_T_2740, _T_2741) @[lsu_bus_buffer.scala 419:87] + node _T_2743 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2744 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2745 = and(_T_2743, _T_2744) @[lsu_bus_buffer.scala 419:87] + node _T_2746 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2747 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2748 = and(_T_2746, _T_2747) @[lsu_bus_buffer.scala 419:87] + node _T_2749 = cat(_T_2748, _T_2745) @[Cat.scala 29:58] + node _T_2750 = cat(_T_2749, _T_2742) @[Cat.scala 29:58] + node _T_2751 = cat(_T_2750, _T_2739) @[Cat.scala 29:58] + node _T_2752 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2753 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2754 = and(_T_2752, _T_2753) @[lsu_bus_buffer.scala 419:87] + node _T_2755 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2756 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2757 = and(_T_2755, _T_2756) @[lsu_bus_buffer.scala 419:87] + node _T_2758 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2759 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2760 = and(_T_2758, _T_2759) @[lsu_bus_buffer.scala 419:87] + node _T_2761 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2762 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2763 = and(_T_2761, _T_2762) @[lsu_bus_buffer.scala 419:87] + node _T_2764 = cat(_T_2763, _T_2760) @[Cat.scala 29:58] + node _T_2765 = cat(_T_2764, _T_2757) @[Cat.scala 29:58] + node _T_2766 = cat(_T_2765, _T_2754) @[Cat.scala 29:58] + buf_rsp_pickage[0] <= _T_2721 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[1] <= _T_2736 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[2] <= _T_2751 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[3] <= _T_2766 @[lsu_bus_buffer.scala 419:19] + node _T_2767 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2768 = and(_T_2767, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2769 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2770 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2771 = or(_T_2769, _T_2770) @[lsu_bus_buffer.scala 422:32] + node _T_2772 = eq(_T_2771, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2773 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2774 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2775 = and(_T_2773, _T_2774) @[lsu_bus_buffer.scala 423:41] + node _T_2776 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2777 = and(_T_2775, _T_2776) @[lsu_bus_buffer.scala 423:71] + node _T_2778 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2779 = and(_T_2777, _T_2778) @[lsu_bus_buffer.scala 423:90] + node _T_2780 = or(_T_2772, _T_2779) @[lsu_bus_buffer.scala 422:59] + node _T_2781 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2782 = and(_T_2781, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2783 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2784 = and(_T_2782, _T_2783) @[lsu_bus_buffer.scala 424:52] + node _T_2785 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2786 = and(_T_2784, _T_2785) @[lsu_bus_buffer.scala 424:71] + node _T_2787 = or(_T_2780, _T_2786) @[lsu_bus_buffer.scala 423:110] + node _T_2788 = and(_T_2768, _T_2787) @[lsu_bus_buffer.scala 421:112] + node _T_2789 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2790 = and(_T_2789, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2791 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2792 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2793 = or(_T_2791, _T_2792) @[lsu_bus_buffer.scala 422:32] + node _T_2794 = eq(_T_2793, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2795 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2796 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2797 = and(_T_2795, _T_2796) @[lsu_bus_buffer.scala 423:41] + node _T_2798 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2799 = and(_T_2797, _T_2798) @[lsu_bus_buffer.scala 423:71] + node _T_2800 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2801 = and(_T_2799, _T_2800) @[lsu_bus_buffer.scala 423:90] + node _T_2802 = or(_T_2794, _T_2801) @[lsu_bus_buffer.scala 422:59] + node _T_2803 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2804 = and(_T_2803, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2805 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2806 = and(_T_2804, _T_2805) @[lsu_bus_buffer.scala 424:52] + node _T_2807 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2808 = and(_T_2806, _T_2807) @[lsu_bus_buffer.scala 424:71] + node _T_2809 = or(_T_2802, _T_2808) @[lsu_bus_buffer.scala 423:110] + node _T_2810 = and(_T_2790, _T_2809) @[lsu_bus_buffer.scala 421:112] + node _T_2811 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2812 = and(_T_2811, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2813 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2814 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2815 = or(_T_2813, _T_2814) @[lsu_bus_buffer.scala 422:32] + node _T_2816 = eq(_T_2815, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2817 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2818 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2819 = and(_T_2817, _T_2818) @[lsu_bus_buffer.scala 423:41] + node _T_2820 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2821 = and(_T_2819, _T_2820) @[lsu_bus_buffer.scala 423:71] + node _T_2822 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_2823 = and(_T_2821, _T_2822) @[lsu_bus_buffer.scala 423:90] + node _T_2824 = or(_T_2816, _T_2823) @[lsu_bus_buffer.scala 422:59] + node _T_2825 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2826 = and(_T_2825, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2827 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2828 = and(_T_2826, _T_2827) @[lsu_bus_buffer.scala 424:52] + node _T_2829 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_2830 = and(_T_2828, _T_2829) @[lsu_bus_buffer.scala 424:71] + node _T_2831 = or(_T_2824, _T_2830) @[lsu_bus_buffer.scala 423:110] + node _T_2832 = and(_T_2812, _T_2831) @[lsu_bus_buffer.scala 421:112] + node _T_2833 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2834 = and(_T_2833, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2835 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2836 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2837 = or(_T_2835, _T_2836) @[lsu_bus_buffer.scala 422:32] + node _T_2838 = eq(_T_2837, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2839 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2840 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2841 = and(_T_2839, _T_2840) @[lsu_bus_buffer.scala 423:41] + node _T_2842 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2843 = and(_T_2841, _T_2842) @[lsu_bus_buffer.scala 423:71] + node _T_2844 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_2845 = and(_T_2843, _T_2844) @[lsu_bus_buffer.scala 423:90] + node _T_2846 = or(_T_2838, _T_2845) @[lsu_bus_buffer.scala 422:59] + node _T_2847 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2848 = and(_T_2847, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2849 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2850 = and(_T_2848, _T_2849) @[lsu_bus_buffer.scala 424:52] + node _T_2851 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_2852 = and(_T_2850, _T_2851) @[lsu_bus_buffer.scala 424:71] + node _T_2853 = or(_T_2846, _T_2852) @[lsu_bus_buffer.scala 423:110] + node _T_2854 = and(_T_2834, _T_2853) @[lsu_bus_buffer.scala 421:112] + node _T_2855 = cat(_T_2854, _T_2832) @[Cat.scala 29:58] + node _T_2856 = cat(_T_2855, _T_2810) @[Cat.scala 29:58] + node _T_2857 = cat(_T_2856, _T_2788) @[Cat.scala 29:58] + node _T_2858 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2859 = and(_T_2858, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2860 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2861 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2862 = or(_T_2860, _T_2861) @[lsu_bus_buffer.scala 422:32] + node _T_2863 = eq(_T_2862, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2864 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2865 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2866 = and(_T_2864, _T_2865) @[lsu_bus_buffer.scala 423:41] + node _T_2867 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2868 = and(_T_2866, _T_2867) @[lsu_bus_buffer.scala 423:71] + node _T_2869 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2870 = and(_T_2868, _T_2869) @[lsu_bus_buffer.scala 423:90] + node _T_2871 = or(_T_2863, _T_2870) @[lsu_bus_buffer.scala 422:59] + node _T_2872 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2873 = and(_T_2872, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2874 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2875 = and(_T_2873, _T_2874) @[lsu_bus_buffer.scala 424:52] + node _T_2876 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2877 = and(_T_2875, _T_2876) @[lsu_bus_buffer.scala 424:71] + node _T_2878 = or(_T_2871, _T_2877) @[lsu_bus_buffer.scala 423:110] + node _T_2879 = and(_T_2859, _T_2878) @[lsu_bus_buffer.scala 421:112] + node _T_2880 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2881 = and(_T_2880, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2882 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2883 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2884 = or(_T_2882, _T_2883) @[lsu_bus_buffer.scala 422:32] + node _T_2885 = eq(_T_2884, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2886 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2887 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2888 = and(_T_2886, _T_2887) @[lsu_bus_buffer.scala 423:41] + node _T_2889 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2890 = and(_T_2888, _T_2889) @[lsu_bus_buffer.scala 423:71] + node _T_2891 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2892 = and(_T_2890, _T_2891) @[lsu_bus_buffer.scala 423:90] + node _T_2893 = or(_T_2885, _T_2892) @[lsu_bus_buffer.scala 422:59] + node _T_2894 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2895 = and(_T_2894, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2896 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2897 = and(_T_2895, _T_2896) @[lsu_bus_buffer.scala 424:52] + node _T_2898 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2899 = and(_T_2897, _T_2898) @[lsu_bus_buffer.scala 424:71] + node _T_2900 = or(_T_2893, _T_2899) @[lsu_bus_buffer.scala 423:110] + node _T_2901 = and(_T_2881, _T_2900) @[lsu_bus_buffer.scala 421:112] + node _T_2902 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2903 = and(_T_2902, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2904 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2905 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2906 = or(_T_2904, _T_2905) @[lsu_bus_buffer.scala 422:32] + node _T_2907 = eq(_T_2906, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2908 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2909 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2910 = and(_T_2908, _T_2909) @[lsu_bus_buffer.scala 423:41] + node _T_2911 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2912 = and(_T_2910, _T_2911) @[lsu_bus_buffer.scala 423:71] + node _T_2913 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_2914 = and(_T_2912, _T_2913) @[lsu_bus_buffer.scala 423:90] + node _T_2915 = or(_T_2907, _T_2914) @[lsu_bus_buffer.scala 422:59] + node _T_2916 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2917 = and(_T_2916, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2918 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2919 = and(_T_2917, _T_2918) @[lsu_bus_buffer.scala 424:52] + node _T_2920 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_2921 = and(_T_2919, _T_2920) @[lsu_bus_buffer.scala 424:71] + node _T_2922 = or(_T_2915, _T_2921) @[lsu_bus_buffer.scala 423:110] + node _T_2923 = and(_T_2903, _T_2922) @[lsu_bus_buffer.scala 421:112] + node _T_2924 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2925 = and(_T_2924, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2926 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2927 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2928 = or(_T_2926, _T_2927) @[lsu_bus_buffer.scala 422:32] + node _T_2929 = eq(_T_2928, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2930 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2931 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2932 = and(_T_2930, _T_2931) @[lsu_bus_buffer.scala 423:41] + node _T_2933 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2934 = and(_T_2932, _T_2933) @[lsu_bus_buffer.scala 423:71] + node _T_2935 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_2936 = and(_T_2934, _T_2935) @[lsu_bus_buffer.scala 423:90] + node _T_2937 = or(_T_2929, _T_2936) @[lsu_bus_buffer.scala 422:59] + node _T_2938 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2939 = and(_T_2938, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2940 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2941 = and(_T_2939, _T_2940) @[lsu_bus_buffer.scala 424:52] + node _T_2942 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_2943 = and(_T_2941, _T_2942) @[lsu_bus_buffer.scala 424:71] + node _T_2944 = or(_T_2937, _T_2943) @[lsu_bus_buffer.scala 423:110] + node _T_2945 = and(_T_2925, _T_2944) @[lsu_bus_buffer.scala 421:112] + node _T_2946 = cat(_T_2945, _T_2923) @[Cat.scala 29:58] + node _T_2947 = cat(_T_2946, _T_2901) @[Cat.scala 29:58] + node _T_2948 = cat(_T_2947, _T_2879) @[Cat.scala 29:58] + node _T_2949 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2950 = and(_T_2949, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2951 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2952 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2953 = or(_T_2951, _T_2952) @[lsu_bus_buffer.scala 422:32] + node _T_2954 = eq(_T_2953, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2955 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2956 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2957 = and(_T_2955, _T_2956) @[lsu_bus_buffer.scala 423:41] + node _T_2958 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_2959 = and(_T_2957, _T_2958) @[lsu_bus_buffer.scala 423:71] + node _T_2960 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2961 = and(_T_2959, _T_2960) @[lsu_bus_buffer.scala 423:90] + node _T_2962 = or(_T_2954, _T_2961) @[lsu_bus_buffer.scala 422:59] + node _T_2963 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2964 = and(_T_2963, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2965 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_2966 = and(_T_2964, _T_2965) @[lsu_bus_buffer.scala 424:52] + node _T_2967 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2968 = and(_T_2966, _T_2967) @[lsu_bus_buffer.scala 424:71] + node _T_2969 = or(_T_2962, _T_2968) @[lsu_bus_buffer.scala 423:110] + node _T_2970 = and(_T_2950, _T_2969) @[lsu_bus_buffer.scala 421:112] + node _T_2971 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2972 = and(_T_2971, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2973 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2974 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2975 = or(_T_2973, _T_2974) @[lsu_bus_buffer.scala 422:32] + node _T_2976 = eq(_T_2975, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2977 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2978 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2979 = and(_T_2977, _T_2978) @[lsu_bus_buffer.scala 423:41] + node _T_2980 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_2981 = and(_T_2979, _T_2980) @[lsu_bus_buffer.scala 423:71] + node _T_2982 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2983 = and(_T_2981, _T_2982) @[lsu_bus_buffer.scala 423:90] + node _T_2984 = or(_T_2976, _T_2983) @[lsu_bus_buffer.scala 422:59] + node _T_2985 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2986 = and(_T_2985, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2987 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_2988 = and(_T_2986, _T_2987) @[lsu_bus_buffer.scala 424:52] + node _T_2989 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2990 = and(_T_2988, _T_2989) @[lsu_bus_buffer.scala 424:71] + node _T_2991 = or(_T_2984, _T_2990) @[lsu_bus_buffer.scala 423:110] + node _T_2992 = and(_T_2972, _T_2991) @[lsu_bus_buffer.scala 421:112] + node _T_2993 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2994 = and(_T_2993, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2995 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2996 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2997 = or(_T_2995, _T_2996) @[lsu_bus_buffer.scala 422:32] + node _T_2998 = eq(_T_2997, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2999 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3000 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3001 = and(_T_2999, _T_3000) @[lsu_bus_buffer.scala 423:41] + node _T_3002 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_3003 = and(_T_3001, _T_3002) @[lsu_bus_buffer.scala 423:71] + node _T_3004 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_3005 = and(_T_3003, _T_3004) @[lsu_bus_buffer.scala 423:90] + node _T_3006 = or(_T_2998, _T_3005) @[lsu_bus_buffer.scala 422:59] + node _T_3007 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3008 = and(_T_3007, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3009 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_3010 = and(_T_3008, _T_3009) @[lsu_bus_buffer.scala 424:52] + node _T_3011 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_3012 = and(_T_3010, _T_3011) @[lsu_bus_buffer.scala 424:71] + node _T_3013 = or(_T_3006, _T_3012) @[lsu_bus_buffer.scala 423:110] + node _T_3014 = and(_T_2994, _T_3013) @[lsu_bus_buffer.scala 421:112] + node _T_3015 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3016 = and(_T_3015, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_3017 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3018 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3019 = or(_T_3017, _T_3018) @[lsu_bus_buffer.scala 422:32] + node _T_3020 = eq(_T_3019, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3021 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3022 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3023 = and(_T_3021, _T_3022) @[lsu_bus_buffer.scala 423:41] + node _T_3024 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_3025 = and(_T_3023, _T_3024) @[lsu_bus_buffer.scala 423:71] + node _T_3026 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_3027 = and(_T_3025, _T_3026) @[lsu_bus_buffer.scala 423:90] + node _T_3028 = or(_T_3020, _T_3027) @[lsu_bus_buffer.scala 422:59] + node _T_3029 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3030 = and(_T_3029, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3031 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_3032 = and(_T_3030, _T_3031) @[lsu_bus_buffer.scala 424:52] + node _T_3033 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_3034 = and(_T_3032, _T_3033) @[lsu_bus_buffer.scala 424:71] + node _T_3035 = or(_T_3028, _T_3034) @[lsu_bus_buffer.scala 423:110] + node _T_3036 = and(_T_3016, _T_3035) @[lsu_bus_buffer.scala 421:112] + node _T_3037 = cat(_T_3036, _T_3014) @[Cat.scala 29:58] + node _T_3038 = cat(_T_3037, _T_2992) @[Cat.scala 29:58] + node _T_3039 = cat(_T_3038, _T_2970) @[Cat.scala 29:58] + node _T_3040 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3041 = and(_T_3040, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3042 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3043 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3044 = or(_T_3042, _T_3043) @[lsu_bus_buffer.scala 422:32] + node _T_3045 = eq(_T_3044, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3046 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3047 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3048 = and(_T_3046, _T_3047) @[lsu_bus_buffer.scala 423:41] + node _T_3049 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3050 = and(_T_3048, _T_3049) @[lsu_bus_buffer.scala 423:71] + node _T_3051 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_3052 = and(_T_3050, _T_3051) @[lsu_bus_buffer.scala 423:90] + node _T_3053 = or(_T_3045, _T_3052) @[lsu_bus_buffer.scala 422:59] + node _T_3054 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3055 = and(_T_3054, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3056 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3057 = and(_T_3055, _T_3056) @[lsu_bus_buffer.scala 424:52] + node _T_3058 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_3059 = and(_T_3057, _T_3058) @[lsu_bus_buffer.scala 424:71] + node _T_3060 = or(_T_3053, _T_3059) @[lsu_bus_buffer.scala 423:110] + node _T_3061 = and(_T_3041, _T_3060) @[lsu_bus_buffer.scala 421:112] + node _T_3062 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3063 = and(_T_3062, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3064 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3065 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3066 = or(_T_3064, _T_3065) @[lsu_bus_buffer.scala 422:32] + node _T_3067 = eq(_T_3066, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3068 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3069 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3070 = and(_T_3068, _T_3069) @[lsu_bus_buffer.scala 423:41] + node _T_3071 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3072 = and(_T_3070, _T_3071) @[lsu_bus_buffer.scala 423:71] + node _T_3073 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_3074 = and(_T_3072, _T_3073) @[lsu_bus_buffer.scala 423:90] + node _T_3075 = or(_T_3067, _T_3074) @[lsu_bus_buffer.scala 422:59] + node _T_3076 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3077 = and(_T_3076, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3078 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3079 = and(_T_3077, _T_3078) @[lsu_bus_buffer.scala 424:52] + node _T_3080 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_3081 = and(_T_3079, _T_3080) @[lsu_bus_buffer.scala 424:71] + node _T_3082 = or(_T_3075, _T_3081) @[lsu_bus_buffer.scala 423:110] + node _T_3083 = and(_T_3063, _T_3082) @[lsu_bus_buffer.scala 421:112] + node _T_3084 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3085 = and(_T_3084, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3086 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3087 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3088 = or(_T_3086, _T_3087) @[lsu_bus_buffer.scala 422:32] + node _T_3089 = eq(_T_3088, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3090 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3091 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3092 = and(_T_3090, _T_3091) @[lsu_bus_buffer.scala 423:41] + node _T_3093 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3094 = and(_T_3092, _T_3093) @[lsu_bus_buffer.scala 423:71] + node _T_3095 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_3096 = and(_T_3094, _T_3095) @[lsu_bus_buffer.scala 423:90] + node _T_3097 = or(_T_3089, _T_3096) @[lsu_bus_buffer.scala 422:59] + node _T_3098 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3099 = and(_T_3098, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3100 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3101 = and(_T_3099, _T_3100) @[lsu_bus_buffer.scala 424:52] + node _T_3102 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_3103 = and(_T_3101, _T_3102) @[lsu_bus_buffer.scala 424:71] + node _T_3104 = or(_T_3097, _T_3103) @[lsu_bus_buffer.scala 423:110] + node _T_3105 = and(_T_3085, _T_3104) @[lsu_bus_buffer.scala 421:112] + node _T_3106 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3107 = and(_T_3106, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3108 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3109 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3110 = or(_T_3108, _T_3109) @[lsu_bus_buffer.scala 422:32] + node _T_3111 = eq(_T_3110, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3112 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3113 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3114 = and(_T_3112, _T_3113) @[lsu_bus_buffer.scala 423:41] + node _T_3115 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3116 = and(_T_3114, _T_3115) @[lsu_bus_buffer.scala 423:71] + node _T_3117 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_3118 = and(_T_3116, _T_3117) @[lsu_bus_buffer.scala 423:90] + node _T_3119 = or(_T_3111, _T_3118) @[lsu_bus_buffer.scala 422:59] + node _T_3120 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3121 = and(_T_3120, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3122 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3123 = and(_T_3121, _T_3122) @[lsu_bus_buffer.scala 424:52] + node _T_3124 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_3125 = and(_T_3123, _T_3124) @[lsu_bus_buffer.scala 424:71] + node _T_3126 = or(_T_3119, _T_3125) @[lsu_bus_buffer.scala 423:110] + node _T_3127 = and(_T_3107, _T_3126) @[lsu_bus_buffer.scala 421:112] + node _T_3128 = cat(_T_3127, _T_3105) @[Cat.scala 29:58] + node _T_3129 = cat(_T_3128, _T_3083) @[Cat.scala 29:58] + node _T_3130 = cat(_T_3129, _T_3061) @[Cat.scala 29:58] + buf_rspage_set[0] <= _T_2857 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[1] <= _T_2948 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[2] <= _T_3039 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[3] <= _T_3130 @[lsu_bus_buffer.scala 421:18] + node _T_3131 = bits(buf_rspage_set[0], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3132 = bits(buf_rspage[0], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3133 = or(_T_3131, _T_3132) @[lsu_bus_buffer.scala 425:88] + node _T_3134 = bits(buf_rspage_set[0], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3135 = bits(buf_rspage[0], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3136 = or(_T_3134, _T_3135) @[lsu_bus_buffer.scala 425:88] + node _T_3137 = bits(buf_rspage_set[0], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3138 = bits(buf_rspage[0], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3139 = or(_T_3137, _T_3138) @[lsu_bus_buffer.scala 425:88] + node _T_3140 = bits(buf_rspage_set[0], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3141 = bits(buf_rspage[0], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3142 = or(_T_3140, _T_3141) @[lsu_bus_buffer.scala 425:88] + node _T_3143 = cat(_T_3142, _T_3139) @[Cat.scala 29:58] + node _T_3144 = cat(_T_3143, _T_3136) @[Cat.scala 29:58] + node _T_3145 = cat(_T_3144, _T_3133) @[Cat.scala 29:58] + node _T_3146 = bits(buf_rspage_set[1], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3147 = bits(buf_rspage[1], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3148 = or(_T_3146, _T_3147) @[lsu_bus_buffer.scala 425:88] + node _T_3149 = bits(buf_rspage_set[1], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3150 = bits(buf_rspage[1], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3151 = or(_T_3149, _T_3150) @[lsu_bus_buffer.scala 425:88] + node _T_3152 = bits(buf_rspage_set[1], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3153 = bits(buf_rspage[1], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3154 = or(_T_3152, _T_3153) @[lsu_bus_buffer.scala 425:88] + node _T_3155 = bits(buf_rspage_set[1], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3156 = bits(buf_rspage[1], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3157 = or(_T_3155, _T_3156) @[lsu_bus_buffer.scala 425:88] + node _T_3158 = cat(_T_3157, _T_3154) @[Cat.scala 29:58] + node _T_3159 = cat(_T_3158, _T_3151) @[Cat.scala 29:58] + node _T_3160 = cat(_T_3159, _T_3148) @[Cat.scala 29:58] + node _T_3161 = bits(buf_rspage_set[2], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3162 = bits(buf_rspage[2], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3163 = or(_T_3161, _T_3162) @[lsu_bus_buffer.scala 425:88] + node _T_3164 = bits(buf_rspage_set[2], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3165 = bits(buf_rspage[2], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3166 = or(_T_3164, _T_3165) @[lsu_bus_buffer.scala 425:88] + node _T_3167 = bits(buf_rspage_set[2], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3168 = bits(buf_rspage[2], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3169 = or(_T_3167, _T_3168) @[lsu_bus_buffer.scala 425:88] + node _T_3170 = bits(buf_rspage_set[2], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3171 = bits(buf_rspage[2], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3172 = or(_T_3170, _T_3171) @[lsu_bus_buffer.scala 425:88] + node _T_3173 = cat(_T_3172, _T_3169) @[Cat.scala 29:58] + node _T_3174 = cat(_T_3173, _T_3166) @[Cat.scala 29:58] + node _T_3175 = cat(_T_3174, _T_3163) @[Cat.scala 29:58] + node _T_3176 = bits(buf_rspage_set[3], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3177 = bits(buf_rspage[3], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3178 = or(_T_3176, _T_3177) @[lsu_bus_buffer.scala 425:88] + node _T_3179 = bits(buf_rspage_set[3], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3180 = bits(buf_rspage[3], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3181 = or(_T_3179, _T_3180) @[lsu_bus_buffer.scala 425:88] + node _T_3182 = bits(buf_rspage_set[3], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3183 = bits(buf_rspage[3], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3184 = or(_T_3182, _T_3183) @[lsu_bus_buffer.scala 425:88] + node _T_3185 = bits(buf_rspage_set[3], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3186 = bits(buf_rspage[3], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3187 = or(_T_3185, _T_3186) @[lsu_bus_buffer.scala 425:88] + node _T_3188 = cat(_T_3187, _T_3184) @[Cat.scala 29:58] + node _T_3189 = cat(_T_3188, _T_3181) @[Cat.scala 29:58] + node _T_3190 = cat(_T_3189, _T_3178) @[Cat.scala 29:58] + buf_rspage_in[0] <= _T_3145 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[1] <= _T_3160 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[2] <= _T_3175 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[3] <= _T_3190 @[lsu_bus_buffer.scala 425:17] + node _T_3191 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3192 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3193 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3194 = or(_T_3192, _T_3193) @[lsu_bus_buffer.scala 426:110] + node _T_3195 = eq(_T_3194, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3196 = and(_T_3191, _T_3195) @[lsu_bus_buffer.scala 426:82] + node _T_3197 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3198 = and(_T_3196, _T_3197) @[lsu_bus_buffer.scala 426:136] + node _T_3199 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3200 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3201 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3202 = or(_T_3200, _T_3201) @[lsu_bus_buffer.scala 426:110] + node _T_3203 = eq(_T_3202, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3204 = and(_T_3199, _T_3203) @[lsu_bus_buffer.scala 426:82] + node _T_3205 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3206 = and(_T_3204, _T_3205) @[lsu_bus_buffer.scala 426:136] + node _T_3207 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3208 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3209 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3210 = or(_T_3208, _T_3209) @[lsu_bus_buffer.scala 426:110] + node _T_3211 = eq(_T_3210, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3212 = and(_T_3207, _T_3211) @[lsu_bus_buffer.scala 426:82] + node _T_3213 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3214 = and(_T_3212, _T_3213) @[lsu_bus_buffer.scala 426:136] + node _T_3215 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3216 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3217 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3218 = or(_T_3216, _T_3217) @[lsu_bus_buffer.scala 426:110] + node _T_3219 = eq(_T_3218, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3220 = and(_T_3215, _T_3219) @[lsu_bus_buffer.scala 426:82] + node _T_3221 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3222 = and(_T_3220, _T_3221) @[lsu_bus_buffer.scala 426:136] + node _T_3223 = cat(_T_3222, _T_3214) @[Cat.scala 29:58] + node _T_3224 = cat(_T_3223, _T_3206) @[Cat.scala 29:58] + node _T_3225 = cat(_T_3224, _T_3198) @[Cat.scala 29:58] + node _T_3226 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3227 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3228 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3229 = or(_T_3227, _T_3228) @[lsu_bus_buffer.scala 426:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3231 = and(_T_3226, _T_3230) @[lsu_bus_buffer.scala 426:82] + node _T_3232 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3233 = and(_T_3231, _T_3232) @[lsu_bus_buffer.scala 426:136] + node _T_3234 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3235 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3236 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3237 = or(_T_3235, _T_3236) @[lsu_bus_buffer.scala 426:110] + node _T_3238 = eq(_T_3237, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3239 = and(_T_3234, _T_3238) @[lsu_bus_buffer.scala 426:82] + node _T_3240 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3241 = and(_T_3239, _T_3240) @[lsu_bus_buffer.scala 426:136] + node _T_3242 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3243 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3244 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3245 = or(_T_3243, _T_3244) @[lsu_bus_buffer.scala 426:110] + node _T_3246 = eq(_T_3245, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3247 = and(_T_3242, _T_3246) @[lsu_bus_buffer.scala 426:82] + node _T_3248 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3249 = and(_T_3247, _T_3248) @[lsu_bus_buffer.scala 426:136] + node _T_3250 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3251 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3252 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3253 = or(_T_3251, _T_3252) @[lsu_bus_buffer.scala 426:110] + node _T_3254 = eq(_T_3253, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3255 = and(_T_3250, _T_3254) @[lsu_bus_buffer.scala 426:82] + node _T_3256 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3257 = and(_T_3255, _T_3256) @[lsu_bus_buffer.scala 426:136] + node _T_3258 = cat(_T_3257, _T_3249) @[Cat.scala 29:58] + node _T_3259 = cat(_T_3258, _T_3241) @[Cat.scala 29:58] + node _T_3260 = cat(_T_3259, _T_3233) @[Cat.scala 29:58] + node _T_3261 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3262 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3263 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3264 = or(_T_3262, _T_3263) @[lsu_bus_buffer.scala 426:110] + node _T_3265 = eq(_T_3264, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3266 = and(_T_3261, _T_3265) @[lsu_bus_buffer.scala 426:82] + node _T_3267 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3268 = and(_T_3266, _T_3267) @[lsu_bus_buffer.scala 426:136] + node _T_3269 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3270 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3271 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3272 = or(_T_3270, _T_3271) @[lsu_bus_buffer.scala 426:110] + node _T_3273 = eq(_T_3272, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3274 = and(_T_3269, _T_3273) @[lsu_bus_buffer.scala 426:82] + node _T_3275 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3276 = and(_T_3274, _T_3275) @[lsu_bus_buffer.scala 426:136] + node _T_3277 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3278 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3279 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3280 = or(_T_3278, _T_3279) @[lsu_bus_buffer.scala 426:110] + node _T_3281 = eq(_T_3280, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3282 = and(_T_3277, _T_3281) @[lsu_bus_buffer.scala 426:82] + node _T_3283 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3284 = and(_T_3282, _T_3283) @[lsu_bus_buffer.scala 426:136] + node _T_3285 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3286 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3287 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3288 = or(_T_3286, _T_3287) @[lsu_bus_buffer.scala 426:110] + node _T_3289 = eq(_T_3288, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3290 = and(_T_3285, _T_3289) @[lsu_bus_buffer.scala 426:82] + node _T_3291 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3292 = and(_T_3290, _T_3291) @[lsu_bus_buffer.scala 426:136] + node _T_3293 = cat(_T_3292, _T_3284) @[Cat.scala 29:58] + node _T_3294 = cat(_T_3293, _T_3276) @[Cat.scala 29:58] + node _T_3295 = cat(_T_3294, _T_3268) @[Cat.scala 29:58] + node _T_3296 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3297 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3298 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3299 = or(_T_3297, _T_3298) @[lsu_bus_buffer.scala 426:110] + node _T_3300 = eq(_T_3299, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3301 = and(_T_3296, _T_3300) @[lsu_bus_buffer.scala 426:82] + node _T_3302 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3303 = and(_T_3301, _T_3302) @[lsu_bus_buffer.scala 426:136] + node _T_3304 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3305 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3306 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3307 = or(_T_3305, _T_3306) @[lsu_bus_buffer.scala 426:110] + node _T_3308 = eq(_T_3307, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3309 = and(_T_3304, _T_3308) @[lsu_bus_buffer.scala 426:82] + node _T_3310 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3311 = and(_T_3309, _T_3310) @[lsu_bus_buffer.scala 426:136] + node _T_3312 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3313 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3314 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3315 = or(_T_3313, _T_3314) @[lsu_bus_buffer.scala 426:110] + node _T_3316 = eq(_T_3315, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3317 = and(_T_3312, _T_3316) @[lsu_bus_buffer.scala 426:82] + node _T_3318 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3319 = and(_T_3317, _T_3318) @[lsu_bus_buffer.scala 426:136] + node _T_3320 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3321 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3322 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3323 = or(_T_3321, _T_3322) @[lsu_bus_buffer.scala 426:110] + node _T_3324 = eq(_T_3323, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3325 = and(_T_3320, _T_3324) @[lsu_bus_buffer.scala 426:82] + node _T_3326 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3327 = and(_T_3325, _T_3326) @[lsu_bus_buffer.scala 426:136] + node _T_3328 = cat(_T_3327, _T_3319) @[Cat.scala 29:58] + node _T_3329 = cat(_T_3328, _T_3311) @[Cat.scala 29:58] + node _T_3330 = cat(_T_3329, _T_3303) @[Cat.scala 29:58] + buf_rspage[0] <= _T_3225 @[lsu_bus_buffer.scala 426:14] + buf_rspage[1] <= _T_3260 @[lsu_bus_buffer.scala 426:14] + buf_rspage[2] <= _T_3295 @[lsu_bus_buffer.scala 426:14] + buf_rspage[3] <= _T_3330 @[lsu_bus_buffer.scala 426:14] + node _T_3331 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 427:75] + node _T_3332 = and(ibuf_drain_vld, _T_3331) @[lsu_bus_buffer.scala 427:63] + node _T_3333 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 427:75] + node _T_3334 = and(ibuf_drain_vld, _T_3333) @[lsu_bus_buffer.scala 427:63] + node _T_3335 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 427:75] + node _T_3336 = and(ibuf_drain_vld, _T_3335) @[lsu_bus_buffer.scala 427:63] + node _T_3337 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 427:75] + node _T_3338 = and(ibuf_drain_vld, _T_3337) @[lsu_bus_buffer.scala 427:63] + node _T_3339 = cat(_T_3338, _T_3336) @[Cat.scala 29:58] + node _T_3340 = cat(_T_3339, _T_3334) @[Cat.scala 29:58] + node _T_3341 = cat(_T_3340, _T_3332) @[Cat.scala 29:58] + ibuf_drainvec_vld <= _T_3341 @[lsu_bus_buffer.scala 427:21] + node _T_3342 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 428:64] + node _T_3343 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3344 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3345 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 429:46] + node _T_3346 = and(_T_3344, _T_3345) @[lsu_bus_buffer.scala 429:35] + node _T_3347 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3348 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3349 = mux(_T_3346, _T_3347, _T_3348) @[lsu_bus_buffer.scala 429:8] + node _T_3350 = mux(_T_3342, _T_3343, _T_3349) @[lsu_bus_buffer.scala 428:46] + node _T_3351 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 428:64] + node _T_3352 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3353 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3354 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 429:46] + node _T_3355 = and(_T_3353, _T_3354) @[lsu_bus_buffer.scala 429:35] + node _T_3356 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3357 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3358 = mux(_T_3355, _T_3356, _T_3357) @[lsu_bus_buffer.scala 429:8] + node _T_3359 = mux(_T_3351, _T_3352, _T_3358) @[lsu_bus_buffer.scala 428:46] + node _T_3360 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 428:64] + node _T_3361 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3362 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3363 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 429:46] + node _T_3364 = and(_T_3362, _T_3363) @[lsu_bus_buffer.scala 429:35] + node _T_3365 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3366 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3367 = mux(_T_3364, _T_3365, _T_3366) @[lsu_bus_buffer.scala 429:8] + node _T_3368 = mux(_T_3360, _T_3361, _T_3367) @[lsu_bus_buffer.scala 428:46] + node _T_3369 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 428:64] + node _T_3370 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3371 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3372 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 429:46] + node _T_3373 = and(_T_3371, _T_3372) @[lsu_bus_buffer.scala 429:35] + node _T_3374 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3375 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3376 = mux(_T_3373, _T_3374, _T_3375) @[lsu_bus_buffer.scala 429:8] + node _T_3377 = mux(_T_3369, _T_3370, _T_3376) @[lsu_bus_buffer.scala 428:46] + buf_byteen_in[0] <= _T_3350 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[1] <= _T_3359 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[2] <= _T_3368 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[3] <= _T_3377 @[lsu_bus_buffer.scala 428:17] + node _T_3378 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 430:62] + node _T_3379 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3380 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 430:119] + node _T_3381 = and(_T_3379, _T_3380) @[lsu_bus_buffer.scala 430:108] + node _T_3382 = mux(_T_3381, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3383 = mux(_T_3378, ibuf_addr, _T_3382) @[lsu_bus_buffer.scala 430:44] + node _T_3384 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 430:62] + node _T_3385 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3386 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 430:119] + node _T_3387 = and(_T_3385, _T_3386) @[lsu_bus_buffer.scala 430:108] + node _T_3388 = mux(_T_3387, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3389 = mux(_T_3384, ibuf_addr, _T_3388) @[lsu_bus_buffer.scala 430:44] + node _T_3390 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 430:62] + node _T_3391 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3392 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 430:119] + node _T_3393 = and(_T_3391, _T_3392) @[lsu_bus_buffer.scala 430:108] + node _T_3394 = mux(_T_3393, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3395 = mux(_T_3390, ibuf_addr, _T_3394) @[lsu_bus_buffer.scala 430:44] + node _T_3396 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 430:62] + node _T_3397 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3398 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 430:119] + node _T_3399 = and(_T_3397, _T_3398) @[lsu_bus_buffer.scala 430:108] + node _T_3400 = mux(_T_3399, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3401 = mux(_T_3396, ibuf_addr, _T_3400) @[lsu_bus_buffer.scala 430:44] + buf_addr_in[0] <= _T_3383 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[1] <= _T_3389 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[2] <= _T_3395 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[3] <= _T_3401 @[lsu_bus_buffer.scala 430:15] + node _T_3402 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 431:63] + node _T_3403 = mux(_T_3402, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3404 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 431:63] + node _T_3405 = mux(_T_3404, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3406 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 431:63] + node _T_3407 = mux(_T_3406, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3408 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 431:63] + node _T_3409 = mux(_T_3408, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3410 = cat(_T_3409, _T_3407) @[Cat.scala 29:58] + node _T_3411 = cat(_T_3410, _T_3405) @[Cat.scala 29:58] + node _T_3412 = cat(_T_3411, _T_3403) @[Cat.scala 29:58] + buf_dual_in <= _T_3412 @[lsu_bus_buffer.scala 431:15] + node _T_3413 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 432:65] + node _T_3414 = mux(_T_3413, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3415 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 432:65] + node _T_3416 = mux(_T_3415, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3417 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 432:65] + node _T_3418 = mux(_T_3417, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3419 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 432:65] + node _T_3420 = mux(_T_3419, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3421 = cat(_T_3420, _T_3418) @[Cat.scala 29:58] + node _T_3422 = cat(_T_3421, _T_3416) @[Cat.scala 29:58] + node _T_3423 = cat(_T_3422, _T_3414) @[Cat.scala 29:58] + buf_samedw_in <= _T_3423 @[lsu_bus_buffer.scala 432:17] + node _T_3424 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 433:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3427 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 433:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3430 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 433:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3433 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 433:66] + node _T_3434 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3435 = mux(_T_3433, _T_3434, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3436 = cat(_T_3435, _T_3432) @[Cat.scala 29:58] + node _T_3437 = cat(_T_3436, _T_3429) @[Cat.scala 29:58] + node _T_3438 = cat(_T_3437, _T_3426) @[Cat.scala 29:58] + buf_nomerge_in <= _T_3438 @[lsu_bus_buffer.scala 433:18] + node _T_3439 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 434:65] + node _T_3440 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3441 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 434:118] + node _T_3442 = and(_T_3440, _T_3441) @[lsu_bus_buffer.scala 434:107] + node _T_3443 = mux(_T_3439, ibuf_dual, _T_3442) @[lsu_bus_buffer.scala 434:47] + node _T_3444 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 434:65] + node _T_3445 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3446 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 434:118] + node _T_3447 = and(_T_3445, _T_3446) @[lsu_bus_buffer.scala 434:107] + node _T_3448 = mux(_T_3444, ibuf_dual, _T_3447) @[lsu_bus_buffer.scala 434:47] + node _T_3449 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 434:65] + node _T_3450 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3451 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 434:118] + node _T_3452 = and(_T_3450, _T_3451) @[lsu_bus_buffer.scala 434:107] + node _T_3453 = mux(_T_3449, ibuf_dual, _T_3452) @[lsu_bus_buffer.scala 434:47] + node _T_3454 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 434:65] + node _T_3455 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3456 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 434:118] + node _T_3457 = and(_T_3455, _T_3456) @[lsu_bus_buffer.scala 434:107] + node _T_3458 = mux(_T_3454, ibuf_dual, _T_3457) @[lsu_bus_buffer.scala 434:47] + node _T_3459 = cat(_T_3458, _T_3453) @[Cat.scala 29:58] + node _T_3460 = cat(_T_3459, _T_3448) @[Cat.scala 29:58] + node _T_3461 = cat(_T_3460, _T_3443) @[Cat.scala 29:58] + buf_dualhi_in <= _T_3461 @[lsu_bus_buffer.scala 434:17] + node _T_3462 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 435:65] + node _T_3463 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3464 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 435:125] + node _T_3465 = and(_T_3463, _T_3464) @[lsu_bus_buffer.scala 435:114] + node _T_3466 = mux(_T_3465, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3467 = mux(_T_3462, ibuf_dualtag, _T_3466) @[lsu_bus_buffer.scala 435:47] + node _T_3468 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 435:65] + node _T_3469 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3470 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 435:125] + node _T_3471 = and(_T_3469, _T_3470) @[lsu_bus_buffer.scala 435:114] + node _T_3472 = mux(_T_3471, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3473 = mux(_T_3468, ibuf_dualtag, _T_3472) @[lsu_bus_buffer.scala 435:47] + node _T_3474 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 435:65] + node _T_3475 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3476 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 435:125] + node _T_3477 = and(_T_3475, _T_3476) @[lsu_bus_buffer.scala 435:114] + node _T_3478 = mux(_T_3477, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3479 = mux(_T_3474, ibuf_dualtag, _T_3478) @[lsu_bus_buffer.scala 435:47] + node _T_3480 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 435:65] + node _T_3481 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3482 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 435:125] + node _T_3483 = and(_T_3481, _T_3482) @[lsu_bus_buffer.scala 435:114] + node _T_3484 = mux(_T_3483, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3485 = mux(_T_3480, ibuf_dualtag, _T_3484) @[lsu_bus_buffer.scala 435:47] + buf_dualtag_in[0] <= _T_3467 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[1] <= _T_3473 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[2] <= _T_3479 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[3] <= _T_3485 @[lsu_bus_buffer.scala 435:18] + node _T_3486 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 436:69] + node _T_3487 = mux(_T_3486, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3488 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 436:69] + node _T_3489 = mux(_T_3488, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3490 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 436:69] + node _T_3491 = mux(_T_3490, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3492 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 436:69] + node _T_3493 = mux(_T_3492, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3494 = cat(_T_3493, _T_3491) @[Cat.scala 29:58] + node _T_3495 = cat(_T_3494, _T_3489) @[Cat.scala 29:58] + node _T_3496 = cat(_T_3495, _T_3487) @[Cat.scala 29:58] + buf_sideeffect_in <= _T_3496 @[lsu_bus_buffer.scala 436:21] + node _T_3497 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 437:65] + node _T_3498 = mux(_T_3497, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3499 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 437:65] + node _T_3500 = mux(_T_3499, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3501 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 437:65] + node _T_3502 = mux(_T_3501, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3503 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 437:65] + node _T_3504 = mux(_T_3503, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3505 = cat(_T_3504, _T_3502) @[Cat.scala 29:58] + node _T_3506 = cat(_T_3505, _T_3500) @[Cat.scala 29:58] + node _T_3507 = cat(_T_3506, _T_3498) @[Cat.scala 29:58] + buf_unsign_in <= _T_3507 @[lsu_bus_buffer.scala 437:17] + node _T_3508 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 438:60] + node _T_3509 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[lsu_bus_buffer.scala 438:42] + node _T_3511 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 438:60] + node _T_3512 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[lsu_bus_buffer.scala 438:42] + node _T_3514 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 438:60] + node _T_3515 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[lsu_bus_buffer.scala 438:42] + node _T_3517 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 438:60] + node _T_3518 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3519 = mux(_T_3517, ibuf_sz, _T_3518) @[lsu_bus_buffer.scala 438:42] + buf_sz_in[0] <= _T_3510 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[1] <= _T_3513 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[2] <= _T_3516 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[3] <= _T_3519 @[lsu_bus_buffer.scala 438:13] + node _T_3520 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 439:64] + node _T_3521 = mux(_T_3520, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3522 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 439:64] + node _T_3523 = mux(_T_3522, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3524 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 439:64] + node _T_3525 = mux(_T_3524, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3526 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 439:64] + node _T_3527 = mux(_T_3526, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3528 = cat(_T_3527, _T_3525) @[Cat.scala 29:58] + node _T_3529 = cat(_T_3528, _T_3523) @[Cat.scala 29:58] + node _T_3530 = cat(_T_3529, _T_3521) @[Cat.scala 29:58] + buf_write_in <= _T_3530 @[lsu_bus_buffer.scala 439:16] + node _T_3531 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3531 : @[Conditional.scala 40:58] + node _T_3532 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3533 = mux(_T_3532, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[0] <= _T_3533 @[lsu_bus_buffer.scala 444:25] + node _T_3534 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3535 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3536 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3537 = and(_T_3535, _T_3536) @[lsu_bus_buffer.scala 445:95] + node _T_3538 = eq(UInt<1>("h00"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3539 = and(_T_3537, _T_3538) @[lsu_bus_buffer.scala 445:112] + node _T_3540 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3541 = eq(UInt<1>("h00"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3542 = and(_T_3540, _T_3541) @[lsu_bus_buffer.scala 445:161] + node _T_3543 = or(_T_3539, _T_3542) @[lsu_bus_buffer.scala 445:132] + node _T_3544 = and(_T_3534, _T_3543) @[lsu_bus_buffer.scala 445:63] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[lsu_bus_buffer.scala 445:201] + node _T_3547 = or(_T_3544, _T_3546) @[lsu_bus_buffer.scala 445:183] + buf_state_en[0] <= _T_3547 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 446:22] + buf_data_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 447:24] + node _T_3548 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3549 = and(ibuf_drain_vld, _T_3548) @[lsu_bus_buffer.scala 448:47] + node _T_3550 = bits(_T_3549, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3551 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3552 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3553 = mux(_T_3550, _T_3551, _T_3552) @[lsu_bus_buffer.scala 448:30] + buf_data_in[0] <= _T_3553 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3554 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3554 : @[Conditional.scala 39:67] + node _T_3555 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3556 = mux(_T_3555, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[0] <= _T_3556 @[lsu_bus_buffer.scala 453:25] + node _T_3557 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[0] <= _T_3557 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3558 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3558 : @[Conditional.scala 39:67] + node _T_3559 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3560 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3561 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3562 = and(_T_3560, _T_3561) @[lsu_bus_buffer.scala 459:104] + node _T_3563 = mux(_T_3562, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3564 = mux(_T_3559, UInt<3>("h00"), _T_3563) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[0] <= _T_3564 @[lsu_bus_buffer.scala 459:25] + node _T_3565 = eq(obuf_tag0, UInt<3>("h00")) @[lsu_bus_buffer.scala 460:48] + node _T_3566 = eq(obuf_tag1, UInt<3>("h00")) @[lsu_bus_buffer.scala 460:104] + node _T_3567 = and(obuf_merge, _T_3566) @[lsu_bus_buffer.scala 460:91] + node _T_3568 = or(_T_3565, _T_3567) @[lsu_bus_buffer.scala 460:77] + node _T_3569 = and(_T_3568, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3570 = and(_T_3569, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[0] <= _T_3570 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[lsu_bus_buffer.scala 461:29] + node _T_3571 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3572 = or(_T_3571, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[0] <= _T_3572 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3573 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 464:56] + node _T_3574 = eq(_T_3573, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3575 = and(buf_state_en[0], _T_3574) @[lsu_bus_buffer.scala 464:44] + node _T_3576 = and(_T_3575, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3577 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3578 = and(_T_3576, _T_3577) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[0] <= _T_3578 @[lsu_bus_buffer.scala 464:25] + node _T_3579 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[0] <= _T_3579 @[lsu_bus_buffer.scala 465:28] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3581 = and(_T_3580, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3582 = and(_T_3581, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[0] <= _T_3582 @[lsu_bus_buffer.scala 466:24] + node _T_3583 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3584 = and(_T_3583, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3585 = and(_T_3584, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[0] <= _T_3585 @[lsu_bus_buffer.scala 467:25] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3587 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3588 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3589 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3590 = mux(_T_3587, _T_3588, _T_3589) @[lsu_bus_buffer.scala 468:73] + node _T_3591 = mux(buf_error_en[0], _T_3586, _T_3590) @[lsu_bus_buffer.scala 468:30] + buf_data_in[0] <= _T_3591 @[lsu_bus_buffer.scala 468:24] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3592 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3592 : @[Conditional.scala 39:67] + node _T_3593 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 472:69] + node _T_3594 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3595 = and(_T_3593, _T_3594) @[lsu_bus_buffer.scala 472:73] + node _T_3596 = or(io.dec_tlu_force_halt, _T_3595) @[lsu_bus_buffer.scala 472:57] + node _T_3597 = bits(_T_3596, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3598 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3599 = and(buf_dual[0], _T_3598) @[lsu_bus_buffer.scala 473:28] + node _T_3600 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 473:57] + node _T_3601 = eq(_T_3600, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3602 = and(_T_3599, _T_3601) @[lsu_bus_buffer.scala 473:45] + node _T_3603 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3604 = and(_T_3602, _T_3603) @[lsu_bus_buffer.scala 473:61] + node _T_3605 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 474:27] + node _T_3606 = or(_T_3605, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3607 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3608 = and(buf_dual[0], _T_3607) @[lsu_bus_buffer.scala 474:68] + node _T_3609 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 474:97] + node _T_3610 = eq(_T_3609, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3611 = and(_T_3608, _T_3610) @[lsu_bus_buffer.scala 474:85] + node _T_3612 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3613 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3614 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3615 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3616 = eq(buf_dualtag[0], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3617 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_3618 = eq(buf_dualtag[0], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_3619 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_3620 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3621 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3622 = mux(_T_3616, _T_3617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3623 = mux(_T_3618, _T_3619, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3624 = or(_T_3620, _T_3621) @[Mux.scala 27:72] + node _T_3625 = or(_T_3624, _T_3622) @[Mux.scala 27:72] + node _T_3626 = or(_T_3625, _T_3623) @[Mux.scala 27:72] + wire _T_3627 : UInt<1> @[Mux.scala 27:72] + _T_3627 <= _T_3626 @[Mux.scala 27:72] + node _T_3628 = and(_T_3611, _T_3627) @[lsu_bus_buffer.scala 474:101] + node _T_3629 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_3630 = and(_T_3628, _T_3629) @[lsu_bus_buffer.scala 474:138] + node _T_3631 = and(_T_3630, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_3632 = or(_T_3606, _T_3631) @[lsu_bus_buffer.scala 474:53] + node _T_3633 = mux(_T_3632, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_3634 = mux(_T_3604, UInt<3>("h04"), _T_3633) @[lsu_bus_buffer.scala 473:14] + node _T_3635 = mux(_T_3597, UInt<3>("h00"), _T_3634) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[0] <= _T_3635 @[lsu_bus_buffer.scala 472:27] + node _T_3636 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 475:73] + node _T_3637 = and(bus_rsp_write, _T_3636) @[lsu_bus_buffer.scala 475:52] + node _T_3638 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 476:46] + node _T_3639 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 477:23] + node _T_3640 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 477:47] + node _T_3641 = and(_T_3639, _T_3640) @[lsu_bus_buffer.scala 477:27] + node _T_3642 = or(_T_3638, _T_3641) @[lsu_bus_buffer.scala 476:77] + node _T_3643 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 478:26] + node _T_3644 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 478:54] + node _T_3645 = not(_T_3644) @[lsu_bus_buffer.scala 478:44] + node _T_3646 = and(_T_3643, _T_3645) @[lsu_bus_buffer.scala 478:42] + node _T_3647 = and(_T_3646, buf_samedw[0]) @[lsu_bus_buffer.scala 478:58] + node _T_3648 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 478:94] + node _T_3649 = and(_T_3647, _T_3648) @[lsu_bus_buffer.scala 478:74] + node _T_3650 = or(_T_3642, _T_3649) @[lsu_bus_buffer.scala 477:71] + node _T_3651 = and(bus_rsp_read, _T_3650) @[lsu_bus_buffer.scala 476:25] + node _T_3652 = or(_T_3637, _T_3651) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[0] <= _T_3652 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[lsu_bus_buffer.scala 479:29] + node _T_3653 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_3654 = or(_T_3653, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[0] <= _T_3654 @[lsu_bus_buffer.scala 480:25] + node _T_3655 = and(buf_state_bus_en[0], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_3656 = and(_T_3655, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[0] <= _T_3656 @[lsu_bus_buffer.scala 481:24] + node _T_3657 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_3658 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 482:111] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[lsu_bus_buffer.scala 482:91] + node _T_3660 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 483:42] + node _T_3661 = and(bus_rsp_read_error, _T_3660) @[lsu_bus_buffer.scala 483:31] + node _T_3662 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 483:66] + node _T_3663 = and(_T_3661, _T_3662) @[lsu_bus_buffer.scala 483:46] + node _T_3664 = or(_T_3659, _T_3663) @[lsu_bus_buffer.scala 482:143] + node _T_3665 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 484:54] + node _T_3666 = and(bus_rsp_write_error, _T_3665) @[lsu_bus_buffer.scala 484:33] + node _T_3667 = or(_T_3664, _T_3666) @[lsu_bus_buffer.scala 483:88] + node _T_3668 = and(_T_3657, _T_3667) @[lsu_bus_buffer.scala 482:68] + buf_error_en[0] <= _T_3668 @[lsu_bus_buffer.scala 482:25] + node _T_3669 = eq(buf_error_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_3670 = and(buf_state_en[0], _T_3669) @[lsu_bus_buffer.scala 485:48] + node _T_3671 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_3672 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_3673 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_3674 = mux(_T_3671, _T_3672, _T_3673) @[lsu_bus_buffer.scala 485:72] + node _T_3675 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_3676 = mux(_T_3670, _T_3674, _T_3675) @[lsu_bus_buffer.scala 485:30] + buf_data_in[0] <= _T_3676 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3677 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3677 : @[Conditional.scala 39:67] + node _T_3678 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_3679 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 490:86] + node _T_3680 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 490:101] + node _T_3681 = bits(_T_3680, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_3682 = or(_T_3679, _T_3681) @[lsu_bus_buffer.scala 490:90] + node _T_3683 = or(_T_3682, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_3684 = mux(_T_3683, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_3685 = mux(_T_3678, UInt<3>("h00"), _T_3684) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[0] <= _T_3685 @[lsu_bus_buffer.scala 490:25] + node _T_3686 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 491:66] + node _T_3687 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 492:21] + node _T_3688 = bits(_T_3687, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_3689 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[lsu_bus_buffer.scala 492:58] + node _T_3690 = and(_T_3688, _T_3689) @[lsu_bus_buffer.scala 492:38] + node _T_3691 = or(_T_3686, _T_3690) @[lsu_bus_buffer.scala 491:95] + node _T_3692 = and(bus_rsp_read, _T_3691) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[0] <= _T_3692 @[lsu_bus_buffer.scala 491:29] + node _T_3693 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_3694 = or(_T_3693, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[0] <= _T_3694 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3695 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3695 : @[Conditional.scala 39:67] + node _T_3696 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_3697 = mux(_T_3696, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[0] <= _T_3697 @[lsu_bus_buffer.scala 498:25] + node _T_3698 = eq(RspPtr, UInt<2>("h00")) @[lsu_bus_buffer.scala 499:37] + node _T_3699 = eq(buf_dualtag[0], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_3700 = and(buf_dual[0], _T_3699) @[lsu_bus_buffer.scala 499:80] + node _T_3701 = or(_T_3698, _T_3700) @[lsu_bus_buffer.scala 499:65] + node _T_3702 = or(_T_3701, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[0] <= _T_3702 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3703 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3703 : @[Conditional.scala 39:67] + buf_nxtstate[0] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_3704 = bits(buf_state_en[0], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3704 : @[Reg.scala 28:19] + _T_3705 <= buf_nxtstate[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[0] <= _T_3705 @[lsu_bus_buffer.scala 512:18] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_3706 <= buf_age_in_0 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[0] <= _T_3706 @[lsu_bus_buffer.scala 513:17] + reg _T_3707 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_3707 <= buf_rspage_in[0] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[0] <= _T_3707 @[lsu_bus_buffer.scala 514:20] + node _T_3708 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_3709 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3708 : @[Reg.scala 28:19] + _T_3709 <= buf_dualtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[0] <= _T_3709 @[lsu_bus_buffer.scala 515:20] + node _T_3710 = bits(buf_dual_in, 0, 0) @[lsu_bus_buffer.scala 516:74] + node _T_3711 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_3712 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3711 : @[Reg.scala 28:19] + _T_3712 <= _T_3710 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[0] <= _T_3712 @[lsu_bus_buffer.scala 516:17] + node _T_3713 = bits(buf_samedw_in, 0, 0) @[lsu_bus_buffer.scala 517:78] + node _T_3714 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_3715 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3714 : @[Reg.scala 28:19] + _T_3715 <= _T_3713 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[0] <= _T_3715 @[lsu_bus_buffer.scala 517:19] + node _T_3716 = bits(buf_nomerge_in, 0, 0) @[lsu_bus_buffer.scala 518:80] + node _T_3717 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_3718 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3717 : @[Reg.scala 28:19] + _T_3718 <= _T_3716 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[0] <= _T_3718 @[lsu_bus_buffer.scala 518:20] + node _T_3719 = bits(buf_dualhi_in, 0, 0) @[lsu_bus_buffer.scala 519:78] + node _T_3720 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_3721 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3720 : @[Reg.scala 28:19] + _T_3721 <= _T_3719 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[0] <= _T_3721 @[lsu_bus_buffer.scala 519:19] + node _T_3722 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3722 : @[Conditional.scala 40:58] + node _T_3723 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3724 = mux(_T_3723, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[1] <= _T_3724 @[lsu_bus_buffer.scala 444:25] + node _T_3725 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3726 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3727 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3728 = and(_T_3726, _T_3727) @[lsu_bus_buffer.scala 445:95] + node _T_3729 = eq(UInt<1>("h01"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3730 = and(_T_3728, _T_3729) @[lsu_bus_buffer.scala 445:112] + node _T_3731 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3732 = eq(UInt<1>("h01"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3733 = and(_T_3731, _T_3732) @[lsu_bus_buffer.scala 445:161] + node _T_3734 = or(_T_3730, _T_3733) @[lsu_bus_buffer.scala 445:132] + node _T_3735 = and(_T_3725, _T_3734) @[lsu_bus_buffer.scala 445:63] + node _T_3736 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3737 = and(ibuf_drain_vld, _T_3736) @[lsu_bus_buffer.scala 445:201] + node _T_3738 = or(_T_3735, _T_3737) @[lsu_bus_buffer.scala 445:183] + buf_state_en[1] <= _T_3738 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 446:22] + buf_data_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 447:24] + node _T_3739 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3740 = and(ibuf_drain_vld, _T_3739) @[lsu_bus_buffer.scala 448:47] + node _T_3741 = bits(_T_3740, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3742 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3743 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3744 = mux(_T_3741, _T_3742, _T_3743) @[lsu_bus_buffer.scala 448:30] + buf_data_in[1] <= _T_3744 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3745 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3745 : @[Conditional.scala 39:67] + node _T_3746 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3747 = mux(_T_3746, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[1] <= _T_3747 @[lsu_bus_buffer.scala 453:25] + node _T_3748 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[1] <= _T_3748 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3749 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3749 : @[Conditional.scala 39:67] + node _T_3750 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3751 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3752 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3753 = and(_T_3751, _T_3752) @[lsu_bus_buffer.scala 459:104] + node _T_3754 = mux(_T_3753, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3755 = mux(_T_3750, UInt<3>("h00"), _T_3754) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[1] <= _T_3755 @[lsu_bus_buffer.scala 459:25] + node _T_3756 = eq(obuf_tag0, UInt<3>("h01")) @[lsu_bus_buffer.scala 460:48] + node _T_3757 = eq(obuf_tag1, UInt<3>("h01")) @[lsu_bus_buffer.scala 460:104] + node _T_3758 = and(obuf_merge, _T_3757) @[lsu_bus_buffer.scala 460:91] + node _T_3759 = or(_T_3756, _T_3758) @[lsu_bus_buffer.scala 460:77] + node _T_3760 = and(_T_3759, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3761 = and(_T_3760, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[1] <= _T_3761 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[lsu_bus_buffer.scala 461:29] + node _T_3762 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3763 = or(_T_3762, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[1] <= _T_3763 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3764 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 464:56] + node _T_3765 = eq(_T_3764, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3766 = and(buf_state_en[1], _T_3765) @[lsu_bus_buffer.scala 464:44] + node _T_3767 = and(_T_3766, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3768 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3769 = and(_T_3767, _T_3768) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[1] <= _T_3769 @[lsu_bus_buffer.scala 464:25] + node _T_3770 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[1] <= _T_3770 @[lsu_bus_buffer.scala 465:28] + node _T_3771 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3772 = and(_T_3771, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3773 = and(_T_3772, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[1] <= _T_3773 @[lsu_bus_buffer.scala 466:24] + node _T_3774 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3775 = and(_T_3774, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3776 = and(_T_3775, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[1] <= _T_3776 @[lsu_bus_buffer.scala 467:25] + node _T_3777 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3778 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3779 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3780 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3781 = mux(_T_3778, _T_3779, _T_3780) @[lsu_bus_buffer.scala 468:73] + node _T_3782 = mux(buf_error_en[1], _T_3777, _T_3781) @[lsu_bus_buffer.scala 468:30] + buf_data_in[1] <= _T_3782 @[lsu_bus_buffer.scala 468:24] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3783 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3783 : @[Conditional.scala 39:67] + node _T_3784 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 472:69] + node _T_3785 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3786 = and(_T_3784, _T_3785) @[lsu_bus_buffer.scala 472:73] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[lsu_bus_buffer.scala 472:57] + node _T_3788 = bits(_T_3787, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[lsu_bus_buffer.scala 473:28] + node _T_3791 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 473:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3793 = and(_T_3790, _T_3792) @[lsu_bus_buffer.scala 473:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3795 = and(_T_3793, _T_3794) @[lsu_bus_buffer.scala 473:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 474:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[lsu_bus_buffer.scala 474:68] + node _T_3800 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 474:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3802 = and(_T_3799, _T_3801) @[lsu_bus_buffer.scala 474:85] + node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3804 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3806 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3808 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_3810 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3814 = mux(_T_3809, _T_3810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3815 = or(_T_3811, _T_3812) @[Mux.scala 27:72] + node _T_3816 = or(_T_3815, _T_3813) @[Mux.scala 27:72] + node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] + wire _T_3818 : UInt<1> @[Mux.scala 27:72] + _T_3818 <= _T_3817 @[Mux.scala 27:72] + node _T_3819 = and(_T_3802, _T_3818) @[lsu_bus_buffer.scala 474:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_3821 = and(_T_3819, _T_3820) @[lsu_bus_buffer.scala 474:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_3823 = or(_T_3797, _T_3822) @[lsu_bus_buffer.scala 474:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[lsu_bus_buffer.scala 473:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[1] <= _T_3826 @[lsu_bus_buffer.scala 472:27] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 475:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[lsu_bus_buffer.scala 475:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 476:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 477:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 477:47] + node _T_3832 = and(_T_3830, _T_3831) @[lsu_bus_buffer.scala 477:27] + node _T_3833 = or(_T_3829, _T_3832) @[lsu_bus_buffer.scala 476:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 478:26] + node _T_3835 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 478:54] + node _T_3836 = not(_T_3835) @[lsu_bus_buffer.scala 478:44] + node _T_3837 = and(_T_3834, _T_3836) @[lsu_bus_buffer.scala 478:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[lsu_bus_buffer.scala 478:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 478:94] + node _T_3840 = and(_T_3838, _T_3839) @[lsu_bus_buffer.scala 478:74] + node _T_3841 = or(_T_3833, _T_3840) @[lsu_bus_buffer.scala 477:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[lsu_bus_buffer.scala 476:25] + node _T_3843 = or(_T_3828, _T_3842) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[1] <= _T_3843 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[lsu_bus_buffer.scala 479:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[1] <= _T_3845 @[lsu_bus_buffer.scala 480:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[1] <= _T_3847 @[lsu_bus_buffer.scala 481:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 482:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[lsu_bus_buffer.scala 482:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 483:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[lsu_bus_buffer.scala 483:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 483:66] + node _T_3854 = and(_T_3852, _T_3853) @[lsu_bus_buffer.scala 483:46] + node _T_3855 = or(_T_3850, _T_3854) @[lsu_bus_buffer.scala 482:143] + node _T_3856 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 484:54] + node _T_3857 = and(bus_rsp_write_error, _T_3856) @[lsu_bus_buffer.scala 484:33] + node _T_3858 = or(_T_3855, _T_3857) @[lsu_bus_buffer.scala 483:88] + node _T_3859 = and(_T_3848, _T_3858) @[lsu_bus_buffer.scala 482:68] + buf_error_en[1] <= _T_3859 @[lsu_bus_buffer.scala 482:25] + node _T_3860 = eq(buf_error_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_3861 = and(buf_state_en[1], _T_3860) @[lsu_bus_buffer.scala 485:48] + node _T_3862 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_3863 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_3864 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_3865 = mux(_T_3862, _T_3863, _T_3864) @[lsu_bus_buffer.scala 485:72] + node _T_3866 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_3867 = mux(_T_3861, _T_3865, _T_3866) @[lsu_bus_buffer.scala 485:30] + buf_data_in[1] <= _T_3867 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3868 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3868 : @[Conditional.scala 39:67] + node _T_3869 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_3870 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 490:86] + node _T_3871 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 490:101] + node _T_3872 = bits(_T_3871, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_3873 = or(_T_3870, _T_3872) @[lsu_bus_buffer.scala 490:90] + node _T_3874 = or(_T_3873, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_3875 = mux(_T_3874, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_3876 = mux(_T_3869, UInt<3>("h00"), _T_3875) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[1] <= _T_3876 @[lsu_bus_buffer.scala 490:25] + node _T_3877 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 491:66] + node _T_3878 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 492:21] + node _T_3879 = bits(_T_3878, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_3880 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[lsu_bus_buffer.scala 492:58] + node _T_3881 = and(_T_3879, _T_3880) @[lsu_bus_buffer.scala 492:38] + node _T_3882 = or(_T_3877, _T_3881) @[lsu_bus_buffer.scala 491:95] + node _T_3883 = and(bus_rsp_read, _T_3882) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[1] <= _T_3883 @[lsu_bus_buffer.scala 491:29] + node _T_3884 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_3885 = or(_T_3884, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[1] <= _T_3885 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3886 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3886 : @[Conditional.scala 39:67] + node _T_3887 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_3888 = mux(_T_3887, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[1] <= _T_3888 @[lsu_bus_buffer.scala 498:25] + node _T_3889 = eq(RspPtr, UInt<2>("h01")) @[lsu_bus_buffer.scala 499:37] + node _T_3890 = eq(buf_dualtag[1], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_3891 = and(buf_dual[1], _T_3890) @[lsu_bus_buffer.scala 499:80] + node _T_3892 = or(_T_3889, _T_3891) @[lsu_bus_buffer.scala 499:65] + node _T_3893 = or(_T_3892, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[1] <= _T_3893 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3894 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3894 : @[Conditional.scala 39:67] + buf_nxtstate[1] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_3895 = bits(buf_state_en[1], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_3896 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3895 : @[Reg.scala 28:19] + _T_3896 <= buf_nxtstate[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[1] <= _T_3896 @[lsu_bus_buffer.scala 512:18] + reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_3897 <= buf_age_in_1 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[1] <= _T_3897 @[lsu_bus_buffer.scala 513:17] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_3898 <= buf_rspage_in[1] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[1] <= _T_3898 @[lsu_bus_buffer.scala 514:20] + node _T_3899 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_3900 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3899 : @[Reg.scala 28:19] + _T_3900 <= buf_dualtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[1] <= _T_3900 @[lsu_bus_buffer.scala 515:20] + node _T_3901 = bits(buf_dual_in, 1, 1) @[lsu_bus_buffer.scala 516:74] + node _T_3902 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_3903 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3902 : @[Reg.scala 28:19] + _T_3903 <= _T_3901 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[1] <= _T_3903 @[lsu_bus_buffer.scala 516:17] + node _T_3904 = bits(buf_samedw_in, 1, 1) @[lsu_bus_buffer.scala 517:78] + node _T_3905 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_3906 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3905 : @[Reg.scala 28:19] + _T_3906 <= _T_3904 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[1] <= _T_3906 @[lsu_bus_buffer.scala 517:19] + node _T_3907 = bits(buf_nomerge_in, 1, 1) @[lsu_bus_buffer.scala 518:80] + node _T_3908 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_3909 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3908 : @[Reg.scala 28:19] + _T_3909 <= _T_3907 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[1] <= _T_3909 @[lsu_bus_buffer.scala 518:20] + node _T_3910 = bits(buf_dualhi_in, 1, 1) @[lsu_bus_buffer.scala 519:78] + node _T_3911 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_3912 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3911 : @[Reg.scala 28:19] + _T_3912 <= _T_3910 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[1] <= _T_3912 @[lsu_bus_buffer.scala 519:19] + node _T_3913 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3913 : @[Conditional.scala 40:58] + node _T_3914 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3915 = mux(_T_3914, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[2] <= _T_3915 @[lsu_bus_buffer.scala 444:25] + node _T_3916 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3917 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3918 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3919 = and(_T_3917, _T_3918) @[lsu_bus_buffer.scala 445:95] + node _T_3920 = eq(UInt<2>("h02"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3921 = and(_T_3919, _T_3920) @[lsu_bus_buffer.scala 445:112] + node _T_3922 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3923 = eq(UInt<2>("h02"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3924 = and(_T_3922, _T_3923) @[lsu_bus_buffer.scala 445:161] + node _T_3925 = or(_T_3921, _T_3924) @[lsu_bus_buffer.scala 445:132] + node _T_3926 = and(_T_3916, _T_3925) @[lsu_bus_buffer.scala 445:63] + node _T_3927 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3928 = and(ibuf_drain_vld, _T_3927) @[lsu_bus_buffer.scala 445:201] + node _T_3929 = or(_T_3926, _T_3928) @[lsu_bus_buffer.scala 445:183] + buf_state_en[2] <= _T_3929 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 446:22] + buf_data_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 447:24] + node _T_3930 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3931 = and(ibuf_drain_vld, _T_3930) @[lsu_bus_buffer.scala 448:47] + node _T_3932 = bits(_T_3931, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3933 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3934 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3935 = mux(_T_3932, _T_3933, _T_3934) @[lsu_bus_buffer.scala 448:30] + buf_data_in[2] <= _T_3935 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3936 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3936 : @[Conditional.scala 39:67] + node _T_3937 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3938 = mux(_T_3937, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[2] <= _T_3938 @[lsu_bus_buffer.scala 453:25] + node _T_3939 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[2] <= _T_3939 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3940 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3940 : @[Conditional.scala 39:67] + node _T_3941 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3942 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3943 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3944 = and(_T_3942, _T_3943) @[lsu_bus_buffer.scala 459:104] + node _T_3945 = mux(_T_3944, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3946 = mux(_T_3941, UInt<3>("h00"), _T_3945) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[2] <= _T_3946 @[lsu_bus_buffer.scala 459:25] + node _T_3947 = eq(obuf_tag0, UInt<3>("h02")) @[lsu_bus_buffer.scala 460:48] + node _T_3948 = eq(obuf_tag1, UInt<3>("h02")) @[lsu_bus_buffer.scala 460:104] + node _T_3949 = and(obuf_merge, _T_3948) @[lsu_bus_buffer.scala 460:91] + node _T_3950 = or(_T_3947, _T_3949) @[lsu_bus_buffer.scala 460:77] + node _T_3951 = and(_T_3950, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3952 = and(_T_3951, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[2] <= _T_3952 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[lsu_bus_buffer.scala 461:29] + node _T_3953 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3954 = or(_T_3953, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[2] <= _T_3954 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3955 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 464:56] + node _T_3956 = eq(_T_3955, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3957 = and(buf_state_en[2], _T_3956) @[lsu_bus_buffer.scala 464:44] + node _T_3958 = and(_T_3957, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3959 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3960 = and(_T_3958, _T_3959) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[2] <= _T_3960 @[lsu_bus_buffer.scala 464:25] + node _T_3961 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[2] <= _T_3961 @[lsu_bus_buffer.scala 465:28] + node _T_3962 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3963 = and(_T_3962, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3964 = and(_T_3963, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[2] <= _T_3964 @[lsu_bus_buffer.scala 466:24] + node _T_3965 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3966 = and(_T_3965, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3967 = and(_T_3966, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[2] <= _T_3967 @[lsu_bus_buffer.scala 467:25] + node _T_3968 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3969 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3970 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3971 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3972 = mux(_T_3969, _T_3970, _T_3971) @[lsu_bus_buffer.scala 468:73] + node _T_3973 = mux(buf_error_en[2], _T_3968, _T_3972) @[lsu_bus_buffer.scala 468:30] + buf_data_in[2] <= _T_3973 @[lsu_bus_buffer.scala 468:24] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3974 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3974 : @[Conditional.scala 39:67] + node _T_3975 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 472:69] + node _T_3976 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3977 = and(_T_3975, _T_3976) @[lsu_bus_buffer.scala 472:73] + node _T_3978 = or(io.dec_tlu_force_halt, _T_3977) @[lsu_bus_buffer.scala 472:57] + node _T_3979 = bits(_T_3978, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3980 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3981 = and(buf_dual[2], _T_3980) @[lsu_bus_buffer.scala 473:28] + node _T_3982 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 473:57] + node _T_3983 = eq(_T_3982, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3984 = and(_T_3981, _T_3983) @[lsu_bus_buffer.scala 473:45] + node _T_3985 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3986 = and(_T_3984, _T_3985) @[lsu_bus_buffer.scala 473:61] + node _T_3987 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 474:27] + node _T_3988 = or(_T_3987, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3989 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3990 = and(buf_dual[2], _T_3989) @[lsu_bus_buffer.scala 474:68] + node _T_3991 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 474:97] + node _T_3992 = eq(_T_3991, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3993 = and(_T_3990, _T_3992) @[lsu_bus_buffer.scala 474:85] + node _T_3994 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3995 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3996 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3997 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3998 = eq(buf_dualtag[2], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3999 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4000 = eq(buf_dualtag[2], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4001 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4002 = mux(_T_3994, _T_3995, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4003 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4004 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4005 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4006 = or(_T_4002, _T_4003) @[Mux.scala 27:72] + node _T_4007 = or(_T_4006, _T_4004) @[Mux.scala 27:72] + node _T_4008 = or(_T_4007, _T_4005) @[Mux.scala 27:72] + wire _T_4009 : UInt<1> @[Mux.scala 27:72] + _T_4009 <= _T_4008 @[Mux.scala 27:72] + node _T_4010 = and(_T_3993, _T_4009) @[lsu_bus_buffer.scala 474:101] + node _T_4011 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_4012 = and(_T_4010, _T_4011) @[lsu_bus_buffer.scala 474:138] + node _T_4013 = and(_T_4012, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_4014 = or(_T_3988, _T_4013) @[lsu_bus_buffer.scala 474:53] + node _T_4015 = mux(_T_4014, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_4016 = mux(_T_3986, UInt<3>("h04"), _T_4015) @[lsu_bus_buffer.scala 473:14] + node _T_4017 = mux(_T_3979, UInt<3>("h00"), _T_4016) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[2] <= _T_4017 @[lsu_bus_buffer.scala 472:27] + node _T_4018 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 475:73] + node _T_4019 = and(bus_rsp_write, _T_4018) @[lsu_bus_buffer.scala 475:52] + node _T_4020 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 476:46] + node _T_4021 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 477:23] + node _T_4022 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 477:47] + node _T_4023 = and(_T_4021, _T_4022) @[lsu_bus_buffer.scala 477:27] + node _T_4024 = or(_T_4020, _T_4023) @[lsu_bus_buffer.scala 476:77] + node _T_4025 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 478:26] + node _T_4026 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 478:54] + node _T_4027 = not(_T_4026) @[lsu_bus_buffer.scala 478:44] + node _T_4028 = and(_T_4025, _T_4027) @[lsu_bus_buffer.scala 478:42] + node _T_4029 = and(_T_4028, buf_samedw[2]) @[lsu_bus_buffer.scala 478:58] + node _T_4030 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 478:94] + node _T_4031 = and(_T_4029, _T_4030) @[lsu_bus_buffer.scala 478:74] + node _T_4032 = or(_T_4024, _T_4031) @[lsu_bus_buffer.scala 477:71] + node _T_4033 = and(bus_rsp_read, _T_4032) @[lsu_bus_buffer.scala 476:25] + node _T_4034 = or(_T_4019, _T_4033) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[2] <= _T_4034 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[lsu_bus_buffer.scala 479:29] + node _T_4035 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_4036 = or(_T_4035, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[2] <= _T_4036 @[lsu_bus_buffer.scala 480:25] + node _T_4037 = and(buf_state_bus_en[2], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_4038 = and(_T_4037, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[2] <= _T_4038 @[lsu_bus_buffer.scala 481:24] + node _T_4039 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_4040 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 482:111] + node _T_4041 = and(bus_rsp_read_error, _T_4040) @[lsu_bus_buffer.scala 482:91] + node _T_4042 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 483:42] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[lsu_bus_buffer.scala 483:31] + node _T_4044 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 483:66] + node _T_4045 = and(_T_4043, _T_4044) @[lsu_bus_buffer.scala 483:46] + node _T_4046 = or(_T_4041, _T_4045) @[lsu_bus_buffer.scala 482:143] + node _T_4047 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 484:54] + node _T_4048 = and(bus_rsp_write_error, _T_4047) @[lsu_bus_buffer.scala 484:33] + node _T_4049 = or(_T_4046, _T_4048) @[lsu_bus_buffer.scala 483:88] + node _T_4050 = and(_T_4039, _T_4049) @[lsu_bus_buffer.scala 482:68] + buf_error_en[2] <= _T_4050 @[lsu_bus_buffer.scala 482:25] + node _T_4051 = eq(buf_error_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_4052 = and(buf_state_en[2], _T_4051) @[lsu_bus_buffer.scala 485:48] + node _T_4053 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_4054 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_4055 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_4056 = mux(_T_4053, _T_4054, _T_4055) @[lsu_bus_buffer.scala 485:72] + node _T_4057 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_4058 = mux(_T_4052, _T_4056, _T_4057) @[lsu_bus_buffer.scala 485:30] + buf_data_in[2] <= _T_4058 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4059 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4059 : @[Conditional.scala 39:67] + node _T_4060 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_4061 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 490:86] + node _T_4062 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 490:101] + node _T_4063 = bits(_T_4062, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_4064 = or(_T_4061, _T_4063) @[lsu_bus_buffer.scala 490:90] + node _T_4065 = or(_T_4064, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_4066 = mux(_T_4065, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_4067 = mux(_T_4060, UInt<3>("h00"), _T_4066) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[2] <= _T_4067 @[lsu_bus_buffer.scala 490:25] + node _T_4068 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 491:66] + node _T_4069 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 492:21] + node _T_4070 = bits(_T_4069, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_4071 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[lsu_bus_buffer.scala 492:58] + node _T_4072 = and(_T_4070, _T_4071) @[lsu_bus_buffer.scala 492:38] + node _T_4073 = or(_T_4068, _T_4072) @[lsu_bus_buffer.scala 491:95] + node _T_4074 = and(bus_rsp_read, _T_4073) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[2] <= _T_4074 @[lsu_bus_buffer.scala 491:29] + node _T_4075 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_4076 = or(_T_4075, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[2] <= _T_4076 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4077 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4077 : @[Conditional.scala 39:67] + node _T_4078 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_4079 = mux(_T_4078, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[2] <= _T_4079 @[lsu_bus_buffer.scala 498:25] + node _T_4080 = eq(RspPtr, UInt<2>("h02")) @[lsu_bus_buffer.scala 499:37] + node _T_4081 = eq(buf_dualtag[2], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_4082 = and(buf_dual[2], _T_4081) @[lsu_bus_buffer.scala 499:80] + node _T_4083 = or(_T_4080, _T_4082) @[lsu_bus_buffer.scala 499:65] + node _T_4084 = or(_T_4083, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[2] <= _T_4084 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4085 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4085 : @[Conditional.scala 39:67] + buf_nxtstate[2] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_4086 = bits(buf_state_en[2], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_4087 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4086 : @[Reg.scala 28:19] + _T_4087 <= buf_nxtstate[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[2] <= _T_4087 @[lsu_bus_buffer.scala 512:18] + reg _T_4088 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_4088 <= buf_age_in_2 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[2] <= _T_4088 @[lsu_bus_buffer.scala 513:17] + reg _T_4089 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_4089 <= buf_rspage_in[2] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[2] <= _T_4089 @[lsu_bus_buffer.scala 514:20] + node _T_4090 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4090 : @[Reg.scala 28:19] + _T_4091 <= buf_dualtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[2] <= _T_4091 @[lsu_bus_buffer.scala 515:20] + node _T_4092 = bits(buf_dual_in, 2, 2) @[lsu_bus_buffer.scala 516:74] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_4094 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4093 : @[Reg.scala 28:19] + _T_4094 <= _T_4092 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[2] <= _T_4094 @[lsu_bus_buffer.scala 516:17] + node _T_4095 = bits(buf_samedw_in, 2, 2) @[lsu_bus_buffer.scala 517:78] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4096 : @[Reg.scala 28:19] + _T_4097 <= _T_4095 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[2] <= _T_4097 @[lsu_bus_buffer.scala 517:19] + node _T_4098 = bits(buf_nomerge_in, 2, 2) @[lsu_bus_buffer.scala 518:80] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4099 : @[Reg.scala 28:19] + _T_4100 <= _T_4098 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[2] <= _T_4100 @[lsu_bus_buffer.scala 518:20] + node _T_4101 = bits(buf_dualhi_in, 2, 2) @[lsu_bus_buffer.scala 519:78] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4102 : @[Reg.scala 28:19] + _T_4103 <= _T_4101 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[2] <= _T_4103 @[lsu_bus_buffer.scala 519:19] + node _T_4104 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4104 : @[Conditional.scala 40:58] + node _T_4105 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_4106 = mux(_T_4105, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[3] <= _T_4106 @[lsu_bus_buffer.scala 444:25] + node _T_4107 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_4108 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_4109 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_4110 = and(_T_4108, _T_4109) @[lsu_bus_buffer.scala 445:95] + node _T_4111 = eq(UInt<2>("h03"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_4112 = and(_T_4110, _T_4111) @[lsu_bus_buffer.scala 445:112] + node _T_4113 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_4114 = eq(UInt<2>("h03"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_4115 = and(_T_4113, _T_4114) @[lsu_bus_buffer.scala 445:161] + node _T_4116 = or(_T_4112, _T_4115) @[lsu_bus_buffer.scala 445:132] + node _T_4117 = and(_T_4107, _T_4116) @[lsu_bus_buffer.scala 445:63] + node _T_4118 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_4119 = and(ibuf_drain_vld, _T_4118) @[lsu_bus_buffer.scala 445:201] + node _T_4120 = or(_T_4117, _T_4119) @[lsu_bus_buffer.scala 445:183] + buf_state_en[3] <= _T_4120 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 446:22] + buf_data_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 447:24] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[lsu_bus_buffer.scala 448:47] + node _T_4123 = bits(_T_4122, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_4124 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_4125 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_4126 = mux(_T_4123, _T_4124, _T_4125) @[lsu_bus_buffer.scala 448:30] + buf_data_in[3] <= _T_4126 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_4127 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4127 : @[Conditional.scala 39:67] + node _T_4128 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_4129 = mux(_T_4128, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[3] <= _T_4129 @[lsu_bus_buffer.scala 453:25] + node _T_4130 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[3] <= _T_4130 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4131 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4131 : @[Conditional.scala 39:67] + node _T_4132 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_4133 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_4134 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_4135 = and(_T_4133, _T_4134) @[lsu_bus_buffer.scala 459:104] + node _T_4136 = mux(_T_4135, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_4137 = mux(_T_4132, UInt<3>("h00"), _T_4136) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[3] <= _T_4137 @[lsu_bus_buffer.scala 459:25] + node _T_4138 = eq(obuf_tag0, UInt<3>("h03")) @[lsu_bus_buffer.scala 460:48] + node _T_4139 = eq(obuf_tag1, UInt<3>("h03")) @[lsu_bus_buffer.scala 460:104] + node _T_4140 = and(obuf_merge, _T_4139) @[lsu_bus_buffer.scala 460:91] + node _T_4141 = or(_T_4138, _T_4140) @[lsu_bus_buffer.scala 460:77] + node _T_4142 = and(_T_4141, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_4143 = and(_T_4142, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[3] <= _T_4143 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[lsu_bus_buffer.scala 461:29] + node _T_4144 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_4145 = or(_T_4144, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[3] <= _T_4145 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_4146 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 464:56] + node _T_4147 = eq(_T_4146, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_4148 = and(buf_state_en[3], _T_4147) @[lsu_bus_buffer.scala 464:44] + node _T_4149 = and(_T_4148, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_4150 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_4151 = and(_T_4149, _T_4150) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[3] <= _T_4151 @[lsu_bus_buffer.scala 464:25] + node _T_4152 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[3] <= _T_4152 @[lsu_bus_buffer.scala 465:28] + node _T_4153 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_4154 = and(_T_4153, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_4155 = and(_T_4154, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[3] <= _T_4155 @[lsu_bus_buffer.scala 466:24] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_4157 = and(_T_4156, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_4158 = and(_T_4157, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[3] <= _T_4158 @[lsu_bus_buffer.scala 467:25] + node _T_4159 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_4160 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_4161 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_4163 = mux(_T_4160, _T_4161, _T_4162) @[lsu_bus_buffer.scala 468:73] + node _T_4164 = mux(buf_error_en[3], _T_4159, _T_4163) @[lsu_bus_buffer.scala 468:30] + buf_data_in[3] <= _T_4164 @[lsu_bus_buffer.scala 468:24] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4165 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4165 : @[Conditional.scala 39:67] + node _T_4166 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 472:69] + node _T_4167 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_4168 = and(_T_4166, _T_4167) @[lsu_bus_buffer.scala 472:73] + node _T_4169 = or(io.dec_tlu_force_halt, _T_4168) @[lsu_bus_buffer.scala 472:57] + node _T_4170 = bits(_T_4169, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_4171 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_4172 = and(buf_dual[3], _T_4171) @[lsu_bus_buffer.scala 473:28] + node _T_4173 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 473:57] + node _T_4174 = eq(_T_4173, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_4175 = and(_T_4172, _T_4174) @[lsu_bus_buffer.scala 473:45] + node _T_4176 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_4177 = and(_T_4175, _T_4176) @[lsu_bus_buffer.scala 473:61] + node _T_4178 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 474:27] + node _T_4179 = or(_T_4178, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_4180 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_4181 = and(buf_dual[3], _T_4180) @[lsu_bus_buffer.scala 474:68] + node _T_4182 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 474:97] + node _T_4183 = eq(_T_4182, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_4184 = and(_T_4181, _T_4183) @[lsu_bus_buffer.scala 474:85] + node _T_4185 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_4186 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_4187 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_4188 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_4189 = eq(buf_dualtag[3], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_4190 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4191 = eq(buf_dualtag[3], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4192 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4193 = mux(_T_4185, _T_4186, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4194 = mux(_T_4187, _T_4188, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4195 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4196 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4197 = or(_T_4193, _T_4194) @[Mux.scala 27:72] + node _T_4198 = or(_T_4197, _T_4195) @[Mux.scala 27:72] + node _T_4199 = or(_T_4198, _T_4196) @[Mux.scala 27:72] + wire _T_4200 : UInt<1> @[Mux.scala 27:72] + _T_4200 <= _T_4199 @[Mux.scala 27:72] + node _T_4201 = and(_T_4184, _T_4200) @[lsu_bus_buffer.scala 474:101] + node _T_4202 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_4203 = and(_T_4201, _T_4202) @[lsu_bus_buffer.scala 474:138] + node _T_4204 = and(_T_4203, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_4205 = or(_T_4179, _T_4204) @[lsu_bus_buffer.scala 474:53] + node _T_4206 = mux(_T_4205, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_4207 = mux(_T_4177, UInt<3>("h04"), _T_4206) @[lsu_bus_buffer.scala 473:14] + node _T_4208 = mux(_T_4170, UInt<3>("h00"), _T_4207) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[3] <= _T_4208 @[lsu_bus_buffer.scala 472:27] + node _T_4209 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 475:73] + node _T_4210 = and(bus_rsp_write, _T_4209) @[lsu_bus_buffer.scala 475:52] + node _T_4211 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 476:46] + node _T_4212 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 477:23] + node _T_4213 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 477:47] + node _T_4214 = and(_T_4212, _T_4213) @[lsu_bus_buffer.scala 477:27] + node _T_4215 = or(_T_4211, _T_4214) @[lsu_bus_buffer.scala 476:77] + node _T_4216 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 478:26] + node _T_4217 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 478:54] + node _T_4218 = not(_T_4217) @[lsu_bus_buffer.scala 478:44] + node _T_4219 = and(_T_4216, _T_4218) @[lsu_bus_buffer.scala 478:42] + node _T_4220 = and(_T_4219, buf_samedw[3]) @[lsu_bus_buffer.scala 478:58] + node _T_4221 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 478:94] + node _T_4222 = and(_T_4220, _T_4221) @[lsu_bus_buffer.scala 478:74] + node _T_4223 = or(_T_4215, _T_4222) @[lsu_bus_buffer.scala 477:71] + node _T_4224 = and(bus_rsp_read, _T_4223) @[lsu_bus_buffer.scala 476:25] + node _T_4225 = or(_T_4210, _T_4224) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[3] <= _T_4225 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[lsu_bus_buffer.scala 479:29] + node _T_4226 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_4227 = or(_T_4226, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[3] <= _T_4227 @[lsu_bus_buffer.scala 480:25] + node _T_4228 = and(buf_state_bus_en[3], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_4229 = and(_T_4228, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[3] <= _T_4229 @[lsu_bus_buffer.scala 481:24] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_4231 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 482:111] + node _T_4232 = and(bus_rsp_read_error, _T_4231) @[lsu_bus_buffer.scala 482:91] + node _T_4233 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 483:42] + node _T_4234 = and(bus_rsp_read_error, _T_4233) @[lsu_bus_buffer.scala 483:31] + node _T_4235 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 483:66] + node _T_4236 = and(_T_4234, _T_4235) @[lsu_bus_buffer.scala 483:46] + node _T_4237 = or(_T_4232, _T_4236) @[lsu_bus_buffer.scala 482:143] + node _T_4238 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 484:54] + node _T_4239 = and(bus_rsp_write_error, _T_4238) @[lsu_bus_buffer.scala 484:33] + node _T_4240 = or(_T_4237, _T_4239) @[lsu_bus_buffer.scala 483:88] + node _T_4241 = and(_T_4230, _T_4240) @[lsu_bus_buffer.scala 482:68] + buf_error_en[3] <= _T_4241 @[lsu_bus_buffer.scala 482:25] + node _T_4242 = eq(buf_error_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_4243 = and(buf_state_en[3], _T_4242) @[lsu_bus_buffer.scala 485:48] + node _T_4244 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_4245 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_4246 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_4247 = mux(_T_4244, _T_4245, _T_4246) @[lsu_bus_buffer.scala 485:72] + node _T_4248 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_4249 = mux(_T_4243, _T_4247, _T_4248) @[lsu_bus_buffer.scala 485:30] + buf_data_in[3] <= _T_4249 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4250 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4250 : @[Conditional.scala 39:67] + node _T_4251 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_4252 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 490:86] + node _T_4253 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 490:101] + node _T_4254 = bits(_T_4253, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_4255 = or(_T_4252, _T_4254) @[lsu_bus_buffer.scala 490:90] + node _T_4256 = or(_T_4255, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_4257 = mux(_T_4256, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_4258 = mux(_T_4251, UInt<3>("h00"), _T_4257) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[3] <= _T_4258 @[lsu_bus_buffer.scala 490:25] + node _T_4259 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 491:66] + node _T_4260 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 492:21] + node _T_4261 = bits(_T_4260, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_4262 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[lsu_bus_buffer.scala 492:58] + node _T_4263 = and(_T_4261, _T_4262) @[lsu_bus_buffer.scala 492:38] + node _T_4264 = or(_T_4259, _T_4263) @[lsu_bus_buffer.scala 491:95] + node _T_4265 = and(bus_rsp_read, _T_4264) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[3] <= _T_4265 @[lsu_bus_buffer.scala 491:29] + node _T_4266 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_4267 = or(_T_4266, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[3] <= _T_4267 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4268 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4268 : @[Conditional.scala 39:67] + node _T_4269 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_4270 = mux(_T_4269, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[3] <= _T_4270 @[lsu_bus_buffer.scala 498:25] + node _T_4271 = eq(RspPtr, UInt<2>("h03")) @[lsu_bus_buffer.scala 499:37] + node _T_4272 = eq(buf_dualtag[3], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_4273 = and(buf_dual[3], _T_4272) @[lsu_bus_buffer.scala 499:80] + node _T_4274 = or(_T_4271, _T_4273) @[lsu_bus_buffer.scala 499:65] + node _T_4275 = or(_T_4274, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[3] <= _T_4275 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4276 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4276 : @[Conditional.scala 39:67] + buf_nxtstate[3] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_4277 = bits(buf_state_en[3], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_4278 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4277 : @[Reg.scala 28:19] + _T_4278 <= buf_nxtstate[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[3] <= _T_4278 @[lsu_bus_buffer.scala 512:18] + reg _T_4279 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_4279 <= buf_age_in_3 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[3] <= _T_4279 @[lsu_bus_buffer.scala 513:17] + reg _T_4280 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_4280 <= buf_rspage_in[3] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[3] <= _T_4280 @[lsu_bus_buffer.scala 514:20] + node _T_4281 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_4282 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4281 : @[Reg.scala 28:19] + _T_4282 <= buf_dualtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[3] <= _T_4282 @[lsu_bus_buffer.scala 515:20] + node _T_4283 = bits(buf_dual_in, 3, 3) @[lsu_bus_buffer.scala 516:74] + node _T_4284 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_4285 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4284 : @[Reg.scala 28:19] + _T_4285 <= _T_4283 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[3] <= _T_4285 @[lsu_bus_buffer.scala 516:17] + node _T_4286 = bits(buf_samedw_in, 3, 3) @[lsu_bus_buffer.scala 517:78] + node _T_4287 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_4288 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4287 : @[Reg.scala 28:19] + _T_4288 <= _T_4286 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[3] <= _T_4288 @[lsu_bus_buffer.scala 517:19] + node _T_4289 = bits(buf_nomerge_in, 3, 3) @[lsu_bus_buffer.scala 518:80] + node _T_4290 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_4291 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4290 : @[Reg.scala 28:19] + _T_4291 <= _T_4289 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[3] <= _T_4291 @[lsu_bus_buffer.scala 518:20] + node _T_4292 = bits(buf_dualhi_in, 3, 3) @[lsu_bus_buffer.scala 519:78] + node _T_4293 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_4294 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4293 : @[Reg.scala 28:19] + _T_4294 <= _T_4292 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[3] <= _T_4294 @[lsu_bus_buffer.scala 519:19] + node _T_4295 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4295 : @[Reg.scala 28:19] + _T_4296 <= buf_ldfwd_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4297 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4298 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4297 : @[Reg.scala 28:19] + _T_4298 <= buf_ldfwd_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4299 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4300 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4299 : @[Reg.scala 28:19] + _T_4300 <= buf_ldfwd_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4301 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4302 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4301 : @[Reg.scala 28:19] + _T_4302 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4303 = cat(_T_4302, _T_4300) @[Cat.scala 29:58] + node _T_4304 = cat(_T_4303, _T_4298) @[Cat.scala 29:58] + node _T_4305 = cat(_T_4304, _T_4296) @[Cat.scala 29:58] + buf_ldfwd <= _T_4305 @[lsu_bus_buffer.scala 522:13] + node _T_4306 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4307 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4306 : @[Reg.scala 28:19] + _T_4307 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4308 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4309 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4308 : @[Reg.scala 28:19] + _T_4309 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4310 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4311 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4310 : @[Reg.scala 28:19] + _T_4311 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4312 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4313 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4312 : @[Reg.scala 28:19] + _T_4313 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_ldfwdtag[0] <= _T_4307 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[1] <= _T_4309 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[2] <= _T_4311 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[3] <= _T_4313 @[lsu_bus_buffer.scala 523:16] + node _T_4314 = bits(buf_sideeffect_in, 0, 0) @[lsu_bus_buffer.scala 524:105] + node _T_4315 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4316 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4315 : @[Reg.scala 28:19] + _T_4316 <= _T_4314 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4317 = bits(buf_sideeffect_in, 1, 1) @[lsu_bus_buffer.scala 524:105] + node _T_4318 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4319 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4318 : @[Reg.scala 28:19] + _T_4319 <= _T_4317 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4320 = bits(buf_sideeffect_in, 2, 2) @[lsu_bus_buffer.scala 524:105] + node _T_4321 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4322 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4321 : @[Reg.scala 28:19] + _T_4322 <= _T_4320 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4323 = bits(buf_sideeffect_in, 3, 3) @[lsu_bus_buffer.scala 524:105] + node _T_4324 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4325 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4324 : @[Reg.scala 28:19] + _T_4325 <= _T_4323 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4326 = cat(_T_4325, _T_4322) @[Cat.scala 29:58] + node _T_4327 = cat(_T_4326, _T_4319) @[Cat.scala 29:58] + node _T_4328 = cat(_T_4327, _T_4316) @[Cat.scala 29:58] + buf_sideeffect <= _T_4328 @[lsu_bus_buffer.scala 524:18] + node _T_4329 = bits(buf_unsign_in, 0, 0) @[lsu_bus_buffer.scala 525:97] + node _T_4330 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4331 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4330 : @[Reg.scala 28:19] + _T_4331 <= _T_4329 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4332 = bits(buf_unsign_in, 1, 1) @[lsu_bus_buffer.scala 525:97] + node _T_4333 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4334 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4333 : @[Reg.scala 28:19] + _T_4334 <= _T_4332 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4335 = bits(buf_unsign_in, 2, 2) @[lsu_bus_buffer.scala 525:97] + node _T_4336 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4337 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4336 : @[Reg.scala 28:19] + _T_4337 <= _T_4335 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4338 = bits(buf_unsign_in, 3, 3) @[lsu_bus_buffer.scala 525:97] + node _T_4339 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4340 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4339 : @[Reg.scala 28:19] + _T_4340 <= _T_4338 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4341 = cat(_T_4340, _T_4337) @[Cat.scala 29:58] + node _T_4342 = cat(_T_4341, _T_4334) @[Cat.scala 29:58] + node _T_4343 = cat(_T_4342, _T_4331) @[Cat.scala 29:58] + buf_unsign <= _T_4343 @[lsu_bus_buffer.scala 525:14] + node _T_4344 = bits(buf_write_in, 0, 0) @[lsu_bus_buffer.scala 526:95] + node _T_4345 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4346 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4345 : @[Reg.scala 28:19] + _T_4346 <= _T_4344 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4347 = bits(buf_write_in, 1, 1) @[lsu_bus_buffer.scala 526:95] + node _T_4348 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4349 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4348 : @[Reg.scala 28:19] + _T_4349 <= _T_4347 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4350 = bits(buf_write_in, 2, 2) @[lsu_bus_buffer.scala 526:95] + node _T_4351 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4352 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4351 : @[Reg.scala 28:19] + _T_4352 <= _T_4350 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4353 = bits(buf_write_in, 3, 3) @[lsu_bus_buffer.scala 526:95] + node _T_4354 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4355 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4354 : @[Reg.scala 28:19] + _T_4355 <= _T_4353 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4356 = cat(_T_4355, _T_4352) @[Cat.scala 29:58] + node _T_4357 = cat(_T_4356, _T_4349) @[Cat.scala 29:58] + node _T_4358 = cat(_T_4357, _T_4346) @[Cat.scala 29:58] + buf_write <= _T_4358 @[lsu_bus_buffer.scala 526:13] + node _T_4359 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4360 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4359 : @[Reg.scala 28:19] + _T_4360 <= buf_sz_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4361 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4362 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4361 : @[Reg.scala 28:19] + _T_4362 <= buf_sz_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4363 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4364 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4363 : @[Reg.scala 28:19] + _T_4364 <= buf_sz_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4365 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4366 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4365 : @[Reg.scala 28:19] + _T_4366 <= buf_sz_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_sz[0] <= _T_4360 @[lsu_bus_buffer.scala 527:10] + buf_sz[1] <= _T_4362 @[lsu_bus_buffer.scala 527:10] + buf_sz[2] <= _T_4364 @[lsu_bus_buffer.scala 527:10] + buf_sz[3] <= _T_4366 @[lsu_bus_buffer.scala 527:10] + node _T_4367 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_4 of rvclkhdr_26 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_4367 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4368 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4367 : @[Reg.scala 28:19] + _T_4368 <= buf_addr_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4369 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_5 of rvclkhdr_27 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_4369 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4370 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4369 : @[Reg.scala 28:19] + _T_4370 <= buf_addr_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4371 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_6 of rvclkhdr_28 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_4371 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4372 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4371 : @[Reg.scala 28:19] + _T_4372 <= buf_addr_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4373 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_7 of rvclkhdr_29 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_4373 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4374 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4373 : @[Reg.scala 28:19] + _T_4374 <= buf_addr_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_addr[0] <= _T_4368 @[lsu_bus_buffer.scala 528:12] + buf_addr[1] <= _T_4370 @[lsu_bus_buffer.scala 528:12] + buf_addr[2] <= _T_4372 @[lsu_bus_buffer.scala 528:12] + buf_addr[3] <= _T_4374 @[lsu_bus_buffer.scala 528:12] + node _T_4375 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4376 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4375 : @[Reg.scala 28:19] + _T_4376 <= buf_byteen_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4377 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4378 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4377 : @[Reg.scala 28:19] + _T_4378 <= buf_byteen_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4379 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4380 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4379 : @[Reg.scala 28:19] + _T_4380 <= buf_byteen_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4381 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4382 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4381 : @[Reg.scala 28:19] + _T_4382 <= buf_byteen_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen[0] <= _T_4376 @[lsu_bus_buffer.scala 529:14] + buf_byteen[1] <= _T_4378 @[lsu_bus_buffer.scala 529:14] + buf_byteen[2] <= _T_4380 @[lsu_bus_buffer.scala 529:14] + buf_byteen[3] <= _T_4382 @[lsu_bus_buffer.scala 529:14] + inst rvclkhdr_8 of rvclkhdr_30 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4383 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[0] : @[Reg.scala 28:19] + _T_4383 <= buf_data_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_9 of rvclkhdr_31 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4384 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[1] : @[Reg.scala 28:19] + _T_4384 <= buf_data_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_10 of rvclkhdr_32 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4385 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[2] : @[Reg.scala 28:19] + _T_4385 <= buf_data_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_11 of rvclkhdr_33 @[lib.scala 404:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 407:17] + rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4386 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[3] : @[Reg.scala 28:19] + _T_4386 <= buf_data_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_data[0] <= _T_4383 @[lsu_bus_buffer.scala 530:12] + buf_data[1] <= _T_4384 @[lsu_bus_buffer.scala 530:12] + buf_data[2] <= _T_4385 @[lsu_bus_buffer.scala 530:12] + buf_data[3] <= _T_4386 @[lsu_bus_buffer.scala 530:12] + node _T_4387 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4388 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 531:133] + node _T_4389 = mux(buf_error_en[0], UInt<1>("h01"), _T_4388) @[lsu_bus_buffer.scala 531:98] + node _T_4390 = and(_T_4387, _T_4389) @[lsu_bus_buffer.scala 531:93] + reg _T_4391 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4391 <= _T_4390 @[lsu_bus_buffer.scala 531:80] + node _T_4392 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4393 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 531:133] + node _T_4394 = mux(buf_error_en[1], UInt<1>("h01"), _T_4393) @[lsu_bus_buffer.scala 531:98] + node _T_4395 = and(_T_4392, _T_4394) @[lsu_bus_buffer.scala 531:93] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4396 <= _T_4395 @[lsu_bus_buffer.scala 531:80] + node _T_4397 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4398 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 531:133] + node _T_4399 = mux(buf_error_en[2], UInt<1>("h01"), _T_4398) @[lsu_bus_buffer.scala 531:98] + node _T_4400 = and(_T_4397, _T_4399) @[lsu_bus_buffer.scala 531:93] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4401 <= _T_4400 @[lsu_bus_buffer.scala 531:80] + node _T_4402 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4403 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 531:133] + node _T_4404 = mux(buf_error_en[3], UInt<1>("h01"), _T_4403) @[lsu_bus_buffer.scala 531:98] + node _T_4405 = and(_T_4402, _T_4404) @[lsu_bus_buffer.scala 531:93] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4406 <= _T_4405 @[lsu_bus_buffer.scala 531:80] + node _T_4407 = cat(_T_4406, _T_4401) @[Cat.scala 29:58] + node _T_4408 = cat(_T_4407, _T_4396) @[Cat.scala 29:58] + node _T_4409 = cat(_T_4408, _T_4391) @[Cat.scala 29:58] + buf_error <= _T_4409 @[lsu_bus_buffer.scala 531:13] + node _T_4410 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4411 = mux(io.ldst_dual_m, _T_4410, io.lsu_busreq_m) @[lsu_bus_buffer.scala 532:28] + node _T_4412 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4413 = mux(io.ldst_dual_r, _T_4412, io.lsu_busreq_r) @[lsu_bus_buffer.scala 532:94] + node _T_4414 = add(_T_4411, _T_4413) @[lsu_bus_buffer.scala 532:88] + node _T_4415 = add(_T_4414, ibuf_valid) @[lsu_bus_buffer.scala 532:154] + node _T_4416 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4417 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4418 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4419 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4420 = add(_T_4416, _T_4417) @[lsu_bus_buffer.scala 532:217] + node _T_4421 = add(_T_4420, _T_4418) @[lsu_bus_buffer.scala 532:217] + node _T_4422 = add(_T_4421, _T_4419) @[lsu_bus_buffer.scala 532:217] + node _T_4423 = add(_T_4415, _T_4422) @[lsu_bus_buffer.scala 532:169] + node buf_numvld_any = tail(_T_4423, 1) @[lsu_bus_buffer.scala 532:169] + node _T_4424 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 533:60] + node _T_4425 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4426 = and(_T_4424, _T_4425) @[lsu_bus_buffer.scala 533:64] + node _T_4427 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4428 = and(_T_4426, _T_4427) @[lsu_bus_buffer.scala 533:89] + node _T_4429 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 533:60] + node _T_4430 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4431 = and(_T_4429, _T_4430) @[lsu_bus_buffer.scala 533:64] + node _T_4432 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4433 = and(_T_4431, _T_4432) @[lsu_bus_buffer.scala 533:89] + node _T_4434 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 533:60] + node _T_4435 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4436 = and(_T_4434, _T_4435) @[lsu_bus_buffer.scala 533:64] + node _T_4437 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4438 = and(_T_4436, _T_4437) @[lsu_bus_buffer.scala 533:89] + node _T_4439 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 533:60] + node _T_4440 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4441 = and(_T_4439, _T_4440) @[lsu_bus_buffer.scala 533:64] + node _T_4442 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4443 = and(_T_4441, _T_4442) @[lsu_bus_buffer.scala 533:89] + node _T_4444 = add(_T_4443, _T_4438) @[lsu_bus_buffer.scala 533:142] + node _T_4445 = add(_T_4444, _T_4433) @[lsu_bus_buffer.scala 533:142] + node _T_4446 = add(_T_4445, _T_4428) @[lsu_bus_buffer.scala 533:142] + buf_numvld_wrcmd_any <= _T_4446 @[lsu_bus_buffer.scala 533:24] + node _T_4447 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4448 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4449 = and(_T_4447, _T_4448) @[lsu_bus_buffer.scala 534:73] + node _T_4450 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4451 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4452 = and(_T_4450, _T_4451) @[lsu_bus_buffer.scala 534:73] + node _T_4453 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4454 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4455 = and(_T_4453, _T_4454) @[lsu_bus_buffer.scala 534:73] + node _T_4456 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4457 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4458 = and(_T_4456, _T_4457) @[lsu_bus_buffer.scala 534:73] + node _T_4459 = add(_T_4458, _T_4455) @[lsu_bus_buffer.scala 534:126] + node _T_4460 = add(_T_4459, _T_4452) @[lsu_bus_buffer.scala 534:126] + node _T_4461 = add(_T_4460, _T_4449) @[lsu_bus_buffer.scala 534:126] + buf_numvld_cmd_any <= _T_4461 @[lsu_bus_buffer.scala 534:22] + node _T_4462 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4463 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4464 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4465 = and(_T_4463, _T_4464) @[lsu_bus_buffer.scala 535:100] + node _T_4466 = or(_T_4462, _T_4465) @[lsu_bus_buffer.scala 535:74] + node _T_4467 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4468 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4469 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4470 = and(_T_4468, _T_4469) @[lsu_bus_buffer.scala 535:100] + node _T_4471 = or(_T_4467, _T_4470) @[lsu_bus_buffer.scala 535:74] + node _T_4472 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4473 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4474 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4475 = and(_T_4473, _T_4474) @[lsu_bus_buffer.scala 535:100] + node _T_4476 = or(_T_4472, _T_4475) @[lsu_bus_buffer.scala 535:74] + node _T_4477 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4478 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4479 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4480 = and(_T_4478, _T_4479) @[lsu_bus_buffer.scala 535:100] + node _T_4481 = or(_T_4477, _T_4480) @[lsu_bus_buffer.scala 535:74] + node _T_4482 = add(_T_4481, _T_4476) @[lsu_bus_buffer.scala 535:154] + node _T_4483 = add(_T_4482, _T_4471) @[lsu_bus_buffer.scala 535:154] + node _T_4484 = add(_T_4483, _T_4466) @[lsu_bus_buffer.scala 535:154] + buf_numvld_pend_any <= _T_4484 @[lsu_bus_buffer.scala 535:23] + node _T_4485 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4486 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4487 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4488 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4489 = or(_T_4488, _T_4487) @[lsu_bus_buffer.scala 536:93] + node _T_4490 = or(_T_4489, _T_4486) @[lsu_bus_buffer.scala 536:93] + node _T_4491 = or(_T_4490, _T_4485) @[lsu_bus_buffer.scala 536:93] + any_done_wait_state <= _T_4491 @[lsu_bus_buffer.scala 536:23] + node _T_4492 = orr(buf_numvld_pend_any) @[lsu_bus_buffer.scala 537:53] + io.lsu_bus_buffer_pend_any <= _T_4492 @[lsu_bus_buffer.scala 537:30] + node _T_4493 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[lsu_bus_buffer.scala 538:52] + node _T_4494 = geq(buf_numvld_any, UInt<2>("h03")) @[lsu_bus_buffer.scala 538:92] + node _T_4495 = eq(buf_numvld_any, UInt<3>("h04")) @[lsu_bus_buffer.scala 538:121] + node _T_4496 = mux(_T_4493, _T_4494, _T_4495) @[lsu_bus_buffer.scala 538:36] + io.lsu_bus_buffer_full_any <= _T_4496 @[lsu_bus_buffer.scala 538:30] + node _T_4497 = orr(buf_state[0]) @[lsu_bus_buffer.scala 539:52] + node _T_4498 = orr(buf_state[1]) @[lsu_bus_buffer.scala 539:52] + node _T_4499 = orr(buf_state[2]) @[lsu_bus_buffer.scala 539:52] + node _T_4500 = orr(buf_state[3]) @[lsu_bus_buffer.scala 539:52] + node _T_4501 = or(_T_4497, _T_4498) @[lsu_bus_buffer.scala 539:65] + node _T_4502 = or(_T_4501, _T_4499) @[lsu_bus_buffer.scala 539:65] + node _T_4503 = or(_T_4502, _T_4500) @[lsu_bus_buffer.scala 539:65] + node _T_4504 = eq(_T_4503, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:34] + node _T_4505 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:72] + node _T_4506 = and(_T_4504, _T_4505) @[lsu_bus_buffer.scala 539:70] + node _T_4507 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:86] + node _T_4508 = and(_T_4506, _T_4507) @[lsu_bus_buffer.scala 539:84] + io.lsu_bus_buffer_empty_any <= _T_4508 @[lsu_bus_buffer.scala 539:31] + node _T_4509 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[lsu_bus_buffer.scala 541:64] + node _T_4510 = and(_T_4509, io.lsu_pkt_m.bits.load) @[lsu_bus_buffer.scala 541:85] + node _T_4511 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_bus_buffer.scala 541:112] + node _T_4512 = and(_T_4510, _T_4511) @[lsu_bus_buffer.scala 541:110] + node _T_4513 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 541:129] + node _T_4514 = and(_T_4512, _T_4513) @[lsu_bus_buffer.scala 541:127] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= _T_4514 @[lsu_bus_buffer.scala 541:45] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= WrPtr0_m @[lsu_bus_buffer.scala 542:43] + wire lsu_nonblock_load_valid_r : UInt<1> + lsu_nonblock_load_valid_r <= UInt<1>("h00") + node _T_4515 = eq(io.lsu_commit_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:74] + node _T_4516 = and(lsu_nonblock_load_valid_r, _T_4515) @[lsu_bus_buffer.scala 544:72] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= _T_4516 @[lsu_bus_buffer.scala 544:43] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 545:47] + node _T_4517 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4518 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 546:106] + node _T_4519 = eq(_T_4518, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4520 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4521 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 546:106] + node _T_4522 = eq(_T_4521, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4523 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4524 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 546:106] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4526 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4527 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 546:106] + node _T_4528 = eq(_T_4527, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4529 = mux(_T_4517, _T_4519, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4530 = mux(_T_4520, _T_4522, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4531 = mux(_T_4523, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4532 = mux(_T_4526, _T_4528, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4533 = or(_T_4529, _T_4530) @[Mux.scala 27:72] + node _T_4534 = or(_T_4533, _T_4531) @[Mux.scala 27:72] + node _T_4535 = or(_T_4534, _T_4532) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_load_data_ready <= _T_4535 @[Mux.scala 27:72] + node _T_4536 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4537 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 547:117] + node _T_4538 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 547:133] + node _T_4539 = eq(_T_4538, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4540 = and(_T_4537, _T_4539) @[lsu_bus_buffer.scala 547:121] + node _T_4541 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4542 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 547:117] + node _T_4543 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 547:133] + node _T_4544 = eq(_T_4543, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4545 = and(_T_4542, _T_4544) @[lsu_bus_buffer.scala 547:121] + node _T_4546 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4547 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 547:117] + node _T_4548 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 547:133] + node _T_4549 = eq(_T_4548, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4550 = and(_T_4547, _T_4549) @[lsu_bus_buffer.scala 547:121] + node _T_4551 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4552 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 547:117] + node _T_4553 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 547:133] + node _T_4554 = eq(_T_4553, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4555 = and(_T_4552, _T_4554) @[lsu_bus_buffer.scala 547:121] + node _T_4556 = mux(_T_4536, _T_4540, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4557 = mux(_T_4541, _T_4545, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4558 = mux(_T_4546, _T_4550, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4559 = mux(_T_4551, _T_4555, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4560 = or(_T_4556, _T_4557) @[Mux.scala 27:72] + node _T_4561 = or(_T_4560, _T_4558) @[Mux.scala 27:72] + node _T_4562 = or(_T_4561, _T_4559) @[Mux.scala 27:72] + wire _T_4563 : UInt<1> @[Mux.scala 27:72] + _T_4563 <= _T_4562 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_error <= _T_4563 @[lsu_bus_buffer.scala 547:48] + node _T_4564 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4565 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 548:114] + node _T_4566 = eq(_T_4565, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4567 = and(_T_4564, _T_4566) @[lsu_bus_buffer.scala 548:102] + node _T_4568 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4569 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4570 = or(_T_4568, _T_4569) @[lsu_bus_buffer.scala 548:134] + node _T_4571 = and(_T_4567, _T_4570) @[lsu_bus_buffer.scala 548:118] + node _T_4572 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4573 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 548:114] + node _T_4574 = eq(_T_4573, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4575 = and(_T_4572, _T_4574) @[lsu_bus_buffer.scala 548:102] + node _T_4576 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4577 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4578 = or(_T_4576, _T_4577) @[lsu_bus_buffer.scala 548:134] + node _T_4579 = and(_T_4575, _T_4578) @[lsu_bus_buffer.scala 548:118] + node _T_4580 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4581 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 548:114] + node _T_4582 = eq(_T_4581, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4583 = and(_T_4580, _T_4582) @[lsu_bus_buffer.scala 548:102] + node _T_4584 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4585 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4586 = or(_T_4584, _T_4585) @[lsu_bus_buffer.scala 548:134] + node _T_4587 = and(_T_4583, _T_4586) @[lsu_bus_buffer.scala 548:118] + node _T_4588 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4589 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 548:114] + node _T_4590 = eq(_T_4589, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4591 = and(_T_4588, _T_4590) @[lsu_bus_buffer.scala 548:102] + node _T_4592 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4593 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4594 = or(_T_4592, _T_4593) @[lsu_bus_buffer.scala 548:134] + node _T_4595 = and(_T_4591, _T_4594) @[lsu_bus_buffer.scala 548:118] + node _T_4596 = mux(_T_4571, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4597 = mux(_T_4579, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4598 = mux(_T_4587, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4599 = mux(_T_4595, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4600 = or(_T_4596, _T_4597) @[Mux.scala 27:72] + node _T_4601 = or(_T_4600, _T_4598) @[Mux.scala 27:72] + node _T_4602 = or(_T_4601, _T_4599) @[Mux.scala 27:72] + wire _T_4603 : UInt<2> @[Mux.scala 27:72] + _T_4603 <= _T_4602 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= _T_4603 @[lsu_bus_buffer.scala 548:45] + node _T_4604 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4605 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 549:101] + node _T_4606 = eq(_T_4605, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4607 = and(_T_4604, _T_4606) @[lsu_bus_buffer.scala 549:89] + node _T_4608 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4609 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4610 = or(_T_4608, _T_4609) @[lsu_bus_buffer.scala 549:121] + node _T_4611 = and(_T_4607, _T_4610) @[lsu_bus_buffer.scala 549:105] + node _T_4612 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4613 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 549:101] + node _T_4614 = eq(_T_4613, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4615 = and(_T_4612, _T_4614) @[lsu_bus_buffer.scala 549:89] + node _T_4616 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4617 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4618 = or(_T_4616, _T_4617) @[lsu_bus_buffer.scala 549:121] + node _T_4619 = and(_T_4615, _T_4618) @[lsu_bus_buffer.scala 549:105] + node _T_4620 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4621 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 549:101] + node _T_4622 = eq(_T_4621, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4623 = and(_T_4620, _T_4622) @[lsu_bus_buffer.scala 549:89] + node _T_4624 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4625 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4626 = or(_T_4624, _T_4625) @[lsu_bus_buffer.scala 549:121] + node _T_4627 = and(_T_4623, _T_4626) @[lsu_bus_buffer.scala 549:105] + node _T_4628 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4629 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 549:101] + node _T_4630 = eq(_T_4629, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4631 = and(_T_4628, _T_4630) @[lsu_bus_buffer.scala 549:89] + node _T_4632 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4633 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4634 = or(_T_4632, _T_4633) @[lsu_bus_buffer.scala 549:121] + node _T_4635 = and(_T_4631, _T_4634) @[lsu_bus_buffer.scala 549:105] + node _T_4636 = mux(_T_4611, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4637 = mux(_T_4619, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4638 = mux(_T_4627, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4639 = mux(_T_4635, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4640 = or(_T_4636, _T_4637) @[Mux.scala 27:72] + node _T_4641 = or(_T_4640, _T_4638) @[Mux.scala 27:72] + node _T_4642 = or(_T_4641, _T_4639) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_lo <= _T_4642 @[Mux.scala 27:72] + node _T_4643 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4644 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 550:101] + node _T_4645 = eq(_T_4644, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4646 = and(_T_4643, _T_4645) @[lsu_bus_buffer.scala 550:89] + node _T_4647 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 550:120] + node _T_4648 = and(_T_4646, _T_4647) @[lsu_bus_buffer.scala 550:105] + node _T_4649 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4650 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 550:101] + node _T_4651 = eq(_T_4650, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4652 = and(_T_4649, _T_4651) @[lsu_bus_buffer.scala 550:89] + node _T_4653 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 550:120] + node _T_4654 = and(_T_4652, _T_4653) @[lsu_bus_buffer.scala 550:105] + node _T_4655 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4656 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 550:101] + node _T_4657 = eq(_T_4656, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4658 = and(_T_4655, _T_4657) @[lsu_bus_buffer.scala 550:89] + node _T_4659 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 550:120] + node _T_4660 = and(_T_4658, _T_4659) @[lsu_bus_buffer.scala 550:105] + node _T_4661 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4662 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 550:101] + node _T_4663 = eq(_T_4662, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4664 = and(_T_4661, _T_4663) @[lsu_bus_buffer.scala 550:89] + node _T_4665 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 550:120] + node _T_4666 = and(_T_4664, _T_4665) @[lsu_bus_buffer.scala 550:105] + node _T_4667 = mux(_T_4648, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4668 = mux(_T_4654, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4669 = mux(_T_4660, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4670 = mux(_T_4666, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4671 = or(_T_4667, _T_4668) @[Mux.scala 27:72] + node _T_4672 = or(_T_4671, _T_4669) @[Mux.scala 27:72] + node _T_4673 = or(_T_4672, _T_4670) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_hi <= _T_4673 @[Mux.scala 27:72] + node _T_4674 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_4675 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_4676 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_4677 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_4678 = mux(_T_4674, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4679 = mux(_T_4675, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4680 = mux(_T_4676, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4681 = mux(_T_4677, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4682 = or(_T_4678, _T_4679) @[Mux.scala 27:72] + node _T_4683 = or(_T_4682, _T_4680) @[Mux.scala 27:72] + node _T_4684 = or(_T_4683, _T_4681) @[Mux.scala 27:72] + wire _T_4685 : UInt<32> @[Mux.scala 27:72] + _T_4685 <= _T_4684 @[Mux.scala 27:72] + node lsu_nonblock_addr_offset = bits(_T_4685, 1, 0) @[lsu_bus_buffer.scala 551:96] + node _T_4686 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_4687 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_4688 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_4689 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_4690 = mux(_T_4686, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4691 = mux(_T_4687, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4692 = mux(_T_4688, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4693 = mux(_T_4689, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4694 = or(_T_4690, _T_4691) @[Mux.scala 27:72] + node _T_4695 = or(_T_4694, _T_4692) @[Mux.scala 27:72] + node _T_4696 = or(_T_4695, _T_4693) @[Mux.scala 27:72] + wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] + lsu_nonblock_sz <= _T_4696 @[Mux.scala 27:72] + node _T_4697 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_4698 = bits(buf_unsign, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_4699 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_4700 = bits(buf_unsign, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_4701 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_4702 = bits(buf_unsign, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4703 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4704 = bits(buf_unsign, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4705 = mux(_T_4697, _T_4698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4706 = mux(_T_4699, _T_4700, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4707 = mux(_T_4701, _T_4702, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4708 = mux(_T_4703, _T_4704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4709 = or(_T_4705, _T_4706) @[Mux.scala 27:72] + node _T_4710 = or(_T_4709, _T_4707) @[Mux.scala 27:72] + node _T_4711 = or(_T_4710, _T_4708) @[Mux.scala 27:72] + wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_unsign <= _T_4711 @[Mux.scala 27:72] + node _T_4712 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] + node _T_4713 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[lsu_bus_buffer.scala 555:121] + node lsu_nonblock_data_unalgn = dshr(_T_4712, _T_4713) @[lsu_bus_buffer.scala 555:92] + node _T_4714 = eq(io.dctl_busbuff.lsu_nonblock_load_data_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 557:82] + node _T_4715 = and(lsu_nonblock_load_data_ready, _T_4714) @[lsu_bus_buffer.scala 557:80] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= _T_4715 @[lsu_bus_buffer.scala 557:48] + node _T_4716 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 558:81] + node _T_4717 = and(lsu_nonblock_unsign, _T_4716) @[lsu_bus_buffer.scala 558:63] + node _T_4718 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 558:131] + node _T_4719 = cat(UInt<24>("h00"), _T_4718) @[Cat.scala 29:58] + node _T_4720 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 559:45] + node _T_4721 = and(lsu_nonblock_unsign, _T_4720) @[lsu_bus_buffer.scala 559:26] + node _T_4722 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 559:95] + node _T_4723 = cat(UInt<16>("h00"), _T_4722) @[Cat.scala 29:58] + node _T_4724 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 560:6] + node _T_4725 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 560:45] + node _T_4726 = and(_T_4724, _T_4725) @[lsu_bus_buffer.scala 560:27] + node _T_4727 = bits(lsu_nonblock_data_unalgn, 7, 7) @[lsu_bus_buffer.scala 560:93] + node _T_4728 = bits(_T_4727, 0, 0) @[Bitwise.scala 72:15] + node _T_4729 = mux(_T_4728, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_4730 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 560:123] + node _T_4731 = cat(_T_4729, _T_4730) @[Cat.scala 29:58] + node _T_4732 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 561:6] + node _T_4733 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 561:45] + node _T_4734 = and(_T_4732, _T_4733) @[lsu_bus_buffer.scala 561:27] + node _T_4735 = bits(lsu_nonblock_data_unalgn, 15, 15) @[lsu_bus_buffer.scala 561:93] + node _T_4736 = bits(_T_4735, 0, 0) @[Bitwise.scala 72:15] + node _T_4737 = mux(_T_4736, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_4738 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 561:124] + node _T_4739 = cat(_T_4737, _T_4738) @[Cat.scala 29:58] + node _T_4740 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[lsu_bus_buffer.scala 562:21] + node _T_4741 = mux(_T_4717, _T_4719, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4742 = mux(_T_4721, _T_4723, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4743 = mux(_T_4726, _T_4731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4744 = mux(_T_4734, _T_4739, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4745 = mux(_T_4740, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4746 = or(_T_4741, _T_4742) @[Mux.scala 27:72] + node _T_4747 = or(_T_4746, _T_4743) @[Mux.scala 27:72] + node _T_4748 = or(_T_4747, _T_4744) @[Mux.scala 27:72] + node _T_4749 = or(_T_4748, _T_4745) @[Mux.scala 27:72] + wire _T_4750 : UInt<64> @[Mux.scala 27:72] + _T_4750 <= _T_4749 @[Mux.scala 27:72] + io.lsu_nonblock_load_data <= _T_4750 @[lsu_bus_buffer.scala 558:29] + node _T_4751 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4752 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 563:89] + node _T_4753 = and(_T_4751, _T_4752) @[lsu_bus_buffer.scala 563:73] + node _T_4754 = and(_T_4753, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4755 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4756 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 563:89] + node _T_4757 = and(_T_4755, _T_4756) @[lsu_bus_buffer.scala 563:73] + node _T_4758 = and(_T_4757, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4759 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4760 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 563:89] + node _T_4761 = and(_T_4759, _T_4760) @[lsu_bus_buffer.scala 563:73] + node _T_4762 = and(_T_4761, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4763 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4764 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 563:89] + node _T_4765 = and(_T_4763, _T_4764) @[lsu_bus_buffer.scala 563:73] + node _T_4766 = and(_T_4765, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4767 = or(_T_4754, _T_4758) @[lsu_bus_buffer.scala 563:153] + node _T_4768 = or(_T_4767, _T_4762) @[lsu_bus_buffer.scala 563:153] + node _T_4769 = or(_T_4768, _T_4766) @[lsu_bus_buffer.scala 563:153] + node _T_4770 = and(obuf_valid, obuf_sideeffect) @[lsu_bus_buffer.scala 563:171] + node _T_4771 = and(_T_4770, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:189] + node _T_4772 = or(_T_4769, _T_4771) @[lsu_bus_buffer.scala 563:157] + bus_sideeffect_pend <= _T_4772 @[lsu_bus_buffer.scala 563:23] + node _T_4773 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4774 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4775 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4776 = eq(_T_4774, _T_4775) @[lsu_bus_buffer.scala 565:37] + node _T_4777 = and(obuf_valid, _T_4776) @[lsu_bus_buffer.scala 565:19] + node _T_4778 = eq(obuf_tag0, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:73] + node _T_4779 = eq(obuf_tag1, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:107] + node _T_4780 = and(obuf_merge, _T_4779) @[lsu_bus_buffer.scala 565:95] + node _T_4781 = or(_T_4778, _T_4780) @[lsu_bus_buffer.scala 565:81] + node _T_4782 = eq(_T_4781, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4783 = and(_T_4777, _T_4782) @[lsu_bus_buffer.scala 565:59] + node _T_4784 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4785 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4786 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4787 = eq(_T_4785, _T_4786) @[lsu_bus_buffer.scala 565:37] + node _T_4788 = and(obuf_valid, _T_4787) @[lsu_bus_buffer.scala 565:19] + node _T_4789 = eq(obuf_tag0, UInt<1>("h01")) @[lsu_bus_buffer.scala 565:73] + node _T_4790 = eq(obuf_tag1, UInt<1>("h01")) @[lsu_bus_buffer.scala 565:107] + node _T_4791 = and(obuf_merge, _T_4790) @[lsu_bus_buffer.scala 565:95] + node _T_4792 = or(_T_4789, _T_4791) @[lsu_bus_buffer.scala 565:81] + node _T_4793 = eq(_T_4792, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4794 = and(_T_4788, _T_4793) @[lsu_bus_buffer.scala 565:59] + node _T_4795 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4796 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4797 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4798 = eq(_T_4796, _T_4797) @[lsu_bus_buffer.scala 565:37] + node _T_4799 = and(obuf_valid, _T_4798) @[lsu_bus_buffer.scala 565:19] + node _T_4800 = eq(obuf_tag0, UInt<2>("h02")) @[lsu_bus_buffer.scala 565:73] + node _T_4801 = eq(obuf_tag1, UInt<2>("h02")) @[lsu_bus_buffer.scala 565:107] + node _T_4802 = and(obuf_merge, _T_4801) @[lsu_bus_buffer.scala 565:95] + node _T_4803 = or(_T_4800, _T_4802) @[lsu_bus_buffer.scala 565:81] + node _T_4804 = eq(_T_4803, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4805 = and(_T_4799, _T_4804) @[lsu_bus_buffer.scala 565:59] + node _T_4806 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4807 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4808 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4809 = eq(_T_4807, _T_4808) @[lsu_bus_buffer.scala 565:37] + node _T_4810 = and(obuf_valid, _T_4809) @[lsu_bus_buffer.scala 565:19] + node _T_4811 = eq(obuf_tag0, UInt<2>("h03")) @[lsu_bus_buffer.scala 565:73] + node _T_4812 = eq(obuf_tag1, UInt<2>("h03")) @[lsu_bus_buffer.scala 565:107] + node _T_4813 = and(obuf_merge, _T_4812) @[lsu_bus_buffer.scala 565:95] + node _T_4814 = or(_T_4811, _T_4813) @[lsu_bus_buffer.scala 565:81] + node _T_4815 = eq(_T_4814, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4816 = and(_T_4810, _T_4815) @[lsu_bus_buffer.scala 565:59] + node _T_4817 = mux(_T_4773, _T_4783, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4818 = mux(_T_4784, _T_4794, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4819 = mux(_T_4795, _T_4805, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4820 = mux(_T_4806, _T_4816, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4821 = or(_T_4817, _T_4818) @[Mux.scala 27:72] + node _T_4822 = or(_T_4821, _T_4819) @[Mux.scala 27:72] + node _T_4823 = or(_T_4822, _T_4820) @[Mux.scala 27:72] + wire _T_4824 : UInt<1> @[Mux.scala 27:72] + _T_4824 <= _T_4823 @[Mux.scala 27:72] + bus_addr_match_pending <= _T_4824 @[lsu_bus_buffer.scala 564:26] + node _T_4825 = or(obuf_cmd_done, obuf_data_done) @[lsu_bus_buffer.scala 567:54] + node _T_4826 = mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 567:75] + node _T_4827 = and(io.lsu_axi.aw.ready, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 567:153] + node _T_4828 = mux(_T_4825, _T_4826, _T_4827) @[lsu_bus_buffer.scala 567:39] + node _T_4829 = mux(obuf_write, _T_4828, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 567:23] + bus_cmd_ready <= _T_4829 @[lsu_bus_buffer.scala 567:17] + node _T_4830 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 568:40] + bus_wcmd_sent <= _T_4830 @[lsu_bus_buffer.scala 568:17] + node _T_4831 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 569:40] + bus_wdata_sent <= _T_4831 @[lsu_bus_buffer.scala 569:18] + node _T_4832 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 570:35] + node _T_4833 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 570:70] + node _T_4834 = and(_T_4832, _T_4833) @[lsu_bus_buffer.scala 570:52] + node _T_4835 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 570:112] + node _T_4836 = or(_T_4834, _T_4835) @[lsu_bus_buffer.scala 570:89] + bus_cmd_sent <= _T_4836 @[lsu_bus_buffer.scala 570:16] + node _T_4837 = and(io.lsu_axi.r.valid, io.lsu_axi.r.ready) @[lsu_bus_buffer.scala 571:38] + bus_rsp_read <= _T_4837 @[lsu_bus_buffer.scala 571:16] + node _T_4838 = and(io.lsu_axi.b.valid, io.lsu_axi.b.ready) @[lsu_bus_buffer.scala 572:39] + bus_rsp_write <= _T_4838 @[lsu_bus_buffer.scala 572:17] + bus_rsp_read_tag <= io.lsu_axi.r.bits.id @[lsu_bus_buffer.scala 573:20] + bus_rsp_write_tag <= io.lsu_axi.b.bits.id @[lsu_bus_buffer.scala 574:21] + node _T_4839 = neq(io.lsu_axi.b.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 575:66] + node _T_4840 = and(bus_rsp_write, _T_4839) @[lsu_bus_buffer.scala 575:40] + bus_rsp_write_error <= _T_4840 @[lsu_bus_buffer.scala 575:23] + node _T_4841 = neq(io.lsu_axi.r.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 576:64] + node _T_4842 = and(bus_rsp_read, _T_4841) @[lsu_bus_buffer.scala 576:38] + bus_rsp_read_error <= _T_4842 @[lsu_bus_buffer.scala 576:22] + bus_rsp_rdata <= io.lsu_axi.r.bits.data @[lsu_bus_buffer.scala 577:17] + node _T_4843 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 580:37] + node _T_4844 = eq(obuf_cmd_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:52] + node _T_4845 = and(_T_4843, _T_4844) @[lsu_bus_buffer.scala 580:50] + node _T_4846 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:69] + node _T_4847 = and(_T_4845, _T_4846) @[lsu_bus_buffer.scala 580:67] + io.lsu_axi.aw.valid <= _T_4847 @[lsu_bus_buffer.scala 580:23] + io.lsu_axi.aw.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 581:25] + node _T_4848 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 582:75] + node _T_4849 = cat(_T_4848, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4850 = mux(obuf_sideeffect, obuf_addr, _T_4849) @[lsu_bus_buffer.scala 582:33] + io.lsu_axi.aw.bits.addr <= _T_4850 @[lsu_bus_buffer.scala 582:27] + node _T_4851 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4852 = mux(obuf_sideeffect, _T_4851, UInt<3>("h03")) @[lsu_bus_buffer.scala 583:33] + io.lsu_axi.aw.bits.size <= _T_4852 @[lsu_bus_buffer.scala 583:27] + io.lsu_axi.aw.bits.prot <= UInt<3>("h01") @[lsu_bus_buffer.scala 584:27] + node _T_4853 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 585:34] + io.lsu_axi.aw.bits.cache <= _T_4853 @[lsu_bus_buffer.scala 585:28] + node _T_4854 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 586:41] + io.lsu_axi.aw.bits.region <= _T_4854 @[lsu_bus_buffer.scala 586:29] + io.lsu_axi.aw.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 587:26] + io.lsu_axi.aw.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 588:28] + io.lsu_axi.aw.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 589:26] + io.lsu_axi.aw.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 590:27] + node _T_4855 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 592:36] + node _T_4856 = eq(obuf_data_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 592:51] + node _T_4857 = and(_T_4855, _T_4856) @[lsu_bus_buffer.scala 592:49] + node _T_4858 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 592:69] + node _T_4859 = and(_T_4857, _T_4858) @[lsu_bus_buffer.scala 592:67] + io.lsu_axi.w.valid <= _T_4859 @[lsu_bus_buffer.scala 592:22] + node _T_4860 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] + node _T_4861 = mux(_T_4860, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_4862 = and(obuf_byteen, _T_4861) @[lsu_bus_buffer.scala 593:41] + io.lsu_axi.w.bits.strb <= _T_4862 @[lsu_bus_buffer.scala 593:26] + io.lsu_axi.w.bits.data <= obuf_data @[lsu_bus_buffer.scala 594:26] + io.lsu_axi.w.bits.last <= UInt<1>("h01") @[lsu_bus_buffer.scala 595:26] + node _T_4863 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:39] + node _T_4864 = and(obuf_valid, _T_4863) @[lsu_bus_buffer.scala 597:37] + node _T_4865 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:53] + node _T_4866 = and(_T_4864, _T_4865) @[lsu_bus_buffer.scala 597:51] + node _T_4867 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:68] + node _T_4868 = and(_T_4866, _T_4867) @[lsu_bus_buffer.scala 597:66] + io.lsu_axi.ar.valid <= _T_4868 @[lsu_bus_buffer.scala 597:23] + io.lsu_axi.ar.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 598:25] + node _T_4869 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 599:75] + node _T_4870 = cat(_T_4869, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4871 = mux(obuf_sideeffect, obuf_addr, _T_4870) @[lsu_bus_buffer.scala 599:33] + io.lsu_axi.ar.bits.addr <= _T_4871 @[lsu_bus_buffer.scala 599:27] + node _T_4872 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4873 = mux(obuf_sideeffect, _T_4872, UInt<3>("h03")) @[lsu_bus_buffer.scala 600:33] + io.lsu_axi.ar.bits.size <= _T_4873 @[lsu_bus_buffer.scala 600:27] + io.lsu_axi.ar.bits.prot <= UInt<3>("h01") @[lsu_bus_buffer.scala 601:27] + node _T_4874 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 602:34] + io.lsu_axi.ar.bits.cache <= _T_4874 @[lsu_bus_buffer.scala 602:28] + node _T_4875 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 603:41] + io.lsu_axi.ar.bits.region <= _T_4875 @[lsu_bus_buffer.scala 603:29] + io.lsu_axi.ar.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 604:26] + io.lsu_axi.ar.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 605:28] + io.lsu_axi.ar.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 606:26] + io.lsu_axi.ar.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 607:27] + io.lsu_axi.b.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 608:22] + io.lsu_axi.r.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 609:22] + node _T_4876 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4877 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 610:137] + node _T_4878 = and(io.lsu_bus_clk_en_q, _T_4877) @[lsu_bus_buffer.scala 610:126] + node _T_4879 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 610:152] + node _T_4880 = and(_T_4878, _T_4879) @[lsu_bus_buffer.scala 610:141] + node _T_4881 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4882 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 610:137] + node _T_4883 = and(io.lsu_bus_clk_en_q, _T_4882) @[lsu_bus_buffer.scala 610:126] + node _T_4884 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 610:152] + node _T_4885 = and(_T_4883, _T_4884) @[lsu_bus_buffer.scala 610:141] + node _T_4886 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4887 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 610:137] + node _T_4888 = and(io.lsu_bus_clk_en_q, _T_4887) @[lsu_bus_buffer.scala 610:126] + node _T_4889 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 610:152] + node _T_4890 = and(_T_4888, _T_4889) @[lsu_bus_buffer.scala 610:141] + node _T_4891 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4892 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 610:137] + node _T_4893 = and(io.lsu_bus_clk_en_q, _T_4892) @[lsu_bus_buffer.scala 610:126] + node _T_4894 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 610:152] + node _T_4895 = and(_T_4893, _T_4894) @[lsu_bus_buffer.scala 610:141] + node _T_4896 = mux(_T_4876, _T_4880, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4897 = mux(_T_4881, _T_4885, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4898 = mux(_T_4886, _T_4890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4899 = mux(_T_4891, _T_4895, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4900 = or(_T_4896, _T_4897) @[Mux.scala 27:72] + node _T_4901 = or(_T_4900, _T_4898) @[Mux.scala 27:72] + node _T_4902 = or(_T_4901, _T_4899) @[Mux.scala 27:72] + wire _T_4903 : UInt<1> @[Mux.scala 27:72] + _T_4903 <= _T_4902 @[Mux.scala 27:72] + io.tlu_busbuff.lsu_imprecise_error_store_any <= _T_4903 @[lsu_bus_buffer.scala 610:48] + node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4905 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 611:104] + node _T_4906 = and(_T_4904, _T_4905) @[lsu_bus_buffer.scala 611:93] + node _T_4907 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 611:119] + node _T_4908 = and(_T_4906, _T_4907) @[lsu_bus_buffer.scala 611:108] + node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4910 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 611:104] + node _T_4911 = and(_T_4909, _T_4910) @[lsu_bus_buffer.scala 611:93] + node _T_4912 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 611:119] + node _T_4913 = and(_T_4911, _T_4912) @[lsu_bus_buffer.scala 611:108] + node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4915 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 611:104] + node _T_4916 = and(_T_4914, _T_4915) @[lsu_bus_buffer.scala 611:93] + node _T_4917 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 611:119] + node _T_4918 = and(_T_4916, _T_4917) @[lsu_bus_buffer.scala 611:108] + node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4920 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 611:104] + node _T_4921 = and(_T_4919, _T_4920) @[lsu_bus_buffer.scala 611:93] + node _T_4922 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 611:119] + node _T_4923 = and(_T_4921, _T_4922) @[lsu_bus_buffer.scala 611:108] + node _T_4924 = mux(_T_4908, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4925 = mux(_T_4913, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4926 = mux(_T_4918, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4927 = mux(_T_4923, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4928 = or(_T_4924, _T_4925) @[Mux.scala 27:72] + node _T_4929 = or(_T_4928, _T_4926) @[Mux.scala 27:72] + node _T_4930 = or(_T_4929, _T_4927) @[Mux.scala 27:72] + wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72] + lsu_imprecise_error_store_tag <= _T_4930 @[Mux.scala 27:72] + node _T_4931 = eq(io.tlu_busbuff.lsu_imprecise_error_store_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 613:97] + node _T_4932 = and(io.dctl_busbuff.lsu_nonblock_load_data_error, _T_4931) @[lsu_bus_buffer.scala 613:95] + io.tlu_busbuff.lsu_imprecise_error_load_any <= _T_4932 @[lsu_bus_buffer.scala 613:47] + node _T_4933 = mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.dctl_busbuff.lsu_nonblock_load_data_tag]) @[lsu_bus_buffer.scala 614:53] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= _T_4933 @[lsu_bus_buffer.scala 614:47] + node _T_4934 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 620:59] + node _T_4935 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 620:104] + node _T_4936 = or(_T_4934, _T_4935) @[lsu_bus_buffer.scala 620:82] + node _T_4937 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 620:149] + node _T_4938 = or(_T_4936, _T_4937) @[lsu_bus_buffer.scala 620:126] + io.tlu_busbuff.lsu_pmu_bus_trxn <= _T_4938 @[lsu_bus_buffer.scala 620:35] + node _T_4939 = and(io.lsu_busreq_r, io.ldst_dual_r) @[lsu_bus_buffer.scala 621:60] + node _T_4940 = and(_T_4939, io.lsu_commit_r) @[lsu_bus_buffer.scala 621:77] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= _T_4940 @[lsu_bus_buffer.scala 621:41] + node _T_4941 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[lsu_bus_buffer.scala 622:83] + io.tlu_busbuff.lsu_pmu_bus_error <= _T_4941 @[lsu_bus_buffer.scala 622:36] + node _T_4942 = eq(io.lsu_axi.aw.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:61] + node _T_4943 = and(io.lsu_axi.aw.valid, _T_4942) @[lsu_bus_buffer.scala 624:59] + node _T_4944 = eq(io.lsu_axi.w.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:107] + node _T_4945 = and(io.lsu_axi.w.valid, _T_4944) @[lsu_bus_buffer.scala 624:105] + node _T_4946 = or(_T_4943, _T_4945) @[lsu_bus_buffer.scala 624:83] + node _T_4947 = eq(io.lsu_axi.ar.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:153] + node _T_4948 = and(io.lsu_axi.ar.valid, _T_4947) @[lsu_bus_buffer.scala 624:151] + node _T_4949 = or(_T_4946, _T_4948) @[lsu_bus_buffer.scala 624:128] + io.tlu_busbuff.lsu_pmu_bus_busy <= _T_4949 @[lsu_bus_buffer.scala 624:35] + reg _T_4950 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 626:49] + _T_4950 <= WrPtr0_m @[lsu_bus_buffer.scala 626:49] + WrPtr0_r <= _T_4950 @[lsu_bus_buffer.scala 626:12] + reg _T_4951 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 627:49] + _T_4951 <= WrPtr1_m @[lsu_bus_buffer.scala 627:49] + WrPtr1_r <= _T_4951 @[lsu_bus_buffer.scala 627:12] + node _T_4952 = eq(io.flush_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 628:75] + node _T_4953 = and(io.lsu_busreq_m, _T_4952) @[lsu_bus_buffer.scala 628:73] + node _T_4954 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 628:89] + node _T_4955 = and(_T_4953, _T_4954) @[lsu_bus_buffer.scala 628:87] + reg _T_4956 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 628:56] + _T_4956 <= _T_4955 @[lsu_bus_buffer.scala 628:56] + io.lsu_busreq_r <= _T_4956 @[lsu_bus_buffer.scala 628:19] + reg _T_4957 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 629:66] + _T_4957 <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_buffer.scala 629:66] + lsu_nonblock_load_valid_r <= _T_4957 @[lsu_bus_buffer.scala 629:29] + + module lsu_bus_intf : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip clk_override : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip active_clk : Clock, flip lsu_busm_clk : Clock, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, bus_read_data_m : UInt<32>, lsu_nonblock_load_data : UInt<32>, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, flip lsu_bus_clk_en : UInt<1>} + + wire lsu_bus_clk_en_q : UInt<1> + lsu_bus_clk_en_q <= UInt<1>("h00") + wire ldst_byteen_m : UInt<4> + ldst_byteen_m <= UInt<1>("h00") + wire ldst_byteen_r : UInt<4> + ldst_byteen_r <= UInt<1>("h00") + wire ldst_byteen_ext_m : UInt<8> + ldst_byteen_ext_m <= UInt<1>("h00") + wire ldst_byteen_ext_r : UInt<8> + ldst_byteen_ext_r <= UInt<1>("h00") + wire ldst_byteen_hi_m : UInt<4> + ldst_byteen_hi_m <= UInt<1>("h00") + wire ldst_byteen_hi_r : UInt<4> + ldst_byteen_hi_r <= UInt<1>("h00") + wire ldst_byteen_lo_m : UInt<4> + ldst_byteen_lo_m <= UInt<1>("h00") + wire ldst_byteen_lo_r : UInt<4> + ldst_byteen_lo_r <= UInt<1>("h00") + wire is_sideeffects_r : UInt<1> + is_sideeffects_r <= UInt<1>("h00") + wire store_data_ext_r : UInt<64> + store_data_ext_r <= UInt<1>("h00") + wire store_data_hi_r : UInt<32> + store_data_hi_r <= UInt<1>("h00") + wire store_data_lo_r : UInt<32> + store_data_lo_r <= UInt<1>("h00") + wire addr_match_dw_lo_r_m : UInt<1> + addr_match_dw_lo_r_m <= UInt<1>("h00") + wire addr_match_word_lo_r_m : UInt<1> + addr_match_word_lo_r_m <= UInt<1>("h00") + wire no_word_merge_r : UInt<1> + no_word_merge_r <= UInt<1>("h00") + wire no_dword_merge_r : UInt<1> + no_dword_merge_r <= UInt<1>("h00") + wire ld_addr_rhit_lo_lo : UInt<1> + ld_addr_rhit_lo_lo <= UInt<1>("h00") + wire ld_addr_rhit_hi_lo : UInt<1> + ld_addr_rhit_hi_lo <= UInt<1>("h00") + wire ld_addr_rhit_lo_hi : UInt<1> + ld_addr_rhit_lo_hi <= UInt<1>("h00") + wire ld_addr_rhit_hi_hi : UInt<1> + ld_addr_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_rhit_lo_lo : UInt<4> + ld_byte_rhit_lo_lo <= UInt<1>("h00") + wire ld_byte_rhit_hi_lo : UInt<4> + ld_byte_rhit_hi_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo_hi : UInt<4> + ld_byte_rhit_lo_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi_hi : UInt<4> + ld_byte_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_hit_lo : UInt<4> + ld_byte_hit_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo : UInt<4> + ld_byte_rhit_lo <= UInt<1>("h00") + wire ld_byte_hit_hi : UInt<4> + ld_byte_hit_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi : UInt<4> + ld_byte_rhit_hi <= UInt<1>("h00") + wire ld_fwddata_rpipe_lo : UInt<32> + ld_fwddata_rpipe_lo <= UInt<1>("h00") + wire ld_fwddata_rpipe_hi : UInt<32> + ld_fwddata_rpipe_hi <= UInt<1>("h00") + wire ld_byte_hit_buf_lo : UInt<4> + ld_byte_hit_buf_lo <= UInt<1>("h00") + wire ld_byte_hit_buf_hi : UInt<4> + ld_byte_hit_buf_hi <= UInt<1>("h00") + wire ld_fwddata_buf_lo : UInt<32> + ld_fwddata_buf_lo <= UInt<1>("h00") + wire ld_fwddata_buf_hi : UInt<32> + ld_fwddata_buf_hi <= UInt<1>("h00") + wire ld_fwddata_lo : UInt<64> + ld_fwddata_lo <= UInt<1>("h00") + wire ld_fwddata_hi : UInt<64> + ld_fwddata_hi <= UInt<1>("h00") + wire ld_fwddata_m : UInt<64> + ld_fwddata_m <= UInt<1>("h00") + wire ld_full_hit_hi_m : UInt<1> + ld_full_hit_hi_m <= UInt<1>("h01") + wire ld_full_hit_lo_m : UInt<1> + ld_full_hit_lo_m <= UInt<1>("h01") + wire ld_full_hit_m : UInt<1> + ld_full_hit_m <= UInt<1>("h00") + inst bus_buffer of lsu_bus_buffer @[lsu_bus_intf.scala 100:39] + bus_buffer.clock <= clock + bus_buffer.reset <= reset + bus_buffer.io.scan_mode <= io.scan_mode @[lsu_bus_intf.scala 102:29] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_store_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_load_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_busy <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_error <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_error @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_trxn <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu_bus_intf.scala 103:18] + bus_buffer.io.clk_override <= io.clk_override @[lsu_bus_intf.scala 104:51] + bus_buffer.io.lsu_bus_obuf_c1_clken <= io.lsu_bus_obuf_c1_clken @[lsu_bus_intf.scala 105:51] + bus_buffer.io.lsu_busm_clken <= io.lsu_busm_clken @[lsu_bus_intf.scala 106:51] + bus_buffer.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu_bus_intf.scala 107:51] + bus_buffer.io.lsu_c2_r_clk <= io.lsu_c2_r_clk @[lsu_bus_intf.scala 108:51] + bus_buffer.io.lsu_bus_ibuf_c1_clk <= io.lsu_bus_ibuf_c1_clk @[lsu_bus_intf.scala 109:51] + bus_buffer.io.lsu_bus_obuf_c1_clk <= io.lsu_bus_obuf_c1_clk @[lsu_bus_intf.scala 110:51] + bus_buffer.io.lsu_bus_buf_c1_clk <= io.lsu_bus_buf_c1_clk @[lsu_bus_intf.scala 111:51] + bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[lsu_bus_intf.scala 112:51] + bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[lsu_bus_intf.scala 113:51] + bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu_bus_intf.scala 114:51] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.store <= io.lsu_pkt_m.bits.store @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.load <= io.lsu_pkt_m.bits.load @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.word <= io.lsu_pkt_m.bits.word @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.half <= io.lsu_pkt_m.bits.half @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.by <= io.lsu_pkt_m.bits.by @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_m <= io.lsu_pkt_r.bits.store_data_bypass_m @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.load_ldst_bypass_d <= io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_d <= io.lsu_pkt_r.bits.store_data_bypass_d @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.dma <= io.lsu_pkt_r.bits.dma @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.unsign <= io.lsu_pkt_r.bits.unsign @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.store <= io.lsu_pkt_r.bits.store @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.load <= io.lsu_pkt_r.bits.load @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.dword <= io.lsu_pkt_r.bits.dword @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.word <= io.lsu_pkt_r.bits.word @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.half <= io.lsu_pkt_r.bits.half @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.by <= io.lsu_pkt_r.bits.by @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.stack <= io.lsu_pkt_r.bits.stack @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.fast_int <= io.lsu_pkt_r.bits.fast_int @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[lsu_bus_intf.scala 121:51] + bus_buffer.io.end_addr_m <= io.end_addr_m @[lsu_bus_intf.scala 122:51] + bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[lsu_bus_intf.scala 123:51] + bus_buffer.io.end_addr_r <= io.end_addr_r @[lsu_bus_intf.scala 124:51] + bus_buffer.io.store_data_r <= io.store_data_r @[lsu_bus_intf.scala 125:51] + bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[lsu_bus_intf.scala 127:51] + bus_buffer.io.flush_m_up <= io.flush_m_up @[lsu_bus_intf.scala 128:51] + bus_buffer.io.flush_r <= io.flush_r @[lsu_bus_intf.scala 129:51] + bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[lsu_bus_intf.scala 130:51] + bus_buffer.io.lsu_axi.r.bits.last <= io.axi.r.bits.last @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.resp <= io.axi.r.bits.resp @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.data <= io.axi.r.bits.data @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.id <= io.axi.r.bits.id @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.valid <= io.axi.r.valid @[lsu_bus_intf.scala 131:51] + io.axi.r.ready <= bus_buffer.io.lsu_axi.r.ready @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.qos <= bus_buffer.io.lsu_axi.ar.bits.qos @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.prot <= bus_buffer.io.lsu_axi.ar.bits.prot @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.cache <= bus_buffer.io.lsu_axi.ar.bits.cache @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.lock <= bus_buffer.io.lsu_axi.ar.bits.lock @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.burst <= bus_buffer.io.lsu_axi.ar.bits.burst @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.size <= bus_buffer.io.lsu_axi.ar.bits.size @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.len <= bus_buffer.io.lsu_axi.ar.bits.len @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.region <= bus_buffer.io.lsu_axi.ar.bits.region @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.addr <= bus_buffer.io.lsu_axi.ar.bits.addr @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.id <= bus_buffer.io.lsu_axi.ar.bits.id @[lsu_bus_intf.scala 131:51] + io.axi.ar.valid <= bus_buffer.io.lsu_axi.ar.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.ar.ready <= io.axi.ar.ready @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.bits.id <= io.axi.b.bits.id @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.bits.resp <= io.axi.b.bits.resp @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.valid <= io.axi.b.valid @[lsu_bus_intf.scala 131:51] + io.axi.b.ready <= bus_buffer.io.lsu_axi.b.ready @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.last <= bus_buffer.io.lsu_axi.w.bits.last @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.strb <= bus_buffer.io.lsu_axi.w.bits.strb @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.data <= bus_buffer.io.lsu_axi.w.bits.data @[lsu_bus_intf.scala 131:51] + io.axi.w.valid <= bus_buffer.io.lsu_axi.w.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.w.ready <= io.axi.w.ready @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.qos <= bus_buffer.io.lsu_axi.aw.bits.qos @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.prot <= bus_buffer.io.lsu_axi.aw.bits.prot @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.cache <= bus_buffer.io.lsu_axi.aw.bits.cache @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.lock <= bus_buffer.io.lsu_axi.aw.bits.lock @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.burst <= bus_buffer.io.lsu_axi.aw.bits.burst @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.size <= bus_buffer.io.lsu_axi.aw.bits.size @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.len <= bus_buffer.io.lsu_axi.aw.bits.len @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.region <= bus_buffer.io.lsu_axi.aw.bits.region @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.addr <= bus_buffer.io.lsu_axi.aw.bits.addr @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.id <= bus_buffer.io.lsu_axi.aw.bits.id @[lsu_bus_intf.scala 131:51] + io.axi.aw.valid <= bus_buffer.io.lsu_axi.aw.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.aw.ready <= io.axi.aw.ready @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 132:51] + io.lsu_nonblock_load_data <= bus_buffer.io.lsu_nonblock_load_data @[lsu_bus_intf.scala 133:29] + io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[lsu_bus_intf.scala 134:38] + io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[lsu_bus_intf.scala 135:38] + io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[lsu_bus_intf.scala 136:38] + io.lsu_bus_buffer_empty_any <= bus_buffer.io.lsu_bus_buffer_empty_any @[lsu_bus_intf.scala 137:38] + ld_byte_hit_buf_lo <= bus_buffer.io.ld_byte_hit_buf_lo @[lsu_bus_intf.scala 139:38] + ld_byte_hit_buf_hi <= bus_buffer.io.ld_byte_hit_buf_hi @[lsu_bus_intf.scala 140:38] + ld_fwddata_buf_lo <= bus_buffer.io.ld_fwddata_buf_lo @[lsu_bus_intf.scala 141:38] + ld_fwddata_buf_hi <= bus_buffer.io.ld_fwddata_buf_hi @[lsu_bus_intf.scala 142:38] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_data_error <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_intf.scala 143:19] + bus_buffer.io.no_word_merge_r <= no_word_merge_r @[lsu_bus_intf.scala 144:51] + bus_buffer.io.no_dword_merge_r <= no_dword_merge_r @[lsu_bus_intf.scala 145:51] + bus_buffer.io.is_sideeffects_r <= is_sideeffects_r @[lsu_bus_intf.scala 146:51] + bus_buffer.io.ldst_dual_d <= io.ldst_dual_d @[lsu_bus_intf.scala 147:51] + bus_buffer.io.ldst_dual_m <= io.ldst_dual_m @[lsu_bus_intf.scala 148:51] + bus_buffer.io.ldst_dual_r <= io.ldst_dual_r @[lsu_bus_intf.scala 149:51] + bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[lsu_bus_intf.scala 150:51] + bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[lsu_bus_intf.scala 151:51] + bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[lsu_bus_intf.scala 152:51] + node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[lsu_bus_intf.scala 154:63] + node _T_1 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[lsu_bus_intf.scala 154:107] + node _T_2 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[lsu_bus_intf.scala 154:148] + node _T_3 = mux(_T, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4 = mux(_T_1, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_2, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = or(_T_3, _T_4) @[Mux.scala 27:72] + node _T_7 = or(_T_6, _T_5) @[Mux.scala 27:72] + wire _T_8 : UInt<4> @[Mux.scala 27:72] + _T_8 <= _T_7 @[Mux.scala 27:72] + ldst_byteen_m <= _T_8 @[lsu_bus_intf.scala 154:27] + node _T_9 = bits(io.lsu_addr_r, 31, 3) @[lsu_bus_intf.scala 155:44] + node _T_10 = bits(io.lsu_addr_m, 31, 3) @[lsu_bus_intf.scala 155:68] + node _T_11 = eq(_T_9, _T_10) @[lsu_bus_intf.scala 155:51] + addr_match_dw_lo_r_m <= _T_11 @[lsu_bus_intf.scala 155:27] + node _T_12 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_intf.scala 156:68] + node _T_13 = bits(io.lsu_addr_m, 2, 2) @[lsu_bus_intf.scala 156:85] + node _T_14 = xor(_T_12, _T_13) @[lsu_bus_intf.scala 156:71] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[lsu_bus_intf.scala 156:53] + node _T_16 = and(addr_match_dw_lo_r_m, _T_15) @[lsu_bus_intf.scala 156:51] + addr_match_word_lo_r_m <= _T_16 @[lsu_bus_intf.scala 156:27] + node _T_17 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 157:48] + node _T_18 = and(io.lsu_busreq_r, _T_17) @[lsu_bus_intf.scala 157:46] + node _T_19 = and(_T_18, io.lsu_busreq_m) @[lsu_bus_intf.scala 157:64] + node _T_20 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 157:110] + node _T_21 = or(io.lsu_pkt_m.bits.load, _T_20) @[lsu_bus_intf.scala 157:108] + node _T_22 = and(_T_19, _T_21) @[lsu_bus_intf.scala 157:82] + no_word_merge_r <= _T_22 @[lsu_bus_intf.scala 157:27] + node _T_23 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 158:48] + node _T_24 = and(io.lsu_busreq_r, _T_23) @[lsu_bus_intf.scala 158:46] + node _T_25 = and(_T_24, io.lsu_busreq_m) @[lsu_bus_intf.scala 158:64] + node _T_26 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 158:110] + node _T_27 = or(io.lsu_pkt_m.bits.load, _T_26) @[lsu_bus_intf.scala 158:108] + node _T_28 = and(_T_25, _T_27) @[lsu_bus_intf.scala 158:82] + no_dword_merge_r <= _T_28 @[lsu_bus_intf.scala 158:27] + node _T_29 = bits(ldst_byteen_m, 3, 0) @[lsu_bus_intf.scala 160:43] + node _T_30 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 160:65] + node _T_31 = dshl(_T_29, _T_30) @[lsu_bus_intf.scala 160:49] + ldst_byteen_ext_m <= _T_31 @[lsu_bus_intf.scala 160:27] + node _T_32 = bits(ldst_byteen_r, 3, 0) @[lsu_bus_intf.scala 161:43] + node _T_33 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 161:65] + node _T_34 = dshl(_T_32, _T_33) @[lsu_bus_intf.scala 161:49] + ldst_byteen_ext_r <= _T_34 @[lsu_bus_intf.scala 161:27] + node _T_35 = bits(io.store_data_r, 31, 0) @[lsu_bus_intf.scala 162:45] + node _T_36 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 162:72] + node _T_37 = cat(_T_36, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_38 = dshl(_T_35, _T_37) @[lsu_bus_intf.scala 162:52] + store_data_ext_r <= _T_38 @[lsu_bus_intf.scala 162:27] + node _T_39 = bits(ldst_byteen_ext_m, 7, 4) @[lsu_bus_intf.scala 163:47] + ldst_byteen_hi_m <= _T_39 @[lsu_bus_intf.scala 163:27] + node _T_40 = bits(ldst_byteen_ext_m, 3, 0) @[lsu_bus_intf.scala 164:47] + ldst_byteen_lo_m <= _T_40 @[lsu_bus_intf.scala 164:27] + node _T_41 = bits(ldst_byteen_ext_r, 7, 4) @[lsu_bus_intf.scala 165:47] + ldst_byteen_hi_r <= _T_41 @[lsu_bus_intf.scala 165:27] + node _T_42 = bits(ldst_byteen_ext_r, 3, 0) @[lsu_bus_intf.scala 166:47] + ldst_byteen_lo_r <= _T_42 @[lsu_bus_intf.scala 166:27] + node _T_43 = bits(store_data_ext_r, 63, 32) @[lsu_bus_intf.scala 168:46] + store_data_hi_r <= _T_43 @[lsu_bus_intf.scala 168:27] + node _T_44 = bits(store_data_ext_r, 31, 0) @[lsu_bus_intf.scala 169:46] + store_data_lo_r <= _T_44 @[lsu_bus_intf.scala 169:27] + node _T_45 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 170:44] + node _T_46 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 170:68] + node _T_47 = eq(_T_45, _T_46) @[lsu_bus_intf.scala 170:51] + node _T_48 = and(_T_47, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 170:76] + node _T_49 = and(_T_48, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 170:97] + node _T_50 = and(_T_49, io.lsu_busreq_m) @[lsu_bus_intf.scala 170:123] + ld_addr_rhit_lo_lo <= _T_50 @[lsu_bus_intf.scala 170:27] + node _T_51 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 171:44] + node _T_52 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 171:68] + node _T_53 = eq(_T_51, _T_52) @[lsu_bus_intf.scala 171:51] + node _T_54 = and(_T_53, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 171:76] + node _T_55 = and(_T_54, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 171:97] + node _T_56 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_intf.scala 171:123] + ld_addr_rhit_lo_hi <= _T_56 @[lsu_bus_intf.scala 171:27] + node _T_57 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 172:44] + node _T_58 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 172:68] + node _T_59 = eq(_T_57, _T_58) @[lsu_bus_intf.scala 172:51] + node _T_60 = and(_T_59, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 172:76] + node _T_61 = and(_T_60, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 172:97] + node _T_62 = and(_T_61, io.lsu_busreq_m) @[lsu_bus_intf.scala 172:123] + ld_addr_rhit_hi_lo <= _T_62 @[lsu_bus_intf.scala 172:27] + node _T_63 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 173:44] + node _T_64 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 173:68] + node _T_65 = eq(_T_63, _T_64) @[lsu_bus_intf.scala 173:51] + node _T_66 = and(_T_65, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 173:76] + node _T_67 = and(_T_66, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 173:97] + node _T_68 = and(_T_67, io.lsu_busreq_m) @[lsu_bus_intf.scala 173:123] + ld_addr_rhit_hi_hi <= _T_68 @[lsu_bus_intf.scala 173:27] + node _T_69 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 175:88] + node _T_70 = and(ld_addr_rhit_lo_lo, _T_69) @[lsu_bus_intf.scala 175:70] + node _T_71 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 175:110] + node _T_72 = and(_T_70, _T_71) @[lsu_bus_intf.scala 175:92] + node _T_73 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 175:88] + node _T_74 = and(ld_addr_rhit_lo_lo, _T_73) @[lsu_bus_intf.scala 175:70] + node _T_75 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 175:110] + node _T_76 = and(_T_74, _T_75) @[lsu_bus_intf.scala 175:92] + node _T_77 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 175:88] + node _T_78 = and(ld_addr_rhit_lo_lo, _T_77) @[lsu_bus_intf.scala 175:70] + node _T_79 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 175:110] + node _T_80 = and(_T_78, _T_79) @[lsu_bus_intf.scala 175:92] + node _T_81 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 175:88] + node _T_82 = and(ld_addr_rhit_lo_lo, _T_81) @[lsu_bus_intf.scala 175:70] + node _T_83 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 175:110] + node _T_84 = and(_T_82, _T_83) @[lsu_bus_intf.scala 175:92] + node _T_85 = cat(_T_84, _T_80) @[Cat.scala 29:58] + node _T_86 = cat(_T_85, _T_76) @[Cat.scala 29:58] + node _T_87 = cat(_T_86, _T_72) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_87 @[lsu_bus_intf.scala 175:27] + node _T_88 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 176:88] + node _T_89 = and(ld_addr_rhit_lo_hi, _T_88) @[lsu_bus_intf.scala 176:70] + node _T_90 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 176:110] + node _T_91 = and(_T_89, _T_90) @[lsu_bus_intf.scala 176:92] + node _T_92 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 176:88] + node _T_93 = and(ld_addr_rhit_lo_hi, _T_92) @[lsu_bus_intf.scala 176:70] + node _T_94 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 176:110] + node _T_95 = and(_T_93, _T_94) @[lsu_bus_intf.scala 176:92] + node _T_96 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 176:88] + node _T_97 = and(ld_addr_rhit_lo_hi, _T_96) @[lsu_bus_intf.scala 176:70] + node _T_98 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 176:110] + node _T_99 = and(_T_97, _T_98) @[lsu_bus_intf.scala 176:92] + node _T_100 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 176:88] + node _T_101 = and(ld_addr_rhit_lo_hi, _T_100) @[lsu_bus_intf.scala 176:70] + node _T_102 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 176:110] + node _T_103 = and(_T_101, _T_102) @[lsu_bus_intf.scala 176:92] + node _T_104 = cat(_T_103, _T_99) @[Cat.scala 29:58] + node _T_105 = cat(_T_104, _T_95) @[Cat.scala 29:58] + node _T_106 = cat(_T_105, _T_91) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_106 @[lsu_bus_intf.scala 176:27] + node _T_107 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 177:88] + node _T_108 = and(ld_addr_rhit_hi_lo, _T_107) @[lsu_bus_intf.scala 177:70] + node _T_109 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 177:110] + node _T_110 = and(_T_108, _T_109) @[lsu_bus_intf.scala 177:92] + node _T_111 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 177:88] + node _T_112 = and(ld_addr_rhit_hi_lo, _T_111) @[lsu_bus_intf.scala 177:70] + node _T_113 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 177:110] + node _T_114 = and(_T_112, _T_113) @[lsu_bus_intf.scala 177:92] + node _T_115 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 177:88] + node _T_116 = and(ld_addr_rhit_hi_lo, _T_115) @[lsu_bus_intf.scala 177:70] + node _T_117 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 177:110] + node _T_118 = and(_T_116, _T_117) @[lsu_bus_intf.scala 177:92] + node _T_119 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 177:88] + node _T_120 = and(ld_addr_rhit_hi_lo, _T_119) @[lsu_bus_intf.scala 177:70] + node _T_121 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 177:110] + node _T_122 = and(_T_120, _T_121) @[lsu_bus_intf.scala 177:92] + node _T_123 = cat(_T_122, _T_118) @[Cat.scala 29:58] + node _T_124 = cat(_T_123, _T_114) @[Cat.scala 29:58] + node _T_125 = cat(_T_124, _T_110) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_125 @[lsu_bus_intf.scala 177:27] + node _T_126 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 178:88] + node _T_127 = and(ld_addr_rhit_hi_hi, _T_126) @[lsu_bus_intf.scala 178:70] + node _T_128 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 178:110] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_intf.scala 178:92] + node _T_130 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 178:88] + node _T_131 = and(ld_addr_rhit_hi_hi, _T_130) @[lsu_bus_intf.scala 178:70] + node _T_132 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 178:110] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_intf.scala 178:92] + node _T_134 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 178:88] + node _T_135 = and(ld_addr_rhit_hi_hi, _T_134) @[lsu_bus_intf.scala 178:70] + node _T_136 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 178:110] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_intf.scala 178:92] + node _T_138 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 178:88] + node _T_139 = and(ld_addr_rhit_hi_hi, _T_138) @[lsu_bus_intf.scala 178:70] + node _T_140 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 178:110] + node _T_141 = and(_T_139, _T_140) @[lsu_bus_intf.scala 178:92] + node _T_142 = cat(_T_141, _T_137) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_133) @[Cat.scala 29:58] + node _T_144 = cat(_T_143, _T_129) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_144 @[lsu_bus_intf.scala 178:27] + node _T_145 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 180:69] + node _T_146 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 180:93] + node _T_147 = or(_T_145, _T_146) @[lsu_bus_intf.scala 180:73] + node _T_148 = bits(ld_byte_hit_buf_lo, 0, 0) @[lsu_bus_intf.scala 180:117] + node _T_149 = or(_T_147, _T_148) @[lsu_bus_intf.scala 180:97] + node _T_150 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 180:69] + node _T_151 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 180:93] + node _T_152 = or(_T_150, _T_151) @[lsu_bus_intf.scala 180:73] + node _T_153 = bits(ld_byte_hit_buf_lo, 1, 1) @[lsu_bus_intf.scala 180:117] + node _T_154 = or(_T_152, _T_153) @[lsu_bus_intf.scala 180:97] + node _T_155 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 180:69] + node _T_156 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 180:93] + node _T_157 = or(_T_155, _T_156) @[lsu_bus_intf.scala 180:73] + node _T_158 = bits(ld_byte_hit_buf_lo, 2, 2) @[lsu_bus_intf.scala 180:117] + node _T_159 = or(_T_157, _T_158) @[lsu_bus_intf.scala 180:97] + node _T_160 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 180:69] + node _T_161 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 180:93] + node _T_162 = or(_T_160, _T_161) @[lsu_bus_intf.scala 180:73] + node _T_163 = bits(ld_byte_hit_buf_lo, 3, 3) @[lsu_bus_intf.scala 180:117] + node _T_164 = or(_T_162, _T_163) @[lsu_bus_intf.scala 180:97] + node _T_165 = cat(_T_164, _T_159) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, _T_154) @[Cat.scala 29:58] + node _T_167 = cat(_T_166, _T_149) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_167 @[lsu_bus_intf.scala 180:27] + node _T_168 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 181:69] + node _T_169 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 181:93] + node _T_170 = or(_T_168, _T_169) @[lsu_bus_intf.scala 181:73] + node _T_171 = bits(ld_byte_hit_buf_hi, 0, 0) @[lsu_bus_intf.scala 181:117] + node _T_172 = or(_T_170, _T_171) @[lsu_bus_intf.scala 181:97] + node _T_173 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 181:69] + node _T_174 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 181:93] + node _T_175 = or(_T_173, _T_174) @[lsu_bus_intf.scala 181:73] + node _T_176 = bits(ld_byte_hit_buf_hi, 1, 1) @[lsu_bus_intf.scala 181:117] + node _T_177 = or(_T_175, _T_176) @[lsu_bus_intf.scala 181:97] + node _T_178 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 181:69] + node _T_179 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 181:93] + node _T_180 = or(_T_178, _T_179) @[lsu_bus_intf.scala 181:73] + node _T_181 = bits(ld_byte_hit_buf_hi, 2, 2) @[lsu_bus_intf.scala 181:117] + node _T_182 = or(_T_180, _T_181) @[lsu_bus_intf.scala 181:97] + node _T_183 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 181:69] + node _T_184 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 181:93] + node _T_185 = or(_T_183, _T_184) @[lsu_bus_intf.scala 181:73] + node _T_186 = bits(ld_byte_hit_buf_hi, 3, 3) @[lsu_bus_intf.scala 181:117] + node _T_187 = or(_T_185, _T_186) @[lsu_bus_intf.scala 181:97] + node _T_188 = cat(_T_187, _T_182) @[Cat.scala 29:58] + node _T_189 = cat(_T_188, _T_177) @[Cat.scala 29:58] + node _T_190 = cat(_T_189, _T_172) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_190 @[lsu_bus_intf.scala 181:27] + node _T_191 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 182:69] + node _T_192 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 182:93] + node _T_193 = or(_T_191, _T_192) @[lsu_bus_intf.scala 182:73] + node _T_194 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 182:69] + node _T_195 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 182:93] + node _T_196 = or(_T_194, _T_195) @[lsu_bus_intf.scala 182:73] + node _T_197 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 182:69] + node _T_198 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 182:93] + node _T_199 = or(_T_197, _T_198) @[lsu_bus_intf.scala 182:73] + node _T_200 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 182:69] + node _T_201 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 182:93] + node _T_202 = or(_T_200, _T_201) @[lsu_bus_intf.scala 182:73] + node _T_203 = cat(_T_202, _T_199) @[Cat.scala 29:58] + node _T_204 = cat(_T_203, _T_196) @[Cat.scala 29:58] + node _T_205 = cat(_T_204, _T_193) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_205 @[lsu_bus_intf.scala 182:27] + node _T_206 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 183:69] + node _T_207 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 183:93] + node _T_208 = or(_T_206, _T_207) @[lsu_bus_intf.scala 183:73] + node _T_209 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 183:69] + node _T_210 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 183:93] + node _T_211 = or(_T_209, _T_210) @[lsu_bus_intf.scala 183:73] + node _T_212 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 183:69] + node _T_213 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 183:93] + node _T_214 = or(_T_212, _T_213) @[lsu_bus_intf.scala 183:73] + node _T_215 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 183:69] + node _T_216 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 183:93] + node _T_217 = or(_T_215, _T_216) @[lsu_bus_intf.scala 183:73] + node _T_218 = cat(_T_217, _T_214) @[Cat.scala 29:58] + node _T_219 = cat(_T_218, _T_211) @[Cat.scala 29:58] + node _T_220 = cat(_T_219, _T_208) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_220 @[lsu_bus_intf.scala 183:27] + node _T_221 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 184:79] + node _T_222 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 184:101] + node _T_223 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 184:136] + node _T_224 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 184:158] + node _T_225 = mux(_T_221, _T_222, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_226 = mux(_T_223, _T_224, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_227 = or(_T_225, _T_226) @[Mux.scala 27:72] + wire _T_228 : UInt<8> @[Mux.scala 27:72] + _T_228 <= _T_227 @[Mux.scala 27:72] + node _T_229 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 184:79] + node _T_230 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 184:101] + node _T_231 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 184:136] + node _T_232 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 184:158] + node _T_233 = mux(_T_229, _T_230, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_234 = mux(_T_231, _T_232, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_235 = or(_T_233, _T_234) @[Mux.scala 27:72] + wire _T_236 : UInt<8> @[Mux.scala 27:72] + _T_236 <= _T_235 @[Mux.scala 27:72] + node _T_237 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 184:79] + node _T_238 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 184:101] + node _T_239 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 184:136] + node _T_240 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 184:158] + node _T_241 = mux(_T_237, _T_238, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_242 = mux(_T_239, _T_240, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_243 = or(_T_241, _T_242) @[Mux.scala 27:72] + wire _T_244 : UInt<8> @[Mux.scala 27:72] + _T_244 <= _T_243 @[Mux.scala 27:72] + node _T_245 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 184:79] + node _T_246 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 184:101] + node _T_247 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 184:136] + node _T_248 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 184:158] + node _T_249 = mux(_T_245, _T_246, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_250 = mux(_T_247, _T_248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_251 = or(_T_249, _T_250) @[Mux.scala 27:72] + wire _T_252 : UInt<8> @[Mux.scala 27:72] + _T_252 <= _T_251 @[Mux.scala 27:72] + node _T_253 = cat(_T_252, _T_244) @[Cat.scala 29:58] + node _T_254 = cat(_T_253, _T_236) @[Cat.scala 29:58] + node _T_255 = cat(_T_254, _T_228) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_255 @[lsu_bus_intf.scala 184:27] + node _T_256 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 185:79] + node _T_257 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 185:101] + node _T_258 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 185:136] + node _T_259 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 185:158] + node _T_260 = mux(_T_256, _T_257, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = or(_T_260, _T_261) @[Mux.scala 27:72] + wire _T_263 : UInt<8> @[Mux.scala 27:72] + _T_263 <= _T_262 @[Mux.scala 27:72] + node _T_264 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 185:79] + node _T_265 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 185:101] + node _T_266 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 185:136] + node _T_267 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 185:158] + node _T_268 = mux(_T_264, _T_265, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_269 = mux(_T_266, _T_267, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_270 = or(_T_268, _T_269) @[Mux.scala 27:72] + wire _T_271 : UInt<8> @[Mux.scala 27:72] + _T_271 <= _T_270 @[Mux.scala 27:72] + node _T_272 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 185:79] + node _T_273 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 185:101] + node _T_274 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 185:136] + node _T_275 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 185:158] + node _T_276 = mux(_T_272, _T_273, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_277 = mux(_T_274, _T_275, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_278 = or(_T_276, _T_277) @[Mux.scala 27:72] + wire _T_279 : UInt<8> @[Mux.scala 27:72] + _T_279 <= _T_278 @[Mux.scala 27:72] + node _T_280 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 185:79] + node _T_281 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 185:101] + node _T_282 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 185:136] + node _T_283 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 185:158] + node _T_284 = mux(_T_280, _T_281, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_285 = mux(_T_282, _T_283, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_286 = or(_T_284, _T_285) @[Mux.scala 27:72] + wire _T_287 : UInt<8> @[Mux.scala 27:72] + _T_287 <= _T_286 @[Mux.scala 27:72] + node _T_288 = cat(_T_287, _T_279) @[Cat.scala 29:58] + node _T_289 = cat(_T_288, _T_271) @[Cat.scala 29:58] + node _T_290 = cat(_T_289, _T_263) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_290 @[lsu_bus_intf.scala 185:27] + node _T_291 = bits(ld_byte_rhit_lo, 0, 0) @[lsu_bus_intf.scala 186:70] + node _T_292 = bits(ld_fwddata_rpipe_lo, 7, 0) @[lsu_bus_intf.scala 186:94] + node _T_293 = bits(ld_fwddata_buf_lo, 7, 0) @[lsu_bus_intf.scala 186:128] + node _T_294 = mux(_T_291, _T_292, _T_293) @[lsu_bus_intf.scala 186:54] + node _T_295 = bits(ld_byte_rhit_lo, 1, 1) @[lsu_bus_intf.scala 186:70] + node _T_296 = bits(ld_fwddata_rpipe_lo, 15, 8) @[lsu_bus_intf.scala 186:94] + node _T_297 = bits(ld_fwddata_buf_lo, 15, 8) @[lsu_bus_intf.scala 186:128] + node _T_298 = mux(_T_295, _T_296, _T_297) @[lsu_bus_intf.scala 186:54] + node _T_299 = bits(ld_byte_rhit_lo, 2, 2) @[lsu_bus_intf.scala 186:70] + node _T_300 = bits(ld_fwddata_rpipe_lo, 23, 16) @[lsu_bus_intf.scala 186:94] + node _T_301 = bits(ld_fwddata_buf_lo, 23, 16) @[lsu_bus_intf.scala 186:128] + node _T_302 = mux(_T_299, _T_300, _T_301) @[lsu_bus_intf.scala 186:54] + node _T_303 = bits(ld_byte_rhit_lo, 3, 3) @[lsu_bus_intf.scala 186:70] + node _T_304 = bits(ld_fwddata_rpipe_lo, 31, 24) @[lsu_bus_intf.scala 186:94] + node _T_305 = bits(ld_fwddata_buf_lo, 31, 24) @[lsu_bus_intf.scala 186:128] + node _T_306 = mux(_T_303, _T_304, _T_305) @[lsu_bus_intf.scala 186:54] + node _T_307 = cat(_T_306, _T_302) @[Cat.scala 29:58] + node _T_308 = cat(_T_307, _T_298) @[Cat.scala 29:58] + node _T_309 = cat(_T_308, _T_294) @[Cat.scala 29:58] + ld_fwddata_lo <= _T_309 @[lsu_bus_intf.scala 186:27] + node _T_310 = bits(ld_byte_rhit_hi, 0, 0) @[lsu_bus_intf.scala 187:70] + node _T_311 = bits(ld_fwddata_rpipe_hi, 7, 0) @[lsu_bus_intf.scala 187:94] + node _T_312 = bits(ld_fwddata_buf_hi, 7, 0) @[lsu_bus_intf.scala 187:128] + node _T_313 = mux(_T_310, _T_311, _T_312) @[lsu_bus_intf.scala 187:54] + node _T_314 = bits(ld_byte_rhit_hi, 1, 1) @[lsu_bus_intf.scala 187:70] + node _T_315 = bits(ld_fwddata_rpipe_hi, 15, 8) @[lsu_bus_intf.scala 187:94] + node _T_316 = bits(ld_fwddata_buf_hi, 15, 8) @[lsu_bus_intf.scala 187:128] + node _T_317 = mux(_T_314, _T_315, _T_316) @[lsu_bus_intf.scala 187:54] + node _T_318 = bits(ld_byte_rhit_hi, 2, 2) @[lsu_bus_intf.scala 187:70] + node _T_319 = bits(ld_fwddata_rpipe_hi, 23, 16) @[lsu_bus_intf.scala 187:94] + node _T_320 = bits(ld_fwddata_buf_hi, 23, 16) @[lsu_bus_intf.scala 187:128] + node _T_321 = mux(_T_318, _T_319, _T_320) @[lsu_bus_intf.scala 187:54] + node _T_322 = bits(ld_byte_rhit_hi, 3, 3) @[lsu_bus_intf.scala 187:70] + node _T_323 = bits(ld_fwddata_rpipe_hi, 31, 24) @[lsu_bus_intf.scala 187:94] + node _T_324 = bits(ld_fwddata_buf_hi, 31, 24) @[lsu_bus_intf.scala 187:128] + node _T_325 = mux(_T_322, _T_323, _T_324) @[lsu_bus_intf.scala 187:54] + node _T_326 = cat(_T_325, _T_321) @[Cat.scala 29:58] + node _T_327 = cat(_T_326, _T_317) @[Cat.scala 29:58] + node _T_328 = cat(_T_327, _T_313) @[Cat.scala 29:58] + ld_fwddata_hi <= _T_328 @[lsu_bus_intf.scala 187:27] + node _T_329 = bits(ld_byte_hit_lo, 0, 0) @[lsu_bus_intf.scala 188:66] + node _T_330 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 188:89] + node _T_331 = eq(_T_330, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_332 = or(_T_329, _T_331) @[lsu_bus_intf.scala 188:70] + node _T_333 = bits(ld_byte_hit_lo, 1, 1) @[lsu_bus_intf.scala 188:66] + node _T_334 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 188:89] + node _T_335 = eq(_T_334, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_336 = or(_T_333, _T_335) @[lsu_bus_intf.scala 188:70] + node _T_337 = bits(ld_byte_hit_lo, 2, 2) @[lsu_bus_intf.scala 188:66] + node _T_338 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 188:89] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_340 = or(_T_337, _T_339) @[lsu_bus_intf.scala 188:70] + node _T_341 = bits(ld_byte_hit_lo, 3, 3) @[lsu_bus_intf.scala 188:66] + node _T_342 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 188:89] + node _T_343 = eq(_T_342, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_344 = or(_T_341, _T_343) @[lsu_bus_intf.scala 188:70] + node _T_345 = and(_T_332, _T_336) @[lsu_bus_intf.scala 188:111] + node _T_346 = and(_T_345, _T_340) @[lsu_bus_intf.scala 188:111] + node _T_347 = and(_T_346, _T_344) @[lsu_bus_intf.scala 188:111] + ld_full_hit_lo_m <= _T_347 @[lsu_bus_intf.scala 188:27] + node _T_348 = bits(ld_byte_hit_hi, 0, 0) @[lsu_bus_intf.scala 189:66] + node _T_349 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 189:89] + node _T_350 = eq(_T_349, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_351 = or(_T_348, _T_350) @[lsu_bus_intf.scala 189:70] + node _T_352 = bits(ld_byte_hit_hi, 1, 1) @[lsu_bus_intf.scala 189:66] + node _T_353 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 189:89] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_355 = or(_T_352, _T_354) @[lsu_bus_intf.scala 189:70] + node _T_356 = bits(ld_byte_hit_hi, 2, 2) @[lsu_bus_intf.scala 189:66] + node _T_357 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 189:89] + node _T_358 = eq(_T_357, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_359 = or(_T_356, _T_358) @[lsu_bus_intf.scala 189:70] + node _T_360 = bits(ld_byte_hit_hi, 3, 3) @[lsu_bus_intf.scala 189:66] + node _T_361 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 189:89] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_363 = or(_T_360, _T_362) @[lsu_bus_intf.scala 189:70] + node _T_364 = and(_T_351, _T_355) @[lsu_bus_intf.scala 189:111] + node _T_365 = and(_T_364, _T_359) @[lsu_bus_intf.scala 189:111] + node _T_366 = and(_T_365, _T_363) @[lsu_bus_intf.scala 189:111] + ld_full_hit_hi_m <= _T_366 @[lsu_bus_intf.scala 189:27] + node _T_367 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[lsu_bus_intf.scala 190:47] + node _T_368 = and(_T_367, io.lsu_busreq_m) @[lsu_bus_intf.scala 190:66] + node _T_369 = and(_T_368, io.lsu_pkt_m.bits.load) @[lsu_bus_intf.scala 190:84] + node _T_370 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[lsu_bus_intf.scala 190:111] + node _T_371 = and(_T_369, _T_370) @[lsu_bus_intf.scala 190:109] + ld_full_hit_m <= _T_371 @[lsu_bus_intf.scala 190:27] + node _T_372 = bits(ld_fwddata_hi, 31, 0) @[lsu_bus_intf.scala 191:47] + node _T_373 = bits(ld_fwddata_lo, 31, 0) @[lsu_bus_intf.scala 191:68] + node _T_374 = cat(_T_372, _T_373) @[Cat.scala 29:58] + node _T_375 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 191:97] + node _T_376 = mul(UInt<4>("h08"), _T_375) @[lsu_bus_intf.scala 191:83] + node _T_377 = dshr(_T_374, _T_376) @[lsu_bus_intf.scala 191:76] + ld_fwddata_m <= _T_377 @[lsu_bus_intf.scala 191:27] + node _T_378 = bits(ld_fwddata_m, 31, 0) @[lsu_bus_intf.scala 192:42] + io.bus_read_data_m <= _T_378 @[lsu_bus_intf.scala 192:27] + reg _T_379 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 195:32] + _T_379 <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 195:32] + lsu_bus_clk_en_q <= _T_379 @[lsu_bus_intf.scala 195:22] + reg _T_380 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 199:33] + _T_380 <= io.is_sideeffects_m @[lsu_bus_intf.scala 199:33] + is_sideeffects_r <= _T_380 @[lsu_bus_intf.scala 199:23] + reg _T_381 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<4>("h00"))) @[lsu_bus_intf.scala 200:33] + _T_381 <= ldst_byteen_m @[lsu_bus_intf.scala 200:33] + ldst_byteen_r <= _T_381 @[lsu_bus_intf.scala 200:23] + + module lsu : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>}, lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_active : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_pmu_misaligned_m : UInt<1>, lsu_trigger_match_m : UInt<4>, flip lsu_bus_clk_en : UInt<1>, flip scan_mode : UInt<1>, flip active_clk : Clock, lsu_nonblock_load_data : UInt<32>} + + wire dma_dccm_wdata : UInt<64> + dma_dccm_wdata <= UInt<64>("h00") + wire dma_dccm_wdata_lo : UInt<32> + dma_dccm_wdata_lo <= UInt<32>("h00") + wire dma_dccm_wdata_hi : UInt<32> + dma_dccm_wdata_hi <= UInt<32>("h00") + wire dma_mem_tag_m : UInt<3> + dma_mem_tag_m <= UInt<3>("h00") + wire lsu_raw_fwd_lo_r : UInt<1> + lsu_raw_fwd_lo_r <= UInt<1>("h00") + wire lsu_raw_fwd_hi_r : UInt<1> + lsu_raw_fwd_hi_r <= UInt<1>("h00") + wire lsu_busm_clken : UInt<1> + lsu_busm_clken <= UInt<1>("h00") + wire lsu_bus_obuf_c1_clken : UInt<1> + lsu_bus_obuf_c1_clken <= UInt<1>("h00") + wire lsu_busreq_r : UInt<1> + lsu_busreq_r <= UInt<1>("h00") + inst lsu_lsc_ctl of lsu_lsc_ctl @[lsu.scala 72:30] + lsu_lsc_ctl.clock <= clock + lsu_lsc_ctl.reset <= reset + io.lsu_result_corr_r <= lsu_lsc_ctl.io.lsu_result_corr_r @[lsu.scala 75:24] + inst dccm_ctl of lsu_dccm_ctl @[lsu.scala 76:30] + dccm_ctl.clock <= clock + dccm_ctl.reset <= reset + inst stbuf of lsu_stbuf @[lsu.scala 77:30] + stbuf.clock <= clock + stbuf.reset <= reset + inst ecc of lsu_ecc @[lsu.scala 78:30] + ecc.clock <= clock + ecc.reset <= reset + inst trigger of lsu_trigger @[lsu.scala 79:30] + trigger.clock <= clock + trigger.reset <= reset + inst clkdomain of lsu_clkdomain @[lsu.scala 80:30] + clkdomain.clock <= clock + clkdomain.reset <= reset + inst bus_intf of lsu_bus_intf @[lsu.scala 81:30] + bus_intf.clock <= clock + bus_intf.reset <= reset + node lsu_raw_fwd_lo_m = orr(stbuf.io.stbuf_fwdbyteen_lo_m) @[lsu.scala 83:56] + node lsu_raw_fwd_hi_m = orr(stbuf.io.stbuf_fwdbyteen_hi_m) @[lsu.scala 84:56] + node _T = or(stbuf.io.lsu_stbuf_full_any, bus_intf.io.lsu_bus_buffer_full_any) @[lsu.scala 87:57] + node _T_1 = or(_T, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 87:95] + io.lsu_store_stall_any <= _T_1 @[lsu.scala 87:26] + node _T_2 = or(bus_intf.io.lsu_bus_buffer_full_any, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 88:64] + io.lsu_load_stall_any <= _T_2 @[lsu.scala 88:25] + io.lsu_fastint_stall_any <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 89:28] + node _T_3 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 94:58] + node _T_4 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_3) @[lsu.scala 94:56] + node _T_5 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 94:126] + node _T_6 = and(_T_4, _T_5) @[lsu.scala 94:93] + node ldst_nodma_mtor = and(_T_6, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 94:158] + node _T_7 = or(io.dec_lsu_valid_raw_d, ldst_nodma_mtor) @[lsu.scala 95:53] + node _T_8 = or(_T_7, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 95:71] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[lsu.scala 95:28] + io.lsu_dma.dccm_ready <= _T_9 @[lsu.scala 95:25] + node _T_10 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 96:58] + node _T_11 = and(_T_10, lsu_lsc_ctl.io.addr_in_dccm_d) @[lsu.scala 96:97] + node _T_12 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_sz, 1, 1) @[lsu.scala 96:164] + node dma_dccm_wen = and(_T_11, _T_12) @[lsu.scala 96:129] + node _T_13 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 97:58] + node dma_pic_wen = and(_T_13, lsu_lsc_ctl.io.addr_in_pic_d) @[lsu.scala 97:97] + node _T_14 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu.scala 98:100] + node _T_15 = cat(_T_14, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_16 = dshr(io.lsu_dma.dma_lsc_ctl.dma_mem_wdata, _T_15) @[lsu.scala 98:58] + dma_dccm_wdata <= _T_16 @[lsu.scala 98:18] + node _T_17 = bits(dma_dccm_wdata, 63, 32) @[lsu.scala 99:38] + dma_dccm_wdata_hi <= _T_17 @[lsu.scala 99:21] + node _T_18 = bits(dma_dccm_wdata, 31, 0) @[lsu.scala 100:38] + dma_dccm_wdata_lo <= _T_18 @[lsu.scala 100:21] + node _T_19 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 109:58] + node _T_20 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_19) @[lsu.scala 109:56] + node _T_21 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 109:130] + node _T_22 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, _T_21) @[lsu.scala 109:128] + node _T_23 = or(_T_20, _T_22) @[lsu.scala 109:94] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[lsu.scala 109:22] + node _T_25 = and(_T_24, bus_intf.io.lsu_bus_buffer_empty_any) @[lsu.scala 109:167] + io.lsu_idle_any <= _T_25 @[lsu.scala 109:19] + node _T_26 = or(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_r.valid) @[lsu.scala 110:53] + node _T_27 = or(_T_26, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 110:86] + node _T_28 = eq(bus_intf.io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu.scala 110:128] + node _T_29 = or(_T_27, _T_28) @[lsu.scala 110:126] + io.lsu_active <= _T_29 @[lsu.scala 110:18] + node _T_30 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, lsu_lsc_ctl.io.lsu_pkt_r.bits.store) @[lsu.scala 112:61] + node _T_31 = and(_T_30, lsu_lsc_ctl.io.addr_in_dccm_r) @[lsu.scala 112:99] + node _T_32 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[lsu.scala 112:133] + node _T_33 = and(_T_31, _T_32) @[lsu.scala 112:131] + node _T_34 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 112:145] + node _T_35 = or(lsu_lsc_ctl.io.lsu_pkt_r.bits.by, lsu_lsc_ctl.io.lsu_pkt_r.bits.half) @[lsu.scala 112:217] + node _T_36 = eq(ecc.io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu.scala 112:257] + node _T_37 = and(_T_35, _T_36) @[lsu.scala 112:255] + node _T_38 = or(_T_34, _T_37) @[lsu.scala 112:180] + node store_stbuf_reqvld_r = and(_T_33, _T_38) @[lsu.scala 112:142] + node _T_39 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 114:90] + node _T_40 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_39) @[lsu.scala 114:52] + node _T_41 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 114:162] + node lsu_cmpen_m = and(_T_40, _T_41) @[lsu.scala 114:129] + node _T_42 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 116:92] + node _T_43 = and(_T_42, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 116:131] + node _T_44 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_43) @[lsu.scala 116:53] + node _T_45 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[lsu.scala 116:167] + node _T_46 = and(_T_44, _T_45) @[lsu.scala 116:165] + node _T_47 = eq(lsu_lsc_ctl.io.lsu_exc_m, UInt<1>("h00")) @[lsu.scala 116:181] + node _T_48 = and(_T_46, _T_47) @[lsu.scala 116:179] + node _T_49 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu.scala 116:209] + node lsu_busreq_m = and(_T_48, _T_49) @[lsu.scala 116:207] + node _T_50 = bits(lsu_lsc_ctl.io.lsu_addr_m, 0, 0) @[lsu.scala 120:127] + node _T_51 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.half, _T_50) @[lsu.scala 120:100] + node _T_52 = bits(lsu_lsc_ctl.io.lsu_addr_m, 1, 0) @[lsu.scala 120:197] + node _T_53 = orr(_T_52) @[lsu.scala 120:203] + node _T_54 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.word, _T_53) @[lsu.scala 120:170] + node _T_55 = or(_T_51, _T_54) @[lsu.scala 120:132] + node _T_56 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_55) @[lsu.scala 120:61] + io.lsu_pmu_misaligned_m <= _T_56 @[lsu.scala 120:27] + node _T_57 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.load) @[lsu.scala 121:73] + node _T_58 = and(_T_57, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 121:110] + io.lsu_tlu.lsu_pmu_load_external_m <= _T_58 @[lsu.scala 121:39] + node _T_59 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 122:73] + node _T_60 = and(_T_59, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 122:111] + io.lsu_tlu.lsu_pmu_store_external_m <= _T_60 @[lsu.scala 122:39] + lsu_lsc_ctl.io.clk_override <= io.clk_override @[lsu.scala 126:46] + lsu_lsc_ctl.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[lsu.scala 127:46] + lsu_lsc_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 128:46] + lsu_lsc_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[lsu.scala 129:46] + lsu_lsc_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 130:46] + lsu_lsc_ctl.io.lsu_store_c1_m_clk <= clkdomain.io.lsu_store_c1_m_clk @[lsu.scala 131:46] + lsu_lsc_ctl.io.lsu_ld_data_r <= dccm_ctl.io.lsu_ld_data_r @[lsu.scala 132:46] + lsu_lsc_ctl.io.lsu_ld_data_corr_r <= dccm_ctl.io.lsu_ld_data_corr_r @[lsu.scala 133:46] + lsu_lsc_ctl.io.lsu_single_ecc_error_r <= ecc.io.lsu_single_ecc_error_r @[lsu.scala 134:46] + lsu_lsc_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[lsu.scala 135:46] + lsu_lsc_ctl.io.lsu_ld_data_m <= dccm_ctl.io.lsu_ld_data_m @[lsu.scala 136:46] + lsu_lsc_ctl.io.lsu_single_ecc_error_m <= ecc.io.lsu_single_ecc_error_m @[lsu.scala 137:46] + lsu_lsc_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[lsu.scala 138:46] + lsu_lsc_ctl.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 139:46] + lsu_lsc_ctl.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 140:46] + node _T_61 = bits(lsu_lsc_ctl.io.lsu_addr_d, 2, 2) @[lsu.scala 141:74] + node _T_62 = bits(lsu_lsc_ctl.io.end_addr_d, 2, 2) @[lsu.scala 141:107] + node _T_63 = neq(_T_61, _T_62) @[lsu.scala 141:78] + lsu_lsc_ctl.io.ldst_dual_d <= _T_63 @[lsu.scala 141:46] + node _T_64 = bits(lsu_lsc_ctl.io.lsu_addr_m, 2, 2) @[lsu.scala 142:74] + node _T_65 = bits(lsu_lsc_ctl.io.end_addr_m, 2, 2) @[lsu.scala 142:107] + node _T_66 = neq(_T_64, _T_65) @[lsu.scala 142:78] + lsu_lsc_ctl.io.ldst_dual_m <= _T_66 @[lsu.scala 142:46] + node _T_67 = bits(lsu_lsc_ctl.io.lsu_addr_r, 2, 2) @[lsu.scala 143:74] + node _T_68 = bits(lsu_lsc_ctl.io.end_addr_r, 2, 2) @[lsu.scala 143:107] + node _T_69 = neq(_T_67, _T_68) @[lsu.scala 143:78] + lsu_lsc_ctl.io.ldst_dual_r <= _T_69 @[lsu.scala 143:46] + io.lsu_exu.lsu_result_m <= lsu_lsc_ctl.io.lsu_exu.lsu_result_m @[lsu.scala 144:46] + lsu_lsc_ctl.io.lsu_exu.exu_lsu_rs2_d <= io.lsu_exu.exu_lsu_rs2_d @[lsu.scala 144:46] + lsu_lsc_ctl.io.lsu_exu.exu_lsu_rs1_d <= io.lsu_exu.exu_lsu_rs1_d @[lsu.scala 144:46] + lsu_lsc_ctl.io.lsu_p.bits.store_data_bypass_m <= io.lsu_p.bits.store_data_bypass_m @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.load_ldst_bypass_d <= io.lsu_p.bits.load_ldst_bypass_d @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.store_data_bypass_d <= io.lsu_p.bits.store_data_bypass_d @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.dma <= io.lsu_p.bits.dma @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.unsign <= io.lsu_p.bits.unsign @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.store <= io.lsu_p.bits.store @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.load <= io.lsu_p.bits.load @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.dword <= io.lsu_p.bits.dword @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.word <= io.lsu_p.bits.word @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.half <= io.lsu_p.bits.half @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.by <= io.lsu_p.bits.by @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.stack <= io.lsu_p.bits.stack @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.bits.fast_int <= io.lsu_p.bits.fast_int @[lsu.scala 145:46] + lsu_lsc_ctl.io.lsu_p.valid <= io.lsu_p.valid @[lsu.scala 145:46] + lsu_lsc_ctl.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 146:46] + lsu_lsc_ctl.io.dec_lsu_offset_d <= io.dec_lsu_offset_d @[lsu.scala 147:46] + lsu_lsc_ctl.io.picm_mask_data_m <= dccm_ctl.io.picm_mask_data_m @[lsu.scala 148:46] + lsu_lsc_ctl.io.bus_read_data_m <= bus_intf.io.bus_read_data_m @[lsu.scala 149:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[lsu.scala 150:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[lsu.scala 150:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[lsu.scala 150:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[lsu.scala 150:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_dccm_req <= io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[lsu.scala 150:46] + lsu_lsc_ctl.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu.scala 151:46] + lsu_lsc_ctl.io.scan_mode <= io.scan_mode @[lsu.scala 152:46] + io.lsu_single_ecc_error_incr <= lsu_lsc_ctl.io.lsu_single_ecc_error_incr @[lsu.scala 160:49] + io.lsu_error_pkt_r.bits.addr <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.addr @[lsu.scala 161:49] + io.lsu_error_pkt_r.bits.mscause <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.mscause @[lsu.scala 161:49] + io.lsu_error_pkt_r.bits.exc_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.exc_type @[lsu.scala 161:49] + io.lsu_error_pkt_r.bits.inst_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.inst_type @[lsu.scala 161:49] + io.lsu_error_pkt_r.bits.single_ecc_error <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.single_ecc_error @[lsu.scala 161:49] + io.lsu_error_pkt_r.valid <= lsu_lsc_ctl.io.lsu_error_pkt_r.valid @[lsu.scala 161:49] + io.lsu_fir_addr <= lsu_lsc_ctl.io.lsu_fir_addr @[lsu.scala 162:49] + io.lsu_fir_error <= lsu_lsc_ctl.io.lsu_fir_error @[lsu.scala 163:49] + dccm_ctl.io.clk_override <= io.clk_override @[lsu.scala 166:46] + node _T_70 = bits(lsu_lsc_ctl.io.lsu_addr_m, 2, 2) @[lsu.scala 167:74] + node _T_71 = bits(lsu_lsc_ctl.io.end_addr_m, 2, 2) @[lsu.scala 167:107] + node _T_72 = neq(_T_70, _T_71) @[lsu.scala 167:78] + dccm_ctl.io.ldst_dual_m <= _T_72 @[lsu.scala 167:46] + node _T_73 = bits(lsu_lsc_ctl.io.lsu_addr_r, 2, 2) @[lsu.scala 168:74] + node _T_74 = bits(lsu_lsc_ctl.io.end_addr_r, 2, 2) @[lsu.scala 168:107] + node _T_75 = neq(_T_73, _T_74) @[lsu.scala 168:78] + dccm_ctl.io.ldst_dual_r <= _T_75 @[lsu.scala 168:46] + dccm_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[lsu.scala 169:46] + dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 170:46] + dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 171:46] + dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 172:46] + dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_store_c1_r_clk @[lsu.scala 173:46] + dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dma @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.bits.unsign @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.store <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.load <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dword @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.word <= lsu_lsc_ctl.io.lsu_pkt_d.bits.word @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.half <= lsu_lsc_ctl.io.lsu_pkt_d.bits.half @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.by <= lsu_lsc_ctl.io.lsu_pkt_d.bits.by @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_d.bits.stack @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.bits.fast_int @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[lsu.scala 174:46] + dccm_ctl.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 175:46] + dccm_ctl.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 176:46] + dccm_ctl.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 176:46] + dccm_ctl.io.addr_in_dccm_d <= lsu_lsc_ctl.io.addr_in_dccm_d @[lsu.scala 177:46] + dccm_ctl.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 178:46] + dccm_ctl.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 179:46] + dccm_ctl.io.addr_in_pic_d <= lsu_lsc_ctl.io.addr_in_pic_d @[lsu.scala 180:46] + dccm_ctl.io.addr_in_pic_m <= lsu_lsc_ctl.io.addr_in_pic_m @[lsu.scala 181:46] + dccm_ctl.io.addr_in_pic_r <= lsu_lsc_ctl.io.addr_in_pic_r @[lsu.scala 182:46] + dccm_ctl.io.lsu_raw_fwd_lo_r <= lsu_raw_fwd_lo_r @[lsu.scala 183:46] + dccm_ctl.io.lsu_raw_fwd_hi_r <= lsu_raw_fwd_hi_r @[lsu.scala 184:46] + dccm_ctl.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 185:46] + dccm_ctl.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 186:46] + node _T_76 = bits(lsu_lsc_ctl.io.lsu_addr_m, 15, 0) @[lsu.scala 187:74] + dccm_ctl.io.lsu_addr_m <= _T_76 @[lsu.scala 187:46] + dccm_ctl.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 188:46] + node _T_77 = bits(lsu_lsc_ctl.io.end_addr_d, 15, 0) @[lsu.scala 189:74] + dccm_ctl.io.end_addr_d <= _T_77 @[lsu.scala 189:46] + node _T_78 = bits(lsu_lsc_ctl.io.end_addr_m, 15, 0) @[lsu.scala 190:74] + dccm_ctl.io.end_addr_m <= _T_78 @[lsu.scala 190:46] + node _T_79 = bits(lsu_lsc_ctl.io.end_addr_r, 15, 0) @[lsu.scala 191:74] + dccm_ctl.io.end_addr_r <= _T_79 @[lsu.scala 191:46] + dccm_ctl.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 192:46] + dccm_ctl.io.stbuf_addr_any <= stbuf.io.stbuf_addr_any @[lsu.scala 193:46] + dccm_ctl.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 194:46] + dccm_ctl.io.stbuf_ecc_any <= ecc.io.stbuf_ecc_any @[lsu.scala 195:46] + dccm_ctl.io.stbuf_fwddata_hi_m <= stbuf.io.stbuf_fwddata_hi_m @[lsu.scala 196:46] + dccm_ctl.io.stbuf_fwddata_lo_m <= stbuf.io.stbuf_fwddata_lo_m @[lsu.scala 197:46] + dccm_ctl.io.stbuf_fwdbyteen_lo_m <= stbuf.io.stbuf_fwdbyteen_lo_m @[lsu.scala 198:46] + dccm_ctl.io.stbuf_fwdbyteen_hi_m <= stbuf.io.stbuf_fwdbyteen_hi_m @[lsu.scala 199:46] + dccm_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[lsu.scala 200:46] + dccm_ctl.io.single_ecc_error_hi_r <= ecc.io.single_ecc_error_hi_r @[lsu.scala 201:46] + dccm_ctl.io.single_ecc_error_lo_r <= ecc.io.single_ecc_error_lo_r @[lsu.scala 202:46] + dccm_ctl.io.sec_data_hi_r <= ecc.io.sec_data_hi_r @[lsu.scala 203:46] + dccm_ctl.io.sec_data_lo_r <= ecc.io.sec_data_lo_r @[lsu.scala 204:46] + dccm_ctl.io.sec_data_hi_r_ff <= ecc.io.sec_data_hi_r_ff @[lsu.scala 205:46] + dccm_ctl.io.sec_data_lo_r_ff <= ecc.io.sec_data_lo_r_ff @[lsu.scala 206:46] + dccm_ctl.io.sec_data_ecc_hi_r_ff <= ecc.io.sec_data_ecc_hi_r_ff @[lsu.scala 207:46] + dccm_ctl.io.sec_data_ecc_lo_r_ff <= ecc.io.sec_data_ecc_lo_r_ff @[lsu.scala 208:46] + dccm_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[lsu.scala 209:46] + dccm_ctl.io.sec_data_hi_m <= ecc.io.sec_data_hi_m @[lsu.scala 210:46] + dccm_ctl.io.sec_data_lo_m <= ecc.io.sec_data_lo_m @[lsu.scala 211:46] + dccm_ctl.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[lsu.scala 212:46] + dccm_ctl.io.dma_dccm_wen <= dma_dccm_wen @[lsu.scala 213:46] + dccm_ctl.io.dma_pic_wen <= dma_pic_wen @[lsu.scala 214:46] + dccm_ctl.io.dma_mem_tag_m <= dma_mem_tag_m @[lsu.scala 215:46] + dccm_ctl.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[lsu.scala 216:46] + dccm_ctl.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[lsu.scala 217:46] + dccm_ctl.io.dma_dccm_wdata_ecc_hi <= ecc.io.dma_dccm_wdata_ecc_hi @[lsu.scala 218:46] + dccm_ctl.io.dma_dccm_wdata_ecc_lo <= ecc.io.dma_dccm_wdata_ecc_lo @[lsu.scala 219:46] + dccm_ctl.io.scan_mode <= io.scan_mode @[lsu.scala 220:46] + io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rdata @[lsu.scala 222:27] + io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rtag @[lsu.scala 222:27] + io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_ecc_error @[lsu.scala 222:27] + io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rvalid @[lsu.scala 222:27] + dccm_ctl.io.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[lsu.scala 222:27] + dccm_ctl.io.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[lsu.scala 222:27] + dccm_ctl.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[lsu.scala 223:11] + dccm_ctl.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[lsu.scala 223:11] + io.dccm.wr_data_hi <= dccm_ctl.io.dccm.wr_data_hi @[lsu.scala 223:11] + io.dccm.wr_data_lo <= dccm_ctl.io.dccm.wr_data_lo @[lsu.scala 223:11] + io.dccm.rd_addr_hi <= dccm_ctl.io.dccm.rd_addr_hi @[lsu.scala 223:11] + io.dccm.rd_addr_lo <= dccm_ctl.io.dccm.rd_addr_lo @[lsu.scala 223:11] + io.dccm.wr_addr_hi <= dccm_ctl.io.dccm.wr_addr_hi @[lsu.scala 223:11] + io.dccm.wr_addr_lo <= dccm_ctl.io.dccm.wr_addr_lo @[lsu.scala 223:11] + io.dccm.rden <= dccm_ctl.io.dccm.rden @[lsu.scala 223:11] + io.dccm.wren <= dccm_ctl.io.dccm.wren @[lsu.scala 223:11] + dccm_ctl.io.lsu_pic.picm_rd_data <= io.lsu_pic.picm_rd_data @[lsu.scala 224:14] + io.lsu_pic.picm_wr_data <= dccm_ctl.io.lsu_pic.picm_wr_data @[lsu.scala 224:14] + io.lsu_pic.picm_wraddr <= dccm_ctl.io.lsu_pic.picm_wraddr @[lsu.scala 224:14] + io.lsu_pic.picm_rdaddr <= dccm_ctl.io.lsu_pic.picm_rdaddr @[lsu.scala 224:14] + io.lsu_pic.picm_mken <= dccm_ctl.io.lsu_pic.picm_mken @[lsu.scala 224:14] + io.lsu_pic.picm_rden <= dccm_ctl.io.lsu_pic.picm_rden @[lsu.scala 224:14] + io.lsu_pic.picm_wren <= dccm_ctl.io.lsu_pic.picm_wren @[lsu.scala 224:14] + node _T_80 = bits(lsu_lsc_ctl.io.lsu_addr_d, 2, 2) @[lsu.scala 227:78] + node _T_81 = bits(lsu_lsc_ctl.io.end_addr_d, 2, 2) @[lsu.scala 227:111] + node _T_82 = neq(_T_80, _T_81) @[lsu.scala 227:82] + stbuf.io.ldst_dual_d <= _T_82 @[lsu.scala 227:50] + node _T_83 = bits(lsu_lsc_ctl.io.lsu_addr_m, 2, 2) @[lsu.scala 228:78] + node _T_84 = bits(lsu_lsc_ctl.io.end_addr_m, 2, 2) @[lsu.scala 228:111] + node _T_85 = neq(_T_83, _T_84) @[lsu.scala 228:82] + stbuf.io.ldst_dual_m <= _T_85 @[lsu.scala 228:50] + node _T_86 = bits(lsu_lsc_ctl.io.lsu_addr_r, 2, 2) @[lsu.scala 229:78] + node _T_87 = bits(lsu_lsc_ctl.io.end_addr_r, 2, 2) @[lsu.scala 229:111] + node _T_88 = neq(_T_86, _T_87) @[lsu.scala 229:82] + stbuf.io.ldst_dual_r <= _T_88 @[lsu.scala 229:50] + stbuf.io.lsu_stbuf_c1_clk <= clkdomain.io.lsu_stbuf_c1_clk @[lsu.scala 230:54] + stbuf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 231:54] + stbuf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 232:48] + stbuf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 232:48] + stbuf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 233:48] + stbuf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 233:48] + stbuf.io.store_stbuf_reqvld_r <= store_stbuf_reqvld_r @[lsu.scala 234:48] + stbuf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 235:49] + stbuf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 236:49] + stbuf.io.store_data_hi_r <= dccm_ctl.io.store_data_hi_r @[lsu.scala 237:62] + stbuf.io.store_data_lo_r <= dccm_ctl.io.store_data_lo_r @[lsu.scala 238:62] + stbuf.io.store_datafn_hi_r <= dccm_ctl.io.store_datafn_hi_r @[lsu.scala 239:49] + stbuf.io.store_datafn_lo_r <= dccm_ctl.io.store_datafn_lo_r @[lsu.scala 240:56] + stbuf.io.lsu_stbuf_commit_any <= dccm_ctl.io.lsu_stbuf_commit_any @[lsu.scala 241:52] + stbuf.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 242:64] + stbuf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 243:64] + stbuf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 244:64] + stbuf.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[lsu.scala 245:64] + stbuf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 246:64] + stbuf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 247:64] + stbuf.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 248:49] + stbuf.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 249:56] + stbuf.io.lsu_cmpen_m <= lsu_cmpen_m @[lsu.scala 250:54] + stbuf.io.scan_mode <= io.scan_mode @[lsu.scala 251:49] + ecc.io.clk_override <= io.clk_override @[lsu.scala 255:50] + ecc.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 256:52] + ecc.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 257:52] + ecc.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 257:52] + ecc.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 258:52] + ecc.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 258:52] + ecc.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 259:54] + ecc.io.dec_tlu_core_ecc_disable <= io.dec_tlu_core_ecc_disable @[lsu.scala 260:50] + ecc.io.lsu_dccm_rden_r <= dccm_ctl.io.lsu_dccm_rden_r @[lsu.scala 261:56] + ecc.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 262:50] + ecc.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 263:58] + ecc.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 264:58] + ecc.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 265:58] + ecc.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 266:58] + ecc.io.dccm_rdata_hi_r <= dccm_ctl.io.dccm_rdata_hi_r @[lsu.scala 267:54] + ecc.io.dccm_rdata_lo_r <= dccm_ctl.io.dccm_rdata_lo_r @[lsu.scala 268:54] + ecc.io.dccm_rdata_hi_m <= dccm_ctl.io.dccm_rdata_hi_m @[lsu.scala 269:54] + ecc.io.dccm_rdata_lo_m <= dccm_ctl.io.dccm_rdata_lo_m @[lsu.scala 270:54] + ecc.io.dccm_data_ecc_hi_r <= dccm_ctl.io.dccm_data_ecc_hi_r @[lsu.scala 271:50] + ecc.io.dccm_data_ecc_lo_r <= dccm_ctl.io.dccm_data_ecc_lo_r @[lsu.scala 272:50] + ecc.io.dccm_data_ecc_hi_m <= dccm_ctl.io.dccm_data_ecc_hi_m @[lsu.scala 273:50] + ecc.io.dccm_data_ecc_lo_m <= dccm_ctl.io.dccm_data_ecc_lo_m @[lsu.scala 274:50] + ecc.io.ld_single_ecc_error_r <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 275:50] + ecc.io.ld_single_ecc_error_r_ff <= dccm_ctl.io.ld_single_ecc_error_r_ff @[lsu.scala 276:50] + ecc.io.lsu_dccm_rden_m <= dccm_ctl.io.lsu_dccm_rden_m @[lsu.scala 277:50] + ecc.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 278:50] + ecc.io.dma_dccm_wen <= dma_dccm_wen @[lsu.scala 279:50] + ecc.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[lsu.scala 280:50] + ecc.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[lsu.scala 281:50] + ecc.io.scan_mode <= io.scan_mode @[lsu.scala 282:50] + trigger.io.trigger_pkt_any[0].tdata2 <= io.trigger_pkt_any[0].tdata2 @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].m <= io.trigger_pkt_any[0].m @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].execute <= io.trigger_pkt_any[0].execute @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].load <= io.trigger_pkt_any[0].load @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].store <= io.trigger_pkt_any[0].store @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].match_pkt <= io.trigger_pkt_any[0].match_pkt @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[0].select <= io.trigger_pkt_any[0].select @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].tdata2 <= io.trigger_pkt_any[1].tdata2 @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].m <= io.trigger_pkt_any[1].m @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].execute <= io.trigger_pkt_any[1].execute @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].load <= io.trigger_pkt_any[1].load @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].store <= io.trigger_pkt_any[1].store @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].match_pkt <= io.trigger_pkt_any[1].match_pkt @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[1].select <= io.trigger_pkt_any[1].select @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].tdata2 <= io.trigger_pkt_any[2].tdata2 @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].m <= io.trigger_pkt_any[2].m @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].execute <= io.trigger_pkt_any[2].execute @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].load <= io.trigger_pkt_any[2].load @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].store <= io.trigger_pkt_any[2].store @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].match_pkt <= io.trigger_pkt_any[2].match_pkt @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[2].select <= io.trigger_pkt_any[2].select @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].tdata2 <= io.trigger_pkt_any[3].tdata2 @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].m <= io.trigger_pkt_any[3].m @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].execute <= io.trigger_pkt_any[3].execute @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].load <= io.trigger_pkt_any[3].load @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].store <= io.trigger_pkt_any[3].store @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].match_pkt <= io.trigger_pkt_any[3].match_pkt @[lsu.scala 286:50] + trigger.io.trigger_pkt_any[3].select <= io.trigger_pkt_any[3].select @[lsu.scala 286:50] + trigger.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 287:50] + trigger.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 287:50] + trigger.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 288:50] + trigger.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[lsu.scala 289:50] + io.lsu_trigger_match_m <= trigger.io.lsu_trigger_match_m @[lsu.scala 291:50] + clkdomain.io.active_clk <= io.active_clk @[lsu.scala 295:50] + clkdomain.io.clk_override <= io.clk_override @[lsu.scala 296:50] + clkdomain.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu.scala 297:50] + clkdomain.io.dma_dccm_req <= io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[lsu.scala 298:50] + clkdomain.io.ldst_stbuf_reqvld_r <= stbuf.io.ldst_stbuf_reqvld_r @[lsu.scala 299:50] + clkdomain.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 300:50] + clkdomain.io.stbuf_reqvld_flushed_any <= stbuf.io.stbuf_reqvld_flushed_any @[lsu.scala 301:50] + clkdomain.io.lsu_busreq_r <= bus_intf.io.lsu_busreq_r @[lsu.scala 302:50] + clkdomain.io.lsu_bus_buffer_pend_any <= bus_intf.io.lsu_bus_buffer_pend_any @[lsu.scala 303:50] + clkdomain.io.lsu_bus_buffer_empty_any <= bus_intf.io.lsu_bus_buffer_empty_any @[lsu.scala 304:50] + clkdomain.io.lsu_stbuf_empty_any <= stbuf.io.lsu_stbuf_empty_any @[lsu.scala 305:50] + clkdomain.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 306:50] + clkdomain.io.lsu_p.bits.store_data_bypass_m <= io.lsu_p.bits.store_data_bypass_m @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.load_ldst_bypass_d <= io.lsu_p.bits.load_ldst_bypass_d @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.store_data_bypass_d <= io.lsu_p.bits.store_data_bypass_d @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.dma <= io.lsu_p.bits.dma @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.unsign <= io.lsu_p.bits.unsign @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.store <= io.lsu_p.bits.store @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.load <= io.lsu_p.bits.load @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.dword <= io.lsu_p.bits.dword @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.word <= io.lsu_p.bits.word @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.half <= io.lsu_p.bits.half @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.by <= io.lsu_p.bits.by @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.stack <= io.lsu_p.bits.stack @[lsu.scala 307:50] + clkdomain.io.lsu_p.bits.fast_int <= io.lsu_p.bits.fast_int @[lsu.scala 307:50] + clkdomain.io.lsu_p.valid <= io.lsu_p.valid @[lsu.scala 307:50] + clkdomain.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dma @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.bits.unsign @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.store <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.load <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dword @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.word <= lsu_lsc_ctl.io.lsu_pkt_d.bits.word @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.half <= lsu_lsc_ctl.io.lsu_pkt_d.bits.half @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.by <= lsu_lsc_ctl.io.lsu_pkt_d.bits.by @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_d.bits.stack @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.bits.fast_int @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[lsu.scala 308:50] + clkdomain.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 309:50] + clkdomain.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 310:50] + clkdomain.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 310:50] + clkdomain.io.scan_mode <= io.scan_mode @[lsu.scala 311:50] + bus_intf.io.scan_mode <= io.scan_mode @[lsu.scala 315:49] + io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu.scala 316:26] + bus_intf.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu.scala 316:26] + bus_intf.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu.scala 316:26] + bus_intf.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_error @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu.scala 316:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu.scala 316:26] + bus_intf.io.clk_override <= io.clk_override @[lsu.scala 317:49] + bus_intf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 318:49] + bus_intf.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 319:49] + bus_intf.io.lsu_busm_clken <= lsu_busm_clken @[lsu.scala 320:49] + bus_intf.io.lsu_bus_obuf_c1_clken <= lsu_bus_obuf_c1_clken @[lsu.scala 321:49] + bus_intf.io.lsu_bus_ibuf_c1_clk <= clkdomain.io.lsu_bus_ibuf_c1_clk @[lsu.scala 322:49] + bus_intf.io.lsu_bus_obuf_c1_clk <= clkdomain.io.lsu_bus_obuf_c1_clk @[lsu.scala 323:49] + bus_intf.io.lsu_bus_buf_c1_clk <= clkdomain.io.lsu_bus_buf_c1_clk @[lsu.scala 324:49] + bus_intf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 325:49] + bus_intf.io.active_clk <= io.active_clk @[lsu.scala 326:49] + bus_intf.io.lsu_busm_clk <= clkdomain.io.lsu_busm_clk @[lsu.scala 327:49] + bus_intf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 328:49] + bus_intf.io.lsu_busreq_m <= lsu_busreq_m @[lsu.scala 329:49] + node _T_89 = bits(lsu_lsc_ctl.io.lsu_addr_d, 2, 2) @[lsu.scala 330:77] + node _T_90 = bits(lsu_lsc_ctl.io.end_addr_d, 2, 2) @[lsu.scala 330:110] + node _T_91 = neq(_T_89, _T_90) @[lsu.scala 330:81] + bus_intf.io.ldst_dual_d <= _T_91 @[lsu.scala 330:49] + node _T_92 = bits(lsu_lsc_ctl.io.lsu_addr_m, 2, 2) @[lsu.scala 331:77] + node _T_93 = bits(lsu_lsc_ctl.io.end_addr_m, 2, 2) @[lsu.scala 331:110] + node _T_94 = neq(_T_92, _T_93) @[lsu.scala 331:81] + bus_intf.io.ldst_dual_m <= _T_94 @[lsu.scala 331:49] + node _T_95 = bits(lsu_lsc_ctl.io.lsu_addr_r, 2, 2) @[lsu.scala 332:77] + node _T_96 = bits(lsu_lsc_ctl.io.end_addr_r, 2, 2) @[lsu.scala 332:110] + node _T_97 = neq(_T_95, _T_96) @[lsu.scala 332:81] + bus_intf.io.ldst_dual_r <= _T_97 @[lsu.scala 332:49] + node _T_98 = and(lsu_lsc_ctl.io.addr_external_m, lsu_lsc_ctl.io.lsu_pkt_m.valid) @[lsu.scala 333:119] + node _T_99 = bits(_T_98, 0, 0) @[Bitwise.scala 72:15] + node _T_100 = mux(_T_99, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_101 = and(lsu_lsc_ctl.io.lsu_addr_m, _T_100) @[lsu.scala 333:78] + bus_intf.io.lsu_addr_m <= _T_101 @[lsu.scala 333:49] + node _T_102 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15] + node _T_103 = mux(_T_102, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_104 = and(lsu_lsc_ctl.io.lsu_addr_r, _T_103) @[lsu.scala 334:78] + bus_intf.io.lsu_addr_r <= _T_104 @[lsu.scala 334:49] + node _T_105 = and(lsu_lsc_ctl.io.addr_external_m, lsu_lsc_ctl.io.lsu_pkt_m.valid) @[lsu.scala 335:119] + node _T_106 = bits(_T_105, 0, 0) @[Bitwise.scala 72:15] + node _T_107 = mux(_T_106, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_108 = and(lsu_lsc_ctl.io.end_addr_m, _T_107) @[lsu.scala 335:78] + bus_intf.io.end_addr_m <= _T_108 @[lsu.scala 335:49] + node _T_109 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15] + node _T_110 = mux(_T_109, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_111 = and(lsu_lsc_ctl.io.end_addr_r, _T_110) @[lsu.scala 336:78] + bus_intf.io.end_addr_r <= _T_111 @[lsu.scala 336:49] + node _T_112 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15] + node _T_113 = mux(_T_112, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_114 = and(dccm_ctl.io.store_data_r, _T_113) @[lsu.scala 337:77] + bus_intf.io.store_data_r <= _T_114 @[lsu.scala 337:49] + bus_intf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 338:49] + bus_intf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 339:49] + bus_intf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 339:49] + bus_intf.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu.scala 340:49] + bus_intf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 341:49] + bus_intf.io.is_sideeffects_m <= lsu_lsc_ctl.io.is_sideeffects_m @[lsu.scala 342:49] + bus_intf.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 343:49] + bus_intf.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 344:49] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu.scala 346:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu.scala 346:27] + io.lsu_nonblock_load_data <= bus_intf.io.lsu_nonblock_load_data @[lsu.scala 347:29] + lsu_busreq_r <= bus_intf.io.lsu_busreq_r @[lsu.scala 348:16] + bus_intf.io.axi.r.bits.last <= io.axi.r.bits.last @[lsu.scala 349:49] + bus_intf.io.axi.r.bits.resp <= io.axi.r.bits.resp @[lsu.scala 349:49] + bus_intf.io.axi.r.bits.data <= io.axi.r.bits.data @[lsu.scala 349:49] + bus_intf.io.axi.r.bits.id <= io.axi.r.bits.id @[lsu.scala 349:49] + bus_intf.io.axi.r.valid <= io.axi.r.valid @[lsu.scala 349:49] + io.axi.r.ready <= bus_intf.io.axi.r.ready @[lsu.scala 349:49] + io.axi.ar.bits.qos <= bus_intf.io.axi.ar.bits.qos @[lsu.scala 349:49] + io.axi.ar.bits.prot <= bus_intf.io.axi.ar.bits.prot @[lsu.scala 349:49] + io.axi.ar.bits.cache <= bus_intf.io.axi.ar.bits.cache @[lsu.scala 349:49] + io.axi.ar.bits.lock <= bus_intf.io.axi.ar.bits.lock @[lsu.scala 349:49] + io.axi.ar.bits.burst <= bus_intf.io.axi.ar.bits.burst @[lsu.scala 349:49] + io.axi.ar.bits.size <= bus_intf.io.axi.ar.bits.size @[lsu.scala 349:49] + io.axi.ar.bits.len <= bus_intf.io.axi.ar.bits.len @[lsu.scala 349:49] + io.axi.ar.bits.region <= bus_intf.io.axi.ar.bits.region @[lsu.scala 349:49] + io.axi.ar.bits.addr <= bus_intf.io.axi.ar.bits.addr @[lsu.scala 349:49] + io.axi.ar.bits.id <= bus_intf.io.axi.ar.bits.id @[lsu.scala 349:49] + io.axi.ar.valid <= bus_intf.io.axi.ar.valid @[lsu.scala 349:49] + bus_intf.io.axi.ar.ready <= io.axi.ar.ready @[lsu.scala 349:49] + bus_intf.io.axi.b.bits.id <= io.axi.b.bits.id @[lsu.scala 349:49] + bus_intf.io.axi.b.bits.resp <= io.axi.b.bits.resp @[lsu.scala 349:49] + bus_intf.io.axi.b.valid <= io.axi.b.valid @[lsu.scala 349:49] + io.axi.b.ready <= bus_intf.io.axi.b.ready @[lsu.scala 349:49] + io.axi.w.bits.last <= bus_intf.io.axi.w.bits.last @[lsu.scala 349:49] + io.axi.w.bits.strb <= bus_intf.io.axi.w.bits.strb @[lsu.scala 349:49] + io.axi.w.bits.data <= bus_intf.io.axi.w.bits.data @[lsu.scala 349:49] + io.axi.w.valid <= bus_intf.io.axi.w.valid @[lsu.scala 349:49] + bus_intf.io.axi.w.ready <= io.axi.w.ready @[lsu.scala 349:49] + io.axi.aw.bits.qos <= bus_intf.io.axi.aw.bits.qos @[lsu.scala 349:49] + io.axi.aw.bits.prot <= bus_intf.io.axi.aw.bits.prot @[lsu.scala 349:49] + io.axi.aw.bits.cache <= bus_intf.io.axi.aw.bits.cache @[lsu.scala 349:49] + io.axi.aw.bits.lock <= bus_intf.io.axi.aw.bits.lock @[lsu.scala 349:49] + io.axi.aw.bits.burst <= bus_intf.io.axi.aw.bits.burst @[lsu.scala 349:49] + io.axi.aw.bits.size <= bus_intf.io.axi.aw.bits.size @[lsu.scala 349:49] + io.axi.aw.bits.len <= bus_intf.io.axi.aw.bits.len @[lsu.scala 349:49] + io.axi.aw.bits.region <= bus_intf.io.axi.aw.bits.region @[lsu.scala 349:49] + io.axi.aw.bits.addr <= bus_intf.io.axi.aw.bits.addr @[lsu.scala 349:49] + io.axi.aw.bits.id <= bus_intf.io.axi.aw.bits.id @[lsu.scala 349:49] + io.axi.aw.valid <= bus_intf.io.axi.aw.valid @[lsu.scala 349:49] + bus_intf.io.axi.aw.ready <= io.axi.aw.ready @[lsu.scala 349:49] + bus_intf.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 350:49] + reg _T_115 : UInt, clkdomain.io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 352:67] + _T_115 <= io.lsu_dma.dma_mem_tag @[lsu.scala 352:67] + dma_mem_tag_m <= _T_115 @[lsu.scala 352:57] + reg _T_116 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 353:67] + _T_116 <= lsu_raw_fwd_hi_m @[lsu.scala 353:67] + lsu_raw_fwd_hi_r <= _T_116 @[lsu.scala 353:57] + reg _T_117 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 354:67] + _T_117 <= lsu_raw_fwd_lo_m @[lsu.scala 354:67] + lsu_raw_fwd_lo_r <= _T_117 @[lsu.scala 354:57] + diff --git a/lsu.v b/lsu.v new file mode 100644 index 00000000..2d1d7bc1 --- /dev/null +++ b/lsu.v @@ -0,0 +1,11116 @@ +module lsu_addrcheck( + input reset, + input io_lsu_c2_m_clk, + input [31:0] io_start_addr_d, + input [31:0] io_end_addr_d, + input io_lsu_pkt_d_valid, + input io_lsu_pkt_d_bits_fast_int, + input io_lsu_pkt_d_bits_by, + input io_lsu_pkt_d_bits_half, + input io_lsu_pkt_d_bits_word, + input io_lsu_pkt_d_bits_load, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_d_bits_dma, + input [31:0] io_dec_tlu_mrac_ff, + input [3:0] io_rs1_region_d, + output io_is_sideeffects_m, + output io_addr_in_dccm_d, + output io_addr_in_pic_d, + output io_addr_external_d, + output io_access_fault_d, + output io_misaligned_fault_d, + output [3:0] io_exc_mscause_d, + output io_fir_dccm_access_error_d, + output io_fir_nondccm_access_error_d +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 370:49] + wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 375:39] + wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 370:49] + wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 375:39] + wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45] + wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 375:39] + wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 375:39] + wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60] + wire _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:55] + wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:91] + wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58] + wire [31:0] _T_26 = io_dec_tlu_mrac_ff >> csr_idx; // @[lsu_addrcheck.scala 61:50] + wire _T_29 = start_addr_dccm_or_pic | addr_in_iccm; // @[lsu_addrcheck.scala 61:121] + wire _T_30 = ~_T_29; // @[lsu_addrcheck.scala 61:62] + wire _T_31 = _T_26[0] & _T_30; // @[lsu_addrcheck.scala 61:60] + wire _T_32 = _T_31 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 61:137] + wire _T_33 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[lsu_addrcheck.scala 61:185] + wire is_sideeffects_d = _T_32 & _T_33; // @[lsu_addrcheck.scala 61:158] + wire _T_35 = io_start_addr_d[1:0] == 2'h0; // @[lsu_addrcheck.scala 62:80] + wire _T_36 = io_lsu_pkt_d_bits_word & _T_35; // @[lsu_addrcheck.scala 62:56] + wire _T_38 = ~io_start_addr_d[0]; // @[lsu_addrcheck.scala 62:138] + wire _T_39 = io_lsu_pkt_d_bits_half & _T_38; // @[lsu_addrcheck.scala 62:116] + wire _T_40 = _T_36 | _T_39; // @[lsu_addrcheck.scala 62:90] + wire is_aligned_d = _T_40 | io_lsu_pkt_d_bits_by; // @[lsu_addrcheck.scala 62:148] + wire [31:0] _T_51 = io_start_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 67:56] + wire _T_53 = _T_51 == 32'h7fffffff; // @[lsu_addrcheck.scala 67:88] + wire [31:0] _T_56 = io_start_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 68:56] + wire _T_58 = _T_56 == 32'hffffffff; // @[lsu_addrcheck.scala 68:88] + wire _T_60 = _T_53 | _T_58; // @[lsu_addrcheck.scala 67:153] + wire [31:0] _T_62 = io_start_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 69:56] + wire _T_64 = _T_62 == 32'hbfffffff; // @[lsu_addrcheck.scala 69:88] + wire _T_66 = _T_60 | _T_64; // @[lsu_addrcheck.scala 68:153] + wire [31:0] _T_68 = io_start_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 70:56] + wire _T_70 = _T_68 == 32'h8fffffff; // @[lsu_addrcheck.scala 70:88] + wire _T_72 = _T_66 | _T_70; // @[lsu_addrcheck.scala 69:153] + wire [31:0] _T_98 = io_end_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 76:57] + wire _T_100 = _T_98 == 32'h7fffffff; // @[lsu_addrcheck.scala 76:89] + wire [31:0] _T_103 = io_end_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 77:58] + wire _T_105 = _T_103 == 32'hffffffff; // @[lsu_addrcheck.scala 77:90] + wire _T_107 = _T_100 | _T_105; // @[lsu_addrcheck.scala 76:154] + wire [31:0] _T_109 = io_end_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 78:58] + wire _T_111 = _T_109 == 32'hbfffffff; // @[lsu_addrcheck.scala 78:90] + wire _T_113 = _T_107 | _T_111; // @[lsu_addrcheck.scala 77:155] + wire [31:0] _T_115 = io_end_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 79:58] + wire _T_117 = _T_115 == 32'h8fffffff; // @[lsu_addrcheck.scala 79:90] + wire _T_119 = _T_113 | _T_117; // @[lsu_addrcheck.scala 78:155] + wire non_dccm_access_ok = _T_72 & _T_119; // @[lsu_addrcheck.scala 75:7] + wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[lsu_addrcheck.scala 85:57] + wire _T_146 = io_start_addr_d[1:0] != 2'h0; // @[lsu_addrcheck.scala 86:76] + wire _T_147 = ~io_lsu_pkt_d_bits_word; // @[lsu_addrcheck.scala 86:92] + wire _T_148 = _T_146 | _T_147; // @[lsu_addrcheck.scala 86:90] + wire picm_access_fault_d = io_addr_in_pic_d & _T_148; // @[lsu_addrcheck.scala 86:51] + wire _T_149 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[lsu_addrcheck.scala 91:87] + wire _T_150 = ~_T_149; // @[lsu_addrcheck.scala 91:64] + wire _T_151 = start_addr_in_dccm_region_d & _T_150; // @[lsu_addrcheck.scala 91:62] + wire _T_152 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[lsu_addrcheck.scala 93:57] + wire _T_153 = ~_T_152; // @[lsu_addrcheck.scala 93:36] + wire _T_154 = end_addr_in_dccm_region_d & _T_153; // @[lsu_addrcheck.scala 93:34] + wire _T_155 = _T_151 | _T_154; // @[lsu_addrcheck.scala 91:112] + wire _T_156 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 95:29] + wire _T_157 = _T_155 | _T_156; // @[lsu_addrcheck.scala 93:85] + wire _T_158 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 97:29] + wire unmapped_access_fault_d = _T_157 | _T_158; // @[lsu_addrcheck.scala 95:85] + wire _T_160 = ~start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 99:33] + wire _T_161 = ~non_dccm_access_ok; // @[lsu_addrcheck.scala 99:64] + wire mpu_access_fault_d = _T_160 & _T_161; // @[lsu_addrcheck.scala 99:62] + wire _T_163 = unmapped_access_fault_d | mpu_access_fault_d; // @[lsu_addrcheck.scala 111:49] + wire _T_164 = _T_163 | picm_access_fault_d; // @[lsu_addrcheck.scala 111:70] + wire _T_165 = _T_164 | regpred_access_fault_d; // @[lsu_addrcheck.scala 111:92] + wire _T_166 = _T_165 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 111:118] + wire _T_167 = ~io_lsu_pkt_d_bits_dma; // @[lsu_addrcheck.scala 111:141] + wire [3:0] _T_173 = picm_access_fault_d ? 4'h6 : 4'h0; // @[lsu_addrcheck.scala 112:164] + wire [3:0] _T_174 = regpred_access_fault_d ? 4'h5 : _T_173; // @[lsu_addrcheck.scala 112:120] + wire [3:0] _T_175 = mpu_access_fault_d ? 4'h3 : _T_174; // @[lsu_addrcheck.scala 112:80] + wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_175; // @[lsu_addrcheck.scala 112:35] + wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[lsu_addrcheck.scala 113:61] + wire _T_178 = ~is_aligned_d; // @[lsu_addrcheck.scala 114:59] + wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_178; // @[lsu_addrcheck.scala 114:57] + wire _T_179 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[lsu_addrcheck.scala 115:90] + wire _T_180 = regcross_misaligned_fault_d | _T_179; // @[lsu_addrcheck.scala 115:57] + wire _T_181 = _T_180 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 115:113] + wire [3:0] _T_185 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[lsu_addrcheck.scala 116:80] + wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_185; // @[lsu_addrcheck.scala 116:39] + wire _T_190 = ~start_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:66] + wire _T_191 = start_addr_in_dccm_region_d & _T_190; // @[lsu_addrcheck.scala 118:64] + wire _T_192 = ~end_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:120] + wire _T_193 = end_addr_in_dccm_region_d & _T_192; // @[lsu_addrcheck.scala 118:118] + wire _T_194 = _T_191 | _T_193; // @[lsu_addrcheck.scala 118:88] + wire _T_195 = _T_194 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 118:142] + wire _T_197 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 119:66] + wire _T_198 = ~_T_197; // @[lsu_addrcheck.scala 119:36] + wire _T_199 = _T_198 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 119:95] + reg _T_201; // @[lsu_addrcheck.scala 121:60] + assign io_is_sideeffects_m = _T_201; // @[lsu_addrcheck.scala 121:50] + assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 56:32] + assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 57:32] + assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[lsu_addrcheck.scala 59:30] + assign io_access_fault_d = _T_166 & _T_167; // @[lsu_addrcheck.scala 111:21] + assign io_misaligned_fault_d = _T_181 & _T_167; // @[lsu_addrcheck.scala 115:25] + assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[lsu_addrcheck.scala 117:21] + assign io_fir_dccm_access_error_d = _T_195 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 118:31] + assign io_fir_nondccm_access_error_d = _T_199 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 119:33] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_201 = _RAND_0[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_201 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_201 <= 1'h0; + end else begin + _T_201 <= _T_32 & _T_33; + end + end +endmodule +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module lsu_lsc_ctl( + input clock, + input reset, + input io_clk_override, + input io_lsu_c1_m_clk, + input io_lsu_c1_r_clk, + input io_lsu_c2_m_clk, + input io_lsu_c2_r_clk, + input io_lsu_store_c1_m_clk, + input [31:0] io_lsu_ld_data_corr_r, + input io_lsu_single_ecc_error_r, + input io_lsu_double_ecc_error_r, + input [31:0] io_lsu_ld_data_m, + input io_lsu_single_ecc_error_m, + input io_lsu_double_ecc_error_m, + input io_flush_m_up, + input io_flush_r, + input io_ldst_dual_d, + input [31:0] io_lsu_exu_exu_lsu_rs1_d, + input [31:0] io_lsu_exu_exu_lsu_rs2_d, + output [31:0] io_lsu_exu_lsu_result_m, + input io_lsu_p_valid, + input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_by, + input io_lsu_p_bits_half, + input io_lsu_p_bits_word, + input io_lsu_p_bits_dword, + input io_lsu_p_bits_load, + input io_lsu_p_bits_store, + input io_lsu_p_bits_unsign, + input io_lsu_p_bits_dma, + input io_lsu_p_bits_store_data_bypass_d, + input io_lsu_p_bits_load_ldst_bypass_d, + input io_lsu_p_bits_store_data_bypass_m, + input io_dec_lsu_valid_raw_d, + input [11:0] io_dec_lsu_offset_d, + input [31:0] io_picm_mask_data_m, + input [31:0] io_bus_read_data_m, + output [31:0] io_lsu_result_corr_r, + output [31:0] io_lsu_addr_d, + output [31:0] io_lsu_addr_m, + output [31:0] io_lsu_addr_r, + output [31:0] io_end_addr_d, + output [31:0] io_end_addr_m, + output [31:0] io_end_addr_r, + output [31:0] io_store_data_m, + input [31:0] io_dec_tlu_mrac_ff, + output io_lsu_exc_m, + output io_is_sideeffects_m, + output io_lsu_commit_r, + output io_lsu_single_ecc_error_incr, + output io_lsu_error_pkt_r_valid, + output io_lsu_error_pkt_r_bits_single_ecc_error, + output io_lsu_error_pkt_r_bits_inst_type, + output io_lsu_error_pkt_r_bits_exc_type, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, + output [30:0] io_lsu_fir_addr, + output [1:0] io_lsu_fir_error, + output io_addr_in_dccm_d, + output io_addr_in_dccm_m, + output io_addr_in_dccm_r, + output io_addr_in_pic_d, + output io_addr_in_pic_m, + output io_addr_in_pic_r, + output io_addr_external_m, + input io_dma_lsc_ctl_dma_dccm_req, + input [31:0] io_dma_lsc_ctl_dma_mem_addr, + input [2:0] io_dma_lsc_ctl_dma_mem_sz, + input io_dma_lsc_ctl_dma_mem_write, + input [63:0] io_dma_lsc_ctl_dma_mem_wdata, + output io_lsu_pkt_d_valid, + output io_lsu_pkt_d_bits_fast_int, + output io_lsu_pkt_d_bits_by, + output io_lsu_pkt_d_bits_half, + output io_lsu_pkt_d_bits_word, + output io_lsu_pkt_d_bits_dword, + output io_lsu_pkt_d_bits_load, + output io_lsu_pkt_d_bits_store, + output io_lsu_pkt_d_bits_unsign, + output io_lsu_pkt_d_bits_dma, + output io_lsu_pkt_d_bits_store_data_bypass_d, + output io_lsu_pkt_d_bits_load_ldst_bypass_d, + output io_lsu_pkt_d_bits_store_data_bypass_m, + output io_lsu_pkt_m_valid, + output io_lsu_pkt_m_bits_fast_int, + output io_lsu_pkt_m_bits_by, + output io_lsu_pkt_m_bits_half, + output io_lsu_pkt_m_bits_word, + output io_lsu_pkt_m_bits_dword, + output io_lsu_pkt_m_bits_load, + output io_lsu_pkt_m_bits_store, + output io_lsu_pkt_m_bits_unsign, + output io_lsu_pkt_m_bits_dma, + output io_lsu_pkt_m_bits_store_data_bypass_m, + output io_lsu_pkt_r_valid, + output io_lsu_pkt_r_bits_by, + output io_lsu_pkt_r_bits_half, + output io_lsu_pkt_r_bits_word, + output io_lsu_pkt_r_bits_dword, + output io_lsu_pkt_r_bits_load, + output io_lsu_pkt_r_bits_store, + output io_lsu_pkt_r_bits_unsign, + output io_lsu_pkt_r_bits_dma +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; +`endif // RANDOMIZE_REG_INIT + wire addrcheck_reset; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_start_addr_d; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_end_addr_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 117:25] + wire [3:0] addrcheck_io_rs1_region_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_external_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_access_fault_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_misaligned_fault_d; // @[lsu_lsc_ctl.scala 117:25] + wire [3:0] addrcheck_io_exc_mscause_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_fir_dccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_fir_nondccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25] + wire rvclkhdr_io_clk; // @[lib.scala 417:23] + wire rvclkhdr_io_en; // @[lib.scala 417:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_lsu_exu_exu_lsu_rs1_d : io_dma_lsc_ctl_dma_mem_addr; // @[lsu_lsc_ctl.scala 99:28] + wire [11:0] _T_4 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] + wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_4; // @[lsu_lsc_ctl.scala 100:51] + wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_exu_lsu_result_m : lsu_rs1_d; // @[lsu_lsc_ctl.scala 103:28] + wire [12:0] _T_7 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58] + wire [12:0] _T_9 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _T_11 = _T_7 + _T_9; // @[lib.scala 92:39] + wire _T_14 = lsu_offset_d[11] ^ _T_11[12]; // @[lib.scala 93:46] + wire _T_15 = ~_T_14; // @[lib.scala 93:33] + wire [19:0] _T_17 = _T_15 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_19 = _T_17 & rs1_d[31:12]; // @[lib.scala 93:58] + wire _T_21 = ~lsu_offset_d[11]; // @[lib.scala 94:18] + wire _T_23 = _T_21 & _T_11[12]; // @[lib.scala 94:30] + wire [19:0] _T_25 = _T_23 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_28 = rs1_d[31:12] + 20'h1; // @[lib.scala 94:54] + wire [19:0] _T_29 = _T_25 & _T_28; // @[lib.scala 94:41] + wire [19:0] _T_30 = _T_19 | _T_29; // @[lib.scala 93:72] + wire _T_33 = ~_T_11[12]; // @[lib.scala 95:31] + wire _T_34 = lsu_offset_d[11] & _T_33; // @[lib.scala 95:29] + wire [19:0] _T_36 = _T_34 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_39 = rs1_d[31:12] - 20'h1; // @[lib.scala 95:54] + wire [19:0] _T_40 = _T_36 & _T_39; // @[lib.scala 95:41] + wire [19:0] _T_41 = _T_30 | _T_40; // @[lib.scala 94:61] + wire [2:0] _T_44 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_45 = _T_44 & 3'h1; // @[lsu_lsc_ctl.scala 108:58] + wire [2:0] _T_47 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_48 = _T_47 & 3'h3; // @[lsu_lsc_ctl.scala 109:40] + wire [2:0] _T_49 = _T_45 | _T_48; // @[lsu_lsc_ctl.scala 108:70] + wire [2:0] _T_51 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] addr_offset_d = _T_49 | _T_51; // @[lsu_lsc_ctl.scala 109:52] + wire [12:0] _T_55 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58] + wire [11:0] _T_58 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _GEN_9 = {{1'd0}, _T_58}; // @[lsu_lsc_ctl.scala 112:60] + wire [12:0] end_addr_offset_d = _T_55 + _GEN_9; // @[lsu_lsc_ctl.scala 112:60] + wire [18:0] _T_63 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_65 = {_T_63,end_addr_offset_d}; // @[Cat.scala 29:58] + reg access_fault_m; // @[lsu_lsc_ctl.scala 148:75] + reg misaligned_fault_m; // @[lsu_lsc_ctl.scala 149:75] + reg [3:0] exc_mscause_m; // @[lsu_lsc_ctl.scala 150:75] + reg fir_dccm_access_error_m; // @[lsu_lsc_ctl.scala 151:75] + reg fir_nondccm_access_error_m; // @[lsu_lsc_ctl.scala 152:75] + wire _T_70 = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:34] + wire _T_71 = ~io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 155:64] + wire _T_72 = io_lsu_single_ecc_error_r & _T_71; // @[lsu_lsc_ctl.scala 155:62] + wire _T_73 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 155:111] + wire _T_74 = _T_72 & _T_73; // @[lsu_lsc_ctl.scala 155:92] + wire _T_77 = _T_70 | io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 177:67] + wire _T_78 = _T_77 & io_lsu_pkt_m_valid; // @[lsu_lsc_ctl.scala 177:96] + wire _T_79 = ~io_lsu_pkt_m_bits_dma; // @[lsu_lsc_ctl.scala 177:119] + wire _T_80 = _T_78 & _T_79; // @[lsu_lsc_ctl.scala 177:117] + wire _T_81 = ~io_lsu_pkt_m_bits_fast_int; // @[lsu_lsc_ctl.scala 177:144] + wire _T_82 = _T_80 & _T_81; // @[lsu_lsc_ctl.scala 177:142] + wire _T_83 = ~io_flush_m_up; // @[lsu_lsc_ctl.scala 177:174] + wire lsu_error_pkt_m_valid = _T_82 & _T_83; // @[lsu_lsc_ctl.scala 177:172] + wire _T_85 = ~lsu_error_pkt_m_valid; // @[lsu_lsc_ctl.scala 178:75] + wire _T_86 = io_lsu_single_ecc_error_m & _T_85; // @[lsu_lsc_ctl.scala 178:73] + wire lsu_error_pkt_m_bits_single_ecc_error = _T_86 & _T_79; // @[lsu_lsc_ctl.scala 178:99] + wire lsu_error_pkt_m_bits_exc_type = ~misaligned_fault_m; // @[lsu_lsc_ctl.scala 180:46] + wire _T_91 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[lsu_lsc_ctl.scala 181:78] + wire _T_92 = ~access_fault_m; // @[lsu_lsc_ctl.scala 181:102] + wire _T_93 = _T_91 & _T_92; // @[lsu_lsc_ctl.scala 181:100] + wire _T_100 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 183:166] + wire _T_105 = lsu_error_pkt_m_valid | lsu_error_pkt_m_bits_single_ecc_error; // @[lsu_lsc_ctl.scala 184:73] + wire _T_106 = _T_105 | io_clk_override; // @[lsu_lsc_ctl.scala 184:113] + reg _T_110_bits_inst_type; // @[Reg.scala 27:20] + reg _T_110_bits_exc_type; // @[Reg.scala 27:20] + reg [3:0] _T_110_bits_mscause; // @[Reg.scala 27:20] + reg [31:0] _T_110_bits_addr; // @[Reg.scala 27:20] + reg _T_111; // @[lsu_lsc_ctl.scala 185:83] + reg _T_112; // @[lsu_lsc_ctl.scala 186:67] + reg [1:0] _T_113; // @[lsu_lsc_ctl.scala 187:75] + wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 195:30] + wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 196:62] + wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 197:62] + wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 198:62] + wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 199:62] + wire _T_125 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 212:64] + wire _T_126 = io_flush_m_up & _T_125; // @[lsu_lsc_ctl.scala 212:61] + wire _T_127 = ~_T_126; // @[lsu_lsc_ctl.scala 212:45] + wire _T_128 = io_lsu_p_valid & _T_127; // @[lsu_lsc_ctl.scala 212:43] + wire _T_130 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 213:68] + wire _T_131 = io_flush_m_up & _T_130; // @[lsu_lsc_ctl.scala 213:65] + wire _T_132 = ~_T_131; // @[lsu_lsc_ctl.scala 213:49] + wire _T_135 = io_flush_m_up & _T_79; // @[lsu_lsc_ctl.scala 214:65] + wire _T_136 = ~_T_135; // @[lsu_lsc_ctl.scala 214:49] + reg _T_139_bits_fast_int; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_by; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_half; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_word; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_dword; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_load; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_store; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_unsign; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_dma; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:65] + reg _T_141_bits_by; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_half; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_word; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_dword; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_load; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_store; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_unsign; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_dma; // @[lsu_lsc_ctl.scala 217:65] + reg _T_142; // @[lsu_lsc_ctl.scala 218:65] + reg _T_143; // @[lsu_lsc_ctl.scala 219:65] + wire [5:0] _T_146 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] + wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_146; // @[lsu_lsc_ctl.scala 221:66] + reg _T_154; // @[lsu_lsc_ctl.scala 224:48] + reg _T_156; // @[lsu_lsc_ctl.scala 224:110] + wire int_ = _T_154 != _T_156; // @[lsu_lsc_ctl.scala 224:72] + reg _T_158; // @[lsu_lsc_ctl.scala 225:48] + reg _T_160; // @[lsu_lsc_ctl.scala 225:110] + wire int1 = _T_158 != _T_160; // @[lsu_lsc_ctl.scala 225:72] + reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 226:72] + reg [31:0] _T_161; // @[lsu_lsc_ctl.scala 227:62] + reg [31:0] _T_162; // @[lsu_lsc_ctl.scala 228:62] + reg [28:0] end_addr_pre_m; // @[Reg.scala 27:20] + wire [28:0] _T_164 = int_ ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 229:27] + reg [2:0] _T_166; // @[lsu_lsc_ctl.scala 229:103] + reg [28:0] end_addr_pre_r; // @[Reg.scala 27:20] + wire [28:0] _T_169 = int1 ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 230:27] + reg [2:0] _T_171; // @[lsu_lsc_ctl.scala 230:104] + wire _T_174 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 231:69] + wire _T_175 = _T_174 | io_clk_override; // @[lsu_lsc_ctl.scala 231:87] + wire _T_179 = io_lsu_pkt_m_valid & int_; // @[lsu_lsc_ctl.scala 232:69] + wire _T_180 = _T_179 | io_clk_override; // @[lsu_lsc_ctl.scala 232:76] + reg _T_183; // @[lsu_lsc_ctl.scala 233:62] + reg _T_184; // @[lsu_lsc_ctl.scala 234:62] + reg _T_185; // @[lsu_lsc_ctl.scala 235:62] + reg _T_186; // @[lsu_lsc_ctl.scala 236:62] + reg _T_187; // @[lsu_lsc_ctl.scala 237:62] + reg addr_external_r; // @[lsu_lsc_ctl.scala 238:66] + wire _T_188 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 239:77] + reg [31:0] bus_read_data_r; // @[Reg.scala 27:20] + wire _T_191 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 246:68] + wire _T_192 = io_lsu_pkt_r_valid & _T_191; // @[lsu_lsc_ctl.scala 246:41] + wire _T_193 = ~io_flush_r; // @[lsu_lsc_ctl.scala 246:96] + wire _T_194 = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 246:94] + wire _T_195 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 246:110] + wire _T_198 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 247:69] + wire [31:0] _T_200 = _T_198 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_201 = io_picm_mask_data_m | _T_200; // @[lsu_lsc_ctl.scala 247:59] + wire [31:0] _T_203 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_exu_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 247:94] + wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 268:33] + wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 269:33] + wire _T_208 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 270:74] + wire [31:0] _T_210 = _T_208 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_213 = _T_210 & _T_212; // @[lsu_lsc_ctl.scala 270:102] + wire _T_214 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 271:43] + wire [31:0] _T_216 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_218 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_219 = _T_216 & _T_218; // @[lsu_lsc_ctl.scala 271:71] + wire [31:0] _T_220 = _T_213 | _T_219; // @[lsu_lsc_ctl.scala 270:141] + wire _T_221 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 272:17] + wire _T_222 = _T_221 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 272:43] + wire [31:0] _T_224 = _T_222 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_227 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = {_T_227,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_230 = _T_224 & _T_229; // @[lsu_lsc_ctl.scala 272:71] + wire [31:0] _T_231 = _T_220 | _T_230; // @[lsu_lsc_ctl.scala 271:114] + wire _T_233 = _T_221 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 273:43] + wire [31:0] _T_235 = _T_233 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_238 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_240 = {_T_238,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_241 = _T_235 & _T_240; // @[lsu_lsc_ctl.scala 273:71] + wire [31:0] _T_242 = _T_231 | _T_241; // @[lsu_lsc_ctl.scala 272:134] + wire [31:0] _T_244 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_244 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 274:43] + wire _T_248 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 275:66] + wire [31:0] _T_250 = _T_248 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_252 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_253 = _T_250 & _T_252; // @[lsu_lsc_ctl.scala 275:94] + wire _T_254 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 276:43] + wire [31:0] _T_256 = _T_254 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_258 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_259 = _T_256 & _T_258; // @[lsu_lsc_ctl.scala 276:71] + wire [31:0] _T_260 = _T_253 | _T_259; // @[lsu_lsc_ctl.scala 275:138] + wire _T_261 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 277:17] + wire _T_262 = _T_261 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 277:43] + wire [31:0] _T_264 = _T_262 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_267 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_269 = {_T_267,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_270 = _T_264 & _T_269; // @[lsu_lsc_ctl.scala 277:71] + wire [31:0] _T_271 = _T_260 | _T_270; // @[lsu_lsc_ctl.scala 276:119] + wire _T_273 = _T_261 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 278:43] + wire [31:0] _T_275 = _T_273 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_278 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = {_T_278,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_281 = _T_275 & _T_280; // @[lsu_lsc_ctl.scala 278:71] + wire [31:0] _T_282 = _T_271 | _T_281; // @[lsu_lsc_ctl.scala 277:144] + wire [31:0] _T_284 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_286 = _T_284 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 279:43] + lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 117:25] + .reset(addrcheck_reset), + .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk), + .io_start_addr_d(addrcheck_io_start_addr_d), + .io_end_addr_d(addrcheck_io_end_addr_d), + .io_lsu_pkt_d_valid(addrcheck_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_fast_int(addrcheck_io_lsu_pkt_d_bits_fast_int), + .io_lsu_pkt_d_bits_by(addrcheck_io_lsu_pkt_d_bits_by), + .io_lsu_pkt_d_bits_half(addrcheck_io_lsu_pkt_d_bits_half), + .io_lsu_pkt_d_bits_word(addrcheck_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_load(addrcheck_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(addrcheck_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_dma(addrcheck_io_lsu_pkt_d_bits_dma), + .io_dec_tlu_mrac_ff(addrcheck_io_dec_tlu_mrac_ff), + .io_rs1_region_d(addrcheck_io_rs1_region_d), + .io_is_sideeffects_m(addrcheck_io_is_sideeffects_m), + .io_addr_in_dccm_d(addrcheck_io_addr_in_dccm_d), + .io_addr_in_pic_d(addrcheck_io_addr_in_pic_d), + .io_addr_external_d(addrcheck_io_addr_external_d), + .io_access_fault_d(addrcheck_io_access_fault_d), + .io_misaligned_fault_d(addrcheck_io_misaligned_fault_d), + .io_exc_mscause_d(addrcheck_io_exc_mscause_d), + .io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d), + .io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d) + ); + rvclkhdr rvclkhdr ( // @[lib.scala 417:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + assign io_lsu_exu_lsu_result_m = _T_242 | _T_246; // @[lsu_lsc_ctl.scala 270:35] + assign io_lsu_result_corr_r = _T_282 | _T_286; // @[lsu_lsc_ctl.scala 275:27] + assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 244:28] + assign io_lsu_addr_m = _T_161; // @[lsu_lsc_ctl.scala 227:24] + assign io_lsu_addr_r = _T_162; // @[lsu_lsc_ctl.scala 228:24] + assign io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 114:24] + assign io_end_addr_m = {_T_164,_T_166}; // @[lsu_lsc_ctl.scala 229:17] + assign io_end_addr_r = {_T_169,_T_171}; // @[lsu_lsc_ctl.scala 230:17] + assign io_store_data_m = _T_201 & _T_203; // @[lsu_lsc_ctl.scala 247:29] + assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:16] + assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 127:42] + assign io_lsu_commit_r = _T_194 & _T_195; // @[lsu_lsc_ctl.scala 246:19] + assign io_lsu_single_ecc_error_incr = _T_74 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 155:32] + assign io_lsu_error_pkt_r_valid = _T_112; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 186:30] + assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_111; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 185:46] + assign io_lsu_error_pkt_r_bits_inst_type = _T_110_bits_inst_type; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_exc_type = _T_110_bits_exc_type; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_mscause = _T_110_bits_mscause; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_addr = _T_110_bits_addr; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 242:28] + assign io_lsu_fir_error = _T_113; // @[lsu_lsc_ctl.scala 187:38] + assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 128:42] + assign io_addr_in_dccm_m = _T_183; // @[lsu_lsc_ctl.scala 233:24] + assign io_addr_in_dccm_r = _T_184; // @[lsu_lsc_ctl.scala 234:24] + assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 129:42] + assign io_addr_in_pic_m = _T_185; // @[lsu_lsc_ctl.scala 235:24] + assign io_addr_in_pic_r = _T_186; // @[lsu_lsc_ctl.scala 236:24] + assign io_addr_external_m = _T_187; // @[lsu_lsc_ctl.scala 237:24] + assign io_lsu_pkt_d_valid = _T_128 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24] + assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_m_valid = _T_142; // @[lsu_lsc_ctl.scala 216:28 lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_m_bits_fast_int = _T_139_bits_fast_int; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_by = _T_139_bits_by; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_half = _T_139_bits_half; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_word = _T_139_bits_word; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_dword = _T_139_bits_dword; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_load = _T_139_bits_load; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store = _T_139_bits_store; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_unsign = _T_139_bits_unsign; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_dma = _T_139_bits_dma; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_139_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_valid = _T_143; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28] + assign io_lsu_pkt_r_bits_by = _T_141_bits_by; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_half = _T_141_bits_half; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_word = _T_141_bits_word; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_dword = _T_141_bits_dword; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_load = _T_141_bits_load; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store = _T_141_bits_store; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_unsign = _T_141_bits_unsign; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_dma = _T_141_bits_dma; // @[lsu_lsc_ctl.scala 217:28] + assign addrcheck_reset = reset; + assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_start_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 121:42] + assign addrcheck_io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 122:42] + assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 124:42] + assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[lsu_lsc_ctl.scala 125:42] + assign rvclkhdr_io_clk = clock; // @[lib.scala 419:18] + assign rvclkhdr_io_en = _T_105 | io_clk_override; // @[lib.scala 420:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_174 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_179 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + access_fault_m = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + misaligned_fault_m = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + exc_mscause_m = _RAND_2[3:0]; + _RAND_3 = {1{`RANDOM}}; + fir_dccm_access_error_m = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + fir_nondccm_access_error_m = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_110_bits_inst_type = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_110_bits_exc_type = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_110_bits_mscause = _RAND_7[3:0]; + _RAND_8 = {1{`RANDOM}}; + _T_110_bits_addr = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + _T_111 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + _T_112 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_113 = _RAND_11[1:0]; + _RAND_12 = {1{`RANDOM}}; + _T_139_bits_fast_int = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + _T_139_bits_by = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + _T_139_bits_half = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + _T_139_bits_word = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + _T_139_bits_dword = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + _T_139_bits_load = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + _T_139_bits_store = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + _T_139_bits_unsign = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + _T_139_bits_dma = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + _T_139_bits_store_data_bypass_m = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + _T_141_bits_by = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + _T_141_bits_half = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + _T_141_bits_word = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + _T_141_bits_dword = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + _T_141_bits_load = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + _T_141_bits_store = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + _T_141_bits_unsign = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + _T_141_bits_dma = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + _T_142 = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + _T_143 = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + _T_154 = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + _T_156 = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + _T_158 = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + _T_160 = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + store_data_pre_m = _RAND_36[31:0]; + _RAND_37 = {1{`RANDOM}}; + _T_161 = _RAND_37[31:0]; + _RAND_38 = {1{`RANDOM}}; + _T_162 = _RAND_38[31:0]; + _RAND_39 = {1{`RANDOM}}; + end_addr_pre_m = _RAND_39[28:0]; + _RAND_40 = {1{`RANDOM}}; + _T_166 = _RAND_40[2:0]; + _RAND_41 = {1{`RANDOM}}; + end_addr_pre_r = _RAND_41[28:0]; + _RAND_42 = {1{`RANDOM}}; + _T_171 = _RAND_42[2:0]; + _RAND_43 = {1{`RANDOM}}; + _T_183 = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + _T_184 = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + _T_185 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + _T_186 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + _T_187 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + addr_external_r = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + bus_read_data_r = _RAND_49[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + access_fault_m = 1'h0; + end + if (reset) begin + misaligned_fault_m = 1'h0; + end + if (reset) begin + exc_mscause_m = 4'h0; + end + if (reset) begin + fir_dccm_access_error_m = 1'h0; + end + if (reset) begin + fir_nondccm_access_error_m = 1'h0; + end + if (reset) begin + _T_110_bits_inst_type = 1'h0; + end + if (reset) begin + _T_110_bits_exc_type = 1'h0; + end + if (reset) begin + _T_110_bits_mscause = 4'h0; + end + if (reset) begin + _T_110_bits_addr = 32'h0; + end + if (reset) begin + _T_111 = 1'h0; + end + if (reset) begin + _T_112 = 1'h0; + end + if (reset) begin + _T_113 = 2'h0; + end + if (reset) begin + _T_139_bits_fast_int = 1'h0; + end + if (reset) begin + _T_139_bits_by = 1'h0; + end + if (reset) begin + _T_139_bits_half = 1'h0; + end + if (reset) begin + _T_139_bits_word = 1'h0; + end + if (reset) begin + _T_139_bits_dword = 1'h0; + end + if (reset) begin + _T_139_bits_load = 1'h0; + end + if (reset) begin + _T_139_bits_store = 1'h0; + end + if (reset) begin + _T_139_bits_unsign = 1'h0; + end + if (reset) begin + _T_139_bits_dma = 1'h0; + end + if (reset) begin + _T_139_bits_store_data_bypass_m = 1'h0; + end + if (reset) begin + _T_141_bits_by = 1'h0; + end + if (reset) begin + _T_141_bits_half = 1'h0; + end + if (reset) begin + _T_141_bits_word = 1'h0; + end + if (reset) begin + _T_141_bits_dword = 1'h0; + end + if (reset) begin + _T_141_bits_load = 1'h0; + end + if (reset) begin + _T_141_bits_store = 1'h0; + end + if (reset) begin + _T_141_bits_unsign = 1'h0; + end + if (reset) begin + _T_141_bits_dma = 1'h0; + end + if (reset) begin + _T_142 = 1'h0; + end + if (reset) begin + _T_143 = 1'h0; + end + if (reset) begin + _T_154 = 1'h0; + end + if (reset) begin + _T_156 = 1'h0; + end + if (reset) begin + _T_158 = 1'h0; + end + if (reset) begin + _T_160 = 1'h0; + end + if (reset) begin + store_data_pre_m = 32'h0; + end + if (reset) begin + _T_161 = 32'h0; + end + if (reset) begin + _T_162 = 32'h0; + end + if (reset) begin + end_addr_pre_m = 29'h0; + end + if (reset) begin + _T_166 = 3'h0; + end + if (reset) begin + end_addr_pre_r = 29'h0; + end + if (reset) begin + _T_171 = 3'h0; + end + if (reset) begin + _T_183 = 1'h0; + end + if (reset) begin + _T_184 = 1'h0; + end + if (reset) begin + _T_185 = 1'h0; + end + if (reset) begin + _T_186 = 1'h0; + end + if (reset) begin + _T_187 = 1'h0; + end + if (reset) begin + addr_external_r = 1'h0; + end + if (reset) begin + bus_read_data_r = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + access_fault_m <= 1'h0; + end else begin + access_fault_m <= addrcheck_io_access_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + misaligned_fault_m <= 1'h0; + end else begin + misaligned_fault_m <= addrcheck_io_misaligned_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + exc_mscause_m <= 4'h0; + end else begin + exc_mscause_m <= addrcheck_io_exc_mscause_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_dccm_access_error_m <= 1'h0; + end else begin + fir_dccm_access_error_m <= addrcheck_io_fir_dccm_access_error_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_nondccm_access_error_m <= 1'h0; + end else begin + fir_nondccm_access_error_m <= addrcheck_io_fir_nondccm_access_error_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_inst_type <= 1'h0; + end else if (_T_106) begin + _T_110_bits_inst_type <= io_lsu_pkt_m_bits_store; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_exc_type <= 1'h0; + end else if (_T_106) begin + _T_110_bits_exc_type <= lsu_error_pkt_m_bits_exc_type; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_mscause <= 4'h0; + end else if (_T_106) begin + if (_T_93) begin + _T_110_bits_mscause <= 4'h1; + end else begin + _T_110_bits_mscause <= exc_mscause_m; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_addr <= 32'h0; + end else if (_T_106) begin + _T_110_bits_addr <= io_lsu_addr_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_111 <= 1'h0; + end else begin + _T_111 <= _T_86 & _T_79; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_112 <= 1'h0; + end else begin + _T_112 <= _T_82 & _T_83; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_113 <= 2'h0; + end else if (fir_nondccm_access_error_m) begin + _T_113 <= 2'h3; + end else if (fir_dccm_access_error_m) begin + _T_113 <= 2'h2; + end else if (_T_100) begin + _T_113 <= 2'h1; + end else begin + _T_113 <= 2'h0; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_fast_int <= 1'h0; + end else begin + _T_139_bits_fast_int <= io_lsu_pkt_d_bits_fast_int; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_by <= 1'h0; + end else begin + _T_139_bits_by <= io_lsu_pkt_d_bits_by; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_half <= 1'h0; + end else begin + _T_139_bits_half <= io_lsu_pkt_d_bits_half; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_word <= 1'h0; + end else begin + _T_139_bits_word <= io_lsu_pkt_d_bits_word; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_dword <= 1'h0; + end else begin + _T_139_bits_dword <= io_lsu_pkt_d_bits_dword; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_load <= 1'h0; + end else begin + _T_139_bits_load <= io_lsu_pkt_d_bits_load; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_store <= 1'h0; + end else begin + _T_139_bits_store <= io_lsu_pkt_d_bits_store; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_unsign <= 1'h0; + end else begin + _T_139_bits_unsign <= io_lsu_pkt_d_bits_unsign; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_dma <= 1'h0; + end else begin + _T_139_bits_dma <= io_lsu_pkt_d_bits_dma; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_store_data_bypass_m <= 1'h0; + end else begin + _T_139_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_by <= 1'h0; + end else begin + _T_141_bits_by <= io_lsu_pkt_m_bits_by; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_half <= 1'h0; + end else begin + _T_141_bits_half <= io_lsu_pkt_m_bits_half; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_word <= 1'h0; + end else begin + _T_141_bits_word <= io_lsu_pkt_m_bits_word; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_dword <= 1'h0; + end else begin + _T_141_bits_dword <= io_lsu_pkt_m_bits_dword; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_load <= 1'h0; + end else begin + _T_141_bits_load <= io_lsu_pkt_m_bits_load; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_store <= 1'h0; + end else begin + _T_141_bits_store <= io_lsu_pkt_m_bits_store; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_unsign <= 1'h0; + end else begin + _T_141_bits_unsign <= io_lsu_pkt_m_bits_unsign; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_dma <= 1'h0; + end else begin + _T_141_bits_dma <= io_lsu_pkt_m_bits_dma; + end + end + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_142 <= 1'h0; + end else begin + _T_142 <= io_lsu_pkt_d_valid & _T_132; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_143 <= 1'h0; + end else begin + _T_143 <= io_lsu_pkt_m_valid & _T_136; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_154 <= 1'h0; + end else begin + _T_154 <= io_lsu_addr_d[2]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_156 <= 1'h0; + end else begin + _T_156 <= io_end_addr_d[2]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_158 <= 1'h0; + end else begin + _T_158 <= io_lsu_addr_m[2]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_160 <= 1'h0; + end else begin + _T_160 <= io_end_addr_m[2]; + end + end + always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin + if (reset) begin + store_data_pre_m <= 32'h0; + end else if (io_lsu_pkt_d_bits_store_data_bypass_d) begin + store_data_pre_m <= io_lsu_exu_lsu_result_m; + end else if (io_dma_lsc_ctl_dma_dccm_req) begin + store_data_pre_m <= dma_mem_wdata_shifted[31:0]; + end else begin + store_data_pre_m <= io_lsu_exu_exu_lsu_rs2_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_161 <= 32'h0; + end else begin + _T_161 <= io_lsu_addr_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_162 <= 32'h0; + end else begin + _T_162 <= io_lsu_addr_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + end_addr_pre_m <= 29'h0; + end else if (_T_175) begin + end_addr_pre_m <= io_end_addr_d[31:3]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_166 <= 3'h0; + end else begin + _T_166 <= io_end_addr_d[2:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + end_addr_pre_r <= 29'h0; + end else if (_T_180) begin + end_addr_pre_r <= io_end_addr_m[31:3]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_171 <= 3'h0; + end else begin + _T_171 <= io_end_addr_m[2:0]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_183 <= 1'h0; + end else begin + _T_183 <= io_addr_in_dccm_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_184 <= 1'h0; + end else begin + _T_184 <= io_addr_in_dccm_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_185 <= 1'h0; + end else begin + _T_185 <= io_addr_in_pic_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_186 <= 1'h0; + end else begin + _T_186 <= io_addr_in_pic_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_187 <= 1'h0; + end else begin + _T_187 <= addrcheck_io_addr_external_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + addr_external_r <= 1'h0; + end else begin + addr_external_r <= io_addr_external_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + bus_read_data_r <= 32'h0; + end else if (_T_188) begin + bus_read_data_r <= io_bus_read_data_m; + end + end +endmodule +module lsu_dccm_ctl( + input clock, + input reset, + input io_clk_override, + input io_lsu_c2_m_clk, + input io_lsu_free_c2_clk, + input io_lsu_store_c1_r_clk, + input io_lsu_pkt_d_valid, + input io_lsu_pkt_d_bits_word, + input io_lsu_pkt_d_bits_dword, + input io_lsu_pkt_d_bits_load, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_d_bits_dma, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_dma, + input io_addr_in_dccm_d, + input io_addr_in_dccm_m, + input io_addr_in_dccm_r, + input io_addr_in_pic_d, + input io_addr_in_pic_m, + input io_addr_in_pic_r, + input io_lsu_raw_fwd_lo_r, + input io_lsu_raw_fwd_hi_r, + input io_lsu_commit_r, + input io_ldst_dual_m, + input [31:0] io_lsu_addr_d, + input [15:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [15:0] io_end_addr_d, + input [15:0] io_end_addr_m, + input [15:0] io_end_addr_r, + input io_stbuf_reqvld_any, + input [15:0] io_stbuf_addr_any, + input [31:0] io_stbuf_data_any, + input [6:0] io_stbuf_ecc_any, + input [31:0] io_stbuf_fwddata_hi_m, + input [31:0] io_stbuf_fwddata_lo_m, + input [3:0] io_stbuf_fwdbyteen_lo_m, + input [3:0] io_stbuf_fwdbyteen_hi_m, + output [31:0] io_lsu_ld_data_corr_r, + input io_lsu_double_ecc_error_r, + input io_single_ecc_error_hi_r, + input io_single_ecc_error_lo_r, + input [31:0] io_sec_data_hi_r_ff, + input [31:0] io_sec_data_lo_r_ff, + input [6:0] io_sec_data_ecc_hi_r_ff, + input [6:0] io_sec_data_ecc_lo_r_ff, + output [31:0] io_dccm_rdata_hi_m, + output [31:0] io_dccm_rdata_lo_m, + output [6:0] io_dccm_data_ecc_hi_m, + output [6:0] io_dccm_data_ecc_lo_m, + output [31:0] io_lsu_ld_data_m, + input io_lsu_double_ecc_error_m, + input [31:0] io_sec_data_hi_m, + input [31:0] io_sec_data_lo_m, + input [31:0] io_store_data_m, + input io_dma_dccm_wen, + input io_dma_pic_wen, + input [2:0] io_dma_mem_tag_m, + input [31:0] io_dma_dccm_wdata_lo, + input [31:0] io_dma_dccm_wdata_hi, + input [6:0] io_dma_dccm_wdata_ecc_hi, + input [6:0] io_dma_dccm_wdata_ecc_lo, + output [31:0] io_store_data_hi_r, + output [31:0] io_store_data_lo_r, + output [31:0] io_store_datafn_hi_r, + output [31:0] io_store_datafn_lo_r, + output [31:0] io_store_data_r, + output io_ld_single_ecc_error_r, + output io_ld_single_ecc_error_r_ff, + output [31:0] io_picm_mask_data_m, + output io_lsu_stbuf_commit_any, + output io_lsu_dccm_rden_m, + input [31:0] io_dma_dccm_ctl_dma_mem_addr, + input [63:0] io_dma_dccm_ctl_dma_mem_wdata, + output io_dma_dccm_ctl_dccm_dma_rvalid, + output io_dma_dccm_ctl_dccm_dma_ecc_error, + output [2:0] io_dma_dccm_ctl_dccm_dma_rtag, + output [63:0] io_dma_dccm_ctl_dccm_dma_rdata, + output io_dccm_wren, + output io_dccm_rden, + output [15:0] io_dccm_wr_addr_lo, + output [15:0] io_dccm_wr_addr_hi, + output [15:0] io_dccm_rd_addr_lo, + output [15:0] io_dccm_rd_addr_hi, + output [38:0] io_dccm_wr_data_lo, + output [38:0] io_dccm_wr_data_hi, + input [38:0] io_dccm_rd_data_lo, + input [38:0] io_dccm_rd_data_hi, + output io_lsu_pic_picm_wren, + output io_lsu_pic_picm_rden, + output io_lsu_pic_picm_mken, + output [31:0] io_lsu_pic_picm_rdaddr, + output [31:0] io_lsu_pic_picm_wraddr, + output [31:0] io_lsu_pic_picm_wr_data, + input [31:0] io_lsu_pic_picm_rd_data +); +`ifdef RANDOMIZE_REG_INIT + reg [63:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire [63:0] picm_rd_data_m = {io_lsu_pic_picm_rd_data,io_lsu_pic_picm_rd_data}; // @[Cat.scala 29:58] + wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58] + wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58] + wire _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_load; // @[lsu_dccm_ctl.scala 145:63] + wire [7:0] _T_6 = {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m}; // @[Cat.scala 29:58] + wire [63:0] _T_9 = {io_stbuf_fwddata_hi_m,io_stbuf_fwddata_lo_m}; // @[Cat.scala 29:58] + wire [7:0] _T_14 = io_addr_in_dccm_m ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_16 = _T_14 & dccm_rdata_corr_m[7:0]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_17 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : _T_16; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_18 = _T_6[0] ? _T_9[7:0] : _T_17; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_22 = {{4'd0}, _T_18[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_24 = {_T_18[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_26 = _T_24 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_27 = _T_22 | _T_26; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_4 = {{2'd0}, _T_27[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_32 = _GEN_4 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_34 = {_T_27[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_36 = _T_34 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_37 = _T_32 | _T_36; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_5 = {{1'd0}, _T_37[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_42 = _GEN_5 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_44 = {_T_37[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_46 = _T_44 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_47 = _T_42 | _T_46; // @[Bitwise.scala 103:39] + wire [7:0] _T_58 = _T_14 & dccm_rdata_corr_m[15:8]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_59 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : _T_58; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_60 = _T_6[1] ? _T_9[15:8] : _T_59; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_64 = {{4'd0}, _T_60[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_66 = {_T_60[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_68 = _T_66 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_69 = _T_64 | _T_68; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_6 = {{2'd0}, _T_69[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_74 = _GEN_6 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_76 = {_T_69[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_78 = _T_76 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_79 = _T_74 | _T_78; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_7 = {{1'd0}, _T_79[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_84 = _GEN_7 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_86 = {_T_79[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_88 = _T_86 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_89 = _T_84 | _T_88; // @[Bitwise.scala 103:39] + wire [7:0] _T_100 = _T_14 & dccm_rdata_corr_m[23:16]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_101 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : _T_100; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_102 = _T_6[2] ? _T_9[23:16] : _T_101; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_106 = {{4'd0}, _T_102[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_108 = {_T_102[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_110 = _T_108 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_111 = _T_106 | _T_110; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_8 = {{2'd0}, _T_111[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_116 = _GEN_8 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_118 = {_T_111[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_120 = _T_118 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_121 = _T_116 | _T_120; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_9 = {{1'd0}, _T_121[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_126 = _GEN_9 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_128 = {_T_121[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_130 = _T_128 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_131 = _T_126 | _T_130; // @[Bitwise.scala 103:39] + wire [7:0] _T_142 = _T_14 & dccm_rdata_corr_m[31:24]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_143 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : _T_142; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_144 = _T_6[3] ? _T_9[31:24] : _T_143; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_148 = {{4'd0}, _T_144[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_150 = {_T_144[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_152 = _T_150 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_153 = _T_148 | _T_152; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_10 = {{2'd0}, _T_153[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_158 = _GEN_10 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_160 = {_T_153[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_162 = _T_160 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_163 = _T_158 | _T_162; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_11 = {{1'd0}, _T_163[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_168 = _GEN_11 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_170 = {_T_163[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_172 = _T_170 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_173 = _T_168 | _T_172; // @[Bitwise.scala 103:39] + wire [7:0] _T_184 = _T_14 & dccm_rdata_corr_m[39:32]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_185 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : _T_184; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_186 = _T_6[4] ? _T_9[39:32] : _T_185; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_190 = {{4'd0}, _T_186[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_192 = {_T_186[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_194 = _T_192 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_195 = _T_190 | _T_194; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_12 = {{2'd0}, _T_195[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_200 = _GEN_12 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_202 = {_T_195[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_204 = _T_202 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_205 = _T_200 | _T_204; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_13 = {{1'd0}, _T_205[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_210 = _GEN_13 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_212 = {_T_205[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_214 = _T_212 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_215 = _T_210 | _T_214; // @[Bitwise.scala 103:39] + wire [7:0] _T_226 = _T_14 & dccm_rdata_corr_m[47:40]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_227 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : _T_226; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_228 = _T_6[5] ? _T_9[47:40] : _T_227; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_232 = {{4'd0}, _T_228[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_234 = {_T_228[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_236 = _T_234 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_237 = _T_232 | _T_236; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_14 = {{2'd0}, _T_237[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_242 = _GEN_14 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_244 = {_T_237[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_246 = _T_244 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_247 = _T_242 | _T_246; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_15 = {{1'd0}, _T_247[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_252 = _GEN_15 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_254 = {_T_247[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_256 = _T_254 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_257 = _T_252 | _T_256; // @[Bitwise.scala 103:39] + wire [7:0] _T_268 = _T_14 & dccm_rdata_corr_m[55:48]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_269 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : _T_268; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_270 = _T_6[6] ? _T_9[55:48] : _T_269; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_274 = {{4'd0}, _T_270[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_276 = {_T_270[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_278 = _T_276 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_279 = _T_274 | _T_278; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_16 = {{2'd0}, _T_279[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_284 = _GEN_16 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_286 = {_T_279[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_288 = _T_286 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_289 = _T_284 | _T_288; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_17 = {{1'd0}, _T_289[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_294 = _GEN_17 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_296 = {_T_289[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_298 = _T_296 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_299 = _T_294 | _T_298; // @[Bitwise.scala 103:39] + wire [7:0] _T_310 = _T_14 & dccm_rdata_corr_m[63:56]; // @[lsu_dccm_ctl.scala 155:294] + wire [7:0] _T_311 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : _T_310; // @[lsu_dccm_ctl.scala 155:214] + wire [7:0] _T_312 = _T_6[7] ? _T_9[63:56] : _T_311; // @[lsu_dccm_ctl.scala 155:78] + wire [7:0] _T_316 = {{4'd0}, _T_312[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_318 = {_T_312[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_320 = _T_318 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_321 = _T_316 | _T_320; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_18 = {{2'd0}, _T_321[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_326 = _GEN_18 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_328 = {_T_321[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_330 = _T_328 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_331 = _T_326 | _T_330; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_19 = {{1'd0}, _T_331[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_336 = _GEN_19 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_338 = {_T_331[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_340 = _T_338 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_341 = _T_336 | _T_340; // @[Bitwise.scala 103:39] + wire [63:0] _T_349 = {_T_47,_T_89,_T_131,_T_173,_T_215,_T_257,_T_299,_T_341}; // @[Cat.scala 29:58] + wire [63:0] _T_353 = {{32'd0}, _T_349[63:32]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_355 = {_T_349[31:0], 32'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_357 = _T_355 & 64'hffffffff00000000; // @[Bitwise.scala 103:75] + wire [63:0] _T_358 = _T_353 | _T_357; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_20 = {{16'd0}, _T_358[63:16]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_363 = _GEN_20 & 64'hffff0000ffff; // @[Bitwise.scala 103:31] + wire [63:0] _T_365 = {_T_358[47:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_367 = _T_365 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75] + wire [63:0] _T_368 = _T_363 | _T_367; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_21 = {{8'd0}, _T_368[63:8]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_373 = _GEN_21 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31] + wire [63:0] _T_375 = {_T_368[55:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_377 = _T_375 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75] + wire [63:0] _T_378 = _T_373 | _T_377; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_22 = {{4'd0}, _T_378[63:4]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_383 = _GEN_22 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31] + wire [63:0] _T_385 = {_T_378[59:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_387 = _T_385 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75] + wire [63:0] _T_388 = _T_383 | _T_387; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_23 = {{2'd0}, _T_388[63:2]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_393 = _GEN_23 & 64'h3333333333333333; // @[Bitwise.scala 103:31] + wire [63:0] _T_395 = {_T_388[61:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_397 = _T_395 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75] + wire [63:0] _T_398 = _T_393 | _T_397; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_24 = {{1'd0}, _T_398[63:1]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_403 = _GEN_24 & 64'h5555555555555555; // @[Bitwise.scala 103:31] + wire [63:0] _T_405 = {_T_398[62:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_407 = _T_405 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] lsu_rdata_corr_m = _T_403 | _T_407; // @[Bitwise.scala 103:39] + wire [63:0] _T_4 = {lsu_rdata_corr_m[31:0],lsu_rdata_corr_m[31:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_419 = _T_14 & dccm_rdata_m[7:0]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_420 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : _T_419; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_421 = _T_6[0] ? _T_9[7:0] : _T_420; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_425 = {{4'd0}, _T_421[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_427 = {_T_421[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_429 = _T_427 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_430 = _T_425 | _T_429; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_25 = {{2'd0}, _T_430[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_435 = _GEN_25 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_437 = {_T_430[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_439 = _T_437 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_440 = _T_435 | _T_439; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_26 = {{1'd0}, _T_440[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_445 = _GEN_26 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_447 = {_T_440[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_449 = _T_447 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_450 = _T_445 | _T_449; // @[Bitwise.scala 103:39] + wire [7:0] _T_461 = _T_14 & dccm_rdata_m[15:8]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_462 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : _T_461; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_463 = _T_6[1] ? _T_9[15:8] : _T_462; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_467 = {{4'd0}, _T_463[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_469 = {_T_463[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_471 = _T_469 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_472 = _T_467 | _T_471; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_27 = {{2'd0}, _T_472[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_477 = _GEN_27 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_479 = {_T_472[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_481 = _T_479 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_482 = _T_477 | _T_481; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_28 = {{1'd0}, _T_482[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_487 = _GEN_28 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_489 = {_T_482[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_491 = _T_489 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_492 = _T_487 | _T_491; // @[Bitwise.scala 103:39] + wire [7:0] _T_503 = _T_14 & dccm_rdata_m[23:16]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_504 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : _T_503; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_505 = _T_6[2] ? _T_9[23:16] : _T_504; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_509 = {{4'd0}, _T_505[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_511 = {_T_505[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_513 = _T_511 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_514 = _T_509 | _T_513; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_29 = {{2'd0}, _T_514[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_519 = _GEN_29 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_521 = {_T_514[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_523 = _T_521 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_524 = _T_519 | _T_523; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_30 = {{1'd0}, _T_524[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_529 = _GEN_30 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_531 = {_T_524[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_533 = _T_531 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_534 = _T_529 | _T_533; // @[Bitwise.scala 103:39] + wire [7:0] _T_545 = _T_14 & dccm_rdata_m[31:24]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_546 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : _T_545; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_547 = _T_6[3] ? _T_9[31:24] : _T_546; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_551 = {{4'd0}, _T_547[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_553 = {_T_547[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_555 = _T_553 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_556 = _T_551 | _T_555; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_31 = {{2'd0}, _T_556[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_561 = _GEN_31 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_563 = {_T_556[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_565 = _T_563 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_566 = _T_561 | _T_565; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_32 = {{1'd0}, _T_566[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_571 = _GEN_32 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_573 = {_T_566[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_575 = _T_573 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_576 = _T_571 | _T_575; // @[Bitwise.scala 103:39] + wire [7:0] _T_587 = _T_14 & dccm_rdata_m[39:32]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_588 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : _T_587; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_589 = _T_6[4] ? _T_9[39:32] : _T_588; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_593 = {{4'd0}, _T_589[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_595 = {_T_589[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_597 = _T_595 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_598 = _T_593 | _T_597; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_33 = {{2'd0}, _T_598[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_603 = _GEN_33 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_605 = {_T_598[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_607 = _T_605 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_608 = _T_603 | _T_607; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_34 = {{1'd0}, _T_608[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_613 = _GEN_34 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_615 = {_T_608[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_617 = _T_615 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_618 = _T_613 | _T_617; // @[Bitwise.scala 103:39] + wire [7:0] _T_629 = _T_14 & dccm_rdata_m[47:40]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_630 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : _T_629; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_631 = _T_6[5] ? _T_9[47:40] : _T_630; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_635 = {{4'd0}, _T_631[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_637 = {_T_631[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_639 = _T_637 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_640 = _T_635 | _T_639; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_35 = {{2'd0}, _T_640[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_645 = _GEN_35 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_647 = {_T_640[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_649 = _T_647 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_650 = _T_645 | _T_649; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_36 = {{1'd0}, _T_650[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_655 = _GEN_36 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_657 = {_T_650[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_659 = _T_657 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_660 = _T_655 | _T_659; // @[Bitwise.scala 103:39] + wire [7:0] _T_671 = _T_14 & dccm_rdata_m[55:48]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_672 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : _T_671; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_673 = _T_6[6] ? _T_9[55:48] : _T_672; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_677 = {{4'd0}, _T_673[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_679 = {_T_673[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_681 = _T_679 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_682 = _T_677 | _T_681; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_37 = {{2'd0}, _T_682[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_687 = _GEN_37 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_689 = {_T_682[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_691 = _T_689 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_692 = _T_687 | _T_691; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_38 = {{1'd0}, _T_692[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_697 = _GEN_38 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_699 = {_T_692[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_701 = _T_699 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_702 = _T_697 | _T_701; // @[Bitwise.scala 103:39] + wire [7:0] _T_713 = _T_14 & dccm_rdata_m[63:56]; // @[lsu_dccm_ctl.scala 156:294] + wire [7:0] _T_714 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : _T_713; // @[lsu_dccm_ctl.scala 156:214] + wire [7:0] _T_715 = _T_6[7] ? _T_9[63:56] : _T_714; // @[lsu_dccm_ctl.scala 156:78] + wire [7:0] _T_719 = {{4'd0}, _T_715[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_721 = {_T_715[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_723 = _T_721 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_724 = _T_719 | _T_723; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_39 = {{2'd0}, _T_724[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_729 = _GEN_39 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_731 = {_T_724[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_733 = _T_731 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_734 = _T_729 | _T_733; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_40 = {{1'd0}, _T_734[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_739 = _GEN_40 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_741 = {_T_734[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_743 = _T_741 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_744 = _T_739 | _T_743; // @[Bitwise.scala 103:39] + wire [63:0] _T_752 = {_T_450,_T_492,_T_534,_T_576,_T_618,_T_660,_T_702,_T_744}; // @[Cat.scala 29:58] + wire [63:0] _T_756 = {{32'd0}, _T_752[63:32]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_758 = {_T_752[31:0], 32'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_760 = _T_758 & 64'hffffffff00000000; // @[Bitwise.scala 103:75] + wire [63:0] _T_761 = _T_756 | _T_760; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_41 = {{16'd0}, _T_761[63:16]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_766 = _GEN_41 & 64'hffff0000ffff; // @[Bitwise.scala 103:31] + wire [63:0] _T_768 = {_T_761[47:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_770 = _T_768 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75] + wire [63:0] _T_771 = _T_766 | _T_770; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_42 = {{8'd0}, _T_771[63:8]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_776 = _GEN_42 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31] + wire [63:0] _T_778 = {_T_771[55:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_780 = _T_778 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75] + wire [63:0] _T_781 = _T_776 | _T_780; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_43 = {{4'd0}, _T_781[63:4]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_786 = _GEN_43 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31] + wire [63:0] _T_788 = {_T_781[59:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_790 = _T_788 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75] + wire [63:0] _T_791 = _T_786 | _T_790; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_44 = {{2'd0}, _T_791[63:2]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_796 = _GEN_44 & 64'h3333333333333333; // @[Bitwise.scala 103:31] + wire [63:0] _T_798 = {_T_791[61:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_800 = _T_798 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75] + wire [63:0] _T_801 = _T_796 | _T_800; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_45 = {{1'd0}, _T_801[63:1]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_806 = _GEN_45 & 64'h5555555555555555; // @[Bitwise.scala 103:31] + wire [63:0] _T_808 = {_T_801[62:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_810 = _T_808 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] lsu_rdata_m = _T_806 | _T_810; // @[Bitwise.scala 103:39] + wire _T_813 = io_addr_in_pic_m | io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 157:123] + wire _T_814 = _T & _T_813; // @[lsu_dccm_ctl.scala 157:103] + wire _T_815 = _T_814 | io_clk_override; // @[lsu_dccm_ctl.scala 157:145] + reg [63:0] _T_818; // @[Reg.scala 27:20] + wire [3:0] _GEN_46 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_dccm_ctl.scala 159:54] + wire [5:0] _T_823 = 4'h8 * _GEN_46; // @[lsu_dccm_ctl.scala 159:54] + wire [63:0] lsu_ld_data_corr_m = lsu_rdata_corr_m >> _T_823; // @[lsu_dccm_ctl.scala 159:48] + wire [63:0] _T_821 = lsu_rdata_m >> _T_823; // @[lsu_dccm_ctl.scala 158:43] + wire _T_827 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:60] + wire _T_830 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:133] + wire _T_831 = _T_827 | _T_830; // @[lsu_dccm_ctl.scala 163:101] + wire _T_832 = _T_831 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 163:175] + wire _T_833 = _T_832 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 163:196] + wire _T_834 = _T_833 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 163:222] + wire _T_835 = _T_834 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 163:246] + wire _T_838 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:37] + wire _T_841 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:110] + wire _T_842 = _T_838 | _T_841; // @[lsu_dccm_ctl.scala 164:78] + wire _T_843 = _T_842 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 164:152] + wire _T_844 = _T_843 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 164:173] + wire _T_845 = _T_844 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 164:199] + wire _T_846 = _T_845 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 164:223] + wire kill_ecc_corr_lo_r = _T_835 | _T_846; // @[lsu_dccm_ctl.scala 163:267] + wire _T_849 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:60] + wire _T_852 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:133] + wire _T_853 = _T_849 | _T_852; // @[lsu_dccm_ctl.scala 166:101] + wire _T_854 = _T_853 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 166:175] + wire _T_855 = _T_854 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 166:196] + wire _T_856 = _T_855 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 166:222] + wire _T_857 = _T_856 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 166:246] + wire _T_860 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:37] + wire _T_863 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:110] + wire _T_864 = _T_860 | _T_863; // @[lsu_dccm_ctl.scala 167:78] + wire _T_865 = _T_864 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 167:152] + wire _T_866 = _T_865 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 167:173] + wire _T_867 = _T_866 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 167:199] + wire _T_868 = _T_867 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 167:223] + wire kill_ecc_corr_hi_r = _T_857 | _T_868; // @[lsu_dccm_ctl.scala 166:267] + wire _T_869 = io_lsu_pkt_r_bits_load & io_single_ecc_error_lo_r; // @[lsu_dccm_ctl.scala 169:60] + wire _T_870 = ~io_lsu_raw_fwd_lo_r; // @[lsu_dccm_ctl.scala 169:89] + wire ld_single_ecc_error_lo_r = _T_869 & _T_870; // @[lsu_dccm_ctl.scala 169:87] + wire _T_871 = io_lsu_pkt_r_bits_load & io_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 170:60] + wire _T_872 = ~io_lsu_raw_fwd_hi_r; // @[lsu_dccm_ctl.scala 170:89] + wire ld_single_ecc_error_hi_r = _T_871 & _T_872; // @[lsu_dccm_ctl.scala 170:87] + wire _T_873 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 171:63] + wire _T_874 = ~io_lsu_double_ecc_error_r; // @[lsu_dccm_ctl.scala 171:93] + wire _T_876 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_dccm_ctl.scala 172:81] + wire _T_877 = ld_single_ecc_error_lo_r & _T_876; // @[lsu_dccm_ctl.scala 172:62] + wire _T_878 = ~kill_ecc_corr_lo_r; // @[lsu_dccm_ctl.scala 172:108] + wire _T_880 = ld_single_ecc_error_hi_r & _T_876; // @[lsu_dccm_ctl.scala 173:62] + wire _T_881 = ~kill_ecc_corr_hi_r; // @[lsu_dccm_ctl.scala 173:108] + wire _T_882 = io_lsu_pkt_d_bits_word | io_lsu_pkt_d_bits_dword; // @[lsu_dccm_ctl.scala 175:125] + wire _T_883 = ~_T_882; // @[lsu_dccm_ctl.scala 175:100] + wire _T_885 = io_lsu_addr_d[1:0] != 2'h0; // @[lsu_dccm_ctl.scala 175:174] + wire _T_886 = _T_883 | _T_885; // @[lsu_dccm_ctl.scala 175:152] + wire _T_887 = io_lsu_pkt_d_bits_store & _T_886; // @[lsu_dccm_ctl.scala 175:97] + wire _T_888 = io_lsu_pkt_d_bits_load | _T_887; // @[lsu_dccm_ctl.scala 175:70] + wire _T_889 = io_lsu_pkt_d_valid & _T_888; // @[lsu_dccm_ctl.scala 175:44] + wire lsu_dccm_rden_d = _T_889 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 175:191] + reg ld_single_ecc_error_lo_r_ff; // @[lsu_dccm_ctl.scala 284:73] + reg ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 283:73] + wire _T_890 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 178:63] + reg lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 282:73] + wire _T_891 = ~lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 178:96] + wire _T_893 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[lsu_dccm_ctl.scala 179:75] + wire _T_894 = _T_893 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 179:93] + wire _T_895 = ~_T_894; // @[lsu_dccm_ctl.scala 179:57] + wire _T_898 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[lsu_dccm_ctl.scala 180:95] + wire _T_901 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[lsu_dccm_ctl.scala 181:76] + wire _T_902 = _T_898 | _T_901; // @[lsu_dccm_ctl.scala 180:171] + wire _T_903 = ~_T_902; // @[lsu_dccm_ctl.scala 180:24] + wire _T_904 = lsu_dccm_rden_d & _T_903; // @[lsu_dccm_ctl.scala 180:22] + wire _T_905 = _T_895 | _T_904; // @[lsu_dccm_ctl.scala 179:124] + wire _T_907 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[lsu_dccm_ctl.scala 185:41] + reg [15:0] ld_sec_addr_lo_r_ff; // @[Reg.scala 27:20] + reg [15:0] ld_sec_addr_hi_r_ff; // @[Reg.scala 27:20] + wire [15:0] _T_914 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[lsu_dccm_ctl.scala 189:8] + wire [15:0] _T_918 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 190:8] + wire [15:0] _T_924 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[lsu_dccm_ctl.scala 193:8] + wire [15:0] _T_928 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 194:8] + wire [38:0] _T_936 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58] + wire [38:0] _T_939 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58] + wire [38:0] _T_940 = ld_single_ecc_error_lo_r_ff ? _T_936 : _T_939; // @[lsu_dccm_ctl.scala 200:8] + wire [38:0] _T_944 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58] + wire [38:0] _T_947 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58] + wire [38:0] _T_948 = io_dma_dccm_wen ? _T_944 : _T_947; // @[lsu_dccm_ctl.scala 202:8] + wire [38:0] _T_958 = ld_single_ecc_error_hi_r_ff ? _T_939 : _T_936; // @[lsu_dccm_ctl.scala 206:8] + wire [38:0] _T_962 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58] + wire [38:0] _T_966 = io_dma_dccm_wen ? _T_962 : _T_947; // @[lsu_dccm_ctl.scala 208:8] + wire [3:0] _T_969 = io_lsu_pkt_m_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_971 = io_lsu_pkt_m_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_972 = _T_971 & 4'h1; // @[lsu_dccm_ctl.scala 212:94] + wire [3:0] _T_974 = io_lsu_pkt_m_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_975 = _T_974 & 4'h3; // @[lsu_dccm_ctl.scala 213:38] + wire [3:0] _T_976 = _T_972 | _T_975; // @[lsu_dccm_ctl.scala 212:107] + wire [3:0] _T_978 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_980 = _T_976 | _T_978; // @[lsu_dccm_ctl.scala 213:51] + wire [3:0] store_byteen_m = _T_969 & _T_980; // @[lsu_dccm_ctl.scala 212:58] + wire [3:0] _T_982 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_984 = io_lsu_pkt_r_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_985 = _T_984 & 4'h1; // @[lsu_dccm_ctl.scala 216:94] + wire [3:0] _T_987 = io_lsu_pkt_r_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_988 = _T_987 & 4'h3; // @[lsu_dccm_ctl.scala 217:38] + wire [3:0] _T_989 = _T_985 | _T_988; // @[lsu_dccm_ctl.scala 216:107] + wire [3:0] _T_991 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_993 = _T_989 | _T_991; // @[lsu_dccm_ctl.scala 217:51] + wire [3:0] store_byteen_r = _T_982 & _T_993; // @[lsu_dccm_ctl.scala 216:58] + wire [6:0] _GEN_48 = {{3'd0}, store_byteen_m}; // @[lsu_dccm_ctl.scala 220:45] + wire [6:0] _T_996 = _GEN_48 << io_lsu_addr_m[1:0]; // @[lsu_dccm_ctl.scala 220:45] + wire [6:0] _GEN_49 = {{3'd0}, store_byteen_r}; // @[lsu_dccm_ctl.scala 222:45] + wire [6:0] _T_999 = _GEN_49 << io_lsu_addr_r[1:0]; // @[lsu_dccm_ctl.scala 222:45] + wire _T_1002 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[lsu_dccm_ctl.scala 225:67] + wire dccm_wr_bypass_d_m_lo = _T_1002 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 225:101] + wire _T_1005 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[lsu_dccm_ctl.scala 226:67] + wire dccm_wr_bypass_d_m_hi = _T_1005 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 226:101] + wire _T_1008 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 228:67] + wire dccm_wr_bypass_d_r_lo = _T_1008 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 228:101] + wire _T_1011 = io_stbuf_addr_any[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 229:67] + wire dccm_wr_bypass_d_r_hi = _T_1011 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 229:101] + wire [63:0] _T_1014 = {32'h0,io_store_data_m}; // @[Cat.scala 29:58] + wire [126:0] _GEN_51 = {{63'd0}, _T_1014}; // @[lsu_dccm_ctl.scala 258:72] + wire [126:0] _T_1017 = _GEN_51 << _T_823; // @[lsu_dccm_ctl.scala 258:72] + wire [63:0] store_data_pre_m = _T_1017[63:0]; // @[lsu_dccm_ctl.scala 258:29] + wire [31:0] store_data_hi_m = store_data_pre_m[63:32]; // @[lsu_dccm_ctl.scala 259:48] + wire [31:0] store_data_lo_m = store_data_pre_m[31:0]; // @[lsu_dccm_ctl.scala 260:48] + wire [7:0] store_byteen_ext_m = {{1'd0}, _T_996}; // @[lsu_dccm_ctl.scala 220:22] + wire _T_1023 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo; // @[lsu_dccm_ctl.scala 261:211] + wire [7:0] _T_1027 = _T_1023 ? io_stbuf_data_any[7:0] : io_sec_data_lo_m[7:0]; // @[lsu_dccm_ctl.scala 261:185] + wire [7:0] _T_1028 = store_byteen_ext_m[0] ? store_data_lo_m[7:0] : _T_1027; // @[lsu_dccm_ctl.scala 261:120] + wire [7:0] _T_1032 = {{4'd0}, _T_1028[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1034 = {_T_1028[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1036 = _T_1034 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1037 = _T_1032 | _T_1036; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_52 = {{2'd0}, _T_1037[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1042 = _GEN_52 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1044 = {_T_1037[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1046 = _T_1044 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1047 = _T_1042 | _T_1046; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_53 = {{1'd0}, _T_1047[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1052 = _GEN_53 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1054 = {_T_1047[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1056 = _T_1054 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1057 = _T_1052 | _T_1056; // @[Bitwise.scala 103:39] + wire [7:0] _T_1065 = _T_1023 ? io_stbuf_data_any[15:8] : io_sec_data_lo_m[15:8]; // @[lsu_dccm_ctl.scala 261:185] + wire [7:0] _T_1066 = store_byteen_ext_m[1] ? store_data_lo_m[15:8] : _T_1065; // @[lsu_dccm_ctl.scala 261:120] + wire [7:0] _T_1070 = {{4'd0}, _T_1066[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1072 = {_T_1066[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1074 = _T_1072 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1075 = _T_1070 | _T_1074; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_54 = {{2'd0}, _T_1075[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1080 = _GEN_54 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1082 = {_T_1075[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1084 = _T_1082 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1085 = _T_1080 | _T_1084; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_55 = {{1'd0}, _T_1085[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1090 = _GEN_55 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1092 = {_T_1085[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1094 = _T_1092 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1095 = _T_1090 | _T_1094; // @[Bitwise.scala 103:39] + wire [7:0] _T_1103 = _T_1023 ? io_stbuf_data_any[23:16] : io_sec_data_lo_m[23:16]; // @[lsu_dccm_ctl.scala 261:185] + wire [7:0] _T_1104 = store_byteen_ext_m[2] ? store_data_lo_m[23:16] : _T_1103; // @[lsu_dccm_ctl.scala 261:120] + wire [7:0] _T_1108 = {{4'd0}, _T_1104[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1110 = {_T_1104[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1112 = _T_1110 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1113 = _T_1108 | _T_1112; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_56 = {{2'd0}, _T_1113[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1118 = _GEN_56 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1120 = {_T_1113[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1122 = _T_1120 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1123 = _T_1118 | _T_1122; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_57 = {{1'd0}, _T_1123[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1128 = _GEN_57 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1130 = {_T_1123[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1132 = _T_1130 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1133 = _T_1128 | _T_1132; // @[Bitwise.scala 103:39] + wire [7:0] _T_1141 = _T_1023 ? io_stbuf_data_any[31:24] : io_sec_data_lo_m[31:24]; // @[lsu_dccm_ctl.scala 261:185] + wire [7:0] _T_1142 = store_byteen_ext_m[3] ? store_data_lo_m[31:24] : _T_1141; // @[lsu_dccm_ctl.scala 261:120] + wire [7:0] _T_1146 = {{4'd0}, _T_1142[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1148 = {_T_1142[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1150 = _T_1148 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1151 = _T_1146 | _T_1150; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_58 = {{2'd0}, _T_1151[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1156 = _GEN_58 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1158 = {_T_1151[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1160 = _T_1158 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1161 = _T_1156 | _T_1160; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_59 = {{1'd0}, _T_1161[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1166 = _GEN_59 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1168 = {_T_1161[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1170 = _T_1168 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1171 = _T_1166 | _T_1170; // @[Bitwise.scala 103:39] + wire [31:0] _T_1175 = {_T_1057,_T_1095,_T_1133,_T_1171}; // @[Cat.scala 29:58] + wire [31:0] _T_1179 = {{16'd0}, _T_1175[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1181 = {_T_1175[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1183 = _T_1181 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1184 = _T_1179 | _T_1183; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_60 = {{8'd0}, _T_1184[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1189 = _GEN_60 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1191 = {_T_1184[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1193 = _T_1191 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1194 = _T_1189 | _T_1193; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_61 = {{4'd0}, _T_1194[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1199 = _GEN_61 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1201 = {_T_1194[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1203 = _T_1201 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1204 = _T_1199 | _T_1203; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_62 = {{2'd0}, _T_1204[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1209 = _GEN_62 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1211 = {_T_1204[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1213 = _T_1211 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1214 = _T_1209 | _T_1213; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_63 = {{1'd0}, _T_1214[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1219 = _GEN_63 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1221 = {_T_1214[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1223 = _T_1221 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + reg [31:0] _T_1225; // @[lsu_dccm_ctl.scala 261:72] + wire _T_1229 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi; // @[lsu_dccm_ctl.scala 262:177] + wire [7:0] _T_1233 = _T_1229 ? io_stbuf_data_any[7:0] : io_sec_data_hi_m[7:0]; // @[lsu_dccm_ctl.scala 262:151] + wire [7:0] _T_1234 = store_byteen_ext_m[4] ? store_data_hi_m[7:0] : _T_1233; // @[lsu_dccm_ctl.scala 262:86] + wire [7:0] _T_1238 = {{4'd0}, _T_1234[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1240 = {_T_1234[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1242 = _T_1240 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1243 = _T_1238 | _T_1242; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_64 = {{2'd0}, _T_1243[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1248 = _GEN_64 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1250 = {_T_1243[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1252 = _T_1250 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1253 = _T_1248 | _T_1252; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_65 = {{1'd0}, _T_1253[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1258 = _GEN_65 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1260 = {_T_1253[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1262 = _T_1260 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1263 = _T_1258 | _T_1262; // @[Bitwise.scala 103:39] + wire [7:0] _T_1271 = _T_1229 ? io_stbuf_data_any[15:8] : io_sec_data_hi_m[15:8]; // @[lsu_dccm_ctl.scala 262:151] + wire [7:0] _T_1272 = store_byteen_ext_m[5] ? store_data_hi_m[15:8] : _T_1271; // @[lsu_dccm_ctl.scala 262:86] + wire [7:0] _T_1276 = {{4'd0}, _T_1272[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1278 = {_T_1272[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1280 = _T_1278 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1281 = _T_1276 | _T_1280; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_66 = {{2'd0}, _T_1281[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1286 = _GEN_66 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1288 = {_T_1281[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1290 = _T_1288 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1291 = _T_1286 | _T_1290; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_67 = {{1'd0}, _T_1291[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1296 = _GEN_67 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1298 = {_T_1291[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1300 = _T_1298 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1301 = _T_1296 | _T_1300; // @[Bitwise.scala 103:39] + wire [7:0] _T_1309 = _T_1229 ? io_stbuf_data_any[23:16] : io_sec_data_hi_m[23:16]; // @[lsu_dccm_ctl.scala 262:151] + wire [7:0] _T_1310 = store_byteen_ext_m[6] ? store_data_hi_m[23:16] : _T_1309; // @[lsu_dccm_ctl.scala 262:86] + wire [7:0] _T_1314 = {{4'd0}, _T_1310[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1316 = {_T_1310[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1318 = _T_1316 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1319 = _T_1314 | _T_1318; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_68 = {{2'd0}, _T_1319[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1324 = _GEN_68 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1326 = {_T_1319[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1328 = _T_1326 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1329 = _T_1324 | _T_1328; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_69 = {{1'd0}, _T_1329[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1334 = _GEN_69 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1336 = {_T_1329[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1338 = _T_1336 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1339 = _T_1334 | _T_1338; // @[Bitwise.scala 103:39] + wire [7:0] _T_1347 = _T_1229 ? io_stbuf_data_any[31:24] : io_sec_data_hi_m[31:24]; // @[lsu_dccm_ctl.scala 262:151] + wire [7:0] _T_1348 = store_byteen_ext_m[7] ? store_data_hi_m[31:24] : _T_1347; // @[lsu_dccm_ctl.scala 262:86] + wire [7:0] _T_1352 = {{4'd0}, _T_1348[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1354 = {_T_1348[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1356 = _T_1354 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1357 = _T_1352 | _T_1356; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_70 = {{2'd0}, _T_1357[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1362 = _GEN_70 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1364 = {_T_1357[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1366 = _T_1364 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1367 = _T_1362 | _T_1366; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_71 = {{1'd0}, _T_1367[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1372 = _GEN_71 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1374 = {_T_1367[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1376 = _T_1374 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1377 = _T_1372 | _T_1376; // @[Bitwise.scala 103:39] + wire [31:0] _T_1381 = {_T_1263,_T_1301,_T_1339,_T_1377}; // @[Cat.scala 29:58] + wire [31:0] _T_1385 = {{16'd0}, _T_1381[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1387 = {_T_1381[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1389 = _T_1387 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1390 = _T_1385 | _T_1389; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_72 = {{8'd0}, _T_1390[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1395 = _GEN_72 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1397 = {_T_1390[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1399 = _T_1397 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1400 = _T_1395 | _T_1399; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_73 = {{4'd0}, _T_1400[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1405 = _GEN_73 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1407 = {_T_1400[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1409 = _T_1407 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1410 = _T_1405 | _T_1409; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_74 = {{2'd0}, _T_1410[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1415 = _GEN_74 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1417 = {_T_1410[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1419 = _T_1417 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1420 = _T_1415 | _T_1419; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_75 = {{1'd0}, _T_1420[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1425 = _GEN_75 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1427 = {_T_1420[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1429 = _T_1427 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire [31:0] _T_1430 = _T_1425 | _T_1429; // @[Bitwise.scala 103:39] + wire _T_1431 = io_ldst_dual_m & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 262:295] + wire _T_1432 = _T_1431 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 262:316] + wire _T_1433 = _T_1432 | io_clk_override; // @[lsu_dccm_ctl.scala 262:343] + reg [31:0] _T_1436; // @[Reg.scala 27:20] + wire _T_1437 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[lsu_dccm_ctl.scala 263:105] + wire [7:0] store_byteen_ext_r = {{1'd0}, _T_999}; // @[lsu_dccm_ctl.scala 222:22] + wire _T_1439 = ~store_byteen_ext_r[0]; // @[lsu_dccm_ctl.scala 263:131] + wire _T_1440 = _T_1437 & _T_1439; // @[lsu_dccm_ctl.scala 263:129] + wire [7:0] _T_1444 = _T_1440 ? io_stbuf_data_any[7:0] : io_store_data_lo_r[7:0]; // @[lsu_dccm_ctl.scala 263:79] + wire [7:0] _T_1448 = {{4'd0}, _T_1444[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1450 = {_T_1444[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1452 = _T_1450 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1453 = _T_1448 | _T_1452; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_76 = {{2'd0}, _T_1453[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1458 = _GEN_76 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1460 = {_T_1453[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1462 = _T_1460 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1463 = _T_1458 | _T_1462; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_77 = {{1'd0}, _T_1463[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1468 = _GEN_77 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1470 = {_T_1463[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1472 = _T_1470 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1473 = _T_1468 | _T_1472; // @[Bitwise.scala 103:39] + wire _T_1476 = ~store_byteen_ext_r[1]; // @[lsu_dccm_ctl.scala 263:131] + wire _T_1477 = _T_1437 & _T_1476; // @[lsu_dccm_ctl.scala 263:129] + wire [7:0] _T_1481 = _T_1477 ? io_stbuf_data_any[15:8] : io_store_data_lo_r[15:8]; // @[lsu_dccm_ctl.scala 263:79] + wire [7:0] _T_1485 = {{4'd0}, _T_1481[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1487 = {_T_1481[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1489 = _T_1487 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1490 = _T_1485 | _T_1489; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_78 = {{2'd0}, _T_1490[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1495 = _GEN_78 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1497 = {_T_1490[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1499 = _T_1497 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1500 = _T_1495 | _T_1499; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_79 = {{1'd0}, _T_1500[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1505 = _GEN_79 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1507 = {_T_1500[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1509 = _T_1507 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1510 = _T_1505 | _T_1509; // @[Bitwise.scala 103:39] + wire _T_1513 = ~store_byteen_ext_r[2]; // @[lsu_dccm_ctl.scala 263:131] + wire _T_1514 = _T_1437 & _T_1513; // @[lsu_dccm_ctl.scala 263:129] + wire [7:0] _T_1518 = _T_1514 ? io_stbuf_data_any[23:16] : io_store_data_lo_r[23:16]; // @[lsu_dccm_ctl.scala 263:79] + wire [7:0] _T_1522 = {{4'd0}, _T_1518[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1524 = {_T_1518[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1526 = _T_1524 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1527 = _T_1522 | _T_1526; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_80 = {{2'd0}, _T_1527[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1532 = _GEN_80 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1534 = {_T_1527[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1536 = _T_1534 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1537 = _T_1532 | _T_1536; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_81 = {{1'd0}, _T_1537[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1542 = _GEN_81 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1544 = {_T_1537[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1546 = _T_1544 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1547 = _T_1542 | _T_1546; // @[Bitwise.scala 103:39] + wire _T_1550 = ~store_byteen_ext_r[3]; // @[lsu_dccm_ctl.scala 263:131] + wire _T_1551 = _T_1437 & _T_1550; // @[lsu_dccm_ctl.scala 263:129] + wire [7:0] _T_1555 = _T_1551 ? io_stbuf_data_any[31:24] : io_store_data_lo_r[31:24]; // @[lsu_dccm_ctl.scala 263:79] + wire [7:0] _T_1559 = {{4'd0}, _T_1555[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1561 = {_T_1555[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1563 = _T_1561 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1564 = _T_1559 | _T_1563; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_82 = {{2'd0}, _T_1564[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1569 = _GEN_82 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1571 = {_T_1564[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1573 = _T_1571 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1574 = _T_1569 | _T_1573; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_83 = {{1'd0}, _T_1574[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1579 = _GEN_83 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1581 = {_T_1574[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1583 = _T_1581 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1584 = _T_1579 | _T_1583; // @[Bitwise.scala 103:39] + wire [31:0] _T_1588 = {_T_1473,_T_1510,_T_1547,_T_1584}; // @[Cat.scala 29:58] + wire [31:0] _T_1592 = {{16'd0}, _T_1588[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1594 = {_T_1588[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1596 = _T_1594 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1597 = _T_1592 | _T_1596; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_84 = {{8'd0}, _T_1597[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1602 = _GEN_84 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1604 = {_T_1597[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1606 = _T_1604 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1607 = _T_1602 | _T_1606; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_85 = {{4'd0}, _T_1607[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1612 = _GEN_85 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1614 = {_T_1607[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1616 = _T_1614 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1617 = _T_1612 | _T_1616; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_86 = {{2'd0}, _T_1617[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1622 = _GEN_86 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1624 = {_T_1617[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1626 = _T_1624 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1627 = _T_1622 | _T_1626; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_87 = {{1'd0}, _T_1627[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1632 = _GEN_87 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1634 = {_T_1627[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1636 = _T_1634 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire _T_1638 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi; // @[lsu_dccm_ctl.scala 264:105] + wire _T_1640 = ~store_byteen_ext_r[4]; // @[lsu_dccm_ctl.scala 264:131] + wire _T_1641 = _T_1638 & _T_1640; // @[lsu_dccm_ctl.scala 264:129] + wire [7:0] _T_1645 = _T_1641 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[lsu_dccm_ctl.scala 264:79] + wire [7:0] _T_1649 = {{4'd0}, _T_1645[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1651 = {_T_1645[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1653 = _T_1651 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1654 = _T_1649 | _T_1653; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_88 = {{2'd0}, _T_1654[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1659 = _GEN_88 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1661 = {_T_1654[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1663 = _T_1661 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1664 = _T_1659 | _T_1663; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_89 = {{1'd0}, _T_1664[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1669 = _GEN_89 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1671 = {_T_1664[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1673 = _T_1671 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1674 = _T_1669 | _T_1673; // @[Bitwise.scala 103:39] + wire _T_1677 = ~store_byteen_ext_r[5]; // @[lsu_dccm_ctl.scala 264:131] + wire _T_1678 = _T_1638 & _T_1677; // @[lsu_dccm_ctl.scala 264:129] + wire [7:0] _T_1682 = _T_1678 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[lsu_dccm_ctl.scala 264:79] + wire [7:0] _T_1686 = {{4'd0}, _T_1682[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1688 = {_T_1682[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1690 = _T_1688 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1691 = _T_1686 | _T_1690; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_90 = {{2'd0}, _T_1691[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1696 = _GEN_90 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1698 = {_T_1691[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1700 = _T_1698 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1701 = _T_1696 | _T_1700; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_91 = {{1'd0}, _T_1701[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1706 = _GEN_91 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1708 = {_T_1701[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1710 = _T_1708 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1711 = _T_1706 | _T_1710; // @[Bitwise.scala 103:39] + wire _T_1714 = ~store_byteen_ext_r[6]; // @[lsu_dccm_ctl.scala 264:131] + wire _T_1715 = _T_1638 & _T_1714; // @[lsu_dccm_ctl.scala 264:129] + wire [7:0] _T_1719 = _T_1715 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[lsu_dccm_ctl.scala 264:79] + wire [7:0] _T_1723 = {{4'd0}, _T_1719[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1725 = {_T_1719[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1727 = _T_1725 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1728 = _T_1723 | _T_1727; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_92 = {{2'd0}, _T_1728[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1733 = _GEN_92 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1735 = {_T_1728[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1737 = _T_1735 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1738 = _T_1733 | _T_1737; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_93 = {{1'd0}, _T_1738[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1743 = _GEN_93 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1745 = {_T_1738[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1747 = _T_1745 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1748 = _T_1743 | _T_1747; // @[Bitwise.scala 103:39] + wire _T_1751 = ~store_byteen_ext_r[7]; // @[lsu_dccm_ctl.scala 264:131] + wire _T_1752 = _T_1638 & _T_1751; // @[lsu_dccm_ctl.scala 264:129] + wire [7:0] _T_1756 = _T_1752 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[lsu_dccm_ctl.scala 264:79] + wire [7:0] _T_1760 = {{4'd0}, _T_1756[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1762 = {_T_1756[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1764 = _T_1762 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1765 = _T_1760 | _T_1764; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_94 = {{2'd0}, _T_1765[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1770 = _GEN_94 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1772 = {_T_1765[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1774 = _T_1772 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1775 = _T_1770 | _T_1774; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_95 = {{1'd0}, _T_1775[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1780 = _GEN_95 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1782 = {_T_1775[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1784 = _T_1782 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1785 = _T_1780 | _T_1784; // @[Bitwise.scala 103:39] + wire [31:0] _T_1789 = {_T_1674,_T_1711,_T_1748,_T_1785}; // @[Cat.scala 29:58] + wire [31:0] _T_1793 = {{16'd0}, _T_1789[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1795 = {_T_1789[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1797 = _T_1795 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1798 = _T_1793 | _T_1797; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_96 = {{8'd0}, _T_1798[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1803 = _GEN_96 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1805 = {_T_1798[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1807 = _T_1805 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1808 = _T_1803 | _T_1807; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_97 = {{4'd0}, _T_1808[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1813 = _GEN_97 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1815 = {_T_1808[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1817 = _T_1815 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1818 = _T_1813 | _T_1817; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_98 = {{2'd0}, _T_1818[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1823 = _GEN_98 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1825 = {_T_1818[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1827 = _T_1825 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1828 = _T_1823 | _T_1827; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_99 = {{1'd0}, _T_1828[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1833 = _GEN_99 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1835 = {_T_1828[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1837 = _T_1835 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] _T_1841 = {io_store_data_hi_r,io_store_data_lo_r}; // @[Cat.scala 29:58] + wire [3:0] _GEN_100 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[lsu_dccm_ctl.scala 265:94] + wire [5:0] _T_1843 = 4'h8 * _GEN_100; // @[lsu_dccm_ctl.scala 265:94] + wire [63:0] _T_1844 = _T_1841 >> _T_1843; // @[lsu_dccm_ctl.scala 265:88] + wire [7:0] _T_1847 = store_byteen_r[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1850 = store_byteen_r[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1853 = store_byteen_r[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1856 = store_byteen_r[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1860 = {_T_1847,_T_1850,_T_1853,_T_1856}; // @[Cat.scala 29:58] + wire [31:0] _T_1864 = {{16'd0}, _T_1860[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1866 = {_T_1860[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1868 = _T_1866 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1869 = _T_1864 | _T_1868; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_101 = {{8'd0}, _T_1869[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1874 = _GEN_101 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1876 = {_T_1869[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1878 = _T_1876 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1879 = _T_1874 | _T_1878; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_102 = {{4'd0}, _T_1879[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1884 = _GEN_102 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1886 = {_T_1879[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1888 = _T_1886 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1889 = _T_1884 | _T_1888; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_103 = {{2'd0}, _T_1889[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1894 = _GEN_103 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1896 = {_T_1889[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1898 = _T_1896 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1899 = _T_1894 | _T_1898; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_104 = {{1'd0}, _T_1899[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1904 = _GEN_104 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1906 = {_T_1899[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1908 = _T_1906 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire [31:0] _T_1909 = _T_1904 | _T_1908; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_105 = {{32'd0}, _T_1909}; // @[lsu_dccm_ctl.scala 265:115] + wire [63:0] _T_1910 = _T_1844 & _GEN_105; // @[lsu_dccm_ctl.scala 265:115] + wire _T_1915 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_dccm_ctl.scala 272:58] + wire _T_1916 = _T_1915 & io_addr_in_pic_r; // @[lsu_dccm_ctl.scala 272:84] + wire _T_1917 = _T_1916 & io_lsu_commit_r; // @[lsu_dccm_ctl.scala 272:103] + wire _T_1919 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_load; // @[lsu_dccm_ctl.scala 273:58] + wire _T_1921 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 274:58] + wire [31:0] _T_1925 = {17'h0,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58] + wire [14:0] _T_1931 = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[lsu_dccm_ctl.scala 276:93] + wire [31:0] _T_1932 = {17'h0,_T_1931}; // @[Cat.scala 29:58] + reg _T_1939; // @[lsu_dccm_ctl.scala 280:61] + wire _T_1945 = io_ld_single_ecc_error_r | io_clk_override; // @[lsu_dccm_ctl.scala 285:90] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + assign io_lsu_ld_data_corr_r = _T_818[31:0]; // @[lsu_dccm_ctl.scala 157:28] + assign io_dccm_rdata_hi_m = io_dccm_rd_data_hi[31:0]; // @[lsu_dccm_ctl.scala 268:27] + assign io_dccm_rdata_lo_m = io_dccm_rd_data_lo[31:0]; // @[lsu_dccm_ctl.scala 267:27] + assign io_dccm_data_ecc_hi_m = io_dccm_rd_data_hi[38:32]; // @[lsu_dccm_ctl.scala 270:27] + assign io_dccm_data_ecc_lo_m = io_dccm_rd_data_lo[38:32]; // @[lsu_dccm_ctl.scala 269:27] + assign io_lsu_ld_data_m = _T_821[31:0]; // @[lsu_dccm_ctl.scala 121:20 lsu_dccm_ctl.scala 158:28] + assign io_store_data_hi_r = _T_1436; // @[lsu_dccm_ctl.scala 262:29] + assign io_store_data_lo_r = _T_1225; // @[lsu_dccm_ctl.scala 261:29] + assign io_store_datafn_hi_r = _T_1833 | _T_1837; // @[lsu_dccm_ctl.scala 264:29] + assign io_store_datafn_lo_r = _T_1632 | _T_1636; // @[lsu_dccm_ctl.scala 263:29] + assign io_store_data_r = _T_1910[31:0]; // @[lsu_dccm_ctl.scala 265:29] + assign io_ld_single_ecc_error_r = _T_873 & _T_874; // @[lsu_dccm_ctl.scala 171:34] + assign io_ld_single_ecc_error_r_ff = _T_890 & _T_891; // @[lsu_dccm_ctl.scala 178:31] + assign io_picm_mask_data_m = picm_rd_data_m[31:0]; // @[lsu_dccm_ctl.scala 277:27] + assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_905; // @[lsu_dccm_ctl.scala 179:31] + assign io_lsu_dccm_rden_m = _T_1939; // @[lsu_dccm_ctl.scala 280:24] + assign io_dma_dccm_ctl_dccm_dma_rvalid = _T & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 145:41] + assign io_dma_dccm_ctl_dccm_dma_ecc_error = io_lsu_double_ecc_error_m; // @[lsu_dccm_ctl.scala 146:41] + assign io_dma_dccm_ctl_dccm_dma_rtag = io_dma_mem_tag_m; // @[lsu_dccm_ctl.scala 148:41] + assign io_dma_dccm_ctl_dccm_dma_rdata = io_ldst_dual_m ? lsu_rdata_corr_m : _T_4; // @[lsu_dccm_ctl.scala 147:41] + assign io_dccm_wren = _T_907 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 185:22] + assign io_dccm_rden = lsu_dccm_rden_d & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 186:22] + assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_914 : _T_918; // @[lsu_dccm_ctl.scala 188:22] + assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_924 : _T_928; // @[lsu_dccm_ctl.scala 192:22] + assign io_dccm_rd_addr_lo = io_lsu_addr_d[15:0]; // @[lsu_dccm_ctl.scala 196:22] + assign io_dccm_rd_addr_hi = io_end_addr_d; // @[lsu_dccm_ctl.scala 197:22] + assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_940 : _T_948; // @[lsu_dccm_ctl.scala 199:22] + assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_958 : _T_966; // @[lsu_dccm_ctl.scala 205:22] + assign io_lsu_pic_picm_wren = _T_1917 | io_dma_pic_wen; // @[lsu_dccm_ctl.scala 272:35] + assign io_lsu_pic_picm_rden = _T_1919 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 273:35] + assign io_lsu_pic_picm_mken = _T_1921 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 274:35] + assign io_lsu_pic_picm_rdaddr = 32'hf00c0000 | _T_1925; // @[lsu_dccm_ctl.scala 275:35] + assign io_lsu_pic_picm_wraddr = 32'hf00c0000 | _T_1932; // @[lsu_dccm_ctl.scala 276:35] + assign io_lsu_pic_picm_wr_data = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[lsu_dccm_ctl.scala 278:35] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = _T_814 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_1432 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {2{`RANDOM}}; + _T_818 = _RAND_0[63:0]; + _RAND_1 = {1{`RANDOM}}; + ld_single_ecc_error_lo_r_ff = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + ld_single_ecc_error_hi_r_ff = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + lsu_double_ecc_error_r_ff = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ld_sec_addr_lo_r_ff = _RAND_4[15:0]; + _RAND_5 = {1{`RANDOM}}; + ld_sec_addr_hi_r_ff = _RAND_5[15:0]; + _RAND_6 = {1{`RANDOM}}; + _T_1225 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + _T_1436 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + _T_1939 = _RAND_8[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_818 = 64'h0; + end + if (reset) begin + ld_single_ecc_error_lo_r_ff = 1'h0; + end + if (reset) begin + ld_single_ecc_error_hi_r_ff = 1'h0; + end + if (reset) begin + lsu_double_ecc_error_r_ff = 1'h0; + end + if (reset) begin + ld_sec_addr_lo_r_ff = 16'h0; + end + if (reset) begin + ld_sec_addr_hi_r_ff = 16'h0; + end + if (reset) begin + _T_1225 = 32'h0; + end + if (reset) begin + _T_1436 = 32'h0; + end + if (reset) begin + _T_1939 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_818 <= 64'h0; + end else if (_T_815) begin + _T_818 <= lsu_ld_data_corr_m; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ld_single_ecc_error_lo_r_ff <= 1'h0; + end else begin + ld_single_ecc_error_lo_r_ff <= _T_877 & _T_878; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ld_single_ecc_error_hi_r_ff <= 1'h0; + end else begin + ld_single_ecc_error_hi_r_ff <= _T_880 & _T_881; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + lsu_double_ecc_error_r_ff <= 1'h0; + end else begin + lsu_double_ecc_error_r_ff <= io_lsu_double_ecc_error_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ld_sec_addr_lo_r_ff <= 16'h0; + end else if (_T_1945) begin + ld_sec_addr_lo_r_ff <= io_lsu_addr_r[15:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ld_sec_addr_hi_r_ff <= 16'h0; + end else if (_T_1945) begin + ld_sec_addr_hi_r_ff <= io_end_addr_r; + end + end + always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin + if (reset) begin + _T_1225 <= 32'h0; + end else begin + _T_1225 <= _T_1219 | _T_1223; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1436 <= 32'h0; + end else if (_T_1433) begin + _T_1436 <= _T_1430; + end + end + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_1939 <= 1'h0; + end else begin + _T_1939 <= _T_889 & io_addr_in_dccm_d; + end + end +endmodule +module lsu_stbuf( + input clock, + input reset, + input io_lsu_stbuf_c1_clk, + input io_lsu_free_c2_clk, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_dword, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_dma, + input io_store_stbuf_reqvld_r, + input io_lsu_commit_r, + input io_dec_lsu_valid_raw_d, + input [31:0] io_store_data_hi_r, + input [31:0] io_store_data_lo_r, + input [31:0] io_store_datafn_hi_r, + input [31:0] io_store_datafn_lo_r, + input io_lsu_stbuf_commit_any, + input [31:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_m, + input [31:0] io_end_addr_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input io_addr_in_dccm_m, + input io_addr_in_dccm_r, + output io_stbuf_reqvld_any, + output io_stbuf_reqvld_flushed_any, + output [15:0] io_stbuf_addr_any, + output [31:0] io_stbuf_data_any, + output io_lsu_stbuf_full_any, + output io_ldst_stbuf_reqvld_r, + output [31:0] io_stbuf_fwddata_hi_m, + output [31:0] io_stbuf_fwddata_lo_m, + output [3:0] io_stbuf_fwdbyteen_hi_m, + output [3:0] io_stbuf_fwdbyteen_lo_m +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire [1:0] _T_5 = io_lsu_pkt_r_bits_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [7:0] _T_7 = io_lsu_pkt_r_bits_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_18 = {{1'd0}, io_lsu_pkt_r_bits_by}; // @[Mux.scala 27:72] + wire [1:0] _T_8 = _GEN_18 | _T_5; // @[Mux.scala 27:72] + wire [3:0] _GEN_19 = {{2'd0}, _T_8}; // @[Mux.scala 27:72] + wire [3:0] _T_9 = _GEN_19 | _T_6; // @[Mux.scala 27:72] + wire [7:0] _GEN_20 = {{4'd0}, _T_9}; // @[Mux.scala 27:72] + wire [7:0] ldst_byteen_r = _GEN_20 | _T_7; // @[Mux.scala 27:72] + wire dual_stbuf_write_r = io_ldst_dual_r & io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 115:43] + wire [10:0] _GEN_21 = {{3'd0}, ldst_byteen_r}; // @[lsu_stbuf.scala 117:39] + wire [10:0] _T_12 = _GEN_21 << io_lsu_addr_r[1:0]; // @[lsu_stbuf.scala 117:39] + wire [7:0] store_byteen_ext_r = _T_12[7:0]; // @[lsu_stbuf.scala 117:22] + wire [3:0] _T_15 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_15; // @[lsu_stbuf.scala 118:52] + wire [3:0] store_byteen_lo_r = store_byteen_ext_r[3:0] & _T_15; // @[lsu_stbuf.scala 119:52] + reg [1:0] RdPtr; // @[Reg.scala 27:20] + wire [1:0] RdPtrPlus1 = RdPtr + 2'h1; // @[lsu_stbuf.scala 121:26] + reg [1:0] WrPtr; // @[Reg.scala 27:20] + wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[lsu_stbuf.scala 122:26] + wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[lsu_stbuf.scala 123:26] + wire _T_22 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_stbuf.scala 125:46] + reg [15:0] stbuf_addr_0; // @[Reg.scala 27:20] + wire _T_26 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120] + reg _T_587; // @[lsu_stbuf.scala 160:14] + reg _T_579; // @[lsu_stbuf.scala 160:14] + reg _T_571; // @[lsu_stbuf.scala 160:14] + reg _T_563; // @[lsu_stbuf.scala 160:14] + wire [3:0] stbuf_vld = {_T_587,_T_579,_T_571,_T_563}; // @[Cat.scala 29:58] + wire _T_28 = _T_26 & stbuf_vld[0]; // @[lsu_stbuf.scala 127:179] + reg _T_622; // @[lsu_stbuf.scala 163:14] + reg _T_614; // @[lsu_stbuf.scala 163:14] + reg _T_606; // @[lsu_stbuf.scala 163:14] + reg _T_598; // @[lsu_stbuf.scala 163:14] + wire [3:0] stbuf_dma_kill = {_T_622,_T_614,_T_606,_T_598}; // @[Cat.scala 29:58] + wire _T_30 = ~stbuf_dma_kill[0]; // @[lsu_stbuf.scala 127:197] + wire _T_31 = _T_28 & _T_30; // @[lsu_stbuf.scala 127:195] + wire _T_211 = io_lsu_stbuf_commit_any | io_stbuf_reqvld_flushed_any; // @[lsu_stbuf.scala 138:81] + wire _T_212 = 2'h3 == RdPtr; // @[lsu_stbuf.scala 138:124] + wire _T_214 = _T_211 & _T_212; // @[lsu_stbuf.scala 138:112] + wire _T_208 = 2'h2 == RdPtr; // @[lsu_stbuf.scala 138:124] + wire _T_210 = _T_211 & _T_208; // @[lsu_stbuf.scala 138:112] + wire _T_204 = 2'h1 == RdPtr; // @[lsu_stbuf.scala 138:124] + wire _T_206 = _T_211 & _T_204; // @[lsu_stbuf.scala 138:112] + wire _T_200 = 2'h0 == RdPtr; // @[lsu_stbuf.scala 138:124] + wire _T_202 = _T_211 & _T_200; // @[lsu_stbuf.scala 138:112] + wire [3:0] stbuf_reset = {_T_214,_T_210,_T_206,_T_202}; // @[Cat.scala 29:58] + wire _T_33 = ~stbuf_reset[0]; // @[lsu_stbuf.scala 127:218] + wire _T_34 = _T_31 & _T_33; // @[lsu_stbuf.scala 127:216] + reg [15:0] stbuf_addr_1; // @[Reg.scala 27:20] + wire _T_37 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120] + wire _T_39 = _T_37 & stbuf_vld[1]; // @[lsu_stbuf.scala 127:179] + wire _T_41 = ~stbuf_dma_kill[1]; // @[lsu_stbuf.scala 127:197] + wire _T_42 = _T_39 & _T_41; // @[lsu_stbuf.scala 127:195] + wire _T_44 = ~stbuf_reset[1]; // @[lsu_stbuf.scala 127:218] + wire _T_45 = _T_42 & _T_44; // @[lsu_stbuf.scala 127:216] + reg [15:0] stbuf_addr_2; // @[Reg.scala 27:20] + wire _T_48 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120] + wire _T_50 = _T_48 & stbuf_vld[2]; // @[lsu_stbuf.scala 127:179] + wire _T_52 = ~stbuf_dma_kill[2]; // @[lsu_stbuf.scala 127:197] + wire _T_53 = _T_50 & _T_52; // @[lsu_stbuf.scala 127:195] + wire _T_55 = ~stbuf_reset[2]; // @[lsu_stbuf.scala 127:218] + wire _T_56 = _T_53 & _T_55; // @[lsu_stbuf.scala 127:216] + reg [15:0] stbuf_addr_3; // @[Reg.scala 27:20] + wire _T_59 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120] + wire _T_61 = _T_59 & stbuf_vld[3]; // @[lsu_stbuf.scala 127:179] + wire _T_63 = ~stbuf_dma_kill[3]; // @[lsu_stbuf.scala 127:197] + wire _T_64 = _T_61 & _T_63; // @[lsu_stbuf.scala 127:195] + wire _T_66 = ~stbuf_reset[3]; // @[lsu_stbuf.scala 127:218] + wire _T_67 = _T_64 & _T_66; // @[lsu_stbuf.scala 127:216] + wire [3:0] store_matchvec_lo_r = {_T_67,_T_56,_T_45,_T_34}; // @[Cat.scala 29:58] + wire _T_72 = stbuf_addr_0[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120] + wire _T_74 = _T_72 & stbuf_vld[0]; // @[lsu_stbuf.scala 128:179] + wire _T_77 = _T_74 & _T_30; // @[lsu_stbuf.scala 128:194] + wire _T_78 = _T_77 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215] + wire _T_81 = _T_78 & _T_33; // @[lsu_stbuf.scala 128:236] + wire _T_84 = stbuf_addr_1[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120] + wire _T_86 = _T_84 & stbuf_vld[1]; // @[lsu_stbuf.scala 128:179] + wire _T_89 = _T_86 & _T_41; // @[lsu_stbuf.scala 128:194] + wire _T_90 = _T_89 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215] + wire _T_93 = _T_90 & _T_44; // @[lsu_stbuf.scala 128:236] + wire _T_96 = stbuf_addr_2[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120] + wire _T_98 = _T_96 & stbuf_vld[2]; // @[lsu_stbuf.scala 128:179] + wire _T_101 = _T_98 & _T_52; // @[lsu_stbuf.scala 128:194] + wire _T_102 = _T_101 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215] + wire _T_105 = _T_102 & _T_55; // @[lsu_stbuf.scala 128:236] + wire _T_108 = stbuf_addr_3[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120] + wire _T_110 = _T_108 & stbuf_vld[3]; // @[lsu_stbuf.scala 128:179] + wire _T_113 = _T_110 & _T_63; // @[lsu_stbuf.scala 128:194] + wire _T_114 = _T_113 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215] + wire _T_117 = _T_114 & _T_66; // @[lsu_stbuf.scala 128:236] + wire [3:0] store_matchvec_hi_r = {_T_117,_T_105,_T_93,_T_81}; // @[Cat.scala 29:58] + wire store_coalesce_lo_r = |store_matchvec_lo_r; // @[lsu_stbuf.scala 130:49] + wire store_coalesce_hi_r = |store_matchvec_hi_r; // @[lsu_stbuf.scala 131:49] + wire _T_120 = 2'h0 == WrPtr; // @[lsu_stbuf.scala 134:18] + wire _T_121 = ~store_coalesce_lo_r; // @[lsu_stbuf.scala 134:31] + wire _T_122 = _T_120 & _T_121; // @[lsu_stbuf.scala 134:29] + wire _T_124 = _T_120 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31] + wire _T_125 = ~store_coalesce_hi_r; // @[lsu_stbuf.scala 135:54] + wire _T_126 = _T_124 & _T_125; // @[lsu_stbuf.scala 135:52] + wire _T_127 = _T_122 | _T_126; // @[lsu_stbuf.scala 134:53] + wire _T_128 = 2'h0 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20] + wire _T_129 = _T_128 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36] + wire _T_130 = store_coalesce_lo_r | store_coalesce_hi_r; // @[lsu_stbuf.scala 136:81] + wire _T_131 = ~_T_130; // @[lsu_stbuf.scala 136:59] + wire _T_132 = _T_129 & _T_131; // @[lsu_stbuf.scala 136:57] + wire _T_133 = _T_127 | _T_132; // @[lsu_stbuf.scala 135:76] + wire _T_135 = _T_133 | store_matchvec_lo_r[0]; // @[lsu_stbuf.scala 136:105] + wire _T_137 = _T_135 | store_matchvec_hi_r[0]; // @[lsu_stbuf.scala 137:32] + wire _T_138 = io_ldst_stbuf_reqvld_r & _T_137; // @[lsu_stbuf.scala 133:79] + wire _T_139 = 2'h1 == WrPtr; // @[lsu_stbuf.scala 134:18] + wire _T_141 = _T_139 & _T_121; // @[lsu_stbuf.scala 134:29] + wire _T_143 = _T_139 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31] + wire _T_145 = _T_143 & _T_125; // @[lsu_stbuf.scala 135:52] + wire _T_146 = _T_141 | _T_145; // @[lsu_stbuf.scala 134:53] + wire _T_147 = 2'h1 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20] + wire _T_148 = _T_147 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36] + wire _T_151 = _T_148 & _T_131; // @[lsu_stbuf.scala 136:57] + wire _T_152 = _T_146 | _T_151; // @[lsu_stbuf.scala 135:76] + wire _T_154 = _T_152 | store_matchvec_lo_r[1]; // @[lsu_stbuf.scala 136:105] + wire _T_156 = _T_154 | store_matchvec_hi_r[1]; // @[lsu_stbuf.scala 137:32] + wire _T_157 = io_ldst_stbuf_reqvld_r & _T_156; // @[lsu_stbuf.scala 133:79] + wire _T_158 = 2'h2 == WrPtr; // @[lsu_stbuf.scala 134:18] + wire _T_160 = _T_158 & _T_121; // @[lsu_stbuf.scala 134:29] + wire _T_162 = _T_158 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31] + wire _T_164 = _T_162 & _T_125; // @[lsu_stbuf.scala 135:52] + wire _T_165 = _T_160 | _T_164; // @[lsu_stbuf.scala 134:53] + wire _T_166 = 2'h2 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20] + wire _T_167 = _T_166 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36] + wire _T_170 = _T_167 & _T_131; // @[lsu_stbuf.scala 136:57] + wire _T_171 = _T_165 | _T_170; // @[lsu_stbuf.scala 135:76] + wire _T_173 = _T_171 | store_matchvec_lo_r[2]; // @[lsu_stbuf.scala 136:105] + wire _T_175 = _T_173 | store_matchvec_hi_r[2]; // @[lsu_stbuf.scala 137:32] + wire _T_176 = io_ldst_stbuf_reqvld_r & _T_175; // @[lsu_stbuf.scala 133:79] + wire _T_177 = 2'h3 == WrPtr; // @[lsu_stbuf.scala 134:18] + wire _T_179 = _T_177 & _T_121; // @[lsu_stbuf.scala 134:29] + wire _T_181 = _T_177 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31] + wire _T_183 = _T_181 & _T_125; // @[lsu_stbuf.scala 135:52] + wire _T_184 = _T_179 | _T_183; // @[lsu_stbuf.scala 134:53] + wire _T_185 = 2'h3 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20] + wire _T_186 = _T_185 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36] + wire _T_189 = _T_186 & _T_131; // @[lsu_stbuf.scala 136:57] + wire _T_190 = _T_184 | _T_189; // @[lsu_stbuf.scala 135:76] + wire _T_192 = _T_190 | store_matchvec_lo_r[3]; // @[lsu_stbuf.scala 136:105] + wire _T_194 = _T_192 | store_matchvec_hi_r[3]; // @[lsu_stbuf.scala 137:32] + wire _T_195 = io_ldst_stbuf_reqvld_r & _T_194; // @[lsu_stbuf.scala 133:79] + wire [3:0] stbuf_wr_en = {_T_195,_T_176,_T_157,_T_138}; // @[Cat.scala 29:58] + wire _T_218 = ~io_ldst_dual_r; // @[lsu_stbuf.scala 139:56] + wire _T_219 = _T_218 | io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 139:72] + wire _T_222 = _T_219 & _T_120; // @[lsu_stbuf.scala 139:99] + wire _T_224 = _T_222 & _T_121; // @[lsu_stbuf.scala 139:129] + wire _T_226 = _T_224 | store_matchvec_lo_r[0]; // @[lsu_stbuf.scala 139:153] + wire _T_231 = _T_219 & _T_139; // @[lsu_stbuf.scala 139:99] + wire _T_233 = _T_231 & _T_121; // @[lsu_stbuf.scala 139:129] + wire _T_235 = _T_233 | store_matchvec_lo_r[1]; // @[lsu_stbuf.scala 139:153] + wire _T_240 = _T_219 & _T_158; // @[lsu_stbuf.scala 139:99] + wire _T_242 = _T_240 & _T_121; // @[lsu_stbuf.scala 139:129] + wire _T_244 = _T_242 | store_matchvec_lo_r[2]; // @[lsu_stbuf.scala 139:153] + wire _T_249 = _T_219 & _T_177; // @[lsu_stbuf.scala 139:99] + wire _T_251 = _T_249 & _T_121; // @[lsu_stbuf.scala 139:129] + wire _T_253 = _T_251 | store_matchvec_lo_r[3]; // @[lsu_stbuf.scala 139:153] + wire [3:0] sel_lo = {_T_253,_T_244,_T_235,_T_226}; // @[Cat.scala 29:58] + reg [3:0] stbuf_byteen_0; // @[lsu_stbuf.scala 166:14] + wire [3:0] _T_273 = stbuf_byteen_0 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89] + wire [3:0] _T_274 = stbuf_byteen_0 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126] + wire [3:0] stbuf_byteenin_0 = sel_lo[0] ? _T_273 : _T_274; // @[lsu_stbuf.scala 142:61] + reg [3:0] stbuf_byteen_1; // @[lsu_stbuf.scala 166:14] + wire [3:0] _T_277 = stbuf_byteen_1 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89] + wire [3:0] _T_278 = stbuf_byteen_1 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126] + wire [3:0] stbuf_byteenin_1 = sel_lo[1] ? _T_277 : _T_278; // @[lsu_stbuf.scala 142:61] + reg [3:0] stbuf_byteen_2; // @[lsu_stbuf.scala 166:14] + wire [3:0] _T_281 = stbuf_byteen_2 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89] + wire [3:0] _T_282 = stbuf_byteen_2 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126] + wire [3:0] stbuf_byteenin_2 = sel_lo[2] ? _T_281 : _T_282; // @[lsu_stbuf.scala 142:61] + reg [3:0] stbuf_byteen_3; // @[lsu_stbuf.scala 166:14] + wire [3:0] _T_285 = stbuf_byteen_3 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89] + wire [3:0] _T_286 = stbuf_byteen_3 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126] + wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_285 : _T_286; // @[lsu_stbuf.scala 142:61] + wire _T_290 = ~stbuf_byteen_0[0]; // @[lsu_stbuf.scala 144:70] + wire _T_292 = _T_290 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90] + reg [31:0] stbuf_data_0; // @[Reg.scala 27:20] + wire [7:0] _T_295 = _T_292 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 144:69] + wire _T_299 = _T_290 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31] + wire [7:0] _T_302 = _T_299 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 145:10] + wire [7:0] datain1_0 = sel_lo[0] ? _T_295 : _T_302; // @[lsu_stbuf.scala 144:54] + wire _T_306 = ~stbuf_byteen_1[0]; // @[lsu_stbuf.scala 144:70] + wire _T_308 = _T_306 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90] + reg [31:0] stbuf_data_1; // @[Reg.scala 27:20] + wire [7:0] _T_311 = _T_308 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 144:69] + wire _T_315 = _T_306 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31] + wire [7:0] _T_318 = _T_315 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 145:10] + wire [7:0] datain1_1 = sel_lo[1] ? _T_311 : _T_318; // @[lsu_stbuf.scala 144:54] + wire _T_322 = ~stbuf_byteen_2[0]; // @[lsu_stbuf.scala 144:70] + wire _T_324 = _T_322 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90] + reg [31:0] stbuf_data_2; // @[Reg.scala 27:20] + wire [7:0] _T_327 = _T_324 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 144:69] + wire _T_331 = _T_322 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31] + wire [7:0] _T_334 = _T_331 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 145:10] + wire [7:0] datain1_2 = sel_lo[2] ? _T_327 : _T_334; // @[lsu_stbuf.scala 144:54] + wire _T_338 = ~stbuf_byteen_3[0]; // @[lsu_stbuf.scala 144:70] + wire _T_340 = _T_338 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90] + reg [31:0] stbuf_data_3; // @[Reg.scala 27:20] + wire [7:0] _T_343 = _T_340 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 144:69] + wire _T_347 = _T_338 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31] + wire [7:0] _T_350 = _T_347 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 145:10] + wire [7:0] datain1_3 = sel_lo[3] ? _T_343 : _T_350; // @[lsu_stbuf.scala 144:54] + wire _T_354 = ~stbuf_byteen_0[1]; // @[lsu_stbuf.scala 147:70] + wire _T_356 = _T_354 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90] + wire [7:0] _T_359 = _T_356 ? io_store_datafn_lo_r[15:8] : stbuf_data_0[15:8]; // @[lsu_stbuf.scala 147:69] + wire _T_363 = _T_354 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31] + wire [7:0] _T_366 = _T_363 ? io_store_datafn_hi_r[15:8] : stbuf_data_0[15:8]; // @[lsu_stbuf.scala 148:10] + wire [7:0] datain2_0 = sel_lo[0] ? _T_359 : _T_366; // @[lsu_stbuf.scala 147:54] + wire _T_370 = ~stbuf_byteen_1[1]; // @[lsu_stbuf.scala 147:70] + wire _T_372 = _T_370 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90] + wire [7:0] _T_375 = _T_372 ? io_store_datafn_lo_r[15:8] : stbuf_data_1[15:8]; // @[lsu_stbuf.scala 147:69] + wire _T_379 = _T_370 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31] + wire [7:0] _T_382 = _T_379 ? io_store_datafn_hi_r[15:8] : stbuf_data_1[15:8]; // @[lsu_stbuf.scala 148:10] + wire [7:0] datain2_1 = sel_lo[1] ? _T_375 : _T_382; // @[lsu_stbuf.scala 147:54] + wire _T_386 = ~stbuf_byteen_2[1]; // @[lsu_stbuf.scala 147:70] + wire _T_388 = _T_386 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90] + wire [7:0] _T_391 = _T_388 ? io_store_datafn_lo_r[15:8] : stbuf_data_2[15:8]; // @[lsu_stbuf.scala 147:69] + wire _T_395 = _T_386 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31] + wire [7:0] _T_398 = _T_395 ? io_store_datafn_hi_r[15:8] : stbuf_data_2[15:8]; // @[lsu_stbuf.scala 148:10] + wire [7:0] datain2_2 = sel_lo[2] ? _T_391 : _T_398; // @[lsu_stbuf.scala 147:54] + wire _T_402 = ~stbuf_byteen_3[1]; // @[lsu_stbuf.scala 147:70] + wire _T_404 = _T_402 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90] + wire [7:0] _T_407 = _T_404 ? io_store_datafn_lo_r[15:8] : stbuf_data_3[15:8]; // @[lsu_stbuf.scala 147:69] + wire _T_411 = _T_402 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31] + wire [7:0] _T_414 = _T_411 ? io_store_datafn_hi_r[15:8] : stbuf_data_3[15:8]; // @[lsu_stbuf.scala 148:10] + wire [7:0] datain2_3 = sel_lo[3] ? _T_407 : _T_414; // @[lsu_stbuf.scala 147:54] + wire _T_418 = ~stbuf_byteen_0[2]; // @[lsu_stbuf.scala 150:70] + wire _T_420 = _T_418 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90] + wire [7:0] _T_423 = _T_420 ? io_store_datafn_lo_r[23:16] : stbuf_data_0[23:16]; // @[lsu_stbuf.scala 150:69] + wire _T_427 = _T_418 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31] + wire [7:0] _T_430 = _T_427 ? io_store_datafn_hi_r[23:16] : stbuf_data_0[23:16]; // @[lsu_stbuf.scala 151:10] + wire [7:0] datain3_0 = sel_lo[0] ? _T_423 : _T_430; // @[lsu_stbuf.scala 150:54] + wire _T_434 = ~stbuf_byteen_1[2]; // @[lsu_stbuf.scala 150:70] + wire _T_436 = _T_434 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90] + wire [7:0] _T_439 = _T_436 ? io_store_datafn_lo_r[23:16] : stbuf_data_1[23:16]; // @[lsu_stbuf.scala 150:69] + wire _T_443 = _T_434 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31] + wire [7:0] _T_446 = _T_443 ? io_store_datafn_hi_r[23:16] : stbuf_data_1[23:16]; // @[lsu_stbuf.scala 151:10] + wire [7:0] datain3_1 = sel_lo[1] ? _T_439 : _T_446; // @[lsu_stbuf.scala 150:54] + wire _T_450 = ~stbuf_byteen_2[2]; // @[lsu_stbuf.scala 150:70] + wire _T_452 = _T_450 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90] + wire [7:0] _T_455 = _T_452 ? io_store_datafn_lo_r[23:16] : stbuf_data_2[23:16]; // @[lsu_stbuf.scala 150:69] + wire _T_459 = _T_450 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31] + wire [7:0] _T_462 = _T_459 ? io_store_datafn_hi_r[23:16] : stbuf_data_2[23:16]; // @[lsu_stbuf.scala 151:10] + wire [7:0] datain3_2 = sel_lo[2] ? _T_455 : _T_462; // @[lsu_stbuf.scala 150:54] + wire _T_466 = ~stbuf_byteen_3[2]; // @[lsu_stbuf.scala 150:70] + wire _T_468 = _T_466 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90] + wire [7:0] _T_471 = _T_468 ? io_store_datafn_lo_r[23:16] : stbuf_data_3[23:16]; // @[lsu_stbuf.scala 150:69] + wire _T_475 = _T_466 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31] + wire [7:0] _T_478 = _T_475 ? io_store_datafn_hi_r[23:16] : stbuf_data_3[23:16]; // @[lsu_stbuf.scala 151:10] + wire [7:0] datain3_3 = sel_lo[3] ? _T_471 : _T_478; // @[lsu_stbuf.scala 150:54] + wire _T_482 = ~stbuf_byteen_0[3]; // @[lsu_stbuf.scala 153:70] + wire _T_484 = _T_482 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90] + wire [7:0] _T_487 = _T_484 ? io_store_datafn_lo_r[31:24] : stbuf_data_0[31:24]; // @[lsu_stbuf.scala 153:69] + wire _T_491 = _T_482 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31] + wire [7:0] _T_494 = _T_491 ? io_store_datafn_hi_r[31:24] : stbuf_data_0[31:24]; // @[lsu_stbuf.scala 154:10] + wire [7:0] datain4_0 = sel_lo[0] ? _T_487 : _T_494; // @[lsu_stbuf.scala 153:54] + wire _T_498 = ~stbuf_byteen_1[3]; // @[lsu_stbuf.scala 153:70] + wire _T_500 = _T_498 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90] + wire [7:0] _T_503 = _T_500 ? io_store_datafn_lo_r[31:24] : stbuf_data_1[31:24]; // @[lsu_stbuf.scala 153:69] + wire _T_507 = _T_498 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31] + wire [7:0] _T_510 = _T_507 ? io_store_datafn_hi_r[31:24] : stbuf_data_1[31:24]; // @[lsu_stbuf.scala 154:10] + wire [7:0] datain4_1 = sel_lo[1] ? _T_503 : _T_510; // @[lsu_stbuf.scala 153:54] + wire _T_514 = ~stbuf_byteen_2[3]; // @[lsu_stbuf.scala 153:70] + wire _T_516 = _T_514 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90] + wire [7:0] _T_519 = _T_516 ? io_store_datafn_lo_r[31:24] : stbuf_data_2[31:24]; // @[lsu_stbuf.scala 153:69] + wire _T_523 = _T_514 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31] + wire [7:0] _T_526 = _T_523 ? io_store_datafn_hi_r[31:24] : stbuf_data_2[31:24]; // @[lsu_stbuf.scala 154:10] + wire [7:0] datain4_2 = sel_lo[2] ? _T_519 : _T_526; // @[lsu_stbuf.scala 153:54] + wire _T_530 = ~stbuf_byteen_3[3]; // @[lsu_stbuf.scala 153:70] + wire _T_532 = _T_530 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90] + wire [7:0] _T_535 = _T_532 ? io_store_datafn_lo_r[31:24] : stbuf_data_3[31:24]; // @[lsu_stbuf.scala 153:69] + wire _T_539 = _T_530 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31] + wire [7:0] _T_542 = _T_539 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[lsu_stbuf.scala 154:10] + wire [7:0] datain4_3 = sel_lo[3] ? _T_535 : _T_542; // @[lsu_stbuf.scala 153:54] + wire [31:0] stbuf_datain_0 = {datain4_0,datain3_0,datain2_0,datain1_0}; // @[Cat.scala 29:58] + wire [31:0] stbuf_datain_1 = {datain4_1,datain3_1,datain2_1,datain1_1}; // @[Cat.scala 29:58] + wire [31:0] stbuf_datain_2 = {datain4_2,datain3_2,datain2_2,datain1_2}; // @[Cat.scala 29:58] + wire [31:0] stbuf_datain_3 = {datain4_3,datain3_3,datain2_3,datain1_3}; // @[Cat.scala 29:58] + wire _T_559 = stbuf_wr_en[0] | stbuf_vld[0]; // @[lsu_stbuf.scala 160:18] + wire _T_567 = stbuf_wr_en[1] | stbuf_vld[1]; // @[lsu_stbuf.scala 160:18] + wire _T_575 = stbuf_wr_en[2] | stbuf_vld[2]; // @[lsu_stbuf.scala 160:18] + wire _T_583 = stbuf_wr_en[3] | stbuf_vld[3]; // @[lsu_stbuf.scala 160:18] + wire [15:0] cmpaddr_hi_m = {{2'd0}, io_end_addr_m[15:2]}; // @[lsu_stbuf.scala 208:16] + wire _T_786 = stbuf_addr_3[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115] + wire _T_788 = _T_786 & stbuf_vld[3]; // @[lsu_stbuf.scala 212:139] + wire _T_791 = _T_788 & _T_63; // @[lsu_stbuf.scala 212:154] + wire _T_792 = _T_791 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175] + wire _T_777 = stbuf_addr_2[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115] + wire _T_779 = _T_777 & stbuf_vld[2]; // @[lsu_stbuf.scala 212:139] + wire _T_782 = _T_779 & _T_52; // @[lsu_stbuf.scala 212:154] + wire _T_783 = _T_782 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175] + wire _T_768 = stbuf_addr_1[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115] + wire _T_770 = _T_768 & stbuf_vld[1]; // @[lsu_stbuf.scala 212:139] + wire _T_773 = _T_770 & _T_41; // @[lsu_stbuf.scala 212:154] + wire _T_774 = _T_773 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175] + wire _T_759 = stbuf_addr_0[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115] + wire _T_761 = _T_759 & stbuf_vld[0]; // @[lsu_stbuf.scala 212:139] + wire _T_764 = _T_761 & _T_30; // @[lsu_stbuf.scala 212:154] + wire _T_765 = _T_764 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175] + wire [3:0] stbuf_match_hi = {_T_792,_T_783,_T_774,_T_765}; // @[Cat.scala 29:58] + wire [15:0] cmpaddr_lo_m = {{2'd0}, io_lsu_addr_m[15:2]}; // @[lsu_stbuf.scala 209:17] + wire _T_824 = stbuf_addr_3[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115] + wire _T_826 = _T_824 & stbuf_vld[3]; // @[lsu_stbuf.scala 213:139] + wire _T_829 = _T_826 & _T_63; // @[lsu_stbuf.scala 213:154] + wire _T_830 = _T_829 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175] + wire _T_815 = stbuf_addr_2[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115] + wire _T_817 = _T_815 & stbuf_vld[2]; // @[lsu_stbuf.scala 213:139] + wire _T_820 = _T_817 & _T_52; // @[lsu_stbuf.scala 213:154] + wire _T_821 = _T_820 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175] + wire _T_806 = stbuf_addr_1[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115] + wire _T_808 = _T_806 & stbuf_vld[1]; // @[lsu_stbuf.scala 213:139] + wire _T_811 = _T_808 & _T_41; // @[lsu_stbuf.scala 213:154] + wire _T_812 = _T_811 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175] + wire _T_797 = stbuf_addr_0[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115] + wire _T_799 = _T_797 & stbuf_vld[0]; // @[lsu_stbuf.scala 213:139] + wire _T_802 = _T_799 & _T_30; // @[lsu_stbuf.scala 213:154] + wire _T_803 = _T_802 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175] + wire [3:0] stbuf_match_lo = {_T_830,_T_821,_T_812,_T_803}; // @[Cat.scala 29:58] + wire _T_853 = stbuf_match_hi[3] | stbuf_match_lo[3]; // @[lsu_stbuf.scala 214:78] + wire _T_854 = _T_853 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99] + wire _T_855 = _T_854 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120] + wire _T_856 = _T_855 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144] + wire _T_847 = stbuf_match_hi[2] | stbuf_match_lo[2]; // @[lsu_stbuf.scala 214:78] + wire _T_848 = _T_847 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99] + wire _T_849 = _T_848 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120] + wire _T_850 = _T_849 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144] + wire _T_841 = stbuf_match_hi[1] | stbuf_match_lo[1]; // @[lsu_stbuf.scala 214:78] + wire _T_842 = _T_841 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99] + wire _T_843 = _T_842 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120] + wire _T_844 = _T_843 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144] + wire _T_835 = stbuf_match_hi[0] | stbuf_match_lo[0]; // @[lsu_stbuf.scala 214:78] + wire _T_836 = _T_835 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99] + wire _T_837 = _T_836 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120] + wire _T_838 = _T_837 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144] + wire [3:0] stbuf_dma_kill_en = {_T_856,_T_850,_T_844,_T_838}; // @[Cat.scala 29:58] + wire _T_594 = stbuf_dma_kill_en[0] | stbuf_dma_kill[0]; // @[lsu_stbuf.scala 163:18] + wire _T_602 = stbuf_dma_kill_en[1] | stbuf_dma_kill[1]; // @[lsu_stbuf.scala 163:18] + wire _T_610 = stbuf_dma_kill_en[2] | stbuf_dma_kill[2]; // @[lsu_stbuf.scala 163:18] + wire _T_618 = stbuf_dma_kill_en[3] | stbuf_dma_kill[3]; // @[lsu_stbuf.scala 163:18] + wire [3:0] _T_628 = stbuf_wr_en[0] ? stbuf_byteenin_0 : stbuf_byteen_0; // @[lsu_stbuf.scala 166:18] + wire [3:0] _T_632 = _T_33 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_637 = stbuf_wr_en[1] ? stbuf_byteenin_1 : stbuf_byteen_1; // @[lsu_stbuf.scala 166:18] + wire [3:0] _T_641 = _T_44 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_646 = stbuf_wr_en[2] ? stbuf_byteenin_2 : stbuf_byteen_2; // @[lsu_stbuf.scala 166:18] + wire [3:0] _T_650 = _T_55 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_655 = stbuf_wr_en[3] ? stbuf_byteenin_3 : stbuf_byteen_3; // @[lsu_stbuf.scala 166:18] + wire [3:0] _T_659 = _T_66 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_686 = stbuf_vld >> RdPtr; // @[lsu_stbuf.scala 183:43] + wire [3:0] _T_688 = stbuf_dma_kill >> RdPtr; // @[lsu_stbuf.scala 183:67] + wire _T_695 = ~_T_688[0]; // @[lsu_stbuf.scala 184:46] + wire _T_696 = _T_686[0] & _T_695; // @[lsu_stbuf.scala 184:44] + wire _T_697 = |stbuf_dma_kill_en; // @[lsu_stbuf.scala 184:91] + wire _T_698 = ~_T_697; // @[lsu_stbuf.scala 184:71] + wire [15:0] _GEN_9 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[lsu_stbuf.scala 185:22] + wire [15:0] _GEN_10 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_9; // @[lsu_stbuf.scala 185:22] + wire [31:0] _GEN_13 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[lsu_stbuf.scala 186:22] + wire [31:0] _GEN_14 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_13; // @[lsu_stbuf.scala 186:22] + wire _T_700 = ~dual_stbuf_write_r; // @[lsu_stbuf.scala 188:44] + wire _T_701 = io_ldst_stbuf_reqvld_r & _T_700; // @[lsu_stbuf.scala 188:42] + wire _T_702 = store_coalesce_hi_r | store_coalesce_lo_r; // @[lsu_stbuf.scala 188:88] + wire _T_703 = ~_T_702; // @[lsu_stbuf.scala 188:66] + wire _T_704 = _T_701 & _T_703; // @[lsu_stbuf.scala 188:64] + wire _T_705 = io_ldst_stbuf_reqvld_r & dual_stbuf_write_r; // @[lsu_stbuf.scala 189:30] + wire _T_706 = store_coalesce_hi_r & store_coalesce_lo_r; // @[lsu_stbuf.scala 189:76] + wire _T_707 = ~_T_706; // @[lsu_stbuf.scala 189:54] + wire _T_708 = _T_705 & _T_707; // @[lsu_stbuf.scala 189:52] + wire WrPtrEn = _T_704 | _T_708; // @[lsu_stbuf.scala 188:113] + wire _T_713 = _T_705 & _T_703; // @[lsu_stbuf.scala 190:67] + wire [3:0] _T_718 = {3'h0,stbuf_vld[0]}; // @[Cat.scala 29:58] + wire [3:0] _T_720 = {3'h0,stbuf_vld[1]}; // @[Cat.scala 29:58] + wire [3:0] _T_722 = {3'h0,stbuf_vld[2]}; // @[Cat.scala 29:58] + wire [3:0] _T_724 = {3'h0,stbuf_vld[3]}; // @[Cat.scala 29:58] + wire [3:0] _T_727 = _T_718 + _T_720; // @[lsu_stbuf.scala 197:101] + wire [3:0] _T_729 = _T_727 + _T_722; // @[lsu_stbuf.scala 197:101] + wire [3:0] stbuf_numvld_any = _T_729 + _T_724; // @[lsu_stbuf.scala 197:101] + wire _T_731 = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 198:39] + wire _T_732 = _T_731 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 198:65] + wire _T_733 = ~io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 198:87] + wire isdccmst_m = _T_732 & _T_733; // @[lsu_stbuf.scala 198:85] + wire _T_734 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 199:39] + wire _T_735 = _T_734 & io_addr_in_dccm_r; // @[lsu_stbuf.scala 199:65] + wire _T_736 = ~io_lsu_pkt_r_bits_dma; // @[lsu_stbuf.scala 199:87] + wire isdccmst_r = _T_735 & _T_736; // @[lsu_stbuf.scala 199:85] + wire [1:0] _T_737 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58] + wire _T_738 = isdccmst_m & io_ldst_dual_m; // @[lsu_stbuf.scala 201:62] + wire [2:0] _GEN_22 = {{1'd0}, _T_737}; // @[lsu_stbuf.scala 201:47] + wire [2:0] _T_739 = _GEN_22 << _T_738; // @[lsu_stbuf.scala 201:47] + wire [1:0] _T_740 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58] + wire _T_741 = isdccmst_r & io_ldst_dual_r; // @[lsu_stbuf.scala 202:62] + wire [2:0] _GEN_23 = {{1'd0}, _T_740}; // @[lsu_stbuf.scala 202:47] + wire [2:0] _T_742 = _GEN_23 << _T_741; // @[lsu_stbuf.scala 202:47] + wire [1:0] stbuf_specvld_m = _T_739[1:0]; // @[lsu_stbuf.scala 201:19] + wire [3:0] _T_743 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58] + wire [3:0] _T_745 = stbuf_numvld_any + _T_743; // @[lsu_stbuf.scala 203:44] + wire [1:0] stbuf_specvld_r = _T_742[1:0]; // @[lsu_stbuf.scala 202:19] + wire [3:0] _T_746 = {2'h0,stbuf_specvld_r}; // @[Cat.scala 29:58] + wire [3:0] stbuf_specvld_any = _T_745 + _T_746; // @[lsu_stbuf.scala 203:78] + wire _T_748 = ~io_ldst_dual_d; // @[lsu_stbuf.scala 205:34] + wire _T_749 = _T_748 & io_dec_lsu_valid_raw_d; // @[lsu_stbuf.scala 205:50] + wire _T_751 = stbuf_specvld_any >= 4'h4; // @[lsu_stbuf.scala 205:102] + wire _T_752 = stbuf_specvld_any >= 4'h3; // @[lsu_stbuf.scala 205:143] + wire _T_862 = stbuf_match_hi[0] & stbuf_byteen_0[0]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_0 = _T_862 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137] + wire _T_866 = stbuf_match_hi[0] & stbuf_byteen_0[1]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_1 = _T_866 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137] + wire _T_870 = stbuf_match_hi[0] & stbuf_byteen_0[2]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_2 = _T_870 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137] + wire _T_874 = stbuf_match_hi[0] & stbuf_byteen_0[3]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_3 = _T_874 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137] + wire _T_878 = stbuf_match_hi[1] & stbuf_byteen_1[0]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_0 = _T_878 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137] + wire _T_882 = stbuf_match_hi[1] & stbuf_byteen_1[1]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_1 = _T_882 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137] + wire _T_886 = stbuf_match_hi[1] & stbuf_byteen_1[2]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_2 = _T_886 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137] + wire _T_890 = stbuf_match_hi[1] & stbuf_byteen_1[3]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_3 = _T_890 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137] + wire _T_894 = stbuf_match_hi[2] & stbuf_byteen_2[0]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_0 = _T_894 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137] + wire _T_898 = stbuf_match_hi[2] & stbuf_byteen_2[1]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_1 = _T_898 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137] + wire _T_902 = stbuf_match_hi[2] & stbuf_byteen_2[2]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_2 = _T_902 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137] + wire _T_906 = stbuf_match_hi[2] & stbuf_byteen_2[3]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_3 = _T_906 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137] + wire _T_910 = stbuf_match_hi[3] & stbuf_byteen_3[0]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_0 = _T_910 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137] + wire _T_914 = stbuf_match_hi[3] & stbuf_byteen_3[1]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_1 = _T_914 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137] + wire _T_918 = stbuf_match_hi[3] & stbuf_byteen_3[2]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_2 = _T_918 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137] + wire _T_922 = stbuf_match_hi[3] & stbuf_byteen_3[3]; // @[lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_3 = _T_922 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137] + wire _T_926 = stbuf_match_lo[0] & stbuf_byteen_0[0]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_0 = _T_926 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137] + wire _T_930 = stbuf_match_lo[0] & stbuf_byteen_0[1]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_1 = _T_930 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137] + wire _T_934 = stbuf_match_lo[0] & stbuf_byteen_0[2]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_2 = _T_934 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137] + wire _T_938 = stbuf_match_lo[0] & stbuf_byteen_0[3]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_3 = _T_938 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137] + wire _T_942 = stbuf_match_lo[1] & stbuf_byteen_1[0]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_0 = _T_942 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137] + wire _T_946 = stbuf_match_lo[1] & stbuf_byteen_1[1]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_1 = _T_946 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137] + wire _T_950 = stbuf_match_lo[1] & stbuf_byteen_1[2]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_2 = _T_950 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137] + wire _T_954 = stbuf_match_lo[1] & stbuf_byteen_1[3]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_3 = _T_954 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137] + wire _T_958 = stbuf_match_lo[2] & stbuf_byteen_2[0]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_0 = _T_958 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137] + wire _T_962 = stbuf_match_lo[2] & stbuf_byteen_2[1]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_1 = _T_962 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137] + wire _T_966 = stbuf_match_lo[2] & stbuf_byteen_2[2]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_2 = _T_966 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137] + wire _T_970 = stbuf_match_lo[2] & stbuf_byteen_2[3]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_3 = _T_970 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137] + wire _T_974 = stbuf_match_lo[3] & stbuf_byteen_3[0]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_0 = _T_974 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137] + wire _T_978 = stbuf_match_lo[3] & stbuf_byteen_3[1]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_1 = _T_978 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137] + wire _T_982 = stbuf_match_lo[3] & stbuf_byteen_3[2]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_2 = _T_982 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137] + wire _T_986 = stbuf_match_lo[3] & stbuf_byteen_3[3]; // @[lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_3 = _T_986 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137] + wire _T_988 = stbuf_fwdbyteenvec_hi_0_0 | stbuf_fwdbyteenvec_hi_1_0; // @[lsu_stbuf.scala 219:147] + wire _T_989 = _T_988 | stbuf_fwdbyteenvec_hi_2_0; // @[lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_0 = _T_989 | stbuf_fwdbyteenvec_hi_3_0; // @[lsu_stbuf.scala 219:147] + wire _T_990 = stbuf_fwdbyteenvec_hi_0_1 | stbuf_fwdbyteenvec_hi_1_1; // @[lsu_stbuf.scala 219:147] + wire _T_991 = _T_990 | stbuf_fwdbyteenvec_hi_2_1; // @[lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_1 = _T_991 | stbuf_fwdbyteenvec_hi_3_1; // @[lsu_stbuf.scala 219:147] + wire _T_992 = stbuf_fwdbyteenvec_hi_0_2 | stbuf_fwdbyteenvec_hi_1_2; // @[lsu_stbuf.scala 219:147] + wire _T_993 = _T_992 | stbuf_fwdbyteenvec_hi_2_2; // @[lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_2 = _T_993 | stbuf_fwdbyteenvec_hi_3_2; // @[lsu_stbuf.scala 219:147] + wire _T_994 = stbuf_fwdbyteenvec_hi_0_3 | stbuf_fwdbyteenvec_hi_1_3; // @[lsu_stbuf.scala 219:147] + wire _T_995 = _T_994 | stbuf_fwdbyteenvec_hi_2_3; // @[lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_3 = _T_995 | stbuf_fwdbyteenvec_hi_3_3; // @[lsu_stbuf.scala 219:147] + wire _T_996 = stbuf_fwdbyteenvec_lo_0_0 | stbuf_fwdbyteenvec_lo_1_0; // @[lsu_stbuf.scala 220:147] + wire _T_997 = _T_996 | stbuf_fwdbyteenvec_lo_2_0; // @[lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_0 = _T_997 | stbuf_fwdbyteenvec_lo_3_0; // @[lsu_stbuf.scala 220:147] + wire _T_998 = stbuf_fwdbyteenvec_lo_0_1 | stbuf_fwdbyteenvec_lo_1_1; // @[lsu_stbuf.scala 220:147] + wire _T_999 = _T_998 | stbuf_fwdbyteenvec_lo_2_1; // @[lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_1 = _T_999 | stbuf_fwdbyteenvec_lo_3_1; // @[lsu_stbuf.scala 220:147] + wire _T_1000 = stbuf_fwdbyteenvec_lo_0_2 | stbuf_fwdbyteenvec_lo_1_2; // @[lsu_stbuf.scala 220:147] + wire _T_1001 = _T_1000 | stbuf_fwdbyteenvec_lo_2_2; // @[lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_2 = _T_1001 | stbuf_fwdbyteenvec_lo_3_2; // @[lsu_stbuf.scala 220:147] + wire _T_1002 = stbuf_fwdbyteenvec_lo_0_3 | stbuf_fwdbyteenvec_lo_1_3; // @[lsu_stbuf.scala 220:147] + wire _T_1003 = _T_1002 | stbuf_fwdbyteenvec_lo_2_3; // @[lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_3 = _T_1003 | stbuf_fwdbyteenvec_lo_3_3; // @[lsu_stbuf.scala 220:147] + wire [31:0] _T_1006 = stbuf_match_hi[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1007 = _T_1006 & stbuf_data_0; // @[lsu_stbuf.scala 222:97] + wire [31:0] _T_1010 = stbuf_match_hi[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1011 = _T_1010 & stbuf_data_1; // @[lsu_stbuf.scala 222:97] + wire [31:0] _T_1014 = stbuf_match_hi[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1015 = _T_1014 & stbuf_data_2; // @[lsu_stbuf.scala 222:97] + wire [31:0] _T_1018 = stbuf_match_hi[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1019 = _T_1018 & stbuf_data_3; // @[lsu_stbuf.scala 222:97] + wire [31:0] _T_1021 = _T_1019 | _T_1015; // @[lsu_stbuf.scala 222:130] + wire [31:0] _T_1022 = _T_1021 | _T_1011; // @[lsu_stbuf.scala 222:130] + wire [31:0] stbuf_fwddata_hi_pre_m = _T_1022 | _T_1007; // @[lsu_stbuf.scala 222:130] + wire [31:0] _T_1025 = stbuf_match_lo[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1026 = _T_1025 & stbuf_data_0; // @[lsu_stbuf.scala 223:97] + wire [31:0] _T_1029 = stbuf_match_lo[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1030 = _T_1029 & stbuf_data_1; // @[lsu_stbuf.scala 223:97] + wire [31:0] _T_1033 = stbuf_match_lo[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1034 = _T_1033 & stbuf_data_2; // @[lsu_stbuf.scala 223:97] + wire [31:0] _T_1037 = stbuf_match_lo[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1038 = _T_1037 & stbuf_data_3; // @[lsu_stbuf.scala 223:97] + wire [31:0] _T_1040 = _T_1038 | _T_1034; // @[lsu_stbuf.scala 223:130] + wire [31:0] _T_1041 = _T_1040 | _T_1030; // @[lsu_stbuf.scala 223:130] + wire [31:0] stbuf_fwddata_lo_pre_m = _T_1041 | _T_1026; // @[lsu_stbuf.scala 223:130] + wire _T_1046 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_stbuf.scala 230:49] + wire _T_1047 = _T_1046 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 230:74] + wire _T_1048 = _T_1047 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 230:95] + wire ld_addr_rhit_lo_lo = _T_1048 & _T_736; // @[lsu_stbuf.scala 230:121] + wire _T_1052 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_stbuf.scala 231:49] + wire _T_1053 = _T_1052 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 231:74] + wire _T_1054 = _T_1053 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 231:95] + wire ld_addr_rhit_lo_hi = _T_1054 & _T_736; // @[lsu_stbuf.scala 231:121] + wire _T_1058 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_stbuf.scala 232:49] + wire _T_1059 = _T_1058 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 232:74] + wire _T_1060 = _T_1059 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 232:95] + wire _T_1062 = _T_1060 & _T_736; // @[lsu_stbuf.scala 232:121] + wire ld_addr_rhit_hi_lo = _T_1062 & dual_stbuf_write_r; // @[lsu_stbuf.scala 232:146] + wire _T_1065 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_stbuf.scala 233:49] + wire _T_1066 = _T_1065 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 233:74] + wire _T_1067 = _T_1066 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 233:95] + wire _T_1069 = _T_1067 & _T_736; // @[lsu_stbuf.scala 233:121] + wire ld_addr_rhit_hi_hi = _T_1069 & dual_stbuf_write_r; // @[lsu_stbuf.scala 233:146] + wire _T_1071 = ld_addr_rhit_lo_lo & store_byteen_ext_r[0]; // @[lsu_stbuf.scala 235:79] + wire _T_1073 = ld_addr_rhit_lo_lo & store_byteen_ext_r[1]; // @[lsu_stbuf.scala 235:79] + wire _T_1075 = ld_addr_rhit_lo_lo & store_byteen_ext_r[2]; // @[lsu_stbuf.scala 235:79] + wire _T_1077 = ld_addr_rhit_lo_lo & store_byteen_ext_r[3]; // @[lsu_stbuf.scala 235:79] + wire [3:0] ld_byte_rhit_lo_lo = {_T_1077,_T_1075,_T_1073,_T_1071}; // @[Cat.scala 29:58] + wire _T_1082 = ld_addr_rhit_lo_hi & store_byteen_ext_r[0]; // @[lsu_stbuf.scala 236:79] + wire _T_1084 = ld_addr_rhit_lo_hi & store_byteen_ext_r[1]; // @[lsu_stbuf.scala 236:79] + wire _T_1086 = ld_addr_rhit_lo_hi & store_byteen_ext_r[2]; // @[lsu_stbuf.scala 236:79] + wire _T_1088 = ld_addr_rhit_lo_hi & store_byteen_ext_r[3]; // @[lsu_stbuf.scala 236:79] + wire [3:0] ld_byte_rhit_lo_hi = {_T_1088,_T_1086,_T_1084,_T_1082}; // @[Cat.scala 29:58] + wire _T_1093 = ld_addr_rhit_hi_lo & store_byteen_ext_r[4]; // @[lsu_stbuf.scala 237:79] + wire _T_1095 = ld_addr_rhit_hi_lo & store_byteen_ext_r[5]; // @[lsu_stbuf.scala 237:79] + wire _T_1097 = ld_addr_rhit_hi_lo & store_byteen_ext_r[6]; // @[lsu_stbuf.scala 237:79] + wire _T_1099 = ld_addr_rhit_hi_lo & store_byteen_ext_r[7]; // @[lsu_stbuf.scala 237:79] + wire [3:0] ld_byte_rhit_hi_lo = {_T_1099,_T_1097,_T_1095,_T_1093}; // @[Cat.scala 29:58] + wire _T_1104 = ld_addr_rhit_hi_hi & store_byteen_ext_r[4]; // @[lsu_stbuf.scala 238:79] + wire _T_1106 = ld_addr_rhit_hi_hi & store_byteen_ext_r[5]; // @[lsu_stbuf.scala 238:79] + wire _T_1108 = ld_addr_rhit_hi_hi & store_byteen_ext_r[6]; // @[lsu_stbuf.scala 238:79] + wire _T_1110 = ld_addr_rhit_hi_hi & store_byteen_ext_r[7]; // @[lsu_stbuf.scala 238:79] + wire [3:0] ld_byte_rhit_hi_hi = {_T_1110,_T_1108,_T_1106,_T_1104}; // @[Cat.scala 29:58] + wire _T_1116 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_stbuf.scala 240:79] + wire _T_1119 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_stbuf.scala 240:79] + wire _T_1122 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_stbuf.scala 240:79] + wire _T_1125 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_stbuf.scala 240:79] + wire [3:0] ld_byte_rhit_lo = {_T_1125,_T_1122,_T_1119,_T_1116}; // @[Cat.scala 29:58] + wire _T_1131 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_stbuf.scala 241:79] + wire _T_1134 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_stbuf.scala 241:79] + wire _T_1137 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_stbuf.scala 241:79] + wire _T_1140 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_stbuf.scala 241:79] + wire [3:0] ld_byte_rhit_hi = {_T_1140,_T_1137,_T_1134,_T_1131}; // @[Cat.scala 29:58] + wire [7:0] _T_1146 = ld_byte_rhit_lo_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1148 = _T_1146 & io_store_data_lo_r[7:0]; // @[lsu_stbuf.scala 243:53] + wire [7:0] _T_1151 = ld_byte_rhit_hi_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1153 = _T_1151 & io_store_data_hi_r[7:0]; // @[lsu_stbuf.scala 243:114] + wire [7:0] fwdpipe1_lo = _T_1148 | _T_1153; // @[lsu_stbuf.scala 243:80] + wire [7:0] _T_1156 = ld_byte_rhit_lo_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1158 = _T_1156 & io_store_data_lo_r[15:8]; // @[lsu_stbuf.scala 244:53] + wire [7:0] _T_1161 = ld_byte_rhit_hi_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1163 = _T_1161 & io_store_data_hi_r[15:8]; // @[lsu_stbuf.scala 244:115] + wire [7:0] fwdpipe2_lo = _T_1158 | _T_1163; // @[lsu_stbuf.scala 244:81] + wire [7:0] _T_1166 = ld_byte_rhit_lo_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1168 = _T_1166 & io_store_data_lo_r[23:16]; // @[lsu_stbuf.scala 245:53] + wire [7:0] _T_1171 = ld_byte_rhit_hi_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1173 = _T_1171 & io_store_data_hi_r[23:16]; // @[lsu_stbuf.scala 245:116] + wire [7:0] fwdpipe3_lo = _T_1168 | _T_1173; // @[lsu_stbuf.scala 245:82] + wire [7:0] _T_1176 = ld_byte_rhit_lo_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1178 = _T_1176 & io_store_data_lo_r[31:24]; // @[lsu_stbuf.scala 246:53] + wire [7:0] _T_1181 = ld_byte_rhit_hi_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1183 = _T_1181 & io_store_data_hi_r[31:24]; // @[lsu_stbuf.scala 246:116] + wire [7:0] fwdpipe4_lo = _T_1178 | _T_1183; // @[lsu_stbuf.scala 246:82] + wire [31:0] ld_fwddata_rpipe_lo = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58] + wire [7:0] _T_1189 = ld_byte_rhit_lo_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1191 = _T_1189 & io_store_data_lo_r[7:0]; // @[lsu_stbuf.scala 249:53] + wire [7:0] _T_1194 = ld_byte_rhit_hi_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1196 = _T_1194 & io_store_data_hi_r[7:0]; // @[lsu_stbuf.scala 249:114] + wire [7:0] fwdpipe1_hi = _T_1191 | _T_1196; // @[lsu_stbuf.scala 249:80] + wire [7:0] _T_1199 = ld_byte_rhit_lo_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1201 = _T_1199 & io_store_data_lo_r[15:8]; // @[lsu_stbuf.scala 250:53] + wire [7:0] _T_1204 = ld_byte_rhit_hi_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1206 = _T_1204 & io_store_data_hi_r[15:8]; // @[lsu_stbuf.scala 250:115] + wire [7:0] fwdpipe2_hi = _T_1201 | _T_1206; // @[lsu_stbuf.scala 250:81] + wire [7:0] _T_1209 = ld_byte_rhit_lo_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1211 = _T_1209 & io_store_data_lo_r[23:16]; // @[lsu_stbuf.scala 251:53] + wire [7:0] _T_1214 = ld_byte_rhit_hi_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1216 = _T_1214 & io_store_data_hi_r[23:16]; // @[lsu_stbuf.scala 251:116] + wire [7:0] fwdpipe3_hi = _T_1211 | _T_1216; // @[lsu_stbuf.scala 251:82] + wire [7:0] _T_1219 = ld_byte_rhit_lo_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1221 = _T_1219 & io_store_data_lo_r[31:24]; // @[lsu_stbuf.scala 252:53] + wire [7:0] _T_1224 = ld_byte_rhit_hi_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1226 = _T_1224 & io_store_data_hi_r[31:24]; // @[lsu_stbuf.scala 252:116] + wire [7:0] fwdpipe4_hi = _T_1221 | _T_1226; // @[lsu_stbuf.scala 252:82] + wire [31:0] ld_fwddata_rpipe_hi = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58] + wire _T_1261 = ld_byte_rhit_hi[0] | stbuf_fwdbyteen_hi_pre_m_0; // @[lsu_stbuf.scala 258:83] + wire _T_1263 = ld_byte_rhit_hi[1] | stbuf_fwdbyteen_hi_pre_m_1; // @[lsu_stbuf.scala 258:83] + wire _T_1265 = ld_byte_rhit_hi[2] | stbuf_fwdbyteen_hi_pre_m_2; // @[lsu_stbuf.scala 258:83] + wire _T_1267 = ld_byte_rhit_hi[3] | stbuf_fwdbyteen_hi_pre_m_3; // @[lsu_stbuf.scala 258:83] + wire [2:0] _T_1269 = {_T_1267,_T_1265,_T_1263}; // @[Cat.scala 29:58] + wire _T_1272 = ld_byte_rhit_lo[0] | stbuf_fwdbyteen_lo_pre_m_0; // @[lsu_stbuf.scala 259:83] + wire _T_1274 = ld_byte_rhit_lo[1] | stbuf_fwdbyteen_lo_pre_m_1; // @[lsu_stbuf.scala 259:83] + wire _T_1276 = ld_byte_rhit_lo[2] | stbuf_fwdbyteen_lo_pre_m_2; // @[lsu_stbuf.scala 259:83] + wire _T_1278 = ld_byte_rhit_lo[3] | stbuf_fwdbyteen_lo_pre_m_3; // @[lsu_stbuf.scala 259:83] + wire [2:0] _T_1280 = {_T_1278,_T_1276,_T_1274}; // @[Cat.scala 29:58] + wire [7:0] stbuf_fwdpipe1_lo = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : stbuf_fwddata_lo_pre_m[7:0]; // @[lsu_stbuf.scala 262:30] + wire [7:0] stbuf_fwdpipe2_lo = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : stbuf_fwddata_lo_pre_m[15:8]; // @[lsu_stbuf.scala 263:30] + wire [7:0] stbuf_fwdpipe3_lo = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : stbuf_fwddata_lo_pre_m[23:16]; // @[lsu_stbuf.scala 264:30] + wire [7:0] stbuf_fwdpipe4_lo = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : stbuf_fwddata_lo_pre_m[31:24]; // @[lsu_stbuf.scala 265:30] + wire [15:0] _T_1294 = {stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo}; // @[Cat.scala 29:58] + wire [15:0] _T_1295 = {stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo}; // @[Cat.scala 29:58] + wire [7:0] stbuf_fwdpipe1_hi = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : stbuf_fwddata_hi_pre_m[7:0]; // @[lsu_stbuf.scala 268:30] + wire [7:0] stbuf_fwdpipe2_hi = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : stbuf_fwddata_hi_pre_m[15:8]; // @[lsu_stbuf.scala 269:30] + wire [7:0] stbuf_fwdpipe3_hi = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : stbuf_fwddata_hi_pre_m[23:16]; // @[lsu_stbuf.scala 270:30] + wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[lsu_stbuf.scala 271:30] + wire [15:0] _T_1309 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58] + wire [15:0] _T_1310 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + assign io_stbuf_reqvld_any = _T_696 & _T_698; // @[lsu_stbuf.scala 51:47 lsu_stbuf.scala 184:24] + assign io_stbuf_reqvld_flushed_any = _T_686[0] & _T_688[0]; // @[lsu_stbuf.scala 52:35 lsu_stbuf.scala 183:31] + assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_10; // @[lsu_stbuf.scala 53:35 lsu_stbuf.scala 185:22] + assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_14; // @[lsu_stbuf.scala 54:35 lsu_stbuf.scala 186:22] + assign io_lsu_stbuf_full_any = _T_749 ? _T_751 : _T_752; // @[lsu_stbuf.scala 55:43 lsu_stbuf.scala 205:26] + assign io_ldst_stbuf_reqvld_r = _T_22 & io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 57:43 lsu_stbuf.scala 125:26] + assign io_stbuf_fwddata_hi_m = {_T_1310,_T_1309}; // @[lsu_stbuf.scala 58:43 lsu_stbuf.scala 272:25] + assign io_stbuf_fwddata_lo_m = {_T_1295,_T_1294}; // @[lsu_stbuf.scala 59:43 lsu_stbuf.scala 266:25] + assign io_stbuf_fwdbyteen_hi_m = {_T_1269,_T_1261}; // @[lsu_stbuf.scala 60:37 lsu_stbuf.scala 258:27] + assign io_stbuf_fwdbyteen_lo_m = {_T_1280,_T_1272}; // @[lsu_stbuf.scala 61:37 lsu_stbuf.scala 259:27] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + RdPtr = _RAND_0[1:0]; + _RAND_1 = {1{`RANDOM}}; + WrPtr = _RAND_1[1:0]; + _RAND_2 = {1{`RANDOM}}; + stbuf_addr_0 = _RAND_2[15:0]; + _RAND_3 = {1{`RANDOM}}; + _T_587 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_579 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_571 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_563 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_622 = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + _T_614 = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + _T_606 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + _T_598 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + stbuf_addr_1 = _RAND_11[15:0]; + _RAND_12 = {1{`RANDOM}}; + stbuf_addr_2 = _RAND_12[15:0]; + _RAND_13 = {1{`RANDOM}}; + stbuf_addr_3 = _RAND_13[15:0]; + _RAND_14 = {1{`RANDOM}}; + stbuf_byteen_0 = _RAND_14[3:0]; + _RAND_15 = {1{`RANDOM}}; + stbuf_byteen_1 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + stbuf_byteen_2 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + stbuf_byteen_3 = _RAND_17[3:0]; + _RAND_18 = {1{`RANDOM}}; + stbuf_data_0 = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + stbuf_data_1 = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + stbuf_data_2 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + stbuf_data_3 = _RAND_21[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + RdPtr = 2'h0; + end + if (reset) begin + WrPtr = 2'h0; + end + if (reset) begin + stbuf_addr_0 = 16'h0; + end + if (reset) begin + _T_587 = 1'h0; + end + if (reset) begin + _T_579 = 1'h0; + end + if (reset) begin + _T_571 = 1'h0; + end + if (reset) begin + _T_563 = 1'h0; + end + if (reset) begin + _T_622 = 1'h0; + end + if (reset) begin + _T_614 = 1'h0; + end + if (reset) begin + _T_606 = 1'h0; + end + if (reset) begin + _T_598 = 1'h0; + end + if (reset) begin + stbuf_addr_1 = 16'h0; + end + if (reset) begin + stbuf_addr_2 = 16'h0; + end + if (reset) begin + stbuf_addr_3 = 16'h0; + end + if (reset) begin + stbuf_byteen_0 = 4'h0; + end + if (reset) begin + stbuf_byteen_1 = 4'h0; + end + if (reset) begin + stbuf_byteen_2 = 4'h0; + end + if (reset) begin + stbuf_byteen_3 = 4'h0; + end + if (reset) begin + stbuf_data_0 = 32'h0; + end + if (reset) begin + stbuf_data_1 = 32'h0; + end + if (reset) begin + stbuf_data_2 = 32'h0; + end + if (reset) begin + stbuf_data_3 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + RdPtr <= 2'h0; + end else if (_T_211) begin + RdPtr <= RdPtrPlus1; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + WrPtr <= 2'h0; + end else if (WrPtrEn) begin + if (_T_713) begin + WrPtr <= WrPtrPlus2; + end else begin + WrPtr <= WrPtrPlus1; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_addr_0 <= 16'h0; + end else if (stbuf_wr_en[0]) begin + if (sel_lo[0]) begin + stbuf_addr_0 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_0 <= io_end_addr_r[15:0]; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_587 <= 1'h0; + end else begin + _T_587 <= _T_583 & _T_66; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_579 <= 1'h0; + end else begin + _T_579 <= _T_575 & _T_55; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_571 <= 1'h0; + end else begin + _T_571 <= _T_567 & _T_44; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_563 <= 1'h0; + end else begin + _T_563 <= _T_559 & _T_33; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_622 <= 1'h0; + end else begin + _T_622 <= _T_618 & _T_66; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_614 <= 1'h0; + end else begin + _T_614 <= _T_610 & _T_55; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_606 <= 1'h0; + end else begin + _T_606 <= _T_602 & _T_44; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_598 <= 1'h0; + end else begin + _T_598 <= _T_594 & _T_33; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_addr_1 <= 16'h0; + end else if (stbuf_wr_en[1]) begin + if (sel_lo[1]) begin + stbuf_addr_1 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_1 <= io_end_addr_r[15:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_addr_2 <= 16'h0; + end else if (stbuf_wr_en[2]) begin + if (sel_lo[2]) begin + stbuf_addr_2 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_2 <= io_end_addr_r[15:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_addr_3 <= 16'h0; + end else if (stbuf_wr_en[3]) begin + if (sel_lo[3]) begin + stbuf_addr_3 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_3 <= io_end_addr_r[15:0]; + end + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_0 <= 4'h0; + end else begin + stbuf_byteen_0 <= _T_628 & _T_632; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_1 <= 4'h0; + end else begin + stbuf_byteen_1 <= _T_637 & _T_641; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_2 <= 4'h0; + end else begin + stbuf_byteen_2 <= _T_646 & _T_650; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_3 <= 4'h0; + end else begin + stbuf_byteen_3 <= _T_655 & _T_659; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_data_0 <= 32'h0; + end else if (stbuf_wr_en[0]) begin + stbuf_data_0 <= stbuf_datain_0; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_data_1 <= 32'h0; + end else if (stbuf_wr_en[1]) begin + stbuf_data_1 <= stbuf_datain_1; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_data_2 <= 32'h0; + end else if (stbuf_wr_en[2]) begin + stbuf_data_2 <= stbuf_datain_2; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + stbuf_data_3 <= 32'h0; + end else if (stbuf_wr_en[3]) begin + stbuf_data_3 <= stbuf_datain_3; + end + end +endmodule +module lsu_ecc( + input clock, + input reset, + input io_lsu_c2_r_clk, + input io_clk_override, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input [31:0] io_stbuf_data_any, + input io_dec_tlu_core_ecc_disable, + input [15:0] io_lsu_addr_m, + input [15:0] io_end_addr_m, + input [31:0] io_dccm_rdata_hi_m, + input [31:0] io_dccm_rdata_lo_m, + input [6:0] io_dccm_data_ecc_hi_m, + input [6:0] io_dccm_data_ecc_lo_m, + input io_ld_single_ecc_error_r, + input io_ld_single_ecc_error_r_ff, + input io_lsu_dccm_rden_m, + input io_addr_in_dccm_m, + input io_dma_dccm_wen, + input [31:0] io_dma_dccm_wdata_lo, + input [31:0] io_dma_dccm_wdata_hi, + output [31:0] io_sec_data_hi_r, + output [31:0] io_sec_data_lo_r, + output [31:0] io_sec_data_hi_m, + output [31:0] io_sec_data_lo_m, + output [31:0] io_sec_data_hi_r_ff, + output [31:0] io_sec_data_lo_r_ff, + output [6:0] io_dma_dccm_wdata_ecc_hi, + output [6:0] io_dma_dccm_wdata_ecc_lo, + output [6:0] io_stbuf_ecc_any, + output [6:0] io_sec_data_ecc_hi_r_ff, + output [6:0] io_sec_data_ecc_lo_r_ff, + output io_single_ecc_error_hi_r, + output io_single_ecc_error_lo_r, + output io_lsu_single_ecc_error_r, + output io_lsu_double_ecc_error_r, + output io_lsu_single_ecc_error_m, + output io_lsu_double_ecc_error_m +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire _T_96 = ^io_dccm_rdata_hi_m; // @[lib.scala 193:30] + wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[lib.scala 193:44] + wire _T_98 = _T_96 ^ _T_97; // @[lib.scala 193:35] + wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[lib.scala 193:76] + wire _T_107 = ^_T_106; // @[lib.scala 193:83] + wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[lib.scala 193:71] + wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[lib.scala 193:103] + wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[lib.scala 193:103] + wire _T_124 = ^_T_123; // @[lib.scala 193:110] + wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[lib.scala 193:98] + wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[lib.scala 193:130] + wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[lib.scala 193:130] + wire _T_141 = ^_T_140; // @[lib.scala 193:137] + wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[lib.scala 193:125] + wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[lib.scala 193:157] + wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[lib.scala 193:157] + wire _T_161 = ^_T_160; // @[lib.scala 193:164] + wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[lib.scala 193:152] + wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:184] + wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[lib.scala 193:184] + wire _T_181 = ^_T_180; // @[lib.scala 193:191] + wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[lib.scala 193:179] + wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:211] + wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[lib.scala 193:211] + wire _T_201 = ^_T_200; // @[lib.scala 193:218] + wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[lib.scala 193:206] + wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58] + wire _T_209 = _T_208 != 7'h0; // @[lib.scala 194:44] + wire _T_1130 = ~io_dec_tlu_core_ecc_disable; // @[lsu_ecc.scala 106:48] + wire _T_1137 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[lsu_ecc.scala 124:65] + wire _T_1138 = io_lsu_pkt_m_valid & _T_1137; // @[lsu_ecc.scala 124:39] + wire _T_1139 = _T_1138 & io_addr_in_dccm_m; // @[lsu_ecc.scala 124:92] + wire is_ldst_m = _T_1139 & io_lsu_dccm_rden_m; // @[lsu_ecc.scala 124:112] + wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[lsu_ecc.scala 123:39] + wire _T_1143 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[lsu_ecc.scala 126:48] + wire _T_1144 = is_ldst_m & _T_1143; // @[lsu_ecc.scala 126:33] + wire is_ldst_hi_m = _T_1144 & _T_1130; // @[lsu_ecc.scala 126:73] + wire _T_210 = is_ldst_hi_m & _T_209; // @[lib.scala 194:32] + wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[lib.scala 194:53] + wire _T_215 = ~_T_208[6]; // @[lib.scala 195:55] + wire double_ecc_error_hi_any = _T_210 & _T_215; // @[lib.scala 195:53] + wire _T_218 = _T_208[5:0] == 6'h1; // @[lib.scala 199:41] + wire _T_220 = _T_208[5:0] == 6'h2; // @[lib.scala 199:41] + wire _T_222 = _T_208[5:0] == 6'h3; // @[lib.scala 199:41] + wire _T_224 = _T_208[5:0] == 6'h4; // @[lib.scala 199:41] + wire _T_226 = _T_208[5:0] == 6'h5; // @[lib.scala 199:41] + wire _T_228 = _T_208[5:0] == 6'h6; // @[lib.scala 199:41] + wire _T_230 = _T_208[5:0] == 6'h7; // @[lib.scala 199:41] + wire _T_232 = _T_208[5:0] == 6'h8; // @[lib.scala 199:41] + wire _T_234 = _T_208[5:0] == 6'h9; // @[lib.scala 199:41] + wire _T_236 = _T_208[5:0] == 6'ha; // @[lib.scala 199:41] + wire _T_238 = _T_208[5:0] == 6'hb; // @[lib.scala 199:41] + wire _T_240 = _T_208[5:0] == 6'hc; // @[lib.scala 199:41] + wire _T_242 = _T_208[5:0] == 6'hd; // @[lib.scala 199:41] + wire _T_244 = _T_208[5:0] == 6'he; // @[lib.scala 199:41] + wire _T_246 = _T_208[5:0] == 6'hf; // @[lib.scala 199:41] + wire _T_248 = _T_208[5:0] == 6'h10; // @[lib.scala 199:41] + wire _T_250 = _T_208[5:0] == 6'h11; // @[lib.scala 199:41] + wire _T_252 = _T_208[5:0] == 6'h12; // @[lib.scala 199:41] + wire _T_254 = _T_208[5:0] == 6'h13; // @[lib.scala 199:41] + wire _T_256 = _T_208[5:0] == 6'h14; // @[lib.scala 199:41] + wire _T_258 = _T_208[5:0] == 6'h15; // @[lib.scala 199:41] + wire _T_260 = _T_208[5:0] == 6'h16; // @[lib.scala 199:41] + wire _T_262 = _T_208[5:0] == 6'h17; // @[lib.scala 199:41] + wire _T_264 = _T_208[5:0] == 6'h18; // @[lib.scala 199:41] + wire _T_266 = _T_208[5:0] == 6'h19; // @[lib.scala 199:41] + wire _T_268 = _T_208[5:0] == 6'h1a; // @[lib.scala 199:41] + wire _T_270 = _T_208[5:0] == 6'h1b; // @[lib.scala 199:41] + wire _T_272 = _T_208[5:0] == 6'h1c; // @[lib.scala 199:41] + wire _T_274 = _T_208[5:0] == 6'h1d; // @[lib.scala 199:41] + wire _T_276 = _T_208[5:0] == 6'h1e; // @[lib.scala 199:41] + wire _T_278 = _T_208[5:0] == 6'h1f; // @[lib.scala 199:41] + wire _T_280 = _T_208[5:0] == 6'h20; // @[lib.scala 199:41] + wire _T_282 = _T_208[5:0] == 6'h21; // @[lib.scala 199:41] + wire _T_284 = _T_208[5:0] == 6'h22; // @[lib.scala 199:41] + wire _T_286 = _T_208[5:0] == 6'h23; // @[lib.scala 199:41] + wire _T_288 = _T_208[5:0] == 6'h24; // @[lib.scala 199:41] + wire _T_290 = _T_208[5:0] == 6'h25; // @[lib.scala 199:41] + wire _T_292 = _T_208[5:0] == 6'h26; // @[lib.scala 199:41] + wire _T_294 = _T_208[5:0] == 6'h27; // @[lib.scala 199:41] + wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58] + wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[lib.scala 202:69] + wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[lib.scala 202:69] + wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[lib.scala 202:69] + wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[lib.scala 202:69] + wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[lib.scala 202:69] + wire [38:0] _T_355 = _T_354 ^ _T_315; // @[lib.scala 202:76] + wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[lib.scala 202:31] + wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58] + wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58] + wire _T_474 = ^io_dccm_rdata_lo_m; // @[lib.scala 193:30] + wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[lib.scala 193:44] + wire _T_476 = _T_474 ^ _T_475; // @[lib.scala 193:35] + wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[lib.scala 193:76] + wire _T_485 = ^_T_484; // @[lib.scala 193:83] + wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[lib.scala 193:71] + wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[lib.scala 193:103] + wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[lib.scala 193:103] + wire _T_502 = ^_T_501; // @[lib.scala 193:110] + wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[lib.scala 193:98] + wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[lib.scala 193:130] + wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[lib.scala 193:130] + wire _T_519 = ^_T_518; // @[lib.scala 193:137] + wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[lib.scala 193:125] + wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[lib.scala 193:157] + wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[lib.scala 193:157] + wire _T_539 = ^_T_538; // @[lib.scala 193:164] + wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[lib.scala 193:152] + wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:184] + wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[lib.scala 193:184] + wire _T_559 = ^_T_558; // @[lib.scala 193:191] + wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[lib.scala 193:179] + wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:211] + wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[lib.scala 193:211] + wire _T_579 = ^_T_578; // @[lib.scala 193:218] + wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[lib.scala 193:206] + wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58] + wire _T_587 = _T_586 != 7'h0; // @[lib.scala 194:44] + wire is_ldst_lo_m = is_ldst_m & _T_1130; // @[lsu_ecc.scala 125:33] + wire _T_588 = is_ldst_lo_m & _T_587; // @[lib.scala 194:32] + wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[lib.scala 194:53] + wire _T_593 = ~_T_586[6]; // @[lib.scala 195:55] + wire double_ecc_error_lo_any = _T_588 & _T_593; // @[lib.scala 195:53] + wire _T_596 = _T_586[5:0] == 6'h1; // @[lib.scala 199:41] + wire _T_598 = _T_586[5:0] == 6'h2; // @[lib.scala 199:41] + wire _T_600 = _T_586[5:0] == 6'h3; // @[lib.scala 199:41] + wire _T_602 = _T_586[5:0] == 6'h4; // @[lib.scala 199:41] + wire _T_604 = _T_586[5:0] == 6'h5; // @[lib.scala 199:41] + wire _T_606 = _T_586[5:0] == 6'h6; // @[lib.scala 199:41] + wire _T_608 = _T_586[5:0] == 6'h7; // @[lib.scala 199:41] + wire _T_610 = _T_586[5:0] == 6'h8; // @[lib.scala 199:41] + wire _T_612 = _T_586[5:0] == 6'h9; // @[lib.scala 199:41] + wire _T_614 = _T_586[5:0] == 6'ha; // @[lib.scala 199:41] + wire _T_616 = _T_586[5:0] == 6'hb; // @[lib.scala 199:41] + wire _T_618 = _T_586[5:0] == 6'hc; // @[lib.scala 199:41] + wire _T_620 = _T_586[5:0] == 6'hd; // @[lib.scala 199:41] + wire _T_622 = _T_586[5:0] == 6'he; // @[lib.scala 199:41] + wire _T_624 = _T_586[5:0] == 6'hf; // @[lib.scala 199:41] + wire _T_626 = _T_586[5:0] == 6'h10; // @[lib.scala 199:41] + wire _T_628 = _T_586[5:0] == 6'h11; // @[lib.scala 199:41] + wire _T_630 = _T_586[5:0] == 6'h12; // @[lib.scala 199:41] + wire _T_632 = _T_586[5:0] == 6'h13; // @[lib.scala 199:41] + wire _T_634 = _T_586[5:0] == 6'h14; // @[lib.scala 199:41] + wire _T_636 = _T_586[5:0] == 6'h15; // @[lib.scala 199:41] + wire _T_638 = _T_586[5:0] == 6'h16; // @[lib.scala 199:41] + wire _T_640 = _T_586[5:0] == 6'h17; // @[lib.scala 199:41] + wire _T_642 = _T_586[5:0] == 6'h18; // @[lib.scala 199:41] + wire _T_644 = _T_586[5:0] == 6'h19; // @[lib.scala 199:41] + wire _T_646 = _T_586[5:0] == 6'h1a; // @[lib.scala 199:41] + wire _T_648 = _T_586[5:0] == 6'h1b; // @[lib.scala 199:41] + wire _T_650 = _T_586[5:0] == 6'h1c; // @[lib.scala 199:41] + wire _T_652 = _T_586[5:0] == 6'h1d; // @[lib.scala 199:41] + wire _T_654 = _T_586[5:0] == 6'h1e; // @[lib.scala 199:41] + wire _T_656 = _T_586[5:0] == 6'h1f; // @[lib.scala 199:41] + wire _T_658 = _T_586[5:0] == 6'h20; // @[lib.scala 199:41] + wire _T_660 = _T_586[5:0] == 6'h21; // @[lib.scala 199:41] + wire _T_662 = _T_586[5:0] == 6'h22; // @[lib.scala 199:41] + wire _T_664 = _T_586[5:0] == 6'h23; // @[lib.scala 199:41] + wire _T_666 = _T_586[5:0] == 6'h24; // @[lib.scala 199:41] + wire _T_668 = _T_586[5:0] == 6'h25; // @[lib.scala 199:41] + wire _T_670 = _T_586[5:0] == 6'h26; // @[lib.scala 199:41] + wire _T_672 = _T_586[5:0] == 6'h27; // @[lib.scala 199:41] + wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58] + wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[lib.scala 202:69] + wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[lib.scala 202:69] + wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[lib.scala 202:69] + wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[lib.scala 202:69] + wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[lib.scala 202:69] + wire [38:0] _T_733 = _T_732 ^ _T_693; // @[lib.scala 202:76] + wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[lib.scala 202:31] + wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58] + wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_1159 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[lsu_ecc.scala 148:87] + wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1159; // @[lsu_ecc.scala 148:27] + wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[lib.scala 119:74] + wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[lib.scala 119:74] + wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[lib.scala 119:74] + wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[lib.scala 119:74] + wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74] + wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74] + wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74] + wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74] + wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74] + wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74] + wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74] + wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74] + wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74] + wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74] + wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74] + wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74] + wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74] + wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74] + wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74] + wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74] + wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58] + wire _T_935 = ^dccm_wdata_lo_any; // @[lib.scala 127:13] + wire _T_936 = ^_T_934; // @[lib.scala 127:23] + wire _T_937 = _T_935 ^ _T_936; // @[lib.scala 127:18] + wire [31:0] _T_1163 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : 32'h0; // @[lsu_ecc.scala 149:87] + wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1163; // @[lsu_ecc.scala 149:27] + wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[lib.scala 119:74] + wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[lib.scala 119:74] + wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[lib.scala 119:74] + wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[lib.scala 119:74] + wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74] + wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74] + wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74] + wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74] + wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74] + wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74] + wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74] + wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74] + wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74] + wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74] + wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74] + wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74] + wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74] + wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74] + wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74] + wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74] + wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58] + wire _T_1117 = ^dccm_wdata_hi_any; // @[lib.scala 127:13] + wire _T_1118 = ^_T_1116; // @[lib.scala 127:23] + wire _T_1119 = _T_1117 ^ _T_1118; // @[lib.scala 127:18] + reg _T_1149; // @[lsu_ecc.scala 140:72] + reg _T_1150; // @[lsu_ecc.scala 141:72] + reg _T_1151; // @[lsu_ecc.scala 142:72] + reg _T_1152; // @[lsu_ecc.scala 143:72] + wire _T_1153 = io_lsu_single_ecc_error_m | io_clk_override; // @[lsu_ecc.scala 144:87] + reg [31:0] _T_1154; // @[Reg.scala 27:20] + reg [31:0] _T_1156; // @[Reg.scala 27:20] + wire _T_1165 = io_ld_single_ecc_error_r | io_clk_override; // @[lsu_ecc.scala 156:75] + reg [31:0] _T_1166; // @[Reg.scala 27:20] + reg [31:0] _T_1168; // @[Reg.scala 27:20] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + assign io_sec_data_hi_r = _T_1154; // @[lsu_ecc.scala 113:22 lsu_ecc.scala 144:34] + assign io_sec_data_lo_r = _T_1156; // @[lsu_ecc.scala 116:25 lsu_ecc.scala 145:34] + assign io_sec_data_hi_m = {_T_364,_T_362}; // @[lsu_ecc.scala 89:32 lsu_ecc.scala 133:27] + assign io_sec_data_lo_m = {_T_742,_T_740}; // @[lsu_ecc.scala 90:32 lsu_ecc.scala 135:27] + assign io_sec_data_hi_r_ff = _T_1166; // @[lsu_ecc.scala 156:23] + assign io_sec_data_lo_r_ff = _T_1168; // @[lsu_ecc.scala 157:23] + assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[lsu_ecc.scala 153:28] + assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[lsu_ecc.scala 154:28] + assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[lsu_ecc.scala 152:28] + assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[lsu_ecc.scala 150:28] + assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[lsu_ecc.scala 151:28] + assign io_single_ecc_error_hi_r = _T_1152; // @[lsu_ecc.scala 114:31 lsu_ecc.scala 143:62] + assign io_single_ecc_error_lo_r = _T_1151; // @[lsu_ecc.scala 117:31 lsu_ecc.scala 142:62] + assign io_lsu_single_ecc_error_r = _T_1149; // @[lsu_ecc.scala 119:31 lsu_ecc.scala 140:62] + assign io_lsu_double_ecc_error_r = _T_1150; // @[lsu_ecc.scala 120:31 lsu_ecc.scala 141:62] + assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[lsu_ecc.scala 91:30 lsu_ecc.scala 137:33] + assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 92:30 lsu_ecc.scala 138:33] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_1149 = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_1150 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_1151 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_1152 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_1154 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + _T_1156 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + _T_1166 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + _T_1168 = _RAND_7[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_1149 = 1'h0; + end + if (reset) begin + _T_1150 = 1'h0; + end + if (reset) begin + _T_1151 = 1'h0; + end + if (reset) begin + _T_1152 = 1'h0; + end + if (reset) begin + _T_1154 = 32'h0; + end + if (reset) begin + _T_1156 = 32'h0; + end + if (reset) begin + _T_1166 = 32'h0; + end + if (reset) begin + _T_1168 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1149 <= 1'h0; + end else begin + _T_1149 <= io_lsu_single_ecc_error_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1150 <= 1'h0; + end else begin + _T_1150 <= io_lsu_double_ecc_error_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1151 <= 1'h0; + end else begin + _T_1151 <= _T_588 & _T_586[6]; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1152 <= 1'h0; + end else begin + _T_1152 <= _T_210 & _T_208[6]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1154 <= 32'h0; + end else if (_T_1153) begin + _T_1154 <= io_sec_data_hi_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1156 <= 32'h0; + end else if (_T_1153) begin + _T_1156 <= io_sec_data_lo_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1166 <= 32'h0; + end else if (_T_1165) begin + _T_1166 <= io_sec_data_hi_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1168 <= 32'h0; + end else if (_T_1165) begin + _T_1168 <= io_sec_data_lo_r; + end + end +endmodule +module lsu_trigger( + input io_trigger_pkt_any_0_select, + input io_trigger_pkt_any_0_match_pkt, + input io_trigger_pkt_any_0_store, + input io_trigger_pkt_any_0_load, + input io_trigger_pkt_any_0_m, + input [31:0] io_trigger_pkt_any_0_tdata2, + input io_trigger_pkt_any_1_select, + input io_trigger_pkt_any_1_match_pkt, + input io_trigger_pkt_any_1_store, + input io_trigger_pkt_any_1_load, + input io_trigger_pkt_any_1_m, + input [31:0] io_trigger_pkt_any_1_tdata2, + input io_trigger_pkt_any_2_select, + input io_trigger_pkt_any_2_match_pkt, + input io_trigger_pkt_any_2_store, + input io_trigger_pkt_any_2_load, + input io_trigger_pkt_any_2_m, + input [31:0] io_trigger_pkt_any_2_tdata2, + input io_trigger_pkt_any_3_select, + input io_trigger_pkt_any_3_match_pkt, + input io_trigger_pkt_any_3_store, + input io_trigger_pkt_any_3_load, + input io_trigger_pkt_any_3_m, + input [31:0] io_trigger_pkt_any_3_tdata2, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input [31:0] io_lsu_addr_m, + input [31:0] io_store_data_m, + output [3:0] io_lsu_trigger_match_m +); + wire _T = io_trigger_pkt_any_0_m | io_trigger_pkt_any_1_m; // @[lsu_trigger.scala 16:73] + wire _T_1 = _T | io_trigger_pkt_any_2_m; // @[lsu_trigger.scala 16:73] + wire trigger_enable = _T_1 | io_trigger_pkt_any_3_m; // @[lsu_trigger.scala 16:73] + wire [15:0] _T_4 = io_lsu_pkt_m_bits_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_6 = _T_4 & io_store_data_m[31:16]; // @[lsu_trigger.scala 17:66] + wire _T_7 = io_lsu_pkt_m_bits_half | io_lsu_pkt_m_bits_word; // @[lsu_trigger.scala 17:124] + wire [7:0] _T_9 = _T_7 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_11 = _T_9 & io_store_data_m[15:8]; // @[lsu_trigger.scala 17:151] + wire [31:0] store_data_trigger_m = {_T_6,_T_11,io_store_data_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_15 = trigger_enable ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] ldst_addr_trigger_m = io_lsu_addr_m & _T_15; // @[lsu_trigger.scala 18:43] + wire _T_17 = ~io_trigger_pkt_any_0_select; // @[lsu_trigger.scala 19:53] + wire _T_18 = io_trigger_pkt_any_0_select & io_trigger_pkt_any_0_store; // @[lsu_trigger.scala 19:143] + wire [31:0] _T_20 = _T_17 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_21 = _T_18 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_0 = _T_20 | _T_21; // @[Mux.scala 27:72] + wire _T_24 = ~io_trigger_pkt_any_1_select; // @[lsu_trigger.scala 19:53] + wire _T_25 = io_trigger_pkt_any_1_select & io_trigger_pkt_any_1_store; // @[lsu_trigger.scala 19:143] + wire [31:0] _T_27 = _T_24 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_28 = _T_25 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_1 = _T_27 | _T_28; // @[Mux.scala 27:72] + wire _T_31 = ~io_trigger_pkt_any_2_select; // @[lsu_trigger.scala 19:53] + wire _T_32 = io_trigger_pkt_any_2_select & io_trigger_pkt_any_2_store; // @[lsu_trigger.scala 19:143] + wire [31:0] _T_34 = _T_31 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_35 = _T_32 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_2 = _T_34 | _T_35; // @[Mux.scala 27:72] + wire _T_38 = ~io_trigger_pkt_any_3_select; // @[lsu_trigger.scala 19:53] + wire _T_39 = io_trigger_pkt_any_3_select & io_trigger_pkt_any_3_store; // @[lsu_trigger.scala 19:143] + wire [31:0] _T_41 = _T_38 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_42 = _T_39 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_3 = _T_41 | _T_42; // @[Mux.scala 27:72] + wire _T_44 = ~io_lsu_pkt_m_bits_dma; // @[lsu_trigger.scala 20:70] + wire _T_45 = io_lsu_pkt_m_valid & _T_44; // @[lsu_trigger.scala 20:68] + wire _T_46 = _T_45 & trigger_enable; // @[lsu_trigger.scala 20:93] + wire _T_47 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142] + wire _T_48 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33] + wire _T_50 = _T_48 & _T_17; // @[lsu_trigger.scala 21:58] + wire _T_51 = _T_47 | _T_50; // @[lsu_trigger.scala 20:168] + wire _T_52 = _T_46 & _T_51; // @[lsu_trigger.scala 20:110] + wire _T_55 = &io_trigger_pkt_any_0_tdata2; // @[lib.scala 101:45] + wire _T_56 = ~_T_55; // @[lib.scala 101:39] + wire _T_57 = io_trigger_pkt_any_0_match_pkt & _T_56; // @[lib.scala 101:37] + wire _T_60 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[lib.scala 102:52] + wire _T_61 = _T_57 | _T_60; // @[lib.scala 102:41] + wire _T_63 = &io_trigger_pkt_any_0_tdata2[0]; // @[lib.scala 104:36] + wire _T_64 = _T_63 & _T_57; // @[lib.scala 104:41] + wire _T_67 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[lib.scala 104:78] + wire _T_68 = _T_64 | _T_67; // @[lib.scala 104:23] + wire _T_70 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_71 = _T_70 & _T_57; // @[lib.scala 104:41] + wire _T_74 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[lib.scala 104:78] + wire _T_75 = _T_71 | _T_74; // @[lib.scala 104:23] + wire _T_77 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_78 = _T_77 & _T_57; // @[lib.scala 104:41] + wire _T_81 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[lib.scala 104:78] + wire _T_82 = _T_78 | _T_81; // @[lib.scala 104:23] + wire _T_84 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_85 = _T_84 & _T_57; // @[lib.scala 104:41] + wire _T_88 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[lib.scala 104:78] + wire _T_89 = _T_85 | _T_88; // @[lib.scala 104:23] + wire _T_91 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_92 = _T_91 & _T_57; // @[lib.scala 104:41] + wire _T_95 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[lib.scala 104:78] + wire _T_96 = _T_92 | _T_95; // @[lib.scala 104:23] + wire _T_98 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_99 = _T_98 & _T_57; // @[lib.scala 104:41] + wire _T_102 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[lib.scala 104:78] + wire _T_103 = _T_99 | _T_102; // @[lib.scala 104:23] + wire _T_105 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_106 = _T_105 & _T_57; // @[lib.scala 104:41] + wire _T_109 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[lib.scala 104:78] + wire _T_110 = _T_106 | _T_109; // @[lib.scala 104:23] + wire _T_112 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_113 = _T_112 & _T_57; // @[lib.scala 104:41] + wire _T_116 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[lib.scala 104:78] + wire _T_117 = _T_113 | _T_116; // @[lib.scala 104:23] + wire _T_119 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_120 = _T_119 & _T_57; // @[lib.scala 104:41] + wire _T_123 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[lib.scala 104:78] + wire _T_124 = _T_120 | _T_123; // @[lib.scala 104:23] + wire _T_126 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_127 = _T_126 & _T_57; // @[lib.scala 104:41] + wire _T_130 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[lib.scala 104:78] + wire _T_131 = _T_127 | _T_130; // @[lib.scala 104:23] + wire _T_133 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_134 = _T_133 & _T_57; // @[lib.scala 104:41] + wire _T_137 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[lib.scala 104:78] + wire _T_138 = _T_134 | _T_137; // @[lib.scala 104:23] + wire _T_140 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_141 = _T_140 & _T_57; // @[lib.scala 104:41] + wire _T_144 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[lib.scala 104:78] + wire _T_145 = _T_141 | _T_144; // @[lib.scala 104:23] + wire _T_147 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_148 = _T_147 & _T_57; // @[lib.scala 104:41] + wire _T_151 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[lib.scala 104:78] + wire _T_152 = _T_148 | _T_151; // @[lib.scala 104:23] + wire _T_154 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_155 = _T_154 & _T_57; // @[lib.scala 104:41] + wire _T_158 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[lib.scala 104:78] + wire _T_159 = _T_155 | _T_158; // @[lib.scala 104:23] + wire _T_161 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_162 = _T_161 & _T_57; // @[lib.scala 104:41] + wire _T_165 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[lib.scala 104:78] + wire _T_166 = _T_162 | _T_165; // @[lib.scala 104:23] + wire _T_168 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_169 = _T_168 & _T_57; // @[lib.scala 104:41] + wire _T_172 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[lib.scala 104:78] + wire _T_173 = _T_169 | _T_172; // @[lib.scala 104:23] + wire _T_175 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_176 = _T_175 & _T_57; // @[lib.scala 104:41] + wire _T_179 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[lib.scala 104:78] + wire _T_180 = _T_176 | _T_179; // @[lib.scala 104:23] + wire _T_182 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_183 = _T_182 & _T_57; // @[lib.scala 104:41] + wire _T_186 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[lib.scala 104:78] + wire _T_187 = _T_183 | _T_186; // @[lib.scala 104:23] + wire _T_189 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_190 = _T_189 & _T_57; // @[lib.scala 104:41] + wire _T_193 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[lib.scala 104:78] + wire _T_194 = _T_190 | _T_193; // @[lib.scala 104:23] + wire _T_196 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_197 = _T_196 & _T_57; // @[lib.scala 104:41] + wire _T_200 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[lib.scala 104:78] + wire _T_201 = _T_197 | _T_200; // @[lib.scala 104:23] + wire _T_203 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_204 = _T_203 & _T_57; // @[lib.scala 104:41] + wire _T_207 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[lib.scala 104:78] + wire _T_208 = _T_204 | _T_207; // @[lib.scala 104:23] + wire _T_210 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_211 = _T_210 & _T_57; // @[lib.scala 104:41] + wire _T_214 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[lib.scala 104:78] + wire _T_215 = _T_211 | _T_214; // @[lib.scala 104:23] + wire _T_217 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_218 = _T_217 & _T_57; // @[lib.scala 104:41] + wire _T_221 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[lib.scala 104:78] + wire _T_222 = _T_218 | _T_221; // @[lib.scala 104:23] + wire _T_224 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_225 = _T_224 & _T_57; // @[lib.scala 104:41] + wire _T_228 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[lib.scala 104:78] + wire _T_229 = _T_225 | _T_228; // @[lib.scala 104:23] + wire _T_231 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_232 = _T_231 & _T_57; // @[lib.scala 104:41] + wire _T_235 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[lib.scala 104:78] + wire _T_236 = _T_232 | _T_235; // @[lib.scala 104:23] + wire _T_238 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_239 = _T_238 & _T_57; // @[lib.scala 104:41] + wire _T_242 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[lib.scala 104:78] + wire _T_243 = _T_239 | _T_242; // @[lib.scala 104:23] + wire _T_245 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_246 = _T_245 & _T_57; // @[lib.scala 104:41] + wire _T_249 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[lib.scala 104:78] + wire _T_250 = _T_246 | _T_249; // @[lib.scala 104:23] + wire _T_252 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_253 = _T_252 & _T_57; // @[lib.scala 104:41] + wire _T_256 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[lib.scala 104:78] + wire _T_257 = _T_253 | _T_256; // @[lib.scala 104:23] + wire _T_259 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_260 = _T_259 & _T_57; // @[lib.scala 104:41] + wire _T_263 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[lib.scala 104:78] + wire _T_264 = _T_260 | _T_263; // @[lib.scala 104:23] + wire _T_266 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_267 = _T_266 & _T_57; // @[lib.scala 104:41] + wire _T_270 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[lib.scala 104:78] + wire _T_271 = _T_267 | _T_270; // @[lib.scala 104:23] + wire _T_273 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_274 = _T_273 & _T_57; // @[lib.scala 104:41] + wire _T_277 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[lib.scala 104:78] + wire _T_278 = _T_274 | _T_277; // @[lib.scala 104:23] + wire [7:0] _T_285 = {_T_110,_T_103,_T_96,_T_89,_T_82,_T_75,_T_68,_T_61}; // @[lib.scala 105:14] + wire [15:0] _T_293 = {_T_166,_T_159,_T_152,_T_145,_T_138,_T_131,_T_124,_T_117,_T_285}; // @[lib.scala 105:14] + wire [7:0] _T_300 = {_T_222,_T_215,_T_208,_T_201,_T_194,_T_187,_T_180,_T_173}; // @[lib.scala 105:14] + wire [31:0] _T_309 = {_T_278,_T_271,_T_264,_T_257,_T_250,_T_243,_T_236,_T_229,_T_300,_T_293}; // @[lib.scala 105:14] + wire _T_310 = &_T_309; // @[lib.scala 105:25] + wire _T_311 = _T_52 & _T_310; // @[lsu_trigger.scala 21:92] + wire _T_315 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142] + wire _T_316 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33] + wire _T_318 = _T_316 & _T_24; // @[lsu_trigger.scala 21:58] + wire _T_319 = _T_315 | _T_318; // @[lsu_trigger.scala 20:168] + wire _T_320 = _T_46 & _T_319; // @[lsu_trigger.scala 20:110] + wire _T_323 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 101:45] + wire _T_324 = ~_T_323; // @[lib.scala 101:39] + wire _T_325 = io_trigger_pkt_any_1_match_pkt & _T_324; // @[lib.scala 101:37] + wire _T_328 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 102:52] + wire _T_329 = _T_325 | _T_328; // @[lib.scala 102:41] + wire _T_331 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 104:36] + wire _T_332 = _T_331 & _T_325; // @[lib.scala 104:41] + wire _T_335 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 104:78] + wire _T_336 = _T_332 | _T_335; // @[lib.scala 104:23] + wire _T_338 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_339 = _T_338 & _T_325; // @[lib.scala 104:41] + wire _T_342 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 104:78] + wire _T_343 = _T_339 | _T_342; // @[lib.scala 104:23] + wire _T_345 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_346 = _T_345 & _T_325; // @[lib.scala 104:41] + wire _T_349 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 104:78] + wire _T_350 = _T_346 | _T_349; // @[lib.scala 104:23] + wire _T_352 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_353 = _T_352 & _T_325; // @[lib.scala 104:41] + wire _T_356 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 104:78] + wire _T_357 = _T_353 | _T_356; // @[lib.scala 104:23] + wire _T_359 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_360 = _T_359 & _T_325; // @[lib.scala 104:41] + wire _T_363 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 104:78] + wire _T_364 = _T_360 | _T_363; // @[lib.scala 104:23] + wire _T_366 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_367 = _T_366 & _T_325; // @[lib.scala 104:41] + wire _T_370 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 104:78] + wire _T_371 = _T_367 | _T_370; // @[lib.scala 104:23] + wire _T_373 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_374 = _T_373 & _T_325; // @[lib.scala 104:41] + wire _T_377 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 104:78] + wire _T_378 = _T_374 | _T_377; // @[lib.scala 104:23] + wire _T_380 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_381 = _T_380 & _T_325; // @[lib.scala 104:41] + wire _T_384 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 104:78] + wire _T_385 = _T_381 | _T_384; // @[lib.scala 104:23] + wire _T_387 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_388 = _T_387 & _T_325; // @[lib.scala 104:41] + wire _T_391 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 104:78] + wire _T_392 = _T_388 | _T_391; // @[lib.scala 104:23] + wire _T_394 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_395 = _T_394 & _T_325; // @[lib.scala 104:41] + wire _T_398 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 104:78] + wire _T_399 = _T_395 | _T_398; // @[lib.scala 104:23] + wire _T_401 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_402 = _T_401 & _T_325; // @[lib.scala 104:41] + wire _T_405 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 104:78] + wire _T_406 = _T_402 | _T_405; // @[lib.scala 104:23] + wire _T_408 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_409 = _T_408 & _T_325; // @[lib.scala 104:41] + wire _T_412 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 104:78] + wire _T_413 = _T_409 | _T_412; // @[lib.scala 104:23] + wire _T_415 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_416 = _T_415 & _T_325; // @[lib.scala 104:41] + wire _T_419 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 104:78] + wire _T_420 = _T_416 | _T_419; // @[lib.scala 104:23] + wire _T_422 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_423 = _T_422 & _T_325; // @[lib.scala 104:41] + wire _T_426 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 104:78] + wire _T_427 = _T_423 | _T_426; // @[lib.scala 104:23] + wire _T_429 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_430 = _T_429 & _T_325; // @[lib.scala 104:41] + wire _T_433 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 104:78] + wire _T_434 = _T_430 | _T_433; // @[lib.scala 104:23] + wire _T_436 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_437 = _T_436 & _T_325; // @[lib.scala 104:41] + wire _T_440 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 104:78] + wire _T_441 = _T_437 | _T_440; // @[lib.scala 104:23] + wire _T_443 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_444 = _T_443 & _T_325; // @[lib.scala 104:41] + wire _T_447 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 104:78] + wire _T_448 = _T_444 | _T_447; // @[lib.scala 104:23] + wire _T_450 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_451 = _T_450 & _T_325; // @[lib.scala 104:41] + wire _T_454 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 104:78] + wire _T_455 = _T_451 | _T_454; // @[lib.scala 104:23] + wire _T_457 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_458 = _T_457 & _T_325; // @[lib.scala 104:41] + wire _T_461 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 104:78] + wire _T_462 = _T_458 | _T_461; // @[lib.scala 104:23] + wire _T_464 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_465 = _T_464 & _T_325; // @[lib.scala 104:41] + wire _T_468 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 104:78] + wire _T_469 = _T_465 | _T_468; // @[lib.scala 104:23] + wire _T_471 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_472 = _T_471 & _T_325; // @[lib.scala 104:41] + wire _T_475 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 104:78] + wire _T_476 = _T_472 | _T_475; // @[lib.scala 104:23] + wire _T_478 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_479 = _T_478 & _T_325; // @[lib.scala 104:41] + wire _T_482 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 104:78] + wire _T_483 = _T_479 | _T_482; // @[lib.scala 104:23] + wire _T_485 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_486 = _T_485 & _T_325; // @[lib.scala 104:41] + wire _T_489 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 104:78] + wire _T_490 = _T_486 | _T_489; // @[lib.scala 104:23] + wire _T_492 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_493 = _T_492 & _T_325; // @[lib.scala 104:41] + wire _T_496 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 104:78] + wire _T_497 = _T_493 | _T_496; // @[lib.scala 104:23] + wire _T_499 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_500 = _T_499 & _T_325; // @[lib.scala 104:41] + wire _T_503 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 104:78] + wire _T_504 = _T_500 | _T_503; // @[lib.scala 104:23] + wire _T_506 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_507 = _T_506 & _T_325; // @[lib.scala 104:41] + wire _T_510 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 104:78] + wire _T_511 = _T_507 | _T_510; // @[lib.scala 104:23] + wire _T_513 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_514 = _T_513 & _T_325; // @[lib.scala 104:41] + wire _T_517 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 104:78] + wire _T_518 = _T_514 | _T_517; // @[lib.scala 104:23] + wire _T_520 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_521 = _T_520 & _T_325; // @[lib.scala 104:41] + wire _T_524 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 104:78] + wire _T_525 = _T_521 | _T_524; // @[lib.scala 104:23] + wire _T_527 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_528 = _T_527 & _T_325; // @[lib.scala 104:41] + wire _T_531 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 104:78] + wire _T_532 = _T_528 | _T_531; // @[lib.scala 104:23] + wire _T_534 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_535 = _T_534 & _T_325; // @[lib.scala 104:41] + wire _T_538 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 104:78] + wire _T_539 = _T_535 | _T_538; // @[lib.scala 104:23] + wire _T_541 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_542 = _T_541 & _T_325; // @[lib.scala 104:41] + wire _T_545 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 104:78] + wire _T_546 = _T_542 | _T_545; // @[lib.scala 104:23] + wire [7:0] _T_553 = {_T_378,_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329}; // @[lib.scala 105:14] + wire [15:0] _T_561 = {_T_434,_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_553}; // @[lib.scala 105:14] + wire [7:0] _T_568 = {_T_490,_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441}; // @[lib.scala 105:14] + wire [31:0] _T_577 = {_T_546,_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_568,_T_561}; // @[lib.scala 105:14] + wire _T_578 = &_T_577; // @[lib.scala 105:25] + wire _T_579 = _T_320 & _T_578; // @[lsu_trigger.scala 21:92] + wire _T_583 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142] + wire _T_584 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33] + wire _T_586 = _T_584 & _T_31; // @[lsu_trigger.scala 21:58] + wire _T_587 = _T_583 | _T_586; // @[lsu_trigger.scala 20:168] + wire _T_588 = _T_46 & _T_587; // @[lsu_trigger.scala 20:110] + wire _T_591 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 101:45] + wire _T_592 = ~_T_591; // @[lib.scala 101:39] + wire _T_593 = io_trigger_pkt_any_2_match_pkt & _T_592; // @[lib.scala 101:37] + wire _T_596 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 102:52] + wire _T_597 = _T_593 | _T_596; // @[lib.scala 102:41] + wire _T_599 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 104:36] + wire _T_600 = _T_599 & _T_593; // @[lib.scala 104:41] + wire _T_603 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 104:78] + wire _T_604 = _T_600 | _T_603; // @[lib.scala 104:23] + wire _T_606 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_607 = _T_606 & _T_593; // @[lib.scala 104:41] + wire _T_610 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 104:78] + wire _T_611 = _T_607 | _T_610; // @[lib.scala 104:23] + wire _T_613 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_614 = _T_613 & _T_593; // @[lib.scala 104:41] + wire _T_617 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 104:78] + wire _T_618 = _T_614 | _T_617; // @[lib.scala 104:23] + wire _T_620 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_621 = _T_620 & _T_593; // @[lib.scala 104:41] + wire _T_624 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 104:78] + wire _T_625 = _T_621 | _T_624; // @[lib.scala 104:23] + wire _T_627 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_628 = _T_627 & _T_593; // @[lib.scala 104:41] + wire _T_631 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 104:78] + wire _T_632 = _T_628 | _T_631; // @[lib.scala 104:23] + wire _T_634 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_635 = _T_634 & _T_593; // @[lib.scala 104:41] + wire _T_638 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 104:78] + wire _T_639 = _T_635 | _T_638; // @[lib.scala 104:23] + wire _T_641 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_642 = _T_641 & _T_593; // @[lib.scala 104:41] + wire _T_645 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 104:78] + wire _T_646 = _T_642 | _T_645; // @[lib.scala 104:23] + wire _T_648 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_649 = _T_648 & _T_593; // @[lib.scala 104:41] + wire _T_652 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 104:78] + wire _T_653 = _T_649 | _T_652; // @[lib.scala 104:23] + wire _T_655 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_656 = _T_655 & _T_593; // @[lib.scala 104:41] + wire _T_659 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 104:78] + wire _T_660 = _T_656 | _T_659; // @[lib.scala 104:23] + wire _T_662 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_663 = _T_662 & _T_593; // @[lib.scala 104:41] + wire _T_666 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 104:78] + wire _T_667 = _T_663 | _T_666; // @[lib.scala 104:23] + wire _T_669 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_670 = _T_669 & _T_593; // @[lib.scala 104:41] + wire _T_673 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 104:78] + wire _T_674 = _T_670 | _T_673; // @[lib.scala 104:23] + wire _T_676 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_677 = _T_676 & _T_593; // @[lib.scala 104:41] + wire _T_680 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 104:78] + wire _T_681 = _T_677 | _T_680; // @[lib.scala 104:23] + wire _T_683 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_684 = _T_683 & _T_593; // @[lib.scala 104:41] + wire _T_687 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 104:78] + wire _T_688 = _T_684 | _T_687; // @[lib.scala 104:23] + wire _T_690 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_691 = _T_690 & _T_593; // @[lib.scala 104:41] + wire _T_694 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 104:78] + wire _T_695 = _T_691 | _T_694; // @[lib.scala 104:23] + wire _T_697 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_698 = _T_697 & _T_593; // @[lib.scala 104:41] + wire _T_701 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 104:78] + wire _T_702 = _T_698 | _T_701; // @[lib.scala 104:23] + wire _T_704 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_705 = _T_704 & _T_593; // @[lib.scala 104:41] + wire _T_708 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 104:78] + wire _T_709 = _T_705 | _T_708; // @[lib.scala 104:23] + wire _T_711 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_712 = _T_711 & _T_593; // @[lib.scala 104:41] + wire _T_715 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 104:78] + wire _T_716 = _T_712 | _T_715; // @[lib.scala 104:23] + wire _T_718 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_719 = _T_718 & _T_593; // @[lib.scala 104:41] + wire _T_722 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 104:78] + wire _T_723 = _T_719 | _T_722; // @[lib.scala 104:23] + wire _T_725 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_726 = _T_725 & _T_593; // @[lib.scala 104:41] + wire _T_729 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 104:78] + wire _T_730 = _T_726 | _T_729; // @[lib.scala 104:23] + wire _T_732 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_733 = _T_732 & _T_593; // @[lib.scala 104:41] + wire _T_736 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 104:78] + wire _T_737 = _T_733 | _T_736; // @[lib.scala 104:23] + wire _T_739 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_740 = _T_739 & _T_593; // @[lib.scala 104:41] + wire _T_743 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 104:78] + wire _T_744 = _T_740 | _T_743; // @[lib.scala 104:23] + wire _T_746 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_747 = _T_746 & _T_593; // @[lib.scala 104:41] + wire _T_750 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 104:78] + wire _T_751 = _T_747 | _T_750; // @[lib.scala 104:23] + wire _T_753 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_754 = _T_753 & _T_593; // @[lib.scala 104:41] + wire _T_757 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 104:78] + wire _T_758 = _T_754 | _T_757; // @[lib.scala 104:23] + wire _T_760 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_761 = _T_760 & _T_593; // @[lib.scala 104:41] + wire _T_764 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 104:78] + wire _T_765 = _T_761 | _T_764; // @[lib.scala 104:23] + wire _T_767 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_768 = _T_767 & _T_593; // @[lib.scala 104:41] + wire _T_771 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 104:78] + wire _T_772 = _T_768 | _T_771; // @[lib.scala 104:23] + wire _T_774 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_775 = _T_774 & _T_593; // @[lib.scala 104:41] + wire _T_778 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 104:78] + wire _T_779 = _T_775 | _T_778; // @[lib.scala 104:23] + wire _T_781 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_782 = _T_781 & _T_593; // @[lib.scala 104:41] + wire _T_785 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 104:78] + wire _T_786 = _T_782 | _T_785; // @[lib.scala 104:23] + wire _T_788 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_789 = _T_788 & _T_593; // @[lib.scala 104:41] + wire _T_792 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 104:78] + wire _T_793 = _T_789 | _T_792; // @[lib.scala 104:23] + wire _T_795 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_796 = _T_795 & _T_593; // @[lib.scala 104:41] + wire _T_799 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 104:78] + wire _T_800 = _T_796 | _T_799; // @[lib.scala 104:23] + wire _T_802 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_803 = _T_802 & _T_593; // @[lib.scala 104:41] + wire _T_806 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 104:78] + wire _T_807 = _T_803 | _T_806; // @[lib.scala 104:23] + wire _T_809 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_810 = _T_809 & _T_593; // @[lib.scala 104:41] + wire _T_813 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 104:78] + wire _T_814 = _T_810 | _T_813; // @[lib.scala 104:23] + wire [7:0] _T_821 = {_T_646,_T_639,_T_632,_T_625,_T_618,_T_611,_T_604,_T_597}; // @[lib.scala 105:14] + wire [15:0] _T_829 = {_T_702,_T_695,_T_688,_T_681,_T_674,_T_667,_T_660,_T_653,_T_821}; // @[lib.scala 105:14] + wire [7:0] _T_836 = {_T_758,_T_751,_T_744,_T_737,_T_730,_T_723,_T_716,_T_709}; // @[lib.scala 105:14] + wire [31:0] _T_845 = {_T_814,_T_807,_T_800,_T_793,_T_786,_T_779,_T_772,_T_765,_T_836,_T_829}; // @[lib.scala 105:14] + wire _T_846 = &_T_845; // @[lib.scala 105:25] + wire _T_847 = _T_588 & _T_846; // @[lsu_trigger.scala 21:92] + wire _T_851 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142] + wire _T_852 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33] + wire _T_854 = _T_852 & _T_38; // @[lsu_trigger.scala 21:58] + wire _T_855 = _T_851 | _T_854; // @[lsu_trigger.scala 20:168] + wire _T_856 = _T_46 & _T_855; // @[lsu_trigger.scala 20:110] + wire _T_859 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 101:45] + wire _T_860 = ~_T_859; // @[lib.scala 101:39] + wire _T_861 = io_trigger_pkt_any_3_match_pkt & _T_860; // @[lib.scala 101:37] + wire _T_864 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 102:52] + wire _T_865 = _T_861 | _T_864; // @[lib.scala 102:41] + wire _T_867 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 104:36] + wire _T_868 = _T_867 & _T_861; // @[lib.scala 104:41] + wire _T_871 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 104:78] + wire _T_872 = _T_868 | _T_871; // @[lib.scala 104:23] + wire _T_874 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_875 = _T_874 & _T_861; // @[lib.scala 104:41] + wire _T_878 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 104:78] + wire _T_879 = _T_875 | _T_878; // @[lib.scala 104:23] + wire _T_881 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_882 = _T_881 & _T_861; // @[lib.scala 104:41] + wire _T_885 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 104:78] + wire _T_886 = _T_882 | _T_885; // @[lib.scala 104:23] + wire _T_888 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_889 = _T_888 & _T_861; // @[lib.scala 104:41] + wire _T_892 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 104:78] + wire _T_893 = _T_889 | _T_892; // @[lib.scala 104:23] + wire _T_895 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_896 = _T_895 & _T_861; // @[lib.scala 104:41] + wire _T_899 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 104:78] + wire _T_900 = _T_896 | _T_899; // @[lib.scala 104:23] + wire _T_902 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_903 = _T_902 & _T_861; // @[lib.scala 104:41] + wire _T_906 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 104:78] + wire _T_907 = _T_903 | _T_906; // @[lib.scala 104:23] + wire _T_909 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_910 = _T_909 & _T_861; // @[lib.scala 104:41] + wire _T_913 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 104:78] + wire _T_914 = _T_910 | _T_913; // @[lib.scala 104:23] + wire _T_916 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_917 = _T_916 & _T_861; // @[lib.scala 104:41] + wire _T_920 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 104:78] + wire _T_921 = _T_917 | _T_920; // @[lib.scala 104:23] + wire _T_923 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_924 = _T_923 & _T_861; // @[lib.scala 104:41] + wire _T_927 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 104:78] + wire _T_928 = _T_924 | _T_927; // @[lib.scala 104:23] + wire _T_930 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_931 = _T_930 & _T_861; // @[lib.scala 104:41] + wire _T_934 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 104:78] + wire _T_935 = _T_931 | _T_934; // @[lib.scala 104:23] + wire _T_937 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_938 = _T_937 & _T_861; // @[lib.scala 104:41] + wire _T_941 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 104:78] + wire _T_942 = _T_938 | _T_941; // @[lib.scala 104:23] + wire _T_944 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_945 = _T_944 & _T_861; // @[lib.scala 104:41] + wire _T_948 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 104:78] + wire _T_949 = _T_945 | _T_948; // @[lib.scala 104:23] + wire _T_951 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_952 = _T_951 & _T_861; // @[lib.scala 104:41] + wire _T_955 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 104:78] + wire _T_956 = _T_952 | _T_955; // @[lib.scala 104:23] + wire _T_958 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_959 = _T_958 & _T_861; // @[lib.scala 104:41] + wire _T_962 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 104:78] + wire _T_963 = _T_959 | _T_962; // @[lib.scala 104:23] + wire _T_965 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_966 = _T_965 & _T_861; // @[lib.scala 104:41] + wire _T_969 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 104:78] + wire _T_970 = _T_966 | _T_969; // @[lib.scala 104:23] + wire _T_972 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_973 = _T_972 & _T_861; // @[lib.scala 104:41] + wire _T_976 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 104:78] + wire _T_977 = _T_973 | _T_976; // @[lib.scala 104:23] + wire _T_979 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_980 = _T_979 & _T_861; // @[lib.scala 104:41] + wire _T_983 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 104:78] + wire _T_984 = _T_980 | _T_983; // @[lib.scala 104:23] + wire _T_986 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_987 = _T_986 & _T_861; // @[lib.scala 104:41] + wire _T_990 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 104:78] + wire _T_991 = _T_987 | _T_990; // @[lib.scala 104:23] + wire _T_993 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_994 = _T_993 & _T_861; // @[lib.scala 104:41] + wire _T_997 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 104:78] + wire _T_998 = _T_994 | _T_997; // @[lib.scala 104:23] + wire _T_1000 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_1001 = _T_1000 & _T_861; // @[lib.scala 104:41] + wire _T_1004 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 104:78] + wire _T_1005 = _T_1001 | _T_1004; // @[lib.scala 104:23] + wire _T_1007 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_1008 = _T_1007 & _T_861; // @[lib.scala 104:41] + wire _T_1011 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 104:78] + wire _T_1012 = _T_1008 | _T_1011; // @[lib.scala 104:23] + wire _T_1014 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_1015 = _T_1014 & _T_861; // @[lib.scala 104:41] + wire _T_1018 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 104:78] + wire _T_1019 = _T_1015 | _T_1018; // @[lib.scala 104:23] + wire _T_1021 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_1022 = _T_1021 & _T_861; // @[lib.scala 104:41] + wire _T_1025 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 104:78] + wire _T_1026 = _T_1022 | _T_1025; // @[lib.scala 104:23] + wire _T_1028 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_1029 = _T_1028 & _T_861; // @[lib.scala 104:41] + wire _T_1032 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 104:78] + wire _T_1033 = _T_1029 | _T_1032; // @[lib.scala 104:23] + wire _T_1035 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_1036 = _T_1035 & _T_861; // @[lib.scala 104:41] + wire _T_1039 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 104:78] + wire _T_1040 = _T_1036 | _T_1039; // @[lib.scala 104:23] + wire _T_1042 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_1043 = _T_1042 & _T_861; // @[lib.scala 104:41] + wire _T_1046 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 104:78] + wire _T_1047 = _T_1043 | _T_1046; // @[lib.scala 104:23] + wire _T_1049 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_1050 = _T_1049 & _T_861; // @[lib.scala 104:41] + wire _T_1053 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 104:78] + wire _T_1054 = _T_1050 | _T_1053; // @[lib.scala 104:23] + wire _T_1056 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_1057 = _T_1056 & _T_861; // @[lib.scala 104:41] + wire _T_1060 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 104:78] + wire _T_1061 = _T_1057 | _T_1060; // @[lib.scala 104:23] + wire _T_1063 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_1064 = _T_1063 & _T_861; // @[lib.scala 104:41] + wire _T_1067 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 104:78] + wire _T_1068 = _T_1064 | _T_1067; // @[lib.scala 104:23] + wire _T_1070 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_1071 = _T_1070 & _T_861; // @[lib.scala 104:41] + wire _T_1074 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 104:78] + wire _T_1075 = _T_1071 | _T_1074; // @[lib.scala 104:23] + wire _T_1077 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_1078 = _T_1077 & _T_861; // @[lib.scala 104:41] + wire _T_1081 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 104:78] + wire _T_1082 = _T_1078 | _T_1081; // @[lib.scala 104:23] + wire [7:0] _T_1089 = {_T_914,_T_907,_T_900,_T_893,_T_886,_T_879,_T_872,_T_865}; // @[lib.scala 105:14] + wire [15:0] _T_1097 = {_T_970,_T_963,_T_956,_T_949,_T_942,_T_935,_T_928,_T_921,_T_1089}; // @[lib.scala 105:14] + wire [7:0] _T_1104 = {_T_1026,_T_1019,_T_1012,_T_1005,_T_998,_T_991,_T_984,_T_977}; // @[lib.scala 105:14] + wire [31:0] _T_1113 = {_T_1082,_T_1075,_T_1068,_T_1061,_T_1054,_T_1047,_T_1040,_T_1033,_T_1104,_T_1097}; // @[lib.scala 105:14] + wire _T_1114 = &_T_1113; // @[lib.scala 105:25] + wire _T_1115 = _T_856 & _T_1114; // @[lsu_trigger.scala 21:92] + wire [2:0] _T_1117 = {_T_1115,_T_847,_T_579}; // @[Cat.scala 29:58] + assign io_lsu_trigger_match_m = {_T_1117,_T_311}; // @[lsu_trigger.scala 20:25] +endmodule +module lsu_clkdomain( + input clock, + input io_clk_override, + input io_lsu_busreq_r, + input io_lsu_bus_buffer_pend_any, + input io_lsu_bus_buffer_empty_any, + input io_lsu_bus_clk_en, + output io_lsu_bus_obuf_c1_clken, + output io_lsu_busm_clken, + output io_lsu_c1_m_clk, + output io_lsu_c1_r_clk, + output io_lsu_c2_m_clk, + output io_lsu_c2_r_clk, + output io_lsu_store_c1_m_clk, + output io_lsu_store_c1_r_clk, + output io_lsu_stbuf_c1_clk, + output io_lsu_bus_ibuf_c1_clk, + output io_lsu_bus_buf_c1_clk, + output io_lsu_free_c2_clk +); + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire _T_8 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[lsu_clkdomain.scala 74:62] + wire _T_9 = _T_8 | io_clk_override; // @[lsu_clkdomain.scala 74:80] + wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[lsu_clkdomain.scala 75:32] + wire _T_12 = _T_11 | io_lsu_busreq_r; // @[lsu_clkdomain.scala 75:61] + wire _T_24 = _T_12 | io_clk_override; // @[lsu_clkdomain.scala 79:72] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + assign io_lsu_bus_obuf_c1_clken = _T_9 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 74:30] + assign io_lsu_busm_clken = _T_24 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 79:21] + assign io_lsu_c1_m_clk = clock; // @[lsu_clkdomain.scala 87:26] + assign io_lsu_c1_r_clk = clock; // @[lsu_clkdomain.scala 88:26] + assign io_lsu_c2_m_clk = clock; // @[lsu_clkdomain.scala 89:26] + assign io_lsu_c2_r_clk = clock; // @[lsu_clkdomain.scala 90:26] + assign io_lsu_store_c1_m_clk = clock; // @[lsu_clkdomain.scala 91:26] + assign io_lsu_store_c1_r_clk = clock; // @[lsu_clkdomain.scala 92:26] + assign io_lsu_stbuf_c1_clk = clock; // @[lsu_clkdomain.scala 93:26] + assign io_lsu_bus_ibuf_c1_clk = clock; // @[lsu_clkdomain.scala 94:26] + assign io_lsu_bus_buf_c1_clk = clock; // @[lsu_clkdomain.scala 96:26] + assign io_lsu_free_c2_clk = clock; // @[lsu_clkdomain.scala 98:26] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_lsu_bus_obuf_c1_clken; // @[lib.scala 345:16] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_lsu_busm_clken; // @[lib.scala 345:16] +endmodule +module lsu_bus_buffer( + input clock, + input reset, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + input io_dec_tlu_force_halt, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_dec_lsu_valid_raw_d, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input [31:0] io_lsu_addr_m, + input [31:0] io_end_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_r, + input [31:0] io_store_data_r, + input io_no_word_merge_r, + input io_no_dword_merge_r, + input io_lsu_busreq_m, + input io_ld_full_hit_m, + input io_flush_m_up, + input io_flush_r, + input io_lsu_commit_r, + input io_is_sideeffects_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [7:0] io_ldst_byteen_ext_m, + input io_lsu_axi_aw_ready, + output io_lsu_axi_aw_valid, + output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, + input io_lsu_axi_w_ready, + output io_lsu_axi_w_valid, + output [63:0] io_lsu_axi_w_bits_data, + output io_lsu_axi_b_ready, + input io_lsu_axi_b_valid, + input [1:0] io_lsu_axi_b_bits_resp, + input [2:0] io_lsu_axi_b_bits_id, + input io_lsu_axi_ar_ready, + output io_lsu_axi_ar_valid, + output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, + output io_lsu_axi_r_ready, + input io_lsu_axi_r_valid, + input [2:0] io_lsu_axi_r_bits_id, + input [63:0] io_lsu_axi_r_bits_data, + input [1:0] io_lsu_axi_r_bits_resp, + input io_lsu_bus_clk_en, + input io_lsu_bus_clk_en_q, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [3:0] io_ld_byte_hit_buf_lo, + output [3:0] io_ld_byte_hit_buf_hi, + output [31:0] io_ld_fwddata_buf_lo, + output [31:0] io_ld_fwddata_buf_hi, + output [31:0] io_lsu_nonblock_load_data +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [63:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [31:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; + reg [31:0] _RAND_91; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_11_io_en; // @[lib.scala 404:23] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 77:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 78:46] + reg [31:0] buf_addr_0; // @[Reg.scala 27:20] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 80:74] + reg _T_4355; // @[Reg.scala 27:20] + reg _T_4352; // @[Reg.scala 27:20] + reg _T_4349; // @[Reg.scala 27:20] + reg _T_4346; // @[Reg.scala 27:20] + wire [3:0] buf_write = {_T_4355,_T_4352,_T_4349,_T_4346}; // @[Cat.scala 29:58] + wire _T_4 = _T_2 & buf_write[0]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_0; // @[Reg.scala 27:20] + wire _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_1; // @[Reg.scala 27:20] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_1; // @[Reg.scala 27:20] + wire _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_2; // @[Reg.scala 27:20] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_2; // @[Reg.scala 27:20] + wire _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_3; // @[Reg.scala 27:20] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_3; // @[Reg.scala 27:20] + wire _T_26 = buf_state_3 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_27 = _T_25 & _T_26; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_32 = _T_30 & buf_write[0]; // @[lsu_bus_buffer.scala 81:98] + wire _T_34 = _T_32 & _T_5; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_39 = _T_37 & buf_write[1]; // @[lsu_bus_buffer.scala 81:98] + wire _T_41 = _T_39 & _T_12; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_46 = _T_44 & buf_write[2]; // @[lsu_bus_buffer.scala 81:98] + wire _T_48 = _T_46 & _T_19; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_53 = _T_51 & buf_write[3]; // @[lsu_bus_buffer.scala 81:98] + wire _T_55 = _T_53 & _T_26; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] + reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 513:60] + wire _T_2590 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_4104 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4127 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4131 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] + reg obuf_valid; // @[lsu_bus_buffer.scala 349:54] + wire _T_4165 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4250 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4268 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4276 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_2594 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 417:132] + wire _T_2595 = buf_ageQ_3[3] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2583 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3913 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3936 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3940 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3974 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4059 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4077 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4085 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_2588 = buf_ageQ_3[2] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2576 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3722 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3745 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3749 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3783 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3868 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3886 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3894 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_2581 = buf_ageQ_3[1] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2569 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3531 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3554 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3558 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3592 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3677 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3695 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3703 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_2574 = buf_ageQ_3[0] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_3 = {_T_2595,_T_2588,_T_2581,_T_2574}; // @[Cat.scala 29:58] + wire _T_2694 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2696 = _T_2694 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2688 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2690 = _T_2688 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire _T_2682 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2684 = _T_2682 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_3 = {1'h0,_T_2696,_T_2690,_T_2684}; // @[Cat.scala 29:58] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 150:144] + wire _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 150:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 150:97] + reg [31:0] ibuf_addr; // @[Reg.scala 27:20] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 156:51] + reg ibuf_write; // @[Reg.scala 27:20] + wire _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 156:73] + reg ibuf_valid; // @[lsu_bus_buffer.scala 244:54] + wire _T_514 = _T_513 & ibuf_valid; // @[lsu_bus_buffer.scala 156:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 156:99] + wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[lsu_bus_buffer.scala 161:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 161:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 150:150] + wire _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 513:60] + wire _T_2564 = buf_ageQ_2[3] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2557 = buf_ageQ_2[2] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2550 = buf_ageQ_2[1] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2543 = buf_ageQ_2[0] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_2 = {_T_2564,_T_2557,_T_2550,_T_2543}; // @[Cat.scala 29:58] + wire _T_2673 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2675 = _T_2673 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2661 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2663 = _T_2661 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire _T_2655 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2657 = _T_2655 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_2 = {_T_2675,1'h0,_T_2663,_T_2657}; // @[Cat.scala 29:58] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_248 = |_T_247; // @[lsu_bus_buffer.scala 150:144] + wire _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 150:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 150:97] + wire _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 513:60] + wire _T_2533 = buf_ageQ_1[3] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2526 = buf_ageQ_1[2] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2519 = buf_ageQ_1[1] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2512 = buf_ageQ_1[0] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_1 = {_T_2533,_T_2526,_T_2519,_T_2512}; // @[Cat.scala 29:58] + wire _T_2646 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2648 = _T_2646 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2640 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2642 = _T_2640 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2628 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2630 = _T_2628 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_1 = {_T_2648,_T_2642,1'h0,_T_2630}; // @[Cat.scala 29:58] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_240 = |_T_239; // @[lsu_bus_buffer.scala 150:144] + wire _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 150:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 150:97] + wire _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 513:60] + wire _T_2502 = buf_ageQ_0[3] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2495 = buf_ageQ_0[2] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2488 = buf_ageQ_0[1] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2481 = buf_ageQ_0[0] & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_0 = {_T_2502,_T_2495,_T_2488,_T_2481}; // @[Cat.scala 29:58] + wire _T_2619 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2621 = _T_2619 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2613 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2615 = _T_2613 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2607 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2609 = _T_2607 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_0 = {_T_2621,_T_2615,_T_2609,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_232 = |_T_231; // @[lsu_bus_buffer.scala 150:144] + wire _T_233 = ~_T_232; // @[lsu_bus_buffer.scala 150:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[lsu_bus_buffer.scala 150:97] + wire _T_237 = _T_234 & _T_260; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[lsu_bus_buffer.scala 142:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 142:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_291 = |_T_290; // @[lsu_bus_buffer.scala 150:144] + wire _T_292 = ~_T_291; // @[lsu_bus_buffer.scala 150:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[lsu_bus_buffer.scala 150:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 150:150] + wire _T_296 = _T_293 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_283 = |_T_282; // @[lsu_bus_buffer.scala 150:144] + wire _T_284 = ~_T_283; // @[lsu_bus_buffer.scala 150:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[lsu_bus_buffer.scala 150:97] + wire _T_288 = _T_285 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_275 = |_T_274; // @[lsu_bus_buffer.scala 150:144] + wire _T_276 = ~_T_275; // @[lsu_bus_buffer.scala 150:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[lsu_bus_buffer.scala 150:97] + wire _T_280 = _T_277 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_267 = |_T_266; // @[lsu_bus_buffer.scala 150:144] + wire _T_268 = ~_T_267; // @[lsu_bus_buffer.scala 150:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[lsu_bus_buffer.scala 150:97] + wire _T_272 = _T_269 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[lsu_bus_buffer.scala 142:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 142:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_326 = |_T_325; // @[lsu_bus_buffer.scala 150:144] + wire _T_327 = ~_T_326; // @[lsu_bus_buffer.scala 150:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[lsu_bus_buffer.scala 150:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 150:150] + wire _T_331 = _T_328 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_318 = |_T_317; // @[lsu_bus_buffer.scala 150:144] + wire _T_319 = ~_T_318; // @[lsu_bus_buffer.scala 150:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[lsu_bus_buffer.scala 150:97] + wire _T_323 = _T_320 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_310 = |_T_309; // @[lsu_bus_buffer.scala 150:144] + wire _T_311 = ~_T_310; // @[lsu_bus_buffer.scala 150:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[lsu_bus_buffer.scala 150:97] + wire _T_315 = _T_312 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_302 = |_T_301; // @[lsu_bus_buffer.scala 150:144] + wire _T_303 = ~_T_302; // @[lsu_bus_buffer.scala 150:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[lsu_bus_buffer.scala 150:97] + wire _T_307 = _T_304 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[lsu_bus_buffer.scala 142:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 142:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_361 = |_T_360; // @[lsu_bus_buffer.scala 150:144] + wire _T_362 = ~_T_361; // @[lsu_bus_buffer.scala 150:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[lsu_bus_buffer.scala 150:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 150:150] + wire _T_366 = _T_363 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_353 = |_T_352; // @[lsu_bus_buffer.scala 150:144] + wire _T_354 = ~_T_353; // @[lsu_bus_buffer.scala 150:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[lsu_bus_buffer.scala 150:97] + wire _T_358 = _T_355 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_345 = |_T_344; // @[lsu_bus_buffer.scala 150:144] + wire _T_346 = ~_T_345; // @[lsu_bus_buffer.scala 150:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[lsu_bus_buffer.scala 150:97] + wire _T_350 = _T_347 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_337 = |_T_336; // @[lsu_bus_buffer.scala 150:144] + wire _T_338 = ~_T_337; // @[lsu_bus_buffer.scala 150:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[lsu_bus_buffer.scala 150:97] + wire _T_342 = _T_339 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[lsu_bus_buffer.scala 142:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 142:77] + wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_396 = |_T_395; // @[lsu_bus_buffer.scala 151:144] + wire _T_397 = ~_T_396; // @[lsu_bus_buffer.scala 151:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[lsu_bus_buffer.scala 151:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 157:51] + wire _T_518 = _T_517 & ibuf_write; // @[lsu_bus_buffer.scala 157:73] + wire _T_519 = _T_518 & ibuf_valid; // @[lsu_bus_buffer.scala 157:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 157:99] + wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[lsu_bus_buffer.scala 162:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[lsu_bus_buffer.scala 162:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 151:150] + wire _T_401 = _T_398 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_388 = |_T_387; // @[lsu_bus_buffer.scala 151:144] + wire _T_389 = ~_T_388; // @[lsu_bus_buffer.scala 151:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[lsu_bus_buffer.scala 151:97] + wire _T_393 = _T_390 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_380 = |_T_379; // @[lsu_bus_buffer.scala 151:144] + wire _T_381 = ~_T_380; // @[lsu_bus_buffer.scala 151:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[lsu_bus_buffer.scala 151:97] + wire _T_385 = _T_382 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_372 = |_T_371; // @[lsu_bus_buffer.scala 151:144] + wire _T_373 = ~_T_372; // @[lsu_bus_buffer.scala 151:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[lsu_bus_buffer.scala 151:97] + wire _T_377 = _T_374 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[lsu_bus_buffer.scala 143:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 143:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_431 = |_T_430; // @[lsu_bus_buffer.scala 151:144] + wire _T_432 = ~_T_431; // @[lsu_bus_buffer.scala 151:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[lsu_bus_buffer.scala 151:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 151:150] + wire _T_436 = _T_433 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_423 = |_T_422; // @[lsu_bus_buffer.scala 151:144] + wire _T_424 = ~_T_423; // @[lsu_bus_buffer.scala 151:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[lsu_bus_buffer.scala 151:97] + wire _T_428 = _T_425 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_415 = |_T_414; // @[lsu_bus_buffer.scala 151:144] + wire _T_416 = ~_T_415; // @[lsu_bus_buffer.scala 151:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[lsu_bus_buffer.scala 151:97] + wire _T_420 = _T_417 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_407 = |_T_406; // @[lsu_bus_buffer.scala 151:144] + wire _T_408 = ~_T_407; // @[lsu_bus_buffer.scala 151:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[lsu_bus_buffer.scala 151:97] + wire _T_412 = _T_409 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[lsu_bus_buffer.scala 143:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 143:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_466 = |_T_465; // @[lsu_bus_buffer.scala 151:144] + wire _T_467 = ~_T_466; // @[lsu_bus_buffer.scala 151:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[lsu_bus_buffer.scala 151:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 151:150] + wire _T_471 = _T_468 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_458 = |_T_457; // @[lsu_bus_buffer.scala 151:144] + wire _T_459 = ~_T_458; // @[lsu_bus_buffer.scala 151:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[lsu_bus_buffer.scala 151:97] + wire _T_463 = _T_460 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_450 = |_T_449; // @[lsu_bus_buffer.scala 151:144] + wire _T_451 = ~_T_450; // @[lsu_bus_buffer.scala 151:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[lsu_bus_buffer.scala 151:97] + wire _T_455 = _T_452 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_442 = |_T_441; // @[lsu_bus_buffer.scala 151:144] + wire _T_443 = ~_T_442; // @[lsu_bus_buffer.scala 151:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[lsu_bus_buffer.scala 151:97] + wire _T_447 = _T_444 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[lsu_bus_buffer.scala 143:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 143:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_501 = |_T_500; // @[lsu_bus_buffer.scala 151:144] + wire _T_502 = ~_T_501; // @[lsu_bus_buffer.scala 151:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[lsu_bus_buffer.scala 151:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 151:150] + wire _T_506 = _T_503 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_493 = |_T_492; // @[lsu_bus_buffer.scala 151:144] + wire _T_494 = ~_T_493; // @[lsu_bus_buffer.scala 151:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[lsu_bus_buffer.scala 151:97] + wire _T_498 = _T_495 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_485 = |_T_484; // @[lsu_bus_buffer.scala 151:144] + wire _T_486 = ~_T_485; // @[lsu_bus_buffer.scala 151:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[lsu_bus_buffer.scala 151:97] + wire _T_490 = _T_487 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_477 = |_T_476; // @[lsu_bus_buffer.scala 151:144] + wire _T_478 = ~_T_477; // @[lsu_bus_buffer.scala 151:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[lsu_bus_buffer.scala 151:97] + wire _T_482 = _T_479 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[lsu_bus_buffer.scala 143:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 143:77] + wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] + wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58] + wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] + wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_0; // @[Reg.scala 27:20] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_1; // @[Reg.scala 27:20] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_2; // @[Reg.scala 27:20] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_3; // @[Reg.scala 27:20] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 172:97] + wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] + reg [31:0] ibuf_data; // @[Reg.scala 27:20] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 173:32] + wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[lsu_bus_buffer.scala 178:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[lsu_bus_buffer.scala 178:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[lsu_bus_buffer.scala 178:97] + wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[lsu_bus_buffer.scala 179:32] + wire [3:0] _T_750 = io_lsu_pkt_r_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_751 = io_lsu_pkt_r_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_752 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[lsu_bus_buffer.scala 186:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[lsu_bus_buffer.scala 187:24] + wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[lsu_bus_buffer.scala 188:24] + wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[lsu_bus_buffer.scala 189:24] + wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72] + wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72] + wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72] + wire [31:0] _T_802 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58] + wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58] + wire [31:0] _T_810 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72] + wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72] + wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] + wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] + wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[lsu_bus_buffer.scala 207:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[lsu_bus_buffer.scala 209:31] + wire _T_845 = io_lsu_pkt_r_bits_word & _T_756; // @[Mux.scala 27:72] + wire _T_846 = io_lsu_pkt_r_bits_half & _T_844; // @[Mux.scala 27:72] + wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] + wire is_aligned_r = _T_848 | io_lsu_pkt_r_bits_by; // @[Mux.scala 27:72] + wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[lsu_bus_buffer.scala 211:60] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[lsu_bus_buffer.scala 211:34] + wire _T_852 = ~ibuf_valid; // @[lsu_bus_buffer.scala 211:84] + wire ibuf_byp = _T_851 & _T_852; // @[lsu_bus_buffer.scala 211:82] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[lsu_bus_buffer.scala 212:36] + wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 212:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 212:54] + wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 214:36] + reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 257:55] + wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 220:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 220:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 239:54] + wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 239:80] + wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 239:93] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 239:129] + wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 239:106] + wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 239:152] + wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 239:150] + wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 239:175] + wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 239:173] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 240:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 220:98] + wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 220:82] + wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 220:80] + wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 221:5] + wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 215:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 215:42] + wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 215:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 215:120] + wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 215:100] + wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 215:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 221:16] + reg ibuf_sideeffect; // @[Reg.scala 27:20] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 221:35] + wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 221:55] + wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 221:53] + wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 221:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 220:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 214:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 214:49] + reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 627:49] + reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 626:49] + reg [1:0] ibuf_tag; // @[Reg.scala 27:20] + wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 230:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 234:46] + wire [31:0] ibuf_data_in = {_T_920,_T_911,_T_902,_T_893}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 237:60] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 237:95] + wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 241:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 241:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 241:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 241:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 241:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 241:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 241:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 241:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 241:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 241:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 242:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 244:58] + wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 244:93] + reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] + reg ibuf_dual; // @[Reg.scala 27:20] + reg ibuf_samedw; // @[Reg.scala 27:20] + reg ibuf_nomerge; // @[Reg.scala 27:20] + reg ibuf_unsign; // @[Reg.scala 27:20] + reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire _T_4441 = buf_write[3] & _T_2590; // @[lsu_bus_buffer.scala 533:64] + wire _T_4436 = buf_write[2] & _T_2583; // @[lsu_bus_buffer.scala 533:64] + wire [1:0] _T_4444 = _T_4441 + _T_4436; // @[lsu_bus_buffer.scala 533:142] + wire _T_4431 = buf_write[1] & _T_2576; // @[lsu_bus_buffer.scala 533:64] + wire [1:0] _GEN_376 = {{1'd0}, _T_4431}; // @[lsu_bus_buffer.scala 533:142] + wire [2:0] _T_4445 = _T_4444 + _GEN_376; // @[lsu_bus_buffer.scala 533:142] + wire _T_4426 = buf_write[0] & _T_2569; // @[lsu_bus_buffer.scala 533:64] + wire [2:0] _GEN_377 = {{2'd0}, _T_4426}; // @[lsu_bus_buffer.scala 533:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4445 + _GEN_377; // @[lsu_bus_buffer.scala 533:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 267:43] + wire [1:0] _T_4459 = _T_2590 + _T_2583; // @[lsu_bus_buffer.scala 534:126] + wire [1:0] _GEN_378 = {{1'd0}, _T_2576}; // @[lsu_bus_buffer.scala 534:126] + wire [2:0] _T_4460 = _T_4459 + _GEN_378; // @[lsu_bus_buffer.scala 534:126] + wire [2:0] _GEN_379 = {{2'd0}, _T_2569}; // @[lsu_bus_buffer.scala 534:126] + wire [3:0] buf_numvld_cmd_any = _T_4460 + _GEN_379; // @[lsu_bus_buffer.scala 534:126] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 267:72] + wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 267:51] + reg _T_1791; // @[Reg.scala 27:20] + wire [2:0] obuf_wr_timer = {{2'd0}, _T_1791}; // @[lsu_bus_buffer.scala 365:17] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 267:97] + wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 267:80] + wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 267:114] + wire _T_1918 = |buf_age_3; // @[lsu_bus_buffer.scala 383:58] + wire _T_1919 = ~_T_1918; // @[lsu_bus_buffer.scala 383:45] + wire _T_1921 = _T_1919 & _T_2590; // @[lsu_bus_buffer.scala 383:63] + wire _T_1912 = |buf_age_2; // @[lsu_bus_buffer.scala 383:58] + wire _T_1913 = ~_T_1912; // @[lsu_bus_buffer.scala 383:45] + wire _T_1915 = _T_1913 & _T_2583; // @[lsu_bus_buffer.scala 383:63] + wire _T_1906 = |buf_age_1; // @[lsu_bus_buffer.scala 383:58] + wire _T_1907 = ~_T_1906; // @[lsu_bus_buffer.scala 383:45] + wire _T_1909 = _T_1907 & _T_2576; // @[lsu_bus_buffer.scala 383:63] + wire _T_1900 = |buf_age_0; // @[lsu_bus_buffer.scala 383:58] + wire _T_1901 = ~_T_1900; // @[lsu_bus_buffer.scala 383:45] + wire _T_1903 = _T_1901 & _T_2569; // @[lsu_bus_buffer.scala 383:63] + wire [3:0] CmdPtr0Dec = {_T_1921,_T_1915,_T_1909,_T_1903}; // @[Cat.scala 29:58] + wire [7:0] _T_1993 = {4'h0,_T_1921,_T_1915,_T_1909,_T_1903}; // @[Cat.scala 29:58] + wire _T_1996 = _T_1993[4] | _T_1993[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_1998 = _T_1996 | _T_1993[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2000 = _T_1998 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2003 = _T_1993[2] | _T_1993[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2005 = _T_2003 | _T_1993[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2007 = _T_2005 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2010 = _T_1993[1] | _T_1993[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2012 = _T_2010 | _T_1993[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2014 = _T_2012 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2016 = {_T_2000,_T_2007,_T_2014}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr0 = _T_2016[1:0]; // @[lsu_bus_buffer.scala 396:11] + wire _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 268:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 268:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 268:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 268:114] + reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] + reg buf_nomerge_1; // @[Reg.scala 27:20] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] + reg buf_nomerge_2; // @[Reg.scala 27:20] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] + reg buf_nomerge_3; // @[Reg.scala 27:20] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 268:31] + wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 268:29] + reg _T_4325; // @[Reg.scala 27:20] + reg _T_4322; // @[Reg.scala 27:20] + reg _T_4319; // @[Reg.scala 27:20] + reg _T_4316; // @[Reg.scala 27:20] + wire [3:0] buf_sideeffect = {_T_4325,_T_4322,_T_4319,_T_4316}; // @[Cat.scala 29:58] + wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72] + wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72] + wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72] + wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72] + wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] + wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] + wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] + wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 269:5] + wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 268:140] + wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 271:58] + wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 271:72] + wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] + wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] + wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 271:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 271:101] + wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 269:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 269:117] + wire _T_4477 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4481 = _T_4477 | _T_2590; // @[lsu_bus_buffer.scala 535:74] + wire _T_4472 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4476 = _T_4472 | _T_2583; // @[lsu_bus_buffer.scala 535:74] + wire [1:0] _T_4482 = _T_4481 + _T_4476; // @[lsu_bus_buffer.scala 535:154] + wire _T_4467 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4471 = _T_4467 | _T_2576; // @[lsu_bus_buffer.scala 535:74] + wire [1:0] _GEN_380 = {{1'd0}, _T_4471}; // @[lsu_bus_buffer.scala 535:154] + wire [2:0] _T_4483 = _T_4482 + _GEN_380; // @[lsu_bus_buffer.scala 535:154] + wire _T_4462 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4466 = _T_4462 | _T_2569; // @[lsu_bus_buffer.scala 535:74] + wire [2:0] _GEN_381 = {{2'd0}, _T_4466}; // @[lsu_bus_buffer.scala 535:154] + wire [3:0] buf_numvld_pend_any = _T_4483 + _GEN_381; // @[lsu_bus_buffer.scala 535:154] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 273:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 273:31] + wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 273:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 273:89] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 273:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 289:32] + wire _T_4751 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4753 = _T_4751 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4754 = _T_4753 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4755 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4757 = _T_4755 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4758 = _T_4757 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4767 = _T_4754 | _T_4758; // @[lsu_bus_buffer.scala 563:153] + wire _T_4759 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4761 = _T_4759 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4762 = _T_4761 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4768 = _T_4767 | _T_4762; // @[lsu_bus_buffer.scala 563:153] + wire _T_4763 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4765 = _T_4763 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4766 = _T_4765 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire bus_sideeffect_pend = _T_4768 | _T_4766; // @[lsu_bus_buffer.scala 563:153] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 289:74] + wire _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 289:52] + wire _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 289:50] + wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] + wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] + wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] + wire _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 290:36] + wire found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 388:31] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 290:47] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 291:141] + wire _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 291:105] + wire _T_1148 = _T_1108 & _T_1147; // @[lsu_bus_buffer.scala 291:103] + reg buf_dual_3; // @[Reg.scala 27:20] + reg buf_dual_2; // @[Reg.scala 27:20] + reg buf_dual_1; // @[Reg.scala 27:20] + reg buf_dual_0; // @[Reg.scala 27:20] + wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58] + wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72] + wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72] + wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72] + wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72] + wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72] + reg buf_samedw_3; // @[Reg.scala 27:20] + reg buf_samedw_2; // @[Reg.scala 27:20] + reg buf_samedw_1; // @[Reg.scala 27:20] + reg buf_samedw_0; // @[Reg.scala 27:20] + wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58] + wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72] + wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72] + wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72] + wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72] + wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] + wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] + wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] + wire _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 292:77] + wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] + wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] + wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] + wire _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 292:150] + wire _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 292:148] + wire _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 292:8] + wire [3:0] _T_1959 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 384:62] + wire [3:0] _T_1960 = buf_age_3 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1961 = |_T_1960; // @[lsu_bus_buffer.scala 384:76] + wire _T_1962 = ~_T_1961; // @[lsu_bus_buffer.scala 384:45] + wire _T_1964 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1965 = _T_1962 & _T_1964; // @[lsu_bus_buffer.scala 384:81] + wire _T_1967 = _T_1965 & _T_2590; // @[lsu_bus_buffer.scala 384:98] + wire [3:0] _T_1949 = buf_age_2 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1950 = |_T_1949; // @[lsu_bus_buffer.scala 384:76] + wire _T_1951 = ~_T_1950; // @[lsu_bus_buffer.scala 384:45] + wire _T_1953 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1954 = _T_1951 & _T_1953; // @[lsu_bus_buffer.scala 384:81] + wire _T_1956 = _T_1954 & _T_2583; // @[lsu_bus_buffer.scala 384:98] + wire [3:0] _T_1938 = buf_age_1 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1939 = |_T_1938; // @[lsu_bus_buffer.scala 384:76] + wire _T_1940 = ~_T_1939; // @[lsu_bus_buffer.scala 384:45] + wire _T_1942 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1943 = _T_1940 & _T_1942; // @[lsu_bus_buffer.scala 384:81] + wire _T_1945 = _T_1943 & _T_2576; // @[lsu_bus_buffer.scala 384:98] + wire [3:0] _T_1927 = buf_age_0 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1928 = |_T_1927; // @[lsu_bus_buffer.scala 384:76] + wire _T_1929 = ~_T_1928; // @[lsu_bus_buffer.scala 384:45] + wire _T_1931 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1932 = _T_1929 & _T_1931; // @[lsu_bus_buffer.scala 384:81] + wire _T_1934 = _T_1932 & _T_2569; // @[lsu_bus_buffer.scala 384:98] + wire [3:0] CmdPtr1Dec = {_T_1967,_T_1956,_T_1945,_T_1934}; // @[Cat.scala 29:58] + wire found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 389:31] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 292:181] + wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] + wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] + wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] + wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72] + wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72] + wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] + wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] + wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] + wire _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 292:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 292:269] + wire _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 291:164] + wire _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 289:98] + wire _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 293:48] + wire _T_1232 = io_lsu_axi_ar_ready | _T_1231; // @[lsu_bus_buffer.scala 293:46] + reg obuf_nosend; // @[Reg.scala 27:20] + wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 293:60] + wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 293:29] + wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 293:77] + wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 293:75] + reg [31:0] obuf_addr; // @[Reg.scala 27:20] + wire _T_4787 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4788 = obuf_valid & _T_4787; // @[lsu_bus_buffer.scala 565:19] + wire _T_4818 = _T_4755 & _T_4788; // @[Mux.scala 27:72] + wire _T_4798 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4799 = obuf_valid & _T_4798; // @[lsu_bus_buffer.scala 565:19] + wire _T_4819 = _T_4759 & _T_4799; // @[Mux.scala 27:72] + wire _T_4822 = _T_4818 | _T_4819; // @[Mux.scala 27:72] + wire _T_4809 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4810 = obuf_valid & _T_4809; // @[lsu_bus_buffer.scala 565:19] + wire _T_4820 = _T_4763 & _T_4810; // @[Mux.scala 27:72] + wire bus_addr_match_pending = _T_4822 | _T_4820; // @[Mux.scala 27:72] + wire _T_1237 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 293:94] + wire _T_1238 = _T_1236 & _T_1237; // @[lsu_bus_buffer.scala 293:92] + wire obuf_wr_en = _T_1238 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 293:118] + wire _T_1240 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 296:47] + wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 568:40] + wire bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 569:40] + wire _T_4834 = bus_wcmd_sent & bus_wdata_sent; // @[lsu_bus_buffer.scala 570:52] + wire _T_4835 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 570:112] + wire bus_cmd_sent = _T_4834 | _T_4835; // @[lsu_bus_buffer.scala 570:89] + wire _T_1241 = bus_cmd_sent | _T_1240; // @[lsu_bus_buffer.scala 296:33] + wire _T_1242 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 296:65] + wire _T_1243 = _T_1241 & _T_1242; // @[lsu_bus_buffer.scala 296:63] + wire _T_1244 = _T_1243 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 296:77] + wire obuf_rst = _T_1244 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 296:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 297:26] + wire [31:0] _T_1281 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1282 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1283 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1284 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1285 = _T_1281 | _T_1282; // @[Mux.scala 27:72] + wire [31:0] _T_1286 = _T_1285 | _T_1283; // @[Mux.scala 27:72] + wire [31:0] _T_1287 = _T_1286 | _T_1284; // @[Mux.scala 27:72] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1287; // @[lsu_bus_buffer.scala 299:25] + reg [1:0] buf_sz_0; // @[Reg.scala 27:20] + wire [1:0] _T_1294 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire [1:0] _T_1295 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_2; // @[Reg.scala 27:20] + wire [1:0] _T_1296 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_3; // @[Reg.scala 27:20] + wire [1:0] _T_1297 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1298 = _T_1294 | _T_1295; // @[Mux.scala 27:72] + wire [1:0] _T_1299 = _T_1298 | _T_1296; // @[Mux.scala 27:72] + wire [1:0] _T_1300 = _T_1299 | _T_1297; // @[Mux.scala 27:72] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1300; // @[lsu_bus_buffer.scala 302:23] + wire [7:0] _T_2018 = {4'h0,_T_1967,_T_1956,_T_1945,_T_1934}; // @[Cat.scala 29:58] + wire _T_2021 = _T_2018[4] | _T_2018[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_2023 = _T_2021 | _T_2018[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2025 = _T_2023 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2028 = _T_2018[2] | _T_2018[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2030 = _T_2028 | _T_2018[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2032 = _T_2030 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2035 = _T_2018[1] | _T_2018[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2037 = _T_2035 | _T_2018[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2039 = _T_2037 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2041 = {_T_2025,_T_2032,_T_2039}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr1 = _T_2041[1:0]; // @[lsu_bus_buffer.scala 398:11] + wire _T_1302 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 310:39] + wire _T_1303 = ~_T_1302; // @[lsu_bus_buffer.scala 310:26] + wire obuf_data_done_in = _T_1303 & bus_wdata_sent; // @[lsu_bus_buffer.scala 313:52] + wire _T_1309 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 314:72] + wire _T_1312 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 314:98] + wire _T_1313 = obuf_sz_in[0] & _T_1312; // @[lsu_bus_buffer.scala 314:96] + wire _T_1314 = _T_1309 | _T_1313; // @[lsu_bus_buffer.scala 314:79] + wire _T_1317 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 314:153] + wire _T_1318 = ~_T_1317; // @[lsu_bus_buffer.scala 314:134] + wire _T_1319 = obuf_sz_in[1] & _T_1318; // @[lsu_bus_buffer.scala 314:132] + wire _T_1320 = _T_1314 | _T_1319; // @[lsu_bus_buffer.scala 314:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1320; // @[lsu_bus_buffer.scala 314:28] + wire _T_1337 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 328:40] + wire _T_1338 = _T_1337 & obuf_aligned_in; // @[lsu_bus_buffer.scala 328:60] + wire _T_1343 = ~obuf_write_in; // @[lsu_bus_buffer.scala 328:113] + wire _T_1344 = _T_1338 & _T_1343; // @[lsu_bus_buffer.scala 328:111] + wire _T_1345 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 328:130] + wire _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 328:128] + wire _T_1347 = ~obuf_nosend; // @[lsu_bus_buffer.scala 329:20] + wire _T_1348 = obuf_valid & _T_1347; // @[lsu_bus_buffer.scala 329:18] + reg obuf_rdrsp_pend; // @[Reg.scala 27:20] + wire bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 571:38] + wire _T_1349 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 329:90] + wire _T_1350 = bus_rsp_read & _T_1349; // @[lsu_bus_buffer.scala 329:70] + wire _T_1351 = ~_T_1350; // @[lsu_bus_buffer.scala 329:55] + wire _T_1352 = obuf_rdrsp_pend & _T_1351; // @[lsu_bus_buffer.scala 329:53] + wire _T_1353 = _T_1348 | _T_1352; // @[lsu_bus_buffer.scala 329:34] + wire obuf_nosend_in = _T_1346 & _T_1353; // @[lsu_bus_buffer.scala 328:177] + wire _T_1321 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 322:45] + wire _T_1322 = obuf_wr_en & _T_1321; // @[lsu_bus_buffer.scala 322:43] + wire _T_1323 = ~_T_1322; // @[lsu_bus_buffer.scala 322:30] + wire _T_1324 = _T_1323 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 322:62] + wire _T_1328 = _T_1324 & _T_1351; // @[lsu_bus_buffer.scala 322:80] + wire _T_1331 = _T_1328 | bus_cmd_sent; // @[lsu_bus_buffer.scala 322:139] + wire obuf_rdrsp_pend_in = _T_1331 & _T_2594; // @[lsu_bus_buffer.scala 322:171] + wire obuf_rdrsp_pend_en = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 323:47] + wire [7:0] _T_1401 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1402 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1403 = io_end_addr_r[2] ? _T_1401 : _T_1402; // @[lsu_bus_buffer.scala 332:46] + wire _T_1404 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 62:123] + wire _T_1405 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 62:123] + wire _T_1406 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 62:123] + wire _T_1407 = CmdPtr1 == 2'h3; // @[lsu_bus_buffer.scala 62:123] + wire [31:0] _T_1408 = _T_1404 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1409 = _T_1405 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1410 = _T_1406 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1411 = _T_1407 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1412 = _T_1408 | _T_1409; // @[Mux.scala 27:72] + wire [31:0] _T_1413 = _T_1412 | _T_1410; // @[Mux.scala 27:72] + wire [31:0] _T_1414 = _T_1413 | _T_1411; // @[Mux.scala 27:72] + wire [3:0] _T_1422 = _T_1404 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1423 = _T_1405 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1424 = _T_1406 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1425 = _T_1407 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1426 = _T_1422 | _T_1423; // @[Mux.scala 27:72] + wire [3:0] _T_1427 = _T_1426 | _T_1424; // @[Mux.scala 27:72] + wire [3:0] _T_1428 = _T_1427 | _T_1425; // @[Mux.scala 27:72] + wire [7:0] _T_1430 = {_T_1428,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1443 = {4'h0,_T_1428}; // @[Cat.scala 29:58] + wire [7:0] _T_1444 = _T_1414[2] ? _T_1430 : _T_1443; // @[lsu_bus_buffer.scala 333:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1403 : _T_1444; // @[lsu_bus_buffer.scala 332:28] + wire [63:0] _T_1446 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1447 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1448 = io_lsu_addr_r[2] ? _T_1446 : _T_1447; // @[lsu_bus_buffer.scala 335:44] + wire [31:0] _T_1467 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1468 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1469 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1470 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1471 = _T_1467 | _T_1468; // @[Mux.scala 27:72] + wire [31:0] _T_1472 = _T_1471 | _T_1469; // @[Mux.scala 27:72] + wire [31:0] _T_1473 = _T_1472 | _T_1470; // @[Mux.scala 27:72] + wire [63:0] _T_1475 = {_T_1473,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1488 = {32'h0,_T_1473}; // @[Cat.scala 29:58] + wire [63:0] _T_1489 = _T_1287[2] ? _T_1475 : _T_1488; // @[lsu_bus_buffer.scala 336:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1448 : _T_1489; // @[lsu_bus_buffer.scala 335:26] + wire [63:0] _T_1491 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1492 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1493 = io_end_addr_r[2] ? _T_1491 : _T_1492; // @[lsu_bus_buffer.scala 337:44] + wire [31:0] _T_1512 = _T_1404 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1513 = _T_1405 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1514 = _T_1406 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1515 = _T_1407 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1516 = _T_1512 | _T_1513; // @[Mux.scala 27:72] + wire [31:0] _T_1517 = _T_1516 | _T_1514; // @[Mux.scala 27:72] + wire [31:0] _T_1518 = _T_1517 | _T_1515; // @[Mux.scala 27:72] + wire [63:0] _T_1520 = {_T_1518,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1533 = {32'h0,_T_1518}; // @[Cat.scala 29:58] + wire [63:0] _T_1534 = _T_1414[2] ? _T_1520 : _T_1533; // @[lsu_bus_buffer.scala 338:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1493 : _T_1534; // @[lsu_bus_buffer.scala 337:26] + wire _T_1619 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 344:30] + wire _T_1620 = _T_1619 & found_cmdptr0; // @[lsu_bus_buffer.scala 344:43] + wire _T_1621 = _T_1620 & found_cmdptr1; // @[lsu_bus_buffer.scala 344:59] + wire _T_1635 = _T_1621 & _T_1107; // @[lsu_bus_buffer.scala 344:75] + wire [2:0] _T_1640 = _T_1404 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1641 = _T_1405 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1644 = _T_1640 | _T_1641; // @[Mux.scala 27:72] + wire [2:0] _T_1642 = _T_1406 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1645 = _T_1644 | _T_1642; // @[Mux.scala 27:72] + wire [2:0] _T_1643 = _T_1407 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1646 = _T_1645 | _T_1643; // @[Mux.scala 27:72] + wire _T_1648 = _T_1646 == 3'h2; // @[lsu_bus_buffer.scala 344:150] + wire _T_1649 = _T_1635 & _T_1648; // @[lsu_bus_buffer.scala 344:118] + wire _T_1688 = _T_1649 & _T_1053; // @[lsu_bus_buffer.scala 345:85] + wire _T_1725 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 346:36] + reg buf_dualhi_3; // @[Reg.scala 27:20] + reg buf_dualhi_2; // @[Reg.scala 27:20] + reg buf_dualhi_1; // @[Reg.scala 27:20] + reg buf_dualhi_0; // @[Reg.scala 27:20] + wire [3:0] _T_1728 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58] + wire _T_1737 = _T_1023 & _T_1728[0]; // @[Mux.scala 27:72] + wire _T_1738 = _T_1024 & _T_1728[1]; // @[Mux.scala 27:72] + wire _T_1741 = _T_1737 | _T_1738; // @[Mux.scala 27:72] + wire _T_1739 = _T_1025 & _T_1728[2]; // @[Mux.scala 27:72] + wire _T_1742 = _T_1741 | _T_1739; // @[Mux.scala 27:72] + wire _T_1740 = _T_1026 & _T_1728[3]; // @[Mux.scala 27:72] + wire _T_1743 = _T_1742 | _T_1740; // @[Mux.scala 27:72] + wire _T_1745 = ~_T_1743; // @[lsu_bus_buffer.scala 346:107] + wire _T_1746 = _T_1725 & _T_1745; // @[lsu_bus_buffer.scala 346:105] + wire _T_1766 = _T_1746 & _T_1185; // @[lsu_bus_buffer.scala 346:177] + wire _T_1767 = _T_1688 & _T_1766; // @[lsu_bus_buffer.scala 345:122] + wire _T_1768 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 347:19] + wire _T_1769 = _T_1768 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 347:35] + wire obuf_merge_en = _T_1767 | _T_1769; // @[lsu_bus_buffer.scala 346:250] + wire _T_1537 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1541 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1545 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1549 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1553 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1557 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1561 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1565 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 339:80] + wire [7:0] _T_1577 = _T_1537 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1582 = _T_1541 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1587 = _T_1545 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1592 = _T_1549 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1597 = _T_1553 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1602 = _T_1557 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1607 = _T_1561 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1612 = _T_1565 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 340:44] + wire [63:0] obuf_data_in = {_T_1612,_T_1607,_T_1602,_T_1597,_T_1592,_T_1587,_T_1582,_T_1577}; // @[Cat.scala 29:58] + wire _T_1771 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 349:58] + wire _T_1772 = ~obuf_rst; // @[lsu_bus_buffer.scala 349:93] + reg [63:0] obuf_data; // @[Reg.scala 27:20] + wire _T_1792 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1793 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 370:30] + wire _T_1794 = ibuf_valid & _T_1793; // @[lsu_bus_buffer.scala 370:19] + wire _T_1795 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 371:18] + wire _T_1796 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 371:57] + wire _T_1797 = io_ldst_dual_r & _T_1796; // @[lsu_bus_buffer.scala 371:45] + wire _T_1798 = _T_1795 | _T_1797; // @[lsu_bus_buffer.scala 371:27] + wire _T_1799 = io_lsu_busreq_r & _T_1798; // @[lsu_bus_buffer.scala 370:58] + wire _T_1800 = _T_1794 | _T_1799; // @[lsu_bus_buffer.scala 370:39] + wire _T_1801 = ~_T_1800; // @[lsu_bus_buffer.scala 370:5] + wire _T_1802 = _T_1792 & _T_1801; // @[lsu_bus_buffer.scala 369:76] + wire _T_1803 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1804 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 370:30] + wire _T_1805 = ibuf_valid & _T_1804; // @[lsu_bus_buffer.scala 370:19] + wire _T_1806 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 371:18] + wire _T_1807 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 371:57] + wire _T_1808 = io_ldst_dual_r & _T_1807; // @[lsu_bus_buffer.scala 371:45] + wire _T_1809 = _T_1806 | _T_1808; // @[lsu_bus_buffer.scala 371:27] + wire _T_1810 = io_lsu_busreq_r & _T_1809; // @[lsu_bus_buffer.scala 370:58] + wire _T_1811 = _T_1805 | _T_1810; // @[lsu_bus_buffer.scala 370:39] + wire _T_1812 = ~_T_1811; // @[lsu_bus_buffer.scala 370:5] + wire _T_1813 = _T_1803 & _T_1812; // @[lsu_bus_buffer.scala 369:76] + wire _T_1814 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1815 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 370:30] + wire _T_1816 = ibuf_valid & _T_1815; // @[lsu_bus_buffer.scala 370:19] + wire _T_1817 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 371:18] + wire _T_1818 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 371:57] + wire _T_1819 = io_ldst_dual_r & _T_1818; // @[lsu_bus_buffer.scala 371:45] + wire _T_1820 = _T_1817 | _T_1819; // @[lsu_bus_buffer.scala 371:27] + wire _T_1821 = io_lsu_busreq_r & _T_1820; // @[lsu_bus_buffer.scala 370:58] + wire _T_1822 = _T_1816 | _T_1821; // @[lsu_bus_buffer.scala 370:39] + wire _T_1823 = ~_T_1822; // @[lsu_bus_buffer.scala 370:5] + wire _T_1824 = _T_1814 & _T_1823; // @[lsu_bus_buffer.scala 369:76] + wire _T_1825 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1826 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 370:30] + wire _T_1828 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 371:18] + wire _T_1829 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 371:57] + wire [1:0] _T_1837 = _T_1824 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] + wire [1:0] _T_1838 = _T_1813 ? 2'h1 : _T_1837; // @[Mux.scala 98:16] + wire [1:0] WrPtr0_m = _T_1802 ? 2'h0 : _T_1838; // @[Mux.scala 98:16] + wire _T_1843 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 376:33] + wire _T_1844 = io_lsu_busreq_m & _T_1843; // @[lsu_bus_buffer.scala 376:22] + wire _T_1845 = _T_1794 | _T_1844; // @[lsu_bus_buffer.scala 375:112] + wire _T_1851 = _T_1845 | _T_1799; // @[lsu_bus_buffer.scala 376:42] + wire _T_1852 = ~_T_1851; // @[lsu_bus_buffer.scala 375:78] + wire _T_1853 = _T_1792 & _T_1852; // @[lsu_bus_buffer.scala 375:76] + wire _T_1857 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 376:33] + wire _T_1858 = io_lsu_busreq_m & _T_1857; // @[lsu_bus_buffer.scala 376:22] + wire _T_1859 = _T_1805 | _T_1858; // @[lsu_bus_buffer.scala 375:112] + wire _T_1865 = _T_1859 | _T_1810; // @[lsu_bus_buffer.scala 376:42] + wire _T_1866 = ~_T_1865; // @[lsu_bus_buffer.scala 375:78] + wire _T_1867 = _T_1803 & _T_1866; // @[lsu_bus_buffer.scala 375:76] + wire _T_1871 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 376:33] + wire _T_1872 = io_lsu_busreq_m & _T_1871; // @[lsu_bus_buffer.scala 376:22] + wire _T_1873 = _T_1816 | _T_1872; // @[lsu_bus_buffer.scala 375:112] + wire _T_1879 = _T_1873 | _T_1821; // @[lsu_bus_buffer.scala 376:42] + wire _T_1880 = ~_T_1879; // @[lsu_bus_buffer.scala 375:78] + wire _T_1881 = _T_1814 & _T_1880; // @[lsu_bus_buffer.scala 375:76] + reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 514:63] + wire _T_2717 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2718 = buf_rspageQ_0[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2714 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2715 = buf_rspageQ_0[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2711 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2712 = buf_rspageQ_0[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2708 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2709 = buf_rspageQ_0[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_0 = {_T_2718,_T_2715,_T_2712,_T_2709}; // @[Cat.scala 29:58] + wire _T_1972 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 387:65] + wire _T_1973 = ~_T_1972; // @[lsu_bus_buffer.scala 387:44] + wire _T_1975 = _T_1973 & _T_2708; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 514:63] + wire _T_2733 = buf_rspageQ_1[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2730 = buf_rspageQ_1[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2727 = buf_rspageQ_1[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2724 = buf_rspageQ_1[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_1 = {_T_2733,_T_2730,_T_2727,_T_2724}; // @[Cat.scala 29:58] + wire _T_1976 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 387:65] + wire _T_1977 = ~_T_1976; // @[lsu_bus_buffer.scala 387:44] + wire _T_1979 = _T_1977 & _T_2711; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 514:63] + wire _T_2748 = buf_rspageQ_2[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2745 = buf_rspageQ_2[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2742 = buf_rspageQ_2[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2739 = buf_rspageQ_2[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_2 = {_T_2748,_T_2745,_T_2742,_T_2739}; // @[Cat.scala 29:58] + wire _T_1980 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 387:65] + wire _T_1981 = ~_T_1980; // @[lsu_bus_buffer.scala 387:44] + wire _T_1983 = _T_1981 & _T_2714; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 514:63] + wire _T_2763 = buf_rspageQ_3[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2760 = buf_rspageQ_3[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2757 = buf_rspageQ_3[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2754 = buf_rspageQ_3[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_3 = {_T_2763,_T_2760,_T_2757,_T_2754}; // @[Cat.scala 29:58] + wire _T_1984 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 387:65] + wire _T_1985 = ~_T_1984; // @[lsu_bus_buffer.scala 387:44] + wire _T_1987 = _T_1985 & _T_2717; // @[lsu_bus_buffer.scala 387:70] + wire [7:0] _T_2043 = {4'h0,_T_1987,_T_1983,_T_1979,_T_1975}; // @[Cat.scala 29:58] + wire _T_2046 = _T_2043[4] | _T_2043[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_2048 = _T_2046 | _T_2043[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2050 = _T_2048 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2053 = _T_2043[2] | _T_2043[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2055 = _T_2053 | _T_2043[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2057 = _T_2055 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2060 = _T_2043[1] | _T_2043[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2062 = _T_2060 | _T_2043[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2064 = _T_2062 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2066 = {_T_2050,_T_2057,_T_2064}; // @[Cat.scala 29:58] + wire _T_3535 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 445:77] + wire _T_3536 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 445:97] + wire _T_3537 = _T_3535 & _T_3536; // @[lsu_bus_buffer.scala 445:95] + wire _T_3538 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 445:112] + wire _T_3540 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 445:144] + wire _T_3541 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3542 = _T_3540 & _T_3541; // @[lsu_bus_buffer.scala 445:161] + wire _T_3543 = _T_3539 | _T_3542; // @[lsu_bus_buffer.scala 445:132] + wire _T_3544 = _T_853 & _T_3543; // @[lsu_bus_buffer.scala 445:63] + wire _T_3545 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3546 = ibuf_drain_vld & _T_3545; // @[lsu_bus_buffer.scala 445:201] + wire _T_3547 = _T_3544 | _T_3546; // @[lsu_bus_buffer.scala 445:183] + wire bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 572:39] + wire _T_3636 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 475:73] + wire _T_3637 = bus_rsp_write & _T_3636; // @[lsu_bus_buffer.scala 475:52] + reg _T_4302; // @[Reg.scala 27:20] + reg _T_4300; // @[Reg.scala 27:20] + reg _T_4298; // @[Reg.scala 27:20] + reg _T_4296; // @[Reg.scala 27:20] + wire [3:0] buf_ldfwd = {_T_4302,_T_4300,_T_4298,_T_4296}; // @[Cat.scala 29:58] + wire _T_3641 = buf_ldfwd[0] & _T_1349; // @[lsu_bus_buffer.scala 477:27] + wire _T_3642 = _T_1349 | _T_3641; // @[lsu_bus_buffer.scala 476:77] + wire _T_3643 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 478:26] + wire _T_3645 = ~buf_write[0]; // @[lsu_bus_buffer.scala 478:44] + wire _T_3646 = _T_3643 & _T_3645; // @[lsu_bus_buffer.scala 478:42] + wire _T_3647 = _T_3646 & buf_samedw_0; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_382 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 478:94] + wire _T_3648 = io_lsu_axi_r_bits_id == _GEN_382; // @[lsu_bus_buffer.scala 478:94] + wire _T_3649 = _T_3647 & _T_3648; // @[lsu_bus_buffer.scala 478:74] + wire _T_3650 = _T_3642 | _T_3649; // @[lsu_bus_buffer.scala 477:71] + wire _T_3651 = bus_rsp_read & _T_3650; // @[lsu_bus_buffer.scala 476:25] + wire _T_3652 = _T_3637 | _T_3651; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_52 = _T_3592 & _T_3652; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_3558 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_3554 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire [3:0] _T_3687 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 492:21] + wire _T_3690 = _T_3687[0] & _T_1349; // @[lsu_bus_buffer.scala 492:38] + wire _T_3691 = _T_3648 | _T_3690; // @[lsu_bus_buffer.scala 491:95] + wire _T_3692 = bus_rsp_read & _T_3691; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_46 = _T_3677 & _T_3692; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_3592 ? buf_resp_state_bus_en_0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_3558 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_77 = _T_3554 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire buf_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58] + wire _T_3571 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3572 = _T_3571 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire [1:0] RspPtr = _T_2066[1:0]; // @[lsu_bus_buffer.scala 399:10] + wire _T_3698 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 499:37] + wire _T_3699 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_3700 = buf_dual_0 & _T_3699; // @[lsu_bus_buffer.scala 499:80] + wire _T_3701 = _T_3698 | _T_3700; // @[lsu_bus_buffer.scala 499:65] + wire _T_3702 = _T_3701 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_41 = _T_3695 ? _T_3702 : _T_3703; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_3677 ? _T_3572 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_3592 ? _T_3572 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_3558 ? _T_3572 : _GEN_54; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_3554 ? obuf_rdrsp_pend_en : _GEN_64; // @[Conditional.scala 39:67] + wire buf_state_en_0 = _T_3531 ? _T_3547 : _GEN_74; // @[Conditional.scala 40:58] + wire _T_2068 = _T_1792 & buf_state_en_0; // @[lsu_bus_buffer.scala 411:94] + wire _T_2074 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 413:23] + wire _T_2076 = _T_2074 & _T_3535; // @[lsu_bus_buffer.scala 413:41] + wire _T_2078 = _T_2076 & _T_1795; // @[lsu_bus_buffer.scala 413:71] + wire _T_2080 = _T_2078 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2081 = _T_4466 | _T_2080; // @[lsu_bus_buffer.scala 412:86] + wire _T_2082 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 414:17] + wire _T_2083 = _T_2082 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 414:35] + wire _T_2085 = _T_2083 & _T_1796; // @[lsu_bus_buffer.scala 414:52] + wire _T_2087 = _T_2085 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2088 = _T_2081 | _T_2087; // @[lsu_bus_buffer.scala 413:114] + wire _T_2089 = _T_2068 & _T_2088; // @[lsu_bus_buffer.scala 411:113] + wire _T_2091 = _T_2089 | buf_age_0[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2105 = _T_2078 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2106 = _T_4471 | _T_2105; // @[lsu_bus_buffer.scala 412:86] + wire _T_2112 = _T_2085 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2113 = _T_2106 | _T_2112; // @[lsu_bus_buffer.scala 413:114] + wire _T_2114 = _T_2068 & _T_2113; // @[lsu_bus_buffer.scala 411:113] + wire _T_2116 = _T_2114 | buf_age_0[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2130 = _T_2078 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2131 = _T_4476 | _T_2130; // @[lsu_bus_buffer.scala 412:86] + wire _T_2137 = _T_2085 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2138 = _T_2131 | _T_2137; // @[lsu_bus_buffer.scala 413:114] + wire _T_2139 = _T_2068 & _T_2138; // @[lsu_bus_buffer.scala 411:113] + wire _T_2141 = _T_2139 | buf_age_0[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2155 = _T_2078 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2156 = _T_4481 | _T_2155; // @[lsu_bus_buffer.scala 412:86] + wire _T_2162 = _T_2085 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2163 = _T_2156 | _T_2162; // @[lsu_bus_buffer.scala 413:114] + wire _T_2164 = _T_2068 & _T_2163; // @[lsu_bus_buffer.scala 411:113] + wire _T_2166 = _T_2164 | buf_age_0[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2168 = {_T_2166,_T_2141,_T_2116}; // @[Cat.scala 29:58] + wire _T_3729 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3730 = _T_3537 & _T_3729; // @[lsu_bus_buffer.scala 445:112] + wire _T_3732 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3733 = _T_3540 & _T_3732; // @[lsu_bus_buffer.scala 445:161] + wire _T_3734 = _T_3730 | _T_3733; // @[lsu_bus_buffer.scala 445:132] + wire _T_3735 = _T_853 & _T_3734; // @[lsu_bus_buffer.scala 445:63] + wire _T_3736 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3737 = ibuf_drain_vld & _T_3736; // @[lsu_bus_buffer.scala 445:201] + wire _T_3738 = _T_3735 | _T_3737; // @[lsu_bus_buffer.scala 445:183] + wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 475:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 475:52] + wire _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 476:46] + wire _T_3832 = buf_ldfwd[1] & _T_1349; // @[lsu_bus_buffer.scala 477:27] + wire _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 476:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 478:26] + wire _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 478:44] + wire _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 478:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] + wire [2:0] _GEN_384 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 478:94] + wire _T_3839 = io_lsu_axi_r_bits_id == _GEN_384; // @[lsu_bus_buffer.scala 478:94] + wire _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 478:74] + wire _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 477:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 476:25] + wire _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_128 = _T_3783 & _T_3843; // @[Conditional.scala 39:67] + wire _GEN_148 = _T_3749 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] + wire _GEN_160 = _T_3745 ? 1'h0 : _GEN_148; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_160; // @[Conditional.scala 40:58] + wire [3:0] _T_3878 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 492:21] + wire _T_3881 = _T_3878[0] & _T_1349; // @[lsu_bus_buffer.scala 492:38] + wire _T_3882 = _T_3839 | _T_3881; // @[lsu_bus_buffer.scala 491:95] + wire _T_3883 = bus_rsp_read & _T_3882; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_122 = _T_3868 & _T_3883; // @[Conditional.scala 39:67] + wire _GEN_129 = _T_3783 ? buf_resp_state_bus_en_1 : _GEN_122; // @[Conditional.scala 39:67] + wire _GEN_139 = _T_3749 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] + wire _GEN_153 = _T_3745 ? 1'h0 : _GEN_139; // @[Conditional.scala 39:67] + wire buf_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_153; // @[Conditional.scala 40:58] + wire _T_3762 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3763 = _T_3762 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_3889 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 499:37] + wire _T_3890 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_3891 = buf_dual_1 & _T_3890; // @[lsu_bus_buffer.scala 499:80] + wire _T_3892 = _T_3889 | _T_3891; // @[lsu_bus_buffer.scala 499:65] + wire _T_3893 = _T_3892 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_117 = _T_3886 ? _T_3893 : _T_3894; // @[Conditional.scala 39:67] + wire _GEN_123 = _T_3868 ? _T_3763 : _GEN_117; // @[Conditional.scala 39:67] + wire _GEN_130 = _T_3783 ? _T_3763 : _GEN_123; // @[Conditional.scala 39:67] + wire _GEN_140 = _T_3749 ? _T_3763 : _GEN_130; // @[Conditional.scala 39:67] + wire _GEN_150 = _T_3745 ? obuf_rdrsp_pend_en : _GEN_140; // @[Conditional.scala 39:67] + wire buf_state_en_1 = _T_3722 ? _T_3738 : _GEN_150; // @[Conditional.scala 40:58] + wire _T_2170 = _T_1803 & buf_state_en_1; // @[lsu_bus_buffer.scala 411:94] + wire _T_2180 = _T_2076 & _T_1806; // @[lsu_bus_buffer.scala 413:71] + wire _T_2182 = _T_2180 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2183 = _T_4466 | _T_2182; // @[lsu_bus_buffer.scala 412:86] + wire _T_2187 = _T_2083 & _T_1807; // @[lsu_bus_buffer.scala 414:52] + wire _T_2189 = _T_2187 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2190 = _T_2183 | _T_2189; // @[lsu_bus_buffer.scala 413:114] + wire _T_2191 = _T_2170 & _T_2190; // @[lsu_bus_buffer.scala 411:113] + wire _T_2193 = _T_2191 | buf_age_1[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2207 = _T_2180 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2208 = _T_4471 | _T_2207; // @[lsu_bus_buffer.scala 412:86] + wire _T_2214 = _T_2187 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2215 = _T_2208 | _T_2214; // @[lsu_bus_buffer.scala 413:114] + wire _T_2216 = _T_2170 & _T_2215; // @[lsu_bus_buffer.scala 411:113] + wire _T_2218 = _T_2216 | buf_age_1[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2232 = _T_2180 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2233 = _T_4476 | _T_2232; // @[lsu_bus_buffer.scala 412:86] + wire _T_2239 = _T_2187 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2240 = _T_2233 | _T_2239; // @[lsu_bus_buffer.scala 413:114] + wire _T_2241 = _T_2170 & _T_2240; // @[lsu_bus_buffer.scala 411:113] + wire _T_2243 = _T_2241 | buf_age_1[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2257 = _T_2180 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2258 = _T_4481 | _T_2257; // @[lsu_bus_buffer.scala 412:86] + wire _T_2264 = _T_2187 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2265 = _T_2258 | _T_2264; // @[lsu_bus_buffer.scala 413:114] + wire _T_2266 = _T_2170 & _T_2265; // @[lsu_bus_buffer.scala 411:113] + wire _T_2268 = _T_2266 | buf_age_1[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2270 = {_T_2268,_T_2243,_T_2218}; // @[Cat.scala 29:58] + wire _T_3920 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3921 = _T_3537 & _T_3920; // @[lsu_bus_buffer.scala 445:112] + wire _T_3923 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3924 = _T_3540 & _T_3923; // @[lsu_bus_buffer.scala 445:161] + wire _T_3925 = _T_3921 | _T_3924; // @[lsu_bus_buffer.scala 445:132] + wire _T_3926 = _T_853 & _T_3925; // @[lsu_bus_buffer.scala 445:63] + wire _T_3927 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3928 = ibuf_drain_vld & _T_3927; // @[lsu_bus_buffer.scala 445:201] + wire _T_3929 = _T_3926 | _T_3928; // @[lsu_bus_buffer.scala 445:183] + wire _T_4018 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 475:73] + wire _T_4019 = bus_rsp_write & _T_4018; // @[lsu_bus_buffer.scala 475:52] + wire _T_4020 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 476:46] + wire _T_4023 = buf_ldfwd[2] & _T_1349; // @[lsu_bus_buffer.scala 477:27] + wire _T_4024 = _T_4020 | _T_4023; // @[lsu_bus_buffer.scala 476:77] + wire _T_4025 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 478:26] + wire _T_4027 = ~buf_write[2]; // @[lsu_bus_buffer.scala 478:44] + wire _T_4028 = _T_4025 & _T_4027; // @[lsu_bus_buffer.scala 478:42] + wire _T_4029 = _T_4028 & buf_samedw_2; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] + wire [2:0] _GEN_386 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 478:94] + wire _T_4030 = io_lsu_axi_r_bits_id == _GEN_386; // @[lsu_bus_buffer.scala 478:94] + wire _T_4031 = _T_4029 & _T_4030; // @[lsu_bus_buffer.scala 478:74] + wire _T_4032 = _T_4024 | _T_4031; // @[lsu_bus_buffer.scala 477:71] + wire _T_4033 = bus_rsp_read & _T_4032; // @[lsu_bus_buffer.scala 476:25] + wire _T_4034 = _T_4019 | _T_4033; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_204 = _T_3974 & _T_4034; // @[Conditional.scala 39:67] + wire _GEN_224 = _T_3940 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] + wire _GEN_236 = _T_3936 ? 1'h0 : _GEN_224; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_236; // @[Conditional.scala 40:58] + wire [3:0] _T_4069 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 492:21] + wire _T_4072 = _T_4069[0] & _T_1349; // @[lsu_bus_buffer.scala 492:38] + wire _T_4073 = _T_4030 | _T_4072; // @[lsu_bus_buffer.scala 491:95] + wire _T_4074 = bus_rsp_read & _T_4073; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_198 = _T_4059 & _T_4074; // @[Conditional.scala 39:67] + wire _GEN_205 = _T_3974 ? buf_resp_state_bus_en_2 : _GEN_198; // @[Conditional.scala 39:67] + wire _GEN_215 = _T_3940 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67] + wire _GEN_229 = _T_3936 ? 1'h0 : _GEN_215; // @[Conditional.scala 39:67] + wire buf_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_229; // @[Conditional.scala 40:58] + wire _T_3953 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3954 = _T_3953 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_4080 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 499:37] + wire _T_4081 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_4082 = buf_dual_2 & _T_4081; // @[lsu_bus_buffer.scala 499:80] + wire _T_4083 = _T_4080 | _T_4082; // @[lsu_bus_buffer.scala 499:65] + wire _T_4084 = _T_4083 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_193 = _T_4077 ? _T_4084 : _T_4085; // @[Conditional.scala 39:67] + wire _GEN_199 = _T_4059 ? _T_3954 : _GEN_193; // @[Conditional.scala 39:67] + wire _GEN_206 = _T_3974 ? _T_3954 : _GEN_199; // @[Conditional.scala 39:67] + wire _GEN_216 = _T_3940 ? _T_3954 : _GEN_206; // @[Conditional.scala 39:67] + wire _GEN_226 = _T_3936 ? obuf_rdrsp_pend_en : _GEN_216; // @[Conditional.scala 39:67] + wire buf_state_en_2 = _T_3913 ? _T_3929 : _GEN_226; // @[Conditional.scala 40:58] + wire _T_2272 = _T_1814 & buf_state_en_2; // @[lsu_bus_buffer.scala 411:94] + wire _T_2282 = _T_2076 & _T_1817; // @[lsu_bus_buffer.scala 413:71] + wire _T_2284 = _T_2282 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2285 = _T_4466 | _T_2284; // @[lsu_bus_buffer.scala 412:86] + wire _T_2289 = _T_2083 & _T_1818; // @[lsu_bus_buffer.scala 414:52] + wire _T_2291 = _T_2289 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2292 = _T_2285 | _T_2291; // @[lsu_bus_buffer.scala 413:114] + wire _T_2293 = _T_2272 & _T_2292; // @[lsu_bus_buffer.scala 411:113] + wire _T_2295 = _T_2293 | buf_age_2[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2309 = _T_2282 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2310 = _T_4471 | _T_2309; // @[lsu_bus_buffer.scala 412:86] + wire _T_2316 = _T_2289 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2317 = _T_2310 | _T_2316; // @[lsu_bus_buffer.scala 413:114] + wire _T_2318 = _T_2272 & _T_2317; // @[lsu_bus_buffer.scala 411:113] + wire _T_2320 = _T_2318 | buf_age_2[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2334 = _T_2282 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2335 = _T_4476 | _T_2334; // @[lsu_bus_buffer.scala 412:86] + wire _T_2341 = _T_2289 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2342 = _T_2335 | _T_2341; // @[lsu_bus_buffer.scala 413:114] + wire _T_2343 = _T_2272 & _T_2342; // @[lsu_bus_buffer.scala 411:113] + wire _T_2345 = _T_2343 | buf_age_2[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2359 = _T_2282 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2360 = _T_4481 | _T_2359; // @[lsu_bus_buffer.scala 412:86] + wire _T_2366 = _T_2289 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2367 = _T_2360 | _T_2366; // @[lsu_bus_buffer.scala 413:114] + wire _T_2368 = _T_2272 & _T_2367; // @[lsu_bus_buffer.scala 411:113] + wire _T_2370 = _T_2368 | buf_age_2[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2372 = {_T_2370,_T_2345,_T_2320}; // @[Cat.scala 29:58] + wire _T_4111 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_4112 = _T_3537 & _T_4111; // @[lsu_bus_buffer.scala 445:112] + wire _T_4114 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_4115 = _T_3540 & _T_4114; // @[lsu_bus_buffer.scala 445:161] + wire _T_4116 = _T_4112 | _T_4115; // @[lsu_bus_buffer.scala 445:132] + wire _T_4117 = _T_853 & _T_4116; // @[lsu_bus_buffer.scala 445:63] + wire _T_4118 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_4119 = ibuf_drain_vld & _T_4118; // @[lsu_bus_buffer.scala 445:201] + wire _T_4120 = _T_4117 | _T_4119; // @[lsu_bus_buffer.scala 445:183] + wire _T_4209 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 475:73] + wire _T_4210 = bus_rsp_write & _T_4209; // @[lsu_bus_buffer.scala 475:52] + wire _T_4211 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 476:46] + wire _T_4214 = buf_ldfwd[3] & _T_1349; // @[lsu_bus_buffer.scala 477:27] + wire _T_4215 = _T_4211 | _T_4214; // @[lsu_bus_buffer.scala 476:77] + wire _T_4216 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 478:26] + wire _T_4218 = ~buf_write[3]; // @[lsu_bus_buffer.scala 478:44] + wire _T_4219 = _T_4216 & _T_4218; // @[lsu_bus_buffer.scala 478:42] + wire _T_4220 = _T_4219 & buf_samedw_3; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] + wire [2:0] _GEN_388 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 478:94] + wire _T_4221 = io_lsu_axi_r_bits_id == _GEN_388; // @[lsu_bus_buffer.scala 478:94] + wire _T_4222 = _T_4220 & _T_4221; // @[lsu_bus_buffer.scala 478:74] + wire _T_4223 = _T_4215 | _T_4222; // @[lsu_bus_buffer.scala 477:71] + wire _T_4224 = bus_rsp_read & _T_4223; // @[lsu_bus_buffer.scala 476:25] + wire _T_4225 = _T_4210 | _T_4224; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_280 = _T_4165 & _T_4225; // @[Conditional.scala 39:67] + wire _GEN_300 = _T_4131 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] + wire _GEN_312 = _T_4127 ? 1'h0 : _GEN_300; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_312; // @[Conditional.scala 40:58] + wire [3:0] _T_4260 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 492:21] + wire _T_4263 = _T_4260[0] & _T_1349; // @[lsu_bus_buffer.scala 492:38] + wire _T_4264 = _T_4221 | _T_4263; // @[lsu_bus_buffer.scala 491:95] + wire _T_4265 = bus_rsp_read & _T_4264; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_274 = _T_4250 & _T_4265; // @[Conditional.scala 39:67] + wire _GEN_281 = _T_4165 ? buf_resp_state_bus_en_3 : _GEN_274; // @[Conditional.scala 39:67] + wire _GEN_291 = _T_4131 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67] + wire _GEN_305 = _T_4127 ? 1'h0 : _GEN_291; // @[Conditional.scala 39:67] + wire buf_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_305; // @[Conditional.scala 40:58] + wire _T_4144 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_4145 = _T_4144 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_4271 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 499:37] + wire _T_4272 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_4273 = buf_dual_3 & _T_4272; // @[lsu_bus_buffer.scala 499:80] + wire _T_4274 = _T_4271 | _T_4273; // @[lsu_bus_buffer.scala 499:65] + wire _T_4275 = _T_4274 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_269 = _T_4268 ? _T_4275 : _T_4276; // @[Conditional.scala 39:67] + wire _GEN_275 = _T_4250 ? _T_4145 : _GEN_269; // @[Conditional.scala 39:67] + wire _GEN_282 = _T_4165 ? _T_4145 : _GEN_275; // @[Conditional.scala 39:67] + wire _GEN_292 = _T_4131 ? _T_4145 : _GEN_282; // @[Conditional.scala 39:67] + wire _GEN_302 = _T_4127 ? obuf_rdrsp_pend_en : _GEN_292; // @[Conditional.scala 39:67] + wire buf_state_en_3 = _T_4104 ? _T_4120 : _GEN_302; // @[Conditional.scala 40:58] + wire _T_2374 = _T_1825 & buf_state_en_3; // @[lsu_bus_buffer.scala 411:94] + wire _T_2384 = _T_2076 & _T_1828; // @[lsu_bus_buffer.scala 413:71] + wire _T_2386 = _T_2384 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2387 = _T_4466 | _T_2386; // @[lsu_bus_buffer.scala 412:86] + wire _T_2391 = _T_2083 & _T_1829; // @[lsu_bus_buffer.scala 414:52] + wire _T_2393 = _T_2391 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2394 = _T_2387 | _T_2393; // @[lsu_bus_buffer.scala 413:114] + wire _T_2395 = _T_2374 & _T_2394; // @[lsu_bus_buffer.scala 411:113] + wire _T_2397 = _T_2395 | buf_age_3[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2411 = _T_2384 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2412 = _T_4471 | _T_2411; // @[lsu_bus_buffer.scala 412:86] + wire _T_2418 = _T_2391 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2419 = _T_2412 | _T_2418; // @[lsu_bus_buffer.scala 413:114] + wire _T_2420 = _T_2374 & _T_2419; // @[lsu_bus_buffer.scala 411:113] + wire _T_2422 = _T_2420 | buf_age_3[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2436 = _T_2384 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2437 = _T_4476 | _T_2436; // @[lsu_bus_buffer.scala 412:86] + wire _T_2443 = _T_2391 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2444 = _T_2437 | _T_2443; // @[lsu_bus_buffer.scala 413:114] + wire _T_2445 = _T_2374 & _T_2444; // @[lsu_bus_buffer.scala 411:113] + wire _T_2447 = _T_2445 | buf_age_3[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2461 = _T_2384 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2462 = _T_4481 | _T_2461; // @[lsu_bus_buffer.scala 412:86] + wire _T_2468 = _T_2391 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2469 = _T_2462 | _T_2468; // @[lsu_bus_buffer.scala 413:114] + wire _T_2470 = _T_2374 & _T_2469; // @[lsu_bus_buffer.scala 411:113] + wire _T_2472 = _T_2470 | buf_age_3[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2474 = {_T_2472,_T_2447,_T_2422}; // @[Cat.scala 29:58] + wire _T_2770 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2771 = _T_1792 | _T_2770; // @[lsu_bus_buffer.scala 422:32] + wire _T_2772 = ~_T_2771; // @[lsu_bus_buffer.scala 422:6] + wire _T_2780 = _T_2772 | _T_2080; // @[lsu_bus_buffer.scala 422:59] + wire _T_2787 = _T_2780 | _T_2087; // @[lsu_bus_buffer.scala 423:110] + wire _T_2788 = _T_2068 & _T_2787; // @[lsu_bus_buffer.scala 421:112] + wire _T_2792 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2793 = _T_1803 | _T_2792; // @[lsu_bus_buffer.scala 422:32] + wire _T_2794 = ~_T_2793; // @[lsu_bus_buffer.scala 422:6] + wire _T_2802 = _T_2794 | _T_2105; // @[lsu_bus_buffer.scala 422:59] + wire _T_2809 = _T_2802 | _T_2112; // @[lsu_bus_buffer.scala 423:110] + wire _T_2810 = _T_2068 & _T_2809; // @[lsu_bus_buffer.scala 421:112] + wire _T_2814 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2815 = _T_1814 | _T_2814; // @[lsu_bus_buffer.scala 422:32] + wire _T_2816 = ~_T_2815; // @[lsu_bus_buffer.scala 422:6] + wire _T_2824 = _T_2816 | _T_2130; // @[lsu_bus_buffer.scala 422:59] + wire _T_2831 = _T_2824 | _T_2137; // @[lsu_bus_buffer.scala 423:110] + wire _T_2832 = _T_2068 & _T_2831; // @[lsu_bus_buffer.scala 421:112] + wire _T_2836 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2837 = _T_1825 | _T_2836; // @[lsu_bus_buffer.scala 422:32] + wire _T_2838 = ~_T_2837; // @[lsu_bus_buffer.scala 422:6] + wire _T_2846 = _T_2838 | _T_2155; // @[lsu_bus_buffer.scala 422:59] + wire _T_2853 = _T_2846 | _T_2162; // @[lsu_bus_buffer.scala 423:110] + wire _T_2854 = _T_2068 & _T_2853; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_0 = {_T_2854,_T_2832,_T_2810,_T_2788}; // @[Cat.scala 29:58] + wire _T_2871 = _T_2772 | _T_2182; // @[lsu_bus_buffer.scala 422:59] + wire _T_2878 = _T_2871 | _T_2189; // @[lsu_bus_buffer.scala 423:110] + wire _T_2879 = _T_2170 & _T_2878; // @[lsu_bus_buffer.scala 421:112] + wire _T_2893 = _T_2794 | _T_2207; // @[lsu_bus_buffer.scala 422:59] + wire _T_2900 = _T_2893 | _T_2214; // @[lsu_bus_buffer.scala 423:110] + wire _T_2901 = _T_2170 & _T_2900; // @[lsu_bus_buffer.scala 421:112] + wire _T_2915 = _T_2816 | _T_2232; // @[lsu_bus_buffer.scala 422:59] + wire _T_2922 = _T_2915 | _T_2239; // @[lsu_bus_buffer.scala 423:110] + wire _T_2923 = _T_2170 & _T_2922; // @[lsu_bus_buffer.scala 421:112] + wire _T_2937 = _T_2838 | _T_2257; // @[lsu_bus_buffer.scala 422:59] + wire _T_2944 = _T_2937 | _T_2264; // @[lsu_bus_buffer.scala 423:110] + wire _T_2945 = _T_2170 & _T_2944; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_1 = {_T_2945,_T_2923,_T_2901,_T_2879}; // @[Cat.scala 29:58] + wire _T_2962 = _T_2772 | _T_2284; // @[lsu_bus_buffer.scala 422:59] + wire _T_2969 = _T_2962 | _T_2291; // @[lsu_bus_buffer.scala 423:110] + wire _T_2970 = _T_2272 & _T_2969; // @[lsu_bus_buffer.scala 421:112] + wire _T_2984 = _T_2794 | _T_2309; // @[lsu_bus_buffer.scala 422:59] + wire _T_2991 = _T_2984 | _T_2316; // @[lsu_bus_buffer.scala 423:110] + wire _T_2992 = _T_2272 & _T_2991; // @[lsu_bus_buffer.scala 421:112] + wire _T_3006 = _T_2816 | _T_2334; // @[lsu_bus_buffer.scala 422:59] + wire _T_3013 = _T_3006 | _T_2341; // @[lsu_bus_buffer.scala 423:110] + wire _T_3014 = _T_2272 & _T_3013; // @[lsu_bus_buffer.scala 421:112] + wire _T_3028 = _T_2838 | _T_2359; // @[lsu_bus_buffer.scala 422:59] + wire _T_3035 = _T_3028 | _T_2366; // @[lsu_bus_buffer.scala 423:110] + wire _T_3036 = _T_2272 & _T_3035; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_2 = {_T_3036,_T_3014,_T_2992,_T_2970}; // @[Cat.scala 29:58] + wire _T_3053 = _T_2772 | _T_2386; // @[lsu_bus_buffer.scala 422:59] + wire _T_3060 = _T_3053 | _T_2393; // @[lsu_bus_buffer.scala 423:110] + wire _T_3061 = _T_2374 & _T_3060; // @[lsu_bus_buffer.scala 421:112] + wire _T_3075 = _T_2794 | _T_2411; // @[lsu_bus_buffer.scala 422:59] + wire _T_3082 = _T_3075 | _T_2418; // @[lsu_bus_buffer.scala 423:110] + wire _T_3083 = _T_2374 & _T_3082; // @[lsu_bus_buffer.scala 421:112] + wire _T_3097 = _T_2816 | _T_2436; // @[lsu_bus_buffer.scala 422:59] + wire _T_3104 = _T_3097 | _T_2443; // @[lsu_bus_buffer.scala 423:110] + wire _T_3105 = _T_2374 & _T_3104; // @[lsu_bus_buffer.scala 421:112] + wire _T_3119 = _T_2838 | _T_2461; // @[lsu_bus_buffer.scala 422:59] + wire _T_3126 = _T_3119 | _T_2468; // @[lsu_bus_buffer.scala 423:110] + wire _T_3127 = _T_2374 & _T_3126; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_3 = {_T_3127,_T_3105,_T_3083,_T_3061}; // @[Cat.scala 29:58] + wire _T_3218 = _T_2836 | _T_1825; // @[lsu_bus_buffer.scala 426:110] + wire _T_3219 = ~_T_3218; // @[lsu_bus_buffer.scala 426:84] + wire _T_3220 = buf_rspageQ_0[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3222 = _T_3220 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3210 = _T_2814 | _T_1814; // @[lsu_bus_buffer.scala 426:110] + wire _T_3211 = ~_T_3210; // @[lsu_bus_buffer.scala 426:84] + wire _T_3212 = buf_rspageQ_0[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3214 = _T_3212 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3202 = _T_2792 | _T_1803; // @[lsu_bus_buffer.scala 426:110] + wire _T_3203 = ~_T_3202; // @[lsu_bus_buffer.scala 426:84] + wire _T_3204 = buf_rspageQ_0[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3206 = _T_3204 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3194 = _T_2770 | _T_1792; // @[lsu_bus_buffer.scala 426:110] + wire _T_3195 = ~_T_3194; // @[lsu_bus_buffer.scala 426:84] + wire _T_3196 = buf_rspageQ_0[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3198 = _T_3196 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_0 = {_T_3222,_T_3214,_T_3206,_T_3198}; // @[Cat.scala 29:58] + wire _T_3133 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3136 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3139 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3142 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3144 = {_T_3142,_T_3139,_T_3136}; // @[Cat.scala 29:58] + wire _T_3255 = buf_rspageQ_1[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3257 = _T_3255 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3247 = buf_rspageQ_1[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3249 = _T_3247 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3239 = buf_rspageQ_1[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3241 = _T_3239 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3231 = buf_rspageQ_1[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3233 = _T_3231 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_1 = {_T_3257,_T_3249,_T_3241,_T_3233}; // @[Cat.scala 29:58] + wire _T_3148 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3151 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3154 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3157 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3159 = {_T_3157,_T_3154,_T_3151}; // @[Cat.scala 29:58] + wire _T_3290 = buf_rspageQ_2[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3292 = _T_3290 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3282 = buf_rspageQ_2[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3284 = _T_3282 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3274 = buf_rspageQ_2[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3276 = _T_3274 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3266 = buf_rspageQ_2[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3268 = _T_3266 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_2 = {_T_3292,_T_3284,_T_3276,_T_3268}; // @[Cat.scala 29:58] + wire _T_3163 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3166 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3169 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3172 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3174 = {_T_3172,_T_3169,_T_3166}; // @[Cat.scala 29:58] + wire _T_3325 = buf_rspageQ_3[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3327 = _T_3325 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3317 = buf_rspageQ_3[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3319 = _T_3317 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3309 = buf_rspageQ_3[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3311 = _T_3309 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3301 = buf_rspageQ_3[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3303 = _T_3301 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_3 = {_T_3327,_T_3319,_T_3311,_T_3303}; // @[Cat.scala 29:58] + wire _T_3178 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3181 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3184 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3187 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3189 = {_T_3187,_T_3184,_T_3181}; // @[Cat.scala 29:58] + wire _T_3332 = ibuf_drain_vld & _T_1793; // @[lsu_bus_buffer.scala 427:63] + wire _T_3334 = ibuf_drain_vld & _T_1804; // @[lsu_bus_buffer.scala 427:63] + wire _T_3336 = ibuf_drain_vld & _T_1815; // @[lsu_bus_buffer.scala 427:63] + wire _T_3338 = ibuf_drain_vld & _T_1826; // @[lsu_bus_buffer.scala 427:63] + wire [3:0] ibuf_drainvec_vld = {_T_3338,_T_3336,_T_3334,_T_3332}; // @[Cat.scala 29:58] + wire _T_3346 = _T_3540 & _T_1796; // @[lsu_bus_buffer.scala 429:35] + wire _T_3355 = _T_3540 & _T_1807; // @[lsu_bus_buffer.scala 429:35] + wire _T_3364 = _T_3540 & _T_1818; // @[lsu_bus_buffer.scala 429:35] + wire _T_3373 = _T_3540 & _T_1829; // @[lsu_bus_buffer.scala 429:35] + wire _T_3403 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3405 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3407 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3409 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire [3:0] buf_dual_in = {_T_3409,_T_3407,_T_3405,_T_3403}; // @[Cat.scala 29:58] + wire _T_3414 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3416 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3418 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3420 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire [3:0] buf_samedw_in = {_T_3420,_T_3418,_T_3416,_T_3414}; // @[Cat.scala 29:58] + wire _T_3425 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 433:84] + wire _T_3426 = ibuf_drainvec_vld[0] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3429 = ibuf_drainvec_vld[1] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3432 = ibuf_drainvec_vld[2] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3435 = ibuf_drainvec_vld[3] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire [3:0] buf_nomerge_in = {_T_3435,_T_3432,_T_3429,_T_3426}; // @[Cat.scala 29:58] + wire _T_3443 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3346; // @[lsu_bus_buffer.scala 434:47] + wire _T_3448 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3355; // @[lsu_bus_buffer.scala 434:47] + wire _T_3453 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3364; // @[lsu_bus_buffer.scala 434:47] + wire _T_3458 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3373; // @[lsu_bus_buffer.scala 434:47] + wire [3:0] buf_dualhi_in = {_T_3458,_T_3453,_T_3448,_T_3443}; // @[Cat.scala 29:58] + wire _T_3487 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3489 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3491 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3493 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire [3:0] buf_sideeffect_in = {_T_3493,_T_3491,_T_3489,_T_3487}; // @[Cat.scala 29:58] + wire _T_3498 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3500 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3502 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3504 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire [3:0] buf_unsign_in = {_T_3504,_T_3502,_T_3500,_T_3498}; // @[Cat.scala 29:58] + wire _T_3521 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3523 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3525 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3527 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire [3:0] buf_write_in = {_T_3527,_T_3525,_T_3523,_T_3521}; // @[Cat.scala 29:58] + wire _T_3560 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 459:89] + wire _T_3562 = _T_3560 & _T_1349; // @[lsu_bus_buffer.scala 459:104] + wire _T_3575 = buf_state_en_0 & _T_3645; // @[lsu_bus_buffer.scala 464:44] + wire _T_3576 = _T_3575 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3578 = _T_3576 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3581 = _T_3571 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3582 = _T_3581 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_4841 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 576:64] + wire bus_rsp_read_error = bus_rsp_read & _T_4841; // @[lsu_bus_buffer.scala 576:38] + wire _T_3585 = _T_3581 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_3659 = bus_rsp_read_error & _T_1349; // @[lsu_bus_buffer.scala 482:91] + wire _T_3661 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 483:31] + wire _T_3663 = _T_3661 & _T_1349; // @[lsu_bus_buffer.scala 483:46] + wire _T_3664 = _T_3659 | _T_3663; // @[lsu_bus_buffer.scala 482:143] + wire _T_4839 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 575:66] + wire bus_rsp_write_error = bus_rsp_write & _T_4839; // @[lsu_bus_buffer.scala 575:40] + wire _T_3666 = bus_rsp_write_error & _T_3636; // @[lsu_bus_buffer.scala 484:33] + wire _T_3667 = _T_3664 | _T_3666; // @[lsu_bus_buffer.scala 483:88] + wire _T_3668 = _T_3571 & _T_3667; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_56 = _T_3592 & _T_3668; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_3558 ? _T_3585 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_82 = _T_3554 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_error_en_0 = _T_3531 ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58] + wire _T_3594 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 472:75] + wire _T_3595 = buf_write[0] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3596 = io_dec_tlu_force_halt | _T_3595; // @[lsu_bus_buffer.scala 472:57] + wire _T_3598 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 473:30] + wire _T_3599 = buf_dual_0 & _T_3598; // @[lsu_bus_buffer.scala 473:28] + wire _T_3602 = _T_3599 & _T_3645; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_29 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_30 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_29; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_31 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_30; // @[lsu_bus_buffer.scala 473:90] + wire _T_3603 = _GEN_31 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3604 = _T_3602 & _T_3603; // @[lsu_bus_buffer.scala 473:61] + wire _T_4489 = _T_2717 | _T_2714; // @[lsu_bus_buffer.scala 536:93] + wire _T_4490 = _T_4489 | _T_2711; // @[lsu_bus_buffer.scala 536:93] + wire any_done_wait_state = _T_4490 | _T_2708; // @[lsu_bus_buffer.scala 536:93] + wire _T_3606 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3612 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3614 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3616 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_3618 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_3620 = _T_3612 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3621 = _T_3614 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3622 = _T_3616 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3623 = _T_3618 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3624 = _T_3620 | _T_3621; // @[Mux.scala 27:72] + wire _T_3625 = _T_3624 | _T_3622; // @[Mux.scala 27:72] + wire _T_3626 = _T_3625 | _T_3623; // @[Mux.scala 27:72] + wire _T_3628 = _T_3602 & _T_3626; // @[lsu_bus_buffer.scala 474:101] + wire _T_3629 = _GEN_31 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_3630 = _T_3628 & _T_3629; // @[lsu_bus_buffer.scala 474:138] + wire _T_3631 = _T_3630 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_3632 = _T_3606 | _T_3631; // @[lsu_bus_buffer.scala 474:53] + wire _T_3655 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_3656 = _T_3655 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_3669 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 485:50] + wire _T_3670 = buf_state_en_0 & _T_3669; // @[lsu_bus_buffer.scala 485:48] + wire _T_3682 = buf_ldfwd[0] | _T_3687[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_3683 = _T_3682 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_39 = _T_3703 ? buf_state_en_0 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_3695 ? io_dec_tlu_force_halt : _T_3703; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_3695 ? io_dec_tlu_force_halt : _GEN_39; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_3677 ? io_dec_tlu_force_halt : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_3677 ? io_dec_tlu_force_halt : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_3592 & _T_3656; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_3592 ? io_dec_tlu_force_halt : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_3592 ? io_dec_tlu_force_halt : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_3558 ? _T_3578 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_3558 ? _T_3582 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_3558 ? io_dec_tlu_force_halt : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_3554 ? io_dec_tlu_force_halt : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_3554 ? io_dec_tlu_force_halt : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_3554 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67] + wire buf_wr_en_0 = _T_3531 & buf_state_en_0; // @[Conditional.scala 40:58] + wire buf_data_en_0 = _T_3531 ? buf_state_en_0 : _GEN_81; // @[Conditional.scala 40:58] + wire buf_rst_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_76; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_79; // @[Conditional.scala 40:58] + wire _T_3766 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 464:44] + wire _T_3767 = _T_3766 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3769 = _T_3767 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3772 = _T_3762 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3773 = _T_3772 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_3776 = _T_3772 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 482:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 483:31] + wire _T_3854 = _T_3852 & _T_1349; // @[lsu_bus_buffer.scala 483:46] + wire _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 482:143] + wire _T_3857 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 484:33] + wire _T_3858 = _T_3855 | _T_3857; // @[lsu_bus_buffer.scala 483:88] + wire _T_3859 = _T_3762 & _T_3858; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_132 = _T_3783 & _T_3859; // @[Conditional.scala 39:67] + wire _GEN_145 = _T_3749 ? _T_3776 : _GEN_132; // @[Conditional.scala 39:67] + wire _GEN_158 = _T_3745 ? 1'h0 : _GEN_145; // @[Conditional.scala 39:67] + wire buf_error_en_1 = _T_3722 ? 1'h0 : _GEN_158; // @[Conditional.scala 40:58] + wire _T_3786 = buf_write[1] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 472:57] + wire _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 473:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 473:28] + wire _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_105 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_106 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_105; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_107 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_106; // @[lsu_bus_buffer.scala 473:90] + wire _T_3794 = _GEN_107 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 473:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_3809 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] + wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] + wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] + wire _T_3819 = _T_3793 & _T_3817; // @[lsu_bus_buffer.scala 474:101] + wire _T_3820 = _GEN_107 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 474:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 474:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_3860 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 485:50] + wire _T_3861 = buf_state_en_1 & _T_3860; // @[lsu_bus_buffer.scala 485:48] + wire _T_3873 = buf_ldfwd[1] | _T_3878[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_3874 = _T_3873 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_115 = _T_3894 ? buf_state_en_1 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_119 = _T_3886 ? io_dec_tlu_force_halt : _T_3894; // @[Conditional.scala 39:67] + wire _GEN_120 = _T_3886 ? io_dec_tlu_force_halt : _GEN_115; // @[Conditional.scala 39:67] + wire _GEN_125 = _T_3868 ? io_dec_tlu_force_halt : _GEN_119; // @[Conditional.scala 39:67] + wire _GEN_126 = _T_3868 ? io_dec_tlu_force_halt : _GEN_120; // @[Conditional.scala 39:67] + wire _GEN_131 = _T_3783 & _T_3847; // @[Conditional.scala 39:67] + wire _GEN_135 = _T_3783 ? io_dec_tlu_force_halt : _GEN_125; // @[Conditional.scala 39:67] + wire _GEN_136 = _T_3783 ? io_dec_tlu_force_halt : _GEN_126; // @[Conditional.scala 39:67] + wire _GEN_142 = _T_3749 ? _T_3769 : _GEN_136; // @[Conditional.scala 39:67] + wire _GEN_144 = _T_3749 ? _T_3773 : _GEN_131; // @[Conditional.scala 39:67] + wire _GEN_147 = _T_3749 ? io_dec_tlu_force_halt : _GEN_135; // @[Conditional.scala 39:67] + wire _GEN_152 = _T_3745 ? io_dec_tlu_force_halt : _GEN_147; // @[Conditional.scala 39:67] + wire _GEN_155 = _T_3745 ? io_dec_tlu_force_halt : _GEN_142; // @[Conditional.scala 39:67] + wire _GEN_157 = _T_3745 ? 1'h0 : _GEN_144; // @[Conditional.scala 39:67] + wire buf_wr_en_1 = _T_3722 & buf_state_en_1; // @[Conditional.scala 40:58] + wire buf_data_en_1 = _T_3722 ? buf_state_en_1 : _GEN_157; // @[Conditional.scala 40:58] + wire buf_rst_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_152; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_155; // @[Conditional.scala 40:58] + wire _T_3957 = buf_state_en_2 & _T_4027; // @[lsu_bus_buffer.scala 464:44] + wire _T_3958 = _T_3957 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3960 = _T_3958 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3963 = _T_3953 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3964 = _T_3963 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_3967 = _T_3963 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_4041 = bus_rsp_read_error & _T_4020; // @[lsu_bus_buffer.scala 482:91] + wire _T_4043 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 483:31] + wire _T_4045 = _T_4043 & _T_1349; // @[lsu_bus_buffer.scala 483:46] + wire _T_4046 = _T_4041 | _T_4045; // @[lsu_bus_buffer.scala 482:143] + wire _T_4048 = bus_rsp_write_error & _T_4018; // @[lsu_bus_buffer.scala 484:33] + wire _T_4049 = _T_4046 | _T_4048; // @[lsu_bus_buffer.scala 483:88] + wire _T_4050 = _T_3953 & _T_4049; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_208 = _T_3974 & _T_4050; // @[Conditional.scala 39:67] + wire _GEN_221 = _T_3940 ? _T_3967 : _GEN_208; // @[Conditional.scala 39:67] + wire _GEN_234 = _T_3936 ? 1'h0 : _GEN_221; // @[Conditional.scala 39:67] + wire buf_error_en_2 = _T_3913 ? 1'h0 : _GEN_234; // @[Conditional.scala 40:58] + wire _T_3977 = buf_write[2] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3978 = io_dec_tlu_force_halt | _T_3977; // @[lsu_bus_buffer.scala 472:57] + wire _T_3980 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 473:30] + wire _T_3981 = buf_dual_2 & _T_3980; // @[lsu_bus_buffer.scala 473:28] + wire _T_3984 = _T_3981 & _T_4027; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_181 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_182 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_181; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_183 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_182; // @[lsu_bus_buffer.scala 473:90] + wire _T_3985 = _GEN_183 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3986 = _T_3984 & _T_3985; // @[lsu_bus_buffer.scala 473:61] + wire _T_3988 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3994 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3996 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3998 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_4000 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_4002 = _T_3994 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4003 = _T_3996 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4004 = _T_3998 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4005 = _T_4000 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4006 = _T_4002 | _T_4003; // @[Mux.scala 27:72] + wire _T_4007 = _T_4006 | _T_4004; // @[Mux.scala 27:72] + wire _T_4008 = _T_4007 | _T_4005; // @[Mux.scala 27:72] + wire _T_4010 = _T_3984 & _T_4008; // @[lsu_bus_buffer.scala 474:101] + wire _T_4011 = _GEN_183 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_4012 = _T_4010 & _T_4011; // @[lsu_bus_buffer.scala 474:138] + wire _T_4013 = _T_4012 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_4014 = _T_3988 | _T_4013; // @[lsu_bus_buffer.scala 474:53] + wire _T_4037 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_4038 = _T_4037 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_4051 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 485:50] + wire _T_4052 = buf_state_en_2 & _T_4051; // @[lsu_bus_buffer.scala 485:48] + wire _T_4064 = buf_ldfwd[2] | _T_4069[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_4065 = _T_4064 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_191 = _T_4085 ? buf_state_en_2 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_195 = _T_4077 ? io_dec_tlu_force_halt : _T_4085; // @[Conditional.scala 39:67] + wire _GEN_196 = _T_4077 ? io_dec_tlu_force_halt : _GEN_191; // @[Conditional.scala 39:67] + wire _GEN_201 = _T_4059 ? io_dec_tlu_force_halt : _GEN_195; // @[Conditional.scala 39:67] + wire _GEN_202 = _T_4059 ? io_dec_tlu_force_halt : _GEN_196; // @[Conditional.scala 39:67] + wire _GEN_207 = _T_3974 & _T_4038; // @[Conditional.scala 39:67] + wire _GEN_211 = _T_3974 ? io_dec_tlu_force_halt : _GEN_201; // @[Conditional.scala 39:67] + wire _GEN_212 = _T_3974 ? io_dec_tlu_force_halt : _GEN_202; // @[Conditional.scala 39:67] + wire _GEN_218 = _T_3940 ? _T_3960 : _GEN_212; // @[Conditional.scala 39:67] + wire _GEN_220 = _T_3940 ? _T_3964 : _GEN_207; // @[Conditional.scala 39:67] + wire _GEN_223 = _T_3940 ? io_dec_tlu_force_halt : _GEN_211; // @[Conditional.scala 39:67] + wire _GEN_228 = _T_3936 ? io_dec_tlu_force_halt : _GEN_223; // @[Conditional.scala 39:67] + wire _GEN_231 = _T_3936 ? io_dec_tlu_force_halt : _GEN_218; // @[Conditional.scala 39:67] + wire _GEN_233 = _T_3936 ? 1'h0 : _GEN_220; // @[Conditional.scala 39:67] + wire buf_wr_en_2 = _T_3913 & buf_state_en_2; // @[Conditional.scala 40:58] + wire buf_data_en_2 = _T_3913 ? buf_state_en_2 : _GEN_233; // @[Conditional.scala 40:58] + wire buf_rst_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_228; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_231; // @[Conditional.scala 40:58] + wire _T_4148 = buf_state_en_3 & _T_4218; // @[lsu_bus_buffer.scala 464:44] + wire _T_4149 = _T_4148 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_4151 = _T_4149 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_4154 = _T_4144 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_4155 = _T_4154 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_4158 = _T_4154 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_4232 = bus_rsp_read_error & _T_4211; // @[lsu_bus_buffer.scala 482:91] + wire _T_4234 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 483:31] + wire _T_4236 = _T_4234 & _T_1349; // @[lsu_bus_buffer.scala 483:46] + wire _T_4237 = _T_4232 | _T_4236; // @[lsu_bus_buffer.scala 482:143] + wire _T_4239 = bus_rsp_write_error & _T_4209; // @[lsu_bus_buffer.scala 484:33] + wire _T_4240 = _T_4237 | _T_4239; // @[lsu_bus_buffer.scala 483:88] + wire _T_4241 = _T_4144 & _T_4240; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_284 = _T_4165 & _T_4241; // @[Conditional.scala 39:67] + wire _GEN_297 = _T_4131 ? _T_4158 : _GEN_284; // @[Conditional.scala 39:67] + wire _GEN_310 = _T_4127 ? 1'h0 : _GEN_297; // @[Conditional.scala 39:67] + wire buf_error_en_3 = _T_4104 ? 1'h0 : _GEN_310; // @[Conditional.scala 40:58] + wire _T_4168 = buf_write[3] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_4169 = io_dec_tlu_force_halt | _T_4168; // @[lsu_bus_buffer.scala 472:57] + wire _T_4171 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 473:30] + wire _T_4172 = buf_dual_3 & _T_4171; // @[lsu_bus_buffer.scala 473:28] + wire _T_4175 = _T_4172 & _T_4218; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_257 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_258 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_257; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_259 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_258; // @[lsu_bus_buffer.scala 473:90] + wire _T_4176 = _GEN_259 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_4177 = _T_4175 & _T_4176; // @[lsu_bus_buffer.scala 473:61] + wire _T_4179 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_4185 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_4187 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_4189 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_4191 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_4193 = _T_4185 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4194 = _T_4187 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4195 = _T_4189 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4196 = _T_4191 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4197 = _T_4193 | _T_4194; // @[Mux.scala 27:72] + wire _T_4198 = _T_4197 | _T_4195; // @[Mux.scala 27:72] + wire _T_4199 = _T_4198 | _T_4196; // @[Mux.scala 27:72] + wire _T_4201 = _T_4175 & _T_4199; // @[lsu_bus_buffer.scala 474:101] + wire _T_4202 = _GEN_259 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_4203 = _T_4201 & _T_4202; // @[lsu_bus_buffer.scala 474:138] + wire _T_4204 = _T_4203 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_4205 = _T_4179 | _T_4204; // @[lsu_bus_buffer.scala 474:53] + wire _T_4228 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_4229 = _T_4228 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_4242 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 485:50] + wire _T_4243 = buf_state_en_3 & _T_4242; // @[lsu_bus_buffer.scala 485:48] + wire _T_4255 = buf_ldfwd[3] | _T_4260[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_4256 = _T_4255 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_267 = _T_4276 ? buf_state_en_3 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_271 = _T_4268 ? io_dec_tlu_force_halt : _T_4276; // @[Conditional.scala 39:67] + wire _GEN_272 = _T_4268 ? io_dec_tlu_force_halt : _GEN_267; // @[Conditional.scala 39:67] + wire _GEN_277 = _T_4250 ? io_dec_tlu_force_halt : _GEN_271; // @[Conditional.scala 39:67] + wire _GEN_278 = _T_4250 ? io_dec_tlu_force_halt : _GEN_272; // @[Conditional.scala 39:67] + wire _GEN_283 = _T_4165 & _T_4229; // @[Conditional.scala 39:67] + wire _GEN_287 = _T_4165 ? io_dec_tlu_force_halt : _GEN_277; // @[Conditional.scala 39:67] + wire _GEN_288 = _T_4165 ? io_dec_tlu_force_halt : _GEN_278; // @[Conditional.scala 39:67] + wire _GEN_294 = _T_4131 ? _T_4151 : _GEN_288; // @[Conditional.scala 39:67] + wire _GEN_296 = _T_4131 ? _T_4155 : _GEN_283; // @[Conditional.scala 39:67] + wire _GEN_299 = _T_4131 ? io_dec_tlu_force_halt : _GEN_287; // @[Conditional.scala 39:67] + wire _GEN_304 = _T_4127 ? io_dec_tlu_force_halt : _GEN_299; // @[Conditional.scala 39:67] + wire _GEN_307 = _T_4127 ? io_dec_tlu_force_halt : _GEN_294; // @[Conditional.scala 39:67] + wire _GEN_309 = _T_4127 ? 1'h0 : _GEN_296; // @[Conditional.scala 39:67] + wire buf_wr_en_3 = _T_4104 & buf_state_en_3; // @[Conditional.scala 40:58] + wire buf_data_en_3 = _T_4104 ? buf_state_en_3 : _GEN_309; // @[Conditional.scala 40:58] + wire buf_rst_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_304; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_307; // @[Conditional.scala 40:58] + reg _T_4331; // @[Reg.scala 27:20] + reg _T_4334; // @[Reg.scala 27:20] + reg _T_4337; // @[Reg.scala 27:20] + reg _T_4340; // @[Reg.scala 27:20] + wire [3:0] buf_unsign = {_T_4340,_T_4337,_T_4334,_T_4331}; // @[Cat.scala 29:58] + wire _T_4387 = ~buf_rst_0; // @[lsu_bus_buffer.scala 531:81] + reg _T_4406; // @[lsu_bus_buffer.scala 531:80] + reg _T_4401; // @[lsu_bus_buffer.scala 531:80] + reg _T_4396; // @[lsu_bus_buffer.scala 531:80] + reg _T_4391; // @[lsu_bus_buffer.scala 531:80] + wire [3:0] buf_error = {_T_4406,_T_4401,_T_4396,_T_4391}; // @[Cat.scala 29:58] + wire _T_4389 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4392 = ~buf_rst_1; // @[lsu_bus_buffer.scala 531:81] + wire _T_4394 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4397 = ~buf_rst_2; // @[lsu_bus_buffer.scala 531:81] + wire _T_4399 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4402 = ~buf_rst_3; // @[lsu_bus_buffer.scala 531:81] + wire _T_4404 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 531:98] + wire [1:0] _T_4410 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4411 = io_ldst_dual_m ? _T_4410 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 532:28] + wire [1:0] _T_4412 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4413 = io_ldst_dual_r ? _T_4412 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 532:94] + wire [2:0] _T_4414 = _T_4411 + _T_4413; // @[lsu_bus_buffer.scala 532:88] + wire [2:0] _GEN_390 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 532:154] + wire [3:0] _T_4415 = _T_4414 + _GEN_390; // @[lsu_bus_buffer.scala 532:154] + wire [1:0] _T_4420 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 532:217] + wire [1:0] _GEN_391 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 532:217] + wire [2:0] _T_4421 = _T_4420 + _GEN_391; // @[lsu_bus_buffer.scala 532:217] + wire [2:0] _GEN_392 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 532:217] + wire [3:0] _T_4422 = _T_4421 + _GEN_392; // @[lsu_bus_buffer.scala 532:217] + wire [3:0] buf_numvld_any = _T_4415 + _T_4422; // @[lsu_bus_buffer.scala 532:169] + wire _T_4493 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 538:52] + wire _T_4494 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 538:92] + wire _T_4495 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 538:121] + wire _T_4497 = |buf_state_0; // @[lsu_bus_buffer.scala 539:52] + wire _T_4498 = |buf_state_1; // @[lsu_bus_buffer.scala 539:52] + wire _T_4499 = |buf_state_2; // @[lsu_bus_buffer.scala 539:52] + wire _T_4500 = |buf_state_3; // @[lsu_bus_buffer.scala 539:52] + wire _T_4501 = _T_4497 | _T_4498; // @[lsu_bus_buffer.scala 539:65] + wire _T_4502 = _T_4501 | _T_4499; // @[lsu_bus_buffer.scala 539:65] + wire _T_4503 = _T_4502 | _T_4500; // @[lsu_bus_buffer.scala 539:65] + wire _T_4504 = ~_T_4503; // @[lsu_bus_buffer.scala 539:34] + wire _T_4506 = _T_4504 & _T_852; // @[lsu_bus_buffer.scala 539:70] + wire _T_4509 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 541:64] + wire _T_4510 = _T_4509 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 541:85] + wire _T_4511 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 541:112] + wire _T_4512 = _T_4510 & _T_4511; // @[lsu_bus_buffer.scala 541:110] + wire _T_4513 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 541:129] + wire _T_4515 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 544:74] + reg lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 629:66] + wire _T_4529 = _T_2770 & _T_3645; // @[Mux.scala 27:72] + wire _T_4530 = _T_2792 & _T_3836; // @[Mux.scala 27:72] + wire _T_4531 = _T_2814 & _T_4027; // @[Mux.scala 27:72] + wire _T_4532 = _T_2836 & _T_4218; // @[Mux.scala 27:72] + wire _T_4533 = _T_4529 | _T_4530; // @[Mux.scala 27:72] + wire _T_4534 = _T_4533 | _T_4531; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4534 | _T_4532; // @[Mux.scala 27:72] + wire _T_4540 = buf_error[0] & _T_3645; // @[lsu_bus_buffer.scala 547:121] + wire _T_4545 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 547:121] + wire _T_4550 = buf_error[2] & _T_4027; // @[lsu_bus_buffer.scala 547:121] + wire _T_4555 = buf_error[3] & _T_4218; // @[lsu_bus_buffer.scala 547:121] + wire _T_4556 = _T_2770 & _T_4540; // @[Mux.scala 27:72] + wire _T_4557 = _T_2792 & _T_4545; // @[Mux.scala 27:72] + wire _T_4558 = _T_2814 & _T_4550; // @[Mux.scala 27:72] + wire _T_4559 = _T_2836 & _T_4555; // @[Mux.scala 27:72] + wire _T_4560 = _T_4556 | _T_4557; // @[Mux.scala 27:72] + wire _T_4561 = _T_4560 | _T_4558; // @[Mux.scala 27:72] + wire _T_4568 = ~buf_dual_0; // @[lsu_bus_buffer.scala 548:121] + wire _T_4569 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 548:136] + wire _T_4570 = _T_4568 | _T_4569; // @[lsu_bus_buffer.scala 548:134] + wire _T_4571 = _T_4529 & _T_4570; // @[lsu_bus_buffer.scala 548:118] + wire _T_4576 = ~buf_dual_1; // @[lsu_bus_buffer.scala 548:121] + wire _T_4577 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 548:136] + wire _T_4578 = _T_4576 | _T_4577; // @[lsu_bus_buffer.scala 548:134] + wire _T_4579 = _T_4530 & _T_4578; // @[lsu_bus_buffer.scala 548:118] + wire _T_4584 = ~buf_dual_2; // @[lsu_bus_buffer.scala 548:121] + wire _T_4585 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 548:136] + wire _T_4586 = _T_4584 | _T_4585; // @[lsu_bus_buffer.scala 548:134] + wire _T_4587 = _T_4531 & _T_4586; // @[lsu_bus_buffer.scala 548:118] + wire _T_4592 = ~buf_dual_3; // @[lsu_bus_buffer.scala 548:121] + wire _T_4593 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 548:136] + wire _T_4594 = _T_4592 | _T_4593; // @[lsu_bus_buffer.scala 548:134] + wire _T_4595 = _T_4532 & _T_4594; // @[lsu_bus_buffer.scala 548:118] + wire [1:0] _T_4598 = _T_4587 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4599 = _T_4595 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_393 = {{1'd0}, _T_4579}; // @[Mux.scala 27:72] + wire [1:0] _T_4601 = _GEN_393 | _T_4598; // @[Mux.scala 27:72] + wire [31:0] _T_4636 = _T_4571 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4637 = _T_4579 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4638 = _T_4587 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4639 = _T_4595 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4640 = _T_4636 | _T_4637; // @[Mux.scala 27:72] + wire [31:0] _T_4641 = _T_4640 | _T_4638; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_lo = _T_4641 | _T_4639; // @[Mux.scala 27:72] + wire _T_4648 = _T_4529 & _T_3643; // @[lsu_bus_buffer.scala 550:105] + wire _T_4654 = _T_4530 & _T_3834; // @[lsu_bus_buffer.scala 550:105] + wire _T_4660 = _T_4531 & _T_4025; // @[lsu_bus_buffer.scala 550:105] + wire _T_4666 = _T_4532 & _T_4216; // @[lsu_bus_buffer.scala 550:105] + wire [31:0] _T_4667 = _T_4648 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4668 = _T_4654 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4669 = _T_4660 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4670 = _T_4666 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4671 = _T_4667 | _T_4668; // @[Mux.scala 27:72] + wire [31:0] _T_4672 = _T_4671 | _T_4669; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_hi = _T_4672 | _T_4670; // @[Mux.scala 27:72] + wire _T_4674 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 62:123] + wire _T_4675 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 62:123] + wire _T_4676 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 62:123] + wire _T_4677 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 62:123] + wire [31:0] _T_4678 = _T_4674 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4679 = _T_4675 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4680 = _T_4676 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4681 = _T_4677 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4682 = _T_4678 | _T_4679; // @[Mux.scala 27:72] + wire [31:0] _T_4683 = _T_4682 | _T_4680; // @[Mux.scala 27:72] + wire [31:0] _T_4684 = _T_4683 | _T_4681; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_addr_offset = _T_4684[1:0]; // @[lsu_bus_buffer.scala 551:96] + wire [1:0] _T_4690 = _T_4674 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4691 = _T_4675 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4692 = _T_4676 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4693 = _T_4677 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4694 = _T_4690 | _T_4691; // @[Mux.scala 27:72] + wire [1:0] _T_4695 = _T_4694 | _T_4692; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_sz = _T_4695 | _T_4693; // @[Mux.scala 27:72] + wire _T_4705 = _T_4674 & buf_unsign[0]; // @[Mux.scala 27:72] + wire _T_4706 = _T_4675 & buf_unsign[1]; // @[Mux.scala 27:72] + wire _T_4707 = _T_4676 & buf_unsign[2]; // @[Mux.scala 27:72] + wire _T_4708 = _T_4677 & buf_unsign[3]; // @[Mux.scala 27:72] + wire _T_4709 = _T_4705 | _T_4706; // @[Mux.scala 27:72] + wire _T_4710 = _T_4709 | _T_4707; // @[Mux.scala 27:72] + wire lsu_nonblock_unsign = _T_4710 | _T_4708; // @[Mux.scala 27:72] + wire [63:0] _T_4712 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] + wire [3:0] _GEN_394 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 555:121] + wire [5:0] _T_4713 = _GEN_394 * 4'h8; // @[lsu_bus_buffer.scala 555:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4712 >> _T_4713; // @[lsu_bus_buffer.scala 555:92] + wire _T_4714 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 557:82] + wire _T_4716 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 558:81] + wire _T_4717 = lsu_nonblock_unsign & _T_4716; // @[lsu_bus_buffer.scala 558:63] + wire [31:0] _T_4719 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4720 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 559:45] + wire _T_4721 = lsu_nonblock_unsign & _T_4720; // @[lsu_bus_buffer.scala 559:26] + wire [31:0] _T_4723 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4724 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 560:6] + wire _T_4726 = _T_4724 & _T_4716; // @[lsu_bus_buffer.scala 560:27] + wire [23:0] _T_4729 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4731 = {_T_4729,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4734 = _T_4724 & _T_4720; // @[lsu_bus_buffer.scala 561:27] + wire [15:0] _T_4737 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4739 = {_T_4737,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4740 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 562:21] + wire [31:0] _T_4741 = _T_4717 ? _T_4719 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4742 = _T_4721 ? _T_4723 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4743 = _T_4726 ? _T_4731 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4744 = _T_4734 ? _T_4739 : 32'h0; // @[Mux.scala 27:72] + wire [63:0] _T_4745 = _T_4740 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4746 = _T_4741 | _T_4742; // @[Mux.scala 27:72] + wire [31:0] _T_4747 = _T_4746 | _T_4743; // @[Mux.scala 27:72] + wire [31:0] _T_4748 = _T_4747 | _T_4744; // @[Mux.scala 27:72] + wire [63:0] _GEN_395 = {{32'd0}, _T_4748}; // @[Mux.scala 27:72] + wire [63:0] _T_4749 = _GEN_395 | _T_4745; // @[Mux.scala 27:72] + wire _T_4878 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4880 = _T_4878 & buf_write[0]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4883 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4885 = _T_4883 & buf_write[1]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4888 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4890 = _T_4888 & buf_write[2]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4893 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4895 = _T_4893 & buf_write[3]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4896 = _T_2770 & _T_4880; // @[Mux.scala 27:72] + wire _T_4897 = _T_2792 & _T_4885; // @[Mux.scala 27:72] + wire _T_4898 = _T_2814 & _T_4890; // @[Mux.scala 27:72] + wire _T_4899 = _T_2836 & _T_4895; // @[Mux.scala 27:72] + wire _T_4900 = _T_4896 | _T_4897; // @[Mux.scala 27:72] + wire _T_4901 = _T_4900 | _T_4898; // @[Mux.scala 27:72] + wire _T_4911 = _T_2792 & buf_error[1]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4913 = _T_4911 & buf_write[1]; // @[lsu_bus_buffer.scala 611:108] + wire _T_4916 = _T_2814 & buf_error[2]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4918 = _T_4916 & buf_write[2]; // @[lsu_bus_buffer.scala 611:108] + wire _T_4921 = _T_2836 & buf_error[3]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4923 = _T_4921 & buf_write[3]; // @[lsu_bus_buffer.scala 611:108] + wire [1:0] _T_4926 = _T_4918 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4927 = _T_4923 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_396 = {{1'd0}, _T_4913}; // @[Mux.scala 27:72] + wire [1:0] _T_4929 = _GEN_396 | _T_4926; // @[Mux.scala 27:72] + wire [1:0] lsu_imprecise_error_store_tag = _T_4929 | _T_4927; // @[Mux.scala 27:72] + wire _T_4931 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 613:97] + wire [31:0] _GEN_369 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_370 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_369; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_371 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_370; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_373 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_374 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_373; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_375 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_374; // @[lsu_bus_buffer.scala 614:53] + wire _T_4936 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 620:82] + wire _T_4939 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 621:60] + wire _T_4942 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 624:61] + wire _T_4943 = io_lsu_axi_aw_valid & _T_4942; // @[lsu_bus_buffer.scala 624:59] + wire _T_4944 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 624:107] + wire _T_4945 = io_lsu_axi_w_valid & _T_4944; // @[lsu_bus_buffer.scala 624:105] + wire _T_4946 = _T_4943 | _T_4945; // @[lsu_bus_buffer.scala 624:83] + wire _T_4947 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 624:153] + wire _T_4948 = io_lsu_axi_ar_valid & _T_4947; // @[lsu_bus_buffer.scala 624:151] + wire _T_4952 = ~io_flush_r; // @[lsu_bus_buffer.scala 628:75] + wire _T_4953 = io_lsu_busreq_m & _T_4952; // @[lsu_bus_buffer.scala 628:73] + reg _T_4956; // @[lsu_bus_buffer.scala 628:56] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4936 | _T_4835; // @[lsu_bus_buffer.scala 620:35] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4939 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 621:41] + assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 622:36] + assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4946 | _T_4948; // @[lsu_bus_buffer.scala 624:35] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4931; // @[lsu_bus_buffer.scala 613:47] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4901 | _T_4899; // @[lsu_bus_buffer.scala 610:48] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_371 : _GEN_375; // @[lsu_bus_buffer.scala 614:47] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4512 & _T_4513; // @[lsu_bus_buffer.scala 541:45] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1802 ? 2'h0 : _T_1838; // @[lsu_bus_buffer.scala 542:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4515; // @[lsu_bus_buffer.scala 544:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 545:47] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4714; // @[lsu_bus_buffer.scala 557:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4561 | _T_4559; // @[lsu_bus_buffer.scala 547:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4601 | _T_4599; // @[lsu_bus_buffer.scala 548:45] + assign io_lsu_axi_aw_valid = 1'h0; // @[lsu_bus_buffer.scala 580:23] + assign io_lsu_axi_aw_bits_addr = {obuf_addr[31:3],3'h0}; // @[lsu_bus_buffer.scala 582:27] + assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 586:29] + assign io_lsu_axi_w_valid = 1'h0; // @[lsu_bus_buffer.scala 592:22] + assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 594:26] + assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 608:22] + assign io_lsu_axi_ar_valid = _T_1348 & _T_1237; // @[lsu_bus_buffer.scala 597:23] + assign io_lsu_axi_ar_bits_addr = {obuf_addr[31:3],3'h0}; // @[lsu_bus_buffer.scala 599:27] + assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 603:29] + assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 609:22] + assign io_lsu_busreq_r = _T_4956; // @[lsu_bus_buffer.scala 628:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 537:30] + assign io_lsu_bus_buffer_full_any = _T_4493 ? _T_4494 : _T_4495; // @[lsu_bus_buffer.scala 538:30] + assign io_lsu_bus_buffer_empty_any = _T_4506 & _T_1231; // @[lsu_bus_buffer.scala 539:31] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 142:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 143:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 169:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 175:24] + assign io_lsu_nonblock_load_data = _T_4749[31:0]; // @[lsu_bus_buffer.scala 558:29] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = _T_3531 & buf_state_en_0; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = _T_3722 & buf_state_en_1; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = _T_3913 & buf_state_en_2; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = _T_4104 & buf_state_en_3; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = _T_3531 ? buf_state_en_0 : _GEN_81; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = _T_3722 ? buf_state_en_1 : _GEN_157; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = _T_3913 ? buf_state_en_2 : _GEN_233; // @[lib.scala 407:17] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_11_io_en = _T_4104 ? buf_state_en_3 : _GEN_309; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_addr_0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_4355 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_4352 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_4349 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_4346 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + buf_state_0 = _RAND_5[2:0]; + _RAND_6 = {1{`RANDOM}}; + buf_addr_1 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + buf_state_1 = _RAND_7[2:0]; + _RAND_8 = {1{`RANDOM}}; + buf_addr_2 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + buf_state_2 = _RAND_9[2:0]; + _RAND_10 = {1{`RANDOM}}; + buf_addr_3 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + buf_state_3 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + buf_byteen_3 = _RAND_12[3:0]; + _RAND_13 = {1{`RANDOM}}; + buf_byteen_2 = _RAND_13[3:0]; + _RAND_14 = {1{`RANDOM}}; + buf_byteen_1 = _RAND_14[3:0]; + _RAND_15 = {1{`RANDOM}}; + buf_byteen_0 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + buf_ageQ_3 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + obuf_valid = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + ibuf_addr = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + ibuf_write = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + ibuf_valid = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + ibuf_byteen = _RAND_21[3:0]; + _RAND_22 = {1{`RANDOM}}; + buf_ageQ_2 = _RAND_22[3:0]; + _RAND_23 = {1{`RANDOM}}; + buf_ageQ_1 = _RAND_23[3:0]; + _RAND_24 = {1{`RANDOM}}; + buf_ageQ_0 = _RAND_24[3:0]; + _RAND_25 = {1{`RANDOM}}; + buf_data_0 = _RAND_25[31:0]; + _RAND_26 = {1{`RANDOM}}; + buf_data_1 = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + buf_data_2 = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + buf_data_3 = _RAND_28[31:0]; + _RAND_29 = {1{`RANDOM}}; + ibuf_data = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + ibuf_timer = _RAND_30[2:0]; + _RAND_31 = {1{`RANDOM}}; + ibuf_sideeffect = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + WrPtr1_r = _RAND_32[1:0]; + _RAND_33 = {1{`RANDOM}}; + WrPtr0_r = _RAND_33[1:0]; + _RAND_34 = {1{`RANDOM}}; + ibuf_tag = _RAND_34[1:0]; + _RAND_35 = {1{`RANDOM}}; + ibuf_dualtag = _RAND_35[1:0]; + _RAND_36 = {1{`RANDOM}}; + ibuf_dual = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + ibuf_samedw = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + ibuf_nomerge = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + ibuf_unsign = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + ibuf_sz = _RAND_40[1:0]; + _RAND_41 = {1{`RANDOM}}; + _T_1791 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + buf_nomerge_0 = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + buf_nomerge_1 = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + buf_nomerge_2 = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + buf_nomerge_3 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + _T_4325 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + _T_4322 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + _T_4319 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + _T_4316 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + buf_dual_3 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + buf_dual_2 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + buf_dual_1 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + buf_dual_0 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + buf_samedw_3 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + buf_samedw_2 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + buf_samedw_1 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + buf_samedw_0 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + obuf_nosend = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + obuf_addr = _RAND_59[31:0]; + _RAND_60 = {1{`RANDOM}}; + buf_sz_0 = _RAND_60[1:0]; + _RAND_61 = {1{`RANDOM}}; + buf_sz_1 = _RAND_61[1:0]; + _RAND_62 = {1{`RANDOM}}; + buf_sz_2 = _RAND_62[1:0]; + _RAND_63 = {1{`RANDOM}}; + buf_sz_3 = _RAND_63[1:0]; + _RAND_64 = {1{`RANDOM}}; + obuf_rdrsp_pend = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + buf_dualhi_3 = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + buf_dualhi_2 = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + buf_dualhi_1 = _RAND_67[0:0]; + _RAND_68 = {1{`RANDOM}}; + buf_dualhi_0 = _RAND_68[0:0]; + _RAND_69 = {2{`RANDOM}}; + obuf_data = _RAND_69[63:0]; + _RAND_70 = {1{`RANDOM}}; + buf_rspageQ_0 = _RAND_70[3:0]; + _RAND_71 = {1{`RANDOM}}; + buf_rspageQ_1 = _RAND_71[3:0]; + _RAND_72 = {1{`RANDOM}}; + buf_rspageQ_2 = _RAND_72[3:0]; + _RAND_73 = {1{`RANDOM}}; + buf_rspageQ_3 = _RAND_73[3:0]; + _RAND_74 = {1{`RANDOM}}; + _T_4302 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + _T_4300 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + _T_4298 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + _T_4296 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + buf_dualtag_0 = _RAND_78[1:0]; + _RAND_79 = {1{`RANDOM}}; + buf_dualtag_1 = _RAND_79[1:0]; + _RAND_80 = {1{`RANDOM}}; + buf_dualtag_2 = _RAND_80[1:0]; + _RAND_81 = {1{`RANDOM}}; + buf_dualtag_3 = _RAND_81[1:0]; + _RAND_82 = {1{`RANDOM}}; + _T_4331 = _RAND_82[0:0]; + _RAND_83 = {1{`RANDOM}}; + _T_4334 = _RAND_83[0:0]; + _RAND_84 = {1{`RANDOM}}; + _T_4337 = _RAND_84[0:0]; + _RAND_85 = {1{`RANDOM}}; + _T_4340 = _RAND_85[0:0]; + _RAND_86 = {1{`RANDOM}}; + _T_4406 = _RAND_86[0:0]; + _RAND_87 = {1{`RANDOM}}; + _T_4401 = _RAND_87[0:0]; + _RAND_88 = {1{`RANDOM}}; + _T_4396 = _RAND_88[0:0]; + _RAND_89 = {1{`RANDOM}}; + _T_4391 = _RAND_89[0:0]; + _RAND_90 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_90[0:0]; + _RAND_91 = {1{`RANDOM}}; + _T_4956 = _RAND_91[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_addr_0 = 32'h0; + end + if (reset) begin + _T_4355 = 1'h0; + end + if (reset) begin + _T_4352 = 1'h0; + end + if (reset) begin + _T_4349 = 1'h0; + end + if (reset) begin + _T_4346 = 1'h0; + end + if (reset) begin + buf_state_0 = 3'h0; + end + if (reset) begin + buf_addr_1 = 32'h0; + end + if (reset) begin + buf_state_1 = 3'h0; + end + if (reset) begin + buf_addr_2 = 32'h0; + end + if (reset) begin + buf_state_2 = 3'h0; + end + if (reset) begin + buf_addr_3 = 32'h0; + end + if (reset) begin + buf_state_3 = 3'h0; + end + if (reset) begin + buf_byteen_3 = 4'h0; + end + if (reset) begin + buf_byteen_2 = 4'h0; + end + if (reset) begin + buf_byteen_1 = 4'h0; + end + if (reset) begin + buf_byteen_0 = 4'h0; + end + if (reset) begin + buf_ageQ_3 = 4'h0; + end + if (reset) begin + obuf_valid = 1'h0; + end + if (reset) begin + ibuf_addr = 32'h0; + end + if (reset) begin + ibuf_write = 1'h0; + end + if (reset) begin + ibuf_valid = 1'h0; + end + if (reset) begin + ibuf_byteen = 4'h0; + end + if (reset) begin + buf_ageQ_2 = 4'h0; + end + if (reset) begin + buf_ageQ_1 = 4'h0; + end + if (reset) begin + buf_ageQ_0 = 4'h0; + end + if (reset) begin + buf_data_0 = 32'h0; + end + if (reset) begin + buf_data_1 = 32'h0; + end + if (reset) begin + buf_data_2 = 32'h0; + end + if (reset) begin + buf_data_3 = 32'h0; + end + if (reset) begin + ibuf_data = 32'h0; + end + if (reset) begin + ibuf_timer = 3'h0; + end + if (reset) begin + ibuf_sideeffect = 1'h0; + end + if (reset) begin + WrPtr1_r = 2'h0; + end + if (reset) begin + WrPtr0_r = 2'h0; + end + if (reset) begin + ibuf_tag = 2'h0; + end + if (reset) begin + ibuf_dualtag = 2'h0; + end + if (reset) begin + ibuf_dual = 1'h0; + end + if (reset) begin + ibuf_samedw = 1'h0; + end + if (reset) begin + ibuf_nomerge = 1'h0; + end + if (reset) begin + ibuf_unsign = 1'h0; + end + if (reset) begin + ibuf_sz = 2'h0; + end + if (reset) begin + _T_1791 = 1'h0; + end + if (reset) begin + buf_nomerge_0 = 1'h0; + end + if (reset) begin + buf_nomerge_1 = 1'h0; + end + if (reset) begin + buf_nomerge_2 = 1'h0; + end + if (reset) begin + buf_nomerge_3 = 1'h0; + end + if (reset) begin + _T_4325 = 1'h0; + end + if (reset) begin + _T_4322 = 1'h0; + end + if (reset) begin + _T_4319 = 1'h0; + end + if (reset) begin + _T_4316 = 1'h0; + end + if (reset) begin + buf_dual_3 = 1'h0; + end + if (reset) begin + buf_dual_2 = 1'h0; + end + if (reset) begin + buf_dual_1 = 1'h0; + end + if (reset) begin + buf_dual_0 = 1'h0; + end + if (reset) begin + buf_samedw_3 = 1'h0; + end + if (reset) begin + buf_samedw_2 = 1'h0; + end + if (reset) begin + buf_samedw_1 = 1'h0; + end + if (reset) begin + buf_samedw_0 = 1'h0; + end + if (reset) begin + obuf_nosend = 1'h0; + end + if (reset) begin + obuf_addr = 32'h0; + end + if (reset) begin + buf_sz_0 = 2'h0; + end + if (reset) begin + buf_sz_1 = 2'h0; + end + if (reset) begin + buf_sz_2 = 2'h0; + end + if (reset) begin + buf_sz_3 = 2'h0; + end + if (reset) begin + obuf_rdrsp_pend = 1'h0; + end + if (reset) begin + buf_dualhi_3 = 1'h0; + end + if (reset) begin + buf_dualhi_2 = 1'h0; + end + if (reset) begin + buf_dualhi_1 = 1'h0; + end + if (reset) begin + buf_dualhi_0 = 1'h0; + end + if (reset) begin + obuf_data = 64'h0; + end + if (reset) begin + buf_rspageQ_0 = 4'h0; + end + if (reset) begin + buf_rspageQ_1 = 4'h0; + end + if (reset) begin + buf_rspageQ_2 = 4'h0; + end + if (reset) begin + buf_rspageQ_3 = 4'h0; + end + if (reset) begin + _T_4302 = 1'h0; + end + if (reset) begin + _T_4300 = 1'h0; + end + if (reset) begin + _T_4298 = 1'h0; + end + if (reset) begin + _T_4296 = 1'h0; + end + if (reset) begin + buf_dualtag_0 = 2'h0; + end + if (reset) begin + buf_dualtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_2 = 2'h0; + end + if (reset) begin + buf_dualtag_3 = 2'h0; + end + if (reset) begin + _T_4331 = 1'h0; + end + if (reset) begin + _T_4334 = 1'h0; + end + if (reset) begin + _T_4337 = 1'h0; + end + if (reset) begin + _T_4340 = 1'h0; + end + if (reset) begin + _T_4406 = 1'h0; + end + if (reset) begin + _T_4401 = 1'h0; + end + if (reset) begin + _T_4396 = 1'h0; + end + if (reset) begin + _T_4391 = 1'h0; + end + if (reset) begin + lsu_nonblock_load_valid_r = 1'h0; + end + if (reset) begin + _T_4956 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_0 <= 32'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_addr_0 <= ibuf_addr; + end else if (_T_3346) begin + buf_addr_0 <= io_end_addr_r; + end else begin + buf_addr_0 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4355 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4355 <= buf_write_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4352 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4352 <= buf_write_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4349 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4349 <= buf_write_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4346 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4346 <= buf_write_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_0 <= 3'h0; + end else if (buf_state_en_0) begin + if (_T_3531) begin + if (io_lsu_bus_clk_en) begin + buf_state_0 <= 3'h2; + end else begin + buf_state_0 <= 3'h1; + end + end else if (_T_3554) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h2; + end + end else if (_T_3558) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3562) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h3; + end + end else if (_T_3592) begin + if (_T_3596) begin + buf_state_0 <= 3'h0; + end else if (_T_3604) begin + buf_state_0 <= 3'h4; + end else if (_T_3632) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3677) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3683) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3695) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h6; + end + end else begin + buf_state_0 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_1 <= 32'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_addr_1 <= ibuf_addr; + end else if (_T_3355) begin + buf_addr_1 <= io_end_addr_r; + end else begin + buf_addr_1 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_1 <= 3'h0; + end else if (buf_state_en_1) begin + if (_T_3722) begin + if (io_lsu_bus_clk_en) begin + buf_state_1 <= 3'h2; + end else begin + buf_state_1 <= 3'h1; + end + end else if (_T_3745) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h2; + end + end else if (_T_3749) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3562) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h3; + end + end else if (_T_3783) begin + if (_T_3787) begin + buf_state_1 <= 3'h0; + end else if (_T_3795) begin + buf_state_1 <= 3'h4; + end else if (_T_3823) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3868) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3874) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3886) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h6; + end + end else begin + buf_state_1 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_2 <= 32'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_addr_2 <= ibuf_addr; + end else if (_T_3364) begin + buf_addr_2 <= io_end_addr_r; + end else begin + buf_addr_2 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_2 <= 3'h0; + end else if (buf_state_en_2) begin + if (_T_3913) begin + if (io_lsu_bus_clk_en) begin + buf_state_2 <= 3'h2; + end else begin + buf_state_2 <= 3'h1; + end + end else if (_T_3936) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h2; + end + end else if (_T_3940) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3562) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h3; + end + end else if (_T_3974) begin + if (_T_3978) begin + buf_state_2 <= 3'h0; + end else if (_T_3986) begin + buf_state_2 <= 3'h4; + end else if (_T_4014) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4059) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_4065) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4077) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h6; + end + end else begin + buf_state_2 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_3 <= 32'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_addr_3 <= ibuf_addr; + end else if (_T_3373) begin + buf_addr_3 <= io_end_addr_r; + end else begin + buf_addr_3 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_3 <= 3'h0; + end else if (buf_state_en_3) begin + if (_T_4104) begin + if (io_lsu_bus_clk_en) begin + buf_state_3 <= 3'h2; + end else begin + buf_state_3 <= 3'h1; + end + end else if (_T_4127) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h2; + end + end else if (_T_4131) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_3562) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h3; + end + end else if (_T_4165) begin + if (_T_4169) begin + buf_state_3 <= 3'h0; + end else if (_T_4177) begin + buf_state_3 <= 3'h4; + end else if (_T_4205) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4250) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_4256) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4268) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h6; + end + end else begin + buf_state_3 <= 3'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_3 <= 4'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_byteen_3 <= ibuf_byteen_out; + end else if (_T_3373) begin + buf_byteen_3 <= ldst_byteen_hi_r; + end else begin + buf_byteen_3 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_2 <= 4'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_byteen_2 <= ibuf_byteen_out; + end else if (_T_3364) begin + buf_byteen_2 <= ldst_byteen_hi_r; + end else begin + buf_byteen_2 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_1 <= 4'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_byteen_1 <= ibuf_byteen_out; + end else if (_T_3355) begin + buf_byteen_1 <= ldst_byteen_hi_r; + end else begin + buf_byteen_1 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_0 <= 4'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_byteen_0 <= ibuf_byteen_out; + end else if (_T_3346) begin + buf_byteen_0 <= ldst_byteen_hi_r; + end else begin + buf_byteen_0 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_3 <= 4'h0; + end else begin + buf_ageQ_3 <= {_T_2474,_T_2397}; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_valid <= 1'h0; + end else begin + obuf_valid <= _T_1771 & _T_1772; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ibuf_addr <= 32'h0; + end else if (ibuf_wr_en) begin + if (io_ldst_dual_r) begin + ibuf_addr <= io_end_addr_r; + end else begin + ibuf_addr <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_write <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_write <= io_lsu_pkt_r_bits_store; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_valid <= 1'h0; + end else begin + ibuf_valid <= _T_1005 & _T_1006; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_byteen <= 4'h0; + end else if (ibuf_wr_en) begin + if (_T_866) begin + ibuf_byteen <= _T_881; + end else if (io_ldst_dual_r) begin + ibuf_byteen <= ldst_byteen_hi_r; + end else begin + ibuf_byteen <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_2 <= 4'h0; + end else begin + buf_ageQ_2 <= {_T_2372,_T_2295}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_1 <= 4'h0; + end else begin + buf_ageQ_1 <= {_T_2270,_T_2193}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_0 <= 4'h0; + end else begin + buf_ageQ_0 <= {_T_2168,_T_2091}; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_0 <= 32'h0; + end else if (buf_data_en_0) begin + if (_T_3531) begin + if (_T_3546) begin + buf_data_0 <= ibuf_data_out; + end else begin + buf_data_0 <= store_data_lo_r; + end + end else if (_T_3554) begin + buf_data_0 <= 32'h0; + end else if (_T_3558) begin + if (buf_error_en_0) begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3592) begin + if (_T_3670) begin + if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_1 <= 32'h0; + end else if (buf_data_en_1) begin + if (_T_3722) begin + if (_T_3737) begin + buf_data_1 <= ibuf_data_out; + end else begin + buf_data_1 <= store_data_lo_r; + end + end else if (_T_3745) begin + buf_data_1 <= 32'h0; + end else if (_T_3749) begin + if (buf_error_en_1) begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3783) begin + if (_T_3861) begin + if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_2 <= 32'h0; + end else if (buf_data_en_2) begin + if (_T_3913) begin + if (_T_3928) begin + buf_data_2 <= ibuf_data_out; + end else begin + buf_data_2 <= store_data_lo_r; + end + end else if (_T_3936) begin + buf_data_2 <= 32'h0; + end else if (_T_3940) begin + if (buf_error_en_2) begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3974) begin + if (_T_4052) begin + if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_3 <= 32'h0; + end else if (buf_data_en_3) begin + if (_T_4104) begin + if (_T_4119) begin + buf_data_3 <= ibuf_data_out; + end else begin + buf_data_3 <= store_data_lo_r; + end + end else if (_T_4127) begin + buf_data_3 <= 32'h0; + end else if (_T_4131) begin + if (buf_error_en_3) begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_4165) begin + if (_T_4243) begin + if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ibuf_data <= 32'h0; + end else if (ibuf_wr_en) begin + ibuf_data <= ibuf_data_in; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_923) begin + ibuf_timer <= _T_926; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sideeffect <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_sideeffect <= io_is_sideeffects_r; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr1_r <= 2'h0; + end else if (_T_1853) begin + WrPtr1_r <= 2'h0; + end else if (_T_1867) begin + WrPtr1_r <= 2'h1; + end else if (_T_1881) begin + WrPtr1_r <= 2'h2; + end else begin + WrPtr1_r <= 2'h3; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr0_r <= 2'h0; + end else if (_T_1802) begin + WrPtr0_r <= 2'h0; + end else if (_T_1813) begin + WrPtr0_r <= 2'h1; + end else if (_T_1824) begin + WrPtr0_r <= 2'h2; + end else begin + WrPtr0_r <= 2'h3; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_tag <= 2'h0; + end else if (ibuf_wr_en) begin + if (!(_T_866)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dualtag <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_dualtag <= WrPtr0_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dual <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_dual <= io_ldst_dual_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_samedw <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_samedw <= ldst_samedw_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_nomerge <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_nomerge <= io_no_dword_merge_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_unsign <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_unsign <= io_lsu_pkt_r_bits_unsign; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sz <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_sz <= ibuf_sz_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1791 <= 1'h0; + end else if (obuf_wr_en) begin + _T_1791 <= obuf_data_done_in; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_nomerge_0 <= buf_nomerge_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_nomerge_1 <= buf_nomerge_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_nomerge_2 <= buf_nomerge_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_nomerge_3 <= buf_nomerge_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4325 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4325 <= buf_sideeffect_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4322 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4322 <= buf_sideeffect_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4319 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4319 <= buf_sideeffect_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4316 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4316 <= buf_sideeffect_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dual_3 <= buf_dual_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dual_2 <= buf_dual_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dual_1 <= buf_dual_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dual_0 <= buf_dual_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_samedw_3 <= buf_samedw_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_samedw_2 <= buf_samedw_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_samedw_1 <= buf_samedw_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_samedw_0 <= buf_samedw_in[0]; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_nosend <= 1'h0; + end else if (obuf_wr_en) begin + obuf_nosend <= obuf_nosend_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_addr <= 32'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_addr <= io_lsu_addr_r; + end else begin + obuf_addr <= _T_1287; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_sz_0 <= ibuf_sz; + end else begin + buf_sz_0 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_sz_1 <= ibuf_sz; + end else begin + buf_sz_1 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_sz_2 <= ibuf_sz; + end else begin + buf_sz_2 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_sz_3 <= ibuf_sz; + end else begin + buf_sz_3 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_pend <= 1'h0; + end else if (obuf_rdrsp_pend_en) begin + obuf_rdrsp_pend <= obuf_rdrsp_pend_in; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dualhi_3 <= buf_dualhi_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dualhi_2 <= buf_dualhi_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dualhi_1 <= buf_dualhi_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dualhi_0 <= buf_dualhi_in[0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_data <= 64'h0; + end else if (obuf_wr_en) begin + obuf_data <= obuf_data_in; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_0 <= 4'h0; + end else begin + buf_rspageQ_0 <= {_T_3144,_T_3133}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_1 <= 4'h0; + end else begin + buf_rspageQ_1 <= {_T_3159,_T_3148}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_2 <= 4'h0; + end else begin + buf_rspageQ_2 <= {_T_3174,_T_3163}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_3 <= 4'h0; + end else begin + buf_rspageQ_3 <= {_T_3189,_T_3178}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4302 <= 1'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4104) begin + _T_4302 <= 1'h0; + end else if (_T_4127) begin + _T_4302 <= 1'h0; + end else begin + _T_4302 <= _T_4131; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4300 <= 1'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3913) begin + _T_4300 <= 1'h0; + end else if (_T_3936) begin + _T_4300 <= 1'h0; + end else begin + _T_4300 <= _T_3940; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4298 <= 1'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3722) begin + _T_4298 <= 1'h0; + end else if (_T_3745) begin + _T_4298 <= 1'h0; + end else begin + _T_4298 <= _T_3749; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4296 <= 1'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3531) begin + _T_4296 <= 1'h0; + end else if (_T_3554) begin + _T_4296 <= 1'h0; + end else begin + _T_4296 <= _T_3558; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_dualtag_0 <= ibuf_dualtag; + end else if (_T_3346) begin + buf_dualtag_0 <= WrPtr0_r; + end else begin + buf_dualtag_0 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_dualtag_1 <= ibuf_dualtag; + end else if (_T_3355) begin + buf_dualtag_1 <= WrPtr0_r; + end else begin + buf_dualtag_1 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_dualtag_2 <= ibuf_dualtag; + end else if (_T_3364) begin + buf_dualtag_2 <= WrPtr0_r; + end else begin + buf_dualtag_2 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_dualtag_3 <= ibuf_dualtag; + end else if (_T_3373) begin + buf_dualtag_3 <= WrPtr0_r; + end else begin + buf_dualtag_3 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4331 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4331 <= buf_unsign_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4334 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4334 <= buf_unsign_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4337 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4337 <= buf_unsign_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4340 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4340 <= buf_unsign_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4406 <= 1'h0; + end else begin + _T_4406 <= _T_4402 & _T_4404; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4401 <= 1'h0; + end else begin + _T_4401 <= _T_4397 & _T_4399; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4396 <= 1'h0; + end else begin + _T_4396 <= _T_4392 & _T_4394; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4391 <= 1'h0; + end else begin + _T_4391 <= _T_4387 & _T_4389; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_nonblock_load_valid_r <= 1'h0; + end else begin + lsu_nonblock_load_valid_r <= io_dctl_busbuff_lsu_nonblock_load_valid_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_4956 <= 1'h0; + end else begin + _T_4956 <= _T_4953 & _T_4513; + end + end +endmodule +module lsu_bus_intf( + input clock, + input reset, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + input io_lsu_c1_r_clk, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_active_clk, + input io_axi_aw_ready, + output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, + input io_axi_w_ready, + output [63:0] io_axi_w_bits_data, + input io_axi_b_valid, + input [1:0] io_axi_b_bits_resp, + input [2:0] io_axi_b_bits_id, + input io_axi_ar_ready, + output io_axi_ar_valid, + output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, + input io_axi_r_valid, + input [2:0] io_axi_r_bits_id, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + input io_dec_lsu_valid_raw_d, + input io_lsu_busreq_m, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input [31:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_m, + input [31:0] io_end_addr_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [31:0] io_store_data_r, + input io_dec_tlu_force_halt, + input io_lsu_commit_r, + input io_is_sideeffects_m, + input io_flush_m_up, + input io_flush_r, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [31:0] io_bus_read_data_m, + output [31:0] io_lsu_nonblock_load_data, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + input io_lsu_bus_clk_en +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire bus_buffer_clock; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_reset; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_store_data_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_word_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_dword_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ld_full_hit_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_m_up; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_commit_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_is_sideeffects_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 100:39] + wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 100:39] + wire [3:0] _T_3 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_4 = io_lsu_pkt_m_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_5 = io_lsu_pkt_m_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72] + wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[lsu_bus_intf.scala 155:51] + wire _T_14 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[lsu_bus_intf.scala 156:71] + wire _T_15 = ~_T_14; // @[lsu_bus_intf.scala 156:53] + wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_15; // @[lsu_bus_intf.scala 156:51] + wire _T_17 = ~io_ldst_dual_r; // @[lsu_bus_intf.scala 157:48] + wire _T_18 = io_lsu_busreq_r & _T_17; // @[lsu_bus_intf.scala 157:46] + wire _T_19 = _T_18 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 157:64] + wire _T_20 = ~addr_match_word_lo_r_m; // @[lsu_bus_intf.scala 157:110] + wire _T_21 = io_lsu_pkt_m_bits_load | _T_20; // @[lsu_bus_intf.scala 157:108] + wire _T_26 = ~addr_match_dw_lo_r_m; // @[lsu_bus_intf.scala 158:110] + wire _T_27 = io_lsu_pkt_m_bits_load | _T_26; // @[lsu_bus_intf.scala 158:108] + wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[lsu_bus_intf.scala 160:49] + wire [6:0] _T_31 = _GEN_0 << io_lsu_addr_m[1:0]; // @[lsu_bus_intf.scala 160:49] + reg [3:0] ldst_byteen_r; // @[lsu_bus_intf.scala 200:33] + wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[lsu_bus_intf.scala 161:49] + wire [6:0] _T_34 = _GEN_1 << io_lsu_addr_r[1:0]; // @[lsu_bus_intf.scala 161:49] + wire [4:0] _T_37 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58] + wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[lsu_bus_intf.scala 162:52] + wire [62:0] _T_38 = _GEN_2 << _T_37; // @[lsu_bus_intf.scala 162:52] + wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 160:27] + wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[lsu_bus_intf.scala 163:47] + wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[lsu_bus_intf.scala 164:47] + wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 161:27] + wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[lsu_bus_intf.scala 165:47] + wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[lsu_bus_intf.scala 166:47] + wire [63:0] store_data_ext_r = {{1'd0}, _T_38}; // @[lsu_bus_intf.scala 162:27] + wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[lsu_bus_intf.scala 168:46] + wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[lsu_bus_intf.scala 169:46] + wire _T_47 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 170:51] + wire _T_48 = _T_47 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 170:76] + wire _T_49 = _T_48 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 170:97] + wire ld_addr_rhit_lo_lo = _T_49 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 170:123] + wire _T_53 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 171:51] + wire _T_54 = _T_53 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 171:76] + wire _T_55 = _T_54 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 171:97] + wire ld_addr_rhit_lo_hi = _T_55 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 171:123] + wire _T_59 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 172:51] + wire _T_60 = _T_59 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 172:76] + wire _T_61 = _T_60 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 172:97] + wire ld_addr_rhit_hi_lo = _T_61 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 172:123] + wire _T_65 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 173:51] + wire _T_66 = _T_65 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 173:76] + wire _T_67 = _T_66 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 173:97] + wire ld_addr_rhit_hi_hi = _T_67 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 173:123] + wire _T_70 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 175:70] + wire _T_72 = _T_70 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 175:92] + wire _T_74 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 175:70] + wire _T_76 = _T_74 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 175:92] + wire _T_78 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 175:70] + wire _T_80 = _T_78 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 175:92] + wire _T_82 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 175:70] + wire _T_84 = _T_82 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 175:92] + wire [3:0] ld_byte_rhit_lo_lo = {_T_84,_T_80,_T_76,_T_72}; // @[Cat.scala 29:58] + wire _T_89 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 176:70] + wire _T_91 = _T_89 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 176:92] + wire _T_93 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 176:70] + wire _T_95 = _T_93 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 176:92] + wire _T_97 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 176:70] + wire _T_99 = _T_97 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 176:92] + wire _T_101 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 176:70] + wire _T_103 = _T_101 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 176:92] + wire [3:0] ld_byte_rhit_lo_hi = {_T_103,_T_99,_T_95,_T_91}; // @[Cat.scala 29:58] + wire _T_108 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 177:70] + wire _T_110 = _T_108 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 177:92] + wire _T_112 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 177:70] + wire _T_114 = _T_112 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 177:92] + wire _T_116 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 177:70] + wire _T_118 = _T_116 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 177:92] + wire _T_120 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 177:70] + wire _T_122 = _T_120 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 177:92] + wire [3:0] ld_byte_rhit_hi_lo = {_T_122,_T_118,_T_114,_T_110}; // @[Cat.scala 29:58] + wire _T_127 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 178:70] + wire _T_129 = _T_127 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 178:92] + wire _T_131 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 178:70] + wire _T_133 = _T_131 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 178:92] + wire _T_135 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 178:70] + wire _T_137 = _T_135 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 178:92] + wire _T_139 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 178:70] + wire _T_141 = _T_139 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 178:92] + wire [3:0] ld_byte_rhit_hi_hi = {_T_141,_T_137,_T_133,_T_129}; // @[Cat.scala 29:58] + wire _T_147 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_bus_intf.scala 180:73] + wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 139:38] + wire _T_149 = _T_147 | ld_byte_hit_buf_lo[0]; // @[lsu_bus_intf.scala 180:97] + wire _T_152 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_bus_intf.scala 180:73] + wire _T_154 = _T_152 | ld_byte_hit_buf_lo[1]; // @[lsu_bus_intf.scala 180:97] + wire _T_157 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_bus_intf.scala 180:73] + wire _T_159 = _T_157 | ld_byte_hit_buf_lo[2]; // @[lsu_bus_intf.scala 180:97] + wire _T_162 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_bus_intf.scala 180:73] + wire _T_164 = _T_162 | ld_byte_hit_buf_lo[3]; // @[lsu_bus_intf.scala 180:97] + wire [3:0] ld_byte_hit_lo = {_T_164,_T_159,_T_154,_T_149}; // @[Cat.scala 29:58] + wire _T_170 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_bus_intf.scala 181:73] + wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 140:38] + wire _T_172 = _T_170 | ld_byte_hit_buf_hi[0]; // @[lsu_bus_intf.scala 181:97] + wire _T_175 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_bus_intf.scala 181:73] + wire _T_177 = _T_175 | ld_byte_hit_buf_hi[1]; // @[lsu_bus_intf.scala 181:97] + wire _T_180 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_bus_intf.scala 181:73] + wire _T_182 = _T_180 | ld_byte_hit_buf_hi[2]; // @[lsu_bus_intf.scala 181:97] + wire _T_185 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_bus_intf.scala 181:73] + wire _T_187 = _T_185 | ld_byte_hit_buf_hi[3]; // @[lsu_bus_intf.scala 181:97] + wire [3:0] ld_byte_hit_hi = {_T_187,_T_182,_T_177,_T_172}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_lo = {_T_162,_T_157,_T_152,_T_147}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_hi = {_T_185,_T_180,_T_175,_T_170}; // @[Cat.scala 29:58] + wire [7:0] _T_225 = ld_byte_rhit_lo_lo[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_226 = ld_byte_rhit_hi_lo[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_227 = _T_225 | _T_226; // @[Mux.scala 27:72] + wire [7:0] _T_233 = ld_byte_rhit_lo_lo[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_234 = ld_byte_rhit_hi_lo[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_235 = _T_233 | _T_234; // @[Mux.scala 27:72] + wire [7:0] _T_241 = ld_byte_rhit_lo_lo[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_242 = ld_byte_rhit_hi_lo[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_243 = _T_241 | _T_242; // @[Mux.scala 27:72] + wire [7:0] _T_249 = ld_byte_rhit_lo_lo[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_250 = ld_byte_rhit_hi_lo[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_251 = _T_249 | _T_250; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_lo = {_T_251,_T_243,_T_235,_T_227}; // @[Cat.scala 29:58] + wire [7:0] _T_260 = ld_byte_rhit_lo_hi[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_261 = ld_byte_rhit_hi_hi[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_262 = _T_260 | _T_261; // @[Mux.scala 27:72] + wire [7:0] _T_268 = ld_byte_rhit_lo_hi[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_269 = ld_byte_rhit_hi_hi[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_270 = _T_268 | _T_269; // @[Mux.scala 27:72] + wire [7:0] _T_276 = ld_byte_rhit_lo_hi[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_277 = ld_byte_rhit_hi_hi[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_278 = _T_276 | _T_277; // @[Mux.scala 27:72] + wire [7:0] _T_284 = ld_byte_rhit_lo_hi[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_285 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_286 = _T_284 | _T_285; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_hi = {_T_286,_T_278,_T_270,_T_262}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 141:38] + wire [7:0] _T_294 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_298 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_302 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_306 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[lsu_bus_intf.scala 186:54] + wire [31:0] _T_309 = {_T_306,_T_302,_T_298,_T_294}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 142:38] + wire [7:0] _T_313 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_317 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_321 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_325 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[lsu_bus_intf.scala 187:54] + wire [31:0] _T_328 = {_T_325,_T_321,_T_317,_T_313}; // @[Cat.scala 29:58] + wire _T_331 = ~ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 188:72] + wire _T_332 = ld_byte_hit_lo[0] | _T_331; // @[lsu_bus_intf.scala 188:70] + wire _T_335 = ~ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 188:72] + wire _T_336 = ld_byte_hit_lo[1] | _T_335; // @[lsu_bus_intf.scala 188:70] + wire _T_339 = ~ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 188:72] + wire _T_340 = ld_byte_hit_lo[2] | _T_339; // @[lsu_bus_intf.scala 188:70] + wire _T_343 = ~ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 188:72] + wire _T_344 = ld_byte_hit_lo[3] | _T_343; // @[lsu_bus_intf.scala 188:70] + wire _T_345 = _T_332 & _T_336; // @[lsu_bus_intf.scala 188:111] + wire _T_346 = _T_345 & _T_340; // @[lsu_bus_intf.scala 188:111] + wire ld_full_hit_lo_m = _T_346 & _T_344; // @[lsu_bus_intf.scala 188:111] + wire _T_350 = ~ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 189:72] + wire _T_351 = ld_byte_hit_hi[0] | _T_350; // @[lsu_bus_intf.scala 189:70] + wire _T_354 = ~ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 189:72] + wire _T_355 = ld_byte_hit_hi[1] | _T_354; // @[lsu_bus_intf.scala 189:70] + wire _T_358 = ~ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 189:72] + wire _T_359 = ld_byte_hit_hi[2] | _T_358; // @[lsu_bus_intf.scala 189:70] + wire _T_362 = ~ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 189:72] + wire _T_363 = ld_byte_hit_hi[3] | _T_362; // @[lsu_bus_intf.scala 189:70] + wire _T_364 = _T_351 & _T_355; // @[lsu_bus_intf.scala 189:111] + wire _T_365 = _T_364 & _T_359; // @[lsu_bus_intf.scala 189:111] + wire ld_full_hit_hi_m = _T_365 & _T_363; // @[lsu_bus_intf.scala 189:111] + wire _T_367 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[lsu_bus_intf.scala 190:47] + wire _T_368 = _T_367 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 190:66] + wire _T_369 = _T_368 & io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 190:84] + wire _T_370 = ~io_is_sideeffects_m; // @[lsu_bus_intf.scala 190:111] + wire [63:0] ld_fwddata_hi = {{32'd0}, _T_328}; // @[lsu_bus_intf.scala 187:27] + wire [63:0] ld_fwddata_lo = {{32'd0}, _T_309}; // @[lsu_bus_intf.scala 186:27] + wire [63:0] _T_374 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58] + wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_bus_intf.scala 191:83] + wire [5:0] _T_376 = 4'h8 * _GEN_3; // @[lsu_bus_intf.scala 191:83] + wire [63:0] ld_fwddata_m = _T_374 >> _T_376; // @[lsu_bus_intf.scala 191:76] + reg lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 195:32] + reg is_sideeffects_r; // @[lsu_bus_intf.scala 199:33] + lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 100:39] + .clock(bus_buffer_clock), + .reset(bus_buffer_reset), + .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn), + .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned), + .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), + .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), + .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), + .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), + .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), + .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), + .io_tlu_busbuff_lsu_imprecise_error_addr_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any), + .io_dctl_busbuff_lsu_nonblock_load_valid_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m), + .io_dctl_busbuff_lsu_nonblock_load_tag_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m), + .io_dctl_busbuff_lsu_nonblock_load_inv_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r), + .io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r), + .io_dctl_busbuff_lsu_nonblock_load_data_valid(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid), + .io_dctl_busbuff_lsu_nonblock_load_data_error(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error), + .io_dctl_busbuff_lsu_nonblock_load_data_tag(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag), + .io_dec_tlu_force_halt(bus_buffer_io_dec_tlu_force_halt), + .io_lsu_c2_r_clk(bus_buffer_io_lsu_c2_r_clk), + .io_lsu_bus_ibuf_c1_clk(bus_buffer_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_buf_c1_clk(bus_buffer_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(bus_buffer_io_lsu_free_c2_clk), + .io_dec_lsu_valid_raw_d(bus_buffer_io_dec_lsu_valid_raw_d), + .io_lsu_pkt_m_valid(bus_buffer_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_load(bus_buffer_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_r_bits_by(bus_buffer_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(bus_buffer_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(bus_buffer_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(bus_buffer_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(bus_buffer_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(bus_buffer_io_lsu_pkt_r_bits_unsign), + .io_lsu_addr_m(bus_buffer_io_lsu_addr_m), + .io_end_addr_m(bus_buffer_io_end_addr_m), + .io_lsu_addr_r(bus_buffer_io_lsu_addr_r), + .io_end_addr_r(bus_buffer_io_end_addr_r), + .io_store_data_r(bus_buffer_io_store_data_r), + .io_no_word_merge_r(bus_buffer_io_no_word_merge_r), + .io_no_dword_merge_r(bus_buffer_io_no_dword_merge_r), + .io_lsu_busreq_m(bus_buffer_io_lsu_busreq_m), + .io_ld_full_hit_m(bus_buffer_io_ld_full_hit_m), + .io_flush_m_up(bus_buffer_io_flush_m_up), + .io_flush_r(bus_buffer_io_flush_r), + .io_lsu_commit_r(bus_buffer_io_lsu_commit_r), + .io_is_sideeffects_r(bus_buffer_io_is_sideeffects_r), + .io_ldst_dual_d(bus_buffer_io_ldst_dual_d), + .io_ldst_dual_m(bus_buffer_io_ldst_dual_m), + .io_ldst_dual_r(bus_buffer_io_ldst_dual_r), + .io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m), + .io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready), + .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), + .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region), + .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), + .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), + .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), + .io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready), + .io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid), + .io_lsu_axi_b_bits_resp(bus_buffer_io_lsu_axi_b_bits_resp), + .io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id), + .io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready), + .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), + .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region), + .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), + .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), + .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), + .io_lsu_axi_r_bits_data(bus_buffer_io_lsu_axi_r_bits_data), + .io_lsu_axi_r_bits_resp(bus_buffer_io_lsu_axi_r_bits_resp), + .io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en), + .io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q), + .io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(bus_buffer_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_full_any(bus_buffer_io_lsu_bus_buffer_full_any), + .io_lsu_bus_buffer_empty_any(bus_buffer_io_lsu_bus_buffer_empty_any), + .io_ld_byte_hit_buf_lo(bus_buffer_io_ld_byte_hit_buf_lo), + .io_ld_byte_hit_buf_hi(bus_buffer_io_ld_byte_hit_buf_hi), + .io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo), + .io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi), + .io_lsu_nonblock_load_data(bus_buffer_io_lsu_nonblock_load_data) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 103:18] + assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 131:51] + assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 131:51] + assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 134:38] + assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 135:38] + assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 136:38] + assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 137:38] + assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 192:27] + assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 133:29] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 143:19] + assign bus_buffer_clock = clock; + assign bus_buffer_reset = reset; + assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 107:51] + assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 108:51] + assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 109:51] + assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 111:51] + assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 112:51] + assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 114:51] + assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 117:27] + assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 117:27] + assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 121:51] + assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 122:51] + assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 123:51] + assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 124:51] + assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 125:51] + assign bus_buffer_io_no_word_merge_r = _T_19 & _T_21; // @[lsu_bus_intf.scala 144:51] + assign bus_buffer_io_no_dword_merge_r = _T_19 & _T_27; // @[lsu_bus_intf.scala 145:51] + assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 127:51] + assign bus_buffer_io_ld_full_hit_m = _T_369 & _T_370; // @[lsu_bus_intf.scala 151:51] + assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 128:51] + assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 129:51] + assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 130:51] + assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 146:51] + assign bus_buffer_io_ldst_dual_d = io_ldst_dual_d; // @[lsu_bus_intf.scala 147:51] + assign bus_buffer_io_ldst_dual_m = io_ldst_dual_m; // @[lsu_bus_intf.scala 148:51] + assign bus_buffer_io_ldst_dual_r = io_ldst_dual_r; // @[lsu_bus_intf.scala 149:51] + assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 150:51] + assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 132:51] + assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 152:51] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + ldst_byteen_r = _RAND_0[3:0]; + _RAND_1 = {1{`RANDOM}}; + lsu_bus_clk_en_q = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + is_sideeffects_r = _RAND_2[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + ldst_byteen_r = 4'h0; + end + if (reset) begin + lsu_bus_clk_en_q = 1'h0; + end + if (reset) begin + is_sideeffects_r = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + ldst_byteen_r <= 4'h0; + end else begin + ldst_byteen_r <= _T_6 | _T_5; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + lsu_bus_clk_en_q <= 1'h0; + end else begin + lsu_bus_clk_en_q <= io_lsu_bus_clk_en; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + is_sideeffects_r <= 1'h0; + end else begin + is_sideeffects_r <= io_is_sideeffects_m; + end + end +endmodule +module lsu( + input clock, + input reset, + input io_clk_override, + input io_lsu_dma_dma_lsc_ctl_dma_dccm_req, + input [31:0] io_lsu_dma_dma_lsc_ctl_dma_mem_addr, + input [2:0] io_lsu_dma_dma_lsc_ctl_dma_mem_sz, + input io_lsu_dma_dma_lsc_ctl_dma_mem_write, + input [63:0] io_lsu_dma_dma_lsc_ctl_dma_mem_wdata, + input [31:0] io_lsu_dma_dma_dccm_ctl_dma_mem_addr, + input [63:0] io_lsu_dma_dma_dccm_ctl_dma_mem_wdata, + output io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid, + output io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error, + output [2:0] io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag, + output [63:0] io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata, + output io_lsu_dma_dccm_ready, + input [2:0] io_lsu_dma_dma_mem_tag, + output io_lsu_pic_picm_wren, + output io_lsu_pic_picm_rden, + output io_lsu_pic_picm_mken, + output [31:0] io_lsu_pic_picm_rdaddr, + output [31:0] io_lsu_pic_picm_wraddr, + output [31:0] io_lsu_pic_picm_wr_data, + input [31:0] io_lsu_pic_picm_rd_data, + input [31:0] io_lsu_exu_exu_lsu_rs1_d, + input [31:0] io_lsu_exu_exu_lsu_rs2_d, + output [31:0] io_lsu_exu_lsu_result_m, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, + input io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, + output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag, + output io_dccm_wren, + output io_dccm_rden, + output [15:0] io_dccm_wr_addr_lo, + output [15:0] io_dccm_wr_addr_hi, + output [15:0] io_dccm_rd_addr_lo, + output [15:0] io_dccm_rd_addr_hi, + output [38:0] io_dccm_wr_data_lo, + output [38:0] io_dccm_wr_data_hi, + input [38:0] io_dccm_rd_data_lo, + input [38:0] io_dccm_rd_data_hi, + output io_lsu_tlu_lsu_pmu_load_external_m, + output io_lsu_tlu_lsu_pmu_store_external_m, + input io_axi_aw_ready, + output io_axi_aw_valid, + output [2:0] io_axi_aw_bits_id, + output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, + output [7:0] io_axi_aw_bits_len, + output [2:0] io_axi_aw_bits_size, + output [1:0] io_axi_aw_bits_burst, + output io_axi_aw_bits_lock, + output [3:0] io_axi_aw_bits_cache, + output [2:0] io_axi_aw_bits_prot, + output [3:0] io_axi_aw_bits_qos, + input io_axi_w_ready, + output io_axi_w_valid, + output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, + output io_axi_w_bits_last, + output io_axi_b_ready, + input io_axi_b_valid, + input [1:0] io_axi_b_bits_resp, + input [2:0] io_axi_b_bits_id, + input io_axi_ar_ready, + output io_axi_ar_valid, + output [2:0] io_axi_ar_bits_id, + output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, + output [7:0] io_axi_ar_bits_len, + output [2:0] io_axi_ar_bits_size, + output [1:0] io_axi_ar_bits_burst, + output io_axi_ar_bits_lock, + output [3:0] io_axi_ar_bits_cache, + output [2:0] io_axi_ar_bits_prot, + output [3:0] io_axi_ar_bits_qos, + output io_axi_r_ready, + input io_axi_r_valid, + input [2:0] io_axi_r_bits_id, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + input io_axi_r_bits_last, + input io_dec_tlu_flush_lower_r, + input io_dec_tlu_i0_kill_writeb_r, + input io_dec_tlu_force_halt, + input io_dec_tlu_core_ecc_disable, + input [11:0] io_dec_lsu_offset_d, + input io_lsu_p_valid, + input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_stack, + input io_lsu_p_bits_by, + input io_lsu_p_bits_half, + input io_lsu_p_bits_word, + input io_lsu_p_bits_dword, + input io_lsu_p_bits_load, + input io_lsu_p_bits_store, + input io_lsu_p_bits_unsign, + input io_lsu_p_bits_dma, + input io_lsu_p_bits_store_data_bypass_d, + input io_lsu_p_bits_load_ldst_bypass_d, + input io_lsu_p_bits_store_data_bypass_m, + input io_trigger_pkt_any_0_select, + input io_trigger_pkt_any_0_match_pkt, + input io_trigger_pkt_any_0_store, + input io_trigger_pkt_any_0_load, + input io_trigger_pkt_any_0_execute, + input io_trigger_pkt_any_0_m, + input [31:0] io_trigger_pkt_any_0_tdata2, + input io_trigger_pkt_any_1_select, + input io_trigger_pkt_any_1_match_pkt, + input io_trigger_pkt_any_1_store, + input io_trigger_pkt_any_1_load, + input io_trigger_pkt_any_1_execute, + input io_trigger_pkt_any_1_m, + input [31:0] io_trigger_pkt_any_1_tdata2, + input io_trigger_pkt_any_2_select, + input io_trigger_pkt_any_2_match_pkt, + input io_trigger_pkt_any_2_store, + input io_trigger_pkt_any_2_load, + input io_trigger_pkt_any_2_execute, + input io_trigger_pkt_any_2_m, + input [31:0] io_trigger_pkt_any_2_tdata2, + input io_trigger_pkt_any_3_select, + input io_trigger_pkt_any_3_match_pkt, + input io_trigger_pkt_any_3_store, + input io_trigger_pkt_any_3_load, + input io_trigger_pkt_any_3_execute, + input io_trigger_pkt_any_3_m, + input [31:0] io_trigger_pkt_any_3_tdata2, + input io_dec_lsu_valid_raw_d, + input [31:0] io_dec_tlu_mrac_ff, + output [31:0] io_lsu_result_corr_r, + output io_lsu_load_stall_any, + output io_lsu_store_stall_any, + output io_lsu_fastint_stall_any, + output io_lsu_idle_any, + output io_lsu_active, + output [30:0] io_lsu_fir_addr, + output [1:0] io_lsu_fir_error, + output io_lsu_single_ecc_error_incr, + output io_lsu_error_pkt_r_valid, + output io_lsu_error_pkt_r_bits_single_ecc_error, + output io_lsu_error_pkt_r_bits_inst_type, + output io_lsu_error_pkt_r_bits_exc_type, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, + output io_lsu_pmu_misaligned_m, + output [3:0] io_lsu_trigger_match_m, + input io_lsu_bus_clk_en, + input io_scan_mode, + input io_active_clk, + output [31:0] io_lsu_nonblock_load_data +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire lsu_lsc_ctl_clock; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_reset; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_clk_override; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_c1_m_clk; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_c1_r_clk; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_c2_m_clk; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_c2_r_clk; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_store_c1_m_clk; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_double_ecc_error_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_flush_m_up; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_flush_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_ldst_dual_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_exu_lsu_result_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_valid; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_fast_int; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_by; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_half; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_word; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_dword; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_load; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_store; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_unsign; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_dma; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_dec_lsu_valid_raw_d; // @[lsu.scala 72:30] + wire [11:0] lsu_lsc_ctl_io_dec_lsu_offset_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_picm_mask_data_m; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_bus_read_data_m; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_d; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_dec_tlu_mrac_ff; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 72:30] + wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 72:30] + wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 72:30] + wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 72:30] + wire [31:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 72:30] + wire [2:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 72:30] + wire [63:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_by; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_half; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_dword; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 72:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 72:30] + wire dccm_ctl_clock; // @[lsu.scala 76:30] + wire dccm_ctl_reset; // @[lsu.scala 76:30] + wire dccm_ctl_io_clk_override; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_c2_m_clk; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_free_c2_clk; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_store_c1_r_clk; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_dccm_d; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_dccm_m; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_dccm_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_pic_d; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_pic_m; // @[lsu.scala 76:30] + wire dccm_ctl_io_addr_in_pic_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_raw_fwd_lo_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_raw_fwd_hi_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_commit_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_ldst_dual_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_addr_d; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_lsu_addr_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_addr_r; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_end_addr_d; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_end_addr_m; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_end_addr_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_stbuf_reqvld_any; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_stbuf_addr_any; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_stbuf_data_any; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_stbuf_ecc_any; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_stbuf_fwddata_hi_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_stbuf_fwddata_lo_m; // @[lsu.scala 76:30] + wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 76:30] + wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_single_ecc_error_hi_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_single_ecc_error_lo_r; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_sec_data_hi_r_ff; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_sec_data_lo_r_ff; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_ld_data_m; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_double_ecc_error_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_sec_data_hi_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_sec_data_lo_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_data_m; // @[lsu.scala 76:30] + wire dccm_ctl_io_dma_dccm_wen; // @[lsu.scala 76:30] + wire dccm_ctl_io_dma_pic_wen; // @[lsu.scala 76:30] + wire [2:0] dccm_ctl_io_dma_mem_tag_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_dma_dccm_wdata_lo; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_dma_dccm_wdata_hi; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 76:30] + wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_data_hi_r; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_data_lo_r; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_store_data_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 76:30] + wire dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 76:30] + wire [63:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 76:30] + wire dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 76:30] + wire dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 76:30] + wire [2:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 76:30] + wire [63:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 76:30] + wire dccm_ctl_io_dccm_wren; // @[lsu.scala 76:30] + wire dccm_ctl_io_dccm_rden; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 76:30] + wire [15:0] dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 76:30] + wire [38:0] dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 76:30] + wire [38:0] dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 76:30] + wire [38:0] dccm_ctl_io_dccm_rd_data_lo; // @[lsu.scala 76:30] + wire [38:0] dccm_ctl_io_dccm_rd_data_hi; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 76:30] + wire dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 76:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_rd_data; // @[lsu.scala 76:30] + wire stbuf_clock; // @[lsu.scala 77:30] + wire stbuf_reset; // @[lsu.scala 77:30] + wire stbuf_io_lsu_stbuf_c1_clk; // @[lsu.scala 77:30] + wire stbuf_io_lsu_free_c2_clk; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_m_valid; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_m_bits_store; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_m_bits_dma; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_valid; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_by; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_half; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_word; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_dword; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_store; // @[lsu.scala 77:30] + wire stbuf_io_lsu_pkt_r_bits_dma; // @[lsu.scala 77:30] + wire stbuf_io_store_stbuf_reqvld_r; // @[lsu.scala 77:30] + wire stbuf_io_lsu_commit_r; // @[lsu.scala 77:30] + wire stbuf_io_dec_lsu_valid_raw_d; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_store_data_hi_r; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_store_data_lo_r; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_store_datafn_hi_r; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_store_datafn_lo_r; // @[lsu.scala 77:30] + wire stbuf_io_lsu_stbuf_commit_any; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_lsu_addr_m; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_lsu_addr_r; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_end_addr_m; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_end_addr_r; // @[lsu.scala 77:30] + wire stbuf_io_ldst_dual_d; // @[lsu.scala 77:30] + wire stbuf_io_ldst_dual_m; // @[lsu.scala 77:30] + wire stbuf_io_ldst_dual_r; // @[lsu.scala 77:30] + wire stbuf_io_addr_in_dccm_m; // @[lsu.scala 77:30] + wire stbuf_io_addr_in_dccm_r; // @[lsu.scala 77:30] + wire stbuf_io_stbuf_reqvld_any; // @[lsu.scala 77:30] + wire stbuf_io_stbuf_reqvld_flushed_any; // @[lsu.scala 77:30] + wire [15:0] stbuf_io_stbuf_addr_any; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_stbuf_data_any; // @[lsu.scala 77:30] + wire stbuf_io_lsu_stbuf_full_any; // @[lsu.scala 77:30] + wire stbuf_io_ldst_stbuf_reqvld_r; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 77:30] + wire [31:0] stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 77:30] + wire [3:0] stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 77:30] + wire [3:0] stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 77:30] + wire ecc_clock; // @[lsu.scala 78:30] + wire ecc_reset; // @[lsu.scala 78:30] + wire ecc_io_lsu_c2_r_clk; // @[lsu.scala 78:30] + wire ecc_io_clk_override; // @[lsu.scala 78:30] + wire ecc_io_lsu_pkt_m_valid; // @[lsu.scala 78:30] + wire ecc_io_lsu_pkt_m_bits_load; // @[lsu.scala 78:30] + wire ecc_io_lsu_pkt_m_bits_store; // @[lsu.scala 78:30] + wire ecc_io_lsu_pkt_m_bits_dma; // @[lsu.scala 78:30] + wire [31:0] ecc_io_stbuf_data_any; // @[lsu.scala 78:30] + wire ecc_io_dec_tlu_core_ecc_disable; // @[lsu.scala 78:30] + wire [15:0] ecc_io_lsu_addr_m; // @[lsu.scala 78:30] + wire [15:0] ecc_io_end_addr_m; // @[lsu.scala 78:30] + wire [31:0] ecc_io_dccm_rdata_hi_m; // @[lsu.scala 78:30] + wire [31:0] ecc_io_dccm_rdata_lo_m; // @[lsu.scala 78:30] + wire [6:0] ecc_io_dccm_data_ecc_hi_m; // @[lsu.scala 78:30] + wire [6:0] ecc_io_dccm_data_ecc_lo_m; // @[lsu.scala 78:30] + wire ecc_io_ld_single_ecc_error_r; // @[lsu.scala 78:30] + wire ecc_io_ld_single_ecc_error_r_ff; // @[lsu.scala 78:30] + wire ecc_io_lsu_dccm_rden_m; // @[lsu.scala 78:30] + wire ecc_io_addr_in_dccm_m; // @[lsu.scala 78:30] + wire ecc_io_dma_dccm_wen; // @[lsu.scala 78:30] + wire [31:0] ecc_io_dma_dccm_wdata_lo; // @[lsu.scala 78:30] + wire [31:0] ecc_io_dma_dccm_wdata_hi; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_hi_r; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_lo_r; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_hi_m; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_lo_m; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_hi_r_ff; // @[lsu.scala 78:30] + wire [31:0] ecc_io_sec_data_lo_r_ff; // @[lsu.scala 78:30] + wire [6:0] ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 78:30] + wire [6:0] ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 78:30] + wire [6:0] ecc_io_stbuf_ecc_any; // @[lsu.scala 78:30] + wire [6:0] ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 78:30] + wire [6:0] ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 78:30] + wire ecc_io_single_ecc_error_hi_r; // @[lsu.scala 78:30] + wire ecc_io_single_ecc_error_lo_r; // @[lsu.scala 78:30] + wire ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 78:30] + wire ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 78:30] + wire ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 78:30] + wire ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 78:30] + wire trigger_io_trigger_pkt_any_0_select; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_0_store; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_0_load; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_0_m; // @[lsu.scala 79:30] + wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_1_select; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_1_store; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_1_load; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_1_m; // @[lsu.scala 79:30] + wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_2_select; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_2_store; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_2_load; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_2_m; // @[lsu.scala 79:30] + wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_3_select; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_3_store; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_3_load; // @[lsu.scala 79:30] + wire trigger_io_trigger_pkt_any_3_m; // @[lsu.scala 79:30] + wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_valid; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_bits_half; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_bits_word; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_bits_load; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_bits_store; // @[lsu.scala 79:30] + wire trigger_io_lsu_pkt_m_bits_dma; // @[lsu.scala 79:30] + wire [31:0] trigger_io_lsu_addr_m; // @[lsu.scala 79:30] + wire [31:0] trigger_io_store_data_m; // @[lsu.scala 79:30] + wire [3:0] trigger_io_lsu_trigger_match_m; // @[lsu.scala 79:30] + wire clkdomain_clock; // @[lsu.scala 80:30] + wire clkdomain_io_clk_override; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_busreq_r; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_buffer_pend_any; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_buffer_empty_any; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_clk_en; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_obuf_c1_clken; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_busm_clken; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 80:30] + wire clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 80:30] + wire bus_intf_clock; // @[lsu.scala 81:30] + wire bus_intf_reset; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 81:30] + wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_c1_r_clk; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_c2_r_clk; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_buf_c1_clk; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_free_c2_clk; // @[lsu.scala 81:30] + wire bus_intf_io_active_clk; // @[lsu.scala 81:30] + wire bus_intf_io_axi_aw_ready; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 81:30] + wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 81:30] + wire bus_intf_io_axi_w_ready; // @[lsu.scala 81:30] + wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 81:30] + wire bus_intf_io_axi_b_valid; // @[lsu.scala 81:30] + wire [1:0] bus_intf_io_axi_b_bits_resp; // @[lsu.scala 81:30] + wire [2:0] bus_intf_io_axi_b_bits_id; // @[lsu.scala 81:30] + wire bus_intf_io_axi_ar_ready; // @[lsu.scala 81:30] + wire bus_intf_io_axi_ar_valid; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 81:30] + wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 81:30] + wire bus_intf_io_axi_r_valid; // @[lsu.scala 81:30] + wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 81:30] + wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 81:30] + wire [1:0] bus_intf_io_axi_r_bits_resp; // @[lsu.scala 81:30] + wire bus_intf_io_dec_lsu_valid_raw_d; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_busreq_m; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_m_valid; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_m_bits_by; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_m_bits_half; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_m_bits_word; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_m_bits_load; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_valid; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_by; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_half; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_word; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_load; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_store; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_lsu_addr_m; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_lsu_addr_r; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_end_addr_m; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_end_addr_r; // @[lsu.scala 81:30] + wire bus_intf_io_ldst_dual_d; // @[lsu.scala 81:30] + wire bus_intf_io_ldst_dual_m; // @[lsu.scala 81:30] + wire bus_intf_io_ldst_dual_r; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_store_data_r; // @[lsu.scala 81:30] + wire bus_intf_io_dec_tlu_force_halt; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_commit_r; // @[lsu.scala 81:30] + wire bus_intf_io_is_sideeffects_m; // @[lsu.scala 81:30] + wire bus_intf_io_flush_m_up; // @[lsu.scala 81:30] + wire bus_intf_io_flush_r; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_busreq_r; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_bus_read_data_m; // @[lsu.scala 81:30] + wire [31:0] bus_intf_io_lsu_nonblock_load_data; // @[lsu.scala 81:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 81:30] + wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 81:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 81:30] + wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 81:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 81:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 81:30] + wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 81:30] + wire bus_intf_io_lsu_bus_clk_en; // @[lsu.scala 81:30] + wire _T = stbuf_io_lsu_stbuf_full_any | bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 87:57] + wire _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 94:58] + wire _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[lsu.scala 94:56] + wire _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 94:126] + wire _T_6 = _T_4 & _T_5; // @[lsu.scala 94:93] + wire ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 94:158] + wire _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[lsu.scala 95:53] + wire _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 95:71] + wire _T_10 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 96:58] + wire _T_11 = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 96:97] + wire [5:0] _T_15 = {io_lsu_dma_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] + wire [63:0] dma_dccm_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata >> _T_15; // @[lsu.scala 98:58] + wire _T_21 = ~lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 109:130] + wire _T_22 = lsu_lsc_ctl_io_lsu_pkt_r_valid & _T_21; // @[lsu.scala 109:128] + wire _T_23 = _T_4 | _T_22; // @[lsu.scala 109:94] + wire _T_24 = ~_T_23; // @[lsu.scala 109:22] + wire _T_26 = lsu_lsc_ctl_io_lsu_pkt_m_valid | lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 110:53] + wire _T_27 = _T_26 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 110:86] + wire _T_28 = ~bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 110:128] + wire _T_30 = lsu_lsc_ctl_io_lsu_pkt_r_valid & lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 112:61] + wire _T_31 = _T_30 & lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 112:99] + wire _T_32 = ~io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 112:133] + wire _T_33 = _T_31 & _T_32; // @[lsu.scala 112:131] + wire _T_35 = lsu_lsc_ctl_io_lsu_pkt_r_bits_by | lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 112:217] + wire _T_36 = ~ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 112:257] + wire _T_37 = _T_35 & _T_36; // @[lsu.scala 112:255] + wire _T_38 = _T_21 | _T_37; // @[lsu.scala 112:180] + wire _T_39 = lsu_lsc_ctl_io_lsu_pkt_m_bits_load | lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 114:90] + wire _T_43 = _T_39 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 116:131] + wire _T_44 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_43; // @[lsu.scala 116:53] + wire _T_45 = ~io_dec_tlu_flush_lower_r; // @[lsu.scala 116:167] + wire _T_46 = _T_44 & _T_45; // @[lsu.scala 116:165] + wire _T_47 = ~lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 116:181] + wire _T_48 = _T_46 & _T_47; // @[lsu.scala 116:179] + wire _T_49 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 116:209] + wire _T_51 = lsu_lsc_ctl_io_lsu_pkt_m_bits_half & lsu_lsc_ctl_io_lsu_addr_m[0]; // @[lsu.scala 120:100] + wire _T_53 = |lsu_lsc_ctl_io_lsu_addr_m[1:0]; // @[lsu.scala 120:203] + wire _T_54 = lsu_lsc_ctl_io_lsu_pkt_m_bits_word & _T_53; // @[lsu.scala 120:170] + wire _T_55 = _T_51 | _T_54; // @[lsu.scala 120:132] + wire _T_57 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 121:73] + wire _T_59 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 122:73] + wire _T_98 = lsu_lsc_ctl_io_addr_external_m & lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 333:119] + wire [31:0] _T_100 = _T_98 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 348:16] + wire [31:0] _T_103 = lsu_busreq_r ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + reg [2:0] dma_mem_tag_m; // @[lsu.scala 352:67] + reg lsu_raw_fwd_hi_r; // @[lsu.scala 353:67] + reg lsu_raw_fwd_lo_r; // @[lsu.scala 354:67] + lsu_lsc_ctl lsu_lsc_ctl ( // @[lsu.scala 72:30] + .clock(lsu_lsc_ctl_clock), + .reset(lsu_lsc_ctl_reset), + .io_clk_override(lsu_lsc_ctl_io_clk_override), + .io_lsu_c1_m_clk(lsu_lsc_ctl_io_lsu_c1_m_clk), + .io_lsu_c1_r_clk(lsu_lsc_ctl_io_lsu_c1_r_clk), + .io_lsu_c2_m_clk(lsu_lsc_ctl_io_lsu_c2_m_clk), + .io_lsu_c2_r_clk(lsu_lsc_ctl_io_lsu_c2_r_clk), + .io_lsu_store_c1_m_clk(lsu_lsc_ctl_io_lsu_store_c1_m_clk), + .io_lsu_ld_data_corr_r(lsu_lsc_ctl_io_lsu_ld_data_corr_r), + .io_lsu_single_ecc_error_r(lsu_lsc_ctl_io_lsu_single_ecc_error_r), + .io_lsu_double_ecc_error_r(lsu_lsc_ctl_io_lsu_double_ecc_error_r), + .io_lsu_ld_data_m(lsu_lsc_ctl_io_lsu_ld_data_m), + .io_lsu_single_ecc_error_m(lsu_lsc_ctl_io_lsu_single_ecc_error_m), + .io_lsu_double_ecc_error_m(lsu_lsc_ctl_io_lsu_double_ecc_error_m), + .io_flush_m_up(lsu_lsc_ctl_io_flush_m_up), + .io_flush_r(lsu_lsc_ctl_io_flush_r), + .io_ldst_dual_d(lsu_lsc_ctl_io_ldst_dual_d), + .io_lsu_exu_exu_lsu_rs1_d(lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d), + .io_lsu_exu_exu_lsu_rs2_d(lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d), + .io_lsu_exu_lsu_result_m(lsu_lsc_ctl_io_lsu_exu_lsu_result_m), + .io_lsu_p_valid(lsu_lsc_ctl_io_lsu_p_valid), + .io_lsu_p_bits_fast_int(lsu_lsc_ctl_io_lsu_p_bits_fast_int), + .io_lsu_p_bits_by(lsu_lsc_ctl_io_lsu_p_bits_by), + .io_lsu_p_bits_half(lsu_lsc_ctl_io_lsu_p_bits_half), + .io_lsu_p_bits_word(lsu_lsc_ctl_io_lsu_p_bits_word), + .io_lsu_p_bits_dword(lsu_lsc_ctl_io_lsu_p_bits_dword), + .io_lsu_p_bits_load(lsu_lsc_ctl_io_lsu_p_bits_load), + .io_lsu_p_bits_store(lsu_lsc_ctl_io_lsu_p_bits_store), + .io_lsu_p_bits_unsign(lsu_lsc_ctl_io_lsu_p_bits_unsign), + .io_lsu_p_bits_dma(lsu_lsc_ctl_io_lsu_p_bits_dma), + .io_lsu_p_bits_store_data_bypass_d(lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d), + .io_lsu_p_bits_load_ldst_bypass_d(lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d), + .io_lsu_p_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m), + .io_dec_lsu_valid_raw_d(lsu_lsc_ctl_io_dec_lsu_valid_raw_d), + .io_dec_lsu_offset_d(lsu_lsc_ctl_io_dec_lsu_offset_d), + .io_picm_mask_data_m(lsu_lsc_ctl_io_picm_mask_data_m), + .io_bus_read_data_m(lsu_lsc_ctl_io_bus_read_data_m), + .io_lsu_result_corr_r(lsu_lsc_ctl_io_lsu_result_corr_r), + .io_lsu_addr_d(lsu_lsc_ctl_io_lsu_addr_d), + .io_lsu_addr_m(lsu_lsc_ctl_io_lsu_addr_m), + .io_lsu_addr_r(lsu_lsc_ctl_io_lsu_addr_r), + .io_end_addr_d(lsu_lsc_ctl_io_end_addr_d), + .io_end_addr_m(lsu_lsc_ctl_io_end_addr_m), + .io_end_addr_r(lsu_lsc_ctl_io_end_addr_r), + .io_store_data_m(lsu_lsc_ctl_io_store_data_m), + .io_dec_tlu_mrac_ff(lsu_lsc_ctl_io_dec_tlu_mrac_ff), + .io_lsu_exc_m(lsu_lsc_ctl_io_lsu_exc_m), + .io_is_sideeffects_m(lsu_lsc_ctl_io_is_sideeffects_m), + .io_lsu_commit_r(lsu_lsc_ctl_io_lsu_commit_r), + .io_lsu_single_ecc_error_incr(lsu_lsc_ctl_io_lsu_single_ecc_error_incr), + .io_lsu_error_pkt_r_valid(lsu_lsc_ctl_io_lsu_error_pkt_r_valid), + .io_lsu_error_pkt_r_bits_single_ecc_error(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error), + .io_lsu_error_pkt_r_bits_inst_type(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type), + .io_lsu_error_pkt_r_bits_exc_type(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type), + .io_lsu_error_pkt_r_bits_mscause(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause), + .io_lsu_error_pkt_r_bits_addr(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr), + .io_lsu_fir_addr(lsu_lsc_ctl_io_lsu_fir_addr), + .io_lsu_fir_error(lsu_lsc_ctl_io_lsu_fir_error), + .io_addr_in_dccm_d(lsu_lsc_ctl_io_addr_in_dccm_d), + .io_addr_in_dccm_m(lsu_lsc_ctl_io_addr_in_dccm_m), + .io_addr_in_dccm_r(lsu_lsc_ctl_io_addr_in_dccm_r), + .io_addr_in_pic_d(lsu_lsc_ctl_io_addr_in_pic_d), + .io_addr_in_pic_m(lsu_lsc_ctl_io_addr_in_pic_m), + .io_addr_in_pic_r(lsu_lsc_ctl_io_addr_in_pic_r), + .io_addr_external_m(lsu_lsc_ctl_io_addr_external_m), + .io_dma_lsc_ctl_dma_dccm_req(lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req), + .io_dma_lsc_ctl_dma_mem_addr(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr), + .io_dma_lsc_ctl_dma_mem_sz(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz), + .io_dma_lsc_ctl_dma_mem_write(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write), + .io_dma_lsc_ctl_dma_mem_wdata(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata), + .io_lsu_pkt_d_valid(lsu_lsc_ctl_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int), + .io_lsu_pkt_d_bits_by(lsu_lsc_ctl_io_lsu_pkt_d_bits_by), + .io_lsu_pkt_d_bits_half(lsu_lsc_ctl_io_lsu_pkt_d_bits_half), + .io_lsu_pkt_d_bits_word(lsu_lsc_ctl_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_dword(lsu_lsc_ctl_io_lsu_pkt_d_bits_dword), + .io_lsu_pkt_d_bits_load(lsu_lsc_ctl_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(lsu_lsc_ctl_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign), + .io_lsu_pkt_d_bits_dma(lsu_lsc_ctl_io_lsu_pkt_d_bits_dma), + .io_lsu_pkt_d_bits_store_data_bypass_d(lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d), + .io_lsu_pkt_d_bits_load_ldst_bypass_d(lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d), + .io_lsu_pkt_d_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m), + .io_lsu_pkt_m_valid(lsu_lsc_ctl_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int), + .io_lsu_pkt_m_bits_by(lsu_lsc_ctl_io_lsu_pkt_m_bits_by), + .io_lsu_pkt_m_bits_half(lsu_lsc_ctl_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(lsu_lsc_ctl_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_dword(lsu_lsc_ctl_io_lsu_pkt_m_bits_dword), + .io_lsu_pkt_m_bits_load(lsu_lsc_ctl_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(lsu_lsc_ctl_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign), + .io_lsu_pkt_m_bits_dma(lsu_lsc_ctl_io_lsu_pkt_m_bits_dma), + .io_lsu_pkt_m_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m), + .io_lsu_pkt_r_valid(lsu_lsc_ctl_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(lsu_lsc_ctl_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(lsu_lsc_ctl_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(lsu_lsc_ctl_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_dword(lsu_lsc_ctl_io_lsu_pkt_r_bits_dword), + .io_lsu_pkt_r_bits_load(lsu_lsc_ctl_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(lsu_lsc_ctl_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign), + .io_lsu_pkt_r_bits_dma(lsu_lsc_ctl_io_lsu_pkt_r_bits_dma) + ); + lsu_dccm_ctl dccm_ctl ( // @[lsu.scala 76:30] + .clock(dccm_ctl_clock), + .reset(dccm_ctl_reset), + .io_clk_override(dccm_ctl_io_clk_override), + .io_lsu_c2_m_clk(dccm_ctl_io_lsu_c2_m_clk), + .io_lsu_free_c2_clk(dccm_ctl_io_lsu_free_c2_clk), + .io_lsu_store_c1_r_clk(dccm_ctl_io_lsu_store_c1_r_clk), + .io_lsu_pkt_d_valid(dccm_ctl_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_word(dccm_ctl_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_dword(dccm_ctl_io_lsu_pkt_d_bits_dword), + .io_lsu_pkt_d_bits_load(dccm_ctl_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(dccm_ctl_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_dma(dccm_ctl_io_lsu_pkt_d_bits_dma), + .io_lsu_pkt_m_valid(dccm_ctl_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_by(dccm_ctl_io_lsu_pkt_m_bits_by), + .io_lsu_pkt_m_bits_half(dccm_ctl_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(dccm_ctl_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_load(dccm_ctl_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(dccm_ctl_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(dccm_ctl_io_lsu_pkt_m_bits_dma), + .io_lsu_pkt_r_valid(dccm_ctl_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(dccm_ctl_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(dccm_ctl_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(dccm_ctl_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(dccm_ctl_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(dccm_ctl_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_dma(dccm_ctl_io_lsu_pkt_r_bits_dma), + .io_addr_in_dccm_d(dccm_ctl_io_addr_in_dccm_d), + .io_addr_in_dccm_m(dccm_ctl_io_addr_in_dccm_m), + .io_addr_in_dccm_r(dccm_ctl_io_addr_in_dccm_r), + .io_addr_in_pic_d(dccm_ctl_io_addr_in_pic_d), + .io_addr_in_pic_m(dccm_ctl_io_addr_in_pic_m), + .io_addr_in_pic_r(dccm_ctl_io_addr_in_pic_r), + .io_lsu_raw_fwd_lo_r(dccm_ctl_io_lsu_raw_fwd_lo_r), + .io_lsu_raw_fwd_hi_r(dccm_ctl_io_lsu_raw_fwd_hi_r), + .io_lsu_commit_r(dccm_ctl_io_lsu_commit_r), + .io_ldst_dual_m(dccm_ctl_io_ldst_dual_m), + .io_lsu_addr_d(dccm_ctl_io_lsu_addr_d), + .io_lsu_addr_m(dccm_ctl_io_lsu_addr_m), + .io_lsu_addr_r(dccm_ctl_io_lsu_addr_r), + .io_end_addr_d(dccm_ctl_io_end_addr_d), + .io_end_addr_m(dccm_ctl_io_end_addr_m), + .io_end_addr_r(dccm_ctl_io_end_addr_r), + .io_stbuf_reqvld_any(dccm_ctl_io_stbuf_reqvld_any), + .io_stbuf_addr_any(dccm_ctl_io_stbuf_addr_any), + .io_stbuf_data_any(dccm_ctl_io_stbuf_data_any), + .io_stbuf_ecc_any(dccm_ctl_io_stbuf_ecc_any), + .io_stbuf_fwddata_hi_m(dccm_ctl_io_stbuf_fwddata_hi_m), + .io_stbuf_fwddata_lo_m(dccm_ctl_io_stbuf_fwddata_lo_m), + .io_stbuf_fwdbyteen_lo_m(dccm_ctl_io_stbuf_fwdbyteen_lo_m), + .io_stbuf_fwdbyteen_hi_m(dccm_ctl_io_stbuf_fwdbyteen_hi_m), + .io_lsu_ld_data_corr_r(dccm_ctl_io_lsu_ld_data_corr_r), + .io_lsu_double_ecc_error_r(dccm_ctl_io_lsu_double_ecc_error_r), + .io_single_ecc_error_hi_r(dccm_ctl_io_single_ecc_error_hi_r), + .io_single_ecc_error_lo_r(dccm_ctl_io_single_ecc_error_lo_r), + .io_sec_data_hi_r_ff(dccm_ctl_io_sec_data_hi_r_ff), + .io_sec_data_lo_r_ff(dccm_ctl_io_sec_data_lo_r_ff), + .io_sec_data_ecc_hi_r_ff(dccm_ctl_io_sec_data_ecc_hi_r_ff), + .io_sec_data_ecc_lo_r_ff(dccm_ctl_io_sec_data_ecc_lo_r_ff), + .io_dccm_rdata_hi_m(dccm_ctl_io_dccm_rdata_hi_m), + .io_dccm_rdata_lo_m(dccm_ctl_io_dccm_rdata_lo_m), + .io_dccm_data_ecc_hi_m(dccm_ctl_io_dccm_data_ecc_hi_m), + .io_dccm_data_ecc_lo_m(dccm_ctl_io_dccm_data_ecc_lo_m), + .io_lsu_ld_data_m(dccm_ctl_io_lsu_ld_data_m), + .io_lsu_double_ecc_error_m(dccm_ctl_io_lsu_double_ecc_error_m), + .io_sec_data_hi_m(dccm_ctl_io_sec_data_hi_m), + .io_sec_data_lo_m(dccm_ctl_io_sec_data_lo_m), + .io_store_data_m(dccm_ctl_io_store_data_m), + .io_dma_dccm_wen(dccm_ctl_io_dma_dccm_wen), + .io_dma_pic_wen(dccm_ctl_io_dma_pic_wen), + .io_dma_mem_tag_m(dccm_ctl_io_dma_mem_tag_m), + .io_dma_dccm_wdata_lo(dccm_ctl_io_dma_dccm_wdata_lo), + .io_dma_dccm_wdata_hi(dccm_ctl_io_dma_dccm_wdata_hi), + .io_dma_dccm_wdata_ecc_hi(dccm_ctl_io_dma_dccm_wdata_ecc_hi), + .io_dma_dccm_wdata_ecc_lo(dccm_ctl_io_dma_dccm_wdata_ecc_lo), + .io_store_data_hi_r(dccm_ctl_io_store_data_hi_r), + .io_store_data_lo_r(dccm_ctl_io_store_data_lo_r), + .io_store_datafn_hi_r(dccm_ctl_io_store_datafn_hi_r), + .io_store_datafn_lo_r(dccm_ctl_io_store_datafn_lo_r), + .io_store_data_r(dccm_ctl_io_store_data_r), + .io_ld_single_ecc_error_r(dccm_ctl_io_ld_single_ecc_error_r), + .io_ld_single_ecc_error_r_ff(dccm_ctl_io_ld_single_ecc_error_r_ff), + .io_picm_mask_data_m(dccm_ctl_io_picm_mask_data_m), + .io_lsu_stbuf_commit_any(dccm_ctl_io_lsu_stbuf_commit_any), + .io_lsu_dccm_rden_m(dccm_ctl_io_lsu_dccm_rden_m), + .io_dma_dccm_ctl_dma_mem_addr(dccm_ctl_io_dma_dccm_ctl_dma_mem_addr), + .io_dma_dccm_ctl_dma_mem_wdata(dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata), + .io_dma_dccm_ctl_dccm_dma_rvalid(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid), + .io_dma_dccm_ctl_dccm_dma_ecc_error(dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error), + .io_dma_dccm_ctl_dccm_dma_rtag(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag), + .io_dma_dccm_ctl_dccm_dma_rdata(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata), + .io_dccm_wren(dccm_ctl_io_dccm_wren), + .io_dccm_rden(dccm_ctl_io_dccm_rden), + .io_dccm_wr_addr_lo(dccm_ctl_io_dccm_wr_addr_lo), + .io_dccm_wr_addr_hi(dccm_ctl_io_dccm_wr_addr_hi), + .io_dccm_rd_addr_lo(dccm_ctl_io_dccm_rd_addr_lo), + .io_dccm_rd_addr_hi(dccm_ctl_io_dccm_rd_addr_hi), + .io_dccm_wr_data_lo(dccm_ctl_io_dccm_wr_data_lo), + .io_dccm_wr_data_hi(dccm_ctl_io_dccm_wr_data_hi), + .io_dccm_rd_data_lo(dccm_ctl_io_dccm_rd_data_lo), + .io_dccm_rd_data_hi(dccm_ctl_io_dccm_rd_data_hi), + .io_lsu_pic_picm_wren(dccm_ctl_io_lsu_pic_picm_wren), + .io_lsu_pic_picm_rden(dccm_ctl_io_lsu_pic_picm_rden), + .io_lsu_pic_picm_mken(dccm_ctl_io_lsu_pic_picm_mken), + .io_lsu_pic_picm_rdaddr(dccm_ctl_io_lsu_pic_picm_rdaddr), + .io_lsu_pic_picm_wraddr(dccm_ctl_io_lsu_pic_picm_wraddr), + .io_lsu_pic_picm_wr_data(dccm_ctl_io_lsu_pic_picm_wr_data), + .io_lsu_pic_picm_rd_data(dccm_ctl_io_lsu_pic_picm_rd_data) + ); + lsu_stbuf stbuf ( // @[lsu.scala 77:30] + .clock(stbuf_clock), + .reset(stbuf_reset), + .io_lsu_stbuf_c1_clk(stbuf_io_lsu_stbuf_c1_clk), + .io_lsu_free_c2_clk(stbuf_io_lsu_free_c2_clk), + .io_lsu_pkt_m_valid(stbuf_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_store(stbuf_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(stbuf_io_lsu_pkt_m_bits_dma), + .io_lsu_pkt_r_valid(stbuf_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(stbuf_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(stbuf_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(stbuf_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_dword(stbuf_io_lsu_pkt_r_bits_dword), + .io_lsu_pkt_r_bits_store(stbuf_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_dma(stbuf_io_lsu_pkt_r_bits_dma), + .io_store_stbuf_reqvld_r(stbuf_io_store_stbuf_reqvld_r), + .io_lsu_commit_r(stbuf_io_lsu_commit_r), + .io_dec_lsu_valid_raw_d(stbuf_io_dec_lsu_valid_raw_d), + .io_store_data_hi_r(stbuf_io_store_data_hi_r), + .io_store_data_lo_r(stbuf_io_store_data_lo_r), + .io_store_datafn_hi_r(stbuf_io_store_datafn_hi_r), + .io_store_datafn_lo_r(stbuf_io_store_datafn_lo_r), + .io_lsu_stbuf_commit_any(stbuf_io_lsu_stbuf_commit_any), + .io_lsu_addr_m(stbuf_io_lsu_addr_m), + .io_lsu_addr_r(stbuf_io_lsu_addr_r), + .io_end_addr_m(stbuf_io_end_addr_m), + .io_end_addr_r(stbuf_io_end_addr_r), + .io_ldst_dual_d(stbuf_io_ldst_dual_d), + .io_ldst_dual_m(stbuf_io_ldst_dual_m), + .io_ldst_dual_r(stbuf_io_ldst_dual_r), + .io_addr_in_dccm_m(stbuf_io_addr_in_dccm_m), + .io_addr_in_dccm_r(stbuf_io_addr_in_dccm_r), + .io_stbuf_reqvld_any(stbuf_io_stbuf_reqvld_any), + .io_stbuf_reqvld_flushed_any(stbuf_io_stbuf_reqvld_flushed_any), + .io_stbuf_addr_any(stbuf_io_stbuf_addr_any), + .io_stbuf_data_any(stbuf_io_stbuf_data_any), + .io_lsu_stbuf_full_any(stbuf_io_lsu_stbuf_full_any), + .io_ldst_stbuf_reqvld_r(stbuf_io_ldst_stbuf_reqvld_r), + .io_stbuf_fwddata_hi_m(stbuf_io_stbuf_fwddata_hi_m), + .io_stbuf_fwddata_lo_m(stbuf_io_stbuf_fwddata_lo_m), + .io_stbuf_fwdbyteen_hi_m(stbuf_io_stbuf_fwdbyteen_hi_m), + .io_stbuf_fwdbyteen_lo_m(stbuf_io_stbuf_fwdbyteen_lo_m) + ); + lsu_ecc ecc ( // @[lsu.scala 78:30] + .clock(ecc_clock), + .reset(ecc_reset), + .io_lsu_c2_r_clk(ecc_io_lsu_c2_r_clk), + .io_clk_override(ecc_io_clk_override), + .io_lsu_pkt_m_valid(ecc_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_load(ecc_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(ecc_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(ecc_io_lsu_pkt_m_bits_dma), + .io_stbuf_data_any(ecc_io_stbuf_data_any), + .io_dec_tlu_core_ecc_disable(ecc_io_dec_tlu_core_ecc_disable), + .io_lsu_addr_m(ecc_io_lsu_addr_m), + .io_end_addr_m(ecc_io_end_addr_m), + .io_dccm_rdata_hi_m(ecc_io_dccm_rdata_hi_m), + .io_dccm_rdata_lo_m(ecc_io_dccm_rdata_lo_m), + .io_dccm_data_ecc_hi_m(ecc_io_dccm_data_ecc_hi_m), + .io_dccm_data_ecc_lo_m(ecc_io_dccm_data_ecc_lo_m), + .io_ld_single_ecc_error_r(ecc_io_ld_single_ecc_error_r), + .io_ld_single_ecc_error_r_ff(ecc_io_ld_single_ecc_error_r_ff), + .io_lsu_dccm_rden_m(ecc_io_lsu_dccm_rden_m), + .io_addr_in_dccm_m(ecc_io_addr_in_dccm_m), + .io_dma_dccm_wen(ecc_io_dma_dccm_wen), + .io_dma_dccm_wdata_lo(ecc_io_dma_dccm_wdata_lo), + .io_dma_dccm_wdata_hi(ecc_io_dma_dccm_wdata_hi), + .io_sec_data_hi_r(ecc_io_sec_data_hi_r), + .io_sec_data_lo_r(ecc_io_sec_data_lo_r), + .io_sec_data_hi_m(ecc_io_sec_data_hi_m), + .io_sec_data_lo_m(ecc_io_sec_data_lo_m), + .io_sec_data_hi_r_ff(ecc_io_sec_data_hi_r_ff), + .io_sec_data_lo_r_ff(ecc_io_sec_data_lo_r_ff), + .io_dma_dccm_wdata_ecc_hi(ecc_io_dma_dccm_wdata_ecc_hi), + .io_dma_dccm_wdata_ecc_lo(ecc_io_dma_dccm_wdata_ecc_lo), + .io_stbuf_ecc_any(ecc_io_stbuf_ecc_any), + .io_sec_data_ecc_hi_r_ff(ecc_io_sec_data_ecc_hi_r_ff), + .io_sec_data_ecc_lo_r_ff(ecc_io_sec_data_ecc_lo_r_ff), + .io_single_ecc_error_hi_r(ecc_io_single_ecc_error_hi_r), + .io_single_ecc_error_lo_r(ecc_io_single_ecc_error_lo_r), + .io_lsu_single_ecc_error_r(ecc_io_lsu_single_ecc_error_r), + .io_lsu_double_ecc_error_r(ecc_io_lsu_double_ecc_error_r), + .io_lsu_single_ecc_error_m(ecc_io_lsu_single_ecc_error_m), + .io_lsu_double_ecc_error_m(ecc_io_lsu_double_ecc_error_m) + ); + lsu_trigger trigger ( // @[lsu.scala 79:30] + .io_trigger_pkt_any_0_select(trigger_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_pkt(trigger_io_trigger_pkt_any_0_match_pkt), + .io_trigger_pkt_any_0_store(trigger_io_trigger_pkt_any_0_store), + .io_trigger_pkt_any_0_load(trigger_io_trigger_pkt_any_0_load), + .io_trigger_pkt_any_0_m(trigger_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(trigger_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(trigger_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_pkt(trigger_io_trigger_pkt_any_1_match_pkt), + .io_trigger_pkt_any_1_store(trigger_io_trigger_pkt_any_1_store), + .io_trigger_pkt_any_1_load(trigger_io_trigger_pkt_any_1_load), + .io_trigger_pkt_any_1_m(trigger_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(trigger_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(trigger_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_pkt(trigger_io_trigger_pkt_any_2_match_pkt), + .io_trigger_pkt_any_2_store(trigger_io_trigger_pkt_any_2_store), + .io_trigger_pkt_any_2_load(trigger_io_trigger_pkt_any_2_load), + .io_trigger_pkt_any_2_m(trigger_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(trigger_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(trigger_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_pkt(trigger_io_trigger_pkt_any_3_match_pkt), + .io_trigger_pkt_any_3_store(trigger_io_trigger_pkt_any_3_store), + .io_trigger_pkt_any_3_load(trigger_io_trigger_pkt_any_3_load), + .io_trigger_pkt_any_3_m(trigger_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(trigger_io_trigger_pkt_any_3_tdata2), + .io_lsu_pkt_m_valid(trigger_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_half(trigger_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(trigger_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_load(trigger_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(trigger_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(trigger_io_lsu_pkt_m_bits_dma), + .io_lsu_addr_m(trigger_io_lsu_addr_m), + .io_store_data_m(trigger_io_store_data_m), + .io_lsu_trigger_match_m(trigger_io_lsu_trigger_match_m) + ); + lsu_clkdomain clkdomain ( // @[lsu.scala 80:30] + .clock(clkdomain_clock), + .io_clk_override(clkdomain_io_clk_override), + .io_lsu_busreq_r(clkdomain_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(clkdomain_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_empty_any(clkdomain_io_lsu_bus_buffer_empty_any), + .io_lsu_bus_clk_en(clkdomain_io_lsu_bus_clk_en), + .io_lsu_bus_obuf_c1_clken(clkdomain_io_lsu_bus_obuf_c1_clken), + .io_lsu_busm_clken(clkdomain_io_lsu_busm_clken), + .io_lsu_c1_m_clk(clkdomain_io_lsu_c1_m_clk), + .io_lsu_c1_r_clk(clkdomain_io_lsu_c1_r_clk), + .io_lsu_c2_m_clk(clkdomain_io_lsu_c2_m_clk), + .io_lsu_c2_r_clk(clkdomain_io_lsu_c2_r_clk), + .io_lsu_store_c1_m_clk(clkdomain_io_lsu_store_c1_m_clk), + .io_lsu_store_c1_r_clk(clkdomain_io_lsu_store_c1_r_clk), + .io_lsu_stbuf_c1_clk(clkdomain_io_lsu_stbuf_c1_clk), + .io_lsu_bus_ibuf_c1_clk(clkdomain_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_buf_c1_clk(clkdomain_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(clkdomain_io_lsu_free_c2_clk) + ); + lsu_bus_intf bus_intf ( // @[lsu.scala 81:30] + .clock(bus_intf_clock), + .reset(bus_intf_reset), + .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn), + .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned), + .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error), + .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy), + .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), + .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), + .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any), + .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any), + .io_tlu_busbuff_lsu_imprecise_error_addr_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any), + .io_lsu_c1_r_clk(bus_intf_io_lsu_c1_r_clk), + .io_lsu_c2_r_clk(bus_intf_io_lsu_c2_r_clk), + .io_lsu_bus_ibuf_c1_clk(bus_intf_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_buf_c1_clk(bus_intf_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(bus_intf_io_lsu_free_c2_clk), + .io_active_clk(bus_intf_io_active_clk), + .io_axi_aw_ready(bus_intf_io_axi_aw_ready), + .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr), + .io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region), + .io_axi_w_ready(bus_intf_io_axi_w_ready), + .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data), + .io_axi_b_valid(bus_intf_io_axi_b_valid), + .io_axi_b_bits_resp(bus_intf_io_axi_b_bits_resp), + .io_axi_b_bits_id(bus_intf_io_axi_b_bits_id), + .io_axi_ar_ready(bus_intf_io_axi_ar_ready), + .io_axi_ar_valid(bus_intf_io_axi_ar_valid), + .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr), + .io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region), + .io_axi_r_valid(bus_intf_io_axi_r_valid), + .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id), + .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data), + .io_axi_r_bits_resp(bus_intf_io_axi_r_bits_resp), + .io_dec_lsu_valid_raw_d(bus_intf_io_dec_lsu_valid_raw_d), + .io_lsu_busreq_m(bus_intf_io_lsu_busreq_m), + .io_lsu_pkt_m_valid(bus_intf_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_by(bus_intf_io_lsu_pkt_m_bits_by), + .io_lsu_pkt_m_bits_half(bus_intf_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(bus_intf_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_load(bus_intf_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_r_valid(bus_intf_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(bus_intf_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(bus_intf_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(bus_intf_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(bus_intf_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(bus_intf_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(bus_intf_io_lsu_pkt_r_bits_unsign), + .io_lsu_addr_m(bus_intf_io_lsu_addr_m), + .io_lsu_addr_r(bus_intf_io_lsu_addr_r), + .io_end_addr_m(bus_intf_io_end_addr_m), + .io_end_addr_r(bus_intf_io_end_addr_r), + .io_ldst_dual_d(bus_intf_io_ldst_dual_d), + .io_ldst_dual_m(bus_intf_io_ldst_dual_m), + .io_ldst_dual_r(bus_intf_io_ldst_dual_r), + .io_store_data_r(bus_intf_io_store_data_r), + .io_dec_tlu_force_halt(bus_intf_io_dec_tlu_force_halt), + .io_lsu_commit_r(bus_intf_io_lsu_commit_r), + .io_is_sideeffects_m(bus_intf_io_is_sideeffects_m), + .io_flush_m_up(bus_intf_io_flush_m_up), + .io_flush_r(bus_intf_io_flush_r), + .io_lsu_busreq_r(bus_intf_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(bus_intf_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_full_any(bus_intf_io_lsu_bus_buffer_full_any), + .io_lsu_bus_buffer_empty_any(bus_intf_io_lsu_bus_buffer_empty_any), + .io_bus_read_data_m(bus_intf_io_bus_read_data_m), + .io_lsu_nonblock_load_data(bus_intf_io_lsu_nonblock_load_data), + .io_dctl_busbuff_lsu_nonblock_load_valid_m(bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m), + .io_dctl_busbuff_lsu_nonblock_load_tag_m(bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m), + .io_dctl_busbuff_lsu_nonblock_load_inv_r(bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r), + .io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r), + .io_dctl_busbuff_lsu_nonblock_load_data_valid(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid), + .io_dctl_busbuff_lsu_nonblock_load_data_error(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error), + .io_dctl_busbuff_lsu_nonblock_load_data_tag(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag), + .io_lsu_bus_clk_en(bus_intf_io_lsu_bus_clk_en) + ); + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 222:27] + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 222:27] + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 222:27] + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 222:27] + assign io_lsu_dma_dccm_ready = ~_T_8; // @[lsu.scala 95:25] + assign io_lsu_pic_picm_wren = dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 224:14] + assign io_lsu_pic_picm_rden = dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 224:14] + assign io_lsu_pic_picm_mken = dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 224:14] + assign io_lsu_pic_picm_rdaddr = dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 224:14] + assign io_lsu_pic_picm_wraddr = dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 224:14] + assign io_lsu_pic_picm_wr_data = dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 224:14] + assign io_lsu_exu_lsu_result_m = lsu_lsc_ctl_io_lsu_exu_lsu_result_m; // @[lsu.scala 144:46] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 316:26] + assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 316:26] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 346:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 346:27] + assign io_dccm_wren = dccm_ctl_io_dccm_wren; // @[lsu.scala 223:11] + assign io_dccm_rden = dccm_ctl_io_dccm_rden; // @[lsu.scala 223:11] + assign io_dccm_wr_addr_lo = dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 223:11] + assign io_dccm_wr_addr_hi = dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 223:11] + assign io_dccm_rd_addr_lo = dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 223:11] + assign io_dccm_rd_addr_hi = dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 223:11] + assign io_dccm_wr_data_lo = dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 223:11] + assign io_dccm_wr_data_hi = dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 223:11] + assign io_lsu_tlu_lsu_pmu_load_external_m = _T_57 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 121:39] + assign io_lsu_tlu_lsu_pmu_store_external_m = _T_59 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 122:39] + assign io_axi_aw_valid = 1'h0; // @[lsu.scala 349:49] + assign io_axi_aw_bits_id = 3'h0; // @[lsu.scala 349:49] + assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 349:49] + assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 349:49] + assign io_axi_aw_bits_len = 8'h0; // @[lsu.scala 349:49] + assign io_axi_aw_bits_size = 3'h3; // @[lsu.scala 349:49] + assign io_axi_aw_bits_burst = 2'h1; // @[lsu.scala 349:49] + assign io_axi_aw_bits_lock = 1'h0; // @[lsu.scala 349:49] + assign io_axi_aw_bits_cache = 4'hf; // @[lsu.scala 349:49] + assign io_axi_aw_bits_prot = 3'h1; // @[lsu.scala 349:49] + assign io_axi_aw_bits_qos = 4'h0; // @[lsu.scala 349:49] + assign io_axi_w_valid = 1'h0; // @[lsu.scala 349:49] + assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 349:49] + assign io_axi_w_bits_strb = 8'h0; // @[lsu.scala 349:49] + assign io_axi_w_bits_last = 1'h1; // @[lsu.scala 349:49] + assign io_axi_b_ready = 1'h1; // @[lsu.scala 349:49] + assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 349:49] + assign io_axi_ar_bits_id = 3'h0; // @[lsu.scala 349:49] + assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 349:49] + assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 349:49] + assign io_axi_ar_bits_len = 8'h0; // @[lsu.scala 349:49] + assign io_axi_ar_bits_size = 3'h3; // @[lsu.scala 349:49] + assign io_axi_ar_bits_burst = 2'h1; // @[lsu.scala 349:49] + assign io_axi_ar_bits_lock = 1'h0; // @[lsu.scala 349:49] + assign io_axi_ar_bits_cache = 4'hf; // @[lsu.scala 349:49] + assign io_axi_ar_bits_prot = 3'h1; // @[lsu.scala 349:49] + assign io_axi_ar_bits_qos = 4'h0; // @[lsu.scala 349:49] + assign io_axi_r_ready = 1'h1; // @[lsu.scala 349:49] + assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 75:24] + assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 88:25] + assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 87:26] + assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 89:28] + assign io_lsu_idle_any = _T_24 & bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 109:19] + assign io_lsu_active = _T_27 | _T_28; // @[lsu.scala 110:18] + assign io_lsu_fir_addr = lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 162:49] + assign io_lsu_fir_error = lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 163:49] + assign io_lsu_single_ecc_error_incr = lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 160:49] + assign io_lsu_error_pkt_r_valid = lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 161:49] + assign io_lsu_error_pkt_r_bits_single_ecc_error = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 161:49] + assign io_lsu_error_pkt_r_bits_inst_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 161:49] + assign io_lsu_error_pkt_r_bits_exc_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 161:49] + assign io_lsu_error_pkt_r_bits_mscause = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 161:49] + assign io_lsu_error_pkt_r_bits_addr = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 161:49] + assign io_lsu_pmu_misaligned_m = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_55; // @[lsu.scala 120:27] + assign io_lsu_trigger_match_m = trigger_io_lsu_trigger_match_m; // @[lsu.scala 291:50] + assign io_lsu_nonblock_load_data = bus_intf_io_lsu_nonblock_load_data; // @[lsu.scala 347:29] + assign lsu_lsc_ctl_clock = clock; + assign lsu_lsc_ctl_reset = reset; + assign lsu_lsc_ctl_io_clk_override = io_clk_override; // @[lsu.scala 126:46] + assign lsu_lsc_ctl_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 127:46] + assign lsu_lsc_ctl_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 128:46] + assign lsu_lsc_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 129:46] + assign lsu_lsc_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 130:46] + assign lsu_lsc_ctl_io_lsu_store_c1_m_clk = clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 131:46] + assign lsu_lsc_ctl_io_lsu_ld_data_corr_r = dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 133:46] + assign lsu_lsc_ctl_io_lsu_single_ecc_error_r = ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 134:46] + assign lsu_lsc_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 135:46] + assign lsu_lsc_ctl_io_lsu_ld_data_m = dccm_ctl_io_lsu_ld_data_m; // @[lsu.scala 136:46] + assign lsu_lsc_ctl_io_lsu_single_ecc_error_m = ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 137:46] + assign lsu_lsc_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 138:46] + assign lsu_lsc_ctl_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 139:46] + assign lsu_lsc_ctl_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 140:46] + assign lsu_lsc_ctl_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 141:46] + assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d = io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 144:46] + assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d = io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 144:46] + assign lsu_lsc_ctl_io_lsu_p_valid = io_lsu_p_valid; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_fast_int = io_lsu_p_bits_fast_int; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_by = io_lsu_p_bits_by; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_half = io_lsu_p_bits_half; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_word = io_lsu_p_bits_word; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_dword = io_lsu_p_bits_dword; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_load = io_lsu_p_bits_load; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_store = io_lsu_p_bits_store; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_unsign = io_lsu_p_bits_unsign; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_dma = io_lsu_p_bits_dma; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d = io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d = io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m = io_lsu_p_bits_store_data_bypass_m; // @[lsu.scala 145:46] + assign lsu_lsc_ctl_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 146:46] + assign lsu_lsc_ctl_io_dec_lsu_offset_d = io_dec_lsu_offset_d; // @[lsu.scala 147:46] + assign lsu_lsc_ctl_io_picm_mask_data_m = dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 148:46] + assign lsu_lsc_ctl_io_bus_read_data_m = bus_intf_io_bus_read_data_m; // @[lsu.scala 149:46] + assign lsu_lsc_ctl_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu.scala 151:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req = io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 150:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 150:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 150:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 150:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 150:46] + assign dccm_ctl_clock = clock; + assign dccm_ctl_reset = reset; + assign dccm_ctl_io_clk_override = io_clk_override; // @[lsu.scala 166:46] + assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 169:46] + assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 171:46] + assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 173:46] + assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_d_bits_word = lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_d_bits_dword = lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_d_bits_load = lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_d_bits_dma = lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 174:46] + assign dccm_ctl_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 175:46] + assign dccm_ctl_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 176:46] + assign dccm_ctl_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 176:46] + assign dccm_ctl_io_addr_in_dccm_d = lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 177:46] + assign dccm_ctl_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 178:46] + assign dccm_ctl_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 179:46] + assign dccm_ctl_io_addr_in_pic_d = lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 180:46] + assign dccm_ctl_io_addr_in_pic_m = lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 181:46] + assign dccm_ctl_io_addr_in_pic_r = lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 182:46] + assign dccm_ctl_io_lsu_raw_fwd_lo_r = lsu_raw_fwd_lo_r; // @[lsu.scala 183:46] + assign dccm_ctl_io_lsu_raw_fwd_hi_r = lsu_raw_fwd_hi_r; // @[lsu.scala 184:46] + assign dccm_ctl_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 185:46] + assign dccm_ctl_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 167:46] + assign dccm_ctl_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 186:46] + assign dccm_ctl_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[lsu.scala 187:46] + assign dccm_ctl_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 188:46] + assign dccm_ctl_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[lsu.scala 189:46] + assign dccm_ctl_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[lsu.scala 190:46] + assign dccm_ctl_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r[15:0]; // @[lsu.scala 191:46] + assign dccm_ctl_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[lsu.scala 192:46] + assign dccm_ctl_io_stbuf_addr_any = stbuf_io_stbuf_addr_any; // @[lsu.scala 193:46] + assign dccm_ctl_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 194:46] + assign dccm_ctl_io_stbuf_ecc_any = ecc_io_stbuf_ecc_any; // @[lsu.scala 195:46] + assign dccm_ctl_io_stbuf_fwddata_hi_m = stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 196:46] + assign dccm_ctl_io_stbuf_fwddata_lo_m = stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 197:46] + assign dccm_ctl_io_stbuf_fwdbyteen_lo_m = stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 198:46] + assign dccm_ctl_io_stbuf_fwdbyteen_hi_m = stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 199:46] + assign dccm_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 200:46] + assign dccm_ctl_io_single_ecc_error_hi_r = ecc_io_single_ecc_error_hi_r; // @[lsu.scala 201:46] + assign dccm_ctl_io_single_ecc_error_lo_r = ecc_io_single_ecc_error_lo_r; // @[lsu.scala 202:46] + assign dccm_ctl_io_sec_data_hi_r_ff = ecc_io_sec_data_hi_r_ff; // @[lsu.scala 205:46] + assign dccm_ctl_io_sec_data_lo_r_ff = ecc_io_sec_data_lo_r_ff; // @[lsu.scala 206:46] + assign dccm_ctl_io_sec_data_ecc_hi_r_ff = ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 207:46] + assign dccm_ctl_io_sec_data_ecc_lo_r_ff = ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 208:46] + assign dccm_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 209:46] + assign dccm_ctl_io_sec_data_hi_m = ecc_io_sec_data_hi_m; // @[lsu.scala 210:46] + assign dccm_ctl_io_sec_data_lo_m = ecc_io_sec_data_lo_m; // @[lsu.scala 211:46] + assign dccm_ctl_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 212:46] + assign dccm_ctl_io_dma_dccm_wen = _T_11 & io_lsu_dma_dma_lsc_ctl_dma_mem_sz[1]; // @[lsu.scala 213:46] + assign dccm_ctl_io_dma_pic_wen = _T_10 & lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 214:46] + assign dccm_ctl_io_dma_mem_tag_m = dma_mem_tag_m; // @[lsu.scala 215:46] + assign dccm_ctl_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 216:46] + assign dccm_ctl_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 217:46] + assign dccm_ctl_io_dma_dccm_wdata_ecc_hi = ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 218:46] + assign dccm_ctl_io_dma_dccm_wdata_ecc_lo = ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 219:46] + assign dccm_ctl_io_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 222:27] + assign dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 222:27] + assign dccm_ctl_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[lsu.scala 223:11] + assign dccm_ctl_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[lsu.scala 223:11] + assign dccm_ctl_io_lsu_pic_picm_rd_data = io_lsu_pic_picm_rd_data; // @[lsu.scala 224:14] + assign stbuf_clock = clock; + assign stbuf_reset = reset; + assign stbuf_io_lsu_stbuf_c1_clk = clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 230:54] + assign stbuf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 231:54] + assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 232:48] + assign stbuf_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 232:48] + assign stbuf_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 232:48] + assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_dword = lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 233:48] + assign stbuf_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 233:48] + assign stbuf_io_store_stbuf_reqvld_r = _T_33 & _T_38; // @[lsu.scala 234:48] + assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 235:49] + assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 236:49] + assign stbuf_io_store_data_hi_r = dccm_ctl_io_store_data_hi_r; // @[lsu.scala 237:62] + assign stbuf_io_store_data_lo_r = dccm_ctl_io_store_data_lo_r; // @[lsu.scala 238:62] + assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 239:49] + assign stbuf_io_store_datafn_lo_r = dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 240:56] + assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 241:52] + assign stbuf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 243:64] + assign stbuf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 244:64] + assign stbuf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 246:64] + assign stbuf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 247:64] + assign stbuf_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 227:50] + assign stbuf_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 228:50] + assign stbuf_io_ldst_dual_r = lsu_lsc_ctl_io_lsu_addr_r[2] != lsu_lsc_ctl_io_end_addr_r[2]; // @[lsu.scala 229:50] + assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 248:49] + assign stbuf_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 249:56] + assign ecc_clock = clock; + assign ecc_reset = reset; + assign ecc_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 256:52] + assign ecc_io_clk_override = io_clk_override; // @[lsu.scala 255:50] + assign ecc_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 257:52] + assign ecc_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 257:52] + assign ecc_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 257:52] + assign ecc_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 257:52] + assign ecc_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 259:54] + assign ecc_io_dec_tlu_core_ecc_disable = io_dec_tlu_core_ecc_disable; // @[lsu.scala 260:50] + assign ecc_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[lsu.scala 265:58] + assign ecc_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[lsu.scala 266:58] + assign ecc_io_dccm_rdata_hi_m = dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 269:54] + assign ecc_io_dccm_rdata_lo_m = dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 270:54] + assign ecc_io_dccm_data_ecc_hi_m = dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 273:50] + assign ecc_io_dccm_data_ecc_lo_m = dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 274:50] + assign ecc_io_ld_single_ecc_error_r = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 275:50] + assign ecc_io_ld_single_ecc_error_r_ff = dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 276:50] + assign ecc_io_lsu_dccm_rden_m = dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 277:50] + assign ecc_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 278:50] + assign ecc_io_dma_dccm_wen = _T_11 & io_lsu_dma_dma_lsc_ctl_dma_mem_sz[1]; // @[lsu.scala 279:50] + assign ecc_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 280:50] + assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 281:50] + assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_0_match_pkt = io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_0_load = io_trigger_pkt_any_0_load; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_0_m = io_trigger_pkt_any_0_m; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_0_tdata2 = io_trigger_pkt_any_0_tdata2; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_select = io_trigger_pkt_any_1_select; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_match_pkt = io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_store = io_trigger_pkt_any_1_store; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_load = io_trigger_pkt_any_1_load; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_m = io_trigger_pkt_any_1_m; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_1_tdata2 = io_trigger_pkt_any_1_tdata2; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_select = io_trigger_pkt_any_2_select; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_match_pkt = io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_store = io_trigger_pkt_any_2_store; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_load = io_trigger_pkt_any_2_load; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_m = io_trigger_pkt_any_2_m; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_2_tdata2 = io_trigger_pkt_any_2_tdata2; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_select = io_trigger_pkt_any_3_select; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_match_pkt = io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_store = io_trigger_pkt_any_3_store; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_load = io_trigger_pkt_any_3_load; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_m = io_trigger_pkt_any_3_m; // @[lsu.scala 286:50] + assign trigger_io_trigger_pkt_any_3_tdata2 = io_trigger_pkt_any_3_tdata2; // @[lsu.scala 286:50] + assign trigger_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 287:50] + assign trigger_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 287:50] + assign trigger_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 287:50] + assign trigger_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 287:50] + assign trigger_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 287:50] + assign trigger_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 287:50] + assign trigger_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 288:50] + assign trigger_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 289:50] + assign clkdomain_clock = clock; + assign clkdomain_io_clk_override = io_clk_override; // @[lsu.scala 296:50] + assign clkdomain_io_lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 302:50] + assign clkdomain_io_lsu_bus_buffer_pend_any = bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 303:50] + assign clkdomain_io_lsu_bus_buffer_empty_any = bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 304:50] + assign clkdomain_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 306:50] + assign bus_intf_clock = clock; + assign bus_intf_reset = reset; + assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 316:26] + assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 316:26] + assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 316:26] + assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 318:49] + assign bus_intf_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 319:49] + assign bus_intf_io_lsu_bus_ibuf_c1_clk = clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 322:49] + assign bus_intf_io_lsu_bus_buf_c1_clk = clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 324:49] + assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 325:49] + assign bus_intf_io_active_clk = io_active_clk; // @[lsu.scala 326:49] + assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 349:49] + assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 349:49] + assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 349:49] + assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 349:49] + assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 349:49] + assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 349:49] + assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 349:49] + assign bus_intf_io_axi_r_bits_id = io_axi_r_bits_id; // @[lsu.scala 349:49] + assign bus_intf_io_axi_r_bits_data = io_axi_r_bits_data; // @[lsu.scala 349:49] + assign bus_intf_io_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu.scala 349:49] + assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 328:49] + assign bus_intf_io_lsu_busreq_m = _T_48 & _T_49; // @[lsu.scala 329:49] + assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 338:49] + assign bus_intf_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 338:49] + assign bus_intf_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 338:49] + assign bus_intf_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 338:49] + assign bus_intf_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 338:49] + assign bus_intf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_pkt_r_bits_unsign = lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 339:49] + assign bus_intf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m & _T_100; // @[lsu.scala 333:49] + assign bus_intf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r & _T_103; // @[lsu.scala 334:49] + assign bus_intf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m & _T_100; // @[lsu.scala 335:49] + assign bus_intf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r & _T_103; // @[lsu.scala 336:49] + assign bus_intf_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 330:49] + assign bus_intf_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 331:49] + assign bus_intf_io_ldst_dual_r = lsu_lsc_ctl_io_lsu_addr_r[2] != lsu_lsc_ctl_io_end_addr_r[2]; // @[lsu.scala 332:49] + assign bus_intf_io_store_data_r = dccm_ctl_io_store_data_r & _T_103; // @[lsu.scala 337:49] + assign bus_intf_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu.scala 340:49] + assign bus_intf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 341:49] + assign bus_intf_io_is_sideeffects_m = lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 342:49] + assign bus_intf_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 343:49] + assign bus_intf_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 344:49] + assign bus_intf_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 350:49] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dma_mem_tag_m = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + lsu_raw_fwd_hi_r = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + lsu_raw_fwd_lo_r = _RAND_2[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dma_mem_tag_m = 3'h0; + end + if (reset) begin + lsu_raw_fwd_hi_r = 1'h0; + end + if (reset) begin + lsu_raw_fwd_lo_r = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clkdomain_io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + dma_mem_tag_m <= 3'h0; + end else begin + dma_mem_tag_m <= io_lsu_dma_dma_mem_tag; + end + end + always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_raw_fwd_hi_r <= 1'h0; + end else begin + lsu_raw_fwd_hi_r <= |stbuf_io_stbuf_fwdbyteen_hi_m; + end + end + always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_raw_fwd_lo_r <= 1'h0; + end else begin + lsu_raw_fwd_lo_r <= |stbuf_io_stbuf_fwdbyteen_lo_m; + end + end +endmodule diff --git a/lsu_bus_intf.anno.json b/lsu_bus_intf.anno.json new file mode 100644 index 00000000..df7ef78c --- /dev/null +++ b/lsu_bus_intf.anno.json @@ -0,0 +1,113 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_misaligned", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r", + "~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_bus_read_data_m", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m", + "~lsu_bus_intf|lsu_bus_intf>io_end_addr_m", + "~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store", + "~lsu_bus_intf|lsu_bus_intf>io_store_data_r", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half", + "~lsu_bus_intf|lsu_bus_intf>io_end_addr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_valid_m", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_load", + "~lsu_bus_intf|lsu_bus_intf>io_flush_m_up", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_valid", + "~lsu_bus_intf|lsu_bus_intf>io_is_sideeffects_m", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m", + "~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt", + "~lsu_bus_intf|lsu_bus_intf>io_end_addr_m", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r", + "~lsu_bus_intf|lsu_bus_intf>io_end_addr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_busy", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready", + "~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready", + "~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_tag_m", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_lsu_bus_buffer_full_any", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_d", + "~lsu_bus_intf|lsu_bus_intf>io_dec_lsu_valid_raw_d", + "~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_m", + "~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m", + "~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_inv_r", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_trxn", + "sources":[ + "~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready", + "~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready", + "~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"lsu_bus_intf.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"lsu_bus_intf" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/lsu_bus_intf.fir b/lsu_bus_intf.fir new file mode 100644 index 00000000..aecef0c5 --- /dev/null +++ b/lsu_bus_intf.fir @@ -0,0 +1,7199 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit lsu_bus_intf : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_bus_buffer : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_nonblock_load_data : UInt<32>} + + wire buf_addr : UInt<32>[4] @[lsu_bus_buffer.scala 71:22] + wire buf_state : UInt<3>[4] @[lsu_bus_buffer.scala 72:23] + wire buf_write : UInt<4> + buf_write <= UInt<1>("h00") + wire CmdPtr0 : UInt<2> + CmdPtr0 <= UInt<1>("h00") + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[lsu_bus_buffer.scala 77:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[lsu_bus_buffer.scala 78:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_2 = eq(_T, _T_1) @[lsu_bus_buffer.scala 80:74] + node _T_3 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 80:109] + node _T_4 = and(_T_2, _T_3) @[lsu_bus_buffer.scala 80:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_6 = and(_T_4, _T_5) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_9 = eq(_T_7, _T_8) @[lsu_bus_buffer.scala 80:74] + node _T_10 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 80:109] + node _T_11 = and(_T_9, _T_10) @[lsu_bus_buffer.scala 80:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_13 = and(_T_11, _T_12) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_16 = eq(_T_14, _T_15) @[lsu_bus_buffer.scala 80:74] + node _T_17 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 80:109] + node _T_18 = and(_T_16, _T_17) @[lsu_bus_buffer.scala 80:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_20 = and(_T_18, _T_19) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 80:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 80:89] + node _T_23 = eq(_T_21, _T_22) @[lsu_bus_buffer.scala 80:74] + node _T_24 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 80:109] + node _T_25 = and(_T_23, _T_24) @[lsu_bus_buffer.scala 80:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 80:129] + node _T_27 = and(_T_25, _T_26) @[lsu_bus_buffer.scala 80:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_buffer.scala 80:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_30 = eq(_T_28, _T_29) @[lsu_bus_buffer.scala 81:74] + node _T_31 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 81:109] + node _T_32 = and(_T_30, _T_31) @[lsu_bus_buffer.scala 81:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_34 = and(_T_32, _T_33) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_37 = eq(_T_35, _T_36) @[lsu_bus_buffer.scala 81:74] + node _T_38 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 81:109] + node _T_39 = and(_T_37, _T_38) @[lsu_bus_buffer.scala 81:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_41 = and(_T_39, _T_40) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_44 = eq(_T_42, _T_43) @[lsu_bus_buffer.scala 81:74] + node _T_45 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 81:109] + node _T_46 = and(_T_44, _T_45) @[lsu_bus_buffer.scala 81:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_48 = and(_T_46, _T_47) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 81:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 81:89] + node _T_51 = eq(_T_49, _T_50) @[lsu_bus_buffer.scala 81:74] + node _T_52 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 81:109] + node _T_53 = and(_T_51, _T_52) @[lsu_bus_buffer.scala 81:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 81:129] + node _T_55 = and(_T_53, _T_54) @[lsu_bus_buffer.scala 81:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_buffer.scala 81:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[lsu_bus_buffer.scala 82:33] + wire ld_byte_ibuf_hit_lo : UInt<4> + ld_byte_ibuf_hit_lo <= UInt<1>("h00") + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[lsu_bus_buffer.scala 84:33] + wire ld_byte_ibuf_hit_hi : UInt<4> + ld_byte_ibuf_hit_hi <= UInt<1>("h00") + wire buf_byteen : UInt<4>[4] @[lsu_bus_buffer.scala 86:24] + buf_byteen[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + buf_byteen[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:14] + wire buf_nxtstate : UInt<3>[4] @[lsu_bus_buffer.scala 88:26] + buf_nxtstate[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + buf_nxtstate[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:16] + wire buf_wr_en : UInt<1>[4] @[lsu_bus_buffer.scala 90:23] + buf_wr_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + buf_wr_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:13] + wire buf_data_en : UInt<1>[4] @[lsu_bus_buffer.scala 92:25] + buf_data_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + buf_data_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:15] + wire buf_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 94:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:20] + wire buf_ldfwd_in : UInt<1>[4] @[lsu_bus_buffer.scala 96:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:16] + wire buf_ldfwd_en : UInt<1>[4] @[lsu_bus_buffer.scala 98:26] + buf_ldfwd_en[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + buf_ldfwd_en[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 99:16] + wire buf_data_in : UInt<32>[4] @[lsu_bus_buffer.scala 100:25] + buf_data_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + buf_data_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 102:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 103:19] + wire buf_error_en : UInt<1>[4] @[lsu_bus_buffer.scala 104:26] + buf_error_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + buf_error_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:16] + wire bus_rsp_read_error : UInt<1> + bus_rsp_read_error <= UInt<1>("h00") + wire bus_rsp_rdata : UInt<64> + bus_rsp_rdata <= UInt<1>("h00") + wire bus_rsp_write_error : UInt<1> + bus_rsp_write_error <= UInt<1>("h00") + wire buf_dualtag : UInt<2>[4] @[lsu_bus_buffer.scala 109:25] + buf_dualtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + buf_dualtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 110:15] + wire buf_ldfwd : UInt<4> + buf_ldfwd <= UInt<1>("h00") + wire buf_resp_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 112:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:25] + wire any_done_wait_state : UInt<1> + any_done_wait_state <= UInt<1>("h00") + wire bus_rsp_write : UInt<1> + bus_rsp_write <= UInt<1>("h00") + wire bus_rsp_write_tag : UInt<3> + bus_rsp_write_tag <= UInt<1>("h00") + wire buf_ldfwdtag : UInt<2>[4] @[lsu_bus_buffer.scala 117:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:16] + wire buf_rst : UInt<1>[4] @[lsu_bus_buffer.scala 119:21] + buf_rst[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + buf_rst[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:11] + wire ibuf_drainvec_vld : UInt<4> + ibuf_drainvec_vld <= UInt<1>("h00") + wire buf_byteen_in : UInt<4>[4] @[lsu_bus_buffer.scala 122:27] + buf_byteen_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + buf_byteen_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 123:17] + wire buf_addr_in : UInt<32>[4] @[lsu_bus_buffer.scala 124:25] + buf_addr_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + buf_addr_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 125:15] + wire buf_dual_in : UInt<4> + buf_dual_in <= UInt<1>("h00") + wire buf_samedw_in : UInt<4> + buf_samedw_in <= UInt<1>("h00") + wire buf_nomerge_in : UInt<4> + buf_nomerge_in <= UInt<1>("h00") + wire buf_dualhi_in : UInt<4> + buf_dualhi_in <= UInt<1>("h00") + wire buf_dualtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 130:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:18] + wire buf_sideeffect_in : UInt<4> + buf_sideeffect_in <= UInt<1>("h00") + wire buf_unsign_in : UInt<4> + buf_unsign_in <= UInt<1>("h00") + wire buf_sz_in : UInt<2>[4] @[lsu_bus_buffer.scala 134:23] + buf_sz_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + buf_sz_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 135:13] + wire buf_write_in : UInt<4> + buf_write_in <= UInt<1>("h00") + wire buf_unsign : UInt<4> + buf_unsign <= UInt<1>("h00") + wire buf_error : UInt<4> + buf_error <= UInt<1>("h00") + wire CmdPtr1 : UInt<2> + CmdPtr1 <= UInt<1>("h00") + wire ibuf_data : UInt<32> + ibuf_data <= UInt<1>("h00") + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[lsu_bus_buffer.scala 142:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 142:98] + node _T_58 = or(_T_56, _T_57) @[lsu_bus_buffer.scala 142:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[lsu_bus_buffer.scala 142:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 142:98] + node _T_61 = or(_T_59, _T_60) @[lsu_bus_buffer.scala 142:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[lsu_bus_buffer.scala 142:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 142:98] + node _T_64 = or(_T_62, _T_63) @[lsu_bus_buffer.scala 142:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[lsu_bus_buffer.scala 142:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 142:98] + node _T_67 = or(_T_65, _T_66) @[lsu_bus_buffer.scala 142:77] + node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] + io.ld_byte_hit_buf_lo <= _T_70 @[lsu_bus_buffer.scala 142:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[lsu_bus_buffer.scala 143:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 143:98] + node _T_73 = or(_T_71, _T_72) @[lsu_bus_buffer.scala 143:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[lsu_bus_buffer.scala 143:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 143:98] + node _T_76 = or(_T_74, _T_75) @[lsu_bus_buffer.scala 143:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[lsu_bus_buffer.scala 143:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 143:98] + node _T_79 = or(_T_77, _T_78) @[lsu_bus_buffer.scala 143:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[lsu_bus_buffer.scala 143:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 143:98] + node _T_82 = or(_T_80, _T_81) @[lsu_bus_buffer.scala 143:77] + node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] + io.ld_byte_hit_buf_hi <= _T_85 @[lsu_bus_buffer.scala 143:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[lsu_bus_buffer.scala 145:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_89 = and(_T_87, _T_88) @[lsu_bus_buffer.scala 145:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[lsu_bus_buffer.scala 145:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_93 = and(_T_91, _T_92) @[lsu_bus_buffer.scala 145:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[lsu_bus_buffer.scala 145:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_97 = and(_T_95, _T_96) @[lsu_bus_buffer.scala 145:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 145:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[lsu_bus_buffer.scala 145:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 145:132] + node _T_101 = and(_T_99, _T_100) @[lsu_bus_buffer.scala 145:114] + node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] + node _T_104 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[lsu_bus_buffer.scala 145:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_107 = and(_T_105, _T_106) @[lsu_bus_buffer.scala 145:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[lsu_bus_buffer.scala 145:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_111 = and(_T_109, _T_110) @[lsu_bus_buffer.scala 145:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[lsu_bus_buffer.scala 145:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_115 = and(_T_113, _T_114) @[lsu_bus_buffer.scala 145:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 145:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[lsu_bus_buffer.scala 145:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 145:132] + node _T_119 = and(_T_117, _T_118) @[lsu_bus_buffer.scala 145:114] + node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] + node _T_122 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[lsu_bus_buffer.scala 145:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_125 = and(_T_123, _T_124) @[lsu_bus_buffer.scala 145:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[lsu_bus_buffer.scala 145:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_buffer.scala 145:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[lsu_bus_buffer.scala 145:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_buffer.scala 145:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 145:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[lsu_bus_buffer.scala 145:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 145:132] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_buffer.scala 145:114] + node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] + node _T_140 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[lsu_bus_buffer.scala 145:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_143 = and(_T_141, _T_142) @[lsu_bus_buffer.scala 145:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[lsu_bus_buffer.scala 145:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_147 = and(_T_145, _T_146) @[lsu_bus_buffer.scala 145:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[lsu_bus_buffer.scala 145:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_151 = and(_T_149, _T_150) @[lsu_bus_buffer.scala 145:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 145:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[lsu_bus_buffer.scala 145:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 145:132] + node _T_155 = and(_T_153, _T_154) @[lsu_bus_buffer.scala 145:114] + node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] + node _T_158 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[lsu_bus_buffer.scala 146:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_161 = and(_T_159, _T_160) @[lsu_bus_buffer.scala 146:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[lsu_bus_buffer.scala 146:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_165 = and(_T_163, _T_164) @[lsu_bus_buffer.scala 146:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[lsu_bus_buffer.scala 146:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_169 = and(_T_167, _T_168) @[lsu_bus_buffer.scala 146:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 146:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[lsu_bus_buffer.scala 146:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 146:132] + node _T_173 = and(_T_171, _T_172) @[lsu_bus_buffer.scala 146:114] + node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] + node _T_176 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[lsu_bus_buffer.scala 146:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_179 = and(_T_177, _T_178) @[lsu_bus_buffer.scala 146:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[lsu_bus_buffer.scala 146:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_183 = and(_T_181, _T_182) @[lsu_bus_buffer.scala 146:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[lsu_bus_buffer.scala 146:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_187 = and(_T_185, _T_186) @[lsu_bus_buffer.scala 146:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 146:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[lsu_bus_buffer.scala 146:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 146:132] + node _T_191 = and(_T_189, _T_190) @[lsu_bus_buffer.scala 146:114] + node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] + node _T_194 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[lsu_bus_buffer.scala 146:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_197 = and(_T_195, _T_196) @[lsu_bus_buffer.scala 146:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[lsu_bus_buffer.scala 146:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_201 = and(_T_199, _T_200) @[lsu_bus_buffer.scala 146:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[lsu_bus_buffer.scala 146:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_205 = and(_T_203, _T_204) @[lsu_bus_buffer.scala 146:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 146:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[lsu_bus_buffer.scala 146:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 146:132] + node _T_209 = and(_T_207, _T_208) @[lsu_bus_buffer.scala 146:114] + node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] + node _T_212 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[lsu_bus_buffer.scala 146:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_215 = and(_T_213, _T_214) @[lsu_bus_buffer.scala 146:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[lsu_bus_buffer.scala 146:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_219 = and(_T_217, _T_218) @[lsu_bus_buffer.scala 146:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[lsu_bus_buffer.scala 146:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_223 = and(_T_221, _T_222) @[lsu_bus_buffer.scala 146:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 146:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[lsu_bus_buffer.scala 146:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 146:132] + node _T_227 = and(_T_225, _T_226) @[lsu_bus_buffer.scala 146:114] + node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] + node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] + wire buf_age_younger : UInt<4>[4] @[lsu_bus_buffer.scala 148:29] + buf_age_younger[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + buf_age_younger[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 149:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_232 = orr(_T_231) @[lsu_bus_buffer.scala 150:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_234 = and(_T_230, _T_233) @[lsu_bus_buffer.scala 150:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_237 = and(_T_234, _T_236) @[lsu_bus_buffer.scala 150:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_240 = orr(_T_239) @[lsu_bus_buffer.scala 150:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_242 = and(_T_238, _T_241) @[lsu_bus_buffer.scala 150:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_245 = and(_T_242, _T_244) @[lsu_bus_buffer.scala 150:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_248 = orr(_T_247) @[lsu_bus_buffer.scala 150:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_250 = and(_T_246, _T_249) @[lsu_bus_buffer.scala 150:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_253 = and(_T_250, _T_252) @[lsu_bus_buffer.scala 150:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_256 = orr(_T_255) @[lsu_bus_buffer.scala 150:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_258 = and(_T_254, _T_257) @[lsu_bus_buffer.scala 150:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 150:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_261 = and(_T_258, _T_260) @[lsu_bus_buffer.scala 150:148] + node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] + node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] + node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_267 = orr(_T_266) @[lsu_bus_buffer.scala 150:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_269 = and(_T_265, _T_268) @[lsu_bus_buffer.scala 150:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_272 = and(_T_269, _T_271) @[lsu_bus_buffer.scala 150:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_275 = orr(_T_274) @[lsu_bus_buffer.scala 150:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_277 = and(_T_273, _T_276) @[lsu_bus_buffer.scala 150:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_280 = and(_T_277, _T_279) @[lsu_bus_buffer.scala 150:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_283 = orr(_T_282) @[lsu_bus_buffer.scala 150:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_285 = and(_T_281, _T_284) @[lsu_bus_buffer.scala 150:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_288 = and(_T_285, _T_287) @[lsu_bus_buffer.scala 150:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_291 = orr(_T_290) @[lsu_bus_buffer.scala 150:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_293 = and(_T_289, _T_292) @[lsu_bus_buffer.scala 150:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 150:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_296 = and(_T_293, _T_295) @[lsu_bus_buffer.scala 150:148] + node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_302 = orr(_T_301) @[lsu_bus_buffer.scala 150:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_304 = and(_T_300, _T_303) @[lsu_bus_buffer.scala 150:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_307 = and(_T_304, _T_306) @[lsu_bus_buffer.scala 150:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_310 = orr(_T_309) @[lsu_bus_buffer.scala 150:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_312 = and(_T_308, _T_311) @[lsu_bus_buffer.scala 150:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_315 = and(_T_312, _T_314) @[lsu_bus_buffer.scala 150:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_318 = orr(_T_317) @[lsu_bus_buffer.scala 150:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_320 = and(_T_316, _T_319) @[lsu_bus_buffer.scala 150:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_323 = and(_T_320, _T_322) @[lsu_bus_buffer.scala 150:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_326 = orr(_T_325) @[lsu_bus_buffer.scala 150:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_328 = and(_T_324, _T_327) @[lsu_bus_buffer.scala 150:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 150:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_331 = and(_T_328, _T_330) @[lsu_bus_buffer.scala 150:148] + node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] + node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] + node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[lsu_bus_buffer.scala 150:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 150:122] + node _T_337 = orr(_T_336) @[lsu_bus_buffer.scala 150:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_339 = and(_T_335, _T_338) @[lsu_bus_buffer.scala 150:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_342 = and(_T_339, _T_341) @[lsu_bus_buffer.scala 150:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[lsu_bus_buffer.scala 150:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 150:122] + node _T_345 = orr(_T_344) @[lsu_bus_buffer.scala 150:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_347 = and(_T_343, _T_346) @[lsu_bus_buffer.scala 150:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_350 = and(_T_347, _T_349) @[lsu_bus_buffer.scala 150:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[lsu_bus_buffer.scala 150:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 150:122] + node _T_353 = orr(_T_352) @[lsu_bus_buffer.scala 150:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_355 = and(_T_351, _T_354) @[lsu_bus_buffer.scala 150:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_358 = and(_T_355, _T_357) @[lsu_bus_buffer.scala 150:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[lsu_bus_buffer.scala 150:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 150:122] + node _T_361 = orr(_T_360) @[lsu_bus_buffer.scala 150:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:99] + node _T_363 = and(_T_359, _T_362) @[lsu_bus_buffer.scala 150:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 150:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_buffer.scala 150:150] + node _T_366 = and(_T_363, _T_365) @[lsu_bus_buffer.scala 150:148] + node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] + ld_byte_hitvecfn_lo[0] <= _T_264 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[lsu_bus_buffer.scala 150:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[lsu_bus_buffer.scala 150:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_372 = orr(_T_371) @[lsu_bus_buffer.scala 151:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_374 = and(_T_370, _T_373) @[lsu_bus_buffer.scala 151:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_377 = and(_T_374, _T_376) @[lsu_bus_buffer.scala 151:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_380 = orr(_T_379) @[lsu_bus_buffer.scala 151:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_382 = and(_T_378, _T_381) @[lsu_bus_buffer.scala 151:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_385 = and(_T_382, _T_384) @[lsu_bus_buffer.scala 151:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_388 = orr(_T_387) @[lsu_bus_buffer.scala 151:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_390 = and(_T_386, _T_389) @[lsu_bus_buffer.scala 151:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_393 = and(_T_390, _T_392) @[lsu_bus_buffer.scala 151:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_396 = orr(_T_395) @[lsu_bus_buffer.scala 151:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_398 = and(_T_394, _T_397) @[lsu_bus_buffer.scala 151:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 151:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_401 = and(_T_398, _T_400) @[lsu_bus_buffer.scala 151:148] + node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_407 = orr(_T_406) @[lsu_bus_buffer.scala 151:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_409 = and(_T_405, _T_408) @[lsu_bus_buffer.scala 151:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_412 = and(_T_409, _T_411) @[lsu_bus_buffer.scala 151:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_415 = orr(_T_414) @[lsu_bus_buffer.scala 151:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_417 = and(_T_413, _T_416) @[lsu_bus_buffer.scala 151:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_420 = and(_T_417, _T_419) @[lsu_bus_buffer.scala 151:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_423 = orr(_T_422) @[lsu_bus_buffer.scala 151:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_425 = and(_T_421, _T_424) @[lsu_bus_buffer.scala 151:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_428 = and(_T_425, _T_427) @[lsu_bus_buffer.scala 151:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_431 = orr(_T_430) @[lsu_bus_buffer.scala 151:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_433 = and(_T_429, _T_432) @[lsu_bus_buffer.scala 151:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 151:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_436 = and(_T_433, _T_435) @[lsu_bus_buffer.scala 151:148] + node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] + node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_442 = orr(_T_441) @[lsu_bus_buffer.scala 151:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_444 = and(_T_440, _T_443) @[lsu_bus_buffer.scala 151:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_447 = and(_T_444, _T_446) @[lsu_bus_buffer.scala 151:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_450 = orr(_T_449) @[lsu_bus_buffer.scala 151:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_452 = and(_T_448, _T_451) @[lsu_bus_buffer.scala 151:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_455 = and(_T_452, _T_454) @[lsu_bus_buffer.scala 151:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_458 = orr(_T_457) @[lsu_bus_buffer.scala 151:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_460 = and(_T_456, _T_459) @[lsu_bus_buffer.scala 151:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_463 = and(_T_460, _T_462) @[lsu_bus_buffer.scala 151:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_466 = orr(_T_465) @[lsu_bus_buffer.scala 151:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_468 = and(_T_464, _T_467) @[lsu_bus_buffer.scala 151:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 151:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_471 = and(_T_468, _T_470) @[lsu_bus_buffer.scala 151:148] + node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[lsu_bus_buffer.scala 151:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 151:122] + node _T_477 = orr(_T_476) @[lsu_bus_buffer.scala 151:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_479 = and(_T_475, _T_478) @[lsu_bus_buffer.scala 151:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_482 = and(_T_479, _T_481) @[lsu_bus_buffer.scala 151:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[lsu_bus_buffer.scala 151:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 151:122] + node _T_485 = orr(_T_484) @[lsu_bus_buffer.scala 151:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_487 = and(_T_483, _T_486) @[lsu_bus_buffer.scala 151:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_490 = and(_T_487, _T_489) @[lsu_bus_buffer.scala 151:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[lsu_bus_buffer.scala 151:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 151:122] + node _T_493 = orr(_T_492) @[lsu_bus_buffer.scala 151:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_495 = and(_T_491, _T_494) @[lsu_bus_buffer.scala 151:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_498 = and(_T_495, _T_497) @[lsu_bus_buffer.scala 151:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[lsu_bus_buffer.scala 151:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 151:122] + node _T_501 = orr(_T_500) @[lsu_bus_buffer.scala 151:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:99] + node _T_503 = and(_T_499, _T_502) @[lsu_bus_buffer.scala 151:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 151:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[lsu_bus_buffer.scala 151:150] + node _T_506 = and(_T_503, _T_505) @[lsu_bus_buffer.scala 151:148] + node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] + node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] + ld_byte_hitvecfn_hi[0] <= _T_404 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[lsu_bus_buffer.scala 151:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[lsu_bus_buffer.scala 151:23] + wire ibuf_addr : UInt<32> + ibuf_addr <= UInt<1>("h00") + wire ibuf_write : UInt<1> + ibuf_write <= UInt<1>("h00") + wire ibuf_valid : UInt<1> + ibuf_valid <= UInt<1>("h00") + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 156:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 156:64] + node _T_512 = eq(_T_510, _T_511) @[lsu_bus_buffer.scala 156:51] + node _T_513 = and(_T_512, ibuf_write) @[lsu_bus_buffer.scala 156:73] + node _T_514 = and(_T_513, ibuf_valid) @[lsu_bus_buffer.scala 156:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[lsu_bus_buffer.scala 156:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 157:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 157:64] + node _T_517 = eq(_T_515, _T_516) @[lsu_bus_buffer.scala 157:51] + node _T_518 = and(_T_517, ibuf_write) @[lsu_bus_buffer.scala 157:73] + node _T_519 = and(_T_518, ibuf_valid) @[lsu_bus_buffer.scala 157:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[lsu_bus_buffer.scala 157:99] + wire ibuf_byteen : UInt<4> + ibuf_byteen <= UInt<1>("h00") + node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] + node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_522 = and(_T_521, ibuf_byteen) @[lsu_bus_buffer.scala 161:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[lsu_bus_buffer.scala 161:69] + ld_byte_ibuf_hit_lo <= _T_523 @[lsu_bus_buffer.scala 161:23] + node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(_T_525, ibuf_byteen) @[lsu_bus_buffer.scala 162:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[lsu_bus_buffer.scala 162:69] + ld_byte_ibuf_hit_hi <= _T_527 @[lsu_bus_buffer.scala 162:23] + wire buf_data : UInt<32>[4] @[lsu_bus_buffer.scala 164:22] + buf_data[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + buf_data[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 165:12] + wire fwd_data : UInt<32> + fwd_data <= UInt<1>("h00") + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 167:81] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 167:81] + node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] + node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 167:81] + node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] + node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 167:81] + node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] + node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] + node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] + node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 168:81] + node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 168:81] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 168:81] + node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] + node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 168:81] + node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] + node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] + node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[lsu_bus_buffer.scala 169:86] + node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] + node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_559 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_560 = and(_T_558, _T_559) @[lsu_bus_buffer.scala 169:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[lsu_bus_buffer.scala 169:86] + node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] + node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_564 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_565 = and(_T_563, _T_564) @[lsu_bus_buffer.scala 169:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[lsu_bus_buffer.scala 169:86] + node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_569 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_570 = and(_T_568, _T_569) @[lsu_bus_buffer.scala 169:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[lsu_bus_buffer.scala 169:86] + node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] + node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_574 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 169:104] + node _T_575 = and(_T_573, _T_574) @[lsu_bus_buffer.scala 169:91] + node _T_576 = or(_T_560, _T_565) @[lsu_bus_buffer.scala 169:123] + node _T_577 = or(_T_576, _T_570) @[lsu_bus_buffer.scala 169:123] + node _T_578 = or(_T_577, _T_575) @[lsu_bus_buffer.scala 169:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[lsu_bus_buffer.scala 170:60] + node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_583 = and(_T_581, _T_582) @[lsu_bus_buffer.scala 170:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[lsu_bus_buffer.scala 170:60] + node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] + node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_587 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_588 = and(_T_586, _T_587) @[lsu_bus_buffer.scala 170:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[lsu_bus_buffer.scala 170:60] + node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] + node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_592 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_593 = and(_T_591, _T_592) @[lsu_bus_buffer.scala 170:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[lsu_bus_buffer.scala 170:60] + node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] + node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_597 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 170:78] + node _T_598 = and(_T_596, _T_597) @[lsu_bus_buffer.scala 170:65] + node _T_599 = or(_T_583, _T_588) @[lsu_bus_buffer.scala 170:97] + node _T_600 = or(_T_599, _T_593) @[lsu_bus_buffer.scala 170:97] + node _T_601 = or(_T_600, _T_598) @[lsu_bus_buffer.scala 170:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[lsu_bus_buffer.scala 171:60] + node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] + node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_605 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_606 = and(_T_604, _T_605) @[lsu_bus_buffer.scala 171:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[lsu_bus_buffer.scala 171:60] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_611 = and(_T_609, _T_610) @[lsu_bus_buffer.scala 171:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[lsu_bus_buffer.scala 171:60] + node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] + node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_615 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_616 = and(_T_614, _T_615) @[lsu_bus_buffer.scala 171:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[lsu_bus_buffer.scala 171:60] + node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_620 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 171:78] + node _T_621 = and(_T_619, _T_620) @[lsu_bus_buffer.scala 171:65] + node _T_622 = or(_T_606, _T_611) @[lsu_bus_buffer.scala 171:97] + node _T_623 = or(_T_622, _T_616) @[lsu_bus_buffer.scala 171:97] + node _T_624 = or(_T_623, _T_621) @[lsu_bus_buffer.scala 171:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[lsu_bus_buffer.scala 172:60] + node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_629 = and(_T_627, _T_628) @[lsu_bus_buffer.scala 172:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[lsu_bus_buffer.scala 172:60] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_634 = and(_T_632, _T_633) @[lsu_bus_buffer.scala 172:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[lsu_bus_buffer.scala 172:60] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_639 = and(_T_637, _T_638) @[lsu_bus_buffer.scala 172:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[lsu_bus_buffer.scala 172:60] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_643 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 172:78] + node _T_644 = and(_T_642, _T_643) @[lsu_bus_buffer.scala 172:65] + node _T_645 = or(_T_629, _T_634) @[lsu_bus_buffer.scala 172:97] + node _T_646 = or(_T_645, _T_639) @[lsu_bus_buffer.scala 172:97] + node _T_647 = or(_T_646, _T_644) @[lsu_bus_buffer.scala 172:97] + node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] + node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[lsu_bus_buffer.scala 173:32] + node _T_652 = or(_T_650, _T_651) @[lsu_bus_buffer.scala 172:103] + io.ld_fwddata_buf_lo <= _T_652 @[lsu_bus_buffer.scala 169:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[lsu_bus_buffer.scala 175:86] + node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] + node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_656 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_657 = and(_T_655, _T_656) @[lsu_bus_buffer.scala 175:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[lsu_bus_buffer.scala 175:86] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_662 = and(_T_660, _T_661) @[lsu_bus_buffer.scala 175:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[lsu_bus_buffer.scala 175:86] + node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] + node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_666 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_667 = and(_T_665, _T_666) @[lsu_bus_buffer.scala 175:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[lsu_bus_buffer.scala 175:86] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 175:104] + node _T_672 = and(_T_670, _T_671) @[lsu_bus_buffer.scala 175:91] + node _T_673 = or(_T_657, _T_662) @[lsu_bus_buffer.scala 175:123] + node _T_674 = or(_T_673, _T_667) @[lsu_bus_buffer.scala 175:123] + node _T_675 = or(_T_674, _T_672) @[lsu_bus_buffer.scala 175:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[lsu_bus_buffer.scala 176:60] + node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] + node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_679 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_680 = and(_T_678, _T_679) @[lsu_bus_buffer.scala 176:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[lsu_bus_buffer.scala 176:60] + node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] + node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_684 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_685 = and(_T_683, _T_684) @[lsu_bus_buffer.scala 176:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[lsu_bus_buffer.scala 176:60] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] + node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_689 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_690 = and(_T_688, _T_689) @[lsu_bus_buffer.scala 176:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[lsu_bus_buffer.scala 176:60] + node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] + node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_694 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 176:78] + node _T_695 = and(_T_693, _T_694) @[lsu_bus_buffer.scala 176:65] + node _T_696 = or(_T_680, _T_685) @[lsu_bus_buffer.scala 176:97] + node _T_697 = or(_T_696, _T_690) @[lsu_bus_buffer.scala 176:97] + node _T_698 = or(_T_697, _T_695) @[lsu_bus_buffer.scala 176:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[lsu_bus_buffer.scala 177:60] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] + node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_702 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_703 = and(_T_701, _T_702) @[lsu_bus_buffer.scala 177:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[lsu_bus_buffer.scala 177:60] + node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] + node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_707 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_708 = and(_T_706, _T_707) @[lsu_bus_buffer.scala 177:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[lsu_bus_buffer.scala 177:60] + node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_713 = and(_T_711, _T_712) @[lsu_bus_buffer.scala 177:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[lsu_bus_buffer.scala 177:60] + node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] + node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_717 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 177:78] + node _T_718 = and(_T_716, _T_717) @[lsu_bus_buffer.scala 177:65] + node _T_719 = or(_T_703, _T_708) @[lsu_bus_buffer.scala 177:97] + node _T_720 = or(_T_719, _T_713) @[lsu_bus_buffer.scala 177:97] + node _T_721 = or(_T_720, _T_718) @[lsu_bus_buffer.scala 177:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[lsu_bus_buffer.scala 178:60] + node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] + node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_725 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_726 = and(_T_724, _T_725) @[lsu_bus_buffer.scala 178:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[lsu_bus_buffer.scala 178:60] + node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] + node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_730 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_731 = and(_T_729, _T_730) @[lsu_bus_buffer.scala 178:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[lsu_bus_buffer.scala 178:60] + node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] + node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_735 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_736 = and(_T_734, _T_735) @[lsu_bus_buffer.scala 178:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[lsu_bus_buffer.scala 178:60] + node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] + node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_740 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 178:78] + node _T_741 = and(_T_739, _T_740) @[lsu_bus_buffer.scala 178:65] + node _T_742 = or(_T_726, _T_731) @[lsu_bus_buffer.scala 178:97] + node _T_743 = or(_T_742, _T_736) @[lsu_bus_buffer.scala 178:97] + node _T_744 = or(_T_743, _T_741) @[lsu_bus_buffer.scala 178:97] + node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] + node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 179:32] + node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 178:103] + io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 175:24] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 181:77] + node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = or(_T_750, _T_751) @[Mux.scala 27:72] + node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_r <= _T_754 @[Mux.scala 27:72] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 186:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[lsu_bus_buffer.scala 186:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 187:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[lsu_bus_buffer.scala 187:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[lsu_bus_buffer.scala 187:60] + node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 188:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[lsu_bus_buffer.scala 188:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[lsu_bus_buffer.scala 188:60] + node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 189:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[lsu_bus_buffer.scala 189:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[lsu_bus_buffer.scala 189:60] + node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] + node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_762, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_766, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = or(_T_769, _T_770) @[Mux.scala 27:72] + node _T_774 = or(_T_773, _T_771) @[Mux.scala 27:72] + node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] + wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 191:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[lsu_bus_buffer.scala 191:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 192:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[lsu_bus_buffer.scala 192:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[lsu_bus_buffer.scala 192:50] + node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 193:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[lsu_bus_buffer.scala 193:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[lsu_bus_buffer.scala 193:50] + node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 194:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[lsu_bus_buffer.scala 194:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[lsu_bus_buffer.scala 194:50] + node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_783, _T_785, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_787, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = or(_T_790, _T_791) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_792) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] + wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 196:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[lsu_bus_buffer.scala 196:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 197:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[lsu_bus_buffer.scala 197:24] + node _T_801 = bits(io.store_data_r, 31, 24) @[lsu_bus_buffer.scala 197:64] + node _T_802 = cat(UInt<24>("h00"), _T_801) @[Cat.scala 29:58] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 198:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[lsu_bus_buffer.scala 198:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[lsu_bus_buffer.scala 198:63] + node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 199:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[lsu_bus_buffer.scala 199:24] + node _T_809 = bits(io.store_data_r, 31, 8) @[lsu_bus_buffer.scala 199:62] + node _T_810 = cat(UInt<8>("h00"), _T_809) @[Cat.scala 29:58] + node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_804, _T_806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_808, _T_810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = or(_T_811, _T_812) @[Mux.scala 27:72] + node _T_816 = or(_T_815, _T_813) @[Mux.scala 27:72] + node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] + wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] + store_data_hi_r <= _T_817 @[Mux.scala 27:72] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 201:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[lsu_bus_buffer.scala 201:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 202:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[lsu_bus_buffer.scala 202:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[lsu_bus_buffer.scala 202:52] + node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 203:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[lsu_bus_buffer.scala 203:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[lsu_bus_buffer.scala 203:52] + node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 204:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[lsu_bus_buffer.scala 204:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[lsu_bus_buffer.scala 204:52] + node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] + node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_834 = mux(_T_825, _T_827, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_835 = mux(_T_829, _T_831, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_836 = or(_T_832, _T_833) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] + wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] + store_data_lo_r <= _T_838 @[Mux.scala 27:72] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[lsu_bus_buffer.scala 207:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[lsu_bus_buffer.scala 207:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[lsu_bus_buffer.scala 207:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 208:72] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[lsu_bus_buffer.scala 208:79] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[lsu_bus_buffer.scala 209:45] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[lsu_bus_buffer.scala 209:31] + node _T_845 = mux(io.lsu_pkt_r.bits.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = mux(io.lsu_pkt_r.bits.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_847 = mux(io.lsu_pkt_r.bits.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_848 = or(_T_845, _T_846) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] + wire is_aligned_r : UInt<1> @[Mux.scala 27:72] + is_aligned_r <= _T_849 @[Mux.scala 27:72] + node _T_850 = or(io.lsu_pkt_r.bits.load, io.no_word_merge_r) @[lsu_bus_buffer.scala 211:60] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[lsu_bus_buffer.scala 211:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 211:84] + node ibuf_byp = and(_T_851, _T_852) @[lsu_bus_buffer.scala 211:82] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 212:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[lsu_bus_buffer.scala 212:56] + node ibuf_wr_en = and(_T_853, _T_854) @[lsu_bus_buffer.scala 212:54] + wire ibuf_drain_vld : UInt<1> + ibuf_drain_vld <= UInt<1>("h00") + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 214:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[lsu_bus_buffer.scala 214:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 214:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 215:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[lsu_bus_buffer.scala 215:42] + node _T_859 = and(_T_858, ibuf_valid) @[lsu_bus_buffer.scala 215:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 215:112] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 215:137] + node _T_862 = neq(_T_860, _T_861) @[lsu_bus_buffer.scala 215:120] + node _T_863 = or(io.lsu_pkt_m.bits.load, _T_862) @[lsu_bus_buffer.scala 215:100] + node ibuf_force_drain = and(_T_859, _T_863) @[lsu_bus_buffer.scala 215:74] + wire ibuf_sideeffect : UInt<1> + ibuf_sideeffect <= UInt<1>("h00") + wire ibuf_timer : UInt<3> + ibuf_timer <= UInt<1>("h00") + wire ibuf_merge_en : UInt<1> + ibuf_merge_en <= UInt<1>("h00") + wire ibuf_merge_in : UInt<1> + ibuf_merge_in <= UInt<1>("h00") + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 220:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[lsu_bus_buffer.scala 220:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 220:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[lsu_bus_buffer.scala 220:82] + node _T_868 = and(_T_865, _T_867) @[lsu_bus_buffer.scala 220:80] + node _T_869 = or(_T_868, ibuf_byp) @[lsu_bus_buffer.scala 221:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[lsu_bus_buffer.scala 221:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[lsu_bus_buffer.scala 221:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 221:55] + node _T_873 = or(_T_871, _T_872) @[lsu_bus_buffer.scala 221:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[lsu_bus_buffer.scala 221:67] + node _T_875 = and(ibuf_valid, _T_874) @[lsu_bus_buffer.scala 220:32] + ibuf_drain_vld <= _T_875 @[lsu_bus_buffer.scala 220:18] + wire ibuf_tag : UInt<2> + ibuf_tag <= UInt<1>("h00") + wire WrPtr1_r : UInt<2> + WrPtr1_r <= UInt<1>("h00") + wire WrPtr0_r : UInt<2> + WrPtr0_r <= UInt<1>("h00") + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 226:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[lsu_bus_buffer.scala 226:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[lsu_bus_buffer.scala 226:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 229:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 230:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[lsu_bus_buffer.scala 230:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 230:95] + node _T_881 = or(_T_879, _T_880) @[lsu_bus_buffer.scala 230:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 231:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 231:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[lsu_bus_buffer.scala 231:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[lsu_bus_buffer.scala 230:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 235:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 235:45] + node _T_888 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 235:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[lsu_bus_buffer.scala 235:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[lsu_bus_buffer.scala 236:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 236:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[lsu_bus_buffer.scala 236:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[lsu_bus_buffer.scala 234:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 235:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 235:45] + node _T_897 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 235:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[lsu_bus_buffer.scala 235:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[lsu_bus_buffer.scala 236:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 236:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[lsu_bus_buffer.scala 236:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[lsu_bus_buffer.scala 234:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 235:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 235:45] + node _T_906 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 235:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[lsu_bus_buffer.scala 235:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[lsu_bus_buffer.scala 236:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 236:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[lsu_bus_buffer.scala 236:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[lsu_bus_buffer.scala 234:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 234:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 235:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 235:45] + node _T_915 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 235:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[lsu_bus_buffer.scala 235:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[lsu_bus_buffer.scala 236:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 236:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[lsu_bus_buffer.scala 236:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[lsu_bus_buffer.scala 234:46] + node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] + node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] + node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 237:60] + node _T_924 = bits(_T_923, 0, 0) @[lsu_bus_buffer.scala 237:81] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 237:95] + node _T_926 = tail(_T_925, 1) @[lsu_bus_buffer.scala 237:95] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[lsu_bus_buffer.scala 237:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[lsu_bus_buffer.scala 237:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 239:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 239:54] + node _T_930 = and(_T_929, ibuf_valid) @[lsu_bus_buffer.scala 239:80] + node _T_931 = and(_T_930, ibuf_write) @[lsu_bus_buffer.scala 239:93] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_buffer.scala 239:122] + node _T_933 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 239:142] + node _T_934 = eq(_T_932, _T_933) @[lsu_bus_buffer.scala 239:129] + node _T_935 = and(_T_931, _T_934) @[lsu_bus_buffer.scala 239:106] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 239:152] + node _T_937 = and(_T_935, _T_936) @[lsu_bus_buffer.scala 239:150] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 239:175] + node _T_939 = and(_T_937, _T_938) @[lsu_bus_buffer.scala 239:173] + ibuf_merge_en <= _T_939 @[lsu_bus_buffer.scala 239:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 240:20] + ibuf_merge_in <= _T_940 @[lsu_bus_buffer.scala 240:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[lsu_bus_buffer.scala 241:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 241:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 241:114] + node _T_945 = or(_T_943, _T_944) @[lsu_bus_buffer.scala 241:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 241:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[lsu_bus_buffer.scala 241:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[lsu_bus_buffer.scala 241:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 241:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 241:114] + node _T_952 = or(_T_950, _T_951) @[lsu_bus_buffer.scala 241:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 241:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[lsu_bus_buffer.scala 241:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[lsu_bus_buffer.scala 241:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 241:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 241:114] + node _T_959 = or(_T_957, _T_958) @[lsu_bus_buffer.scala 241:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 241:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[lsu_bus_buffer.scala 241:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 241:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[lsu_bus_buffer.scala 241:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 241:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 241:114] + node _T_966 = or(_T_964, _T_965) @[lsu_bus_buffer.scala 241:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 241:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[lsu_bus_buffer.scala 241:48] + node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] + node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] + node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[lsu_bus_buffer.scala 242:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 242:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 242:118] + node _T_975 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 242:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[lsu_bus_buffer.scala 242:81] + node _T_977 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 242:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[lsu_bus_buffer.scala 242:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[lsu_bus_buffer.scala 242:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 242:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 242:118] + node _T_983 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 242:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[lsu_bus_buffer.scala 242:81] + node _T_985 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 242:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[lsu_bus_buffer.scala 242:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[lsu_bus_buffer.scala 242:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 242:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 242:118] + node _T_991 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 242:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[lsu_bus_buffer.scala 242:81] + node _T_993 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 242:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[lsu_bus_buffer.scala 242:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 242:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[lsu_bus_buffer.scala 242:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 242:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 242:118] + node _T_999 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 242:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[lsu_bus_buffer.scala 242:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 242:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[lsu_bus_buffer.scala 242:45] + node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] + node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] + node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[lsu_bus_buffer.scala 244:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 244:93] + node _T_1007 = and(_T_1005, _T_1006) @[lsu_bus_buffer.scala 244:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 244:54] + _T_1008 <= _T_1007 @[lsu_bus_buffer.scala 244:54] + ibuf_valid <= _T_1008 @[lsu_bus_buffer.scala 244:14] + reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_tag <= _T_1009 @[lsu_bus_buffer.scala 245:12] + reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_dual : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dual <= io.ldst_dual_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_samedw : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_samedw <= ldst_samedw_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_nomerge : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_nomerge <= io.no_dword_merge_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1010 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_sideeffect <= _T_1010 @[lsu_bus_buffer.scala 250:19] + reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_unsign <= io.lsu_pkt_r.bits.unsign @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1011 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1011 <= io.lsu_pkt_r.bits.store @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_write <= _T_1011 @[lsu_bus_buffer.scala 252:14] + reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr of rvclkhdr @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1012 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1012 <= ibuf_addr_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 254:13] + reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 255:15] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1014 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1014 <= ibuf_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 256:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 257:55] + _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 257:55] + ibuf_timer <= _T_1015 @[lsu_bus_buffer.scala 257:14] + wire buf_numvld_wrcmd_any : UInt<4> + buf_numvld_wrcmd_any <= UInt<1>("h00") + wire buf_numvld_cmd_any : UInt<4> + buf_numvld_cmd_any <= UInt<1>("h00") + wire obuf_wr_timer : UInt<3> + obuf_wr_timer <= UInt<1>("h00") + wire buf_nomerge : UInt<1>[4] @[lsu_bus_buffer.scala 261:25] + buf_nomerge[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + buf_nomerge[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 262:15] + wire buf_sideeffect : UInt<4> + buf_sideeffect <= UInt<1>("h00") + wire obuf_force_wr_en : UInt<1> + obuf_force_wr_en <= UInt<1>("h00") + wire obuf_wr_en : UInt<1> + obuf_wr_en <= UInt<1>("h00") + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 267:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 267:72] + node _T_1018 = and(_T_1016, _T_1017) @[lsu_bus_buffer.scala 267:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 267:97] + node _T_1020 = and(_T_1018, _T_1019) @[lsu_bus_buffer.scala 267:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:5] + node _T_1022 = and(_T_1020, _T_1021) @[lsu_bus_buffer.scala 267:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 268:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 268:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 268:114] + node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1030 = mux(_T_1026, buf_nomerge[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1031 = or(_T_1027, _T_1028) @[Mux.scala 27:72] + node _T_1032 = or(_T_1031, _T_1029) @[Mux.scala 27:72] + node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] + wire _T_1034 : UInt<1> @[Mux.scala 27:72] + _T_1034 <= _T_1033 @[Mux.scala 27:72] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:31] + node _T_1036 = and(_T_1022, _T_1035) @[lsu_bus_buffer.scala 268:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 269:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 269:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 269:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 269:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 269:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 269:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 269:111] + node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1048 = mux(_T_1043, _T_1044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1049 = or(_T_1045, _T_1046) @[Mux.scala 27:72] + node _T_1050 = or(_T_1049, _T_1047) @[Mux.scala 27:72] + node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] + wire _T_1052 : UInt<1> @[Mux.scala 27:72] + _T_1052 <= _T_1051 @[Mux.scala 27:72] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:5] + node _T_1054 = and(_T_1036, _T_1053) @[lsu_bus_buffer.scala 268:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[lsu_bus_buffer.scala 269:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[lsu_bus_buffer.scala 270:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 270:95] + node _T_1058 = and(_T_1056, _T_1057) @[lsu_bus_buffer.scala 270:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 270:123] + node _T_1060 = tail(_T_1059, 1) @[lsu_bus_buffer.scala 270:123] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[lsu_bus_buffer.scala 270:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[lsu_bus_buffer.scala 270:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[lsu_bus_buffer.scala 271:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:60] + node _T_1065 = and(_T_1063, _T_1064) @[lsu_bus_buffer.scala 271:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 271:93] + node _T_1067 = and(_T_1065, _T_1066) @[lsu_bus_buffer.scala 271:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 271:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 271:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 271:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 271:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 271:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 271:228] + node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = or(_T_1077, _T_1078) @[Mux.scala 27:72] + node _T_1082 = or(_T_1081, _T_1079) @[Mux.scala 27:72] + node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] + wire _T_1084 : UInt<30> @[Mux.scala 27:72] + _T_1084 <= _T_1083 @[Mux.scala 27:72] + node _T_1085 = neq(_T_1068, _T_1084) @[lsu_bus_buffer.scala 271:123] + node _T_1086 = and(_T_1067, _T_1085) @[lsu_bus_buffer.scala 271:101] + obuf_force_wr_en <= _T_1086 @[lsu_bus_buffer.scala 271:20] + wire buf_numvld_pend_any : UInt<4> + buf_numvld_pend_any <= UInt<1>("h00") + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 273:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[lsu_bus_buffer.scala 273:31] + node _T_1089 = eq(io.lsu_pkt_r.bits.store, UInt<1>("h00")) @[lsu_bus_buffer.scala 273:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[lsu_bus_buffer.scala 273:89] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[lsu_bus_buffer.scala 273:61] + wire bus_sideeffect_pend : UInt<1> + bus_sideeffect_pend <= UInt<1>("h00") + wire found_cmdptr0 : UInt<1> + found_cmdptr0 <= UInt<1>("h00") + wire buf_cmd_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 276:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:24] + wire buf_dual : UInt<1>[4] @[lsu_bus_buffer.scala 278:22] + buf_dual[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + buf_dual[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 279:12] + wire buf_samedw : UInt<1>[4] @[lsu_bus_buffer.scala 280:24] + buf_samedw[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + buf_samedw[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 281:14] + wire found_cmdptr1 : UInt<1> + found_cmdptr1 <= UInt<1>("h00") + wire bus_cmd_ready : UInt<1> + bus_cmd_ready <= UInt<1>("h00") + wire obuf_valid : UInt<1> + obuf_valid <= UInt<1>("h00") + wire obuf_nosend : UInt<1> + obuf_nosend <= UInt<1>("h00") + wire bus_addr_match_pending : UInt<1> + bus_addr_match_pending <= UInt<1>("h00") + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[lsu_bus_buffer.scala 289:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[lsu_bus_buffer.scala 289:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[lsu_bus_buffer.scala 289:52] + node _T_1094 = and(_T_1091, _T_1093) @[lsu_bus_buffer.scala 289:50] + node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1099 = mux(_T_1095, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_1096, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1097, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_1098, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = or(_T_1099, _T_1100) @[Mux.scala 27:72] + node _T_1104 = or(_T_1103, _T_1101) @[Mux.scala 27:72] + node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] + wire _T_1106 : UInt<3> @[Mux.scala 27:72] + _T_1106 <= _T_1105 @[Mux.scala 27:72] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[lsu_bus_buffer.scala 290:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[lsu_bus_buffer.scala 290:47] + node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1113 = bits(_T_1111, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1115 = bits(_T_1111, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1117 = bits(_T_1111, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1119 = bits(_T_1111, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1120 = mux(_T_1112, _T_1113, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1116, _T_1117, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1118, _T_1119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = or(_T_1120, _T_1121) @[Mux.scala 27:72] + node _T_1125 = or(_T_1124, _T_1122) @[Mux.scala 27:72] + node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] + wire _T_1127 : UInt<1> @[Mux.scala 27:72] + _T_1127 <= _T_1126 @[Mux.scala 27:72] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:23] + node _T_1129 = and(_T_1108, _T_1128) @[lsu_bus_buffer.scala 291:21] + node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1131 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1133 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1135 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1137 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1138 = mux(_T_1130, _T_1131, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1139 = mux(_T_1132, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1140 = mux(_T_1134, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1141 = mux(_T_1136, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1142 = or(_T_1138, _T_1139) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1140) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] + wire _T_1145 : UInt<1> @[Mux.scala 27:72] + _T_1145 <= _T_1144 @[Mux.scala 27:72] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[lsu_bus_buffer.scala 291:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:105] + node _T_1148 = and(_T_1129, _T_1147) @[lsu_bus_buffer.scala 291:103] + node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] + node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] + node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1153 = bits(_T_1151, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1155 = bits(_T_1151, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1157 = bits(_T_1151, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1159 = bits(_T_1151, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1160 = mux(_T_1152, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1161 = mux(_T_1154, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1162 = mux(_T_1156, _T_1157, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1163 = mux(_T_1158, _T_1159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1164 = or(_T_1160, _T_1161) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1162) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1163) @[Mux.scala 27:72] + wire _T_1167 : UInt<1> @[Mux.scala 27:72] + _T_1167 <= _T_1166 @[Mux.scala 27:72] + node _T_1168 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1170 = cat(_T_1169, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1172 = bits(_T_1170, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1174 = bits(_T_1170, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1176 = bits(_T_1170, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1178 = bits(_T_1170, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1179 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1180 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1181 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1182 = mux(_T_1177, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1183 = or(_T_1179, _T_1180) @[Mux.scala 27:72] + node _T_1184 = or(_T_1183, _T_1181) @[Mux.scala 27:72] + node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] + wire _T_1186 : UInt<1> @[Mux.scala 27:72] + _T_1186 <= _T_1185 @[Mux.scala 27:72] + node _T_1187 = and(_T_1167, _T_1186) @[lsu_bus_buffer.scala 292:77] + node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1189 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1191 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1193 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1195 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1194, _T_1195, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = or(_T_1196, _T_1197) @[Mux.scala 27:72] + node _T_1201 = or(_T_1200, _T_1198) @[Mux.scala 27:72] + node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] + wire _T_1203 : UInt<1> @[Mux.scala 27:72] + _T_1203 <= _T_1202 @[Mux.scala 27:72] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:150] + node _T_1205 = and(_T_1187, _T_1204) @[lsu_bus_buffer.scala 292:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[lsu_bus_buffer.scala 292:181] + node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] + node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] + node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] + node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1212 = bits(_T_1210, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1214 = bits(_T_1210, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1216 = bits(_T_1210, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1218 = bits(_T_1210, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1219 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = or(_T_1219, _T_1220) @[Mux.scala 27:72] + node _T_1224 = or(_T_1223, _T_1221) @[Mux.scala 27:72] + node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] + wire _T_1226 : UInt<1> @[Mux.scala 27:72] + _T_1226 <= _T_1225 @[Mux.scala 27:72] + node _T_1227 = or(_T_1207, _T_1226) @[lsu_bus_buffer.scala 292:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[lsu_bus_buffer.scala 292:269] + node _T_1229 = and(_T_1148, _T_1228) @[lsu_bus_buffer.scala 291:164] + node _T_1230 = or(_T_1094, _T_1229) @[lsu_bus_buffer.scala 289:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[lsu_bus_buffer.scala 293:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[lsu_bus_buffer.scala 293:60] + node _T_1234 = and(_T_1230, _T_1233) @[lsu_bus_buffer.scala 293:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:77] + node _T_1236 = and(_T_1234, _T_1235) @[lsu_bus_buffer.scala 293:75] + node _T_1237 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:94] + node _T_1238 = and(_T_1236, _T_1237) @[lsu_bus_buffer.scala 293:92] + node _T_1239 = and(_T_1238, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 293:118] + obuf_wr_en <= _T_1239 @[lsu_bus_buffer.scala 289:14] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_1240 = and(obuf_valid, obuf_nosend) @[lsu_bus_buffer.scala 296:47] + node _T_1241 = or(bus_cmd_sent, _T_1240) @[lsu_bus_buffer.scala 296:33] + node _T_1242 = eq(obuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 296:65] + node _T_1243 = and(_T_1241, _T_1242) @[lsu_bus_buffer.scala 296:63] + node _T_1244 = and(_T_1243, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 296:77] + node obuf_rst = or(_T_1244, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 296:98] + node _T_1245 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1246 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1247 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1248 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1249 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1250 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1251 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1252 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1253 = mux(_T_1245, _T_1246, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1254 = mux(_T_1247, _T_1248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1255 = mux(_T_1249, _T_1250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1256 = mux(_T_1251, _T_1252, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1257 = or(_T_1253, _T_1254) @[Mux.scala 27:72] + node _T_1258 = or(_T_1257, _T_1255) @[Mux.scala 27:72] + node _T_1259 = or(_T_1258, _T_1256) @[Mux.scala 27:72] + wire _T_1260 : UInt<1> @[Mux.scala 27:72] + _T_1260 <= _T_1259 @[Mux.scala 27:72] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1260) @[lsu_bus_buffer.scala 297:26] + node _T_1261 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1262 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1263 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1264 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1265 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1266 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1267 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1268 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1269 = mux(_T_1261, _T_1262, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1270 = mux(_T_1263, _T_1264, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1271 = mux(_T_1265, _T_1266, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1272 = mux(_T_1267, _T_1268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1273 = or(_T_1269, _T_1270) @[Mux.scala 27:72] + node _T_1274 = or(_T_1273, _T_1271) @[Mux.scala 27:72] + node _T_1275 = or(_T_1274, _T_1272) @[Mux.scala 27:72] + wire _T_1276 : UInt<1> @[Mux.scala 27:72] + _T_1276 <= _T_1275 @[Mux.scala 27:72] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1276) @[lsu_bus_buffer.scala 298:31] + node _T_1277 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1278 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1279 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1280 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1281 = mux(_T_1277, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1282 = mux(_T_1278, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1283 = mux(_T_1279, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1284 = mux(_T_1280, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1285 = or(_T_1281, _T_1282) @[Mux.scala 27:72] + node _T_1286 = or(_T_1285, _T_1283) @[Mux.scala 27:72] + node _T_1287 = or(_T_1286, _T_1284) @[Mux.scala 27:72] + wire _T_1288 : UInt<32> @[Mux.scala 27:72] + _T_1288 <= _T_1287 @[Mux.scala 27:72] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1288) @[lsu_bus_buffer.scala 299:25] + wire buf_sz : UInt<2>[4] @[lsu_bus_buffer.scala 300:20] + buf_sz[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + buf_sz[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 301:10] + node _T_1289 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_1290 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1291 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1292 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1293 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1294 = mux(_T_1290, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1295 = mux(_T_1291, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1296 = mux(_T_1292, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1297 = mux(_T_1293, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1298 = or(_T_1294, _T_1295) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1296) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1297) @[Mux.scala 27:72] + wire _T_1301 : UInt<2> @[Mux.scala 27:72] + _T_1301 <= _T_1300 @[Mux.scala 27:72] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1289, _T_1301) @[lsu_bus_buffer.scala 302:23] + wire obuf_merge_en : UInt<1> + obuf_merge_en <= UInt<1>("h00") + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 305:25] + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 307:25] + wire obuf_cmd_done : UInt<1> + obuf_cmd_done <= UInt<1>("h00") + wire bus_wcmd_sent : UInt<1> + bus_wcmd_sent <= UInt<1>("h00") + node _T_1302 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 310:39] + node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[lsu_bus_buffer.scala 310:26] + node _T_1304 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 310:68] + node obuf_cmd_done_in = and(_T_1303, _T_1304) @[lsu_bus_buffer.scala 310:51] + wire obuf_data_done : UInt<1> + obuf_data_done <= UInt<1>("h00") + wire bus_wdata_sent : UInt<1> + bus_wdata_sent <= UInt<1>("h00") + node _T_1305 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 313:40] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[lsu_bus_buffer.scala 313:27] + node _T_1307 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 313:70] + node obuf_data_done_in = and(_T_1306, _T_1307) @[lsu_bus_buffer.scala 313:52] + node _T_1308 = bits(obuf_sz_in, 1, 0) @[lsu_bus_buffer.scala 314:67] + node _T_1309 = eq(_T_1308, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:72] + node _T_1310 = bits(obuf_sz_in, 0, 0) @[lsu_bus_buffer.scala 314:92] + node _T_1311 = bits(obuf_addr_in, 0, 0) @[lsu_bus_buffer.scala 314:111] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:98] + node _T_1313 = and(_T_1310, _T_1312) @[lsu_bus_buffer.scala 314:96] + node _T_1314 = or(_T_1309, _T_1313) @[lsu_bus_buffer.scala 314:79] + node _T_1315 = bits(obuf_sz_in, 1, 1) @[lsu_bus_buffer.scala 314:129] + node _T_1316 = bits(obuf_addr_in, 1, 0) @[lsu_bus_buffer.scala 314:147] + node _T_1317 = orr(_T_1316) @[lsu_bus_buffer.scala 314:153] + node _T_1318 = eq(_T_1317, UInt<1>("h00")) @[lsu_bus_buffer.scala 314:134] + node _T_1319 = and(_T_1315, _T_1318) @[lsu_bus_buffer.scala 314:132] + node _T_1320 = or(_T_1314, _T_1319) @[lsu_bus_buffer.scala 314:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1320) @[lsu_bus_buffer.scala 314:28] + wire obuf_nosend_in : UInt<1> + obuf_nosend_in <= UInt<1>("h00") + wire obuf_rdrsp_pend : UInt<1> + obuf_rdrsp_pend <= UInt<1>("h00") + wire bus_rsp_read : UInt<1> + bus_rsp_read <= UInt<1>("h00") + wire bus_rsp_read_tag : UInt<3> + bus_rsp_read_tag <= UInt<1>("h00") + wire obuf_rdrsp_tag : UInt<3> + obuf_rdrsp_tag <= UInt<1>("h00") + wire obuf_write : UInt<1> + obuf_write <= UInt<1>("h00") + node _T_1321 = eq(obuf_nosend_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:45] + node _T_1322 = and(obuf_wr_en, _T_1321) @[lsu_bus_buffer.scala 322:43] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:30] + node _T_1324 = and(_T_1323, obuf_rdrsp_pend) @[lsu_bus_buffer.scala 322:62] + node _T_1325 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 322:117] + node _T_1326 = and(bus_rsp_read, _T_1325) @[lsu_bus_buffer.scala 322:97] + node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:82] + node _T_1328 = and(_T_1324, _T_1327) @[lsu_bus_buffer.scala 322:80] + node _T_1329 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:157] + node _T_1330 = and(bus_cmd_sent, _T_1329) @[lsu_bus_buffer.scala 322:155] + node _T_1331 = or(_T_1328, _T_1330) @[lsu_bus_buffer.scala 322:139] + node _T_1332 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:173] + node obuf_rdrsp_pend_in = and(_T_1331, _T_1332) @[lsu_bus_buffer.scala 322:171] + node obuf_rdrsp_pend_en = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 323:47] + wire obuf_tag0 : UInt<3> + obuf_tag0 <= UInt<1>("h00") + node _T_1333 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 325:46] + node _T_1334 = and(bus_cmd_sent, _T_1333) @[lsu_bus_buffer.scala 325:44] + node obuf_rdrsp_tag_in = mux(_T_1334, obuf_tag0, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 325:30] + wire obuf_addr : UInt<32> + obuf_addr <= UInt<1>("h00") + wire obuf_sideeffect : UInt<1> + obuf_sideeffect <= UInt<1>("h00") + node _T_1335 = bits(obuf_addr_in, 31, 3) @[lsu_bus_buffer.scala 328:34] + node _T_1336 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 328:52] + node _T_1337 = eq(_T_1335, _T_1336) @[lsu_bus_buffer.scala 328:40] + node _T_1338 = and(_T_1337, obuf_aligned_in) @[lsu_bus_buffer.scala 328:60] + node _T_1339 = eq(obuf_sideeffect, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:80] + node _T_1340 = and(_T_1338, _T_1339) @[lsu_bus_buffer.scala 328:78] + node _T_1341 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:99] + node _T_1342 = and(_T_1340, _T_1341) @[lsu_bus_buffer.scala 328:97] + node _T_1343 = eq(obuf_write_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:113] + node _T_1344 = and(_T_1342, _T_1343) @[lsu_bus_buffer.scala 328:111] + node _T_1345 = eq(io.tlu_busbuff.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:130] + node _T_1346 = and(_T_1344, _T_1345) @[lsu_bus_buffer.scala 328:128] + node _T_1347 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 329:20] + node _T_1348 = and(obuf_valid, _T_1347) @[lsu_bus_buffer.scala 329:18] + node _T_1349 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 329:90] + node _T_1350 = and(bus_rsp_read, _T_1349) @[lsu_bus_buffer.scala 329:70] + node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[lsu_bus_buffer.scala 329:55] + node _T_1352 = and(obuf_rdrsp_pend, _T_1351) @[lsu_bus_buffer.scala 329:53] + node _T_1353 = or(_T_1348, _T_1352) @[lsu_bus_buffer.scala 329:34] + node _T_1354 = and(_T_1346, _T_1353) @[lsu_bus_buffer.scala 328:177] + obuf_nosend_in <= _T_1354 @[lsu_bus_buffer.scala 328:18] + node _T_1355 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 330:60] + node _T_1356 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1357 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] + node _T_1358 = mux(_T_1355, _T_1356, _T_1357) @[lsu_bus_buffer.scala 330:46] + node _T_1359 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1360 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1361 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1362 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1363 = mux(_T_1359, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1364 = mux(_T_1360, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1365 = mux(_T_1361, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1362, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = or(_T_1363, _T_1364) @[Mux.scala 27:72] + node _T_1368 = or(_T_1367, _T_1365) @[Mux.scala 27:72] + node _T_1369 = or(_T_1368, _T_1366) @[Mux.scala 27:72] + wire _T_1370 : UInt<32> @[Mux.scala 27:72] + _T_1370 <= _T_1369 @[Mux.scala 27:72] + node _T_1371 = bits(_T_1370, 2, 2) @[lsu_bus_buffer.scala 331:36] + node _T_1372 = bits(_T_1371, 0, 0) @[lsu_bus_buffer.scala 331:46] + node _T_1373 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1374 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1375 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1376 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1377 = mux(_T_1373, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1378 = mux(_T_1374, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1379 = mux(_T_1375, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1376, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = or(_T_1377, _T_1378) @[Mux.scala 27:72] + node _T_1382 = or(_T_1381, _T_1379) @[Mux.scala 27:72] + node _T_1383 = or(_T_1382, _T_1380) @[Mux.scala 27:72] + wire _T_1384 : UInt<4> @[Mux.scala 27:72] + _T_1384 <= _T_1383 @[Mux.scala 27:72] + node _T_1385 = cat(_T_1384, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1386 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1387 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1388 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1389 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1390 = mux(_T_1386, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1391 = mux(_T_1387, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1392 = mux(_T_1388, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1393 = mux(_T_1389, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1394 = or(_T_1390, _T_1391) @[Mux.scala 27:72] + node _T_1395 = or(_T_1394, _T_1392) @[Mux.scala 27:72] + node _T_1396 = or(_T_1395, _T_1393) @[Mux.scala 27:72] + wire _T_1397 : UInt<4> @[Mux.scala 27:72] + _T_1397 <= _T_1396 @[Mux.scala 27:72] + node _T_1398 = cat(UInt<4>("h00"), _T_1397) @[Cat.scala 29:58] + node _T_1399 = mux(_T_1372, _T_1385, _T_1398) @[lsu_bus_buffer.scala 331:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1358, _T_1399) @[lsu_bus_buffer.scala 330:28] + node _T_1400 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 332:60] + node _T_1401 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1402 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] + node _T_1403 = mux(_T_1400, _T_1401, _T_1402) @[lsu_bus_buffer.scala 332:46] + node _T_1404 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1405 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1406 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1407 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1408 = mux(_T_1404, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1409 = mux(_T_1405, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1410 = mux(_T_1406, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1411 = mux(_T_1407, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1412 = or(_T_1408, _T_1409) @[Mux.scala 27:72] + node _T_1413 = or(_T_1412, _T_1410) @[Mux.scala 27:72] + node _T_1414 = or(_T_1413, _T_1411) @[Mux.scala 27:72] + wire _T_1415 : UInt<32> @[Mux.scala 27:72] + _T_1415 <= _T_1414 @[Mux.scala 27:72] + node _T_1416 = bits(_T_1415, 2, 2) @[lsu_bus_buffer.scala 333:36] + node _T_1417 = bits(_T_1416, 0, 0) @[lsu_bus_buffer.scala 333:46] + node _T_1418 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1419 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1420 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1421 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1422 = mux(_T_1418, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1423 = mux(_T_1419, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1424 = mux(_T_1420, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1425 = mux(_T_1421, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = or(_T_1422, _T_1423) @[Mux.scala 27:72] + node _T_1427 = or(_T_1426, _T_1424) @[Mux.scala 27:72] + node _T_1428 = or(_T_1427, _T_1425) @[Mux.scala 27:72] + wire _T_1429 : UInt<4> @[Mux.scala 27:72] + _T_1429 <= _T_1428 @[Mux.scala 27:72] + node _T_1430 = cat(_T_1429, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1431 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1432 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1433 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1434 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1435 = mux(_T_1431, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1436 = mux(_T_1432, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1437 = mux(_T_1433, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1438 = mux(_T_1434, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1439 = or(_T_1435, _T_1436) @[Mux.scala 27:72] + node _T_1440 = or(_T_1439, _T_1437) @[Mux.scala 27:72] + node _T_1441 = or(_T_1440, _T_1438) @[Mux.scala 27:72] + wire _T_1442 : UInt<4> @[Mux.scala 27:72] + _T_1442 <= _T_1441 @[Mux.scala 27:72] + node _T_1443 = cat(UInt<4>("h00"), _T_1442) @[Cat.scala 29:58] + node _T_1444 = mux(_T_1417, _T_1430, _T_1443) @[lsu_bus_buffer.scala 333:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1403, _T_1444) @[lsu_bus_buffer.scala 332:28] + node _T_1445 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 335:58] + node _T_1446 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1447 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] + node _T_1448 = mux(_T_1445, _T_1446, _T_1447) @[lsu_bus_buffer.scala 335:44] + node _T_1449 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1450 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1451 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1452 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1453 = mux(_T_1449, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1454 = mux(_T_1450, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1455 = mux(_T_1451, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = mux(_T_1452, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1457 = or(_T_1453, _T_1454) @[Mux.scala 27:72] + node _T_1458 = or(_T_1457, _T_1455) @[Mux.scala 27:72] + node _T_1459 = or(_T_1458, _T_1456) @[Mux.scala 27:72] + wire _T_1460 : UInt<32> @[Mux.scala 27:72] + _T_1460 <= _T_1459 @[Mux.scala 27:72] + node _T_1461 = bits(_T_1460, 2, 2) @[lsu_bus_buffer.scala 336:36] + node _T_1462 = bits(_T_1461, 0, 0) @[lsu_bus_buffer.scala 336:46] + node _T_1463 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1464 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1465 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1466 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1467 = mux(_T_1463, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1468 = mux(_T_1464, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1469 = mux(_T_1465, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1466, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = or(_T_1467, _T_1468) @[Mux.scala 27:72] + node _T_1472 = or(_T_1471, _T_1469) @[Mux.scala 27:72] + node _T_1473 = or(_T_1472, _T_1470) @[Mux.scala 27:72] + wire _T_1474 : UInt<32> @[Mux.scala 27:72] + _T_1474 <= _T_1473 @[Mux.scala 27:72] + node _T_1475 = cat(_T_1474, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1476 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1477 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1478 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1479 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1480 = mux(_T_1476, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1477, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1478, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1479, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = or(_T_1480, _T_1481) @[Mux.scala 27:72] + node _T_1485 = or(_T_1484, _T_1482) @[Mux.scala 27:72] + node _T_1486 = or(_T_1485, _T_1483) @[Mux.scala 27:72] + wire _T_1487 : UInt<32> @[Mux.scala 27:72] + _T_1487 <= _T_1486 @[Mux.scala 27:72] + node _T_1488 = cat(UInt<32>("h00"), _T_1487) @[Cat.scala 29:58] + node _T_1489 = mux(_T_1462, _T_1475, _T_1488) @[lsu_bus_buffer.scala 336:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1448, _T_1489) @[lsu_bus_buffer.scala 335:26] + node _T_1490 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 337:58] + node _T_1491 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1492 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] + node _T_1493 = mux(_T_1490, _T_1491, _T_1492) @[lsu_bus_buffer.scala 337:44] + node _T_1494 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1495 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1496 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1497 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1498 = mux(_T_1494, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1495, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1496, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1497, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = or(_T_1498, _T_1499) @[Mux.scala 27:72] + node _T_1503 = or(_T_1502, _T_1500) @[Mux.scala 27:72] + node _T_1504 = or(_T_1503, _T_1501) @[Mux.scala 27:72] + wire _T_1505 : UInt<32> @[Mux.scala 27:72] + _T_1505 <= _T_1504 @[Mux.scala 27:72] + node _T_1506 = bits(_T_1505, 2, 2) @[lsu_bus_buffer.scala 338:36] + node _T_1507 = bits(_T_1506, 0, 0) @[lsu_bus_buffer.scala 338:46] + node _T_1508 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1509 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1510 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1511 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1512 = mux(_T_1508, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1509, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1510, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1511, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = or(_T_1512, _T_1513) @[Mux.scala 27:72] + node _T_1517 = or(_T_1516, _T_1514) @[Mux.scala 27:72] + node _T_1518 = or(_T_1517, _T_1515) @[Mux.scala 27:72] + wire _T_1519 : UInt<32> @[Mux.scala 27:72] + _T_1519 <= _T_1518 @[Mux.scala 27:72] + node _T_1520 = cat(_T_1519, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1521 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1522 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1523 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1524 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1525 = mux(_T_1521, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1522, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1523, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1524, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = or(_T_1525, _T_1526) @[Mux.scala 27:72] + node _T_1530 = or(_T_1529, _T_1527) @[Mux.scala 27:72] + node _T_1531 = or(_T_1530, _T_1528) @[Mux.scala 27:72] + wire _T_1532 : UInt<32> @[Mux.scala 27:72] + _T_1532 <= _T_1531 @[Mux.scala 27:72] + node _T_1533 = cat(UInt<32>("h00"), _T_1532) @[Cat.scala 29:58] + node _T_1534 = mux(_T_1507, _T_1520, _T_1533) @[lsu_bus_buffer.scala 338:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1493, _T_1534) @[lsu_bus_buffer.scala 337:26] + node _T_1535 = bits(obuf_byteen0_in, 0, 0) @[lsu_bus_buffer.scala 339:59] + node _T_1536 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 339:97] + node _T_1537 = and(obuf_merge_en, _T_1536) @[lsu_bus_buffer.scala 339:80] + node _T_1538 = or(_T_1535, _T_1537) @[lsu_bus_buffer.scala 339:63] + node _T_1539 = bits(obuf_byteen0_in, 1, 1) @[lsu_bus_buffer.scala 339:59] + node _T_1540 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 339:97] + node _T_1541 = and(obuf_merge_en, _T_1540) @[lsu_bus_buffer.scala 339:80] + node _T_1542 = or(_T_1539, _T_1541) @[lsu_bus_buffer.scala 339:63] + node _T_1543 = bits(obuf_byteen0_in, 2, 2) @[lsu_bus_buffer.scala 339:59] + node _T_1544 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 339:97] + node _T_1545 = and(obuf_merge_en, _T_1544) @[lsu_bus_buffer.scala 339:80] + node _T_1546 = or(_T_1543, _T_1545) @[lsu_bus_buffer.scala 339:63] + node _T_1547 = bits(obuf_byteen0_in, 3, 3) @[lsu_bus_buffer.scala 339:59] + node _T_1548 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 339:97] + node _T_1549 = and(obuf_merge_en, _T_1548) @[lsu_bus_buffer.scala 339:80] + node _T_1550 = or(_T_1547, _T_1549) @[lsu_bus_buffer.scala 339:63] + node _T_1551 = bits(obuf_byteen0_in, 4, 4) @[lsu_bus_buffer.scala 339:59] + node _T_1552 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 339:97] + node _T_1553 = and(obuf_merge_en, _T_1552) @[lsu_bus_buffer.scala 339:80] + node _T_1554 = or(_T_1551, _T_1553) @[lsu_bus_buffer.scala 339:63] + node _T_1555 = bits(obuf_byteen0_in, 5, 5) @[lsu_bus_buffer.scala 339:59] + node _T_1556 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 339:97] + node _T_1557 = and(obuf_merge_en, _T_1556) @[lsu_bus_buffer.scala 339:80] + node _T_1558 = or(_T_1555, _T_1557) @[lsu_bus_buffer.scala 339:63] + node _T_1559 = bits(obuf_byteen0_in, 6, 6) @[lsu_bus_buffer.scala 339:59] + node _T_1560 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 339:97] + node _T_1561 = and(obuf_merge_en, _T_1560) @[lsu_bus_buffer.scala 339:80] + node _T_1562 = or(_T_1559, _T_1561) @[lsu_bus_buffer.scala 339:63] + node _T_1563 = bits(obuf_byteen0_in, 7, 7) @[lsu_bus_buffer.scala 339:59] + node _T_1564 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 339:97] + node _T_1565 = and(obuf_merge_en, _T_1564) @[lsu_bus_buffer.scala 339:80] + node _T_1566 = or(_T_1563, _T_1565) @[lsu_bus_buffer.scala 339:63] + node _T_1567 = cat(_T_1566, _T_1562) @[Cat.scala 29:58] + node _T_1568 = cat(_T_1567, _T_1558) @[Cat.scala 29:58] + node _T_1569 = cat(_T_1568, _T_1554) @[Cat.scala 29:58] + node _T_1570 = cat(_T_1569, _T_1550) @[Cat.scala 29:58] + node _T_1571 = cat(_T_1570, _T_1546) @[Cat.scala 29:58] + node _T_1572 = cat(_T_1571, _T_1542) @[Cat.scala 29:58] + node obuf_byteen_in = cat(_T_1572, _T_1538) @[Cat.scala 29:58] + node _T_1573 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 340:76] + node _T_1574 = and(obuf_merge_en, _T_1573) @[lsu_bus_buffer.scala 340:59] + node _T_1575 = bits(obuf_data1_in, 7, 0) @[lsu_bus_buffer.scala 340:94] + node _T_1576 = bits(obuf_data0_in, 7, 0) @[lsu_bus_buffer.scala 340:123] + node _T_1577 = mux(_T_1574, _T_1575, _T_1576) @[lsu_bus_buffer.scala 340:44] + node _T_1578 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 340:76] + node _T_1579 = and(obuf_merge_en, _T_1578) @[lsu_bus_buffer.scala 340:59] + node _T_1580 = bits(obuf_data1_in, 15, 8) @[lsu_bus_buffer.scala 340:94] + node _T_1581 = bits(obuf_data0_in, 15, 8) @[lsu_bus_buffer.scala 340:123] + node _T_1582 = mux(_T_1579, _T_1580, _T_1581) @[lsu_bus_buffer.scala 340:44] + node _T_1583 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 340:76] + node _T_1584 = and(obuf_merge_en, _T_1583) @[lsu_bus_buffer.scala 340:59] + node _T_1585 = bits(obuf_data1_in, 23, 16) @[lsu_bus_buffer.scala 340:94] + node _T_1586 = bits(obuf_data0_in, 23, 16) @[lsu_bus_buffer.scala 340:123] + node _T_1587 = mux(_T_1584, _T_1585, _T_1586) @[lsu_bus_buffer.scala 340:44] + node _T_1588 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 340:76] + node _T_1589 = and(obuf_merge_en, _T_1588) @[lsu_bus_buffer.scala 340:59] + node _T_1590 = bits(obuf_data1_in, 31, 24) @[lsu_bus_buffer.scala 340:94] + node _T_1591 = bits(obuf_data0_in, 31, 24) @[lsu_bus_buffer.scala 340:123] + node _T_1592 = mux(_T_1589, _T_1590, _T_1591) @[lsu_bus_buffer.scala 340:44] + node _T_1593 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 340:76] + node _T_1594 = and(obuf_merge_en, _T_1593) @[lsu_bus_buffer.scala 340:59] + node _T_1595 = bits(obuf_data1_in, 39, 32) @[lsu_bus_buffer.scala 340:94] + node _T_1596 = bits(obuf_data0_in, 39, 32) @[lsu_bus_buffer.scala 340:123] + node _T_1597 = mux(_T_1594, _T_1595, _T_1596) @[lsu_bus_buffer.scala 340:44] + node _T_1598 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 340:76] + node _T_1599 = and(obuf_merge_en, _T_1598) @[lsu_bus_buffer.scala 340:59] + node _T_1600 = bits(obuf_data1_in, 47, 40) @[lsu_bus_buffer.scala 340:94] + node _T_1601 = bits(obuf_data0_in, 47, 40) @[lsu_bus_buffer.scala 340:123] + node _T_1602 = mux(_T_1599, _T_1600, _T_1601) @[lsu_bus_buffer.scala 340:44] + node _T_1603 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 340:76] + node _T_1604 = and(obuf_merge_en, _T_1603) @[lsu_bus_buffer.scala 340:59] + node _T_1605 = bits(obuf_data1_in, 55, 48) @[lsu_bus_buffer.scala 340:94] + node _T_1606 = bits(obuf_data0_in, 55, 48) @[lsu_bus_buffer.scala 340:123] + node _T_1607 = mux(_T_1604, _T_1605, _T_1606) @[lsu_bus_buffer.scala 340:44] + node _T_1608 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 340:76] + node _T_1609 = and(obuf_merge_en, _T_1608) @[lsu_bus_buffer.scala 340:59] + node _T_1610 = bits(obuf_data1_in, 63, 56) @[lsu_bus_buffer.scala 340:94] + node _T_1611 = bits(obuf_data0_in, 63, 56) @[lsu_bus_buffer.scala 340:123] + node _T_1612 = mux(_T_1609, _T_1610, _T_1611) @[lsu_bus_buffer.scala 340:44] + node _T_1613 = cat(_T_1612, _T_1607) @[Cat.scala 29:58] + node _T_1614 = cat(_T_1613, _T_1602) @[Cat.scala 29:58] + node _T_1615 = cat(_T_1614, _T_1597) @[Cat.scala 29:58] + node _T_1616 = cat(_T_1615, _T_1592) @[Cat.scala 29:58] + node _T_1617 = cat(_T_1616, _T_1587) @[Cat.scala 29:58] + node _T_1618 = cat(_T_1617, _T_1582) @[Cat.scala 29:58] + node obuf_data_in = cat(_T_1618, _T_1577) @[Cat.scala 29:58] + wire buf_dualhi : UInt<1>[4] @[lsu_bus_buffer.scala 342:24] + buf_dualhi[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + buf_dualhi[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 343:14] + node _T_1619 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 344:30] + node _T_1620 = and(_T_1619, found_cmdptr0) @[lsu_bus_buffer.scala 344:43] + node _T_1621 = and(_T_1620, found_cmdptr1) @[lsu_bus_buffer.scala 344:59] + node _T_1622 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1623 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1624 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1625 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1626 = mux(_T_1622, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1627 = mux(_T_1623, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1628 = mux(_T_1624, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1629 = mux(_T_1625, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1630 = or(_T_1626, _T_1627) @[Mux.scala 27:72] + node _T_1631 = or(_T_1630, _T_1628) @[Mux.scala 27:72] + node _T_1632 = or(_T_1631, _T_1629) @[Mux.scala 27:72] + wire _T_1633 : UInt<3> @[Mux.scala 27:72] + _T_1633 <= _T_1632 @[Mux.scala 27:72] + node _T_1634 = eq(_T_1633, UInt<3>("h02")) @[lsu_bus_buffer.scala 344:107] + node _T_1635 = and(_T_1621, _T_1634) @[lsu_bus_buffer.scala 344:75] + node _T_1636 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_1637 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_1638 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_1639 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_1640 = mux(_T_1636, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1641 = mux(_T_1637, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1642 = mux(_T_1638, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1643 = mux(_T_1639, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1644 = or(_T_1640, _T_1641) @[Mux.scala 27:72] + node _T_1645 = or(_T_1644, _T_1642) @[Mux.scala 27:72] + node _T_1646 = or(_T_1645, _T_1643) @[Mux.scala 27:72] + wire _T_1647 : UInt<3> @[Mux.scala 27:72] + _T_1647 <= _T_1646 @[Mux.scala 27:72] + node _T_1648 = eq(_T_1647, UInt<3>("h02")) @[lsu_bus_buffer.scala 344:150] + node _T_1649 = and(_T_1635, _T_1648) @[lsu_bus_buffer.scala 344:118] + node _T_1650 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1651 = cat(_T_1650, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1652 = cat(_T_1651, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1653 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1654 = bits(_T_1652, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1655 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1656 = bits(_T_1652, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1657 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1658 = bits(_T_1652, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1659 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1660 = bits(_T_1652, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1661 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1662 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1663 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1664 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1665 = or(_T_1661, _T_1662) @[Mux.scala 27:72] + node _T_1666 = or(_T_1665, _T_1663) @[Mux.scala 27:72] + node _T_1667 = or(_T_1666, _T_1664) @[Mux.scala 27:72] + wire _T_1668 : UInt<1> @[Mux.scala 27:72] + _T_1668 <= _T_1667 @[Mux.scala 27:72] + node _T_1669 = eq(_T_1668, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:5] + node _T_1670 = and(_T_1649, _T_1669) @[lsu_bus_buffer.scala 344:161] + node _T_1671 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1672 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1673 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1674 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1675 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1676 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1677 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1678 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1679 = mux(_T_1671, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1680 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1681 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1682 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1683 = or(_T_1679, _T_1680) @[Mux.scala 27:72] + node _T_1684 = or(_T_1683, _T_1681) @[Mux.scala 27:72] + node _T_1685 = or(_T_1684, _T_1682) @[Mux.scala 27:72] + wire _T_1686 : UInt<1> @[Mux.scala 27:72] + _T_1686 <= _T_1685 @[Mux.scala 27:72] + node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:87] + node _T_1688 = and(_T_1670, _T_1687) @[lsu_bus_buffer.scala 345:85] + node _T_1689 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1690 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1691 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1692 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1693 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1694 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1695 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1696 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1697 = mux(_T_1689, _T_1690, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1698 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1699 = mux(_T_1693, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1700 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1701 = or(_T_1697, _T_1698) @[Mux.scala 27:72] + node _T_1702 = or(_T_1701, _T_1699) @[Mux.scala 27:72] + node _T_1703 = or(_T_1702, _T_1700) @[Mux.scala 27:72] + wire _T_1704 : UInt<1> @[Mux.scala 27:72] + _T_1704 <= _T_1703 @[Mux.scala 27:72] + node _T_1705 = eq(_T_1704, UInt<1>("h00")) @[lsu_bus_buffer.scala 346:6] + node _T_1706 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1707 = cat(_T_1706, buf_dual[1]) @[Cat.scala 29:58] + node _T_1708 = cat(_T_1707, buf_dual[0]) @[Cat.scala 29:58] + node _T_1709 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1710 = bits(_T_1708, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1711 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1712 = bits(_T_1708, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1713 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1714 = bits(_T_1708, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1715 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1716 = bits(_T_1708, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1717 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1718 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1719 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1720 = mux(_T_1715, _T_1716, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1721 = or(_T_1717, _T_1718) @[Mux.scala 27:72] + node _T_1722 = or(_T_1721, _T_1719) @[Mux.scala 27:72] + node _T_1723 = or(_T_1722, _T_1720) @[Mux.scala 27:72] + wire _T_1724 : UInt<1> @[Mux.scala 27:72] + _T_1724 <= _T_1723 @[Mux.scala 27:72] + node _T_1725 = and(_T_1705, _T_1724) @[lsu_bus_buffer.scala 346:36] + node _T_1726 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] + node _T_1727 = cat(_T_1726, buf_dualhi[1]) @[Cat.scala 29:58] + node _T_1728 = cat(_T_1727, buf_dualhi[0]) @[Cat.scala 29:58] + node _T_1729 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1730 = bits(_T_1728, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1731 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1732 = bits(_T_1728, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1733 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1734 = bits(_T_1728, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1735 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1736 = bits(_T_1728, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1737 = mux(_T_1729, _T_1730, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1738 = mux(_T_1731, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1739 = mux(_T_1733, _T_1734, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1740 = mux(_T_1735, _T_1736, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1741 = or(_T_1737, _T_1738) @[Mux.scala 27:72] + node _T_1742 = or(_T_1741, _T_1739) @[Mux.scala 27:72] + node _T_1743 = or(_T_1742, _T_1740) @[Mux.scala 27:72] + wire _T_1744 : UInt<1> @[Mux.scala 27:72] + _T_1744 <= _T_1743 @[Mux.scala 27:72] + node _T_1745 = eq(_T_1744, UInt<1>("h00")) @[lsu_bus_buffer.scala 346:107] + node _T_1746 = and(_T_1725, _T_1745) @[lsu_bus_buffer.scala 346:105] + node _T_1747 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1748 = cat(_T_1747, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1749 = cat(_T_1748, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1750 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_1751 = bits(_T_1749, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_1752 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_1753 = bits(_T_1749, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_1754 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_1755 = bits(_T_1749, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_1756 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_1757 = bits(_T_1749, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_1758 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1759 = mux(_T_1752, _T_1753, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1760 = mux(_T_1754, _T_1755, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1761 = mux(_T_1756, _T_1757, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = or(_T_1758, _T_1759) @[Mux.scala 27:72] + node _T_1763 = or(_T_1762, _T_1760) @[Mux.scala 27:72] + node _T_1764 = or(_T_1763, _T_1761) @[Mux.scala 27:72] + wire _T_1765 : UInt<1> @[Mux.scala 27:72] + _T_1765 <= _T_1764 @[Mux.scala 27:72] + node _T_1766 = and(_T_1746, _T_1765) @[lsu_bus_buffer.scala 346:177] + node _T_1767 = and(_T_1688, _T_1766) @[lsu_bus_buffer.scala 345:122] + node _T_1768 = and(ibuf_buf_byp, ldst_samedw_r) @[lsu_bus_buffer.scala 347:19] + node _T_1769 = and(_T_1768, io.ldst_dual_r) @[lsu_bus_buffer.scala 347:35] + node _T_1770 = or(_T_1767, _T_1769) @[lsu_bus_buffer.scala 346:250] + obuf_merge_en <= _T_1770 @[lsu_bus_buffer.scala 344:17] + reg obuf_wr_enQ : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + obuf_wr_enQ <= obuf_wr_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1771 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 349:58] + node _T_1772 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 349:93] + node _T_1773 = and(_T_1771, _T_1772) @[lsu_bus_buffer.scala 349:91] + reg _T_1774 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 349:54] + _T_1774 <= _T_1773 @[lsu_bus_buffer.scala 349:54] + obuf_valid <= _T_1774 @[lsu_bus_buffer.scala 349:14] + reg _T_1775 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1775 <= obuf_nosend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_nosend <= _T_1775 @[lsu_bus_buffer.scala 350:15] + reg _T_1776 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_rdrsp_pend_en : @[Reg.scala 28:19] + _T_1776 <= obuf_rdrsp_pend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_rdrsp_pend <= _T_1776 @[lsu_bus_buffer.scala 351:19] + reg _T_1777 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1777 <= obuf_cmd_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_cmd_done <= _T_1777 @[lsu_bus_buffer.scala 352:17] + reg _T_1778 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1778 <= obuf_data_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_data_done <= _T_1778 @[lsu_bus_buffer.scala 353:18] + reg _T_1779 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.lsu_busm_clken : @[Reg.scala 28:19] + _T_1779 <= obuf_rdrsp_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_rdrsp_tag <= _T_1779 @[lsu_bus_buffer.scala 354:18] + node _T_1780 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1780 : @[Reg.scala 28:19] + _T_1781 <= obuf_tag0_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_tag0 <= _T_1781 @[lsu_bus_buffer.scala 356:13] + node _T_1782 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_tag1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1782 : @[Reg.scala 28:19] + obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1783 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_merge : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1783 : @[Reg.scala 28:19] + obuf_merge <= obuf_merge_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1784 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1785 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1784 : @[Reg.scala 28:19] + _T_1785 <= obuf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_write <= _T_1785 @[lsu_bus_buffer.scala 359:14] + node _T_1786 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg _T_1787 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1786 : @[Reg.scala 28:19] + _T_1787 <= obuf_sideeffect_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_sideeffect <= _T_1787 @[lsu_bus_buffer.scala 360:19] + node _T_1788 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_sz : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1788 : @[Reg.scala 28:19] + obuf_sz <= obuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1789 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 388:57] + reg obuf_byteen : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1789 : @[Reg.scala 28:19] + obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1790 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1790 <= obuf_addr_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_addr <= _T_1790 @[lsu_bus_buffer.scala 363:13] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg obuf_data : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_data <= obuf_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1791 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1791 <= obuf_data_done_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_wr_timer <= _T_1791 @[lsu_bus_buffer.scala 365:17] + wire WrPtr0_m : UInt<2> + WrPtr0_m <= UInt<1>("h00") + node _T_1792 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1793 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:30] + node _T_1794 = and(ibuf_valid, _T_1793) @[lsu_bus_buffer.scala 370:19] + node _T_1795 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:18] + node _T_1796 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:57] + node _T_1797 = and(io.ldst_dual_r, _T_1796) @[lsu_bus_buffer.scala 371:45] + node _T_1798 = or(_T_1795, _T_1797) @[lsu_bus_buffer.scala 371:27] + node _T_1799 = and(io.lsu_busreq_r, _T_1798) @[lsu_bus_buffer.scala 370:58] + node _T_1800 = or(_T_1794, _T_1799) @[lsu_bus_buffer.scala 370:39] + node _T_1801 = eq(_T_1800, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1802 = and(_T_1792, _T_1801) @[lsu_bus_buffer.scala 369:76] + node _T_1803 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1804 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 370:30] + node _T_1805 = and(ibuf_valid, _T_1804) @[lsu_bus_buffer.scala 370:19] + node _T_1806 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:18] + node _T_1807 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:57] + node _T_1808 = and(io.ldst_dual_r, _T_1807) @[lsu_bus_buffer.scala 371:45] + node _T_1809 = or(_T_1806, _T_1808) @[lsu_bus_buffer.scala 371:27] + node _T_1810 = and(io.lsu_busreq_r, _T_1809) @[lsu_bus_buffer.scala 370:58] + node _T_1811 = or(_T_1805, _T_1810) @[lsu_bus_buffer.scala 370:39] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1813 = and(_T_1803, _T_1812) @[lsu_bus_buffer.scala 369:76] + node _T_1814 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1815 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 370:30] + node _T_1816 = and(ibuf_valid, _T_1815) @[lsu_bus_buffer.scala 370:19] + node _T_1817 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:18] + node _T_1818 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:57] + node _T_1819 = and(io.ldst_dual_r, _T_1818) @[lsu_bus_buffer.scala 371:45] + node _T_1820 = or(_T_1817, _T_1819) @[lsu_bus_buffer.scala 371:27] + node _T_1821 = and(io.lsu_busreq_r, _T_1820) @[lsu_bus_buffer.scala 370:58] + node _T_1822 = or(_T_1816, _T_1821) @[lsu_bus_buffer.scala 370:39] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1824 = and(_T_1814, _T_1823) @[lsu_bus_buffer.scala 369:76] + node _T_1825 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1826 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 370:30] + node _T_1827 = and(ibuf_valid, _T_1826) @[lsu_bus_buffer.scala 370:19] + node _T_1828 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:18] + node _T_1829 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:57] + node _T_1830 = and(io.ldst_dual_r, _T_1829) @[lsu_bus_buffer.scala 371:45] + node _T_1831 = or(_T_1828, _T_1830) @[lsu_bus_buffer.scala 371:27] + node _T_1832 = and(io.lsu_busreq_r, _T_1831) @[lsu_bus_buffer.scala 370:58] + node _T_1833 = or(_T_1827, _T_1832) @[lsu_bus_buffer.scala 370:39] + node _T_1834 = eq(_T_1833, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:5] + node _T_1835 = and(_T_1825, _T_1834) @[lsu_bus_buffer.scala 369:76] + node _T_1836 = mux(_T_1835, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1837 = mux(_T_1824, UInt<2>("h02"), _T_1836) @[Mux.scala 98:16] + node _T_1838 = mux(_T_1813, UInt<1>("h01"), _T_1837) @[Mux.scala 98:16] + node _T_1839 = mux(_T_1802, UInt<1>("h00"), _T_1838) @[Mux.scala 98:16] + WrPtr0_m <= _T_1839 @[lsu_bus_buffer.scala 369:12] + wire WrPtr1_m : UInt<2> + WrPtr1_m <= UInt<1>("h00") + node _T_1840 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1841 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:103] + node _T_1842 = and(ibuf_valid, _T_1841) @[lsu_bus_buffer.scala 375:92] + node _T_1843 = eq(WrPtr0_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 376:33] + node _T_1844 = and(io.lsu_busreq_m, _T_1843) @[lsu_bus_buffer.scala 376:22] + node _T_1845 = or(_T_1842, _T_1844) @[lsu_bus_buffer.scala 375:112] + node _T_1846 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:36] + node _T_1847 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:34] + node _T_1848 = and(io.ldst_dual_r, _T_1847) @[lsu_bus_buffer.scala 378:23] + node _T_1849 = or(_T_1846, _T_1848) @[lsu_bus_buffer.scala 377:46] + node _T_1850 = and(io.lsu_busreq_r, _T_1849) @[lsu_bus_buffer.scala 377:22] + node _T_1851 = or(_T_1845, _T_1850) @[lsu_bus_buffer.scala 376:42] + node _T_1852 = eq(_T_1851, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1853 = and(_T_1840, _T_1852) @[lsu_bus_buffer.scala 375:76] + node _T_1854 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1855 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 375:103] + node _T_1856 = and(ibuf_valid, _T_1855) @[lsu_bus_buffer.scala 375:92] + node _T_1857 = eq(WrPtr0_m, UInt<1>("h01")) @[lsu_bus_buffer.scala 376:33] + node _T_1858 = and(io.lsu_busreq_m, _T_1857) @[lsu_bus_buffer.scala 376:22] + node _T_1859 = or(_T_1856, _T_1858) @[lsu_bus_buffer.scala 375:112] + node _T_1860 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 377:36] + node _T_1861 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 378:34] + node _T_1862 = and(io.ldst_dual_r, _T_1861) @[lsu_bus_buffer.scala 378:23] + node _T_1863 = or(_T_1860, _T_1862) @[lsu_bus_buffer.scala 377:46] + node _T_1864 = and(io.lsu_busreq_r, _T_1863) @[lsu_bus_buffer.scala 377:22] + node _T_1865 = or(_T_1859, _T_1864) @[lsu_bus_buffer.scala 376:42] + node _T_1866 = eq(_T_1865, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1867 = and(_T_1854, _T_1866) @[lsu_bus_buffer.scala 375:76] + node _T_1868 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1869 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 375:103] + node _T_1870 = and(ibuf_valid, _T_1869) @[lsu_bus_buffer.scala 375:92] + node _T_1871 = eq(WrPtr0_m, UInt<2>("h02")) @[lsu_bus_buffer.scala 376:33] + node _T_1872 = and(io.lsu_busreq_m, _T_1871) @[lsu_bus_buffer.scala 376:22] + node _T_1873 = or(_T_1870, _T_1872) @[lsu_bus_buffer.scala 375:112] + node _T_1874 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 377:36] + node _T_1875 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 378:34] + node _T_1876 = and(io.ldst_dual_r, _T_1875) @[lsu_bus_buffer.scala 378:23] + node _T_1877 = or(_T_1874, _T_1876) @[lsu_bus_buffer.scala 377:46] + node _T_1878 = and(io.lsu_busreq_r, _T_1877) @[lsu_bus_buffer.scala 377:22] + node _T_1879 = or(_T_1873, _T_1878) @[lsu_bus_buffer.scala 376:42] + node _T_1880 = eq(_T_1879, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1881 = and(_T_1868, _T_1880) @[lsu_bus_buffer.scala 375:76] + node _T_1882 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 375:65] + node _T_1883 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 375:103] + node _T_1884 = and(ibuf_valid, _T_1883) @[lsu_bus_buffer.scala 375:92] + node _T_1885 = eq(WrPtr0_m, UInt<2>("h03")) @[lsu_bus_buffer.scala 376:33] + node _T_1886 = and(io.lsu_busreq_m, _T_1885) @[lsu_bus_buffer.scala 376:22] + node _T_1887 = or(_T_1884, _T_1886) @[lsu_bus_buffer.scala 375:112] + node _T_1888 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 377:36] + node _T_1889 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 378:34] + node _T_1890 = and(io.ldst_dual_r, _T_1889) @[lsu_bus_buffer.scala 378:23] + node _T_1891 = or(_T_1888, _T_1890) @[lsu_bus_buffer.scala 377:46] + node _T_1892 = and(io.lsu_busreq_r, _T_1891) @[lsu_bus_buffer.scala 377:22] + node _T_1893 = or(_T_1887, _T_1892) @[lsu_bus_buffer.scala 376:42] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:78] + node _T_1895 = and(_T_1882, _T_1894) @[lsu_bus_buffer.scala 375:76] + node _T_1896 = mux(_T_1895, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1897 = mux(_T_1881, UInt<2>("h02"), _T_1896) @[Mux.scala 98:16] + node _T_1898 = mux(_T_1867, UInt<1>("h01"), _T_1897) @[Mux.scala 98:16] + node _T_1899 = mux(_T_1853, UInt<1>("h00"), _T_1898) @[Mux.scala 98:16] + WrPtr1_m <= _T_1899 @[lsu_bus_buffer.scala 375:12] + wire buf_age : UInt<4>[4] @[lsu_bus_buffer.scala 380:21] + buf_age[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + buf_age[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:11] + node _T_1900 = orr(buf_age[0]) @[lsu_bus_buffer.scala 383:58] + node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1902 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1903 = and(_T_1901, _T_1902) @[lsu_bus_buffer.scala 383:63] + node _T_1904 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1905 = and(_T_1903, _T_1904) @[lsu_bus_buffer.scala 383:88] + node _T_1906 = orr(buf_age[1]) @[lsu_bus_buffer.scala 383:58] + node _T_1907 = eq(_T_1906, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1908 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1909 = and(_T_1907, _T_1908) @[lsu_bus_buffer.scala 383:63] + node _T_1910 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1911 = and(_T_1909, _T_1910) @[lsu_bus_buffer.scala 383:88] + node _T_1912 = orr(buf_age[2]) @[lsu_bus_buffer.scala 383:58] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1914 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1915 = and(_T_1913, _T_1914) @[lsu_bus_buffer.scala 383:63] + node _T_1916 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1917 = and(_T_1915, _T_1916) @[lsu_bus_buffer.scala 383:88] + node _T_1918 = orr(buf_age[3]) @[lsu_bus_buffer.scala 383:58] + node _T_1919 = eq(_T_1918, UInt<1>("h00")) @[lsu_bus_buffer.scala 383:45] + node _T_1920 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 383:78] + node _T_1921 = and(_T_1919, _T_1920) @[lsu_bus_buffer.scala 383:63] + node _T_1922 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 383:90] + node _T_1923 = and(_T_1921, _T_1922) @[lsu_bus_buffer.scala 383:88] + node _T_1924 = cat(_T_1923, _T_1917) @[Cat.scala 29:58] + node _T_1925 = cat(_T_1924, _T_1911) @[Cat.scala 29:58] + node CmdPtr0Dec = cat(_T_1925, _T_1905) @[Cat.scala 29:58] + node _T_1926 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1927 = and(buf_age[0], _T_1926) @[lsu_bus_buffer.scala 384:59] + node _T_1928 = orr(_T_1927) @[lsu_bus_buffer.scala 384:76] + node _T_1929 = eq(_T_1928, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1930 = bits(CmdPtr0Dec, 0, 0) @[lsu_bus_buffer.scala 384:94] + node _T_1931 = eq(_T_1930, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1932 = and(_T_1929, _T_1931) @[lsu_bus_buffer.scala 384:81] + node _T_1933 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1934 = and(_T_1932, _T_1933) @[lsu_bus_buffer.scala 384:98] + node _T_1935 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1936 = and(_T_1934, _T_1935) @[lsu_bus_buffer.scala 384:123] + node _T_1937 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1938 = and(buf_age[1], _T_1937) @[lsu_bus_buffer.scala 384:59] + node _T_1939 = orr(_T_1938) @[lsu_bus_buffer.scala 384:76] + node _T_1940 = eq(_T_1939, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1941 = bits(CmdPtr0Dec, 1, 1) @[lsu_bus_buffer.scala 384:94] + node _T_1942 = eq(_T_1941, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1943 = and(_T_1940, _T_1942) @[lsu_bus_buffer.scala 384:81] + node _T_1944 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1945 = and(_T_1943, _T_1944) @[lsu_bus_buffer.scala 384:98] + node _T_1946 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1947 = and(_T_1945, _T_1946) @[lsu_bus_buffer.scala 384:123] + node _T_1948 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1949 = and(buf_age[2], _T_1948) @[lsu_bus_buffer.scala 384:59] + node _T_1950 = orr(_T_1949) @[lsu_bus_buffer.scala 384:76] + node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1952 = bits(CmdPtr0Dec, 2, 2) @[lsu_bus_buffer.scala 384:94] + node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1954 = and(_T_1951, _T_1953) @[lsu_bus_buffer.scala 384:81] + node _T_1955 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1956 = and(_T_1954, _T_1955) @[lsu_bus_buffer.scala 384:98] + node _T_1957 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1958 = and(_T_1956, _T_1957) @[lsu_bus_buffer.scala 384:123] + node _T_1959 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 384:62] + node _T_1960 = and(buf_age[3], _T_1959) @[lsu_bus_buffer.scala 384:59] + node _T_1961 = orr(_T_1960) @[lsu_bus_buffer.scala 384:76] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:45] + node _T_1963 = bits(CmdPtr0Dec, 3, 3) @[lsu_bus_buffer.scala 384:94] + node _T_1964 = eq(_T_1963, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:83] + node _T_1965 = and(_T_1962, _T_1964) @[lsu_bus_buffer.scala 384:81] + node _T_1966 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 384:113] + node _T_1967 = and(_T_1965, _T_1966) @[lsu_bus_buffer.scala 384:98] + node _T_1968 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 384:125] + node _T_1969 = and(_T_1967, _T_1968) @[lsu_bus_buffer.scala 384:123] + node _T_1970 = cat(_T_1969, _T_1958) @[Cat.scala 29:58] + node _T_1971 = cat(_T_1970, _T_1947) @[Cat.scala 29:58] + node CmdPtr1Dec = cat(_T_1971, _T_1936) @[Cat.scala 29:58] + wire buf_rsp_pickage : UInt<4>[4] @[lsu_bus_buffer.scala 385:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 386:19] + node _T_1972 = orr(buf_rsp_pickage[0]) @[lsu_bus_buffer.scala 387:65] + node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1974 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1975 = and(_T_1973, _T_1974) @[lsu_bus_buffer.scala 387:70] + node _T_1976 = orr(buf_rsp_pickage[1]) @[lsu_bus_buffer.scala 387:65] + node _T_1977 = eq(_T_1976, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1978 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1979 = and(_T_1977, _T_1978) @[lsu_bus_buffer.scala 387:70] + node _T_1980 = orr(buf_rsp_pickage[2]) @[lsu_bus_buffer.scala 387:65] + node _T_1981 = eq(_T_1980, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1982 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1983 = and(_T_1981, _T_1982) @[lsu_bus_buffer.scala 387:70] + node _T_1984 = orr(buf_rsp_pickage[3]) @[lsu_bus_buffer.scala 387:65] + node _T_1985 = eq(_T_1984, UInt<1>("h00")) @[lsu_bus_buffer.scala 387:44] + node _T_1986 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 387:85] + node _T_1987 = and(_T_1985, _T_1986) @[lsu_bus_buffer.scala 387:70] + node _T_1988 = cat(_T_1987, _T_1983) @[Cat.scala 29:58] + node _T_1989 = cat(_T_1988, _T_1979) @[Cat.scala 29:58] + node RspPtrDec = cat(_T_1989, _T_1975) @[Cat.scala 29:58] + node _T_1990 = orr(CmdPtr0Dec) @[lsu_bus_buffer.scala 388:31] + found_cmdptr0 <= _T_1990 @[lsu_bus_buffer.scala 388:17] + node _T_1991 = orr(CmdPtr1Dec) @[lsu_bus_buffer.scala 389:31] + found_cmdptr1 <= _T_1991 @[lsu_bus_buffer.scala 389:17] + wire RspPtr : UInt<2> + RspPtr <= UInt<1>("h00") + node _T_1992 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1993 = cat(_T_1992, CmdPtr0Dec) @[Cat.scala 29:58] + node _T_1994 = bits(_T_1993, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_1995 = bits(_T_1993, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_1996 = or(_T_1994, _T_1995) @[lsu_bus_buffer.scala 391:42] + node _T_1997 = bits(_T_1993, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_1998 = or(_T_1996, _T_1997) @[lsu_bus_buffer.scala 391:48] + node _T_1999 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2000 = or(_T_1998, _T_1999) @[lsu_bus_buffer.scala 391:54] + node _T_2001 = bits(_T_1993, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2002 = bits(_T_1993, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2003 = or(_T_2001, _T_2002) @[lsu_bus_buffer.scala 391:67] + node _T_2004 = bits(_T_1993, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2005 = or(_T_2003, _T_2004) @[lsu_bus_buffer.scala 391:73] + node _T_2006 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2007 = or(_T_2005, _T_2006) @[lsu_bus_buffer.scala 391:79] + node _T_2008 = bits(_T_1993, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2009 = bits(_T_1993, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2010 = or(_T_2008, _T_2009) @[lsu_bus_buffer.scala 391:92] + node _T_2011 = bits(_T_1993, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2012 = or(_T_2010, _T_2011) @[lsu_bus_buffer.scala 391:98] + node _T_2013 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2014 = or(_T_2012, _T_2013) @[lsu_bus_buffer.scala 391:104] + node _T_2015 = cat(_T_2000, _T_2007) @[Cat.scala 29:58] + node _T_2016 = cat(_T_2015, _T_2014) @[Cat.scala 29:58] + CmdPtr0 <= _T_2016 @[lsu_bus_buffer.scala 396:11] + node _T_2017 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2018 = cat(_T_2017, CmdPtr1Dec) @[Cat.scala 29:58] + node _T_2019 = bits(_T_2018, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_2020 = bits(_T_2018, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_2021 = or(_T_2019, _T_2020) @[lsu_bus_buffer.scala 391:42] + node _T_2022 = bits(_T_2018, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_2023 = or(_T_2021, _T_2022) @[lsu_bus_buffer.scala 391:48] + node _T_2024 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2025 = or(_T_2023, _T_2024) @[lsu_bus_buffer.scala 391:54] + node _T_2026 = bits(_T_2018, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2027 = bits(_T_2018, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2028 = or(_T_2026, _T_2027) @[lsu_bus_buffer.scala 391:67] + node _T_2029 = bits(_T_2018, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2030 = or(_T_2028, _T_2029) @[lsu_bus_buffer.scala 391:73] + node _T_2031 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2032 = or(_T_2030, _T_2031) @[lsu_bus_buffer.scala 391:79] + node _T_2033 = bits(_T_2018, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2034 = bits(_T_2018, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2035 = or(_T_2033, _T_2034) @[lsu_bus_buffer.scala 391:92] + node _T_2036 = bits(_T_2018, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2037 = or(_T_2035, _T_2036) @[lsu_bus_buffer.scala 391:98] + node _T_2038 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2039 = or(_T_2037, _T_2038) @[lsu_bus_buffer.scala 391:104] + node _T_2040 = cat(_T_2025, _T_2032) @[Cat.scala 29:58] + node _T_2041 = cat(_T_2040, _T_2039) @[Cat.scala 29:58] + CmdPtr1 <= _T_2041 @[lsu_bus_buffer.scala 398:11] + node _T_2042 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2043 = cat(_T_2042, RspPtrDec) @[Cat.scala 29:58] + node _T_2044 = bits(_T_2043, 4, 4) @[lsu_bus_buffer.scala 391:39] + node _T_2045 = bits(_T_2043, 5, 5) @[lsu_bus_buffer.scala 391:45] + node _T_2046 = or(_T_2044, _T_2045) @[lsu_bus_buffer.scala 391:42] + node _T_2047 = bits(_T_2043, 6, 6) @[lsu_bus_buffer.scala 391:51] + node _T_2048 = or(_T_2046, _T_2047) @[lsu_bus_buffer.scala 391:48] + node _T_2049 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:57] + node _T_2050 = or(_T_2048, _T_2049) @[lsu_bus_buffer.scala 391:54] + node _T_2051 = bits(_T_2043, 2, 2) @[lsu_bus_buffer.scala 391:64] + node _T_2052 = bits(_T_2043, 3, 3) @[lsu_bus_buffer.scala 391:70] + node _T_2053 = or(_T_2051, _T_2052) @[lsu_bus_buffer.scala 391:67] + node _T_2054 = bits(_T_2043, 6, 6) @[lsu_bus_buffer.scala 391:76] + node _T_2055 = or(_T_2053, _T_2054) @[lsu_bus_buffer.scala 391:73] + node _T_2056 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:82] + node _T_2057 = or(_T_2055, _T_2056) @[lsu_bus_buffer.scala 391:79] + node _T_2058 = bits(_T_2043, 1, 1) @[lsu_bus_buffer.scala 391:89] + node _T_2059 = bits(_T_2043, 3, 3) @[lsu_bus_buffer.scala 391:95] + node _T_2060 = or(_T_2058, _T_2059) @[lsu_bus_buffer.scala 391:92] + node _T_2061 = bits(_T_2043, 5, 5) @[lsu_bus_buffer.scala 391:101] + node _T_2062 = or(_T_2060, _T_2061) @[lsu_bus_buffer.scala 391:98] + node _T_2063 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 391:107] + node _T_2064 = or(_T_2062, _T_2063) @[lsu_bus_buffer.scala 391:104] + node _T_2065 = cat(_T_2050, _T_2057) @[Cat.scala 29:58] + node _T_2066 = cat(_T_2065, _T_2064) @[Cat.scala 29:58] + RspPtr <= _T_2066 @[lsu_bus_buffer.scala 399:10] + wire buf_state_en : UInt<1>[4] @[lsu_bus_buffer.scala 400:26] + buf_state_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + buf_state_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:16] + wire buf_rspageQ : UInt<4>[4] @[lsu_bus_buffer.scala 402:25] + buf_rspageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + buf_rspageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:15] + wire buf_rspage_set : UInt<4>[4] @[lsu_bus_buffer.scala 404:28] + buf_rspage_set[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + buf_rspage_set[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:18] + wire buf_rspage_in : UInt<4>[4] @[lsu_bus_buffer.scala 406:27] + buf_rspage_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + buf_rspage_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:17] + wire buf_rspage : UInt<4>[4] @[lsu_bus_buffer.scala 408:24] + buf_rspage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + buf_rspage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 409:14] + node _T_2067 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2068 = and(_T_2067, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2069 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2070 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2071 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2072 = and(_T_2070, _T_2071) @[lsu_bus_buffer.scala 412:57] + node _T_2073 = or(_T_2069, _T_2072) @[lsu_bus_buffer.scala 412:31] + node _T_2074 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2075 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2076 = and(_T_2074, _T_2075) @[lsu_bus_buffer.scala 413:41] + node _T_2077 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2078 = and(_T_2076, _T_2077) @[lsu_bus_buffer.scala 413:71] + node _T_2079 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2080 = and(_T_2078, _T_2079) @[lsu_bus_buffer.scala 413:92] + node _T_2081 = or(_T_2073, _T_2080) @[lsu_bus_buffer.scala 412:86] + node _T_2082 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2083 = and(_T_2082, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2084 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2085 = and(_T_2083, _T_2084) @[lsu_bus_buffer.scala 414:52] + node _T_2086 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2087 = and(_T_2085, _T_2086) @[lsu_bus_buffer.scala 414:73] + node _T_2088 = or(_T_2081, _T_2087) @[lsu_bus_buffer.scala 413:114] + node _T_2089 = and(_T_2068, _T_2088) @[lsu_bus_buffer.scala 411:113] + node _T_2090 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2091 = or(_T_2089, _T_2090) @[lsu_bus_buffer.scala 414:97] + node _T_2092 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2093 = and(_T_2092, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2094 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2095 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2096 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2097 = and(_T_2095, _T_2096) @[lsu_bus_buffer.scala 412:57] + node _T_2098 = or(_T_2094, _T_2097) @[lsu_bus_buffer.scala 412:31] + node _T_2099 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2100 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2101 = and(_T_2099, _T_2100) @[lsu_bus_buffer.scala 413:41] + node _T_2102 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2103 = and(_T_2101, _T_2102) @[lsu_bus_buffer.scala 413:71] + node _T_2104 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2105 = and(_T_2103, _T_2104) @[lsu_bus_buffer.scala 413:92] + node _T_2106 = or(_T_2098, _T_2105) @[lsu_bus_buffer.scala 412:86] + node _T_2107 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2108 = and(_T_2107, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2109 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2110 = and(_T_2108, _T_2109) @[lsu_bus_buffer.scala 414:52] + node _T_2111 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2112 = and(_T_2110, _T_2111) @[lsu_bus_buffer.scala 414:73] + node _T_2113 = or(_T_2106, _T_2112) @[lsu_bus_buffer.scala 413:114] + node _T_2114 = and(_T_2093, _T_2113) @[lsu_bus_buffer.scala 411:113] + node _T_2115 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2116 = or(_T_2114, _T_2115) @[lsu_bus_buffer.scala 414:97] + node _T_2117 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2118 = and(_T_2117, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2119 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2120 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2121 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2122 = and(_T_2120, _T_2121) @[lsu_bus_buffer.scala 412:57] + node _T_2123 = or(_T_2119, _T_2122) @[lsu_bus_buffer.scala 412:31] + node _T_2124 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2125 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2126 = and(_T_2124, _T_2125) @[lsu_bus_buffer.scala 413:41] + node _T_2127 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2128 = and(_T_2126, _T_2127) @[lsu_bus_buffer.scala 413:71] + node _T_2129 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2130 = and(_T_2128, _T_2129) @[lsu_bus_buffer.scala 413:92] + node _T_2131 = or(_T_2123, _T_2130) @[lsu_bus_buffer.scala 412:86] + node _T_2132 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2133 = and(_T_2132, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2134 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2135 = and(_T_2133, _T_2134) @[lsu_bus_buffer.scala 414:52] + node _T_2136 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2137 = and(_T_2135, _T_2136) @[lsu_bus_buffer.scala 414:73] + node _T_2138 = or(_T_2131, _T_2137) @[lsu_bus_buffer.scala 413:114] + node _T_2139 = and(_T_2118, _T_2138) @[lsu_bus_buffer.scala 411:113] + node _T_2140 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2141 = or(_T_2139, _T_2140) @[lsu_bus_buffer.scala 414:97] + node _T_2142 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2143 = and(_T_2142, buf_state_en[0]) @[lsu_bus_buffer.scala 411:94] + node _T_2144 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2145 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2146 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2147 = and(_T_2145, _T_2146) @[lsu_bus_buffer.scala 412:57] + node _T_2148 = or(_T_2144, _T_2147) @[lsu_bus_buffer.scala 412:31] + node _T_2149 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2150 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2151 = and(_T_2149, _T_2150) @[lsu_bus_buffer.scala 413:41] + node _T_2152 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:83] + node _T_2153 = and(_T_2151, _T_2152) @[lsu_bus_buffer.scala 413:71] + node _T_2154 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2155 = and(_T_2153, _T_2154) @[lsu_bus_buffer.scala 413:92] + node _T_2156 = or(_T_2148, _T_2155) @[lsu_bus_buffer.scala 412:86] + node _T_2157 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2158 = and(_T_2157, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2159 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:64] + node _T_2160 = and(_T_2158, _T_2159) @[lsu_bus_buffer.scala 414:52] + node _T_2161 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2162 = and(_T_2160, _T_2161) @[lsu_bus_buffer.scala 414:73] + node _T_2163 = or(_T_2156, _T_2162) @[lsu_bus_buffer.scala 413:114] + node _T_2164 = and(_T_2143, _T_2163) @[lsu_bus_buffer.scala 411:113] + node _T_2165 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2166 = or(_T_2164, _T_2165) @[lsu_bus_buffer.scala 414:97] + node _T_2167 = cat(_T_2166, _T_2141) @[Cat.scala 29:58] + node _T_2168 = cat(_T_2167, _T_2116) @[Cat.scala 29:58] + node buf_age_in_0 = cat(_T_2168, _T_2091) @[Cat.scala 29:58] + node _T_2169 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2170 = and(_T_2169, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2171 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2172 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2173 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2174 = and(_T_2172, _T_2173) @[lsu_bus_buffer.scala 412:57] + node _T_2175 = or(_T_2171, _T_2174) @[lsu_bus_buffer.scala 412:31] + node _T_2176 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2177 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2178 = and(_T_2176, _T_2177) @[lsu_bus_buffer.scala 413:41] + node _T_2179 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2180 = and(_T_2178, _T_2179) @[lsu_bus_buffer.scala 413:71] + node _T_2181 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2182 = and(_T_2180, _T_2181) @[lsu_bus_buffer.scala 413:92] + node _T_2183 = or(_T_2175, _T_2182) @[lsu_bus_buffer.scala 412:86] + node _T_2184 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2185 = and(_T_2184, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2186 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2187 = and(_T_2185, _T_2186) @[lsu_bus_buffer.scala 414:52] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2189 = and(_T_2187, _T_2188) @[lsu_bus_buffer.scala 414:73] + node _T_2190 = or(_T_2183, _T_2189) @[lsu_bus_buffer.scala 413:114] + node _T_2191 = and(_T_2170, _T_2190) @[lsu_bus_buffer.scala 411:113] + node _T_2192 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2193 = or(_T_2191, _T_2192) @[lsu_bus_buffer.scala 414:97] + node _T_2194 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2195 = and(_T_2194, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2196 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2197 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2198 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2199 = and(_T_2197, _T_2198) @[lsu_bus_buffer.scala 412:57] + node _T_2200 = or(_T_2196, _T_2199) @[lsu_bus_buffer.scala 412:31] + node _T_2201 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2202 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2203 = and(_T_2201, _T_2202) @[lsu_bus_buffer.scala 413:41] + node _T_2204 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2205 = and(_T_2203, _T_2204) @[lsu_bus_buffer.scala 413:71] + node _T_2206 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2207 = and(_T_2205, _T_2206) @[lsu_bus_buffer.scala 413:92] + node _T_2208 = or(_T_2200, _T_2207) @[lsu_bus_buffer.scala 412:86] + node _T_2209 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2210 = and(_T_2209, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2211 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2212 = and(_T_2210, _T_2211) @[lsu_bus_buffer.scala 414:52] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2214 = and(_T_2212, _T_2213) @[lsu_bus_buffer.scala 414:73] + node _T_2215 = or(_T_2208, _T_2214) @[lsu_bus_buffer.scala 413:114] + node _T_2216 = and(_T_2195, _T_2215) @[lsu_bus_buffer.scala 411:113] + node _T_2217 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2218 = or(_T_2216, _T_2217) @[lsu_bus_buffer.scala 414:97] + node _T_2219 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2220 = and(_T_2219, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2221 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2222 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2223 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2224 = and(_T_2222, _T_2223) @[lsu_bus_buffer.scala 412:57] + node _T_2225 = or(_T_2221, _T_2224) @[lsu_bus_buffer.scala 412:31] + node _T_2226 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2227 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2228 = and(_T_2226, _T_2227) @[lsu_bus_buffer.scala 413:41] + node _T_2229 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2230 = and(_T_2228, _T_2229) @[lsu_bus_buffer.scala 413:71] + node _T_2231 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2232 = and(_T_2230, _T_2231) @[lsu_bus_buffer.scala 413:92] + node _T_2233 = or(_T_2225, _T_2232) @[lsu_bus_buffer.scala 412:86] + node _T_2234 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2235 = and(_T_2234, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2236 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2237 = and(_T_2235, _T_2236) @[lsu_bus_buffer.scala 414:52] + node _T_2238 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2239 = and(_T_2237, _T_2238) @[lsu_bus_buffer.scala 414:73] + node _T_2240 = or(_T_2233, _T_2239) @[lsu_bus_buffer.scala 413:114] + node _T_2241 = and(_T_2220, _T_2240) @[lsu_bus_buffer.scala 411:113] + node _T_2242 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2243 = or(_T_2241, _T_2242) @[lsu_bus_buffer.scala 414:97] + node _T_2244 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2245 = and(_T_2244, buf_state_en[1]) @[lsu_bus_buffer.scala 411:94] + node _T_2246 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2247 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2248 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2249 = and(_T_2247, _T_2248) @[lsu_bus_buffer.scala 412:57] + node _T_2250 = or(_T_2246, _T_2249) @[lsu_bus_buffer.scala 412:31] + node _T_2251 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2252 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2253 = and(_T_2251, _T_2252) @[lsu_bus_buffer.scala 413:41] + node _T_2254 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:83] + node _T_2255 = and(_T_2253, _T_2254) @[lsu_bus_buffer.scala 413:71] + node _T_2256 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2257 = and(_T_2255, _T_2256) @[lsu_bus_buffer.scala 413:92] + node _T_2258 = or(_T_2250, _T_2257) @[lsu_bus_buffer.scala 412:86] + node _T_2259 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2260 = and(_T_2259, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2261 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:64] + node _T_2262 = and(_T_2260, _T_2261) @[lsu_bus_buffer.scala 414:52] + node _T_2263 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2264 = and(_T_2262, _T_2263) @[lsu_bus_buffer.scala 414:73] + node _T_2265 = or(_T_2258, _T_2264) @[lsu_bus_buffer.scala 413:114] + node _T_2266 = and(_T_2245, _T_2265) @[lsu_bus_buffer.scala 411:113] + node _T_2267 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2268 = or(_T_2266, _T_2267) @[lsu_bus_buffer.scala 414:97] + node _T_2269 = cat(_T_2268, _T_2243) @[Cat.scala 29:58] + node _T_2270 = cat(_T_2269, _T_2218) @[Cat.scala 29:58] + node buf_age_in_1 = cat(_T_2270, _T_2193) @[Cat.scala 29:58] + node _T_2271 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2272 = and(_T_2271, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2273 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2274 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2275 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2276 = and(_T_2274, _T_2275) @[lsu_bus_buffer.scala 412:57] + node _T_2277 = or(_T_2273, _T_2276) @[lsu_bus_buffer.scala 412:31] + node _T_2278 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2279 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2280 = and(_T_2278, _T_2279) @[lsu_bus_buffer.scala 413:41] + node _T_2281 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2282 = and(_T_2280, _T_2281) @[lsu_bus_buffer.scala 413:71] + node _T_2283 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2284 = and(_T_2282, _T_2283) @[lsu_bus_buffer.scala 413:92] + node _T_2285 = or(_T_2277, _T_2284) @[lsu_bus_buffer.scala 412:86] + node _T_2286 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2287 = and(_T_2286, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2288 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2289 = and(_T_2287, _T_2288) @[lsu_bus_buffer.scala 414:52] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2291 = and(_T_2289, _T_2290) @[lsu_bus_buffer.scala 414:73] + node _T_2292 = or(_T_2285, _T_2291) @[lsu_bus_buffer.scala 413:114] + node _T_2293 = and(_T_2272, _T_2292) @[lsu_bus_buffer.scala 411:113] + node _T_2294 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2295 = or(_T_2293, _T_2294) @[lsu_bus_buffer.scala 414:97] + node _T_2296 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2297 = and(_T_2296, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2298 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2299 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2300 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2301 = and(_T_2299, _T_2300) @[lsu_bus_buffer.scala 412:57] + node _T_2302 = or(_T_2298, _T_2301) @[lsu_bus_buffer.scala 412:31] + node _T_2303 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2304 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2305 = and(_T_2303, _T_2304) @[lsu_bus_buffer.scala 413:41] + node _T_2306 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2307 = and(_T_2305, _T_2306) @[lsu_bus_buffer.scala 413:71] + node _T_2308 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2309 = and(_T_2307, _T_2308) @[lsu_bus_buffer.scala 413:92] + node _T_2310 = or(_T_2302, _T_2309) @[lsu_bus_buffer.scala 412:86] + node _T_2311 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2312 = and(_T_2311, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2313 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2314 = and(_T_2312, _T_2313) @[lsu_bus_buffer.scala 414:52] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2316 = and(_T_2314, _T_2315) @[lsu_bus_buffer.scala 414:73] + node _T_2317 = or(_T_2310, _T_2316) @[lsu_bus_buffer.scala 413:114] + node _T_2318 = and(_T_2297, _T_2317) @[lsu_bus_buffer.scala 411:113] + node _T_2319 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2320 = or(_T_2318, _T_2319) @[lsu_bus_buffer.scala 414:97] + node _T_2321 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2322 = and(_T_2321, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2323 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2324 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2325 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2326 = and(_T_2324, _T_2325) @[lsu_bus_buffer.scala 412:57] + node _T_2327 = or(_T_2323, _T_2326) @[lsu_bus_buffer.scala 412:31] + node _T_2328 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2329 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2330 = and(_T_2328, _T_2329) @[lsu_bus_buffer.scala 413:41] + node _T_2331 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2332 = and(_T_2330, _T_2331) @[lsu_bus_buffer.scala 413:71] + node _T_2333 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2334 = and(_T_2332, _T_2333) @[lsu_bus_buffer.scala 413:92] + node _T_2335 = or(_T_2327, _T_2334) @[lsu_bus_buffer.scala 412:86] + node _T_2336 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2337 = and(_T_2336, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2338 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2339 = and(_T_2337, _T_2338) @[lsu_bus_buffer.scala 414:52] + node _T_2340 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2341 = and(_T_2339, _T_2340) @[lsu_bus_buffer.scala 414:73] + node _T_2342 = or(_T_2335, _T_2341) @[lsu_bus_buffer.scala 413:114] + node _T_2343 = and(_T_2322, _T_2342) @[lsu_bus_buffer.scala 411:113] + node _T_2344 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2345 = or(_T_2343, _T_2344) @[lsu_bus_buffer.scala 414:97] + node _T_2346 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2347 = and(_T_2346, buf_state_en[2]) @[lsu_bus_buffer.scala 411:94] + node _T_2348 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2349 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2350 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2351 = and(_T_2349, _T_2350) @[lsu_bus_buffer.scala 412:57] + node _T_2352 = or(_T_2348, _T_2351) @[lsu_bus_buffer.scala 412:31] + node _T_2353 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2354 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2355 = and(_T_2353, _T_2354) @[lsu_bus_buffer.scala 413:41] + node _T_2356 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:83] + node _T_2357 = and(_T_2355, _T_2356) @[lsu_bus_buffer.scala 413:71] + node _T_2358 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2359 = and(_T_2357, _T_2358) @[lsu_bus_buffer.scala 413:92] + node _T_2360 = or(_T_2352, _T_2359) @[lsu_bus_buffer.scala 412:86] + node _T_2361 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2362 = and(_T_2361, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2363 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:64] + node _T_2364 = and(_T_2362, _T_2363) @[lsu_bus_buffer.scala 414:52] + node _T_2365 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2366 = and(_T_2364, _T_2365) @[lsu_bus_buffer.scala 414:73] + node _T_2367 = or(_T_2360, _T_2366) @[lsu_bus_buffer.scala 413:114] + node _T_2368 = and(_T_2347, _T_2367) @[lsu_bus_buffer.scala 411:113] + node _T_2369 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2370 = or(_T_2368, _T_2369) @[lsu_bus_buffer.scala 414:97] + node _T_2371 = cat(_T_2370, _T_2345) @[Cat.scala 29:58] + node _T_2372 = cat(_T_2371, _T_2320) @[Cat.scala 29:58] + node buf_age_in_2 = cat(_T_2372, _T_2295) @[Cat.scala 29:58] + node _T_2373 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2374 = and(_T_2373, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2375 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2376 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2377 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2378 = and(_T_2376, _T_2377) @[lsu_bus_buffer.scala 412:57] + node _T_2379 = or(_T_2375, _T_2378) @[lsu_bus_buffer.scala 412:31] + node _T_2380 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2381 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2382 = and(_T_2380, _T_2381) @[lsu_bus_buffer.scala 413:41] + node _T_2383 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2384 = and(_T_2382, _T_2383) @[lsu_bus_buffer.scala 413:71] + node _T_2385 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:104] + node _T_2386 = and(_T_2384, _T_2385) @[lsu_bus_buffer.scala 413:92] + node _T_2387 = or(_T_2379, _T_2386) @[lsu_bus_buffer.scala 412:86] + node _T_2388 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2389 = and(_T_2388, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2390 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2391 = and(_T_2389, _T_2390) @[lsu_bus_buffer.scala 414:52] + node _T_2392 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:85] + node _T_2393 = and(_T_2391, _T_2392) @[lsu_bus_buffer.scala 414:73] + node _T_2394 = or(_T_2387, _T_2393) @[lsu_bus_buffer.scala 413:114] + node _T_2395 = and(_T_2374, _T_2394) @[lsu_bus_buffer.scala 411:113] + node _T_2396 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 414:109] + node _T_2397 = or(_T_2395, _T_2396) @[lsu_bus_buffer.scala 414:97] + node _T_2398 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2399 = and(_T_2398, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2400 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2401 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2402 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2403 = and(_T_2401, _T_2402) @[lsu_bus_buffer.scala 412:57] + node _T_2404 = or(_T_2400, _T_2403) @[lsu_bus_buffer.scala 412:31] + node _T_2405 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2406 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2407 = and(_T_2405, _T_2406) @[lsu_bus_buffer.scala 413:41] + node _T_2408 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2409 = and(_T_2407, _T_2408) @[lsu_bus_buffer.scala 413:71] + node _T_2410 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 413:104] + node _T_2411 = and(_T_2409, _T_2410) @[lsu_bus_buffer.scala 413:92] + node _T_2412 = or(_T_2404, _T_2411) @[lsu_bus_buffer.scala 412:86] + node _T_2413 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2414 = and(_T_2413, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2415 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2416 = and(_T_2414, _T_2415) @[lsu_bus_buffer.scala 414:52] + node _T_2417 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 414:85] + node _T_2418 = and(_T_2416, _T_2417) @[lsu_bus_buffer.scala 414:73] + node _T_2419 = or(_T_2412, _T_2418) @[lsu_bus_buffer.scala 413:114] + node _T_2420 = and(_T_2399, _T_2419) @[lsu_bus_buffer.scala 411:113] + node _T_2421 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 414:109] + node _T_2422 = or(_T_2420, _T_2421) @[lsu_bus_buffer.scala 414:97] + node _T_2423 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2424 = and(_T_2423, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2425 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2426 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2427 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2428 = and(_T_2426, _T_2427) @[lsu_bus_buffer.scala 412:57] + node _T_2429 = or(_T_2425, _T_2428) @[lsu_bus_buffer.scala 412:31] + node _T_2430 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2431 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2432 = and(_T_2430, _T_2431) @[lsu_bus_buffer.scala 413:41] + node _T_2433 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2434 = and(_T_2432, _T_2433) @[lsu_bus_buffer.scala 413:71] + node _T_2435 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 413:104] + node _T_2436 = and(_T_2434, _T_2435) @[lsu_bus_buffer.scala 413:92] + node _T_2437 = or(_T_2429, _T_2436) @[lsu_bus_buffer.scala 412:86] + node _T_2438 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2439 = and(_T_2438, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2440 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2441 = and(_T_2439, _T_2440) @[lsu_bus_buffer.scala 414:52] + node _T_2442 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 414:85] + node _T_2443 = and(_T_2441, _T_2442) @[lsu_bus_buffer.scala 414:73] + node _T_2444 = or(_T_2437, _T_2443) @[lsu_bus_buffer.scala 413:114] + node _T_2445 = and(_T_2424, _T_2444) @[lsu_bus_buffer.scala 411:113] + node _T_2446 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 414:109] + node _T_2447 = or(_T_2445, _T_2446) @[lsu_bus_buffer.scala 414:97] + node _T_2448 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 411:83] + node _T_2449 = and(_T_2448, buf_state_en[3]) @[lsu_bus_buffer.scala 411:94] + node _T_2450 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 412:20] + node _T_2451 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:47] + node _T_2452 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 412:59] + node _T_2453 = and(_T_2451, _T_2452) @[lsu_bus_buffer.scala 412:57] + node _T_2454 = or(_T_2450, _T_2453) @[lsu_bus_buffer.scala 412:31] + node _T_2455 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 413:23] + node _T_2456 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 413:53] + node _T_2457 = and(_T_2455, _T_2456) @[lsu_bus_buffer.scala 413:41] + node _T_2458 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:83] + node _T_2459 = and(_T_2457, _T_2458) @[lsu_bus_buffer.scala 413:71] + node _T_2460 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 413:104] + node _T_2461 = and(_T_2459, _T_2460) @[lsu_bus_buffer.scala 413:92] + node _T_2462 = or(_T_2454, _T_2461) @[lsu_bus_buffer.scala 412:86] + node _T_2463 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 414:17] + node _T_2464 = and(_T_2463, io.ldst_dual_r) @[lsu_bus_buffer.scala 414:35] + node _T_2465 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:64] + node _T_2466 = and(_T_2464, _T_2465) @[lsu_bus_buffer.scala 414:52] + node _T_2467 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 414:85] + node _T_2468 = and(_T_2466, _T_2467) @[lsu_bus_buffer.scala 414:73] + node _T_2469 = or(_T_2462, _T_2468) @[lsu_bus_buffer.scala 413:114] + node _T_2470 = and(_T_2449, _T_2469) @[lsu_bus_buffer.scala 411:113] + node _T_2471 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 414:109] + node _T_2472 = or(_T_2470, _T_2471) @[lsu_bus_buffer.scala 414:97] + node _T_2473 = cat(_T_2472, _T_2447) @[Cat.scala 29:58] + node _T_2474 = cat(_T_2473, _T_2422) @[Cat.scala 29:58] + node buf_age_in_3 = cat(_T_2474, _T_2397) @[Cat.scala 29:58] + wire buf_ageQ : UInt<4>[4] @[lsu_bus_buffer.scala 415:22] + buf_ageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + buf_ageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 416:12] + node _T_2475 = bits(buf_ageQ[0], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2476 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2477 = and(_T_2476, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2478 = eq(_T_2477, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2479 = and(_T_2475, _T_2478) @[lsu_bus_buffer.scala 417:76] + node _T_2480 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2481 = and(_T_2479, _T_2480) @[lsu_bus_buffer.scala 417:130] + node _T_2482 = bits(buf_ageQ[0], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2483 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2484 = and(_T_2483, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2485 = eq(_T_2484, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2486 = and(_T_2482, _T_2485) @[lsu_bus_buffer.scala 417:76] + node _T_2487 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2488 = and(_T_2486, _T_2487) @[lsu_bus_buffer.scala 417:130] + node _T_2489 = bits(buf_ageQ[0], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2490 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2491 = and(_T_2490, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2492 = eq(_T_2491, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2493 = and(_T_2489, _T_2492) @[lsu_bus_buffer.scala 417:76] + node _T_2494 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2495 = and(_T_2493, _T_2494) @[lsu_bus_buffer.scala 417:130] + node _T_2496 = bits(buf_ageQ[0], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2497 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2498 = and(_T_2497, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2499 = eq(_T_2498, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2500 = and(_T_2496, _T_2499) @[lsu_bus_buffer.scala 417:76] + node _T_2501 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2502 = and(_T_2500, _T_2501) @[lsu_bus_buffer.scala 417:130] + node _T_2503 = cat(_T_2502, _T_2495) @[Cat.scala 29:58] + node _T_2504 = cat(_T_2503, _T_2488) @[Cat.scala 29:58] + node _T_2505 = cat(_T_2504, _T_2481) @[Cat.scala 29:58] + node _T_2506 = bits(buf_ageQ[1], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2507 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2508 = and(_T_2507, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2509 = eq(_T_2508, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2510 = and(_T_2506, _T_2509) @[lsu_bus_buffer.scala 417:76] + node _T_2511 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2512 = and(_T_2510, _T_2511) @[lsu_bus_buffer.scala 417:130] + node _T_2513 = bits(buf_ageQ[1], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2514 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2515 = and(_T_2514, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2516 = eq(_T_2515, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2517 = and(_T_2513, _T_2516) @[lsu_bus_buffer.scala 417:76] + node _T_2518 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2519 = and(_T_2517, _T_2518) @[lsu_bus_buffer.scala 417:130] + node _T_2520 = bits(buf_ageQ[1], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2521 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2522 = and(_T_2521, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2523 = eq(_T_2522, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2524 = and(_T_2520, _T_2523) @[lsu_bus_buffer.scala 417:76] + node _T_2525 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2526 = and(_T_2524, _T_2525) @[lsu_bus_buffer.scala 417:130] + node _T_2527 = bits(buf_ageQ[1], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2528 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2529 = and(_T_2528, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2530 = eq(_T_2529, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2531 = and(_T_2527, _T_2530) @[lsu_bus_buffer.scala 417:76] + node _T_2532 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2533 = and(_T_2531, _T_2532) @[lsu_bus_buffer.scala 417:130] + node _T_2534 = cat(_T_2533, _T_2526) @[Cat.scala 29:58] + node _T_2535 = cat(_T_2534, _T_2519) @[Cat.scala 29:58] + node _T_2536 = cat(_T_2535, _T_2512) @[Cat.scala 29:58] + node _T_2537 = bits(buf_ageQ[2], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2538 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2539 = and(_T_2538, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2540 = eq(_T_2539, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2541 = and(_T_2537, _T_2540) @[lsu_bus_buffer.scala 417:76] + node _T_2542 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2543 = and(_T_2541, _T_2542) @[lsu_bus_buffer.scala 417:130] + node _T_2544 = bits(buf_ageQ[2], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2545 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2546 = and(_T_2545, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2547 = eq(_T_2546, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2548 = and(_T_2544, _T_2547) @[lsu_bus_buffer.scala 417:76] + node _T_2549 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2550 = and(_T_2548, _T_2549) @[lsu_bus_buffer.scala 417:130] + node _T_2551 = bits(buf_ageQ[2], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2552 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2555 = and(_T_2551, _T_2554) @[lsu_bus_buffer.scala 417:76] + node _T_2556 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2557 = and(_T_2555, _T_2556) @[lsu_bus_buffer.scala 417:130] + node _T_2558 = bits(buf_ageQ[2], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2559 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2560 = and(_T_2559, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2561 = eq(_T_2560, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2562 = and(_T_2558, _T_2561) @[lsu_bus_buffer.scala 417:76] + node _T_2563 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2564 = and(_T_2562, _T_2563) @[lsu_bus_buffer.scala 417:130] + node _T_2565 = cat(_T_2564, _T_2557) @[Cat.scala 29:58] + node _T_2566 = cat(_T_2565, _T_2550) @[Cat.scala 29:58] + node _T_2567 = cat(_T_2566, _T_2543) @[Cat.scala 29:58] + node _T_2568 = bits(buf_ageQ[3], 0, 0) @[lsu_bus_buffer.scala 417:72] + node _T_2569 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2570 = and(_T_2569, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 417:103] + node _T_2571 = eq(_T_2570, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2572 = and(_T_2568, _T_2571) @[lsu_bus_buffer.scala 417:76] + node _T_2573 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2574 = and(_T_2572, _T_2573) @[lsu_bus_buffer.scala 417:130] + node _T_2575 = bits(buf_ageQ[3], 1, 1) @[lsu_bus_buffer.scala 417:72] + node _T_2576 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2577 = and(_T_2576, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 417:103] + node _T_2578 = eq(_T_2577, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2579 = and(_T_2575, _T_2578) @[lsu_bus_buffer.scala 417:76] + node _T_2580 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2581 = and(_T_2579, _T_2580) @[lsu_bus_buffer.scala 417:130] + node _T_2582 = bits(buf_ageQ[3], 2, 2) @[lsu_bus_buffer.scala 417:72] + node _T_2583 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 417:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2586 = and(_T_2582, _T_2585) @[lsu_bus_buffer.scala 417:76] + node _T_2587 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2588 = and(_T_2586, _T_2587) @[lsu_bus_buffer.scala 417:130] + node _T_2589 = bits(buf_ageQ[3], 3, 3) @[lsu_bus_buffer.scala 417:72] + node _T_2590 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 417:93] + node _T_2591 = and(_T_2590, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 417:103] + node _T_2592 = eq(_T_2591, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:78] + node _T_2593 = and(_T_2589, _T_2592) @[lsu_bus_buffer.scala 417:76] + node _T_2594 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:132] + node _T_2595 = and(_T_2593, _T_2594) @[lsu_bus_buffer.scala 417:130] + node _T_2596 = cat(_T_2595, _T_2588) @[Cat.scala 29:58] + node _T_2597 = cat(_T_2596, _T_2581) @[Cat.scala 29:58] + node _T_2598 = cat(_T_2597, _T_2574) @[Cat.scala 29:58] + buf_age[0] <= _T_2505 @[lsu_bus_buffer.scala 417:11] + buf_age[1] <= _T_2536 @[lsu_bus_buffer.scala 417:11] + buf_age[2] <= _T_2567 @[lsu_bus_buffer.scala 417:11] + buf_age[3] <= _T_2598 @[lsu_bus_buffer.scala 417:11] + node _T_2599 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2600 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2601 = eq(_T_2600, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2602 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2603 = and(_T_2601, _T_2602) @[lsu_bus_buffer.scala 418:104] + node _T_2604 = mux(_T_2599, UInt<1>("h00"), _T_2603) @[lsu_bus_buffer.scala 418:72] + node _T_2605 = eq(UInt<1>("h00"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2606 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2607 = eq(_T_2606, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2608 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2609 = and(_T_2607, _T_2608) @[lsu_bus_buffer.scala 418:104] + node _T_2610 = mux(_T_2605, UInt<1>("h00"), _T_2609) @[lsu_bus_buffer.scala 418:72] + node _T_2611 = eq(UInt<1>("h00"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2612 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2614 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2615 = and(_T_2613, _T_2614) @[lsu_bus_buffer.scala 418:104] + node _T_2616 = mux(_T_2611, UInt<1>("h00"), _T_2615) @[lsu_bus_buffer.scala 418:72] + node _T_2617 = eq(UInt<1>("h00"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2618 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2619 = eq(_T_2618, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2620 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2621 = and(_T_2619, _T_2620) @[lsu_bus_buffer.scala 418:104] + node _T_2622 = mux(_T_2617, UInt<1>("h00"), _T_2621) @[lsu_bus_buffer.scala 418:72] + node _T_2623 = cat(_T_2622, _T_2616) @[Cat.scala 29:58] + node _T_2624 = cat(_T_2623, _T_2610) @[Cat.scala 29:58] + node _T_2625 = cat(_T_2624, _T_2604) @[Cat.scala 29:58] + node _T_2626 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2627 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2628 = eq(_T_2627, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2629 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2630 = and(_T_2628, _T_2629) @[lsu_bus_buffer.scala 418:104] + node _T_2631 = mux(_T_2626, UInt<1>("h00"), _T_2630) @[lsu_bus_buffer.scala 418:72] + node _T_2632 = eq(UInt<1>("h01"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2633 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2634 = eq(_T_2633, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2635 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2636 = and(_T_2634, _T_2635) @[lsu_bus_buffer.scala 418:104] + node _T_2637 = mux(_T_2632, UInt<1>("h00"), _T_2636) @[lsu_bus_buffer.scala 418:72] + node _T_2638 = eq(UInt<1>("h01"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2639 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2640 = eq(_T_2639, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2641 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2642 = and(_T_2640, _T_2641) @[lsu_bus_buffer.scala 418:104] + node _T_2643 = mux(_T_2638, UInt<1>("h00"), _T_2642) @[lsu_bus_buffer.scala 418:72] + node _T_2644 = eq(UInt<1>("h01"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2645 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2646 = eq(_T_2645, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2647 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2648 = and(_T_2646, _T_2647) @[lsu_bus_buffer.scala 418:104] + node _T_2649 = mux(_T_2644, UInt<1>("h00"), _T_2648) @[lsu_bus_buffer.scala 418:72] + node _T_2650 = cat(_T_2649, _T_2643) @[Cat.scala 29:58] + node _T_2651 = cat(_T_2650, _T_2637) @[Cat.scala 29:58] + node _T_2652 = cat(_T_2651, _T_2631) @[Cat.scala 29:58] + node _T_2653 = eq(UInt<2>("h02"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2654 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2655 = eq(_T_2654, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2656 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2657 = and(_T_2655, _T_2656) @[lsu_bus_buffer.scala 418:104] + node _T_2658 = mux(_T_2653, UInt<1>("h00"), _T_2657) @[lsu_bus_buffer.scala 418:72] + node _T_2659 = eq(UInt<2>("h02"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2660 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2661 = eq(_T_2660, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2662 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2663 = and(_T_2661, _T_2662) @[lsu_bus_buffer.scala 418:104] + node _T_2664 = mux(_T_2659, UInt<1>("h00"), _T_2663) @[lsu_bus_buffer.scala 418:72] + node _T_2665 = eq(UInt<2>("h02"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2666 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2667 = eq(_T_2666, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2668 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2669 = and(_T_2667, _T_2668) @[lsu_bus_buffer.scala 418:104] + node _T_2670 = mux(_T_2665, UInt<1>("h00"), _T_2669) @[lsu_bus_buffer.scala 418:72] + node _T_2671 = eq(UInt<2>("h02"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2672 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2673 = eq(_T_2672, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2674 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2675 = and(_T_2673, _T_2674) @[lsu_bus_buffer.scala 418:104] + node _T_2676 = mux(_T_2671, UInt<1>("h00"), _T_2675) @[lsu_bus_buffer.scala 418:72] + node _T_2677 = cat(_T_2676, _T_2670) @[Cat.scala 29:58] + node _T_2678 = cat(_T_2677, _T_2664) @[Cat.scala 29:58] + node _T_2679 = cat(_T_2678, _T_2658) @[Cat.scala 29:58] + node _T_2680 = eq(UInt<2>("h03"), UInt<1>("h00")) @[lsu_bus_buffer.scala 418:76] + node _T_2681 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 418:100] + node _T_2682 = eq(_T_2681, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2683 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2684 = and(_T_2682, _T_2683) @[lsu_bus_buffer.scala 418:104] + node _T_2685 = mux(_T_2680, UInt<1>("h00"), _T_2684) @[lsu_bus_buffer.scala 418:72] + node _T_2686 = eq(UInt<2>("h03"), UInt<1>("h01")) @[lsu_bus_buffer.scala 418:76] + node _T_2687 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 418:100] + node _T_2688 = eq(_T_2687, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2689 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2690 = and(_T_2688, _T_2689) @[lsu_bus_buffer.scala 418:104] + node _T_2691 = mux(_T_2686, UInt<1>("h00"), _T_2690) @[lsu_bus_buffer.scala 418:72] + node _T_2692 = eq(UInt<2>("h03"), UInt<2>("h02")) @[lsu_bus_buffer.scala 418:76] + node _T_2693 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 418:100] + node _T_2694 = eq(_T_2693, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2695 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2696 = and(_T_2694, _T_2695) @[lsu_bus_buffer.scala 418:104] + node _T_2697 = mux(_T_2692, UInt<1>("h00"), _T_2696) @[lsu_bus_buffer.scala 418:72] + node _T_2698 = eq(UInt<2>("h03"), UInt<2>("h03")) @[lsu_bus_buffer.scala 418:76] + node _T_2699 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 418:100] + node _T_2700 = eq(_T_2699, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:89] + node _T_2701 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:119] + node _T_2702 = and(_T_2700, _T_2701) @[lsu_bus_buffer.scala 418:104] + node _T_2703 = mux(_T_2698, UInt<1>("h00"), _T_2702) @[lsu_bus_buffer.scala 418:72] + node _T_2704 = cat(_T_2703, _T_2697) @[Cat.scala 29:58] + node _T_2705 = cat(_T_2704, _T_2691) @[Cat.scala 29:58] + node _T_2706 = cat(_T_2705, _T_2685) @[Cat.scala 29:58] + buf_age_younger[0] <= _T_2625 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[1] <= _T_2652 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[2] <= _T_2679 @[lsu_bus_buffer.scala 418:19] + buf_age_younger[3] <= _T_2706 @[lsu_bus_buffer.scala 418:19] + node _T_2707 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2708 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2709 = and(_T_2707, _T_2708) @[lsu_bus_buffer.scala 419:87] + node _T_2710 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2711 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2712 = and(_T_2710, _T_2711) @[lsu_bus_buffer.scala 419:87] + node _T_2713 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2714 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2715 = and(_T_2713, _T_2714) @[lsu_bus_buffer.scala 419:87] + node _T_2716 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2717 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2718 = and(_T_2716, _T_2717) @[lsu_bus_buffer.scala 419:87] + node _T_2719 = cat(_T_2718, _T_2715) @[Cat.scala 29:58] + node _T_2720 = cat(_T_2719, _T_2712) @[Cat.scala 29:58] + node _T_2721 = cat(_T_2720, _T_2709) @[Cat.scala 29:58] + node _T_2722 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2723 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2724 = and(_T_2722, _T_2723) @[lsu_bus_buffer.scala 419:87] + node _T_2725 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2726 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2727 = and(_T_2725, _T_2726) @[lsu_bus_buffer.scala 419:87] + node _T_2728 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2729 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2730 = and(_T_2728, _T_2729) @[lsu_bus_buffer.scala 419:87] + node _T_2731 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2732 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2733 = and(_T_2731, _T_2732) @[lsu_bus_buffer.scala 419:87] + node _T_2734 = cat(_T_2733, _T_2730) @[Cat.scala 29:58] + node _T_2735 = cat(_T_2734, _T_2727) @[Cat.scala 29:58] + node _T_2736 = cat(_T_2735, _T_2724) @[Cat.scala 29:58] + node _T_2737 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2738 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2739 = and(_T_2737, _T_2738) @[lsu_bus_buffer.scala 419:87] + node _T_2740 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2741 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2742 = and(_T_2740, _T_2741) @[lsu_bus_buffer.scala 419:87] + node _T_2743 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2744 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2745 = and(_T_2743, _T_2744) @[lsu_bus_buffer.scala 419:87] + node _T_2746 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2747 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2748 = and(_T_2746, _T_2747) @[lsu_bus_buffer.scala 419:87] + node _T_2749 = cat(_T_2748, _T_2745) @[Cat.scala 29:58] + node _T_2750 = cat(_T_2749, _T_2742) @[Cat.scala 29:58] + node _T_2751 = cat(_T_2750, _T_2739) @[Cat.scala 29:58] + node _T_2752 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 419:83] + node _T_2753 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2754 = and(_T_2752, _T_2753) @[lsu_bus_buffer.scala 419:87] + node _T_2755 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 419:83] + node _T_2756 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2757 = and(_T_2755, _T_2756) @[lsu_bus_buffer.scala 419:87] + node _T_2758 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 419:83] + node _T_2759 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2760 = and(_T_2758, _T_2759) @[lsu_bus_buffer.scala 419:87] + node _T_2761 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 419:83] + node _T_2762 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 419:102] + node _T_2763 = and(_T_2761, _T_2762) @[lsu_bus_buffer.scala 419:87] + node _T_2764 = cat(_T_2763, _T_2760) @[Cat.scala 29:58] + node _T_2765 = cat(_T_2764, _T_2757) @[Cat.scala 29:58] + node _T_2766 = cat(_T_2765, _T_2754) @[Cat.scala 29:58] + buf_rsp_pickage[0] <= _T_2721 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[1] <= _T_2736 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[2] <= _T_2751 @[lsu_bus_buffer.scala 419:19] + buf_rsp_pickage[3] <= _T_2766 @[lsu_bus_buffer.scala 419:19] + node _T_2767 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2768 = and(_T_2767, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2769 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2770 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2771 = or(_T_2769, _T_2770) @[lsu_bus_buffer.scala 422:32] + node _T_2772 = eq(_T_2771, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2773 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2774 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2775 = and(_T_2773, _T_2774) @[lsu_bus_buffer.scala 423:41] + node _T_2776 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2777 = and(_T_2775, _T_2776) @[lsu_bus_buffer.scala 423:71] + node _T_2778 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2779 = and(_T_2777, _T_2778) @[lsu_bus_buffer.scala 423:90] + node _T_2780 = or(_T_2772, _T_2779) @[lsu_bus_buffer.scala 422:59] + node _T_2781 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2782 = and(_T_2781, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2783 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2784 = and(_T_2782, _T_2783) @[lsu_bus_buffer.scala 424:52] + node _T_2785 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2786 = and(_T_2784, _T_2785) @[lsu_bus_buffer.scala 424:71] + node _T_2787 = or(_T_2780, _T_2786) @[lsu_bus_buffer.scala 423:110] + node _T_2788 = and(_T_2768, _T_2787) @[lsu_bus_buffer.scala 421:112] + node _T_2789 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2790 = and(_T_2789, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2791 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2792 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2793 = or(_T_2791, _T_2792) @[lsu_bus_buffer.scala 422:32] + node _T_2794 = eq(_T_2793, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2795 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2796 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2797 = and(_T_2795, _T_2796) @[lsu_bus_buffer.scala 423:41] + node _T_2798 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2799 = and(_T_2797, _T_2798) @[lsu_bus_buffer.scala 423:71] + node _T_2800 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2801 = and(_T_2799, _T_2800) @[lsu_bus_buffer.scala 423:90] + node _T_2802 = or(_T_2794, _T_2801) @[lsu_bus_buffer.scala 422:59] + node _T_2803 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2804 = and(_T_2803, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2805 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2806 = and(_T_2804, _T_2805) @[lsu_bus_buffer.scala 424:52] + node _T_2807 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2808 = and(_T_2806, _T_2807) @[lsu_bus_buffer.scala 424:71] + node _T_2809 = or(_T_2802, _T_2808) @[lsu_bus_buffer.scala 423:110] + node _T_2810 = and(_T_2790, _T_2809) @[lsu_bus_buffer.scala 421:112] + node _T_2811 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2812 = and(_T_2811, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2813 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2814 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2815 = or(_T_2813, _T_2814) @[lsu_bus_buffer.scala 422:32] + node _T_2816 = eq(_T_2815, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2817 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2818 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2819 = and(_T_2817, _T_2818) @[lsu_bus_buffer.scala 423:41] + node _T_2820 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2821 = and(_T_2819, _T_2820) @[lsu_bus_buffer.scala 423:71] + node _T_2822 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_2823 = and(_T_2821, _T_2822) @[lsu_bus_buffer.scala 423:90] + node _T_2824 = or(_T_2816, _T_2823) @[lsu_bus_buffer.scala 422:59] + node _T_2825 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2826 = and(_T_2825, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2827 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2828 = and(_T_2826, _T_2827) @[lsu_bus_buffer.scala 424:52] + node _T_2829 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_2830 = and(_T_2828, _T_2829) @[lsu_bus_buffer.scala 424:71] + node _T_2831 = or(_T_2824, _T_2830) @[lsu_bus_buffer.scala 423:110] + node _T_2832 = and(_T_2812, _T_2831) @[lsu_bus_buffer.scala 421:112] + node _T_2833 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2834 = and(_T_2833, buf_state_en[0]) @[lsu_bus_buffer.scala 421:93] + node _T_2835 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2836 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2837 = or(_T_2835, _T_2836) @[lsu_bus_buffer.scala 422:32] + node _T_2838 = eq(_T_2837, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2839 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2840 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2841 = and(_T_2839, _T_2840) @[lsu_bus_buffer.scala 423:41] + node _T_2842 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:82] + node _T_2843 = and(_T_2841, _T_2842) @[lsu_bus_buffer.scala 423:71] + node _T_2844 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_2845 = and(_T_2843, _T_2844) @[lsu_bus_buffer.scala 423:90] + node _T_2846 = or(_T_2838, _T_2845) @[lsu_bus_buffer.scala 422:59] + node _T_2847 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2848 = and(_T_2847, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2849 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:63] + node _T_2850 = and(_T_2848, _T_2849) @[lsu_bus_buffer.scala 424:52] + node _T_2851 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_2852 = and(_T_2850, _T_2851) @[lsu_bus_buffer.scala 424:71] + node _T_2853 = or(_T_2846, _T_2852) @[lsu_bus_buffer.scala 423:110] + node _T_2854 = and(_T_2834, _T_2853) @[lsu_bus_buffer.scala 421:112] + node _T_2855 = cat(_T_2854, _T_2832) @[Cat.scala 29:58] + node _T_2856 = cat(_T_2855, _T_2810) @[Cat.scala 29:58] + node _T_2857 = cat(_T_2856, _T_2788) @[Cat.scala 29:58] + node _T_2858 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2859 = and(_T_2858, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2860 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2861 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2862 = or(_T_2860, _T_2861) @[lsu_bus_buffer.scala 422:32] + node _T_2863 = eq(_T_2862, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2864 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2865 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2866 = and(_T_2864, _T_2865) @[lsu_bus_buffer.scala 423:41] + node _T_2867 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2868 = and(_T_2866, _T_2867) @[lsu_bus_buffer.scala 423:71] + node _T_2869 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2870 = and(_T_2868, _T_2869) @[lsu_bus_buffer.scala 423:90] + node _T_2871 = or(_T_2863, _T_2870) @[lsu_bus_buffer.scala 422:59] + node _T_2872 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2873 = and(_T_2872, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2874 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2875 = and(_T_2873, _T_2874) @[lsu_bus_buffer.scala 424:52] + node _T_2876 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2877 = and(_T_2875, _T_2876) @[lsu_bus_buffer.scala 424:71] + node _T_2878 = or(_T_2871, _T_2877) @[lsu_bus_buffer.scala 423:110] + node _T_2879 = and(_T_2859, _T_2878) @[lsu_bus_buffer.scala 421:112] + node _T_2880 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2881 = and(_T_2880, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2882 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2883 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2884 = or(_T_2882, _T_2883) @[lsu_bus_buffer.scala 422:32] + node _T_2885 = eq(_T_2884, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2886 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2887 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2888 = and(_T_2886, _T_2887) @[lsu_bus_buffer.scala 423:41] + node _T_2889 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2890 = and(_T_2888, _T_2889) @[lsu_bus_buffer.scala 423:71] + node _T_2891 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2892 = and(_T_2890, _T_2891) @[lsu_bus_buffer.scala 423:90] + node _T_2893 = or(_T_2885, _T_2892) @[lsu_bus_buffer.scala 422:59] + node _T_2894 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2895 = and(_T_2894, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2896 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2897 = and(_T_2895, _T_2896) @[lsu_bus_buffer.scala 424:52] + node _T_2898 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2899 = and(_T_2897, _T_2898) @[lsu_bus_buffer.scala 424:71] + node _T_2900 = or(_T_2893, _T_2899) @[lsu_bus_buffer.scala 423:110] + node _T_2901 = and(_T_2881, _T_2900) @[lsu_bus_buffer.scala 421:112] + node _T_2902 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2903 = and(_T_2902, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2904 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2905 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2906 = or(_T_2904, _T_2905) @[lsu_bus_buffer.scala 422:32] + node _T_2907 = eq(_T_2906, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2908 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2909 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2910 = and(_T_2908, _T_2909) @[lsu_bus_buffer.scala 423:41] + node _T_2911 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2912 = and(_T_2910, _T_2911) @[lsu_bus_buffer.scala 423:71] + node _T_2913 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_2914 = and(_T_2912, _T_2913) @[lsu_bus_buffer.scala 423:90] + node _T_2915 = or(_T_2907, _T_2914) @[lsu_bus_buffer.scala 422:59] + node _T_2916 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2917 = and(_T_2916, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2918 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2919 = and(_T_2917, _T_2918) @[lsu_bus_buffer.scala 424:52] + node _T_2920 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_2921 = and(_T_2919, _T_2920) @[lsu_bus_buffer.scala 424:71] + node _T_2922 = or(_T_2915, _T_2921) @[lsu_bus_buffer.scala 423:110] + node _T_2923 = and(_T_2903, _T_2922) @[lsu_bus_buffer.scala 421:112] + node _T_2924 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2925 = and(_T_2924, buf_state_en[1]) @[lsu_bus_buffer.scala 421:93] + node _T_2926 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2927 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2928 = or(_T_2926, _T_2927) @[lsu_bus_buffer.scala 422:32] + node _T_2929 = eq(_T_2928, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2930 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2931 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2932 = and(_T_2930, _T_2931) @[lsu_bus_buffer.scala 423:41] + node _T_2933 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:82] + node _T_2934 = and(_T_2932, _T_2933) @[lsu_bus_buffer.scala 423:71] + node _T_2935 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_2936 = and(_T_2934, _T_2935) @[lsu_bus_buffer.scala 423:90] + node _T_2937 = or(_T_2929, _T_2936) @[lsu_bus_buffer.scala 422:59] + node _T_2938 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2939 = and(_T_2938, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2940 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:63] + node _T_2941 = and(_T_2939, _T_2940) @[lsu_bus_buffer.scala 424:52] + node _T_2942 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_2943 = and(_T_2941, _T_2942) @[lsu_bus_buffer.scala 424:71] + node _T_2944 = or(_T_2937, _T_2943) @[lsu_bus_buffer.scala 423:110] + node _T_2945 = and(_T_2925, _T_2944) @[lsu_bus_buffer.scala 421:112] + node _T_2946 = cat(_T_2945, _T_2923) @[Cat.scala 29:58] + node _T_2947 = cat(_T_2946, _T_2901) @[Cat.scala 29:58] + node _T_2948 = cat(_T_2947, _T_2879) @[Cat.scala 29:58] + node _T_2949 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2950 = and(_T_2949, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2951 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2952 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2953 = or(_T_2951, _T_2952) @[lsu_bus_buffer.scala 422:32] + node _T_2954 = eq(_T_2953, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2955 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2956 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2957 = and(_T_2955, _T_2956) @[lsu_bus_buffer.scala 423:41] + node _T_2958 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_2959 = and(_T_2957, _T_2958) @[lsu_bus_buffer.scala 423:71] + node _T_2960 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_2961 = and(_T_2959, _T_2960) @[lsu_bus_buffer.scala 423:90] + node _T_2962 = or(_T_2954, _T_2961) @[lsu_bus_buffer.scala 422:59] + node _T_2963 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2964 = and(_T_2963, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2965 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_2966 = and(_T_2964, _T_2965) @[lsu_bus_buffer.scala 424:52] + node _T_2967 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_2968 = and(_T_2966, _T_2967) @[lsu_bus_buffer.scala 424:71] + node _T_2969 = or(_T_2962, _T_2968) @[lsu_bus_buffer.scala 423:110] + node _T_2970 = and(_T_2950, _T_2969) @[lsu_bus_buffer.scala 421:112] + node _T_2971 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2972 = and(_T_2971, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2973 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2974 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2975 = or(_T_2973, _T_2974) @[lsu_bus_buffer.scala 422:32] + node _T_2976 = eq(_T_2975, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2977 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_2978 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_2979 = and(_T_2977, _T_2978) @[lsu_bus_buffer.scala 423:41] + node _T_2980 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_2981 = and(_T_2979, _T_2980) @[lsu_bus_buffer.scala 423:71] + node _T_2982 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_2983 = and(_T_2981, _T_2982) @[lsu_bus_buffer.scala 423:90] + node _T_2984 = or(_T_2976, _T_2983) @[lsu_bus_buffer.scala 422:59] + node _T_2985 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_2986 = and(_T_2985, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_2987 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_2988 = and(_T_2986, _T_2987) @[lsu_bus_buffer.scala 424:52] + node _T_2989 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_2990 = and(_T_2988, _T_2989) @[lsu_bus_buffer.scala 424:71] + node _T_2991 = or(_T_2984, _T_2990) @[lsu_bus_buffer.scala 423:110] + node _T_2992 = and(_T_2972, _T_2991) @[lsu_bus_buffer.scala 421:112] + node _T_2993 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_2994 = and(_T_2993, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_2995 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_2996 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_2997 = or(_T_2995, _T_2996) @[lsu_bus_buffer.scala 422:32] + node _T_2998 = eq(_T_2997, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_2999 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3000 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3001 = and(_T_2999, _T_3000) @[lsu_bus_buffer.scala 423:41] + node _T_3002 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_3003 = and(_T_3001, _T_3002) @[lsu_bus_buffer.scala 423:71] + node _T_3004 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_3005 = and(_T_3003, _T_3004) @[lsu_bus_buffer.scala 423:90] + node _T_3006 = or(_T_2998, _T_3005) @[lsu_bus_buffer.scala 422:59] + node _T_3007 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3008 = and(_T_3007, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3009 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_3010 = and(_T_3008, _T_3009) @[lsu_bus_buffer.scala 424:52] + node _T_3011 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_3012 = and(_T_3010, _T_3011) @[lsu_bus_buffer.scala 424:71] + node _T_3013 = or(_T_3006, _T_3012) @[lsu_bus_buffer.scala 423:110] + node _T_3014 = and(_T_2994, _T_3013) @[lsu_bus_buffer.scala 421:112] + node _T_3015 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3016 = and(_T_3015, buf_state_en[2]) @[lsu_bus_buffer.scala 421:93] + node _T_3017 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3018 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3019 = or(_T_3017, _T_3018) @[lsu_bus_buffer.scala 422:32] + node _T_3020 = eq(_T_3019, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3021 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3022 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3023 = and(_T_3021, _T_3022) @[lsu_bus_buffer.scala 423:41] + node _T_3024 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:82] + node _T_3025 = and(_T_3023, _T_3024) @[lsu_bus_buffer.scala 423:71] + node _T_3026 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_3027 = and(_T_3025, _T_3026) @[lsu_bus_buffer.scala 423:90] + node _T_3028 = or(_T_3020, _T_3027) @[lsu_bus_buffer.scala 422:59] + node _T_3029 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3030 = and(_T_3029, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3031 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:63] + node _T_3032 = and(_T_3030, _T_3031) @[lsu_bus_buffer.scala 424:52] + node _T_3033 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_3034 = and(_T_3032, _T_3033) @[lsu_bus_buffer.scala 424:71] + node _T_3035 = or(_T_3028, _T_3034) @[lsu_bus_buffer.scala 423:110] + node _T_3036 = and(_T_3016, _T_3035) @[lsu_bus_buffer.scala 421:112] + node _T_3037 = cat(_T_3036, _T_3014) @[Cat.scala 29:58] + node _T_3038 = cat(_T_3037, _T_2992) @[Cat.scala 29:58] + node _T_3039 = cat(_T_3038, _T_2970) @[Cat.scala 29:58] + node _T_3040 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3041 = and(_T_3040, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3042 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3043 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3044 = or(_T_3042, _T_3043) @[lsu_bus_buffer.scala 422:32] + node _T_3045 = eq(_T_3044, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3046 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3047 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3048 = and(_T_3046, _T_3047) @[lsu_bus_buffer.scala 423:41] + node _T_3049 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3050 = and(_T_3048, _T_3049) @[lsu_bus_buffer.scala 423:71] + node _T_3051 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:101] + node _T_3052 = and(_T_3050, _T_3051) @[lsu_bus_buffer.scala 423:90] + node _T_3053 = or(_T_3045, _T_3052) @[lsu_bus_buffer.scala 422:59] + node _T_3054 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3055 = and(_T_3054, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3056 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3057 = and(_T_3055, _T_3056) @[lsu_bus_buffer.scala 424:52] + node _T_3058 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:82] + node _T_3059 = and(_T_3057, _T_3058) @[lsu_bus_buffer.scala 424:71] + node _T_3060 = or(_T_3053, _T_3059) @[lsu_bus_buffer.scala 423:110] + node _T_3061 = and(_T_3041, _T_3060) @[lsu_bus_buffer.scala 421:112] + node _T_3062 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3063 = and(_T_3062, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3064 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3065 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3066 = or(_T_3064, _T_3065) @[lsu_bus_buffer.scala 422:32] + node _T_3067 = eq(_T_3066, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3068 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3069 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3070 = and(_T_3068, _T_3069) @[lsu_bus_buffer.scala 423:41] + node _T_3071 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3072 = and(_T_3070, _T_3071) @[lsu_bus_buffer.scala 423:71] + node _T_3073 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 423:101] + node _T_3074 = and(_T_3072, _T_3073) @[lsu_bus_buffer.scala 423:90] + node _T_3075 = or(_T_3067, _T_3074) @[lsu_bus_buffer.scala 422:59] + node _T_3076 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3077 = and(_T_3076, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3078 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3079 = and(_T_3077, _T_3078) @[lsu_bus_buffer.scala 424:52] + node _T_3080 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 424:82] + node _T_3081 = and(_T_3079, _T_3080) @[lsu_bus_buffer.scala 424:71] + node _T_3082 = or(_T_3075, _T_3081) @[lsu_bus_buffer.scala 423:110] + node _T_3083 = and(_T_3063, _T_3082) @[lsu_bus_buffer.scala 421:112] + node _T_3084 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3085 = and(_T_3084, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3086 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3087 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3088 = or(_T_3086, _T_3087) @[lsu_bus_buffer.scala 422:32] + node _T_3089 = eq(_T_3088, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3090 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3091 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3092 = and(_T_3090, _T_3091) @[lsu_bus_buffer.scala 423:41] + node _T_3093 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3094 = and(_T_3092, _T_3093) @[lsu_bus_buffer.scala 423:71] + node _T_3095 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 423:101] + node _T_3096 = and(_T_3094, _T_3095) @[lsu_bus_buffer.scala 423:90] + node _T_3097 = or(_T_3089, _T_3096) @[lsu_bus_buffer.scala 422:59] + node _T_3098 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3099 = and(_T_3098, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3100 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3101 = and(_T_3099, _T_3100) @[lsu_bus_buffer.scala 424:52] + node _T_3102 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 424:82] + node _T_3103 = and(_T_3101, _T_3102) @[lsu_bus_buffer.scala 424:71] + node _T_3104 = or(_T_3097, _T_3103) @[lsu_bus_buffer.scala 423:110] + node _T_3105 = and(_T_3085, _T_3104) @[lsu_bus_buffer.scala 421:112] + node _T_3106 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:82] + node _T_3107 = and(_T_3106, buf_state_en[3]) @[lsu_bus_buffer.scala 421:93] + node _T_3108 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 422:21] + node _T_3109 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 422:47] + node _T_3110 = or(_T_3108, _T_3109) @[lsu_bus_buffer.scala 422:32] + node _T_3111 = eq(_T_3110, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:6] + node _T_3112 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 423:23] + node _T_3113 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 423:53] + node _T_3114 = and(_T_3112, _T_3113) @[lsu_bus_buffer.scala 423:41] + node _T_3115 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:82] + node _T_3116 = and(_T_3114, _T_3115) @[lsu_bus_buffer.scala 423:71] + node _T_3117 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 423:101] + node _T_3118 = and(_T_3116, _T_3117) @[lsu_bus_buffer.scala 423:90] + node _T_3119 = or(_T_3111, _T_3118) @[lsu_bus_buffer.scala 422:59] + node _T_3120 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 424:17] + node _T_3121 = and(_T_3120, io.ldst_dual_r) @[lsu_bus_buffer.scala 424:35] + node _T_3122 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:63] + node _T_3123 = and(_T_3121, _T_3122) @[lsu_bus_buffer.scala 424:52] + node _T_3124 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 424:82] + node _T_3125 = and(_T_3123, _T_3124) @[lsu_bus_buffer.scala 424:71] + node _T_3126 = or(_T_3119, _T_3125) @[lsu_bus_buffer.scala 423:110] + node _T_3127 = and(_T_3107, _T_3126) @[lsu_bus_buffer.scala 421:112] + node _T_3128 = cat(_T_3127, _T_3105) @[Cat.scala 29:58] + node _T_3129 = cat(_T_3128, _T_3083) @[Cat.scala 29:58] + node _T_3130 = cat(_T_3129, _T_3061) @[Cat.scala 29:58] + buf_rspage_set[0] <= _T_2857 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[1] <= _T_2948 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[2] <= _T_3039 @[lsu_bus_buffer.scala 421:18] + buf_rspage_set[3] <= _T_3130 @[lsu_bus_buffer.scala 421:18] + node _T_3131 = bits(buf_rspage_set[0], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3132 = bits(buf_rspage[0], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3133 = or(_T_3131, _T_3132) @[lsu_bus_buffer.scala 425:88] + node _T_3134 = bits(buf_rspage_set[0], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3135 = bits(buf_rspage[0], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3136 = or(_T_3134, _T_3135) @[lsu_bus_buffer.scala 425:88] + node _T_3137 = bits(buf_rspage_set[0], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3138 = bits(buf_rspage[0], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3139 = or(_T_3137, _T_3138) @[lsu_bus_buffer.scala 425:88] + node _T_3140 = bits(buf_rspage_set[0], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3141 = bits(buf_rspage[0], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3142 = or(_T_3140, _T_3141) @[lsu_bus_buffer.scala 425:88] + node _T_3143 = cat(_T_3142, _T_3139) @[Cat.scala 29:58] + node _T_3144 = cat(_T_3143, _T_3136) @[Cat.scala 29:58] + node _T_3145 = cat(_T_3144, _T_3133) @[Cat.scala 29:58] + node _T_3146 = bits(buf_rspage_set[1], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3147 = bits(buf_rspage[1], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3148 = or(_T_3146, _T_3147) @[lsu_bus_buffer.scala 425:88] + node _T_3149 = bits(buf_rspage_set[1], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3150 = bits(buf_rspage[1], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3151 = or(_T_3149, _T_3150) @[lsu_bus_buffer.scala 425:88] + node _T_3152 = bits(buf_rspage_set[1], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3153 = bits(buf_rspage[1], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3154 = or(_T_3152, _T_3153) @[lsu_bus_buffer.scala 425:88] + node _T_3155 = bits(buf_rspage_set[1], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3156 = bits(buf_rspage[1], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3157 = or(_T_3155, _T_3156) @[lsu_bus_buffer.scala 425:88] + node _T_3158 = cat(_T_3157, _T_3154) @[Cat.scala 29:58] + node _T_3159 = cat(_T_3158, _T_3151) @[Cat.scala 29:58] + node _T_3160 = cat(_T_3159, _T_3148) @[Cat.scala 29:58] + node _T_3161 = bits(buf_rspage_set[2], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3162 = bits(buf_rspage[2], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3163 = or(_T_3161, _T_3162) @[lsu_bus_buffer.scala 425:88] + node _T_3164 = bits(buf_rspage_set[2], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3165 = bits(buf_rspage[2], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3166 = or(_T_3164, _T_3165) @[lsu_bus_buffer.scala 425:88] + node _T_3167 = bits(buf_rspage_set[2], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3168 = bits(buf_rspage[2], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3169 = or(_T_3167, _T_3168) @[lsu_bus_buffer.scala 425:88] + node _T_3170 = bits(buf_rspage_set[2], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3171 = bits(buf_rspage[2], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3172 = or(_T_3170, _T_3171) @[lsu_bus_buffer.scala 425:88] + node _T_3173 = cat(_T_3172, _T_3169) @[Cat.scala 29:58] + node _T_3174 = cat(_T_3173, _T_3166) @[Cat.scala 29:58] + node _T_3175 = cat(_T_3174, _T_3163) @[Cat.scala 29:58] + node _T_3176 = bits(buf_rspage_set[3], 0, 0) @[lsu_bus_buffer.scala 425:84] + node _T_3177 = bits(buf_rspage[3], 0, 0) @[lsu_bus_buffer.scala 425:103] + node _T_3178 = or(_T_3176, _T_3177) @[lsu_bus_buffer.scala 425:88] + node _T_3179 = bits(buf_rspage_set[3], 1, 1) @[lsu_bus_buffer.scala 425:84] + node _T_3180 = bits(buf_rspage[3], 1, 1) @[lsu_bus_buffer.scala 425:103] + node _T_3181 = or(_T_3179, _T_3180) @[lsu_bus_buffer.scala 425:88] + node _T_3182 = bits(buf_rspage_set[3], 2, 2) @[lsu_bus_buffer.scala 425:84] + node _T_3183 = bits(buf_rspage[3], 2, 2) @[lsu_bus_buffer.scala 425:103] + node _T_3184 = or(_T_3182, _T_3183) @[lsu_bus_buffer.scala 425:88] + node _T_3185 = bits(buf_rspage_set[3], 3, 3) @[lsu_bus_buffer.scala 425:84] + node _T_3186 = bits(buf_rspage[3], 3, 3) @[lsu_bus_buffer.scala 425:103] + node _T_3187 = or(_T_3185, _T_3186) @[lsu_bus_buffer.scala 425:88] + node _T_3188 = cat(_T_3187, _T_3184) @[Cat.scala 29:58] + node _T_3189 = cat(_T_3188, _T_3181) @[Cat.scala 29:58] + node _T_3190 = cat(_T_3189, _T_3178) @[Cat.scala 29:58] + buf_rspage_in[0] <= _T_3145 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[1] <= _T_3160 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[2] <= _T_3175 @[lsu_bus_buffer.scala 425:17] + buf_rspage_in[3] <= _T_3190 @[lsu_bus_buffer.scala 425:17] + node _T_3191 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3192 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3193 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3194 = or(_T_3192, _T_3193) @[lsu_bus_buffer.scala 426:110] + node _T_3195 = eq(_T_3194, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3196 = and(_T_3191, _T_3195) @[lsu_bus_buffer.scala 426:82] + node _T_3197 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3198 = and(_T_3196, _T_3197) @[lsu_bus_buffer.scala 426:136] + node _T_3199 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3200 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3201 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3202 = or(_T_3200, _T_3201) @[lsu_bus_buffer.scala 426:110] + node _T_3203 = eq(_T_3202, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3204 = and(_T_3199, _T_3203) @[lsu_bus_buffer.scala 426:82] + node _T_3205 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3206 = and(_T_3204, _T_3205) @[lsu_bus_buffer.scala 426:136] + node _T_3207 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3208 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3209 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3210 = or(_T_3208, _T_3209) @[lsu_bus_buffer.scala 426:110] + node _T_3211 = eq(_T_3210, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3212 = and(_T_3207, _T_3211) @[lsu_bus_buffer.scala 426:82] + node _T_3213 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3214 = and(_T_3212, _T_3213) @[lsu_bus_buffer.scala 426:136] + node _T_3215 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3216 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3217 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3218 = or(_T_3216, _T_3217) @[lsu_bus_buffer.scala 426:110] + node _T_3219 = eq(_T_3218, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3220 = and(_T_3215, _T_3219) @[lsu_bus_buffer.scala 426:82] + node _T_3221 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3222 = and(_T_3220, _T_3221) @[lsu_bus_buffer.scala 426:136] + node _T_3223 = cat(_T_3222, _T_3214) @[Cat.scala 29:58] + node _T_3224 = cat(_T_3223, _T_3206) @[Cat.scala 29:58] + node _T_3225 = cat(_T_3224, _T_3198) @[Cat.scala 29:58] + node _T_3226 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3227 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3228 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3229 = or(_T_3227, _T_3228) @[lsu_bus_buffer.scala 426:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3231 = and(_T_3226, _T_3230) @[lsu_bus_buffer.scala 426:82] + node _T_3232 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3233 = and(_T_3231, _T_3232) @[lsu_bus_buffer.scala 426:136] + node _T_3234 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3235 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3236 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3237 = or(_T_3235, _T_3236) @[lsu_bus_buffer.scala 426:110] + node _T_3238 = eq(_T_3237, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3239 = and(_T_3234, _T_3238) @[lsu_bus_buffer.scala 426:82] + node _T_3240 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3241 = and(_T_3239, _T_3240) @[lsu_bus_buffer.scala 426:136] + node _T_3242 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3243 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3244 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3245 = or(_T_3243, _T_3244) @[lsu_bus_buffer.scala 426:110] + node _T_3246 = eq(_T_3245, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3247 = and(_T_3242, _T_3246) @[lsu_bus_buffer.scala 426:82] + node _T_3248 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3249 = and(_T_3247, _T_3248) @[lsu_bus_buffer.scala 426:136] + node _T_3250 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3251 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3252 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3253 = or(_T_3251, _T_3252) @[lsu_bus_buffer.scala 426:110] + node _T_3254 = eq(_T_3253, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3255 = and(_T_3250, _T_3254) @[lsu_bus_buffer.scala 426:82] + node _T_3256 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3257 = and(_T_3255, _T_3256) @[lsu_bus_buffer.scala 426:136] + node _T_3258 = cat(_T_3257, _T_3249) @[Cat.scala 29:58] + node _T_3259 = cat(_T_3258, _T_3241) @[Cat.scala 29:58] + node _T_3260 = cat(_T_3259, _T_3233) @[Cat.scala 29:58] + node _T_3261 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3262 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3263 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3264 = or(_T_3262, _T_3263) @[lsu_bus_buffer.scala 426:110] + node _T_3265 = eq(_T_3264, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3266 = and(_T_3261, _T_3265) @[lsu_bus_buffer.scala 426:82] + node _T_3267 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3268 = and(_T_3266, _T_3267) @[lsu_bus_buffer.scala 426:136] + node _T_3269 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3270 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3271 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3272 = or(_T_3270, _T_3271) @[lsu_bus_buffer.scala 426:110] + node _T_3273 = eq(_T_3272, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3274 = and(_T_3269, _T_3273) @[lsu_bus_buffer.scala 426:82] + node _T_3275 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3276 = and(_T_3274, _T_3275) @[lsu_bus_buffer.scala 426:136] + node _T_3277 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3278 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3279 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3280 = or(_T_3278, _T_3279) @[lsu_bus_buffer.scala 426:110] + node _T_3281 = eq(_T_3280, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3282 = and(_T_3277, _T_3281) @[lsu_bus_buffer.scala 426:82] + node _T_3283 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3284 = and(_T_3282, _T_3283) @[lsu_bus_buffer.scala 426:136] + node _T_3285 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3286 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3287 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3288 = or(_T_3286, _T_3287) @[lsu_bus_buffer.scala 426:110] + node _T_3289 = eq(_T_3288, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3290 = and(_T_3285, _T_3289) @[lsu_bus_buffer.scala 426:82] + node _T_3291 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3292 = and(_T_3290, _T_3291) @[lsu_bus_buffer.scala 426:136] + node _T_3293 = cat(_T_3292, _T_3284) @[Cat.scala 29:58] + node _T_3294 = cat(_T_3293, _T_3276) @[Cat.scala 29:58] + node _T_3295 = cat(_T_3294, _T_3268) @[Cat.scala 29:58] + node _T_3296 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 426:78] + node _T_3297 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3298 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3299 = or(_T_3297, _T_3298) @[lsu_bus_buffer.scala 426:110] + node _T_3300 = eq(_T_3299, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3301 = and(_T_3296, _T_3300) @[lsu_bus_buffer.scala 426:82] + node _T_3302 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3303 = and(_T_3301, _T_3302) @[lsu_bus_buffer.scala 426:136] + node _T_3304 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 426:78] + node _T_3305 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3306 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3307 = or(_T_3305, _T_3306) @[lsu_bus_buffer.scala 426:110] + node _T_3308 = eq(_T_3307, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3309 = and(_T_3304, _T_3308) @[lsu_bus_buffer.scala 426:82] + node _T_3310 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3311 = and(_T_3309, _T_3310) @[lsu_bus_buffer.scala 426:136] + node _T_3312 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 426:78] + node _T_3313 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3314 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3315 = or(_T_3313, _T_3314) @[lsu_bus_buffer.scala 426:110] + node _T_3316 = eq(_T_3315, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3317 = and(_T_3312, _T_3316) @[lsu_bus_buffer.scala 426:82] + node _T_3318 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3319 = and(_T_3317, _T_3318) @[lsu_bus_buffer.scala 426:136] + node _T_3320 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 426:78] + node _T_3321 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 426:99] + node _T_3322 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 426:125] + node _T_3323 = or(_T_3321, _T_3322) @[lsu_bus_buffer.scala 426:110] + node _T_3324 = eq(_T_3323, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:84] + node _T_3325 = and(_T_3320, _T_3324) @[lsu_bus_buffer.scala 426:82] + node _T_3326 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:138] + node _T_3327 = and(_T_3325, _T_3326) @[lsu_bus_buffer.scala 426:136] + node _T_3328 = cat(_T_3327, _T_3319) @[Cat.scala 29:58] + node _T_3329 = cat(_T_3328, _T_3311) @[Cat.scala 29:58] + node _T_3330 = cat(_T_3329, _T_3303) @[Cat.scala 29:58] + buf_rspage[0] <= _T_3225 @[lsu_bus_buffer.scala 426:14] + buf_rspage[1] <= _T_3260 @[lsu_bus_buffer.scala 426:14] + buf_rspage[2] <= _T_3295 @[lsu_bus_buffer.scala 426:14] + buf_rspage[3] <= _T_3330 @[lsu_bus_buffer.scala 426:14] + node _T_3331 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 427:75] + node _T_3332 = and(ibuf_drain_vld, _T_3331) @[lsu_bus_buffer.scala 427:63] + node _T_3333 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 427:75] + node _T_3334 = and(ibuf_drain_vld, _T_3333) @[lsu_bus_buffer.scala 427:63] + node _T_3335 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 427:75] + node _T_3336 = and(ibuf_drain_vld, _T_3335) @[lsu_bus_buffer.scala 427:63] + node _T_3337 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 427:75] + node _T_3338 = and(ibuf_drain_vld, _T_3337) @[lsu_bus_buffer.scala 427:63] + node _T_3339 = cat(_T_3338, _T_3336) @[Cat.scala 29:58] + node _T_3340 = cat(_T_3339, _T_3334) @[Cat.scala 29:58] + node _T_3341 = cat(_T_3340, _T_3332) @[Cat.scala 29:58] + ibuf_drainvec_vld <= _T_3341 @[lsu_bus_buffer.scala 427:21] + node _T_3342 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 428:64] + node _T_3343 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3344 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3345 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 429:46] + node _T_3346 = and(_T_3344, _T_3345) @[lsu_bus_buffer.scala 429:35] + node _T_3347 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3348 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3349 = mux(_T_3346, _T_3347, _T_3348) @[lsu_bus_buffer.scala 429:8] + node _T_3350 = mux(_T_3342, _T_3343, _T_3349) @[lsu_bus_buffer.scala 428:46] + node _T_3351 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 428:64] + node _T_3352 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3353 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3354 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 429:46] + node _T_3355 = and(_T_3353, _T_3354) @[lsu_bus_buffer.scala 429:35] + node _T_3356 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3357 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3358 = mux(_T_3355, _T_3356, _T_3357) @[lsu_bus_buffer.scala 429:8] + node _T_3359 = mux(_T_3351, _T_3352, _T_3358) @[lsu_bus_buffer.scala 428:46] + node _T_3360 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 428:64] + node _T_3361 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3362 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3363 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 429:46] + node _T_3364 = and(_T_3362, _T_3363) @[lsu_bus_buffer.scala 429:35] + node _T_3365 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3366 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3367 = mux(_T_3364, _T_3365, _T_3366) @[lsu_bus_buffer.scala 429:8] + node _T_3368 = mux(_T_3360, _T_3361, _T_3367) @[lsu_bus_buffer.scala 428:46] + node _T_3369 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 428:64] + node _T_3370 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 428:84] + node _T_3371 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:18] + node _T_3372 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 429:46] + node _T_3373 = and(_T_3371, _T_3372) @[lsu_bus_buffer.scala 429:35] + node _T_3374 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 429:71] + node _T_3375 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 429:94] + node _T_3376 = mux(_T_3373, _T_3374, _T_3375) @[lsu_bus_buffer.scala 429:8] + node _T_3377 = mux(_T_3369, _T_3370, _T_3376) @[lsu_bus_buffer.scala 428:46] + buf_byteen_in[0] <= _T_3350 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[1] <= _T_3359 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[2] <= _T_3368 @[lsu_bus_buffer.scala 428:17] + buf_byteen_in[3] <= _T_3377 @[lsu_bus_buffer.scala 428:17] + node _T_3378 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 430:62] + node _T_3379 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3380 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 430:119] + node _T_3381 = and(_T_3379, _T_3380) @[lsu_bus_buffer.scala 430:108] + node _T_3382 = mux(_T_3381, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3383 = mux(_T_3378, ibuf_addr, _T_3382) @[lsu_bus_buffer.scala 430:44] + node _T_3384 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 430:62] + node _T_3385 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3386 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 430:119] + node _T_3387 = and(_T_3385, _T_3386) @[lsu_bus_buffer.scala 430:108] + node _T_3388 = mux(_T_3387, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3389 = mux(_T_3384, ibuf_addr, _T_3388) @[lsu_bus_buffer.scala 430:44] + node _T_3390 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 430:62] + node _T_3391 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3392 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 430:119] + node _T_3393 = and(_T_3391, _T_3392) @[lsu_bus_buffer.scala 430:108] + node _T_3394 = mux(_T_3393, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3395 = mux(_T_3390, ibuf_addr, _T_3394) @[lsu_bus_buffer.scala 430:44] + node _T_3396 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 430:62] + node _T_3397 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:91] + node _T_3398 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 430:119] + node _T_3399 = and(_T_3397, _T_3398) @[lsu_bus_buffer.scala 430:108] + node _T_3400 = mux(_T_3399, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 430:81] + node _T_3401 = mux(_T_3396, ibuf_addr, _T_3400) @[lsu_bus_buffer.scala 430:44] + buf_addr_in[0] <= _T_3383 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[1] <= _T_3389 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[2] <= _T_3395 @[lsu_bus_buffer.scala 430:15] + buf_addr_in[3] <= _T_3401 @[lsu_bus_buffer.scala 430:15] + node _T_3402 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 431:63] + node _T_3403 = mux(_T_3402, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3404 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 431:63] + node _T_3405 = mux(_T_3404, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3406 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 431:63] + node _T_3407 = mux(_T_3406, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3408 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 431:63] + node _T_3409 = mux(_T_3408, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:45] + node _T_3410 = cat(_T_3409, _T_3407) @[Cat.scala 29:58] + node _T_3411 = cat(_T_3410, _T_3405) @[Cat.scala 29:58] + node _T_3412 = cat(_T_3411, _T_3403) @[Cat.scala 29:58] + buf_dual_in <= _T_3412 @[lsu_bus_buffer.scala 431:15] + node _T_3413 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 432:65] + node _T_3414 = mux(_T_3413, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3415 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 432:65] + node _T_3416 = mux(_T_3415, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3417 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 432:65] + node _T_3418 = mux(_T_3417, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3419 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 432:65] + node _T_3420 = mux(_T_3419, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 432:47] + node _T_3421 = cat(_T_3420, _T_3418) @[Cat.scala 29:58] + node _T_3422 = cat(_T_3421, _T_3416) @[Cat.scala 29:58] + node _T_3423 = cat(_T_3422, _T_3414) @[Cat.scala 29:58] + buf_samedw_in <= _T_3423 @[lsu_bus_buffer.scala 432:17] + node _T_3424 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 433:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3427 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 433:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3430 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 433:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3433 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 433:66] + node _T_3434 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 433:84] + node _T_3435 = mux(_T_3433, _T_3434, io.no_dword_merge_r) @[lsu_bus_buffer.scala 433:48] + node _T_3436 = cat(_T_3435, _T_3432) @[Cat.scala 29:58] + node _T_3437 = cat(_T_3436, _T_3429) @[Cat.scala 29:58] + node _T_3438 = cat(_T_3437, _T_3426) @[Cat.scala 29:58] + buf_nomerge_in <= _T_3438 @[lsu_bus_buffer.scala 433:18] + node _T_3439 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 434:65] + node _T_3440 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3441 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 434:118] + node _T_3442 = and(_T_3440, _T_3441) @[lsu_bus_buffer.scala 434:107] + node _T_3443 = mux(_T_3439, ibuf_dual, _T_3442) @[lsu_bus_buffer.scala 434:47] + node _T_3444 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 434:65] + node _T_3445 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3446 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 434:118] + node _T_3447 = and(_T_3445, _T_3446) @[lsu_bus_buffer.scala 434:107] + node _T_3448 = mux(_T_3444, ibuf_dual, _T_3447) @[lsu_bus_buffer.scala 434:47] + node _T_3449 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 434:65] + node _T_3450 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3451 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 434:118] + node _T_3452 = and(_T_3450, _T_3451) @[lsu_bus_buffer.scala 434:107] + node _T_3453 = mux(_T_3449, ibuf_dual, _T_3452) @[lsu_bus_buffer.scala 434:47] + node _T_3454 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 434:65] + node _T_3455 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:90] + node _T_3456 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 434:118] + node _T_3457 = and(_T_3455, _T_3456) @[lsu_bus_buffer.scala 434:107] + node _T_3458 = mux(_T_3454, ibuf_dual, _T_3457) @[lsu_bus_buffer.scala 434:47] + node _T_3459 = cat(_T_3458, _T_3453) @[Cat.scala 29:58] + node _T_3460 = cat(_T_3459, _T_3448) @[Cat.scala 29:58] + node _T_3461 = cat(_T_3460, _T_3443) @[Cat.scala 29:58] + buf_dualhi_in <= _T_3461 @[lsu_bus_buffer.scala 434:17] + node _T_3462 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 435:65] + node _T_3463 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3464 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 435:125] + node _T_3465 = and(_T_3463, _T_3464) @[lsu_bus_buffer.scala 435:114] + node _T_3466 = mux(_T_3465, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3467 = mux(_T_3462, ibuf_dualtag, _T_3466) @[lsu_bus_buffer.scala 435:47] + node _T_3468 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 435:65] + node _T_3469 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3470 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 435:125] + node _T_3471 = and(_T_3469, _T_3470) @[lsu_bus_buffer.scala 435:114] + node _T_3472 = mux(_T_3471, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3473 = mux(_T_3468, ibuf_dualtag, _T_3472) @[lsu_bus_buffer.scala 435:47] + node _T_3474 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 435:65] + node _T_3475 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3476 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 435:125] + node _T_3477 = and(_T_3475, _T_3476) @[lsu_bus_buffer.scala 435:114] + node _T_3478 = mux(_T_3477, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3479 = mux(_T_3474, ibuf_dualtag, _T_3478) @[lsu_bus_buffer.scala 435:47] + node _T_3480 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 435:65] + node _T_3481 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:97] + node _T_3482 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 435:125] + node _T_3483 = and(_T_3481, _T_3482) @[lsu_bus_buffer.scala 435:114] + node _T_3484 = mux(_T_3483, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 435:87] + node _T_3485 = mux(_T_3480, ibuf_dualtag, _T_3484) @[lsu_bus_buffer.scala 435:47] + buf_dualtag_in[0] <= _T_3467 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[1] <= _T_3473 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[2] <= _T_3479 @[lsu_bus_buffer.scala 435:18] + buf_dualtag_in[3] <= _T_3485 @[lsu_bus_buffer.scala 435:18] + node _T_3486 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 436:69] + node _T_3487 = mux(_T_3486, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3488 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 436:69] + node _T_3489 = mux(_T_3488, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3490 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 436:69] + node _T_3491 = mux(_T_3490, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3492 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 436:69] + node _T_3493 = mux(_T_3492, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 436:51] + node _T_3494 = cat(_T_3493, _T_3491) @[Cat.scala 29:58] + node _T_3495 = cat(_T_3494, _T_3489) @[Cat.scala 29:58] + node _T_3496 = cat(_T_3495, _T_3487) @[Cat.scala 29:58] + buf_sideeffect_in <= _T_3496 @[lsu_bus_buffer.scala 436:21] + node _T_3497 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 437:65] + node _T_3498 = mux(_T_3497, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3499 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 437:65] + node _T_3500 = mux(_T_3499, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3501 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 437:65] + node _T_3502 = mux(_T_3501, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3503 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 437:65] + node _T_3504 = mux(_T_3503, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 437:47] + node _T_3505 = cat(_T_3504, _T_3502) @[Cat.scala 29:58] + node _T_3506 = cat(_T_3505, _T_3500) @[Cat.scala 29:58] + node _T_3507 = cat(_T_3506, _T_3498) @[Cat.scala 29:58] + buf_unsign_in <= _T_3507 @[lsu_bus_buffer.scala 437:17] + node _T_3508 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 438:60] + node _T_3509 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[lsu_bus_buffer.scala 438:42] + node _T_3511 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 438:60] + node _T_3512 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[lsu_bus_buffer.scala 438:42] + node _T_3514 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 438:60] + node _T_3515 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[lsu_bus_buffer.scala 438:42] + node _T_3517 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 438:60] + node _T_3518 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3519 = mux(_T_3517, ibuf_sz, _T_3518) @[lsu_bus_buffer.scala 438:42] + buf_sz_in[0] <= _T_3510 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[1] <= _T_3513 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[2] <= _T_3516 @[lsu_bus_buffer.scala 438:13] + buf_sz_in[3] <= _T_3519 @[lsu_bus_buffer.scala 438:13] + node _T_3520 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 439:64] + node _T_3521 = mux(_T_3520, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3522 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 439:64] + node _T_3523 = mux(_T_3522, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3524 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 439:64] + node _T_3525 = mux(_T_3524, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3526 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 439:64] + node _T_3527 = mux(_T_3526, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 439:46] + node _T_3528 = cat(_T_3527, _T_3525) @[Cat.scala 29:58] + node _T_3529 = cat(_T_3528, _T_3523) @[Cat.scala 29:58] + node _T_3530 = cat(_T_3529, _T_3521) @[Cat.scala 29:58] + buf_write_in <= _T_3530 @[lsu_bus_buffer.scala 439:16] + node _T_3531 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3531 : @[Conditional.scala 40:58] + node _T_3532 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3533 = mux(_T_3532, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[0] <= _T_3533 @[lsu_bus_buffer.scala 444:25] + node _T_3534 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3535 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3536 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3537 = and(_T_3535, _T_3536) @[lsu_bus_buffer.scala 445:95] + node _T_3538 = eq(UInt<1>("h00"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3539 = and(_T_3537, _T_3538) @[lsu_bus_buffer.scala 445:112] + node _T_3540 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3541 = eq(UInt<1>("h00"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3542 = and(_T_3540, _T_3541) @[lsu_bus_buffer.scala 445:161] + node _T_3543 = or(_T_3539, _T_3542) @[lsu_bus_buffer.scala 445:132] + node _T_3544 = and(_T_3534, _T_3543) @[lsu_bus_buffer.scala 445:63] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[lsu_bus_buffer.scala 445:201] + node _T_3547 = or(_T_3544, _T_3546) @[lsu_bus_buffer.scala 445:183] + buf_state_en[0] <= _T_3547 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 446:22] + buf_data_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 447:24] + node _T_3548 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3549 = and(ibuf_drain_vld, _T_3548) @[lsu_bus_buffer.scala 448:47] + node _T_3550 = bits(_T_3549, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3551 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3552 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3553 = mux(_T_3550, _T_3551, _T_3552) @[lsu_bus_buffer.scala 448:30] + buf_data_in[0] <= _T_3553 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3554 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3554 : @[Conditional.scala 39:67] + node _T_3555 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3556 = mux(_T_3555, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[0] <= _T_3556 @[lsu_bus_buffer.scala 453:25] + node _T_3557 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[0] <= _T_3557 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3558 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3558 : @[Conditional.scala 39:67] + node _T_3559 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3560 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3561 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3562 = and(_T_3560, _T_3561) @[lsu_bus_buffer.scala 459:104] + node _T_3563 = mux(_T_3562, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3564 = mux(_T_3559, UInt<3>("h00"), _T_3563) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[0] <= _T_3564 @[lsu_bus_buffer.scala 459:25] + node _T_3565 = eq(obuf_tag0, UInt<3>("h00")) @[lsu_bus_buffer.scala 460:48] + node _T_3566 = eq(obuf_tag1, UInt<3>("h00")) @[lsu_bus_buffer.scala 460:104] + node _T_3567 = and(obuf_merge, _T_3566) @[lsu_bus_buffer.scala 460:91] + node _T_3568 = or(_T_3565, _T_3567) @[lsu_bus_buffer.scala 460:77] + node _T_3569 = and(_T_3568, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3570 = and(_T_3569, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[0] <= _T_3570 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[lsu_bus_buffer.scala 461:29] + node _T_3571 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3572 = or(_T_3571, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[0] <= _T_3572 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3573 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 464:56] + node _T_3574 = eq(_T_3573, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3575 = and(buf_state_en[0], _T_3574) @[lsu_bus_buffer.scala 464:44] + node _T_3576 = and(_T_3575, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3577 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3578 = and(_T_3576, _T_3577) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[0] <= _T_3578 @[lsu_bus_buffer.scala 464:25] + node _T_3579 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[0] <= _T_3579 @[lsu_bus_buffer.scala 465:28] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3581 = and(_T_3580, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3582 = and(_T_3581, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[0] <= _T_3582 @[lsu_bus_buffer.scala 466:24] + node _T_3583 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3584 = and(_T_3583, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3585 = and(_T_3584, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[0] <= _T_3585 @[lsu_bus_buffer.scala 467:25] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3587 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3588 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3589 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3590 = mux(_T_3587, _T_3588, _T_3589) @[lsu_bus_buffer.scala 468:73] + node _T_3591 = mux(buf_error_en[0], _T_3586, _T_3590) @[lsu_bus_buffer.scala 468:30] + buf_data_in[0] <= _T_3591 @[lsu_bus_buffer.scala 468:24] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3592 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3592 : @[Conditional.scala 39:67] + node _T_3593 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 472:69] + node _T_3594 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3595 = and(_T_3593, _T_3594) @[lsu_bus_buffer.scala 472:73] + node _T_3596 = or(io.dec_tlu_force_halt, _T_3595) @[lsu_bus_buffer.scala 472:57] + node _T_3597 = bits(_T_3596, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3598 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3599 = and(buf_dual[0], _T_3598) @[lsu_bus_buffer.scala 473:28] + node _T_3600 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 473:57] + node _T_3601 = eq(_T_3600, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3602 = and(_T_3599, _T_3601) @[lsu_bus_buffer.scala 473:45] + node _T_3603 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3604 = and(_T_3602, _T_3603) @[lsu_bus_buffer.scala 473:61] + node _T_3605 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 474:27] + node _T_3606 = or(_T_3605, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3607 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3608 = and(buf_dual[0], _T_3607) @[lsu_bus_buffer.scala 474:68] + node _T_3609 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 474:97] + node _T_3610 = eq(_T_3609, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3611 = and(_T_3608, _T_3610) @[lsu_bus_buffer.scala 474:85] + node _T_3612 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3613 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3614 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3615 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3616 = eq(buf_dualtag[0], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3617 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_3618 = eq(buf_dualtag[0], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_3619 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_3620 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3621 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3622 = mux(_T_3616, _T_3617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3623 = mux(_T_3618, _T_3619, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3624 = or(_T_3620, _T_3621) @[Mux.scala 27:72] + node _T_3625 = or(_T_3624, _T_3622) @[Mux.scala 27:72] + node _T_3626 = or(_T_3625, _T_3623) @[Mux.scala 27:72] + wire _T_3627 : UInt<1> @[Mux.scala 27:72] + _T_3627 <= _T_3626 @[Mux.scala 27:72] + node _T_3628 = and(_T_3611, _T_3627) @[lsu_bus_buffer.scala 474:101] + node _T_3629 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_3630 = and(_T_3628, _T_3629) @[lsu_bus_buffer.scala 474:138] + node _T_3631 = and(_T_3630, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_3632 = or(_T_3606, _T_3631) @[lsu_bus_buffer.scala 474:53] + node _T_3633 = mux(_T_3632, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_3634 = mux(_T_3604, UInt<3>("h04"), _T_3633) @[lsu_bus_buffer.scala 473:14] + node _T_3635 = mux(_T_3597, UInt<3>("h00"), _T_3634) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[0] <= _T_3635 @[lsu_bus_buffer.scala 472:27] + node _T_3636 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 475:73] + node _T_3637 = and(bus_rsp_write, _T_3636) @[lsu_bus_buffer.scala 475:52] + node _T_3638 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 476:46] + node _T_3639 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 477:23] + node _T_3640 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 477:47] + node _T_3641 = and(_T_3639, _T_3640) @[lsu_bus_buffer.scala 477:27] + node _T_3642 = or(_T_3638, _T_3641) @[lsu_bus_buffer.scala 476:77] + node _T_3643 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 478:26] + node _T_3644 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 478:54] + node _T_3645 = not(_T_3644) @[lsu_bus_buffer.scala 478:44] + node _T_3646 = and(_T_3643, _T_3645) @[lsu_bus_buffer.scala 478:42] + node _T_3647 = and(_T_3646, buf_samedw[0]) @[lsu_bus_buffer.scala 478:58] + node _T_3648 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 478:94] + node _T_3649 = and(_T_3647, _T_3648) @[lsu_bus_buffer.scala 478:74] + node _T_3650 = or(_T_3642, _T_3649) @[lsu_bus_buffer.scala 477:71] + node _T_3651 = and(bus_rsp_read, _T_3650) @[lsu_bus_buffer.scala 476:25] + node _T_3652 = or(_T_3637, _T_3651) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[0] <= _T_3652 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[lsu_bus_buffer.scala 479:29] + node _T_3653 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_3654 = or(_T_3653, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[0] <= _T_3654 @[lsu_bus_buffer.scala 480:25] + node _T_3655 = and(buf_state_bus_en[0], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_3656 = and(_T_3655, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[0] <= _T_3656 @[lsu_bus_buffer.scala 481:24] + node _T_3657 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_3658 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 482:111] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[lsu_bus_buffer.scala 482:91] + node _T_3660 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 483:42] + node _T_3661 = and(bus_rsp_read_error, _T_3660) @[lsu_bus_buffer.scala 483:31] + node _T_3662 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 483:66] + node _T_3663 = and(_T_3661, _T_3662) @[lsu_bus_buffer.scala 483:46] + node _T_3664 = or(_T_3659, _T_3663) @[lsu_bus_buffer.scala 482:143] + node _T_3665 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 484:54] + node _T_3666 = and(bus_rsp_write_error, _T_3665) @[lsu_bus_buffer.scala 484:33] + node _T_3667 = or(_T_3664, _T_3666) @[lsu_bus_buffer.scala 483:88] + node _T_3668 = and(_T_3657, _T_3667) @[lsu_bus_buffer.scala 482:68] + buf_error_en[0] <= _T_3668 @[lsu_bus_buffer.scala 482:25] + node _T_3669 = eq(buf_error_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_3670 = and(buf_state_en[0], _T_3669) @[lsu_bus_buffer.scala 485:48] + node _T_3671 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_3672 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_3673 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_3674 = mux(_T_3671, _T_3672, _T_3673) @[lsu_bus_buffer.scala 485:72] + node _T_3675 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_3676 = mux(_T_3670, _T_3674, _T_3675) @[lsu_bus_buffer.scala 485:30] + buf_data_in[0] <= _T_3676 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3677 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3677 : @[Conditional.scala 39:67] + node _T_3678 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_3679 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 490:86] + node _T_3680 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 490:101] + node _T_3681 = bits(_T_3680, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_3682 = or(_T_3679, _T_3681) @[lsu_bus_buffer.scala 490:90] + node _T_3683 = or(_T_3682, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_3684 = mux(_T_3683, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_3685 = mux(_T_3678, UInt<3>("h00"), _T_3684) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[0] <= _T_3685 @[lsu_bus_buffer.scala 490:25] + node _T_3686 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 491:66] + node _T_3687 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 492:21] + node _T_3688 = bits(_T_3687, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_3689 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[lsu_bus_buffer.scala 492:58] + node _T_3690 = and(_T_3688, _T_3689) @[lsu_bus_buffer.scala 492:38] + node _T_3691 = or(_T_3686, _T_3690) @[lsu_bus_buffer.scala 491:95] + node _T_3692 = and(bus_rsp_read, _T_3691) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[0] <= _T_3692 @[lsu_bus_buffer.scala 491:29] + node _T_3693 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_3694 = or(_T_3693, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[0] <= _T_3694 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3695 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3695 : @[Conditional.scala 39:67] + node _T_3696 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_3697 = mux(_T_3696, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[0] <= _T_3697 @[lsu_bus_buffer.scala 498:25] + node _T_3698 = eq(RspPtr, UInt<2>("h00")) @[lsu_bus_buffer.scala 499:37] + node _T_3699 = eq(buf_dualtag[0], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_3700 = and(buf_dual[0], _T_3699) @[lsu_bus_buffer.scala 499:80] + node _T_3701 = or(_T_3698, _T_3700) @[lsu_bus_buffer.scala 499:65] + node _T_3702 = or(_T_3701, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[0] <= _T_3702 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3703 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3703 : @[Conditional.scala 39:67] + buf_nxtstate[0] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_3704 = bits(buf_state_en[0], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3704 : @[Reg.scala 28:19] + _T_3705 <= buf_nxtstate[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[0] <= _T_3705 @[lsu_bus_buffer.scala 512:18] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_3706 <= buf_age_in_0 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[0] <= _T_3706 @[lsu_bus_buffer.scala 513:17] + reg _T_3707 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_3707 <= buf_rspage_in[0] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[0] <= _T_3707 @[lsu_bus_buffer.scala 514:20] + node _T_3708 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_3709 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3708 : @[Reg.scala 28:19] + _T_3709 <= buf_dualtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[0] <= _T_3709 @[lsu_bus_buffer.scala 515:20] + node _T_3710 = bits(buf_dual_in, 0, 0) @[lsu_bus_buffer.scala 516:74] + node _T_3711 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_3712 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3711 : @[Reg.scala 28:19] + _T_3712 <= _T_3710 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[0] <= _T_3712 @[lsu_bus_buffer.scala 516:17] + node _T_3713 = bits(buf_samedw_in, 0, 0) @[lsu_bus_buffer.scala 517:78] + node _T_3714 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_3715 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3714 : @[Reg.scala 28:19] + _T_3715 <= _T_3713 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[0] <= _T_3715 @[lsu_bus_buffer.scala 517:19] + node _T_3716 = bits(buf_nomerge_in, 0, 0) @[lsu_bus_buffer.scala 518:80] + node _T_3717 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_3718 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3717 : @[Reg.scala 28:19] + _T_3718 <= _T_3716 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[0] <= _T_3718 @[lsu_bus_buffer.scala 518:20] + node _T_3719 = bits(buf_dualhi_in, 0, 0) @[lsu_bus_buffer.scala 519:78] + node _T_3720 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_3721 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3720 : @[Reg.scala 28:19] + _T_3721 <= _T_3719 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[0] <= _T_3721 @[lsu_bus_buffer.scala 519:19] + node _T_3722 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3722 : @[Conditional.scala 40:58] + node _T_3723 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3724 = mux(_T_3723, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[1] <= _T_3724 @[lsu_bus_buffer.scala 444:25] + node _T_3725 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3726 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3727 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3728 = and(_T_3726, _T_3727) @[lsu_bus_buffer.scala 445:95] + node _T_3729 = eq(UInt<1>("h01"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3730 = and(_T_3728, _T_3729) @[lsu_bus_buffer.scala 445:112] + node _T_3731 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3732 = eq(UInt<1>("h01"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3733 = and(_T_3731, _T_3732) @[lsu_bus_buffer.scala 445:161] + node _T_3734 = or(_T_3730, _T_3733) @[lsu_bus_buffer.scala 445:132] + node _T_3735 = and(_T_3725, _T_3734) @[lsu_bus_buffer.scala 445:63] + node _T_3736 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3737 = and(ibuf_drain_vld, _T_3736) @[lsu_bus_buffer.scala 445:201] + node _T_3738 = or(_T_3735, _T_3737) @[lsu_bus_buffer.scala 445:183] + buf_state_en[1] <= _T_3738 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 446:22] + buf_data_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 447:24] + node _T_3739 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3740 = and(ibuf_drain_vld, _T_3739) @[lsu_bus_buffer.scala 448:47] + node _T_3741 = bits(_T_3740, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3742 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3743 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3744 = mux(_T_3741, _T_3742, _T_3743) @[lsu_bus_buffer.scala 448:30] + buf_data_in[1] <= _T_3744 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3745 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3745 : @[Conditional.scala 39:67] + node _T_3746 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3747 = mux(_T_3746, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[1] <= _T_3747 @[lsu_bus_buffer.scala 453:25] + node _T_3748 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[1] <= _T_3748 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3749 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3749 : @[Conditional.scala 39:67] + node _T_3750 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3751 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3752 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3753 = and(_T_3751, _T_3752) @[lsu_bus_buffer.scala 459:104] + node _T_3754 = mux(_T_3753, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3755 = mux(_T_3750, UInt<3>("h00"), _T_3754) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[1] <= _T_3755 @[lsu_bus_buffer.scala 459:25] + node _T_3756 = eq(obuf_tag0, UInt<3>("h01")) @[lsu_bus_buffer.scala 460:48] + node _T_3757 = eq(obuf_tag1, UInt<3>("h01")) @[lsu_bus_buffer.scala 460:104] + node _T_3758 = and(obuf_merge, _T_3757) @[lsu_bus_buffer.scala 460:91] + node _T_3759 = or(_T_3756, _T_3758) @[lsu_bus_buffer.scala 460:77] + node _T_3760 = and(_T_3759, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3761 = and(_T_3760, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[1] <= _T_3761 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[lsu_bus_buffer.scala 461:29] + node _T_3762 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3763 = or(_T_3762, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[1] <= _T_3763 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3764 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 464:56] + node _T_3765 = eq(_T_3764, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3766 = and(buf_state_en[1], _T_3765) @[lsu_bus_buffer.scala 464:44] + node _T_3767 = and(_T_3766, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3768 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3769 = and(_T_3767, _T_3768) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[1] <= _T_3769 @[lsu_bus_buffer.scala 464:25] + node _T_3770 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[1] <= _T_3770 @[lsu_bus_buffer.scala 465:28] + node _T_3771 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3772 = and(_T_3771, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3773 = and(_T_3772, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[1] <= _T_3773 @[lsu_bus_buffer.scala 466:24] + node _T_3774 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3775 = and(_T_3774, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3776 = and(_T_3775, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[1] <= _T_3776 @[lsu_bus_buffer.scala 467:25] + node _T_3777 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3778 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3779 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3780 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3781 = mux(_T_3778, _T_3779, _T_3780) @[lsu_bus_buffer.scala 468:73] + node _T_3782 = mux(buf_error_en[1], _T_3777, _T_3781) @[lsu_bus_buffer.scala 468:30] + buf_data_in[1] <= _T_3782 @[lsu_bus_buffer.scala 468:24] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3783 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3783 : @[Conditional.scala 39:67] + node _T_3784 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 472:69] + node _T_3785 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3786 = and(_T_3784, _T_3785) @[lsu_bus_buffer.scala 472:73] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[lsu_bus_buffer.scala 472:57] + node _T_3788 = bits(_T_3787, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[lsu_bus_buffer.scala 473:28] + node _T_3791 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 473:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3793 = and(_T_3790, _T_3792) @[lsu_bus_buffer.scala 473:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3795 = and(_T_3793, _T_3794) @[lsu_bus_buffer.scala 473:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 474:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[lsu_bus_buffer.scala 474:68] + node _T_3800 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 474:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3802 = and(_T_3799, _T_3801) @[lsu_bus_buffer.scala 474:85] + node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3804 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3806 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3808 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_3810 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3814 = mux(_T_3809, _T_3810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3815 = or(_T_3811, _T_3812) @[Mux.scala 27:72] + node _T_3816 = or(_T_3815, _T_3813) @[Mux.scala 27:72] + node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] + wire _T_3818 : UInt<1> @[Mux.scala 27:72] + _T_3818 <= _T_3817 @[Mux.scala 27:72] + node _T_3819 = and(_T_3802, _T_3818) @[lsu_bus_buffer.scala 474:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_3821 = and(_T_3819, _T_3820) @[lsu_bus_buffer.scala 474:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_3823 = or(_T_3797, _T_3822) @[lsu_bus_buffer.scala 474:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[lsu_bus_buffer.scala 473:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[1] <= _T_3826 @[lsu_bus_buffer.scala 472:27] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 475:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[lsu_bus_buffer.scala 475:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 476:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 477:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 477:47] + node _T_3832 = and(_T_3830, _T_3831) @[lsu_bus_buffer.scala 477:27] + node _T_3833 = or(_T_3829, _T_3832) @[lsu_bus_buffer.scala 476:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 478:26] + node _T_3835 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 478:54] + node _T_3836 = not(_T_3835) @[lsu_bus_buffer.scala 478:44] + node _T_3837 = and(_T_3834, _T_3836) @[lsu_bus_buffer.scala 478:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[lsu_bus_buffer.scala 478:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 478:94] + node _T_3840 = and(_T_3838, _T_3839) @[lsu_bus_buffer.scala 478:74] + node _T_3841 = or(_T_3833, _T_3840) @[lsu_bus_buffer.scala 477:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[lsu_bus_buffer.scala 476:25] + node _T_3843 = or(_T_3828, _T_3842) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[1] <= _T_3843 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[lsu_bus_buffer.scala 479:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[1] <= _T_3845 @[lsu_bus_buffer.scala 480:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[1] <= _T_3847 @[lsu_bus_buffer.scala 481:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 482:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[lsu_bus_buffer.scala 482:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 483:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[lsu_bus_buffer.scala 483:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 483:66] + node _T_3854 = and(_T_3852, _T_3853) @[lsu_bus_buffer.scala 483:46] + node _T_3855 = or(_T_3850, _T_3854) @[lsu_bus_buffer.scala 482:143] + node _T_3856 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 484:54] + node _T_3857 = and(bus_rsp_write_error, _T_3856) @[lsu_bus_buffer.scala 484:33] + node _T_3858 = or(_T_3855, _T_3857) @[lsu_bus_buffer.scala 483:88] + node _T_3859 = and(_T_3848, _T_3858) @[lsu_bus_buffer.scala 482:68] + buf_error_en[1] <= _T_3859 @[lsu_bus_buffer.scala 482:25] + node _T_3860 = eq(buf_error_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_3861 = and(buf_state_en[1], _T_3860) @[lsu_bus_buffer.scala 485:48] + node _T_3862 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_3863 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_3864 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_3865 = mux(_T_3862, _T_3863, _T_3864) @[lsu_bus_buffer.scala 485:72] + node _T_3866 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_3867 = mux(_T_3861, _T_3865, _T_3866) @[lsu_bus_buffer.scala 485:30] + buf_data_in[1] <= _T_3867 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3868 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3868 : @[Conditional.scala 39:67] + node _T_3869 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_3870 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 490:86] + node _T_3871 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 490:101] + node _T_3872 = bits(_T_3871, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_3873 = or(_T_3870, _T_3872) @[lsu_bus_buffer.scala 490:90] + node _T_3874 = or(_T_3873, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_3875 = mux(_T_3874, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_3876 = mux(_T_3869, UInt<3>("h00"), _T_3875) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[1] <= _T_3876 @[lsu_bus_buffer.scala 490:25] + node _T_3877 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 491:66] + node _T_3878 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 492:21] + node _T_3879 = bits(_T_3878, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_3880 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[lsu_bus_buffer.scala 492:58] + node _T_3881 = and(_T_3879, _T_3880) @[lsu_bus_buffer.scala 492:38] + node _T_3882 = or(_T_3877, _T_3881) @[lsu_bus_buffer.scala 491:95] + node _T_3883 = and(bus_rsp_read, _T_3882) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[1] <= _T_3883 @[lsu_bus_buffer.scala 491:29] + node _T_3884 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_3885 = or(_T_3884, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[1] <= _T_3885 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3886 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3886 : @[Conditional.scala 39:67] + node _T_3887 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_3888 = mux(_T_3887, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[1] <= _T_3888 @[lsu_bus_buffer.scala 498:25] + node _T_3889 = eq(RspPtr, UInt<2>("h01")) @[lsu_bus_buffer.scala 499:37] + node _T_3890 = eq(buf_dualtag[1], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_3891 = and(buf_dual[1], _T_3890) @[lsu_bus_buffer.scala 499:80] + node _T_3892 = or(_T_3889, _T_3891) @[lsu_bus_buffer.scala 499:65] + node _T_3893 = or(_T_3892, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[1] <= _T_3893 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3894 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3894 : @[Conditional.scala 39:67] + buf_nxtstate[1] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_3895 = bits(buf_state_en[1], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_3896 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3895 : @[Reg.scala 28:19] + _T_3896 <= buf_nxtstate[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[1] <= _T_3896 @[lsu_bus_buffer.scala 512:18] + reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_3897 <= buf_age_in_1 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[1] <= _T_3897 @[lsu_bus_buffer.scala 513:17] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_3898 <= buf_rspage_in[1] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[1] <= _T_3898 @[lsu_bus_buffer.scala 514:20] + node _T_3899 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_3900 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3899 : @[Reg.scala 28:19] + _T_3900 <= buf_dualtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[1] <= _T_3900 @[lsu_bus_buffer.scala 515:20] + node _T_3901 = bits(buf_dual_in, 1, 1) @[lsu_bus_buffer.scala 516:74] + node _T_3902 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_3903 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3902 : @[Reg.scala 28:19] + _T_3903 <= _T_3901 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[1] <= _T_3903 @[lsu_bus_buffer.scala 516:17] + node _T_3904 = bits(buf_samedw_in, 1, 1) @[lsu_bus_buffer.scala 517:78] + node _T_3905 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_3906 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3905 : @[Reg.scala 28:19] + _T_3906 <= _T_3904 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[1] <= _T_3906 @[lsu_bus_buffer.scala 517:19] + node _T_3907 = bits(buf_nomerge_in, 1, 1) @[lsu_bus_buffer.scala 518:80] + node _T_3908 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_3909 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3908 : @[Reg.scala 28:19] + _T_3909 <= _T_3907 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[1] <= _T_3909 @[lsu_bus_buffer.scala 518:20] + node _T_3910 = bits(buf_dualhi_in, 1, 1) @[lsu_bus_buffer.scala 519:78] + node _T_3911 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_3912 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3911 : @[Reg.scala 28:19] + _T_3912 <= _T_3910 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[1] <= _T_3912 @[lsu_bus_buffer.scala 519:19] + node _T_3913 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3913 : @[Conditional.scala 40:58] + node _T_3914 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_3915 = mux(_T_3914, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[2] <= _T_3915 @[lsu_bus_buffer.scala 444:25] + node _T_3916 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_3917 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_3918 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_3919 = and(_T_3917, _T_3918) @[lsu_bus_buffer.scala 445:95] + node _T_3920 = eq(UInt<2>("h02"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_3921 = and(_T_3919, _T_3920) @[lsu_bus_buffer.scala 445:112] + node _T_3922 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_3923 = eq(UInt<2>("h02"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_3924 = and(_T_3922, _T_3923) @[lsu_bus_buffer.scala 445:161] + node _T_3925 = or(_T_3921, _T_3924) @[lsu_bus_buffer.scala 445:132] + node _T_3926 = and(_T_3916, _T_3925) @[lsu_bus_buffer.scala 445:63] + node _T_3927 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_3928 = and(ibuf_drain_vld, _T_3927) @[lsu_bus_buffer.scala 445:201] + node _T_3929 = or(_T_3926, _T_3928) @[lsu_bus_buffer.scala 445:183] + buf_state_en[2] <= _T_3929 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 446:22] + buf_data_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 447:24] + node _T_3930 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_3931 = and(ibuf_drain_vld, _T_3930) @[lsu_bus_buffer.scala 448:47] + node _T_3932 = bits(_T_3931, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_3933 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_3934 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_3935 = mux(_T_3932, _T_3933, _T_3934) @[lsu_bus_buffer.scala 448:30] + buf_data_in[2] <= _T_3935 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3936 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3936 : @[Conditional.scala 39:67] + node _T_3937 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3938 = mux(_T_3937, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[2] <= _T_3938 @[lsu_bus_buffer.scala 453:25] + node _T_3939 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[2] <= _T_3939 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3940 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3940 : @[Conditional.scala 39:67] + node _T_3941 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_3942 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_3943 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_3944 = and(_T_3942, _T_3943) @[lsu_bus_buffer.scala 459:104] + node _T_3945 = mux(_T_3944, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_3946 = mux(_T_3941, UInt<3>("h00"), _T_3945) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[2] <= _T_3946 @[lsu_bus_buffer.scala 459:25] + node _T_3947 = eq(obuf_tag0, UInt<3>("h02")) @[lsu_bus_buffer.scala 460:48] + node _T_3948 = eq(obuf_tag1, UInt<3>("h02")) @[lsu_bus_buffer.scala 460:104] + node _T_3949 = and(obuf_merge, _T_3948) @[lsu_bus_buffer.scala 460:91] + node _T_3950 = or(_T_3947, _T_3949) @[lsu_bus_buffer.scala 460:77] + node _T_3951 = and(_T_3950, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_3952 = and(_T_3951, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[2] <= _T_3952 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[lsu_bus_buffer.scala 461:29] + node _T_3953 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_3954 = or(_T_3953, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[2] <= _T_3954 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_3955 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 464:56] + node _T_3956 = eq(_T_3955, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_3957 = and(buf_state_en[2], _T_3956) @[lsu_bus_buffer.scala 464:44] + node _T_3958 = and(_T_3957, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_3959 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_3960 = and(_T_3958, _T_3959) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[2] <= _T_3960 @[lsu_bus_buffer.scala 464:25] + node _T_3961 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[2] <= _T_3961 @[lsu_bus_buffer.scala 465:28] + node _T_3962 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_3963 = and(_T_3962, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_3964 = and(_T_3963, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[2] <= _T_3964 @[lsu_bus_buffer.scala 466:24] + node _T_3965 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_3966 = and(_T_3965, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_3967 = and(_T_3966, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[2] <= _T_3967 @[lsu_bus_buffer.scala 467:25] + node _T_3968 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_3969 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_3970 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_3971 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_3972 = mux(_T_3969, _T_3970, _T_3971) @[lsu_bus_buffer.scala 468:73] + node _T_3973 = mux(buf_error_en[2], _T_3968, _T_3972) @[lsu_bus_buffer.scala 468:30] + buf_data_in[2] <= _T_3973 @[lsu_bus_buffer.scala 468:24] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3974 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3974 : @[Conditional.scala 39:67] + node _T_3975 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 472:69] + node _T_3976 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_3977 = and(_T_3975, _T_3976) @[lsu_bus_buffer.scala 472:73] + node _T_3978 = or(io.dec_tlu_force_halt, _T_3977) @[lsu_bus_buffer.scala 472:57] + node _T_3979 = bits(_T_3978, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_3980 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_3981 = and(buf_dual[2], _T_3980) @[lsu_bus_buffer.scala 473:28] + node _T_3982 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 473:57] + node _T_3983 = eq(_T_3982, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_3984 = and(_T_3981, _T_3983) @[lsu_bus_buffer.scala 473:45] + node _T_3985 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_3986 = and(_T_3984, _T_3985) @[lsu_bus_buffer.scala 473:61] + node _T_3987 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 474:27] + node _T_3988 = or(_T_3987, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_3989 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_3990 = and(buf_dual[2], _T_3989) @[lsu_bus_buffer.scala 474:68] + node _T_3991 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 474:97] + node _T_3992 = eq(_T_3991, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_3993 = and(_T_3990, _T_3992) @[lsu_bus_buffer.scala 474:85] + node _T_3994 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_3995 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_3996 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_3997 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_3998 = eq(buf_dualtag[2], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_3999 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4000 = eq(buf_dualtag[2], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4001 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4002 = mux(_T_3994, _T_3995, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4003 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4004 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4005 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4006 = or(_T_4002, _T_4003) @[Mux.scala 27:72] + node _T_4007 = or(_T_4006, _T_4004) @[Mux.scala 27:72] + node _T_4008 = or(_T_4007, _T_4005) @[Mux.scala 27:72] + wire _T_4009 : UInt<1> @[Mux.scala 27:72] + _T_4009 <= _T_4008 @[Mux.scala 27:72] + node _T_4010 = and(_T_3993, _T_4009) @[lsu_bus_buffer.scala 474:101] + node _T_4011 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_4012 = and(_T_4010, _T_4011) @[lsu_bus_buffer.scala 474:138] + node _T_4013 = and(_T_4012, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_4014 = or(_T_3988, _T_4013) @[lsu_bus_buffer.scala 474:53] + node _T_4015 = mux(_T_4014, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_4016 = mux(_T_3986, UInt<3>("h04"), _T_4015) @[lsu_bus_buffer.scala 473:14] + node _T_4017 = mux(_T_3979, UInt<3>("h00"), _T_4016) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[2] <= _T_4017 @[lsu_bus_buffer.scala 472:27] + node _T_4018 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 475:73] + node _T_4019 = and(bus_rsp_write, _T_4018) @[lsu_bus_buffer.scala 475:52] + node _T_4020 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 476:46] + node _T_4021 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 477:23] + node _T_4022 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 477:47] + node _T_4023 = and(_T_4021, _T_4022) @[lsu_bus_buffer.scala 477:27] + node _T_4024 = or(_T_4020, _T_4023) @[lsu_bus_buffer.scala 476:77] + node _T_4025 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 478:26] + node _T_4026 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 478:54] + node _T_4027 = not(_T_4026) @[lsu_bus_buffer.scala 478:44] + node _T_4028 = and(_T_4025, _T_4027) @[lsu_bus_buffer.scala 478:42] + node _T_4029 = and(_T_4028, buf_samedw[2]) @[lsu_bus_buffer.scala 478:58] + node _T_4030 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 478:94] + node _T_4031 = and(_T_4029, _T_4030) @[lsu_bus_buffer.scala 478:74] + node _T_4032 = or(_T_4024, _T_4031) @[lsu_bus_buffer.scala 477:71] + node _T_4033 = and(bus_rsp_read, _T_4032) @[lsu_bus_buffer.scala 476:25] + node _T_4034 = or(_T_4019, _T_4033) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[2] <= _T_4034 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[lsu_bus_buffer.scala 479:29] + node _T_4035 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_4036 = or(_T_4035, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[2] <= _T_4036 @[lsu_bus_buffer.scala 480:25] + node _T_4037 = and(buf_state_bus_en[2], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_4038 = and(_T_4037, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[2] <= _T_4038 @[lsu_bus_buffer.scala 481:24] + node _T_4039 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_4040 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 482:111] + node _T_4041 = and(bus_rsp_read_error, _T_4040) @[lsu_bus_buffer.scala 482:91] + node _T_4042 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 483:42] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[lsu_bus_buffer.scala 483:31] + node _T_4044 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 483:66] + node _T_4045 = and(_T_4043, _T_4044) @[lsu_bus_buffer.scala 483:46] + node _T_4046 = or(_T_4041, _T_4045) @[lsu_bus_buffer.scala 482:143] + node _T_4047 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 484:54] + node _T_4048 = and(bus_rsp_write_error, _T_4047) @[lsu_bus_buffer.scala 484:33] + node _T_4049 = or(_T_4046, _T_4048) @[lsu_bus_buffer.scala 483:88] + node _T_4050 = and(_T_4039, _T_4049) @[lsu_bus_buffer.scala 482:68] + buf_error_en[2] <= _T_4050 @[lsu_bus_buffer.scala 482:25] + node _T_4051 = eq(buf_error_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_4052 = and(buf_state_en[2], _T_4051) @[lsu_bus_buffer.scala 485:48] + node _T_4053 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_4054 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_4055 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_4056 = mux(_T_4053, _T_4054, _T_4055) @[lsu_bus_buffer.scala 485:72] + node _T_4057 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_4058 = mux(_T_4052, _T_4056, _T_4057) @[lsu_bus_buffer.scala 485:30] + buf_data_in[2] <= _T_4058 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4059 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4059 : @[Conditional.scala 39:67] + node _T_4060 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_4061 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 490:86] + node _T_4062 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 490:101] + node _T_4063 = bits(_T_4062, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_4064 = or(_T_4061, _T_4063) @[lsu_bus_buffer.scala 490:90] + node _T_4065 = or(_T_4064, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_4066 = mux(_T_4065, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_4067 = mux(_T_4060, UInt<3>("h00"), _T_4066) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[2] <= _T_4067 @[lsu_bus_buffer.scala 490:25] + node _T_4068 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 491:66] + node _T_4069 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 492:21] + node _T_4070 = bits(_T_4069, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_4071 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[lsu_bus_buffer.scala 492:58] + node _T_4072 = and(_T_4070, _T_4071) @[lsu_bus_buffer.scala 492:38] + node _T_4073 = or(_T_4068, _T_4072) @[lsu_bus_buffer.scala 491:95] + node _T_4074 = and(bus_rsp_read, _T_4073) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[2] <= _T_4074 @[lsu_bus_buffer.scala 491:29] + node _T_4075 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_4076 = or(_T_4075, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[2] <= _T_4076 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4077 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4077 : @[Conditional.scala 39:67] + node _T_4078 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_4079 = mux(_T_4078, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[2] <= _T_4079 @[lsu_bus_buffer.scala 498:25] + node _T_4080 = eq(RspPtr, UInt<2>("h02")) @[lsu_bus_buffer.scala 499:37] + node _T_4081 = eq(buf_dualtag[2], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_4082 = and(buf_dual[2], _T_4081) @[lsu_bus_buffer.scala 499:80] + node _T_4083 = or(_T_4080, _T_4082) @[lsu_bus_buffer.scala 499:65] + node _T_4084 = or(_T_4083, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[2] <= _T_4084 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4085 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4085 : @[Conditional.scala 39:67] + buf_nxtstate[2] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_4086 = bits(buf_state_en[2], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_4087 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4086 : @[Reg.scala 28:19] + _T_4087 <= buf_nxtstate[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[2] <= _T_4087 @[lsu_bus_buffer.scala 512:18] + reg _T_4088 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_4088 <= buf_age_in_2 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[2] <= _T_4088 @[lsu_bus_buffer.scala 513:17] + reg _T_4089 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_4089 <= buf_rspage_in[2] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[2] <= _T_4089 @[lsu_bus_buffer.scala 514:20] + node _T_4090 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4090 : @[Reg.scala 28:19] + _T_4091 <= buf_dualtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[2] <= _T_4091 @[lsu_bus_buffer.scala 515:20] + node _T_4092 = bits(buf_dual_in, 2, 2) @[lsu_bus_buffer.scala 516:74] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_4094 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4093 : @[Reg.scala 28:19] + _T_4094 <= _T_4092 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[2] <= _T_4094 @[lsu_bus_buffer.scala 516:17] + node _T_4095 = bits(buf_samedw_in, 2, 2) @[lsu_bus_buffer.scala 517:78] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4096 : @[Reg.scala 28:19] + _T_4097 <= _T_4095 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[2] <= _T_4097 @[lsu_bus_buffer.scala 517:19] + node _T_4098 = bits(buf_nomerge_in, 2, 2) @[lsu_bus_buffer.scala 518:80] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4099 : @[Reg.scala 28:19] + _T_4100 <= _T_4098 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[2] <= _T_4100 @[lsu_bus_buffer.scala 518:20] + node _T_4101 = bits(buf_dualhi_in, 2, 2) @[lsu_bus_buffer.scala 519:78] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4102 : @[Reg.scala 28:19] + _T_4103 <= _T_4101 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[2] <= _T_4103 @[lsu_bus_buffer.scala 519:19] + node _T_4104 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4104 : @[Conditional.scala 40:58] + node _T_4105 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 444:56] + node _T_4106 = mux(_T_4105, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 444:31] + buf_nxtstate[3] <= _T_4106 @[lsu_bus_buffer.scala 444:25] + node _T_4107 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 445:45] + node _T_4108 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:77] + node _T_4109 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 445:97] + node _T_4110 = and(_T_4108, _T_4109) @[lsu_bus_buffer.scala 445:95] + node _T_4111 = eq(UInt<2>("h03"), WrPtr0_r) @[lsu_bus_buffer.scala 445:117] + node _T_4112 = and(_T_4110, _T_4111) @[lsu_bus_buffer.scala 445:112] + node _T_4113 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 445:144] + node _T_4114 = eq(UInt<2>("h03"), WrPtr1_r) @[lsu_bus_buffer.scala 445:166] + node _T_4115 = and(_T_4113, _T_4114) @[lsu_bus_buffer.scala 445:161] + node _T_4116 = or(_T_4112, _T_4115) @[lsu_bus_buffer.scala 445:132] + node _T_4117 = and(_T_4107, _T_4116) @[lsu_bus_buffer.scala 445:63] + node _T_4118 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 445:206] + node _T_4119 = and(ibuf_drain_vld, _T_4118) @[lsu_bus_buffer.scala 445:201] + node _T_4120 = or(_T_4117, _T_4119) @[lsu_bus_buffer.scala 445:183] + buf_state_en[3] <= _T_4120 @[lsu_bus_buffer.scala 445:25] + buf_wr_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 446:22] + buf_data_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 447:24] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 448:52] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[lsu_bus_buffer.scala 448:47] + node _T_4123 = bits(_T_4122, 0, 0) @[lsu_bus_buffer.scala 448:73] + node _T_4124 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 448:90] + node _T_4125 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 448:114] + node _T_4126 = mux(_T_4123, _T_4124, _T_4125) @[lsu_bus_buffer.scala 448:30] + buf_data_in[3] <= _T_4126 @[lsu_bus_buffer.scala 448:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 449:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 450:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_4127 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4127 : @[Conditional.scala 39:67] + node _T_4128 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_4129 = mux(_T_4128, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[3] <= _T_4129 @[lsu_bus_buffer.scala 453:25] + node _T_4130 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46] + buf_state_en[3] <= _T_4130 @[lsu_bus_buffer.scala 454:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 456:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4131 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4131 : @[Conditional.scala 39:67] + node _T_4132 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 459:60] + node _T_4133 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 459:89] + node _T_4134 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 459:124] + node _T_4135 = and(_T_4133, _T_4134) @[lsu_bus_buffer.scala 459:104] + node _T_4136 = mux(_T_4135, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 459:75] + node _T_4137 = mux(_T_4132, UInt<3>("h00"), _T_4136) @[lsu_bus_buffer.scala 459:31] + buf_nxtstate[3] <= _T_4137 @[lsu_bus_buffer.scala 459:25] + node _T_4138 = eq(obuf_tag0, UInt<3>("h03")) @[lsu_bus_buffer.scala 460:48] + node _T_4139 = eq(obuf_tag1, UInt<3>("h03")) @[lsu_bus_buffer.scala 460:104] + node _T_4140 = and(obuf_merge, _T_4139) @[lsu_bus_buffer.scala 460:91] + node _T_4141 = or(_T_4138, _T_4140) @[lsu_bus_buffer.scala 460:77] + node _T_4142 = and(_T_4141, obuf_valid) @[lsu_bus_buffer.scala 460:135] + node _T_4143 = and(_T_4142, obuf_wr_enQ) @[lsu_bus_buffer.scala 460:148] + buf_cmd_state_bus_en[3] <= _T_4143 @[lsu_bus_buffer.scala 460:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[lsu_bus_buffer.scala 461:29] + node _T_4144 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:49] + node _T_4145 = or(_T_4144, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 462:70] + buf_state_en[3] <= _T_4145 @[lsu_bus_buffer.scala 462:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 463:25] + node _T_4146 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 464:56] + node _T_4147 = eq(_T_4146, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:46] + node _T_4148 = and(buf_state_en[3], _T_4147) @[lsu_bus_buffer.scala 464:44] + node _T_4149 = and(_T_4148, obuf_nosend) @[lsu_bus_buffer.scala 464:60] + node _T_4150 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 464:76] + node _T_4151 = and(_T_4149, _T_4150) @[lsu_bus_buffer.scala 464:74] + buf_ldfwd_en[3] <= _T_4151 @[lsu_bus_buffer.scala 464:25] + node _T_4152 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 465:46] + buf_ldfwdtag_in[3] <= _T_4152 @[lsu_bus_buffer.scala 465:28] + node _T_4153 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:47] + node _T_4154 = and(_T_4153, obuf_nosend) @[lsu_bus_buffer.scala 466:67] + node _T_4155 = and(_T_4154, bus_rsp_read) @[lsu_bus_buffer.scala 466:81] + buf_data_en[3] <= _T_4155 @[lsu_bus_buffer.scala 466:24] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 467:48] + node _T_4157 = and(_T_4156, obuf_nosend) @[lsu_bus_buffer.scala 467:68] + node _T_4158 = and(_T_4157, bus_rsp_read_error) @[lsu_bus_buffer.scala 467:82] + buf_error_en[3] <= _T_4158 @[lsu_bus_buffer.scala 467:25] + node _T_4159 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:61] + node _T_4160 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 468:85] + node _T_4161 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 468:103] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 468:126] + node _T_4163 = mux(_T_4160, _T_4161, _T_4162) @[lsu_bus_buffer.scala 468:73] + node _T_4164 = mux(buf_error_en[3], _T_4159, _T_4163) @[lsu_bus_buffer.scala 468:30] + buf_data_in[3] <= _T_4164 @[lsu_bus_buffer.scala 468:24] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 469:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4165 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4165 : @[Conditional.scala 39:67] + node _T_4166 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 472:69] + node _T_4167 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:75] + node _T_4168 = and(_T_4166, _T_4167) @[lsu_bus_buffer.scala 472:73] + node _T_4169 = or(io.dec_tlu_force_halt, _T_4168) @[lsu_bus_buffer.scala 472:57] + node _T_4170 = bits(_T_4169, 0, 0) @[lsu_bus_buffer.scala 472:104] + node _T_4171 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 473:30] + node _T_4172 = and(buf_dual[3], _T_4171) @[lsu_bus_buffer.scala 473:28] + node _T_4173 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 473:57] + node _T_4174 = eq(_T_4173, UInt<1>("h00")) @[lsu_bus_buffer.scala 473:47] + node _T_4175 = and(_T_4172, _T_4174) @[lsu_bus_buffer.scala 473:45] + node _T_4176 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 473:90] + node _T_4177 = and(_T_4175, _T_4176) @[lsu_bus_buffer.scala 473:61] + node _T_4178 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 474:27] + node _T_4179 = or(_T_4178, any_done_wait_state) @[lsu_bus_buffer.scala 474:31] + node _T_4180 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 474:70] + node _T_4181 = and(buf_dual[3], _T_4180) @[lsu_bus_buffer.scala 474:68] + node _T_4182 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 474:97] + node _T_4183 = eq(_T_4182, UInt<1>("h00")) @[lsu_bus_buffer.scala 474:87] + node _T_4184 = and(_T_4181, _T_4183) @[lsu_bus_buffer.scala 474:85] + node _T_4185 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_4186 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_4187 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_4188 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_4189 = eq(buf_dualtag[3], UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_4190 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4191 = eq(buf_dualtag[3], UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4192 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4193 = mux(_T_4185, _T_4186, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4194 = mux(_T_4187, _T_4188, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4195 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4196 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4197 = or(_T_4193, _T_4194) @[Mux.scala 27:72] + node _T_4198 = or(_T_4197, _T_4195) @[Mux.scala 27:72] + node _T_4199 = or(_T_4198, _T_4196) @[Mux.scala 27:72] + wire _T_4200 : UInt<1> @[Mux.scala 27:72] + _T_4200 <= _T_4199 @[Mux.scala 27:72] + node _T_4201 = and(_T_4184, _T_4200) @[lsu_bus_buffer.scala 474:101] + node _T_4202 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 474:167] + node _T_4203 = and(_T_4201, _T_4202) @[lsu_bus_buffer.scala 474:138] + node _T_4204 = and(_T_4203, any_done_wait_state) @[lsu_bus_buffer.scala 474:187] + node _T_4205 = or(_T_4179, _T_4204) @[lsu_bus_buffer.scala 474:53] + node _T_4206 = mux(_T_4205, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 474:16] + node _T_4207 = mux(_T_4177, UInt<3>("h04"), _T_4206) @[lsu_bus_buffer.scala 473:14] + node _T_4208 = mux(_T_4170, UInt<3>("h00"), _T_4207) @[lsu_bus_buffer.scala 472:33] + buf_nxtstate[3] <= _T_4208 @[lsu_bus_buffer.scala 472:27] + node _T_4209 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 475:73] + node _T_4210 = and(bus_rsp_write, _T_4209) @[lsu_bus_buffer.scala 475:52] + node _T_4211 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 476:46] + node _T_4212 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 477:23] + node _T_4213 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 477:47] + node _T_4214 = and(_T_4212, _T_4213) @[lsu_bus_buffer.scala 477:27] + node _T_4215 = or(_T_4211, _T_4214) @[lsu_bus_buffer.scala 476:77] + node _T_4216 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 478:26] + node _T_4217 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 478:54] + node _T_4218 = not(_T_4217) @[lsu_bus_buffer.scala 478:44] + node _T_4219 = and(_T_4216, _T_4218) @[lsu_bus_buffer.scala 478:42] + node _T_4220 = and(_T_4219, buf_samedw[3]) @[lsu_bus_buffer.scala 478:58] + node _T_4221 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 478:94] + node _T_4222 = and(_T_4220, _T_4221) @[lsu_bus_buffer.scala 478:74] + node _T_4223 = or(_T_4215, _T_4222) @[lsu_bus_buffer.scala 477:71] + node _T_4224 = and(bus_rsp_read, _T_4223) @[lsu_bus_buffer.scala 476:25] + node _T_4225 = or(_T_4210, _T_4224) @[lsu_bus_buffer.scala 475:105] + buf_resp_state_bus_en[3] <= _T_4225 @[lsu_bus_buffer.scala 475:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[lsu_bus_buffer.scala 479:29] + node _T_4226 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:49] + node _T_4227 = or(_T_4226, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 480:70] + buf_state_en[3] <= _T_4227 @[lsu_bus_buffer.scala 480:25] + node _T_4228 = and(buf_state_bus_en[3], bus_rsp_read) @[lsu_bus_buffer.scala 481:47] + node _T_4229 = and(_T_4228, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 481:62] + buf_data_en[3] <= _T_4229 @[lsu_bus_buffer.scala 481:24] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 482:48] + node _T_4231 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 482:111] + node _T_4232 = and(bus_rsp_read_error, _T_4231) @[lsu_bus_buffer.scala 482:91] + node _T_4233 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 483:42] + node _T_4234 = and(bus_rsp_read_error, _T_4233) @[lsu_bus_buffer.scala 483:31] + node _T_4235 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 483:66] + node _T_4236 = and(_T_4234, _T_4235) @[lsu_bus_buffer.scala 483:46] + node _T_4237 = or(_T_4232, _T_4236) @[lsu_bus_buffer.scala 482:143] + node _T_4238 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 484:54] + node _T_4239 = and(bus_rsp_write_error, _T_4238) @[lsu_bus_buffer.scala 484:33] + node _T_4240 = or(_T_4237, _T_4239) @[lsu_bus_buffer.scala 483:88] + node _T_4241 = and(_T_4230, _T_4240) @[lsu_bus_buffer.scala 482:68] + buf_error_en[3] <= _T_4241 @[lsu_bus_buffer.scala 482:25] + node _T_4242 = eq(buf_error_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 485:50] + node _T_4243 = and(buf_state_en[3], _T_4242) @[lsu_bus_buffer.scala 485:48] + node _T_4244 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 485:84] + node _T_4245 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 485:102] + node _T_4246 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:125] + node _T_4247 = mux(_T_4244, _T_4245, _T_4246) @[lsu_bus_buffer.scala 485:72] + node _T_4248 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 485:148] + node _T_4249 = mux(_T_4243, _T_4247, _T_4248) @[lsu_bus_buffer.scala 485:30] + buf_data_in[3] <= _T_4249 @[lsu_bus_buffer.scala 485:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 486:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 487:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4250 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4250 : @[Conditional.scala 39:67] + node _T_4251 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 490:60] + node _T_4252 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 490:86] + node _T_4253 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 490:101] + node _T_4254 = bits(_T_4253, 0, 0) @[lsu_bus_buffer.scala 490:101] + node _T_4255 = or(_T_4252, _T_4254) @[lsu_bus_buffer.scala 490:90] + node _T_4256 = or(_T_4255, any_done_wait_state) @[lsu_bus_buffer.scala 490:118] + node _T_4257 = mux(_T_4256, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 490:75] + node _T_4258 = mux(_T_4251, UInt<3>("h00"), _T_4257) @[lsu_bus_buffer.scala 490:31] + buf_nxtstate[3] <= _T_4258 @[lsu_bus_buffer.scala 490:25] + node _T_4259 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 491:66] + node _T_4260 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 492:21] + node _T_4261 = bits(_T_4260, 0, 0) @[lsu_bus_buffer.scala 492:21] + node _T_4262 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[lsu_bus_buffer.scala 492:58] + node _T_4263 = and(_T_4261, _T_4262) @[lsu_bus_buffer.scala 492:38] + node _T_4264 = or(_T_4259, _T_4263) @[lsu_bus_buffer.scala 491:95] + node _T_4265 = and(bus_rsp_read, _T_4264) @[lsu_bus_buffer.scala 491:45] + buf_state_bus_en[3] <= _T_4265 @[lsu_bus_buffer.scala 491:29] + node _T_4266 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 493:49] + node _T_4267 = or(_T_4266, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 493:70] + buf_state_en[3] <= _T_4267 @[lsu_bus_buffer.scala 493:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 495:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4268 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4268 : @[Conditional.scala 39:67] + node _T_4269 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 498:60] + node _T_4270 = mux(_T_4269, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 498:31] + buf_nxtstate[3] <= _T_4270 @[lsu_bus_buffer.scala 498:25] + node _T_4271 = eq(RspPtr, UInt<2>("h03")) @[lsu_bus_buffer.scala 499:37] + node _T_4272 = eq(buf_dualtag[3], RspPtr) @[lsu_bus_buffer.scala 499:98] + node _T_4273 = and(buf_dual[3], _T_4272) @[lsu_bus_buffer.scala 499:80] + node _T_4274 = or(_T_4271, _T_4273) @[lsu_bus_buffer.scala 499:65] + node _T_4275 = or(_T_4274, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 499:112] + buf_state_en[3] <= _T_4275 @[lsu_bus_buffer.scala 499:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 500:34] + buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 501:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4276 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4276 : @[Conditional.scala 39:67] + buf_nxtstate[3] <= UInt<3>("h00") @[lsu_bus_buffer.scala 504:25] + buf_rst[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 505:20] + buf_state_en[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 506:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 508:25] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 509:34] + skip @[Conditional.scala 39:67] + node _T_4277 = bits(buf_state_en[3], 0, 0) @[lsu_bus_buffer.scala 512:108] + reg _T_4278 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4277 : @[Reg.scala 28:19] + _T_4278 <= buf_nxtstate[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[3] <= _T_4278 @[lsu_bus_buffer.scala 512:18] + reg _T_4279 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 513:60] + _T_4279 <= buf_age_in_3 @[lsu_bus_buffer.scala 513:60] + buf_ageQ[3] <= _T_4279 @[lsu_bus_buffer.scala 513:17] + reg _T_4280 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 514:63] + _T_4280 <= buf_rspage_in[3] @[lsu_bus_buffer.scala 514:63] + buf_rspageQ[3] <= _T_4280 @[lsu_bus_buffer.scala 514:20] + node _T_4281 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 515:109] + reg _T_4282 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4281 : @[Reg.scala 28:19] + _T_4282 <= buf_dualtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[3] <= _T_4282 @[lsu_bus_buffer.scala 515:20] + node _T_4283 = bits(buf_dual_in, 3, 3) @[lsu_bus_buffer.scala 516:74] + node _T_4284 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 516:107] + reg _T_4285 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4284 : @[Reg.scala 28:19] + _T_4285 <= _T_4283 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[3] <= _T_4285 @[lsu_bus_buffer.scala 516:17] + node _T_4286 = bits(buf_samedw_in, 3, 3) @[lsu_bus_buffer.scala 517:78] + node _T_4287 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 517:111] + reg _T_4288 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4287 : @[Reg.scala 28:19] + _T_4288 <= _T_4286 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[3] <= _T_4288 @[lsu_bus_buffer.scala 517:19] + node _T_4289 = bits(buf_nomerge_in, 3, 3) @[lsu_bus_buffer.scala 518:80] + node _T_4290 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 518:113] + reg _T_4291 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4290 : @[Reg.scala 28:19] + _T_4291 <= _T_4289 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[3] <= _T_4291 @[lsu_bus_buffer.scala 518:20] + node _T_4292 = bits(buf_dualhi_in, 3, 3) @[lsu_bus_buffer.scala 519:78] + node _T_4293 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 519:111] + reg _T_4294 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4293 : @[Reg.scala 28:19] + _T_4294 <= _T_4292 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[3] <= _T_4294 @[lsu_bus_buffer.scala 519:19] + node _T_4295 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4295 : @[Reg.scala 28:19] + _T_4296 <= buf_ldfwd_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4297 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4298 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4297 : @[Reg.scala 28:19] + _T_4298 <= buf_ldfwd_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4299 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4300 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4299 : @[Reg.scala 28:19] + _T_4300 <= buf_ldfwd_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4301 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 522:131] + reg _T_4302 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4301 : @[Reg.scala 28:19] + _T_4302 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4303 = cat(_T_4302, _T_4300) @[Cat.scala 29:58] + node _T_4304 = cat(_T_4303, _T_4298) @[Cat.scala 29:58] + node _T_4305 = cat(_T_4304, _T_4296) @[Cat.scala 29:58] + buf_ldfwd <= _T_4305 @[lsu_bus_buffer.scala 522:13] + node _T_4306 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4307 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4306 : @[Reg.scala 28:19] + _T_4307 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4308 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4309 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4308 : @[Reg.scala 28:19] + _T_4309 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4310 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4311 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4310 : @[Reg.scala 28:19] + _T_4311 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4312 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 523:132] + reg _T_4313 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4312 : @[Reg.scala 28:19] + _T_4313 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_ldfwdtag[0] <= _T_4307 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[1] <= _T_4309 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[2] <= _T_4311 @[lsu_bus_buffer.scala 523:16] + buf_ldfwdtag[3] <= _T_4313 @[lsu_bus_buffer.scala 523:16] + node _T_4314 = bits(buf_sideeffect_in, 0, 0) @[lsu_bus_buffer.scala 524:105] + node _T_4315 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4316 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4315 : @[Reg.scala 28:19] + _T_4316 <= _T_4314 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4317 = bits(buf_sideeffect_in, 1, 1) @[lsu_bus_buffer.scala 524:105] + node _T_4318 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4319 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4318 : @[Reg.scala 28:19] + _T_4319 <= _T_4317 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4320 = bits(buf_sideeffect_in, 2, 2) @[lsu_bus_buffer.scala 524:105] + node _T_4321 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4322 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4321 : @[Reg.scala 28:19] + _T_4322 <= _T_4320 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4323 = bits(buf_sideeffect_in, 3, 3) @[lsu_bus_buffer.scala 524:105] + node _T_4324 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 524:138] + reg _T_4325 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4324 : @[Reg.scala 28:19] + _T_4325 <= _T_4323 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4326 = cat(_T_4325, _T_4322) @[Cat.scala 29:58] + node _T_4327 = cat(_T_4326, _T_4319) @[Cat.scala 29:58] + node _T_4328 = cat(_T_4327, _T_4316) @[Cat.scala 29:58] + buf_sideeffect <= _T_4328 @[lsu_bus_buffer.scala 524:18] + node _T_4329 = bits(buf_unsign_in, 0, 0) @[lsu_bus_buffer.scala 525:97] + node _T_4330 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4331 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4330 : @[Reg.scala 28:19] + _T_4331 <= _T_4329 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4332 = bits(buf_unsign_in, 1, 1) @[lsu_bus_buffer.scala 525:97] + node _T_4333 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4334 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4333 : @[Reg.scala 28:19] + _T_4334 <= _T_4332 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4335 = bits(buf_unsign_in, 2, 2) @[lsu_bus_buffer.scala 525:97] + node _T_4336 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4337 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4336 : @[Reg.scala 28:19] + _T_4337 <= _T_4335 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4338 = bits(buf_unsign_in, 3, 3) @[lsu_bus_buffer.scala 525:97] + node _T_4339 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 525:130] + reg _T_4340 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4339 : @[Reg.scala 28:19] + _T_4340 <= _T_4338 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4341 = cat(_T_4340, _T_4337) @[Cat.scala 29:58] + node _T_4342 = cat(_T_4341, _T_4334) @[Cat.scala 29:58] + node _T_4343 = cat(_T_4342, _T_4331) @[Cat.scala 29:58] + buf_unsign <= _T_4343 @[lsu_bus_buffer.scala 525:14] + node _T_4344 = bits(buf_write_in, 0, 0) @[lsu_bus_buffer.scala 526:95] + node _T_4345 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4346 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4345 : @[Reg.scala 28:19] + _T_4346 <= _T_4344 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4347 = bits(buf_write_in, 1, 1) @[lsu_bus_buffer.scala 526:95] + node _T_4348 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4349 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4348 : @[Reg.scala 28:19] + _T_4349 <= _T_4347 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4350 = bits(buf_write_in, 2, 2) @[lsu_bus_buffer.scala 526:95] + node _T_4351 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4352 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4351 : @[Reg.scala 28:19] + _T_4352 <= _T_4350 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4353 = bits(buf_write_in, 3, 3) @[lsu_bus_buffer.scala 526:95] + node _T_4354 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 526:128] + reg _T_4355 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4354 : @[Reg.scala 28:19] + _T_4355 <= _T_4353 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4356 = cat(_T_4355, _T_4352) @[Cat.scala 29:58] + node _T_4357 = cat(_T_4356, _T_4349) @[Cat.scala 29:58] + node _T_4358 = cat(_T_4357, _T_4346) @[Cat.scala 29:58] + buf_write <= _T_4358 @[lsu_bus_buffer.scala 526:13] + node _T_4359 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4360 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4359 : @[Reg.scala 28:19] + _T_4360 <= buf_sz_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4361 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4362 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4361 : @[Reg.scala 28:19] + _T_4362 <= buf_sz_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4363 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4364 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4363 : @[Reg.scala 28:19] + _T_4364 <= buf_sz_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4365 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 527:117] + reg _T_4366 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4365 : @[Reg.scala 28:19] + _T_4366 <= buf_sz_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_sz[0] <= _T_4360 @[lsu_bus_buffer.scala 527:10] + buf_sz[1] <= _T_4362 @[lsu_bus_buffer.scala 527:10] + buf_sz[2] <= _T_4364 @[lsu_bus_buffer.scala 527:10] + buf_sz[3] <= _T_4366 @[lsu_bus_buffer.scala 527:10] + node _T_4367 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_4367 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4368 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4367 : @[Reg.scala 28:19] + _T_4368 <= buf_addr_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4369 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_4369 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4370 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4369 : @[Reg.scala 28:19] + _T_4370 <= buf_addr_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4371 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_4371 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4372 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4371 : @[Reg.scala 28:19] + _T_4372 <= buf_addr_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4373 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 528:80] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_4373 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4374 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4373 : @[Reg.scala 28:19] + _T_4374 <= buf_addr_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_addr[0] <= _T_4368 @[lsu_bus_buffer.scala 528:12] + buf_addr[1] <= _T_4370 @[lsu_bus_buffer.scala 528:12] + buf_addr[2] <= _T_4372 @[lsu_bus_buffer.scala 528:12] + buf_addr[3] <= _T_4374 @[lsu_bus_buffer.scala 528:12] + node _T_4375 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4376 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4375 : @[Reg.scala 28:19] + _T_4376 <= buf_byteen_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4377 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4378 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4377 : @[Reg.scala 28:19] + _T_4378 <= buf_byteen_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4379 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4380 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4379 : @[Reg.scala 28:19] + _T_4380 <= buf_byteen_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4381 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 529:125] + reg _T_4382 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4381 : @[Reg.scala 28:19] + _T_4382 <= buf_byteen_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen[0] <= _T_4376 @[lsu_bus_buffer.scala 529:14] + buf_byteen[1] <= _T_4378 @[lsu_bus_buffer.scala 529:14] + buf_byteen[2] <= _T_4380 @[lsu_bus_buffer.scala 529:14] + buf_byteen[3] <= _T_4382 @[lsu_bus_buffer.scala 529:14] + inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4383 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[0] : @[Reg.scala 28:19] + _T_4383 <= buf_data_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4384 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[1] : @[Reg.scala 28:19] + _T_4384 <= buf_data_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4385 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[2] : @[Reg.scala 28:19] + _T_4385 <= buf_data_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 404:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 407:17] + rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_4386 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when buf_data_en[3] : @[Reg.scala 28:19] + _T_4386 <= buf_data_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_data[0] <= _T_4383 @[lsu_bus_buffer.scala 530:12] + buf_data[1] <= _T_4384 @[lsu_bus_buffer.scala 530:12] + buf_data[2] <= _T_4385 @[lsu_bus_buffer.scala 530:12] + buf_data[3] <= _T_4386 @[lsu_bus_buffer.scala 530:12] + node _T_4387 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4388 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 531:133] + node _T_4389 = mux(buf_error_en[0], UInt<1>("h01"), _T_4388) @[lsu_bus_buffer.scala 531:98] + node _T_4390 = and(_T_4387, _T_4389) @[lsu_bus_buffer.scala 531:93] + reg _T_4391 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4391 <= _T_4390 @[lsu_bus_buffer.scala 531:80] + node _T_4392 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4393 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 531:133] + node _T_4394 = mux(buf_error_en[1], UInt<1>("h01"), _T_4393) @[lsu_bus_buffer.scala 531:98] + node _T_4395 = and(_T_4392, _T_4394) @[lsu_bus_buffer.scala 531:93] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4396 <= _T_4395 @[lsu_bus_buffer.scala 531:80] + node _T_4397 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4398 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 531:133] + node _T_4399 = mux(buf_error_en[2], UInt<1>("h01"), _T_4398) @[lsu_bus_buffer.scala 531:98] + node _T_4400 = and(_T_4397, _T_4399) @[lsu_bus_buffer.scala 531:93] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4401 <= _T_4400 @[lsu_bus_buffer.scala 531:80] + node _T_4402 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:81] + node _T_4403 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 531:133] + node _T_4404 = mux(buf_error_en[3], UInt<1>("h01"), _T_4403) @[lsu_bus_buffer.scala 531:98] + node _T_4405 = and(_T_4402, _T_4404) @[lsu_bus_buffer.scala 531:93] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 531:80] + _T_4406 <= _T_4405 @[lsu_bus_buffer.scala 531:80] + node _T_4407 = cat(_T_4406, _T_4401) @[Cat.scala 29:58] + node _T_4408 = cat(_T_4407, _T_4396) @[Cat.scala 29:58] + node _T_4409 = cat(_T_4408, _T_4391) @[Cat.scala 29:58] + buf_error <= _T_4409 @[lsu_bus_buffer.scala 531:13] + node _T_4410 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4411 = mux(io.ldst_dual_m, _T_4410, io.lsu_busreq_m) @[lsu_bus_buffer.scala 532:28] + node _T_4412 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4413 = mux(io.ldst_dual_r, _T_4412, io.lsu_busreq_r) @[lsu_bus_buffer.scala 532:94] + node _T_4414 = add(_T_4411, _T_4413) @[lsu_bus_buffer.scala 532:88] + node _T_4415 = add(_T_4414, ibuf_valid) @[lsu_bus_buffer.scala 532:154] + node _T_4416 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4417 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4418 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4419 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 532:190] + node _T_4420 = add(_T_4416, _T_4417) @[lsu_bus_buffer.scala 532:217] + node _T_4421 = add(_T_4420, _T_4418) @[lsu_bus_buffer.scala 532:217] + node _T_4422 = add(_T_4421, _T_4419) @[lsu_bus_buffer.scala 532:217] + node _T_4423 = add(_T_4415, _T_4422) @[lsu_bus_buffer.scala 532:169] + node buf_numvld_any = tail(_T_4423, 1) @[lsu_bus_buffer.scala 532:169] + node _T_4424 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 533:60] + node _T_4425 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4426 = and(_T_4424, _T_4425) @[lsu_bus_buffer.scala 533:64] + node _T_4427 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4428 = and(_T_4426, _T_4427) @[lsu_bus_buffer.scala 533:89] + node _T_4429 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 533:60] + node _T_4430 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4431 = and(_T_4429, _T_4430) @[lsu_bus_buffer.scala 533:64] + node _T_4432 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4433 = and(_T_4431, _T_4432) @[lsu_bus_buffer.scala 533:89] + node _T_4434 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 533:60] + node _T_4435 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4436 = and(_T_4434, _T_4435) @[lsu_bus_buffer.scala 533:64] + node _T_4437 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4438 = and(_T_4436, _T_4437) @[lsu_bus_buffer.scala 533:89] + node _T_4439 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 533:60] + node _T_4440 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:79] + node _T_4441 = and(_T_4439, _T_4440) @[lsu_bus_buffer.scala 533:64] + node _T_4442 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:91] + node _T_4443 = and(_T_4441, _T_4442) @[lsu_bus_buffer.scala 533:89] + node _T_4444 = add(_T_4443, _T_4438) @[lsu_bus_buffer.scala 533:142] + node _T_4445 = add(_T_4444, _T_4433) @[lsu_bus_buffer.scala 533:142] + node _T_4446 = add(_T_4445, _T_4428) @[lsu_bus_buffer.scala 533:142] + buf_numvld_wrcmd_any <= _T_4446 @[lsu_bus_buffer.scala 533:24] + node _T_4447 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4448 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4449 = and(_T_4447, _T_4448) @[lsu_bus_buffer.scala 534:73] + node _T_4450 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4451 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4452 = and(_T_4450, _T_4451) @[lsu_bus_buffer.scala 534:73] + node _T_4453 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4454 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4455 = and(_T_4453, _T_4454) @[lsu_bus_buffer.scala 534:73] + node _T_4456 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 534:63] + node _T_4457 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 534:75] + node _T_4458 = and(_T_4456, _T_4457) @[lsu_bus_buffer.scala 534:73] + node _T_4459 = add(_T_4458, _T_4455) @[lsu_bus_buffer.scala 534:126] + node _T_4460 = add(_T_4459, _T_4452) @[lsu_bus_buffer.scala 534:126] + node _T_4461 = add(_T_4460, _T_4449) @[lsu_bus_buffer.scala 534:126] + buf_numvld_cmd_any <= _T_4461 @[lsu_bus_buffer.scala 534:22] + node _T_4462 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4463 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4464 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4465 = and(_T_4463, _T_4464) @[lsu_bus_buffer.scala 535:100] + node _T_4466 = or(_T_4462, _T_4465) @[lsu_bus_buffer.scala 535:74] + node _T_4467 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4468 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4469 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4470 = and(_T_4468, _T_4469) @[lsu_bus_buffer.scala 535:100] + node _T_4471 = or(_T_4467, _T_4470) @[lsu_bus_buffer.scala 535:74] + node _T_4472 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4473 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4474 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4475 = and(_T_4473, _T_4474) @[lsu_bus_buffer.scala 535:100] + node _T_4476 = or(_T_4472, _T_4475) @[lsu_bus_buffer.scala 535:74] + node _T_4477 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 535:63] + node _T_4478 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 535:90] + node _T_4479 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 535:102] + node _T_4480 = and(_T_4478, _T_4479) @[lsu_bus_buffer.scala 535:100] + node _T_4481 = or(_T_4477, _T_4480) @[lsu_bus_buffer.scala 535:74] + node _T_4482 = add(_T_4481, _T_4476) @[lsu_bus_buffer.scala 535:154] + node _T_4483 = add(_T_4482, _T_4471) @[lsu_bus_buffer.scala 535:154] + node _T_4484 = add(_T_4483, _T_4466) @[lsu_bus_buffer.scala 535:154] + buf_numvld_pend_any <= _T_4484 @[lsu_bus_buffer.scala 535:23] + node _T_4485 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4486 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4487 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4488 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 536:61] + node _T_4489 = or(_T_4488, _T_4487) @[lsu_bus_buffer.scala 536:93] + node _T_4490 = or(_T_4489, _T_4486) @[lsu_bus_buffer.scala 536:93] + node _T_4491 = or(_T_4490, _T_4485) @[lsu_bus_buffer.scala 536:93] + any_done_wait_state <= _T_4491 @[lsu_bus_buffer.scala 536:23] + node _T_4492 = orr(buf_numvld_pend_any) @[lsu_bus_buffer.scala 537:53] + io.lsu_bus_buffer_pend_any <= _T_4492 @[lsu_bus_buffer.scala 537:30] + node _T_4493 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[lsu_bus_buffer.scala 538:52] + node _T_4494 = geq(buf_numvld_any, UInt<2>("h03")) @[lsu_bus_buffer.scala 538:92] + node _T_4495 = eq(buf_numvld_any, UInt<3>("h04")) @[lsu_bus_buffer.scala 538:121] + node _T_4496 = mux(_T_4493, _T_4494, _T_4495) @[lsu_bus_buffer.scala 538:36] + io.lsu_bus_buffer_full_any <= _T_4496 @[lsu_bus_buffer.scala 538:30] + node _T_4497 = orr(buf_state[0]) @[lsu_bus_buffer.scala 539:52] + node _T_4498 = orr(buf_state[1]) @[lsu_bus_buffer.scala 539:52] + node _T_4499 = orr(buf_state[2]) @[lsu_bus_buffer.scala 539:52] + node _T_4500 = orr(buf_state[3]) @[lsu_bus_buffer.scala 539:52] + node _T_4501 = or(_T_4497, _T_4498) @[lsu_bus_buffer.scala 539:65] + node _T_4502 = or(_T_4501, _T_4499) @[lsu_bus_buffer.scala 539:65] + node _T_4503 = or(_T_4502, _T_4500) @[lsu_bus_buffer.scala 539:65] + node _T_4504 = eq(_T_4503, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:34] + node _T_4505 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:72] + node _T_4506 = and(_T_4504, _T_4505) @[lsu_bus_buffer.scala 539:70] + node _T_4507 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:86] + node _T_4508 = and(_T_4506, _T_4507) @[lsu_bus_buffer.scala 539:84] + io.lsu_bus_buffer_empty_any <= _T_4508 @[lsu_bus_buffer.scala 539:31] + node _T_4509 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[lsu_bus_buffer.scala 541:64] + node _T_4510 = and(_T_4509, io.lsu_pkt_m.bits.load) @[lsu_bus_buffer.scala 541:85] + node _T_4511 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_bus_buffer.scala 541:112] + node _T_4512 = and(_T_4510, _T_4511) @[lsu_bus_buffer.scala 541:110] + node _T_4513 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 541:129] + node _T_4514 = and(_T_4512, _T_4513) @[lsu_bus_buffer.scala 541:127] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= _T_4514 @[lsu_bus_buffer.scala 541:45] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= WrPtr0_m @[lsu_bus_buffer.scala 542:43] + wire lsu_nonblock_load_valid_r : UInt<1> + lsu_nonblock_load_valid_r <= UInt<1>("h00") + node _T_4515 = eq(io.lsu_commit_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:74] + node _T_4516 = and(lsu_nonblock_load_valid_r, _T_4515) @[lsu_bus_buffer.scala 544:72] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= _T_4516 @[lsu_bus_buffer.scala 544:43] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 545:47] + node _T_4517 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4518 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 546:106] + node _T_4519 = eq(_T_4518, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4520 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4521 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 546:106] + node _T_4522 = eq(_T_4521, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4523 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4524 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 546:106] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4526 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:80] + node _T_4527 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 546:106] + node _T_4528 = eq(_T_4527, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:95] + node _T_4529 = mux(_T_4517, _T_4519, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4530 = mux(_T_4520, _T_4522, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4531 = mux(_T_4523, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4532 = mux(_T_4526, _T_4528, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4533 = or(_T_4529, _T_4530) @[Mux.scala 27:72] + node _T_4534 = or(_T_4533, _T_4531) @[Mux.scala 27:72] + node _T_4535 = or(_T_4534, _T_4532) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_load_data_ready <= _T_4535 @[Mux.scala 27:72] + node _T_4536 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4537 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 547:117] + node _T_4538 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 547:133] + node _T_4539 = eq(_T_4538, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4540 = and(_T_4537, _T_4539) @[lsu_bus_buffer.scala 547:121] + node _T_4541 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4542 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 547:117] + node _T_4543 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 547:133] + node _T_4544 = eq(_T_4543, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4545 = and(_T_4542, _T_4544) @[lsu_bus_buffer.scala 547:121] + node _T_4546 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4547 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 547:117] + node _T_4548 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 547:133] + node _T_4549 = eq(_T_4548, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4550 = and(_T_4547, _T_4549) @[lsu_bus_buffer.scala 547:121] + node _T_4551 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:93] + node _T_4552 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 547:117] + node _T_4553 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 547:133] + node _T_4554 = eq(_T_4553, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123] + node _T_4555 = and(_T_4552, _T_4554) @[lsu_bus_buffer.scala 547:121] + node _T_4556 = mux(_T_4536, _T_4540, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4557 = mux(_T_4541, _T_4545, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4558 = mux(_T_4546, _T_4550, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4559 = mux(_T_4551, _T_4555, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4560 = or(_T_4556, _T_4557) @[Mux.scala 27:72] + node _T_4561 = or(_T_4560, _T_4558) @[Mux.scala 27:72] + node _T_4562 = or(_T_4561, _T_4559) @[Mux.scala 27:72] + wire _T_4563 : UInt<1> @[Mux.scala 27:72] + _T_4563 <= _T_4562 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_error <= _T_4563 @[lsu_bus_buffer.scala 547:48] + node _T_4564 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4565 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 548:114] + node _T_4566 = eq(_T_4565, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4567 = and(_T_4564, _T_4566) @[lsu_bus_buffer.scala 548:102] + node _T_4568 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4569 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4570 = or(_T_4568, _T_4569) @[lsu_bus_buffer.scala 548:134] + node _T_4571 = and(_T_4567, _T_4570) @[lsu_bus_buffer.scala 548:118] + node _T_4572 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4573 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 548:114] + node _T_4574 = eq(_T_4573, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4575 = and(_T_4572, _T_4574) @[lsu_bus_buffer.scala 548:102] + node _T_4576 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4577 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4578 = or(_T_4576, _T_4577) @[lsu_bus_buffer.scala 548:134] + node _T_4579 = and(_T_4575, _T_4578) @[lsu_bus_buffer.scala 548:118] + node _T_4580 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4581 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 548:114] + node _T_4582 = eq(_T_4581, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4583 = and(_T_4580, _T_4582) @[lsu_bus_buffer.scala 548:102] + node _T_4584 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4585 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4586 = or(_T_4584, _T_4585) @[lsu_bus_buffer.scala 548:134] + node _T_4587 = and(_T_4583, _T_4586) @[lsu_bus_buffer.scala 548:118] + node _T_4588 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:91] + node _T_4589 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 548:114] + node _T_4590 = eq(_T_4589, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:104] + node _T_4591 = and(_T_4588, _T_4590) @[lsu_bus_buffer.scala 548:102] + node _T_4592 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:121] + node _T_4593 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 548:136] + node _T_4594 = or(_T_4592, _T_4593) @[lsu_bus_buffer.scala 548:134] + node _T_4595 = and(_T_4591, _T_4594) @[lsu_bus_buffer.scala 548:118] + node _T_4596 = mux(_T_4571, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4597 = mux(_T_4579, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4598 = mux(_T_4587, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4599 = mux(_T_4595, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4600 = or(_T_4596, _T_4597) @[Mux.scala 27:72] + node _T_4601 = or(_T_4600, _T_4598) @[Mux.scala 27:72] + node _T_4602 = or(_T_4601, _T_4599) @[Mux.scala 27:72] + wire _T_4603 : UInt<2> @[Mux.scala 27:72] + _T_4603 <= _T_4602 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= _T_4603 @[lsu_bus_buffer.scala 548:45] + node _T_4604 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4605 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 549:101] + node _T_4606 = eq(_T_4605, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4607 = and(_T_4604, _T_4606) @[lsu_bus_buffer.scala 549:89] + node _T_4608 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4609 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4610 = or(_T_4608, _T_4609) @[lsu_bus_buffer.scala 549:121] + node _T_4611 = and(_T_4607, _T_4610) @[lsu_bus_buffer.scala 549:105] + node _T_4612 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4613 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 549:101] + node _T_4614 = eq(_T_4613, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4615 = and(_T_4612, _T_4614) @[lsu_bus_buffer.scala 549:89] + node _T_4616 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4617 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4618 = or(_T_4616, _T_4617) @[lsu_bus_buffer.scala 549:121] + node _T_4619 = and(_T_4615, _T_4618) @[lsu_bus_buffer.scala 549:105] + node _T_4620 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4621 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 549:101] + node _T_4622 = eq(_T_4621, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4623 = and(_T_4620, _T_4622) @[lsu_bus_buffer.scala 549:89] + node _T_4624 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4625 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4626 = or(_T_4624, _T_4625) @[lsu_bus_buffer.scala 549:121] + node _T_4627 = and(_T_4623, _T_4626) @[lsu_bus_buffer.scala 549:105] + node _T_4628 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 549:78] + node _T_4629 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 549:101] + node _T_4630 = eq(_T_4629, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:91] + node _T_4631 = and(_T_4628, _T_4630) @[lsu_bus_buffer.scala 549:89] + node _T_4632 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:108] + node _T_4633 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 549:123] + node _T_4634 = or(_T_4632, _T_4633) @[lsu_bus_buffer.scala 549:121] + node _T_4635 = and(_T_4631, _T_4634) @[lsu_bus_buffer.scala 549:105] + node _T_4636 = mux(_T_4611, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4637 = mux(_T_4619, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4638 = mux(_T_4627, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4639 = mux(_T_4635, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4640 = or(_T_4636, _T_4637) @[Mux.scala 27:72] + node _T_4641 = or(_T_4640, _T_4638) @[Mux.scala 27:72] + node _T_4642 = or(_T_4641, _T_4639) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_lo <= _T_4642 @[Mux.scala 27:72] + node _T_4643 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4644 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 550:101] + node _T_4645 = eq(_T_4644, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4646 = and(_T_4643, _T_4645) @[lsu_bus_buffer.scala 550:89] + node _T_4647 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 550:120] + node _T_4648 = and(_T_4646, _T_4647) @[lsu_bus_buffer.scala 550:105] + node _T_4649 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4650 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 550:101] + node _T_4651 = eq(_T_4650, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4652 = and(_T_4649, _T_4651) @[lsu_bus_buffer.scala 550:89] + node _T_4653 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 550:120] + node _T_4654 = and(_T_4652, _T_4653) @[lsu_bus_buffer.scala 550:105] + node _T_4655 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4656 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 550:101] + node _T_4657 = eq(_T_4656, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4658 = and(_T_4655, _T_4657) @[lsu_bus_buffer.scala 550:89] + node _T_4659 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 550:120] + node _T_4660 = and(_T_4658, _T_4659) @[lsu_bus_buffer.scala 550:105] + node _T_4661 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 550:78] + node _T_4662 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 550:101] + node _T_4663 = eq(_T_4662, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:91] + node _T_4664 = and(_T_4661, _T_4663) @[lsu_bus_buffer.scala 550:89] + node _T_4665 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 550:120] + node _T_4666 = and(_T_4664, _T_4665) @[lsu_bus_buffer.scala 550:105] + node _T_4667 = mux(_T_4648, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4668 = mux(_T_4654, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4669 = mux(_T_4660, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4670 = mux(_T_4666, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4671 = or(_T_4667, _T_4668) @[Mux.scala 27:72] + node _T_4672 = or(_T_4671, _T_4669) @[Mux.scala 27:72] + node _T_4673 = or(_T_4672, _T_4670) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_hi <= _T_4673 @[Mux.scala 27:72] + node _T_4674 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_4675 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_4676 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_4677 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_4678 = mux(_T_4674, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4679 = mux(_T_4675, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4680 = mux(_T_4676, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4681 = mux(_T_4677, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4682 = or(_T_4678, _T_4679) @[Mux.scala 27:72] + node _T_4683 = or(_T_4682, _T_4680) @[Mux.scala 27:72] + node _T_4684 = or(_T_4683, _T_4681) @[Mux.scala 27:72] + wire _T_4685 : UInt<32> @[Mux.scala 27:72] + _T_4685 <= _T_4684 @[Mux.scala 27:72] + node lsu_nonblock_addr_offset = bits(_T_4685, 1, 0) @[lsu_bus_buffer.scala 551:96] + node _T_4686 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 62:123] + node _T_4687 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 62:123] + node _T_4688 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 62:123] + node _T_4689 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 62:123] + node _T_4690 = mux(_T_4686, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4691 = mux(_T_4687, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4692 = mux(_T_4688, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4693 = mux(_T_4689, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4694 = or(_T_4690, _T_4691) @[Mux.scala 27:72] + node _T_4695 = or(_T_4694, _T_4692) @[Mux.scala 27:72] + node _T_4696 = or(_T_4695, _T_4693) @[Mux.scala 27:72] + wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] + lsu_nonblock_sz <= _T_4696 @[Mux.scala 27:72] + node _T_4697 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:118] + node _T_4698 = bits(buf_unsign, 0, 0) @[lsu_bus_buffer.scala 61:129] + node _T_4699 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:118] + node _T_4700 = bits(buf_unsign, 1, 1) @[lsu_bus_buffer.scala 61:129] + node _T_4701 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:118] + node _T_4702 = bits(buf_unsign, 2, 2) @[lsu_bus_buffer.scala 61:129] + node _T_4703 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:118] + node _T_4704 = bits(buf_unsign, 3, 3) @[lsu_bus_buffer.scala 61:129] + node _T_4705 = mux(_T_4697, _T_4698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4706 = mux(_T_4699, _T_4700, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4707 = mux(_T_4701, _T_4702, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4708 = mux(_T_4703, _T_4704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4709 = or(_T_4705, _T_4706) @[Mux.scala 27:72] + node _T_4710 = or(_T_4709, _T_4707) @[Mux.scala 27:72] + node _T_4711 = or(_T_4710, _T_4708) @[Mux.scala 27:72] + wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_unsign <= _T_4711 @[Mux.scala 27:72] + node _T_4712 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] + node _T_4713 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[lsu_bus_buffer.scala 555:121] + node lsu_nonblock_data_unalgn = dshr(_T_4712, _T_4713) @[lsu_bus_buffer.scala 555:92] + node _T_4714 = eq(io.dctl_busbuff.lsu_nonblock_load_data_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 557:82] + node _T_4715 = and(lsu_nonblock_load_data_ready, _T_4714) @[lsu_bus_buffer.scala 557:80] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= _T_4715 @[lsu_bus_buffer.scala 557:48] + node _T_4716 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 558:81] + node _T_4717 = and(lsu_nonblock_unsign, _T_4716) @[lsu_bus_buffer.scala 558:63] + node _T_4718 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 558:131] + node _T_4719 = cat(UInt<24>("h00"), _T_4718) @[Cat.scala 29:58] + node _T_4720 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 559:45] + node _T_4721 = and(lsu_nonblock_unsign, _T_4720) @[lsu_bus_buffer.scala 559:26] + node _T_4722 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 559:95] + node _T_4723 = cat(UInt<16>("h00"), _T_4722) @[Cat.scala 29:58] + node _T_4724 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 560:6] + node _T_4725 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 560:45] + node _T_4726 = and(_T_4724, _T_4725) @[lsu_bus_buffer.scala 560:27] + node _T_4727 = bits(lsu_nonblock_data_unalgn, 7, 7) @[lsu_bus_buffer.scala 560:93] + node _T_4728 = bits(_T_4727, 0, 0) @[Bitwise.scala 72:15] + node _T_4729 = mux(_T_4728, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_4730 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 560:123] + node _T_4731 = cat(_T_4729, _T_4730) @[Cat.scala 29:58] + node _T_4732 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 561:6] + node _T_4733 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 561:45] + node _T_4734 = and(_T_4732, _T_4733) @[lsu_bus_buffer.scala 561:27] + node _T_4735 = bits(lsu_nonblock_data_unalgn, 15, 15) @[lsu_bus_buffer.scala 561:93] + node _T_4736 = bits(_T_4735, 0, 0) @[Bitwise.scala 72:15] + node _T_4737 = mux(_T_4736, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_4738 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 561:124] + node _T_4739 = cat(_T_4737, _T_4738) @[Cat.scala 29:58] + node _T_4740 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[lsu_bus_buffer.scala 562:21] + node _T_4741 = mux(_T_4717, _T_4719, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4742 = mux(_T_4721, _T_4723, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4743 = mux(_T_4726, _T_4731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4744 = mux(_T_4734, _T_4739, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4745 = mux(_T_4740, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4746 = or(_T_4741, _T_4742) @[Mux.scala 27:72] + node _T_4747 = or(_T_4746, _T_4743) @[Mux.scala 27:72] + node _T_4748 = or(_T_4747, _T_4744) @[Mux.scala 27:72] + node _T_4749 = or(_T_4748, _T_4745) @[Mux.scala 27:72] + wire _T_4750 : UInt<64> @[Mux.scala 27:72] + _T_4750 <= _T_4749 @[Mux.scala 27:72] + io.lsu_nonblock_load_data <= _T_4750 @[lsu_bus_buffer.scala 558:29] + node _T_4751 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4752 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 563:89] + node _T_4753 = and(_T_4751, _T_4752) @[lsu_bus_buffer.scala 563:73] + node _T_4754 = and(_T_4753, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4755 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4756 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 563:89] + node _T_4757 = and(_T_4755, _T_4756) @[lsu_bus_buffer.scala 563:73] + node _T_4758 = and(_T_4757, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4759 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4760 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 563:89] + node _T_4761 = and(_T_4759, _T_4760) @[lsu_bus_buffer.scala 563:73] + node _T_4762 = and(_T_4761, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4763 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 563:62] + node _T_4764 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 563:89] + node _T_4765 = and(_T_4763, _T_4764) @[lsu_bus_buffer.scala 563:73] + node _T_4766 = and(_T_4765, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:93] + node _T_4767 = or(_T_4754, _T_4758) @[lsu_bus_buffer.scala 563:153] + node _T_4768 = or(_T_4767, _T_4762) @[lsu_bus_buffer.scala 563:153] + node _T_4769 = or(_T_4768, _T_4766) @[lsu_bus_buffer.scala 563:153] + node _T_4770 = and(obuf_valid, obuf_sideeffect) @[lsu_bus_buffer.scala 563:171] + node _T_4771 = and(_T_4770, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 563:189] + node _T_4772 = or(_T_4769, _T_4771) @[lsu_bus_buffer.scala 563:157] + bus_sideeffect_pend <= _T_4772 @[lsu_bus_buffer.scala 563:23] + node _T_4773 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4774 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4775 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4776 = eq(_T_4774, _T_4775) @[lsu_bus_buffer.scala 565:37] + node _T_4777 = and(obuf_valid, _T_4776) @[lsu_bus_buffer.scala 565:19] + node _T_4778 = eq(obuf_tag0, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:73] + node _T_4779 = eq(obuf_tag1, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:107] + node _T_4780 = and(obuf_merge, _T_4779) @[lsu_bus_buffer.scala 565:95] + node _T_4781 = or(_T_4778, _T_4780) @[lsu_bus_buffer.scala 565:81] + node _T_4782 = eq(_T_4781, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4783 = and(_T_4777, _T_4782) @[lsu_bus_buffer.scala 565:59] + node _T_4784 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4785 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4786 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4787 = eq(_T_4785, _T_4786) @[lsu_bus_buffer.scala 565:37] + node _T_4788 = and(obuf_valid, _T_4787) @[lsu_bus_buffer.scala 565:19] + node _T_4789 = eq(obuf_tag0, UInt<1>("h01")) @[lsu_bus_buffer.scala 565:73] + node _T_4790 = eq(obuf_tag1, UInt<1>("h01")) @[lsu_bus_buffer.scala 565:107] + node _T_4791 = and(obuf_merge, _T_4790) @[lsu_bus_buffer.scala 565:95] + node _T_4792 = or(_T_4789, _T_4791) @[lsu_bus_buffer.scala 565:81] + node _T_4793 = eq(_T_4792, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4794 = and(_T_4788, _T_4793) @[lsu_bus_buffer.scala 565:59] + node _T_4795 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4796 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4797 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4798 = eq(_T_4796, _T_4797) @[lsu_bus_buffer.scala 565:37] + node _T_4799 = and(obuf_valid, _T_4798) @[lsu_bus_buffer.scala 565:19] + node _T_4800 = eq(obuf_tag0, UInt<2>("h02")) @[lsu_bus_buffer.scala 565:73] + node _T_4801 = eq(obuf_tag1, UInt<2>("h02")) @[lsu_bus_buffer.scala 565:107] + node _T_4802 = and(obuf_merge, _T_4801) @[lsu_bus_buffer.scala 565:95] + node _T_4803 = or(_T_4800, _T_4802) @[lsu_bus_buffer.scala 565:81] + node _T_4804 = eq(_T_4803, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4805 = and(_T_4799, _T_4804) @[lsu_bus_buffer.scala 565:59] + node _T_4806 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 564:71] + node _T_4807 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 565:31] + node _T_4808 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 565:51] + node _T_4809 = eq(_T_4807, _T_4808) @[lsu_bus_buffer.scala 565:37] + node _T_4810 = and(obuf_valid, _T_4809) @[lsu_bus_buffer.scala 565:19] + node _T_4811 = eq(obuf_tag0, UInt<2>("h03")) @[lsu_bus_buffer.scala 565:73] + node _T_4812 = eq(obuf_tag1, UInt<2>("h03")) @[lsu_bus_buffer.scala 565:107] + node _T_4813 = and(obuf_merge, _T_4812) @[lsu_bus_buffer.scala 565:95] + node _T_4814 = or(_T_4811, _T_4813) @[lsu_bus_buffer.scala 565:81] + node _T_4815 = eq(_T_4814, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:61] + node _T_4816 = and(_T_4810, _T_4815) @[lsu_bus_buffer.scala 565:59] + node _T_4817 = mux(_T_4773, _T_4783, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4818 = mux(_T_4784, _T_4794, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4819 = mux(_T_4795, _T_4805, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4820 = mux(_T_4806, _T_4816, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4821 = or(_T_4817, _T_4818) @[Mux.scala 27:72] + node _T_4822 = or(_T_4821, _T_4819) @[Mux.scala 27:72] + node _T_4823 = or(_T_4822, _T_4820) @[Mux.scala 27:72] + wire _T_4824 : UInt<1> @[Mux.scala 27:72] + _T_4824 <= _T_4823 @[Mux.scala 27:72] + bus_addr_match_pending <= _T_4824 @[lsu_bus_buffer.scala 564:26] + node _T_4825 = or(obuf_cmd_done, obuf_data_done) @[lsu_bus_buffer.scala 567:54] + node _T_4826 = mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 567:75] + node _T_4827 = and(io.lsu_axi.aw.ready, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 567:153] + node _T_4828 = mux(_T_4825, _T_4826, _T_4827) @[lsu_bus_buffer.scala 567:39] + node _T_4829 = mux(obuf_write, _T_4828, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 567:23] + bus_cmd_ready <= _T_4829 @[lsu_bus_buffer.scala 567:17] + node _T_4830 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 568:40] + bus_wcmd_sent <= _T_4830 @[lsu_bus_buffer.scala 568:17] + node _T_4831 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 569:40] + bus_wdata_sent <= _T_4831 @[lsu_bus_buffer.scala 569:18] + node _T_4832 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 570:35] + node _T_4833 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 570:70] + node _T_4834 = and(_T_4832, _T_4833) @[lsu_bus_buffer.scala 570:52] + node _T_4835 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 570:112] + node _T_4836 = or(_T_4834, _T_4835) @[lsu_bus_buffer.scala 570:89] + bus_cmd_sent <= _T_4836 @[lsu_bus_buffer.scala 570:16] + node _T_4837 = and(io.lsu_axi.r.valid, io.lsu_axi.r.ready) @[lsu_bus_buffer.scala 571:38] + bus_rsp_read <= _T_4837 @[lsu_bus_buffer.scala 571:16] + node _T_4838 = and(io.lsu_axi.b.valid, io.lsu_axi.b.ready) @[lsu_bus_buffer.scala 572:39] + bus_rsp_write <= _T_4838 @[lsu_bus_buffer.scala 572:17] + bus_rsp_read_tag <= io.lsu_axi.r.bits.id @[lsu_bus_buffer.scala 573:20] + bus_rsp_write_tag <= io.lsu_axi.b.bits.id @[lsu_bus_buffer.scala 574:21] + node _T_4839 = neq(io.lsu_axi.b.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 575:66] + node _T_4840 = and(bus_rsp_write, _T_4839) @[lsu_bus_buffer.scala 575:40] + bus_rsp_write_error <= _T_4840 @[lsu_bus_buffer.scala 575:23] + node _T_4841 = neq(io.lsu_axi.r.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 576:64] + node _T_4842 = and(bus_rsp_read, _T_4841) @[lsu_bus_buffer.scala 576:38] + bus_rsp_read_error <= _T_4842 @[lsu_bus_buffer.scala 576:22] + bus_rsp_rdata <= io.lsu_axi.r.bits.data @[lsu_bus_buffer.scala 577:17] + node _T_4843 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 580:37] + node _T_4844 = eq(obuf_cmd_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:52] + node _T_4845 = and(_T_4843, _T_4844) @[lsu_bus_buffer.scala 580:50] + node _T_4846 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:69] + node _T_4847 = and(_T_4845, _T_4846) @[lsu_bus_buffer.scala 580:67] + io.lsu_axi.aw.valid <= _T_4847 @[lsu_bus_buffer.scala 580:23] + io.lsu_axi.aw.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 581:25] + node _T_4848 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 582:75] + node _T_4849 = cat(_T_4848, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4850 = mux(obuf_sideeffect, obuf_addr, _T_4849) @[lsu_bus_buffer.scala 582:33] + io.lsu_axi.aw.bits.addr <= _T_4850 @[lsu_bus_buffer.scala 582:27] + node _T_4851 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4852 = mux(obuf_sideeffect, _T_4851, UInt<3>("h03")) @[lsu_bus_buffer.scala 583:33] + io.lsu_axi.aw.bits.size <= _T_4852 @[lsu_bus_buffer.scala 583:27] + io.lsu_axi.aw.bits.prot <= UInt<3>("h01") @[lsu_bus_buffer.scala 584:27] + node _T_4853 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 585:34] + io.lsu_axi.aw.bits.cache <= _T_4853 @[lsu_bus_buffer.scala 585:28] + node _T_4854 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 586:41] + io.lsu_axi.aw.bits.region <= _T_4854 @[lsu_bus_buffer.scala 586:29] + io.lsu_axi.aw.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 587:26] + io.lsu_axi.aw.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 588:28] + io.lsu_axi.aw.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 589:26] + io.lsu_axi.aw.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 590:27] + node _T_4855 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 592:36] + node _T_4856 = eq(obuf_data_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 592:51] + node _T_4857 = and(_T_4855, _T_4856) @[lsu_bus_buffer.scala 592:49] + node _T_4858 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 592:69] + node _T_4859 = and(_T_4857, _T_4858) @[lsu_bus_buffer.scala 592:67] + io.lsu_axi.w.valid <= _T_4859 @[lsu_bus_buffer.scala 592:22] + node _T_4860 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] + node _T_4861 = mux(_T_4860, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_4862 = and(obuf_byteen, _T_4861) @[lsu_bus_buffer.scala 593:41] + io.lsu_axi.w.bits.strb <= _T_4862 @[lsu_bus_buffer.scala 593:26] + io.lsu_axi.w.bits.data <= obuf_data @[lsu_bus_buffer.scala 594:26] + io.lsu_axi.w.bits.last <= UInt<1>("h01") @[lsu_bus_buffer.scala 595:26] + node _T_4863 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:39] + node _T_4864 = and(obuf_valid, _T_4863) @[lsu_bus_buffer.scala 597:37] + node _T_4865 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:53] + node _T_4866 = and(_T_4864, _T_4865) @[lsu_bus_buffer.scala 597:51] + node _T_4867 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 597:68] + node _T_4868 = and(_T_4866, _T_4867) @[lsu_bus_buffer.scala 597:66] + io.lsu_axi.ar.valid <= _T_4868 @[lsu_bus_buffer.scala 597:23] + io.lsu_axi.ar.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 598:25] + node _T_4869 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 599:75] + node _T_4870 = cat(_T_4869, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4871 = mux(obuf_sideeffect, obuf_addr, _T_4870) @[lsu_bus_buffer.scala 599:33] + io.lsu_axi.ar.bits.addr <= _T_4871 @[lsu_bus_buffer.scala 599:27] + node _T_4872 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4873 = mux(obuf_sideeffect, _T_4872, UInt<3>("h03")) @[lsu_bus_buffer.scala 600:33] + io.lsu_axi.ar.bits.size <= _T_4873 @[lsu_bus_buffer.scala 600:27] + io.lsu_axi.ar.bits.prot <= UInt<3>("h01") @[lsu_bus_buffer.scala 601:27] + node _T_4874 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 602:34] + io.lsu_axi.ar.bits.cache <= _T_4874 @[lsu_bus_buffer.scala 602:28] + node _T_4875 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 603:41] + io.lsu_axi.ar.bits.region <= _T_4875 @[lsu_bus_buffer.scala 603:29] + io.lsu_axi.ar.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 604:26] + io.lsu_axi.ar.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 605:28] + io.lsu_axi.ar.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 606:26] + io.lsu_axi.ar.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 607:27] + io.lsu_axi.b.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 608:22] + io.lsu_axi.r.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 609:22] + node _T_4876 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4877 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 610:137] + node _T_4878 = and(io.lsu_bus_clk_en_q, _T_4877) @[lsu_bus_buffer.scala 610:126] + node _T_4879 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 610:152] + node _T_4880 = and(_T_4878, _T_4879) @[lsu_bus_buffer.scala 610:141] + node _T_4881 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4882 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 610:137] + node _T_4883 = and(io.lsu_bus_clk_en_q, _T_4882) @[lsu_bus_buffer.scala 610:126] + node _T_4884 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 610:152] + node _T_4885 = and(_T_4883, _T_4884) @[lsu_bus_buffer.scala 610:141] + node _T_4886 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4887 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 610:137] + node _T_4888 = and(io.lsu_bus_clk_en_q, _T_4887) @[lsu_bus_buffer.scala 610:126] + node _T_4889 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 610:152] + node _T_4890 = and(_T_4888, _T_4889) @[lsu_bus_buffer.scala 610:141] + node _T_4891 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 610:93] + node _T_4892 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 610:137] + node _T_4893 = and(io.lsu_bus_clk_en_q, _T_4892) @[lsu_bus_buffer.scala 610:126] + node _T_4894 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 610:152] + node _T_4895 = and(_T_4893, _T_4894) @[lsu_bus_buffer.scala 610:141] + node _T_4896 = mux(_T_4876, _T_4880, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4897 = mux(_T_4881, _T_4885, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4898 = mux(_T_4886, _T_4890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4899 = mux(_T_4891, _T_4895, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4900 = or(_T_4896, _T_4897) @[Mux.scala 27:72] + node _T_4901 = or(_T_4900, _T_4898) @[Mux.scala 27:72] + node _T_4902 = or(_T_4901, _T_4899) @[Mux.scala 27:72] + wire _T_4903 : UInt<1> @[Mux.scala 27:72] + _T_4903 <= _T_4902 @[Mux.scala 27:72] + io.tlu_busbuff.lsu_imprecise_error_store_any <= _T_4903 @[lsu_bus_buffer.scala 610:48] + node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4905 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 611:104] + node _T_4906 = and(_T_4904, _T_4905) @[lsu_bus_buffer.scala 611:93] + node _T_4907 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 611:119] + node _T_4908 = and(_T_4906, _T_4907) @[lsu_bus_buffer.scala 611:108] + node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4910 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 611:104] + node _T_4911 = and(_T_4909, _T_4910) @[lsu_bus_buffer.scala 611:93] + node _T_4912 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 611:119] + node _T_4913 = and(_T_4911, _T_4912) @[lsu_bus_buffer.scala 611:108] + node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4915 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 611:104] + node _T_4916 = and(_T_4914, _T_4915) @[lsu_bus_buffer.scala 611:93] + node _T_4917 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 611:119] + node _T_4918 = and(_T_4916, _T_4917) @[lsu_bus_buffer.scala 611:108] + node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 611:82] + node _T_4920 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 611:104] + node _T_4921 = and(_T_4919, _T_4920) @[lsu_bus_buffer.scala 611:93] + node _T_4922 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 611:119] + node _T_4923 = and(_T_4921, _T_4922) @[lsu_bus_buffer.scala 611:108] + node _T_4924 = mux(_T_4908, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4925 = mux(_T_4913, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4926 = mux(_T_4918, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4927 = mux(_T_4923, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4928 = or(_T_4924, _T_4925) @[Mux.scala 27:72] + node _T_4929 = or(_T_4928, _T_4926) @[Mux.scala 27:72] + node _T_4930 = or(_T_4929, _T_4927) @[Mux.scala 27:72] + wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72] + lsu_imprecise_error_store_tag <= _T_4930 @[Mux.scala 27:72] + node _T_4931 = eq(io.tlu_busbuff.lsu_imprecise_error_store_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 613:97] + node _T_4932 = and(io.dctl_busbuff.lsu_nonblock_load_data_error, _T_4931) @[lsu_bus_buffer.scala 613:95] + io.tlu_busbuff.lsu_imprecise_error_load_any <= _T_4932 @[lsu_bus_buffer.scala 613:47] + node _T_4933 = mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.dctl_busbuff.lsu_nonblock_load_data_tag]) @[lsu_bus_buffer.scala 614:53] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= _T_4933 @[lsu_bus_buffer.scala 614:47] + node _T_4934 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 620:59] + node _T_4935 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 620:104] + node _T_4936 = or(_T_4934, _T_4935) @[lsu_bus_buffer.scala 620:82] + node _T_4937 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 620:149] + node _T_4938 = or(_T_4936, _T_4937) @[lsu_bus_buffer.scala 620:126] + io.tlu_busbuff.lsu_pmu_bus_trxn <= _T_4938 @[lsu_bus_buffer.scala 620:35] + node _T_4939 = and(io.lsu_busreq_r, io.ldst_dual_r) @[lsu_bus_buffer.scala 621:60] + node _T_4940 = and(_T_4939, io.lsu_commit_r) @[lsu_bus_buffer.scala 621:77] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= _T_4940 @[lsu_bus_buffer.scala 621:41] + node _T_4941 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[lsu_bus_buffer.scala 622:83] + io.tlu_busbuff.lsu_pmu_bus_error <= _T_4941 @[lsu_bus_buffer.scala 622:36] + node _T_4942 = eq(io.lsu_axi.aw.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:61] + node _T_4943 = and(io.lsu_axi.aw.valid, _T_4942) @[lsu_bus_buffer.scala 624:59] + node _T_4944 = eq(io.lsu_axi.w.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:107] + node _T_4945 = and(io.lsu_axi.w.valid, _T_4944) @[lsu_bus_buffer.scala 624:105] + node _T_4946 = or(_T_4943, _T_4945) @[lsu_bus_buffer.scala 624:83] + node _T_4947 = eq(io.lsu_axi.ar.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:153] + node _T_4948 = and(io.lsu_axi.ar.valid, _T_4947) @[lsu_bus_buffer.scala 624:151] + node _T_4949 = or(_T_4946, _T_4948) @[lsu_bus_buffer.scala 624:128] + io.tlu_busbuff.lsu_pmu_bus_busy <= _T_4949 @[lsu_bus_buffer.scala 624:35] + reg _T_4950 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 626:49] + _T_4950 <= WrPtr0_m @[lsu_bus_buffer.scala 626:49] + WrPtr0_r <= _T_4950 @[lsu_bus_buffer.scala 626:12] + reg _T_4951 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 627:49] + _T_4951 <= WrPtr1_m @[lsu_bus_buffer.scala 627:49] + WrPtr1_r <= _T_4951 @[lsu_bus_buffer.scala 627:12] + node _T_4952 = eq(io.flush_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 628:75] + node _T_4953 = and(io.lsu_busreq_m, _T_4952) @[lsu_bus_buffer.scala 628:73] + node _T_4954 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 628:89] + node _T_4955 = and(_T_4953, _T_4954) @[lsu_bus_buffer.scala 628:87] + reg _T_4956 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 628:56] + _T_4956 <= _T_4955 @[lsu_bus_buffer.scala 628:56] + io.lsu_busreq_r <= _T_4956 @[lsu_bus_buffer.scala 628:19] + reg _T_4957 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 629:66] + _T_4957 <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_buffer.scala 629:66] + lsu_nonblock_load_valid_r <= _T_4957 @[lsu_bus_buffer.scala 629:29] + + module lsu_bus_intf : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip clk_override : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip active_clk : Clock, flip lsu_busm_clk : Clock, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, bus_read_data_m : UInt<32>, lsu_nonblock_load_data : UInt<32>, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, flip lsu_bus_clk_en : UInt<1>} + + wire lsu_bus_clk_en_q : UInt<1> + lsu_bus_clk_en_q <= UInt<1>("h00") + wire ldst_byteen_m : UInt<4> + ldst_byteen_m <= UInt<1>("h00") + wire ldst_byteen_r : UInt<4> + ldst_byteen_r <= UInt<1>("h00") + wire ldst_byteen_ext_m : UInt<8> + ldst_byteen_ext_m <= UInt<1>("h00") + wire ldst_byteen_ext_r : UInt<8> + ldst_byteen_ext_r <= UInt<1>("h00") + wire ldst_byteen_hi_m : UInt<4> + ldst_byteen_hi_m <= UInt<1>("h00") + wire ldst_byteen_hi_r : UInt<4> + ldst_byteen_hi_r <= UInt<1>("h00") + wire ldst_byteen_lo_m : UInt<4> + ldst_byteen_lo_m <= UInt<1>("h00") + wire ldst_byteen_lo_r : UInt<4> + ldst_byteen_lo_r <= UInt<1>("h00") + wire is_sideeffects_r : UInt<1> + is_sideeffects_r <= UInt<1>("h00") + wire store_data_ext_r : UInt<64> + store_data_ext_r <= UInt<1>("h00") + wire store_data_hi_r : UInt<32> + store_data_hi_r <= UInt<1>("h00") + wire store_data_lo_r : UInt<32> + store_data_lo_r <= UInt<1>("h00") + wire addr_match_dw_lo_r_m : UInt<1> + addr_match_dw_lo_r_m <= UInt<1>("h00") + wire addr_match_word_lo_r_m : UInt<1> + addr_match_word_lo_r_m <= UInt<1>("h00") + wire no_word_merge_r : UInt<1> + no_word_merge_r <= UInt<1>("h00") + wire no_dword_merge_r : UInt<1> + no_dword_merge_r <= UInt<1>("h00") + wire ld_addr_rhit_lo_lo : UInt<1> + ld_addr_rhit_lo_lo <= UInt<1>("h00") + wire ld_addr_rhit_hi_lo : UInt<1> + ld_addr_rhit_hi_lo <= UInt<1>("h00") + wire ld_addr_rhit_lo_hi : UInt<1> + ld_addr_rhit_lo_hi <= UInt<1>("h00") + wire ld_addr_rhit_hi_hi : UInt<1> + ld_addr_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_rhit_lo_lo : UInt<4> + ld_byte_rhit_lo_lo <= UInt<1>("h00") + wire ld_byte_rhit_hi_lo : UInt<4> + ld_byte_rhit_hi_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo_hi : UInt<4> + ld_byte_rhit_lo_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi_hi : UInt<4> + ld_byte_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_hit_lo : UInt<4> + ld_byte_hit_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo : UInt<4> + ld_byte_rhit_lo <= UInt<1>("h00") + wire ld_byte_hit_hi : UInt<4> + ld_byte_hit_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi : UInt<4> + ld_byte_rhit_hi <= UInt<1>("h00") + wire ld_fwddata_rpipe_lo : UInt<32> + ld_fwddata_rpipe_lo <= UInt<1>("h00") + wire ld_fwddata_rpipe_hi : UInt<32> + ld_fwddata_rpipe_hi <= UInt<1>("h00") + wire ld_byte_hit_buf_lo : UInt<4> + ld_byte_hit_buf_lo <= UInt<1>("h00") + wire ld_byte_hit_buf_hi : UInt<4> + ld_byte_hit_buf_hi <= UInt<1>("h00") + wire ld_fwddata_buf_lo : UInt<32> + ld_fwddata_buf_lo <= UInt<1>("h00") + wire ld_fwddata_buf_hi : UInt<32> + ld_fwddata_buf_hi <= UInt<1>("h00") + wire ld_fwddata_lo : UInt<64> + ld_fwddata_lo <= UInt<1>("h00") + wire ld_fwddata_hi : UInt<64> + ld_fwddata_hi <= UInt<1>("h00") + wire ld_fwddata_m : UInt<64> + ld_fwddata_m <= UInt<1>("h00") + wire ld_full_hit_hi_m : UInt<1> + ld_full_hit_hi_m <= UInt<1>("h01") + wire ld_full_hit_lo_m : UInt<1> + ld_full_hit_lo_m <= UInt<1>("h01") + wire ld_full_hit_m : UInt<1> + ld_full_hit_m <= UInt<1>("h00") + inst bus_buffer of lsu_bus_buffer @[lsu_bus_intf.scala 100:39] + bus_buffer.clock <= clock + bus_buffer.reset <= reset + bus_buffer.io.scan_mode <= io.scan_mode @[lsu_bus_intf.scala 102:29] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_store_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_load_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_busy <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_error <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_error @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_trxn <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu_bus_intf.scala 103:18] + bus_buffer.io.clk_override <= io.clk_override @[lsu_bus_intf.scala 104:51] + bus_buffer.io.lsu_bus_obuf_c1_clken <= io.lsu_bus_obuf_c1_clken @[lsu_bus_intf.scala 105:51] + bus_buffer.io.lsu_busm_clken <= io.lsu_busm_clken @[lsu_bus_intf.scala 106:51] + bus_buffer.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu_bus_intf.scala 107:51] + bus_buffer.io.lsu_c2_r_clk <= io.lsu_c2_r_clk @[lsu_bus_intf.scala 108:51] + bus_buffer.io.lsu_bus_ibuf_c1_clk <= io.lsu_bus_ibuf_c1_clk @[lsu_bus_intf.scala 109:51] + bus_buffer.io.lsu_bus_obuf_c1_clk <= io.lsu_bus_obuf_c1_clk @[lsu_bus_intf.scala 110:51] + bus_buffer.io.lsu_bus_buf_c1_clk <= io.lsu_bus_buf_c1_clk @[lsu_bus_intf.scala 111:51] + bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[lsu_bus_intf.scala 112:51] + bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[lsu_bus_intf.scala 113:51] + bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu_bus_intf.scala 114:51] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.store <= io.lsu_pkt_m.bits.store @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.load <= io.lsu_pkt_m.bits.load @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.word <= io.lsu_pkt_m.bits.word @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.half <= io.lsu_pkt_m.bits.half @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.by <= io.lsu_pkt_m.bits.by @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[lsu_bus_intf.scala 117:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_m <= io.lsu_pkt_r.bits.store_data_bypass_m @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.load_ldst_bypass_d <= io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_d <= io.lsu_pkt_r.bits.store_data_bypass_d @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.dma <= io.lsu_pkt_r.bits.dma @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.unsign <= io.lsu_pkt_r.bits.unsign @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.store <= io.lsu_pkt_r.bits.store @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.load <= io.lsu_pkt_r.bits.load @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.dword <= io.lsu_pkt_r.bits.dword @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.word <= io.lsu_pkt_r.bits.word @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.half <= io.lsu_pkt_r.bits.half @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.by <= io.lsu_pkt_r.bits.by @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.stack <= io.lsu_pkt_r.bits.stack @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.bits.fast_int <= io.lsu_pkt_r.bits.fast_int @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[lsu_bus_intf.scala 118:27] + bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[lsu_bus_intf.scala 121:51] + bus_buffer.io.end_addr_m <= io.end_addr_m @[lsu_bus_intf.scala 122:51] + bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[lsu_bus_intf.scala 123:51] + bus_buffer.io.end_addr_r <= io.end_addr_r @[lsu_bus_intf.scala 124:51] + bus_buffer.io.store_data_r <= io.store_data_r @[lsu_bus_intf.scala 125:51] + bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[lsu_bus_intf.scala 127:51] + bus_buffer.io.flush_m_up <= io.flush_m_up @[lsu_bus_intf.scala 128:51] + bus_buffer.io.flush_r <= io.flush_r @[lsu_bus_intf.scala 129:51] + bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[lsu_bus_intf.scala 130:51] + bus_buffer.io.lsu_axi.r.bits.last <= io.axi.r.bits.last @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.resp <= io.axi.r.bits.resp @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.data <= io.axi.r.bits.data @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.bits.id <= io.axi.r.bits.id @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.r.valid <= io.axi.r.valid @[lsu_bus_intf.scala 131:51] + io.axi.r.ready <= bus_buffer.io.lsu_axi.r.ready @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.qos <= bus_buffer.io.lsu_axi.ar.bits.qos @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.prot <= bus_buffer.io.lsu_axi.ar.bits.prot @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.cache <= bus_buffer.io.lsu_axi.ar.bits.cache @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.lock <= bus_buffer.io.lsu_axi.ar.bits.lock @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.burst <= bus_buffer.io.lsu_axi.ar.bits.burst @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.size <= bus_buffer.io.lsu_axi.ar.bits.size @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.len <= bus_buffer.io.lsu_axi.ar.bits.len @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.region <= bus_buffer.io.lsu_axi.ar.bits.region @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.addr <= bus_buffer.io.lsu_axi.ar.bits.addr @[lsu_bus_intf.scala 131:51] + io.axi.ar.bits.id <= bus_buffer.io.lsu_axi.ar.bits.id @[lsu_bus_intf.scala 131:51] + io.axi.ar.valid <= bus_buffer.io.lsu_axi.ar.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.ar.ready <= io.axi.ar.ready @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.bits.id <= io.axi.b.bits.id @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.bits.resp <= io.axi.b.bits.resp @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.b.valid <= io.axi.b.valid @[lsu_bus_intf.scala 131:51] + io.axi.b.ready <= bus_buffer.io.lsu_axi.b.ready @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.last <= bus_buffer.io.lsu_axi.w.bits.last @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.strb <= bus_buffer.io.lsu_axi.w.bits.strb @[lsu_bus_intf.scala 131:51] + io.axi.w.bits.data <= bus_buffer.io.lsu_axi.w.bits.data @[lsu_bus_intf.scala 131:51] + io.axi.w.valid <= bus_buffer.io.lsu_axi.w.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.w.ready <= io.axi.w.ready @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.qos <= bus_buffer.io.lsu_axi.aw.bits.qos @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.prot <= bus_buffer.io.lsu_axi.aw.bits.prot @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.cache <= bus_buffer.io.lsu_axi.aw.bits.cache @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.lock <= bus_buffer.io.lsu_axi.aw.bits.lock @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.burst <= bus_buffer.io.lsu_axi.aw.bits.burst @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.size <= bus_buffer.io.lsu_axi.aw.bits.size @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.len <= bus_buffer.io.lsu_axi.aw.bits.len @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.region <= bus_buffer.io.lsu_axi.aw.bits.region @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.addr <= bus_buffer.io.lsu_axi.aw.bits.addr @[lsu_bus_intf.scala 131:51] + io.axi.aw.bits.id <= bus_buffer.io.lsu_axi.aw.bits.id @[lsu_bus_intf.scala 131:51] + io.axi.aw.valid <= bus_buffer.io.lsu_axi.aw.valid @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_axi.aw.ready <= io.axi.aw.ready @[lsu_bus_intf.scala 131:51] + bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 132:51] + io.lsu_nonblock_load_data <= bus_buffer.io.lsu_nonblock_load_data @[lsu_bus_intf.scala 133:29] + io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[lsu_bus_intf.scala 134:38] + io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[lsu_bus_intf.scala 135:38] + io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[lsu_bus_intf.scala 136:38] + io.lsu_bus_buffer_empty_any <= bus_buffer.io.lsu_bus_buffer_empty_any @[lsu_bus_intf.scala 137:38] + ld_byte_hit_buf_lo <= bus_buffer.io.ld_byte_hit_buf_lo @[lsu_bus_intf.scala 139:38] + ld_byte_hit_buf_hi <= bus_buffer.io.ld_byte_hit_buf_hi @[lsu_bus_intf.scala 140:38] + ld_fwddata_buf_lo <= bus_buffer.io.ld_fwddata_buf_lo @[lsu_bus_intf.scala 141:38] + ld_fwddata_buf_hi <= bus_buffer.io.ld_fwddata_buf_hi @[lsu_bus_intf.scala 142:38] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_data_error <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu_bus_intf.scala 143:19] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_intf.scala 143:19] + bus_buffer.io.no_word_merge_r <= no_word_merge_r @[lsu_bus_intf.scala 144:51] + bus_buffer.io.no_dword_merge_r <= no_dword_merge_r @[lsu_bus_intf.scala 145:51] + bus_buffer.io.is_sideeffects_r <= is_sideeffects_r @[lsu_bus_intf.scala 146:51] + bus_buffer.io.ldst_dual_d <= io.ldst_dual_d @[lsu_bus_intf.scala 147:51] + bus_buffer.io.ldst_dual_m <= io.ldst_dual_m @[lsu_bus_intf.scala 148:51] + bus_buffer.io.ldst_dual_r <= io.ldst_dual_r @[lsu_bus_intf.scala 149:51] + bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[lsu_bus_intf.scala 150:51] + bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[lsu_bus_intf.scala 151:51] + bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[lsu_bus_intf.scala 152:51] + node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[lsu_bus_intf.scala 154:63] + node _T_1 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[lsu_bus_intf.scala 154:107] + node _T_2 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[lsu_bus_intf.scala 154:148] + node _T_3 = mux(_T, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4 = mux(_T_1, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_2, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = or(_T_3, _T_4) @[Mux.scala 27:72] + node _T_7 = or(_T_6, _T_5) @[Mux.scala 27:72] + wire _T_8 : UInt<4> @[Mux.scala 27:72] + _T_8 <= _T_7 @[Mux.scala 27:72] + ldst_byteen_m <= _T_8 @[lsu_bus_intf.scala 154:27] + node _T_9 = bits(io.lsu_addr_r, 31, 3) @[lsu_bus_intf.scala 155:44] + node _T_10 = bits(io.lsu_addr_m, 31, 3) @[lsu_bus_intf.scala 155:68] + node _T_11 = eq(_T_9, _T_10) @[lsu_bus_intf.scala 155:51] + addr_match_dw_lo_r_m <= _T_11 @[lsu_bus_intf.scala 155:27] + node _T_12 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_intf.scala 156:68] + node _T_13 = bits(io.lsu_addr_m, 2, 2) @[lsu_bus_intf.scala 156:85] + node _T_14 = xor(_T_12, _T_13) @[lsu_bus_intf.scala 156:71] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[lsu_bus_intf.scala 156:53] + node _T_16 = and(addr_match_dw_lo_r_m, _T_15) @[lsu_bus_intf.scala 156:51] + addr_match_word_lo_r_m <= _T_16 @[lsu_bus_intf.scala 156:27] + node _T_17 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 157:48] + node _T_18 = and(io.lsu_busreq_r, _T_17) @[lsu_bus_intf.scala 157:46] + node _T_19 = and(_T_18, io.lsu_busreq_m) @[lsu_bus_intf.scala 157:64] + node _T_20 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 157:110] + node _T_21 = or(io.lsu_pkt_m.bits.load, _T_20) @[lsu_bus_intf.scala 157:108] + node _T_22 = and(_T_19, _T_21) @[lsu_bus_intf.scala 157:82] + no_word_merge_r <= _T_22 @[lsu_bus_intf.scala 157:27] + node _T_23 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 158:48] + node _T_24 = and(io.lsu_busreq_r, _T_23) @[lsu_bus_intf.scala 158:46] + node _T_25 = and(_T_24, io.lsu_busreq_m) @[lsu_bus_intf.scala 158:64] + node _T_26 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 158:110] + node _T_27 = or(io.lsu_pkt_m.bits.load, _T_26) @[lsu_bus_intf.scala 158:108] + node _T_28 = and(_T_25, _T_27) @[lsu_bus_intf.scala 158:82] + no_dword_merge_r <= _T_28 @[lsu_bus_intf.scala 158:27] + node _T_29 = bits(ldst_byteen_m, 3, 0) @[lsu_bus_intf.scala 160:43] + node _T_30 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 160:65] + node _T_31 = dshl(_T_29, _T_30) @[lsu_bus_intf.scala 160:49] + ldst_byteen_ext_m <= _T_31 @[lsu_bus_intf.scala 160:27] + node _T_32 = bits(ldst_byteen_r, 3, 0) @[lsu_bus_intf.scala 161:43] + node _T_33 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 161:65] + node _T_34 = dshl(_T_32, _T_33) @[lsu_bus_intf.scala 161:49] + ldst_byteen_ext_r <= _T_34 @[lsu_bus_intf.scala 161:27] + node _T_35 = bits(io.store_data_r, 31, 0) @[lsu_bus_intf.scala 162:45] + node _T_36 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 162:72] + node _T_37 = cat(_T_36, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_38 = dshl(_T_35, _T_37) @[lsu_bus_intf.scala 162:52] + store_data_ext_r <= _T_38 @[lsu_bus_intf.scala 162:27] + node _T_39 = bits(ldst_byteen_ext_m, 7, 4) @[lsu_bus_intf.scala 163:47] + ldst_byteen_hi_m <= _T_39 @[lsu_bus_intf.scala 163:27] + node _T_40 = bits(ldst_byteen_ext_m, 3, 0) @[lsu_bus_intf.scala 164:47] + ldst_byteen_lo_m <= _T_40 @[lsu_bus_intf.scala 164:27] + node _T_41 = bits(ldst_byteen_ext_r, 7, 4) @[lsu_bus_intf.scala 165:47] + ldst_byteen_hi_r <= _T_41 @[lsu_bus_intf.scala 165:27] + node _T_42 = bits(ldst_byteen_ext_r, 3, 0) @[lsu_bus_intf.scala 166:47] + ldst_byteen_lo_r <= _T_42 @[lsu_bus_intf.scala 166:27] + node _T_43 = bits(store_data_ext_r, 63, 32) @[lsu_bus_intf.scala 168:46] + store_data_hi_r <= _T_43 @[lsu_bus_intf.scala 168:27] + node _T_44 = bits(store_data_ext_r, 31, 0) @[lsu_bus_intf.scala 169:46] + store_data_lo_r <= _T_44 @[lsu_bus_intf.scala 169:27] + node _T_45 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 170:44] + node _T_46 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 170:68] + node _T_47 = eq(_T_45, _T_46) @[lsu_bus_intf.scala 170:51] + node _T_48 = and(_T_47, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 170:76] + node _T_49 = and(_T_48, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 170:97] + node _T_50 = and(_T_49, io.lsu_busreq_m) @[lsu_bus_intf.scala 170:123] + ld_addr_rhit_lo_lo <= _T_50 @[lsu_bus_intf.scala 170:27] + node _T_51 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 171:44] + node _T_52 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 171:68] + node _T_53 = eq(_T_51, _T_52) @[lsu_bus_intf.scala 171:51] + node _T_54 = and(_T_53, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 171:76] + node _T_55 = and(_T_54, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 171:97] + node _T_56 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_intf.scala 171:123] + ld_addr_rhit_lo_hi <= _T_56 @[lsu_bus_intf.scala 171:27] + node _T_57 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 172:44] + node _T_58 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 172:68] + node _T_59 = eq(_T_57, _T_58) @[lsu_bus_intf.scala 172:51] + node _T_60 = and(_T_59, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 172:76] + node _T_61 = and(_T_60, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 172:97] + node _T_62 = and(_T_61, io.lsu_busreq_m) @[lsu_bus_intf.scala 172:123] + ld_addr_rhit_hi_lo <= _T_62 @[lsu_bus_intf.scala 172:27] + node _T_63 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 173:44] + node _T_64 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 173:68] + node _T_65 = eq(_T_63, _T_64) @[lsu_bus_intf.scala 173:51] + node _T_66 = and(_T_65, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 173:76] + node _T_67 = and(_T_66, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 173:97] + node _T_68 = and(_T_67, io.lsu_busreq_m) @[lsu_bus_intf.scala 173:123] + ld_addr_rhit_hi_hi <= _T_68 @[lsu_bus_intf.scala 173:27] + node _T_69 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 175:88] + node _T_70 = and(ld_addr_rhit_lo_lo, _T_69) @[lsu_bus_intf.scala 175:70] + node _T_71 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 175:110] + node _T_72 = and(_T_70, _T_71) @[lsu_bus_intf.scala 175:92] + node _T_73 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 175:88] + node _T_74 = and(ld_addr_rhit_lo_lo, _T_73) @[lsu_bus_intf.scala 175:70] + node _T_75 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 175:110] + node _T_76 = and(_T_74, _T_75) @[lsu_bus_intf.scala 175:92] + node _T_77 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 175:88] + node _T_78 = and(ld_addr_rhit_lo_lo, _T_77) @[lsu_bus_intf.scala 175:70] + node _T_79 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 175:110] + node _T_80 = and(_T_78, _T_79) @[lsu_bus_intf.scala 175:92] + node _T_81 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 175:88] + node _T_82 = and(ld_addr_rhit_lo_lo, _T_81) @[lsu_bus_intf.scala 175:70] + node _T_83 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 175:110] + node _T_84 = and(_T_82, _T_83) @[lsu_bus_intf.scala 175:92] + node _T_85 = cat(_T_84, _T_80) @[Cat.scala 29:58] + node _T_86 = cat(_T_85, _T_76) @[Cat.scala 29:58] + node _T_87 = cat(_T_86, _T_72) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_87 @[lsu_bus_intf.scala 175:27] + node _T_88 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 176:88] + node _T_89 = and(ld_addr_rhit_lo_hi, _T_88) @[lsu_bus_intf.scala 176:70] + node _T_90 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 176:110] + node _T_91 = and(_T_89, _T_90) @[lsu_bus_intf.scala 176:92] + node _T_92 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 176:88] + node _T_93 = and(ld_addr_rhit_lo_hi, _T_92) @[lsu_bus_intf.scala 176:70] + node _T_94 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 176:110] + node _T_95 = and(_T_93, _T_94) @[lsu_bus_intf.scala 176:92] + node _T_96 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 176:88] + node _T_97 = and(ld_addr_rhit_lo_hi, _T_96) @[lsu_bus_intf.scala 176:70] + node _T_98 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 176:110] + node _T_99 = and(_T_97, _T_98) @[lsu_bus_intf.scala 176:92] + node _T_100 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 176:88] + node _T_101 = and(ld_addr_rhit_lo_hi, _T_100) @[lsu_bus_intf.scala 176:70] + node _T_102 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 176:110] + node _T_103 = and(_T_101, _T_102) @[lsu_bus_intf.scala 176:92] + node _T_104 = cat(_T_103, _T_99) @[Cat.scala 29:58] + node _T_105 = cat(_T_104, _T_95) @[Cat.scala 29:58] + node _T_106 = cat(_T_105, _T_91) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_106 @[lsu_bus_intf.scala 176:27] + node _T_107 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 177:88] + node _T_108 = and(ld_addr_rhit_hi_lo, _T_107) @[lsu_bus_intf.scala 177:70] + node _T_109 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 177:110] + node _T_110 = and(_T_108, _T_109) @[lsu_bus_intf.scala 177:92] + node _T_111 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 177:88] + node _T_112 = and(ld_addr_rhit_hi_lo, _T_111) @[lsu_bus_intf.scala 177:70] + node _T_113 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 177:110] + node _T_114 = and(_T_112, _T_113) @[lsu_bus_intf.scala 177:92] + node _T_115 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 177:88] + node _T_116 = and(ld_addr_rhit_hi_lo, _T_115) @[lsu_bus_intf.scala 177:70] + node _T_117 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 177:110] + node _T_118 = and(_T_116, _T_117) @[lsu_bus_intf.scala 177:92] + node _T_119 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 177:88] + node _T_120 = and(ld_addr_rhit_hi_lo, _T_119) @[lsu_bus_intf.scala 177:70] + node _T_121 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 177:110] + node _T_122 = and(_T_120, _T_121) @[lsu_bus_intf.scala 177:92] + node _T_123 = cat(_T_122, _T_118) @[Cat.scala 29:58] + node _T_124 = cat(_T_123, _T_114) @[Cat.scala 29:58] + node _T_125 = cat(_T_124, _T_110) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_125 @[lsu_bus_intf.scala 177:27] + node _T_126 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 178:88] + node _T_127 = and(ld_addr_rhit_hi_hi, _T_126) @[lsu_bus_intf.scala 178:70] + node _T_128 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 178:110] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_intf.scala 178:92] + node _T_130 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 178:88] + node _T_131 = and(ld_addr_rhit_hi_hi, _T_130) @[lsu_bus_intf.scala 178:70] + node _T_132 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 178:110] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_intf.scala 178:92] + node _T_134 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 178:88] + node _T_135 = and(ld_addr_rhit_hi_hi, _T_134) @[lsu_bus_intf.scala 178:70] + node _T_136 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 178:110] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_intf.scala 178:92] + node _T_138 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 178:88] + node _T_139 = and(ld_addr_rhit_hi_hi, _T_138) @[lsu_bus_intf.scala 178:70] + node _T_140 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 178:110] + node _T_141 = and(_T_139, _T_140) @[lsu_bus_intf.scala 178:92] + node _T_142 = cat(_T_141, _T_137) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_133) @[Cat.scala 29:58] + node _T_144 = cat(_T_143, _T_129) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_144 @[lsu_bus_intf.scala 178:27] + node _T_145 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 180:69] + node _T_146 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 180:93] + node _T_147 = or(_T_145, _T_146) @[lsu_bus_intf.scala 180:73] + node _T_148 = bits(ld_byte_hit_buf_lo, 0, 0) @[lsu_bus_intf.scala 180:117] + node _T_149 = or(_T_147, _T_148) @[lsu_bus_intf.scala 180:97] + node _T_150 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 180:69] + node _T_151 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 180:93] + node _T_152 = or(_T_150, _T_151) @[lsu_bus_intf.scala 180:73] + node _T_153 = bits(ld_byte_hit_buf_lo, 1, 1) @[lsu_bus_intf.scala 180:117] + node _T_154 = or(_T_152, _T_153) @[lsu_bus_intf.scala 180:97] + node _T_155 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 180:69] + node _T_156 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 180:93] + node _T_157 = or(_T_155, _T_156) @[lsu_bus_intf.scala 180:73] + node _T_158 = bits(ld_byte_hit_buf_lo, 2, 2) @[lsu_bus_intf.scala 180:117] + node _T_159 = or(_T_157, _T_158) @[lsu_bus_intf.scala 180:97] + node _T_160 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 180:69] + node _T_161 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 180:93] + node _T_162 = or(_T_160, _T_161) @[lsu_bus_intf.scala 180:73] + node _T_163 = bits(ld_byte_hit_buf_lo, 3, 3) @[lsu_bus_intf.scala 180:117] + node _T_164 = or(_T_162, _T_163) @[lsu_bus_intf.scala 180:97] + node _T_165 = cat(_T_164, _T_159) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, _T_154) @[Cat.scala 29:58] + node _T_167 = cat(_T_166, _T_149) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_167 @[lsu_bus_intf.scala 180:27] + node _T_168 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 181:69] + node _T_169 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 181:93] + node _T_170 = or(_T_168, _T_169) @[lsu_bus_intf.scala 181:73] + node _T_171 = bits(ld_byte_hit_buf_hi, 0, 0) @[lsu_bus_intf.scala 181:117] + node _T_172 = or(_T_170, _T_171) @[lsu_bus_intf.scala 181:97] + node _T_173 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 181:69] + node _T_174 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 181:93] + node _T_175 = or(_T_173, _T_174) @[lsu_bus_intf.scala 181:73] + node _T_176 = bits(ld_byte_hit_buf_hi, 1, 1) @[lsu_bus_intf.scala 181:117] + node _T_177 = or(_T_175, _T_176) @[lsu_bus_intf.scala 181:97] + node _T_178 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 181:69] + node _T_179 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 181:93] + node _T_180 = or(_T_178, _T_179) @[lsu_bus_intf.scala 181:73] + node _T_181 = bits(ld_byte_hit_buf_hi, 2, 2) @[lsu_bus_intf.scala 181:117] + node _T_182 = or(_T_180, _T_181) @[lsu_bus_intf.scala 181:97] + node _T_183 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 181:69] + node _T_184 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 181:93] + node _T_185 = or(_T_183, _T_184) @[lsu_bus_intf.scala 181:73] + node _T_186 = bits(ld_byte_hit_buf_hi, 3, 3) @[lsu_bus_intf.scala 181:117] + node _T_187 = or(_T_185, _T_186) @[lsu_bus_intf.scala 181:97] + node _T_188 = cat(_T_187, _T_182) @[Cat.scala 29:58] + node _T_189 = cat(_T_188, _T_177) @[Cat.scala 29:58] + node _T_190 = cat(_T_189, _T_172) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_190 @[lsu_bus_intf.scala 181:27] + node _T_191 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 182:69] + node _T_192 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 182:93] + node _T_193 = or(_T_191, _T_192) @[lsu_bus_intf.scala 182:73] + node _T_194 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 182:69] + node _T_195 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 182:93] + node _T_196 = or(_T_194, _T_195) @[lsu_bus_intf.scala 182:73] + node _T_197 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 182:69] + node _T_198 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 182:93] + node _T_199 = or(_T_197, _T_198) @[lsu_bus_intf.scala 182:73] + node _T_200 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 182:69] + node _T_201 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 182:93] + node _T_202 = or(_T_200, _T_201) @[lsu_bus_intf.scala 182:73] + node _T_203 = cat(_T_202, _T_199) @[Cat.scala 29:58] + node _T_204 = cat(_T_203, _T_196) @[Cat.scala 29:58] + node _T_205 = cat(_T_204, _T_193) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_205 @[lsu_bus_intf.scala 182:27] + node _T_206 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 183:69] + node _T_207 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 183:93] + node _T_208 = or(_T_206, _T_207) @[lsu_bus_intf.scala 183:73] + node _T_209 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 183:69] + node _T_210 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 183:93] + node _T_211 = or(_T_209, _T_210) @[lsu_bus_intf.scala 183:73] + node _T_212 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 183:69] + node _T_213 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 183:93] + node _T_214 = or(_T_212, _T_213) @[lsu_bus_intf.scala 183:73] + node _T_215 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 183:69] + node _T_216 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 183:93] + node _T_217 = or(_T_215, _T_216) @[lsu_bus_intf.scala 183:73] + node _T_218 = cat(_T_217, _T_214) @[Cat.scala 29:58] + node _T_219 = cat(_T_218, _T_211) @[Cat.scala 29:58] + node _T_220 = cat(_T_219, _T_208) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_220 @[lsu_bus_intf.scala 183:27] + node _T_221 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 184:79] + node _T_222 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 184:101] + node _T_223 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 184:136] + node _T_224 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 184:158] + node _T_225 = mux(_T_221, _T_222, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_226 = mux(_T_223, _T_224, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_227 = or(_T_225, _T_226) @[Mux.scala 27:72] + wire _T_228 : UInt<8> @[Mux.scala 27:72] + _T_228 <= _T_227 @[Mux.scala 27:72] + node _T_229 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 184:79] + node _T_230 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 184:101] + node _T_231 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 184:136] + node _T_232 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 184:158] + node _T_233 = mux(_T_229, _T_230, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_234 = mux(_T_231, _T_232, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_235 = or(_T_233, _T_234) @[Mux.scala 27:72] + wire _T_236 : UInt<8> @[Mux.scala 27:72] + _T_236 <= _T_235 @[Mux.scala 27:72] + node _T_237 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 184:79] + node _T_238 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 184:101] + node _T_239 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 184:136] + node _T_240 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 184:158] + node _T_241 = mux(_T_237, _T_238, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_242 = mux(_T_239, _T_240, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_243 = or(_T_241, _T_242) @[Mux.scala 27:72] + wire _T_244 : UInt<8> @[Mux.scala 27:72] + _T_244 <= _T_243 @[Mux.scala 27:72] + node _T_245 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 184:79] + node _T_246 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 184:101] + node _T_247 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 184:136] + node _T_248 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 184:158] + node _T_249 = mux(_T_245, _T_246, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_250 = mux(_T_247, _T_248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_251 = or(_T_249, _T_250) @[Mux.scala 27:72] + wire _T_252 : UInt<8> @[Mux.scala 27:72] + _T_252 <= _T_251 @[Mux.scala 27:72] + node _T_253 = cat(_T_252, _T_244) @[Cat.scala 29:58] + node _T_254 = cat(_T_253, _T_236) @[Cat.scala 29:58] + node _T_255 = cat(_T_254, _T_228) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_255 @[lsu_bus_intf.scala 184:27] + node _T_256 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 185:79] + node _T_257 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 185:101] + node _T_258 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 185:136] + node _T_259 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 185:158] + node _T_260 = mux(_T_256, _T_257, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = or(_T_260, _T_261) @[Mux.scala 27:72] + wire _T_263 : UInt<8> @[Mux.scala 27:72] + _T_263 <= _T_262 @[Mux.scala 27:72] + node _T_264 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 185:79] + node _T_265 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 185:101] + node _T_266 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 185:136] + node _T_267 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 185:158] + node _T_268 = mux(_T_264, _T_265, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_269 = mux(_T_266, _T_267, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_270 = or(_T_268, _T_269) @[Mux.scala 27:72] + wire _T_271 : UInt<8> @[Mux.scala 27:72] + _T_271 <= _T_270 @[Mux.scala 27:72] + node _T_272 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 185:79] + node _T_273 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 185:101] + node _T_274 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 185:136] + node _T_275 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 185:158] + node _T_276 = mux(_T_272, _T_273, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_277 = mux(_T_274, _T_275, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_278 = or(_T_276, _T_277) @[Mux.scala 27:72] + wire _T_279 : UInt<8> @[Mux.scala 27:72] + _T_279 <= _T_278 @[Mux.scala 27:72] + node _T_280 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 185:79] + node _T_281 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 185:101] + node _T_282 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 185:136] + node _T_283 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 185:158] + node _T_284 = mux(_T_280, _T_281, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_285 = mux(_T_282, _T_283, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_286 = or(_T_284, _T_285) @[Mux.scala 27:72] + wire _T_287 : UInt<8> @[Mux.scala 27:72] + _T_287 <= _T_286 @[Mux.scala 27:72] + node _T_288 = cat(_T_287, _T_279) @[Cat.scala 29:58] + node _T_289 = cat(_T_288, _T_271) @[Cat.scala 29:58] + node _T_290 = cat(_T_289, _T_263) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_290 @[lsu_bus_intf.scala 185:27] + node _T_291 = bits(ld_byte_rhit_lo, 0, 0) @[lsu_bus_intf.scala 186:70] + node _T_292 = bits(ld_fwddata_rpipe_lo, 7, 0) @[lsu_bus_intf.scala 186:94] + node _T_293 = bits(ld_fwddata_buf_lo, 7, 0) @[lsu_bus_intf.scala 186:128] + node _T_294 = mux(_T_291, _T_292, _T_293) @[lsu_bus_intf.scala 186:54] + node _T_295 = bits(ld_byte_rhit_lo, 1, 1) @[lsu_bus_intf.scala 186:70] + node _T_296 = bits(ld_fwddata_rpipe_lo, 15, 8) @[lsu_bus_intf.scala 186:94] + node _T_297 = bits(ld_fwddata_buf_lo, 15, 8) @[lsu_bus_intf.scala 186:128] + node _T_298 = mux(_T_295, _T_296, _T_297) @[lsu_bus_intf.scala 186:54] + node _T_299 = bits(ld_byte_rhit_lo, 2, 2) @[lsu_bus_intf.scala 186:70] + node _T_300 = bits(ld_fwddata_rpipe_lo, 23, 16) @[lsu_bus_intf.scala 186:94] + node _T_301 = bits(ld_fwddata_buf_lo, 23, 16) @[lsu_bus_intf.scala 186:128] + node _T_302 = mux(_T_299, _T_300, _T_301) @[lsu_bus_intf.scala 186:54] + node _T_303 = bits(ld_byte_rhit_lo, 3, 3) @[lsu_bus_intf.scala 186:70] + node _T_304 = bits(ld_fwddata_rpipe_lo, 31, 24) @[lsu_bus_intf.scala 186:94] + node _T_305 = bits(ld_fwddata_buf_lo, 31, 24) @[lsu_bus_intf.scala 186:128] + node _T_306 = mux(_T_303, _T_304, _T_305) @[lsu_bus_intf.scala 186:54] + node _T_307 = cat(_T_306, _T_302) @[Cat.scala 29:58] + node _T_308 = cat(_T_307, _T_298) @[Cat.scala 29:58] + node _T_309 = cat(_T_308, _T_294) @[Cat.scala 29:58] + ld_fwddata_lo <= _T_309 @[lsu_bus_intf.scala 186:27] + node _T_310 = bits(ld_byte_rhit_hi, 0, 0) @[lsu_bus_intf.scala 187:70] + node _T_311 = bits(ld_fwddata_rpipe_hi, 7, 0) @[lsu_bus_intf.scala 187:94] + node _T_312 = bits(ld_fwddata_buf_hi, 7, 0) @[lsu_bus_intf.scala 187:128] + node _T_313 = mux(_T_310, _T_311, _T_312) @[lsu_bus_intf.scala 187:54] + node _T_314 = bits(ld_byte_rhit_hi, 1, 1) @[lsu_bus_intf.scala 187:70] + node _T_315 = bits(ld_fwddata_rpipe_hi, 15, 8) @[lsu_bus_intf.scala 187:94] + node _T_316 = bits(ld_fwddata_buf_hi, 15, 8) @[lsu_bus_intf.scala 187:128] + node _T_317 = mux(_T_314, _T_315, _T_316) @[lsu_bus_intf.scala 187:54] + node _T_318 = bits(ld_byte_rhit_hi, 2, 2) @[lsu_bus_intf.scala 187:70] + node _T_319 = bits(ld_fwddata_rpipe_hi, 23, 16) @[lsu_bus_intf.scala 187:94] + node _T_320 = bits(ld_fwddata_buf_hi, 23, 16) @[lsu_bus_intf.scala 187:128] + node _T_321 = mux(_T_318, _T_319, _T_320) @[lsu_bus_intf.scala 187:54] + node _T_322 = bits(ld_byte_rhit_hi, 3, 3) @[lsu_bus_intf.scala 187:70] + node _T_323 = bits(ld_fwddata_rpipe_hi, 31, 24) @[lsu_bus_intf.scala 187:94] + node _T_324 = bits(ld_fwddata_buf_hi, 31, 24) @[lsu_bus_intf.scala 187:128] + node _T_325 = mux(_T_322, _T_323, _T_324) @[lsu_bus_intf.scala 187:54] + node _T_326 = cat(_T_325, _T_321) @[Cat.scala 29:58] + node _T_327 = cat(_T_326, _T_317) @[Cat.scala 29:58] + node _T_328 = cat(_T_327, _T_313) @[Cat.scala 29:58] + ld_fwddata_hi <= _T_328 @[lsu_bus_intf.scala 187:27] + node _T_329 = bits(ld_byte_hit_lo, 0, 0) @[lsu_bus_intf.scala 188:66] + node _T_330 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 188:89] + node _T_331 = eq(_T_330, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_332 = or(_T_329, _T_331) @[lsu_bus_intf.scala 188:70] + node _T_333 = bits(ld_byte_hit_lo, 1, 1) @[lsu_bus_intf.scala 188:66] + node _T_334 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 188:89] + node _T_335 = eq(_T_334, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_336 = or(_T_333, _T_335) @[lsu_bus_intf.scala 188:70] + node _T_337 = bits(ld_byte_hit_lo, 2, 2) @[lsu_bus_intf.scala 188:66] + node _T_338 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 188:89] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_340 = or(_T_337, _T_339) @[lsu_bus_intf.scala 188:70] + node _T_341 = bits(ld_byte_hit_lo, 3, 3) @[lsu_bus_intf.scala 188:66] + node _T_342 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 188:89] + node _T_343 = eq(_T_342, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_344 = or(_T_341, _T_343) @[lsu_bus_intf.scala 188:70] + node _T_345 = and(_T_332, _T_336) @[lsu_bus_intf.scala 188:111] + node _T_346 = and(_T_345, _T_340) @[lsu_bus_intf.scala 188:111] + node _T_347 = and(_T_346, _T_344) @[lsu_bus_intf.scala 188:111] + ld_full_hit_lo_m <= _T_347 @[lsu_bus_intf.scala 188:27] + node _T_348 = bits(ld_byte_hit_hi, 0, 0) @[lsu_bus_intf.scala 189:66] + node _T_349 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 189:89] + node _T_350 = eq(_T_349, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_351 = or(_T_348, _T_350) @[lsu_bus_intf.scala 189:70] + node _T_352 = bits(ld_byte_hit_hi, 1, 1) @[lsu_bus_intf.scala 189:66] + node _T_353 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 189:89] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_355 = or(_T_352, _T_354) @[lsu_bus_intf.scala 189:70] + node _T_356 = bits(ld_byte_hit_hi, 2, 2) @[lsu_bus_intf.scala 189:66] + node _T_357 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 189:89] + node _T_358 = eq(_T_357, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_359 = or(_T_356, _T_358) @[lsu_bus_intf.scala 189:70] + node _T_360 = bits(ld_byte_hit_hi, 3, 3) @[lsu_bus_intf.scala 189:66] + node _T_361 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 189:89] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] + node _T_363 = or(_T_360, _T_362) @[lsu_bus_intf.scala 189:70] + node _T_364 = and(_T_351, _T_355) @[lsu_bus_intf.scala 189:111] + node _T_365 = and(_T_364, _T_359) @[lsu_bus_intf.scala 189:111] + node _T_366 = and(_T_365, _T_363) @[lsu_bus_intf.scala 189:111] + ld_full_hit_hi_m <= _T_366 @[lsu_bus_intf.scala 189:27] + node _T_367 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[lsu_bus_intf.scala 190:47] + node _T_368 = and(_T_367, io.lsu_busreq_m) @[lsu_bus_intf.scala 190:66] + node _T_369 = and(_T_368, io.lsu_pkt_m.bits.load) @[lsu_bus_intf.scala 190:84] + node _T_370 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[lsu_bus_intf.scala 190:111] + node _T_371 = and(_T_369, _T_370) @[lsu_bus_intf.scala 190:109] + ld_full_hit_m <= _T_371 @[lsu_bus_intf.scala 190:27] + node _T_372 = bits(ld_fwddata_hi, 31, 0) @[lsu_bus_intf.scala 191:47] + node _T_373 = bits(ld_fwddata_lo, 31, 0) @[lsu_bus_intf.scala 191:68] + node _T_374 = cat(_T_372, _T_373) @[Cat.scala 29:58] + node _T_375 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 191:97] + node _T_376 = mul(UInt<4>("h08"), _T_375) @[lsu_bus_intf.scala 191:83] + node _T_377 = dshr(_T_374, _T_376) @[lsu_bus_intf.scala 191:76] + ld_fwddata_m <= _T_377 @[lsu_bus_intf.scala 191:27] + node _T_378 = bits(ld_fwddata_m, 31, 0) @[lsu_bus_intf.scala 192:42] + io.bus_read_data_m <= _T_378 @[lsu_bus_intf.scala 192:27] + reg _T_379 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 195:32] + _T_379 <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 195:32] + lsu_bus_clk_en_q <= _T_379 @[lsu_bus_intf.scala 195:22] + reg _T_380 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 199:33] + _T_380 <= io.is_sideeffects_m @[lsu_bus_intf.scala 199:33] + is_sideeffects_r <= _T_380 @[lsu_bus_intf.scala 199:23] + reg _T_381 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<4>("h00"))) @[lsu_bus_intf.scala 200:33] + _T_381 <= ldst_byteen_m @[lsu_bus_intf.scala 200:33] + ldst_byteen_r <= _T_381 @[lsu_bus_intf.scala 200:23] + diff --git a/lsu_bus_intf.v b/lsu_bus_intf.v new file mode 100644 index 00000000..cbeea71a --- /dev/null +++ b/lsu_bus_intf.v @@ -0,0 +1,5244 @@ +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module lsu_bus_buffer( + input clock, + input reset, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + input io_dec_tlu_force_halt, + input io_lsu_bus_obuf_c1_clken, + input io_lsu_busm_clken, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_dec_lsu_valid_raw_d, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input [31:0] io_lsu_addr_m, + input [31:0] io_end_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_r, + input [31:0] io_store_data_r, + input io_no_word_merge_r, + input io_no_dword_merge_r, + input io_lsu_busreq_m, + input io_ld_full_hit_m, + input io_flush_m_up, + input io_flush_r, + input io_lsu_commit_r, + input io_is_sideeffects_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [7:0] io_ldst_byteen_ext_m, + input io_lsu_axi_aw_ready, + output io_lsu_axi_aw_valid, + output [2:0] io_lsu_axi_aw_bits_id, + output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, + output [2:0] io_lsu_axi_aw_bits_size, + output [3:0] io_lsu_axi_aw_bits_cache, + input io_lsu_axi_w_ready, + output io_lsu_axi_w_valid, + output [63:0] io_lsu_axi_w_bits_data, + output [7:0] io_lsu_axi_w_bits_strb, + output io_lsu_axi_b_ready, + input io_lsu_axi_b_valid, + input [1:0] io_lsu_axi_b_bits_resp, + input [2:0] io_lsu_axi_b_bits_id, + input io_lsu_axi_ar_ready, + output io_lsu_axi_ar_valid, + output [2:0] io_lsu_axi_ar_bits_id, + output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, + output [2:0] io_lsu_axi_ar_bits_size, + output [3:0] io_lsu_axi_ar_bits_cache, + output io_lsu_axi_r_ready, + input io_lsu_axi_r_valid, + input [2:0] io_lsu_axi_r_bits_id, + input [63:0] io_lsu_axi_r_bits_data, + input [1:0] io_lsu_axi_r_bits_resp, + input io_lsu_bus_clk_en, + input io_lsu_bus_clk_en_q, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [3:0] io_ld_byte_hit_buf_lo, + output [3:0] io_ld_byte_hit_buf_hi, + output [31:0] io_ld_fwddata_buf_lo, + output [31:0] io_ld_fwddata_buf_hi, + output [31:0] io_lsu_nonblock_load_data +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [63:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; + reg [31:0] _RAND_91; + reg [31:0] _RAND_92; + reg [31:0] _RAND_93; + reg [31:0] _RAND_94; + reg [31:0] _RAND_95; + reg [31:0] _RAND_96; + reg [31:0] _RAND_97; + reg [31:0] _RAND_98; + reg [31:0] _RAND_99; + reg [31:0] _RAND_100; + reg [31:0] _RAND_101; + reg [31:0] _RAND_102; + reg [31:0] _RAND_103; + reg [31:0] _RAND_104; + reg [31:0] _RAND_105; + reg [31:0] _RAND_106; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_11_io_en; // @[lib.scala 404:23] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 77:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 78:46] + reg [31:0] buf_addr_0; // @[Reg.scala 27:20] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 80:74] + reg _T_4355; // @[Reg.scala 27:20] + reg _T_4352; // @[Reg.scala 27:20] + reg _T_4349; // @[Reg.scala 27:20] + reg _T_4346; // @[Reg.scala 27:20] + wire [3:0] buf_write = {_T_4355,_T_4352,_T_4349,_T_4346}; // @[Cat.scala 29:58] + wire _T_4 = _T_2 & buf_write[0]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_0; // @[Reg.scala 27:20] + wire _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_1; // @[Reg.scala 27:20] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_1; // @[Reg.scala 27:20] + wire _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_2; // @[Reg.scala 27:20] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_2; // @[Reg.scala 27:20] + wire _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + reg [31:0] buf_addr_3; // @[Reg.scala 27:20] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 80:74] + wire _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 80:98] + reg [2:0] buf_state_3; // @[Reg.scala 27:20] + wire _T_26 = buf_state_3 != 3'h0; // @[lsu_bus_buffer.scala 80:129] + wire _T_27 = _T_25 & _T_26; // @[lsu_bus_buffer.scala 80:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_32 = _T_30 & buf_write[0]; // @[lsu_bus_buffer.scala 81:98] + wire _T_34 = _T_32 & _T_5; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_39 = _T_37 & buf_write[1]; // @[lsu_bus_buffer.scala 81:98] + wire _T_41 = _T_39 & _T_12; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_46 = _T_44 & buf_write[2]; // @[lsu_bus_buffer.scala 81:98] + wire _T_48 = _T_46 & _T_19; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 81:74] + wire _T_53 = _T_51 & buf_write[3]; // @[lsu_bus_buffer.scala 81:98] + wire _T_55 = _T_53 & _T_26; // @[lsu_bus_buffer.scala 81:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141] + reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 145:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] + reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 513:60] + wire _T_2590 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_4104 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4127 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4131 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] + reg [1:0] _T_1781; // @[Reg.scala 27:20] + wire [2:0] obuf_tag0 = {{1'd0}, _T_1781}; // @[lsu_bus_buffer.scala 356:13] + wire _T_4138 = obuf_tag0 == 3'h3; // @[lsu_bus_buffer.scala 460:48] + reg obuf_merge; // @[Reg.scala 27:20] + reg [1:0] obuf_tag1; // @[Reg.scala 27:20] + wire [2:0] _GEN_376 = {{1'd0}, obuf_tag1}; // @[lsu_bus_buffer.scala 460:104] + wire _T_4139 = _GEN_376 == 3'h3; // @[lsu_bus_buffer.scala 460:104] + wire _T_4140 = obuf_merge & _T_4139; // @[lsu_bus_buffer.scala 460:91] + wire _T_4141 = _T_4138 | _T_4140; // @[lsu_bus_buffer.scala 460:77] + reg obuf_valid; // @[lsu_bus_buffer.scala 349:54] + wire _T_4142 = _T_4141 & obuf_valid; // @[lsu_bus_buffer.scala 460:135] + reg obuf_wr_enQ; // @[Reg.scala 27:20] + wire _T_4143 = _T_4142 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 460:148] + wire _T_4165 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4250 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4268 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4276 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] + wire _GEN_290 = _T_4131 & _T_4143; // @[Conditional.scala 39:67] + wire _GEN_303 = _T_4127 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_303; // @[Conditional.scala 40:58] + wire _T_2591 = _T_2590 & buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 417:103] + wire _T_2592 = ~_T_2591; // @[lsu_bus_buffer.scala 417:78] + wire _T_2593 = buf_ageQ_3[3] & _T_2592; // @[lsu_bus_buffer.scala 417:76] + wire _T_2594 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 417:132] + wire _T_2595 = _T_2593 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2583 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3913 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3936 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3940 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3947 = obuf_tag0 == 3'h2; // @[lsu_bus_buffer.scala 460:48] + wire _T_3948 = _GEN_376 == 3'h2; // @[lsu_bus_buffer.scala 460:104] + wire _T_3949 = obuf_merge & _T_3948; // @[lsu_bus_buffer.scala 460:91] + wire _T_3950 = _T_3947 | _T_3949; // @[lsu_bus_buffer.scala 460:77] + wire _T_3951 = _T_3950 & obuf_valid; // @[lsu_bus_buffer.scala 460:135] + wire _T_3952 = _T_3951 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 460:148] + wire _T_3974 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4059 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4077 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4085 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] + wire _GEN_214 = _T_3940 & _T_3952; // @[Conditional.scala 39:67] + wire _GEN_227 = _T_3936 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_227; // @[Conditional.scala 40:58] + wire _T_2584 = _T_2583 & buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 417:103] + wire _T_2585 = ~_T_2584; // @[lsu_bus_buffer.scala 417:78] + wire _T_2586 = buf_ageQ_3[2] & _T_2585; // @[lsu_bus_buffer.scala 417:76] + wire _T_2588 = _T_2586 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2576 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3722 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3745 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3749 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3756 = obuf_tag0 == 3'h1; // @[lsu_bus_buffer.scala 460:48] + wire _T_3757 = _GEN_376 == 3'h1; // @[lsu_bus_buffer.scala 460:104] + wire _T_3758 = obuf_merge & _T_3757; // @[lsu_bus_buffer.scala 460:91] + wire _T_3759 = _T_3756 | _T_3758; // @[lsu_bus_buffer.scala 460:77] + wire _T_3760 = _T_3759 & obuf_valid; // @[lsu_bus_buffer.scala 460:135] + wire _T_3761 = _T_3760 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 460:148] + wire _T_3783 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3868 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3886 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3894 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] + wire _GEN_138 = _T_3749 & _T_3761; // @[Conditional.scala 39:67] + wire _GEN_151 = _T_3745 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_151; // @[Conditional.scala 40:58] + wire _T_2577 = _T_2576 & buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 417:103] + wire _T_2578 = ~_T_2577; // @[lsu_bus_buffer.scala 417:78] + wire _T_2579 = buf_ageQ_3[1] & _T_2578; // @[lsu_bus_buffer.scala 417:76] + wire _T_2581 = _T_2579 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2569 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 417:93] + wire _T_3531 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3554 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3558 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3565 = obuf_tag0 == 3'h0; // @[lsu_bus_buffer.scala 460:48] + wire _T_3566 = _GEN_376 == 3'h0; // @[lsu_bus_buffer.scala 460:104] + wire _T_3567 = obuf_merge & _T_3566; // @[lsu_bus_buffer.scala 460:91] + wire _T_3568 = _T_3565 | _T_3567; // @[lsu_bus_buffer.scala 460:77] + wire _T_3569 = _T_3568 & obuf_valid; // @[lsu_bus_buffer.scala 460:135] + wire _T_3570 = _T_3569 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 460:148] + wire _T_3592 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3677 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3695 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3703 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] + wire _GEN_62 = _T_3558 & _T_3570; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_3554 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_75; // @[Conditional.scala 40:58] + wire _T_2570 = _T_2569 & buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 417:103] + wire _T_2571 = ~_T_2570; // @[lsu_bus_buffer.scala 417:78] + wire _T_2572 = buf_ageQ_3[0] & _T_2571; // @[lsu_bus_buffer.scala 417:76] + wire _T_2574 = _T_2572 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_3 = {_T_2595,_T_2588,_T_2581,_T_2574}; // @[Cat.scala 29:58] + wire _T_2694 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2696 = _T_2694 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2688 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2690 = _T_2688 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire _T_2682 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2684 = _T_2682 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_3 = {1'h0,_T_2696,_T_2690,_T_2684}; // @[Cat.scala 29:58] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 150:144] + wire _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 150:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 150:97] + reg [31:0] ibuf_addr; // @[Reg.scala 27:20] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 156:51] + reg ibuf_write; // @[Reg.scala 27:20] + wire _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 156:73] + reg ibuf_valid; // @[lsu_bus_buffer.scala 244:54] + wire _T_514 = _T_513 & ibuf_valid; // @[lsu_bus_buffer.scala 156:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 156:99] + wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[lsu_bus_buffer.scala 161:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 161:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 150:150] + wire _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 513:60] + wire _T_2562 = buf_ageQ_2[3] & _T_2592; // @[lsu_bus_buffer.scala 417:76] + wire _T_2564 = _T_2562 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2555 = buf_ageQ_2[2] & _T_2585; // @[lsu_bus_buffer.scala 417:76] + wire _T_2557 = _T_2555 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2548 = buf_ageQ_2[1] & _T_2578; // @[lsu_bus_buffer.scala 417:76] + wire _T_2550 = _T_2548 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2541 = buf_ageQ_2[0] & _T_2571; // @[lsu_bus_buffer.scala 417:76] + wire _T_2543 = _T_2541 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_2 = {_T_2564,_T_2557,_T_2550,_T_2543}; // @[Cat.scala 29:58] + wire _T_2673 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2675 = _T_2673 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2661 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2663 = _T_2661 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire _T_2655 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2657 = _T_2655 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_2 = {_T_2675,1'h0,_T_2663,_T_2657}; // @[Cat.scala 29:58] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_248 = |_T_247; // @[lsu_bus_buffer.scala 150:144] + wire _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 150:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 150:97] + wire _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 513:60] + wire _T_2531 = buf_ageQ_1[3] & _T_2592; // @[lsu_bus_buffer.scala 417:76] + wire _T_2533 = _T_2531 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2524 = buf_ageQ_1[2] & _T_2585; // @[lsu_bus_buffer.scala 417:76] + wire _T_2526 = _T_2524 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2517 = buf_ageQ_1[1] & _T_2578; // @[lsu_bus_buffer.scala 417:76] + wire _T_2519 = _T_2517 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2510 = buf_ageQ_1[0] & _T_2571; // @[lsu_bus_buffer.scala 417:76] + wire _T_2512 = _T_2510 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_1 = {_T_2533,_T_2526,_T_2519,_T_2512}; // @[Cat.scala 29:58] + wire _T_2646 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2648 = _T_2646 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2640 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2642 = _T_2640 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2628 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2630 = _T_2628 & _T_5; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_1 = {_T_2648,_T_2642,1'h0,_T_2630}; // @[Cat.scala 29:58] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_240 = |_T_239; // @[lsu_bus_buffer.scala 150:144] + wire _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 150:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 150:97] + wire _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 150:148] + reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 513:60] + wire _T_2500 = buf_ageQ_0[3] & _T_2592; // @[lsu_bus_buffer.scala 417:76] + wire _T_2502 = _T_2500 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2493 = buf_ageQ_0[2] & _T_2585; // @[lsu_bus_buffer.scala 417:76] + wire _T_2495 = _T_2493 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2486 = buf_ageQ_0[1] & _T_2578; // @[lsu_bus_buffer.scala 417:76] + wire _T_2488 = _T_2486 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire _T_2479 = buf_ageQ_0[0] & _T_2571; // @[lsu_bus_buffer.scala 417:76] + wire _T_2481 = _T_2479 & _T_2594; // @[lsu_bus_buffer.scala 417:130] + wire [3:0] buf_age_0 = {_T_2502,_T_2495,_T_2488,_T_2481}; // @[Cat.scala 29:58] + wire _T_2619 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2621 = _T_2619 & _T_26; // @[lsu_bus_buffer.scala 418:104] + wire _T_2613 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2615 = _T_2613 & _T_19; // @[lsu_bus_buffer.scala 418:104] + wire _T_2607 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 418:89] + wire _T_2609 = _T_2607 & _T_12; // @[lsu_bus_buffer.scala 418:104] + wire [3:0] buf_age_younger_0 = {_T_2621,_T_2615,_T_2609,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_232 = |_T_231; // @[lsu_bus_buffer.scala 150:144] + wire _T_233 = ~_T_232; // @[lsu_bus_buffer.scala 150:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[lsu_bus_buffer.scala 150:97] + wire _T_237 = _T_234 & _T_260; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[lsu_bus_buffer.scala 142:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 142:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 145:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_291 = |_T_290; // @[lsu_bus_buffer.scala 150:144] + wire _T_292 = ~_T_291; // @[lsu_bus_buffer.scala 150:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[lsu_bus_buffer.scala 150:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 150:150] + wire _T_296 = _T_293 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_283 = |_T_282; // @[lsu_bus_buffer.scala 150:144] + wire _T_284 = ~_T_283; // @[lsu_bus_buffer.scala 150:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[lsu_bus_buffer.scala 150:97] + wire _T_288 = _T_285 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_275 = |_T_274; // @[lsu_bus_buffer.scala 150:144] + wire _T_276 = ~_T_275; // @[lsu_bus_buffer.scala 150:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[lsu_bus_buffer.scala 150:97] + wire _T_280 = _T_277 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_267 = |_T_266; // @[lsu_bus_buffer.scala 150:144] + wire _T_268 = ~_T_267; // @[lsu_bus_buffer.scala 150:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[lsu_bus_buffer.scala 150:97] + wire _T_272 = _T_269 & _T_295; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[lsu_bus_buffer.scala 142:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 142:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 145:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_326 = |_T_325; // @[lsu_bus_buffer.scala 150:144] + wire _T_327 = ~_T_326; // @[lsu_bus_buffer.scala 150:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[lsu_bus_buffer.scala 150:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 150:150] + wire _T_331 = _T_328 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_318 = |_T_317; // @[lsu_bus_buffer.scala 150:144] + wire _T_319 = ~_T_318; // @[lsu_bus_buffer.scala 150:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[lsu_bus_buffer.scala 150:97] + wire _T_323 = _T_320 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_310 = |_T_309; // @[lsu_bus_buffer.scala 150:144] + wire _T_311 = ~_T_310; // @[lsu_bus_buffer.scala 150:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[lsu_bus_buffer.scala 150:97] + wire _T_315 = _T_312 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_302 = |_T_301; // @[lsu_bus_buffer.scala 150:144] + wire _T_303 = ~_T_302; // @[lsu_bus_buffer.scala 150:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[lsu_bus_buffer.scala 150:97] + wire _T_307 = _T_304 & _T_330; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[lsu_bus_buffer.scala 142:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 142:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 145:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114] + wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122] + wire _T_361 = |_T_360; // @[lsu_bus_buffer.scala 150:144] + wire _T_362 = ~_T_361; // @[lsu_bus_buffer.scala 150:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[lsu_bus_buffer.scala 150:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 150:150] + wire _T_366 = _T_363 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122] + wire _T_353 = |_T_352; // @[lsu_bus_buffer.scala 150:144] + wire _T_354 = ~_T_353; // @[lsu_bus_buffer.scala 150:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[lsu_bus_buffer.scala 150:97] + wire _T_358 = _T_355 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122] + wire _T_345 = |_T_344; // @[lsu_bus_buffer.scala 150:144] + wire _T_346 = ~_T_345; // @[lsu_bus_buffer.scala 150:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[lsu_bus_buffer.scala 150:97] + wire _T_350 = _T_347 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122] + wire _T_337 = |_T_336; // @[lsu_bus_buffer.scala 150:144] + wire _T_338 = ~_T_337; // @[lsu_bus_buffer.scala 150:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[lsu_bus_buffer.scala 150:97] + wire _T_342 = _T_339 & _T_365; // @[lsu_bus_buffer.scala 150:148] + wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[lsu_bus_buffer.scala 142:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 142:77] + wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 146:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_396 = |_T_395; // @[lsu_bus_buffer.scala 151:144] + wire _T_397 = ~_T_396; // @[lsu_bus_buffer.scala 151:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[lsu_bus_buffer.scala 151:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 157:51] + wire _T_518 = _T_517 & ibuf_write; // @[lsu_bus_buffer.scala 157:73] + wire _T_519 = _T_518 & ibuf_valid; // @[lsu_bus_buffer.scala 157:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 157:99] + wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[lsu_bus_buffer.scala 162:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[lsu_bus_buffer.scala 162:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 151:150] + wire _T_401 = _T_398 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_388 = |_T_387; // @[lsu_bus_buffer.scala 151:144] + wire _T_389 = ~_T_388; // @[lsu_bus_buffer.scala 151:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[lsu_bus_buffer.scala 151:97] + wire _T_393 = _T_390 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_380 = |_T_379; // @[lsu_bus_buffer.scala 151:144] + wire _T_381 = ~_T_380; // @[lsu_bus_buffer.scala 151:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[lsu_bus_buffer.scala 151:97] + wire _T_385 = _T_382 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_372 = |_T_371; // @[lsu_bus_buffer.scala 151:144] + wire _T_373 = ~_T_372; // @[lsu_bus_buffer.scala 151:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[lsu_bus_buffer.scala 151:97] + wire _T_377 = _T_374 & _T_400; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[lsu_bus_buffer.scala 143:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 143:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 146:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_431 = |_T_430; // @[lsu_bus_buffer.scala 151:144] + wire _T_432 = ~_T_431; // @[lsu_bus_buffer.scala 151:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[lsu_bus_buffer.scala 151:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 151:150] + wire _T_436 = _T_433 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_423 = |_T_422; // @[lsu_bus_buffer.scala 151:144] + wire _T_424 = ~_T_423; // @[lsu_bus_buffer.scala 151:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[lsu_bus_buffer.scala 151:97] + wire _T_428 = _T_425 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_415 = |_T_414; // @[lsu_bus_buffer.scala 151:144] + wire _T_416 = ~_T_415; // @[lsu_bus_buffer.scala 151:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[lsu_bus_buffer.scala 151:97] + wire _T_420 = _T_417 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_407 = |_T_406; // @[lsu_bus_buffer.scala 151:144] + wire _T_408 = ~_T_407; // @[lsu_bus_buffer.scala 151:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[lsu_bus_buffer.scala 151:97] + wire _T_412 = _T_409 & _T_435; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[lsu_bus_buffer.scala 143:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 143:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 146:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_466 = |_T_465; // @[lsu_bus_buffer.scala 151:144] + wire _T_467 = ~_T_466; // @[lsu_bus_buffer.scala 151:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[lsu_bus_buffer.scala 151:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 151:150] + wire _T_471 = _T_468 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_458 = |_T_457; // @[lsu_bus_buffer.scala 151:144] + wire _T_459 = ~_T_458; // @[lsu_bus_buffer.scala 151:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[lsu_bus_buffer.scala 151:97] + wire _T_463 = _T_460 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_450 = |_T_449; // @[lsu_bus_buffer.scala 151:144] + wire _T_451 = ~_T_450; // @[lsu_bus_buffer.scala 151:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[lsu_bus_buffer.scala 151:97] + wire _T_455 = _T_452 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_442 = |_T_441; // @[lsu_bus_buffer.scala 151:144] + wire _T_443 = ~_T_442; // @[lsu_bus_buffer.scala 151:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[lsu_bus_buffer.scala 151:97] + wire _T_447 = _T_444 & _T_470; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[lsu_bus_buffer.scala 143:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 143:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 146:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114] + wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122] + wire _T_501 = |_T_500; // @[lsu_bus_buffer.scala 151:144] + wire _T_502 = ~_T_501; // @[lsu_bus_buffer.scala 151:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[lsu_bus_buffer.scala 151:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 151:150] + wire _T_506 = _T_503 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122] + wire _T_493 = |_T_492; // @[lsu_bus_buffer.scala 151:144] + wire _T_494 = ~_T_493; // @[lsu_bus_buffer.scala 151:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[lsu_bus_buffer.scala 151:97] + wire _T_498 = _T_495 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122] + wire _T_485 = |_T_484; // @[lsu_bus_buffer.scala 151:144] + wire _T_486 = ~_T_485; // @[lsu_bus_buffer.scala 151:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[lsu_bus_buffer.scala 151:97] + wire _T_490 = _T_487 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122] + wire _T_477 = |_T_476; // @[lsu_bus_buffer.scala 151:144] + wire _T_478 = ~_T_477; // @[lsu_bus_buffer.scala 151:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[lsu_bus_buffer.scala 151:97] + wire _T_482 = _T_479 & _T_505; // @[lsu_bus_buffer.scala 151:148] + wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[lsu_bus_buffer.scala 143:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 143:77] + wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] + wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58] + wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] + wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_0; // @[Reg.scala 27:20] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_1; // @[Reg.scala 27:20] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_2; // @[Reg.scala 27:20] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_3; // @[Reg.scala 27:20] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 169:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[lsu_bus_buffer.scala 169:123] + wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 170:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[lsu_bus_buffer.scala 170:97] + wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 172:97] + wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] + reg [31:0] ibuf_data; // @[Reg.scala 27:20] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 173:32] + wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 175:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[lsu_bus_buffer.scala 175:123] + wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 176:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[lsu_bus_buffer.scala 176:97] + wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 177:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[lsu_bus_buffer.scala 177:97] + wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 178:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[lsu_bus_buffer.scala 178:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[lsu_bus_buffer.scala 178:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[lsu_bus_buffer.scala 178:97] + wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[lsu_bus_buffer.scala 179:32] + wire [3:0] _T_750 = io_lsu_pkt_r_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_751 = io_lsu_pkt_r_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_752 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[lsu_bus_buffer.scala 186:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[lsu_bus_buffer.scala 187:24] + wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[lsu_bus_buffer.scala 188:24] + wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[lsu_bus_buffer.scala 189:24] + wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72] + wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72] + wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72] + wire [31:0] _T_802 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58] + wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58] + wire [31:0] _T_810 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72] + wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72] + wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] + wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] + wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[lsu_bus_buffer.scala 207:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[lsu_bus_buffer.scala 209:31] + wire _T_845 = io_lsu_pkt_r_bits_word & _T_756; // @[Mux.scala 27:72] + wire _T_846 = io_lsu_pkt_r_bits_half & _T_844; // @[Mux.scala 27:72] + wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] + wire is_aligned_r = _T_848 | io_lsu_pkt_r_bits_by; // @[Mux.scala 27:72] + wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[lsu_bus_buffer.scala 211:60] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[lsu_bus_buffer.scala 211:34] + wire _T_852 = ~ibuf_valid; // @[lsu_bus_buffer.scala 211:84] + wire ibuf_byp = _T_851 & _T_852; // @[lsu_bus_buffer.scala 211:82] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[lsu_bus_buffer.scala 212:36] + wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 212:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 212:54] + wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 214:36] + reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 257:55] + wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 220:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 220:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 239:54] + wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 239:80] + wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 239:93] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 239:129] + wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 239:106] + wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 239:152] + wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 239:150] + wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 239:175] + wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 239:173] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 240:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 220:98] + wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 220:82] + wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 220:80] + wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 221:5] + wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 215:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 215:42] + wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 215:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 215:120] + wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 215:100] + wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 215:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 221:16] + reg ibuf_sideeffect; // @[Reg.scala 27:20] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 221:35] + wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 221:55] + wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 221:53] + wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 221:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 220:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 214:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 214:49] + reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 627:49] + reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 626:49] + reg [1:0] ibuf_tag; // @[Reg.scala 27:20] + wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 230:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 234:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 235:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 236:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 234:46] + wire [31:0] ibuf_data_in = {_T_920,_T_911,_T_902,_T_893}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 237:60] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 237:95] + wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 241:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 241:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 241:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 241:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 241:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 241:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 241:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 241:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 241:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 241:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 242:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 242:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 244:58] + wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 244:93] + reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] + reg ibuf_dual; // @[Reg.scala 27:20] + reg ibuf_samedw; // @[Reg.scala 27:20] + reg ibuf_nomerge; // @[Reg.scala 27:20] + reg ibuf_unsign; // @[Reg.scala 27:20] + reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire _T_4441 = buf_write[3] & _T_2590; // @[lsu_bus_buffer.scala 533:64] + wire _T_4442 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 533:91] + wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 533:89] + wire _T_4436 = buf_write[2] & _T_2583; // @[lsu_bus_buffer.scala 533:64] + wire _T_4437 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 533:91] + wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 533:89] + wire [1:0] _T_4444 = _T_4443 + _T_4438; // @[lsu_bus_buffer.scala 533:142] + wire _T_4431 = buf_write[1] & _T_2576; // @[lsu_bus_buffer.scala 533:64] + wire _T_4432 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 533:91] + wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 533:89] + wire [1:0] _GEN_380 = {{1'd0}, _T_4433}; // @[lsu_bus_buffer.scala 533:142] + wire [2:0] _T_4445 = _T_4444 + _GEN_380; // @[lsu_bus_buffer.scala 533:142] + wire _T_4426 = buf_write[0] & _T_2569; // @[lsu_bus_buffer.scala 533:64] + wire _T_4427 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 533:91] + wire _T_4428 = _T_4426 & _T_4427; // @[lsu_bus_buffer.scala 533:89] + wire [2:0] _GEN_381 = {{2'd0}, _T_4428}; // @[lsu_bus_buffer.scala 533:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4445 + _GEN_381; // @[lsu_bus_buffer.scala 533:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 267:43] + wire _T_4458 = _T_2590 & _T_4442; // @[lsu_bus_buffer.scala 534:73] + wire _T_4455 = _T_2583 & _T_4437; // @[lsu_bus_buffer.scala 534:73] + wire [1:0] _T_4459 = _T_4458 + _T_4455; // @[lsu_bus_buffer.scala 534:126] + wire _T_4452 = _T_2576 & _T_4432; // @[lsu_bus_buffer.scala 534:73] + wire [1:0] _GEN_382 = {{1'd0}, _T_4452}; // @[lsu_bus_buffer.scala 534:126] + wire [2:0] _T_4460 = _T_4459 + _GEN_382; // @[lsu_bus_buffer.scala 534:126] + wire _T_4449 = _T_2569 & _T_4427; // @[lsu_bus_buffer.scala 534:73] + wire [2:0] _GEN_383 = {{2'd0}, _T_4449}; // @[lsu_bus_buffer.scala 534:126] + wire [3:0] buf_numvld_cmd_any = _T_4460 + _GEN_383; // @[lsu_bus_buffer.scala 534:126] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 267:72] + wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 267:51] + reg _T_1791; // @[Reg.scala 27:20] + wire [2:0] obuf_wr_timer = {{2'd0}, _T_1791}; // @[lsu_bus_buffer.scala 365:17] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 267:97] + wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 267:80] + wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 267:114] + wire _T_1918 = |buf_age_3; // @[lsu_bus_buffer.scala 383:58] + wire _T_1919 = ~_T_1918; // @[lsu_bus_buffer.scala 383:45] + wire _T_1921 = _T_1919 & _T_2590; // @[lsu_bus_buffer.scala 383:63] + wire _T_1923 = _T_1921 & _T_4442; // @[lsu_bus_buffer.scala 383:88] + wire _T_1912 = |buf_age_2; // @[lsu_bus_buffer.scala 383:58] + wire _T_1913 = ~_T_1912; // @[lsu_bus_buffer.scala 383:45] + wire _T_1915 = _T_1913 & _T_2583; // @[lsu_bus_buffer.scala 383:63] + wire _T_1917 = _T_1915 & _T_4437; // @[lsu_bus_buffer.scala 383:88] + wire _T_1906 = |buf_age_1; // @[lsu_bus_buffer.scala 383:58] + wire _T_1907 = ~_T_1906; // @[lsu_bus_buffer.scala 383:45] + wire _T_1909 = _T_1907 & _T_2576; // @[lsu_bus_buffer.scala 383:63] + wire _T_1911 = _T_1909 & _T_4432; // @[lsu_bus_buffer.scala 383:88] + wire _T_1900 = |buf_age_0; // @[lsu_bus_buffer.scala 383:58] + wire _T_1901 = ~_T_1900; // @[lsu_bus_buffer.scala 383:45] + wire _T_1903 = _T_1901 & _T_2569; // @[lsu_bus_buffer.scala 383:63] + wire _T_1905 = _T_1903 & _T_4427; // @[lsu_bus_buffer.scala 383:88] + wire [3:0] CmdPtr0Dec = {_T_1923,_T_1917,_T_1911,_T_1905}; // @[Cat.scala 29:58] + wire [7:0] _T_1993 = {4'h0,_T_1923,_T_1917,_T_1911,_T_1905}; // @[Cat.scala 29:58] + wire _T_1996 = _T_1993[4] | _T_1993[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_1998 = _T_1996 | _T_1993[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2000 = _T_1998 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2003 = _T_1993[2] | _T_1993[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2005 = _T_2003 | _T_1993[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2007 = _T_2005 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2010 = _T_1993[1] | _T_1993[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2012 = _T_2010 | _T_1993[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2014 = _T_2012 | _T_1993[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2016 = {_T_2000,_T_2007,_T_2014}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr0 = _T_2016[1:0]; // @[lsu_bus_buffer.scala 396:11] + wire _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 268:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 268:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 268:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 268:114] + reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] + reg buf_nomerge_1; // @[Reg.scala 27:20] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] + reg buf_nomerge_2; // @[Reg.scala 27:20] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] + reg buf_nomerge_3; // @[Reg.scala 27:20] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 268:31] + wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 268:29] + reg _T_4325; // @[Reg.scala 27:20] + reg _T_4322; // @[Reg.scala 27:20] + reg _T_4319; // @[Reg.scala 27:20] + reg _T_4316; // @[Reg.scala 27:20] + wire [3:0] buf_sideeffect = {_T_4325,_T_4322,_T_4319,_T_4316}; // @[Cat.scala 29:58] + wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72] + wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72] + wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72] + wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72] + wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] + wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] + wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] + wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 269:5] + wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 268:140] + wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 271:58] + wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 271:72] + wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] + wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] + wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 271:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 271:101] + wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 269:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 269:117] + wire _T_4477 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4481 = _T_4477 | _T_4458; // @[lsu_bus_buffer.scala 535:74] + wire _T_4472 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4476 = _T_4472 | _T_4455; // @[lsu_bus_buffer.scala 535:74] + wire [1:0] _T_4482 = _T_4481 + _T_4476; // @[lsu_bus_buffer.scala 535:154] + wire _T_4467 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4471 = _T_4467 | _T_4452; // @[lsu_bus_buffer.scala 535:74] + wire [1:0] _GEN_384 = {{1'd0}, _T_4471}; // @[lsu_bus_buffer.scala 535:154] + wire [2:0] _T_4483 = _T_4482 + _GEN_384; // @[lsu_bus_buffer.scala 535:154] + wire _T_4462 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 535:63] + wire _T_4466 = _T_4462 | _T_4449; // @[lsu_bus_buffer.scala 535:74] + wire [2:0] _GEN_385 = {{2'd0}, _T_4466}; // @[lsu_bus_buffer.scala 535:154] + wire [3:0] buf_numvld_pend_any = _T_4483 + _GEN_385; // @[lsu_bus_buffer.scala 535:154] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 273:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 273:31] + wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 273:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 273:89] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 273:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 289:32] + wire _T_4751 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4753 = _T_4751 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4754 = _T_4753 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4755 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4757 = _T_4755 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4758 = _T_4757 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4767 = _T_4754 | _T_4758; // @[lsu_bus_buffer.scala 563:153] + wire _T_4759 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4761 = _T_4759 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4762 = _T_4761 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4768 = _T_4767 | _T_4762; // @[lsu_bus_buffer.scala 563:153] + wire _T_4763 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 563:62] + wire _T_4765 = _T_4763 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 563:73] + wire _T_4766 = _T_4765 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:93] + wire _T_4769 = _T_4768 | _T_4766; // @[lsu_bus_buffer.scala 563:153] + reg obuf_sideeffect; // @[Reg.scala 27:20] + wire _T_4770 = obuf_valid & obuf_sideeffect; // @[lsu_bus_buffer.scala 563:171] + wire _T_4771 = _T_4770 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 563:189] + wire bus_sideeffect_pend = _T_4769 | _T_4771; // @[lsu_bus_buffer.scala 563:157] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 289:74] + wire _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 289:52] + wire _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 289:50] + wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] + wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] + wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] + wire _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 290:36] + wire found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 388:31] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 290:47] + wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58] + wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72] + wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72] + wire _T_1124 = _T_1120 | _T_1121; // @[Mux.scala 27:72] + wire _T_1122 = _T_1025 & _T_1111[2]; // @[Mux.scala 27:72] + wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72] + wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72] + wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72] + wire _T_1128 = ~_T_1126; // @[lsu_bus_buffer.scala 291:23] + wire _T_1129 = _T_1108 & _T_1128; // @[lsu_bus_buffer.scala 291:21] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 291:141] + wire _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 291:105] + wire _T_1148 = _T_1129 & _T_1147; // @[lsu_bus_buffer.scala 291:103] + reg buf_dual_3; // @[Reg.scala 27:20] + reg buf_dual_2; // @[Reg.scala 27:20] + reg buf_dual_1; // @[Reg.scala 27:20] + reg buf_dual_0; // @[Reg.scala 27:20] + wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58] + wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72] + wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72] + wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72] + wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72] + wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72] + reg buf_samedw_3; // @[Reg.scala 27:20] + reg buf_samedw_2; // @[Reg.scala 27:20] + reg buf_samedw_1; // @[Reg.scala 27:20] + reg buf_samedw_0; // @[Reg.scala 27:20] + wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58] + wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72] + wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72] + wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72] + wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72] + wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] + wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] + wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] + wire _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 292:77] + wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] + wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] + wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] + wire _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 292:150] + wire _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 292:148] + wire _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 292:8] + wire [3:0] _T_1959 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 384:62] + wire [3:0] _T_1960 = buf_age_3 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1961 = |_T_1960; // @[lsu_bus_buffer.scala 384:76] + wire _T_1962 = ~_T_1961; // @[lsu_bus_buffer.scala 384:45] + wire _T_1964 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1965 = _T_1962 & _T_1964; // @[lsu_bus_buffer.scala 384:81] + wire _T_1967 = _T_1965 & _T_2590; // @[lsu_bus_buffer.scala 384:98] + wire _T_1969 = _T_1967 & _T_4442; // @[lsu_bus_buffer.scala 384:123] + wire [3:0] _T_1949 = buf_age_2 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1950 = |_T_1949; // @[lsu_bus_buffer.scala 384:76] + wire _T_1951 = ~_T_1950; // @[lsu_bus_buffer.scala 384:45] + wire _T_1953 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1954 = _T_1951 & _T_1953; // @[lsu_bus_buffer.scala 384:81] + wire _T_1956 = _T_1954 & _T_2583; // @[lsu_bus_buffer.scala 384:98] + wire _T_1958 = _T_1956 & _T_4437; // @[lsu_bus_buffer.scala 384:123] + wire [3:0] _T_1938 = buf_age_1 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1939 = |_T_1938; // @[lsu_bus_buffer.scala 384:76] + wire _T_1940 = ~_T_1939; // @[lsu_bus_buffer.scala 384:45] + wire _T_1942 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1943 = _T_1940 & _T_1942; // @[lsu_bus_buffer.scala 384:81] + wire _T_1945 = _T_1943 & _T_2576; // @[lsu_bus_buffer.scala 384:98] + wire _T_1947 = _T_1945 & _T_4432; // @[lsu_bus_buffer.scala 384:123] + wire [3:0] _T_1927 = buf_age_0 & _T_1959; // @[lsu_bus_buffer.scala 384:59] + wire _T_1928 = |_T_1927; // @[lsu_bus_buffer.scala 384:76] + wire _T_1929 = ~_T_1928; // @[lsu_bus_buffer.scala 384:45] + wire _T_1931 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 384:83] + wire _T_1932 = _T_1929 & _T_1931; // @[lsu_bus_buffer.scala 384:81] + wire _T_1934 = _T_1932 & _T_2569; // @[lsu_bus_buffer.scala 384:98] + wire _T_1936 = _T_1934 & _T_4427; // @[lsu_bus_buffer.scala 384:123] + wire [3:0] CmdPtr1Dec = {_T_1969,_T_1958,_T_1947,_T_1936}; // @[Cat.scala 29:58] + wire found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 389:31] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 292:181] + wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] + wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] + wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] + wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72] + wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72] + wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] + wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] + wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] + wire _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 292:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 292:269] + wire _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 291:164] + wire _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 289:98] + reg obuf_write; // @[Reg.scala 27:20] + reg obuf_cmd_done; // @[Reg.scala 27:20] + reg obuf_data_done; // @[Reg.scala 27:20] + wire _T_4825 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 567:54] + wire _T_4826 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 567:75] + wire _T_4827 = io_lsu_axi_aw_ready & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 567:153] + wire _T_4828 = _T_4825 ? _T_4826 : _T_4827; // @[lsu_bus_buffer.scala 567:39] + wire bus_cmd_ready = obuf_write ? _T_4828 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 567:23] + wire _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 293:48] + wire _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 293:46] + reg obuf_nosend; // @[Reg.scala 27:20] + wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 293:60] + wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 293:29] + wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 293:77] + wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 293:75] + reg [31:0] obuf_addr; // @[Reg.scala 27:20] + wire _T_4776 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4777 = obuf_valid & _T_4776; // @[lsu_bus_buffer.scala 565:19] + wire _T_4779 = obuf_tag1 == 2'h0; // @[lsu_bus_buffer.scala 565:107] + wire _T_4780 = obuf_merge & _T_4779; // @[lsu_bus_buffer.scala 565:95] + wire _T_4781 = _T_3565 | _T_4780; // @[lsu_bus_buffer.scala 565:81] + wire _T_4782 = ~_T_4781; // @[lsu_bus_buffer.scala 565:61] + wire _T_4783 = _T_4777 & _T_4782; // @[lsu_bus_buffer.scala 565:59] + wire _T_4817 = _T_4751 & _T_4783; // @[Mux.scala 27:72] + wire _T_4787 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4788 = obuf_valid & _T_4787; // @[lsu_bus_buffer.scala 565:19] + wire _T_4790 = obuf_tag1 == 2'h1; // @[lsu_bus_buffer.scala 565:107] + wire _T_4791 = obuf_merge & _T_4790; // @[lsu_bus_buffer.scala 565:95] + wire _T_4792 = _T_3756 | _T_4791; // @[lsu_bus_buffer.scala 565:81] + wire _T_4793 = ~_T_4792; // @[lsu_bus_buffer.scala 565:61] + wire _T_4794 = _T_4788 & _T_4793; // @[lsu_bus_buffer.scala 565:59] + wire _T_4818 = _T_4755 & _T_4794; // @[Mux.scala 27:72] + wire _T_4821 = _T_4817 | _T_4818; // @[Mux.scala 27:72] + wire _T_4798 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4799 = obuf_valid & _T_4798; // @[lsu_bus_buffer.scala 565:19] + wire _T_4801 = obuf_tag1 == 2'h2; // @[lsu_bus_buffer.scala 565:107] + wire _T_4802 = obuf_merge & _T_4801; // @[lsu_bus_buffer.scala 565:95] + wire _T_4803 = _T_3947 | _T_4802; // @[lsu_bus_buffer.scala 565:81] + wire _T_4804 = ~_T_4803; // @[lsu_bus_buffer.scala 565:61] + wire _T_4805 = _T_4799 & _T_4804; // @[lsu_bus_buffer.scala 565:59] + wire _T_4819 = _T_4759 & _T_4805; // @[Mux.scala 27:72] + wire _T_4822 = _T_4821 | _T_4819; // @[Mux.scala 27:72] + wire _T_4809 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 565:37] + wire _T_4810 = obuf_valid & _T_4809; // @[lsu_bus_buffer.scala 565:19] + wire _T_4812 = obuf_tag1 == 2'h3; // @[lsu_bus_buffer.scala 565:107] + wire _T_4813 = obuf_merge & _T_4812; // @[lsu_bus_buffer.scala 565:95] + wire _T_4814 = _T_4138 | _T_4813; // @[lsu_bus_buffer.scala 565:81] + wire _T_4815 = ~_T_4814; // @[lsu_bus_buffer.scala 565:61] + wire _T_4816 = _T_4810 & _T_4815; // @[lsu_bus_buffer.scala 565:59] + wire _T_4820 = _T_4763 & _T_4816; // @[Mux.scala 27:72] + wire bus_addr_match_pending = _T_4822 | _T_4820; // @[Mux.scala 27:72] + wire _T_1237 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 293:94] + wire _T_1238 = _T_1236 & _T_1237; // @[lsu_bus_buffer.scala 293:92] + wire obuf_wr_en = _T_1238 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 293:118] + wire _T_1240 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 296:47] + wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 568:40] + wire _T_4832 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 570:35] + wire bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 569:40] + wire _T_4833 = obuf_data_done | bus_wdata_sent; // @[lsu_bus_buffer.scala 570:70] + wire _T_4834 = _T_4832 & _T_4833; // @[lsu_bus_buffer.scala 570:52] + wire _T_4835 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 570:112] + wire bus_cmd_sent = _T_4834 | _T_4835; // @[lsu_bus_buffer.scala 570:89] + wire _T_1241 = bus_cmd_sent | _T_1240; // @[lsu_bus_buffer.scala 296:33] + wire _T_1242 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 296:65] + wire _T_1243 = _T_1241 & _T_1242; // @[lsu_bus_buffer.scala 296:63] + wire _T_1244 = _T_1243 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 296:77] + wire obuf_rst = _T_1244 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 296:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 297:26] + wire [31:0] _T_1281 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1282 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1283 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1284 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1285 = _T_1281 | _T_1282; // @[Mux.scala 27:72] + wire [31:0] _T_1286 = _T_1285 | _T_1283; // @[Mux.scala 27:72] + wire [31:0] _T_1287 = _T_1286 | _T_1284; // @[Mux.scala 27:72] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1287; // @[lsu_bus_buffer.scala 299:25] + reg [1:0] buf_sz_0; // @[Reg.scala 27:20] + wire [1:0] _T_1294 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire [1:0] _T_1295 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_2; // @[Reg.scala 27:20] + wire [1:0] _T_1296 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_3; // @[Reg.scala 27:20] + wire [1:0] _T_1297 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1298 = _T_1294 | _T_1295; // @[Mux.scala 27:72] + wire [1:0] _T_1299 = _T_1298 | _T_1296; // @[Mux.scala 27:72] + wire [1:0] _T_1300 = _T_1299 | _T_1297; // @[Mux.scala 27:72] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1300; // @[lsu_bus_buffer.scala 302:23] + wire [7:0] _T_2018 = {4'h0,_T_1969,_T_1958,_T_1947,_T_1936}; // @[Cat.scala 29:58] + wire _T_2021 = _T_2018[4] | _T_2018[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_2023 = _T_2021 | _T_2018[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2025 = _T_2023 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2028 = _T_2018[2] | _T_2018[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2030 = _T_2028 | _T_2018[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2032 = _T_2030 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2035 = _T_2018[1] | _T_2018[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2037 = _T_2035 | _T_2018[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2039 = _T_2037 | _T_2018[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2041 = {_T_2025,_T_2032,_T_2039}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr1 = _T_2041[1:0]; // @[lsu_bus_buffer.scala 398:11] + wire _T_1302 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 310:39] + wire _T_1303 = ~_T_1302; // @[lsu_bus_buffer.scala 310:26] + wire obuf_cmd_done_in = _T_1303 & _T_4832; // @[lsu_bus_buffer.scala 310:51] + wire obuf_data_done_in = _T_1303 & _T_4833; // @[lsu_bus_buffer.scala 313:52] + wire _T_1309 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 314:72] + wire _T_1312 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 314:98] + wire _T_1313 = obuf_sz_in[0] & _T_1312; // @[lsu_bus_buffer.scala 314:96] + wire _T_1314 = _T_1309 | _T_1313; // @[lsu_bus_buffer.scala 314:79] + wire _T_1317 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 314:153] + wire _T_1318 = ~_T_1317; // @[lsu_bus_buffer.scala 314:134] + wire _T_1319 = obuf_sz_in[1] & _T_1318; // @[lsu_bus_buffer.scala 314:132] + wire _T_1320 = _T_1314 | _T_1319; // @[lsu_bus_buffer.scala 314:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1320; // @[lsu_bus_buffer.scala 314:28] + wire _T_1337 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 328:40] + wire _T_1338 = _T_1337 & obuf_aligned_in; // @[lsu_bus_buffer.scala 328:60] + wire _T_1339 = ~obuf_sideeffect; // @[lsu_bus_buffer.scala 328:80] + wire _T_1340 = _T_1338 & _T_1339; // @[lsu_bus_buffer.scala 328:78] + wire _T_1341 = ~obuf_write; // @[lsu_bus_buffer.scala 328:99] + wire _T_1342 = _T_1340 & _T_1341; // @[lsu_bus_buffer.scala 328:97] + wire _T_1343 = ~obuf_write_in; // @[lsu_bus_buffer.scala 328:113] + wire _T_1344 = _T_1342 & _T_1343; // @[lsu_bus_buffer.scala 328:111] + wire _T_1345 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 328:130] + wire _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 328:128] + wire _T_1347 = ~obuf_nosend; // @[lsu_bus_buffer.scala 329:20] + wire _T_1348 = obuf_valid & _T_1347; // @[lsu_bus_buffer.scala 329:18] + reg obuf_rdrsp_pend; // @[Reg.scala 27:20] + wire bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 571:38] + reg [2:0] obuf_rdrsp_tag; // @[Reg.scala 27:20] + wire _T_1349 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 329:90] + wire _T_1350 = bus_rsp_read & _T_1349; // @[lsu_bus_buffer.scala 329:70] + wire _T_1351 = ~_T_1350; // @[lsu_bus_buffer.scala 329:55] + wire _T_1352 = obuf_rdrsp_pend & _T_1351; // @[lsu_bus_buffer.scala 329:53] + wire _T_1353 = _T_1348 | _T_1352; // @[lsu_bus_buffer.scala 329:34] + wire obuf_nosend_in = _T_1346 & _T_1353; // @[lsu_bus_buffer.scala 328:177] + wire _T_1321 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 322:45] + wire _T_1322 = obuf_wr_en & _T_1321; // @[lsu_bus_buffer.scala 322:43] + wire _T_1323 = ~_T_1322; // @[lsu_bus_buffer.scala 322:30] + wire _T_1324 = _T_1323 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 322:62] + wire _T_1328 = _T_1324 & _T_1351; // @[lsu_bus_buffer.scala 322:80] + wire _T_1330 = bus_cmd_sent & _T_1341; // @[lsu_bus_buffer.scala 322:155] + wire _T_1331 = _T_1328 | _T_1330; // @[lsu_bus_buffer.scala 322:139] + wire obuf_rdrsp_pend_in = _T_1331 & _T_2594; // @[lsu_bus_buffer.scala 322:171] + wire obuf_rdrsp_pend_en = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 323:47] + wire [7:0] _T_1356 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1357 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1358 = io_lsu_addr_r[2] ? _T_1356 : _T_1357; // @[lsu_bus_buffer.scala 330:46] + wire [3:0] _T_1377 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1378 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1379 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1380 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1381 = _T_1377 | _T_1378; // @[Mux.scala 27:72] + wire [3:0] _T_1382 = _T_1381 | _T_1379; // @[Mux.scala 27:72] + wire [3:0] _T_1383 = _T_1382 | _T_1380; // @[Mux.scala 27:72] + wire [7:0] _T_1385 = {_T_1383,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1398 = {4'h0,_T_1383}; // @[Cat.scala 29:58] + wire [7:0] _T_1399 = _T_1287[2] ? _T_1385 : _T_1398; // @[lsu_bus_buffer.scala 331:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1358 : _T_1399; // @[lsu_bus_buffer.scala 330:28] + wire [7:0] _T_1401 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1402 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1403 = io_end_addr_r[2] ? _T_1401 : _T_1402; // @[lsu_bus_buffer.scala 332:46] + wire _T_1404 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 62:123] + wire _T_1405 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 62:123] + wire _T_1406 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 62:123] + wire _T_1407 = CmdPtr1 == 2'h3; // @[lsu_bus_buffer.scala 62:123] + wire [31:0] _T_1408 = _T_1404 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1409 = _T_1405 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1410 = _T_1406 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1411 = _T_1407 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1412 = _T_1408 | _T_1409; // @[Mux.scala 27:72] + wire [31:0] _T_1413 = _T_1412 | _T_1410; // @[Mux.scala 27:72] + wire [31:0] _T_1414 = _T_1413 | _T_1411; // @[Mux.scala 27:72] + wire [3:0] _T_1422 = _T_1404 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1423 = _T_1405 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1424 = _T_1406 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1425 = _T_1407 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1426 = _T_1422 | _T_1423; // @[Mux.scala 27:72] + wire [3:0] _T_1427 = _T_1426 | _T_1424; // @[Mux.scala 27:72] + wire [3:0] _T_1428 = _T_1427 | _T_1425; // @[Mux.scala 27:72] + wire [7:0] _T_1430 = {_T_1428,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1443 = {4'h0,_T_1428}; // @[Cat.scala 29:58] + wire [7:0] _T_1444 = _T_1414[2] ? _T_1430 : _T_1443; // @[lsu_bus_buffer.scala 333:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1403 : _T_1444; // @[lsu_bus_buffer.scala 332:28] + wire [63:0] _T_1446 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1447 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1448 = io_lsu_addr_r[2] ? _T_1446 : _T_1447; // @[lsu_bus_buffer.scala 335:44] + wire [31:0] _T_1467 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1468 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1469 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1470 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1471 = _T_1467 | _T_1468; // @[Mux.scala 27:72] + wire [31:0] _T_1472 = _T_1471 | _T_1469; // @[Mux.scala 27:72] + wire [31:0] _T_1473 = _T_1472 | _T_1470; // @[Mux.scala 27:72] + wire [63:0] _T_1475 = {_T_1473,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1488 = {32'h0,_T_1473}; // @[Cat.scala 29:58] + wire [63:0] _T_1489 = _T_1287[2] ? _T_1475 : _T_1488; // @[lsu_bus_buffer.scala 336:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1448 : _T_1489; // @[lsu_bus_buffer.scala 335:26] + wire [63:0] _T_1491 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1492 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1493 = io_end_addr_r[2] ? _T_1491 : _T_1492; // @[lsu_bus_buffer.scala 337:44] + wire [31:0] _T_1512 = _T_1404 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1513 = _T_1405 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1514 = _T_1406 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1515 = _T_1407 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1516 = _T_1512 | _T_1513; // @[Mux.scala 27:72] + wire [31:0] _T_1517 = _T_1516 | _T_1514; // @[Mux.scala 27:72] + wire [31:0] _T_1518 = _T_1517 | _T_1515; // @[Mux.scala 27:72] + wire [63:0] _T_1520 = {_T_1518,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1533 = {32'h0,_T_1518}; // @[Cat.scala 29:58] + wire [63:0] _T_1534 = _T_1414[2] ? _T_1520 : _T_1533; // @[lsu_bus_buffer.scala 338:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1493 : _T_1534; // @[lsu_bus_buffer.scala 337:26] + wire _T_1619 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 344:30] + wire _T_1620 = _T_1619 & found_cmdptr0; // @[lsu_bus_buffer.scala 344:43] + wire _T_1621 = _T_1620 & found_cmdptr1; // @[lsu_bus_buffer.scala 344:59] + wire _T_1635 = _T_1621 & _T_1107; // @[lsu_bus_buffer.scala 344:75] + wire [2:0] _T_1640 = _T_1404 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1641 = _T_1405 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1644 = _T_1640 | _T_1641; // @[Mux.scala 27:72] + wire [2:0] _T_1642 = _T_1406 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1645 = _T_1644 | _T_1642; // @[Mux.scala 27:72] + wire [2:0] _T_1643 = _T_1407 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1646 = _T_1645 | _T_1643; // @[Mux.scala 27:72] + wire _T_1648 = _T_1646 == 3'h2; // @[lsu_bus_buffer.scala 344:150] + wire _T_1649 = _T_1635 & _T_1648; // @[lsu_bus_buffer.scala 344:118] + wire _T_1670 = _T_1649 & _T_1128; // @[lsu_bus_buffer.scala 344:161] + wire _T_1688 = _T_1670 & _T_1053; // @[lsu_bus_buffer.scala 345:85] + wire _T_1725 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 346:36] + reg buf_dualhi_3; // @[Reg.scala 27:20] + reg buf_dualhi_2; // @[Reg.scala 27:20] + reg buf_dualhi_1; // @[Reg.scala 27:20] + reg buf_dualhi_0; // @[Reg.scala 27:20] + wire [3:0] _T_1728 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58] + wire _T_1737 = _T_1023 & _T_1728[0]; // @[Mux.scala 27:72] + wire _T_1738 = _T_1024 & _T_1728[1]; // @[Mux.scala 27:72] + wire _T_1741 = _T_1737 | _T_1738; // @[Mux.scala 27:72] + wire _T_1739 = _T_1025 & _T_1728[2]; // @[Mux.scala 27:72] + wire _T_1742 = _T_1741 | _T_1739; // @[Mux.scala 27:72] + wire _T_1740 = _T_1026 & _T_1728[3]; // @[Mux.scala 27:72] + wire _T_1743 = _T_1742 | _T_1740; // @[Mux.scala 27:72] + wire _T_1745 = ~_T_1743; // @[lsu_bus_buffer.scala 346:107] + wire _T_1746 = _T_1725 & _T_1745; // @[lsu_bus_buffer.scala 346:105] + wire _T_1766 = _T_1746 & _T_1185; // @[lsu_bus_buffer.scala 346:177] + wire _T_1767 = _T_1688 & _T_1766; // @[lsu_bus_buffer.scala 345:122] + wire _T_1768 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 347:19] + wire _T_1769 = _T_1768 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 347:35] + wire obuf_merge_en = _T_1767 | _T_1769; // @[lsu_bus_buffer.scala 346:250] + wire _T_1537 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1538 = obuf_byteen0_in[0] | _T_1537; // @[lsu_bus_buffer.scala 339:63] + wire _T_1541 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1542 = obuf_byteen0_in[1] | _T_1541; // @[lsu_bus_buffer.scala 339:63] + wire _T_1545 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1546 = obuf_byteen0_in[2] | _T_1545; // @[lsu_bus_buffer.scala 339:63] + wire _T_1549 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1550 = obuf_byteen0_in[3] | _T_1549; // @[lsu_bus_buffer.scala 339:63] + wire _T_1553 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1554 = obuf_byteen0_in[4] | _T_1553; // @[lsu_bus_buffer.scala 339:63] + wire _T_1557 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1558 = obuf_byteen0_in[5] | _T_1557; // @[lsu_bus_buffer.scala 339:63] + wire _T_1561 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1562 = obuf_byteen0_in[6] | _T_1561; // @[lsu_bus_buffer.scala 339:63] + wire _T_1565 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 339:80] + wire _T_1566 = obuf_byteen0_in[7] | _T_1565; // @[lsu_bus_buffer.scala 339:63] + wire [7:0] obuf_byteen_in = {_T_1566,_T_1562,_T_1558,_T_1554,_T_1550,_T_1546,_T_1542,_T_1538}; // @[Cat.scala 29:58] + wire [7:0] _T_1577 = _T_1537 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1582 = _T_1541 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1587 = _T_1545 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1592 = _T_1549 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1597 = _T_1553 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1602 = _T_1557 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1607 = _T_1561 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 340:44] + wire [7:0] _T_1612 = _T_1565 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 340:44] + wire [63:0] obuf_data_in = {_T_1612,_T_1607,_T_1602,_T_1597,_T_1592,_T_1587,_T_1582,_T_1577}; // @[Cat.scala 29:58] + wire _T_1771 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 349:58] + wire _T_1772 = ~obuf_rst; // @[lsu_bus_buffer.scala 349:93] + wire _T_1780 = io_lsu_bus_obuf_c1_clken & obuf_wr_en; // @[lib.scala 388:57] + reg [1:0] obuf_sz; // @[Reg.scala 27:20] + reg [7:0] obuf_byteen; // @[Reg.scala 27:20] + reg [63:0] obuf_data; // @[Reg.scala 27:20] + wire _T_1792 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1793 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 370:30] + wire _T_1794 = ibuf_valid & _T_1793; // @[lsu_bus_buffer.scala 370:19] + wire _T_1795 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 371:18] + wire _T_1796 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 371:57] + wire _T_1797 = io_ldst_dual_r & _T_1796; // @[lsu_bus_buffer.scala 371:45] + wire _T_1798 = _T_1795 | _T_1797; // @[lsu_bus_buffer.scala 371:27] + wire _T_1799 = io_lsu_busreq_r & _T_1798; // @[lsu_bus_buffer.scala 370:58] + wire _T_1800 = _T_1794 | _T_1799; // @[lsu_bus_buffer.scala 370:39] + wire _T_1801 = ~_T_1800; // @[lsu_bus_buffer.scala 370:5] + wire _T_1802 = _T_1792 & _T_1801; // @[lsu_bus_buffer.scala 369:76] + wire _T_1803 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1804 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 370:30] + wire _T_1805 = ibuf_valid & _T_1804; // @[lsu_bus_buffer.scala 370:19] + wire _T_1806 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 371:18] + wire _T_1807 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 371:57] + wire _T_1808 = io_ldst_dual_r & _T_1807; // @[lsu_bus_buffer.scala 371:45] + wire _T_1809 = _T_1806 | _T_1808; // @[lsu_bus_buffer.scala 371:27] + wire _T_1810 = io_lsu_busreq_r & _T_1809; // @[lsu_bus_buffer.scala 370:58] + wire _T_1811 = _T_1805 | _T_1810; // @[lsu_bus_buffer.scala 370:39] + wire _T_1812 = ~_T_1811; // @[lsu_bus_buffer.scala 370:5] + wire _T_1813 = _T_1803 & _T_1812; // @[lsu_bus_buffer.scala 369:76] + wire _T_1814 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1815 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 370:30] + wire _T_1816 = ibuf_valid & _T_1815; // @[lsu_bus_buffer.scala 370:19] + wire _T_1817 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 371:18] + wire _T_1818 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 371:57] + wire _T_1819 = io_ldst_dual_r & _T_1818; // @[lsu_bus_buffer.scala 371:45] + wire _T_1820 = _T_1817 | _T_1819; // @[lsu_bus_buffer.scala 371:27] + wire _T_1821 = io_lsu_busreq_r & _T_1820; // @[lsu_bus_buffer.scala 370:58] + wire _T_1822 = _T_1816 | _T_1821; // @[lsu_bus_buffer.scala 370:39] + wire _T_1823 = ~_T_1822; // @[lsu_bus_buffer.scala 370:5] + wire _T_1824 = _T_1814 & _T_1823; // @[lsu_bus_buffer.scala 369:76] + wire _T_1825 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 369:65] + wire _T_1826 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 370:30] + wire _T_1828 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 371:18] + wire _T_1829 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 371:57] + wire [1:0] _T_1837 = _T_1824 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] + wire [1:0] _T_1838 = _T_1813 ? 2'h1 : _T_1837; // @[Mux.scala 98:16] + wire [1:0] WrPtr0_m = _T_1802 ? 2'h0 : _T_1838; // @[Mux.scala 98:16] + wire _T_1843 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 376:33] + wire _T_1844 = io_lsu_busreq_m & _T_1843; // @[lsu_bus_buffer.scala 376:22] + wire _T_1845 = _T_1794 | _T_1844; // @[lsu_bus_buffer.scala 375:112] + wire _T_1851 = _T_1845 | _T_1799; // @[lsu_bus_buffer.scala 376:42] + wire _T_1852 = ~_T_1851; // @[lsu_bus_buffer.scala 375:78] + wire _T_1853 = _T_1792 & _T_1852; // @[lsu_bus_buffer.scala 375:76] + wire _T_1857 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 376:33] + wire _T_1858 = io_lsu_busreq_m & _T_1857; // @[lsu_bus_buffer.scala 376:22] + wire _T_1859 = _T_1805 | _T_1858; // @[lsu_bus_buffer.scala 375:112] + wire _T_1865 = _T_1859 | _T_1810; // @[lsu_bus_buffer.scala 376:42] + wire _T_1866 = ~_T_1865; // @[lsu_bus_buffer.scala 375:78] + wire _T_1867 = _T_1803 & _T_1866; // @[lsu_bus_buffer.scala 375:76] + wire _T_1871 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 376:33] + wire _T_1872 = io_lsu_busreq_m & _T_1871; // @[lsu_bus_buffer.scala 376:22] + wire _T_1873 = _T_1816 | _T_1872; // @[lsu_bus_buffer.scala 375:112] + wire _T_1879 = _T_1873 | _T_1821; // @[lsu_bus_buffer.scala 376:42] + wire _T_1880 = ~_T_1879; // @[lsu_bus_buffer.scala 375:78] + wire _T_1881 = _T_1814 & _T_1880; // @[lsu_bus_buffer.scala 375:76] + reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 514:63] + wire _T_2717 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2718 = buf_rspageQ_0[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2714 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2715 = buf_rspageQ_0[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2711 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2712 = buf_rspageQ_0[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2708 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 419:102] + wire _T_2709 = buf_rspageQ_0[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_0 = {_T_2718,_T_2715,_T_2712,_T_2709}; // @[Cat.scala 29:58] + wire _T_1972 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 387:65] + wire _T_1973 = ~_T_1972; // @[lsu_bus_buffer.scala 387:44] + wire _T_1975 = _T_1973 & _T_2708; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 514:63] + wire _T_2733 = buf_rspageQ_1[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2730 = buf_rspageQ_1[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2727 = buf_rspageQ_1[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2724 = buf_rspageQ_1[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_1 = {_T_2733,_T_2730,_T_2727,_T_2724}; // @[Cat.scala 29:58] + wire _T_1976 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 387:65] + wire _T_1977 = ~_T_1976; // @[lsu_bus_buffer.scala 387:44] + wire _T_1979 = _T_1977 & _T_2711; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 514:63] + wire _T_2748 = buf_rspageQ_2[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2745 = buf_rspageQ_2[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2742 = buf_rspageQ_2[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2739 = buf_rspageQ_2[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_2 = {_T_2748,_T_2745,_T_2742,_T_2739}; // @[Cat.scala 29:58] + wire _T_1980 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 387:65] + wire _T_1981 = ~_T_1980; // @[lsu_bus_buffer.scala 387:44] + wire _T_1983 = _T_1981 & _T_2714; // @[lsu_bus_buffer.scala 387:70] + reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 514:63] + wire _T_2763 = buf_rspageQ_3[3] & _T_2717; // @[lsu_bus_buffer.scala 419:87] + wire _T_2760 = buf_rspageQ_3[2] & _T_2714; // @[lsu_bus_buffer.scala 419:87] + wire _T_2757 = buf_rspageQ_3[1] & _T_2711; // @[lsu_bus_buffer.scala 419:87] + wire _T_2754 = buf_rspageQ_3[0] & _T_2708; // @[lsu_bus_buffer.scala 419:87] + wire [3:0] buf_rsp_pickage_3 = {_T_2763,_T_2760,_T_2757,_T_2754}; // @[Cat.scala 29:58] + wire _T_1984 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 387:65] + wire _T_1985 = ~_T_1984; // @[lsu_bus_buffer.scala 387:44] + wire _T_1987 = _T_1985 & _T_2717; // @[lsu_bus_buffer.scala 387:70] + wire [7:0] _T_2043 = {4'h0,_T_1987,_T_1983,_T_1979,_T_1975}; // @[Cat.scala 29:58] + wire _T_2046 = _T_2043[4] | _T_2043[5]; // @[lsu_bus_buffer.scala 391:42] + wire _T_2048 = _T_2046 | _T_2043[6]; // @[lsu_bus_buffer.scala 391:48] + wire _T_2050 = _T_2048 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:54] + wire _T_2053 = _T_2043[2] | _T_2043[3]; // @[lsu_bus_buffer.scala 391:67] + wire _T_2055 = _T_2053 | _T_2043[6]; // @[lsu_bus_buffer.scala 391:73] + wire _T_2057 = _T_2055 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:79] + wire _T_2060 = _T_2043[1] | _T_2043[3]; // @[lsu_bus_buffer.scala 391:92] + wire _T_2062 = _T_2060 | _T_2043[5]; // @[lsu_bus_buffer.scala 391:98] + wire _T_2064 = _T_2062 | _T_2043[7]; // @[lsu_bus_buffer.scala 391:104] + wire [2:0] _T_2066 = {_T_2050,_T_2057,_T_2064}; // @[Cat.scala 29:58] + wire _T_3535 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 445:77] + wire _T_3536 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 445:97] + wire _T_3537 = _T_3535 & _T_3536; // @[lsu_bus_buffer.scala 445:95] + wire _T_3538 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 445:112] + wire _T_3540 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 445:144] + wire _T_3541 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3542 = _T_3540 & _T_3541; // @[lsu_bus_buffer.scala 445:161] + wire _T_3543 = _T_3539 | _T_3542; // @[lsu_bus_buffer.scala 445:132] + wire _T_3544 = _T_853 & _T_3543; // @[lsu_bus_buffer.scala 445:63] + wire _T_3545 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3546 = ibuf_drain_vld & _T_3545; // @[lsu_bus_buffer.scala 445:201] + wire _T_3547 = _T_3544 | _T_3546; // @[lsu_bus_buffer.scala 445:183] + wire bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 572:39] + wire _T_3636 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 475:73] + wire _T_3637 = bus_rsp_write & _T_3636; // @[lsu_bus_buffer.scala 475:52] + wire _T_3638 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 476:46] + reg _T_4302; // @[Reg.scala 27:20] + reg _T_4300; // @[Reg.scala 27:20] + reg _T_4298; // @[Reg.scala 27:20] + reg _T_4296; // @[Reg.scala 27:20] + wire [3:0] buf_ldfwd = {_T_4302,_T_4300,_T_4298,_T_4296}; // @[Cat.scala 29:58] + reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_386 = {{1'd0}, buf_ldfwdtag_0}; // @[lsu_bus_buffer.scala 477:47] + wire _T_3640 = io_lsu_axi_r_bits_id == _GEN_386; // @[lsu_bus_buffer.scala 477:47] + wire _T_3641 = buf_ldfwd[0] & _T_3640; // @[lsu_bus_buffer.scala 477:27] + wire _T_3642 = _T_3638 | _T_3641; // @[lsu_bus_buffer.scala 476:77] + wire _T_3643 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 478:26] + wire _T_3645 = ~buf_write[0]; // @[lsu_bus_buffer.scala 478:44] + wire _T_3646 = _T_3643 & _T_3645; // @[lsu_bus_buffer.scala 478:42] + wire _T_3647 = _T_3646 & buf_samedw_0; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_387 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 478:94] + wire _T_3648 = io_lsu_axi_r_bits_id == _GEN_387; // @[lsu_bus_buffer.scala 478:94] + wire _T_3649 = _T_3647 & _T_3648; // @[lsu_bus_buffer.scala 478:74] + wire _T_3650 = _T_3642 | _T_3649; // @[lsu_bus_buffer.scala 477:71] + wire _T_3651 = bus_rsp_read & _T_3650; // @[lsu_bus_buffer.scala 476:25] + wire _T_3652 = _T_3637 | _T_3651; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_52 = _T_3592 & _T_3652; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_3558 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_3554 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire [3:0] _T_3687 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 492:21] + reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20] + wire [1:0] _GEN_33 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_34 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_33; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_35 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_34; // @[lsu_bus_buffer.scala 492:58] + wire [2:0] _GEN_389 = {{1'd0}, _GEN_35}; // @[lsu_bus_buffer.scala 492:58] + wire _T_3689 = io_lsu_axi_r_bits_id == _GEN_389; // @[lsu_bus_buffer.scala 492:58] + wire _T_3690 = _T_3687[0] & _T_3689; // @[lsu_bus_buffer.scala 492:38] + wire _T_3691 = _T_3648 | _T_3690; // @[lsu_bus_buffer.scala 491:95] + wire _T_3692 = bus_rsp_read & _T_3691; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_46 = _T_3677 & _T_3692; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_3592 ? buf_resp_state_bus_en_0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_3558 ? buf_cmd_state_bus_en_0 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_77 = _T_3554 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire buf_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58] + wire _T_3571 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3572 = _T_3571 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire [1:0] RspPtr = _T_2066[1:0]; // @[lsu_bus_buffer.scala 399:10] + wire _T_3698 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 499:37] + wire _T_3699 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_3700 = buf_dual_0 & _T_3699; // @[lsu_bus_buffer.scala 499:80] + wire _T_3701 = _T_3698 | _T_3700; // @[lsu_bus_buffer.scala 499:65] + wire _T_3702 = _T_3701 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_41 = _T_3695 ? _T_3702 : _T_3703; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_3677 ? _T_3572 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_3592 ? _T_3572 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_3558 ? _T_3572 : _GEN_54; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_3554 ? obuf_rdrsp_pend_en : _GEN_64; // @[Conditional.scala 39:67] + wire buf_state_en_0 = _T_3531 ? _T_3547 : _GEN_74; // @[Conditional.scala 40:58] + wire _T_2068 = _T_1792 & buf_state_en_0; // @[lsu_bus_buffer.scala 411:94] + wire _T_2074 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 413:23] + wire _T_2076 = _T_2074 & _T_3535; // @[lsu_bus_buffer.scala 413:41] + wire _T_2078 = _T_2076 & _T_1795; // @[lsu_bus_buffer.scala 413:71] + wire _T_2080 = _T_2078 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2081 = _T_4466 | _T_2080; // @[lsu_bus_buffer.scala 412:86] + wire _T_2082 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 414:17] + wire _T_2083 = _T_2082 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 414:35] + wire _T_2085 = _T_2083 & _T_1796; // @[lsu_bus_buffer.scala 414:52] + wire _T_2087 = _T_2085 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2088 = _T_2081 | _T_2087; // @[lsu_bus_buffer.scala 413:114] + wire _T_2089 = _T_2068 & _T_2088; // @[lsu_bus_buffer.scala 411:113] + wire _T_2091 = _T_2089 | buf_age_0[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2105 = _T_2078 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2106 = _T_4471 | _T_2105; // @[lsu_bus_buffer.scala 412:86] + wire _T_2112 = _T_2085 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2113 = _T_2106 | _T_2112; // @[lsu_bus_buffer.scala 413:114] + wire _T_2114 = _T_2068 & _T_2113; // @[lsu_bus_buffer.scala 411:113] + wire _T_2116 = _T_2114 | buf_age_0[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2130 = _T_2078 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2131 = _T_4476 | _T_2130; // @[lsu_bus_buffer.scala 412:86] + wire _T_2137 = _T_2085 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2138 = _T_2131 | _T_2137; // @[lsu_bus_buffer.scala 413:114] + wire _T_2139 = _T_2068 & _T_2138; // @[lsu_bus_buffer.scala 411:113] + wire _T_2141 = _T_2139 | buf_age_0[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2155 = _T_2078 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2156 = _T_4481 | _T_2155; // @[lsu_bus_buffer.scala 412:86] + wire _T_2162 = _T_2085 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2163 = _T_2156 | _T_2162; // @[lsu_bus_buffer.scala 413:114] + wire _T_2164 = _T_2068 & _T_2163; // @[lsu_bus_buffer.scala 411:113] + wire _T_2166 = _T_2164 | buf_age_0[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2168 = {_T_2166,_T_2141,_T_2116}; // @[Cat.scala 29:58] + wire _T_3729 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3730 = _T_3537 & _T_3729; // @[lsu_bus_buffer.scala 445:112] + wire _T_3732 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3733 = _T_3540 & _T_3732; // @[lsu_bus_buffer.scala 445:161] + wire _T_3734 = _T_3730 | _T_3733; // @[lsu_bus_buffer.scala 445:132] + wire _T_3735 = _T_853 & _T_3734; // @[lsu_bus_buffer.scala 445:63] + wire _T_3736 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3737 = ibuf_drain_vld & _T_3736; // @[lsu_bus_buffer.scala 445:201] + wire _T_3738 = _T_3735 | _T_3737; // @[lsu_bus_buffer.scala 445:183] + wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 475:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 475:52] + wire _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 476:46] + wire [2:0] _GEN_390 = {{1'd0}, buf_ldfwdtag_1}; // @[lsu_bus_buffer.scala 477:47] + wire _T_3831 = io_lsu_axi_r_bits_id == _GEN_390; // @[lsu_bus_buffer.scala 477:47] + wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[lsu_bus_buffer.scala 477:27] + wire _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 476:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 478:26] + wire _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 478:44] + wire _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 478:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] + wire [2:0] _GEN_391 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 478:94] + wire _T_3839 = io_lsu_axi_r_bits_id == _GEN_391; // @[lsu_bus_buffer.scala 478:94] + wire _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 478:74] + wire _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 477:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 476:25] + wire _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_128 = _T_3783 & _T_3843; // @[Conditional.scala 39:67] + wire _GEN_148 = _T_3749 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] + wire _GEN_160 = _T_3745 ? 1'h0 : _GEN_148; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_160; // @[Conditional.scala 40:58] + wire [3:0] _T_3878 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 492:21] + wire [1:0] _GEN_109 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_110 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_109; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_111 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_110; // @[lsu_bus_buffer.scala 492:58] + wire [2:0] _GEN_393 = {{1'd0}, _GEN_111}; // @[lsu_bus_buffer.scala 492:58] + wire _T_3880 = io_lsu_axi_r_bits_id == _GEN_393; // @[lsu_bus_buffer.scala 492:58] + wire _T_3881 = _T_3878[0] & _T_3880; // @[lsu_bus_buffer.scala 492:38] + wire _T_3882 = _T_3839 | _T_3881; // @[lsu_bus_buffer.scala 491:95] + wire _T_3883 = bus_rsp_read & _T_3882; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_122 = _T_3868 & _T_3883; // @[Conditional.scala 39:67] + wire _GEN_129 = _T_3783 ? buf_resp_state_bus_en_1 : _GEN_122; // @[Conditional.scala 39:67] + wire _GEN_139 = _T_3749 ? buf_cmd_state_bus_en_1 : _GEN_129; // @[Conditional.scala 39:67] + wire _GEN_153 = _T_3745 ? 1'h0 : _GEN_139; // @[Conditional.scala 39:67] + wire buf_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_153; // @[Conditional.scala 40:58] + wire _T_3762 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3763 = _T_3762 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_3889 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 499:37] + wire _T_3890 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_3891 = buf_dual_1 & _T_3890; // @[lsu_bus_buffer.scala 499:80] + wire _T_3892 = _T_3889 | _T_3891; // @[lsu_bus_buffer.scala 499:65] + wire _T_3893 = _T_3892 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_117 = _T_3886 ? _T_3893 : _T_3894; // @[Conditional.scala 39:67] + wire _GEN_123 = _T_3868 ? _T_3763 : _GEN_117; // @[Conditional.scala 39:67] + wire _GEN_130 = _T_3783 ? _T_3763 : _GEN_123; // @[Conditional.scala 39:67] + wire _GEN_140 = _T_3749 ? _T_3763 : _GEN_130; // @[Conditional.scala 39:67] + wire _GEN_150 = _T_3745 ? obuf_rdrsp_pend_en : _GEN_140; // @[Conditional.scala 39:67] + wire buf_state_en_1 = _T_3722 ? _T_3738 : _GEN_150; // @[Conditional.scala 40:58] + wire _T_2170 = _T_1803 & buf_state_en_1; // @[lsu_bus_buffer.scala 411:94] + wire _T_2180 = _T_2076 & _T_1806; // @[lsu_bus_buffer.scala 413:71] + wire _T_2182 = _T_2180 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2183 = _T_4466 | _T_2182; // @[lsu_bus_buffer.scala 412:86] + wire _T_2187 = _T_2083 & _T_1807; // @[lsu_bus_buffer.scala 414:52] + wire _T_2189 = _T_2187 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2190 = _T_2183 | _T_2189; // @[lsu_bus_buffer.scala 413:114] + wire _T_2191 = _T_2170 & _T_2190; // @[lsu_bus_buffer.scala 411:113] + wire _T_2193 = _T_2191 | buf_age_1[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2207 = _T_2180 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2208 = _T_4471 | _T_2207; // @[lsu_bus_buffer.scala 412:86] + wire _T_2214 = _T_2187 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2215 = _T_2208 | _T_2214; // @[lsu_bus_buffer.scala 413:114] + wire _T_2216 = _T_2170 & _T_2215; // @[lsu_bus_buffer.scala 411:113] + wire _T_2218 = _T_2216 | buf_age_1[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2232 = _T_2180 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2233 = _T_4476 | _T_2232; // @[lsu_bus_buffer.scala 412:86] + wire _T_2239 = _T_2187 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2240 = _T_2233 | _T_2239; // @[lsu_bus_buffer.scala 413:114] + wire _T_2241 = _T_2170 & _T_2240; // @[lsu_bus_buffer.scala 411:113] + wire _T_2243 = _T_2241 | buf_age_1[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2257 = _T_2180 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2258 = _T_4481 | _T_2257; // @[lsu_bus_buffer.scala 412:86] + wire _T_2264 = _T_2187 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2265 = _T_2258 | _T_2264; // @[lsu_bus_buffer.scala 413:114] + wire _T_2266 = _T_2170 & _T_2265; // @[lsu_bus_buffer.scala 411:113] + wire _T_2268 = _T_2266 | buf_age_1[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2270 = {_T_2268,_T_2243,_T_2218}; // @[Cat.scala 29:58] + wire _T_3920 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_3921 = _T_3537 & _T_3920; // @[lsu_bus_buffer.scala 445:112] + wire _T_3923 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_3924 = _T_3540 & _T_3923; // @[lsu_bus_buffer.scala 445:161] + wire _T_3925 = _T_3921 | _T_3924; // @[lsu_bus_buffer.scala 445:132] + wire _T_3926 = _T_853 & _T_3925; // @[lsu_bus_buffer.scala 445:63] + wire _T_3927 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_3928 = ibuf_drain_vld & _T_3927; // @[lsu_bus_buffer.scala 445:201] + wire _T_3929 = _T_3926 | _T_3928; // @[lsu_bus_buffer.scala 445:183] + wire _T_4018 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 475:73] + wire _T_4019 = bus_rsp_write & _T_4018; // @[lsu_bus_buffer.scala 475:52] + wire _T_4020 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 476:46] + wire [2:0] _GEN_394 = {{1'd0}, buf_ldfwdtag_2}; // @[lsu_bus_buffer.scala 477:47] + wire _T_4022 = io_lsu_axi_r_bits_id == _GEN_394; // @[lsu_bus_buffer.scala 477:47] + wire _T_4023 = buf_ldfwd[2] & _T_4022; // @[lsu_bus_buffer.scala 477:27] + wire _T_4024 = _T_4020 | _T_4023; // @[lsu_bus_buffer.scala 476:77] + wire _T_4025 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 478:26] + wire _T_4027 = ~buf_write[2]; // @[lsu_bus_buffer.scala 478:44] + wire _T_4028 = _T_4025 & _T_4027; // @[lsu_bus_buffer.scala 478:42] + wire _T_4029 = _T_4028 & buf_samedw_2; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] + wire [2:0] _GEN_395 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 478:94] + wire _T_4030 = io_lsu_axi_r_bits_id == _GEN_395; // @[lsu_bus_buffer.scala 478:94] + wire _T_4031 = _T_4029 & _T_4030; // @[lsu_bus_buffer.scala 478:74] + wire _T_4032 = _T_4024 | _T_4031; // @[lsu_bus_buffer.scala 477:71] + wire _T_4033 = bus_rsp_read & _T_4032; // @[lsu_bus_buffer.scala 476:25] + wire _T_4034 = _T_4019 | _T_4033; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_204 = _T_3974 & _T_4034; // @[Conditional.scala 39:67] + wire _GEN_224 = _T_3940 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] + wire _GEN_236 = _T_3936 ? 1'h0 : _GEN_224; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_236; // @[Conditional.scala 40:58] + wire [3:0] _T_4069 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 492:21] + wire [1:0] _GEN_185 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_186 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_185; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_187 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_186; // @[lsu_bus_buffer.scala 492:58] + wire [2:0] _GEN_397 = {{1'd0}, _GEN_187}; // @[lsu_bus_buffer.scala 492:58] + wire _T_4071 = io_lsu_axi_r_bits_id == _GEN_397; // @[lsu_bus_buffer.scala 492:58] + wire _T_4072 = _T_4069[0] & _T_4071; // @[lsu_bus_buffer.scala 492:38] + wire _T_4073 = _T_4030 | _T_4072; // @[lsu_bus_buffer.scala 491:95] + wire _T_4074 = bus_rsp_read & _T_4073; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_198 = _T_4059 & _T_4074; // @[Conditional.scala 39:67] + wire _GEN_205 = _T_3974 ? buf_resp_state_bus_en_2 : _GEN_198; // @[Conditional.scala 39:67] + wire _GEN_215 = _T_3940 ? buf_cmd_state_bus_en_2 : _GEN_205; // @[Conditional.scala 39:67] + wire _GEN_229 = _T_3936 ? 1'h0 : _GEN_215; // @[Conditional.scala 39:67] + wire buf_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_229; // @[Conditional.scala 40:58] + wire _T_3953 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_3954 = _T_3953 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_4080 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 499:37] + wire _T_4081 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_4082 = buf_dual_2 & _T_4081; // @[lsu_bus_buffer.scala 499:80] + wire _T_4083 = _T_4080 | _T_4082; // @[lsu_bus_buffer.scala 499:65] + wire _T_4084 = _T_4083 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_193 = _T_4077 ? _T_4084 : _T_4085; // @[Conditional.scala 39:67] + wire _GEN_199 = _T_4059 ? _T_3954 : _GEN_193; // @[Conditional.scala 39:67] + wire _GEN_206 = _T_3974 ? _T_3954 : _GEN_199; // @[Conditional.scala 39:67] + wire _GEN_216 = _T_3940 ? _T_3954 : _GEN_206; // @[Conditional.scala 39:67] + wire _GEN_226 = _T_3936 ? obuf_rdrsp_pend_en : _GEN_216; // @[Conditional.scala 39:67] + wire buf_state_en_2 = _T_3913 ? _T_3929 : _GEN_226; // @[Conditional.scala 40:58] + wire _T_2272 = _T_1814 & buf_state_en_2; // @[lsu_bus_buffer.scala 411:94] + wire _T_2282 = _T_2076 & _T_1817; // @[lsu_bus_buffer.scala 413:71] + wire _T_2284 = _T_2282 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2285 = _T_4466 | _T_2284; // @[lsu_bus_buffer.scala 412:86] + wire _T_2289 = _T_2083 & _T_1818; // @[lsu_bus_buffer.scala 414:52] + wire _T_2291 = _T_2289 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2292 = _T_2285 | _T_2291; // @[lsu_bus_buffer.scala 413:114] + wire _T_2293 = _T_2272 & _T_2292; // @[lsu_bus_buffer.scala 411:113] + wire _T_2295 = _T_2293 | buf_age_2[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2309 = _T_2282 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2310 = _T_4471 | _T_2309; // @[lsu_bus_buffer.scala 412:86] + wire _T_2316 = _T_2289 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2317 = _T_2310 | _T_2316; // @[lsu_bus_buffer.scala 413:114] + wire _T_2318 = _T_2272 & _T_2317; // @[lsu_bus_buffer.scala 411:113] + wire _T_2320 = _T_2318 | buf_age_2[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2334 = _T_2282 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2335 = _T_4476 | _T_2334; // @[lsu_bus_buffer.scala 412:86] + wire _T_2341 = _T_2289 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2342 = _T_2335 | _T_2341; // @[lsu_bus_buffer.scala 413:114] + wire _T_2343 = _T_2272 & _T_2342; // @[lsu_bus_buffer.scala 411:113] + wire _T_2345 = _T_2343 | buf_age_2[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2359 = _T_2282 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2360 = _T_4481 | _T_2359; // @[lsu_bus_buffer.scala 412:86] + wire _T_2366 = _T_2289 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2367 = _T_2360 | _T_2366; // @[lsu_bus_buffer.scala 413:114] + wire _T_2368 = _T_2272 & _T_2367; // @[lsu_bus_buffer.scala 411:113] + wire _T_2370 = _T_2368 | buf_age_2[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2372 = {_T_2370,_T_2345,_T_2320}; // @[Cat.scala 29:58] + wire _T_4111 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 445:117] + wire _T_4112 = _T_3537 & _T_4111; // @[lsu_bus_buffer.scala 445:112] + wire _T_4114 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 445:166] + wire _T_4115 = _T_3540 & _T_4114; // @[lsu_bus_buffer.scala 445:161] + wire _T_4116 = _T_4112 | _T_4115; // @[lsu_bus_buffer.scala 445:132] + wire _T_4117 = _T_853 & _T_4116; // @[lsu_bus_buffer.scala 445:63] + wire _T_4118 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 445:206] + wire _T_4119 = ibuf_drain_vld & _T_4118; // @[lsu_bus_buffer.scala 445:201] + wire _T_4120 = _T_4117 | _T_4119; // @[lsu_bus_buffer.scala 445:183] + wire _T_4209 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 475:73] + wire _T_4210 = bus_rsp_write & _T_4209; // @[lsu_bus_buffer.scala 475:52] + wire _T_4211 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 476:46] + wire [2:0] _GEN_398 = {{1'd0}, buf_ldfwdtag_3}; // @[lsu_bus_buffer.scala 477:47] + wire _T_4213 = io_lsu_axi_r_bits_id == _GEN_398; // @[lsu_bus_buffer.scala 477:47] + wire _T_4214 = buf_ldfwd[3] & _T_4213; // @[lsu_bus_buffer.scala 477:27] + wire _T_4215 = _T_4211 | _T_4214; // @[lsu_bus_buffer.scala 476:77] + wire _T_4216 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 478:26] + wire _T_4218 = ~buf_write[3]; // @[lsu_bus_buffer.scala 478:44] + wire _T_4219 = _T_4216 & _T_4218; // @[lsu_bus_buffer.scala 478:42] + wire _T_4220 = _T_4219 & buf_samedw_3; // @[lsu_bus_buffer.scala 478:58] + reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] + wire [2:0] _GEN_399 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 478:94] + wire _T_4221 = io_lsu_axi_r_bits_id == _GEN_399; // @[lsu_bus_buffer.scala 478:94] + wire _T_4222 = _T_4220 & _T_4221; // @[lsu_bus_buffer.scala 478:74] + wire _T_4223 = _T_4215 | _T_4222; // @[lsu_bus_buffer.scala 477:71] + wire _T_4224 = bus_rsp_read & _T_4223; // @[lsu_bus_buffer.scala 476:25] + wire _T_4225 = _T_4210 | _T_4224; // @[lsu_bus_buffer.scala 475:105] + wire _GEN_280 = _T_4165 & _T_4225; // @[Conditional.scala 39:67] + wire _GEN_300 = _T_4131 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] + wire _GEN_312 = _T_4127 ? 1'h0 : _GEN_300; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_312; // @[Conditional.scala 40:58] + wire [3:0] _T_4260 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 492:21] + wire [1:0] _GEN_261 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_262 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_261; // @[lsu_bus_buffer.scala 492:58] + wire [1:0] _GEN_263 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_262; // @[lsu_bus_buffer.scala 492:58] + wire [2:0] _GEN_401 = {{1'd0}, _GEN_263}; // @[lsu_bus_buffer.scala 492:58] + wire _T_4262 = io_lsu_axi_r_bits_id == _GEN_401; // @[lsu_bus_buffer.scala 492:58] + wire _T_4263 = _T_4260[0] & _T_4262; // @[lsu_bus_buffer.scala 492:38] + wire _T_4264 = _T_4221 | _T_4263; // @[lsu_bus_buffer.scala 491:95] + wire _T_4265 = bus_rsp_read & _T_4264; // @[lsu_bus_buffer.scala 491:45] + wire _GEN_274 = _T_4250 & _T_4265; // @[Conditional.scala 39:67] + wire _GEN_281 = _T_4165 ? buf_resp_state_bus_en_3 : _GEN_274; // @[Conditional.scala 39:67] + wire _GEN_291 = _T_4131 ? buf_cmd_state_bus_en_3 : _GEN_281; // @[Conditional.scala 39:67] + wire _GEN_305 = _T_4127 ? 1'h0 : _GEN_291; // @[Conditional.scala 39:67] + wire buf_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_305; // @[Conditional.scala 40:58] + wire _T_4144 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 462:49] + wire _T_4145 = _T_4144 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 462:70] + wire _T_4271 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 499:37] + wire _T_4272 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 499:98] + wire _T_4273 = buf_dual_3 & _T_4272; // @[lsu_bus_buffer.scala 499:80] + wire _T_4274 = _T_4271 | _T_4273; // @[lsu_bus_buffer.scala 499:65] + wire _T_4275 = _T_4274 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 499:112] + wire _GEN_269 = _T_4268 ? _T_4275 : _T_4276; // @[Conditional.scala 39:67] + wire _GEN_275 = _T_4250 ? _T_4145 : _GEN_269; // @[Conditional.scala 39:67] + wire _GEN_282 = _T_4165 ? _T_4145 : _GEN_275; // @[Conditional.scala 39:67] + wire _GEN_292 = _T_4131 ? _T_4145 : _GEN_282; // @[Conditional.scala 39:67] + wire _GEN_302 = _T_4127 ? obuf_rdrsp_pend_en : _GEN_292; // @[Conditional.scala 39:67] + wire buf_state_en_3 = _T_4104 ? _T_4120 : _GEN_302; // @[Conditional.scala 40:58] + wire _T_2374 = _T_1825 & buf_state_en_3; // @[lsu_bus_buffer.scala 411:94] + wire _T_2384 = _T_2076 & _T_1828; // @[lsu_bus_buffer.scala 413:71] + wire _T_2386 = _T_2384 & _T_1793; // @[lsu_bus_buffer.scala 413:92] + wire _T_2387 = _T_4466 | _T_2386; // @[lsu_bus_buffer.scala 412:86] + wire _T_2391 = _T_2083 & _T_1829; // @[lsu_bus_buffer.scala 414:52] + wire _T_2393 = _T_2391 & _T_1795; // @[lsu_bus_buffer.scala 414:73] + wire _T_2394 = _T_2387 | _T_2393; // @[lsu_bus_buffer.scala 413:114] + wire _T_2395 = _T_2374 & _T_2394; // @[lsu_bus_buffer.scala 411:113] + wire _T_2397 = _T_2395 | buf_age_3[0]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2411 = _T_2384 & _T_1804; // @[lsu_bus_buffer.scala 413:92] + wire _T_2412 = _T_4471 | _T_2411; // @[lsu_bus_buffer.scala 412:86] + wire _T_2418 = _T_2391 & _T_1806; // @[lsu_bus_buffer.scala 414:73] + wire _T_2419 = _T_2412 | _T_2418; // @[lsu_bus_buffer.scala 413:114] + wire _T_2420 = _T_2374 & _T_2419; // @[lsu_bus_buffer.scala 411:113] + wire _T_2422 = _T_2420 | buf_age_3[1]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2436 = _T_2384 & _T_1815; // @[lsu_bus_buffer.scala 413:92] + wire _T_2437 = _T_4476 | _T_2436; // @[lsu_bus_buffer.scala 412:86] + wire _T_2443 = _T_2391 & _T_1817; // @[lsu_bus_buffer.scala 414:73] + wire _T_2444 = _T_2437 | _T_2443; // @[lsu_bus_buffer.scala 413:114] + wire _T_2445 = _T_2374 & _T_2444; // @[lsu_bus_buffer.scala 411:113] + wire _T_2447 = _T_2445 | buf_age_3[2]; // @[lsu_bus_buffer.scala 414:97] + wire _T_2461 = _T_2384 & _T_1826; // @[lsu_bus_buffer.scala 413:92] + wire _T_2462 = _T_4481 | _T_2461; // @[lsu_bus_buffer.scala 412:86] + wire _T_2468 = _T_2391 & _T_1828; // @[lsu_bus_buffer.scala 414:73] + wire _T_2469 = _T_2462 | _T_2468; // @[lsu_bus_buffer.scala 413:114] + wire _T_2470 = _T_2374 & _T_2469; // @[lsu_bus_buffer.scala 411:113] + wire _T_2472 = _T_2470 | buf_age_3[3]; // @[lsu_bus_buffer.scala 414:97] + wire [2:0] _T_2474 = {_T_2472,_T_2447,_T_2422}; // @[Cat.scala 29:58] + wire _T_2770 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2771 = _T_1792 | _T_2770; // @[lsu_bus_buffer.scala 422:32] + wire _T_2772 = ~_T_2771; // @[lsu_bus_buffer.scala 422:6] + wire _T_2780 = _T_2772 | _T_2080; // @[lsu_bus_buffer.scala 422:59] + wire _T_2787 = _T_2780 | _T_2087; // @[lsu_bus_buffer.scala 423:110] + wire _T_2788 = _T_2068 & _T_2787; // @[lsu_bus_buffer.scala 421:112] + wire _T_2792 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2793 = _T_1803 | _T_2792; // @[lsu_bus_buffer.scala 422:32] + wire _T_2794 = ~_T_2793; // @[lsu_bus_buffer.scala 422:6] + wire _T_2802 = _T_2794 | _T_2105; // @[lsu_bus_buffer.scala 422:59] + wire _T_2809 = _T_2802 | _T_2112; // @[lsu_bus_buffer.scala 423:110] + wire _T_2810 = _T_2068 & _T_2809; // @[lsu_bus_buffer.scala 421:112] + wire _T_2814 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2815 = _T_1814 | _T_2814; // @[lsu_bus_buffer.scala 422:32] + wire _T_2816 = ~_T_2815; // @[lsu_bus_buffer.scala 422:6] + wire _T_2824 = _T_2816 | _T_2130; // @[lsu_bus_buffer.scala 422:59] + wire _T_2831 = _T_2824 | _T_2137; // @[lsu_bus_buffer.scala 423:110] + wire _T_2832 = _T_2068 & _T_2831; // @[lsu_bus_buffer.scala 421:112] + wire _T_2836 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 422:47] + wire _T_2837 = _T_1825 | _T_2836; // @[lsu_bus_buffer.scala 422:32] + wire _T_2838 = ~_T_2837; // @[lsu_bus_buffer.scala 422:6] + wire _T_2846 = _T_2838 | _T_2155; // @[lsu_bus_buffer.scala 422:59] + wire _T_2853 = _T_2846 | _T_2162; // @[lsu_bus_buffer.scala 423:110] + wire _T_2854 = _T_2068 & _T_2853; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_0 = {_T_2854,_T_2832,_T_2810,_T_2788}; // @[Cat.scala 29:58] + wire _T_2871 = _T_2772 | _T_2182; // @[lsu_bus_buffer.scala 422:59] + wire _T_2878 = _T_2871 | _T_2189; // @[lsu_bus_buffer.scala 423:110] + wire _T_2879 = _T_2170 & _T_2878; // @[lsu_bus_buffer.scala 421:112] + wire _T_2893 = _T_2794 | _T_2207; // @[lsu_bus_buffer.scala 422:59] + wire _T_2900 = _T_2893 | _T_2214; // @[lsu_bus_buffer.scala 423:110] + wire _T_2901 = _T_2170 & _T_2900; // @[lsu_bus_buffer.scala 421:112] + wire _T_2915 = _T_2816 | _T_2232; // @[lsu_bus_buffer.scala 422:59] + wire _T_2922 = _T_2915 | _T_2239; // @[lsu_bus_buffer.scala 423:110] + wire _T_2923 = _T_2170 & _T_2922; // @[lsu_bus_buffer.scala 421:112] + wire _T_2937 = _T_2838 | _T_2257; // @[lsu_bus_buffer.scala 422:59] + wire _T_2944 = _T_2937 | _T_2264; // @[lsu_bus_buffer.scala 423:110] + wire _T_2945 = _T_2170 & _T_2944; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_1 = {_T_2945,_T_2923,_T_2901,_T_2879}; // @[Cat.scala 29:58] + wire _T_2962 = _T_2772 | _T_2284; // @[lsu_bus_buffer.scala 422:59] + wire _T_2969 = _T_2962 | _T_2291; // @[lsu_bus_buffer.scala 423:110] + wire _T_2970 = _T_2272 & _T_2969; // @[lsu_bus_buffer.scala 421:112] + wire _T_2984 = _T_2794 | _T_2309; // @[lsu_bus_buffer.scala 422:59] + wire _T_2991 = _T_2984 | _T_2316; // @[lsu_bus_buffer.scala 423:110] + wire _T_2992 = _T_2272 & _T_2991; // @[lsu_bus_buffer.scala 421:112] + wire _T_3006 = _T_2816 | _T_2334; // @[lsu_bus_buffer.scala 422:59] + wire _T_3013 = _T_3006 | _T_2341; // @[lsu_bus_buffer.scala 423:110] + wire _T_3014 = _T_2272 & _T_3013; // @[lsu_bus_buffer.scala 421:112] + wire _T_3028 = _T_2838 | _T_2359; // @[lsu_bus_buffer.scala 422:59] + wire _T_3035 = _T_3028 | _T_2366; // @[lsu_bus_buffer.scala 423:110] + wire _T_3036 = _T_2272 & _T_3035; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_2 = {_T_3036,_T_3014,_T_2992,_T_2970}; // @[Cat.scala 29:58] + wire _T_3053 = _T_2772 | _T_2386; // @[lsu_bus_buffer.scala 422:59] + wire _T_3060 = _T_3053 | _T_2393; // @[lsu_bus_buffer.scala 423:110] + wire _T_3061 = _T_2374 & _T_3060; // @[lsu_bus_buffer.scala 421:112] + wire _T_3075 = _T_2794 | _T_2411; // @[lsu_bus_buffer.scala 422:59] + wire _T_3082 = _T_3075 | _T_2418; // @[lsu_bus_buffer.scala 423:110] + wire _T_3083 = _T_2374 & _T_3082; // @[lsu_bus_buffer.scala 421:112] + wire _T_3097 = _T_2816 | _T_2436; // @[lsu_bus_buffer.scala 422:59] + wire _T_3104 = _T_3097 | _T_2443; // @[lsu_bus_buffer.scala 423:110] + wire _T_3105 = _T_2374 & _T_3104; // @[lsu_bus_buffer.scala 421:112] + wire _T_3119 = _T_2838 | _T_2461; // @[lsu_bus_buffer.scala 422:59] + wire _T_3126 = _T_3119 | _T_2468; // @[lsu_bus_buffer.scala 423:110] + wire _T_3127 = _T_2374 & _T_3126; // @[lsu_bus_buffer.scala 421:112] + wire [3:0] buf_rspage_set_3 = {_T_3127,_T_3105,_T_3083,_T_3061}; // @[Cat.scala 29:58] + wire _T_3218 = _T_2836 | _T_1825; // @[lsu_bus_buffer.scala 426:110] + wire _T_3219 = ~_T_3218; // @[lsu_bus_buffer.scala 426:84] + wire _T_3220 = buf_rspageQ_0[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3222 = _T_3220 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3210 = _T_2814 | _T_1814; // @[lsu_bus_buffer.scala 426:110] + wire _T_3211 = ~_T_3210; // @[lsu_bus_buffer.scala 426:84] + wire _T_3212 = buf_rspageQ_0[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3214 = _T_3212 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3202 = _T_2792 | _T_1803; // @[lsu_bus_buffer.scala 426:110] + wire _T_3203 = ~_T_3202; // @[lsu_bus_buffer.scala 426:84] + wire _T_3204 = buf_rspageQ_0[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3206 = _T_3204 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3194 = _T_2770 | _T_1792; // @[lsu_bus_buffer.scala 426:110] + wire _T_3195 = ~_T_3194; // @[lsu_bus_buffer.scala 426:84] + wire _T_3196 = buf_rspageQ_0[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3198 = _T_3196 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_0 = {_T_3222,_T_3214,_T_3206,_T_3198}; // @[Cat.scala 29:58] + wire _T_3133 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3136 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3139 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3142 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3144 = {_T_3142,_T_3139,_T_3136}; // @[Cat.scala 29:58] + wire _T_3255 = buf_rspageQ_1[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3257 = _T_3255 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3247 = buf_rspageQ_1[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3249 = _T_3247 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3239 = buf_rspageQ_1[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3241 = _T_3239 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3231 = buf_rspageQ_1[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3233 = _T_3231 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_1 = {_T_3257,_T_3249,_T_3241,_T_3233}; // @[Cat.scala 29:58] + wire _T_3148 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3151 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3154 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3157 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3159 = {_T_3157,_T_3154,_T_3151}; // @[Cat.scala 29:58] + wire _T_3290 = buf_rspageQ_2[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3292 = _T_3290 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3282 = buf_rspageQ_2[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3284 = _T_3282 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3274 = buf_rspageQ_2[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3276 = _T_3274 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3266 = buf_rspageQ_2[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3268 = _T_3266 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_2 = {_T_3292,_T_3284,_T_3276,_T_3268}; // @[Cat.scala 29:58] + wire _T_3163 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3166 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3169 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3172 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3174 = {_T_3172,_T_3169,_T_3166}; // @[Cat.scala 29:58] + wire _T_3325 = buf_rspageQ_3[3] & _T_3219; // @[lsu_bus_buffer.scala 426:82] + wire _T_3327 = _T_3325 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3317 = buf_rspageQ_3[2] & _T_3211; // @[lsu_bus_buffer.scala 426:82] + wire _T_3319 = _T_3317 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3309 = buf_rspageQ_3[1] & _T_3203; // @[lsu_bus_buffer.scala 426:82] + wire _T_3311 = _T_3309 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire _T_3301 = buf_rspageQ_3[0] & _T_3195; // @[lsu_bus_buffer.scala 426:82] + wire _T_3303 = _T_3301 & _T_2594; // @[lsu_bus_buffer.scala 426:136] + wire [3:0] buf_rspage_3 = {_T_3327,_T_3319,_T_3311,_T_3303}; // @[Cat.scala 29:58] + wire _T_3178 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3181 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3184 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 425:88] + wire _T_3187 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 425:88] + wire [2:0] _T_3189 = {_T_3187,_T_3184,_T_3181}; // @[Cat.scala 29:58] + wire _T_3332 = ibuf_drain_vld & _T_1793; // @[lsu_bus_buffer.scala 427:63] + wire _T_3334 = ibuf_drain_vld & _T_1804; // @[lsu_bus_buffer.scala 427:63] + wire _T_3336 = ibuf_drain_vld & _T_1815; // @[lsu_bus_buffer.scala 427:63] + wire _T_3338 = ibuf_drain_vld & _T_1826; // @[lsu_bus_buffer.scala 427:63] + wire [3:0] ibuf_drainvec_vld = {_T_3338,_T_3336,_T_3334,_T_3332}; // @[Cat.scala 29:58] + wire _T_3346 = _T_3540 & _T_1796; // @[lsu_bus_buffer.scala 429:35] + wire _T_3355 = _T_3540 & _T_1807; // @[lsu_bus_buffer.scala 429:35] + wire _T_3364 = _T_3540 & _T_1818; // @[lsu_bus_buffer.scala 429:35] + wire _T_3373 = _T_3540 & _T_1829; // @[lsu_bus_buffer.scala 429:35] + wire _T_3403 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3405 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3407 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire _T_3409 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 431:45] + wire [3:0] buf_dual_in = {_T_3409,_T_3407,_T_3405,_T_3403}; // @[Cat.scala 29:58] + wire _T_3414 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3416 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3418 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire _T_3420 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 432:47] + wire [3:0] buf_samedw_in = {_T_3420,_T_3418,_T_3416,_T_3414}; // @[Cat.scala 29:58] + wire _T_3425 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 433:84] + wire _T_3426 = ibuf_drainvec_vld[0] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3429 = ibuf_drainvec_vld[1] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3432 = ibuf_drainvec_vld[2] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire _T_3435 = ibuf_drainvec_vld[3] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 433:48] + wire [3:0] buf_nomerge_in = {_T_3435,_T_3432,_T_3429,_T_3426}; // @[Cat.scala 29:58] + wire _T_3443 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3346; // @[lsu_bus_buffer.scala 434:47] + wire _T_3448 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3355; // @[lsu_bus_buffer.scala 434:47] + wire _T_3453 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3364; // @[lsu_bus_buffer.scala 434:47] + wire _T_3458 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3373; // @[lsu_bus_buffer.scala 434:47] + wire [3:0] buf_dualhi_in = {_T_3458,_T_3453,_T_3448,_T_3443}; // @[Cat.scala 29:58] + wire _T_3487 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3489 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3491 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire _T_3493 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 436:51] + wire [3:0] buf_sideeffect_in = {_T_3493,_T_3491,_T_3489,_T_3487}; // @[Cat.scala 29:58] + wire _T_3498 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3500 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3502 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire _T_3504 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 437:47] + wire [3:0] buf_unsign_in = {_T_3504,_T_3502,_T_3500,_T_3498}; // @[Cat.scala 29:58] + wire _T_3521 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3523 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3525 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire _T_3527 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 439:46] + wire [3:0] buf_write_in = {_T_3527,_T_3525,_T_3523,_T_3521}; // @[Cat.scala 29:58] + wire _T_3560 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 459:89] + wire _T_3562 = _T_3560 & _T_1349; // @[lsu_bus_buffer.scala 459:104] + wire _T_3575 = buf_state_en_0 & _T_3645; // @[lsu_bus_buffer.scala 464:44] + wire _T_3576 = _T_3575 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3578 = _T_3576 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3581 = _T_3571 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3582 = _T_3581 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_4841 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 576:64] + wire bus_rsp_read_error = bus_rsp_read & _T_4841; // @[lsu_bus_buffer.scala 576:38] + wire _T_3585 = _T_3581 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_3659 = bus_rsp_read_error & _T_3638; // @[lsu_bus_buffer.scala 482:91] + wire _T_3661 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 483:31] + wire _T_3663 = _T_3661 & _T_3640; // @[lsu_bus_buffer.scala 483:46] + wire _T_3664 = _T_3659 | _T_3663; // @[lsu_bus_buffer.scala 482:143] + wire _T_4839 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 575:66] + wire bus_rsp_write_error = bus_rsp_write & _T_4839; // @[lsu_bus_buffer.scala 575:40] + wire _T_3666 = bus_rsp_write_error & _T_3636; // @[lsu_bus_buffer.scala 484:33] + wire _T_3667 = _T_3664 | _T_3666; // @[lsu_bus_buffer.scala 483:88] + wire _T_3668 = _T_3571 & _T_3667; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_56 = _T_3592 & _T_3668; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_3558 ? _T_3585 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_82 = _T_3554 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_error_en_0 = _T_3531 ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58] + wire _T_3594 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 472:75] + wire _T_3595 = buf_write[0] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3596 = io_dec_tlu_force_halt | _T_3595; // @[lsu_bus_buffer.scala 472:57] + wire _T_3598 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 473:30] + wire _T_3599 = buf_dual_0 & _T_3598; // @[lsu_bus_buffer.scala 473:28] + wire _T_3602 = _T_3599 & _T_3645; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_29 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_30 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_29; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_31 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_30; // @[lsu_bus_buffer.scala 473:90] + wire _T_3603 = _GEN_31 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3604 = _T_3602 & _T_3603; // @[lsu_bus_buffer.scala 473:61] + wire _T_4489 = _T_2717 | _T_2714; // @[lsu_bus_buffer.scala 536:93] + wire _T_4490 = _T_4489 | _T_2711; // @[lsu_bus_buffer.scala 536:93] + wire any_done_wait_state = _T_4490 | _T_2708; // @[lsu_bus_buffer.scala 536:93] + wire _T_3606 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3612 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3614 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3616 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_3618 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_3620 = _T_3612 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3621 = _T_3614 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3622 = _T_3616 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3623 = _T_3618 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3624 = _T_3620 | _T_3621; // @[Mux.scala 27:72] + wire _T_3625 = _T_3624 | _T_3622; // @[Mux.scala 27:72] + wire _T_3626 = _T_3625 | _T_3623; // @[Mux.scala 27:72] + wire _T_3628 = _T_3602 & _T_3626; // @[lsu_bus_buffer.scala 474:101] + wire _T_3629 = _GEN_31 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_3630 = _T_3628 & _T_3629; // @[lsu_bus_buffer.scala 474:138] + wire _T_3631 = _T_3630 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_3632 = _T_3606 | _T_3631; // @[lsu_bus_buffer.scala 474:53] + wire _T_3655 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_3656 = _T_3655 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_3669 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 485:50] + wire _T_3670 = buf_state_en_0 & _T_3669; // @[lsu_bus_buffer.scala 485:48] + wire _T_3682 = buf_ldfwd[0] | _T_3687[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_3683 = _T_3682 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_39 = _T_3703 ? buf_state_en_0 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_3695 ? io_dec_tlu_force_halt : _T_3703; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_3695 ? io_dec_tlu_force_halt : _GEN_39; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_3677 ? io_dec_tlu_force_halt : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_3677 ? io_dec_tlu_force_halt : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_3592 & _T_3656; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_3592 ? io_dec_tlu_force_halt : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_3592 ? io_dec_tlu_force_halt : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_3558 ? _T_3578 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_3558 ? _T_3582 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_3558 ? io_dec_tlu_force_halt : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_3554 ? io_dec_tlu_force_halt : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_3554 ? io_dec_tlu_force_halt : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_3554 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67] + wire buf_wr_en_0 = _T_3531 & buf_state_en_0; // @[Conditional.scala 40:58] + wire buf_data_en_0 = _T_3531 ? buf_state_en_0 : _GEN_81; // @[Conditional.scala 40:58] + wire buf_rst_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_76; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_79; // @[Conditional.scala 40:58] + wire _T_3766 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 464:44] + wire _T_3767 = _T_3766 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3769 = _T_3767 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3772 = _T_3762 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3773 = _T_3772 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_3776 = _T_3772 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 482:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 483:31] + wire _T_3854 = _T_3852 & _T_3831; // @[lsu_bus_buffer.scala 483:46] + wire _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 482:143] + wire _T_3857 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 484:33] + wire _T_3858 = _T_3855 | _T_3857; // @[lsu_bus_buffer.scala 483:88] + wire _T_3859 = _T_3762 & _T_3858; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_132 = _T_3783 & _T_3859; // @[Conditional.scala 39:67] + wire _GEN_145 = _T_3749 ? _T_3776 : _GEN_132; // @[Conditional.scala 39:67] + wire _GEN_158 = _T_3745 ? 1'h0 : _GEN_145; // @[Conditional.scala 39:67] + wire buf_error_en_1 = _T_3722 ? 1'h0 : _GEN_158; // @[Conditional.scala 40:58] + wire _T_3786 = buf_write[1] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 472:57] + wire _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 473:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 473:28] + wire _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_105 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_106 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_105; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_107 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_106; // @[lsu_bus_buffer.scala 473:90] + wire _T_3794 = _GEN_107 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 473:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_3809 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] + wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] + wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] + wire _T_3819 = _T_3793 & _T_3817; // @[lsu_bus_buffer.scala 474:101] + wire _T_3820 = _GEN_107 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 474:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 474:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_3860 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 485:50] + wire _T_3861 = buf_state_en_1 & _T_3860; // @[lsu_bus_buffer.scala 485:48] + wire _T_3873 = buf_ldfwd[1] | _T_3878[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_3874 = _T_3873 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_115 = _T_3894 ? buf_state_en_1 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_119 = _T_3886 ? io_dec_tlu_force_halt : _T_3894; // @[Conditional.scala 39:67] + wire _GEN_120 = _T_3886 ? io_dec_tlu_force_halt : _GEN_115; // @[Conditional.scala 39:67] + wire _GEN_125 = _T_3868 ? io_dec_tlu_force_halt : _GEN_119; // @[Conditional.scala 39:67] + wire _GEN_126 = _T_3868 ? io_dec_tlu_force_halt : _GEN_120; // @[Conditional.scala 39:67] + wire _GEN_131 = _T_3783 & _T_3847; // @[Conditional.scala 39:67] + wire _GEN_135 = _T_3783 ? io_dec_tlu_force_halt : _GEN_125; // @[Conditional.scala 39:67] + wire _GEN_136 = _T_3783 ? io_dec_tlu_force_halt : _GEN_126; // @[Conditional.scala 39:67] + wire _GEN_142 = _T_3749 ? _T_3769 : _GEN_136; // @[Conditional.scala 39:67] + wire _GEN_144 = _T_3749 ? _T_3773 : _GEN_131; // @[Conditional.scala 39:67] + wire _GEN_147 = _T_3749 ? io_dec_tlu_force_halt : _GEN_135; // @[Conditional.scala 39:67] + wire _GEN_152 = _T_3745 ? io_dec_tlu_force_halt : _GEN_147; // @[Conditional.scala 39:67] + wire _GEN_155 = _T_3745 ? io_dec_tlu_force_halt : _GEN_142; // @[Conditional.scala 39:67] + wire _GEN_157 = _T_3745 ? 1'h0 : _GEN_144; // @[Conditional.scala 39:67] + wire buf_wr_en_1 = _T_3722 & buf_state_en_1; // @[Conditional.scala 40:58] + wire buf_data_en_1 = _T_3722 ? buf_state_en_1 : _GEN_157; // @[Conditional.scala 40:58] + wire buf_rst_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_152; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_155; // @[Conditional.scala 40:58] + wire _T_3957 = buf_state_en_2 & _T_4027; // @[lsu_bus_buffer.scala 464:44] + wire _T_3958 = _T_3957 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_3960 = _T_3958 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_3963 = _T_3953 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_3964 = _T_3963 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_3967 = _T_3963 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_4041 = bus_rsp_read_error & _T_4020; // @[lsu_bus_buffer.scala 482:91] + wire _T_4043 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 483:31] + wire _T_4045 = _T_4043 & _T_4022; // @[lsu_bus_buffer.scala 483:46] + wire _T_4046 = _T_4041 | _T_4045; // @[lsu_bus_buffer.scala 482:143] + wire _T_4048 = bus_rsp_write_error & _T_4018; // @[lsu_bus_buffer.scala 484:33] + wire _T_4049 = _T_4046 | _T_4048; // @[lsu_bus_buffer.scala 483:88] + wire _T_4050 = _T_3953 & _T_4049; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_208 = _T_3974 & _T_4050; // @[Conditional.scala 39:67] + wire _GEN_221 = _T_3940 ? _T_3967 : _GEN_208; // @[Conditional.scala 39:67] + wire _GEN_234 = _T_3936 ? 1'h0 : _GEN_221; // @[Conditional.scala 39:67] + wire buf_error_en_2 = _T_3913 ? 1'h0 : _GEN_234; // @[Conditional.scala 40:58] + wire _T_3977 = buf_write[2] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_3978 = io_dec_tlu_force_halt | _T_3977; // @[lsu_bus_buffer.scala 472:57] + wire _T_3980 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 473:30] + wire _T_3981 = buf_dual_2 & _T_3980; // @[lsu_bus_buffer.scala 473:28] + wire _T_3984 = _T_3981 & _T_4027; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_181 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_182 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_181; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_183 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_182; // @[lsu_bus_buffer.scala 473:90] + wire _T_3985 = _GEN_183 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_3986 = _T_3984 & _T_3985; // @[lsu_bus_buffer.scala 473:61] + wire _T_3988 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_3994 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_3996 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_3998 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_4000 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_4002 = _T_3994 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4003 = _T_3996 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4004 = _T_3998 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4005 = _T_4000 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4006 = _T_4002 | _T_4003; // @[Mux.scala 27:72] + wire _T_4007 = _T_4006 | _T_4004; // @[Mux.scala 27:72] + wire _T_4008 = _T_4007 | _T_4005; // @[Mux.scala 27:72] + wire _T_4010 = _T_3984 & _T_4008; // @[lsu_bus_buffer.scala 474:101] + wire _T_4011 = _GEN_183 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_4012 = _T_4010 & _T_4011; // @[lsu_bus_buffer.scala 474:138] + wire _T_4013 = _T_4012 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_4014 = _T_3988 | _T_4013; // @[lsu_bus_buffer.scala 474:53] + wire _T_4037 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_4038 = _T_4037 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_4051 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 485:50] + wire _T_4052 = buf_state_en_2 & _T_4051; // @[lsu_bus_buffer.scala 485:48] + wire _T_4064 = buf_ldfwd[2] | _T_4069[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_4065 = _T_4064 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_191 = _T_4085 ? buf_state_en_2 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_195 = _T_4077 ? io_dec_tlu_force_halt : _T_4085; // @[Conditional.scala 39:67] + wire _GEN_196 = _T_4077 ? io_dec_tlu_force_halt : _GEN_191; // @[Conditional.scala 39:67] + wire _GEN_201 = _T_4059 ? io_dec_tlu_force_halt : _GEN_195; // @[Conditional.scala 39:67] + wire _GEN_202 = _T_4059 ? io_dec_tlu_force_halt : _GEN_196; // @[Conditional.scala 39:67] + wire _GEN_207 = _T_3974 & _T_4038; // @[Conditional.scala 39:67] + wire _GEN_211 = _T_3974 ? io_dec_tlu_force_halt : _GEN_201; // @[Conditional.scala 39:67] + wire _GEN_212 = _T_3974 ? io_dec_tlu_force_halt : _GEN_202; // @[Conditional.scala 39:67] + wire _GEN_218 = _T_3940 ? _T_3960 : _GEN_212; // @[Conditional.scala 39:67] + wire _GEN_220 = _T_3940 ? _T_3964 : _GEN_207; // @[Conditional.scala 39:67] + wire _GEN_223 = _T_3940 ? io_dec_tlu_force_halt : _GEN_211; // @[Conditional.scala 39:67] + wire _GEN_228 = _T_3936 ? io_dec_tlu_force_halt : _GEN_223; // @[Conditional.scala 39:67] + wire _GEN_231 = _T_3936 ? io_dec_tlu_force_halt : _GEN_218; // @[Conditional.scala 39:67] + wire _GEN_233 = _T_3936 ? 1'h0 : _GEN_220; // @[Conditional.scala 39:67] + wire buf_wr_en_2 = _T_3913 & buf_state_en_2; // @[Conditional.scala 40:58] + wire buf_data_en_2 = _T_3913 ? buf_state_en_2 : _GEN_233; // @[Conditional.scala 40:58] + wire buf_rst_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_228; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_231; // @[Conditional.scala 40:58] + wire _T_4148 = buf_state_en_3 & _T_4218; // @[lsu_bus_buffer.scala 464:44] + wire _T_4149 = _T_4148 & obuf_nosend; // @[lsu_bus_buffer.scala 464:60] + wire _T_4151 = _T_4149 & _T_2594; // @[lsu_bus_buffer.scala 464:74] + wire _T_4154 = _T_4144 & obuf_nosend; // @[lsu_bus_buffer.scala 466:67] + wire _T_4155 = _T_4154 & bus_rsp_read; // @[lsu_bus_buffer.scala 466:81] + wire _T_4158 = _T_4154 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 467:82] + wire _T_4232 = bus_rsp_read_error & _T_4211; // @[lsu_bus_buffer.scala 482:91] + wire _T_4234 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 483:31] + wire _T_4236 = _T_4234 & _T_4213; // @[lsu_bus_buffer.scala 483:46] + wire _T_4237 = _T_4232 | _T_4236; // @[lsu_bus_buffer.scala 482:143] + wire _T_4239 = bus_rsp_write_error & _T_4209; // @[lsu_bus_buffer.scala 484:33] + wire _T_4240 = _T_4237 | _T_4239; // @[lsu_bus_buffer.scala 483:88] + wire _T_4241 = _T_4144 & _T_4240; // @[lsu_bus_buffer.scala 482:68] + wire _GEN_284 = _T_4165 & _T_4241; // @[Conditional.scala 39:67] + wire _GEN_297 = _T_4131 ? _T_4158 : _GEN_284; // @[Conditional.scala 39:67] + wire _GEN_310 = _T_4127 ? 1'h0 : _GEN_297; // @[Conditional.scala 39:67] + wire buf_error_en_3 = _T_4104 ? 1'h0 : _GEN_310; // @[Conditional.scala 40:58] + wire _T_4168 = buf_write[3] & _T_3594; // @[lsu_bus_buffer.scala 472:73] + wire _T_4169 = io_dec_tlu_force_halt | _T_4168; // @[lsu_bus_buffer.scala 472:57] + wire _T_4171 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 473:30] + wire _T_4172 = buf_dual_3 & _T_4171; // @[lsu_bus_buffer.scala 473:28] + wire _T_4175 = _T_4172 & _T_4218; // @[lsu_bus_buffer.scala 473:45] + wire [2:0] _GEN_257 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_258 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_257; // @[lsu_bus_buffer.scala 473:90] + wire [2:0] _GEN_259 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_258; // @[lsu_bus_buffer.scala 473:90] + wire _T_4176 = _GEN_259 != 3'h4; // @[lsu_bus_buffer.scala 473:90] + wire _T_4177 = _T_4175 & _T_4176; // @[lsu_bus_buffer.scala 473:61] + wire _T_4179 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 474:31] + wire _T_4185 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 61:118] + wire _T_4187 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 61:118] + wire _T_4189 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 61:118] + wire _T_4191 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 61:118] + wire _T_4193 = _T_4185 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4194 = _T_4187 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4195 = _T_4189 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4196 = _T_4191 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4197 = _T_4193 | _T_4194; // @[Mux.scala 27:72] + wire _T_4198 = _T_4197 | _T_4195; // @[Mux.scala 27:72] + wire _T_4199 = _T_4198 | _T_4196; // @[Mux.scala 27:72] + wire _T_4201 = _T_4175 & _T_4199; // @[lsu_bus_buffer.scala 474:101] + wire _T_4202 = _GEN_259 == 3'h4; // @[lsu_bus_buffer.scala 474:167] + wire _T_4203 = _T_4201 & _T_4202; // @[lsu_bus_buffer.scala 474:138] + wire _T_4204 = _T_4203 & any_done_wait_state; // @[lsu_bus_buffer.scala 474:187] + wire _T_4205 = _T_4179 | _T_4204; // @[lsu_bus_buffer.scala 474:53] + wire _T_4228 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 481:47] + wire _T_4229 = _T_4228 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 481:62] + wire _T_4242 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 485:50] + wire _T_4243 = buf_state_en_3 & _T_4242; // @[lsu_bus_buffer.scala 485:48] + wire _T_4255 = buf_ldfwd[3] | _T_4260[0]; // @[lsu_bus_buffer.scala 490:90] + wire _T_4256 = _T_4255 | any_done_wait_state; // @[lsu_bus_buffer.scala 490:118] + wire _GEN_267 = _T_4276 ? buf_state_en_3 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67] + wire _GEN_271 = _T_4268 ? io_dec_tlu_force_halt : _T_4276; // @[Conditional.scala 39:67] + wire _GEN_272 = _T_4268 ? io_dec_tlu_force_halt : _GEN_267; // @[Conditional.scala 39:67] + wire _GEN_277 = _T_4250 ? io_dec_tlu_force_halt : _GEN_271; // @[Conditional.scala 39:67] + wire _GEN_278 = _T_4250 ? io_dec_tlu_force_halt : _GEN_272; // @[Conditional.scala 39:67] + wire _GEN_283 = _T_4165 & _T_4229; // @[Conditional.scala 39:67] + wire _GEN_287 = _T_4165 ? io_dec_tlu_force_halt : _GEN_277; // @[Conditional.scala 39:67] + wire _GEN_288 = _T_4165 ? io_dec_tlu_force_halt : _GEN_278; // @[Conditional.scala 39:67] + wire _GEN_294 = _T_4131 ? _T_4151 : _GEN_288; // @[Conditional.scala 39:67] + wire _GEN_296 = _T_4131 ? _T_4155 : _GEN_283; // @[Conditional.scala 39:67] + wire _GEN_299 = _T_4131 ? io_dec_tlu_force_halt : _GEN_287; // @[Conditional.scala 39:67] + wire _GEN_304 = _T_4127 ? io_dec_tlu_force_halt : _GEN_299; // @[Conditional.scala 39:67] + wire _GEN_307 = _T_4127 ? io_dec_tlu_force_halt : _GEN_294; // @[Conditional.scala 39:67] + wire _GEN_309 = _T_4127 ? 1'h0 : _GEN_296; // @[Conditional.scala 39:67] + wire buf_wr_en_3 = _T_4104 & buf_state_en_3; // @[Conditional.scala 40:58] + wire buf_data_en_3 = _T_4104 ? buf_state_en_3 : _GEN_309; // @[Conditional.scala 40:58] + wire buf_rst_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_304; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_307; // @[Conditional.scala 40:58] + reg _T_4331; // @[Reg.scala 27:20] + reg _T_4334; // @[Reg.scala 27:20] + reg _T_4337; // @[Reg.scala 27:20] + reg _T_4340; // @[Reg.scala 27:20] + wire [3:0] buf_unsign = {_T_4340,_T_4337,_T_4334,_T_4331}; // @[Cat.scala 29:58] + wire _T_4387 = ~buf_rst_0; // @[lsu_bus_buffer.scala 531:81] + reg _T_4406; // @[lsu_bus_buffer.scala 531:80] + reg _T_4401; // @[lsu_bus_buffer.scala 531:80] + reg _T_4396; // @[lsu_bus_buffer.scala 531:80] + reg _T_4391; // @[lsu_bus_buffer.scala 531:80] + wire [3:0] buf_error = {_T_4406,_T_4401,_T_4396,_T_4391}; // @[Cat.scala 29:58] + wire _T_4389 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4392 = ~buf_rst_1; // @[lsu_bus_buffer.scala 531:81] + wire _T_4394 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4397 = ~buf_rst_2; // @[lsu_bus_buffer.scala 531:81] + wire _T_4399 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 531:98] + wire _T_4402 = ~buf_rst_3; // @[lsu_bus_buffer.scala 531:81] + wire _T_4404 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 531:98] + wire [1:0] _T_4410 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4411 = io_ldst_dual_m ? _T_4410 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 532:28] + wire [1:0] _T_4412 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4413 = io_ldst_dual_r ? _T_4412 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 532:94] + wire [2:0] _T_4414 = _T_4411 + _T_4413; // @[lsu_bus_buffer.scala 532:88] + wire [2:0] _GEN_406 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 532:154] + wire [3:0] _T_4415 = _T_4414 + _GEN_406; // @[lsu_bus_buffer.scala 532:154] + wire [1:0] _T_4420 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 532:217] + wire [1:0] _GEN_407 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 532:217] + wire [2:0] _T_4421 = _T_4420 + _GEN_407; // @[lsu_bus_buffer.scala 532:217] + wire [2:0] _GEN_408 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 532:217] + wire [3:0] _T_4422 = _T_4421 + _GEN_408; // @[lsu_bus_buffer.scala 532:217] + wire [3:0] buf_numvld_any = _T_4415 + _T_4422; // @[lsu_bus_buffer.scala 532:169] + wire _T_4493 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 538:52] + wire _T_4494 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 538:92] + wire _T_4495 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 538:121] + wire _T_4497 = |buf_state_0; // @[lsu_bus_buffer.scala 539:52] + wire _T_4498 = |buf_state_1; // @[lsu_bus_buffer.scala 539:52] + wire _T_4499 = |buf_state_2; // @[lsu_bus_buffer.scala 539:52] + wire _T_4500 = |buf_state_3; // @[lsu_bus_buffer.scala 539:52] + wire _T_4501 = _T_4497 | _T_4498; // @[lsu_bus_buffer.scala 539:65] + wire _T_4502 = _T_4501 | _T_4499; // @[lsu_bus_buffer.scala 539:65] + wire _T_4503 = _T_4502 | _T_4500; // @[lsu_bus_buffer.scala 539:65] + wire _T_4504 = ~_T_4503; // @[lsu_bus_buffer.scala 539:34] + wire _T_4506 = _T_4504 & _T_852; // @[lsu_bus_buffer.scala 539:70] + wire _T_4509 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 541:64] + wire _T_4510 = _T_4509 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 541:85] + wire _T_4511 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 541:112] + wire _T_4512 = _T_4510 & _T_4511; // @[lsu_bus_buffer.scala 541:110] + wire _T_4513 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 541:129] + wire _T_4515 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 544:74] + reg lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 629:66] + wire _T_4529 = _T_2770 & _T_3645; // @[Mux.scala 27:72] + wire _T_4530 = _T_2792 & _T_3836; // @[Mux.scala 27:72] + wire _T_4531 = _T_2814 & _T_4027; // @[Mux.scala 27:72] + wire _T_4532 = _T_2836 & _T_4218; // @[Mux.scala 27:72] + wire _T_4533 = _T_4529 | _T_4530; // @[Mux.scala 27:72] + wire _T_4534 = _T_4533 | _T_4531; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4534 | _T_4532; // @[Mux.scala 27:72] + wire _T_4540 = buf_error[0] & _T_3645; // @[lsu_bus_buffer.scala 547:121] + wire _T_4545 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 547:121] + wire _T_4550 = buf_error[2] & _T_4027; // @[lsu_bus_buffer.scala 547:121] + wire _T_4555 = buf_error[3] & _T_4218; // @[lsu_bus_buffer.scala 547:121] + wire _T_4556 = _T_2770 & _T_4540; // @[Mux.scala 27:72] + wire _T_4557 = _T_2792 & _T_4545; // @[Mux.scala 27:72] + wire _T_4558 = _T_2814 & _T_4550; // @[Mux.scala 27:72] + wire _T_4559 = _T_2836 & _T_4555; // @[Mux.scala 27:72] + wire _T_4560 = _T_4556 | _T_4557; // @[Mux.scala 27:72] + wire _T_4561 = _T_4560 | _T_4558; // @[Mux.scala 27:72] + wire _T_4568 = ~buf_dual_0; // @[lsu_bus_buffer.scala 548:121] + wire _T_4569 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 548:136] + wire _T_4570 = _T_4568 | _T_4569; // @[lsu_bus_buffer.scala 548:134] + wire _T_4571 = _T_4529 & _T_4570; // @[lsu_bus_buffer.scala 548:118] + wire _T_4576 = ~buf_dual_1; // @[lsu_bus_buffer.scala 548:121] + wire _T_4577 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 548:136] + wire _T_4578 = _T_4576 | _T_4577; // @[lsu_bus_buffer.scala 548:134] + wire _T_4579 = _T_4530 & _T_4578; // @[lsu_bus_buffer.scala 548:118] + wire _T_4584 = ~buf_dual_2; // @[lsu_bus_buffer.scala 548:121] + wire _T_4585 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 548:136] + wire _T_4586 = _T_4584 | _T_4585; // @[lsu_bus_buffer.scala 548:134] + wire _T_4587 = _T_4531 & _T_4586; // @[lsu_bus_buffer.scala 548:118] + wire _T_4592 = ~buf_dual_3; // @[lsu_bus_buffer.scala 548:121] + wire _T_4593 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 548:136] + wire _T_4594 = _T_4592 | _T_4593; // @[lsu_bus_buffer.scala 548:134] + wire _T_4595 = _T_4532 & _T_4594; // @[lsu_bus_buffer.scala 548:118] + wire [1:0] _T_4598 = _T_4587 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4599 = _T_4595 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_409 = {{1'd0}, _T_4579}; // @[Mux.scala 27:72] + wire [1:0] _T_4601 = _GEN_409 | _T_4598; // @[Mux.scala 27:72] + wire [31:0] _T_4636 = _T_4571 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4637 = _T_4579 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4638 = _T_4587 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4639 = _T_4595 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4640 = _T_4636 | _T_4637; // @[Mux.scala 27:72] + wire [31:0] _T_4641 = _T_4640 | _T_4638; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_lo = _T_4641 | _T_4639; // @[Mux.scala 27:72] + wire _T_4648 = _T_4529 & _T_3643; // @[lsu_bus_buffer.scala 550:105] + wire _T_4654 = _T_4530 & _T_3834; // @[lsu_bus_buffer.scala 550:105] + wire _T_4660 = _T_4531 & _T_4025; // @[lsu_bus_buffer.scala 550:105] + wire _T_4666 = _T_4532 & _T_4216; // @[lsu_bus_buffer.scala 550:105] + wire [31:0] _T_4667 = _T_4648 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4668 = _T_4654 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4669 = _T_4660 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4670 = _T_4666 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4671 = _T_4667 | _T_4668; // @[Mux.scala 27:72] + wire [31:0] _T_4672 = _T_4671 | _T_4669; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_hi = _T_4672 | _T_4670; // @[Mux.scala 27:72] + wire _T_4674 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 62:123] + wire _T_4675 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 62:123] + wire _T_4676 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 62:123] + wire _T_4677 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 62:123] + wire [31:0] _T_4678 = _T_4674 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4679 = _T_4675 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4680 = _T_4676 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4681 = _T_4677 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4682 = _T_4678 | _T_4679; // @[Mux.scala 27:72] + wire [31:0] _T_4683 = _T_4682 | _T_4680; // @[Mux.scala 27:72] + wire [31:0] _T_4684 = _T_4683 | _T_4681; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_addr_offset = _T_4684[1:0]; // @[lsu_bus_buffer.scala 551:96] + wire [1:0] _T_4690 = _T_4674 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4691 = _T_4675 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4692 = _T_4676 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4693 = _T_4677 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4694 = _T_4690 | _T_4691; // @[Mux.scala 27:72] + wire [1:0] _T_4695 = _T_4694 | _T_4692; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_sz = _T_4695 | _T_4693; // @[Mux.scala 27:72] + wire _T_4705 = _T_4674 & buf_unsign[0]; // @[Mux.scala 27:72] + wire _T_4706 = _T_4675 & buf_unsign[1]; // @[Mux.scala 27:72] + wire _T_4707 = _T_4676 & buf_unsign[2]; // @[Mux.scala 27:72] + wire _T_4708 = _T_4677 & buf_unsign[3]; // @[Mux.scala 27:72] + wire _T_4709 = _T_4705 | _T_4706; // @[Mux.scala 27:72] + wire _T_4710 = _T_4709 | _T_4707; // @[Mux.scala 27:72] + wire lsu_nonblock_unsign = _T_4710 | _T_4708; // @[Mux.scala 27:72] + wire [63:0] _T_4712 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] + wire [3:0] _GEN_410 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 555:121] + wire [5:0] _T_4713 = _GEN_410 * 4'h8; // @[lsu_bus_buffer.scala 555:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4712 >> _T_4713; // @[lsu_bus_buffer.scala 555:92] + wire _T_4714 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 557:82] + wire _T_4716 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 558:81] + wire _T_4717 = lsu_nonblock_unsign & _T_4716; // @[lsu_bus_buffer.scala 558:63] + wire [31:0] _T_4719 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4720 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 559:45] + wire _T_4721 = lsu_nonblock_unsign & _T_4720; // @[lsu_bus_buffer.scala 559:26] + wire [31:0] _T_4723 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4724 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 560:6] + wire _T_4726 = _T_4724 & _T_4716; // @[lsu_bus_buffer.scala 560:27] + wire [23:0] _T_4729 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4731 = {_T_4729,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4734 = _T_4724 & _T_4720; // @[lsu_bus_buffer.scala 561:27] + wire [15:0] _T_4737 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4739 = {_T_4737,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4740 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 562:21] + wire [31:0] _T_4741 = _T_4717 ? _T_4719 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4742 = _T_4721 ? _T_4723 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4743 = _T_4726 ? _T_4731 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4744 = _T_4734 ? _T_4739 : 32'h0; // @[Mux.scala 27:72] + wire [63:0] _T_4745 = _T_4740 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4746 = _T_4741 | _T_4742; // @[Mux.scala 27:72] + wire [31:0] _T_4747 = _T_4746 | _T_4743; // @[Mux.scala 27:72] + wire [31:0] _T_4748 = _T_4747 | _T_4744; // @[Mux.scala 27:72] + wire [63:0] _GEN_411 = {{32'd0}, _T_4748}; // @[Mux.scala 27:72] + wire [63:0] _T_4749 = _GEN_411 | _T_4745; // @[Mux.scala 27:72] + wire _T_4843 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 580:37] + wire _T_4844 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 580:52] + wire _T_4845 = _T_4843 & _T_4844; // @[lsu_bus_buffer.scala 580:50] + wire [31:0] _T_4849 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] + wire [2:0] _T_4851 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] + wire _T_4856 = ~obuf_data_done; // @[lsu_bus_buffer.scala 592:51] + wire _T_4857 = _T_4843 & _T_4856; // @[lsu_bus_buffer.scala 592:49] + wire [7:0] _T_4861 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire _T_4864 = obuf_valid & _T_1341; // @[lsu_bus_buffer.scala 597:37] + wire _T_4866 = _T_4864 & _T_1347; // @[lsu_bus_buffer.scala 597:51] + wire _T_4878 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4880 = _T_4878 & buf_write[0]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4883 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4885 = _T_4883 & buf_write[1]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4888 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4890 = _T_4888 & buf_write[2]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4893 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 610:126] + wire _T_4895 = _T_4893 & buf_write[3]; // @[lsu_bus_buffer.scala 610:141] + wire _T_4896 = _T_2770 & _T_4880; // @[Mux.scala 27:72] + wire _T_4897 = _T_2792 & _T_4885; // @[Mux.scala 27:72] + wire _T_4898 = _T_2814 & _T_4890; // @[Mux.scala 27:72] + wire _T_4899 = _T_2836 & _T_4895; // @[Mux.scala 27:72] + wire _T_4900 = _T_4896 | _T_4897; // @[Mux.scala 27:72] + wire _T_4901 = _T_4900 | _T_4898; // @[Mux.scala 27:72] + wire _T_4911 = _T_2792 & buf_error[1]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4913 = _T_4911 & buf_write[1]; // @[lsu_bus_buffer.scala 611:108] + wire _T_4916 = _T_2814 & buf_error[2]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4918 = _T_4916 & buf_write[2]; // @[lsu_bus_buffer.scala 611:108] + wire _T_4921 = _T_2836 & buf_error[3]; // @[lsu_bus_buffer.scala 611:93] + wire _T_4923 = _T_4921 & buf_write[3]; // @[lsu_bus_buffer.scala 611:108] + wire [1:0] _T_4926 = _T_4918 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4927 = _T_4923 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_412 = {{1'd0}, _T_4913}; // @[Mux.scala 27:72] + wire [1:0] _T_4929 = _GEN_412 | _T_4926; // @[Mux.scala 27:72] + wire [1:0] lsu_imprecise_error_store_tag = _T_4929 | _T_4927; // @[Mux.scala 27:72] + wire _T_4931 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 613:97] + wire [31:0] _GEN_369 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_370 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_369; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_371 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_370; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_373 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_374 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_373; // @[lsu_bus_buffer.scala 614:53] + wire [31:0] _GEN_375 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_374; // @[lsu_bus_buffer.scala 614:53] + wire _T_4936 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 620:82] + wire _T_4939 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 621:60] + wire _T_4942 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 624:61] + wire _T_4943 = io_lsu_axi_aw_valid & _T_4942; // @[lsu_bus_buffer.scala 624:59] + wire _T_4944 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 624:107] + wire _T_4945 = io_lsu_axi_w_valid & _T_4944; // @[lsu_bus_buffer.scala 624:105] + wire _T_4946 = _T_4943 | _T_4945; // @[lsu_bus_buffer.scala 624:83] + wire _T_4947 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 624:153] + wire _T_4948 = io_lsu_axi_ar_valid & _T_4947; // @[lsu_bus_buffer.scala 624:151] + wire _T_4952 = ~io_flush_r; // @[lsu_bus_buffer.scala 628:75] + wire _T_4953 = io_lsu_busreq_m & _T_4952; // @[lsu_bus_buffer.scala 628:73] + reg _T_4956; // @[lsu_bus_buffer.scala 628:56] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4936 | _T_4835; // @[lsu_bus_buffer.scala 620:35] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4939 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 621:41] + assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 622:36] + assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4946 | _T_4948; // @[lsu_bus_buffer.scala 624:35] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4931; // @[lsu_bus_buffer.scala 613:47] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4901 | _T_4899; // @[lsu_bus_buffer.scala 610:48] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_371 : _GEN_375; // @[lsu_bus_buffer.scala 614:47] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4512 & _T_4513; // @[lsu_bus_buffer.scala 541:45] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1802 ? 2'h0 : _T_1838; // @[lsu_bus_buffer.scala 542:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4515; // @[lsu_bus_buffer.scala 544:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 545:47] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4714; // @[lsu_bus_buffer.scala 557:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4561 | _T_4559; // @[lsu_bus_buffer.scala 547:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4601 | _T_4599; // @[lsu_bus_buffer.scala 548:45] + assign io_lsu_axi_aw_valid = _T_4845 & _T_1237; // @[lsu_bus_buffer.scala 580:23] + assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1781}; // @[lsu_bus_buffer.scala 581:25] + assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4849; // @[lsu_bus_buffer.scala 582:27] + assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 586:29] + assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4851 : 3'h3; // @[lsu_bus_buffer.scala 583:27] + assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 585:28] + assign io_lsu_axi_w_valid = _T_4857 & _T_1237; // @[lsu_bus_buffer.scala 592:22] + assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 594:26] + assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4861; // @[lsu_bus_buffer.scala 593:26] + assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 608:22] + assign io_lsu_axi_ar_valid = _T_4866 & _T_1237; // @[lsu_bus_buffer.scala 597:23] + assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1781}; // @[lsu_bus_buffer.scala 598:25] + assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4849; // @[lsu_bus_buffer.scala 599:27] + assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 603:29] + assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4851 : 3'h3; // @[lsu_bus_buffer.scala 600:27] + assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 602:28] + assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 609:22] + assign io_lsu_busreq_r = _T_4956; // @[lsu_bus_buffer.scala 628:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 537:30] + assign io_lsu_bus_buffer_full_any = _T_4493 ? _T_4494 : _T_4495; // @[lsu_bus_buffer.scala 538:30] + assign io_lsu_bus_buffer_empty_any = _T_4506 & _T_1231; // @[lsu_bus_buffer.scala 539:31] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 142:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 143:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 169:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 175:24] + assign io_lsu_nonblock_load_data = _T_4749[31:0]; // @[lsu_bus_buffer.scala 558:29] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = _T_3531 & buf_state_en_0; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = _T_3722 & buf_state_en_1; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = _T_3913 & buf_state_en_2; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = _T_4104 & buf_state_en_3; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = _T_3531 ? buf_state_en_0 : _GEN_81; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = _T_3722 ? buf_state_en_1 : _GEN_157; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = _T_3913 ? buf_state_en_2 : _GEN_233; // @[lib.scala 407:17] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_11_io_en = _T_4104 ? buf_state_en_3 : _GEN_309; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_addr_0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_4355 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_4352 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_4349 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_4346 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + buf_state_0 = _RAND_5[2:0]; + _RAND_6 = {1{`RANDOM}}; + buf_addr_1 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + buf_state_1 = _RAND_7[2:0]; + _RAND_8 = {1{`RANDOM}}; + buf_addr_2 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + buf_state_2 = _RAND_9[2:0]; + _RAND_10 = {1{`RANDOM}}; + buf_addr_3 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + buf_state_3 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + buf_byteen_3 = _RAND_12[3:0]; + _RAND_13 = {1{`RANDOM}}; + buf_byteen_2 = _RAND_13[3:0]; + _RAND_14 = {1{`RANDOM}}; + buf_byteen_1 = _RAND_14[3:0]; + _RAND_15 = {1{`RANDOM}}; + buf_byteen_0 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + buf_ageQ_3 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + _T_1781 = _RAND_17[1:0]; + _RAND_18 = {1{`RANDOM}}; + obuf_merge = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + obuf_tag1 = _RAND_19[1:0]; + _RAND_20 = {1{`RANDOM}}; + obuf_valid = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + obuf_wr_enQ = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ibuf_addr = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + ibuf_write = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + ibuf_valid = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + ibuf_byteen = _RAND_25[3:0]; + _RAND_26 = {1{`RANDOM}}; + buf_ageQ_2 = _RAND_26[3:0]; + _RAND_27 = {1{`RANDOM}}; + buf_ageQ_1 = _RAND_27[3:0]; + _RAND_28 = {1{`RANDOM}}; + buf_ageQ_0 = _RAND_28[3:0]; + _RAND_29 = {1{`RANDOM}}; + buf_data_0 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + buf_data_1 = _RAND_30[31:0]; + _RAND_31 = {1{`RANDOM}}; + buf_data_2 = _RAND_31[31:0]; + _RAND_32 = {1{`RANDOM}}; + buf_data_3 = _RAND_32[31:0]; + _RAND_33 = {1{`RANDOM}}; + ibuf_data = _RAND_33[31:0]; + _RAND_34 = {1{`RANDOM}}; + ibuf_timer = _RAND_34[2:0]; + _RAND_35 = {1{`RANDOM}}; + ibuf_sideeffect = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + WrPtr1_r = _RAND_36[1:0]; + _RAND_37 = {1{`RANDOM}}; + WrPtr0_r = _RAND_37[1:0]; + _RAND_38 = {1{`RANDOM}}; + ibuf_tag = _RAND_38[1:0]; + _RAND_39 = {1{`RANDOM}}; + ibuf_dualtag = _RAND_39[1:0]; + _RAND_40 = {1{`RANDOM}}; + ibuf_dual = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + ibuf_samedw = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + ibuf_nomerge = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + ibuf_unsign = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + ibuf_sz = _RAND_44[1:0]; + _RAND_45 = {1{`RANDOM}}; + _T_1791 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + buf_nomerge_0 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + buf_nomerge_1 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + buf_nomerge_2 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + buf_nomerge_3 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + _T_4325 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + _T_4322 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_4319 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + _T_4316 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + obuf_sideeffect = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + buf_dual_3 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + buf_dual_2 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + buf_dual_1 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + buf_dual_0 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + buf_samedw_3 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + buf_samedw_2 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + buf_samedw_1 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + buf_samedw_0 = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + obuf_write = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + obuf_cmd_done = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + obuf_data_done = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + obuf_nosend = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + obuf_addr = _RAND_67[31:0]; + _RAND_68 = {1{`RANDOM}}; + buf_sz_0 = _RAND_68[1:0]; + _RAND_69 = {1{`RANDOM}}; + buf_sz_1 = _RAND_69[1:0]; + _RAND_70 = {1{`RANDOM}}; + buf_sz_2 = _RAND_70[1:0]; + _RAND_71 = {1{`RANDOM}}; + buf_sz_3 = _RAND_71[1:0]; + _RAND_72 = {1{`RANDOM}}; + obuf_rdrsp_pend = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + obuf_rdrsp_tag = _RAND_73[2:0]; + _RAND_74 = {1{`RANDOM}}; + buf_dualhi_3 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + buf_dualhi_2 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + buf_dualhi_1 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + buf_dualhi_0 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + obuf_sz = _RAND_78[1:0]; + _RAND_79 = {1{`RANDOM}}; + obuf_byteen = _RAND_79[7:0]; + _RAND_80 = {2{`RANDOM}}; + obuf_data = _RAND_80[63:0]; + _RAND_81 = {1{`RANDOM}}; + buf_rspageQ_0 = _RAND_81[3:0]; + _RAND_82 = {1{`RANDOM}}; + buf_rspageQ_1 = _RAND_82[3:0]; + _RAND_83 = {1{`RANDOM}}; + buf_rspageQ_2 = _RAND_83[3:0]; + _RAND_84 = {1{`RANDOM}}; + buf_rspageQ_3 = _RAND_84[3:0]; + _RAND_85 = {1{`RANDOM}}; + _T_4302 = _RAND_85[0:0]; + _RAND_86 = {1{`RANDOM}}; + _T_4300 = _RAND_86[0:0]; + _RAND_87 = {1{`RANDOM}}; + _T_4298 = _RAND_87[0:0]; + _RAND_88 = {1{`RANDOM}}; + _T_4296 = _RAND_88[0:0]; + _RAND_89 = {1{`RANDOM}}; + buf_ldfwdtag_0 = _RAND_89[1:0]; + _RAND_90 = {1{`RANDOM}}; + buf_dualtag_0 = _RAND_90[1:0]; + _RAND_91 = {1{`RANDOM}}; + buf_ldfwdtag_3 = _RAND_91[1:0]; + _RAND_92 = {1{`RANDOM}}; + buf_ldfwdtag_2 = _RAND_92[1:0]; + _RAND_93 = {1{`RANDOM}}; + buf_ldfwdtag_1 = _RAND_93[1:0]; + _RAND_94 = {1{`RANDOM}}; + buf_dualtag_1 = _RAND_94[1:0]; + _RAND_95 = {1{`RANDOM}}; + buf_dualtag_2 = _RAND_95[1:0]; + _RAND_96 = {1{`RANDOM}}; + buf_dualtag_3 = _RAND_96[1:0]; + _RAND_97 = {1{`RANDOM}}; + _T_4331 = _RAND_97[0:0]; + _RAND_98 = {1{`RANDOM}}; + _T_4334 = _RAND_98[0:0]; + _RAND_99 = {1{`RANDOM}}; + _T_4337 = _RAND_99[0:0]; + _RAND_100 = {1{`RANDOM}}; + _T_4340 = _RAND_100[0:0]; + _RAND_101 = {1{`RANDOM}}; + _T_4406 = _RAND_101[0:0]; + _RAND_102 = {1{`RANDOM}}; + _T_4401 = _RAND_102[0:0]; + _RAND_103 = {1{`RANDOM}}; + _T_4396 = _RAND_103[0:0]; + _RAND_104 = {1{`RANDOM}}; + _T_4391 = _RAND_104[0:0]; + _RAND_105 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_105[0:0]; + _RAND_106 = {1{`RANDOM}}; + _T_4956 = _RAND_106[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_addr_0 = 32'h0; + end + if (reset) begin + _T_4355 = 1'h0; + end + if (reset) begin + _T_4352 = 1'h0; + end + if (reset) begin + _T_4349 = 1'h0; + end + if (reset) begin + _T_4346 = 1'h0; + end + if (reset) begin + buf_state_0 = 3'h0; + end + if (reset) begin + buf_addr_1 = 32'h0; + end + if (reset) begin + buf_state_1 = 3'h0; + end + if (reset) begin + buf_addr_2 = 32'h0; + end + if (reset) begin + buf_state_2 = 3'h0; + end + if (reset) begin + buf_addr_3 = 32'h0; + end + if (reset) begin + buf_state_3 = 3'h0; + end + if (reset) begin + buf_byteen_3 = 4'h0; + end + if (reset) begin + buf_byteen_2 = 4'h0; + end + if (reset) begin + buf_byteen_1 = 4'h0; + end + if (reset) begin + buf_byteen_0 = 4'h0; + end + if (reset) begin + buf_ageQ_3 = 4'h0; + end + if (reset) begin + _T_1781 = 2'h0; + end + if (reset) begin + obuf_merge = 1'h0; + end + if (reset) begin + obuf_tag1 = 2'h0; + end + if (reset) begin + obuf_valid = 1'h0; + end + if (reset) begin + obuf_wr_enQ = 1'h0; + end + if (reset) begin + ibuf_addr = 32'h0; + end + if (reset) begin + ibuf_write = 1'h0; + end + if (reset) begin + ibuf_valid = 1'h0; + end + if (reset) begin + ibuf_byteen = 4'h0; + end + if (reset) begin + buf_ageQ_2 = 4'h0; + end + if (reset) begin + buf_ageQ_1 = 4'h0; + end + if (reset) begin + buf_ageQ_0 = 4'h0; + end + if (reset) begin + buf_data_0 = 32'h0; + end + if (reset) begin + buf_data_1 = 32'h0; + end + if (reset) begin + buf_data_2 = 32'h0; + end + if (reset) begin + buf_data_3 = 32'h0; + end + if (reset) begin + ibuf_data = 32'h0; + end + if (reset) begin + ibuf_timer = 3'h0; + end + if (reset) begin + ibuf_sideeffect = 1'h0; + end + if (reset) begin + WrPtr1_r = 2'h0; + end + if (reset) begin + WrPtr0_r = 2'h0; + end + if (reset) begin + ibuf_tag = 2'h0; + end + if (reset) begin + ibuf_dualtag = 2'h0; + end + if (reset) begin + ibuf_dual = 1'h0; + end + if (reset) begin + ibuf_samedw = 1'h0; + end + if (reset) begin + ibuf_nomerge = 1'h0; + end + if (reset) begin + ibuf_unsign = 1'h0; + end + if (reset) begin + ibuf_sz = 2'h0; + end + if (reset) begin + _T_1791 = 1'h0; + end + if (reset) begin + buf_nomerge_0 = 1'h0; + end + if (reset) begin + buf_nomerge_1 = 1'h0; + end + if (reset) begin + buf_nomerge_2 = 1'h0; + end + if (reset) begin + buf_nomerge_3 = 1'h0; + end + if (reset) begin + _T_4325 = 1'h0; + end + if (reset) begin + _T_4322 = 1'h0; + end + if (reset) begin + _T_4319 = 1'h0; + end + if (reset) begin + _T_4316 = 1'h0; + end + if (reset) begin + obuf_sideeffect = 1'h0; + end + if (reset) begin + buf_dual_3 = 1'h0; + end + if (reset) begin + buf_dual_2 = 1'h0; + end + if (reset) begin + buf_dual_1 = 1'h0; + end + if (reset) begin + buf_dual_0 = 1'h0; + end + if (reset) begin + buf_samedw_3 = 1'h0; + end + if (reset) begin + buf_samedw_2 = 1'h0; + end + if (reset) begin + buf_samedw_1 = 1'h0; + end + if (reset) begin + buf_samedw_0 = 1'h0; + end + if (reset) begin + obuf_write = 1'h0; + end + if (reset) begin + obuf_cmd_done = 1'h0; + end + if (reset) begin + obuf_data_done = 1'h0; + end + if (reset) begin + obuf_nosend = 1'h0; + end + if (reset) begin + obuf_addr = 32'h0; + end + if (reset) begin + buf_sz_0 = 2'h0; + end + if (reset) begin + buf_sz_1 = 2'h0; + end + if (reset) begin + buf_sz_2 = 2'h0; + end + if (reset) begin + buf_sz_3 = 2'h0; + end + if (reset) begin + obuf_rdrsp_pend = 1'h0; + end + if (reset) begin + obuf_rdrsp_tag = 3'h0; + end + if (reset) begin + buf_dualhi_3 = 1'h0; + end + if (reset) begin + buf_dualhi_2 = 1'h0; + end + if (reset) begin + buf_dualhi_1 = 1'h0; + end + if (reset) begin + buf_dualhi_0 = 1'h0; + end + if (reset) begin + obuf_sz = 2'h0; + end + if (reset) begin + obuf_byteen = 8'h0; + end + if (reset) begin + obuf_data = 64'h0; + end + if (reset) begin + buf_rspageQ_0 = 4'h0; + end + if (reset) begin + buf_rspageQ_1 = 4'h0; + end + if (reset) begin + buf_rspageQ_2 = 4'h0; + end + if (reset) begin + buf_rspageQ_3 = 4'h0; + end + if (reset) begin + _T_4302 = 1'h0; + end + if (reset) begin + _T_4300 = 1'h0; + end + if (reset) begin + _T_4298 = 1'h0; + end + if (reset) begin + _T_4296 = 1'h0; + end + if (reset) begin + buf_ldfwdtag_0 = 2'h0; + end + if (reset) begin + buf_dualtag_0 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_3 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_2 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_2 = 2'h0; + end + if (reset) begin + buf_dualtag_3 = 2'h0; + end + if (reset) begin + _T_4331 = 1'h0; + end + if (reset) begin + _T_4334 = 1'h0; + end + if (reset) begin + _T_4337 = 1'h0; + end + if (reset) begin + _T_4340 = 1'h0; + end + if (reset) begin + _T_4406 = 1'h0; + end + if (reset) begin + _T_4401 = 1'h0; + end + if (reset) begin + _T_4396 = 1'h0; + end + if (reset) begin + _T_4391 = 1'h0; + end + if (reset) begin + lsu_nonblock_load_valid_r = 1'h0; + end + if (reset) begin + _T_4956 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_0 <= 32'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_addr_0 <= ibuf_addr; + end else if (_T_3346) begin + buf_addr_0 <= io_end_addr_r; + end else begin + buf_addr_0 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4355 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4355 <= buf_write_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4352 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4352 <= buf_write_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4349 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4349 <= buf_write_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4346 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4346 <= buf_write_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_0 <= 3'h0; + end else if (buf_state_en_0) begin + if (_T_3531) begin + if (io_lsu_bus_clk_en) begin + buf_state_0 <= 3'h2; + end else begin + buf_state_0 <= 3'h1; + end + end else if (_T_3554) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h2; + end + end else if (_T_3558) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3562) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h3; + end + end else if (_T_3592) begin + if (_T_3596) begin + buf_state_0 <= 3'h0; + end else if (_T_3604) begin + buf_state_0 <= 3'h4; + end else if (_T_3632) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3677) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3683) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3695) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h6; + end + end else begin + buf_state_0 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_1 <= 32'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_addr_1 <= ibuf_addr; + end else if (_T_3355) begin + buf_addr_1 <= io_end_addr_r; + end else begin + buf_addr_1 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_1 <= 3'h0; + end else if (buf_state_en_1) begin + if (_T_3722) begin + if (io_lsu_bus_clk_en) begin + buf_state_1 <= 3'h2; + end else begin + buf_state_1 <= 3'h1; + end + end else if (_T_3745) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h2; + end + end else if (_T_3749) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3562) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h3; + end + end else if (_T_3783) begin + if (_T_3787) begin + buf_state_1 <= 3'h0; + end else if (_T_3795) begin + buf_state_1 <= 3'h4; + end else if (_T_3823) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3868) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3874) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3886) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h6; + end + end else begin + buf_state_1 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_2 <= 32'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_addr_2 <= ibuf_addr; + end else if (_T_3364) begin + buf_addr_2 <= io_end_addr_r; + end else begin + buf_addr_2 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_2 <= 3'h0; + end else if (buf_state_en_2) begin + if (_T_3913) begin + if (io_lsu_bus_clk_en) begin + buf_state_2 <= 3'h2; + end else begin + buf_state_2 <= 3'h1; + end + end else if (_T_3936) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h2; + end + end else if (_T_3940) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3562) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h3; + end + end else if (_T_3974) begin + if (_T_3978) begin + buf_state_2 <= 3'h0; + end else if (_T_3986) begin + buf_state_2 <= 3'h4; + end else if (_T_4014) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4059) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_4065) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4077) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h6; + end + end else begin + buf_state_2 <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr_3 <= 32'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_addr_3 <= ibuf_addr; + end else if (_T_3373) begin + buf_addr_3 <= io_end_addr_r; + end else begin + buf_addr_3 <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_3 <= 3'h0; + end else if (buf_state_en_3) begin + if (_T_4104) begin + if (io_lsu_bus_clk_en) begin + buf_state_3 <= 3'h2; + end else begin + buf_state_3 <= 3'h1; + end + end else if (_T_4127) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h2; + end + end else if (_T_4131) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_3562) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h3; + end + end else if (_T_4165) begin + if (_T_4169) begin + buf_state_3 <= 3'h0; + end else if (_T_4177) begin + buf_state_3 <= 3'h4; + end else if (_T_4205) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4250) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_4256) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4268) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h6; + end + end else begin + buf_state_3 <= 3'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_3 <= 4'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_byteen_3 <= ibuf_byteen_out; + end else if (_T_3373) begin + buf_byteen_3 <= ldst_byteen_hi_r; + end else begin + buf_byteen_3 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_2 <= 4'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_byteen_2 <= ibuf_byteen_out; + end else if (_T_3364) begin + buf_byteen_2 <= ldst_byteen_hi_r; + end else begin + buf_byteen_2 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_1 <= 4'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_byteen_1 <= ibuf_byteen_out; + end else if (_T_3355) begin + buf_byteen_1 <= ldst_byteen_hi_r; + end else begin + buf_byteen_1 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_0 <= 4'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_byteen_0 <= ibuf_byteen_out; + end else if (_T_3346) begin + buf_byteen_0 <= ldst_byteen_hi_r; + end else begin + buf_byteen_0 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_3 <= 4'h0; + end else begin + buf_ageQ_3 <= {_T_2474,_T_2397}; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1781 <= 2'h0; + end else if (_T_1780) begin + if (ibuf_buf_byp) begin + _T_1781 <= WrPtr0_r; + end else begin + _T_1781 <= CmdPtr0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_merge <= 1'h0; + end else if (_T_1780) begin + obuf_merge <= obuf_merge_en; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_tag1 <= 2'h0; + end else if (_T_1780) begin + if (ibuf_buf_byp) begin + obuf_tag1 <= WrPtr1_r; + end else begin + obuf_tag1 <= CmdPtr1; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_valid <= 1'h0; + end else begin + obuf_valid <= _T_1771 & _T_1772; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_wr_enQ <= 1'h0; + end else if (io_lsu_busm_clken) begin + obuf_wr_enQ <= obuf_wr_en; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ibuf_addr <= 32'h0; + end else if (ibuf_wr_en) begin + if (io_ldst_dual_r) begin + ibuf_addr <= io_end_addr_r; + end else begin + ibuf_addr <= io_lsu_addr_r; + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_write <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_write <= io_lsu_pkt_r_bits_store; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_valid <= 1'h0; + end else begin + ibuf_valid <= _T_1005 & _T_1006; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_byteen <= 4'h0; + end else if (ibuf_wr_en) begin + if (_T_866) begin + ibuf_byteen <= _T_881; + end else if (io_ldst_dual_r) begin + ibuf_byteen <= ldst_byteen_hi_r; + end else begin + ibuf_byteen <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_2 <= 4'h0; + end else begin + buf_ageQ_2 <= {_T_2372,_T_2295}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_1 <= 4'h0; + end else begin + buf_ageQ_1 <= {_T_2270,_T_2193}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_0 <= 4'h0; + end else begin + buf_ageQ_0 <= {_T_2168,_T_2091}; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_0 <= 32'h0; + end else if (buf_data_en_0) begin + if (_T_3531) begin + if (_T_3546) begin + buf_data_0 <= ibuf_data_out; + end else begin + buf_data_0 <= store_data_lo_r; + end + end else if (_T_3554) begin + buf_data_0 <= 32'h0; + end else if (_T_3558) begin + if (buf_error_en_0) begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3592) begin + if (_T_3670) begin + if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_1 <= 32'h0; + end else if (buf_data_en_1) begin + if (_T_3722) begin + if (_T_3737) begin + buf_data_1 <= ibuf_data_out; + end else begin + buf_data_1 <= store_data_lo_r; + end + end else if (_T_3745) begin + buf_data_1 <= 32'h0; + end else if (_T_3749) begin + if (buf_error_en_1) begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3783) begin + if (_T_3861) begin + if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_2 <= 32'h0; + end else if (buf_data_en_2) begin + if (_T_3913) begin + if (_T_3928) begin + buf_data_2 <= ibuf_data_out; + end else begin + buf_data_2 <= store_data_lo_r; + end + end else if (_T_3936) begin + buf_data_2 <= 32'h0; + end else if (_T_3940) begin + if (buf_error_en_2) begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3974) begin + if (_T_4052) begin + if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data_3 <= 32'h0; + end else if (buf_data_en_3) begin + if (_T_4104) begin + if (_T_4119) begin + buf_data_3 <= ibuf_data_out; + end else begin + buf_data_3 <= store_data_lo_r; + end + end else if (_T_4127) begin + buf_data_3 <= 32'h0; + end else if (_T_4131) begin + if (buf_error_en_3) begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_4165) begin + if (_T_4243) begin + if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ibuf_data <= 32'h0; + end else if (ibuf_wr_en) begin + ibuf_data <= ibuf_data_in; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_923) begin + ibuf_timer <= _T_926; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sideeffect <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_sideeffect <= io_is_sideeffects_r; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr1_r <= 2'h0; + end else if (_T_1853) begin + WrPtr1_r <= 2'h0; + end else if (_T_1867) begin + WrPtr1_r <= 2'h1; + end else if (_T_1881) begin + WrPtr1_r <= 2'h2; + end else begin + WrPtr1_r <= 2'h3; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr0_r <= 2'h0; + end else if (_T_1802) begin + WrPtr0_r <= 2'h0; + end else if (_T_1813) begin + WrPtr0_r <= 2'h1; + end else if (_T_1824) begin + WrPtr0_r <= 2'h2; + end else begin + WrPtr0_r <= 2'h3; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_tag <= 2'h0; + end else if (ibuf_wr_en) begin + if (!(_T_866)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dualtag <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_dualtag <= WrPtr0_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dual <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_dual <= io_ldst_dual_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_samedw <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_samedw <= ldst_samedw_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_nomerge <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_nomerge <= io_no_dword_merge_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_unsign <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_unsign <= io_lsu_pkt_r_bits_unsign; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sz <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_sz <= ibuf_sz_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_1791 <= 1'h0; + end else if (obuf_wr_en) begin + _T_1791 <= obuf_data_done_in; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_nomerge_0 <= buf_nomerge_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_nomerge_1 <= buf_nomerge_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_nomerge_2 <= buf_nomerge_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_nomerge_3 <= buf_nomerge_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4325 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4325 <= buf_sideeffect_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4322 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4322 <= buf_sideeffect_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4319 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4319 <= buf_sideeffect_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4316 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4316 <= buf_sideeffect_in[0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_sideeffect <= 1'h0; + end else if (_T_1780) begin + if (ibuf_buf_byp) begin + obuf_sideeffect <= io_is_sideeffects_r; + end else begin + obuf_sideeffect <= _T_1051; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dual_3 <= buf_dual_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dual_2 <= buf_dual_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dual_1 <= buf_dual_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dual_0 <= buf_dual_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_samedw_3 <= buf_samedw_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_samedw_2 <= buf_samedw_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_samedw_1 <= buf_samedw_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_samedw_0 <= buf_samedw_in[0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_write <= 1'h0; + end else if (_T_1780) begin + if (ibuf_buf_byp) begin + obuf_write <= io_lsu_pkt_r_bits_store; + end else begin + obuf_write <= _T_1202; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_cmd_done <= 1'h0; + end else if (io_lsu_busm_clken) begin + obuf_cmd_done <= obuf_cmd_done_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_data_done <= 1'h0; + end else if (io_lsu_busm_clken) begin + obuf_data_done <= obuf_data_done_in; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_nosend <= 1'h0; + end else if (obuf_wr_en) begin + obuf_nosend <= obuf_nosend_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_addr <= 32'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_addr <= io_lsu_addr_r; + end else begin + obuf_addr <= _T_1287; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_sz_0 <= ibuf_sz; + end else begin + buf_sz_0 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_sz_1 <= ibuf_sz; + end else begin + buf_sz_1 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_sz_2 <= ibuf_sz; + end else begin + buf_sz_2 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_sz_3 <= ibuf_sz; + end else begin + buf_sz_3 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_pend <= 1'h0; + end else if (obuf_rdrsp_pend_en) begin + obuf_rdrsp_pend <= obuf_rdrsp_pend_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_rdrsp_tag <= 3'h0; + end else if (io_lsu_busm_clken) begin + if (_T_1330) begin + obuf_rdrsp_tag <= obuf_tag0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dualhi_3 <= buf_dualhi_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dualhi_2 <= buf_dualhi_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dualhi_1 <= buf_dualhi_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dualhi_0 <= buf_dualhi_in[0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_sz <= 2'h0; + end else if (_T_1780) begin + if (ibuf_buf_byp) begin + obuf_sz <= ibuf_sz_in; + end else begin + obuf_sz <= _T_1300; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_byteen <= 8'h0; + end else if (_T_1780) begin + obuf_byteen <= obuf_byteen_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + obuf_data <= 64'h0; + end else if (obuf_wr_en) begin + obuf_data <= obuf_data_in; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_0 <= 4'h0; + end else begin + buf_rspageQ_0 <= {_T_3144,_T_3133}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_1 <= 4'h0; + end else begin + buf_rspageQ_1 <= {_T_3159,_T_3148}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_2 <= 4'h0; + end else begin + buf_rspageQ_2 <= {_T_3174,_T_3163}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_3 <= 4'h0; + end else begin + buf_rspageQ_3 <= {_T_3189,_T_3178}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4302 <= 1'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4104) begin + _T_4302 <= 1'h0; + end else if (_T_4127) begin + _T_4302 <= 1'h0; + end else begin + _T_4302 <= _T_4131; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4300 <= 1'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3913) begin + _T_4300 <= 1'h0; + end else if (_T_3936) begin + _T_4300 <= 1'h0; + end else begin + _T_4300 <= _T_3940; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4298 <= 1'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3722) begin + _T_4298 <= 1'h0; + end else if (_T_3745) begin + _T_4298 <= 1'h0; + end else begin + _T_4298 <= _T_3749; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4296 <= 1'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3531) begin + _T_4296 <= 1'h0; + end else if (_T_3554) begin + _T_4296 <= 1'h0; + end else begin + _T_4296 <= _T_3558; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3531) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3554) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3558) begin + buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_0 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_dualtag_0 <= ibuf_dualtag; + end else if (_T_3346) begin + buf_dualtag_0 <= WrPtr0_r; + end else begin + buf_dualtag_0 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4104) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_4127) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_4131) begin + buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_3 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3913) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3936) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3940) begin + buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_2 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3722) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3745) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3749) begin + buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_1 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_dualtag_1 <= ibuf_dualtag; + end else if (_T_3355) begin + buf_dualtag_1 <= WrPtr0_r; + end else begin + buf_dualtag_1 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_dualtag_2 <= ibuf_dualtag; + end else if (_T_3364) begin + buf_dualtag_2 <= WrPtr0_r; + end else begin + buf_dualtag_2 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_dualtag_3 <= ibuf_dualtag; + end else if (_T_3373) begin + buf_dualtag_3 <= WrPtr0_r; + end else begin + buf_dualtag_3 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4331 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4331 <= buf_unsign_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4334 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4334 <= buf_unsign_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4337 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4337 <= buf_unsign_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4340 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4340 <= buf_unsign_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4406 <= 1'h0; + end else begin + _T_4406 <= _T_4402 & _T_4404; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4401 <= 1'h0; + end else begin + _T_4401 <= _T_4397 & _T_4399; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4396 <= 1'h0; + end else begin + _T_4396 <= _T_4392 & _T_4394; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4391 <= 1'h0; + end else begin + _T_4391 <= _T_4387 & _T_4389; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_nonblock_load_valid_r <= 1'h0; + end else begin + lsu_nonblock_load_valid_r <= io_dctl_busbuff_lsu_nonblock_load_valid_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_4956 <= 1'h0; + end else begin + _T_4956 <= _T_4953 & _T_4513; + end + end +endmodule +module lsu_bus_intf( + input clock, + input reset, + input io_scan_mode, + input io_clk_override, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + input io_lsu_bus_obuf_c1_clken, + input io_lsu_busm_clken, + input io_lsu_c1_r_clk, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_obuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_active_clk, + input io_lsu_busm_clk, + input io_axi_aw_ready, + output io_axi_aw_valid, + output [2:0] io_axi_aw_bits_id, + output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, + output [7:0] io_axi_aw_bits_len, + output [2:0] io_axi_aw_bits_size, + output [1:0] io_axi_aw_bits_burst, + output io_axi_aw_bits_lock, + output [3:0] io_axi_aw_bits_cache, + output [2:0] io_axi_aw_bits_prot, + output [3:0] io_axi_aw_bits_qos, + input io_axi_w_ready, + output io_axi_w_valid, + output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, + output io_axi_w_bits_last, + output io_axi_b_ready, + input io_axi_b_valid, + input [1:0] io_axi_b_bits_resp, + input [2:0] io_axi_b_bits_id, + input io_axi_ar_ready, + output io_axi_ar_valid, + output [2:0] io_axi_ar_bits_id, + output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, + output [7:0] io_axi_ar_bits_len, + output [2:0] io_axi_ar_bits_size, + output [1:0] io_axi_ar_bits_burst, + output io_axi_ar_bits_lock, + output [3:0] io_axi_ar_bits_cache, + output [2:0] io_axi_ar_bits_prot, + output [3:0] io_axi_ar_bits_qos, + output io_axi_r_ready, + input io_axi_r_valid, + input [2:0] io_axi_r_bits_id, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + input io_axi_r_bits_last, + input io_dec_lsu_valid_raw_d, + input io_lsu_busreq_m, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_fast_int, + input io_lsu_pkt_m_bits_stack, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_dword, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_unsign, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_m_bits_store_data_bypass_d, + input io_lsu_pkt_m_bits_load_ldst_bypass_d, + input io_lsu_pkt_m_bits_store_data_bypass_m, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_fast_int, + input io_lsu_pkt_r_bits_stack, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_dword, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input io_lsu_pkt_r_bits_dma, + input io_lsu_pkt_r_bits_store_data_bypass_d, + input io_lsu_pkt_r_bits_load_ldst_bypass_d, + input io_lsu_pkt_r_bits_store_data_bypass_m, + input [31:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_m, + input [31:0] io_end_addr_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [31:0] io_store_data_r, + input io_dec_tlu_force_halt, + input io_lsu_commit_r, + input io_is_sideeffects_m, + input io_flush_m_up, + input io_flush_r, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [31:0] io_bus_read_data_m, + output [31:0] io_lsu_nonblock_load_data, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + input io_lsu_bus_clk_en +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire bus_buffer_clock; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_reset; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_obuf_c1_clken; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busm_clken; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_store_data_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_word_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_dword_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ld_full_hit_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_m_up; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_commit_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_is_sideeffects_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 100:39] + wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39] + wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 100:39] + wire [3:0] _T_3 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_4 = io_lsu_pkt_m_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_5 = io_lsu_pkt_m_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72] + wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[lsu_bus_intf.scala 155:51] + wire _T_14 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[lsu_bus_intf.scala 156:71] + wire _T_15 = ~_T_14; // @[lsu_bus_intf.scala 156:53] + wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_15; // @[lsu_bus_intf.scala 156:51] + wire _T_17 = ~io_ldst_dual_r; // @[lsu_bus_intf.scala 157:48] + wire _T_18 = io_lsu_busreq_r & _T_17; // @[lsu_bus_intf.scala 157:46] + wire _T_19 = _T_18 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 157:64] + wire _T_20 = ~addr_match_word_lo_r_m; // @[lsu_bus_intf.scala 157:110] + wire _T_21 = io_lsu_pkt_m_bits_load | _T_20; // @[lsu_bus_intf.scala 157:108] + wire _T_26 = ~addr_match_dw_lo_r_m; // @[lsu_bus_intf.scala 158:110] + wire _T_27 = io_lsu_pkt_m_bits_load | _T_26; // @[lsu_bus_intf.scala 158:108] + wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[lsu_bus_intf.scala 160:49] + wire [6:0] _T_31 = _GEN_0 << io_lsu_addr_m[1:0]; // @[lsu_bus_intf.scala 160:49] + reg [3:0] ldst_byteen_r; // @[lsu_bus_intf.scala 200:33] + wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[lsu_bus_intf.scala 161:49] + wire [6:0] _T_34 = _GEN_1 << io_lsu_addr_r[1:0]; // @[lsu_bus_intf.scala 161:49] + wire [4:0] _T_37 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58] + wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[lsu_bus_intf.scala 162:52] + wire [62:0] _T_38 = _GEN_2 << _T_37; // @[lsu_bus_intf.scala 162:52] + wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 160:27] + wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[lsu_bus_intf.scala 163:47] + wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[lsu_bus_intf.scala 164:47] + wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 161:27] + wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[lsu_bus_intf.scala 165:47] + wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[lsu_bus_intf.scala 166:47] + wire [63:0] store_data_ext_r = {{1'd0}, _T_38}; // @[lsu_bus_intf.scala 162:27] + wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[lsu_bus_intf.scala 168:46] + wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[lsu_bus_intf.scala 169:46] + wire _T_47 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 170:51] + wire _T_48 = _T_47 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 170:76] + wire _T_49 = _T_48 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 170:97] + wire ld_addr_rhit_lo_lo = _T_49 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 170:123] + wire _T_53 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 171:51] + wire _T_54 = _T_53 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 171:76] + wire _T_55 = _T_54 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 171:97] + wire ld_addr_rhit_lo_hi = _T_55 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 171:123] + wire _T_59 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 172:51] + wire _T_60 = _T_59 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 172:76] + wire _T_61 = _T_60 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 172:97] + wire ld_addr_rhit_hi_lo = _T_61 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 172:123] + wire _T_65 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 173:51] + wire _T_66 = _T_65 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 173:76] + wire _T_67 = _T_66 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 173:97] + wire ld_addr_rhit_hi_hi = _T_67 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 173:123] + wire _T_70 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 175:70] + wire _T_72 = _T_70 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 175:92] + wire _T_74 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 175:70] + wire _T_76 = _T_74 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 175:92] + wire _T_78 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 175:70] + wire _T_80 = _T_78 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 175:92] + wire _T_82 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 175:70] + wire _T_84 = _T_82 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 175:92] + wire [3:0] ld_byte_rhit_lo_lo = {_T_84,_T_80,_T_76,_T_72}; // @[Cat.scala 29:58] + wire _T_89 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 176:70] + wire _T_91 = _T_89 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 176:92] + wire _T_93 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 176:70] + wire _T_95 = _T_93 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 176:92] + wire _T_97 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 176:70] + wire _T_99 = _T_97 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 176:92] + wire _T_101 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 176:70] + wire _T_103 = _T_101 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 176:92] + wire [3:0] ld_byte_rhit_lo_hi = {_T_103,_T_99,_T_95,_T_91}; // @[Cat.scala 29:58] + wire _T_108 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 177:70] + wire _T_110 = _T_108 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 177:92] + wire _T_112 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 177:70] + wire _T_114 = _T_112 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 177:92] + wire _T_116 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 177:70] + wire _T_118 = _T_116 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 177:92] + wire _T_120 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 177:70] + wire _T_122 = _T_120 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 177:92] + wire [3:0] ld_byte_rhit_hi_lo = {_T_122,_T_118,_T_114,_T_110}; // @[Cat.scala 29:58] + wire _T_127 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 178:70] + wire _T_129 = _T_127 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 178:92] + wire _T_131 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 178:70] + wire _T_133 = _T_131 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 178:92] + wire _T_135 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 178:70] + wire _T_137 = _T_135 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 178:92] + wire _T_139 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 178:70] + wire _T_141 = _T_139 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 178:92] + wire [3:0] ld_byte_rhit_hi_hi = {_T_141,_T_137,_T_133,_T_129}; // @[Cat.scala 29:58] + wire _T_147 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_bus_intf.scala 180:73] + wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 139:38] + wire _T_149 = _T_147 | ld_byte_hit_buf_lo[0]; // @[lsu_bus_intf.scala 180:97] + wire _T_152 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_bus_intf.scala 180:73] + wire _T_154 = _T_152 | ld_byte_hit_buf_lo[1]; // @[lsu_bus_intf.scala 180:97] + wire _T_157 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_bus_intf.scala 180:73] + wire _T_159 = _T_157 | ld_byte_hit_buf_lo[2]; // @[lsu_bus_intf.scala 180:97] + wire _T_162 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_bus_intf.scala 180:73] + wire _T_164 = _T_162 | ld_byte_hit_buf_lo[3]; // @[lsu_bus_intf.scala 180:97] + wire [3:0] ld_byte_hit_lo = {_T_164,_T_159,_T_154,_T_149}; // @[Cat.scala 29:58] + wire _T_170 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_bus_intf.scala 181:73] + wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 140:38] + wire _T_172 = _T_170 | ld_byte_hit_buf_hi[0]; // @[lsu_bus_intf.scala 181:97] + wire _T_175 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_bus_intf.scala 181:73] + wire _T_177 = _T_175 | ld_byte_hit_buf_hi[1]; // @[lsu_bus_intf.scala 181:97] + wire _T_180 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_bus_intf.scala 181:73] + wire _T_182 = _T_180 | ld_byte_hit_buf_hi[2]; // @[lsu_bus_intf.scala 181:97] + wire _T_185 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_bus_intf.scala 181:73] + wire _T_187 = _T_185 | ld_byte_hit_buf_hi[3]; // @[lsu_bus_intf.scala 181:97] + wire [3:0] ld_byte_hit_hi = {_T_187,_T_182,_T_177,_T_172}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_lo = {_T_162,_T_157,_T_152,_T_147}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_hi = {_T_185,_T_180,_T_175,_T_170}; // @[Cat.scala 29:58] + wire [7:0] _T_225 = ld_byte_rhit_lo_lo[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_226 = ld_byte_rhit_hi_lo[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_227 = _T_225 | _T_226; // @[Mux.scala 27:72] + wire [7:0] _T_233 = ld_byte_rhit_lo_lo[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_234 = ld_byte_rhit_hi_lo[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_235 = _T_233 | _T_234; // @[Mux.scala 27:72] + wire [7:0] _T_241 = ld_byte_rhit_lo_lo[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_242 = ld_byte_rhit_hi_lo[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_243 = _T_241 | _T_242; // @[Mux.scala 27:72] + wire [7:0] _T_249 = ld_byte_rhit_lo_lo[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_250 = ld_byte_rhit_hi_lo[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_251 = _T_249 | _T_250; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_lo = {_T_251,_T_243,_T_235,_T_227}; // @[Cat.scala 29:58] + wire [7:0] _T_260 = ld_byte_rhit_lo_hi[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_261 = ld_byte_rhit_hi_hi[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_262 = _T_260 | _T_261; // @[Mux.scala 27:72] + wire [7:0] _T_268 = ld_byte_rhit_lo_hi[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_269 = ld_byte_rhit_hi_hi[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_270 = _T_268 | _T_269; // @[Mux.scala 27:72] + wire [7:0] _T_276 = ld_byte_rhit_lo_hi[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_277 = ld_byte_rhit_hi_hi[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_278 = _T_276 | _T_277; // @[Mux.scala 27:72] + wire [7:0] _T_284 = ld_byte_rhit_lo_hi[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_285 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_286 = _T_284 | _T_285; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_hi = {_T_286,_T_278,_T_270,_T_262}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 141:38] + wire [7:0] _T_294 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_298 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_302 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_306 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[lsu_bus_intf.scala 186:54] + wire [31:0] _T_309 = {_T_306,_T_302,_T_298,_T_294}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 142:38] + wire [7:0] _T_313 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_317 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_321 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[lsu_bus_intf.scala 187:54] + wire [7:0] _T_325 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[lsu_bus_intf.scala 187:54] + wire [31:0] _T_328 = {_T_325,_T_321,_T_317,_T_313}; // @[Cat.scala 29:58] + wire _T_331 = ~ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 188:72] + wire _T_332 = ld_byte_hit_lo[0] | _T_331; // @[lsu_bus_intf.scala 188:70] + wire _T_335 = ~ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 188:72] + wire _T_336 = ld_byte_hit_lo[1] | _T_335; // @[lsu_bus_intf.scala 188:70] + wire _T_339 = ~ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 188:72] + wire _T_340 = ld_byte_hit_lo[2] | _T_339; // @[lsu_bus_intf.scala 188:70] + wire _T_343 = ~ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 188:72] + wire _T_344 = ld_byte_hit_lo[3] | _T_343; // @[lsu_bus_intf.scala 188:70] + wire _T_345 = _T_332 & _T_336; // @[lsu_bus_intf.scala 188:111] + wire _T_346 = _T_345 & _T_340; // @[lsu_bus_intf.scala 188:111] + wire ld_full_hit_lo_m = _T_346 & _T_344; // @[lsu_bus_intf.scala 188:111] + wire _T_350 = ~ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 189:72] + wire _T_351 = ld_byte_hit_hi[0] | _T_350; // @[lsu_bus_intf.scala 189:70] + wire _T_354 = ~ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 189:72] + wire _T_355 = ld_byte_hit_hi[1] | _T_354; // @[lsu_bus_intf.scala 189:70] + wire _T_358 = ~ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 189:72] + wire _T_359 = ld_byte_hit_hi[2] | _T_358; // @[lsu_bus_intf.scala 189:70] + wire _T_362 = ~ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 189:72] + wire _T_363 = ld_byte_hit_hi[3] | _T_362; // @[lsu_bus_intf.scala 189:70] + wire _T_364 = _T_351 & _T_355; // @[lsu_bus_intf.scala 189:111] + wire _T_365 = _T_364 & _T_359; // @[lsu_bus_intf.scala 189:111] + wire ld_full_hit_hi_m = _T_365 & _T_363; // @[lsu_bus_intf.scala 189:111] + wire _T_367 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[lsu_bus_intf.scala 190:47] + wire _T_368 = _T_367 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 190:66] + wire _T_369 = _T_368 & io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 190:84] + wire _T_370 = ~io_is_sideeffects_m; // @[lsu_bus_intf.scala 190:111] + wire [63:0] ld_fwddata_hi = {{32'd0}, _T_328}; // @[lsu_bus_intf.scala 187:27] + wire [63:0] ld_fwddata_lo = {{32'd0}, _T_309}; // @[lsu_bus_intf.scala 186:27] + wire [63:0] _T_374 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58] + wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_bus_intf.scala 191:83] + wire [5:0] _T_376 = 4'h8 * _GEN_3; // @[lsu_bus_intf.scala 191:83] + wire [63:0] ld_fwddata_m = _T_374 >> _T_376; // @[lsu_bus_intf.scala 191:76] + reg lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 195:32] + reg is_sideeffects_r; // @[lsu_bus_intf.scala 199:33] + lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 100:39] + .clock(bus_buffer_clock), + .reset(bus_buffer_reset), + .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn), + .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned), + .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), + .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), + .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), + .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), + .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), + .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), + .io_tlu_busbuff_lsu_imprecise_error_addr_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any), + .io_dctl_busbuff_lsu_nonblock_load_valid_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m), + .io_dctl_busbuff_lsu_nonblock_load_tag_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m), + .io_dctl_busbuff_lsu_nonblock_load_inv_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r), + .io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r), + .io_dctl_busbuff_lsu_nonblock_load_data_valid(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid), + .io_dctl_busbuff_lsu_nonblock_load_data_error(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error), + .io_dctl_busbuff_lsu_nonblock_load_data_tag(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag), + .io_dec_tlu_force_halt(bus_buffer_io_dec_tlu_force_halt), + .io_lsu_bus_obuf_c1_clken(bus_buffer_io_lsu_bus_obuf_c1_clken), + .io_lsu_busm_clken(bus_buffer_io_lsu_busm_clken), + .io_lsu_c2_r_clk(bus_buffer_io_lsu_c2_r_clk), + .io_lsu_bus_ibuf_c1_clk(bus_buffer_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_buf_c1_clk(bus_buffer_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(bus_buffer_io_lsu_free_c2_clk), + .io_dec_lsu_valid_raw_d(bus_buffer_io_dec_lsu_valid_raw_d), + .io_lsu_pkt_m_valid(bus_buffer_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_load(bus_buffer_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_r_bits_by(bus_buffer_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(bus_buffer_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(bus_buffer_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(bus_buffer_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(bus_buffer_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(bus_buffer_io_lsu_pkt_r_bits_unsign), + .io_lsu_addr_m(bus_buffer_io_lsu_addr_m), + .io_end_addr_m(bus_buffer_io_end_addr_m), + .io_lsu_addr_r(bus_buffer_io_lsu_addr_r), + .io_end_addr_r(bus_buffer_io_end_addr_r), + .io_store_data_r(bus_buffer_io_store_data_r), + .io_no_word_merge_r(bus_buffer_io_no_word_merge_r), + .io_no_dword_merge_r(bus_buffer_io_no_dword_merge_r), + .io_lsu_busreq_m(bus_buffer_io_lsu_busreq_m), + .io_ld_full_hit_m(bus_buffer_io_ld_full_hit_m), + .io_flush_m_up(bus_buffer_io_flush_m_up), + .io_flush_r(bus_buffer_io_flush_r), + .io_lsu_commit_r(bus_buffer_io_lsu_commit_r), + .io_is_sideeffects_r(bus_buffer_io_is_sideeffects_r), + .io_ldst_dual_d(bus_buffer_io_ldst_dual_d), + .io_ldst_dual_m(bus_buffer_io_ldst_dual_m), + .io_ldst_dual_r(bus_buffer_io_ldst_dual_r), + .io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m), + .io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready), + .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), + .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id), + .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region), + .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache), + .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), + .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), + .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), + .io_lsu_axi_w_bits_strb(bus_buffer_io_lsu_axi_w_bits_strb), + .io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready), + .io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid), + .io_lsu_axi_b_bits_resp(bus_buffer_io_lsu_axi_b_bits_resp), + .io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id), + .io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready), + .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), + .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id), + .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region), + .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache), + .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), + .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), + .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), + .io_lsu_axi_r_bits_data(bus_buffer_io_lsu_axi_r_bits_data), + .io_lsu_axi_r_bits_resp(bus_buffer_io_lsu_axi_r_bits_resp), + .io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en), + .io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q), + .io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(bus_buffer_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_full_any(bus_buffer_io_lsu_bus_buffer_full_any), + .io_lsu_bus_buffer_empty_any(bus_buffer_io_lsu_bus_buffer_empty_any), + .io_ld_byte_hit_buf_lo(bus_buffer_io_ld_byte_hit_buf_lo), + .io_ld_byte_hit_buf_hi(bus_buffer_io_ld_byte_hit_buf_hi), + .io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo), + .io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi), + .io_lsu_nonblock_load_data(bus_buffer_io_lsu_nonblock_load_data) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 103:18] + assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_len = 8'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_burst = 2'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_lock = 1'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_prot = 3'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_aw_bits_qos = 4'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 131:51] + assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 131:51] + assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 131:51] + assign io_axi_w_bits_last = 1'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_b_ready = 1'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_len = 8'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_burst = 2'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_lock = 1'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_prot = 3'h1; // @[lsu_bus_intf.scala 131:51] + assign io_axi_ar_bits_qos = 4'h0; // @[lsu_bus_intf.scala 131:51] + assign io_axi_r_ready = 1'h1; // @[lsu_bus_intf.scala 131:51] + assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 134:38] + assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 135:38] + assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 136:38] + assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 137:38] + assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 192:27] + assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 133:29] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 143:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 143:19] + assign bus_buffer_clock = clock; + assign bus_buffer_reset = reset; + assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 107:51] + assign bus_buffer_io_lsu_bus_obuf_c1_clken = io_lsu_bus_obuf_c1_clken; // @[lsu_bus_intf.scala 105:51] + assign bus_buffer_io_lsu_busm_clken = io_lsu_busm_clken; // @[lsu_bus_intf.scala 106:51] + assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 108:51] + assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 109:51] + assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 111:51] + assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 112:51] + assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 114:51] + assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 117:27] + assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 117:27] + assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 118:27] + assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 121:51] + assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 122:51] + assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 123:51] + assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 124:51] + assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 125:51] + assign bus_buffer_io_no_word_merge_r = _T_19 & _T_21; // @[lsu_bus_intf.scala 144:51] + assign bus_buffer_io_no_dword_merge_r = _T_19 & _T_27; // @[lsu_bus_intf.scala 145:51] + assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 127:51] + assign bus_buffer_io_ld_full_hit_m = _T_369 & _T_370; // @[lsu_bus_intf.scala 151:51] + assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 128:51] + assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 129:51] + assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 130:51] + assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 146:51] + assign bus_buffer_io_ldst_dual_d = io_ldst_dual_d; // @[lsu_bus_intf.scala 147:51] + assign bus_buffer_io_ldst_dual_m = io_ldst_dual_m; // @[lsu_bus_intf.scala 148:51] + assign bus_buffer_io_ldst_dual_r = io_ldst_dual_r; // @[lsu_bus_intf.scala 149:51] + assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 150:51] + assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 131:51] + assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 132:51] + assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 152:51] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + ldst_byteen_r = _RAND_0[3:0]; + _RAND_1 = {1{`RANDOM}}; + lsu_bus_clk_en_q = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + is_sideeffects_r = _RAND_2[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + ldst_byteen_r = 4'h0; + end + if (reset) begin + lsu_bus_clk_en_q = 1'h0; + end + if (reset) begin + is_sideeffects_r = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + ldst_byteen_r <= 4'h0; + end else begin + ldst_byteen_r <= _T_6 | _T_5; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + lsu_bus_clk_en_q <= 1'h0; + end else begin + lsu_bus_clk_en_q <= io_lsu_bus_clk_en; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + is_sideeffects_r <= 1'h0; + end else begin + is_sideeffects_r <= io_is_sideeffects_m; + end + end +endmodule diff --git a/lsu_lsc_ctl.anno.json b/lsu_lsc_ctl.anno.json new file mode 100644 index 00000000..0a7903d3 --- /dev/null +++ b/lsu_lsc_ctl.anno.json @@ -0,0 +1,331 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_addr", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_store_data_m", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_picm_mask_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dma", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dma", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_stack", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_valid", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_dccm_req", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_valid", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_m_up", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_unsign", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_incr", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_by", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_dccm_d", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_corr_r", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"lsu_lsc_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"lsu_lsc_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/lsu_lsc_ctl.fir b/lsu_lsc_ctl.fir new file mode 100644 index 00000000..76a95948 --- /dev/null +++ b/lsu_lsc_ctl.fir @@ -0,0 +1,987 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit lsu_lsc_ctl : + module lsu_addrcheck : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} + + node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 370:27] + node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 370:49] + wire start_addr_in_dccm_d : UInt<1> @[lib.scala 371:26] + node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 375:24] + node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 375:39] + start_addr_in_dccm_d <= _T_2 @[lib.scala 375:16] + node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 370:27] + node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 370:49] + wire end_addr_in_dccm_d : UInt<1> @[lib.scala 371:26] + node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 375:24] + node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 375:39] + end_addr_in_dccm_d <= _T_5 @[lib.scala 375:16] + wire addr_in_iccm : UInt<1> + addr_in_iccm <= UInt<1>("h00") + node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37] + node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45] + addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18] + node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89] + node _T_9 = bits(_T_8, 31, 28) @[lib.scala 370:27] + node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 370:49] + wire start_addr_in_pic_d : UInt<1> @[lib.scala 371:26] + node _T_10 = bits(_T_8, 31, 15) @[lib.scala 375:24] + node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 375:39] + start_addr_in_pic_d <= _T_11 @[lib.scala 375:16] + node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83] + node _T_13 = bits(_T_12, 31, 28) @[lib.scala 370:27] + node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 370:49] + wire end_addr_in_pic_d : UInt<1> @[lib.scala 371:26] + node _T_14 = bits(_T_12, 31, 15) @[lib.scala 375:24] + node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 375:39] + end_addr_in_pic_d <= _T_15 @[lib.scala 375:16] + node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60] + node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49] + node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55] + node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74] + node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109] + node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115] + node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91] + node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57] + io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32] + node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56] + io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32] + node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63] + node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33] + io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30] + node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51] + node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50] + node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50] + node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92] + node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62] + node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60] + node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137] + node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185] + node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158] + node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80] + node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56] + node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134] + node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138] + node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116] + node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90] + node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148] + node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58] + node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58] + node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58] + node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99] + node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33] + node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49] + node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56] + node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121] + node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88] + node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30] + node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49] + node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56] + node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121] + node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88] + node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30] + node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153] + node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49] + node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56] + node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121] + node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88] + node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30] + node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153] + node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49] + node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56] + node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121] + node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88] + node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30] + node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153] + node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49] + node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56] + node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121] + node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88] + node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30] + node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153] + node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49] + node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56] + node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121] + node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88] + node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30] + node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153] + node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49] + node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56] + node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121] + node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88] + node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30] + node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153] + node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49] + node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56] + node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121] + node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88] + node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30] + node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153] + node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48] + node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57] + node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122] + node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89] + node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31] + node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49] + node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58] + node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123] + node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90] + node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32] + node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154] + node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49] + node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58] + node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123] + node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90] + node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32] + node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155] + node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49] + node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58] + node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123] + node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90] + node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32] + node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155] + node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49] + node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58] + node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123] + node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90] + node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32] + node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155] + node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49] + node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58] + node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123] + node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90] + node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32] + node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155] + node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49] + node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58] + node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123] + node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90] + node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32] + node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155] + node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49] + node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58] + node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123] + node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90] + node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32] + node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155] + node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7] + node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104] + node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57] + node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70] + node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76] + node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92] + node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90] + node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51] + wire unmapped_access_fault_d : UInt<1> + unmapped_access_fault_d <= UInt<1>("h01") + wire mpu_access_fault_d : UInt<1> + mpu_access_fault_d <= UInt<1>("h01") + node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64] + node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62] + node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36] + node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34] + node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112] + node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29] + node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85] + node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29] + node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85] + unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29] + node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33] + node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64] + node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62] + mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29] + node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49] + node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70] + node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92] + node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118] + node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141] + node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139] + io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21] + node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60] + node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100] + node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144] + node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185] + node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164] + node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120] + node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80] + node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35] + node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53] + node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78] + node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61] + node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59] + node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57] + node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90] + node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57] + node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113] + node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136] + node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134] + io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25] + node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111] + node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80] + node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39] + node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50] + node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84] + node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113] + node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27] + io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21] + node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66] + node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64] + node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120] + node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118] + node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88] + node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142] + node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163] + io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31] + node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66] + node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36] + node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95] + node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116] + io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33] + reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60] + _T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60] + io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50] + + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_lsc_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} + + wire end_addr_pre_m : UInt<29> + end_addr_pre_m <= UInt<29>("h00") + wire end_addr_pre_r : UInt<29> + end_addr_pre_r <= UInt<29>("h00") + wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 93:29] + wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 94:29] + wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29] + wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 96:29] + wire _T : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 97:35] + _T.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + _T.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35] + lsu_error_pkt_m.bits.addr <= _T.bits.addr @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.mscause <= _T.bits.mscause @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.exc_type <= _T.bits.exc_type @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.inst_type <= _T.bits.inst_type @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.bits.single_ecc_error <= _T.bits.single_ecc_error @[lsu_lsc_ctl.scala 97:20] + lsu_error_pkt_m.valid <= _T.valid @[lsu_lsc_ctl.scala 97:20] + node _T_1 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 99:52] + node lsu_rs1_d = mux(_T_1, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 99:28] + node _T_2 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 100:44] + node _T_3 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node lsu_offset_d = and(_T_2, _T_4) @[lsu_lsc_ctl.scala 100:51] + node _T_5 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 103:66] + node rs1_d = mux(_T_5, io.lsu_exu.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 103:28] + node _T_6 = bits(rs1_d, 11, 0) @[lib.scala 92:31] + node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58] + node _T_8 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60] + node _T_9 = cat(UInt<1>("h00"), _T_8) @[Cat.scala 29:58] + node _T_10 = add(_T_7, _T_9) @[lib.scala 92:39] + node _T_11 = tail(_T_10, 1) @[lib.scala 92:39] + node _T_12 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41] + node _T_13 = bits(_T_11, 12, 12) @[lib.scala 93:50] + node _T_14 = xor(_T_12, _T_13) @[lib.scala 93:46] + node _T_15 = not(_T_14) @[lib.scala 93:33] + node _T_16 = bits(_T_15, 0, 0) @[Bitwise.scala 72:15] + node _T_17 = mux(_T_16, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_18 = bits(rs1_d, 31, 12) @[lib.scala 93:63] + node _T_19 = and(_T_17, _T_18) @[lib.scala 93:58] + node _T_20 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25] + node _T_21 = not(_T_20) @[lib.scala 94:18] + node _T_22 = bits(_T_11, 12, 12) @[lib.scala 94:34] + node _T_23 = and(_T_21, _T_22) @[lib.scala 94:30] + node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15] + node _T_25 = mux(_T_24, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_26 = bits(rs1_d, 31, 12) @[lib.scala 94:47] + node _T_27 = add(_T_26, UInt<1>("h01")) @[lib.scala 94:54] + node _T_28 = tail(_T_27, 1) @[lib.scala 94:54] + node _T_29 = and(_T_25, _T_28) @[lib.scala 94:41] + node _T_30 = or(_T_19, _T_29) @[lib.scala 93:72] + node _T_31 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24] + node _T_32 = bits(_T_11, 12, 12) @[lib.scala 95:34] + node _T_33 = not(_T_32) @[lib.scala 95:31] + node _T_34 = and(_T_31, _T_33) @[lib.scala 95:29] + node _T_35 = bits(_T_34, 0, 0) @[Bitwise.scala 72:15] + node _T_36 = mux(_T_35, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_37 = bits(rs1_d, 31, 12) @[lib.scala 95:47] + node _T_38 = sub(_T_37, UInt<1>("h01")) @[lib.scala 95:54] + node _T_39 = tail(_T_38, 1) @[lib.scala 95:54] + node _T_40 = and(_T_36, _T_39) @[lib.scala 95:41] + node _T_41 = or(_T_30, _T_40) @[lib.scala 94:61] + node _T_42 = bits(_T_11, 11, 0) @[lib.scala 96:22] + node full_addr_d = cat(_T_41, _T_42) @[Cat.scala 29:58] + node _T_43 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_44 = mux(_T_43, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_45 = and(_T_44, UInt<3>("h01")) @[lsu_lsc_ctl.scala 108:58] + node _T_46 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_47 = mux(_T_46, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_48 = and(_T_47, UInt<3>("h03")) @[lsu_lsc_ctl.scala 109:40] + node _T_49 = or(_T_45, _T_48) @[lsu_lsc_ctl.scala 108:70] + node _T_50 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15] + node _T_51 = mux(_T_50, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_52 = and(_T_51, UInt<3>("h07")) @[lsu_lsc_ctl.scala 110:40] + node addr_offset_d = or(_T_49, _T_52) @[lsu_lsc_ctl.scala 109:52] + node _T_53 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 112:39] + node _T_54 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 112:52] + node _T_55 = cat(_T_53, _T_54) @[Cat.scala 29:58] + node _T_56 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_57 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 112:91] + node _T_58 = cat(_T_56, _T_57) @[Cat.scala 29:58] + node _T_59 = add(_T_55, _T_58) @[lsu_lsc_ctl.scala 112:60] + node end_addr_offset_d = tail(_T_59, 1) @[lsu_lsc_ctl.scala 112:60] + node _T_60 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 113:32] + node _T_61 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 113:70] + node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] + node _T_63 = mux(_T_62, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] + node _T_64 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 113:93] + node _T_65 = cat(_T_63, _T_64) @[Cat.scala 29:58] + node _T_66 = add(_T_60, _T_65) @[lsu_lsc_ctl.scala 113:39] + node full_end_addr_d = tail(_T_66, 1) @[lsu_lsc_ctl.scala 113:39] + io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 114:24] + inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 117:25] + addrcheck.clock <= clock + addrcheck.reset <= reset + addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 121:42] + addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 122:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 123:42] + addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 124:42] + node _T_67 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 125:50] + addrcheck.io.rs1_region_d <= _T_67 @[lsu_lsc_ctl.scala 125:42] + addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 126:42] + io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 127:42] + io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 128:42] + io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 129:42] + addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 136:42] + wire exc_mscause_r : UInt<4> + exc_mscause_r <= UInt<4>("h00") + wire fir_dccm_access_error_r : UInt<1> + fir_dccm_access_error_r <= UInt<1>("h00") + wire fir_nondccm_access_error_r : UInt<1> + fir_nondccm_access_error_r <= UInt<1>("h00") + wire access_fault_r : UInt<1> + access_fault_r <= UInt<1>("h00") + wire misaligned_fault_r : UInt<1> + misaligned_fault_r <= UInt<1>("h00") + wire lsu_fir_error_m : UInt<2> + lsu_fir_error_m <= UInt<2>("h00") + wire fir_dccm_access_error_m : UInt<1> + fir_dccm_access_error_m <= UInt<1>("h00") + wire fir_nondccm_access_error_m : UInt<1> + fir_nondccm_access_error_m <= UInt<1>("h00") + reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 148:75] + access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 148:75] + reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75] + misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 149:75] + reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75] + exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 150:75] + reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75] + _T_68 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 151:75] + fir_dccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 151:38] + reg _T_69 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75] + _T_69 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 152:75] + fir_nondccm_access_error_m <= _T_69 @[lsu_lsc_ctl.scala 152:38] + node _T_70 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 154:34] + io.lsu_exc_m <= _T_70 @[lsu_lsc_ctl.scala 154:16] + node _T_71 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 155:64] + node _T_72 = and(io.lsu_single_ecc_error_r, _T_71) @[lsu_lsc_ctl.scala 155:62] + node _T_73 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 155:111] + node _T_74 = and(_T_72, _T_73) @[lsu_lsc_ctl.scala 155:92] + node _T_75 = and(_T_74, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 155:136] + io.lsu_single_ecc_error_incr <= _T_75 @[lsu_lsc_ctl.scala 155:32] + node _T_76 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 177:46] + node _T_77 = or(_T_76, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 177:67] + node _T_78 = and(_T_77, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 177:96] + node _T_79 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:119] + node _T_80 = and(_T_78, _T_79) @[lsu_lsc_ctl.scala 177:117] + node _T_81 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:144] + node _T_82 = and(_T_80, _T_81) @[lsu_lsc_ctl.scala 177:142] + node _T_83 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:174] + node _T_84 = and(_T_82, _T_83) @[lsu_lsc_ctl.scala 177:172] + lsu_error_pkt_m.valid <= _T_84 @[lsu_lsc_ctl.scala 177:27] + node _T_85 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:75] + node _T_86 = and(io.lsu_single_ecc_error_m, _T_85) @[lsu_lsc_ctl.scala 178:73] + node _T_87 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:101] + node _T_88 = and(_T_86, _T_87) @[lsu_lsc_ctl.scala 178:99] + lsu_error_pkt_m.bits.single_ecc_error <= _T_88 @[lsu_lsc_ctl.scala 178:43] + lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 179:43] + node _T_89 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 180:46] + lsu_error_pkt_m.bits.exc_type <= _T_89 @[lsu_lsc_ctl.scala 180:43] + node _T_90 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:80] + node _T_91 = and(io.lsu_double_ecc_error_m, _T_90) @[lsu_lsc_ctl.scala 181:78] + node _T_92 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:102] + node _T_93 = and(_T_91, _T_92) @[lsu_lsc_ctl.scala 181:100] + node _T_94 = eq(_T_93, UInt<1>("h01")) @[lsu_lsc_ctl.scala 181:118] + node _T_95 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 181:149] + node _T_96 = mux(_T_94, UInt<4>("h01"), _T_95) @[lsu_lsc_ctl.scala 181:49] + lsu_error_pkt_m.bits.mscause <= _T_96 @[lsu_lsc_ctl.scala 181:43] + node _T_97 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 182:59] + lsu_error_pkt_m.bits.addr <= _T_97 @[lsu_lsc_ctl.scala 182:43] + node _T_98 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:72] + node _T_99 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:117] + node _T_100 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 183:166] + node _T_101 = bits(_T_100, 0, 0) @[lsu_lsc_ctl.scala 183:195] + node _T_102 = mux(_T_101, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 183:137] + node _T_103 = mux(_T_99, UInt<2>("h02"), _T_102) @[lsu_lsc_ctl.scala 183:92] + node _T_104 = mux(_T_98, UInt<2>("h03"), _T_103) @[lsu_lsc_ctl.scala 183:44] + lsu_fir_error_m <= _T_104 @[lsu_lsc_ctl.scala 183:38] + node _T_105 = or(lsu_error_pkt_m.valid, lsu_error_pkt_m.bits.single_ecc_error) @[lsu_lsc_ctl.scala 184:73] + node _T_106 = or(_T_105, io.clk_override) @[lsu_lsc_ctl.scala 184:113] + node _T_107 = bits(_T_106, 0, 0) @[lib.scala 8:44] + node _T_108 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr of rvclkhdr @[lib.scala 417:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 419:18] + rvclkhdr.io.en <= _T_107 @[lib.scala 420:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 421:24] + wire _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 423:50] + _T_109.bits.addr <= UInt<32>("h00") @[lib.scala 423:50] + _T_109.bits.mscause <= UInt<4>("h00") @[lib.scala 423:50] + _T_109.bits.exc_type <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.bits.inst_type <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 423:50] + _T_109.valid <= UInt<1>("h00") @[lib.scala 423:50] + reg _T_110 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, clock with : (reset => (reset, _T_109)) @[Reg.scala 27:20] + when _T_107 : @[Reg.scala 28:19] + _T_110.bits.addr <= lsu_error_pkt_m.bits.addr @[Reg.scala 28:23] + _T_110.bits.mscause <= lsu_error_pkt_m.bits.mscause @[Reg.scala 28:23] + _T_110.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[Reg.scala 28:23] + _T_110.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[Reg.scala 28:23] + _T_110.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[Reg.scala 28:23] + _T_110.valid <= lsu_error_pkt_m.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.lsu_error_pkt_r.bits.addr <= _T_110.bits.addr @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.mscause <= _T_110.bits.mscause @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.exc_type <= _T_110.bits.exc_type @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.inst_type <= _T_110.bits.inst_type @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.bits.single_ecc_error <= _T_110.bits.single_ecc_error @[lsu_lsc_ctl.scala 184:24] + io.lsu_error_pkt_r.valid <= _T_110.valid @[lsu_lsc_ctl.scala 184:24] + reg _T_111 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 185:83] + _T_111 <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 185:83] + io.lsu_error_pkt_r.bits.single_ecc_error <= _T_111 @[lsu_lsc_ctl.scala 185:46] + reg _T_112 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 186:67] + _T_112 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 186:67] + io.lsu_error_pkt_r.valid <= _T_112 @[lsu_lsc_ctl.scala 186:30] + reg _T_113 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:75] + _T_113 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 187:75] + io.lsu_fir_error <= _T_113 @[lsu_lsc_ctl.scala 187:38] + dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 189:27] + dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:26] + dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27] + dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22] + dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27] + dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27] + node _T_114 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30] + dma_pkt_d.bits.load <= _T_114 @[lsu_lsc_ctl.scala 195:27] + node _T_115 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56] + node _T_116 = eq(_T_115, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62] + dma_pkt_d.bits.by <= _T_116 @[lsu_lsc_ctl.scala 196:27] + node _T_117 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56] + node _T_118 = eq(_T_117, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62] + dma_pkt_d.bits.half <= _T_118 @[lsu_lsc_ctl.scala 197:27] + node _T_119 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56] + node _T_120 = eq(_T_119, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62] + dma_pkt_d.bits.word <= _T_120 @[lsu_lsc_ctl.scala 198:27] + node _T_121 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56] + node _T_122 = eq(_T_121, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62] + dma_pkt_d.bits.dword <= _T_122 @[lsu_lsc_ctl.scala 199:27] + dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39] + dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39] + dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39] + wire lsu_ld_datafn_r : UInt<32> + lsu_ld_datafn_r <= UInt<32>("h00") + wire lsu_ld_datafn_corr_r : UInt<32> + lsu_ld_datafn_corr_r <= UInt<32>("h00") + wire lsu_ld_datafn_m : UInt<32> + lsu_ld_datafn_m <= UInt<32>("h00") + node _T_123 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50] + node _T_124 = mux(_T_123, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26] + io.lsu_pkt_d.bits.store_data_bypass_m <= _T_124.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_124.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.store_data_bypass_d <= _T_124.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.dma <= _T_124.bits.dma @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.unsign <= _T_124.bits.unsign @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.store <= _T_124.bits.store @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.load <= _T_124.bits.load @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.dword <= _T_124.bits.dword @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.word <= _T_124.bits.word @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.half <= _T_124.bits.half @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.by <= _T_124.bits.by @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.stack <= _T_124.bits.stack @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.fast_int <= _T_124.bits.fast_int @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.valid <= _T_124.valid @[lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20] + node _T_125 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64] + node _T_126 = and(io.flush_m_up, _T_125) @[lsu_lsc_ctl.scala 212:61] + node _T_127 = eq(_T_126, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45] + node _T_128 = and(io.lsu_p.valid, _T_127) @[lsu_lsc_ctl.scala 212:43] + node _T_129 = or(_T_128, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90] + io.lsu_pkt_d.valid <= _T_129 @[lsu_lsc_ctl.scala 212:24] + node _T_130 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68] + node _T_131 = and(io.flush_m_up, _T_130) @[lsu_lsc_ctl.scala 213:65] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49] + node _T_133 = and(io.lsu_pkt_d.valid, _T_132) @[lsu_lsc_ctl.scala 213:47] + lsu_pkt_m_in.valid <= _T_133 @[lsu_lsc_ctl.scala 213:24] + node _T_134 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68] + node _T_135 = and(io.flush_m_up, _T_134) @[lsu_lsc_ctl.scala 214:65] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49] + node _T_137 = and(io.lsu_pkt_m.valid, _T_136) @[lsu_lsc_ctl.scala 214:47] + lsu_pkt_r_in.valid <= _T_137 @[lsu_lsc_ctl.scala 214:24] + wire _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_138.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + reg _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_138)) @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 216:65] + _T_139.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65] + _T_139.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65] + io.lsu_pkt_m.bits.store_data_bypass_m <= _T_139.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_139.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.store_data_bypass_d <= _T_139.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.dma <= _T_139.bits.dma @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.unsign <= _T_139.bits.unsign @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.store <= _T_139.bits.store @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.load <= _T_139.bits.load @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.dword <= _T_139.bits.dword @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.word <= _T_139.bits.word @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.half <= _T_139.bits.half @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.by <= _T_139.bits.by @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.stack <= _T_139.bits.stack @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.fast_int <= _T_139.bits.fast_int @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.valid <= _T_139.valid @[lsu_lsc_ctl.scala 216:28] + wire _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_140.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + reg _T_141 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_140)) @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 217:65] + _T_141.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65] + _T_141.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65] + io.lsu_pkt_r.bits.store_data_bypass_m <= _T_141.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_141.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.store_data_bypass_d <= _T_141.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.dma <= _T_141.bits.dma @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.unsign <= _T_141.bits.unsign @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.store <= _T_141.bits.store @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.load <= _T_141.bits.load @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.dword <= _T_141.bits.dword @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.word <= _T_141.bits.word @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.half <= _T_141.bits.half @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.by <= _T_141.bits.by @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.stack <= _T_141.bits.stack @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.fast_int <= _T_141.bits.fast_int @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.valid <= _T_141.valid @[lsu_lsc_ctl.scala 217:28] + reg _T_142 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65] + _T_142 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65] + io.lsu_pkt_m.valid <= _T_142 @[lsu_lsc_ctl.scala 218:28] + reg _T_143 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65] + _T_143 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65] + io.lsu_pkt_r.valid <= _T_143 @[lsu_lsc_ctl.scala 219:28] + node _T_144 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59] + node _T_145 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100] + node _T_146 = cat(_T_145, UInt<3>("h00")) @[Cat.scala 29:58] + node dma_mem_wdata_shifted = dshr(_T_144, _T_146) @[lsu_lsc_ctl.scala 221:66] + node _T_147 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63] + node _T_148 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91] + node _T_149 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122] + node store_data_d = mux(_T_147, _T_148, _T_149) @[lsu_lsc_ctl.scala 222:34] + node _T_150 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73] + node _T_151 = bits(io.lsu_exu.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:103] + node _T_152 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:122] + node store_data_m_in = mux(_T_150, _T_151, _T_152) @[lsu_lsc_ctl.scala 223:34] + node _T_153 = bits(io.lsu_addr_d, 2, 2) @[lsu_lsc_ctl.scala 225:61] + reg _T_154 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:47] + _T_154 <= _T_153 @[lsu_lsc_ctl.scala 225:47] + node _T_155 = bits(io.end_addr_d, 2, 2) @[lsu_lsc_ctl.scala 225:123] + reg _T_156 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:109] + _T_156 <= _T_155 @[lsu_lsc_ctl.scala 225:109] + node int = neq(_T_154, _T_156) @[lsu_lsc_ctl.scala 225:71] + node _T_157 = bits(io.lsu_addr_m, 2, 2) @[lsu_lsc_ctl.scala 226:62] + reg _T_158 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:48] + _T_158 <= _T_157 @[lsu_lsc_ctl.scala 226:48] + node _T_159 = bits(io.end_addr_m, 2, 2) @[lsu_lsc_ctl.scala 226:124] + reg _T_160 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:110] + _T_160 <= _T_159 @[lsu_lsc_ctl.scala 226:110] + node int1 = neq(_T_158, _T_160) @[lsu_lsc_ctl.scala 226:72] + reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:72] + store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 229:72] + reg _T_161 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:62] + _T_161 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 230:62] + io.lsu_addr_m <= _T_161 @[lsu_lsc_ctl.scala 230:24] + reg _T_162 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 231:62] + _T_162 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 231:62] + io.lsu_addr_r <= _T_162 @[lsu_lsc_ctl.scala 231:24] + node _T_163 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:60] + node _T_164 = mux(int, end_addr_pre_m, _T_163) @[lsu_lsc_ctl.scala 232:27] + node _T_165 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 232:117] + reg _T_166 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:103] + _T_166 <= _T_165 @[lsu_lsc_ctl.scala 232:103] + node _T_167 = cat(_T_164, _T_166) @[Cat.scala 29:58] + io.end_addr_m <= _T_167 @[lsu_lsc_ctl.scala 232:17] + node _T_168 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 233:61] + node _T_169 = mux(int1, end_addr_pre_r, _T_168) @[lsu_lsc_ctl.scala 233:27] + node _T_170 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 233:118] + reg _T_171 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:104] + _T_171 <= _T_170 @[lsu_lsc_ctl.scala 233:104] + node _T_172 = cat(_T_169, _T_171) @[Cat.scala 29:58] + io.end_addr_r <= _T_172 @[lsu_lsc_ctl.scala 233:17] + node _T_173 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 234:41] + node _T_174 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 234:69] + node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 234:87] + node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_175 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_175 : @[Reg.scala 28:19] + _T_177 <= _T_173 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + end_addr_pre_m <= _T_177 @[lsu_lsc_ctl.scala 234:18] + node _T_178 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 235:41] + node _T_179 = and(io.lsu_pkt_m.valid, int) @[lsu_lsc_ctl.scala 235:69] + node _T_180 = or(_T_179, io.clk_override) @[lsu_lsc_ctl.scala 235:76] + node _T_181 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_180 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_182 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_180 : @[Reg.scala 28:19] + _T_182 <= _T_178 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + end_addr_pre_r <= _T_182 @[lsu_lsc_ctl.scala 235:18] + reg _T_183 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62] + _T_183 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 236:62] + io.addr_in_dccm_m <= _T_183 @[lsu_lsc_ctl.scala 236:24] + reg _T_184 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62] + _T_184 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 237:62] + io.addr_in_dccm_r <= _T_184 @[lsu_lsc_ctl.scala 237:24] + reg _T_185 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:62] + _T_185 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 238:62] + io.addr_in_pic_m <= _T_185 @[lsu_lsc_ctl.scala 238:24] + reg _T_186 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 239:62] + _T_186 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 239:62] + io.addr_in_pic_r <= _T_186 @[lsu_lsc_ctl.scala 239:24] + reg _T_187 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 240:62] + _T_187 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 240:62] + io.addr_external_m <= _T_187 @[lsu_lsc_ctl.scala 240:24] + reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 241:66] + addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 241:66] + node _T_188 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 242:77] + node _T_189 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_188 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_188 : @[Reg.scala 28:19] + bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_190 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 245:52] + io.lsu_fir_addr <= _T_190 @[lsu_lsc_ctl.scala 245:28] + io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 247:28] + node _T_191 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 249:68] + node _T_192 = and(io.lsu_pkt_r.valid, _T_191) @[lsu_lsc_ctl.scala 249:41] + node _T_193 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 249:96] + node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 249:94] + node _T_195 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 249:110] + node _T_196 = and(_T_194, _T_195) @[lsu_lsc_ctl.scala 249:108] + io.lsu_commit_r <= _T_196 @[lsu_lsc_ctl.scala 249:19] + node _T_197 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 250:52] + node _T_198 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 250:69] + node _T_199 = bits(_T_198, 0, 0) @[Bitwise.scala 72:15] + node _T_200 = mux(_T_199, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_201 = or(_T_197, _T_200) @[lsu_lsc_ctl.scala 250:59] + node _T_202 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 250:133] + node _T_203 = mux(_T_202, io.lsu_exu.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 250:94] + node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 250:89] + io.store_data_m <= _T_204 @[lsu_lsc_ctl.scala 250:29] + node _T_205 = mux(io.addr_external_m, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 271:33] + lsu_ld_datafn_m <= _T_205 @[lsu_lsc_ctl.scala 271:27] + node _T_206 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 272:49] + node _T_207 = mux(_T_206, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 272:33] + lsu_ld_datafn_corr_r <= _T_207 @[lsu_lsc_ctl.scala 272:27] + node _T_208 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 273:74] + node _T_209 = bits(_T_208, 0, 0) @[Bitwise.scala 72:15] + node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_211 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 273:133] + node _T_212 = cat(UInt<24>("h00"), _T_211) @[Cat.scala 29:58] + node _T_213 = and(_T_210, _T_212) @[lsu_lsc_ctl.scala 273:102] + node _T_214 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 274:43] + node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15] + node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_217 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 274:102] + node _T_218 = cat(UInt<16>("h00"), _T_217) @[Cat.scala 29:58] + node _T_219 = and(_T_216, _T_218) @[lsu_lsc_ctl.scala 274:71] + node _T_220 = or(_T_213, _T_219) @[lsu_lsc_ctl.scala 273:141] + node _T_221 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 275:17] + node _T_222 = and(_T_221, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 275:43] + node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15] + node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_225 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 275:102] + node _T_226 = bits(_T_225, 0, 0) @[Bitwise.scala 72:15] + node _T_227 = mux(_T_226, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_228 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 275:125] + node _T_229 = cat(_T_227, _T_228) @[Cat.scala 29:58] + node _T_230 = and(_T_224, _T_229) @[lsu_lsc_ctl.scala 275:71] + node _T_231 = or(_T_220, _T_230) @[lsu_lsc_ctl.scala 274:114] + node _T_232 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 276:17] + node _T_233 = and(_T_232, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 276:43] + node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15] + node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_236 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 276:101] + node _T_237 = bits(_T_236, 0, 0) @[Bitwise.scala 72:15] + node _T_238 = mux(_T_237, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_239 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 276:125] + node _T_240 = cat(_T_238, _T_239) @[Cat.scala 29:58] + node _T_241 = and(_T_235, _T_240) @[lsu_lsc_ctl.scala 276:71] + node _T_242 = or(_T_231, _T_241) @[lsu_lsc_ctl.scala 275:134] + node _T_243 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_244 = mux(_T_243, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_245 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 277:60] + node _T_246 = and(_T_244, _T_245) @[lsu_lsc_ctl.scala 277:43] + node _T_247 = or(_T_242, _T_246) @[lsu_lsc_ctl.scala 276:134] + io.lsu_exu.lsu_result_m <= _T_247 @[lsu_lsc_ctl.scala 273:35] + node _T_248 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 278:66] + node _T_249 = bits(_T_248, 0, 0) @[Bitwise.scala 72:15] + node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_251 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 278:130] + node _T_252 = cat(UInt<24>("h00"), _T_251) @[Cat.scala 29:58] + node _T_253 = and(_T_250, _T_252) @[lsu_lsc_ctl.scala 278:94] + node _T_254 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 279:43] + node _T_255 = bits(_T_254, 0, 0) @[Bitwise.scala 72:15] + node _T_256 = mux(_T_255, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_257 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 279:107] + node _T_258 = cat(UInt<16>("h00"), _T_257) @[Cat.scala 29:58] + node _T_259 = and(_T_256, _T_258) @[lsu_lsc_ctl.scala 279:71] + node _T_260 = or(_T_253, _T_259) @[lsu_lsc_ctl.scala 278:138] + node _T_261 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 280:17] + node _T_262 = and(_T_261, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 280:43] + node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15] + node _T_264 = mux(_T_263, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 280:107] + node _T_266 = bits(_T_265, 0, 0) @[Bitwise.scala 72:15] + node _T_267 = mux(_T_266, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_268 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 280:135] + node _T_269 = cat(_T_267, _T_268) @[Cat.scala 29:58] + node _T_270 = and(_T_264, _T_269) @[lsu_lsc_ctl.scala 280:71] + node _T_271 = or(_T_260, _T_270) @[lsu_lsc_ctl.scala 279:119] + node _T_272 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 281:17] + node _T_273 = and(_T_272, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 281:43] + node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15] + node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 281:106] + node _T_277 = bits(_T_276, 0, 0) @[Bitwise.scala 72:15] + node _T_278 = mux(_T_277, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_279 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 281:135] + node _T_280 = cat(_T_278, _T_279) @[Cat.scala 29:58] + node _T_281 = and(_T_275, _T_280) @[lsu_lsc_ctl.scala 281:71] + node _T_282 = or(_T_271, _T_281) @[lsu_lsc_ctl.scala 280:144] + node _T_283 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_284 = mux(_T_283, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_285 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 282:65] + node _T_286 = and(_T_284, _T_285) @[lsu_lsc_ctl.scala 282:43] + node _T_287 = or(_T_282, _T_286) @[lsu_lsc_ctl.scala 281:144] + io.lsu_result_corr_r <= _T_287 @[lsu_lsc_ctl.scala 278:27] + diff --git a/lsu_lsc_ctl.v b/lsu_lsc_ctl.v new file mode 100644 index 00000000..528cdc60 --- /dev/null +++ b/lsu_lsc_ctl.v @@ -0,0 +1,1500 @@ +module lsu_addrcheck( + input reset, + input io_lsu_c2_m_clk, + input [31:0] io_start_addr_d, + input [31:0] io_end_addr_d, + input io_lsu_pkt_d_valid, + input io_lsu_pkt_d_bits_fast_int, + input io_lsu_pkt_d_bits_by, + input io_lsu_pkt_d_bits_half, + input io_lsu_pkt_d_bits_word, + input io_lsu_pkt_d_bits_load, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_d_bits_dma, + input [31:0] io_dec_tlu_mrac_ff, + input [3:0] io_rs1_region_d, + output io_is_sideeffects_m, + output io_addr_in_dccm_d, + output io_addr_in_pic_d, + output io_addr_external_d, + output io_access_fault_d, + output io_misaligned_fault_d, + output [3:0] io_exc_mscause_d, + output io_fir_dccm_access_error_d, + output io_fir_nondccm_access_error_d +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 370:49] + wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 375:39] + wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 370:49] + wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 375:39] + wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45] + wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 375:39] + wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 375:39] + wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60] + wire _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:55] + wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:91] + wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58] + wire [31:0] _T_26 = io_dec_tlu_mrac_ff >> csr_idx; // @[lsu_addrcheck.scala 61:50] + wire _T_29 = start_addr_dccm_or_pic | addr_in_iccm; // @[lsu_addrcheck.scala 61:121] + wire _T_30 = ~_T_29; // @[lsu_addrcheck.scala 61:62] + wire _T_31 = _T_26[0] & _T_30; // @[lsu_addrcheck.scala 61:60] + wire _T_32 = _T_31 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 61:137] + wire _T_33 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[lsu_addrcheck.scala 61:185] + wire is_sideeffects_d = _T_32 & _T_33; // @[lsu_addrcheck.scala 61:158] + wire _T_35 = io_start_addr_d[1:0] == 2'h0; // @[lsu_addrcheck.scala 62:80] + wire _T_36 = io_lsu_pkt_d_bits_word & _T_35; // @[lsu_addrcheck.scala 62:56] + wire _T_38 = ~io_start_addr_d[0]; // @[lsu_addrcheck.scala 62:138] + wire _T_39 = io_lsu_pkt_d_bits_half & _T_38; // @[lsu_addrcheck.scala 62:116] + wire _T_40 = _T_36 | _T_39; // @[lsu_addrcheck.scala 62:90] + wire is_aligned_d = _T_40 | io_lsu_pkt_d_bits_by; // @[lsu_addrcheck.scala 62:148] + wire [31:0] _T_51 = io_start_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 67:56] + wire _T_53 = _T_51 == 32'h7fffffff; // @[lsu_addrcheck.scala 67:88] + wire [31:0] _T_56 = io_start_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 68:56] + wire _T_58 = _T_56 == 32'hffffffff; // @[lsu_addrcheck.scala 68:88] + wire _T_60 = _T_53 | _T_58; // @[lsu_addrcheck.scala 67:153] + wire [31:0] _T_62 = io_start_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 69:56] + wire _T_64 = _T_62 == 32'hbfffffff; // @[lsu_addrcheck.scala 69:88] + wire _T_66 = _T_60 | _T_64; // @[lsu_addrcheck.scala 68:153] + wire [31:0] _T_68 = io_start_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 70:56] + wire _T_70 = _T_68 == 32'h8fffffff; // @[lsu_addrcheck.scala 70:88] + wire _T_72 = _T_66 | _T_70; // @[lsu_addrcheck.scala 69:153] + wire [31:0] _T_98 = io_end_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 76:57] + wire _T_100 = _T_98 == 32'h7fffffff; // @[lsu_addrcheck.scala 76:89] + wire [31:0] _T_103 = io_end_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 77:58] + wire _T_105 = _T_103 == 32'hffffffff; // @[lsu_addrcheck.scala 77:90] + wire _T_107 = _T_100 | _T_105; // @[lsu_addrcheck.scala 76:154] + wire [31:0] _T_109 = io_end_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 78:58] + wire _T_111 = _T_109 == 32'hbfffffff; // @[lsu_addrcheck.scala 78:90] + wire _T_113 = _T_107 | _T_111; // @[lsu_addrcheck.scala 77:155] + wire [31:0] _T_115 = io_end_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 79:58] + wire _T_117 = _T_115 == 32'h8fffffff; // @[lsu_addrcheck.scala 79:90] + wire _T_119 = _T_113 | _T_117; // @[lsu_addrcheck.scala 78:155] + wire non_dccm_access_ok = _T_72 & _T_119; // @[lsu_addrcheck.scala 75:7] + wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[lsu_addrcheck.scala 85:57] + wire _T_146 = io_start_addr_d[1:0] != 2'h0; // @[lsu_addrcheck.scala 86:76] + wire _T_147 = ~io_lsu_pkt_d_bits_word; // @[lsu_addrcheck.scala 86:92] + wire _T_148 = _T_146 | _T_147; // @[lsu_addrcheck.scala 86:90] + wire picm_access_fault_d = io_addr_in_pic_d & _T_148; // @[lsu_addrcheck.scala 86:51] + wire _T_149 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[lsu_addrcheck.scala 91:87] + wire _T_150 = ~_T_149; // @[lsu_addrcheck.scala 91:64] + wire _T_151 = start_addr_in_dccm_region_d & _T_150; // @[lsu_addrcheck.scala 91:62] + wire _T_152 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[lsu_addrcheck.scala 93:57] + wire _T_153 = ~_T_152; // @[lsu_addrcheck.scala 93:36] + wire _T_154 = end_addr_in_dccm_region_d & _T_153; // @[lsu_addrcheck.scala 93:34] + wire _T_155 = _T_151 | _T_154; // @[lsu_addrcheck.scala 91:112] + wire _T_156 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 95:29] + wire _T_157 = _T_155 | _T_156; // @[lsu_addrcheck.scala 93:85] + wire _T_158 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 97:29] + wire unmapped_access_fault_d = _T_157 | _T_158; // @[lsu_addrcheck.scala 95:85] + wire _T_160 = ~start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 99:33] + wire _T_161 = ~non_dccm_access_ok; // @[lsu_addrcheck.scala 99:64] + wire mpu_access_fault_d = _T_160 & _T_161; // @[lsu_addrcheck.scala 99:62] + wire _T_163 = unmapped_access_fault_d | mpu_access_fault_d; // @[lsu_addrcheck.scala 111:49] + wire _T_164 = _T_163 | picm_access_fault_d; // @[lsu_addrcheck.scala 111:70] + wire _T_165 = _T_164 | regpred_access_fault_d; // @[lsu_addrcheck.scala 111:92] + wire _T_166 = _T_165 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 111:118] + wire _T_167 = ~io_lsu_pkt_d_bits_dma; // @[lsu_addrcheck.scala 111:141] + wire [3:0] _T_173 = picm_access_fault_d ? 4'h6 : 4'h0; // @[lsu_addrcheck.scala 112:164] + wire [3:0] _T_174 = regpred_access_fault_d ? 4'h5 : _T_173; // @[lsu_addrcheck.scala 112:120] + wire [3:0] _T_175 = mpu_access_fault_d ? 4'h3 : _T_174; // @[lsu_addrcheck.scala 112:80] + wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_175; // @[lsu_addrcheck.scala 112:35] + wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[lsu_addrcheck.scala 113:61] + wire _T_178 = ~is_aligned_d; // @[lsu_addrcheck.scala 114:59] + wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_178; // @[lsu_addrcheck.scala 114:57] + wire _T_179 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[lsu_addrcheck.scala 115:90] + wire _T_180 = regcross_misaligned_fault_d | _T_179; // @[lsu_addrcheck.scala 115:57] + wire _T_181 = _T_180 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 115:113] + wire [3:0] _T_185 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[lsu_addrcheck.scala 116:80] + wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_185; // @[lsu_addrcheck.scala 116:39] + wire _T_190 = ~start_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:66] + wire _T_191 = start_addr_in_dccm_region_d & _T_190; // @[lsu_addrcheck.scala 118:64] + wire _T_192 = ~end_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:120] + wire _T_193 = end_addr_in_dccm_region_d & _T_192; // @[lsu_addrcheck.scala 118:118] + wire _T_194 = _T_191 | _T_193; // @[lsu_addrcheck.scala 118:88] + wire _T_195 = _T_194 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 118:142] + wire _T_197 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 119:66] + wire _T_198 = ~_T_197; // @[lsu_addrcheck.scala 119:36] + wire _T_199 = _T_198 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 119:95] + reg _T_201; // @[lsu_addrcheck.scala 121:60] + assign io_is_sideeffects_m = _T_201; // @[lsu_addrcheck.scala 121:50] + assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 56:32] + assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 57:32] + assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[lsu_addrcheck.scala 59:30] + assign io_access_fault_d = _T_166 & _T_167; // @[lsu_addrcheck.scala 111:21] + assign io_misaligned_fault_d = _T_181 & _T_167; // @[lsu_addrcheck.scala 115:25] + assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[lsu_addrcheck.scala 117:21] + assign io_fir_dccm_access_error_d = _T_195 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 118:31] + assign io_fir_nondccm_access_error_d = _T_199 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 119:33] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_201 = _RAND_0[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_201 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_201 <= 1'h0; + end else begin + _T_201 <= _T_32 & _T_33; + end + end +endmodule +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module lsu_lsc_ctl( + input clock, + input reset, + input io_clk_override, + input io_lsu_c1_m_clk, + input io_lsu_c1_r_clk, + input io_lsu_c2_m_clk, + input io_lsu_c2_r_clk, + input io_lsu_store_c1_m_clk, + input [31:0] io_lsu_ld_data_r, + input [31:0] io_lsu_ld_data_corr_r, + input io_lsu_single_ecc_error_r, + input io_lsu_double_ecc_error_r, + input [31:0] io_lsu_ld_data_m, + input io_lsu_single_ecc_error_m, + input io_lsu_double_ecc_error_m, + input io_flush_m_up, + input io_flush_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [31:0] io_lsu_exu_exu_lsu_rs1_d, + input [31:0] io_lsu_exu_exu_lsu_rs2_d, + output [31:0] io_lsu_exu_lsu_result_m, + input io_lsu_p_valid, + input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_stack, + input io_lsu_p_bits_by, + input io_lsu_p_bits_half, + input io_lsu_p_bits_word, + input io_lsu_p_bits_dword, + input io_lsu_p_bits_load, + input io_lsu_p_bits_store, + input io_lsu_p_bits_unsign, + input io_lsu_p_bits_dma, + input io_lsu_p_bits_store_data_bypass_d, + input io_lsu_p_bits_load_ldst_bypass_d, + input io_lsu_p_bits_store_data_bypass_m, + input io_dec_lsu_valid_raw_d, + input [11:0] io_dec_lsu_offset_d, + input [31:0] io_picm_mask_data_m, + input [31:0] io_bus_read_data_m, + output [31:0] io_lsu_result_corr_r, + output [31:0] io_lsu_addr_d, + output [31:0] io_lsu_addr_m, + output [31:0] io_lsu_addr_r, + output [31:0] io_end_addr_d, + output [31:0] io_end_addr_m, + output [31:0] io_end_addr_r, + output [31:0] io_store_data_m, + input [31:0] io_dec_tlu_mrac_ff, + output io_lsu_exc_m, + output io_is_sideeffects_m, + output io_lsu_commit_r, + output io_lsu_single_ecc_error_incr, + output io_lsu_error_pkt_r_valid, + output io_lsu_error_pkt_r_bits_single_ecc_error, + output io_lsu_error_pkt_r_bits_inst_type, + output io_lsu_error_pkt_r_bits_exc_type, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, + output [30:0] io_lsu_fir_addr, + output [1:0] io_lsu_fir_error, + output io_addr_in_dccm_d, + output io_addr_in_dccm_m, + output io_addr_in_dccm_r, + output io_addr_in_pic_d, + output io_addr_in_pic_m, + output io_addr_in_pic_r, + output io_addr_external_m, + input io_dma_lsc_ctl_dma_dccm_req, + input [31:0] io_dma_lsc_ctl_dma_mem_addr, + input [2:0] io_dma_lsc_ctl_dma_mem_sz, + input io_dma_lsc_ctl_dma_mem_write, + input [63:0] io_dma_lsc_ctl_dma_mem_wdata, + output io_lsu_pkt_d_valid, + output io_lsu_pkt_d_bits_fast_int, + output io_lsu_pkt_d_bits_stack, + output io_lsu_pkt_d_bits_by, + output io_lsu_pkt_d_bits_half, + output io_lsu_pkt_d_bits_word, + output io_lsu_pkt_d_bits_dword, + output io_lsu_pkt_d_bits_load, + output io_lsu_pkt_d_bits_store, + output io_lsu_pkt_d_bits_unsign, + output io_lsu_pkt_d_bits_dma, + output io_lsu_pkt_d_bits_store_data_bypass_d, + output io_lsu_pkt_d_bits_load_ldst_bypass_d, + output io_lsu_pkt_d_bits_store_data_bypass_m, + output io_lsu_pkt_m_valid, + output io_lsu_pkt_m_bits_fast_int, + output io_lsu_pkt_m_bits_stack, + output io_lsu_pkt_m_bits_by, + output io_lsu_pkt_m_bits_half, + output io_lsu_pkt_m_bits_word, + output io_lsu_pkt_m_bits_dword, + output io_lsu_pkt_m_bits_load, + output io_lsu_pkt_m_bits_store, + output io_lsu_pkt_m_bits_unsign, + output io_lsu_pkt_m_bits_dma, + output io_lsu_pkt_m_bits_store_data_bypass_d, + output io_lsu_pkt_m_bits_load_ldst_bypass_d, + output io_lsu_pkt_m_bits_store_data_bypass_m, + output io_lsu_pkt_r_valid, + output io_lsu_pkt_r_bits_fast_int, + output io_lsu_pkt_r_bits_stack, + output io_lsu_pkt_r_bits_by, + output io_lsu_pkt_r_bits_half, + output io_lsu_pkt_r_bits_word, + output io_lsu_pkt_r_bits_dword, + output io_lsu_pkt_r_bits_load, + output io_lsu_pkt_r_bits_store, + output io_lsu_pkt_r_bits_unsign, + output io_lsu_pkt_r_bits_dma, + output io_lsu_pkt_r_bits_store_data_bypass_d, + output io_lsu_pkt_r_bits_load_ldst_bypass_d, + output io_lsu_pkt_r_bits_store_data_bypass_m, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; +`endif // RANDOMIZE_REG_INIT + wire addrcheck_reset; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_start_addr_d; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_end_addr_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 117:25] + wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 117:25] + wire [3:0] addrcheck_io_rs1_region_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_addr_external_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_access_fault_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_misaligned_fault_d; // @[lsu_lsc_ctl.scala 117:25] + wire [3:0] addrcheck_io_exc_mscause_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_fir_dccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25] + wire addrcheck_io_fir_nondccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25] + wire rvclkhdr_io_clk; // @[lib.scala 417:23] + wire rvclkhdr_io_en; // @[lib.scala 417:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_lsu_exu_exu_lsu_rs1_d : io_dma_lsc_ctl_dma_mem_addr; // @[lsu_lsc_ctl.scala 99:28] + wire [11:0] _T_4 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] + wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_4; // @[lsu_lsc_ctl.scala 100:51] + wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_exu_lsu_result_m : lsu_rs1_d; // @[lsu_lsc_ctl.scala 103:28] + wire [12:0] _T_7 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58] + wire [12:0] _T_9 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _T_11 = _T_7 + _T_9; // @[lib.scala 92:39] + wire _T_14 = lsu_offset_d[11] ^ _T_11[12]; // @[lib.scala 93:46] + wire _T_15 = ~_T_14; // @[lib.scala 93:33] + wire [19:0] _T_17 = _T_15 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_19 = _T_17 & rs1_d[31:12]; // @[lib.scala 93:58] + wire _T_21 = ~lsu_offset_d[11]; // @[lib.scala 94:18] + wire _T_23 = _T_21 & _T_11[12]; // @[lib.scala 94:30] + wire [19:0] _T_25 = _T_23 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_28 = rs1_d[31:12] + 20'h1; // @[lib.scala 94:54] + wire [19:0] _T_29 = _T_25 & _T_28; // @[lib.scala 94:41] + wire [19:0] _T_30 = _T_19 | _T_29; // @[lib.scala 93:72] + wire _T_33 = ~_T_11[12]; // @[lib.scala 95:31] + wire _T_34 = lsu_offset_d[11] & _T_33; // @[lib.scala 95:29] + wire [19:0] _T_36 = _T_34 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_39 = rs1_d[31:12] - 20'h1; // @[lib.scala 95:54] + wire [19:0] _T_40 = _T_36 & _T_39; // @[lib.scala 95:41] + wire [19:0] _T_41 = _T_30 | _T_40; // @[lib.scala 94:61] + wire [2:0] _T_44 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_45 = _T_44 & 3'h1; // @[lsu_lsc_ctl.scala 108:58] + wire [2:0] _T_47 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_48 = _T_47 & 3'h3; // @[lsu_lsc_ctl.scala 109:40] + wire [2:0] _T_49 = _T_45 | _T_48; // @[lsu_lsc_ctl.scala 108:70] + wire [2:0] _T_51 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] addr_offset_d = _T_49 | _T_51; // @[lsu_lsc_ctl.scala 109:52] + wire [12:0] _T_55 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58] + wire [11:0] _T_58 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _GEN_9 = {{1'd0}, _T_58}; // @[lsu_lsc_ctl.scala 112:60] + wire [12:0] end_addr_offset_d = _T_55 + _GEN_9; // @[lsu_lsc_ctl.scala 112:60] + wire [18:0] _T_63 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_65 = {_T_63,end_addr_offset_d}; // @[Cat.scala 29:58] + reg access_fault_m; // @[lsu_lsc_ctl.scala 148:75] + reg misaligned_fault_m; // @[lsu_lsc_ctl.scala 149:75] + reg [3:0] exc_mscause_m; // @[lsu_lsc_ctl.scala 150:75] + reg fir_dccm_access_error_m; // @[lsu_lsc_ctl.scala 151:75] + reg fir_nondccm_access_error_m; // @[lsu_lsc_ctl.scala 152:75] + wire _T_70 = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:34] + wire _T_71 = ~io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 155:64] + wire _T_72 = io_lsu_single_ecc_error_r & _T_71; // @[lsu_lsc_ctl.scala 155:62] + wire _T_73 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 155:111] + wire _T_74 = _T_72 & _T_73; // @[lsu_lsc_ctl.scala 155:92] + wire _T_77 = _T_70 | io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 177:67] + wire _T_78 = _T_77 & io_lsu_pkt_m_valid; // @[lsu_lsc_ctl.scala 177:96] + wire _T_79 = ~io_lsu_pkt_m_bits_dma; // @[lsu_lsc_ctl.scala 177:119] + wire _T_80 = _T_78 & _T_79; // @[lsu_lsc_ctl.scala 177:117] + wire _T_81 = ~io_lsu_pkt_m_bits_fast_int; // @[lsu_lsc_ctl.scala 177:144] + wire _T_82 = _T_80 & _T_81; // @[lsu_lsc_ctl.scala 177:142] + wire _T_83 = ~io_flush_m_up; // @[lsu_lsc_ctl.scala 177:174] + wire lsu_error_pkt_m_valid = _T_82 & _T_83; // @[lsu_lsc_ctl.scala 177:172] + wire _T_85 = ~lsu_error_pkt_m_valid; // @[lsu_lsc_ctl.scala 178:75] + wire _T_86 = io_lsu_single_ecc_error_m & _T_85; // @[lsu_lsc_ctl.scala 178:73] + wire lsu_error_pkt_m_bits_single_ecc_error = _T_86 & _T_79; // @[lsu_lsc_ctl.scala 178:99] + wire lsu_error_pkt_m_bits_exc_type = ~misaligned_fault_m; // @[lsu_lsc_ctl.scala 180:46] + wire _T_91 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[lsu_lsc_ctl.scala 181:78] + wire _T_92 = ~access_fault_m; // @[lsu_lsc_ctl.scala 181:102] + wire _T_93 = _T_91 & _T_92; // @[lsu_lsc_ctl.scala 181:100] + wire _T_100 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 183:166] + wire _T_105 = lsu_error_pkt_m_valid | lsu_error_pkt_m_bits_single_ecc_error; // @[lsu_lsc_ctl.scala 184:73] + wire _T_106 = _T_105 | io_clk_override; // @[lsu_lsc_ctl.scala 184:113] + reg _T_110_bits_inst_type; // @[Reg.scala 27:20] + reg _T_110_bits_exc_type; // @[Reg.scala 27:20] + reg [3:0] _T_110_bits_mscause; // @[Reg.scala 27:20] + reg [31:0] _T_110_bits_addr; // @[Reg.scala 27:20] + reg _T_111; // @[lsu_lsc_ctl.scala 185:83] + reg _T_112; // @[lsu_lsc_ctl.scala 186:67] + reg [1:0] _T_113; // @[lsu_lsc_ctl.scala 187:75] + wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 195:30] + wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 196:62] + wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 197:62] + wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 198:62] + wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 199:62] + wire _T_125 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 212:64] + wire _T_126 = io_flush_m_up & _T_125; // @[lsu_lsc_ctl.scala 212:61] + wire _T_127 = ~_T_126; // @[lsu_lsc_ctl.scala 212:45] + wire _T_128 = io_lsu_p_valid & _T_127; // @[lsu_lsc_ctl.scala 212:43] + wire _T_130 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 213:68] + wire _T_131 = io_flush_m_up & _T_130; // @[lsu_lsc_ctl.scala 213:65] + wire _T_132 = ~_T_131; // @[lsu_lsc_ctl.scala 213:49] + wire _T_135 = io_flush_m_up & _T_79; // @[lsu_lsc_ctl.scala 214:65] + wire _T_136 = ~_T_135; // @[lsu_lsc_ctl.scala 214:49] + reg _T_139_bits_fast_int; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_stack; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_by; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_half; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_word; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_dword; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_load; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_store; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_unsign; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_dma; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 216:65] + reg _T_139_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:65] + reg _T_141_bits_fast_int; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_stack; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_by; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_half; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_word; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_dword; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_load; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_store; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_unsign; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_dma; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:65] + reg _T_142; // @[lsu_lsc_ctl.scala 218:65] + reg _T_143; // @[lsu_lsc_ctl.scala 219:65] + wire [5:0] _T_146 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] + wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_146; // @[lsu_lsc_ctl.scala 221:66] + reg _T_154; // @[lsu_lsc_ctl.scala 225:47] + reg _T_156; // @[lsu_lsc_ctl.scala 225:109] + wire int_ = _T_154 != _T_156; // @[lsu_lsc_ctl.scala 225:71] + reg _T_158; // @[lsu_lsc_ctl.scala 226:48] + reg _T_160; // @[lsu_lsc_ctl.scala 226:110] + wire int1 = _T_158 != _T_160; // @[lsu_lsc_ctl.scala 226:72] + reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 229:72] + reg [31:0] _T_161; // @[lsu_lsc_ctl.scala 230:62] + reg [31:0] _T_162; // @[lsu_lsc_ctl.scala 231:62] + reg [28:0] end_addr_pre_m; // @[Reg.scala 27:20] + wire [28:0] _T_164 = int_ ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 232:27] + reg [2:0] _T_166; // @[lsu_lsc_ctl.scala 232:103] + reg [28:0] end_addr_pre_r; // @[Reg.scala 27:20] + wire [28:0] _T_169 = int1 ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 233:27] + reg [2:0] _T_171; // @[lsu_lsc_ctl.scala 233:104] + wire _T_174 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 234:69] + wire _T_175 = _T_174 | io_clk_override; // @[lsu_lsc_ctl.scala 234:87] + wire _T_179 = io_lsu_pkt_m_valid & int_; // @[lsu_lsc_ctl.scala 235:69] + wire _T_180 = _T_179 | io_clk_override; // @[lsu_lsc_ctl.scala 235:76] + reg _T_183; // @[lsu_lsc_ctl.scala 236:62] + reg _T_184; // @[lsu_lsc_ctl.scala 237:62] + reg _T_185; // @[lsu_lsc_ctl.scala 238:62] + reg _T_186; // @[lsu_lsc_ctl.scala 239:62] + reg _T_187; // @[lsu_lsc_ctl.scala 240:62] + reg addr_external_r; // @[lsu_lsc_ctl.scala 241:66] + wire _T_188 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 242:77] + reg [31:0] bus_read_data_r; // @[Reg.scala 27:20] + wire _T_191 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 249:68] + wire _T_192 = io_lsu_pkt_r_valid & _T_191; // @[lsu_lsc_ctl.scala 249:41] + wire _T_193 = ~io_flush_r; // @[lsu_lsc_ctl.scala 249:96] + wire _T_194 = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 249:94] + wire _T_195 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 249:110] + wire _T_198 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 250:69] + wire [31:0] _T_200 = _T_198 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_201 = io_picm_mask_data_m | _T_200; // @[lsu_lsc_ctl.scala 250:59] + wire [31:0] _T_203 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_exu_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 250:94] + wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 271:33] + wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 272:33] + wire _T_208 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 273:74] + wire [31:0] _T_210 = _T_208 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_213 = _T_210 & _T_212; // @[lsu_lsc_ctl.scala 273:102] + wire _T_214 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 274:43] + wire [31:0] _T_216 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_218 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_219 = _T_216 & _T_218; // @[lsu_lsc_ctl.scala 274:71] + wire [31:0] _T_220 = _T_213 | _T_219; // @[lsu_lsc_ctl.scala 273:141] + wire _T_221 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 275:17] + wire _T_222 = _T_221 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 275:43] + wire [31:0] _T_224 = _T_222 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_227 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = {_T_227,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_230 = _T_224 & _T_229; // @[lsu_lsc_ctl.scala 275:71] + wire [31:0] _T_231 = _T_220 | _T_230; // @[lsu_lsc_ctl.scala 274:114] + wire _T_233 = _T_221 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 276:43] + wire [31:0] _T_235 = _T_233 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_238 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_240 = {_T_238,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_241 = _T_235 & _T_240; // @[lsu_lsc_ctl.scala 276:71] + wire [31:0] _T_242 = _T_231 | _T_241; // @[lsu_lsc_ctl.scala 275:134] + wire [31:0] _T_244 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_244 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 277:43] + wire _T_248 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 278:66] + wire [31:0] _T_250 = _T_248 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_252 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_253 = _T_250 & _T_252; // @[lsu_lsc_ctl.scala 278:94] + wire _T_254 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 279:43] + wire [31:0] _T_256 = _T_254 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_258 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_259 = _T_256 & _T_258; // @[lsu_lsc_ctl.scala 279:71] + wire [31:0] _T_260 = _T_253 | _T_259; // @[lsu_lsc_ctl.scala 278:138] + wire _T_261 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 280:17] + wire _T_262 = _T_261 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 280:43] + wire [31:0] _T_264 = _T_262 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_267 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_269 = {_T_267,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_270 = _T_264 & _T_269; // @[lsu_lsc_ctl.scala 280:71] + wire [31:0] _T_271 = _T_260 | _T_270; // @[lsu_lsc_ctl.scala 279:119] + wire _T_273 = _T_261 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 281:43] + wire [31:0] _T_275 = _T_273 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_278 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = {_T_278,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_281 = _T_275 & _T_280; // @[lsu_lsc_ctl.scala 281:71] + wire [31:0] _T_282 = _T_271 | _T_281; // @[lsu_lsc_ctl.scala 280:144] + wire [31:0] _T_284 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_286 = _T_284 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 282:43] + lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 117:25] + .reset(addrcheck_reset), + .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk), + .io_start_addr_d(addrcheck_io_start_addr_d), + .io_end_addr_d(addrcheck_io_end_addr_d), + .io_lsu_pkt_d_valid(addrcheck_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_fast_int(addrcheck_io_lsu_pkt_d_bits_fast_int), + .io_lsu_pkt_d_bits_by(addrcheck_io_lsu_pkt_d_bits_by), + .io_lsu_pkt_d_bits_half(addrcheck_io_lsu_pkt_d_bits_half), + .io_lsu_pkt_d_bits_word(addrcheck_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_load(addrcheck_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(addrcheck_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_dma(addrcheck_io_lsu_pkt_d_bits_dma), + .io_dec_tlu_mrac_ff(addrcheck_io_dec_tlu_mrac_ff), + .io_rs1_region_d(addrcheck_io_rs1_region_d), + .io_is_sideeffects_m(addrcheck_io_is_sideeffects_m), + .io_addr_in_dccm_d(addrcheck_io_addr_in_dccm_d), + .io_addr_in_pic_d(addrcheck_io_addr_in_pic_d), + .io_addr_external_d(addrcheck_io_addr_external_d), + .io_access_fault_d(addrcheck_io_access_fault_d), + .io_misaligned_fault_d(addrcheck_io_misaligned_fault_d), + .io_exc_mscause_d(addrcheck_io_exc_mscause_d), + .io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d), + .io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d) + ); + rvclkhdr rvclkhdr ( // @[lib.scala 417:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + assign io_lsu_exu_lsu_result_m = _T_242 | _T_246; // @[lsu_lsc_ctl.scala 273:35] + assign io_lsu_result_corr_r = _T_282 | _T_286; // @[lsu_lsc_ctl.scala 278:27] + assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 247:28] + assign io_lsu_addr_m = _T_161; // @[lsu_lsc_ctl.scala 230:24] + assign io_lsu_addr_r = _T_162; // @[lsu_lsc_ctl.scala 231:24] + assign io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 114:24] + assign io_end_addr_m = {_T_164,_T_166}; // @[lsu_lsc_ctl.scala 232:17] + assign io_end_addr_r = {_T_169,_T_171}; // @[lsu_lsc_ctl.scala 233:17] + assign io_store_data_m = _T_201 & _T_203; // @[lsu_lsc_ctl.scala 250:29] + assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:16] + assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 127:42] + assign io_lsu_commit_r = _T_194 & _T_195; // @[lsu_lsc_ctl.scala 249:19] + assign io_lsu_single_ecc_error_incr = _T_74 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 155:32] + assign io_lsu_error_pkt_r_valid = _T_112; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 186:30] + assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_111; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 185:46] + assign io_lsu_error_pkt_r_bits_inst_type = _T_110_bits_inst_type; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_exc_type = _T_110_bits_exc_type; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_mscause = _T_110_bits_mscause; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_error_pkt_r_bits_addr = _T_110_bits_addr; // @[lsu_lsc_ctl.scala 184:24] + assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 245:28] + assign io_lsu_fir_error = _T_113; // @[lsu_lsc_ctl.scala 187:38] + assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 128:42] + assign io_addr_in_dccm_m = _T_183; // @[lsu_lsc_ctl.scala 236:24] + assign io_addr_in_dccm_r = _T_184; // @[lsu_lsc_ctl.scala 237:24] + assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 129:42] + assign io_addr_in_pic_m = _T_185; // @[lsu_lsc_ctl.scala 238:24] + assign io_addr_in_pic_r = _T_186; // @[lsu_lsc_ctl.scala 239:24] + assign io_addr_external_m = _T_187; // @[lsu_lsc_ctl.scala 240:24] + assign io_lsu_pkt_d_valid = _T_128 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24] + assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_stack = io_dec_lsu_valid_raw_d & io_lsu_p_bits_stack; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_m_valid = _T_142; // @[lsu_lsc_ctl.scala 216:28 lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_m_bits_fast_int = _T_139_bits_fast_int; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_stack = _T_139_bits_stack; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_by = _T_139_bits_by; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_half = _T_139_bits_half; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_word = _T_139_bits_word; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_dword = _T_139_bits_dword; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_load = _T_139_bits_load; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store = _T_139_bits_store; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_unsign = _T_139_bits_unsign; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_dma = _T_139_bits_dma; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store_data_bypass_d = _T_139_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_load_ldst_bypass_d = _T_139_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_139_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_valid = _T_143; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28] + assign io_lsu_pkt_r_bits_fast_int = _T_141_bits_fast_int; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_stack = _T_141_bits_stack; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_by = _T_141_bits_by; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_half = _T_141_bits_half; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_word = _T_141_bits_word; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_dword = _T_141_bits_dword; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_load = _T_141_bits_load; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store = _T_141_bits_store; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_unsign = _T_141_bits_unsign; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_dma = _T_141_bits_dma; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store_data_bypass_d = _T_141_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_load_ldst_bypass_d = _T_141_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store_data_bypass_m = _T_141_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:28] + assign addrcheck_reset = reset; + assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_start_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 121:42] + assign addrcheck_io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 122:42] + assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 124:42] + assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[lsu_lsc_ctl.scala 125:42] + assign rvclkhdr_io_clk = clock; // @[lib.scala 419:18] + assign rvclkhdr_io_en = _T_105 | io_clk_override; // @[lib.scala 420:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_174 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_179 | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + access_fault_m = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + misaligned_fault_m = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + exc_mscause_m = _RAND_2[3:0]; + _RAND_3 = {1{`RANDOM}}; + fir_dccm_access_error_m = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + fir_nondccm_access_error_m = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_110_bits_inst_type = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_110_bits_exc_type = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_110_bits_mscause = _RAND_7[3:0]; + _RAND_8 = {1{`RANDOM}}; + _T_110_bits_addr = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + _T_111 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + _T_112 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_113 = _RAND_11[1:0]; + _RAND_12 = {1{`RANDOM}}; + _T_139_bits_fast_int = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + _T_139_bits_stack = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + _T_139_bits_by = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + _T_139_bits_half = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + _T_139_bits_word = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + _T_139_bits_dword = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + _T_139_bits_load = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + _T_139_bits_store = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + _T_139_bits_unsign = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + _T_139_bits_dma = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + _T_139_bits_store_data_bypass_d = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + _T_139_bits_load_ldst_bypass_d = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + _T_139_bits_store_data_bypass_m = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + _T_141_bits_fast_int = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + _T_141_bits_stack = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + _T_141_bits_by = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + _T_141_bits_half = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + _T_141_bits_word = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + _T_141_bits_dword = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + _T_141_bits_load = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + _T_141_bits_store = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + _T_141_bits_unsign = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + _T_141_bits_dma = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + _T_141_bits_store_data_bypass_d = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + _T_141_bits_load_ldst_bypass_d = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + _T_141_bits_store_data_bypass_m = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + _T_142 = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + _T_143 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + _T_154 = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + _T_156 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + _T_158 = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + _T_160 = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + store_data_pre_m = _RAND_44[31:0]; + _RAND_45 = {1{`RANDOM}}; + _T_161 = _RAND_45[31:0]; + _RAND_46 = {1{`RANDOM}}; + _T_162 = _RAND_46[31:0]; + _RAND_47 = {1{`RANDOM}}; + end_addr_pre_m = _RAND_47[28:0]; + _RAND_48 = {1{`RANDOM}}; + _T_166 = _RAND_48[2:0]; + _RAND_49 = {1{`RANDOM}}; + end_addr_pre_r = _RAND_49[28:0]; + _RAND_50 = {1{`RANDOM}}; + _T_171 = _RAND_50[2:0]; + _RAND_51 = {1{`RANDOM}}; + _T_183 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_184 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + _T_185 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + _T_186 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + _T_187 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + addr_external_r = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + bus_read_data_r = _RAND_57[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + access_fault_m = 1'h0; + end + if (reset) begin + misaligned_fault_m = 1'h0; + end + if (reset) begin + exc_mscause_m = 4'h0; + end + if (reset) begin + fir_dccm_access_error_m = 1'h0; + end + if (reset) begin + fir_nondccm_access_error_m = 1'h0; + end + if (reset) begin + _T_110_bits_inst_type = 1'h0; + end + if (reset) begin + _T_110_bits_exc_type = 1'h0; + end + if (reset) begin + _T_110_bits_mscause = 4'h0; + end + if (reset) begin + _T_110_bits_addr = 32'h0; + end + if (reset) begin + _T_111 = 1'h0; + end + if (reset) begin + _T_112 = 1'h0; + end + if (reset) begin + _T_113 = 2'h0; + end + if (reset) begin + _T_139_bits_fast_int = 1'h0; + end + if (reset) begin + _T_139_bits_stack = 1'h0; + end + if (reset) begin + _T_139_bits_by = 1'h0; + end + if (reset) begin + _T_139_bits_half = 1'h0; + end + if (reset) begin + _T_139_bits_word = 1'h0; + end + if (reset) begin + _T_139_bits_dword = 1'h0; + end + if (reset) begin + _T_139_bits_load = 1'h0; + end + if (reset) begin + _T_139_bits_store = 1'h0; + end + if (reset) begin + _T_139_bits_unsign = 1'h0; + end + if (reset) begin + _T_139_bits_dma = 1'h0; + end + if (reset) begin + _T_139_bits_store_data_bypass_d = 1'h0; + end + if (reset) begin + _T_139_bits_load_ldst_bypass_d = 1'h0; + end + if (reset) begin + _T_139_bits_store_data_bypass_m = 1'h0; + end + if (reset) begin + _T_141_bits_fast_int = 1'h0; + end + if (reset) begin + _T_141_bits_stack = 1'h0; + end + if (reset) begin + _T_141_bits_by = 1'h0; + end + if (reset) begin + _T_141_bits_half = 1'h0; + end + if (reset) begin + _T_141_bits_word = 1'h0; + end + if (reset) begin + _T_141_bits_dword = 1'h0; + end + if (reset) begin + _T_141_bits_load = 1'h0; + end + if (reset) begin + _T_141_bits_store = 1'h0; + end + if (reset) begin + _T_141_bits_unsign = 1'h0; + end + if (reset) begin + _T_141_bits_dma = 1'h0; + end + if (reset) begin + _T_141_bits_store_data_bypass_d = 1'h0; + end + if (reset) begin + _T_141_bits_load_ldst_bypass_d = 1'h0; + end + if (reset) begin + _T_141_bits_store_data_bypass_m = 1'h0; + end + if (reset) begin + _T_142 = 1'h0; + end + if (reset) begin + _T_143 = 1'h0; + end + if (reset) begin + _T_154 = 1'h0; + end + if (reset) begin + _T_156 = 1'h0; + end + if (reset) begin + _T_158 = 1'h0; + end + if (reset) begin + _T_160 = 1'h0; + end + if (reset) begin + store_data_pre_m = 32'h0; + end + if (reset) begin + _T_161 = 32'h0; + end + if (reset) begin + _T_162 = 32'h0; + end + if (reset) begin + end_addr_pre_m = 29'h0; + end + if (reset) begin + _T_166 = 3'h0; + end + if (reset) begin + end_addr_pre_r = 29'h0; + end + if (reset) begin + _T_171 = 3'h0; + end + if (reset) begin + _T_183 = 1'h0; + end + if (reset) begin + _T_184 = 1'h0; + end + if (reset) begin + _T_185 = 1'h0; + end + if (reset) begin + _T_186 = 1'h0; + end + if (reset) begin + _T_187 = 1'h0; + end + if (reset) begin + addr_external_r = 1'h0; + end + if (reset) begin + bus_read_data_r = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + access_fault_m <= 1'h0; + end else begin + access_fault_m <= addrcheck_io_access_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + misaligned_fault_m <= 1'h0; + end else begin + misaligned_fault_m <= addrcheck_io_misaligned_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + exc_mscause_m <= 4'h0; + end else begin + exc_mscause_m <= addrcheck_io_exc_mscause_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_dccm_access_error_m <= 1'h0; + end else begin + fir_dccm_access_error_m <= addrcheck_io_fir_dccm_access_error_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_nondccm_access_error_m <= 1'h0; + end else begin + fir_nondccm_access_error_m <= addrcheck_io_fir_nondccm_access_error_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_inst_type <= 1'h0; + end else if (_T_106) begin + _T_110_bits_inst_type <= io_lsu_pkt_m_bits_store; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_exc_type <= 1'h0; + end else if (_T_106) begin + _T_110_bits_exc_type <= lsu_error_pkt_m_bits_exc_type; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_mscause <= 4'h0; + end else if (_T_106) begin + if (_T_93) begin + _T_110_bits_mscause <= 4'h1; + end else begin + _T_110_bits_mscause <= exc_mscause_m; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_110_bits_addr <= 32'h0; + end else if (_T_106) begin + _T_110_bits_addr <= io_lsu_addr_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_111 <= 1'h0; + end else begin + _T_111 <= _T_86 & _T_79; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_112 <= 1'h0; + end else begin + _T_112 <= _T_82 & _T_83; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_113 <= 2'h0; + end else if (fir_nondccm_access_error_m) begin + _T_113 <= 2'h3; + end else if (fir_dccm_access_error_m) begin + _T_113 <= 2'h2; + end else if (_T_100) begin + _T_113 <= 2'h1; + end else begin + _T_113 <= 2'h0; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_fast_int <= 1'h0; + end else begin + _T_139_bits_fast_int <= io_lsu_pkt_d_bits_fast_int; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_stack <= 1'h0; + end else begin + _T_139_bits_stack <= io_lsu_pkt_d_bits_stack; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_by <= 1'h0; + end else begin + _T_139_bits_by <= io_lsu_pkt_d_bits_by; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_half <= 1'h0; + end else begin + _T_139_bits_half <= io_lsu_pkt_d_bits_half; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_word <= 1'h0; + end else begin + _T_139_bits_word <= io_lsu_pkt_d_bits_word; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_dword <= 1'h0; + end else begin + _T_139_bits_dword <= io_lsu_pkt_d_bits_dword; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_load <= 1'h0; + end else begin + _T_139_bits_load <= io_lsu_pkt_d_bits_load; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_store <= 1'h0; + end else begin + _T_139_bits_store <= io_lsu_pkt_d_bits_store; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_unsign <= 1'h0; + end else begin + _T_139_bits_unsign <= io_lsu_pkt_d_bits_unsign; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_dma <= 1'h0; + end else begin + _T_139_bits_dma <= io_lsu_pkt_d_bits_dma; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_store_data_bypass_d <= 1'h0; + end else begin + _T_139_bits_store_data_bypass_d <= io_lsu_pkt_d_bits_store_data_bypass_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_load_ldst_bypass_d <= 1'h0; + end else begin + _T_139_bits_load_ldst_bypass_d <= io_lsu_pkt_d_bits_load_ldst_bypass_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_139_bits_store_data_bypass_m <= 1'h0; + end else begin + _T_139_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_fast_int <= 1'h0; + end else begin + _T_141_bits_fast_int <= io_lsu_pkt_m_bits_fast_int; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_stack <= 1'h0; + end else begin + _T_141_bits_stack <= io_lsu_pkt_m_bits_stack; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_by <= 1'h0; + end else begin + _T_141_bits_by <= io_lsu_pkt_m_bits_by; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_half <= 1'h0; + end else begin + _T_141_bits_half <= io_lsu_pkt_m_bits_half; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_word <= 1'h0; + end else begin + _T_141_bits_word <= io_lsu_pkt_m_bits_word; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_dword <= 1'h0; + end else begin + _T_141_bits_dword <= io_lsu_pkt_m_bits_dword; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_load <= 1'h0; + end else begin + _T_141_bits_load <= io_lsu_pkt_m_bits_load; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_store <= 1'h0; + end else begin + _T_141_bits_store <= io_lsu_pkt_m_bits_store; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_unsign <= 1'h0; + end else begin + _T_141_bits_unsign <= io_lsu_pkt_m_bits_unsign; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_dma <= 1'h0; + end else begin + _T_141_bits_dma <= io_lsu_pkt_m_bits_dma; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_store_data_bypass_d <= 1'h0; + end else begin + _T_141_bits_store_data_bypass_d <= io_lsu_pkt_m_bits_store_data_bypass_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_load_ldst_bypass_d <= 1'h0; + end else begin + _T_141_bits_load_ldst_bypass_d <= io_lsu_pkt_m_bits_load_ldst_bypass_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_141_bits_store_data_bypass_m <= 1'h0; + end else begin + _T_141_bits_store_data_bypass_m <= io_lsu_pkt_m_bits_store_data_bypass_m; + end + end + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_142 <= 1'h0; + end else begin + _T_142 <= io_lsu_pkt_d_valid & _T_132; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_143 <= 1'h0; + end else begin + _T_143 <= io_lsu_pkt_m_valid & _T_136; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_154 <= 1'h0; + end else begin + _T_154 <= io_lsu_addr_d[2]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_156 <= 1'h0; + end else begin + _T_156 <= io_end_addr_d[2]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_158 <= 1'h0; + end else begin + _T_158 <= io_lsu_addr_m[2]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_160 <= 1'h0; + end else begin + _T_160 <= io_end_addr_m[2]; + end + end + always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin + if (reset) begin + store_data_pre_m <= 32'h0; + end else if (io_lsu_pkt_d_bits_store_data_bypass_d) begin + store_data_pre_m <= io_lsu_exu_lsu_result_m; + end else if (io_dma_lsc_ctl_dma_dccm_req) begin + store_data_pre_m <= dma_mem_wdata_shifted[31:0]; + end else begin + store_data_pre_m <= io_lsu_exu_exu_lsu_rs2_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_161 <= 32'h0; + end else begin + _T_161 <= io_lsu_addr_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_162 <= 32'h0; + end else begin + _T_162 <= io_lsu_addr_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + end_addr_pre_m <= 29'h0; + end else if (_T_175) begin + end_addr_pre_m <= io_end_addr_d[31:3]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_166 <= 3'h0; + end else begin + _T_166 <= io_end_addr_d[2:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + end_addr_pre_r <= 29'h0; + end else if (_T_180) begin + end_addr_pre_r <= io_end_addr_m[31:3]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_171 <= 3'h0; + end else begin + _T_171 <= io_end_addr_m[2:0]; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_183 <= 1'h0; + end else begin + _T_183 <= io_addr_in_dccm_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_184 <= 1'h0; + end else begin + _T_184 <= io_addr_in_dccm_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_185 <= 1'h0; + end else begin + _T_185 <= io_addr_in_pic_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_186 <= 1'h0; + end else begin + _T_186 <= io_addr_in_pic_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_187 <= 1'h0; + end else begin + _T_187 <= addrcheck_io_addr_external_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + addr_external_r <= 1'h0; + end else begin + addr_external_r <= io_addr_external_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + bus_read_data_r <= 32'h0; + end else if (_T_188) begin + bus_read_data_r <= io_bus_read_data_m; + end + end +endmodule diff --git a/src/main/scala/exu/exu.scala b/src/main/scala/exu/exu.scala index 79f3afe7..3fa755db 100644 --- a/src/main/scala/exu/exu.scala +++ b/src/main/scala/exu/exu.scala @@ -22,6 +22,7 @@ class exu extends Module with lib with RequireAsyncReset{ //debug val dbg_cmd_wrdata = Input(UInt(32.W)) // Debug data to primary I0 RS1 val dec_csr_rddata_d = Input(UInt(32.W)) + val lsu_nonblock_load_data = Input(UInt(32.W)) //lsu val lsu_exu = Flipped(new lsu_exu()) //ifu_ifc @@ -86,13 +87,13 @@ class exu extends Module with lib with RequireAsyncReset{ io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_result_r, io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1).asBool -> io.lsu_exu.lsu_result_m, io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(2).asBool -> io.dec_exu.decode_exu.exu_i0_result_x, - io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(3).asBool -> io.lsu_exu.lsu_nonblock_load_data + io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(3).asBool -> io.lsu_nonblock_load_data )) val i0_rs2_bypass_data_d = Mux1H(Seq( io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_result_r, io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1).asBool -> io.lsu_exu.lsu_result_m, io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(2).asBool -> io.dec_exu.decode_exu.exu_i0_result_x, - io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(3).asBool -> io.lsu_exu.lsu_nonblock_load_data + io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(3).asBool -> io.lsu_nonblock_load_data )) val i0_rs1_d = Mux1H(Seq( diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala index 1599b4f6..ba5fab16 100644 --- a/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -176,8 +176,7 @@ class lsu_exu extends Bundle{ val exu_lsu_rs1_d = Input(UInt(32.W)) val exu_lsu_rs2_d = Input(UInt(32.W)) val lsu_result_m = Output(UInt(32.W)) - val lsu_nonblock_load_data = Output(UInt(32.W)) - + //val lsu_nonblock_load_data = Output(UInt(32.W)) } class lsu_dec extends Bundle { val tlu_busbuff = new tlu_busbuff diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala index 4963cca9..5ae6353e 100644 --- a/src/main/scala/lsu/lsu.scala +++ b/src/main/scala/lsu/lsu.scala @@ -1,358 +1,359 @@ -//package lsu -// -//import lib._ -//import chisel3._ -//import chisel3.util._ -//import include._ -//import mem._ -// -//class lsu extends Module with RequireAsyncReset with param with lib { -// val io = IO (new Bundle { -// val clk_override = Input(Bool()) -// val lsu_dma = new lsu_dma -// val lsu_pic = new lsu_pic -// val lsu_exu = new lsu_exu -// val lsu_dec = new lsu_dec -// val dccm = Flipped(new mem_lsu) -// val lsu_tlu = new lsu_tlu -// val axi = new axi_channels(LSU_BUS_TAG) -// -// val dec_tlu_flush_lower_r = Input(Bool()) -// val dec_tlu_i0_kill_writeb_r = Input(Bool()) -// val dec_tlu_force_halt = Input(Bool()) -// -// val dec_tlu_core_ecc_disable = Input(Bool()) -// -// val dec_lsu_offset_d = Input(UInt(12.W)) -// val lsu_p = Flipped(Valid(new lsu_pkt_t())) -// val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t())) -// -// val dec_lsu_valid_raw_d = Input(Bool()) -// val dec_tlu_mrac_ff = Input(UInt(32.W)) -// -// //Outputs -// val lsu_result_m = Output(UInt(32.W)) -// val lsu_result_corr_r = Output(UInt(32.W)) -// val lsu_load_stall_any = Output(Bool()) -// val lsu_store_stall_any = Output(Bool()) -// val lsu_fastint_stall_any = Output(Bool()) -// val lsu_idle_any = Output(Bool()) -// val lsu_active = Output(Bool()) -// val lsu_fir_addr = Output(UInt(31.W)) -// val lsu_fir_error = Output(UInt(2.W)) -// val lsu_single_ecc_error_incr = Output(Bool()) -// val lsu_error_pkt_r = Valid(new lsu_error_pkt_t()) -// val lsu_pmu_misaligned_m = Output(Bool()) -// val lsu_trigger_match_m = Output(UInt(4.W)) -// -// val lsu_bus_clk_en = Input(Bool()) -// -// val scan_mode = Input(Bool()) -// val active_clk = Input(Clock()) -// -// }) -// val dma_dccm_wdata = WireInit(0.U(64.W)) -// val dma_dccm_wdata_lo = WireInit(0.U(32.W)) -// val dma_dccm_wdata_hi = WireInit(0.U(32.W)) -// val dma_mem_tag_m = WireInit(0.U(3.W)) -// val lsu_raw_fwd_lo_r = WireInit(0.U(1.W)) -// val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) -// val lsu_busm_clken = WireInit(0.U(1.W)) -// val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W)) -// val lsu_addr_d = WireInit(0.U(32.W)) -// val lsu_addr_m = WireInit(0.U(32.W)) -// val lsu_addr_r = WireInit(0.U(32.W)) -// val end_addr_d = WireInit(0.U(32.W)) -// val end_addr_m = WireInit(0.U(32.W)) -// val end_addr_r = WireInit(0.U(32.W)) -// val lsu_busreq_r = WireInit(Bool(),false.B) -// -// val lsu_lsc_ctl = Module(new lsu_lsc_ctl()) -// io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m -// io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r -// val dccm_ctl = Module(new lsu_dccm_ctl()) -// val stbuf = Module(new lsu_stbuf()) -// val ecc = Module(new lsu_ecc()) -// val trigger = Module(new lsu_trigger()) -// val clkdomain = Module(new lsu_clkdomain()) -// val bus_intf = Module(new lsu_bus_intf()) -// -// val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR -// val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR -// -// // block stores in decode - for either bus or stbuf reasons -// io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff -// io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff -// io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage -// -// // Ready to accept dma trxns -// // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m -// val dma_mem_tag_d = io.lsu_dma.dma_mem_tag -// val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store -// io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff) -// val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1) -// val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d -// dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores -// dma_dccm_wdata_hi := dma_dccm_wdata(63,32) -// dma_dccm_wdata_lo := dma_dccm_wdata(31,0) -// -// val flush_m_up = io.dec_tlu_flush_lower_r -// val flush_r = io.dec_tlu_i0_kill_writeb_r -// -// // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence. -// // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error -// // Store buffer now have only non-dma dccm stores -// // stbuf_empty not needed since it has only dccm stores -// -// io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any -// io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock -// // Instantiate the store buffer -// val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r)) -// // Disable Forwarding for now -// val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) -// // Bus signals -// val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int -// // Dual signals -// val ldst_dual_d = lsu_addr_d(2) =/= end_addr_d(2) -// val ldst_dual_m = lsu_addr_m(2) =/= end_addr_m(2) -// val ldst_dual_r = lsu_addr_r(2) =/= end_addr_r(2) -// // PMU signals -// io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR)) -// io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m -// io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m -// -// //LSU_LSC_Control -// //Inputs -// lsu_lsc_ctl.io.clk_override := io.clk_override -// lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk -// lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk -// lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk -// lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk -// lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk -// lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r -// lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r -// lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r -// lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r -// lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m -// lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m -// lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m -// lsu_lsc_ctl.io.flush_m_up := flush_m_up -// lsu_lsc_ctl.io.flush_r := flush_r -// lsu_lsc_ctl.io.ldst_dual_d := ldst_dual_d -// lsu_lsc_ctl.io.ldst_dual_m := ldst_dual_m -// lsu_lsc_ctl.io.ldst_dual_r := ldst_dual_r -// lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu -// lsu_lsc_ctl.io.lsu_p <> io.lsu_p -// lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d -// lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d -// lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m -// lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m -// lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl -// lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff -// lsu_lsc_ctl.io.scan_mode := io.scan_mode -// //Outputs -// lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d -// lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m -// lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r -// end_addr_d := lsu_lsc_ctl.io.lsu_addr_d -// end_addr_m := lsu_lsc_ctl.io.lsu_addr_m -// end_addr_r := lsu_lsc_ctl.io.lsu_addr_r -// io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr -// io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r -// io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr -// io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error -// // DCCM Control -// //Inputs -// dccm_ctl.io.clk_override := io.clk_override -// dccm_ctl.io.ldst_dual_m := ldst_dual_m -// dccm_ctl.io.ldst_dual_r := ldst_dual_r -// dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk -// dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk -// dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk -// dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk -// dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk -// dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d -// dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r -// dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d -// dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m -// dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r -// dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d -// dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m -// dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r -// dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r -// dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r -// dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r -// dccm_ctl.io.lsu_addr_d := lsu_addr_d -// dccm_ctl.io.lsu_addr_m := lsu_addr_m(DCCM_BITS-1,0) -// dccm_ctl.io.lsu_addr_r := lsu_addr_r -// dccm_ctl.io.end_addr_d := end_addr_d(DCCM_BITS-1,0) -// dccm_ctl.io.end_addr_m := end_addr_m(DCCM_BITS-1,0) -// dccm_ctl.io.end_addr_r := end_addr_r(DCCM_BITS-1,0) -// dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any -// dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any -// dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any -// dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any -// dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m -// dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m -// dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m -// dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m -// dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r -// dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r -// dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r -// dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r -// dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r -// dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff -// dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff -// dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff -// dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff -// dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m -// dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m -// dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m -// dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m -// dccm_ctl.io.dma_dccm_wen := dma_dccm_wen -// dccm_ctl.io.dma_pic_wen := dma_pic_wen -// dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m -// dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo -// dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi -// dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi -// dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo -// dccm_ctl.io.scan_mode := io.scan_mode -// //Outputs -// io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl -// io.dccm <> dccm_ctl.io.dccm -// io.lsu_pic <> dccm_ctl.io.lsu_pic -// //Store Buffer -// //Inputs -// stbuf.io.ldst_dual_d := ldst_dual_d -// stbuf.io.ldst_dual_m := ldst_dual_m -// stbuf.io.ldst_dual_r := ldst_dual_r -// stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk -// stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk -// stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r -// stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r -// stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r -// stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d -// stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r -// stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r -// stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r -// stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r -// stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any -// stbuf.io.lsu_addr_d := lsu_addr_d -// stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m -// stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r -// stbuf.io.end_addr_d := end_addr_d -// stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m -// stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r -// stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m -// stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r -// stbuf.io.lsu_cmpen_m := lsu_cmpen_m -// stbuf.io.scan_mode := io.scan_mode -// -// // ECC -// //Inputs -// ecc.io.clk_override := io.clk_override -// ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk -// ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r -// ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any -// ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable -// ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r -// ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r -// ecc.io.lsu_addr_r := lsu_addr_r -// ecc.io.end_addr_r := end_addr_r -// ecc.io.lsu_addr_m := lsu_addr_m -// ecc.io.end_addr_m := end_addr_m -// ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r -// ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r -// ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m -// ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m -// ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r -// ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r -// ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m -// ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m -// ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r -// ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff -// ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m -// ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m -// ecc.io.dma_dccm_wen := dma_dccm_wen -// ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo -// ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi -// ecc.io.scan_mode := io.scan_mode -// -// //Trigger -// //Inputs -// trigger.io.trigger_pkt_any <> io.trigger_pkt_any -// trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m -// trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m -// //Outputs -// io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m -// -// //Clock Domain -// //Inputs -// clkdomain.io.active_clk := io.active_clk -// clkdomain.io.clk_override := io.clk_override -// clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt -// clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req -// clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r -// clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any -// clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any -// clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r -// clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any -// clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any -// clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any -// clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en -// clkdomain.io.lsu_p := io.lsu_p -// clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d -// clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r -// clkdomain.io.scan_mode := io.scan_mode -// -// //Bus Interface -// //Inputs -// bus_intf.io.scan_mode := io.scan_mode -// io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff -// bus_intf.io.clk_override := io.clk_override -// bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk -// bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk -// bus_intf.io.lsu_busm_clken := lsu_busm_clken -// bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken -// bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk -// bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk -// bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk -// bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk -// bus_intf.io.active_clk := io.active_clk -// bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk -// bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d -// bus_intf.io.lsu_busreq_m := lsu_busreq_m -// bus_intf.io.ldst_dual_d := ldst_dual_d -// bus_intf.io.ldst_dual_m := ldst_dual_m -// bus_intf.io.ldst_dual_r := ldst_dual_r -// bus_intf.io.lsu_addr_m := lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) -// bus_intf.io.lsu_addr_r := lsu_addr_r & Fill(32,lsu_busreq_r) -// bus_intf.io.end_addr_m := end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) -// bus_intf.io.end_addr_r := end_addr_r & Fill(32,lsu_busreq_r) -// bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r) -// bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m -// bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r -// bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt -// bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r -// bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m -// bus_intf.io.flush_m_up := flush_m_up -// bus_intf.io.flush_r := flush_r -// //Outputs -// io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff -// lsu_busreq_r := bus_intf.io.lsu_busreq_r -// io.axi <> bus_intf.io.axi -// bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en -// -// withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)} -// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)} -// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)} -// -//} -//object lsu_main extends App { -// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu())) -//} \ No newline at end of file +package lsu + +import lib._ +import chisel3._ +import chisel3.util._ +import include._ +import mem._ + +class lsu extends Module with RequireAsyncReset with param with lib { + val io = IO (new Bundle { + val clk_override = Input(Bool()) + val lsu_dma = new lsu_dma + val lsu_pic = new lsu_pic + val lsu_exu = new lsu_exu + val lsu_dec = new lsu_dec + val dccm = Flipped(new mem_lsu) + val lsu_tlu = new lsu_tlu + val axi = new axi_channels(LSU_BUS_TAG) + + val dec_tlu_flush_lower_r = Input(Bool()) + val dec_tlu_i0_kill_writeb_r = Input(Bool()) + val dec_tlu_force_halt = Input(Bool()) + + val dec_tlu_core_ecc_disable = Input(Bool()) + + val dec_lsu_offset_d = Input(UInt(12.W)) + val lsu_p = Flipped(Valid(new lsu_pkt_t())) + val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t())) + + val dec_lsu_valid_raw_d = Input(Bool()) + val dec_tlu_mrac_ff = Input(UInt(32.W)) + + //Outputs + // val lsu_result_m = Output(UInt(32.W)) + val lsu_result_corr_r = Output(UInt(32.W)) + val lsu_load_stall_any = Output(Bool()) + val lsu_store_stall_any = Output(Bool()) + val lsu_fastint_stall_any = Output(Bool()) + val lsu_idle_any = Output(Bool()) + val lsu_active = Output(Bool()) + val lsu_fir_addr = Output(UInt(31.W)) + val lsu_fir_error = Output(UInt(2.W)) + val lsu_single_ecc_error_incr = Output(Bool()) + val lsu_error_pkt_r = Valid(new lsu_error_pkt_t()) + val lsu_pmu_misaligned_m = Output(Bool()) + val lsu_trigger_match_m = Output(UInt(4.W)) + + val lsu_bus_clk_en = Input(Bool()) + val scan_mode = Input(Bool()) + val active_clk = Input(Clock()) + val lsu_nonblock_load_data = Output(UInt(32.W)) + }) + val dma_dccm_wdata = WireInit(0.U(64.W)) + val dma_dccm_wdata_lo = WireInit(0.U(32.W)) + val dma_dccm_wdata_hi = WireInit(0.U(32.W)) + val dma_mem_tag_m = WireInit(0.U(3.W)) + val lsu_raw_fwd_lo_r = WireInit(0.U(1.W)) + val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) + val lsu_busm_clken = WireInit(0.U(1.W)) + val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W)) +// val lsu_addr_d = WireInit(0.U(32.W)) +// val lsu_addr_m = WireInit(0.U(32.W)) +// val lsu_addr_r = WireInit(0.U(32.W)) +// val end_addr_d = WireInit(0.U(32.W)) +// val end_addr_m = WireInit(0.U(32.W)) +// val end_addr_r = WireInit(0.U(32.W)) + val lsu_busreq_r = WireInit(Bool(),false.B) +// val ldst_dual_d = WireInit(Bool(),false.B) +// val ldst_dual_m = WireInit(Bool(),false.B) +// val ldst_dual_r = WireInit(Bool(),false.B) + + val lsu_lsc_ctl = Module(new lsu_lsc_ctl()) + // io.lsu_exu.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m + // io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data + io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r + val dccm_ctl = Module(new lsu_dccm_ctl()) + val stbuf = Module(new lsu_stbuf()) + val ecc = Module(new lsu_ecc()) + val trigger = Module(new lsu_trigger()) + val clkdomain = Module(new lsu_clkdomain()) + val bus_intf = Module(new lsu_bus_intf()) + + val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR + val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR + + // block stores in decode - for either bus or stbuf reasons + io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff + io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff + io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage + + // Ready to accept dma trxns + // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m + val dma_mem_tag_d = io.lsu_dma.dma_mem_tag + val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store + io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff) + val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1) + val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d + dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores + dma_dccm_wdata_hi := dma_dccm_wdata(63,32) + dma_dccm_wdata_lo := dma_dccm_wdata(31,0) + + val flush_m_up = io.dec_tlu_flush_lower_r + val flush_r = io.dec_tlu_i0_kill_writeb_r + + // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence. + // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error + // Store buffer now have only non-dma dccm stores + // stbuf_empty not needed since it has only dccm stores + io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any + io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock + // Instantiate the store buffer + val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r)) + // Disable Forwarding for now + val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) + // Bus signals + val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int + // Dual signals + + // PMU signals + io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR)) + io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m + io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m + + //LSU_LSC_Control + //Inputs + lsu_lsc_ctl.io.clk_override := io.clk_override + lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk + lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk + lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk + lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk + lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk + lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r + lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r + lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r + lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r + lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m + lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m + lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m + lsu_lsc_ctl.io.flush_m_up := flush_m_up + lsu_lsc_ctl.io.flush_r := flush_r + lsu_lsc_ctl.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2) + lsu_lsc_ctl.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) + lsu_lsc_ctl.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) + lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu + lsu_lsc_ctl.io.lsu_p <> io.lsu_p + lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d + lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d + lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m + lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m + lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl + lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff + lsu_lsc_ctl.io.scan_mode := io.scan_mode + //Outputs + + +// ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2) +// ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) +// ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) + + io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr + io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r + io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr + io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error + // DCCM Control + //Inputs + dccm_ctl.io.clk_override := io.clk_override + dccm_ctl.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) + dccm_ctl.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) + dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk + dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk + dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk + dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk + dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk + dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d + dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r + dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d + dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m + dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r + dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d + dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m + dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r + dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r + dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r + dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r + dccm_ctl.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d + dccm_ctl.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m(DCCM_BITS-1,0) + dccm_ctl.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r + dccm_ctl.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d(DCCM_BITS-1,0) + dccm_ctl.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m(DCCM_BITS-1,0) + dccm_ctl.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r(DCCM_BITS-1,0) + dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any + dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any + dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any + dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any + dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m + dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m + dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m + dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m + dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r + dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r + dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r + dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r + dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r + dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff + dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff + dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff + dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff + dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m + dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m + dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m + dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m + dccm_ctl.io.dma_dccm_wen := dma_dccm_wen + dccm_ctl.io.dma_pic_wen := dma_pic_wen + dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m + dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo + dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi + dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi + dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo + dccm_ctl.io.scan_mode := io.scan_mode + //Outputs + io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl + io.dccm <> dccm_ctl.io.dccm + io.lsu_pic <> dccm_ctl.io.lsu_pic + //Store Buffer + //Inputs + stbuf.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2) + stbuf.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) + stbuf.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) + stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk + stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk + stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r + stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r + stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r + stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d + stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r + stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r + stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r + stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r + stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any + stbuf.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d + stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m + stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r + stbuf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d + stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m + stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r + stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m + stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r + stbuf.io.lsu_cmpen_m := lsu_cmpen_m + stbuf.io.scan_mode := io.scan_mode + + // ECC + //Inputs + ecc.io.clk_override := io.clk_override + ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk + ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r + ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any + ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable + ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r + ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r + ecc.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r + ecc.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r + ecc.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m + ecc.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m + ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r + ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r + ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m + ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m + ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r + ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r + ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m + ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m + ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r + ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff + ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m + ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m + ecc.io.dma_dccm_wen := dma_dccm_wen + ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo + ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi + ecc.io.scan_mode := io.scan_mode + + //Trigger + //Inputs + trigger.io.trigger_pkt_any <> io.trigger_pkt_any + trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m + trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m + //Outputs + io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m + + //Clock Domain + //Inputs + clkdomain.io.active_clk := io.active_clk + clkdomain.io.clk_override := io.clk_override + clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt + clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req + clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r + clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any + clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any + clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r + clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any + clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any + clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any + clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en + clkdomain.io.lsu_p := io.lsu_p + clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d + clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r + clkdomain.io.scan_mode := io.scan_mode + + //Bus Interface + //Inputs + bus_intf.io.scan_mode := io.scan_mode + io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff + bus_intf.io.clk_override := io.clk_override + bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk + bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk + bus_intf.io.lsu_busm_clken := lsu_busm_clken + bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken + bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk + bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk + bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk + bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk + bus_intf.io.active_clk := io.active_clk + bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk + bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d + bus_intf.io.lsu_busreq_m := lsu_busreq_m + bus_intf.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2) + bus_intf.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2) + bus_intf.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2) + bus_intf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) + bus_intf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r & Fill(32,lsu_busreq_r) + bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) + bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r & Fill(32,lsu_busreq_r) + bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r) + bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r + bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt + bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r + bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m + bus_intf.io.flush_m_up := flush_m_up + bus_intf.io.flush_r := flush_r + //Outputs + io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff + io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data + lsu_busreq_r := bus_intf.io.lsu_busreq_r + io.axi <> bus_intf.io.axi + bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en + + withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)} + withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)} + withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)} + +} +object lsu_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new lsu())) +} \ No newline at end of file diff --git a/src/main/scala/lsu/lsu_bus_buffer.scala b/src/main/scala/lsu/lsu_bus_buffer.scala index 96d1b244..6ce06e2f 100644 --- a/src/main/scala/lsu/lsu_bus_buffer.scala +++ b/src/main/scala/lsu/lsu_bus_buffer.scala @@ -1,632 +1,633 @@ -//package lsu -//import chisel3._ -//import chisel3.util._ -//import lib._ -//import include._ -//import chisel3.experimental.{ChiselEnum, chiselName} -//import chisel3.util.ImplicitConversions.intToUInt -//import ifu._ -// -//@chiselName -//class lsu_bus_buffer extends Module with RequireAsyncReset with lib { -// val io = IO(new Bundle { -// val clk_override = Input(Bool()) -// val scan_mode = Input(Bool()) -// val tlu_busbuff = new tlu_busbuff() -// val dctl_busbuff = new dctl_busbuff() -// val dec_tlu_force_halt = Input(Bool()) -// val lsu_bus_obuf_c1_clken = Input(Bool()) -// val lsu_busm_clken = Input(Bool()) -// val lsu_c2_r_clk = Input(Clock()) -// val lsu_bus_ibuf_c1_clk = Input(Clock()) -// val lsu_bus_obuf_c1_clk = Input(Clock()) -// val lsu_bus_buf_c1_clk = Input(Clock()) -// val lsu_free_c2_clk = Input(Clock()) -// val lsu_busm_clk = Input(Clock()) -// val dec_lsu_valid_raw_d = Input(Bool()) -// val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) -// val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) -// val lsu_addr_m = Input(UInt(32.W)) -// val end_addr_m = Input(UInt(32.W)) -// val lsu_addr_r = Input(UInt(32.W)) -// val end_addr_r = Input(UInt(32.W)) -// val store_data_r = Input(UInt(32.W)) -// val no_word_merge_r = Input(Bool()) -// val no_dword_merge_r = Input(Bool()) -// val lsu_busreq_m = Input(Bool()) -// val ld_full_hit_m = Input(Bool()) -// val flush_m_up = Input(Bool()) -// val flush_r = Input(Bool()) -// val lsu_commit_r = Input(Bool()) -// val is_sideeffects_r = Input(Bool()) -// val ldst_dual_d = Input(Bool()) -// val ldst_dual_m = Input(Bool()) -// val ldst_dual_r = Input(Bool()) -// val ldst_byteen_ext_m = Input(UInt(8.W)) -// val lsu_axi = new axi_channels(LSU_BUS_TAG) -// val lsu_bus_clk_en = Input(Bool()) -// val lsu_bus_clk_en_q = Input(Bool()) -// -// val lsu_busreq_r = Output(Bool()) -// val lsu_bus_buffer_pend_any = Output(Bool()) -// val lsu_bus_buffer_full_any = Output(Bool()) -// val lsu_bus_buffer_empty_any = Output(Bool()) -// // val lsu_bus_idle_any = Output(Bool()) -// val ld_byte_hit_buf_lo = Output((UInt(4.W))) -// val ld_byte_hit_buf_hi = Output((UInt(4.W))) -// val ld_fwddata_buf_lo = Output((UInt(32.W))) -// val ld_fwddata_buf_hi = Output((UInt(32.W))) -// }) -// def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) -// def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) -// -// val DEPTH = LSU_NUM_NBLOAD -// val DEPTH_LOG2 = LSU_NUM_NBLOAD_WIDTH -// val TIMER = 8 -// val TIMER_MAX = TIMER - 1 -// val TIMER_LOG2 = if (TIMER < 2) 1 else log2Ceil(TIMER) -// -// val idle_C :: wait_C :: cmd_C :: resp_C :: done_partial_C :: done_wait_C :: done_C :: Nil = Enum(7) -// val buf_addr = Wire(Vec(DEPTH, UInt(32.W))) -// val buf_state = Wire(Vec(DEPTH, UInt(3.W))) -// val buf_write = WireInit(UInt(DEPTH.W), 0.U) -// val CmdPtr0 = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// -// -// val ldst_byteen_hi_m = io.ldst_byteen_ext_m(7, 4) -// val ldst_byteen_lo_m = io.ldst_byteen_ext_m(3, 0) -// -// val ld_addr_hitvec_lo = (0 until DEPTH).map(i => (io.lsu_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) -// val ld_addr_hitvec_hi = (0 until DEPTH).map(i => (io.end_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) -// val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W))) -// val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W), 0.U) -// val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W))) -// val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W), 0.U) -// val buf_byteen = Wire(Vec(DEPTH, UInt(4.W))) -// buf_byteen := buf_byteen.map(i=>0.U) -// val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W))) -// buf_nxtstate := buf_nxtstate.map(i=>0.U) -// val buf_wr_en = Wire(Vec(DEPTH, Bool())) -// buf_wr_en := buf_wr_en.map(i=> false.B) -// val buf_data_en = Wire(Vec(DEPTH, Bool())) -// buf_data_en := buf_data_en.map(i=> false.B) -// val buf_state_bus_en = Wire(Vec(DEPTH, Bool())) -// buf_state_bus_en := buf_state_bus_en.map(i=> false.B) -// val buf_ldfwd_in = Wire(Vec(DEPTH, Bool())) -// buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B) -// val buf_ldfwd_en = Wire(Vec(DEPTH, Bool())) -// buf_ldfwd_en := buf_ldfwd_en.map(i=> io.dec_tlu_force_halt) -// val buf_data_in = Wire(Vec(DEPTH, UInt(32.W))) -// buf_data_in := buf_data_in.map(i=> 0.U) -// val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) -// buf_ldfwdtag_in := buf_ldfwdtag_in.map(i=> 0.U) -// val buf_error_en = Wire(Vec(DEPTH, Bool())) -// buf_error_en := buf_error_en.map(i=> false.B) -// val bus_rsp_read_error = WireInit(Bool(), false.B) -// val bus_rsp_rdata = WireInit(UInt(64.W), 0.U) -// val bus_rsp_write_error = WireInit(Bool(), false.B) -// val buf_dualtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) -// buf_dualtag := buf_dualtag.map(i=> 0.U) -// val buf_ldfwd = WireInit(UInt(DEPTH.W), 0.U) -// val buf_resp_state_bus_en = Wire(Vec(DEPTH, Bool())) -// buf_resp_state_bus_en := buf_resp_state_bus_en.map(i=> false.B) -// val any_done_wait_state = WireInit(Bool(), false.B) -// val bus_rsp_write = WireInit(Bool(), false.B) -// val bus_rsp_write_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) -// val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) -// buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U) -// val buf_rst = Wire(Vec(DEPTH, Bool())) -// buf_rst := buf_rst.map(i=> false.B) -// val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U) -// val buf_byteen_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_byteen_in := buf_byteen_in.map(i=> 0.U) -// val buf_addr_in = Wire(Vec(DEPTH, UInt(32.W))) -// buf_addr_in := buf_addr_in.map(i=> 0.U) -// val buf_dual_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_samedw_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_nomerge_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_dualhi_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_dualtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) -// buf_dualtag_in := buf_dualtag_in.map(i=> 0.U) -// val buf_sideeffect_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_unsign_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_sz_in = Wire(Vec(DEPTH, UInt(2.W))) -// buf_sz_in := buf_sz_in.map(i=> 0.U) -// val buf_write_in = WireInit(UInt(DEPTH.W), 0.U) -// val buf_unsign = WireInit(UInt(DEPTH.W), 0.U) -// val buf_error = WireInit(UInt(DEPTH.W), 0.U) -// val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// -// val ibuf_data = WireInit(UInt(32.W), 0.U) -// io.ld_byte_hit_buf_lo := (0 until 4).map(i => (ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).asUInt).reverse.reduce(Cat(_, _)) -// io.ld_byte_hit_buf_hi := (0 until 4).map(i => (ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).asUInt).reverse.reduce(Cat(_, _)) -// -// val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).asUInt).reverse.reduce(Cat(_, _))) -// val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).asUInt).reverse.reduce(Cat(_, _))) -// -// val buf_age_younger = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_age_younger := buf_age_younger.map(i=> 0.U) -// ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).asUInt).reverse.reduce(Cat(_, _))) -// ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).asUInt).reverse.reduce(Cat(_, _))) -// -// val ibuf_addr = WireInit(UInt(32.W), 0.U) -// val ibuf_write = WireInit(Bool(), false.B) -// val ibuf_valid = WireInit(Bool(), false.B) -// val ld_addr_ibuf_hit_lo = (io.lsu_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m -// val ld_addr_ibuf_hit_hi = (io.end_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m -// -// val ibuf_byteen = WireInit(UInt(4.W), 0.U) -// -// ld_byte_ibuf_hit_lo := Fill(4, ld_addr_ibuf_hit_lo) & ibuf_byteen & ldst_byteen_lo_m -// ld_byte_ibuf_hit_hi := Fill(4, ld_addr_ibuf_hit_hi) & ibuf_byteen & ldst_byteen_hi_m -// -// val buf_data = Wire(Vec(DEPTH, UInt(32.W))) -// buf_data := buf_data.map(i=> 0.U) -// val fwd_data = WireInit(UInt(32.W), 0.U) -// val ld_fwddata_buf_lo_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_lo(i))).reverse.reduce(Cat(_,_)) -// val ld_fwddata_buf_hi_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_hi(i))).reverse.reduce(Cat(_,_)) -// io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | -// (ld_fwddata_buf_lo_initial & ibuf_data) -// -// io.ld_fwddata_buf_hi := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), -// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | -// (ld_fwddata_buf_hi_initial & ibuf_data) -// -// val bus_coalescing_disable = io.tlu_busbuff.dec_tlu_wb_coalescing_disable | BUILD_AHB_LITE.B -// val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.bits.by -> 1.U(4.W), -// io.lsu_pkt_r.bits.half -> 3.U(4.W), -// io.lsu_pkt_r.bits.word -> 15.U(4.W))) -// -// val ldst_byteen_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(4.W), -// (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)), -// (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)), -// (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1)))) -// -// val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r, -// (io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U), -// (io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)), -// (io.lsu_addr_r(1,0)===3.U)->Cat(ldst_byteen_r(0) , 0.U(3.W)))) -// -// val store_data_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(32.W), -// (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(24.W) , io.store_data_r(31,24)), -// (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(16.W), io.store_data_r(31,16)), -// (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(8.W), io.store_data_r(31,8)))) -// -// val store_data_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->io.store_data_r, -// (io.lsu_addr_r(1,0)===1.U)->Cat(io.store_data_r(23,0), 0.U(8.W)), -// (io.lsu_addr_r(1,0)===2.U)->Cat(io.store_data_r(15,0), 0.U(16.W)), -// (io.lsu_addr_r(1,0)===3.U)->Cat(io.store_data_r(7 ,0) , 0.U(24.W)))) -// -// -// val ldst_samedw_r = io.lsu_addr_r(3) === io.end_addr_r(3) -// val is_aligned_r = Mux1H(Seq(io.lsu_pkt_r.bits.word -> (io.lsu_addr_r(1, 0) === 0.U), -// io.lsu_pkt_r.bits.half -> !io.lsu_addr_r(0), -// io.lsu_pkt_r.bits.by -> 1.U)) -// val ibuf_byp = io.lsu_busreq_r & (io.lsu_pkt_r.bits.load | io.no_word_merge_r) & !ibuf_valid -// val ibuf_wr_en = io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp -// val ibuf_drain_vld = WireInit(Bool(), false.B) -// val ibuf_rst = (ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt -// val ibuf_force_drain = io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.bits.load | (ibuf_addr(31, 2) =/= io.lsu_addr_m(31, 2))) -// val ibuf_sideeffect = WireInit(Bool(), false.B) -// val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) -// val ibuf_merge_en = WireInit(Bool(), false.B) -// val ibuf_merge_in = WireInit(Bool(), false.B) -// ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in)) -// | ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable) -// val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// val WrPtr0_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// -// val ibuf_tag_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_tag, Mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r)) -// val ibuf_dualtag_in = WrPtr0_r -// val ibuf_sz_in = Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) -// val ibuf_addr_in = Mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) -// val ibuf_byteen_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3, 0) | ldst_byteen_lo_r(3, 0), -// Mux(io.ldst_dual_r, ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0))) -// -// -// val ibuf_data_in = (0 until 4).map(i => Mux(ibuf_merge_en & ibuf_merge_in, -// Mux(ldst_byteen_lo_r(i), store_data_lo_r((8 * i) + 7, 8 * i), ibuf_data((8 * i) + 7, 8 * i)), -// Mux(io.ldst_dual_r, store_data_hi_r((8 * i) + 7, 8 * i), store_data_lo_r((8 * i) + 7, 8 * i)))).reverse.reduce(Cat(_, _)) -// val ibuf_timer_in = Mux(ibuf_wr_en, 0.U, Mux((ibuf_timer < TIMER_MAX.U).asBool(), ibuf_timer+1.U, ibuf_timer)) -// -// ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.bits.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable -// ibuf_merge_in := !io.ldst_dual_r -// val ibuf_byteen_out = (0 until 4).map(i=>(Mux(ibuf_merge_en & !ibuf_merge_in, ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_)) -// val ibuf_data_out = (0 until 4).map(i=>Mux(ibuf_merge_en & !ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8*i)+7, 8*i), ibuf_data((8*i)+7, 8*i)), ibuf_data((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) -// -// ibuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(ibuf_wr_en, true.B, ibuf_valid) & !ibuf_rst, false.B)} -// ibuf_tag := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_tag_in, 0.U, ibuf_wr_en)} -// val ibuf_dualtag = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_dualtag_in, 0.U, ibuf_wr_en)} -// val ibuf_dual = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.ldst_dual_r, 0.U, ibuf_wr_en)} -// val ibuf_samedw = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en)} -// val ibuf_nomerge = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en)} -// ibuf_sideeffect := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en)} -// val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.unsign, 0.U, ibuf_wr_en)} -// ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.store, 0.U, ibuf_wr_en)} -// val ibuf_sz = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_sz_in, 0.U, ibuf_wr_en)} -// ibuf_addr := rvdffe(ibuf_addr_in, ibuf_wr_en, clock, io.scan_mode) -// ibuf_byteen := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_byteen_in, 0.U, ibuf_wr_en)} -// ibuf_data := rvdffe(ibuf_data_in, ibuf_wr_en, clock, io.scan_mode) -// ibuf_timer := withClock(io.lsu_free_c2_clk) {RegNext(ibuf_timer_in, 0.U)} -// val buf_numvld_wrcmd_any = WireInit(UInt(4.W), 0.U) -// val buf_numvld_cmd_any = WireInit(UInt(4.W), 0.U) -// val obuf_wr_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) -// val buf_nomerge = Wire(Vec(DEPTH, Bool())) -// buf_nomerge := buf_nomerge.map(i=> false.B) -// -// val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) -// val obuf_force_wr_en = WireInit(Bool(), false.B) -// val obuf_wr_en = WireInit(Bool(), false.B) -// val obuf_wr_wait = (buf_numvld_wrcmd_any===1.U) & (buf_numvld_cmd_any===1.U) & (obuf_wr_timer =/= TIMER_MAX.U) & -// !bus_coalescing_disable & !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_nomerge(i))) & -// !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_sideeffect(i))) & !obuf_force_wr_en -// val obuf_wr_timer_in = Mux(obuf_wr_en, 0.U(3.W), Mux(buf_numvld_cmd_any.orR & (obuf_wr_timer(CmdPtr0===i.U)->buf_addr(i)(31,2)))) -// val buf_numvld_pend_any = WireInit(UInt(4.W), 0.U) -// val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.bits.store | io.no_dword_merge_r) -// val bus_sideeffect_pend = WireInit(Bool(), false.B) -// val found_cmdptr0 = WireInit(Bool(), false.B) -// val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool())) -// buf_cmd_state_bus_en := buf_cmd_state_bus_en.map(i=> false.B) -// val buf_dual = Wire(Vec(DEPTH, Bool())) -// buf_dual := buf_dual.map(i=> false.B) -// val buf_samedw = Wire(Vec(DEPTH, Bool())) -// buf_samedw := buf_samedw.map(i=> false.B) -// val found_cmdptr1 = WireInit(Bool(), false.B) -// val bus_cmd_ready = WireInit(Bool(), false.B) -// val obuf_valid = WireInit(Bool(), false.B) -// val obuf_nosend = WireInit(Bool(), false.B) -// // val lsu_bus_cntr_overflow = WireInit(Bool(), false.B) -// val bus_addr_match_pending = WireInit(Bool(), false.B) -// -// obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) | -// ((indexing(buf_state, CmdPtr0) === cmd_C) & -// found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !(indexing(buf_sideeffect, CmdPtr0) & bus_sideeffect_pend) & -// (!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_write, CmdPtr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) | -// obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !bus_addr_match_pending & io.lsu_bus_clk_en -// -// val bus_cmd_sent = WireInit(Bool(), false.B) -// val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -// val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, indexing(buf_write, CmdPtr0)) -// val obuf_sideeffect_in = Mux(ibuf_buf_byp, io.is_sideeffects_r, indexing(buf_sideeffect, CmdPtr0)) -// val obuf_addr_in = Mux(ibuf_buf_byp, io.lsu_addr_r, indexing(buf_addr, CmdPtr0)) -// val buf_sz = Wire(Vec(DEPTH, UInt(2.W))) -// buf_sz := buf_sz.map(i=> 0.U) -// val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half), indexing(buf_sz, CmdPtr0)) -// val obuf_merge_en = WireInit(Bool(), false.B) -// val obuf_merge_in = obuf_merge_en -// val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) -// -// val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) -// val obuf_cmd_done = WireInit(Bool(), false.B) -// val bus_wcmd_sent = WireInit(Bool(), false.B) -// val obuf_cmd_done_in = !(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent) -// val obuf_data_done = WireInit(Bool(), false.B) -// val bus_wdata_sent = WireInit(Bool(), false.B) -// val obuf_data_done_in = !(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent) -// val obuf_aligned_in = Mux(ibuf_buf_byp, is_aligned_r, obuf_sz_in(1,0)===0.U | (obuf_sz_in(0) & !obuf_addr_in(0)) | (obuf_sz_in(1)&(!obuf_addr_in(1,0).orR))) -// -// val obuf_nosend_in = WireInit(Bool(), false.B) -// val obuf_rdrsp_pend = WireInit(Bool(), false.B) -// val bus_rsp_read = WireInit(Bool(), false.B) -// val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) -// val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) -// val obuf_write = WireInit(Bool(), false.B) -// val obuf_rdrsp_pend_in = ((!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | (bus_cmd_sent & !obuf_write)) & !io.dec_tlu_force_halt -// val obuf_rdrsp_pend_en = io.lsu_bus_clk_en | io.dec_tlu_force_halt -// val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U) -// val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag) -// val obuf_addr = WireInit(UInt(32.W), 0.U) -// val obuf_sideeffect = WireInit(Bool(), false.B) -// obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.tlu_busbuff.dec_tlu_external_ldfwd_disable & -// ((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) -// val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)), -// Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr0)))) -// val obuf_byteen1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_hi_r)), -// Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr1)))) -// -// val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)), -// Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_data, CmdPtr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr0)))) -// val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)), -// Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_data, CmdPtr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr1)))) -// val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) -// val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data0_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) -// -// val buf_dualhi = Wire(Vec(DEPTH, Bool())) -// buf_dualhi := buf_dualhi.map(i=> false.B) -// obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, CmdPtr1) === cmd_C) & -// !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_sideeffect, CmdPtr0) & -// (!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0))) | -// (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) -// val obuf_wr_enQ = rvdff_fpga (obuf_wr_en,io.lsu_busm_clk,io.lsu_busm_clken,clock) -// obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & !obuf_rst, false.B)} -// obuf_nosend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)} -// obuf_rdrsp_pend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_rdrsp_pend_in, false.B,obuf_rdrsp_pend_en)} -// obuf_cmd_done := rvdff_fpga (obuf_cmd_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) -// obuf_data_done := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) -// obuf_rdrsp_tag := rvdff_fpga (obuf_rdrsp_tag_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) -// -// obuf_tag0 := rvdffs_fpga (obuf_tag0_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// val obuf_tag1 = rvdffs_fpga (obuf_tag1_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// val obuf_merge = rvdffs_fpga (obuf_merge_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// obuf_write := rvdffs_fpga (obuf_write_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// obuf_sideeffect := rvdffs_fpga (obuf_sideeffect_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// val obuf_sz = rvdffs_fpga (obuf_sz_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) -// obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode) -// val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode) -// obuf_wr_timer := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,obuf_wr_en,clock) -// val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// -// -// WrPtr0_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & -// !((ibuf_valid & (ibuf_tag===i.U)) | (io.lsu_busreq_r & -// ((WrPtr0_r === i.U) | (io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U)) -// -// -// val WrPtr1_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// WrPtr1_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | -// (io.lsu_busreq_m & (WrPtr0_m===i.U)) | -// (io.lsu_busreq_r & (((WrPtr0_r === i.U)) | -// (io.ldst_dual_r & (WrPtr1_r===i.U)))))) -> i.U)) -// -// val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_age := buf_age.map(i=> 0.U) -// -// val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) -// val CmdPtr1Dec = (0 until DEPTH).map(i=> (!((buf_age(i) & (~CmdPtr0Dec)).orR) & !CmdPtr0Dec(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) -// val buf_rsp_pickage = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_rsp_pickage := buf_rsp_pickage.map(i=> 0.U) -// val RspPtrDec = (0 until DEPTH).map(i=> (!(buf_rsp_pickage(i).orR) & (buf_state(i)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_)) -// found_cmdptr0 := CmdPtr0Dec.orR -// found_cmdptr1 := CmdPtr1Dec.orR -// -// def Enc8x3(in: UInt) : UInt = Cat(in(4)|in(5)|in(6)|in(7), in(2)|in(3)|in(6)|in(7), in(1)|in(3)|in(5)|in(7)) -// -// -// -// val RspPtr = WireInit(UInt(DEPTH_LOG2.W), 0.U) -// CmdPtr0 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr0Dec)) -// -// CmdPtr1 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr1Dec)) -// RspPtr := Enc8x3(Cat(Fill(8-DEPTH, 0.U),RspPtrDec)) -// val buf_state_en = Wire(Vec(DEPTH, Bool())) -// buf_state_en := buf_state_en.map(i=> false.B) -// val buf_rspageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_rspageQ := buf_rspageQ.map(i=> 0.U) -// val buf_rspage_set = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_rspage_set := buf_rspage_set.map(i=> 0.U) -// val buf_rspage_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_rspage_in := buf_rspage_in.map(i=> 0.U) -// val buf_rspage = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_rspage := buf_rspage.map(i=> 0.U) -// -// val buf_age_in = (0 until DEPTH).map(i=>(0 until DEPTH).map(j=> ((((buf_state(i)===idle_C) & buf_state_en(i)) & -// (((buf_state(j)===wait_C) | ((buf_state(j)===cmd_C) & !buf_cmd_state_bus_en(j))) | -// (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r === i.U) & (ibuf_tag === j.U)) | -// (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_))) -// val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) -// buf_ageQ := buf_ageQ.map(i=> 0.U) -// buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & !((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j)) & !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) -// buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_))) -// buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_))) -// -// buf_rspage_set := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(((buf_state(i)===idle_C) & buf_state_en(i)) & -// (!((buf_state(j)===idle_C) | (buf_state(j)===done_C)) | -// (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) | -// (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_))) -// buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_))) -// buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))& !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) -// ibuf_drainvec_vld := (0 until DEPTH).map(i=>(ibuf_drain_vld & (ibuf_tag === i.U)).asUInt).reverse.reduce(Cat(_,_)) -// buf_byteen_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), -// Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0)))) -// buf_addr_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_addr, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), io.end_addr_r, io.lsu_addr_r))) -// buf_dual_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r)).asUInt).reverse.reduce(Cat(_,_)) -// buf_samedw_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r)).asUInt).reverse.reduce(Cat(_,_)) -// buf_nomerge_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_nomerge | ibuf_force_drain, io.no_dword_merge_r)).asUInt).reverse.reduce(Cat(_,_)) -// buf_dualhi_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual ,ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U))).asUInt).reverse.reduce(Cat(_,_)) -// buf_dualtag_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), WrPtr0_r, WrPtr1_r))) -// buf_sideeffect_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)).asUInt).reverse.reduce(Cat(_,_)) -// buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.bits.unsign)).asUInt).reverse.reduce(Cat(_,_)) -// buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half))) -// buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.bits.store)).asUInt).reverse.reduce(Cat(_,_)) -// -// for(i<- 0 until DEPTH) { -// switch(buf_state(i)) { -// is(idle_C) { -// buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C) -// buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag)) -// buf_wr_en(i) := buf_state_en(i) -// buf_data_en(i) := buf_state_en(i) -// buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) -// buf_cmd_state_bus_en(i) := 0.U -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(wait_C) { -// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) -// buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt -// buf_cmd_state_bus_en(i) := 0.U -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(cmd_C) { -// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) -// buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ -// buf_state_bus_en(i) := buf_cmd_state_bus_en(i) -// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -// buf_ldfwd_in(i) := true.B -// buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt -// buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(LSU_BUS_TAG - 2, 0)).asUInt -// buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read -// buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error -// buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(resp_C) { -// buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !bus_rsp_write_error)).asBool(), idle_C, -// Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, -// Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) -// buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) | -// (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W))) | -// (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) | -// (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i)))))) -// buf_state_bus_en(i) := buf_resp_state_bus_en(i) -// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -// buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en -// buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) | -// (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | -// (bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) -// buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) -// buf_cmd_state_bus_en(i) := 0.U -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(done_partial_C) { // Other part of dual load hasn't returned -// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) -// buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | -// (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) -// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -// buf_cmd_state_bus_en(i) := 0.U -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns -// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) -// buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt -// buf_cmd_state_bus_en(i) := 0.U -// buf_rst(i) := io.dec_tlu_force_halt -// } -// is(done_C) { -// buf_nxtstate(i) := idle_C -// buf_rst(i) := true.B -// buf_state_en(i) := true.B -// buf_ldfwd_in(i) := false.B -// buf_ldfwd_en(i) := buf_state_en(i) -// buf_cmd_state_bus_en(i) := 0.U -// } -// } -// buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())} -// buf_ageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_age_in(i), 0.U)} -// buf_rspageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_rspage_in(i), 0.U)} -// buf_dualtag(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualtag_in(i), 0.U, buf_wr_en(i).asBool())} -// buf_dual(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dual_in(i), false.B, buf_wr_en(i).asBool())} -// buf_samedw(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_samedw_in(i), false.B, buf_wr_en(i).asBool())} -// buf_nomerge(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nomerge_in(i), false.B, buf_wr_en(i).asBool())} -// buf_dualhi(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualhi_in(i), false.B, buf_wr_en(i).asBool())} -// } -// -// buf_ldfwd := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwd_in(i), false.B, buf_ldfwd_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) -// buf_ldfwdtag := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwdtag_in(i), 0.U, buf_ldfwd_en(i).asBool())}) -// buf_sideeffect := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sideeffect_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) -// buf_unsign := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_unsign_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) -// buf_write := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_write_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) -// buf_sz := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sz_in(i), 0.U, buf_wr_en(i).asBool())}) -// buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode)) -// buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())}) -// buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode)) -// buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(!buf_rst(i) & Mux(buf_error_en(i), true.B, buf_error(i)), false.B)}).asUInt()).reverse.reduce(Cat(_,_)) -// val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_) -// buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) -// buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) -// buf_numvld_pend_any := (0 until DEPTH).map(i=>((buf_state(i)===wait_C) | ((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i))).asUInt).reverse.reduce(_ +& _) -// any_done_wait_state := (0 until DEPTH).map(i=>buf_state(i)===done_wait_C).reverse.reduce(_|_) -// io.lsu_bus_buffer_pend_any := buf_numvld_pend_any.orR -// io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U) -// io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid -// -// io.dctl_busbuff.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & !io.flush_m_up & !io.ld_full_hit_m -// io.dctl_busbuff.lsu_nonblock_load_tag_m := WrPtr0_m -// val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B) -// io.dctl_busbuff.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r -// io.dctl_busbuff.lsu_nonblock_load_inv_tag_r := WrPtr0_r -// val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(buf_write(i))))) -// io.dctl_busbuff.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i)))) -// io.dctl_busbuff.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U)) -// val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i))) -// val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) & buf_dualhi(i))) -> buf_data(i))) -// val lsu_nonblock_addr_offset = indexing(buf_addr, io.dctl_busbuff.lsu_nonblock_load_data_tag)(1,0) -// val lsu_nonblock_sz = indexing(buf_sz, io.dctl_busbuff.lsu_nonblock_load_data_tag) -// val lsu_nonblock_unsign = indexing(buf_unsign, io.dctl_busbuff.lsu_nonblock_load_data_tag) -// // val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.dctl_busbuff.lsu_nonblock_load_data_tag) -// val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U) -// -// io.dctl_busbuff.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.dctl_busbuff.lsu_nonblock_load_data_error -// io.dctl_busbuff.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)), -// (lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)), -// (!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)), -// (!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)), -// (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) -// bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) | (obuf_valid & obuf_sideeffect & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) -// bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> -// ( obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) -// -// bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.w.ready), io.lsu_axi.ar.ready) -// bus_wcmd_sent := io.lsu_axi.aw.valid & io.lsu_axi.aw.ready -// bus_wdata_sent := io.lsu_axi.w.valid & io.lsu_axi.w.ready -// bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) -// bus_rsp_read := io.lsu_axi.r.valid & io.lsu_axi.r.ready -// bus_rsp_write := io.lsu_axi.b.valid & io.lsu_axi.b.ready -// bus_rsp_read_tag := io.lsu_axi.r.bits.id -// bus_rsp_write_tag := io.lsu_axi.b.bits.id -// bus_rsp_write_error := bus_rsp_write & (io.lsu_axi.b.bits.resp =/= 0.U) -// bus_rsp_read_error := bus_rsp_read & (io.lsu_axi.r.bits.resp =/= 0.U) -// bus_rsp_rdata := io.lsu_axi.r.bits.data -// -// // AXI Command signals -// io.lsu_axi.aw.valid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending -// io.lsu_axi.aw.bits.id := obuf_tag0 -// io.lsu_axi.aw.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W))) -// io.lsu_axi.aw.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) -// io.lsu_axi.aw.bits.prot := 1.U(3.W) -// io.lsu_axi.aw.bits.cache := Mux(obuf_sideeffect, 0.U, 15.U) -// io.lsu_axi.aw.bits.region := obuf_addr(31,28) -// io.lsu_axi.aw.bits.len := 0.U -// io.lsu_axi.aw.bits.burst := 1.U(2.W) -// io.lsu_axi.aw.bits.qos := 0.U -// io.lsu_axi.aw.bits.lock := 0.U -// -// io.lsu_axi.w.valid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending -// io.lsu_axi.w.bits.strb := obuf_byteen & Fill(8, obuf_write) -// io.lsu_axi.w.bits.data := obuf_data -// io.lsu_axi.w.bits.last := 1.U -// -// io.lsu_axi.ar.valid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending -// io.lsu_axi.ar.bits.id := obuf_tag0 -// io.lsu_axi.ar.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W))) -// io.lsu_axi.ar.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) -// io.lsu_axi.ar.bits.prot := 1.U(3.W) -// io.lsu_axi.ar.bits.cache := Mux(obuf_sideeffect, 0.U(4.W), 15.U) -// io.lsu_axi.ar.bits.region := obuf_addr(31,28) -// io.lsu_axi.ar.bits.len := 0.U -// io.lsu_axi.ar.bits.burst := 1.U(2.W) -// io.lsu_axi.ar.bits.qos := 0.U -// io.lsu_axi.ar.bits.lock := 0.U -// io.lsu_axi.b.ready := 1.U -// io.lsu_axi.r.ready := 1.U -// io.tlu_busbuff.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i)))) -// val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U)) -// -// io.tlu_busbuff.lsu_imprecise_error_load_any := io.dctl_busbuff.lsu_nonblock_load_data_error & !io.tlu_busbuff.lsu_imprecise_error_store_any -// io.tlu_busbuff.lsu_imprecise_error_addr_any := Mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.dctl_busbuff.lsu_nonblock_load_data_tag)) -// //lsu_bus_cntr_overflow := 0.U -// -// // io.lsu_bus_idle_any := 1.U -// -// // PMU signals -// io.tlu_busbuff.lsu_pmu_bus_trxn := (io.lsu_axi.aw.valid & io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) -// io.tlu_busbuff.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r -// io.tlu_busbuff.lsu_pmu_bus_error := io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any -// -// io.tlu_busbuff.lsu_pmu_bus_busy := (io.lsu_axi.aw.valid & !io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & !io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & !io.lsu_axi.ar.ready) -// -// WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)} -// WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)} -// io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} -// lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)} -//} -//object buffer extends App { -// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer())) -//} +package lsu +import chisel3._ +import chisel3.util._ +import lib._ +import include._ +import chisel3.experimental.{ChiselEnum, chiselName} +import chisel3.util.ImplicitConversions.intToUInt +import ifu._ + +@chiselName +class lsu_bus_buffer extends Module with RequireAsyncReset with lib { + val io = IO(new Bundle { + val clk_override = Input(Bool()) + val scan_mode = Input(Bool()) + val tlu_busbuff = new tlu_busbuff() + val dctl_busbuff = new dctl_busbuff() + val dec_tlu_force_halt = Input(Bool()) + val lsu_bus_obuf_c1_clken = Input(Bool()) + val lsu_busm_clken = Input(Bool()) + val lsu_c2_r_clk = Input(Clock()) + val lsu_bus_ibuf_c1_clk = Input(Clock()) + val lsu_bus_obuf_c1_clk = Input(Clock()) + val lsu_bus_buf_c1_clk = Input(Clock()) + val lsu_free_c2_clk = Input(Clock()) + val lsu_busm_clk = Input(Clock()) + val dec_lsu_valid_raw_d = Input(Bool()) + val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) + val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) + val lsu_addr_m = Input(UInt(32.W)) + val end_addr_m = Input(UInt(32.W)) + val lsu_addr_r = Input(UInt(32.W)) + val end_addr_r = Input(UInt(32.W)) + val store_data_r = Input(UInt(32.W)) + val no_word_merge_r = Input(Bool()) + val no_dword_merge_r = Input(Bool()) + val lsu_busreq_m = Input(Bool()) + val ld_full_hit_m = Input(Bool()) + val flush_m_up = Input(Bool()) + val flush_r = Input(Bool()) + val lsu_commit_r = Input(Bool()) + val is_sideeffects_r = Input(Bool()) + val ldst_dual_d = Input(Bool()) + val ldst_dual_m = Input(Bool()) + val ldst_dual_r = Input(Bool()) + val ldst_byteen_ext_m = Input(UInt(8.W)) + val lsu_axi = new axi_channels(LSU_BUS_TAG) + val lsu_bus_clk_en = Input(Bool()) + val lsu_bus_clk_en_q = Input(Bool()) + + val lsu_busreq_r = Output(Bool()) + val lsu_bus_buffer_pend_any = Output(Bool()) + val lsu_bus_buffer_full_any = Output(Bool()) + val lsu_bus_buffer_empty_any = Output(Bool()) + // val lsu_bus_idle_any = Output(Bool()) + val ld_byte_hit_buf_lo = Output((UInt(4.W))) + val ld_byte_hit_buf_hi = Output((UInt(4.W))) + val ld_fwddata_buf_lo = Output((UInt(32.W))) + val ld_fwddata_buf_hi = Output((UInt(32.W))) + val lsu_nonblock_load_data = Output((UInt(32.W))) + }) + def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) + def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) + + val DEPTH = LSU_NUM_NBLOAD + val DEPTH_LOG2 = LSU_NUM_NBLOAD_WIDTH + val TIMER = 8 + val TIMER_MAX = TIMER - 1 + val TIMER_LOG2 = if (TIMER < 2) 1 else log2Ceil(TIMER) + + val idle_C :: wait_C :: cmd_C :: resp_C :: done_partial_C :: done_wait_C :: done_C :: Nil = Enum(7) + val buf_addr = Wire(Vec(DEPTH, UInt(32.W))) + val buf_state = Wire(Vec(DEPTH, UInt(3.W))) + val buf_write = WireInit(UInt(DEPTH.W), 0.U) + val CmdPtr0 = WireInit(UInt(DEPTH_LOG2.W), 0.U) + + + val ldst_byteen_hi_m = io.ldst_byteen_ext_m(7, 4) + val ldst_byteen_lo_m = io.ldst_byteen_ext_m(3, 0) + + val ld_addr_hitvec_lo = (0 until DEPTH).map(i => (io.lsu_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) + val ld_addr_hitvec_hi = (0 until DEPTH).map(i => (io.end_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) + val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W))) + val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W), 0.U) + val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W))) + val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W), 0.U) + val buf_byteen = Wire(Vec(DEPTH, UInt(4.W))) + buf_byteen := buf_byteen.map(i=>0.U) + val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W))) + buf_nxtstate := buf_nxtstate.map(i=>0.U) + val buf_wr_en = Wire(Vec(DEPTH, Bool())) + buf_wr_en := buf_wr_en.map(i=> false.B) + val buf_data_en = Wire(Vec(DEPTH, Bool())) + buf_data_en := buf_data_en.map(i=> false.B) + val buf_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_state_bus_en := buf_state_bus_en.map(i=> false.B) + val buf_ldfwd_in = Wire(Vec(DEPTH, Bool())) + buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B) + val buf_ldfwd_en = Wire(Vec(DEPTH, Bool())) + buf_ldfwd_en := buf_ldfwd_en.map(i=> io.dec_tlu_force_halt) + val buf_data_in = Wire(Vec(DEPTH, UInt(32.W))) + buf_data_in := buf_data_in.map(i=> 0.U) + val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_ldfwdtag_in := buf_ldfwdtag_in.map(i=> 0.U) + val buf_error_en = Wire(Vec(DEPTH, Bool())) + buf_error_en := buf_error_en.map(i=> false.B) + val bus_rsp_read_error = WireInit(Bool(), false.B) + val bus_rsp_rdata = WireInit(UInt(64.W), 0.U) + val bus_rsp_write_error = WireInit(Bool(), false.B) + val buf_dualtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_dualtag := buf_dualtag.map(i=> 0.U) + val buf_ldfwd = WireInit(UInt(DEPTH.W), 0.U) + val buf_resp_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_resp_state_bus_en := buf_resp_state_bus_en.map(i=> false.B) + val any_done_wait_state = WireInit(Bool(), false.B) + val bus_rsp_write = WireInit(Bool(), false.B) + val bus_rsp_write_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U) + val buf_rst = Wire(Vec(DEPTH, Bool())) + buf_rst := buf_rst.map(i=> false.B) + val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U) + val buf_byteen_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_byteen_in := buf_byteen_in.map(i=> 0.U) + val buf_addr_in = Wire(Vec(DEPTH, UInt(32.W))) + buf_addr_in := buf_addr_in.map(i=> 0.U) + val buf_dual_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_samedw_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_nomerge_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_dualhi_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_dualtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_dualtag_in := buf_dualtag_in.map(i=> 0.U) + val buf_sideeffect_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_unsign_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_sz_in = Wire(Vec(DEPTH, UInt(2.W))) + buf_sz_in := buf_sz_in.map(i=> 0.U) + val buf_write_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_unsign = WireInit(UInt(DEPTH.W), 0.U) + val buf_error = WireInit(UInt(DEPTH.W), 0.U) + val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) + + val ibuf_data = WireInit(UInt(32.W), 0.U) + io.ld_byte_hit_buf_lo := (0 until 4).map(i => (ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).asUInt).reverse.reduce(Cat(_, _)) + io.ld_byte_hit_buf_hi := (0 until 4).map(i => (ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).asUInt).reverse.reduce(Cat(_, _)) + + val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).asUInt).reverse.reduce(Cat(_, _))) + val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).asUInt).reverse.reduce(Cat(_, _))) + + val buf_age_younger = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_age_younger := buf_age_younger.map(i=> 0.U) + ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).asUInt).reverse.reduce(Cat(_, _))) + ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).asUInt).reverse.reduce(Cat(_, _))) + + val ibuf_addr = WireInit(UInt(32.W), 0.U) + val ibuf_write = WireInit(Bool(), false.B) + val ibuf_valid = WireInit(Bool(), false.B) + val ld_addr_ibuf_hit_lo = (io.lsu_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m + val ld_addr_ibuf_hit_hi = (io.end_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m + + val ibuf_byteen = WireInit(UInt(4.W), 0.U) + + ld_byte_ibuf_hit_lo := Fill(4, ld_addr_ibuf_hit_lo) & ibuf_byteen & ldst_byteen_lo_m + ld_byte_ibuf_hit_hi := Fill(4, ld_addr_ibuf_hit_hi) & ibuf_byteen & ldst_byteen_hi_m + + val buf_data = Wire(Vec(DEPTH, UInt(32.W))) + buf_data := buf_data.map(i=> 0.U) + val fwd_data = WireInit(UInt(32.W), 0.U) + val ld_fwddata_buf_lo_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_lo(i))).reverse.reduce(Cat(_,_)) + val ld_fwddata_buf_hi_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_hi(i))).reverse.reduce(Cat(_,_)) + io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | + (ld_fwddata_buf_lo_initial & ibuf_data) + + io.ld_fwddata_buf_hi := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | + (ld_fwddata_buf_hi_initial & ibuf_data) + + val bus_coalescing_disable = io.tlu_busbuff.dec_tlu_wb_coalescing_disable | BUILD_AHB_LITE.B + val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.bits.by -> 1.U(4.W), + io.lsu_pkt_r.bits.half -> 3.U(4.W), + io.lsu_pkt_r.bits.word -> 15.U(4.W))) + + val ldst_byteen_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(4.W), + (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)), + (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)), + (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1)))) + + val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r, + (io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U), + (io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)), + (io.lsu_addr_r(1,0)===3.U)->Cat(ldst_byteen_r(0) , 0.U(3.W)))) + + val store_data_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(32.W), + (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(24.W) , io.store_data_r(31,24)), + (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(16.W), io.store_data_r(31,16)), + (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(8.W), io.store_data_r(31,8)))) + + val store_data_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->io.store_data_r, + (io.lsu_addr_r(1,0)===1.U)->Cat(io.store_data_r(23,0), 0.U(8.W)), + (io.lsu_addr_r(1,0)===2.U)->Cat(io.store_data_r(15,0), 0.U(16.W)), + (io.lsu_addr_r(1,0)===3.U)->Cat(io.store_data_r(7 ,0) , 0.U(24.W)))) + + + val ldst_samedw_r = io.lsu_addr_r(3) === io.end_addr_r(3) + val is_aligned_r = Mux1H(Seq(io.lsu_pkt_r.bits.word -> (io.lsu_addr_r(1, 0) === 0.U), + io.lsu_pkt_r.bits.half -> !io.lsu_addr_r(0), + io.lsu_pkt_r.bits.by -> 1.U)) + val ibuf_byp = io.lsu_busreq_r & (io.lsu_pkt_r.bits.load | io.no_word_merge_r) & !ibuf_valid + val ibuf_wr_en = io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp + val ibuf_drain_vld = WireInit(Bool(), false.B) + val ibuf_rst = (ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt + val ibuf_force_drain = io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.bits.load | (ibuf_addr(31, 2) =/= io.lsu_addr_m(31, 2))) + val ibuf_sideeffect = WireInit(Bool(), false.B) + val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) + val ibuf_merge_en = WireInit(Bool(), false.B) + val ibuf_merge_in = WireInit(Bool(), false.B) + ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in)) + | ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable) + val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U) + val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) + val WrPtr0_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) + + val ibuf_tag_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_tag, Mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r)) + val ibuf_dualtag_in = WrPtr0_r + val ibuf_sz_in = Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) + val ibuf_addr_in = Mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) + val ibuf_byteen_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3, 0) | ldst_byteen_lo_r(3, 0), + Mux(io.ldst_dual_r, ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0))) + + + val ibuf_data_in = (0 until 4).map(i => Mux(ibuf_merge_en & ibuf_merge_in, + Mux(ldst_byteen_lo_r(i), store_data_lo_r((8 * i) + 7, 8 * i), ibuf_data((8 * i) + 7, 8 * i)), + Mux(io.ldst_dual_r, store_data_hi_r((8 * i) + 7, 8 * i), store_data_lo_r((8 * i) + 7, 8 * i)))).reverse.reduce(Cat(_, _)) + val ibuf_timer_in = Mux(ibuf_wr_en, 0.U, Mux((ibuf_timer < TIMER_MAX.U).asBool(), ibuf_timer+1.U, ibuf_timer)) + + ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.bits.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable + ibuf_merge_in := !io.ldst_dual_r + val ibuf_byteen_out = (0 until 4).map(i=>(Mux(ibuf_merge_en & !ibuf_merge_in, ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_)) + val ibuf_data_out = (0 until 4).map(i=>Mux(ibuf_merge_en & !ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8*i)+7, 8*i), ibuf_data((8*i)+7, 8*i)), ibuf_data((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) + + ibuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(ibuf_wr_en, true.B, ibuf_valid) & !ibuf_rst, false.B)} + ibuf_tag := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_tag_in, 0.U, ibuf_wr_en)} + val ibuf_dualtag = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_dualtag_in, 0.U, ibuf_wr_en)} + val ibuf_dual = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.ldst_dual_r, 0.U, ibuf_wr_en)} + val ibuf_samedw = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en)} + val ibuf_nomerge = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en)} + ibuf_sideeffect := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en)} + val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.unsign, 0.U, ibuf_wr_en)} + ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.store, 0.U, ibuf_wr_en)} + val ibuf_sz = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_sz_in, 0.U, ibuf_wr_en)} + ibuf_addr := rvdffe(ibuf_addr_in, ibuf_wr_en, clock, io.scan_mode) + ibuf_byteen := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_byteen_in, 0.U, ibuf_wr_en)} + ibuf_data := rvdffe(ibuf_data_in, ibuf_wr_en, clock, io.scan_mode) + ibuf_timer := withClock(io.lsu_free_c2_clk) {RegNext(ibuf_timer_in, 0.U)} + val buf_numvld_wrcmd_any = WireInit(UInt(4.W), 0.U) + val buf_numvld_cmd_any = WireInit(UInt(4.W), 0.U) + val obuf_wr_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) + val buf_nomerge = Wire(Vec(DEPTH, Bool())) + buf_nomerge := buf_nomerge.map(i=> false.B) + + val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) + val obuf_force_wr_en = WireInit(Bool(), false.B) + val obuf_wr_en = WireInit(Bool(), false.B) + val obuf_wr_wait = (buf_numvld_wrcmd_any===1.U) & (buf_numvld_cmd_any===1.U) & (obuf_wr_timer =/= TIMER_MAX.U) & + !bus_coalescing_disable & !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_nomerge(i))) & + !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_sideeffect(i))) & !obuf_force_wr_en + val obuf_wr_timer_in = Mux(obuf_wr_en, 0.U(3.W), Mux(buf_numvld_cmd_any.orR & (obuf_wr_timer(CmdPtr0===i.U)->buf_addr(i)(31,2)))) + val buf_numvld_pend_any = WireInit(UInt(4.W), 0.U) + val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.bits.store | io.no_dword_merge_r) + val bus_sideeffect_pend = WireInit(Bool(), false.B) + val found_cmdptr0 = WireInit(Bool(), false.B) + val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_cmd_state_bus_en := buf_cmd_state_bus_en.map(i=> false.B) + val buf_dual = Wire(Vec(DEPTH, Bool())) + buf_dual := buf_dual.map(i=> false.B) + val buf_samedw = Wire(Vec(DEPTH, Bool())) + buf_samedw := buf_samedw.map(i=> false.B) + val found_cmdptr1 = WireInit(Bool(), false.B) + val bus_cmd_ready = WireInit(Bool(), false.B) + val obuf_valid = WireInit(Bool(), false.B) + val obuf_nosend = WireInit(Bool(), false.B) + // val lsu_bus_cntr_overflow = WireInit(Bool(), false.B) + val bus_addr_match_pending = WireInit(Bool(), false.B) + + obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) | + ((indexing(buf_state, CmdPtr0) === cmd_C) & + found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !(indexing(buf_sideeffect, CmdPtr0) & bus_sideeffect_pend) & + (!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_write, CmdPtr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) | + obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !bus_addr_match_pending & io.lsu_bus_clk_en + + val bus_cmd_sent = WireInit(Bool(), false.B) + val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, indexing(buf_write, CmdPtr0)) + val obuf_sideeffect_in = Mux(ibuf_buf_byp, io.is_sideeffects_r, indexing(buf_sideeffect, CmdPtr0)) + val obuf_addr_in = Mux(ibuf_buf_byp, io.lsu_addr_r, indexing(buf_addr, CmdPtr0)) + val buf_sz = Wire(Vec(DEPTH, UInt(2.W))) + buf_sz := buf_sz.map(i=> 0.U) + val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half), indexing(buf_sz, CmdPtr0)) + val obuf_merge_en = WireInit(Bool(), false.B) + val obuf_merge_in = obuf_merge_en + val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) + + val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) + val obuf_cmd_done = WireInit(Bool(), false.B) + val bus_wcmd_sent = WireInit(Bool(), false.B) + val obuf_cmd_done_in = !(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent) + val obuf_data_done = WireInit(Bool(), false.B) + val bus_wdata_sent = WireInit(Bool(), false.B) + val obuf_data_done_in = !(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent) + val obuf_aligned_in = Mux(ibuf_buf_byp, is_aligned_r, obuf_sz_in(1,0)===0.U | (obuf_sz_in(0) & !obuf_addr_in(0)) | (obuf_sz_in(1)&(!obuf_addr_in(1,0).orR))) + + val obuf_nosend_in = WireInit(Bool(), false.B) + val obuf_rdrsp_pend = WireInit(Bool(), false.B) + val bus_rsp_read = WireInit(Bool(), false.B) + val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_write = WireInit(Bool(), false.B) + val obuf_rdrsp_pend_in = ((!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | (bus_cmd_sent & !obuf_write)) & !io.dec_tlu_force_halt + val obuf_rdrsp_pend_en = io.lsu_bus_clk_en | io.dec_tlu_force_halt + val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag) + val obuf_addr = WireInit(UInt(32.W), 0.U) + val obuf_sideeffect = WireInit(Bool(), false.B) + obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.tlu_busbuff.dec_tlu_external_ldfwd_disable & + ((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) + val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)), + Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr0)))) + val obuf_byteen1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_hi_r)), + Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr1)))) + + val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)), + Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_data, CmdPtr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr0)))) + val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)), + Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_data, CmdPtr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr1)))) + val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) + val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data0_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) + + val buf_dualhi = Wire(Vec(DEPTH, Bool())) + buf_dualhi := buf_dualhi.map(i=> false.B) + obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, CmdPtr1) === cmd_C) & + !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_sideeffect, CmdPtr0) & + (!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0))) | + (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) + val obuf_wr_enQ = rvdff_fpga (obuf_wr_en,io.lsu_busm_clk,io.lsu_busm_clken,clock) + obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & !obuf_rst, false.B)} + obuf_nosend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)} + obuf_rdrsp_pend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_rdrsp_pend_in, false.B,obuf_rdrsp_pend_en)} + obuf_cmd_done := rvdff_fpga (obuf_cmd_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) + obuf_data_done := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) + obuf_rdrsp_tag := rvdff_fpga (obuf_rdrsp_tag_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) + + obuf_tag0 := rvdffs_fpga (obuf_tag0_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + val obuf_tag1 = rvdffs_fpga (obuf_tag1_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + val obuf_merge = rvdffs_fpga (obuf_merge_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + obuf_write := rvdffs_fpga (obuf_write_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + obuf_sideeffect := rvdffs_fpga (obuf_sideeffect_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + val obuf_sz = rvdffs_fpga (obuf_sz_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) + obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode) + val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode) + obuf_wr_timer := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,obuf_wr_en,clock) + val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) + + + WrPtr0_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & + !((ibuf_valid & (ibuf_tag===i.U)) | (io.lsu_busreq_r & + ((WrPtr0_r === i.U) | (io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U)) + + + val WrPtr1_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) + WrPtr1_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | + (io.lsu_busreq_m & (WrPtr0_m===i.U)) | + (io.lsu_busreq_r & (((WrPtr0_r === i.U)) | + (io.ldst_dual_r & (WrPtr1_r===i.U)))))) -> i.U)) + + val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_age := buf_age.map(i=> 0.U) + + val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) + val CmdPtr1Dec = (0 until DEPTH).map(i=> (!((buf_age(i) & (~CmdPtr0Dec)).orR) & !CmdPtr0Dec(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) + val buf_rsp_pickage = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rsp_pickage := buf_rsp_pickage.map(i=> 0.U) + val RspPtrDec = (0 until DEPTH).map(i=> (!(buf_rsp_pickage(i).orR) & (buf_state(i)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_)) + found_cmdptr0 := CmdPtr0Dec.orR + found_cmdptr1 := CmdPtr1Dec.orR + + def Enc8x3(in: UInt) : UInt = Cat(in(4)|in(5)|in(6)|in(7), in(2)|in(3)|in(6)|in(7), in(1)|in(3)|in(5)|in(7)) + + + + val RspPtr = WireInit(UInt(DEPTH_LOG2.W), 0.U) + CmdPtr0 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr0Dec)) + + CmdPtr1 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr1Dec)) + RspPtr := Enc8x3(Cat(Fill(8-DEPTH, 0.U),RspPtrDec)) + val buf_state_en = Wire(Vec(DEPTH, Bool())) + buf_state_en := buf_state_en.map(i=> false.B) + val buf_rspageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspageQ := buf_rspageQ.map(i=> 0.U) + val buf_rspage_set = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage_set := buf_rspage_set.map(i=> 0.U) + val buf_rspage_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage_in := buf_rspage_in.map(i=> 0.U) + val buf_rspage = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage := buf_rspage.map(i=> 0.U) + + val buf_age_in = (0 until DEPTH).map(i=>(0 until DEPTH).map(j=> ((((buf_state(i)===idle_C) & buf_state_en(i)) & + (((buf_state(j)===wait_C) | ((buf_state(j)===cmd_C) & !buf_cmd_state_bus_en(j))) | + (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r === i.U) & (ibuf_tag === j.U)) | + (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_))) + val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_ageQ := buf_ageQ.map(i=> 0.U) + buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & !((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j)) & !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) + buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_))) + buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_))) + + buf_rspage_set := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(((buf_state(i)===idle_C) & buf_state_en(i)) & + (!((buf_state(j)===idle_C) | (buf_state(j)===done_C)) | + (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) | + (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_))) + buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_))) + buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))& !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) + ibuf_drainvec_vld := (0 until DEPTH).map(i=>(ibuf_drain_vld & (ibuf_tag === i.U)).asUInt).reverse.reduce(Cat(_,_)) + buf_byteen_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), + Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0)))) + buf_addr_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_addr, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), io.end_addr_r, io.lsu_addr_r))) + buf_dual_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_samedw_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_nomerge_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_nomerge | ibuf_force_drain, io.no_dword_merge_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_dualhi_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual ,ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U))).asUInt).reverse.reduce(Cat(_,_)) + buf_dualtag_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), WrPtr0_r, WrPtr1_r))) + buf_sideeffect_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.bits.unsign)).asUInt).reverse.reduce(Cat(_,_)) + buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half))) + buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.bits.store)).asUInt).reverse.reduce(Cat(_,_)) + + for(i<- 0 until DEPTH) { + switch(buf_state(i)) { + is(idle_C) { + buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C) + buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag)) + buf_wr_en(i) := buf_state_en(i) + buf_data_en(i) := buf_state_en(i) + buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) + buf_cmd_state_bus_en(i) := 0.U + buf_rst(i) := io.dec_tlu_force_halt + } + is(wait_C) { + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) + buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt + buf_cmd_state_bus_en(i) := 0.U + buf_rst(i) := io.dec_tlu_force_halt + } + is(cmd_C) { + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) + buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ + buf_state_bus_en(i) := buf_cmd_state_bus_en(i) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + buf_ldfwd_in(i) := true.B + buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt + buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(LSU_BUS_TAG - 2, 0)).asUInt + buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read + buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error + buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) + buf_rst(i) := io.dec_tlu_force_halt + } + is(resp_C) { + buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !bus_rsp_write_error)).asBool(), idle_C, + Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, + Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) + buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) | + (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W))) | + (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) | + (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i)))))) + buf_state_bus_en(i) := buf_resp_state_bus_en(i) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en + buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) | + (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | + (bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) + buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) + buf_cmd_state_bus_en(i) := 0.U + buf_rst(i) := io.dec_tlu_force_halt + } + is(done_partial_C) { // Other part of dual load hasn't returned + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) + buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | + (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + buf_cmd_state_bus_en(i) := 0.U + buf_rst(i) := io.dec_tlu_force_halt + } + is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) + buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt + buf_cmd_state_bus_en(i) := 0.U + buf_rst(i) := io.dec_tlu_force_halt + } + is(done_C) { + buf_nxtstate(i) := idle_C + buf_rst(i) := true.B + buf_state_en(i) := true.B + buf_ldfwd_in(i) := false.B + buf_ldfwd_en(i) := buf_state_en(i) + buf_cmd_state_bus_en(i) := 0.U + } + } + buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())} + buf_ageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_age_in(i), 0.U)} + buf_rspageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_rspage_in(i), 0.U)} + buf_dualtag(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualtag_in(i), 0.U, buf_wr_en(i).asBool())} + buf_dual(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dual_in(i), false.B, buf_wr_en(i).asBool())} + buf_samedw(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_samedw_in(i), false.B, buf_wr_en(i).asBool())} + buf_nomerge(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nomerge_in(i), false.B, buf_wr_en(i).asBool())} + buf_dualhi(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualhi_in(i), false.B, buf_wr_en(i).asBool())} + } + + buf_ldfwd := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwd_in(i), false.B, buf_ldfwd_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_ldfwdtag := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwdtag_in(i), 0.U, buf_ldfwd_en(i).asBool())}) + buf_sideeffect := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sideeffect_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_unsign := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_unsign_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_write := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_write_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_sz := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sz_in(i), 0.U, buf_wr_en(i).asBool())}) + buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode)) + buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())}) + buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode)) + buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(!buf_rst(i) & Mux(buf_error_en(i), true.B, buf_error(i)), false.B)}).asUInt()).reverse.reduce(Cat(_,_)) + val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_) + buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) + buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) + buf_numvld_pend_any := (0 until DEPTH).map(i=>((buf_state(i)===wait_C) | ((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i))).asUInt).reverse.reduce(_ +& _) + any_done_wait_state := (0 until DEPTH).map(i=>buf_state(i)===done_wait_C).reverse.reduce(_|_) + io.lsu_bus_buffer_pend_any := buf_numvld_pend_any.orR + io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U) + io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid + + io.dctl_busbuff.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & !io.flush_m_up & !io.ld_full_hit_m + io.dctl_busbuff.lsu_nonblock_load_tag_m := WrPtr0_m + val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B) + io.dctl_busbuff.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r := WrPtr0_r + val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(buf_write(i))))) + io.dctl_busbuff.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i)))) + io.dctl_busbuff.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U)) + val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i))) + val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) & buf_dualhi(i))) -> buf_data(i))) + val lsu_nonblock_addr_offset = indexing(buf_addr, io.dctl_busbuff.lsu_nonblock_load_data_tag)(1,0) + val lsu_nonblock_sz = indexing(buf_sz, io.dctl_busbuff.lsu_nonblock_load_data_tag) + val lsu_nonblock_unsign = indexing(buf_unsign, io.dctl_busbuff.lsu_nonblock_load_data_tag) + // val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.dctl_busbuff.lsu_nonblock_load_data_tag) + val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U) + + io.dctl_busbuff.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.dctl_busbuff.lsu_nonblock_load_data_error + io.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)), + (lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)), + (!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)), + (!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)), + (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) + bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) | (obuf_valid & obuf_sideeffect & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) + bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> + ( obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) + + bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.w.ready), io.lsu_axi.ar.ready) + bus_wcmd_sent := io.lsu_axi.aw.valid & io.lsu_axi.aw.ready + bus_wdata_sent := io.lsu_axi.w.valid & io.lsu_axi.w.ready + bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) + bus_rsp_read := io.lsu_axi.r.valid & io.lsu_axi.r.ready + bus_rsp_write := io.lsu_axi.b.valid & io.lsu_axi.b.ready + bus_rsp_read_tag := io.lsu_axi.r.bits.id + bus_rsp_write_tag := io.lsu_axi.b.bits.id + bus_rsp_write_error := bus_rsp_write & (io.lsu_axi.b.bits.resp =/= 0.U) + bus_rsp_read_error := bus_rsp_read & (io.lsu_axi.r.bits.resp =/= 0.U) + bus_rsp_rdata := io.lsu_axi.r.bits.data + + // AXI Command signals + io.lsu_axi.aw.valid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending + io.lsu_axi.aw.bits.id := obuf_tag0 + io.lsu_axi.aw.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W))) + io.lsu_axi.aw.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) + io.lsu_axi.aw.bits.prot := 1.U(3.W) + io.lsu_axi.aw.bits.cache := Mux(obuf_sideeffect, 0.U, 15.U) + io.lsu_axi.aw.bits.region := obuf_addr(31,28) + io.lsu_axi.aw.bits.len := 0.U + io.lsu_axi.aw.bits.burst := 1.U(2.W) + io.lsu_axi.aw.bits.qos := 0.U + io.lsu_axi.aw.bits.lock := 0.U + + io.lsu_axi.w.valid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending + io.lsu_axi.w.bits.strb := obuf_byteen & Fill(8, obuf_write) + io.lsu_axi.w.bits.data := obuf_data + io.lsu_axi.w.bits.last := 1.U + + io.lsu_axi.ar.valid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending + io.lsu_axi.ar.bits.id := obuf_tag0 + io.lsu_axi.ar.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W))) + io.lsu_axi.ar.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) + io.lsu_axi.ar.bits.prot := 1.U(3.W) + io.lsu_axi.ar.bits.cache := Mux(obuf_sideeffect, 0.U(4.W), 15.U) + io.lsu_axi.ar.bits.region := obuf_addr(31,28) + io.lsu_axi.ar.bits.len := 0.U + io.lsu_axi.ar.bits.burst := 1.U(2.W) + io.lsu_axi.ar.bits.qos := 0.U + io.lsu_axi.ar.bits.lock := 0.U + io.lsu_axi.b.ready := 1.U + io.lsu_axi.r.ready := 1.U + io.tlu_busbuff.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i)))) + val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U)) + + io.tlu_busbuff.lsu_imprecise_error_load_any := io.dctl_busbuff.lsu_nonblock_load_data_error & !io.tlu_busbuff.lsu_imprecise_error_store_any + io.tlu_busbuff.lsu_imprecise_error_addr_any := Mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.dctl_busbuff.lsu_nonblock_load_data_tag)) + //lsu_bus_cntr_overflow := 0.U + + // io.lsu_bus_idle_any := 1.U + + // PMU signals + io.tlu_busbuff.lsu_pmu_bus_trxn := (io.lsu_axi.aw.valid & io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) + io.tlu_busbuff.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r + io.tlu_busbuff.lsu_pmu_bus_error := io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any + + io.tlu_busbuff.lsu_pmu_bus_busy := (io.lsu_axi.aw.valid & !io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & !io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & !io.lsu_axi.ar.ready) + + WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)} + WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)} + io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} + lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)} +} +object buffer extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer())) +} diff --git a/src/main/scala/lsu/lsu_bus_intf.scala b/src/main/scala/lsu/lsu_bus_intf.scala index 4a246ab5..e800d75d 100644 --- a/src/main/scala/lsu/lsu_bus_intf.scala +++ b/src/main/scala/lsu/lsu_bus_intf.scala @@ -1,205 +1,205 @@ -//package lsu -//import chisel3._ -//import chisel3.util._ -//import lib._ -//import include._ -// -//class lsu_bus_intf extends Module with RequireAsyncReset with lib { -// val io = IO (new Bundle { -// val scan_mode = Input(Bool()) -// val clk_override = Input(Bool()) -// val tlu_busbuff = new tlu_busbuff() -// val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable -// val lsu_busm_clken = Input(Bool()) -// val lsu_c1_r_clk = Input(Clock()) -// val lsu_c2_r_clk = Input(Clock()) -// val lsu_bus_ibuf_c1_clk = Input(Clock()) -// val lsu_bus_obuf_c1_clk = Input(Clock()) -// val lsu_bus_buf_c1_clk = Input(Clock()) -// val lsu_free_c2_clk = Input(Clock()) -// val active_clk = Input(Clock()) -// val lsu_busm_clk = Input(Clock()) -// val axi = new axi_channels(LSU_BUS_TAG) -// val dec_lsu_valid_raw_d = Input(Bool()) -// val lsu_busreq_m = Input(Bool()) -// -// val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) -// val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) -// -// val lsu_addr_m = Input(UInt(32.W)) -// val lsu_addr_r = Input(UInt(32.W)) -// -// val end_addr_m = Input(UInt(32.W)) -// val end_addr_r = Input(UInt(32.W)) -// val ldst_dual_d = Input(Bool()) -// val ldst_dual_m = Input(Bool()) -// val ldst_dual_r = Input(Bool()) -// -// val store_data_r = Input(UInt(32.W)) -// val dec_tlu_force_halt = Input(Bool()) -// -// val lsu_commit_r = Input(Bool()) -// val is_sideeffects_m = Input(Bool()) -// val flush_m_up = Input(Bool()) -// val flush_r = Input(Bool()) -// -// val lsu_busreq_r = Output(Bool()) -// val lsu_bus_buffer_pend_any = Output(Bool()) -// val lsu_bus_buffer_full_any = Output(Bool()) -// val lsu_bus_buffer_empty_any = Output(Bool()) -// //val lsu_bus_idle_any = Output(Bool()) -// val bus_read_data_m = Output(UInt(32.W)) -// -// val dctl_busbuff = new dctl_busbuff() -// -// val lsu_bus_clk_en = Input(Bool()) -// }) -// -// val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B) -// val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U) -// val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) -// val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U) -// val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U) -// val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U) -// val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U) -// val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U) -// val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U) -// val is_sideeffects_r = WireInit(Bool(), init = false.B) -// val store_data_ext_r = WireInit(UInt(64.W), init = 0.U) -// val store_data_hi_r = WireInit(UInt(32.W), init = 0.U) -// val store_data_lo_r = WireInit(UInt(32.W), init = 0.U) -// val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B) -// val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B) -// val no_word_merge_r = WireInit(Bool(), init = false.B) -// val no_dword_merge_r = WireInit(Bool(), init = false.B) -// val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B) -// val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B) -// val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B) -// val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B) -// val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U) -// val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U) -// val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U) -// val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U) -// val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U) -// val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U) -// val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U) -// val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U) -// val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U) -// val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U) -// val ld_full_hit_hi_m = WireInit(Bool(), init = true.B) -// val ld_full_hit_lo_m = WireInit(Bool(), init = true.B) -// val ld_full_hit_m = WireInit(Bool(), init = false.B) -// -// val bus_buffer = Module(new lsu_bus_buffer) -// -// bus_buffer.io.scan_mode := io.scan_mode -// io.tlu_busbuff <> bus_buffer.io.tlu_busbuff -// bus_buffer.io.clk_override := io.clk_override -// bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken -// bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken -// bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt -// bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk -// bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk -// bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk -// bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk -// bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk -// bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk -// bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d -// -// // -// bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m -// bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r -// // -// -// bus_buffer.io.lsu_addr_m := io.lsu_addr_m -// bus_buffer.io.end_addr_m := io.end_addr_m -// bus_buffer.io.lsu_addr_r := io.lsu_addr_r -// bus_buffer.io.end_addr_r := io.end_addr_r -// bus_buffer.io.store_data_r := io.store_data_r -// -// bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m -// bus_buffer.io.flush_m_up := io.flush_m_up -// bus_buffer.io.flush_r := io.flush_r -// bus_buffer.io.lsu_commit_r := io.lsu_commit_r -// bus_buffer.io.lsu_axi <> io.axi -// bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en -// -// io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r -// io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any -// io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any -// io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any -// //io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any -// ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo -// ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi -// ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo -// ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi -// io.dctl_busbuff <> bus_buffer.io.dctl_busbuff -// bus_buffer.io.no_word_merge_r := no_word_merge_r -// bus_buffer.io.no_dword_merge_r := no_dword_merge_r -// bus_buffer.io.is_sideeffects_r := is_sideeffects_r -// bus_buffer.io.ldst_dual_d := io.ldst_dual_d -// bus_buffer.io.ldst_dual_m := io.ldst_dual_m -// bus_buffer.io.ldst_dual_r := io.ldst_dual_r -// bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m -// bus_buffer.io.ld_full_hit_m := ld_full_hit_m -// bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q -// -// ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W))) -// addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3)) -// addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2)) -// no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m) -// no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m) -// -// ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0) -// ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0) -// store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W)) -// ldst_byteen_hi_m := ldst_byteen_ext_m(7,4) -// ldst_byteen_lo_m := ldst_byteen_ext_m(3,0) -// ldst_byteen_hi_r := ldst_byteen_ext_r(7,4) -// ldst_byteen_lo_r := ldst_byteen_ext_r(3,0) -// -// store_data_hi_r := store_data_ext_r(63,32) -// store_data_lo_r := store_data_ext_r(31,0) -// ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m -// ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m -// ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m -// ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m -// -// ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) -// -// ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_)) -// ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_)) -// ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) -// ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) -// ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) -// ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) -// ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_) -// ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_) -// ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m -// ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0)) -// io.bus_read_data_m := ld_fwddata_m(31,0) -// -// withClock(io.active_clk) { -// lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U) -// } -// -// withClock(io.lsu_c1_r_clk) { -// is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U) -// ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W)) -// } -//} -//object bus_intf extends App { -// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf())) -//} \ No newline at end of file +package lsu +import chisel3._ +import chisel3.util._ +import lib._ +import include._ + +class lsu_bus_intf extends Module with RequireAsyncReset with lib { + val io = IO (new Bundle { + val scan_mode = Input(Bool()) + val clk_override = Input(Bool()) + val tlu_busbuff = new tlu_busbuff() + val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable + val lsu_busm_clken = Input(Bool()) + val lsu_c1_r_clk = Input(Clock()) + val lsu_c2_r_clk = Input(Clock()) + val lsu_bus_ibuf_c1_clk = Input(Clock()) + val lsu_bus_obuf_c1_clk = Input(Clock()) + val lsu_bus_buf_c1_clk = Input(Clock()) + val lsu_free_c2_clk = Input(Clock()) + val active_clk = Input(Clock()) + val lsu_busm_clk = Input(Clock()) + val axi = new axi_channels(LSU_BUS_TAG) + val dec_lsu_valid_raw_d = Input(Bool()) + val lsu_busreq_m = Input(Bool()) + + val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) + val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) + + val lsu_addr_m = Input(UInt(32.W)) + val lsu_addr_r = Input(UInt(32.W)) + + val end_addr_m = Input(UInt(32.W)) + val end_addr_r = Input(UInt(32.W)) + val ldst_dual_d = Input(Bool()) + val ldst_dual_m = Input(Bool()) + val ldst_dual_r = Input(Bool()) + + val store_data_r = Input(UInt(32.W)) + val dec_tlu_force_halt = Input(Bool()) + + val lsu_commit_r = Input(Bool()) + val is_sideeffects_m = Input(Bool()) + val flush_m_up = Input(Bool()) + val flush_r = Input(Bool()) + + val lsu_busreq_r = Output(Bool()) + val lsu_bus_buffer_pend_any = Output(Bool()) + val lsu_bus_buffer_full_any = Output(Bool()) + val lsu_bus_buffer_empty_any = Output(Bool()) + //val lsu_bus_idle_any = Output(Bool()) + val bus_read_data_m = Output(UInt(32.W)) + val lsu_nonblock_load_data = Output((UInt(32.W))) + val dctl_busbuff = new dctl_busbuff() + + val lsu_bus_clk_en = Input(Bool()) + }) + + val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B) + val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U) + val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U) + val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U) + val is_sideeffects_r = WireInit(Bool(), init = false.B) + val store_data_ext_r = WireInit(UInt(64.W), init = 0.U) + val store_data_hi_r = WireInit(UInt(32.W), init = 0.U) + val store_data_lo_r = WireInit(UInt(32.W), init = 0.U) + val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B) + val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B) + val no_word_merge_r = WireInit(Bool(), init = false.B) + val no_dword_merge_r = WireInit(Bool(), init = false.B) + val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B) + val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B) + val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B) + val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B) + val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U) + val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U) + val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U) + val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U) + val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U) + val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U) + val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U) + val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U) + val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U) + val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U) + val ld_full_hit_hi_m = WireInit(Bool(), init = true.B) + val ld_full_hit_lo_m = WireInit(Bool(), init = true.B) + val ld_full_hit_m = WireInit(Bool(), init = false.B) + + val bus_buffer = Module(new lsu_bus_buffer) + + bus_buffer.io.scan_mode := io.scan_mode + io.tlu_busbuff <> bus_buffer.io.tlu_busbuff + bus_buffer.io.clk_override := io.clk_override + bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken + bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken + bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt + bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk + bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk + bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk + bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk + bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk + bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk + bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d + + // + bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m + bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r + // + + bus_buffer.io.lsu_addr_m := io.lsu_addr_m + bus_buffer.io.end_addr_m := io.end_addr_m + bus_buffer.io.lsu_addr_r := io.lsu_addr_r + bus_buffer.io.end_addr_r := io.end_addr_r + bus_buffer.io.store_data_r := io.store_data_r + + bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m + bus_buffer.io.flush_m_up := io.flush_m_up + bus_buffer.io.flush_r := io.flush_r + bus_buffer.io.lsu_commit_r := io.lsu_commit_r + bus_buffer.io.lsu_axi <> io.axi + bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en + io.lsu_nonblock_load_data := bus_buffer.io.lsu_nonblock_load_data + io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r + io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any + io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any + io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any + //io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any + ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo + ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi + ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo + ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi + io.dctl_busbuff <> bus_buffer.io.dctl_busbuff + bus_buffer.io.no_word_merge_r := no_word_merge_r + bus_buffer.io.no_dword_merge_r := no_dword_merge_r + bus_buffer.io.is_sideeffects_r := is_sideeffects_r + bus_buffer.io.ldst_dual_d := io.ldst_dual_d + bus_buffer.io.ldst_dual_m := io.ldst_dual_m + bus_buffer.io.ldst_dual_r := io.ldst_dual_r + bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m + bus_buffer.io.ld_full_hit_m := ld_full_hit_m + bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q + + ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W))) + addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3)) + addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2)) + no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m) + no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m) + + ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0) + ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0) + store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W)) + ldst_byteen_hi_m := ldst_byteen_ext_m(7,4) + ldst_byteen_lo_m := ldst_byteen_ext_m(3,0) + ldst_byteen_hi_r := ldst_byteen_ext_r(7,4) + ldst_byteen_lo_r := ldst_byteen_ext_r(3,0) + + store_data_hi_r := store_data_ext_r(63,32) + store_data_lo_r := store_data_ext_r(31,0) + ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m + ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m + ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m + ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m + + ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) + + ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) + ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_) + ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_) + ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m + ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0)) + io.bus_read_data_m := ld_fwddata_m(31,0) + + withClock(io.active_clk) { + lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U) + } + + withClock(io.lsu_c1_r_clk) { + is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U) + ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W)) + } +} +object bus_intf extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf())) +} \ No newline at end of file diff --git a/src/main/scala/lsu/lsu_lsc_ctl.scala b/src/main/scala/lsu/lsu_lsc_ctl.scala index 9c9ad2af..f7c80764 100644 --- a/src/main/scala/lsu/lsu_lsc_ctl.scala +++ b/src/main/scala/lsu/lsu_lsc_ctl.scala @@ -26,9 +26,9 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val flush_m_up = Input(UInt(1.W)) val flush_r = Input(UInt(1.W)) - val ldst_dual_d = Input(UInt(1.W)) - val ldst_dual_m = Input(UInt(1.W)) - val ldst_dual_r = Input(UInt(1.W)) + val ldst_dual_d = Input(Bool()) + val ldst_dual_m = Input(Bool()) + val ldst_dual_r = Input(Bool()) val lsu_exu = new lsu_exu() @@ -39,7 +39,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val picm_mask_data_m = Input(UInt(32.W)) val bus_read_data_m = Input(UInt(32.W)) //coming from bus interface - val lsu_result_m = Output(UInt(32.W)) + // val lsu_result_m = Output(UInt(32.W)) val lsu_result_corr_r = Output(UInt(32.W)) // This is the ECC corrected data going to RF // lsu address down the pipe @@ -100,7 +100,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d) val rs1_d_raw = lsu_rs1_d val offset_d = lsu_offset_d - val rs1_d = Mux(io.lsu_pkt_d.bits.load_ldst_bypass_d.asBool,io.lsu_result_m,rs1_d_raw) + val rs1_d = Mux(io.lsu_pkt_d.bits.load_ldst_bypass_d.asBool,io.lsu_exu.lsu_result_m,rs1_d_raw) // generate the ls address val full_addr_d = rvlsadder(rs1_d,offset_d) @@ -220,15 +220,16 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val dma_mem_wdata_shifted = io.dma_lsc_ctl.dma_mem_wdata(63,0) >> Cat(io.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores val store_data_d = Mux(io.dma_lsc_ctl.dma_dccm_req.asBool,dma_mem_wdata_shifted(31,0),io.lsu_exu.exu_lsu_rs2_d(31,0)) // Write to PIC still happens in r stage - val store_data_m_in = Mux(io.lsu_pkt_d.bits.store_data_bypass_d.asBool,io.lsu_result_m(31,0),store_data_d(31,0)) - + val store_data_m_in = Mux(io.lsu_pkt_d.bits.store_data_bypass_d.asBool,io.lsu_exu.lsu_result_m(31,0),store_data_d(31,0)) + val int = withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d(2),0.U)} =/= withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2),0.U)} + val int1 = withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m(2),0.U)} =/= withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2),0.U)} val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)} io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)} io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)} - io.end_addr_m := Cat(Mux(io.ldst_dual_m,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)}) - io.end_addr_r := Cat(Mux(io.ldst_dual_r,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2,0),0.U)}) + io.end_addr_m := Cat(Mux(int,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)}) + io.end_addr_r := Cat(Mux(int1,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2,0),0.U)}) end_addr_pre_m := rvdffe(io.end_addr_d(31,3),((io.lsu_pkt_d.valid & io.ldst_dual_d) | io.clk_override),clock,io.scan_mode) - end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & io.ldst_dual_m) | io.clk_override),clock,io.scan_mode) + end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & int) | io.clk_override),clock,io.scan_mode) io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)} io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)} io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)} @@ -243,14 +244,14 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib io.lsu_addr_d := full_addr_d // Interrupt as a flush source allows the WB to occur io.lsu_commit_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.bits.store | io.lsu_pkt_r.bits.load) & !io.flush_r & !io.lsu_pkt_r.bits.dma - io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,!io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.bits.store_data_bypass_m.asBool,io.lsu_result_m,store_data_pre_m) + io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,!io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.bits.store_data_bypass_m.asBool,io.lsu_exu.lsu_result_m,store_data_pre_m) if (LOAD_TO_USE_PLUS1 == 1){ //bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl lsu_ld_datafn_r := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_r) lsu_ld_datafn_corr_r := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_corr_r) // this is really R stage but don't want to make all the changes to support M,R buses - io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) | + io.lsu_exu.lsu_result_m := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) | ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_r(15,0))) | ((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat((Fill(24, lsu_ld_datafn_r(7))) ,lsu_ld_datafn_r(7,0))) | ((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat((Fill(16,lsu_ld_datafn_r(15))) ,lsu_ld_datafn_r(15,0))) | @@ -266,7 +267,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib else { lsu_ld_datafn_m := Mux(io.addr_external_m, io.bus_read_data_m,io.lsu_ld_data_m) lsu_ld_datafn_corr_r := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r) - io.lsu_result_m := ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) | + io.lsu_exu.lsu_result_m := ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) | ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_m(15,0))) | ((Fill(32,!io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat((Fill(24, lsu_ld_datafn_m(7))) ,lsu_ld_datafn_m(7,0))) | ((Fill(32,!io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat((Fill(16,lsu_ld_datafn_m(15))) ,lsu_ld_datafn_m(15,0))) | diff --git a/target/scala-2.12/classes/exu/exu$$anon$1.class b/target/scala-2.12/classes/exu/exu$$anon$1.class index c9dc09bd197d8316cf354f819d696a43405ffb30..f8d45123ff358bf3e2256d53ef90ae56f4e31fc3 100644 GIT binary patch literal 3262 zcma)8X>%Jz5Pjn~StK@=B3}v4ZH34NqTC@kA;DJ=*m1x)2qcJ=c5N?S?~2tb2Uo&< zhWq}?9{?A2sz?=;Z&dMD_zx6scD1s!tf{C<)3e?Ex~FHld*-iye*Xi&LHs0;GOpF~ z{AaV8?bz9U3WPvMdCsgF)`9$R&DJeL!5V=CmG)H2nxzRSb&!H}0{cVdv1=8}ESuhl zvrsWDW2)krj$O^RevVjLwW{Dgfvx|KQ;-zsi~$RDhscUnp4VoL?6BilSq1AEPDG?2 zC9u|)$KcKtY>&7MRs3nwqC(R%uCqX`v(5!m_vRFIb9Y*K+!}6+U0iT2&5arfJ2!)n&OOAtIic?Ok1;>jmzayr9-Od z=9QvrRBM(epoWaAu3=NImu8FQ1-*FH)isYNmzJ)}Rk!Hsl2OzJdaP=#$g?k5PI7K72Blnpo;Cm?68U*!R%2LJA>I{D*A)j zF%{Wh_IT@R!jM($!h_P{6DoEGnj<{GW2S9-gs8bNs-c1NV;Ad)#4cn=j_H3XkkeqgEZrK>;{YLS$ybcSt zMRx^z#$g)!9PDG4Xy*-kKQglWah8#-%%|*GK4p9IDVvi|*_wRH#^h7BC7-e>`IODa zr))i>Dg-U(IDW~mJgFdEJNO$0f8nGJUvXULGdu7#=Mq2#JcNfy1()*($0#@-1*c-c zo3S?rygv#~$AY)wKn(a$6r70#Z;u5ZiGsUg!8>BXN2B2GSn$qR@K6-o8w>7_1s{)s zH^zdqvEUO?@TOSsE}V?n?cpf6FBZHz*7Il-yd@SqhH>U0GfXTp@7hRD4=!SI8PD9t zS>~ICuv$7jMH{LY~ukPOT;Er}`_4@D_2seHpJWiXFpQdgEWq^_dX@xV?g}G=8!~`3RQ-b5HQabyDzI N#u=NPz>l`s!A*_m~AmctWo zjThb@z%QUF6RM=j;y*GCxK4u zMlHvGHfy?`n;p?01Uia~cGYqYuO)tYU%j64)|ryG5r~vU2q;ayOAvn5zh+8_aNrJb5*Rd8bxgEX>=k>9ig$&80|( z6e-!)3cgjXIe~x?ZCv*)m;BP)LZMhL6|VawGvLjorRrkUFZd<7Q7F+sr&@~}Sl^I?O!2PUO3oKt?S9ICyp4v8JnOW;j)8{iwW9RLz&K`fwBalhCUPk6R%)^~ zUXZD|c2gO7E`?c~7wBy;ql!_*rerRr(190OTxO->+%#|*`*rTTBt2@tCYgp~jaA&Z z21AL-BVN|2_!VABWR%pW;Z@d4EU`4q32Yn)9W3c6Le^&_6lRx(1s#i$(dZmAwIFo; zHJQSZmin&p%SquX%1OSfE}~?-6uKbmIyxW04ew@Nb_@w2|>V>G`GaXB?bh4=>)hIi5 zl?l~gJJ~<1Gqv)Z<)1U>9Nt`J+T*iy!Srppu5YGKTfw4NI&1o7*I#ic;=RKye+QA6BL>r$^9U0m4ILpWe zrYJj=qHIcvvLz|XhNLLlk)muyin8e_%9caA8G`io45r zeHqufvGV2|4I5bRZN;rl#Qq|G_A#;o}pWek1 z?f*P7^ox5~TEU5?5$Rp)7<%&8Mj4K>_+$af2dy8S7)BaL*a@zn8@JGdpV^-OWHtYd z?V=rhVvw@8iP#!Oyk4@5JtpxbGvOQZ+65-lX*b)qm9XxysX%}fX=~mKS zQeGZ^TksvnHfS8b=YIo{Kah^`OMWxo_6fnypi#ama$t)P{GiGSelBsz>fuMP9GFvr OA3?`e3ljK|2jE}7g1EE* diff --git a/target/scala-2.12/classes/exu/exu.class b/target/scala-2.12/classes/exu/exu.class index b1eec122f6d6aab1660cbc5c0f27e07ae3dafc2b..ffaeaa3ed95dd10299f1e20122b4fefadf1cf976 100644 GIT binary patch literal 263741 zcmcd!2YejG)!%m7y}OYtxmS#gY}{o@u9A&8$+9h5F0$lqb3REY`D`_-xPWm;NJ3}{ zp`?&X;7cz+2sl6zNCE^15CQ}Ukc1Xe2rVIv0N;D_X7_eiCIVWxCUeoJEVNVS${+2rQ(!n1(8s&->s`9(cw0mlm z+NVz#W6s`Q-m-P=s=~xsi?tyMwxE4`$?nzDqlsc&JG(DdQnzP(+5W8~8}NETWZz-1 zvox+BVkPR1c}>G|qtU`sHDl|P;ig`h(Dfmig49_NLm#$iYGGu0OVg&>(~Gwi_V$#I zKYhlw@|H|aNn+}_g?ln*PnuMiG78K{wOY7L-J@^ZH)__7d7bO>&S}j%tL#u_=$=vS zW6HZ~s;7foPC+!1E-0xsb$vlyqOj1?PK}hLW^Y}vXXhymC5462gL+{N>hbnJ-h`u2j#!W7fyk0~iASfQ)HC$#+XmNip)H_zHp)|ojwR#Lcq zVPRoGbXs95FJ?y4-Ro4NYHxYbirHf$as8a=p{kNZM2nm|w6LnYxvKo|rjGGtEiA=}Dg(a6qW1#!)h2RmD*2s?GPstNIMuy)L%k&(!`I{0U* zUbQMwm>Q#Ph?dmlCM$MTS1v1@lp3qeiJCP9iNrj8$ux7$S#w&qZW?cOjGns(+H-SN zA~B!Wvv54rb4l+yRo^tMyvVAoN|ftKx*_g~?Bn)orp!H9yR)o!Zz;dNID0+iTyHz2 zyk+O4x`LARiO~^ba0NYv8S9hcg;-{otFHxt=7m zS3q3O(sivUr*Cp9F}X97lTlZ1JgvHLioPkcaq{-K7E>F?&g)s)c(|owry5%~Y4|~w zoYUEA=MQz|Z{zuODU=_|Qj{9Q5>@j`mTq7RW{+J6_1;>Lw`NXX)$EzA9iz(%^;wzC zLw3wLP*qyHqJ8udZOpuxD?3InZrnPh=m48oppBSp^wyqL(q2FG@bX!SoIR;?%SPw! zn3rBU)EJgRyRqS;*X$_GENx_oN#n-ss$RufJI2i0wNHx`oCbVq)yx&MwwLxTEuVQ{ z$j&)wXop3)5kp&*vt(4scIdaGu%FI7s25CISv+n5#BKGclCfIOENGX!vC)V=F*a>B zw9l5D>eC91MLnyB)-K3BYtFvS8xAioR%3uipISV&Y|n}fhg)WETfC3sS_ZhrHgE2n zFmG2XrwHP;Oe@5Cj9sw5b<*LS;xQE&luMvo-JIm7b zc|`{q;7vppVSDXM9T_%S#rjqn2Wux3XcNF5n^4|TGiCgW&e4l@?aMjD<MaO6dcSkBG+Bj?6!p5yf9Ne4oz~1Bp;+WH%Ts3@4JLvDM9Dks8 zr#c+l58}Hky=o@byEBz{c*>9(b+nChY2M+}0WaX6VGY??hJIIzM7z86_NOXmp5BT6 zPSlvKB3@^nvS{DxRp{3!`gO(Zv&u6|HyKv(*z#R9;6E)nCtbCH!FaP!8<7IJF%^wV zNA{YNRr3&(v!ZzGoR*zO;-gPbczLr%&E0q8v{AWdmF!wwet6`%HEN!R&n?h~)j0M> zC3Gkc`eXZ+vd%;#RR}m6GdYJht=TcBI~~b*c{Qd2uI5ZBURPuLj*MFY@!PT!`a|W; zY<@bMU#OvU}u$eq?T*L zQp@fBl8sY=qeoAn9c+ig^V`Rl_pFBgBjO9=btK?v$=y-WTX#esoqNi>U5?(?EPfh4 zMI5iP+ZFoxwgvmr5o*_^8)k0Kn=rOeuR*=?-llVhjmqCy(%X7u299Ui>FCd$<)uqw zwN~-g@?MBn?&ryrU*^f*rVa;OQ#vP%-BsOUjBejqj`6xYw?-Yo^LN5{Ch~cFg8dnO z`_vC$oG3)U_Oz}#d&;bdiyB+kiufMN>M)+tYlrvNZe6mkYVCL!XXrjPS&cxy8@8}` z4aDVSyFRBu|DybLuKe`5m~VE#{d3gXv!I;iXG6dB@_;+1{zx49aa@mV)+!4NBYMZ= zF@^iq&eKQXeQHZd`(EBJRFlh{QlO2Az&JU&yrp$hGmK+Pv~gY@;O&4vf>F6yo zm7%IK#COS5hQpKszpg5$`Ysl=ba%FcYC~sj2Ie_ZZKg6xRr3A0E~s{aj>zUrbMJ0b z8LKLJ-aLRJW>kubQXQQgMJ1*(K~*O2N$pP+x1~B-VQyuA=iYSjnso2(&gPY=j^?&> zPf=}W=ia_9Q<(^b28)_Xp{nGNys8w4>6oJK{Y`CqcQeMi^D=&W<{D?T9PeY zttk*XT~*@U`<)Dc?Ga0Z$aI+P;Ua0UnD4oq!RxbB#p2h2^B@7MnKVkw;YbAQ7ir^0 z%4`v2Rb{BBn64%+GhbC=ydci|?R0fvQHyLl$g0Y4kDVU7){9kzaZ4fxV#+JnWJ@kp zm0Xe(SsrYiPGeVcY&P$~hLd4EJ%Fv6V-u{ZjPAj?uj2LH>E?7xQKGxM^FX4fr?Uwp zR{}owRa037esYNb;Eq&#rlYm06Q<}6_7=6Lnz}oSN>pV|tsUjg<;ON%f-N}Q=jvfejM*+JRi1TaB z{8|LXnxRQDbCSKOz3C2Q;_ZEH$^EIeOmp%eT_OfAfm~yEs-tN)UMc{t3tA=9)SK)` zALv5m;ZA9Ny_vS+O=t$noF&O#T$|}=YU^uG7u!a<_Vy-wE6xDWyvMbfQ z8x7~V3gac2n9-H&_Fn>E`7Ifk40W)zcR?^<8Of&3?rxaPOm=iNq2efE)5-6HXygr& z@09OkMGq#MQ@yEVy2IV3m7Se!=mO_ravwO?&6Z*`WmTC&C-=c6>tM2}w~ZUMx*alx zXuC39X{@=gEzl>2;tqw(W7G`W##b}609oXH!DOA!TdgcBgy#+IlgnK@@b|qSzmVD3TsgD8ns^MUrUl zvP457xu$wevbJU|^vXOjq2AEf)s~(M#cuIrEUwMoM%Fd%fgr6ISPu3ct0C2z+}zm> z6(7>QUkqgJ{6_(}ztm=jP;m)VKu(O2GC6SxYqINW8>z6O#7d^o1@*%lq) z5_RrnAUo7O$lJmry~5%a0Mf%e1HCOi$|o-F10YW~hIElFS>TmS7lBM3w+Xi|TWF|P z2(Ew>w34_x+G6h36qg)1ytN%e4lg-!cq=`I99{xBXmv2oZ>P4PyVdP$AQ`V**^o>u zTecy&5^e)ou67-u=hrrDNNi0mt6tv#H?KU*S+Np?6ZI>TIB?k+bStrtB{E*wQ0X>o zb7UAfx8Yoru53uGNG@Mjy9`|5@MLW`@_4B zN$>SC-}N$n-NIrCL0;v?n%ZT_#L7zOpbgMLVyTBST)&|K z8*h1HV{HS3IPc?$s;cVxdfqnh0M#!KTD4yu42S*l;K{0A9w6zLH&2oWPh9=v7C=XF zV#{^ za|AJ$TFkb`+f|Hw!-X=>qvmxN?RG&-h=SX)6|`M8R9y5rO=OZ?tRoXSwQH00+p^8V zy$C>|rG^Lz%!2BnUq#NkwY5-NyI%EGYnLT!q5ZQ0G@#i?>KhUbFj7&~Z7m#$Ma}JI z!>nw@ZO36QHiYdIfU-VOwVG#mV;`zyXJ8GXc$>{yjZ!A>A5a|-u-lC|sv)mDTq8XZ zt69Dg;#?HESWBedD-4562yU9*#Ty zyfR51jyrxi9C!SAIPUoKa2$8%WykUUxj2sZ&&6@Pe=gvZIxu93H3?Ybnz zJEk~*0*duDRmsw-tyQ(abjd*KJq^qXyTry9Sq|;epFF ztZPWr;=m1_LlX{fw?f{AYIxvlfF3U%lcES)^dXoK=QK4%OmNf^4K-`3HzaGTSAhL$ zxDDlR*pytpenld=ZarM${n1=jvnjc@dNZ^&QqUOq&;<`<_Lz{5OvAe6%j*#Y^#OM%9_O5n)S(Tl|B}xb=+5Bpmwv+f^K%XmtF5=p?TfH(4<3g5fsh;6;T55 zGHa^q{fy6+R!no{*z2Z99v;l~gE;Fme5zYWyy)et0O3@cN9ykD=*_gJi|c#4` zRjREj)z(%I^PZ*($fAv%oxMH1-Kj2Bxy+3qV3yMTA_-<;GRmFfQEWKWl@7k>hA&iY zfE7$_P&dZZdUex~92MLgNp*F#9a5DdsPyq_2g+O3Z9^4B-L5JI%-=LKb*H)(t(~PR z<9zBkA-AEgqXAl~$W(VhM6Fr3Y-4S85v+;x7v+|PQX18!sG3rnVNw>R0+Nkgmf8Y$ zx2{xosyz*JZP)}o+)>+I?j#2@b+?*9NPFOxm3?357fluB45F>+Uh=rAoauItX!rgm z-REG&n(7B+{TJ>tZiK*!!h!1F+u;u6mIhWx1Jz#|?oDoKV1+bL{iWfqWj3dqk`RlQ zda+j(uTh%-)n65EZtjAB71BWUmxkM(TN+p)4OD;Wg050?>0BT^8uwu030r9Q_a zZ!1V0U+Qx_^0tE1@ufb;BX2869bXFWbo&8$TS4mSQlF=hw-uzGF7T zjl8WO^>mrf)5zNjQcsupJdM1qAoX;a&(p};3Q|wc^?4e3p@3w6PtWyv8hKkm>gl;Y zPa|(DNIgB*=V|0^1*xa!`aF%itswRET%V_rw-uzGp6l~8^0tE1({p{EM&4GCdU~$U z)5zNjQcutIc^Y|JLF(ywK2IYr6p-xi>3QHzv#qC(KigZ1<2b9(kPhkivr|r1!)w_2X}hvko7cPl2qE~>G@etBPme; zcjh%WwkDg}o0A8+@rQ0pTjMJ=>;3ss@6Y#nA9=f8Qt!|Ac^`ROLF)YlKJOzh6p-v+ zuLVBuBX286y}!WcedKKgsrMK7ypO!CAoczNpZAfs6{Ox@;PXE6wu03A3w+*3-d2!$ ze*w7D9bd@X3Q|um@Oc_}TS4mS1wKzBZ!1VWz0l`r0zo!@ZJdM1qAocVjpQn+x6{MbCoOgdb~D_GJX1ArEo#rz04-C;h@iE5v=Ho| zrQPN?12T>opk-z-PMUhUlikgHr5B>P!*2#;95X=6%s`0b;{=<_RI{bs<+lW4jwPUF zmLPUUpru||E=Kih>pTF<1-mWnKEFATb<6=RGY7%sZCc21bbyxWKs*^K?wDWuwc(PZ z4YW)fg3D;++K>CS;gX{bv`iZ!EsoWP<#w=o658--zY&mdi~ub&0ukq}G-NnB@^CD{ zaD+lrU6%HOPaUt>>PSn9EP?Ry6p0y*jy(2CFs{Thzm^tDd)aTo6?Z5rD;9!ih`Seb z_VrrY>wZJ7uq%;=T?vFwo@*&AxARZG9ap@ef(#IZ6fSiaq03juTH0HFL#`k!kq2Q3 zM3<-;Ewe>Ly5cwFibvFtA%Z~5#RaCgez+^i%|!fWT!C3456lt>wS2x#)n47pEyetn zT+xXtGC=<5EOA9A(h?nd*INd2zhlukQ=?X`j z@s#O6aOL3YTNp-l_`bob?}|d40F~)u6uNH&IPd9HQyy_R(+Opk@-ip;^<9C6g0eCp zY`kT$01xQeV{uH@d)2ccq`(HEu3|gS%Hx8>bT+wCthVb7*BS| z6eE_t!EeVEV>llxvjc(SE!!1UI3+97fmreCxB>}hWo0`4K*GsbCn)5BgmbQ*axlZz zL0VD{&cJ$gT!DlaWjYWYUL9BH;0&!y2Li&YKk zmXw22vR)lm9Nn+C>2Y69djz11?veqd_9tSuD>n+C>2Y69d zjz11?TGlB?9tSuP>n+C>2Y69djz11?a@HwF9tSub>n+C>2Y69Z4o<^*bTGp%2Wgp( zKMrt~*3ps20nW>M%W=g4UX+#Nj{}^mb;^;)0nW~P%W=g4UX+#Nj{}^hb;^;)0Zz<% z%W=g4UX+#Nj{}^Tb;^;)0nW;L%W=g4UX+#Nj{}^kb;^;)0Zzzz%E1g<2Wd$;I6dpt zam4{%l~fHn>G0cqyy|ZcC@&V`O7$%{2I?1Xi{x%yj_@&Yfz1#8?3$%ouKrh$}h9NU+vt zOTq>QS$O;l@hl?oadXTO2Aij6Z92$hYRnjGjKk8#!z@6mr>(Q2m7v1go=LnP;VNdF zY80Z*BoOURcfpF0~Q@ z**$z}%{Es9*q_+zy(xfirFJ(adtrevxFD+pg40?qMo-$h6GF`CB zl^11y1D`sWNjB|Hb#$cLdcegIlmW}9c`Zw&nK9p3fcA0lK!{mv@RQBd{(xWt&npH6 zjn5X;Ux68mjU`yZ8Q?tprnxFn3$t#{x^CyA=54;L_xH1AQ8J(%lSONyp8ViP&DRA3Jwsf{N!?M|a zc}2`vM=I+@v9KPyTY$|&afb)ddJ=6A)xw<{s9H09{r5QiB?q-K5b8RZ5ars&pt|$2 zE$cPp<+6Q5RDPSW9V@>B*9Y%U?}yL(VM%?a_Yf=qZ`zAcx07Ar#$00B8#0i;v=V*;~(bZCvfzon#D=}k&A(D22Z&0 zfG4J9J#idl%;+(CvGx0S3$*o!7SLhF7sj{l{UQgde~7AoHjEVA``c4JdtpPH_Ec{Z zbdU1DIPzA;=YAN|&=w@w7+w z(A3${l4b{9$SOXBVdklCKjv>s^c?S}dO&NkjB_!EhpN%s@@Jr^_DAP(|Gj@51>})0k;Z@XMKjnzS z?}}V}W!7~;F(J9;y9=nwhu$Ys**+~P)oBCCHSF&i_JJI%J2r#a16$BEr<m>e_m<%e;*8t4;qVXkk-j{hN%r<`#XGw5eb-V;Q;FD{~C)YXR1dfY`92q#`ejP-V z<(Px&zSl88W|$dYH@<-t{3b`79m(M-ihrGFKUPcHvBuL_II^z}j254KU`U|bp~@aS zP-Xa9OKiK69gadEW5)N4>#>$Mz%!5EDr`rUf=z3R;KfIuIt{+T9(zm)K)|vHrqwXx z2gc24_ZA+ExPb_4HiUpw<*Z}1#lS`!XgrTA@M*oLHwn-75qnnz+TBC|0I025s9s%% zdw-xX<44Aiu@!y-dm4B_*li21_M?w+1v<@7sS$r>HzI7;A{sIIJ~v|jRy1m>m&3y# zZCqm)42`#Yuo}+~ff>Ir?#0%-&u%>jMZebTe+63a0cyPmkEsrGB-Hr*)E9vI!=(Oe z{)E$eptGk5HZ+7cv+n&i1456{u=X3KT%=qaRW#!Xrd+CQKd7 z_te|YFREb5mC99U^B=Z*Xe%eL(SMTBfAMAqW!j_(+~&7x@7~0ePbr^9vv1kH6<54= z-zK~7@FxVcOS?JYi=W#~*((V6Gs-JtEs%$1!AXtZfbkcZoT^2^CYmtXzZUPO;5lw%6RL zWUkOQ2i;L(4ssFQSCnhf++^DvW_!(@PUfca*arN#ua!TxMK&6|PWeAHIFrY=o$s|c zn=BT?m&VZgMffiXuYT}3ce03Y+ ze3z)@O!*#BE17aVQLC7815ve1xsj-~O!+=h>zQ&BQ5%@@1ELz3ax+nY^cJGFFy$yw z+nDl0qINLlR-(>g%56mLV#@7AH8SN#L^U(z$3(R-*?zeMB8$%Kb#0$CO_Z^&zG_ zK-7ns@*q(kWy(WDeT*r;BI+WhJWSLjO!+lYA7{!VL|w*|M~S+eDUT6#B~yMw)Tfy8 zI8mQr$`eFg&6FpJ`aDy9OVk&c@)S{DX3Enen-?-neuz0zRr|C5cN%_ zJWJHKnerS_-(|}4L|xC67l^u%DK8Rr6I1?3)XhwJiKwGY`4dsMGUd-i-OiN15cOlG z{FSIXnDR1FKV{0_i26BGULopkro2kjFPQQgQTH+Bb)tUBlsAZakSTvB>Q_wp2T{Lf z%9}(z%9MW+^&6)Ai>N1<@^7Mk%as2R^)yrdOVsa}@)l8lV9Ni9dX6b?6ZHa9-XZFb zOnH~6Kf!2D)L)pY67@1uHKJZ&s!r5vOf`slgQ*ds{=w87qW;NLlc;|))gtP@OpOxt zKc>crdWWfTPUR>}WkhLA%_YiUY93KJOdUd$#ngPFVsL5>QH-fWiOOT@FrxCAI-Drj z%YFn=!Q^ycBo~dJrI)$m@h&q+2n*hrxCT7 zsndx%gQ+u!I+Lk0iK=AkETWb%bv9AUnOaQLN~X>sY86vUh^l33DN$>gT1M1*rp_g5 z15@V_)xgyGL~UZ~0;0AsbsMW*K5Veb`i-~Gv>Jp-wnR*6MElgcX z)NZDpNz@*uCWvZdY9&z}OsyiSi>b?q>Sk&+QN2uEPSk#;t|00lQ&$poHdAYeI?U8n zL>*!3YNF0#YAsP868F$9+z=&u7v)<=(zcRx$Kp5IV+qx+BcUmH+mi`p_lhLJ$;S}P z?oCN@rv=F2jzJ_f@fcEB2`PHmeMsz_NoE3t0;`CY{8i*nCH}SmL1&jtDl||mTY(v} zDuOlto|?f%`HpM2)n+I$yUNFc$gSbVoFS~?ew`u2a2wB1VzxD@>!Dq;Ehh~%&t9NZ zV4&)L6Y7LMM-k1#3p}+b?;9XUbG~PV z9b;QyQjk?c>~LGkcMB#lne&C1vxzWC%3{tfX+Jp}PtJaHkPTdJd*l~Bfpi>@e1l>F zDH}R%qpp36k6(9tJ7bazz{P?_=Kko!rf~ zoE;4E_OYeB6_Jhae0$#P9aQdOFz1fyV+x62;5|eh&R~f!Ws5v!d-!f)$3&lvy<-A9 z-d)bwX`5Vh%%ZY!DIFx7eYweu)Pq7M_^#yI#hXk?$3_3<-r+?99zNaMS>vohz{96s zG~nUWFBMtDd^3-2A;N_{muxMZD;N^-1!W{7O z)ZcQz%Ts^hfS0HK!T~Q&Zee^M2zYt&i-wF}v>GygQ8Z-yqG-tYMbVJ)i=rXp7excw zwcjT2G%lPXc@}{k+i`Dr5|9mPxTQO7lTI?SA=XOshNfA}clt!Y~GNp+$)-$D69uaQ-L>Z{+nLg$v|?eKnX;Rx ztxU;~!gi+Yp}d_;*-LpzrnFIBiYe_xH8G`wuBMsNNmMISx`@g!Wgk&{nbJ*EJ5zdy z>SRhUQTv$EM^q0}_7l~|lmkQ^V9G(F4l(5rQRgt_Y@*I($~lDP157zg)CZYzE?qsJ zDMyI<2va^l)CEjAkEjco@FX%shi2juNBfLqyU9%RMnC|I zuFUV7H+eOnsXQ8@=}hyMn0eGM46Wr67OiKRx5docQFunSZuY?rHESf5-qF;HYq+z1 zJcgp=9PA2a-euk$16%jNK_=N{!Cp~VgN8o6H>MaStf!5_LufJovDh?!2@r}f2w-t< z9xd+WSGdZ9=0kDw0rOYPe9*iG7UP<*9M<(gr{sH6DCa@*QTVvjd<>3ev75^ol9wIA zLAi+zA+GO*le>#d^Kn&~;Dm3N5_oqpO;}rN zfCwx-TSx39xi!_}HD1%Vzu1F#fJ1r1As73?ftACf+|4fHs0NpMnqRg~ ziCN>ViJtE*cw9TpbL=8&ptS6FB>s`aF+kk}&=7L+6c$A>k9W?anzb^%>fDf3uR|xKRnahv`S-E84l=0 z*|zuf>8wRCxYe2$1B3G|Wjh2+e>kSK$WqR-l%%EXvXqpiG+IiNr8HX#bY~0h3j7=+ zx;1BSA#}JAv#P9RG4nO6nyG8xh$%(0RzR#~#i)CjRt*fibjFpcEOI+i^dI+WPIi~- z-^-Y_+NzDI=UHn6vQ%FWfW&q8*&>}AHw5ZBYkkc8i3L44&u&b7T50SuE%09q>GrN9 zoR!Y3jb>%cYOr8|vC)|6?SWdjIs$p$+G1^uS>+bEH3B~A1+5)s8F<6msVb8L`&uoW zItB-jL2nylC9${dg5I`~S&g8tjJBHKHdWNr319Z}_geUd&Gys#6ULjEm9|=9))cFi zsUIXqWuQ?SyOTY=sqWrny1Toxn^}9QIN7WC+w6CB3w&xet%EV^5EQHIf(C~8I0x4F_tNLY%sQ70!s5A$$l!S}Qrez^&)o35 z1Jn8txJrEU20Xn!xP;(yN0bA1f7tp+%sSutD8zaH>!$TFxR0XIX8e9S-NCGju=oot zc$UqjyT*FhLNnb09rRKhu|0XbYkneXecXZv+E}K&t1Z)%>BTeIrby!19grfPnRU5! zMGW+>3^nxOxMW(Ng4)`l;2oPx3m%89=1$nmm7fe(=i1%jghxAi-?6T?K8G>$c}sz1 zm7gFFeTk`;6Lk%Z39gpLXW9y;U29#7Zn)0pOSouSUxl_tAMibd@!)!9eH|m`Yt}dL z%l6J>Q3}62a(y`G{i^u=s@k`#Z)043$5LRO=v7pq>zVo)qHYA}h!Xb7h0onPnsy`3 zng=l{&a_>>}BdT zlnsyA*i-Pei3j*y1o>`Dfi8U=$=qux?eHRHM-{(URHb?$=;7&jm{S!ep9lVfQR@Ng zA*OzfY&;AGaPwlZ<7^9VdH^l-2o?7zQ@=@azrmiEm4l-Q(+5%T2@-sgsox>Nr@RIm zai3dLFyz3#u|VI|f(6{h&gO1}+oz>3y!}Xy@_fk1=Sfmn@}&MW#pa z>D>AYOin;WfO;9`5FpxtdId&&?7Te~-m0=bTiOZ7km$UxS+8RZy@4Nz;s!g+`iFTn z7X7B{0hPZ)n-)Ab58-ICAE2wsruPw3)-E*if2{w;t$$l@0kS6CRlxgNPv4_5>uu{D zMEfpNujermg^vh^@WHOg`6iM@b$sw&5QQgf*O1}ul->cvg~W+<-zTtK!S&>9yEdAG zMVXcY6EP`%H;cwtWPD@-;EXbuccQ#Jrv88s=QH&vQSfkW;3ETz4#$u#i;iH%Xk!d2 zj#8DbY)gv?xnn_-q4(C0z&rY!%|3+N^L^^pC=^~E9gFwuRu(ZM7GjwIvr{}$qZ46f zizs;DonpPg)Z3^gMXFMhg&Wk;vR2I^aT;|BOrk_jx0EiJ1)~zD!wecxGnx8hDt5M| zz@%3_WtYIj8t+EYGN#^10`n}T8z%Bd0KRqjIc1ky3QUouDSHW1@1g9ameLFJm6Q$N zIowCt%Pa+^(Y8|d3Z_0l*)^83A7=2V$XcfUin8GwhewElZybI@)CL&wa9B**J7{;n z4(|t9v;k~d7e+V2hcND)PfobAQ!`puM>m6;qFZ1Vl2F1o6i*VO9hL$Uf<08HBvYTJ z>=ZM8XxxfUhll-xFc(PzaHIb{3GB9%Lri^+7`Vl}NL0I}oDEZ_Bn>`0n#2#I>(H9NjM#W>9{D&Y;K|QKFHL+QhDby zeFQ$^Ul{!eQ(vLH3p^OS9qGMe;QH{w6}=EKT*TDZsgz5Y`VXQ$&eVSq1rL!U#S;eZ zCEj?bE7j8j_iVW9MK1^F0P_l_{+EQW5|2iWscshiG=Fl5euk-U)77h)rVs@WYUeOb zC+17;5=y-#Ttg*%g=sk?d>zxGM17TMjHs_$3i!zT0=uT~V9ClNGy1K5FR*k49~PqD ziAKL2{Vqt*1GM*+3Ch>wl!x>hSHCeDy&?L2xU-W8Z5d=n;kj$9_mLcK+MNdyJw2UG ze6A#VOH`?e9%b4P!hb6~3}r=F^mhLE9sLp0hLQkmRbW5m!5tE|e@H^}-bqdKQ~0L3 zs6Ers*HhHmole2qTM_I?14jqL!vlXf$i8rj=X=*HsPhKvu0aKh{ychD3?Sakv=M~h z7fc&X6iie)FFxX+H!}(kWDFUBuAN061a#2{q7N}`0_i=>v{Q+C1T5eSEj(`tc^Gyc zquTt2X{V9Y6HJ>z6wE5Zo4Cvk@Kn<;dqujVp*yud-Q9zaP2i`k(WhhJr)S^`@qWTJ z__B*r=TVrLoFOU17H~a3(JMBXeKrQs^PHue%d{DU^hKu4Ch8@ol@Rr3rp+bluS{D& z)Zds^PSmSRTSC<9OgodPzgx-?`00a&$A7{P9?&!}H2oW1gW=JquOrocC|T49yI8U4 zfBBgj= zV)>+1z_ePD9mcdeqDJ6d0qW5}>}XfSgDxL#Vq>WiUj#wyAdAf) zAT!~IC!iE9HXD9uPkW@KYLDfhjE5$i{vP^G@@4-}EJ&B(^RF#?~_}L%89ogEuB0EU3-# zfg}1rY$Ma!NCxJ1`RP5hu@=tzw6(F=R%lD>!q_&Zb&}W)rgal_mS~K9eW|u2T875h zMdB%ZCWMi;k0hI!c95tRrkz97Zl)a}Y7f(B$|=^yG@4h6!5C`d;XnOCOk_fcb;b5! zh;_R{Ok6Z$@Cy?66K23}U%OLXEVdsi9P5i6U>Z$M#o%qw)hOKI=TM^@W*W^m#f~uT zQbKti(=H?GLrlAZs1GykQ$&4~X`dzPV@&%zQ5P}oOGI5_DIWxwwlmjsHutr`ynpNy z@MhzqaJ~*IwGZa^*deY=1ct^cD z_SG2p=xde&yBK_k-1JTSjrNO7`wDseJ20NuF30|B#=gfinjneY0I^pDZR$Kdu-Nxu z0ycJi>?Wqs?mA-w=j)fbYr(Mjb0#QKY|4g{G~GX6QuccWix|x5(2NAK@9&HR zS_H>G5_=TJjo4#MqnD-F<4k*s;5^B+KM?g4)1D^^9xV#&I}ffefN6U8`6KpwrqLTj z>{+-ay6#SnOa;?kh`~J0g|QcyMo<4S_+b-z^J`=o9ve1k?%eG8lSpR28K2Db`DF8S@3VrCs9<_&d>Rbo@##!oM3OU^zL==lOkYaW z9HuWLs+8$9M9pRTTB7DNogQf73z@!&^2(XMm8iw8SccaSXfjyik>`vOn8h3G%xHXR zJORs1sJ-Ei{$Zl3RpspLz1aI2=)E(0xf33LxH%YX;wxeRZ6(upP>ohWD2V3}dycgW zZolzb{sJ3^X9u%U{Du-=2X(N@;_I27B;^fEZzQS#%-}OtS37?#fFE+&Gd*1_j_>EO zzBoJ)7?goC9$;e|)6=B617gmr2?HE#L(1YflL@*>c+j=8Ql#C;^xdT049)M-?rNIL z;w_}t3Y&a!9%q-J$URKoOG+>cI!x3Vdoqyt!wys$XQZsJ#XFhaL6ZBJzK^IL*w2Cg z@*nSGMu9OD!}$Qyd+F*SrXL{c9HyU56s&&g274d}a|HOv02JK28UFH+-beoj%q5<% z$7zlret!JJFcijN^yniD7cl)?LUF1H$$3-KP z9Q=$4LYI-yCz*ae30(nwHf!ua>JUm@1yWW+9DZBUA&133gM3;1vrPXeX?+eJ6|-8f zXF9$a$GLsa}fQv52@FCn?Fi?|ffGtKb$fr8&8 zL6}^~L4Wi?sD1~337HcAF4O7vr#Ma?WU;w^y+i{yl7a6toqnT=!=!<$Cj55_5W59| zH^h&^YCE7H0$@j;I*Oy)nSK?4{IRDp^wS0C-a$p&$#nXyDE>1v1uXqc6Ne3Y8u=|d z{tNuM5vTa^F=<^3i{FQf2d2dD2g7vSANK983~bie-etufU^@M{6Nh_qeyRoDp~V4% zY4~}?ia*SB`jsdC2-B}4jE^y$9ysEUGo2nQ;!onQ(@pqrAAbt#Sr&hq>GYrx{~h+e zJt-Fd16_HR>GaGIf1c^zCz~%a{br(GV)_q>`ZLpSC+e?Er)Q4%-}p*U@@I{0*kxMH2sj9wsDsL$dfkN#tKl{{@NsCu;)D$x2|0 zz=S)OfbD*CdeC7y(;w!tEW-3hi87h~I8jli|CXpY)1M&X@5fS6=6nUO;U&xXf9bQR891F$*J z#<4yIGwuh0QZ!b^ltV<#gKpZE?r81Z&Da9yJ?0Z^A#C|%v2vJr!_{ExVVz;-AU>qI zULfohV4E0Q%$C4{FLnlmdsip?hS%HI-67Vv@n4^^FA??>oBg=$48wuz(%{9pp9#j! zWC?^?2@5bvV0T-W$Z?lN!VE$L--ba?EfqARYMG!RRp$yCQWaW=%R{Qd90jK#RTl^v zQWctv=R>M45;UY5p23>K3j;#KlU9iXLc@bni338z(@u#4Lc=pli338zgGY%2Lc`NT zi336_f#Qh+Lc@bRi338zBRYvgEO_`P=aA6wEKTAN3!aim9Ad#UFNs4ec(NsNh=m_w zi8Vq(!&4{e8e+i{B#A>TcpM~ghy@RQBo49Q5ssWgLc_xui9;-S&?0e&1y4;R4zb|r zhr}TkJlBvo#8PHsK|;fG2k9DO!4n0ELo9f1AaRHVPXXi{5*nWGM;v0ollzE6EO;g# zafk&^+anIK;F)^FAr?F#k2u7F=im{CSnyOk;t&g-T}K>Z!IS7XhlGY_%n^rJ@FY3n z5DT6QM;v0o)8B|gEO?e1afk&^Y$Fb_;Q4FBAr?GkjX1=DXQmN{SnxD7&LN@UnPIK+bIlo5wma6fJ05DT6yMjT?nlfsBYEO;Imafk&^_aY9l;2B=TAr?H5i*rb5 zc-9tihy_p7A`Y?O`B=mu7CZ%uIK+ZyS`mj>@Z>7u5DT6|MI2(m)24_+EO>Slafk&^ zh2k6%8lL?`9Ad$foQOj#cwQ56hy_nyA`Y?O8B4?=7CbSDIK+bIA`ypJ@RTFs5DT7V zL>ywllZiNogoY;z5rJOfJX2@0S|Zt4;1i# zNbo=b510fG6!3sb@Ejiw#>69~m*8+Lc#aPTWWjTMI3x?6$A^Qo;5j}VrUlRO;Xo~Tjt@s@!E<~# zSPP!x!{J)+93KwYg6H^f$QC@uhhsJINa-awYzv;_!+~4y93Kwdg6H^f@D@DBhr_qv zIX)b>1<&!}5H5I*4+n993S2a z1kdr|%|P%RAKnfG&+*|6LGT#Gxq_QR=3{)`1%Yp z7haY@pMD|`rwf_655rs%tP<-HKc1xNClXk?w7~r;B7V!Te_}~DlbGza0ltQ!BD(uJ zdf^8H@uSPKY!PPeW2$n6#QgjH8;j=`82ahPgIHY8{@|iE<{ z{(F%NI?H`3_tBw>k^3~f`_*S!J5ul_2Cth&70kdvi`V0)OKVbH4frDzG&g>gv9_$K87oiWBUYZmC#*b$4_J8$ z-<&FH?(cxsl$~G~zC7jm@ZG5=AHF{I@bC?)hlejwJv@Am%I(0{s62&lQF#iVo$?eu zI^`*Ra>`Tq;FPEExhYTKV^f~Or=~oG4^4RrpPBL$J~HJgd}7K|_`sB>JtBpVOF0jp zmhu!nEafSDR?1WOsFbJhNhwd^gHoQt=cGJ^k4bq7pOW$vJ|yKSd`8Ms_=uFJ@ChkT z;Zsqb!iS$aT88ET>|ZWDfeF`o+kmjp2EouJcZL1cnZfO z@DvU+;3=F!z*9IvfTyteKTl!TexAa1`#gnR@*y3HTgdbDYa;!+NWUS{Z;JF=BK@{V zza!G`iu8LTy6bA>Ayw#ACdl7 zq;HAzei1ZYZP88{>A}ti@B$1vb z(jt*g7U>j`o-WdNY4=IQjwl1(u7DWMOr1&Wg@K>>2i^-5a~*h)`)bKNLP!r7E|p4 z_*ip|x>nJ0e-BZ181BTlqGi^t>JCMzoiY7pHMwTy-AZKU^*5^N>BH3488@qYZ&vr+ ztoE&$F@5IE>Y>duuLlJ^_Yd$luBdM-Lrt~bRL{$O7BX@a2xFxr_c{1`Dp-yvQ`NK8 zb09aaOi~Z4=fXW1N>kUVM-(OZd7vYzx=zUlP_PJTP(hV?Kz+yob$$@24-Yb^G7qSa zIG{cn1PT^V4Qflx^?>@A1M0#cP_SYvET~Hc5>pF2pe}VleLM&h{3to7pcZ;SUFLxL zWDqF$?eippy21fV~2h>*_P}c^5f}iFG71RfRtw_YE?r6&_IcJD`3U1nPl72DQ=y>Olw8LqVW^HOQc9JfI$SK>a!h6nxDbc1Re| z;OPbRr~~S;AW-nFKv+-%dhc81X{pB@P)`JbdNMqy0gdQhP``CRJrxA%=|Kjy+S5|c zIG}zP1nT#L464=x>JJX6XM;e&SM7ruQ)@h+o_9dK5CjT7un!ArKr!V7^+yNPOF^LE zQ=35rwa(L0e|A9qB?uIJ(-RidfQE$i9#Ahkp#ByF>Xq=I2IM|3s8=0OuLXg6Jv^uZ zwN#y_rQUEr{XGcOKf;3=P)m71z3G7ZXAr1=g$FgDma6x()W022{|N#G-=+;}pnE~R z<$(HM5GYvIeiA{wWEstrohfw@$s9XnBUJ$4ugA8i3C#LcpPz6DthMrVV!yHh+aO^MV@ZfEphJYC>pG>VWQjTRkmxiUVq55U5j6DyTvS)TAI# zrwuZwZJw4YazITE0yQNxC~fLMV#*6@ngeQj5U3fUK@BXXc6wTBrUPnL5UANF6;!bU zYEBTSl0gP_mZzmk9Z+RKpyq}KHL!8Y3u>MNYJL!?1))I=ET)p4mRjh5S`-AT{G@`a za6l~%0<~n2LGALi)EN$_r9q(13=L{vhF1+~rrwLS<`U1(4Pi>X#mOKosK z)dzuUIH{mEI-oWMf!cghL2YqBZ4CmoZID4_Jnq}>fZ7oRYG-&*1DZ7Rf;!6ql?(#4 zD?F$Hy*RXaS}Ns$Y77F^bW%YzJD}1*pjrkQRJ*68S{+ckgFt0MgBsXFUbhF-9tYIk zAW&_gK@Dv1?D2qVcR+Onf$BV|pt>AT`+`7qpHxsi4yfKBP< z$@C<)l(TYQ3tG94Tc3smHLwx=pvQgA%6%Y5->u&-~(K-aDt$Xvqto|bY}?rT9S_i;nv zke~)OczQuOEBCdamHW7Zaad3TdKvwQr=^^g`&!V-ecVj>B!Y5Q?rT9S_i;<-kf5{y zwbVyFE#<7-*Me5=ZsHEei+pIZVeCW_JM%a;fq=Ty1L}7UsNV;H`a@_?1B)pysAnBe&jo>cJ~Sxp#euZc$2~3OtR2>Z z)(+z~{UKv&U@heZ<*Xgng4Pb>c>p0nX@46?OMSxAQm;7fdo{>?uZ0Ko#y~(_<^lD0 z2h=};K)o3r)V~G->XRN&&WczqXhkfZ))3Zx{~HLX%RQjpc3SG4pq6?!G$>s?VNkke zgVOZ?PUT9G2fS%Dm z?Ey8!0hJ#Fs^Fx88tQ-=76fW|Xi)mdfw=E8o|YQrfEpbHYD{QQ1G~+5L5+1ljSB)b zJ~Sx(l!3I=)t;7`=zuyk2vlKcPy=fzFQ`clsMCT#6@><+PZ>x{ea_QTr#qmg27#Iu z8q~mA$_r|`18PPPsF|Tb>9YsYQlIyPsF_bDfr&7t~Vo zLxUQa`@EnQIG`2=fm#$E)PQa?U-qWm;zOGAUw69b842&V0<|nWsO19z^%W1O6%MGCL7-~FgIYZhP}h1u)jFWo1c6$6Qb9Ru^7NoJd3b(U z*m0_UAT4#Br==R4mf9H9QkzaHsLc+jEkU5Rh6XjT!Sk!0mfGfk+8zXI#~_3Hng`TQ z2h>?Xppt_O>gyg*yBtudAW(4jTgX5knESrz0oCMyY7PPg$I1;VsBd{dwK$+!gFwM) zb%P4(+a6FE2h^S*PH&3*1L|-PsB;Gy)Q>%&jyRw`5CrPH zK?d~`52z11pgt4?>iqDa2DDeu9Uf30c0he32-HWzgBs96!8<*mE^t77EC|$vgAD4Y z9#9uKpe_yqb;%%u`k4omvzx9Sw3{v-@j0kB@_@R+ zao?3e?z<{Hr~w7~-5yZRZn}EVZn}6N>Y%pNJswcbZn}EVZn}6ZYgkYNYAG)$XE$9v zXg6Iv=ygy*-S25BXE$9vXg6IvT{bMJ0R{R49#CI#0{z;cK)-H~K|SaJ<*domgVyBX znY)A9QV)4RIcxItpf!1T{O_QG`jrQivnEduT9b$84i74*hdrR2HF*^*-Qs{c8U*TxgAD3152#xmP`3qv zx_yvA{l){zS-q$StzN{Fx(79;9`}H{!)d8IgIWp>4IflcPk2E6%mMZDAW(2l`JjS& z(gW&l2h=@5px|WmK?U_&52$+`Q1=Cax_^*CJ>>!Atn<`^)_LOj?}OS>&w4;T%$GdUTLMJ?{bam;>rJL7*NVWKb`7Kt17rdNK&qZwDFFiylx< zIiQ{n0`*LIPy>3K`J)Gvvm#axS`n)c_KMh-JfNHvv3k&oSUvoT*n#~F@+S|d7aaG! z805Y`4zm0H>;d(X1L{vfp#D6_p#I_k^%n=!UxPrsJjkH_>H+mP2h=M;pk5thP%nEx zz2<;=JqXkr;Xw`Pwf%1%P|n(6J!tK)9)9iczz%?W#RKY}PD}kOsHOfLx~2604rB?y zYaUQ)t4a(4hKJ4{G8HNKY5(Fw| zkU{;!1IlzjS;q#Y8c`z#2j=4Oi^Xs-A|99+nSRvB!($aS*C~oIZkv&SF~rD+>#9*; z3>DAP<#3iFo~D>HecVxF)VHPDBS}JNgRFt4d8*>%MPTy5;q5TPnAyLC@kfo)uqEKhqUcW3m~E70OPB>E%;qJ`HRef6SoFS?P;OL+52kK#MlaBWj|aHV{7DA`s1nrmpQmm@^(1u7$r1?Eg|WY zu*+RS5=z*`OK6riORKzq{?6kC*kcZug?QL~4A5&&pK-CmlrXeWSjxRGP*=}wv2s1;ZSQCcqqFr;<}SpDOU%< zd=SZpi&(V-$Eeyl@^brE4G(fBk9(?i(5c#C1J2R)Rc*#hsM?3+Mf9&4p8bwRSO%W{ zPE|V(&WG3SDjk8sJ^=sD<5l{I@ljD=uVTV~ijp@S3LImMiHylPYFs8Sb|pzVEt+Rs zV0@Ann`eB?xSSW8XIzNIqDA8(pwLfw#>GHIICTk7IULlO9OD82^fCB%A^f`t{#^|J zF5v*LkVojJ<-qz!=#|(Wc7$HZO@7Astcaf-fCbUSsLn@?Yvg9DO0V??*oDX98Ab|1o6?xtMPYxnf-M(skO&&nsk{j(G zKz7Y6r)Cz_%nl$|J)jQXHonuZGtQVf;iz$A*aETRQN(tMrlf9ZcgFA91w$vaJ0ukR zed8u@tp8c-sQhWkbMpe_9~!qFE9^%=*xwn>w-vikgOBt7_a0TfGO$+U`729GIeVNPTd;eL;bKs;~t<)?z;&l4}3{YK?pm-FQv78 zC|qrSB~^YTobsdcF8H{-fx>h_gu{*Mg43kLu9-VDNx23*0%E0J{V;b5@fJsKPl87VP1nhcHugQMT0 z!SRs^5`z=T;3P0O@jV(mEm9;gIE4&O1A|lEqrvHs84`oD$lx3>IO{zcEQyqg`)l^K zZ^jRdCvSir+<#7?-vFhqQ!WNTzeDLr86S-!DrCZ_8<`ui-&wP!$Nj)~D!l3JgaesW zzA78GA`3zdTgum@%8SA&e_g6v5l;CVQspJ#l)oueUK&pMTTqpPKHyyO{$yViJ`_&*7gFVO!YSV?RX#VI@_ka}4}?>`U#k4UaLTgR+M6Qhhf{t) zTJlH2DL*Jxz95|PLsI1n!zs(&#&3#T98URRX~~y{Q~tG7`4i!kACW45GMw_GQspbc zDL*DvzABvZZ=}kf4yXLMRQa>vl%J3)e=eNzlTzg`gj4>lRQXHcl%J9+UlUIGX{qwH z;gp||D*s5RQX%sl%JImmWrOFS4Q+`9L{7^XMze|-L4yXJN zsq!P?l;4ypKNe2;pHk(=!zuqus{CX)<$p_+p9-h^AF1*);gtU?RsMZA<+r5D&xTX} zpH%tzaLR8>m0t{}{Ek%lrEtpcN|pZ{N?BE;%6|=~tV)&t7EW1{D!&>|S(hrm9!}Yi zD*rv4azv{9W;o>>sq(+VDVtK||AbSvq{?rFQ;tfN-wvl7lPbR(PB|`9&QZfDGpVv3 zPB~Yq90{kKCsj7XDG!kNwlPVX6Qywo>J}sQ`1gY}m zaLT7hl}`_+JW;AVEu8YHQso)plnbTGv%)D)k}4O6Q$9_qToO*XNUB^GPI zDN^MH;gnC8DlZDBJXNY(5l(rURC!4_<>^x8rQwukNR<=elxIqntHLSIk}6k+Q=TnV zUJ*{YSgKqTPI-=0d38AD5~=c%v3Q?8IIr@|>OmMS-eQ(hufPKQ%IL#o^wPI;+R zITKF#OsVqTaLNg(a(g)CN~v;ZIOQs-^1g7&%cROZ;gqYT%6;LKmrIoogi~H2RX!9> zd8JhOoN&rDQsr~QDX)?$e;}OlYN_%E!ztHFmCp~QobzGn>cGf?fv*nC`H0-)q7yLr zQMt*A6EJy!+~krIF!?dL$)zV?@FO{3D zIRTR&mz!LD0wzBpH@W5nOkO58x$Xo^eo}6-?gUI;E;m_!0w%AJo7{K;Ca;v6+XK75NIt7B zIZcD)T6M`88YG`nmzw zk7|(Iq%Qfm2FcCplB+aGZc&$fN`vH9b;&gvB)6$cKBGZ$ySn6B4U#+5C7;(I`MSE~ ziy9;y>XI*Mkld**xn6_hE_KOQG)TUoF8Qhk$=&Lbc^V}5s7r3rAo-@cM_1L~4*YLI+KUGgmrlJBZZ?$;oBP+jtX z2Fdr-CEwK``M$d3dm1DUsY@QxAbD6_@&gT$AE--yq(SmSb;(aONPeU)`I!dEkJTl= z&>;DVy5v_HBtKP`JfcDJGj+*tG)R7~F8Qqn$uHC;k866IetU>aay5uh!B)?Uc{7r-8cj}VAYmhvyE_qRdvc}88* zszLIsx@5Qp$#d$G5gH_aR+o&_AbDP0GD?HwFY1ydHAw!dE?HWGi4|T~(8YC~OOIFb!`KP*Mv!l4aE;2WXHir!F~2gJgMi$srmfE2v8j)gW0>U2?bv$x7;yBQ;1? zR+qd(gJczT$uSxvtEx+m(;ykGE;&JiWHoikNg5=pt4mJNAQ_`BIZcCP4Ry&G8YF9~ zOU}|DSxa4Vjt0qCb;)`EUXpc?TpxGu`3AAqB>6M$ul#U&#dlrcYbiQPb@M+fU+kPf zACO;g=Nz^7wn<3=y|<0!O7vZ5%I}VOO-c#Oa#z*PseyIwrrO!Zx5Rk|th;LG27y`b zq1w4oV4ZuacJ}ezbKY*>qT0DxV3vDH&GWy@Mof}c0d#hL>48Mww$Vq`gEj$(pmSeU z4>AMjEO^jQRixcN6S+-Q#K$-7DP}?Nq`#_2$A9L@0M&r{_<}x#CkW_3)y}yAc!17> zR6G0l9zSo(gQadN>%K=|mTy<>d`n=RhpM`LYhay+saoz6Sm)uYmiq!Zd8%sXnSphlrn;(T z2iAGIYUjCub)KQ>wvTV7^q#7js+|`GW_gxs=f#0_o~_z>NnoAlsCK?Pu+DR(r7DM; zdjjh`U)A#Rz&bCG?o+Y6BCyVjR4qRkSm(vkN)^iw2hiEp%xIP#xuUaOdMu#MxSV)g zrSqx)IygRoWb)ZO;Knzg;zxfB7_tukRz1jmYHldB#gu z%Vdbrmr449KQh^rOump85`5K6T78+(V( zubN5j(?!#eaxx(U0s<%n6_S_`pQH?eT-$FVUd)wWI zFk$b_*n5lj-Vb8$t?t8)u=jTCy~BI&CzwHcGJo(v4R*6A!<~$EKO4JI+GCgYZITYe zZk7(==L7tF4E77V^mU$8CpOkD9Yt6w_B3pgzO_r=M@c8QNN0lCPU&2pl;HfcT{@55 zejNz7&=2rOKV!em(%(_iWqH@lrrFJ-Y>~Fln`D(T% z%FeYsof{O?xw?1fSWo9h1$B<`?i}ao+@zq+HEcDMZrAp7ZszHnxXo0r=O$CK-IVH@ zt(vxa%ARTYJu~v8R-T?T+qOzqgsYYZxy?--aQ+7>}LAy8E0#zwAskh zvz_0bwY_aN_Vn!Fw`Uz&9i`1Co}L{&J>@7>z9LF>y<^-ozc*Gyjb@G&I#UrH}`bziq*TSeVpCYdb6o*T<{K4mfe)SmYF-$wwpRTcAC22pWW2mZtAtu zRL^eegA53^n{Kn42D)-5QL$2QC%x=Cvfi*dZar&;kz-UUiX*R7OtRG$1}iIOgzykq z^9~*&h=%e|Rnf6miq=ys4yUMu8chQq&m}?B#7$nJldhCYR%FrCSi5PuD@L=f+&jg~ zID&MP0+nIrX4!)|+$?xt;TER{^LCo%*-eY=rn`+BP0L*oPqno|eC(zNcA8d#b`@Ft z`mo*fc$Ddh{OO&NC-snXLpEjQR@u~(+$xv~<6-_xrTH}_>xT1iS$8!L7j%p9VxsOd zcGC;O2-0kszDMwKlxe+Z1h;rb5Wyp4ORw+kvvk?eU(QFy2W{M zFI~GZf^>f)*b-&h>RDp9dPWe%ahOEHZRb&fr4qb^m!-Rd1ydP*M-XM&;R#kBkExQp zq-@H;OA4k+@lyUwHSlW+Nxn<)t3d%Fc*7HdejdL{bDSn11bcXC!LKsBjF(?;i5cI} z*3x&rAmjIWLeSr1igPZTdYf~>R9Rlu+msmXMg^EU;4w8&Hnq|8zPt{~@p7`Y!@Qhe ztvoO9W$hz`Fl2`*rf0C+tpcwgcl(4_5V}?56}`HBp4-zXcc{d11V#YAv&UJ~X|okS;rNMg>M2}k zX6s#m3yR@2vyJz)yWNE0!PjUWE&CeDqXl29@oFAlZQ&HcRTQp^=G$jbPsD#W?Dt)ow`&C$-Nz?~YrhU`vt zUPExFCa>x7+-|NJWfo3mhlyt6pj1aN+rri(5VN&-E!k{5uO*m`<(N^*N19yOY=UQ2 zM~G&VU^ZDW+tSv}r&*e#{G5v8@=1%iKKGopSTkz#{PPyK*;J3&QKH#&FSD&|?E*1d zhs)K!O8l(zQ;*dp-APa z@~$~NRoFF+r#W}^Unnwdl`vJ_g@UR#)_giomz8sQx}coFGn~qTkLCZP?VZ^#>Z!Ut{lF``sPNcOZpZzOoym^b!#YP6dNMwthBe4LuU3TT?l zL%br|-rtFncSPIU`ulQF8PF!YiR|W3-b8S-DR1g=Qw-=ZkF(PSXOUCQcr#gO1aBq? zHRsK}bIMlH7Aho42iq`Tp4zX-st&g4K6kz%t2#uo2Yl_V3_=UuLiT+WZz1^JlDAY3 z!X2I<%)}&(k={u!Eig6A~Kb?DAkTu;*}$|U^Y6vjLaKi-w6qwnKczVC>6 zE8a@>dj@YM_}!Yf_V{f#&vrS`(H4hrxUT!ifw@ixpwx!9k(K82HiA-H-qvgO7TQhZ zwYRsOY{LtPG;Cz@Oxea_o+;SK;#s1%ce%XntYVk?geqJ&0rreeRj>LRa2ZcHwc}RdAsj@8<1-SZxr56F!Aak1L(s z>~l}^!%=48e#z|oQivq)&T-cZCm~Pr?t)i6cn>eH)`(NyrQj*=$$QGW&+wjt?k)Tl zZ(VW9y97MtT?(G^Uc8s=!CKx+@ZeT{tG5T@l*5AnryP40IOV;0Z`p{& z3*wYRIKU~#p8lu&h5W*gTV!+PDc@*bztQ{}vPRlrw)YI)Xx@Ttd4crhePvg-@xFqq z{dhkwR~1XYyDiaY$|;hwyL=zf$GyB??B>^HA8zBgr z1n&p%0dmj%e1On%ARp+}bA^~~Jp%Q6_%MtQ^YY;n+51qz`{8`J z-19R&TlufV>~cN6J2Y!AA-{jN+r5KE#mI`8SEoU+**@wVS_< zGJoeeCz@Zt(zt`)A?u&ucL@5U`Dm{(DoSMUK*!iSpfQf&V`Lvr@-c!BWBFJwAFf;) z^}bI)-cR5YWFLOy69gY7@`6!&E-i%ZDqM#xy=n?s=Y16M9bPcm+jq%CSaV z8vO$GzF$Dz&)_p;AAaRC1RrMdnNAbI1!zFrOoMF_+I3ys$`i3tk`1zr4zSp$rXP8^kLkrR|n*S3xqJR2~o%F&SKN zOy+UCat3cA_&mXz`Fy^YH^qga4h}RXgKe$-$3&i%1$=?*LJ7V=aA6_Gr5EM7oMS!R z#|*^)hZH=(MI0}6VSuIhB0+sIU+iaqLu}=J`fVvKL}G})NW3hM?oNKEY@hQx1^Y|* z62U%Ry0ny6$ohHZQcSubwoyJEm6J|(;Vyoc>_SC;m*B$P{BFSoOI5q2hT4J7B0LeY zSe9GLm&$Une5oL}j4u=9Xhd~zF^c>2mU#Rm3Zon9=Z3j(=lULgk8GwMzeg~0FTdAm zCjZX0YxxcJdU+k59(A9rhAK{0Eh&OCBMQ!-<$Ss9NGe}0IC3Aq&uhFH3fTb5#t8WV z9Q6}h&kWwr@0VR@$nO_iSix5aF3=1%Q5HzWNJsh|so?uaTREReWpbZuKfoW5U24W3 z5L|kYKPb3FS6r%paDG_23T+#vb91cm+eeVLZ-HkuhHq=3|_{ zC^?JFqx@0XesBJ$VE-}xn3sLA$c*#%8s-*xSda6^W!b*`aY6P8{)Croe}%Urd}fbj zfVg8MTj6t0PwKDYt7IPr@l}EkPx2=PAKb;ub4_RdT^_+x{3*Hj5dM_Vdo^Dz^rkEo zCuY2#{8voOcpLXQ0F!fK*6=m5{h@q~VE<|Uw3mG`g5&*^1k=kx1jqZn35lEX@N|im0M|Lw^Za?)i#z!9f)_9F7X&XXr7?wC9{D#K$?4*A<=XKr&XIec`4t z?s2`yUzE*H?M66kJPQ;xEa@X7QHp6%%QSEx=kbC9qoZ zDt}e>VF7Zse#s#sRh@PO?;DV|4zP1 zu)mpa_OdTVaB85nWNN{+MDb2iJB0|Cp2^RKNH)(_0^Ybz$?{y*cJW=Z$|k-` zPr{Bg)`_^)7!`-ftg&SJ>|$Kj_)dZR$>SQ}6NjWQn)= zdxFIK{C$svoEV4rA$h-d_#t7x!~C#wKl#xLIy4`28(bnjr0t3H2mAwB=zacyAoL;s zP!_Trc1Aj0%=x=)NxpObW4FP(#Fr~Q20!8-$p$~=9|;CO<{yhAv}C(w?pBxignuH- ze9k`+WIpAeiZYm!&-iEZeqZv>g#A9}pNoN#aNoymaH;yte8Invg}&xr2tr@-FP(up z>RLo!@vr3lj`6RA{l4a33kKW|SrW zT{8666}%*5ZtUv$4gW^&d5V7{^gPCo<@Xd9^S$C?HsK|Edi2s+slMgk$}&IlZv~m} z_;)HY%f(elGKl|ieq8QbN~PV>{U%&+{kAoC;tQN^1TqBj^g z&EQ5lT3l2fEgrO$^u2O$wAdVF`7{4$u{lp#0aq^BEq`VF#D9`qxy*kOTsgzfI9;K- zEXVpRKTG>r4g9RI-#LEHv!8q9E9EmE*P((6uWagP{Jf*yI&E#MFFWGt-{+D3=Z~k|_ zyHQr|Il+0*owC-7%9MSgfRx=HWv!H-vfJ|{Jhfr1Vz*Y!xXdrh)~oT$ZtD?yG7M}F zH!#@)tLwA_tO2Y+-oGYoDS8Bf2@)b^jdM@bD(}-B**5fo(I;5et3z7~JtG*SQ_r<< z&?5vaE?Kd7;%Q6KBNR-ir-$48lio|nWnMxDNft|_Erl4~T3|3a#ay}V7JSP4$m0?; zqmx+{tVdf4K?@j*C@35|S9=Ret1wn8dRS$(6xvd#g@FkZ)m$!w;}79-r&QWfbSeg> zn5UC_JZrqt6UPIXkHFp$vQj#2DU@trY#ycjY(l3<{2@~A)PS}Wor;4g?&;(<|Fr7p zqp)|Btkj6M6iOw)lyEA!E7&I+t<7;Nl+tsn=NxLSE#6am=`d%(1%&*bIcrY7 zcxecfmc?^vOCeqcOc_C3ew|Esuqcu}=l97X_t>5j{cxTjU|byXTsGa6wiKqzf+;JS z9%r}q!1>8^m;b%o;xDL*mxDk#S-dxGDa6ZzDeooTPZal5+80&DD?p%vEIx>~6yg=Z zRP++3Gb^{}!`+^*^Al|`(w4$PRWMZr3-Wb^(t^*Yn(g8Xcadzpt*_5zARK|$%Qx19yMbnU zivR-R%-I3?IU5bfqGhMY)0V>NYGA4fPMf^Lvcc9M5LY&Mxq^i~(QcjmaAX5`G|heU zQTbYzJZaV8L3P=?skEi=E(T1D;N2A=wcAX-y(n|s0?_fyF&yj~_39{ED5)xg+m$Z?rYTZ*{Q;lHN8xNQ1I zaoJ=`_BmQ*Vs7#mLE-LyB-Z2NQf&cNj|Pwaa^P48*amUrp1ifZmaAwa@K`%l2~V} zB*}Jvj*3ZQUF=B`tf|>b<8&KKJ;cg`<#z93$)S!zIOF6{FQF|(sB43%tqiqwsk1Ck za!2cR??>2WSvr@jBg@`HTMF5_VCs6w-X~Uj&vDA3Do&@J@v`^|+ER!ofJtzQ%kRdq zt`wCYal5@!RhiB~6J_PcXiK4-1SZML?Nzvf3CWKLE}%qHtHoK`<>&3VLM`8=>J**F z){~ujnzj^9C4))!a%!#MhH0#O#BZpI(`jvrEdD%gDa7l8sqZDeP7t>a7k|kS2fSPU z_zNFtx!ZdIS?tT|Qo=@r^i_>=}F&C93P1UF10-Qs&}3CeXWXC|FUr_17Y+ER#T zfXQ%*JCg^8eCsy+>@d>jsL%(h{DG4me5#7EpE%k#ZD~Fip}D8qp*K}WODE|KWQQEI zrEsVrn1)`XeZ%RK=neTL`m;AMfA*^SL#O(UWPkS1mcpOLU>b`7dK0GUe7gz$&_wR^ z7HugyH3ieudl2rRyyfkLb-!F~Eqm0f?LI#*hgcWlXiuNofeTuy($3#p55PsTeYV?u z&Xe_>ohIQ0L)zK*liyTXGu%ViCk}xw8E{97E`)pyVZWcZipoQX^9(_p*8Orq`&d+T zVH9OO=(cf~vNrm6X|ZP2xiEc-ESDP-G%Y3n8HJf(lcDW3m}I|~mgOvrbXkp!8L z$&^ieN?QsOSzxkMP2kB2^51E~b2xra)dXE(x06kLPFo5S?ZLEHHSv{b;w$$k-d8oz z0WuwA6Gv!EVImt$wyKF^qKRW}6Ngkybc9St*~E9Wr7+P6OeZxH=2C(Qb1Aop!>T57 zAd@4TI6+$q6P>|yRx@G66`W@-JXhHtsG6V~61lR8leDEU(FIHwRTH?e;W3fp9>s^M zCg{dPSJ}iV+ESS42Bw>;37jf;On5HmKT|;NVe+WnDk5%3236ni#ch1n3!kt^d+@j`=X_nxQX_n2Z@aGeM&tiMd7(P+;rx$GY zlKnYHTMB<}1#_$5kM$Q2&D~S_sj48|?&&QH{zh90!9HO6h=PBBz@f#u14Zn@K>5T- zaq{t*pPL0js6SKnq%Xw#%AWj5TMAG5f$1lD@|V*S=?|mw>ihG+JosGIgWDjAa|h(! zW!h4B&>u{H!Gkcm;V#F*eSRo^;2wR}o_Iw2A~1)(P&%|WBnF4DX`XWd_beXqzLYa3 zsqA&sdoTG=HUKUUpz(znX-hG_fnWv-<1=+vk^RP20f*=O%VYU$hfVvp9X0RX|7NjD3Oq6xs?;L`zLu6TcF<^*7_I5D03$oT9v933fU20Mu@V1smLBzm8Bb*BV}27^9*-u zFJ-)A^NJv!RK0*3hu-64C&wdQX#; z%hQ%Zc{&)}oTr;``4`G6vOkHhDY;W_2D;9WW$CW}423M+?VBme;#2Xi$ci(nva`^2 zmMlv*`DZC)XM>sTl%>}Z-8Z6@5BG{@=yEcL1>fdmycxU{hehw17P~e->uhk;@r}sD)LwtVLXfEvC^HtMT)U5 z2D4Z>)-dPo+Aw?;mD=svU;TUtmwfd-Ce|KSUkt#n@+W-xx$br!7JilQ8Mtp9(=7sDH*)KUlD~BeACZnAkdS~d}Xpe>d5_&;$NEuQ)DI4w6Ql7L~a+o4a zl}*uT*P1rtbB!J5;^t^`4BFY|<>nP=H<|aD51>71zG%KAIV_J_)>+m|4r?204{I;9 zW3BV73nfRGA*^^p6dP3RcC-hI zeOc^?$YGHqB}Z{qJhFHRw3)?k zDc)OhM1@3^isEQ@L>-JeBsoe*CCZd2hjw_0=_O{N%`36D1maM#RLL48W6}05IjZCs zw0R}>mIPlawN%?u?a*#5b)eKi$x*sf>Dx*VMEhLnEv2_hjxw=j8kA{__N6kfm)Rvb zcn?05k3jn+|B0WI9A!(Dtx*=bWgjW~V%e9`9x8jR>~YCau4}o$<%XiYr`(g})<}-> zQRSZ*+g9&c{Z_Om zt6!{+`HkrsGdKqR$9xoXBIXClQKNQ^Mm3tE-B4p!jXh}3)VN$TNOII1RdZI&xss!n zp;qx)nD<)owVKvyfi|z!-dfO&O^$69+ZOFpu^VIaBu8A8xTLrgw3FlRj6;6JU8)^k z+a@_`XVh+28~Ip!YwZKIF%NY%*4bTWujHtkQnz*8Ovw=+5nnkTpFrNUWKdp4bp= zr^MS52cmsA@rA^fBuA1Zsa#S;v^h!rlLn!klC&ggDcU!ZK1li)?Wv^yCH*Zq>ZR4o ztk)jx*n0EoA>Zq5srPohchO!Z2W%HZKi)+LLK{X;{Z;Kcxqyhe(d}#_74~nD6wv)1OLz z8ttz1kJCSs92wS(${C1bM$?S089mT0$yk-KT5>dK*`Q~GThTt%z>be_b~G&CFtH)( zM#Cu$mo-G38-CpIbi*@}qfz5Vxs9OP=*dQTjbN{F*T%ydk3{=R6H^o9b5m>6%1xo) zET~!OW@RNu^O4QxHeY~tPxH^3e`j7`z~l# zwSTSsCdttus6*)v@VCSA4$pRYUUFnt$*!LbKeNYXFUm$9WnbzT*%5W8hf5ZRcOEN@=KQslA~)% z*Q~A`&`$5Vyz2_I-*mmu^`hkHR=rzBw?>kqdt~>R?yw_&nTO%+(S|!O8#}Nde4U3R zox^9wBa)IS>oUt^#(d7jw~_hwEL7mV|7P;~oAU2dm__C9u6-^u$>-mL<$kAR5Bjq( zA1b1fzkNitj;xp;HBqsk{haZFk5gnfZ)3IsghlZ{_EoxFJOFjkLZJI!F^m!c8WN5D zlRo0G`m<91z?x|BpY{{2-owiLL#v|Yf74gA-k+8I7uH1&{%wEJi$SdXzw|=%M2m(y z@!pl!PhD0~gF~WIT6N5_A6VFMEJiXdlfvJ@KZERLO;%Z>m!hXvL(8AHFR-dt!CTSe ztEJ~WaGa7@svP4fQuskB{CzpZYgo0b& zt!q&m!4v~|PbUKlSlLYrDP={At%X0%8=dhwTDRAaZba*<4^GySJnM(1riIT_m*(r}6)EzCZO$=QQt7vgA&5iRU~ zx|7v?I*4R#%sLhF@QNWW3ciXjiFIV1i$HY62p1K9T_>OUuait+U5ZGc#b6gDpS=P; zm31pZ0T+W_)cp1e{8HAVhy`8@eo^#YSf)>vz-*JjdcZ-{|A? zH`mVf+?|cS!RK0>@0($){^s1ZzQ^7Kb1u&N%`#qpbMHESkH1OgUY!4%Y0Um|z_tD- z-b6Vd=E2Q2ZhyJpy8fPgljVY#4>#l3{pEzKK1{s{b3)9En|1vDa>I50F#RUY4KY7% z<{0?P5m)_~c@yV|m?t-T9Q@^qv!3i>vv2ZT5%Wcl#ku?sfAabIyYs`BX0W+>+Q{#- zb-n*pkB9Sp$6<0_sHYD~j`OpJ7O?qx`ncbw?Mfj%CZ4yh`%5F7Zc^6nrAol`YnDNs&upKIySh<`cyxpb|BSEz#5JinJ0_OOMZ$sTFW~O=WlM z>7|-pVv6Z8Qcp38QNc&X)@+%cV?J}tm1oXRZ|=kH)nny1R<3x_XGZC<^1Uu8PW0n^ zU%J<)Y|du)>1kGAnu)2V$E)B}qj&{$QahEc(9ACr@a#PGtJ%;}-KLg9rZ1#knqyIWb#XQyH`0w+ypj?f~|L}$<^<34I zt75+DvDB8Y6iW+z*sIz(fb$8t6t-GVSj`D5CaoS%?MYiuv2~riKCS2ORmoj3fAyGN zo%{_fhnKKt^&GxxIV|R}9@ndv#}rqeClb!LWmIR+>4|(*6Io1VJ+@ajnFA}%GuR7y zPG9w$7V}z<@72$1zq##xlfp!{PS5TCB)47p?Rxd+Wj)USS)5(5rdNsdIR7`bgktQs zrnuj+GKp=_bNxTfbur)dSpT>A9$3z2vyFPr|K~X`=Di;8|32>v%6-?XU9ai6e@${< z%zr)R*Czid=00zFxn4c9>kHtTEdX&5=yAVxi=d!`f$P<{&H7rnrfWf54|?pc?Rp4o zO`K(0^)+$L*Mzt(^!Q)8yVL_7Q^Yf(ebzq0s z>-rkGZfnG~PMojhRAM{zxwx)#;hGP6y+@ym>sPmE9_S}XvTTqad~d|w(3i$_UmC9E z;VM^q^f@UMbK;s8DqH%TT>r9lMfu8Ld-bJKXqJj=xj4&MW42G9n?f}=-t+UeK0k$S ze!S=C9es`p{EU2iqzaG=dTj`T%W%pH-D}H;sV_lAXv8oT_HFSB z?`wS?i|jm7p1H34^m$a4s=~eoz5R2S)>iDOz9ftEk`$MvK9@y%S<+kv%j@x!{BTtw zJEpJBBELGt6{^o?(O;o7pF#BLswO<9-I#r+FVP!fiHgfqpVJ#-nJSiQDm$Ss)f;B1 zx|XZ+6_Tp#q&~Md)ZDt}m+s)|b9>{IW13fIS_OU%EHk(iNAlKEF5K@^vm@ zQ%3$p(2x2Oz9E;exQz8VzA=|^{!(_{&zQ^3=u7#AUCOTI?0Vw%oIck#^jy2-wDE_+|Zy^4^qP(3kp6 zv(#P7-C5>qvOn~>zp3WlHUCuZ^|`-!%Dt=XhsYnc6(d=#2KjdDX!fUG0dBeq;Hm-gmURRgy?yppI*C8E2woJN}3u>ddbjBhEOsnJv@h$mIjNSA9{Xx<%cpyni-tm zDW{iMvBc`z&V2CHlA4BMdM(jwiApVTtrgels-7o$Ep_FDTI)W2ZDg?NB}FeOeo6|Z zk9Y_wuIG!MF9qa_D`ze>GtSq2Uow=^^G45` z0Q1I`J9LQB^F}{Jc^{7a{f>`DbbcyGCqo&%zT6D(ZQp=h45+BV{i2GE~-cNzWw>x#Y?x zy0X`ENk7G=e9-a}EPoNg6#2a+T@6+B>ZB=}T4v%#>g#$^L(eB|tMf+62`yuBRw?Hv zoIYo$rdKJwN@+aqxw6q!sq~!EE0rrJw6va49g#A2rBmR`)nVstgO{TDQL z$`Gp;G`*l*<$@*_H9f!dqINY3nYV`j!e;1WsI3<^y|DcUh0RsmoDbM!8S3hJrsvsz zlxNCZ>tsmKb4|~+|1j5-`PRXZr01KSZ~t+=DRXYIAz9BkJ?E}L&MEV*lcBzzcY5Ak zqr6k*-XcSqo_l)kUBlc{=3gg6hMs?V{$1nzQ|91&Lqk0W^&GqoIjGFTd4|S%9_o2` zo$^qbi!}{R^<30*@jB+BDCFzu8Z6cYRZ)^SC&{{8;dcnM&iAlEcbUps%dqHK> z^%PB8Jv;U6EL7P^S?bBqZiXy9L-hqP z&SqssPcZb?Gg{B+BA?O9tRA9&EdKSL(HqDp_l=^3hLXraqc?<^gmXQ`g0g)&RMGj)`nsd}as+Duhu zYX`$@8B+>z%<<^$gZCxX5L&cNS0AvslmKBALa?OwKaQ)H7Mny-FqAZ{lhCqibEcK4@FdTK%Bw z$_cHlro{By+2xrm>6ll4+R~ei;7@63e7tOj(y%55s)D2^!^;=6d{ZaJHXEDx_i*c%9pqS{F%0;dyy9zUX$<6=Ry6|rp3qH(##nP~{Qq01tvoMy3wk4~~Zbf?s ztHK^byPj2LU!pzBq7CJl#SqV`8G51}!Kxb`MEg98F?@jb1gjBbW0s(3Rx>CIZEsd9 zXffJHS!~c7Xg^|cL6?{%ID*v$61T zLY8Fwl+_EV!;(X$vy_k*m?dOAOAVEnCA2I{3*C?QOO`I(#VpbjEJM1$EG9E+U|NRu zDb~<*ky*@PtdV&j+DWXjr7W{p>aeDkx6ppXnpt-+i}elGJS>J;!qQobu*cDEU@gN- zFiUt1)+!vj;ZLyE#e$fnSV`8V*c7yPv$n;~q5Yd>Mx0=lh|?^~_64)p&aifovzR6F zKGwc?ZDuLngms8QJfoVh?5N4CW7I{~sl-~AQ?fI&lDwyS4l<*1JMY)~CX^tZ&7qSiegBn5EJ$1tQ!`YPDb=cH8*=%y1LCjKT7@JXNI-6N{Fq>6(1GCiK&F0qq zgIVH3*}VAiY(e}HwlE=vElL>47AL&M?o6!2mL%TG?n*MSyOY|orAb@ZvU(U-y?Ay{ zz3ylSv3u*SW6SIP!tP7%!|qRhhOJ2cky(;|W)G$y_9@A1Wy&h{P<F;cFvxzLP*)q1h`5^Xs^X<&h zg0r11#<5*3P3(=9gV^qt7ulXx-PoJ0zGr(|PhxMizQp#maWG4p-E4o`bY^MWo*l@X z&McXCv3E0%v4dHy*n3&evG?0q*`ao$*x`1E*az*C*@x{{vX9#T$v*CIC;KFuvrn^! zvCp!9WuJGP$iC=gVMjV8u%n&2v2QxP#E#_{*|#~p*mpS_+40V1cB1nD_I>9a>|}0f z_CxL%b}IJ(JKd!^`?1R`_EVRS*_p0&*txD_*w5X{vh&@3X6L$_*{|KP9>R|?7ICZL zPGbia8rCwb6$>(Eu<~K8Stn*NKF&;GZNM3gOIXFQw%~$|=fP!y3pIYps)S{M3khih zt{pg2NFuoQ;G~fK;5vY_guDta8=N^b8C*wjVWAblbpmG%y&GH(xMHCb!F2`~9(n;> zE;w80QE*+rMM&A;x`Hb%rGe`PE>hYIt~f+)!{a*3saGfvX-?65Mcb zHLaJyjR038jN&p9Tx=M{WfZtt;lbeU09QNgCvc;|#f47=HwIkY@PXjQf~yn$Gq`c! z62iX#Hy&JkvD?8-0GCv(Gq{Q15{n%HHwj#FvHjpCgR2)YAKVmh^&>`sn+h%^g2pxt zTv`N;Z92GAn;F~;a2XN5fSU;}-L@OtEN~5NFM*p4u0iBTaC5*lj_eL@F1SX;OMsgP zu4&}o;O2vCQoJ{~1>l+&Zv$>2xMoot+#+x-qk_RL2G=6$5V$+RwT{{bZV9+nCCY)j z3tZb0A>i%?*QUfQa7)2ul^6YhQwL@?LQ5O2&d)4lcW732^s;>riqG zxck9%D%lI%3UD1uQr`!_buLML9|V_EsvWqM;JTDb0rwEN+)@X@Jq)f}smrpxz++*Onm);KUad5Ykeiqyl;Chy63~m*;Tg%i0_awMpWp;sk3S6HuFM?YQ zt~Vb6ZVkA8yc@Wu!S&_mz&!)5KmQ!uv*2zkOJiFLZeUp&+jHOslzkc8^WX-TeF)qO z;0BdF4(>&8x0ihn+&XYW$_)kg61ZXIa>2a}ZfLnR;MRj1QEn-?4d8~CuL15AaHGmc zg4+mgWcfwlUIjP0{1|YrfxDxE6CUD~`#Dm)mZd?V5^A>Ou zD^Q%bf}2p0f!hXda)ndiwu75gk@9p0xTzH>PhST&rQ+-09N?x`d=A`BaMLO^2e%8{ z%u2Pvy#a1U6hH@^zil6~OjRe2WN zesBw`+zak)a0{v$!5sj%xXKxD?|@rWmHc}b+>)x~-$8J9MoZw{19x}TpTWHk?yl%= z;0}RX7TpxwVQ@>McYyl<+`Z9j!F>qso@%YZeFW~lY6;*z2DiK##p)AqE2>efJ_UDw z^;^Mx2JXS?t-*Z`?t$u5uf72HP<5(TUxHg1L-YF;xJP1We!m9yaLfKZ?SI|1&gnsdQ@5ANxj zBfy;mx26`=x*xzjTa#+tDR9r!Y60#vxaVrs0rw-gwY6w$KY@Fp7LDx;xaVWrf;$Ut zU2GD#bKqW#%>(x{xR+yBfjbZGrMMJuzku5iR|(v&;MT`cJ^c;b#yF~{7r?zz+Xn7; zaIeMv3GNSYuhypH%tdha+H{=x6I@2~*lmWLb9yt_l0QY)4awt3q+>UtEjqqS_JL6F|!j0e@@yo%5fO{i;8n{q! zyW+QilfdnXUjxnrZg)K9GTaPqZ#?EQ+yd^+1jH}g3T|Hl;ujtU?yZC+;KISZoiH9; zF>w16P&>mTz`c`z+8J&GcOc;+xJYmZ6TSsk9NfE!4Z%f$dp|J-TnTXRB@P5v65Qd$ zY;dK(9ZGx&TxoD0Cawfm2HXcp6~S?EA19f>l?C@v(jaiR{`AT zNt3`;1ov6e$KWb~`!Z=KxXR$ZNctOG6>wiCodj1E+*kG5gNp`tv|fF1)xaI8hvRB^ zb#TY(;kX(e1MZu8?}DoV?z?)Mz|{ozZE`rcTHsF9`yE^?xZ}xb;NrlYOs)#9Hn{JT zar_9c1MXBZjvwK5!TpeoIS-Eq_hT~VJUjv1>69FBiQvwpGys6_xccCJPWcX8D!5-$4uVSq_e=dc;L^ces9zdf2Dsnq_W{=c+#mJZ zf@=uw_xhiJYXt7k`n$k226r*l1g;6VOZCr#YYOgvsT7xH;QmgfxHJd%SDKN9g|`T6 zWnigiSoQFh;4Y`t2iFQ*P+D1>RkUWE42HCY;M#yQrVRtv7F=-JW^kF{Lem}tmjx~) zJp^1kaHg~$z_kY_rFR3@0h}d016(#ZbNbWZI)V#JUkt7jIBWW6;BvqfOWy&mGq~`K zXmGjUY#9=`F5n_EdVuQ+u6Ra6aNWQ~W~>I+9bAcwh2VOCi)wHyxSrrjHE0U%7H}mS zYysB`T$u)sgS!=6>4wSRdV?$5unf39;CRF3;QE3q-*5uBe&EVAJOl1Fa1|RK2G<{4 zg+?^C0pKb(qOlDGSE&)jWe~WkjVLaI!BuHI65J4Q)f(r3yB%C~6Dzo(;9?q|1vd;_ z^`IE#)FG*aX+{T;F4NQ0yhy{V#}J~CV@+C83t}LxOy$g#uRY%Tat~b z;8I#~aMQr0wfqa*ba1JyCW4y*E~C{g;AVnLZ!LkF1+HPM)8J-(>5Ja1Vj&+JWZn zVQ@X#)4V+bu6u{)!95D@mJUn7JqE64HqFuF;BL*PIeG$Iuk0n@R)Oo2Jqp~D;Cgo~ z0q!Yq{j&c6w;EjEjt_!c1FnC^soXAxFI>yz`Y1=SWaJX>%a}oISlS4 za3gZ;;9dqdymKvZ>%ooc91d;+xRIUbfqMnq=*~mHZ3K5m=dZxM3T|xYUEp2=Hzqd~ zTpqabx#hsw!HvtMHMj}f#9Uf~o54-UJq>OPxXHQif!hjhQkPcXwt<`4r53pD;HGq0 z1#Snp>0Rc5dmY@gE*HQ#z|HLPIk=tRW_0ZUZWp-OT@%5*0d7{;72tM*o7;6VxIN(J zbiD}fO>pzOeg$qXxOv?gfqM(w!fsW-?E|-xW(Nm25*B~#8~&U#t5U0F`Fg) zgYXZTA^ZsLokcMN{%1^z-5UNCV;iu^SZMfnz(?@MV$8-OnHgIpag)u=%An$3Lt0ir1BzTqJHG(_>JHaM`%>Y9S+S)>}m0%mec7h!QuM;>3b`tC& zc!OX!!5)G)3HB1aMX--xKf&7s2MFFFc$eTH!FvSn6C5HqOz;80hXhNE%^3TLwmv5K zgy2(x&j>yz_=4a|g0Bd^COATHl;9hHp&3C_`t=yWw*=o2949zI@IAqg1Sbi8AUH*E zn&2mbGX!S|&Jp}faGu~7f?o-KBe+2DJHa0W7YY6(_#eR~g1-pM>(QVrBEK@33+f|>-i2x0-DO9<{F zxSL=p!7_kUnYQkst*W$jFTrwx`v~qQSV8ar!Gi#)3T>?l(ZD8V-b#|XY9 z_>SN>!3l!z2~HCHKyZrSG{KJqKM|ZEI7@Jj;AevK1iujcO7I)O1%lrR{vfzW@F&6l z2rd!)MesMlWq`y83>EI~Pf@&KdRXaPu%Ft&(RUJrsf1RbO}#s<*VB!Z~~qX@1XT#C5!526O^`@XA7FTzw$ce25;P%bNsvj9O^`#- zji4vNtpLMX+UiTtpI{Kd?F7RKMiGo57*8;XU@E}y0&UG8m`yN`U?IVs1a}kMLvSC# z0|XBN3@_0Zg)^9f6D$u^c3gHt7L|9|K!1Iezz#6Tziy#lw-e9=1iwM>Cc!>}0|Yb` z!G{Pw1Q=+_fC+XU|tyif1}0p*5aKEY=MUlJT4I7V=sfU?9uSz2#Ny?OK7VkK^cMy1eFP*31SH12b?*M$iO; z$pq5~W)e_{gD7A@H2ffWFiUCcUVz~t+Pa_ML4t<~9wS&qu$q8UDu_}lh*Bzua>!WC zSe+Sfr_+V+jK>Yelg4ih#`DHs48{xC3Xwugh7c=l6$^l&TzC z%ZcLdbaQLEvA4Jmv+FV~?Wx|r?sSE!L>l(@rhC*O2XoZuNoiG^vr8>m+*O#;)u+`<~$}e=~uXW|0 zBJwK%|Jt!!esnJ2+~krk7?-uP%`H#)Tz-cuzhHdUPLnHttt)@0E5G2_tbD7;=j}%M zynQ-d`31*i@$|a#*ShleiTqQb{R@ug^3e#?>wqhNtt1zJ{~x#cOJ%jdiD3v>sNZU-FNSxfm?VSSX_zLB**&XvE`m4Cb|zkmXl z+bMG8uXW{5apf1}WbMyz<*#++&vNA#&<()t&vxanb>+`<0+yBE=E`5|%HQG2 zFUZZxH&MRcjQ-8T{DS%D-%hvukgR;Kkl%yy`6O?F{Jm$o6$-Kn1_iF3GXWHal0r>F zYwp@mUy#_U8Y>!R%u^Gw9CgmNQ6|Kw7yu$+Fj$y_G}(ekJk$# zT?fFZQl~}?ec1ddg^_8^jT>rDDBe=o z+p}QY3DdVMXwKx6B&Lj=w<~kngb9Tyqri+*tA&fzUHba2ku$f==~$h2dQ0A^W&1Nj zca3Zty`ZzEdK$>(6htHGf|6=e*UQ%?3JWdm_()0W#LeZqwjWzxQdk(>rx(_sUeETN zrjc4@VwhfDkgBRLX|G$buskzvUf+s_qEXAoRWzr^u=1H()REhBT1T$hHhXb$LD8n% z<0>X?%^7z>$GBmoiAX^~`?k2QZ!M@SOfhZl=#qkhrMe1yLd##!ymE5y#+lp7Ix?rl zN(#5mD=aLCPAyF3#mq>$d$np*?Osr{^u#fdxPE$ce^p5$qD9UaT3EH9scON24ejH~ znx{vj(MUwsaw56I8WM?#9kIf~%(i)L1yiFnlTxfo8x|=jS*}_&BgXBWG3KN_AfG|` zHIemom5IdEW1`W~lM}|S?RiZbhioZ}MI+mX6~r}19_(zMEbOeURZWP8eYK-s138^vKtf*O2kVwqYPnv4ZI(1gd<_+Vl_EEEU zL3?hjN+jm;dKQj@dY;s~TGclUTTo4U?T<>K{&6HO?;(zc(IGe6P3yu%#!CE!$C}#Y)g_^>WtIK6=iMuAEds-pW~x>73s3+^w_rCnC|I zz;~rb6pd^jU9n^Ph=o?is4{4WT(hb&(WsAP`)3-Owrtwyf`TmzwdneyQF+@SQpd9S zD--(0s?yq}xjb&Gv3+*w6Nj$V#xH2DnLKW3$Ef+OnS&EYC8_~WOx#AOJ~d*vUOHh)w;!d*%q|`>yf*yqIc~=8>Ygg(FeM<3|vRzBp9moN^h5C4GulZezmNS*hS00!=q(&VA_HtHlFH6_u742i& zXYJQd;&MGJhSrwno;s^*QG+o|jqv#2%WT}6%DeRH66iNd+OoKJn_zDk;(++mf1CxsrF>JrRt()idq(@-A=XEVTILw-qU^dPjOHUp?rFaYA-(Xn9V;1bF$w}Dl zp4Hn_(Ulr8d>{I|aFWqmOYyp4$oToqY4B?yw&R$ljUD6X?ATptY+AW}Ryq->Q9DPK zHDq!QY*@KXjdy`u?x`g^RxE&e87DzGMWfm_m31sy!iE=md1I1l?q4*NEiK+Wt9kpu z_>>b8Uf!%xV^}WPV}+GaUe!7V{nfley`*3tg*l8kN%LgP)C2dE3i&biw__iP^Z` zld7D-?N03H&njz@ngezwj%wQq{%K(RJ{9*r+?Q+dKHZD=R~z6OiTbYloyXy*isr4A zY&g~Pz>?xENH`-0L%v0AHm^Mc+**q?1t zhl4*ScWj4#so5CSwtWG_EBEs-o;|M10reOvQNWX<2^S!$cO&(q{0iLgmuzq+S=ai6~rm0G){Ze1O zud_ANnCY$RXzR?hrdN0NW;)t?io9%9YpSQmRC3`BKUmLHhN#LgiL$C3V{3M%8h58! z(nafQ+Ix#kWvHqQ@m(^N;V@OeudB-OzKcc8-5qV9THjHdf%%J6tEr4sm3)7$3#wh9 zBeF5m)VtGE#;8i3HxHnQnUbQSRC`BzQHiOHSCvV-QhQRxt*Q1Fm^0bau{&M7GTpng zqiI>Hy{R?bQ&ij0vAeI+RE~o}gGEiHP*rkBUR4UjG)qzUp2pVQJDa+pIf`IL#bKc> zvm#B+&B^A@mJ|q`peph1Jx&I|_K2lHWE#xkaFH}v%=cW*;PsiRV)5(1d60nBOd2I- zaU_EEi?nhhWwr>isxs75OlKpPnX4)>UJ&Q~b~-z;sQI=XWL0Ij$4-x3>xHVqxFwMT zG36C(v?Uj*N-jx?EDyF0r?D$JHk7-3u?bdHM)lyFR`HtdbW^&yDAC>B zu{Y7v)6oc$%K)GIs;MjoKe zqky*;i1TYr{8|LXnxIKCvy#23-RX8@;%$Ac$vvsoOjB|nT_OfAfm}m(s=aY1UMc{t z6IvzH*qdxm@9jk8;ZA9Ny_weH4QK|+oGHm(Set2YZ0&1G7u!ZUclRcHD^3RaAz-?> zwXbJqvNP4Y6AkCN3gac2n9-T+_Fn>E`OO)a;CCYfsOgOIHiy*;wn+~_+byVE^=t-To4APTx}QM@07D3Tsg zD8ns^MUrUl;zWHSxw3j?vbJUw+?9D^qP)JZvo$>%irwVNSXi5VjI3_h1wmRdupGR5 ztol?-a$`p~RD4MH9?_At@yUL8zSL&BP;m)VKu+|LGC6SxINW8>z6O#7 zygR1;*%m#j=EyK|Zo|1KU0I)4nq0EFb}_iX;mO)?P;Mg5aSso96whR zJQkGYOMTZ%liurPzUyWDx`o9Og1pN0HMNVAiDi{=gVw_h8WS0tYGy-&J4|v_qP}JW zT!*Z>uc*F#Q8m*sH&>2tK)401E_v^(5n6NpgZiB2P3O~d4Qx}-W*9D zjJW#AmBWqV##g;6QCV9J2qn3IQIZQNCAol8k_$*BxqwxY3uq;|fY(!pm5I6){`SN? ze|ut{zdbR}-=3J~Z%@qgwykBa!!nz}h{rOxY+Vv=X&4DCNz~QDjay&6 zZr%Dd^+_0h)~u_pf;%F&rYcdjtU6hWjRe^81@CIJJa-m$Ql1RFiwoQmqUGF%>XI81 zfN7X5R-JHld5$3FQj6L4c)N<8Z@5tAdDOh_qTMct2~lucwt}|HhKh?`r-@9mi*;lo zr*>7cZcDaVxEBE^wA2tGfmu*J^sC5Oy{Z;!YuBr;YSrRoEwq1DfI2iANnL%S9(pRO zx~+vhv8cJ-Y?zg;xa~O1#fGq*0#Mc@s#fp}Z|p;r>1Zc%pg4$7+_WhxiupY%?OBZI;J#LCq?NXJ0?= z&%=JlpNIX9Kd(%Zhy9LU4*MN{9`-x_JnYBadD(uve=hdp{d2J&@1F}eCAol9l8gO# ze+$@;_s_+C+?|VkC-&q1Jb!zloWDIW&)=Sy=WkEU^S3AF`P&oo5MS-;#NuTA>g4*m z>g1Z*^>u*7tgTyL3cVZ*1c1uMjm?O-u~{BBdB|amuBt?f`1b3`aC&*nu7d#)Jt#O= z@9KFAR;^A_ykm+TD4sC$keZ1 zvZM|{&^^q@iR)`?H-lpssH{w^s#%lVQt4x1TE~4AI%+oyE$C*Kc-b{x7Mj;B3{5%| z7dO%TUlAn`FEgjO-p}}KX~k4mj=dg=Q+@TVE(3w zsoT|6Xzf&08S7KW3AuHB?e)-7MW(s~B5LL8#p`RUi(svrzbLmXl+vI!M%9$s1e3Bb z6_9M`wA5yJx^MsXNsSLfQq7tnB+bzi6s3XAo^k_mam| z26P7%rLcG?TD#uD)>4--QEN1=@N~N>7JfULu*=9=DO|sR0FMct35Gj zfnJEoR1>trQnw+hsH^55#qu6?FSZU$qA+O7ogGb8sm7gY2>S_sr}T?%xI;|R0r4@1 zE+0E@U(18)sBD%Ouc>}QcK^b2#*GkIQ8-Zj?{;_sxut;>(m?f>hG&yo8dxC>RDWrB zYMD*x#w5g|rC#V&#cR|iK=oIJhnu?~V1+bL{iWft=avRmNCVYhdY)GrSRoBmf9d&N zX<&skP{Yt6bWhlw=PY=jx#I(POZXm0i2{U#M*(iANhe8Ice?$6ysaShbg9qN$lD51PnY^U zjl8WO^>mrf)5r@2B>Q{1%;#z3Z3U^P%Y2?j-d2!$y3FTk0zo%#W zJdM1qAocWYpQn+x6{Mb??ejG9wu02tvwfaM-d2!$dbZEg$lD51PtW#w8hKkm>gm}& zPa|(DNIgB<=V|0^1*xZJ`#g=jtswRE9G|C=7Ya!B_w*car`g)m$Hz9>Xm2Nl7j12+ z+voV)j=ZfPb^9Ej+mW{wq;8+%b35|3g4FGEd~QeHR*<@Vj?eAL+X_;*&+)k(d0Rp1 z_BlScBX286-9E?XcI0gZsoUrJ+>X3ZK(fEv=Yl)kk0a!51*xa!`aF%itswRET%V_r zw-uzGp6l~8^0tE1({p{EM&4GCdU~$U)5zNjQcuqXcjh%Uv?Lqbnv#3F@yBdSgK1Vz z%VoWf;*zHJd4F!!`$$R@eBPg%^*)mQ70P|yM_$wmNr{5b`{h~hBPmhvdA~gCeIz9c zKJS-jy^o|s!RP(*toMuDq<3O-MlXFZLi zM8W6j@~o$k?5{A-=V|1Hr;(H>_&hx?>uDq<3O-NI%X%6~iGt75^Rk{sQljAV^t`O6 zk(4O-JUuV#X(S~IK2OifdKyWIg3r_QvYtj#qTuuNysW2@lqmQ-JumBNB>OAO_jww5 z;b|l#3O-NI&w3h3iGt75^Ru2tQljAV^!%)+k(4O-JUu__X(S~I;7&f#0*iet?K4D1dKs((Ngj3$(QF`RbDmf%!lV zmrTKcqa(0-F4Jylx5AUiGaUohqV{|Y&@y$52wI;`vXQ>G3P=Pl9|jyS6+(}Cd1!4FtkV%dvu zEq%J*f-9VGDpY0xVuKF`V7acP_w%kRig0RFX22gsI3wybl{|`Y;?q-A%&>KkmXw3j zpk5tU=-@?}4n&6q70WcG+nX%?WWNPhAmOB`%mT!Ri57Y~x-A`kOZP%>MG{V;$_zlT zFzknLIrQG{G{hq=Hg(4q&Zat*m&X>)pL%s%@q`y;C1X6fs?M@a$IqM7iH!6 z;{YdOopR)HfK#vDa$IqM7iH!6;{c~)opR)HfU~ZiaxlZzL0VD{PP=+_TycOGWjg*i zz^PcL9C;kz(RjsyBwrtI{rAoSz1R&9tSut>n+C> z2Y69djz11?uGT3>9tSu(>n+C>2Y69djz11?#?~oE9tSu_>n+C>2Y69djz11?V%8}~ z9tSuT>n+C>2Y69djz11?de$jN9tSuf>nR5_Y#pQ}<=~vGSH~3xcu}U~j{}^ib;^;) z0nW^N%W=g4UX+#Nj{}^ob;^;)0nX2Q%W=g4UX+#Nj{}^ub;^;)0nXBT%W=g4UX+#N zj{}^!b;^;)0nXKW%W=g4UX+xB)3qKQ%&^NrTBhTV1DwKjbmVb>leXS+TycOGW##ze z04H*ta^!JdSQb`DBk`$6>P`hv+z<_?c178 z!3W32l$xpV-3Y8+Rha7n6r4N7{!p<3M3@0vU&NIhV>nprvn64Zf-F4#6?hhr_<%X) z2!qWNvNj#$GBsw5GDc%*u&+W+s;9N1y@jB{SMVnBeuT@JajbD1>KqTE-RVwPHGABY znnM*MK3Rw5s!9Zf!Q7NAxL`GAOfn{8Nw9Z9tf4#8)RIoN;Md#3r_^k5HGusYz22Jw z_*QCXL$VhZ0fP&&N>J{2SGoPwnK9Ei5eq8@FM+3w=GIIntYqay+26UR_GOZdJ5%lL z>DC@_aRg<+@9Qyp(2mZcwbzde49rLvl?WB)CRjr+_zS*w-kIvz z85HOul(f!9xM|!@fsx`xR{~qRk$w93Qgt`tUM7g#xsP3F>%X$rYx$He6D!<9t zjFpG*h7Y#Wd*Bm(ST>*O-4Bbr8+YTJ5$=zG#YQQg)9|&nUleMZBvY_-AHHpNUFSC_ zd^+yU0)<9u8fawLECu$UXlhDB&2l=Ln|U7%8;*!fkljhfGti9PdtkeYmb5^4{FIu0 zeFlA6z$2>^ZpxDnBeKwGBi?g*IsWlIe&$ABqgkBfAF>$eX7Gd?4|rl~))R+8#*8kb z8(SZr6Wx1SdqfN9FyjmTo09|8-%His2R%jip0-raZrHS@E!Eoyx5t9OIPzA;=YHtZ z&=w@=s1KP=xcq-_c4+-2wu>S%4?e2lWz);x51)i%t-LQj5x+{r0 zC_rXgI@7YZv9}xM`#W0sJ;6sLb|yVf;74}MXoWb)_tgj*tyj`$gI+ggTxfg-Tlper zWv5N3Sa?u6Ij&aaH&wb3K3QmQgoWnNE=_pLLu6+&AqX#{`}OmVIQ*{2#g}DW7Zekc zYrdy|s+|2XnabYNl2V;EkX*z2UBi1I2kVZ_VD`W^GfiperbL5KwZXq@CH|F|3@Xmo z0L=KZ@fCF5)%+&RHh&UlNw8mayaYMmlk3PQ*E`|_j*Exv893s8H;5?9F*krdKxUX3 zUpH>R3Vwql&i3RmisE13*~4l{JJxs_3w!nzfzjfV4-5%(J51x1v#7y`-K$#=(1b!O(a+2dnY? z5SZ~Z<3Vh_pWChHpy=0n{jWglJw&bd@FCSe^ugPmW`fF=BfJL@1&!abUp@@3^KXetk9n`oCPpRIhdRluW%tAR0ZNK!6Z zyIQ#htsTRoM`U~JIFihbvdux~E-}Y9nqtbe%5`XNoNW%Xz2=T3bFiT$Z4wE$qr@EK zBD(99|3h;VZF89IH8+XOP3Ex;_;K$le{73vH278JYiMv9k8L~OYjFlygk3BrKzHyoQT0r@gDAj!CsCW2au-osm~uB! z+nDkLqE2PX4~g2rlphh*z?6H4YGTTdiE3uby+rL~%1?;e#gzMqYGum(M71;J0irsY z@>8O^nesEDdYSSdQG1y3bE5V!Pn{k zny4=_<$0pM%#;_1x|%7!A?jMD{FbQenescLzRHx}6ZLhbyhzkHnDP=)-(t$kM17kn zuMqWJro2kjO-y->s9TuwI#IVWItU&i>RlV z@-9)&Fy%d>o@2_tiF%$X?-TVKru>Jf-!bLCM7_wA{}J^vQ$8T-Ri=DM)ay)Dh8C+Y*H zGEU_vOwA=qV`?5z22+O+mBZA0qAWPshNu`*hZ4n@I*h11rVb}6pQ*L{W{F?BRiW0*RIsBugkOVqJU9Y@shOdU_u1g0KKR1s5;BWf~Jk0)vh9L7S_ zG}zdms2NP1NYsf;Eh1_bQzsEs%GAk3&1UKeM9pRD6r$!abt+K{m^zK9g-o4J)X7Yp zLDVTsok>(BQ%@vnF;k0)TEf&>L@i@#2~lwHKq*nROf4g76;o#uwT7v4h+450W3w1*O^T}?uh@v$cp%I*hAf|Cv*nB9Mpk<;Q8Z-yqG-tY zMbVJ)i=rXp7ezzHFN%tGmGxV+t*pK0EH&!!vN*>d8*zt05|KTYeLK`1MlibvDhVDE zoU@-T$;lq6u5E5fNY<9kPY-m)*mOID?c!Iw89c zFWHhkZfVP1u{|$|$(~pC&b&2?Nk%q&vSo1RMv{^`DZ9rn37sejvqNnCOA4}Th+S+; z`HsLOCUd?Jb2bVlNm(R?B2Az?Hmjz#W(mTQExE#>^xryMIK%xJU6}%XPMKKCHRys5YPl zU7J21wrJeq*%dnh(TkGa&=RV(Vld~9>O%^NVBmL%Je05wNp2llJ<-K4ZOpP1`IykTUO(&LBQbCFB&lT^os@zKK-Hr zgHOL`z~Iv_8u0Su7Cr3CQ-9%rm#6;10WVMeg+=>HJ1 z7Y=xNatq`8K)}nBUo>R=qScV`i=rXp7ezzHFN%hYUla`)zbG2euKhN8r+(pB$yfw- zWyk&BNkG=6;kNCx6*|etx-?rRxJ$F8@R7+M5VC$Bg|OSFz2!+xHqP_Oxkj+EM*vET zo#@G=?AgSHvK!Qspsd^Nw{Ja(%33eGoju9OMiQP~?nz8G*Jp2jA8g3k6F(S}`*C=v z!m^LLL!r)Yq|f~+>y{+@?GrMY^S#^flbq~H?Cj1@A~KJ=Htj!jOJw)*KQt!q7XKtC z8(I5z{wGP~OG1^nCX|$z>o`n_;-#n*R>s)t0AY=Ex*JYmEDk=^k|`^dRj~BKgry%t zUFza+OQx(=*5KutOj*l+yfWbf8~iB6E{89$WJ;YkuVHIFHq zh+4pu%|tC^$`+zvrwsR(UY_$Si(MsVFC6*=OQvj9wjrQOrkqOV7c(VEc}tkGgQ#Up zNfEW2DGfx`GNq9;RxzcCs5MMU6SdA;d%m)rDa}d?7Pg)#JBixJlng0sX38$g+sc&P zl((HJt(2E!N*hrrrnJ-5My7NSm1asOQ7ugAA}Yg_ZlZQGrH80Crt}ik!IVCtx|p(u zs2-;5C901p`-s}hl>J2QXUb_roz9fg3CkHwIY87Wm~sYPJ&P#^iTWf{K0(yEOgWRN z^O$lLQJDUP=3uN2Z*sd2-Cbirc5%gjVV?5XA1r~3ICjef2QM~ z6Y)<8{#k&3X5*i7w3p8hJ8tf4FX9Jd;u1&u9Avx6O!Fo{0E@27o6TFi8qic84bgO_ zd0Wi9-7gHSH?@^UPr-wL%6rKfQ-WxT4Y{Jss96X?-5f($u0}_iozN+^yz~!#V}z#Z4?Hf#r(%&)BGhsD8e9s#l3m7xR+nyDi52F#Lb7y zN16Gsc?~SaHDNid>w`|o_oh(J!{!t4ajE$v9KT{Wm(wLL-jAJfBONqc*9)g}7n$bM zsxsMWvmjC4aL-1~XG~aK8}Ecedd1JMvZk2PO} z4<~9?d+MN{X{e!2y}Y#RZq1zjhdh+_MrN9by8~?^kH=LYfX>i*+KIeJpT+4`Bx)p&n!Ok`NKy`fD z!g@`RF{8>b%YuHvHff8P7Oa*X+E0@!v8WZd;7s|6SUJC<_h5GDAjerlVj!OnU({}d z8`^beI^o%z>F(}rE#}9&S1@a+H7ur#wT7!oarP#Z3unux5rn$g8WDpkjfC64M&@Yt zbo6yMrZer$9mRE=grlp|rZw79qPV)+)$AgUYH+Eid9^hzW{t7nJbBmm7Cf$<${)Ij z8YnIM9f`juaSYIH0_cy6fzyt+lsX6{y8>7>)0${0>n&x2rEIj6O_s9RQs4{DVYWPl->%>0oBU0R;qm^fN#=rk?7tC4Q&Ou~8S%&Id_iCOC`_zc8o z$n^F=EnGJOdEeS#ZH!s-tWEH}4fv!Nw6>Tf;0+5}c2eNIRtqPK!69RCw~e;8D z+->WbwFC5(QC12bQ$>v(@MS-LuZ3^eY(ITGVZ4D^jaF04Dzef{J&PRG0*%tpo$TpN zb@wLI-Q6AC%*s%8V42)GBm|!pSs)}Xx6|bgrk+QaVF7rApJL9e92c#3c7h9LaK>yNET_5&KruBKK ztsM&9zR9#;IBYd_z-F%e^tZLH-5rj&x1;wR>q_e?jF~T53M{7l9C_#~Oudw-Yp73f zwKR@tE0}hjbsf3^zkl>yG_9{fTcZ#79>RDyJ+r=!k@Gd{2K=(UBUzNfFOOUux%aE$ zkE?3mw7!LLd84Jk>d?!nLf>WTl|R!YoVQT4eBXnPKh>PO^@!2Y zL(=-DbsM6)-BL14{Ssli%TnOJyqXwTE{k+2jKsFu&1Gssy*m1TQ zH$8wB`V|%T1XI67a!=u%n3aR$2Gjdc@EH<(mZ{$%!C!j~HsDSZAol{v{RV(Zo)D(> zJLqlp!YPgG(#?tP?iAdN3#Ui~?Qc|}hiy$a;`>fcFWy8maDQg!R`CaS1xb-jV-+-(UcNOry*3%=(Y@Uqt&qrrty`@*#laon4Xh zO(ct|IPfoz!U)^dWq5B&ZwKN+;>5b|6Iia`8admpg^h%usEDP&^h=6A&7u~IjERf| zoY5G}J5e5E>TMixG>@rw5(R^61BVPOIut{?Bsz>4BaD%#c#NuaW?NcJ$Q=rr486C0 z1m4l-Y<3WC&-baDqfq#Q=qP+XSslHxADbwFY`T>=u*u4%+Ro!}~rKT?aO;^P=$9u+F{n z$r0b|)Qr}Z(e>b_=mwaDB$V(C#jgp`7E6I?z#gj8cBcM@vXjiX!?+Wj4nzKZFc(Pz z@cqQ^Nub$M_A~WmV&F0K8d19~ePE(cDhYBQL=o~WYCE;`crsJY8v$=`N`vg<}MCF~u^kF#0KQH=8rv8QU&h=pM z-bf!E1J{QauIPD);e4k4jY_$IssAAAGfaJ#C>TVJ5F-rSOT1x!XR4Fc6GNkhR5y!W&POiME13E}x_Twk6ry0Db~@8^V!q-oq10Q#HB`d2Ov@qR z>zNiM>Z=Ssmclo==+`af06cg-1BI1+`%0D-nbB|ddx51ZI9Q0@7>#}_`fZS)0krp# z3CiEaDG%v2u6|QA`n~AQ@MI?u+A_$D!nkXUcSsHo?T)>Po}P|IK35XGEvnQ+Z)e&N z!ha_WhO#0odN&__M}NSyp(FrX71*OZctXPV4@qd=A5+uZ3*S^1wPo7-dWu@Q(Mr4Fj46Ymc?Oi zW)ucw3>ks0jYS^@bkT>Rk1%aK={?4@NR{l{^?7 z^|hzE_a}=QV52J*{SO~qMgPmR1nGVN9lyAtd(t?{YN@GHoeY9s;)amX4(XN{Uba{^y8%vcK$F%h%bu9Eq zEuAnifVIGH{_R?bOsK~3u|li{j2E2178lJJOusW^FjfiRWCS=Vc7mmRf@zzmkZCYb z#fawbiXgU+#byu?_?hw(Kq*=bh5|dezhWg!+e&(6@Vge}&0*T9ln47?IQKf7qd?V~ zPu3PNEk#lb-MC7z;Z7!8it?M&+= zDk&PHt1s1>M9a_^DH3nMVIy?LJtUcC+8&}>n6{s&4ATw}wVP?5AgYaNXA{+d6Gd=7 zP`?lpnGj-Kv2F~p9#@Eoi)IYslKTlWU_-E-sZJKd5lU=NY#-Ckr7~a);%XG`@B`E+ z(6yXTG7yg!5_J~SK1;%#|HY zeXa1*Ko9^|E3dtG^|@+tRBmQV$O zogGcfU~jwDbWc%jN5}5I&I;GFPRzu+ay*Llu*GME^p(6H$SR1oI+!N~$6gb=HWs@& zb{$mudg@=Os!RIX`Rn^Ee7eNGI#f|(U*lW4`7b+7dc*_l^uA7L-?nr++ziE)sh%`B z30`BbjNK3eAAQ48&W4}8$xS!n&$wS^+O_0$80j$E<#_*^v74CoHM#~f__;;Urp^F^ z#cqW;+Stvp+nDwZlDUIvHxhLhT!0rf?YqSOkZIp13bqT_%HKO<_cD#%He;||KreM6 zFx2=F$-z+LKB9ikG>|Zr9{nPdM#1qOs4@&d_L3bDGw}fBSlyR3rEa%pPyr)3BZJ z_>HgR@3?UoJD3gPXO{RHsDo7!U(59Eq+G}J9Yn1MGdRZTY~ybZ@LNw?rl*s|acU&C zCk`V5gEDZs8EkB2dLwCWhnVwfLI(#sm9lt}ba%i&*UoAn?M9|IlQ#Tp#}5z^<#smC zX7Lu%+X?%Caefym?Phw0lwjU^m>7HEoeX3L{PqKt#>oroYw=E|w~}Nx(>sWQ4IC=@ z;(+)bW(+a%F`V}?y_>F{#`Hd-4lsQmQSb`T4fa6pOjuk+)Y%X}_~S&ni~b)l-FU({c+{C7oE{5mP#!1N194kj3QTngx!CK!I8 z;Ef~*vkN)sk3I<1@8XXoMe*-3{UXwZxr32eY_1)4xn6;Mts?YKC`caRy-; zeu1&#PcZ!&y8aZ?uP5pmrqh5U{v6Y3SP_37f52|U!F~KUSkIF9Z<$U5jri~J?%S1O z@t5ez%S@*+NBmW$-%K`NXZo!~y}|T5h85>AxU}53>^3A`CVU z!eU@bOQ(SjGnoDumt{Fje}X8B=}!|CWBPMMF{Zyj6g)a<+`;mhPU8*+kIq-=Dm*&> zKomSW-y~`j)BjA=7^c5X)HtToc!C|v^nX#_@l5{@Q4^T{0a5S-9gbZbzP7lIs)VZW zH{?C+1ZJotIu&l*?6gF0rWJPy{y2X~qPb-@oy~xlWHXszP{GA83`AGq)HVPsfi{lq zVX!86A5eD|fLJh*$zXV`q$70O~2FgJ$_#@4`6#LPY%q`6)o z>_uW57(0ob3~R#JA_(`+4)~d`x39ZhEQ8}eP-R~tRyXW|Ntf(O9;X`)T)GA?&iza< zmSC``v*pdnSu1P!S=ThNfIa|8{k3a!O;Ayr|% zg42+y^8^j43eCs!A=U7h)*N0K5E>rFN*oXxo~2405E>qcN*oXx9&1V*5E`CMN*oXx z9xzHA5LyWoPaF^$p7lu_5E`E1NgQIq^Eo+(goej$5{FpuAWh;B3m%I}9Ad%4FNs4e z{G3ay5fU06Oi9-e3m!5_9Ad!}BZ)&ScrGMyhy_o1wIcG(3imIK+a7 z%@K!K@aQ<=5DOj;6ZG}Ar?GVjX1=D2c~fj2@Q`$ zBM!0PA!o!P7Cg#~IK+ZmZWD)C@c1#}5DOkAMjT?nBg2S8EO-DIafk(v`63Rn;Gtcd zLqfyjxQIh6c<2^!hy{<(A`Y?OL0QBh7CiQfIK+a7TM>s?@Te-{5DOkiMI2(mAf=aA6wcqrl!3m*1F9Ad#Eorps$ct8_zhy{;fA`Y?Op-RLd7CbtMIK+YnArXgI z@VF!55DOkp81JbZ{a#Dd2P5rP(9w^`eiQs_(9d2_7im0hQo6KJ1K%M@lcj?pW{~A9l!s=lHNo7Cgs?owDFLKJ1nS&+%c$ zEO?F&yJo?2eAqb)p5w#rS@0Ym_RGX0rI%nAEqIO(J88jleArD3p5w!gTJRhn_Rxao z_^`7UJjaLKwct5E?63vT@nM%Oc#aSIYT}X7OR(D(JjaI}x8ONG?79Wd@nPpJc#aRd zZ^3hX*l!D-utOI- z$A?|I;5k0*)CJG+VYe=Ljt@I_!E=1rwF{o(!#CPIX>*}1<&zeKTkYTdI@&+81<&ze*DrXE4?BOsb9~tS3!dY{2Y}!?K70fSp5w#5pLnG75_}8@p5wy@f#5kl zd=vSjt?Iig6H_~u_1V%hHQ1_>iAoUnG3JT&Qxf2eTbR+C`_x{Q|^2T zhnf30*QcKd!~sNR?h`PV1PjS}#E&Ow`iTTyzslXOBI36U`zMxk6N$-Q8{mT}Dx$lu zy%&Bk5I?#s&K6<=z#eeQFy+-GxtJtQX=CI<>y z`R_$8=q&d)xla#OjNISCyI){-- z8q(b&XJ{>aY1X;{&g?-6k(o~wUxWLjreQLp2j&23;Mlfq{&hhb*cg2W0@K`Jbu@g( zgDtxu(~|)siT3u6UjFqO2HQC2Fp|U2$rYty(>@QYgeAax2`;eFI{;G-?{P>zH;R$eB;Vf z_$*aXbAJ!Crfdhh@Np{7hfh;I`S5|NhlkHpJv@A@>fzy&Rc;49Smh~vuF6yRGL@(B zT`EuEt5lxCH>o^@FH(65-=p#rzDDIKe2dCc_!5<;@Es~o;VV?0!Z)Zqg)dNf3g4gd z6uv&?DSUg%Q~2_fr|{h=PvNUmp29b$JcTb#c?#c~@)W){5P#>5U@& zwn)Dt((j7&dm_C_q&JK77Lk5mq_>LnHj&;g(mOD?mzfk=NS(jSTR9+Cc7 zr1y&SCnCL1r1y*T0g?Vxq(2ksgChO8NPi*HUyAf0kv=TaM@0IlNFNjF<0Ac)NS_et zlOlaeq)&_V8Ie9K(&t3_Ymq)L(icSf8k-ja`zlrqkB7H}s{}AavMfxw1zAMuAMEY-$ zzAw`Mi1fcA{hvrb5b1}M;*RYY&#<_FQca|~NDYxjM4BT~Q>2ziqauxoG%ivm(p-_| ziFAla^F>-9(xD<9Ceq;|Jw~J>L^@KWqeMDdq+>)nR;1%ZI$os5iu5><9xu{Dkxmfl zM3EMWbdpFXi}VDMP7&!;kxmoobdk;w=}eKHDAHn)&Jt;fNJ~XpCeqm=og>n@A}tr` zJdw^9=>m~fh;*SyPZH_LB3&fXQ$(5&X{AW3M7mg{)goOY(xoC@Cej*_E*I$vk=A0W zod@4@u2fekTJDPwZ3o~rC~`+?OFEM}aU_X63#De~$;t5oL;c zntD3q#+3=`0rd=cCPQiJYW1L^`JD@%p1PXp}8&puG z9#H2xpgt7@3VzNTR8VCeQ0F_KJ{<%Keme{c>N5k0skt6d7dfCl8wBcegAA(N1L|T2 z)FnZnEKX^swLze+8)Q%w9#Gdip#Coi)K>=?)ItxauQ{N;9t7%!K?Ze_2h=wl zP~Qv!^{t}{>P83Dw}U`^=ct1Et^?|OL7;9559*eIJo^@T-1mJ4)U83FZX0A!r+7f! z?tr=@2-Kb7K@Di+=>>I{1M2P|P(KI{YC!Hwcv|X*4yYdmfx2gqK~;J{{n!C@ZxE=T z3^J%H52*VbQ1=IcdSH-2E%t!=sRQa~L7*NSWKh)}P(OD-{UQj|F9#Xa5)Y_{98eDj zfqG<+K`r%wdei~+SP-bk2N~2d52#-`pq>Z<^<;QZ1L{1zpq_F-JskuJzP%pQ_r4lW zOFip=dM*eQe6|o4)PQ<)FR14oP%i|5f{(uk71VN1Oa0aX^}8TY@WJ_@f?DAL^`Zmn zr65o*hX*yFxrAB|s8<|NuLgmFZ}11TrM#eCcR>9i2o!wJKd7Kqd0Og^4yZSSK*2}< zVL=VZeXBj7-f}?wIS3SdTND=5fVu=PsJ}X(-VOoaHS)Vtw94XCBod0Of{2h_iVK)rudLH)-8_1_>+@R{78#+0|EK5#&N z7yt@4$vAqTG}Q*BX+fZ1vyMRpRp*W=&2T_PfQ%3u>4HYIqQ+V+I-2Mo&wPa6pX=0yQc$ zC~eF@X7aqC#yX(J1%VnL8k9PqXWu4IOC9TgIxYy*@kbR@p#y3{5GdGaXHWxuv!|ts z98i;jKurz}YG5(t1$BZ0YDy5Osi8p)ET*=3T56gDYI+c;8Alb=Ob677L7<8U8Ps-9 zOU-gXl>~t*4Gn5wG35nS=75?V1ZqxbPy>spQ#~y;*8x=?1Zv(<1vTFRwIB#o#UO)9 zdRl6s1L~w8P$!25HL#fSf?DK&Iwc5HA~dLh#Z;50r79gzRY9N@A5~D*4yYwTpq36Y zsI;f0mN}qmfAvp+OBSrkXu1wZ;LpHVD+ZqYA3d0aYIa zYW-0KwZQ?kF$mPAK?b$cUBW%1%ZOyDF^kny~h(%dmT{wfpR6%{x0d-CgDA@Wm zWJ?XKN8jsl-=`c<=LLa+y;ehl8d#6M&jaey4yX%)K*6@JM-kL#98ebpf%@!G1@$=x z)Wt!dU^CpK*ix4|pe_pn_4z>twcis{mph=Y2m$TpuRZBpw95L)R!Dk zUk(EGm7@ykY6sLcL7=V;4NALyAae<4ds^!M98g~k0tNf~4eH(J1@(0Y)D1zPV5`Bf zpa%3ZdXA^1zUhGaRuCxIShPjEkU5ZA0E_g z0|E6Z4=88lz817{AGfy-+fsKA1k`yRP(N^5>W4us1$$kF1@+^BfI8m;>Rt!bPl7<* z7ar6DM-IwakFEu+N5@^q!?x5f1_J8So|gKh(^3xwwG`|N8WPmNMxI_!k2s(n4FdI8 zXi(a(2GUX&cv|WS2h@{6pq>g3>Y0Iny3hm4S!JySt+K|=;X}Gldto4;KH~xP8>gjy z8`M(23k_;uG35pIdk55uL7-j=4N7}uAT4!~r=?zXK)n_O>h;i|2G&wuP=9bhy%7ZJ zkD)2elMzX&e^RKL-NpVh^Z) zIiTJR0`*>aQ11@})FmEJ&WczqXhkd@91*sqK0IPjx?;DKt_HLeo?#IZlx_?J)TQp0 z(jyM2oFGtUcu>)SfV#{B%30^B2d(qO6FWk-lscfdnJYY?oOPah&^k{%Jme^Xa@Kk3 zLF+v69Fvfs^x*?>-xoYBb&L~JBZ6XTWN1(Wd(3!2jdDPZ4gxhMG$?)CKw9c5PfLw= zKph(d3Qma$>Ar!rlo!2&k()ph}&VDhq0<*`YxV%za)^a~x1} zgFuys2Q{F_%r%~tn&*I;9|UT_Q3X}ufLa&?>ZH)1^hE=SscStgb&3Nj5d^9-JgCJ3 z0d<`RRJ8+YNf4-|;X&051l08&P|F=qD}q4P9#v4znmj#dO&*>f7Pg;SJCK(8KTk`o zb6Tn{sHN(UDya1is0~4&HiiZ@u+H;qo|f9=fZ7}cYRe#l`nm_yRtMC!AW+)}8Pp9P zP^UVel0l$$3^J&1dO)QdPz^z#;8?kkci+Hb>RTRAO%AAZ5UA!s26dwcREq;@XAr2& zAcOj@2h=VH)b1cqtw$A9n**vn2vo-)gZiGQr8*r@T|uC_2N~3D9#B0FsNNt@eS-|@ zb`PjM4ye6Bp!N+is5?BM_B)_X3j%feAcOjm2h;%v)EPmb4h}M?dpw{%;ea|b2-I2O zK@DiHpdWico$Y}7WDuxx!h;&ndh~lepw4wbeJTjld4mkA0rjOIP;k)epo03Pr=`B)fVw&e z6r3&_7Sw>;_pk@lwGOE3f%deE9YJpOl3 zK|SUH<*domgVyBXxx<4B>TwS!XHA|Sv?dRaJRVd~zw&_ko)hRd1qC{szC5U)p74OW z#R2vGAW*jsGN>m#pl)+O-5vz$jzI?Xln2zE4ye0=K;1papq}=Ca#kr0zkD zsb@T(?r~b`$3ZQ1?;wME)&uG%4ygNrK*2fXgW6Khc|bkjfcj|=sGkios9$?PJ?Mb? zc@U^y3^J(aJ)oR*o_f$aPdxv9P~G>U2h<}@OFbIYQjZNXsFysT9(O?fDhSjQgAD3r z52z;{P)`McdU}vSz2X7&j05V~AW+W@GN@NQpnmOudOir$3*kWx=xydT4=86vtRA!? zRv+vYv9EhTIV)oIpcS!t_!Y4O`^Di89#Ahk?t3N3eXkC(``++?dd&g#dJw2T3^J%c zdO*G5fcj$)s5b{0)SDhqe{w**6$I+fgAD3V9#DUAK>alc)Z5`f4d}J~Ee|MX?XVuS zc32O;c6eY1!2Q_+>K{%^{WGYg{uR2V^!Em`1mLe8Q2%y7y&nYXKcPVlte<+@1M0sH zsQ(3l`rxR7`p^btC;^}hb&x^*&D~Ol=77?JKpBG!>KzZLhyyC;(4bVqG%PqU_eD7T zuowLiPEm|;+l&N^Tq6&ztHux`UyP*}z*&lTnqtnhv3DBBd|RqL zf+U1C$QpRMrz%cf1STI$jxa{{GdcZEW2_vI%w)aaO1Q6?>+{9`L&o-tpP;0ceDXa|$Xv_}mHG4G>ftc{^-7LXaUK?n7LD_P zLOk z@(SY%B7U|37DN-HI^StrBR4ynq@4Q3jH^U5#|$h0n>l8D5h$#0%=i*ehKQvrdEo^H zsN{oiK8WRm0LIg`^1A(>97L$PebxAyJb=C_H`+gd?3!6l%`B>!9YC&nKpnni+}Q7C zoIYdxoyJXJ3&a}_ZwkCE?TE$O(!LqLZ5IqTp?yO_!8aSXfMZ_-Mfbz&cKK+@^Y8-Y zJB&LI752wK*xw_^-aqVlbO8jq0Wb{mjJx0lps>Hn4tw=xC+zQrnmJ*Q;eerk7yN@} z1+jeNZXOyxme%gRaJ9SNctF(dOvQr#6eZujsgKDy#=O(`g}i?2NY)8+j92mvz=Rtd z>jz*({SY$U)(D(#YlIK=<8nU*%H+NqZ}PyG)YSMXukA0TwS6R9Z6B2?|0u{BN-grUW8dY#-;k}hV?N;Nr55l9IM;QJrZ;0MNs{S8J`ZZKj@yEUSIG=q^yBu8S< zB7<=-XnjP3ERriRID`xi1%pFAqQPO2;Sz%*$lz!&IN~E391|HUF*u$K9uEe`e?)_Y zkqHumMP%>axVe9gZ0O~1`}_GY+)`_C!#>!8%t z%7p;v_b44H;k|K0g-jTJL`oy}J8RbT*xQU>hc}&_a3GV)*Ja&SWKO7VOSwU+TpmvO z8&c)@;gr8ARjvr9{4J^SN#T@llqxR@r~GZHaw44accjWy;gr8CRjv-F{5`4i(s0T* zNtJ8DDa*!;w?Wn6mnyFhr+kN0d1E-` zJEh8-!zte-Ro)s-`EIH5_HfESkSZs`DgRKaoC>G>BdKy@IOTh!%IR>*vUinRBQ4>S z@0FIE38(xMsq*e{%J)f?+rlZ|FIDacr~H6axhtIVPo>H|;go+SRqhL?{Ge2MZ#dFRQbAa%D+gW;6lmMZ@uobunK$`6H8{<~E9k#NfINR=N8r~D78@~^@v|5K{`WH{x2NtK@t zr~Ix|`Pp#F?@5(^9Zvb*Qso!IDZejO{%ttr|45a8A5QtdQstMzDgRHZ{7N|G52VVk zg;V}es{Dsg%Bmt&{$n_0RjT}_aLSrg`Oo2$b*b`S!zmk5<-dhfj!2c?38$PRRsLr< zWmBsBZa8I2s{HS8%2BEEf5Iupq{{ybryQ3me;7`g$&_={aLTz-Wj&m7o>Vy!PI-t_ z*$k(gFIA3)Q!bDy$HOTPl`7|kQywN&9uiJ@xKz0yoboYJe2CIOT~_<>GM4MN;LGaLSXU%4Ok{Crg#*gi}62s$3pUd5Tnd zemLc+Qss(p%G0FECxug&I>PI-n@IT22Irc}8qobriM#6HYlHRo)#= zxl*d!7EZZJs@xGyd9hTvE1Yt*RJkXd@)D_XUpVEZQsuqjl$S}B_lHxikt&}aPILW0DvE1a^BQSZ1++^Jmn7mYOa{UpQyi9I#;}MwryxipGBQSZn z+~n3HFnNXCQf@MJ1SYSNn`}G+lV6mZOdo;CFUd`|9D&I%%S~pE zz~ootCU+l!$*bii+m68GHFA?3M_}?=xyi00FnOKaWY7P%cO8IH6kT{Oxn!^8;6i9a zhY(6A>7>vhlt6$GdM^SZy*KGy5K$CS5E~*20)iwUct}UEAR;OjP!t6D5fQ|K%KyE+ z+}-T4cR4+T1or>UH_Mlu@4b2R=FRTj<<1Yu7u6-l`XRYWU2?o1k}s)CPV_@^wYubk zen`HoE;+>y$u;Vd)BKQpMO|`+ACj-COV08`a;>`L96u!2sY}lDL-I9s$%p)qT(2&< z&=1KC>XM86kld&)x!4cM*VQE-^Fwlzy5!@2NN!e_T;o#+@>!1f*+D^s!Oi&Lvp*iWAb$b;&pVkle2> zxx)|11L~4CKO_&TOTO)gXOI(kUXX?`Kce0AFE5A@I&&r zy5tvrNPeO&`IR4%pQ=lq@ZKO`@yOBVD)@+Wo4P(LIut4oIYA^EeqWD!3kuc%8F^F#8gx+M2Q z@)vcz&EtmcR0-|CVz{E)n%E*bUjB_*aV8RLhfPF*t256J*^$pk+n1JxxH{gBkFOD6jv z8Kf>*+YiZLb;-JZNJ{FG_5F}Es7p5VL(-@&+1L+Ble%ORKP1iSlFj^(3{jU%^Fz|2 zF4@u#$pY$XNACe{1CHwm!SyEl{em^8jsY^cKhh%AW z$-#a|mQj}+>W5@mb;;p=NS0HV9O;K-d3DLren?hOmmKSdWVpKIct0d7s!LAvLoz~L z@WxO>-^uxyd!&$z$&!|4^@b%C#?Xd_k6 z`K)}gb4~hy{M)cVbvxjeqa}QW2 z)y~PjS?;XbxwdbeyQp^d@ZEFnZg*AfT;Dg#-J}LN-(@3CRbwAI+rRWcYKTnhsp>%! zA4Jf(m#PQNeCRBA&|6g`?VpMCQ5EsKs|gxpTZLaw4Z9{ zwmx`(&iz$8d-xtdcgq7L`Z6&0b>Go9%L7$AclNFG1FCL!^{w+DRmpWQ1a!=nn z4^g$;+qcd`RXg|ft@AKdxBL0ldAMrl0lsw}q1t(%Z=FY~cJ}byhwkY)O11M4-z<+- z?L5r4&SO+NkMOPYSk=y>eCs?;wX=tBa&!;ac-7A1e6u`3wetkuI!{#XJju7tlT8hRQ`__4eYUc&M zb)G5FcQ3hbH;a7hJX_WBV&6K?ksejCyu`Q8^HeQA;alhV(oz-6%Y5i;ZK#)|r*7(; zEiLz{Gj1nVsB~WGLuXb3i@!Z}{50f{{B|(=L%)r5CdF zUsc--0{>*iBo>e=Nvk~F!IaDSQoTa@vmQ<2i}lE4 z1ets(OMm8;nY`%HB))o&Og1KytF!d~yJaS?dNheI=OdF<$mGje`YX50c$rLjAT2@f$TV^uCqe*-f zA(@OPlk2mBD&8`a)jgWTmlcx9L^8P{E2!G7F=^$}M(1`|POh-{%HJK*rY>8hH>gJI zgl{38fwQ+bw=m)CY@EH-{p_VUdz*9H5zgL@vv;_ky^`sqXLAN0Q2PiA(>=skr|XfM zr9IiwfvwV^$ZgUQ{2ay4$6!xnOJ8P5)gmLarIQFtnJ&7m(l^=CnK0?>o6`RR*)HkF zEUBjb*V)ofIPK?tfUCU$*Lv%FZDYhoMB5FhfaeIcxG(Lm9hA*@p6Ah6;95hKgBIoDcoWyZ4W9^-u7je+6q}rTt2- z{)x)|`kR~&x7Js7uI%cZoLlFL?wzZ+I@ivvbA)^6s;{fN}nc}kB z%xlj`YeS{Y+OD2yUVBz^w^_&4v!&Ob)vYy@HtV{2wsQ59qg3vuDAjO}alM@0SP^ZM zy>HIQn%1gH)Ae1Q+ve6e%H8hIhXfrg=Hl(j%##Ys{4H<9m zGGyYvY(s}^Lzi8Km~2CLWI$lHp;xw{uOoM&6)SZB>9wvQ>kX{o)HA2(IYymnG?)jgijKHhG*+=V?4lBvWYJMv5=0H$;3hiuX1O>;7EOrE zHcWEFXv)oJ$GaIvkWNydQjFXvdoYa~1rJQzWcOgkF2js$!<=lx0{v#gVn@VlS(_j} z*@nk=8J2=}6j}UpS+-$CnBke6=^dXXb(C{MHf82!+0?V#ESL)6A>K?SdNn2MTDV2l zeV$tc-2%LTsJklL@QN^kL~EMo5xf>=SnnD^XV(Y{@`AFZjl7^>$;z#wCHG(@{Ms*Od~Iv0=X^oNA8>`Bx62ggTsHL%=Ypvcyo9?cG1_%^)xGQ8vY1mIQ?(gogY5HWtk`az_zwU`>Q8IknqZB4<*Jr7+Mk_$epExuLa%i_Qh;fUR5?*gI5*IMsoN? z`ACy1o2}`Z)j^`!Xqb%^%r>@m^k|mmC?}_?arvUf7|&f-E#{Q!JmQbE{RxmO>IX_gq&Tg(86`$WFH634)Wg zcrBNcjzW>h6XjFe@I>L%B%WkH)qA06ZY_(caxWBAy-|Xad9tkBmM06!DLlol?ASew z?G54{muBtharTX!5Wy}&DAKIMJ)SJDM{!F?3uW^?ovqvxYV+E%=iPX1!Sg!2jw^ha zLg${)-8I$Y>=_0(d#X%y3u~WT98gSj3+qr%r#mLPF0U(l+MCxEJgvv;xjfZp8~cVC z?{oP$A!ilPG#UH5MYN^23n%wYwxzYNCkK@Qtx4P0)D0UhXac9P&M za;hP3C<_hZ4F#b_ypelOS<6`Q2*`O`l5QR3$@D zB_UgT-p_J;N6ee>CbHiT@+N}cO?gw7-`U2g4hLFWt05eY`#y4Dy4?XNHRH`>rJ1~$ zpwyh>zFxdMG|tX8!0VgpWE<cq_p`Yu;LP)fw0fH&;<(Ps(++4R0gM zEaq(lnGBwx^wYRREVG%`3{SDdeY&jMmbaC4pWtl;-As;WE{fS&BHj&UhO(JngoP!U z>1Dq)E|WcI$J@ysJk8q)9<=A}-8~2rbwk+}A3X?Vb3LA!<3b0H=S#TCSiw68E_CD_ z-CYo?4T5miqp)Fx(%Eeu&onLzGYZd3rskAFBzY&^N%rbl-bwJPGwPC3rZb;^72 z9)|Z6F`$?z)(!oqct^vrn!+z#ou(_=rCs_%MhM za`WN1?0vA{{a`*=?)fPnEc6`0hq(1zB4&6OU%l_*llMdUP}zqQe5l~VFg{ES{Fmf< z&Z8pZsa?izvW?$`8PB+`jArJtK!)?-vX$@oaKXw5KEiFJibC1l*O7MjX{00hNZE(; ze5ByRC_c)~hnpA3Xg*r*d4Z1>dXC{^+ zH!qO!e7xN45+5&go4_ZyyDlz}p1!)?(={S-b$_Td*kMet!NpDG4keSutaEs)vX7KrgT;Zo#2 zYjMxpg1y=s|4`O&MgM-*V2}Ncf5}_LG(Jrp(hWXM7}9h;T^UwWfZ$d?YYC6C2HFT6 zm-79r%{-oHERWsF@i2S_$Lm(9+e~^sL-1lIpDB1@GGv=VAa1|a%6ZWYjXvk4Q&Ry) zSu&heZVrl=^v^vev-m988!MkBcr%;h9>|%bsKP1>+z!wPi@iL~Vv_jU)tC(Wa4X_UL=%}1@vI`6OLfM6~e4*gN!~9{v1ygvo zsfyZmXA<6KF;|vb#23kO)%YSo?h*coAV(vriCfuHk=Z6Z#Wsmgu?Kp2crHA}Ud$KE zX5#r`!OWxlQM;L(r`V3=H_+{+c6fTydEpwYxNtSq5<)#V_Y8WBKPEep#2*tJS;CjN zjkmT!*2l6jSbj5(`bDm51|R2-%P!RAj|(n5!JiOZpc!nSERc$k4)Hot!S^B7k{*-F z;Jof$%9qM6HR4MJm!9NL3NBF=G*Q+kg-b)dEg!ojQ!~}1Z0_1(=5IE&LWZ@;dFErv z#8X<_qb}piWdGXpWrBZC@uy_}>{r&NP99Q3QDjDW4V-N3Y5ufqtP6iyFt(g8cMAsI zBjVgJMtLbR#=jINddVewky*i4$o6~k6@vX|_%m+y#UeAx+v}NIKoO8(}-aD@5t7Vsl@YRA#FY}k(TNvYo;I%*Gz8r zb&ic>q&)k=17y^ab$p#{{z1M@F#j5VO*WrXOQt$&Ns#C5WL6Q+9%{wPb>~ifd2VjeMhQeJ>H9S&3b`F>f# z#`g;n2lxS(1YS71=#-fwzH(`D${geeWtq46K|$sn{*GNHN%q*Z+bJ_wUFHx!B+KmO zhXk3!{IEE1(|)JSJZpKiLA}f0m1Pd{cLkaE_A#GWE`!JUaoOMreq1p43I9YKp{b2i zW}&*wr~Fe{<_rF*AoCgjOq9W#oZu(q^Sm7#lGV=fQ-a#p z{Og=yhMCU0$`oE6GS+eQ{Dyxc_q@Qr5qh5Hr*nFWi+QoQm<@ROp5BIOuT_jhL6G?$|DTFC zkBi=5;537qX}9=8xmzr?7V*4tuv=t@nXc#T7TH_Yav$!yweE@&+$ zTmF^*Dt8FwzX~0GC-n=O4-xj`R}sfBK&v3 z@E`mS(NjDSae8{4Uza-+*9gWr&?NAMd?>jn3v z=-584W3mV4$~kEZRtHumpI?=Z6g>jK1PBo`S9ea-v+kEWvTf)EqEDc#SCftudU`N= zyPjj=phpl`+_GYkMbnX@M=+RRR}ZK8=iHZ&!@PtJk}MWWM+z|m7=vBRk=ste=iPT6 zhoBLijIv-n9VrA&U`(Q*uy?-TE-0n4>bfoB12uvYYC#U&U zs-q9X*v>$2XfBV_%pqUIDGPrh8nT^!|5q6Z|w&_MkuDR4+Z| z7P|};onEhYd!(Li+D&y2F(?A>ipZX)(~-jSqF{-#{ z@UoW}55<~3Qpe?mW|fhzPPf{%@r){@!95yPlwiq zM-!b7AC<3l$=*f4g9zEX2kA)RT_rG;1n+JNX_nRC*}LK}-Bg@_EH8It;>+csEX&%! zqptkm#r}q4yb)Kr8q`m*#KCVMl^N zX%K6L>4-SNTfMlK^SsPFL**qqXA#(9Er3XfD=J#v*UYo*?{DaZzn>Nj?y#2g7&-Gi zIZ4bjRFY(eH%G-JF+b!=60E5iO5^kxOFhKO&2oqPu;frzLpZC+p>;L>KUN+(x_C?vv;Z`6c?Z-#35utNK$HHtWj%?587zKXe;VPYlojn5N5% z`uIhCxzjszr0CQDOau2pID>M)-3jwyx!Rict5@5DUS19{&%KcOR(K~WN zdstL-V-#jS;&@JhIl*;cE{+_|C6@BkHpcWdmZ$b89VwaYWTbE6B8xO?*v93KOltv{p6ot!Uy~r-=_$O|*eb8`;DeI#QU(0F$9+!dO@^ zVJz%4aa7erTgbGPO?*#B3KN-NGSy6&vGceB<+{uMNYz9;$h4D9oTnp&33^!3UeyF1 zY`9EhI!AF#)kFu#AjR?c?*bhuOwdD#j;bbxh$dXO^B=34=meQgvWbgyq%hGLOlMUS zt3(s4^okp@<6hqWA?(n{Ro&?VlU-zYF42*~ovvWIs<~sBBDiCiVl^xL`NZ3Mv0YaT zpQ!rN4K};U{#>Rbg+JZFbQk1##>gNUrO2r0}FSnBJl%f7?BguIZI`-zR+Y;Do9N zeIVM0JP2WQr0}3Gn7)DsA@uNEj)n93Q2y{e`rJKnNBi72hdx(2v?iz$wlKV5%yBv6 zoW+yww{k|j=zP;zr`*qyxAXhp@_q97g6K#wzJ6f(3F9+#P?7!GS{mDP&h4>$wL=$x z{n53*EK5)H`zvJWf!_c@HUvxICU3tHWu4DE??>1BWm$Tzf4@R@Aee!ItQntWaFgt5 zRoMs7^#NJdOh*dYL0|@nvcIdyeyb`w7+nX;vh)(bV1?`uFhfMyzg1+vQ7DQBrDf3JE2M-N>`%gROQNTECi%osQ2y(-G*RDB+c-eYCuVsxZX z9tUQeoAM(n%I8&;$D{XnS(($3LU{t132w@dt0@1Vsyq?BC(6nt=}4hG2@D?oi;v38 z>s6F5s472*-Ve&krRhkaJQ>VnyK>HrvWo2g#MhLZDK`aOr^vGOq<)G*b}E>uqU=*D zvKLil=|SN%S(YBpPgBTF2Q%F+ORpn3A4DtP^e0!x88~%@EJF{>XDDQ5f|;odr}D|; zPu7~AZ(QgPta2{x)nXNPuBLCHk>y6{GqjPZH99e@Nh|W=H%mp)7 zsiAcAvX{3shR`3y)Dd^D%UE1lWSm%S8uN-SgoP75kl7QqkM0kV5Wv>3K>R{}7eRJND!$EeufDdvg}#+!(=XI7*RMo- zQh!PRvt$d33rY=YhBhncK+qw{7F;ekCO97Lgy4sQA4YpR_)73K$tI;pEv43IUy`!$ zQN%VwK|?u1INCLaZTO61o3W5F+*k?ibmL>jC(v#+zGHkB?K$J`#y=&SX@%)E(?-c= zZf5Rm?uK@hd6s#uWDC)S6bdPVc0$NQA+Q&6$-*pwlFc%}GTt%??N^o`Ete%*f%XOZ z7Z`~4-2z`0I3?K%jwm>z;B2%j3cgklx&?o+23w7i&AQRL%eq&xg?0%Y6gpJ06=H=# z3l&D2R;X*C9+E9AD6D80M{5iFAnd4QD=ZZ*UbrOM!G$Lmo`yE7@PWdJLy@9IDi?`F z+oQ;^A|uge6**7@e9^?B&5O1~yS?bUML&>i#WITZDb^3|E5+U{_LgKT9$CD0@p@?2 z7vEWYw`Aj;`2&0i+AsM<{*z=YQM5$m63{KNyu`W^8_*stak|7A$yTyM$pIxFK)bl) z^CeeFwo+lGDwe8@c4Daor52(6t8{_Vp^~k1V(I3kVZZc_((jc%g7)V!fn|avTbXfX z=9O81_VqHm%j}bEW#h{>DcfAKm6OU9FNg7!TU74ZaxX}>@+HexFCT^W+4399Z$|rP z1xp31WUDZ_!lDX~qP-Dr4G)uS;jP1ah4)396@DNbv<|+jwTa`&w z7FKygvQ@QIEmO5T+S*mqtF}SAyXr?(p&QvCvTbC0wCf{xMk0RIYE-LNts&ak)s|L! zO0rcq;3M2hp>0~dQ}wQB4^;oO`sb3Z#?Bf?YJ4QwYBsEyS+j#=iz*paJqqKDY8=%* zsuS9WqLxP?@1r(F?TOlt_G)xcH2jXP9i1Kx`_VI_ACG<#?V;$;qrXCXIVK<`NV3Jm z$25sS9Amo242>Cqc6Cg4%$t%ewrFhSSj=N=kJw?c$dA}Lu}{W6jrN1sQ?aMfUW=3B zOp+}wHLgQkXS7q}7RN0?yFc!exD%2sJ}ACuJn}F;I=*3iD%$b!^Wzty-5Gx*9^*(z zOX!+_d`%dcFf(Be+ARtD6W&4lWx~aTpCntYh+4I3C8O;77U&>pGvb**nDTOvyg zO+>yYPEA~#2z!ZtCRviKk}WARseV!;w3Ct+CxK6TEopZW@+9f^ zr*54FXy?>fUI%fmbGpv2b^efSbz9W!RTsK-U#q*jF6`CoQ*T_oiD+-sFI>NvWNT2Y zLG=dEZ&;vVctg~WMiU!7(&#a?A2vGE=$vG0T%&QL#!b-9Yy3>(=OkNdsnnR%c(fB! zA4$b|O)O0+G>JevsL8Y@GtpjeYHf=AZMv}O^G&gin(k_Pyy<6>t@(=PuQz`~vZXzj zwk2&V+G{P$Es&2by0jS90`u46trkaHd@R{omTei|G7;^}mdjc$M|-B_A1(iqZ0XI@ zd!+Y9yDoiKI_gWS0$>Z+><$mX6 z5BjnY4=SRPw{t|bHmrabHBm9Q^X&10kK<)G`!H)R!lJk@=PKPU}(`f7@U5qCYG3FTD^w z@khg%c<;*VrzR`oheM)M{^}TIKd`XjSVhV3uw;23|LJ5etFUr@dMSE(E3~|MyOveB z1>TAt-zq)(#&J$!iE@m`OO_*&<)|FuRjlGIa$0o!R%%L;AxUB>gzy=j=WGELSfyL& zx#<0^)-|b(V7!jJr;CBPtjaAOh&Y)4LR*skMLtz?$ZGzFBNIpWU)%9K!s!2agyJY~hb_+|jlB&c6-Rr!?0Ft>{B0VsIO^MJ z)6>YGVYP1K$i>m$Zo8g0eq0a8H`L_a?fRjcce;tb6Si}?fM|=WquU=4F*WX#eaBr5 zUD)DEY7?t-hXNr6<4*cukjIZJvzxE1J)=H1WOE9Uh&7RF1^80^GKk?VC5yBykyx%)-(?VPYhsQ^DCIj8LKH2 zHSCEES@S#=J~4!O(YHWH7!kd0tVJG-o*2Qr>YpJse)8EZ;FDO#d=zjo==sfWx4$kGWX*A z-%DfmmIIFUKkgpN0WlBmwQ+mP1;_pOgnKL(#C*6H$L=jB9Q9$+J(v?>UfiqW_m&%u z>xaqrXl{u4aWBWfTaGyD$JBc`N5nk2*W=(VSM2rVFq?jl=ZcswS}cCd`S2%?ufLC% zU&funW@>38|KYLYkAk&$*#8haM9vHK^g+q7fA-KEHd{*{=ijY6Qb>!5>u>qJr4g=j z>{VzIo2#XfGmXTJOpA*vl_)N`UkG(z^R--3E~1Wi7BYX%(oPz znB{&|vVc9Q<)F_wDCVISH{bKnw_IGtp3-vhALXJWAMIDo{n&CXe*ZXrju_IFv=+aA zwx%g|_O*@A%k%J;#`f13#TFh%LzPCQFz2>&_j}*qS*Rp_eC?OhMPt%*x)yS657`nI&T1 zLRf$#dHg&nyrc9e+o`RQJGMp~>%{(APFc1~n~OU-7moR$*L$?NxN~)j=7D|!B-1AO zjqi2Y9&Ksd@ulHd9*%OgPn(lGF(;0Bp|YjT$(=7-HN-x{TB2Deqjy(Y(0-IPXkT z*oWGZx+y&F;kwiRrca4?+_iqB%~zhEFUl9kC;Myjb#wW-)9XpizOy7YU>|EsEMF`! z$1<~*#)0e;ZQkfw%K0nHKG)_i-_4(64(X0fo4@>VnL=|W{s@;X zUusKG5gIW}dHq)z|mT#J8dl}EUsY+o#YfJmCU)ql4?I`D0wK=~h=G-ywRMxdQ zzx&JjP364-yQVGmduFLSmb<;oS7EpBCh$?y_jW|?_3_i+?X{He9U^oAT0Y#x2VDiNI{6h%e`ext>g#x?hL%tM ztTFW&p*Z#v?Q|4PMU96UGTE6|q`KHXd`MP*5=d_%= z4LPUGy9`||E$_6vyG?ng%)NQKBrW%}+`Emrr_8?$U5b`}TK?VU{8Q%OY+W5K2ell$ z139S7!&$m|S{`b7c!%;(nTu6)4YXX;a`6u4q9Y&a53RIZ)LzJ?e7KW8j?YHWeV|L# zO5+`!iaVJGdB(P(qC5wVcOz>#d1uQ*p2>?lStfIGQZGs8By$7FVE?n$Uv*8jf~ghE zJDHed8}F{ie>q-I*>t>%rn#1#T6X5C?4&GpWoSoT3oS#n49#;H>Ykb#k+7mc{upiz=h^w5-*#HeY0|d*+VQ zGFQvoe3QBE**ihYUM+j`Rrb1P@FXpRwG7U88SI|LleH|?vN&I6u`-ie=%#9!tYvb( z&17XZM`~{ryhSrfalO}n@J7M1y6IYZyyp|)RxJd--Y4j_v$71P=w@nJt7YviD&bxe z&#zxP)|KOfwzaI)HeE+f_}luGm|iH;d9&VJ3Yo7OkJlV)UP}*q|CLE@(1~4_eDiK^s}EV2PQ6OR&V?LukKbNzy`Q zlAdMB(lur>7+H$p5wtI`+J@hm$r!@w82h0e&+3{=Fq5eUt8Y4p_Bd-`wlR}=4{I1w ziJ3x@S)-7ZXkTZIErprMQkkV%plf-SH7O9lOa+RtrUfRVeV8>X@DtjIS*SWQ6{^qD!w}D~`m9yh1lBt2ch;ux8kSKclbMQiVwuGf znWgAG~x&| zMSR7ENBqb}R;tEERldkZSJksIk>PA)WC|M}Ii5|Zp3ElJ=*q^|7|BdE#<9sY=Cdg^ zN3p3j-(sekN7#%gJu^iWVl$(rv)NG>*qrECHaB`An-{%{&5xqBzWPTy6G9+Dm?{1*wlpD@nGzbXCll7O zWwlDNr)wQx%M+0oiDTJ{M9fFx>uhD>8MIf}vq{6*b4fq4=acKR7m^=kFQyb^t5P0e zt81sSmuo-8*3>D-Uad2Qt*!GpTUR%cZK&6rZLD{UZLW8cZK-#aWi<$4*$o5P)`m0L zmWIpOjz%Myt*xZP^Dcwy+~Di?I(|PGUz}e#JgYZ@`YFuVNp! z3TDS!EoGmyj$og*9>+dw!`O*7Guh`EMcK)WI_y+NU-oszo9vsmR(87W{p{PeJK1-c zMcA3l;p}YYA@+T{aCWZU6n4Jdr|gIJG3-M7h3tRrPqT|1lG&vWQ`k=(E3wNR|6-Rq z6=7F89Y?-?%UHqgx`*_wSa3*_kftm^pTbIoG-DY|r(ekoA;kTh_C`k%qI z02i$Pl9dl>2`(t88Mt(ChM*X5t-wh^hrqQ4X9{`)TpMu4;COHu;6j4SfNKlR9Q-i2 zOmGE)$AN1H&JuhLTzhcV;IF}T09R0I4Xz`&LQ)dAPT)eNZQweCD=fVTt_!#@LpZpu z;EEb7;JSe;V%Pz$JGkP8)!=%7D`u<&t|zz>Mk}~p;JEP#aJ|8mGEN282V6UDWlbBw4FFfc^fb8p!Id|612+&{MROBy4}c3d&jmLK zTqW}eaD%}`gcJcc1Y8yK4RAxjRSu!J3hLoR|F39g!D61Y*| zYFhe%8x5|8Svr zu2#We;2s2*P>{wp8C+698ru|biB==Hso+uyUI8}^T(Wg9xar{PSl5G_0j_rFP;fKB z)eG$eZWg$@g$je44X#1x-{9tet6!)GxVhjO6>0`<9=L{K9Nc_xsbPWO9s<`m>?pVe z;F^Z*0JjialfoszJq)gS;UI8}z%?s84csH(S`>Z&++uKPg()W=1(#l!a`G{7EsI2g zTLP|ik;32}2iK~|NN`Vp%P7(f+){9DicsGt!DSYqzRSS1E!q;?Q{dVcO#t^axOPQ9 z0Jj`m$D-T7tpL}dSU+&jfa_eWHMo`FIu&~h+_T`i7JC`obKtrZuLtgVaNUbn0rvv9 zZpC+ldl6jE;_JYz0@s5N0rwKP-n=8Y)!=&ZpTNBgt}p)_+!}CwO3>I|0oShtjqO!% z_m$WHZY{V0C7uGe4qX2dXTZG%ZeWQc;MRk?zvKhpHh>#cvK_dM;2tQs3f$}9hLl_c zZWFk{r7DBl3~pGdP;hU68(L}+xGmsDlo}5%3*7M1q2RK?jVg5=+*WWSOH=%|fg4kr z;`b)F(WQ@o+YWAA={Ldc05`TwFu1qCO(^{nI2*X}Wfp+j32suEG2q??H?hn{+$Z3cRICH;Q*e(} zJPz(Na8Fcx8{7$Sk4Mlt{~X+t5wy;~0JpS~0o<41o{IPx+*jb1RT>NKB)H|3dVxCy z?&(UufcqNUGnGz(`v%;K%IV-vgL}4eEpXq0TUq%-aNmJ@zVdc(XTUvIr2x3I;9ji! z8@TVmy-?*5aOc3iRAmCV^WauhEf4Moa4%OigS!B3b=5ZD{s-=rs>$Fkf?HFS#`Yt) zwN+_sm%zOm*&f_a;9iTY2ktVsb&<3_eg?N8lGeu+aO(#1(`vu&_YEOZ? z25xh;nc#i}x2bw5aKC}uQau>l@8I63-WA**;IgZyg1ZhbtNQ2Q{sgzJ`aW=ff!kW+ zBXEC%+g{@>a5uocS+fJfrUUM+n)O+Eiw@k5DCCeO0Nl#8T%f%^5DLRGl8oB?quv$aN*#- zit7xnBDk;P8i9)dcPefPxJuwo$4v%T8QeEzj(~KB?jDu1ngUuSa3fk zVBfODfxDP62V6Y3pAv?HO8|E%;T>?b!2O)C8C)W`%LzY$O9FQ_;d5}w;I7n42A2Zv zTCH$!wZZ*TYY@0P;C`#s9$Z~;zt;K|Ts?4q)OsIWeQ>`gVqdj10QYAt?5mcB;I1c9 zTpEGo;Oxg#o1-Rg(SHQId7nB?dE*+d9=@)RVz)8t{!L)ZM;0h!k0@n_lB_#@6dvMm2FmN5f6-?;|t|PcYDb2xk0vDRH0bFNrg;SP* z>jEyU_CRo5!4<8Y4z3%xBDME}>kh7X?N`C|09UL|18_aTm8eq@TrY6E&Ps5-!Ii2r z16&_)CF}eFt}nPUbxwl24_xWGG`4==%GIT@^#@nBF2!X4xC(VCF86~gUvDC~f#53E z>jCZoaN+fffg1#_QoZZo27`-eK;s<(u1W(M?@(}+8&(203|wSG6S(2vsy2EI+z4>h z8;u1w5?r-L=fI5uSF_Q3;6{V1(YOh?G2o&bR|Pi~TvX%dz>NbJ+jthZ@!(=onPonG7zei4oisaEVQ3f}091rO5zr)4(M+4FfkF zT%9Jrf|~)ZcGFehW`e8NbRM`_;OaL04BTvR4Vu0MZVtHm&EEhw7hG!dW#Hz4Yn-+f z+c7{(Y!4O*SQtV+X`@FE<_}nV zUBk4;gQuH6!cn6PnxmI-UcU^Qqcu41zKj##UI8~C!v^kEaQ)jxgIf!3VB5mr)`7df z?L2U=fg99zFu3*L9%y?K+y-z%+U^0j5!~R+1aPl|8bZ2>nb^L=nx;6}D<3@#hon0A%HZ3Q>F9j(D_;KsG1HTWjDvF&~Zw;kMsc3*(o z0d9Qzw&30ZH>rIBI2*W$?bm_Z32t)x#o*os_h5$raJ#@wZGRTrZg5jNbOE;q-1H80 z!R-Y%t;6%+_JNz(VK%t^;AV6T0(Su1><;I_9RxS4V;Z=3z|HMg1Kc5Sb2?EB4uhND ziDK|BxOt3qx~{kA3ovFiSw6NLXFAK*cy<=Xbof7GQsj2aNyc8sA!EUoGr;BeWdUYo zq0ES*B6!GVWW~{Pv?bA&LR&^YKNOGJDzI?;CV~aCN)W7qwkq0cXse^Gi8cyt4BA+< z@n{p!CZbJ3n}W7B+PY}#p>2S+A=<`hQ_1Hndu*8#dlbhL?%Qt4?MPMV?N$@toE`r?zdkFRt>?7DuaDd<-!8-(p2o4jxOYk1S`ve~l93l9S;3&aI z1jh(ICRm`a&)9J~`h?(9g3ky}5PVMX1;LjDUlE)nI7RR^!8ZV1LxKkM&(j3o5`0H+ zhTts0_XPhVI7e`v;0J;W1Q!W@B)CNI6TxMIp9!uITqXF0;2OcN1iumdPVfi8b%H+$ z{v!CB;08d)2y_Gi1c3y4f*^um0*SytU?eaRm*lg3<(K2+9(aBPdT$fgqfqB0&T}C4$NXRS2pQL=sdZs7_FWpe8{S zK{P;L4^yj)p?}5_#1X_3BoNdhNF+!iNCvRBbd*9+pP)8D9fG<9^#E)UK%b;fW^A?; z!}O)}rJ25}K9cD(^mz2wUf+S~o6u1@!7Tl3#`;PPm_Ak?$5==7U>yiX5ws)dO3;&F zBEfKi{sdzPdZRDvM@JI~MiX=+t`|Wcf+@s3D79y78XZj~m`wkiPDh;x#u9WP7)LM@ zkM!AmX(?lKq(_;)px(+@8>u?M3KkR<6wQKSgW_25OoCYivkB%9%q5rykjfKOAP6U@ zNDx6#iJ&q;6+rNOf`#OF609S5jbJ^& z27-+QuM=z{*i7&S!4`rnf^34V1ltJSB-l={gWxR!8$c>eP>TM!li+QFT?D%c_7LnP zc!yvg!G3}R1P2KY5gaCXm*72u_X$2AI709t!BK*b2#yhaOmLjw6M|0(J|j3m@HxR3 z1YZ(-MR1bf6v5X7-w>Q8_?F;1f-?kX3BD&dM{u6t2Z9R(|0B3a@FT$`f}aR36Z}kY zh2Sc|F9g>JekJ&g;CF&Q2(AASg&+B?u)bL=Z+$n4kzjQG${L#R!TMaDoy5y`(n)q^B60M=P&0!3=^{QdP$8 zqoeTzlL&?pj3gLAFq9VYAcDd8r>>Q*HPfvC1iV48jlf2*hu|Q=djv-aJ|;Lpa1x+< zmX5w5I7@Jz;75Wh1iumd1qcivkO)Emx)OLUhBt`bm8b-xn)K|o0pzz6~ff(eWSls*9k2`F=PGz$Sm2#OPwCMZV`PEd)U zDnWIED1umkZZRDt5F`=QCa6cykRX+y89@tzHUyaf-4Z(LK+u_>8$nNkJ_P*;?k5;T zFqB{fK(~~RMiY!9m`E_0U>dd zD5U}@rSui_;Y>e(E*DPgzt!o_>QCwPKj|;)^jC2d6ciM!3o_DCNRUMrWTm69pu)PK zVsunKsDdsi0!RA2`h84KSH60>)D5ZKvI!ce6l>ZCzRE|Z3SfQ=C%QnKe!?Cl9T;;EP(tD9#^m` i$;r=oEWxZ8#_yBsczs#FGpI9sn|y({0x0Uqw;KQth$OQB delta 99 zcmZpXYmwVKvI!ce6l>ZCzRE|Z3SfQ=C%QnKe!?Cl9T;;EP(tD9#^m` i$;r=oEWxZ8#&47Bczs#FF{m?qoqU0}0x0Uqw;KQrJtU?8 diff --git a/target/scala-2.12/classes/exu/exu_main$delayedInit$body.class b/target/scala-2.12/classes/exu/exu_main$delayedInit$body.class index db1df38f1690de382760f8081b6b91a77a14ec95..644a1c9324b1a49b410d1df9805354397c52a6c2 100644 GIT binary patch delta 19 Zcmcb`dW&^~EfeFn$#zTuK(e378vsiS2QB~r delta 19 Zcmcb`dW&^~EfeF{$#zTuK(e378vsiC2P^;p diff --git a/target/scala-2.12/classes/include/aln_dec.class b/target/scala-2.12/classes/include/aln_dec.class index 48dde97aea5f2cfd4c8597ef9b1c5912319865da..277d3bc4870ce2d12e985e0cedb98bf8557c07f4 100644 GIT binary patch delta 27 icmcb~bCYL7Ju4&YPG$x!MpgzrM&`-yS+f9ZYX-sq delta 27 icmcb~bCYL7Ju4&IP8J3(Mm7dLMwZF%S+f9ZnFhuH diff --git a/target/scala-2.12/classes/include/aln_ib.class b/target/scala-2.12/classes/include/aln_ib.class index 5320faabc98be93863a235ccb3cc8eb1768e956d..12365dcf784840a53db9d5e8998d55d46dc6f7ed 100644 GIT binary patch delta 3992 zcmX}vc~DhV90%}w)ftz}1$aDh%q15DwL~-5BuaBD6&H}52ZrDdsEC4~;*tRh2MZKY zTo5z`MZr>35F`*oavGO3quge4S4wf~p8M|i`_DU{bH3km-wz%$Zz#@hTAbgsz}-V_ z5aBb-qOGT`i1Fxc>`r(L=lKXt?X*U)=XhO1#BEO}U4eSXU3+y1>LhN=kf-ulUA=I- ztCy`<>xHMv-4!qEU9;%uZGE0u#CVT0ZeI7sySeyG(9U9gqO@1}?yY^Td$U;J8=#%l z`lcIq;{04So$^cI-d4=_ch+{XK4wwi?`5c4fWIcUM3dMY&|g!nuUT9Vh&Rq60|#iz z3EX4sEfz;ZSr*J6=Vv1x={tv@QMeZ*e^&QklPIT5!Pc|MMpA6-?L_mL^5=68wi7d` zJgSkJ@HKjw)O~7Xi2NPaCp(ChA#S>y#JvzX<>N4uaGoV6mzqWGrs}EAq3HQg>C|tO zO&EHUs6?vDkepY(=jXH0j;BhfMr!aJ^cGQvs0UP^x#)#bd#JytF7wdyr80Dt&ckfB z^U;}1B~jH>^9AUQqE=ETsh8A{g}AYpI!ryJ`i7$yrYj{Jv;EDaYXmxe)E4RzWfzH_ zJC#hGqgpINZ#1=vIz_#rhAx&jEQ>K)p}v=&?jx$-5p%SQ4>J2qK4mXxkN2w>&hwh-)|H)r*`6}#zXqLo)IRDC)nhGs7AlMSo$9a-z3Egc zRZF#AkKQ<4;p;Km86>ISpz;Z|j4Gy{>5^YNE*sMqsuTl9jc?bJ2OA<^2C zqsgZVV{Z}{sCSd_tnt)3s+>}j(HluE*Y!BeP826wzi_5#?^K`cEc`dhFB_>tRI^Pu z^Q87suc^r?=Yup9!R!sk^$`r(w3_G<52zk2d3M9d(uJ_Z`xB>LS(a zd!*4+4b>$bX#`b4b;yvZTLxx3sqf|Qt^F3596oGPcxdyvkiN~m@@NQ0>&s^wm!zEnQdBp2y)DpyxsE@qpUhfX&2j2g2K=@#lf z_33`3g1Su&{Q+qrb%Ppk0O=a)vM%)?W?OL(ojR&VKF*@3YU;fLqzkDtl>H&3Vblq# z?O~)r)KRKMp-f#0G220XFaO@uBe*w>+N;ZQ%vm&2UmcY_dA5UkN_|m;G=sWFxfUZ$ zrEXC}j#*PVn|%Hs#@<=D{D^xA)FsOKC#12|1*-dTq)VtOs?!Oi3#c;6RDv{AS4s(H zYjYBbg*rktKZVqrIsm1fMmUwqp^@ z3T@5T)+Uv`#6M@v!nM*-I91w<7;O!yv=v2_q1s1US8XQ-{w)9dlggnSs;p-wkyPcU zr>4|u10vE;gf$Re=aAG;t~EG2Y{<5-`}sU|P=jKl{Hyd){!=C@&y`uq3ngA@R1PRF im5a(NZTDKWQQoK@D{obARZ$~VRZUPD3f0=87XJe#!B7kU delta 3689 zcmX|@c~q2D7>B{`xz0Z5Uxx?YiP+Himw6Ix`kFVM& zqNZC!J3o_H<=Y#p6TZWFe}rc3wTVc-PYfF(Zuz+z7G})&h~`x$(I=v{xISIq*PqtS zpU!vlH;EK~dak~@>@QDSMCSncM2lDz;Ej{l0_gQT0>^86@qsbgPyO}V1j)5UEDj3Q z_UeK%a3&$xQ?paSNxU|RMIlyg6(493MIrvM?x7*tUCkmr)I-~;3$lo7p^3&$bl5;` zCpT=Lu?h?CZE#08y`O|&XYs(;)!*p=c_u=?sZXR?R7U9URyT8`v`JW(V(lVY%#hPA zVmezsTNB&(nKYNhc9(6`Ed53ewoYQrEHA^{#hqFDZC!@r98KrjRR z1$3S(`$TXPSPi~5Pxg<%M6e8O0te5RbIZU(;61R<0@>$)`@lcJt_x)k0yDv1LDM4H zCxNM84cKC_>>q<`z?0xJaL5ulw;VhS-Us_e$vzj%1^)uOMav!xZUZlZE=y(i0d3$p zu;nt@M}up@Q{Z!O=yEx?0xSj}fc;j;J`dav-T=GD$Q}Z22QPuOAmE9Xm0V^c!Hkn6)abT%Uev(c$ zK1Hn}WV8Mq)nK!VLu}2r(4HS#0ox07^)=O4wpzBX8C0X$s@OVa>eVZg?sn2x>%X@S+vwa3 zwoc;trbI!}c%RxNN;fWz*g68EgG+UOVYrI@@iwVY{fN zvi-p}a5vQyw##gN_fSn>`#~mWgpdfY-McibE!tMm9Vwi zPc?|Gkj*KN>NK`I!|LPVtd3kri5xH+Z{H~QmS^gn`}dl$*SK?fBx@S zTZPAWbS{bQBAfMls_|?;vGq7kbp=~B+Z!jSE@mrdGnY}FV^~@l-L36OD&cHL*jk*T z8o+jd%zm2U6t-Npr)-~|p}C!G57|bSQ_V2!OgUX`R0WkZwi|4NE2(ZYtik3keyi*) zytIGEJ6E}h)f)XY9@m(z@rlNIjf2j*ineFnM6|~78VfaU(0E5`Sgk8*`9DG|X&L|k diff --git a/target/scala-2.12/classes/include/alu_pkt_t.class b/target/scala-2.12/classes/include/alu_pkt_t.class index 7a335c649aba78278a4857ae54e6efa523cf0db2..56bf1e9a74f0db14c9cf494b0ca4c533363f49ba 100644 GIT binary patch delta 549 zcmWN^J4lsb9LMqJ|9dpc?7Z)LF3&ly=BZT9Lyld}&~VCzhAs{*r9nf6ZC;@vQlTNT z#(xDPt<3;Mj5A9X*+#F@6m7c zJ#BDatDVz}^dx;iN9Z!0r$N?hg`TCwtkY3CNSEjowK=bA^aO3qIUSp59c1ROyq==nz8oT5&YGnYsYM9D8IE33-D+J|mP>M6!(}OQC=?jv<3~I9x#% w*Ne#EE@C`FJ*LrsCG5o)G-4fj3+%HF`)w-@*b-9c(=up~N@$3( z@mDH=QPdP=VpAD`Le`o^Lr~NbDAt&smi3)JeCA8@rI|Bq2m+1*w z2)&NcKKhp44-0CetbXC!Bd4{I*Q@jtoujwuI(<(MC7mXcUWaKXeMWE4Rr-eRPdP=( zYd<|qAJWV88+}3R(@uZWZh9c?b%LI!AL&yXWt^_iF6uL0Z_#t~9eqG6oYSxLD6Ml| zN9k$$ir%4Rx4n%!vqoX&`E)#GN6V&0HcVbNO{@Gd$KhT$Q{6d2T8m+?~+kz%r!d`n4`)og&?TD0T^X>88fH!^TBZeoyU+{|FixP`%;aVtYK<2HtT#_bF(j5`=+Fz#en L!?U^s!k;5 diff --git a/target/scala-2.12/classes/include/br_tlu_pkt_t.class b/target/scala-2.12/classes/include/br_tlu_pkt_t.class index 689d19c27c740804b6ccb9f934d75f9a97e496d2..77a6c9f820816585ad201bf1d83fe2f36d6d0b48 100644 GIT binary patch delta 79 zcmdlZut#767aQZg$^Y3zCo8b2Pv&A1n;Z+I-GTHhAl(9_uLJ3WKw5--qU2r%F2;Qf ca*X>Kj2I6vxG^4Nh+;g%kjJ=p@;>%D0K!KX+W-In delta 75 zcmdlZut#767u#faHnGVHZ0eI+fOIU7J_w{|0qK80`Z}9B diff --git a/target/scala-2.12/classes/include/cache_debug_pkt_t.class b/target/scala-2.12/classes/include/cache_debug_pkt_t.class index ad66107f9e7c854f8efe6d2878015c2930e16670..ba0c369fbf14094376b81887a37e8a8102bca385 100644 GIT binary patch delta 67 zcmbOvFiBv81smg!$sgE6C;PFfPqttao7@egOM&zWAiW7lv$EHVerMof`oSR2^pnAa T=@)|s({F|trtgzyvR48C59OHnGWmZ0eIY0qJfa{T@i4U{h!OGx-DC6wx0HTueV1AG5X1Ci@=W$h0Iu#8_W%F@ diff --git a/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class b/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class index 3fd12c6355c7fdf45cd64b9be1f86e33ec65836d..833089127f07cd1689b941aab2c907b63c9a5a99 100644 GIT binary patch delta 127 zcmca9a#Li(em2IvlRvVHPQJ>fK6yWz*kmDg^~ryLv_FuxWEY#<1EkA<^hqGS8A!8n zs89X?q@97ZE{E9U1|XdUr1x?>)ZD|s#k7|}j%go*5z~GKH>Lv&QA`IJ@|X@WG%+1! Vn8tL3VHML+hJ8$XCLiaV1OTw8DZ~H( delta 127 zcmca9a#Li(ezwVf*u*AZWmBJQ$u2foh+Tbh8Ibk|(wl*F50L%;sln|zslx2P2Z7o#5`V5fX2BbMT z)F*!i(r!T7fJ1C@Gmy>&(g!#mYMx-=Vmiqn$8?Ipi0L$g8`BwvD5kRvc}(XRnwZWr VOk=vhu!`v-!#<`HlTUF@0sw$wDbxS} delta 127 zcmca3az|vtA-2i?*~BK_U{jxL!!9;ilwEytC6EpR(%XP^Kalo}OFHJV&5S@I0&k4024T8H||DFt{d<>iwvunE-~z5Iyw0i=Oh4v94XQO diff --git a/target/scala-2.12/classes/include/dctl_busbuff.class b/target/scala-2.12/classes/include/dctl_busbuff.class index c778c5217c3dfa21b3d16846cca56f6f43a5ba80..8e63c91c212bc33c35084be66b64fbaebbf23081 100644 GIT binary patch delta 3886 zcmYkTcMUl!$O z(}GC<#*3rT}vM15$Gp`l^ny5hneL}}PST|bBAs{J^9tqLzT zviJyRL*)^87xyBp@6$^rQzz+bom%Z8rK8k(SgjqW$&&!Jma6rsTD_;s^G#~KqgIb7 z`EFayJw;BGr;@999wmRGXS9Rxm?5W-T0$M69#Mm4qBoD)L*1g@o`v2tY8!Ql>KSeA z$-fEt(}l5j5N9dd*?28)Y8BN$*~FkXl1ikGQh!r}KgW$&YA^MNQujHSZTcLvw^Ns? zUUQKKP&rg9)ny)f7n*t5oj<^n#R9 z6ENEkOuBu6jt`YVHBv8qiJm8wOdY45P{Wqs#sca9b%%0Ils(@>%(heQ<$uMmRG%cg zRxp)I{YZ6Rirz$OEoGrPB%}8swTwDJJymjAhS?S_!@V-C1jYZT!CHV=|M)l8-J$W`;$($i)llvP?USEq& z7*#-BpzJfz^QG1svKP&n*3W1+(RZEolg&-UQ4N%7J<=Gen(DRz>2#`+dN~VeD0P5p zXGZEzl^U9?zw1`Bo0yo5P9gP(8YhqzPOwROihy9kdyHI0s&_HcSgMY4*o8D&$-E1*btyp-Ngbj(l_CwM_CeXZ5q?JPqMlL{zD92w^?(|) z2Wg&C?H-IaaxW4yb(0#t4`~K2m5P%Jl%!Bba6rrJI<1SoWlfsV9cyY%>j=(rsoRvt zQKVVa4eH%0q-&^4)H}zJrcvi9m*X<^J&xI0)Lu^MbOQI{sYa?-HPX3M4P|!{=}fAM zdi5Km5!6AdLk-eErPLbC_8$}9T6Bu2$CP&+(k)7@W>?Wx=ORW&JBk7I&camhC}Q-d zpZ+Y-pJx4eQ-8MTPp1ZF@k)cE2-lwLk+Q5&lVV+o=xav8nUbSx5?JVsZr~pSu}U8N%Pg3wHWP;mZg2G?bg22 R>a-T^meyF|er8MO{{ghqdddI* delta 3596 zcmYk9c~q2D7>7S3mlo6jdrsU9G3Jd| zJQwOLMuyUiu`7IP=PzHyEPTS$tD42Cu#fQMtuU%1!bj<6dEv7$?G~Z-W|0*UtDjwt zD8MtfV@;ws(nsH&iCp~DS!R^CzRL?Yi^iyMSpVo4{k|@uG}>1``7t_Q?y_V0>AUKf z61kfm>nT|oOYi4)EWJxVH6LgE#v0-R_0<$_tO;^GAlFV4jFV8g?v(2zxdu!$&Ns;Q zx?KGejCb2+?J3qI44395o+KDQ-BtKc@{pVZ9s=)!zKN=*fV;t~;A@jrp8#$F&x1Xa zR1X0Kcp7w?qIv+h6tsa3$*K0mkdC+Im#^-171@DkX2w(8;FI`BKN`{$~U0hfbK z;4@#SJ{+76)_@Pe0dv&cG_V4^4tiy%o(OISe+K)^RXqaC2fqhjoTvI&a0O@wJI+`A zU2p+d3qAq|E>LsR!AkH3XvtK4GFS}$0`^^~dL&o?o&|ekss1sT3pRtD7ODOom`^%3Ag@EG_HI5?&Jx`>-O>QmKwxndGn0$v8)R;V5Y7J}`dDOdGCa3$E1t3ItQqVG!em&YQ~*=%g) zFR3Q89cAmjit0qRgKW>{QH^4&VC!I|8qBs6HeP!+X1#N8;$C_k?vM5_ia{-aM(o81+kT~J!TuTndY{#-D4ZMg=!(&b+(~fsjg=G zjcss|QR9o~ZWra=xSQ`bdTue>4{Vn0ROhjsW_zWW>MXWqw%#RFQ`s8WTy{`Rl4jjO zck5b8C7x|RTj!lrBiPEwR_~(t3EK{~M{J|NqPZ<>ciG4tADvBRJHqBvMKzAC zimlUrs^M&V*q%spKWGu-4;XWXm9Ra88Fw?v=7ThIhi$|mI?HFf#^!&RY98CKYy+#Q z=CGY-d*cYzEVi?3o;5}tS3`Gem3!ls?zQyX47Mh=UPq};WvgQ|9iy7aR?YUp*HmNK z_OW%WqZ%e{VIAG=KQ80yX{MO%0b4)=)lJgctX|?)gQp16zm)qldI+n|WSy-#OLabP za}`%~eyG#k<{`3e&LYa@<#0-*$CyN+&G=`m_PpIl5emW5?=Ul{? zCbBxVes*;>4KqEPX(ktDs`|It$-&*O_0XC%Z>>cer=8T2wQsaM?OSb^)~YpVr?jh@ Ly~_LKrY`>j_*N!6 diff --git a/target/scala-2.12/classes/include/dec_aln.class b/target/scala-2.12/classes/include/dec_aln.class index cf9b749db3bab9345f36cd0ef4327ba139116c95..21a707da5924a5732714e1c10ec98768372ecbed 100644 GIT binary patch delta 3869 zcmX}vdr;I>90hQ8)Ig>%VF4{H(I#O_lu1(2GEi%@ESE*(y{v_RiVq%&<^vEDP*k`n zprFP>)KFPa^1Yz>s>mEQv$Dd+jFqOSlaEmQ-Mf3vKR-VAo^$VhXJ>Yn&8_T`TiK=I z=0u&d2r>2&^+tEm%jl<8VcZ*`NjJ$`JT;DY=xCU)$PM%7YMknNi&sp+n#`uLj&+Z4 z4{_RLzt3Cr2$wg77^OT!W;o6_huiN>aHR7mjnpJxv2D`(ntDgf)1JiTk;L6Z8_PD(ZL2ClS3UrJO{}c9zNWQ_-0~6;datu1V;HP>ZPp)B`Fg87I=HUDOTA zKSlP8DVVKVt>ruT2i0d9?uw>LsdH4%>F9k(t)Na)-DaQ{N-d!dQV*4UQ!!h5D$X@f zHz~tRq)Ai_)lR)M3%wYsj5<%b&qnVfY9)0_sbe-~8$Ac@Z0Zp8h#H!PUIt~Q{-It= zM=zPGr7lx1XP_5Ll`FMoU^b6TbS6?o)Hjs#T=d3JIn-h5KWf-KoXDgasaw?RS?HxG z6=z|#D@^*%M<ols4x=Q&jMlYV)K>b8{EU9cU>sh&r_=^@y5KX#XxUh|Sbp>fIGc%c&dG zsFg@dsB6@)B6}+T`;f2sn`3Pdfva#XkGen^RwG?R{Xq3!gLE!+it;H&I*U3&d6pne zRw^#RY;FRHh1yLye~vVo+5wfUMQEb7P!FjO)}gnFxWRHo>F07pjS&hQ1Y$9Y#Xc4>7d3`W3QC@i+ZaD=^E+^^=2*70_s<4&=#b*)OpIU zPNv2>%=W!n%MXR`R-DVAPEapwLz+spP#)WnPNnuy&wh#2Of^#7>XAk&<)E|t(YyK5lIepjvCN}bOF^y_1!Jg z_GW`fr;by-_aL1?*(mpBq>0pChvaPX*7&c`u~J?4VsA3Foq9}7+=pH@^)EGUKhg^7 z78QB`>00W#QqO~!ZPh_^+NmLju(zE0nHqQ)X*PA1detUVOOe0GviXSyi9jE&-zb-1(&t06y;u@ps?(f;;CY9j-jy`J} zU{a_3?e{mTwgGfs@22P4vZMgMS5<)hIbr(sDS^W@x9xE%@B_^|1tn_C4T{kCI4D8m zj0sAk?cT2k57#_8c%hh?lyiuOcJ>U3)3_^SMiVWnZ)iX592=UWo!f-bXBZP!sGXmN z**=3s4GE`x=@~|~BHT7NsmAcP>AHwv1}D`o%B-SvE7#2sX;1xhE7I*>n2&Y`i^_`{ z3cIP>kZAiXOShk+>HD>2n^ngcuckd5l{LG&%80SeT~tF%PmRq!A-)gJ2dlw{VE<34 zmjLbt{{r1UqkJN`1^f-{Fp=^QFc&-nzG9_(JeUPGg3V(o_W~DyhrmbRfJxL#1owcq zK=;X%Tfrjmcd+9W%0t0C@GRIaj`EMd<=_dhMLgvrz=dE9_!t~Gm3lM5a_~0jF^%$A za4UEj>@=P7FmN4s4m8f7{9|whcoK9>pnN2_2s{iv0S6^gZx&bq{tdo4lk!R6Ht-7g z#w^Oi!S&#I(3C{E510*p1Gbz^`6zHPcm(_p96X15N#I`a4)|6w<&(i;@G96jh4Kh+ z19$;6&!yZKTnT;)I(<(0XfPG51)qXL=234pSP9+*d(EeO3RnVO1G_AsJQCap{s>wY zQtk(?0>1-WEu!2TOatq{XQ1a|>dgW7f%m}Psg%co+rjH#*EGtbzWl)`QQ%p-ZWk4DJW-gMF4!9uMvSZ-Cu0D38`?QTZA4PQM7cWYXC`liu;x zY*$sH&1~;eSM@~r_$>Q7*Hsk?|3|p@a_+1beoOf972L@YeqH$BY);J}y!w0VIA0_Dn(#sExsxUQlJLG8 zxRWOQym0r8+?gl*wD7L^+({CC0{$SMcb`_k-Fo5XO+1ekUM>9P&D@C=UMbwMkUJs5 zONGA>?)N44w+Vj)@3Dn<-?W9h_k@os;(4C%KZU=$l{>42Ull%Z8+S5=|029kF?Ujh zpA+s@LY<%z-u-*bY=5?0w(~t^32zkMeg}7^3a=Ax+Q}WO@Poo%+QpqH;d_O*DCJHt zd}%4~{#@j~W!&8={Gsr1ySY;!{I2kkd$^M;{14&7%DJ;j_!Z#;D!7vYud3kPd++6Z zvGB9PdscF1uJBXBJMW{;jVf0)Q+R{$*YDKu;%}grixV4>=gVE5+p`*ds!OhUx N!OP%O*{UJM>3=i62X+7e diff --git a/target/scala-2.12/classes/include/dec_alu.class b/target/scala-2.12/classes/include/dec_alu.class index 37a3912f97ddebeba65cbf433a28f530acada3f4..a5a527748583c08ca9083642f38d1490a594882f 100644 GIT binary patch delta 69 zcmeAc?iSuq&d%sMS)W66axc63>TQoKLSNuI5vv9FmN%tGUzh8 VF}N{$Fk~@$GW0RJOy=Tj1OShp5extT delta 65 zcmeAc?iSuq&OUhyyV&Gjc6CPg$@(0klTWd$PuAlQo6OFk&gcacIVS4Lz{Tjspv&ma U;Ku05kj3c5(8uUHnTxX#07u^svH$=8 diff --git a/target/scala-2.12/classes/include/dec_dbg.class b/target/scala-2.12/classes/include/dec_dbg.class index 59128b14d568417030a392d989fd3a2a015edbe3..15fcd66c1043c4c0d2744e8506385ad434ec3406 100644 GIT binary patch delta 43 zcmX@gb(Cv^GYg~XWXV~Ga<)}jf7 diff --git a/target/scala-2.12/classes/include/dec_div.class b/target/scala-2.12/classes/include/dec_div.class index e5c09177f3f054ab9f7a951a7180d019a6b7eef8..a0861ef332ee26a4cb0b12a54ef2c27503efb431 100644 GIT binary patch delta 39 vcmX>gctCJNB|D?fgctCJNCHv%k>>`tU*$o-}Chuo&<@I6UV)SLuV)SG1W%QXG$dL~K{7MSr diff --git a/target/scala-2.12/classes/include/dec_exu.class b/target/scala-2.12/classes/include/dec_exu.class index 1cb60fb829f59e6d101f9fe041f6202fa61d2eb8..5e489be2f4b4910beeaddfda28243acf887d8654 100644 GIT binary patch delta 3872 zcmYkm3)LXR=(qEFvh4XMV>F@m@`rno>Y9Srnn10l8Y$xf^!%vhR4w%v_2EL?m`7Dm zca?f9!fZ1apYcrpmc77i z%vPrM@^9g1$|DD_6-gCQEmV(H=zT`5q0UkrSEDzY%Ak%>?Mj}xm~BBW?p0C0Q>Hwb z$}h7yR5{f~y`69GIg7}A`&YC{ROZ{i*i6E>1`45eQ_rc%U!qq^J*LKeg>*CZfEu+H zX(9C+u@id`jIjfAWf$(Qhf@ME~dVtdI_ZSs8f{7dZcre z3f5z`ZX1x8sYBGO8<9p*`=P=jgu&D3 zbjqox)PyRe+o(UOPpXk_r0!B94kEQuzfePKkmf2?*I>2}4k5`@YO6Jg7Ru|eOyyZB zb&l%&Ez$+l8Or?#(gf-xuL&c~}gN#!Q2UG0Wg>Txl3=%r^KLa|{8-RfZ6w LrRG+%<+XnS6VfOX delta 3582 zcmYk9X;joz7>8#cyoBWZHdv|z@}eL2Tn)54`A`=X2tDr(_|yP_!Zs(-^|M&g9Z+*GXbMN#1XYTM}fSN+DnnJJLPlBwe z%H?jV>IL_LImPM)`>3j5yKx>A;;ZU}4AJJ&YY%llBmhr1LVK#M72fJ>OkI^0YR;Rl zI3dhOT?*wHb7v3xZ`WJDimy5vMz89t-U|=JlgZ&+FNO~_&RRyy#&k&p?R`~~$kE1G zV&p13lM>^txxPzt;^j^wTbJm&92;W=DRmlXX5-d>y9CQ3Z{b|@DFOajZnr(ox~G&dF81>OVw=TRREZUC==@6M+l39bZx z0N+lcJ`BtPPk~+wsP_XGfQP_mV3&n7Hw`QX?}Gu!)W?Av!Rug)6zWl69(Vz4luCU# zmX`ejg$2J^v-VB^KqKL?kBr@`8p z)CYjc;1Tcz*lh{TO$T>_e}IlGv)fdB7JVrffj2i~S_#$l6@0gbE4jGD_KCfj$2D4P7h7&V#}KhCVlTvo zt>U@$VvocIt>(H)n`bp&tQhqYW6iCq%2uj85|c24a50Fr3)kghzln9*$~8;uidg$^xu%KzC>F5ItU=rOZfEu0<#wo6+xfW} zV%1{JcW|8~Rw3rSlWV+Kxmf*OTt|!T6{}s$HBwt@G2iW#l%Nux*(CN%Y{+h|>%{&N z8@PvSp4eTnUVFK^#eNm*TFP~awmqeMw~zO6N!50<%%Lud`R_NYc{We%j9AM9T&Ihj z5^HvlYl7Huu_k3)$BC7}%)6QI=`81&Jz}*E@mYk}cCmlNMjYn3BC)4pfk(Km75h_c zz)`L%#qMZpe2nk5>=@776zg)F&oad>i?ypTtIKUy$rSbZgG5QIc z@~$FF#Qp{LHkELSXRgD%)rji3eyNrw)-;Qsb&(~&nr`WA&9L;bF17?(GcBRk)Y6*j Hl(+r`;n@@b diff --git a/target/scala-2.12/classes/include/dec_pkt_t.class b/target/scala-2.12/classes/include/dec_pkt_t.class index 964a286225ece4c6b69ac6abd9acf5fdc85a784a..100a49ce69bdcb173dc7c41a4b893c8bebf19388 100644 GIT binary patch delta 1162 zcmWN`TTB*Y9LMqJ`8{4Jl5S2Ov0f2)Uw9BXyu3AMhM;K(Xk-YAhY*m=10X3WAciRi zGgEl~Xr_XPxv6-V6GfY?8CLVcQ(m;h!@M9*7tWHJb5r|WefHh=eAW4?lU|Qbmts$t zyz6n|^;lU=i)a^Zr%!1wO&sN9#3(DvXdXR8TWKG?N~0p2434l;NHghf+DQMTJv3~z zlh-ttrjE9f1w3`l!bn=X5P=BPAjkKIzpq=z3eLyEfIq^kVSwoBIY1%>mrnhKP zw3F~?E6Zsot z(`hs%#!3UNpg+^2^c8(b--~q;6KkcKme4bFFa3w!rpeC9NN1&t&ZbAG(EIc{^~O1Q zBhE?@&8F?NnfB6O=!h{+^cX97G>x{>we%`IM+e6{`IlzWK)jVkx`Ou5WArtBL{rB) zi5+XDhAyJrbRT_2?@)h&lQ$Erl+!u1leW>IJLo2Qi~dT(lbj&Q zND@>In3i`ZN`SbTu54R0JlgIJ~a{n4(fKRb}7< zH4_8s7`#OPGhF}2_LIV$W=EmOWj7Ex{rMI z6tmR}%+Ui-pod_t4#zwljrlqO3-maAq9@g(P-kPI&O?zdM6q6i61@_ObR9}{6F$`~ zSgd#9Gkp+C^a(80=deuoV7b1GGW`e2^*vPR$5^5JQK?_ya}2~v48tmTP=#200Y6q_ z0@h$Es*!^l6rdI*Sc@{$@vKArdVGn^s7D*tqXS>zFgD;6HsVJ#;5RhlI-1anX7phb zp5SXd$7Tb3V?wdTSbS?DvDL(5n|TKUU7Gt}q#12!7?@R-BnyvWW a?8Gi}0K3gG>@nSFA7CyZt;>ubkN*LaKwa9LMqJ`8{3?9m&F@=BT!(?Nimu>DjVirM6LRnM<{FM)g#O(N@& zL!C6!#q86=9D#A%UEufurH+@6z(zIb#1`cyl zMRRBe-AZ55>(m!%rFW#0Qkp^A=z98yUZ62iR$kEn9UbK)L|4-L^b`$`w(^4J(d1|+ zLAr$Aq=#vk*UDcsi$;5$G|+kU65Zo6jg7PNnikQIsA*oh+Xg*C%b+V0? z(cAPW?eDkpm`(*C7db2DFF#-KI8O^}#qb0H3G`e5&H{net=2O2Y(| zfebYb6V+^Fs$yiRGGwbtOj7GGS#8GWYCEQ=eVD4+FioApboC2z)HTddw~?zJAWuES zO!XYI)c?rWz3_$ZhuJzDU+QSg(TSL=KSF^XSBrT%8-+R-0bPJ1y$JL5G8F3?e5D(( zKsRBb-i1Z_AimZouvnkP65WXseI2Fx4$AbOSgN0*T=(D`{Tj>g4!*^EsDKB{5r-A< zVI@YR65~;YDX2z1R-p(rD8Xv3Yf!ruwb+EUXu)>~VI2-*J$^zR&Z8bz(STcML>D%o z8yoSA&;Rhf0XCa3{9r7$m`H3j31~7OqS=f^&}2eP4qD6{Y%>e6-IU`;Q;i*_4m-^j b>@qvB+Z@0ia}2Gf1EF5#0@B;f$dPyp4=GW9LDkg`#%2@(mlO&PMz-O?S$y0BD$JsM$*C}v9L%r!y?tfBGimUlo^YD z%8Uidj0K93(S@;aiLr2ru`t9~7-B38xh%>vtv=sp{fsq@HC-R~YP}$Bz65#ZwKCx~ z65+ElN4L>@pOJ3bO7GKQpXp1oGRs*)ZIY1=+DOOfApJ>aXkM}vU$T)FT2HUge)^eC z(=5N0XupvLT0_s%9{QF}(Zm!hNHJ1J%c;<#^f{fRk*QXG(`vdQ)yQ$$Mjy}-s?w}{ zrKL1G&B$TeM91k6{YBr?P`Z_*bR!4pZhDmt&@c2Q4P;n}$uP2y?w}WFFMUTJQE#Rd zH`B;2T0u|KPWpo0rcqf|{?P5TAj`-J+D;$RYg7lUe4}MF7%*~#Hq!}uk*Xi zT0;wS%xF)}eoxoD6RsB=KO83nW&Wh`;-VyQEYWzHvrJO8j; zMIl0^BT^M2N>w9T?L~}gN37~boH~nmHG&oD9um}R7&VKPY96a}91?W^UR?~Iu0@h= zK(ap61;6e^iav)_eFJHF3hDX{GW2(3LL&#)&1fK6^EirqeJb}wOzJBbqaDN5asD0AcIQ0@sw Tg~yLdPY7E*ReF9Dc{kO6+RNqv delta 830 zcmW;FOHj>W9LDkg`+xo?qtNTw*K?F&2gx3!_{X^04}RXP(6~-aOuXWx_3U?o@f=Hd5fx z65}z_MmN(D+CyjQU243#-)p4FtEGev(M~!;$Ehb>%Xiv9^V5wC&{jH4FVc9QmXEZS z`h7-vX(OGYXDBkXyr$(eEyKuRT2Cjb&>!?EEzHysn`xw-*3eOUlzyi7XfR8Q$}-YS zOX)B@NZ-;4>dn?NM|aRjwvj=)k3OfDXhM#bPjo8{hRB(Y1apaegBmbPK&qkI^smJ`Dx5*a0Igw2Ypkhv++cgQgoT^8up@rQMSv z1;(hN|J7!Uyx=xM6N6f2X&p5|BgbhIeMpC>E2L$HR#H#MNH=Yux99-1`Iafnsfh*L#~S2ajbyO5|lkfeH$tWIH>8byk_1Fc>nRn20#`hzq(32r+8k6jF} zU59kL5kC7sH!|!#WZI{ZWnV?MJ%t?m6>{yb@WVy`8U|qmQHl_@v0AVKomhzzScPHa z;W}315!PS^`S^y26NLiDjY206MNTEwIrUiY>_xHDg$+(WHah1~;!L8{d5kjWJ<6Tr Yc~rQfQR(twlPiKMSGBz`hWu;lFBX#H*8l(j diff --git a/target/scala-2.12/classes/include/decode_exu.class b/target/scala-2.12/classes/include/decode_exu.class index 5bb35e9ec596513ef9907c5fa2abdb3ebf281c36..d0e2574b3f3c961c40820a4831eec628871151ad 100644 GIT binary patch delta 4085 zcmYk;c~I1490qXSRTGa6SaumpO5~4~HAR>)&vZ;Fk1RoFLV@K_r2_0ZmjC!Fz#46w{mv6|KBVv?(=@-uK=8KGQ$H_w&Bb^ZxiU11wp!?Xqgy9Xt`t zVz^64H=YsV!ha9$rFMZh8!Xfm=FS^K#yZ49J$YcLH+ExG*PZ_rD!V==f5*PXq~)7T z_V>B-7SoXbo%@H;{Y7E+_l7&tG2ugnXA18D#JY75^A|l1}OhlS^4vDmgr%Q-C ze-JrbsQ1)7?6v&HRHN8+n3gD>Y12~0vuUM{v#5STeo=*veM^*|kn8jk$G%~@!J*F4 zH1UH-S018vKBn$`i;{d-OSJq>SezU8iIKBPWjUndmt*Xyj(f$DQlPUAO;GoAJUWg# zl~AX6I-3IRiI-FPTDtK^@gtPHd5~G2Wt-&;*=8NTVwT^7)O!h}@z7G}Jk)*$^+rGo zpySXpsQ*m5kpvxp9zx!UvKNp@vu#s*IonOhV-~$@3RDO+LoP|w`wChHU4S|yQ|~h< z6RLuqD|x2SY{@Bf?;!LDGNw`*4Q+>RK_8}3FBq~wS0UGQ>U|9@hb}6$rPFL9XHz>1 zIsv_a2F#&e3RDLD0rj3sy%?wjx($6ak9r|cky6b(noT>OIuoE3kQM5fLA_B>HgppD z7aF*LZlprx(4Wx9nbeC_%Fm?PT9Nd~qE0BZ4!Q=pWm7KzS_#!b&NcvAlp}SDerPK?9Hb6frv1K&d#AVc84K+ZWms9!$ln2!) z$-myOp&={e4S6;jIt)F5d{$D=4DE7A&L-dBwTe37P%(4^a$iloNl-pygSzBXZ#1+J zs)gP_LksA}9HlJd!aW_U>WsFpl3>+=kKS4gbQN?P>R&_YVx_VgnyqgwCD~9j zWH?RfT&Mx+afZ@l=p5ATETv|s8ge~HX%tkcbn6_=W;#!uGN}CpI{OCN4ZVUUT%_JM z=x-%oi#H!_?ZvaqdcMeN;E7f}KP}dMR((O8f#0`k`QSP~Zm84p%sL}C*Xen+INv4K zmty@@tb^(e+^b&C)5IDs)(Wu}i}kTsZ-})|gMqs@=y{x2CyBLGtodTSBUYPOJ#7Zw z#ir%KHa|XEteb5{zQU&GH^sSCtR9U9-m%e*2Q`L?A8(f?H(uXpa%lJ^yL7zbQm8sh zQcoQ(YO?Qjyz6CBCiDb~xf6|e-S zN;bpkE}O}^ute6E&0+y8iKVb)W)aUSmddWOH1>?8Yd&DJHN)5(jfu_GDj5la_$Gp$mjw^!1Nr6UNXYNuM;Xh?DsOLDUzvf8prQ@hBgSrAkZ z`;r7fh(v|#mRP4nMNF$G+EG;6o_oIM-tX;XCcoeJKF>M#J^ABiPGVWJ#Ij}wPkQt4 zN+)jc(eXH+cKjFbZa9x4b5GT;`e}Hb<ON-!6QjuPZr^#x)xLr?2%IEgxe3#6G)i z*7D6}+x<2Cwt2w+vf+O6Ua5Yz&#~>N;iLTrs(tGoIsRi+f9xNjGH|-D%8KdpRDL#t zt2Fp%_-``?tKM^F0-0&~&6#fMx%I42m5XMDE7Ye4^iq#~1JbQWek(vcLi@li>bW}5 z`Ura7$|BYkAEDts7VBKgGcCQvb(VoFn6nTa?-69PM3|mm3L2oMdhQZzvnacrg^fqY z5@PEV*{xNmZ8ptrdqTyZ*CR{EAB7H4_Hg1JSs!q(FzejFGr~+NFN1H-7Uyx`a_}73 ze2&P6fbrl7@CDdsuINR82f&A*Yq-b*!CdeT*m0i7r-7MZJ=iWnNRfXI zCV<7@OVA@q^diB7;3Lp2TI3dR8~8KWDMsYpU>0}<)WnMXD{v)P0XoeW`A{$sJPE!6 z`z{c@DDV*Y82o6V$b-P`;9cqMy6DXZ4};IZ9$e&M;4bh!=(0|H z$9rTMdF(oC*ZO^G{q~uW zvus;#xzi0ik?P7pj}tK9v~T$xWNUP!#}0{q^W^G-cFKG$@q5Jk?vkD5#D5~*bGPg) zA%2y(>mJ!zOuUYG*S)e6P5eCk`ChsEoPDxeN?f;J&Mm}`6My4??D!KeAntTfcBT^F zOZ;Er6A#J$cH%GKALh&5H|5LjQ{ux4b2I3xvWoH@jABp!kB0I_O zDMyX`3h{17MQ6%UvAZ>|wa<*aOOY)%@+jixh`)PGc4iYlO~16e7x6KtWG9FC6XHWlWG938ufzwQmYp@k?-K7*DmzQz zM@r@H?qxDhB3@72bVha-60afN`3KpFBwkMZowKqNM!bZ$rd)Och!?@{m&@JF=VbQ~ z@#g2{{A=R7i8m1+Um^Rs#Gk{huQ;PByYYR>D^6;qi9b+yMxm)n%bP0Qc$h-Zs@{B8 zm4PQ$nfQH$B??`t4g9r2e}(<4O*}_ojKZ4=3lz4mG4Lk}CoAk;W8!NShA6C6n5VE! zt%2WDII335JJq`JRSLapd-F2JeI^LnqmBsUN+!Q@C9LdUU0!zokgg>^*sBcIO}=aOEyce+cUcbT(+gx?KZYv%(Ml?_0G+v20Lh2 zh(jM1>fpt~93t3khjcc_p@_|OXk_864V%Z@Sp=KFB3YF3lf|N0F^geWSS)+N<~w#^ h3mgZrg^p&n$T68McHF??97|ZdV*?8==y<)s`9B%_F~$G@ diff --git a/target/scala-2.12/classes/include/dest_pkt_t.class b/target/scala-2.12/classes/include/dest_pkt_t.class index 2762c74f5480400b6a6d20f0ce3e2360b3162351..8fecb6595e393a7b0b8fc0f6dd8a87471f419542 100644 GIT binary patch delta 115 zcmew^{9Sm%Ha5nGlMUHLC!b+cpS+DtY%(Xi`sB|*+6_n>u!~J@2GY4e`T&q#1*HE1 z>E}S&ibH*}3WwO_a*lJV4;Z)@A2P@>K4LIpe9Yj+_=F*f@hL+d<1>aP#^(&v7+)}~ LW_&O?i?bI1+L9)j delta 115 zcmew^{9Sm%Hnz#1*~BKFVN;)Mz%DkKlU;psE|7Ku(yM@UGmw4`qz?dT6%Mh|gImbEGhYVbdj~L__A2S#+K4EZUe992T_>3Ws@i{{i;|qpqj4v5h LGd`T0#n}r0$x$X) diff --git a/target/scala-2.12/classes/include/div_pkt_t.class b/target/scala-2.12/classes/include/div_pkt_t.class index 4b8d6d9ea32a654339755e29ed71f39597d056a4..ba17cbf73cebdb36e2ec11558adaadaefab49bf3 100644 GIT binary patch delta 43 zcmX@gbChR;A}iyL$?>eBlg(MxCo8gwO)g;#<=xJ}#k7M#j%g=@5!3d`*I4rb7%vQs delta 39 vcmX@gbChR;BJ1QhRX$&*>4In@}r7}Xh+8Pz6#XGsD8a}fts delta 27 jcmcb~b(3quBo;=E$&*>4In^1s7&RD_8Pz9$XGsD8b3X@J diff --git a/target/scala-2.12/classes/include/dma_mem_ctl.class b/target/scala-2.12/classes/include/dma_mem_ctl.class index c337e6c6c9c8cb333ae48bb6ad378bf524797b54..ec3c186f132b12ae1459e905837a78878b49670b 100644 GIT binary patch delta 91 zcmZ1>xxXVy+bPSL_0HkLE>Ayhw8izWg%H)F_qLYO= o-^$7{a52g=C^ITBxHBp;WHBl+G&3qQEN4_<{9 diff --git a/target/scala-2.12/classes/include/exu_bp.class b/target/scala-2.12/classes/include/exu_bp.class index 21ecfa2b1360f0ba0db03acfd6da1cab71e81188..895e8ca05a7b12bd1472f26e9bfa27f45f79eae7 100644 GIT binary patch delta 3925 zcmYk;d2mfv90%}sYm}nxNb(Xow1Q5OS4(21wMA)drB!*vlSNh@f)FHPi6s&el1N?- zvJjFIBt=35Sx6$WubH8iuC{jCsS^HBw9q;}>n55kvfFAI?O2yh zbruVz+Mnkp%BBwe-@Y*b=Pd#D=Y~7du7SR~UGIzZRG&|=5B zAk4#|J7Ji(CfG^z374x@OEE@zeUi-3x#r_{(udukM0BJF4W z)H$OVINiQBid5=0WtxF>#SA%zX6q_W%=k>nOL$u4p4lp&ZMGW4F01?wQom5$XJRji z%Au}PooAu5M;)dfQ+;C5i&C=1Vz&ECdc>gJs%X3+ZER{?(P_L<>YjI*JRY^Ui`X`|`k1A1WPQq-xlFbM@gFQ|3YDXNw7O~Hv}N<}G{?HLpARCJ=LQtCIV_XhMLs2$YzRF{piC*M0$ zsBG#g)hP|VaSqAZiBbR+d6<-HGS67?PBRf05u zx=QsdMH)w)Q)(&2Z1cZGr-5?WkG)w`HTCuZq~TNr_2xmOfz*Dgm6}wBUNQBzl6yI3 z+fj~A3pMHx_Hw8{s9}eZW>NR4Pb!dZpnjnGA3?g7x5iPf0xH4}3UI=iXo)c9JY1=JI2 zy$?W(&f};s>dm$i>Wh8n$1geY4j9+ zR##zZ^bjK&U4_u^EA{&|{a)SZEIKp|5YP4d#3qyQZE_WvO&(&Ie!ryOk2bl8cBjMi zzis^)qewU%;?QF%@{E0NkxE>|*t4MyRa1S>VXu&KK99Zi)C;MKfD19&hp7f9ZG&OB kw$WhK(hR9ux*<=?Fw|+A3=g$T%}LAB2I delta 4017 zcmY+HXHZmU6o&VX<6<<;EyQGEVk4B;Gr>lpi8UG%#dYaL6tJP#Ma7N+g0OrM1sg^| zAr=%NiUouf1*6d!d%6WDnHUQ*F`7iO_kQo*bMlAh`Of>^yXWqYW$xPI7Hf-JlxEt* zpjxA7v{}UH@omKsn-9*T*}T8zMZqSqef&t>C)zuTPIg~*{sh;Ugww8GV-{_L-qU9X zg3MxOko*27aUf{G|1xVZ-OC>A{+uwq^Lj{t=IR~^A)_=u88Ta=e`tipywF)1Ukwu) z8*L_WENr0aIpNFL$Sg|2{j~GV@M#)HMI^dt6&E9VX=jhf9PPY6Qa-}H$O7%WB}#n+ ztGE#**Oeb(5?!O!xmmo#VBd$vQj$GQ!Uk*QT|h#8<=J4X9! z6@4bkvsI+(c0)J6N$zyD9k9Tst7(nqd6jKb*XB79=ixu=MW_13r({26Q?C+DHy zM({G&HeTkRf$PAtV9Uue{}@~b9tWR-{!?Uc4p<7_2mPkXJRaNy{sO)=P3B?XCh!Vq znlAIt!3?k-G$zP=Ft{8%0X_r!%#gjg;6d;Y@ZFg*p9~g)x4^d(WgZUZfmcEEESZl1 zGryarn4%X}=j9y|xO zS|IbG;7YIx{0Ho}Q1<47W#B`wTawJDg1f;xV8=x=j|4Y^*Fo!InFoSd;5Xn4OJqI_ zTm@Ex|APIKWp4p^7<>eFUn=uy;2!WU*lC%}qrffT4bXGB%*TP*;CZn13YiZFSA(a( z=iq>qvbPW{2OonyR>^!iSPV9Toma~|8r%xr1Yb*$xeauH7r-`aWIh5+0c*f!Fkr3h zC4m)S6WB9V<_Ta4cn|E7Ci4m4Ht;*JUAmfEg)LqFCOg0jV4HPvJ_1YuYrtkOAVc<& zzzVP_L;l7a9bRI1rrJ?|PrXDw^ZU#Pt*4G)-pIUP7IiY1|HQm^Hg!^%U)Np!dscT@ z>Y(l==3R1VzJPfH^Y(%|iOg%6dwxNkDa?;Ee`N!8VwjgRZ-b%nJ0heeb-nBQUEXE$}yng77N=N{^;Vt$pmZ!vY2 zF#nc$rxNPSV}2I?X9?{-<16Z(Vs6<>^LXZ!%wO6^ooMD|%#Hi06T*Bi^JeCO2dH1j z{4e-BrL_CDQtCcpKI9rcMI$YUbu6)QMw$l=+KCsT0Ng5c8Im)Cq>KsifVX zvwZ9^>h5Cxg!#zh)Y;1XA@ji}sFTb5SLOjHsguS07W4P3sFMn>sG{AwS5v-%`DNzb zr>L`t`FZ9YYN#`Zc^zDR#c5aTBa&UOIQCj^QR$*^@rmno?0l`C2ymK3YiDnff~&;mRQ8_Gm)@L-MXE1 z&kA%i*SlwHbbG2=S#U$5;+1AFDd~oR$~r@=l3_?yG7WjkdP9|xWw@(kD<;LE^mSG5 IpUZFcAJF!XT>t<8 diff --git a/target/scala-2.12/classes/include/exu_ifu.class b/target/scala-2.12/classes/include/exu_ifu.class index 21eaaad60fbf23e9718906cbaaca94b3654853ec..8479b218e9df957be0592c75ec81f03a578b7762 100644 GIT binary patch delta 27 icmcc3d7E>CGz+8XWEqwiP7ww!Mo|V8Mv=*lEKvYlmIb8% delta 27 icmcc3d7E>CGz+8HWEqwiPEiIfMll8zM$yTQEKvYl#09AU diff --git a/target/scala-2.12/classes/include/gpr_exu.class b/target/scala-2.12/classes/include/gpr_exu.class index f1985ca2ff0f5f066f57acc96ec28efc1dd9e866..e3b63dc745cf25d1dfa5819c1a3956685483c9a2 100644 GIT binary patch delta 43 zcmbQnH;r$@C054N$pUPmlV7l^Prk$|Hd&RelsAQei!qf!k1>rQh%sgIa<+T`A~y^w delta 39 vcmbQnH;r$@CDzIOY+{pNu&OhrPZnV7;!S1XVoYPuV@ziVVoaU9oGl*!=b{R* diff --git a/target/scala-2.12/classes/include/ib_exu.class b/target/scala-2.12/classes/include/ib_exu.class index b6026dc4046825f9234efa6cd2d1ec6838f2d53f..2ffedfc746c9ec4620413427344a29737c94dd47 100644 GIT binary patch delta 39 vcmZ3(w}x-SOIF6j$*)*#Cck7An{2~Y!kfUr#hA#T$C$(r$e1vBFIzqU3!@A4 delta 39 vcmZ3(w}x-SOV-J1Y+{rDv#K*DPgZB^T9~38b5W^fe%T07wgS zs89Y2qyvDo6^Gd5ULai#q)%}?)V#{T#dM89j_Eps5z`F@H>R5mQB1cO@|bQjG%?*_ Vn8tLMVHMLohJ8#|Ctu;51OT|&E2v8hjX1Jd&B>XVy+bPSL_0HkLE>Ayhw8j!Z)5SuK_p+31B zNCyDvEkL@LL!I&dO(*QB1cP@|f;0G%?*} Vn8tLEVHMMThJ8%eCST#41OS3GD$oD` diff --git a/target/scala-2.12/classes/include/ic_mem.class b/target/scala-2.12/classes/include/ic_mem.class index e019665d7ed5b9d1ea775bc69df5fc3f4d0ecb0d..8cac6fb9602bc1d8c31a6621ef5310bf965553ee 100644 GIT binary patch delta 4075 zcmX}vcTiMU6bA6Oi%CqZ5q1fN$%vXPY%&U1lCg%wm{`b&=*ZHSqM&re4vJz#LPEKS z7!^?LBDx|9f(lqbQ4mXtQ4u?qC=z3tQFHI*o$sGLzk9#$y*cZQg83Cz`4v`s4|r*s zS+$QXYw#Mb%E3fx@UmtrO-}sYVlvB5TbAbSz$SQi+=ISG3udz4QxI?_&Mw?xKGHzZ)Eo z%Rj~DRe{#*dB7L^)ITs8cO$vP8+2xqR6PH*1nbx zR3*NNOST=m6Xqu6#5}^qb}ln@EIr(y>J0S$%#J(pT|{TOde*Tj=ruHK7QJB}v>$4N z21HPA7PK9@4fTzrUI4Tn`b$a^MZ0-MQ9A=V3w;nx>Gx1FR1Lj>hR4to^Py7cDKs#a zdJ)hLsis)ktzR5<0-+7iWyp3m^`=0XPy^Iu4)uP3RzNk-TWCZ)J+VM)V?6EFj>LH` zbt0ji&|RqiJnEUDJm_!eqxsaE3S~i!P}c?28z&XJfOb1ZN!CKDjD!|K2cdrXu0F8V{|6jzgLy)EfmYg36$0kn2)< zA{r`!TBSZrqTPa%s9gYEg?cZebQ+WmH9_5%Q*Q#40-b=g$o z1MPFG&of} zA?{+KV(0SolT=cg*iF3u0+OD;P{$ogg=(Qrzf#W)N`xw)7toM& zdLjO!*^*>lmcZqPuXY66(Py4T4Ic z&ezgRsRnPxRTHwD@Ty@K3xs8;~BLu1!ax)yo}jn1Vs3%U(`wN|9&wY1wc zc@|r`{6^0uLw`WVb(AJR=b(P;DV+hW z9ExeTykhFKL1XsN-5TgVG;%Mc8PH8=sD;v1&=qLlK1!ECmmtRyk$RMf-IB_TtU;cI z9QKPuXbw~h^)96}5~_l%4^TQCDu=orq%;892fb59sh29+?F|x-a_Ve`or>>0mr=F|0*f!UwZvuHj| zd=~MU!)Gg>7x?__w1M?Jt!Ke}y7O7UXDXjp`K;x$cfEmis@Jn=e7fQ}nsQsCRqkkv%3aNm$~{e-(yGZ(?rSQQ t2bvqoLv3f}k=8-^M>|Y;to2l$Xd{$1ZI<#>dq8Q|HY&{}!v?JA`vkCL7wu8!S$K8g_ZD(%N{i0Hhl>0T;Tr!*LlZ43q z&Lq+eb)w-LSl^}X2N zL!|q=88rmY-2>>8vjh6evn*dHaVvnn(mYAZgA=wlcMS4G)~vWPCmncgm=>N=)gAFkJS zk#%=M>UCDVHb>Rn8OrS?-`g|QSyV>#GRj>Hj@IAPQ7ntL7@mO*e^JkU;e1#G-@?wL z)x9ZjKdgrB#;AQX+y?K#RxxT1h8gg0=r~sGLtzp;3vFW6{yj{9#qb^M5~uD>g$Lks z*nXVa$H48d61E<%_7J!RUV%;%)IJO*!*bYYqS}9e3*b@s9(J9i?oER^um*ORto9hV z1Kx*irl>s>u7&@=Po}DUI81>R&~}>I`@x0qm@;L$n!Ca2@F08vJ!hzUW8qHt0DeAG z?IU3(yb7J;)&4US@EmMBOYQyPB6u8{W~;qBoB?y;OXxL6-HV00U=?gTSM6bN9lQpc z&r|ydmX232VX(&1?pZL+zlT>%R;q>!}ahwY_Uk~K5#j_ z0PPm5eIQJPC!tlM+Izxym~ZGHUL~p@g5FD%ad0<$2ra*=Jshrw*I|pLYWIQ5;RR^- zo7xA$M0gTf{jT<&FdpW^*RbO5lnyZk@PS84%>j0N^s#^75e)_lW!Lx@jEvL^7gK`yO6D0;VdybR8xJDa#(bM?=sbq&`uuI~zHP2;NK>RL$a zGOpWPUmc=#u~Auv=-t{Kre!YIMJ~$`TBmcJjbWoT+YR`j^R4O)$}N>5nQ=O z-8xF|7Icj6WN|e(PG=*yc5uDr`soDS+sO5btKUglGq|1_<(cX(dX>0|E%M*wvr8=E zjh+-Vy7QuX?Oj3Vk^DL5b981Sme%X{+}0xQ{3X-9 z?7kO1H4ne3HPvouowVCpfObclr`^?7YxlJ4TBXUX-8Xq?4@^I5Ri^RULsOde$W*93 sHr>{qn60&c&92&0b7$?Dd8k%x9-}=sr)V|i9PNdlIgbpQYW diff --git a/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class b/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class index 0df41e3a89bc0e2a625c6cad02819b9b0ab5aabd..bba4904852b645d595d8b5c3144c27f61c54403f 100644 GIT binary patch delta 127 zcmaDX@>pcUNjAnulN;GZC*NmNpL~){Y_bfy`eZhCvB{A@+8Ibs1JVsZ`ZAE-3#0`& z)F=M}(!N02oI`AK7mzLi(#JU-YCdG(VtT|N$Ml%Ni0KJ~8`D#UD5hr&c}&k4nwVZN VOk;YpcUNw&#s>|&Gev#C#Z2GTO@>XRFQbR>}83#6w3>0dzlGLSas5SuK(p+30; zNc#fmjX=7KL!I&UQ`Kp}H#jB!pJB=;`i z9mE`~zL#$tv#M{!7H<|Vv1&%87-|<}k8_3=5gg~dU=bUs=TtzvGaaTsWf2dIy+!m& zz`g7Q^~39O+KF=s19f?co{8$rkz^556V=d4Wz?@!*HK8vP{q_;>fI#tMpCN`sozAs z?>ZWtVbo&kEY)-jdV?q%b)5Q}>NOTOQmH-EZ`6n5&>O2OZyaW8VDjF0bfT%%)D_A+ z0lgq<33ZNYHW9r5YA$tx`iJVBtZu|5W43aAufD;@RJTcZbsSYf-J?8G(2Jo8sH>D^ zGJ3((QtErE`4rXjor2ls>3cO>1@)5Z^9^22r}k1$sP0qI8&7Sa?o%C8(X&!(sB5}R zX_ze}4eea&2kMPT?<%D`;TnE1>_XCk$YdO&ragI*j}NZp{?ev4ih zWv4DsEo|t0scW(gvsEFn&qbvlHG?`pJ*Rx<;YKo5N)B@_HE=Q7Cm~y=2PpixE7GXKgKRw=Ji=kj68M+ur5%ruJyaefL z>KE#hrAP(!Bh@<>X%2OV^2W70SC1X$DnGby|lsjjEwKtVcSDs-!GMNXO{PE5d9oHz0|l z_EJqZA{|ccfb5$PhESWS7t~k9=&hrkQURNhuGHn&jM4g+AjzZdQ6FzXx{$g>`D{fx zkGf2GZ9_VXxPG?pr-n(RUvMQx{EQ^C8@ zE2jR`ah>$T@e!nvx@<=<+bbqPN730t z{XqpDL%NoFOnr77=?dx*<$nU{QtB@CQ3cWky2>grTXzQ%8&$8XF2_rJP}xOPB)N&i zN>4Gg(oGb}b&*_e%k_+0->&i$jjP;5q+CCh>vFlyk?Tdd9+hjWYESW^$}9q_t@7U~ z_oPLfsE#(|chadT#=h+-=iV$9o{G`W%;F`LavEn1RQMU3)lmL5@~pg|W|YaRUVBTs sr1jA*Ya!YdZGv`H%hIlCh1zw^q218#Yd1~JwOgicT79|Kxsqo80#lUPHUIzs delta 4024 zcmY+HXHZmU6o&7PBbJC}fZb@y7!^cfteFrCnueMXbySKV!U`gGMPqLS6)P(47b^-9 zl~u8W*oe|ZQKQ5O*pSTFlS#2AF^QVH_q==0$*<@6&imfG=kCtz%&m0RsdU!apAoA1 zmv|_f-AhG| zuMYNBb0fIpI#>Sh%%77m*nRJ4^LqbC&Syt{Va(4*PBs`E6=TpDHOZhg#!Gb^l47{c z?yIg3X=ixj=wx$tIJ&Lj_oK%ej2fDx)2eERb~4V^7>98#jGfOo)_Qz^HDo4~7}Z5rjFU^@66 z*l;@KeZYlaG57-PK7)EQz(e38u)|Es$ALS+yI`wXln(X#pt_ClFugszR zGcXk_0bhbabE!8IEC3&a9p_O#9^3`q1AUVzj{`Ho>tNHbC=Ul6;6<=e3gw@Ji@;K% zV?M<_z**p7@Cn#y0re(;x!`@!Zz1LJU=~;dHcO>E0#sln=(&jU5O6VA23i(V-V>Y+ z9s!?%otIE=qCu<5T|)n?_d&mC5`^wtJC~c zc$%y0pakGuQ5&HuF6e z3coD;olNe`6<#U4RTg)q39k_T<`(Wu6ka0Sn$4Y2@U_{zd*g37j}x9Ryxvys3=zJE z-LZ`;p~7>7KNH?}JNL7MKN8+6hdb-x$6MjQ@$DQ0+AiP?5 zz%K605q?p4%UteE6@CW(M=tL^VK;Y+h5PK``AFf%gnRDg&M@J5!aeqJCrbEk;V*>` z+Ry#%!vBJ|KES(Y9^mdn;lT%azE1eh!h7U#CmkM9;HPd056q{IYra%?jqnbKxHDgP zmGCwN?hftly59wJ=BHX5cISR-ity9IUq8Z~@xqIQdmrUaqVS`_8y(}0UHC!ab&qo= z629m-@BTvM0}HvkP57U}L%!wCX5kNne|myDYlZ(LJm@5MRtdi;{QV;CEP)pk@$T)5 zIZqM(1Kjm?)4HUMTCTs{B$W88Gdi<%)-AQETAiQhe52G~CF_jTS*UZ3&SyF==?pB> zU(d<{EVZgQ(OZR-+4Z-p^ix)KvMdJH`4rh?oST-@*+(rak2PjK>bYr2r`@w#rbV1_ z&nip{s?cY785JWe0acopR;_i@E^DFM6>Xe$RZG>bX_?w}tyrtk?r1kG4YXQIJFO}& I;GDDme^FKYX8-^I diff --git a/target/scala-2.12/classes/include/ifu_dec.class b/target/scala-2.12/classes/include/ifu_dec.class index a11e095e662f91d31460dff6b846d3d276586025..9eea1f952d6a7c3864688c62812fd7e68276ba00 100644 GIT binary patch delta 63 zcmX@YcZ6@l0#-)8$qQL+CNE$WoBWwoeezu(ZNR2JS&B_;axPn>C@%vSBOik(BR_)z SqX2_8qacGBBk$zfY?%N`I}Z>5 delta 67 zcmX@YcZ6@l0@lfQS;Z!AV^yCl#U?iSGms7k(gtkmj6#zavWia5Ws4N$W8h-sXAor+ VU{GKbWYA_5VlZRmn|zxs69Av05Fh{m diff --git a/target/scala-2.12/classes/include/ifu_dma.class b/target/scala-2.12/classes/include/ifu_dma.class index a25603b1ee6c965a165f7fd6e19e0640f4e175b7..ab67a93210fdb35bbc73505123104cbdbdcf8120 100644 GIT binary patch delta 39 vcmaFF^@wXj0t=($rRDLm& e6GFM+6EVz@MuZX;sNxGB_(lgyOwiYSV)_ETS3m3k delta 212 zcmWN?KT85(90%~lr9p9 lkxGsy`9LO1jAVmn93V#pV_aZ@E4-kCDQ+=C0@bs_^dH|dKcfHu diff --git a/target/scala-2.12/classes/include/load_cam_pkt_t.class b/target/scala-2.12/classes/include/load_cam_pkt_t.class index 64ddaf27a2bf1234e7f0160a088346d707af57af..6c2d95af3bf18d158bcd8f72f631f8b1c4e4cbe9 100644 GIT binary patch delta 51 zcmcb{dyRKP1S{jR$&su!lOtHgCa-2ypF9;vzhKQ2T*|=3xQs!LaXEt#;|c~h#-)>! G*h&DlArGej delta 51 zcmcb{dyRKP1ncCftYVY%Sk)(A0@ABl)frb#zRX%DxQu~|aXEt=;|c~N#+3|ijLRk` Hv6TP-$6*jD diff --git a/target/scala-2.12/classes/include/lsu_dec.class b/target/scala-2.12/classes/include/lsu_dec.class index f6b912b81040d853302993b5676d0aebe3cfa5c1..1c8e5ac930217ccf6a1c40f3c77b4b8d06f0cf77 100644 GIT binary patch delta 39 vcmZqYZs*?6%EGv9avO`ydABlfF>GTHW!TQ3z_4|)25US3`jiWl delta 39 vcmZqYZs*?6$};&7i`eAZEb5FqCLd;r;N8Z+#ju@0lwk*h0>ie+8m#dE0U`_6 diff --git a/target/scala-2.12/classes/include/lsu_error_pkt_t.class b/target/scala-2.12/classes/include/lsu_error_pkt_t.class index 954bef2e9e49193d2078cf3eb81ad8f007effa24..dde71c86612f7cabeb9a79fd59e0cae6e7becd7e 100644 GIT binary patch delta 79 zcmaDN@I+vPAseH`K$?k0GlMUI#Cbt0TJRp4#NUsLc|A6!hAZ^V)Nz$Bwi^+mP bj>(e2h{=kZ0eI&1L+nZ{Q^iI1k$SPVw3-|sWaM6&Sw*yY|TDN(t?4D e$&x{i$%?^<$(q59$%Y|{$(A9X$zt*|_BsH(8Wkb{ diff --git a/target/scala-2.12/classes/include/lsu_exu.class b/target/scala-2.12/classes/include/lsu_exu.class index 6321d40cfb025737a84b2d80886a4983ac236482..29411fb55b3afa5f656b500d6b27a832280db610 100644 GIT binary patch delta 1090 zcmah{OHUI~6#mZKnYJ^ug(;LrEzk!QDcAx9Yg-V9^00_tQBV+~l@K%tzA8wf_7Au* zmAIyqFwHj&#eJbLrCWb_z{lrwUq zl3%LL1aeY5zxJfl+TCK2+)6^9TI^k4b9KeZ&;<2Uz!*`TVlb=IDA~pXlksT56Yr~4 z^?So4r`M8g&K93r%rd}2P7zYG0ngy(P_Os$?Z#w&`El@4&~WHVBI_D9 zoHdHxQ9t2LNzLvNJ}(QXJsCaMy<#XgvyQ8&Yx7fG4=0zBu_2c|_b1QFh2-Y^%%i!8@ptZ2Uwt7znYF@0N6d(5t7^5Q2@NVF_{~)jqmcPRblci-OvO=j zn4iUntrJ}uC&$fJ*_Q|+szF9K!MS|n=KYmhv1n%F&VziL6}^O-$-j#!JKE8wB8GnR zq3j)OM_ffUPIBjdFR)_+-tYL3d^{fPV2@N}lu&x;tvB~-G(QW-4or252BEMg7 zvmFkUzm5(U`#Sb+_VX251q&vf<7goHptmtXGV+`Z4ebIv|z{`%+lKLA|AOG1}n<;_|_kD1k4 zR)1TQK!ia4l~L8rL@Zge3Z^bWASgL^eWjY$OpS1M(OtwU`j)BZ?bw=QUNg2W&8}7S z8G@L5XX{m>9Ut{fs%pwdgORa^0;Omoax>_q9QlQZo}{OnRADskO?l6gETw}KkUPmk zJrN-s9Fzq$u8JN*)l``xo|8{Jxnzh$@2IRwqLe1;2qptUS3LZ<^f>WuXIxf?RPXD} zKw+cnX~IiOLDIak5Lq&U5z*%v6>r8npIx^XCc~$a)DaTduZ{1A zLYhw&;$#H16a^M?m)|PSZ@sxYAMV}mO`H~rG(=*TU#!VPl)N;*xvFSG{deBno#gv_ zZ`t`DhNV$e+WI#0e$LvQd8sd-vX!UQ)#4}0ej-9#n~J@-T3uMa{2=h+swG@MyjR6| z(&2B;+7~;YPZu_R%zt;KFYz+%8|j@;mEv~h{gxG;&OezAPg%WFIp}N{~67|Id@qK{(llOz3Ga%UXU%+tx?c z)0RCVA;8)?awMUfb>W`3+}Pl4RZ2ysJ}PY(1^bnRldQwTHbN&WH0vm}QjKQ|3|MSj z;do`$wE!j^fZ~GnYR$B>MZ#%kYn7~=S<3HZ&5~Bg7BrjX+#MY|>`K9DoRQ%{nBcX! z90ub{8K8dA_-UyTraw++j%X9+@dEJHZgc6LGT*gkSB$((xY6<{#}L~jl6_r4%+J2A5(c8ps}DnG#xe>nVA2mS z5-oiqZIx?I(ywzQo7B3|edLsk8<-}XX&yGR?yAAX+>+4+PGNT=N)3pFJA}}Gm@etA zj9Gj|7>=e764)RfRuAKQkn}S?MW79iZ%d#I%hoHFX2!ORO2sx~t_GQLA9H@3!q==@ ztz0(W5n>0iX-_(MhpR~iY0Ufi(-xf6G{52=%WkH*I~wKYfeUk7EcrQt%PiR-*AmrH+OM+7i#zUJ>1*FgFP(PPxr9$Cm#Na!7so>7?U~H&xY$~_zN(j zpZJ;eO!RXufS=*VNA4=0u!>#0!Dsx$wu9_^*w2oLXN>NLz<33naQZ-yr662v;I*s@dBBxFz$DWr!dG{{k_{5(EGM diff --git a/target/scala-2.12/classes/include/lsu_pkt_t.class b/target/scala-2.12/classes/include/lsu_pkt_t.class index f7f59ab510a964028b97303cf07a2eb7590def62..7499d4c0687359b1e77b037488121b62f696c83e 100644 GIT binary patch delta 171 zcmWN?y$-=p7zW_ao5*QvlE~@AdaC}*K+;LXD7AJr+ay+2Oy6L$xB%h;%#GOvxC0kp z@jlB_ghhDIOexZ(Ni{Q8ug2+#fB1{nJ*URAn)4Yy^BsTlC$IWWe|*8mzSRTY@Pa>h zIdJ;r)8IC75+ITqn$kcl5n7U9l#A7 zK;!o{p9@@Y&y<{$k(ILY!dI+3BOg4)HP6Zp=lF@w_=n$k=o=~fRyKH!ANYX3*x^_k zDQa6tWudAv(YH}Znj2K%i0a&=kYh@?MPqK$j60NZmvZjWk`r2UpSC=pJ*RZ!P@>Z1 E4@?LvRR910 diff --git a/target/scala-2.12/classes/include/lsu_tlu.class b/target/scala-2.12/classes/include/lsu_tlu.class index 9e3a72020823c0283d2e173145e1f706d82eaf38..775bdde32339cd7cba39bd3578d29759c0089b8f 100644 GIT binary patch delta 43 zcmX@XbAo4s5-a1y$qB5YlPy@)Co8dvO)h1P=e@wd#c+{9nc)(H4a0@W4_VUzB8&|y delta 39 vcmX@XbAo4s66@r6RqqcSB5c9eJj7@;3=BpME5o|6Rar48SRYtfIUGMX=ROT$ zSUNvIG?>IDh;tFst%v!0DY5&uCz6xp1? z#Aam}OwQ)!%#4lX`;@1VG?M;NWUrAoi-OJgm~Y13TpVnl7kH1K@;^S}8yRn!3AV@c z{DL3yZ~nqpvfie=#M5lBIn_+Cukd$%?t%_2=avUwuBFAM#JH4I zTuF*+*~X3R;#R7-lVh}`j<&RMFK_6`1YP+-Pv&^g1@v_dkGh2?EnuK!JnI35dV;2X HE{^^I%s))A diff --git a/target/scala-2.12/classes/include/predict_pkt_t.class b/target/scala-2.12/classes/include/predict_pkt_t.class index fa0208d5aaac1475f321b0145e80b6fbc15d74a0..09f3f74a20c56f55f9ef4975f5a8340a34143d09 100644 GIT binary patch delta 176 zcmWN?uMYuX90%aqgP?&7e9q0Ftf5E01 zl?y&kc>*_Z=Sdooew>2l9Z!?A)h72Ht3%%BF<i^K!;&z&m`!r~JzwykaFiKNvcg$XT;zePe32rLScBZ; E4@As4JOBUy diff --git a/target/scala-2.12/classes/include/reg_pkt_t.class b/target/scala-2.12/classes/include/reg_pkt_t.class index 26fbf7b7480d6b5f32e77cb11aeff8b26e2ff180..4da927b9bde159b28f7d3a3ac6f1e46909f8a42e 100644 GIT binary patch delta 51 zcmX@bdy0314=dxR$-b;MlYLmlCeLS8pWF$g@33YHeq`Wc{KO!~_?f|o@e6|+1G0qOay>Wp6}A7`x-{KUY;_?bbD@e6|y<5vbZ#!r*O G*h&D?nGuBm diff --git a/target/scala-2.12/classes/include/rets_pkt_t.class b/target/scala-2.12/classes/include/rets_pkt_t.class index ad188e15e16d81b825a56afd487510f885f1f968..5bed110d1bc51379a1f5137c257c6ec5a1ee4353 100644 GIT binary patch delta 51 zcmey(`$KoAUh*}6@tTWx{qZ@Uh|>*U@{S+Gm9f{4xKkcyX565MfDu|u caYlg)7Pw-I8}_)P#shD3_~L2$XtYXpe`CKYt^fc4 delta 139 zcmWN?y$%6E6oAohlxBv?M751#Dh(}Bdw_inp;y!IZ6&;bM55Y^|FyNmW6-PJ)0~v0 z?9i|>u|c{v%2LnuQZMwM{?dmoh;vcq`c&WREB&Kadi0_2(bTeVo#WUKOh3`&M2|Bg aF63O9abwM$9S=$>-aPqIn>I-{t?eI?@G9#7 diff --git a/target/scala-2.12/classes/include/tlu_exu.class b/target/scala-2.12/classes/include/tlu_exu.class index b950e996871349cb0f966e2becd780999a1c532c..35aa70d4fa10c0c74661f1a1289a13238239cce3 100644 GIT binary patch delta 4005 zcmX}v2UOKn90zdzP^py@9%wl-HRP4%C@q|?%sp_i*8>qJ%M?+DC@vK0aowiy+zW&N zMcfR*QG%8>TzFEmv<{9_bn4i>fBxU^;hc9r_kO?k&+jnKgCzw{OA4Iw+j(nVqSn_< zT=#Ys!@Rp2yEN|sJRd04!{1H3>oeNWpFW*Mo{tB2ql~VXucuUB)dFW8Xh8L@G1HP2>fpN~y_5 z1Pzf|8I;Dov*;IWmOE>3jQ;8-9tH2M787#JTV$^htE)P+ppVda1#FOc2YNhuhp*hrkLuxM7=`sVIP-+|X6XiA& zy(yH9`j&ca7J4J8kYBx{yEb}m$ z(D&+_TSGPf9M2j}t)wa_Z9aN~sl`+Y^_=Rn05_tkL)1fEt>ZCUcs$xU)J^J*g-Cs< zbyO|YA_2WI)GDfya$JPo5Gs*6rmJodX6w5c?HDST`i*i=L~j~pr*2ViCZXp`t*5R~ zEtAn3ORd&bkc`=!QqUPnB~hi+U(^Rna3hw=qkgBlr=k}@?VxT`?U$nGrz>?SX1mIy z)iQL(QR!3_^->yo7Al!KPW?@NxEwd)sKeAF%43D7wn)n};L)aU#(v$5?WQZm(>w8dr?S2G*mcFf|PFQ5eK64mKTq;XUw z)z;RSsy_$RQ%@OtvuK@#d()_+)T;t%5S33ktwZWf?Wg{wCagzq2lbp9xk06|8!+1+ z`d&?G*@%1Vs0WniCZrkE9jfnUq${W&srR-ZO`)z(-L@iKsLQ?;vvvFmNi0=Cxotx_ zi#kcQ+Kx1wIzlzeMjA*RrW|vSPNnwgs?EV{QTM2i@>Och$85Lsy_&6e z0q&(y*D3SYNRy}U!k5fn! zsms*cr;*O5s&&<$#%xh%&^b%FoW)rrRZ2B4LmEmIQm>RF^`j0^FQ`css%Nozh+P%k zMNOouxLe^aE>*aSPL=MWS*5E8l zL9Rt|ZBpef>g762u05+XA-&8TNiOA48<9pgiA;s8FDTR`lhGjATNhD+C+zb+9U@*ZL&j>HpL-Fo9a-m rc{|+Kd^BgxSL>(w$q#=mQ47$rwLq;*3)1ds!H&%|ufpofB~AYa#~KQz delta 3763 zcmYk9cTiMU6o>agj6&=vXreL30=tPuG{FQbj=d1E0E@t~AlMNw7L;bh21>GA6-yMb z7eEZ4h}h_sL{UdmEQ}L1CL|eK5;8jGy?1}-z(4za_kQO-?lR0Wn{>=R>6m?fXJ5rf z)cU)KTfRET3x<*=9O*-z=XNg0uSq=;t&9Oi=f%!7d_jhE`9{2*r9}phdMbi;Kt$T&bFN z?=eBcR9hRA%xfp%5o}Ud*5D}p)kQoG4p#5gQ3P7t)txj;hQ9I)(QX+TvQJ;RS>1Go zTeTa?C$|^H`mXkl9K|b4c!myECtHe~a0ijv#BVq8K4FbB3G9yIYSF)qSOH=`(w(B6r&cpBlV^P^dk^T9*lL$Jqe*+amc z;7_2-9NDLVHt>7!t+}#~1y_S*;A?R3JUJH&9tWR+{pQQQ06Yvn0(&ly-3smke+D~6 z%03-T2d{uF7s@^kTmzO%rbo#<1Y8cD0H1^I(Q+;lJOcg-_KJ}`6wCx~gPj-2?h6X= zD%k1^*~f!x!3t1WEc;M!1y~He0Q)bIa|^*7@G;nXsqA537I+7IdztKh;3lvZY#l56 z1aKW#3EC}}eHa)Ao&^5}2dt2DQD83k8|WG*`%Ew!ybHb)FS|du8N3FzNsxUaxE`zm z?Gt4m4#tBe;6LEUNpdb4%maT1-B!vT4(E~$p~-{SO<39AbS9q0p0-HZIs;`Oa*JeW@)mI029-+4}LG3 zNnB5pAF3wN`zx|ow##hYzNQ+(R>{`MCad;OPQS`l%~qt{%~oU*t&eL(Gb>vmTk{iC1K4uO(u*lhW!ulz zz&7zD&1JGZWgAsOb*paYOXzAtPf@Y4{lYe|lxhmw9kza_sjgzX$!0u5HID5H+xus! zE@rFI?a5iXTjV*KInUPNJnhY5D`9I@Mm2=3fbGq4s%Ewvw%2S^DzrH-n^Ekoa1#!d z&fs_a|sESgul zig_wWsywK2rOF4@9YkrhQLzXgtCMJ`w&>pyUS4t#3u?6QKP`pkbxnNgg~t6Vc1PiP zF$nXHBDaaZcd2n-u+QSz*vpN*p1nmu(06_9hWHrTD^m;}%2b0{nP!MrrW>*pUqiX# qXLzXiD^7}8@lXQP*BMHj5~yS;lHd%y2eeypb9SEeYIm9OS0qF`LeHut_1=1Xx z>XSclh;4S|RAp4uV&G!bX3%BSVF+Z@WhiCTW0=9H&#;@(fZ-maAtMu`*5q!k4gfJK B8wCIW delta 100 zcmbO%Hd$=LLH5c2*u^GaXIGzW%^@~fghPFD1&|H|(p!OaACUe8q)!8BeNM5-9GvQm xMw<;dtr!)x8MqjA7<3tR83Gyg7)lxS8D=mVFzjYDWVpv@#K^>`J-M5!0|3ri8KeLJ diff --git a/target/scala-2.12/classes/include/trap_pkt_t.class b/target/scala-2.12/classes/include/trap_pkt_t.class index 469e83dc86ba57799d48d4092bd9be6e05c8f8f5..b050d0e022f27e71624aca1e6bb9216504d832e3 100644 GIT binary patch delta 139 zcmdlXzC(P&5q8F_lM6USC*NXMpL~Q}Y_d3q`ea59vB@Do+73uh1k%+&`W%qn0i?M( z)hB-i(jGwCh*NBGE0E3y(uaWb8X*0j^Q-O^1}?^{404Ru7>pRNGq^F{V2EP8$&kl* ei=m0}Hp4W=I}EEB?=tLTyvJ~f@ycXH?&$ztk}cK% delta 139 zcmdlXzC(P&5%$T99AcAiv8zwE1JdFg>XWO1bO?~%0i-7a>90Wg9FR8R6r0S=sXjR$ zNP7V3H9)!*NWTQqhd9+4?@un^6rKE^^Q-Pv1}?^H404Ru8H^ZjFt{<^WQbzC#gNB% eo1uyE4#PCYy9}!s?=kFSyw7ln@#0cl4dt<5erxeiEY0O{R8 ydMS|p!M;oJEdv+RI|ezX_Y6i%9~j)2J~BixePYOC`pnS8^o3zM)7#0HIXVD8>m#uM delta 103 zcmcaDbX#ac3ESk2Y+{qU*wiP#1JcKVv^KlgWEOVy$r(V}5lAlu(se-k5s==^uFm*% z@_RPX$v@b4DZXRiVtUUY$Mk{0i0LDP8`CF-D5lR0c}!mznwY*aOlNvG`7%cb06gy` AFaQ7m diff --git a/target/scala-2.12/classes/lsu/buffer$.class b/target/scala-2.12/classes/lsu/buffer$.class new file mode 100644 index 0000000000000000000000000000000000000000..a9d16b8a0ed0861680bdff9e3d8fbca3b56f9678 GIT binary patch literal 3869 zcmbtX33n4!7`-oDLeoG)OMyaV9VAVG0A-UPLR*kx3TS8*QR^gmEd$e;FquF>MclxB z!+rS)p5wxH=sErXf0W1jW+u&)M$9=TC$qfy*89Hiev`lce()!NUHDm`-7Htq`O4&^ zbhIdhK;pc9Nl%-)HI+V@KQ9Yz6iotc<$`YN>BFT`6fFYFs5OzVl=)Md+q|a&n`*j- zb;-UU)1%ToXBUs@R?(DYEo<8sDzvajV9ldNqlgK#`tkzN(UZet*&~|3;%q41jKC5( zBMTMRu&tb{JFb8@&J?_GGzP0_6S^~17U(*gtvSrOj$utvyDKDUScW@f7bUaE`pFh- z(`5d%ou00^dft@jtWkCcy_Bh)YeeoqAat~1d8W2k7o3Xa8q+d8XwS&v7@cPh@++|D zK*3b89296u_Kg#T1Kw>ME3qPm2zmsX{iM2+eRb1nQI84Mx@6#-NM!1X#_<@|w4)Vk zY12Jt5UBQ|H1#X8IKmLP&s7U^;b&Ax=>^M=%1UW8=k4MZfq2L|16*6RqXK*wD0+(H zacoxcB?Xo)cuuR+x?u?{Pu77!d2Lb8>1Tb|PhHtKwql#|l=fgh9!CcfZA5!#981xu zu67ZQP`!ACHKECiRG86r2y9OF1tI=d;fysVS;ce?`|3jd(ut!B%T%EIS;DnIC(6=w zrNc<)b&4N(bMm;tDOE?jwxm^C!`Dex!F+U@%IQ;h!!eL}dJ60zX%3{zu0AExL*5;UX-YIK(! zu0(N$G^v|zXieZoG8DukxH=OO3urU6GEedJm6FVan=8mIoNk~nq?=~Wa3#Szi4$t|%z`D)dg`kr(Ke(}p`vG)#L+X4m;Cp<4_uLe1@By5cr(g zBt(EJW-j>OXsv=2U14X<}2H{PR8JUuoxSbB}W!?R~ETpe%7aS zN1v7)5uE<<5zCU!kg1o;lDDy(U2zKXsG$rd2CEqQdVJoIQ*VVM7GGH8h&5@mfxQ*% z;9fT~*j66fRH3nLJJm?#Iid!tch7l6nJ>MyZpyS_IaYAx7FW7>R-foBBKNTBH}8g3 zh~7XT&9f3|N!`b~UwIM1S3I_=#mHrR&Fi=?fc2h#vL!Y$9%X$$r6Wo@)qfv-%J@R< z<-SCqtt@XsiWdENHGD%Y;9LG$IB=PoKtHxnX@P_7jXGFOU_{mAYR_Z`vGfs1)3l%P zZ4CTEw+lmlIN_yr(7KJ?jiI%tUNU#EyU}F!hLhRrCDVm{0Y0_eyNygE@%X4eK?Dxq z$vKdlpax`XYV92iG#;1Qs$kz#TuX5fPtnjr`*sJJ#!c1=`B2DoqDKw&VE@)JYV}z( zi{Uf(a71M-LNzE`U6+la@SI`xPFEU@7%?EHRlW4ug5o-h~Wlq1_o7gt5S}p9^eZ=A;B)f zcRa@UpbhQp-5z|;`v{`=f#+UcO<)mDA&1i#!#G~x?=(K8d=5WS;*cPJDZDx4vBIMY ip#b&zo?HcvPBtjX6}fgc6rAULku+)2Qd&w|%7;N|D-kNeDF_J=l_DhtDQ&N4ZEvWHV@J*!$iD)_ zhr|JnNc@OUMaU$nwg|#{4YPy=jl2=q8!bsi4-K zJEkotsL?2zu&=q(JyUO0D^l_6)(h`U`=(t*5v4L5R0IoieI--{n=_Hm<6xA8v2j`8 z&h+mKa?PESDi%?%poWHE?O*jzllM9}=6oeA3-ZT@og=||_di8cvVtpRT*fMk&1pCm zY|T${(J)R{d=!%Yv7phMuWVac*Q~5OHc9p@3ACWz4P$+n4LzM6DK8?j+)ZfriAqD8 z&%j#WDF01Qjb?eHr_E^+yi}zhFfQzV#==)DeZty@Y0);m#uoZcbMz;v(VddDD!L?Nfb%TWl!MRRTHOX5yd#mvNC# O)3N7@)i1b141WQ(Af7=0 literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/buffer.class b/target/scala-2.12/classes/lsu/buffer.class new file mode 100644 index 0000000000000000000000000000000000000000..6a2adab7da51d75098d56b1a1aa41775206c6b14 GIT binary patch literal 774 zcmZuvUvJV-6hF6@Qp$kQjWL-62V)9qtc`n7)P!x4%s?g*mN8?@ZF^x|N^9C%Gv56= zKIp?9eDDMKp^T^CHWR(c$+_p;-}(1D_vf$gKLB7Cb_k^1Fw)IvJm!G{gh2kBePX)H zyor8fo^wkmKnWBO^}&onlotxYAx*gWwG(d4SyuMtYK>cg|%>67qY zRyAs}N=q*st(r(mWw~kiBV)RMS0mdANukfWjRzaMnrvt*d+l^i&Z_eAd!o#C#Coo> zwMNT0Tw=-`k3g~Uu6r})Km?9AX*G}Wodpx@cIk$bx&j#jO7G}k*nL$eknR5U*2+K* zmQ~0?J_9PG(|B9KaGSeq#_dDT5lCI*4@sTKvxMV&kLRWIf85Wn$c#MUOu4@2UvPVf zIa)6l&6&PE%Rm9v;ySkoGVTL_k*2vyYAq3iQd poD#Fgp{odqkAihBq5NfTP^h7nK!$D9O9)M(C?TYvjt(jV{04nxo^k*H literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/bus_intf$.class b/target/scala-2.12/classes/lsu/bus_intf$.class new file mode 100644 index 0000000000000000000000000000000000000000..5e1113aff2f02743428216a9bb0667d9f9123eb4 GIT binary patch literal 3872 zcmbtXhjJ5F6g|&PSO_d^Y%sknLCAmrLm-F{unoaP1`=T>ge1;ddNvE|U9nox(ny2! zMtb>#%%so;&*TFVzA2OQwpeRhaWoTYwB_xs=iPhm>d(I)`~hG$eiB$@mMfXDN_o_< z+;J@iA&@+;U(z$CZcSuPj-8hUH-<)m)^b5N^~~W?DTZc&cIu6WdfUBc0-LIuhIPrl zATvYKJ!cn>=~mH{Wi4mh7b?_WAh2eB(HPItg@OsS0#IOSl^7Xj!_h zbQtN3PVpmeN*z}?rE7>+m$a}oe4SJX=KN_YyCZdphH2HAr!w58>6UGcS1iqvm$hD^ zzm%9Na)=TWyD2$)Er$L$22>NR32O0(RV>-$KaHYV$Z2Xr7kLn5PC2qD6*)es2x!Jy zHi1PLY{fBdC2G2Y!W9EIE+5k+)uZ) z;F%=)8p+Txbs!_R`#$s1F?7?oridtpX9YG?Ed_j=( z$eO^7R3wObs5%=F3pg{fGDGq7)soCcJ1fX7nr@)bubXDxa3#Szix=W}9xpQKm)Na( zsbrEQI;PuWx*{n1GW2%hF(%L{Ck=OmXqfhd#;wsSrmL|}i&&*#CWF_M=oMH_%j1UQ zxMt?CW!bLo4Gwvc<|lAYDH~+KhQ6)%gvST+i1027CZ-yR_;`l16>7csoY_m?r-cFV4#mjrIr za8>I~<^PobjOOrPfM!HLw--LZhjF}*kJt+zbK03+D@W2u;8WaehrnmdCT~nwx?6Er z>rMVkOIyyc7nhTw+eY`(LN=wuDv2aE9mS#o4ScV&^}=x2ROcl1fg8NufHym~DhwD`s%2d#0NP3)~;C-=IE!M5<& zs)~)R+pcCR&kbs#diNYyl=;G2>!eI8y0DBZx46>5v--rQ&~Ohce)Vox|5z0WWO!C0 z&FTAC_X{r?@FkBe-r`^Qiq{EW0P8*fWK3*iJj(ihN;fF!bkBWkQO4(Lcli>5wz9kl zXtz_`j0haS zu^E0B?53SKR-g=*{*vsuy{zK~bg~~S+@nT5i{lb5vp483sP_i-eq+^Upg=?C~6P)M+g@GXyVK4`^4 z_HH-6<9!2S_@3ugyc)#fgc5Pg$Rk|s?WN=t!$04_>fiBJhnK}dk86e%f4X?v~K_LjPJ?8sgt@~;5# zA#s2s68tB`vzs1LiObH;^URw!&-?rD_a6WrPApgZYNFj<;2Fyf z-ANfDSdSg$t4@>z#vAF*b2~PXa?D;5IK~TuM`h#%E%F>+@;uBs1SKm>jE)42{>+%J zps2=UeMg`Zg#A0*m#k6F0 zpR2ZUztU5W1D?^C_H1o8m3AwYR=^z+z6@QR8sr6fKN;CNI#9Mxq}2~;`;m&gG@pX? zp;6BHK#iw)bD+&>=)O^r8fiLBY1LtvM2_C`Qj*3n{dK*-CwnhA3F&)=V3+0=_y#y9 z^_sUF7H|y}B5TZ^Fbd<`_Gip}#lj~nf5?i~d6u$If3U%O?V=1fvBFHa*=7r>$$o5R1;2s-_^p!v!_nG8SgvB_|Cz?y= LN~&M5Neur0lU1W; literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/bus_intf.class b/target/scala-2.12/classes/lsu/bus_intf.class new file mode 100644 index 0000000000000000000000000000000000000000..60fd67367f16c7a051357c53e751627854b4cd4f GIT binary patch literal 782 zcmZuvZBNrs6n;*-tt*tl7=lAV2g87gR1!#(8BNE)XhvW(kPxGIw_Zj`*P8CufWN>$ z;|Kk~2S4}&{87f!A*j(NH_tuiKIiQ@{r=Ic+#wcEZ=S3^_%ba}3QioyvnZ>u=rl z>Pc@?)223QjvD!bzSb%_4a#*3*7N1VtX^3wic0a(hlR;iV}p!R$t>^H9jz|vmZ06W z$lX(oc_%~2^n@Q0CKq2de-G-a*blq4r2~E!ahE$D`BRsw0gGU4?=<$Cn^nSS^RL&M zg#t!Rj9|=yiJ>9BjT44F8HjV~y$F3pm{|NJ)>aaBlplo;2j%R4+)u7VO+w}Oq+O5B zq_@vGYELg4Y)9U?g$dk9>)a$1e;W&nX3W_+(ilj4_pG;n4q(%a`Q4Ox7@o3gdO? r)F70nR-!<`^|(G0!;6)Epn9k36dE(6hi#k7}f? literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/lsc_ctl$.class b/target/scala-2.12/classes/lsu/lsc_ctl$.class index 21ac31c6fda2cae609e582f05a424f1de4b7815d..ad18ccbdd36a8f1a0a6721f89b15d8f635aa5f9f 100644 GIT binary patch delta 107 zcmbOsH$!g2T`oqc$>+I6Cx7PB0J3Vi#U~qcdxBYkU>O^zydn=wK9R=?C^m=36|72p h@=qRXD9eY}l~H=~Bwk-uX$Ezm*c09gAQ{WI8vvO39vuJx delta 107 zcmbOsH$!g2T`oq+$>+I6Cx7PB0J3Vi#U~qcdxBYkU>O^zydn=wK9R=?C^m=36|72p h@=qRXD9eY}l~HQ)Bwk-uDF$_**c09gAQ{WI8vvGm9uNQk diff --git a/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class b/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class index 050f20981defc1c1c3e7a380baf2fab8a9a181c5..2a406ce11d85bf60f3f000ec63d24e50d859e79f 100644 GIT binary patch delta 19 Zcmcb^dWUs`JrkqUWCx}IAUToA8vs4W1%Lnm delta 19 Zcmcb^dWUs`JrkqkWCx}IAUToA8vs4G1%3bk diff --git a/target/scala-2.12/classes/lsu/lsu$$anon$1.class b/target/scala-2.12/classes/lsu/lsu$$anon$1.class new file mode 100644 index 0000000000000000000000000000000000000000..74ce089a0ec74b5c2bf7e0319ba071f891fbde1c GIT binary patch literal 7477 zcma)B33yyp75?ue?PFeFlQdgb8cL^ak}lH)%aT%{8w65{q%9PX;brC}dGuvwoTZD1 zh=_;?A|iq;;=Z#)CRL(P6a`Tc5m9hoQE|r&QRKh(<;_f9?)cg7%ba`9Isdumo_p`P z=iNT`^8F70I7X}%X!P>MIR9cXJDo|#))){14as3Q?|AFtn~Ld_=NPCHh*D`)K52Wl zfH46wFkN76puF`!)^n3?VRL3A>w3^Rda@&7Pgl8#qE>;s3@NFa=sPV1c#( znYEL9?I9<&DU=7ifRh9hVZf7PLdjJ0`;<0<#jOj zU@kL4GdnZqxT(UhfjJD{WS)SP^!6q)`(6EIa9D?QCgo$CPxHj_Ki3rasDMZXaFjBQ%sUYX`Ow* z6=*Lz%5EY#Y^T$Xm#4UmrW4dm40^@?YSw6yEN<#VCycHO@EH z5_rB(`jN=l`=#@Z!Td*Zb}}(I$fcAX^DW7Dd7^!=DZ6&E;O=8km2A+>CG1p+Ycf-rV3(UV!~R^^&%5a% zg5_c;c7mIgGMPgr7&1iU#LEGxM7Reiwj|EXg(8rTfU`CWjjOglgNrNrKg%7QTBe76IUp-YWkFA9c93|yDr^@BQ zwXg_BOZhod<=iZkFGftt&*Kz1e)ajaumnq`>@`!d@&sF0hE6HJh=;7o_etm2LKnKF zQqsb5KMIb86@F{T!b-p8T3F?`80+c)s#9noj@8l#SE#)zx|Kb_@GaL0CT|wGtK>GZ zum)?TLAmLwaQ-RmoXn}12=-6K%rSVCG_%jbvA+8UEF9oeoIKh{`!9tJU zdZUF6e(OyZPV`%Ewy@D}y~V;wKK88^PWD@Gvv7(peY?P#DibKs*U0OAYzwIrYhF&@2_gXmJ$KEC|eS@2J3mbX% zJA-}Q)3uxYSf*HT7~_s0&DFTt4ZNS1*Y+J-cJ*!L-MFZH*lOr=0Y8WjMezZAn4|P_ zU6Rc7>#N+Y0o0TMwDnPZ%%rW43(W5<4?S6x^RaLTK53#JpJL(&Ce)kG7Uk7{7q@L0 z>NAy-_e60w?iH9_76$jdswI@pXQF7peY|SyY}PwyVGL)O~_&hg!D9IRjfR}NnKf%K$9>hZ-C1x4}Uo!FV6bW;Tfv=c& zWQv5@#lTlhJSHVgffL(2H=A`*4A|FsU6;KM*eV>4NAV4OQ(#6_GBWTj6HnqHlOj%P z(iE7B41CAL({iNNU~<)2$iVk#uCISrV$-hv#LiPrRrBq&@GQP>!oUxhmpgm?0Q|_r zGx)J?!DK3mDGz@dMGJmbHLYMx4g8{dS^-;ueig+p@tnY7j#Qp_pfS17qy9Yn#-#pl z1q4&~qN<(EtJukmAdMj7)niz5S0Zl_RukyBrY4!ez8`6-lPJ!5K8mvPQIvI$qO5upWr3q8>k@uA zOB)fa<9IAE%Ki21v&>L>EHV^jiJ>S93`JR9D9YkOQI-~pvanE;Wrdeqy;ZSLIbwL;8|L57X~!oR2bZ>1uxgG^I#as7Q6;oo`CSd$cMr6r-CQ)z-xIxjzK|VWPjMmf|^E( zG;*vq1_#4N7EU!n@NwE0ToML%Xu-#8!Iy@?i?!erv~FJ(2FJAE9xeFtFnEa;yg>`T zA`D)t1)rz|Ul|53(}Fi@!B>UBom%io+Gt-L26t(}Cu_migu&ff@F`liuMLBjYr&he z2j%)Oc*Ruk#6h`^+jNW8gB!v|R!%iS@K){IZw!N1X~EmHBi|GTuhxQ3)q-yhgV$)m zr{NY&db%|XUaJM4uATGkVemRF_zt|!PfPW)VX|aF-TB?4_{bPOaR{GgYjhN)F?`l% zjbZ#SzEHyU?r}W0=McVF!r5#-%;uL%*u~}}Y(84Txokeh=GRJ)=AIbGlk9yvu=3Pl zJXykpRC=21@0MV*`OKc>WBB1A{G^0bt$_z?35IJ4F0Li;e8JC0@#`jQ49}0@k7M{t z;34Pv*Ag<+d14eVj^icz`R_6OH;_MdScnqx%7&;n#>MnKhXhG z1UD;zIBHBBUA3yQ5^k-G)>La@Zoju&N?*rkTkyb{n8B8OJDthL#s((8Mi$gfa50PZ zLNl&FD{ey@N@&O9n1kmqPt3r4!LJc<5f+Mr=n%JKv3LkE@hp~z7qB$KXWhsWbVfF! zD>8uY$dy?Lv$K|80#Q0{@wb7_&LV9gZ6$3dolQEIbRH=)3jfU#EBIT_ml}wb zY(;2k73p0<@Y91iNbp(m7XD`p2Gn||EJg&MKG|hm$Cpj?t2;+9{^arg Y6MW+34-0g4p9sFEvdj8Sh&X-5D=B80lK=n! literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/lsu.class b/target/scala-2.12/classes/lsu/lsu.class new file mode 100644 index 0000000000000000000000000000000000000000..c8461bf903aa68e0c71a48d454d775317850fdbc GIT binary patch literal 914395 zcmcG%d0-q#bwA!cJ(o03qmk_OvG#gbUfFB!+Lkmuw(Pa{7#+4{%aSe0_c0zxBYA9H z*5P9@&W6B#3E{r)E8O9}!wmrf3*o*Ygb+f20AB)xFAyN#cXZcum&#iG^4sqp_IzH| zt5>h8K2_EI)ZO*)pWgQ&%d&DyKWVe7Oxv^5ha%^j*uhLh#I9Hx7}O0x+oM&`kiSZQdssh^Vj%cB#;*}3V`PTPtNUY#w?*fk%H+f|Ppwj*nH*;m^R z<(J#B$awq3{0h50vLtp9oanG^$Ghy6v1+F^+OV>r-F9wmv)49kxAV@ry1Epm-xo~Z zQAytuOuxI5-WyEcSxG+{Oy5;WF9g%?sicnv)9g+bVuA#2Wwh!6WRW_=Ju0Hv?-(r+dEF;0Ihr8j!%>&Skb(>FU2r|nKo&u^`& ztvc-38}qTlYx4~kQ#??0>Gr5|!nRX&k!@8=s>YpsOFkBf-9zP?XaE};Zo>4(2Gd(A z={3=SzFSGZC78a|Pp_-mEa~eyF6J9nQwKMsotQIa*VWXmwa?exQdgBEzc+T&wH0r% zW6^b04aKEZbybI>X)bq?i13yRCSuq_2u4V~>g0H#ImHVl~CqrZw@%)!54X z#Oa+;`@lxKc<_$CrnWk}Ye~{^*32~I58a-2YWf@OzFQ+T7wfM~tloLwl32@4#kOp@ zzh~2)i32gGZhh*aeY$1%Xnfbv1MT*nB~`~e_u0{&Lj9(_TW*eHzOyzzup#ZN+uvXx zUgzB2b=UHyGh1i&$5*X5cq-e!AMMn}BK>!5t7_TbZXb4PipzVB$DGYQOAevknf7hb zwfUPiSI0`L))(#8^PTaQ{DxKA&zB!qTW_zZa&|__b;VxW>A!bVy}h#9X|K=a^T#80 zzPgy-d)giCzkAcsEjMqUdu(iF-Nfp;y4a4pmbclteJCF8UG0wVU%SKJvU1R_cDk0^ z9og}t*B>+5bo1Ra{q>uU-fnM0{gbHQx-V8&H#f1mwW@Xp+(8qz5Z^)lcD8F9px%zU zSZCw0wf5a9=Kx%6Shaol_>sn=$goSLYNeMLY}++R<7OA^sRM~_^KH=WE@)y_#hkM-)=Ke*}G?fLub5}i=h&>o3IyOv(GPu+d#zGWT9 zYTILxWNaz%BvKvo>RYz@XnQ^%Z>XtSai}d8b#ATOP>i(BUbuey(Q#UM?x^B+ICoX$ z?GxGIlSk_6E;>~)$E~`$HX4bn-dI<6sKbt)TsF2m(w47tTI()0oN_1b%dY17)_e7B z@aijPHyy+JZld~Hc4K`fRegK6tik$*y!u9~S{hc~bN;TXs*Tak$h0%r)zZ*VI}>ZE zN;IEr9zGPG9o=$s>ug;^Rk_g{mxj1Ivgi8kd$*iv9zA|!b#h`w>(u13rB}LdiB&mH zHMgTbo^RWHB6}A7xUy;0%Ckq;5AT^cwri%pZ_^#)EAFnUi`}&30L|ZZ(BPbKhwtkf zK03J~H&se+x(p{<#>;E-b#?n%Xo0TVV%L=Rr?2g^|8qnJC?;_b546(zS-Gd-E{}{`{2fvbu9cYzIe0`{lxK~_Qqp2b~WF7dh5Af>>oJ2ZSKDK?DFP# zByuUgv3O^3P2}3Tm34Io*ExyfceS#;$DqC9Z8Nd04I7$H=FaWkcP&1-YUf$%kCsDT zf8?vVKZx(+@!{p^6U{U2XRht8A>PG>cL%Xv)&HyS9^7-?9i@Cw`BiOHzO)Savzq&L z!z7Q(JvXUwAwFlXEw4GzJX?;___a*VkRScZ51Jp_YR_z+*?)c2-lmnUO{lJs;lc8ZjNkgTUpms+)|y0mDcy>lVn%wyY6gHpJ|?>d9%r1&*J2-a}4Lr zM1K$L*>W;BxxfC}ku;7=n;MsuJTB#Z-IvEtxHI={gFTZgx1K$T{vSH-&j+q&{pK@w zpWTx^b$Qdx+i^avTkefp-Qel$;OXlZE~igWe{GfY*gebh?JdLQ^*NkBxUS;*Qn#uq zdQ1Gk^1*!m!jkHZEmfzs4bbbjUQXlEeQNt;XZBj__{rw+LcH-ZoM@SA zk6+AhKGkxzE4}(C&g)WpA1p6M-HG<=x3`WTZ#_F%4||$c)(pfZwcQh^nrEC&9#5JtBjama ztoPdb+Ah0}+j+X>%6&KQ+B?2t>-qckL7hYV-v^g*UAoeBy?yz_in|+}9bA6sLeJRc zv6Zc3`|pN}5z?#Pw7uz6^YHO4n?}=J_A<72eCO;j9V*_kbLhg&o7U!wiMqtxlJeU2h;!R`eI48HY22`RO)gS%fPWjD znvFRAXup^3--Py$57kC^f8B)kojS}%Ueq31x?xQ!VFD#}BpC zoZ40@Y=h-JtLq|lRhza?9@{!u=5{RMcC5p892~Ege!}sSe5h-qaa%vTr}yT%NCWQ+ zcMncpcQ4nTK>lC9u)JYDuO{*_Th`O~t}ERqc9rg1+kJV{DZ73iuaK7wJWnnh-F&Kf zu6@n5-J9(s&4(jfPPCpa$9G)@toPQI#@5<1&69Ky zLqoUhoGLBD{a{V@(g9p2H{Y^ryzBZBpSRmKuii0&>(X-J`KqJo)9xhC(-61YbV`PfpA=9Ks=-^th07(ZTH9J;C~R9d z`6Z`{Ll=sprN*|&$+5Yrm=f+^1|Fy!nzIZFRYrd*4kEF^lhuoyJ>HnzBDv; z;oR^vcHKI>eODs(dqrhZ(`sAQToKETcf-i8$yX zJ2QT(@3AdlOI`}{FRVD^Yu;~LHKOSyg?yV-o!!p9`EtlN3a`w}pl`d`H&3LVmbgu0 zV{u|~qOm1mb=g*=Jc*s$?US-?j(CBwmGtm5Z4h3$w-1!Z?lS%v@o*c)2igc^C^7rnRJVWlBnu*5KUCcmbPSnxGDo zgu>+D+(==l#ZLz>eY$j!%PBW$QlgtF${(8&zF)a}DG`olA`g^5WXjoC@`4k`mk9h@R@sytMJyE3!=Jk+e?NiDP7SG_5qs#ZkQ ztq(30zVfoLvbT_+_L9(Y;j1s#)VW(rgnKL0<`p7*xU> z)WTl!)>vN+2_04o=+Ods13k)8_Gm%AfgWX{9`-uc%ZswF80>XF4>eP5dj|^nj*h;< zUL5_3)ZL5Tb6#Ix{&=CI^WeZd3RO_C@u)i%%;H0(=a zn53ZL8q#hX$nPoa?(OctAyBedTS_uzWeZ(B9i7M60Z)w+TG)Rs=E+o1Mb2vZ*+Mwq z)$(1=Pg1qwLAvd5S9eDtzqbu1=>WF1+Dkarg*#$E5zk!M*|NyxsZ3 z-2+H*p6B`Y_Rju(?we*q8uscuy{sY4HKd^@^U7{Dq-`^#;aWR6IkVx#AAfK%GGmhaB@58%Wd=a3=nq-Fml+;3FH!7L8^KHI?kV)2sB{aDB07paRqJU`5;l*< z)l2E^>BiRj?dosu=_qt#|5p@bLGwN7AIJ~jN+nJAOVLW~wcPJEN~$#6A2>>-j_?Ns zT{)O<-_HqQ?qieu1Zp8x?~4_yRg%c_1Dk^ie!qz%E#$^yo|N-g&e{Q%iz(>~DXbXJ zsvhG7Gvlkfb{|H5dwliHSG*dVf+H`Pbc>?3ur_HGnv zNNCHWw{&TT*JUiTHO|7NxNx+$uLD;NF6U1T)|2Id^#*ze^4+v>u;Ugq=YbU3fv}uL&6v26}hz?k6W?4)b;5;qLC^I52=k4&-~f4i-+dX<}PA z7Z>WFGWK9l#3(^fJQxyrSs?uFU*}Q zjaX{whM4fPVgwNz{Yb6D!g;%`-m+{QyXZ)HVi@dBdmCB9;aa5?r@QICxrqVnsm6qjms*Jf zy&Z?UI~(!w9KEWbF4nTo-d}|`#@)CI&`tYvX=ZM0wlFj~Jzbbi+Q{7WRB^gEUc#^@ z^~Ma3*~!4j%2C z+lTFAII~Iux1C#$hDP9Z&u!^5_%wI9U=>2GwuAas9N8Ydw!eS5%V1{wC~E z(^SSSC+H!HUge19Pkh{rFd#(nIE>}d!&n&q!HC{?(xxa-prxqj*+Del4sKxc>`)Xd zX-|jkprU67(R@3!F%ymbAQi3^h2q53qP51T?=&lIBhrf@-Afq}LeT&%`Q1&lHlO4HMm zI7JI1BT4(Auq{;fY$2L&YlqjkvB@G@oK;=)S79rt=2=0sWM1Q1@EWEjFu)`yJ(?mk z6hQWd3ZU#4Kxim{jN_Q^NO5KsqoF}xpR3tIRo@mugDqs;O~wvP+Aq>Gumie)v5k?a*9 zIKPH0@o2a-grWVp!lmL^8AH?fXNKXV{lRe6r082RaxaT43i?X2U%*JPEK(&@pu!@` zGWd$@2oWkM{L(;G$R%Ekh-B(jXl{4dk7i|ARR((R+y4CG9^n)39Jhw z`#oo*MV4q0q!u>oo0^RZQ%HNhm#)SXlD$d^8Vca32fcJFgdk`rfTMmBQEPT=t{{I5 z8JoO}D>_~z{Xnx-;fibIii?C;;oB-V7cP`>f4Mx3*R+FV?#G(B3X`ay!8N1{|G}k< zf4Gy~?&q3`3b$M%w_GGks5>e=qAWw58jsuxj|dtHAX(J1hmHK5R$+x!u8~%*Mk|v2 z5jN7wMWU?GcHh$Y)a+I6p@^;3Utt&(obP`QX;e+-ibJ#IOQmEa9yUPvo<9T)1~kUy zDvTp&D1h7vj!CXUD}sgs$c|8f3UP8q;^dGEp#l|}P?n(vjV8GYO$ZtaXf(-HXhP6X z00%$3$W13B_*g^8%?ej?My}*Eu8{1Hjgc!k9P&^N6*f@Td^fk^5C;p8?A1WfPymN` z8PR8Wat?1%f>&_K2tMu*GFD;6RwFaEYRn+nuieOutr{~(_6r!9u~lOR$$kMNGq!5X zAlWZqWX4vF86^7!jLg`ILmld+3JWO9(B&EnwpLg`&`>~Q!PW{32+l9C4TrjxcdpVE zdG!S^iz0aU9rTlwyoM1pSiv#om9cb%E~_F3wDJ`;Y%{W9o5lu`{R)k2*oH&Cl(;xG zK35no&){{^=tOCl>OQR1UEv88GWf3XWLt$N1Pui=o@}e|grK1Sl0nv8x`IU)@eVrF zy%pYUGxBDe#v79T?lJOao5mZG{Q^ebY(sMJ{QzDXBqJ9z|0*ORz4;AnMN$MCM6y>M zK|=v#L8w55AgxA%v}yz)*{{J!kX9V)Pz@CtP?o_ZjRvh18W1!T&}h(Fp#ecd0UX~NcP5x;QTtbIH!#+RZcR`G$;y+MyAOWWRusP&<$#e04NGzLku8BHV7$^^F;+wL_y8 z$$kMNwRRv|f@=%OegPwqc4$N**)L!u(hg)rXgF~n`?6MPg+rum7#)p6J1QI^XefZJ zFn21}{%x)H3Ym5wTxy8+A!X8m+xnJfOsMkXeTYqEkR9fWUi9E!bbF|*>>)PUL-K@u zzywtWv8jxkwD76Va53bKDu&opESI##^k68}S6~{2}6#12I1T~Zq z#3m!ip~@u>+W4(*0~M4F#3mcaq3Y7aaDgvR(Z(Nj8>pacAU4@RS_K+2o^&F*5!6sd z5Sxr3ox+`u395{lYZOYZIFI#KYc@#1w?WuYZwpc=;QVybsnv}H2uIo`Bgm=BNT7|S zx{UwcbPdwF=l?s zd`uq4PdfN_=WxXVW|6k3Vx3tOh*lMwnMG0PT0i7EK3&9zp+}O=fL?ikZdAflxlT6< zNUO@tbfXY-75>E@AB~^H8xaTpyc}vX=X+ZzVMDbPln$2(@QgA|Wso#0X#&r?swz(m z;X;Ie-wvA$5RL-ZCX+hhC?f5*p0KG55suuDzgW_ry|8k9Po}uEGGrzkMWVwF2M9-* zrpl2*eA_Tmp60zU>CEa@0*s^BwaJRkIEqm#Z_SM3fHgInYUZXV9sKigxB&sak-n*F zoo^JLR#lt%MgizhJ(S>=A#A9JV$k6-0fJGcsSJ`NTqeLEicy=&=nSIJwDQf&APPo@ z>j{vBGEMd9WT61Hs>e(g3Q33S2~dMFP4(#1ppdkx$4m{1M~CYP@PIN+_2@jHz_hBz z%mWHVhw7mOzYJkRJrr>cmkIEIGEHT0sCkBuOqcLBIm=-P=XJWF068dPZ8D^jg96pc zVKX@>G#z$0Kn}_@)uWSx!quuCGdU@>rW~K{;rNi|E=t7yMdUU!_s9M!yrV9n5!}SDcL7Ap{bXriXTGeBw1x2UB z^#pi8nWlPl9#CXj)nn!X#iB#?P=a5Eu%R9bM~BM`OGc{VbC9OWassKAEplzzEHEH$h#R3GO zAhxL(azFy7ljGxMy7r1%x|INBD6(y`qEm*#*Q%Xn%22>MG%S?hmmzGZhl17NG6Bj^ zrm2ih846&ldd!resC2lV0A(oCR1Z=hTqeK|idvh>==`A2wDQf&4+=(y>j{v9GEMd1 z;D^fum_b2lQyCoUaG3xPC@yU(qw|1b&#FCU9#FJ7R1YQiWe6MUp%`buvGlrCu9W!Gn`W$X~fH9P5 z@|PGRb@L59*R97BC`zsBHnWH#&*8cQETT+P-AI%gshb{4<*M~)0tKj5)n;N**g0Hv zfLP|3be2NU^-?uHeatQAXNIF%P=OV_`Weq}Mz&ca94DwUM#5#Akv&@d{OogdAlw#K zRJM$i%QkD2;{;X4NV#mYMlViKWsLO7Hf!|a1XadJuWU2XD-iqV1XadJrEIfCB~DOf zj8w`tBQ?VHRCvRgrg77FlWnf>hOwaxg^X{S7ZjndP9&ofnhSwYbJiSc&QkC=vO z!Ao^(0nV9&&smBuhdl^z&K!Ksaws|Ef$D?T=+*+%Ge@Aa{6utcT?#~?In&f{NTsmX z0iKxy&RL2thsy+bMwzC1kU$lR%eM4R-AsUF=5TYCqRZi`10Qu2hX3Jf4hx zKr<5vIcLow=d2!b<^-Q%=8$ui!p0!)-gtjmh<;qJIlwG)lsQX*JbLcork>Z=^lRlM?IPr6*=gP_G_jGdsT2VPeSLspZY#^%4*i;4=C6fzd zlga3hG#4ny?9XGSeATrI^R0jDGs)wS{{@|M<(^-l$hsy*AV-7-RDdrq5 zg9)l0Ghy@~be0lS8S~OZG3RhS0m4wGsSl71;W7bwn1jt(iYYWpF>z?~^Fhtg1q6Dy9=85O&TIHk8rB&e=fNnX##izEDu8+4s#HcFt0iIn>>O zurp_x>Om^h1}=8^1~S&K8$vBrIbxF`q(Hdx!0KTRJZCA+9ITvgqGBg?LjlrI2~*`d zX(;@x95$1NLd|uRmXA#EjYKjwq*sr6%9NQ)6mJfTDoJ&Dc~1>BR3(c#D?A)hX~5o6#CW5o^B#%+c#C1*=0H5QtuLrpW{3QMgQi zWaj8~mIBn_G69mAqt{sqR)@<3_(Yi|-*i4v#9H-%nNJj;4%ZVPjyZarr2uufOn^A% z=yjHY)!{OjpnNm0Kzj5#8;D*rHuQlWz0OjCUynI@ouyE8$Tvz*We}U{(RmPvQ)daA z%IG`@#H6!?O=WZ*P#jwMX66Bfo5Sr1@PIN+_2@jHn6s(}v8jyCgFvu3OW0IqN79kq=Ku*k2yh=F;c)wUm>$M2yi6x!_yR$=3s6fLGE+y76uW^)F=JC#YpaM$PaCUx z%+%4t!Y(DKGG^-NPaeCJpvsu3qX&RpN>F7G8`?vW-B7;;LcK0wQyE+(!euJEiE9q^ zx)iewmkE%=9ME<3fG#Ka?J);*U5dk06{9JY1!uq`L3ddy1*MP_R~0@C|Xe61bF zm-xe#2gqTL<+^$-mlIUwW^%~G!}KNeX^v|0)n>d(uROpQb2Qi0qq&@*DmOERqO)4d z$CL3ot@1!T*EPp;T|J)534Z0~c&372 z%(>V7zgHyV4SM|n&Y9!9uKw&WC#d?(oTDJFR=Isr36*ROd1N_hU*EC#vIvo^~f$K`1P2dId=7DjyXY< zLADzPO^@ull%UEWHkHxI5qP}VC2T6AlOqt>b+0cNPEfv?R}_lfhUy6fc3pE| z*VO~NoZ#1E4(z&mV3!kA88bQf0~hqZhCguQ#n~Y|{vsKFyzVqIMHw@*MvwTql%UEW zHVhmEb*ts;Li_-I{K;@vhj7|0Ggb74|U2_E3)t@@%1m&A~HK7P^ zz5fc<$mH};sc^11Hk*vUP;X~ol`)5fT|F$!34Z z-OyWlpx6xriW!^AAW4?+Tfq`B^iNGm#^0bj5TKU%!DW}?!J#=s399L4YEkGnTqZyz zb6nV^FmSj`VC^wKqU=&!ctxm<{G~MfwhXU;@6|1$y7C;csq6HWi9*7vjG1Vy7~MId zR~6tCg@p}O>7igZ5DI2&DubNTKkv8zAi%n8Z?^VY^;Vse09 zU!`xmlqQn#f7I&^kjfl7cJkTv~E^ zRGAZ086!(_dQ_PcR2kz6lGCHgoS@1WS(4ME%ABCe7*~s2Gj2fxdUsd0Aj~(8Sxa-$ zI;<57#FlgB*m91-$Nbf6J|d33SnWMXk=U#oLrvdxbI>_Qk>lW`-~?61OcM$#D+dCn z^Cc5FbYWwtsf?NVL-FQt8B9=R%>1E9GQXTjJrL}Gdvsf;AVgq#_h>d{u8Tp;Ak*i;626ZS1YD)TePIX&de34VLbA?F-LmHDMH>`(cUS>ljZ zbKrSnRyTO72cdJ6plUW#Ne@EjC_$AmGe!?W=O{syF*7EM4}MPRO$v~Mg4Cua>Exg= zv#QEW4n5?YqXbpPyy#E>IW*9epvssR9X-07qXbpPyy8%-I8;v{keo9Il5=_>nG^ha z%z@+_g@wcQ1gKz+8RztvF(;^c%v7N8Z@8WS70j{WoE{tI1XYij2Nd!R*Aw7@`RU)B z9s}kCRgakm6xt2f6X1dQx!;@~>*WMhkC_J)whh%2i0S6cG2NUV)8z!e9`h5tIsFM< zPEcjcOM)KL%>`n*j1BXY!nWb|1bASM>E`s9E+;78%sik7ZMdEQ56t1)9EER#56Mp_ z6IvjGRaDJpX6OOkTp*y!*wiaH_+f7YD}*_qo6`fjoZ$Or4(R6efG#JfGPt)GeA5HE zxj;adv8fC$0-^Q<0=hYKKsTp9s>=z=H)M&a9vu8|J(!@%n3F9Y`-dLU%~66XV_rA(h;A+r(PeCC zr5@4EQG#EOIij1Rh%OA{6Y`bYnJ;U-5_ou*)lD@cU-*NBc>49=*yPX!Jgdh02v#!j z4c#6pE3Xin?CGmaAk3R1Y$~I3Dey6gocY1t97S=R;+1kTp?x)xbCi>)WvUPv5+ZLP zzMC`0cXN7tmlISyX8KU5He64DKIS-XPLJbqf?tn0j+>((ZK$3=)Rr?1eV|8ebAhNW z;}o7Rlf|>d#!5wevN^h;Ya^aYX%8al0vV0?UeyNweB+&{0*OB){+P0o34HG&I(x1> zgN*6M096zI+lhG2FKkjjHjEdbf-CF+fsAa~mqoEnEze zb;)|FX$k&iV-P>WJX$J@($V5eH*}o{bbx>2yo2Y%6IC#;Ku`*uZ-^^9v2hYalhD%L2hYCaIiW3v1u^Ako80nzp+ryTP z+K{|0*+BN!BK^q4if?%HyJ5aV_&30?8dkKrQqlYZkX)a;Uf&otcWb3*!-m3AWsZ1_??`r1<9B02r!SQ* z;iGtXIA3}8Djp>_gipUG_(2(}wo20R$R{M{d{u1eelbN13+3|!#k1-I)-eeS^h(zp zMB~$!2B)#tO4zcvd_EH=xJpFb0Wp3UyK(x`ba7&|;2^ zxFccny%cQzkTf6pn4Z2wANed!;Cq<(=VaTudqEzB8>0q(;Jv^HD` zwyM3-DrJ%>bOVWdQmYP<7m{PtUi=Pn?a<`JNO^Q_nw~r@j9#{_3zc@X)0NatWjQ}{ zbz-Qmgx^%Hq!~s^=^OGiPjD9DUwiQX>6uw%J|4D#`|8Z}5Prh+Vu5PI#PL#j^zzW` z^jKkPa*XE$UnTg7vY+5bx+!4{d63asgq=2P=(PXmZG+_H}zPB=T3vt4br|kl^^|(jLRAo*Z zYE^w;$fNllp*awzwo^AGX7JC=!zG-1UWZ7taeNOM#@AqSq3W~_faDXCe@TP)B%Xwo z?k~{AKdq~DP$Q2Lrr?-7MaJZ*N?n{|^+m1>?D4z_;?_kE0X*aShLm~p@;F>Z~78hn87>oo6rGoHE8rx8+U?r$+}F+ zpF<6mJodm+q|BZ(j3(t5~SLjwHgUnvH{*282yU!ypCv5j;V)y5K zH9~gr3+(Lf%6Wz*hb%v6{W)3wB`?dBLYm9J7SsQU7XjQ4ctx~CH(DZdkF)-Q%>9mU ziO^h0GxT3#=nqI^HdIDSbU=M&fUr=RO+DUv0-CC_DB?zakEx;dRz=uWmBZ{|1vD0B zkED`g4_W_@-oB6BzS<|sLAZn>CS!Q4jwr-sO0nA=`58GN$!6f(G)x$UQiEv^xZx8nKe*!zw2 zuYh+Hc*Np@0qEDe7K)V&f6pIvGxT6oVvW{g!!d4PXf5 z=;ZXUctk-mE22I~cac7gRmLHC07B0=|q^U9K3EB(R%LVNN z>lK2!!Fr{j9otO~<*yZV46N4)Isw+}1)T!x4T8>q^*4gf zg7rp0gJ8W$&@fnU7Bm9ZTLhg0>#c&$gY`B+V_>~q&;(fT5HtnWI|WUH^)5lPV7*(= zC9vKj=n7cx74!gDe=F!3Snm^b9jx~YdJwD+2zne?9~AU>us$T{A+SCy=!sx`M9`DK z`lz5MgY_{%PX+7m1U((Bj|+MxSf3E|Y_L8l=(%A1y`blV^(jFw1nbj+UJTa5f?f*N zX9T?*tj`L1C0PF;=v82SPS9(>`n;gmf%OGJZvg9yg5C($mjt~TtS<|CD_CC<^meem zD(IbHeNE82!TP$O_k#5eLGJ_Wn}R+7*0%(G2&``l`UqIx5%e*z{!!4!!TPSCPlEMN zf<6V-_XIr*);|mSELh(c^f|EpMbH<(`hlP?f%UI~z5><{1$_;ye-rc#uzn=yTVVZI z(09Q4iJQB8AA$7?K|cZOKLq_0tX~THIat3E z^b4?lE$EkE{imQ`gY_FhzX9w22>LBpzZLX*uzn}#4`BUX(4WBiFGkfCSbq={0qc)~ zqG0_=P#moP7DQ2fLDgW}f&lD@pfuQypbXeiLG@tA1T6(SE@&Cp2|+8sP71mi>?%R4 z!LAmx2JDoe+rS1vYr(D&)ChK3(0Z_I1#JL3Bj`@B>jZ5AyI#;1u$KsG279TXEZ8>* z%7ML1&^EA_3)&9$3PE>+y;9IFux}Q0FW9RD-4FI^L2Y2)BB%rGHG+17eXF3oVBaQa zAJ`3oy1`y6s0ZxZ1sw#tQBWV)>jVveyfm{&=CI^WeZ`)*EP5G>qO4v@N2EzS4qCBqhCxd{v_N1uC`;(u%`GKw@o;9;(f8k)?08ND5`NQ1+bY=c5%vH z-!4ws>)pjEd;PmOWv_=9r|k9d;*`B!UYxSm&yO_F2lD;<7s+2zT_k@=b&>of)kX4` zR2Ru#Qe7l}Np+F@B~`CqP3u+%{q3?X-?P8a)-}*CJipDvbJkNTrfpeF9mmy=Bfw(o zhKjr(1r%@STxWZG(4cAG<(g&oNv)=}l9hJr)!xuQ*#Ik@azp=m4oe4mop(e3`a1V? z_4YhM57S?fA4x@Bq}DG$xrtP-lK)%p+cz5s;%CujJT7RL-ySOl2KKVMl6YGUuV0wubG+WvVQq6ZFYvBAjQKX8jE>JbfMBZ$)jRflQv-qUOA(>s|JGcPJ*Z zdy3sXh5i##^#Xm)YXkPX$4t|N_3V)*4*3F$h^N@w)9n#sfqMJfdpZi;G?#8T9X)fE ztJ(#6uzw&waJWA}o&~C==^fzC0_-KtFm)D~;H2y`Y=P;BU3f6xzF(Sc)|Fczz~Zyl z!;4d1;O1$*8w=b#%~xLF<|(L5_X7*uJn5>7(a7s+2zT_k@= zb%B2E?#*`;26_vJ`#TEbykeV{G*o!RCC%4acuDiM)RJae z_eqJC{hl^%1iNLr&eQY)SFolnfVBHDAi3auA}bAO_a3IDtf#lYdjbFQW&RC&?_gJZ zA=`euz1s_xnXV*Ar!9{|#ZhQBWs3E&nrgs}4B+P! zMwJcp4&=M(wn*q>T4|`Viduk-ror#)94O#59bP9@>NaiqG?al|)->XtN`;Z8p74|w zB;-KXfzG}{cjq2#X{UFaY`V*zXC=;=HveRd-Sr0R|5 zWE+NkgO_6_e@JJbclYjo>Qm*9sTW9d_u=mDXwh((+;*k5HpG$LjIP82FuKH8DOM?2`f6+fGw z!367o)kB%Lg4HXi0jz_9ZU^g-pmkvN3AzKUenA_-8W40BSce7Sr!9h2@KfYq9kGs5 z75FwYKLRALVim^lX(N1h5Fb4`W*w(|e3+9T?D6vXBcq~l!a7L`_(WnIJ^AA)@Hefn z_$li&<>HHNwSioG$`|v_SOv=46|UO*njGezwThH~pZB1RXBi&^8=f35mM2hS&>A9* zwy<;jQICn)5mXqqN~F*U)`+xo4_Kpuy1+Uo9kU;-vY-QCofp&#)&)U_z#5Yh{a}p? zItY)EN(tr2Te|h?E6aCjj|7GdFo%G*U`foegTh>^_7d%JiCK~BuQQqLwgMIY%O?o%a zPfMic&<}jnD0L}??=&n?<$OX=Av&Li3;BtO)C1M2$54TcD!>FG?HXU3Qxd7`)u}%t z)wEJYwvb}VS426HdR%qtFG#Iksd>Z+x$UJTQV&(9{uik)RqBdIRG`kctx^-ICsn8Z zii%Vk=@W}es7CsUiPTf8Q%?(fK2f?%x-^c`B|GU!s8}Pt`H1s3wT4C$)%j7(3C&>>+pq##e7Ps=PRjIe6-iC9D zsv5$_$F~LM+zkqbYil1X&dltD)H_n|tVUb!vaPYo!?zvyK2ha~`LJ~3{^-K4sgw#= zx3e-BY!2*v>OIvs()b)Q`29lLLL&7(d}^?9XcFID=fbZ%zbxq)txIJnk-|rlS5+FO_Z8FTv(;8K^$$44jkI3k)6s!fh7C_gW0}vVzJQNH zr@n|Ch_^UR{3t>q^<`{;thAhfbCfi{no4~o^)*7n_%wOy8${G+R$Kd0-@+GYy6{lK zKyBRb`T(ZBlln*MpYNi1e}H7$Po(e>#eCDl0H6-Y#+tB5-_Z2IZ~dUo*irQN~C_A`bo95CWQ|pH&y!E ztXyfKT%X`-@H1Ks@EPT$ehY*CCsMx%y|?k`&@;?-nkT=kPW?yfSGdNgEPp+tiyVA_ z7FW&xtg@D*enZ+w+9j#q(u<6NH;VlNv;a~ee5*aU2(C>1p1SqFuv^<8^+&R?BK0S# zHaI=0V1gbZtMz;1z~u1U7_P^Fk2TjR@4Qs<3u09eg*c>UQ&}VnBx~bPl}TkC%d!&m zA6l!I_dWYd)8*n=`2pVS0iRV~TbWR0oJbc+P2I)u!QtY8(rj@Azl%FLeKi3YWFLMs zHjrjp4{Zpn#a>ZVI5#=G7vH-aE6p@^PflK#o7x#r^Oo#DN~qufzJ9**WFWV9@I20N zT-D||*&NY7CqO+csfIdOijBsHrRf4xn!0;#Vu)6SX6&LoEU&k0z(=KPB=g{O z318&EKD`+`+AH9tagVO9f>m$}KI2~=mtABG-xORQY_h>OFA3mQxUCw?H!Ny{qXj(y zx8ntrKj7hoDgow;H&Bs6O}Tm7=pwg`(v>M>$araD7Wd+|;!H_s zhTVJzY^X+-ZA4#ik>!m|db=_<-fjnX!KUieKf`9Qx7yo?kodlOrlKa@lmNV_iOcxg z)(%70J^~X|Z@ZAIw$H&<&$Hs(3|@`W`xuof)dem#q!qSTr#=ICHvxW!)0&b1T=|a4 z1iFVVO^aZc#r^xMVOQ!ykh+@MO08)}rgdaeTk8?8fYf7C+bMM~rgmjg+v_cdQvW=) zlTr_0YELG$v)+nQ>Jw7;QfeQj_GeP})>|=3{mWFIQjcQlu}msoZ^bF~DX9)hJ%y>K zGpUYxD}kxjDXFbU7r5x*n0PphU5N~tobI!&gN7COe@X|rzk?AN#ho1RDaeabA3g8YuG4SHQfUmPB;Hh{QgP<^88mA9H06ZP9li+Fa46t7%#h!)By-)4A z+45M^5nS?z6Yw0oZMZ}b;CZtv)} z5B3|yhra>)ZGzrJx!i|u0sGyOh8N;7KK&5j9a0fqQ@Z^<->0(b+&gqyAzyl_#|2V zdtCes3JLf$#JL|HhR=Zg_hJyQFKhfEyNq9sC;@z)oO>9)0QSS8^Chr9FX$`O4sU>G z9su|njqk(ob$XY&>(S$?H(&06Z&DY03+yjR_1^*etAf4@_BRCKbNUCQ=e`g2KS~;2 zPF5N55-fwaI6dQuf2$Oqwr(wGUYz=lG1s*{r4*P3H%i7?}=%=7UXZn6UFHR z5&*vt%l~0peZdb^{QutXya{^;{E9l^*XW^P*Ga%{(4ouI#i_p1NPc>{h`aEv4F*O3 z(gW|S=+*=;KAOhoX6ah1=_r<-Dh+dK+=PA$zoRRJ-`iHMvRt>}{M+em?g111rHg?Z zJMkE=X#P-*efCH6nAX-&a-#KHcN zpd{Eo6I2cMF9iYE|0yU9_HPAc!2YA4dWcwpmO>;ZXcvlNX>ePG)US8h%^ei6Yrb`uR_fxUIS`2L*x$0z>AD1 z9&IoJH7$~b_nBvS7p}=wW1Oc5kvm1R6(UW7c0eR6XeXAY&yqpSJyQB!h{)AT&HWJB zE=p|>*(s<4BKHc~4UxQ{y%6aTv=1VC1a)KJPukK0k#0#l2$4gAaJNp56!DF5k5vK#MiwHIopT6cZOA zGA(EZB6EV~AaX?zM!;6k21d5z1lypot77Z{h{&Zx%{7Qzmx9+J^5=pcgvjFsJq{v& zDd_PKd9t8~a53_i9Dad5QG@S<4f2Im4F}m%87YCche zduXKQ@9~aSocJ_2aY3H}r%KR2fRh&Vd2qaiAEy-j2?wwXx>g7?^@xHQxbeo#=cQ9B*m(9ypsN?fc*~3;F>#uAm=+@hk zege+@lKWF|+6Da_oV|j60nUCwzXa!?pkIU2FX%Vm924|ga83&PJve6t{Q;aIL4N}0 z9HX=a&ILgcaHa%B!I=>h2S+AcIth-2~ioYzY3dT?a+q&I-` z7D>AkoVN?w1kSqzZ2{+ff||kkpr9-`9}|=V=M#dqf%7Rr+rjyapu55OoSGezL_3`sO+2RVSM2=`BK~u z(<2a-iI6@AQQ1M$=OHRPXnG8ytHsI$L~j)|1yPv?>1l`x+tafU-5|M_AbOXeD-ad7 zryqc*uswYZqQds{b%^d1y$2yGY)?N9qQds{;~^?+Pd@}vVSDch^ zhv);6_DYC8R?w>;`Zz(af#?$iy$+&J67&X$K1I+QA?mUH%@Fn2{#J;-P;%c6(U%B% zCq!Q<=-m)~wV?Mx^bLaE2hleP`T#`VD(FKHeTSfrK=i$WJ_gbE3;H-jKO*Rp5dAwr zpMt2z?1v%hF&kgVJCZt__KGyVkb6PWz68-POWChL)Z_TqAo^`d`vyd1*GPX0 zqCb$d??6;`jr4aR>hbw|5cT-{eTe>2^nL)*{}l8?2{Q-pd;CAo?S$y>(m%pGqx6p< z`dd-QaPU%-ZX*4&>h#ZX{f+)n6fwe^!fX8|y57gjghcw65Q|9GuOSu_gxBDqo8hVQ zP$KFlL&CVts<{gxFC*n;>>V&=!al1T{l!P*4_PGKXq& z5R*AnyA5KKlDi#ZGKXsKhS+6E+XXS1L$&upOy*GS{ScE~q_z!WvWwJqKumU#+T9S7 zU8Hs|#GWixFe?2tLER9Oc~#p3F_~Aj2O;)+$?b#Kiv$foOm>mlBM_5ar1luZWEZJD z0kPML-YJO5T&q2Ue>j)^I}5QlOYR`Vb&=|yI z{?$%EOy*zh6vRF$xziB)w4hmteOAyVh<#qr6^MOF&;t;YSyy`vV&9Uq>kyM!SNkBu zzAtHygV?_cdOXB_B*5CLR=h-4K_(qxQWJ_jvz4 zhvy$ww6gl{Bxq0f%q2%)kFL%f|f%3 zn}U`>{5yhHK>VKt-3)Qr%rdJXE}L0q4a9#Uxwk?5XM)y3{1<{6A^s~t>mmLdK^q|c zJ3)6s{11XQLHxf3ZGl8YP%|WCT4l13kZG04X}c1B3owz{77ic=&V$+siF9Urb*445 z0}?VHGZ=bMp~Qe{B6Cl5=3d+-6ZKO4{g9B^nrVZC%+^c?Bvwi8Zb+;Vv=Z7U4g^}K@UJeW^LvgBxGV`u0uj5R^~xS$i&J#4iYl4GLMIZOsvd9 zkdTR$d7>UZ-(4OXYfNOGgqJhn_$6mh05kLCs?1+yo&pJ(k(sAK;vsPfqw@J=Z8hdT z3le`RY0rU#Y?7Jh;j?qn#1}w9w#&?mAR*gj<|UALj+A&AB%Uwm6_AkaGV|AvkeQo# zH6&!_W?l;knYo$QLqcY5=5HYJMk)IyNW4YRTOjdvL2rY^y9B)h67LoCE=asz(0d^9 zAwho&iH{0;KP0?4{6R>3TGBoYiO&l9C?sTS%wS-Fo=H#_fPrHKa29+y^9h;-pM-?$ zpBa3(qjIqr&`o3>uFiahroq>xhJS#Bw+?(B60*H!z6c4~UNg9oD>K3Gjwdo-g@m_4 zd>s_!~%lLNb4gnZK*Is;O!l|75#4@MqOWd;|xVw%EnF;uw~*vmVA@+x0O1+PH$U z4*ufbiv{Dajf*I!MHHk#N&{<0&kuP+_l1StWosT3E`9jAciA288 znMN!Th|p<8B9Sk2NRde73!OG368S=B2Z=$sL@`a8s5s7@E zBS%CcU+AO}k;oT1CPXCig$@8=i9m#o`4EYGp#wZbB46mNWRb`hIuThU@`cVf7KwbJ zlZ!mSdqvVI_^~@@`Vm{6^VSI zBU(iwU+833k;oT1R#hbOg-%lyiF~1>P(>nN=mb=e5I8M#xM@NbJ47g>7oLm=W%R?7 z5uuEpcrqfC(HBofgfe>L$%s%!e>@ox%IJ|NBSIN{@?=CPqgS5H{?TGAG9jmhmSaz5 z|7bz>WcH7iWKU-QXi@fL_K%ijPiFsUVfJM9kCtXnX8&k$_GI>tmS<09|7cwnnUK>$ zOSC7mf3!$@GW$o%v?sHFv`~98`$tQ)C$oRFSbH-2N6WP*vwyT;doue+OSUJof3#MM zOvq`WW!sb4KU%mwnf;@s+mqQpTD(1({iEgEli5F7z&)A$qb1yv**{vuJ(>NZW!#h5 zKU%*L1G?#b*QE$E)i{?U@|$?P93>YmL0(X#Hz>>n-cp3MHy z((cLZAFb&k6LMN;dG}=Yj}~}OX8&l3_hj~u7I{x*|7e-_WcH61dQWEmXsP#P_Ky~O zPiFsUx%XuDkJfpS2{|paxgq#-I20WSlqm96m*+1F}JemEY&A^k{KiUpFnf;>;!IRlP z+7djO{i996li5Go7Cf2#qy0c+LQV^94W7*Y(dOXE>>q6pp3MHy2I0xL0P z;mPbDZ4;i%{?SI^$?P9(6`sug(HNS+##KLRtAo2xa9TA(WMWgiu!g5kgt{M+jx*A0d>Le}qt0{t-f1`A5jf zs{Mlz%E~`NC@cR6p{)EPgtGFF5X#CwLMSW$2%)U}BZRW@j}XerKSEAc?H`O#R{jw} zS@}l@W#u0sl$C#kP*(mCLRtAo2xa9TA(WMWgiu!g5puF>|6qi&@{bV8%0EIVEB^?g zto$Q{vht4*%E~`NC@cR6p{)EPgtGFFkdsyW2P2e~e}qt0{t-f1`9}z4Le}tT@+CLbfto$Q{vht4*%E~`NC@cR6p{)EPgtGFF5X!3m z2%)U}BZRW@kC2m9`v)VGm4Ad#R{jw}S@}l@W#u0sl$C#kP*(mCLRtAo2xa9TA(WMW zgq*C}KNz8`{3C?2@{bV8%0EIVEB^?gto$Q{vht4*%E~`NC@cR6p{)EPObB;T(y5N!hF?#ynncA|6qjq zs{eTZaMk|72=i6{@&4he{euzatN!Et!&UnSBga+y2P2eK|MC9es{Mlz=BxhW{liuJ z2P4c^{m1)Po=gtGFF?>};C|6qjq%0IsU$f^B<5#}rZ`2HiO z_76swul(ctkDS^+7&$q$e=tH>`N#JkIkkTOn z{euzatN!ErkDS^+7&$q$e=tH>^&j7Vg&#Iex{5$$K*PB<3ssc>l<${euzaEB|=^;3L?*^4OD@ zul(cvgHKHN^06l|U-`%TM^5b@j2u4ET=Y49#V3?|GW)0Y4?c%{N#ih{oGNcdm*oBD zM%!xL5cpH4_oA}@{&ZdHR(d-;*_Oc{;jCnhFm`3n%Jn89}p zW@l#cbt|!nNwxi0W3g*u41J;Zpz*C6PC@sr1}kDk@n76Z;=w%i^eH9$qkTPnHHm-m zn@RkOUrgd({9Y3O;@6V+7r&Lnzxbsj{>ASk@h^T7iGT6aNBoOlIO1RYmJ$ErcZ>KJ zzfZ)!_!T1l#g7f~FMeu>fAK>@{EMF%;$Qs85dY#QhWHmhFvP$3c_IGAj|=fHep-ls z@xwy=i=P$ZUp&6gvX{OWam1RzcFtOJh}-CVKK{ic_4pT0!sA~&y^eqJxHLU*-M2+WUQt z_xoD!_jUi5xAOp#qS)H-CFjhNb6TQEP68q#0wR(ng9!o2nO$-Q z5tkr2DTpLVB9bJ@f2yXZx@)Pfzv!Mj&wa4!o~iGvw@+91^vs;?R@&uCyFzJKD(xzz zU9Gfhly$+U-iaLuq#^?JlL=t+acT zcCXUzQ`-GXdq8OqD(#O-dq`=2Qrg2x`?Jy}D(w-aJ*u?Fl=isN{-U%el=h_3o>JP= zN_$3W&noRXr9H2-7nJs*(q2;9UzPSZrM;}QSCsa5rM;@Oe<lLEJ~YIX|pM9cBRds zv^kYFm(u1|+B`~|S84MpZGNSVQrc*xEugdom9~)57FOCKN?TNEiz#h!r7eM5`y{yQ zRY_|pi!Jq5*jpdLI~6V|E4a;C-D0U99hG3M)u6zS7H5HV8>|hYQdwi86Rb@WtgREQ z?Hfc#6-cngwJfj>1oqV1;J;pr^|d9X+gi?TeJ}NP2tc_w{I_1}9q`|5;Ow;Ivv#(2 zfvDG#!`ju_4c;SQHmJVpZn31^34N#4TH4|RsGcE(dY?k|5<&Hrhw5u2Q%#vn^`lVz zMNm+ND!cmz8G&lXKnSGEuN(2Qp!LqyW zQ}a+`DAZUH)Hr#l@#djEr%)3_P+!PHO)>)2idj>WDby4Z6x3AzPj?>+HH|_|7ePUJ zw=9&Q-N!=BpinbKP*7g<2+pg15c-BB=H9 zP#eudZK6=|BB%s;s35GV%@k^j2x_Z5l%b=qBeT%AQK;=As2%c9yNv8U7HT(z+9QI3 zzt@pn=!V{ASg3szYQG5TfIO6;-PeiPeFrJjk0Pi;A%*&hLLC-C{VWf4#K@XrGj)_g z9TP#p-*(BasUYmWUntZG5fuCd+5Z$Oj#*QuDAZ{Y)R~Y%ouyFcL{R7Dp)ML(Q*5R# zQK(-*6zZ`E>PbkUo>Hi1BB+1m zpm3#;EpZ-(^CSQsoWGQj|eJnNTKpksQeA+wn(MWITIpvuT+%FwsNEL2$v6(fQwCl6)l z+hG=}JcX(tf~qJFWoY*eW)^xS3RPJIRVAcQRVh?85ft1XOZJQ&giO_-P&GwRaH}p! zC|eyPCr@_w)umANL{RnRp&FWpiltDEL{N>Tp^Tl;*-SN|P)$Wp&7`4hEsSJp7<2Ts zq)@FyP_3n*jAe?2YD1ygilEws6skRi>L7yZC=F$cGr#*fQ>ZQ?sIJmb!PtG>C{%Y5 zR1ayWU}Wk&3e{5t^}ak*ZzH>JICJ#%p-_EAQ2nH#jO{)asy~GqAc7hgQm8=`YOn}u zh%}V3_dYgLA5f^FBB){VP=?mjhs>IyHF-8sO&)$AhvZd)u{Fg)eMB=gQk1EWLkcyD zLVY5F8Z8ZFY)!G5`jkSA5kZZWhx*LOdFo?kO^v5epNpU-gcRxv3N=v#HAx<7ijho> zVlp+ALQNAvO%Ey5mlSG-2x_K0)NCV}`h>~U911m81T`0u-%Yw27)0@zbYd zp$vULHHOI)tzNW=su%HtutEs6fv%~IqBXTi9xB1e(KnXK6s=ygiK-XzbUL40{YB$||dqlf$Z%Co`QK|(dtE;sCp4UU{7|T2LXy!FWN-ai}+c8vQVdutf|kLOr4>- z@2qI|!M*lF2z8!9T@XQCl!yA&NTwz*nfi@FT^2#X69{B86$Gf?Db!UF6g&(;7V5f@ zOnt#*>IQ|nDT2BcQm8*E)NK*e9eJp`Mlv;#$<#dxbzcPampqiA>cvS66s=ygiK-Xz zGel+A)MF!=n#@2wp_zIr%G5J?sORRPUQno)BB)pLQ2&{SdJ}-MTLe(}Nvo2(&u%vY zHATDo><$X$6hXP9p^SaG&qBE=lt%;=CJklxn$J`?g^CbCC6|Zt8G)M0>^@qPXBXAv z;ivM-uBkNUq0-V!r4wZ;y*yL~^H3QnR3;HrW_hTrMxdrKyDuAs$}WP+5mKm}6e^bp zDz`jTUL%>B&SZ*Kn%PB_X87sQvI{*3P|-9~1w@%DC=F#b^s)U*CR2qdRACWRk&r?a zrBKC0P{pO8>?Mt?sToYBXr-B5RB48vBrdzAf&fJ;&FrE|GyG6HRPB&L)uB*zMNswRp&A&;)NCeG4JlNt z2nwD>DY?+ChW_Y~g=$Qpnuws9N<-P38_CohCQ~gaR7(+5tB^vqrciA}P;KR*+8fE# zTqaW;C{#xgRHu+a#ZjovBB(C%P~D7V>N_S=-6>QL5fnVRRr2Vw2LY-lg?e8E1rL#x zh3aD@Qwy0)^`%h#L{R-h3N?U24HQ8Ql7|{%BvaornWFVmc2WJ5UA}(G9t0>_KV=uy zPub<`r|gFAX|{;T)W>x9jS}s?Pvm!B5THg=s82;u@Z@C4qt9ljROtsMQ)4OAI1v;) z#5sgew0_Dis-LpU*H0PyCT}T|DOx{e7u8SM-=TiWP(d>bHJR?dDWcssReJXs`zDWt znnt0fi=e)ghcfg{-ZEzQ&7e>-MNqTkq0$&Rqq9)6DbySh)LeNeL*L}FQ1d9%d=bDeJz552f@ppr-A@QE6wbpN;CUARGJy8pIX6WidLH0MU`gu|8=Dq z3$=vqz8^%pZ>jX|voAMt^sQtvMJvthqDnKne5F}1pjOjNtr2Bvt#qbrhKf&DF_~IN zq1KC_HiQ&vBZb-|f{K@hvTruBrdBhV+CrhWilDZI6lyz#+9874DG#;VNT${>nc734 z_KKkPg%oN(g*qUDIw%cg?5{!AGMW03LLCx8{S;ED!xZXg5mcf)l%e~&tYb2DghCw^ zK^+Sz)Nu;+iwNq3Jk${*N8frTQzt3ZDG}7^kV4U#JiDkS&n{n+XEjv%y@AOTt;w^C zYVz#zHF?2+qIVRui|#0Bm%pQ+v760oWHNP`uBj`cHTApnnhFLKy`!LAbVot^JKRz5 zqLHI-6O*ayG*dT3nYt;RDQgg*Zc(T|MNqfpp$y%FBc93B9SU_<1a&W@Q1>a+Um~an z(opt?M%GjUlc|3w)FTnpP5S#deJUly=ec}NTxP3nR-q$^+J@Xm-3lu*eP!78Q%Haqpl#@caL{M&ND4U^**lkRvJQONS1eGkL zQ1sr54$-|A9rE{HG**1Noyiov_o72|??s3Fy%&Q4Me95rqB>8<|GLg|2a_p!??s2` z-ir?TdoS7zePzu;(R(jCME72F$lrU>W~lUgCzGiR^ytedI{GrnAALc9%1oiMh@i4c zLmB&RW*3twS`q6IRm3{pp(55$={E~SD`Fj@ide@xRKyzk8Duw;sXTP|V3)6|oNaidaWUBbnOEWQtbA zIz$z*4*81MU_h0nYbr*xrpn2$DMJ;p`?eq=J$jzYB; zL3IczR7VQcNdy%q4`t|ytcRFPb*4~VL{MEr3Pta|=n&m|(eV!VUNm&SgrAs9(R(jC zME72Fyu-a0g8`cOVoL4X=Tp*|8pjg*HPWh7IHOr}1eP@_dqpN14_422pif*L0e zW$1w=N0>}~PN61oD{@x=F;6aPqh2y%kRD*KrNt9Ux}c;mWTS*$eKFNWa>K#wNM20eMq4e zQK-cts3r1HOO0ge7ba87DAaNh)QXTot)x(^L{O`xp=^e3V041X)EWx4Rs^*!q)_WA z)CLjMMrkNVypc6^lF3v8h1x8F+7eQztrTjT2x_}L)J`LrI>lsa7lqm_g4z>OsJ#?w zp9pHdJk&uWnL5p6iq?5LM0K7H`8rQW5TIzCr$bcd>5#AUbQr2$Ji}y)-saFDy3L_O z{x*k>UySU&vkcS;x~5Kw*3>EaHD%~Fhvyh5T2ko{l~g+9ODY}bjb!RP19gFB>Y^x9 zm*g{L=#GLH7$|z1Lx<=#hYtDM96GKV$<###>JOT!YobhDm(NrXpy+K59irPDI^=J2 z=(uepQ`JYswx3 zs7Dm)u?XskG?cNsm0V^r^^`(A6G8ne4dr-YWcRU9FDcY35!7pWs5eHSu4psmv;?4> zRsodL7E&lXg>s0XoYGKEw~BD!C*kqLP4jfP|*1fg@T6ee0q(^ z6fG2ViV6jt?@%acsLqpxill2QrD#p1l3r8B%HLQhS}5og6$(1vp-|A!olmbbyN?zM zIz@$o&UYvjG<3fN7K#=MIz@$oPWeJXV>Nj!6fG2ViV6jt?@%ac=za+|nB7MU1)ZWo zLFYRZ3K}XtWua)Hpi@*R==@(73bIhNP|ztV6m-fL3Ob{Vyv^KXc3(6-PZbcIrwU4+ zr-A`R3k98`LP4i|p`fupxWC0@swmA=F;S+9OJ^z=P$ei-NfA^jX((fVhx{j#snQgx zj0mc1NTFgVR5=k;d3h*9*XXyIOjV#z6-7{$LJC!xLRAq#Rh5QvRx@&*y2E6uI)$ns zf~qMEW$e$M?lMrdC{%3`RGpAQ)umANL{Rmmp^V)O`5u$01{A8H2r4$DP>m>5V-Zvn zX((qiBMbdLld0wus)Y!uWk{h~QK;4;s5bIY?TlpVFD6s%DO3j$RL77)b)rylBB;*t zP+g5=>H(7}TD|BLRWCZ_s~4R?fTGolPEqxuQ@(o9+1p5_{$?`Ohwi?+ZeCib4`PBIicRn@rtqTkF1wAE96rB<#NuLsoedqav$<$;DHAMt9 zHKb6q&eJKX^K{DBc^dnA@hOujTIcB$)ppX)2HJk3fIilS+S9 zDAarr)Pj&g(L0|yMRz`R%HR3a*!`#eWimzYeCib4`P31Cvw^Q`sZ>Ri&zk>lqAN=hUJ^0)C4iEk|bSL>YOs3-L?n@BuzRl9R&)Dtl zS*R@(YO4rpn>>_}J2YD@Os2L|s2w7xogsyyWx7sLnXXg5OxMsa4pu9ZDO#rM6qV^Z z<;!$~0d;`xzJsFO_oMXgvl{uu!D?eNb%;X!B!W5|QmCIPRH6v#h%}U;n>bkQOs0-f zsAD3i;~|Cmg+iSWL7kL_a-KHuhHP~(nWDABPEqZ!Q@(aM7*OYFrY?vwbx}T3Mrwzx zP9{^dcGxMZ9d^ps4m*PY^*hbfRZ*t?kj|8$D^IJ7$<#FpbzKB?BcxC_Dby_y)SuE& zhQ122x|vMfrcif8PnR-Gq^;DFpXVRGp2GqY4>bVH&g*23*@29NEm`u?sYp1Bn z+9_XU9So@dXr|r>GUc*JXUb(Wa+ToKX39mYtX-liYnObLbuge@flRsFqD*<@GnLFp zrox#_(JE_~sLI+UUuEqI0u-&Xc8RL2UGi1du9QYH6~SaG72SQQMY}JJ{O$_^R9Xs^ zP6U-+9?H<$OmZeu87WjI5me@oLS>;)Sw&FUAK|0bb|p!%XD3$GF_K^ znXap$ku{Zu$y6*|=#4}Ry|MH{4+c~d3e{8u)l3@7&~M1rv`nU&Q>YdqsFopxYDJ-1 zi=f&_Lm9dUhcz9OskRiVod~MEJd}|;OIXu0P#q{#M-fyfc_>3)#3BYNjzV=7L3NRa zGV~j=H3I|Hl|pqBL3Ix)R1XUEo(QU^G?c5Ck&|Z@CR4pBR38yk-;hG}qfq@tPy?i) zjQuj2mC4jV3N=UsH8`YDLnzb-BB-I#P{zLV%*JGD7=;=xg8DF|P$MYRMuzAietx z-RjB8LM^3G%S2GirJ-C#Dq^kCOr~f>tV>i8>yodC4F(jgh;@l7VqNkTv4)=ZWG%pC zidMwBL=~|v`HI+JK*iHFl^|MEo8{NkRwGAWK_*k%DAaZl)Q*rs?W9nn9_bD$Hbx-Xqo}x<{-_{vNTxfI33g z)KSrzIwrlQY=(*@iZGcvPN9AgL7fOG)JY0;N(6OU8p?In$eJq3Wa=D+Ixm8{5K^d% z6zY-)>Q{NF%SJL)jLFm$3iZ1P>S{=#=#6V#q8rz`LG>t zM+EgKq)?A3)DscZQ+X&uf1*-~$<#9n^{)u(c}SsNP^gz8s8`ZZ#(tYA&1C8|h5Anf z^(K^1Zc6~lZ52SdZU1Aaa@tI}Y4NFBRD9}|FFrN4`&cMieCiezpStCXPu+& zeCn1jKDEs@vimABnL>2;Wf1MYjPkoL2vC_QRAv!W7I`Q`fAU+2$y8Pfl}!YdJ)}@M zC{#`nR4!>KcWxtVsxp%)S`q6ORm8gGD`MUGjX+glprUA|qD7f1AfKs1Mxd%PP=zT} z5fN0;kU|xsP{l=1CFG$>8Oc;NCR6mrwQkXkYu)lUu5||iir%=^ExK{7TmHti?ute- zRh`LHCA#}6i*{cX`P~-;sHzmInh2`8G?bw`G+S#hnW{mdYKow0g%qkbg{mWhsw)lU zGW2VEO(s+IC{%qBRD+O0HKb6nBB(~vQ0^v1j=ow>HHj}B=6snB~s%=Q2+EJ+XBB&11Q0|UK)>IuPQ}o8QZqbcv-SRiCwLLZhRhNP4 zLNnD>l&NmgnKE?iOe+i3okH~xLA@sr^`H4n^`ubmi=cW*L)ncy+QnLr*?qJk)-9@t zb<0=88Y`(}p=d>{TT~J2mam94_7~eM6s?GLiz;H>@)famBae2m)@ODft%!AtDq`L8 z6|u%{cfmr@ideU(BGxTm5o_$u5-b$0h;@r9V%_o;vBnm917`QpideU(BGxTm5gQCB zS`q6ORm8gGD`IVRjGR2#OpT={&vBxY=V#InxeP( zb&GEC>z2R8Z!njiTl~7^Z}DsFj2_Emir(VaExN_8`+t0kUn>hWgRZHWqBS*3 zdQBNS`dFyh6l#tLYOXYtv7?WLqPO^Ui*E7j{vY4s*V>3#Q?z#2Evg-M%hwJYd+%eR zXzj3DR6FdJuN`(9svU03WQx`fyG6CbZu#2bU_jB@VYjGu*ezc>Y;2)7VKTLX9(^lC zN8hUd@zKXZt)@_GL{Mwxp$yd}G-WcijzX;$L2U>r)J6)mNdy%y4Q1@l37RpPN}y1i zMNnHp3bmC&Z4*IlmxeO*1TkxKCQ~~o)J_r9u8>0QrcirCPa7{)Dd~82S%V;F;Mhwx^B_kblviI z(=}G>(uRSechhx??xyROzniYx(A{)ds55l;ofYlAbJDxdeZk1?Ys+Mc7Bss>11a7-wCB|Zd z|5+@qsEk|OZ&pFimU=t>{}wC!*MF<3g;lqhI0S`oQE_XNEb=1W`;~#JeeeC@T9}JB{QV=WTrDf*yl-4 zX2{~n%AFx+&}PWx$*s(wT^^qN{0ZJ#9v%!HSRM*=lqXuTEDT$Rx6c{1#Z!du815h7 zPkZVuFxciP0J$ydDfSi@tg+I3m$$i!!!Dy-#Yr;D@GZ-kuq@BFtYpHnvZu;hyF40} zZ7sg%Tg%o{6>m9NRMj-g7Q#MHHIj$gIx{qoouLk$p{{m@Ixs_BGDAatS{m~wczfrO z36yh=2W(+IG|_=>!S{SSEo4EEv^3R1!_x3HB{Q`2w6fUA(cH-5fd5%6o~VqO3U2Xq z;!hFfA45+V9#0$PaQ1lGLJyy6J)U+jnO#}et;r@u*kPa#hWOw`ylHVdo7Rm#@7tT! zneGo}(>l{l>+b2HtSNQVq6@&L_2p0T_NKk3OyTkL#MvX8_P(VhY#Kf*!X~{3ll6pu z?~_gH=jpFZIN0Kb|5+@_qhLbhKu+Y^;`xw2ZEgQZn$hH*0iF?LEhqO3^n667P3{?l zr^Sw*!O+9|DY<6|^qi#k0rXr13b{N30B9im8wCFb!@nW$?*jrjlD|Sn^TFO;p&#RX z1Xk$B#PU{B4`chmhK~X`bo)1vHCq`t||}Y?+5{na96nfd!=5 z4%mj-o;hzFjL`)$Z}EI3J0U*s@M#bqmVp(E56i&8I5#jc9E5=b5+?rI^9}4+e7U53 z^ZK5DwZy!6fq0Q;vEH&z1IvB|pZ)D+PgWNo_zwWQ43c}6zyaW2_TvJ}-rkNb`yXJ- z=(5Ml0WbX}@DI`o!+f3}$kJHJ-MTe$TesG;PT9IoEU;#Q$`?4O)40;Ow|L_D+t2nvWl#p)1EUN!*hPa zi(q)}9Stvee&rZm_8VRW!^`hz_=o2j$MA;V@J}$j@s5VKJ$E>U_xy$r!0_HX8vgBh z$T586H+%|)kKWPnnde`Q;S0avYcPEAj)wnv-n?xXW+jGUj;Kvx)^{@ubB4jkU2=Zc ztiv#m-_Q$&aFTnMbr=>N7Qr!0;WtbPhAH0BFjZJ;j$vBAAp*m+?`W7IEF;G-v)?cq z7-oJ)!|Y)>ls9MfGh=kT=kR*SoW$pUYiY|s03x6D!g7*Rxzh?kxONH46~_5E8t+Mz zw^qLg@LO7@@J?G{d8JNUmZ@BEemU_pt~gpwJe?~pC@21sD=sW2p1~Ctl@rh8ii^vM zXK}?P<;1hO;?i>BIb3mBIq_VsxSX7L9#>pJPCTD0t|TX3z!g`K6Mw}OSCbR-F0wa; z)sPc^!=1U7ocLR=xQ?9oJFd8%oOmHu+(1tJJy#qnCtk!AH>D zaK$a<#7nv2)^g%yTya}D@p7)Xy_|RjSKLuf%=>V+DJ)J-yox(>7di22uDF|=cnw$F zLr%PwEAA;LUdI*pk`u4ziu=fkH*m%M#SG-70e3UC*A}2n^6)%+&ALojf%ZY#CidV{s zPjJPn<-{ks;`KjVs@%ZdNxieJi!pL4~p<-{+z;x}^QmppMYtDN{1S8SIP zzvhaaa^nBEVz-?54Obi{CAM0)Vy~Ro$`wb*iEUhQ3OTWzD~^;CJGkOha$+Y}oJLOU z;)>JBiQQZ=k`sHl;*4_QFs?YWoH!X*oK;Tj<%+Y*iNm?#oO0p_t~j@xI5}6GS5BOQ zE6y(`_Ho70a^gs?xS*UkC0ATnPMnG>E-EKZ%@r4y6Q|*dOUjAUa>b?P#Ob)=vU1|| zTyZ%$G2)6V$cZy>#g*j58M)#ra^g%}aWy${X0Et~oHz?tTuV-zl`F0zC(gzd*OL=x z=ZYK1iF0tpv2x;^TybMLaW1a7shl`BSKM4qoQErJDJRa$6}OfX=i`do%8B!H#qH(9 zQCx9HIdL>s9499(z!i6q6Bp!)yUB?Qam794#D%%yo^s+MTyZZsaZ#?gkDRy|SKLod zT%0Q&ASW)t6%UdUCmYPI4h+j{ygD%15WZ!86P6$FEu&3X4&_@GG+{Z6Z&}!c<#4`b zQ4^LQ@-2&-upGg+ENQ~>Bfe#66P6?SmSs&?e$2NlXTow6-?D-U%TM^0l}uQU=37=V zVfiWFvYH9YF?`D!CM?JDEo+&u9LKk;W5V(?zGXcVmgD)B4NO>m&bN#;VL5?s+1P~T z7kta6CM+lNEt{LLoW!?mX~J?c-?Fs{%PD-zwk9m6@-5q&u$;!X>}bMrI^QzRgyolf z%PuA?XYeh%nXsJ6x9nlUau(mRrwPm1e9K-YEa&ho`5%ePEp!tx&9GMx#_`+Q4e z!tyV^WkwU05BQduO<4ZTx6Eq7@*&?cy9vvG_?9_MSU%!g<~CvZm~WZagyj>yWquQu zPx+S7CM=)vEeo2k{FiT8*o5VCzGYDpmM{30#Z6eg;s)-hq};#<}; zVd>^uHZWo7;akRIN!3R3Cjq+Wor|b$@!LTO<1Pj zTedf0>El~=G+`OZw~RAknUZhW#e`)lzGXKPmZ|xcJxo}p;am1JVVRb1*~^4wI=*Ee z6PD@umi*kgpY&C6qd;tt+&9C3xD;)YytCvQcLxN=f)ELYswTZJR8mQ>t`EAHy8 z&Jov4DsIdbcjxZs+DXMtx#AvNaowb1|5NIdo=M*0F3s`yVo! zRQx_y+$gEo|J>E2;$B>FlcZw*^HGzEdvg=kEUCCVH`{%<;QQ=9OVdGM4y<2~nsHsuxFDdD+J zc*^Q{%J<_vmxDItP2DNs$xnF7{CLV<@tzw&oASQyl<;gQJY_{ZW$$>;y`W9`Sa(Wz zdK8|r3ZAl0yysESrhKV8B|KjWPgwv@**D(vB3M&~+4QEwPoTn67RFQdix0B~ZOSm+ zDd8Dac*A6AC@9$Q>N3M5}tE~r!0x592g&#HfU33 z(VY^WgoURpgQpx6AC@^dQ~Hp1FuhL9M$WMCFv{)T4_a^b4#VeYtL71RwPEyddSR#; zJpx95lyr1`7(J3+32H`ZSc;A z=Bo|fh4uvR;so!~?cU|BQ+ZcJT08lwZT7C-;N6hmO-S%=)x^tc;_zN((SDw@YOjTA zdS~E=pDWKL^Um=30AvprWS<}800$&a2PDoX1kqksaX}7pK@Ryr4s$>{>wt6?gZQ5{ z@4w`D8w4KE*hM*>yyZ&5^M4_spQn!U=Y6yHSkxBpN%(gT{#}TIW2-Jcwk{=juk7(& zjrV4TfeRD7HxycEe3cWte;UxuCDN^ezIB&S^fWqY(%`bv|m@B(KYygbfejs+TiLH`%jg>YKe~zW-fDhbCq~!!|Itm2_tuPp{n0rgyi1G|ImsUB zhMbyR;zF*#F7a;HEQY4OGWv_5XS}yI^>rgR@$H4&8eb3caDAKoKfZPG3X2ItVZ^f! z3e$KdL&=C|xXr)J$YyzwmkjNPyqclmD4Y(pK?VjSgb$2~KoMl81@Rn-QfNGV$j9CKmcEYqS^Xq%M6~o}V2%i!kw_Ft=J^yw zYUW9aQc`w&;E~Ntg;J5BV^J#2(9|e(V5oO{fIbaMLxz5a(rAXJMQOS8t$daB>Bk4? zTlvsi^yyGKGS38*PBTw>ls8Bm4*Qh52mOs##Hn3>4Z$%rx% z{bZC;qtApg`KOw?Cwyu`_?PkC`gj536ID!Rl$j`IqRbja7L>)Wn7t=_c0%~P!04BQf8pwz*`ZZ$d0lTid87Ph9U>b5y%qR z$7J(zqMT&t8kAErG#ARH4rQkQSf6t|GqAn>z;yx6+$cAhd;`j@nLH1IcNBQP2>0jK zpRIVUd8FkVefNZTZ$q-L^P;@OeGAH~anFbH`Q82d8WuYoKlxF9GIS@(uNfMJ02G7R z;JpjFyEP0QeI@k~#=~H;T%(cy-Ec2b-wwSo1rU8hWX`G`eYFIh%;b1!>zsV{1rC6Y z%%Qd)Ry1sBLF9kuJ&3e#y@gOAZBl+p2tPtb7e<9iUXG!{n!FT2MUsp@p@HipTFZ2a z7DYvg^C?tR<6I2EC4>J`fyqoKU!491!*YTRD~^g2!!xM3#;^n`kp%U;L(3XzS*&k- zi5)pweXdOqZBHY1jC=-(x@~UeFc@)j4p%9BpI#EZ=6(q%c8Qx z`6?=_agIST-2BD~^BeDN0t@;YNpm?=j`-d{X-3ya^|hlp%#oH)^;ZZ39clSQf8+|y zqU+=9pg(XJGcc|Gz@@MR$yHzj)PQVR8q`3uWerh7|CZs^qxFomEY&w%5m@qle5qhm z;FDohvYuj5ESV@Biq%Zi2sNS;(e>0AH6}w5YOERB1U1oSo9>&Ys3{qp5jE9}ZibpM zqct1RSM-ieuh^TT=EOELYOb+ufm#q-_z26qFZK1c(9g>!fn>KtEs1AV)KcTw3bhL4 zfb|rviG9o#iLS;1d!?`Tqz0d$fr?!DwMMN8Rd&=`L)8YgVG+h?epCEcvwny!Wd2ZBRW8MLE;3mDluZzAXTnt3y)#Rvuq-C7`Xzj5G zBgg2EOb8^RBkD+4^P`R$)=sF?+lkPg$H0BMzB@iH$xewwal}0u#cA9-Bls|zn9qkdQa}BekbK7`aJ*r1sngBd6$(gp0IRboKW@J;-LopdOmddJny)O&UGf^h7<$ z=<=wiX7u~$eeGzn`Xed@c1thRi)gB#UK&kr)cY+>xb}z{=xd|D3EGVv=qsT=kRDon zP#;234fWAb^hJFM1v#Gufcv3-WM~c4PcyVX>aPyf?CF7#mhbiFAJ2{yTsp6d_qL&X zWdMSAC%CAog$8I42BLx5oYB292n`~m>!3lJ(Sy-o?dT+XWe6HVH1*IBjphUN!CM+; zuMGCJ)8AP9=0T3$p=c;EZ-9ns%!i?2e)A;ns)L0m9PJS>SoGEfyE-CPlWwpTyjg3{ zcrbE_{#MZ?G#m{lTh$m1*KE~?2tMI*KB|FfyuPXS3;-iH>W`$;k3b{H^i9zS&Ga9k zkKWp25iQs>oX~eql7{2@BUi+G+mS1ok!U30XoW^l11oI|8bdT4&=`$oEE-ERa9Brl(tgeu<{PEE zg%NR@tPK-=?xMS792!Sv?}El@X8#O*_BL_%0P%P6`1T=wUq!*f?$;cPz z3zCtDK6@hiBt-NN_p zqA#@x8WBj)3^ap`9*JgXM$beuwVO;6Gz-llqer1xn$fcne3_f%LW_AH_)scAbI=@O zJ{rx@n9oIXxe5Bv*H0orA0|zZ|1D=8nn$J@gXU?bnvdqwso<;xUym(73&^-}Xn|(j zSLiEsTwqsx%={z>ALINpeT}{*4&%|+8i#MtH^d=g0{PV?Vq!wXq?m8fw`AxP^sQ#- zcj!BHXkfBY{K*!gg~VYRTBvdO9(}Jmz}p^~Y!O;ShJJ|_X@)LFi`AjZWbna?Kid+t zgjmc(OEeZgpdVC=z-&v=QZjTlTB;ek3@uZK(%DAyXIqYz6N|ZMxyE7zTA^A5W?P9? zlA-g_O3lz!Xq7sY&h{yPw$*4gvG@wD)>y1TYgCKCY-`b4GV~j?Rx@-RTBi=BvyI`; zwjQk~7T=-u8jB5R1F;DF0t{CUBVsn9jb!NeXrpH6CbUT%N@p9(pDiB66N|+tUSpAf z5>yLVy=1n{Xfql51KO+^x&>`fhtk=`@n_qLwi1hFXsgCz8``E?KqkqDrtN4u8M*>( z*9_f(c95au7fL$YXZ+cAqMgKI722t>*oAhzJ=<=yn+#opc58<2L3=o}jpxs{7wsh$ z>(E|}#Xhu8JDWd~`_X0fO`w;6!Jq9YI!Y{d zpraa#W9S$&TP#h{M83^&be!1iLdP{Wzo1_jo4nL!65r+oIzepqpc5LKljx+nL4ou8 zDRhbq-G@$ThMq>J12aZ+a;ldKk(SB6y1H*$5pe<6Gw2L)J%G+=T+gDjx~{zhuI&5` z^+*0h6Em5gm~-eH;rbb!({Pe^;V0%d^c&&&1^uSsx{NNrotP`=3K@D5UC|8v9sRDe2~(vKa}`}B zuBXvejq4xi4_#N;#7vb-%v642uAys$>nysa;ku5l6RwE!eLgooYIN zs=MeevABlrYAo)dd&EL{!-lQ8kM5IkH_&~}xWCX}{;A-aKTvoPY57t+6@25YTtGfR z4~WGr^gv_rH~KrtR1eWZGVV5ds2TSU`bQl{w`vA|sz>M%vAByKX)GS2$EpQTkqd(- z=m{BmA3f0weTtr{L+NZY`LjJk&xpkX^h{&%FZx%tfY}D%BBST%IT`v8J=Y91?z3v%N$wiNz!IQe*K7y&@LjKL-}aYxJ6odxBnT#{Gx>^N&-0c%`$=*3PCb#W&~; zae0Q`P?r=3Vyu<}$ZAoc@n;N(S|MsBrF)dFUA5ZH;?OWb43 z91wA+X3F$Vh&qYlHSRGA7erkCO=lMC+@#Z!4ROP0H*tD{dyJC@A|BOAS>6B~1}}tR zQF5GzFh-ONBFR)>y7k}rio&}X^Thx-d117dIN>CC8K-cFg!`xWp9sjuGZ00<3lT(w z^AN#^l0zi9Dx%Xb)J~80I@$UZFggWs!g)x+IQbyrQ#VB2`bc;ol8A5~A{kLih@@0S zbo%eP)2D*bsfZKKLn_88HAGUYPU`e&;Dt0qg!7Pw5v7GlT2(}+UzBuua!PJF=8NwV8$q^u=Wyr8uIpKwzM1-@RlM&^DNUne=N!pf4rY$#kS>V^#(tWmGejpe(#lmWXgR$}*xD zh{UKOO0Zgwpd1Lw5i^{Pa*SDdh?FO0%JpyHZLb2nP=SbWHYzZpiV&%&iYUPvEdjaM z!PkPYs49V=5;4QssKl66hDc@AOg-~fffuR}5za;xMpP9dRaFrsSgS`+4FuJQ8O}yE z#;iI-s;g!yK@E7J1`*+G)L=w4AyQKnQG#`P1hqg=iq_3w)Oc>8%8b zs{=38AtIcOI*h0;MCz&{O0Zr_K(73hy-*JX^@thHMm@%?K1AxPW@-)^zzYqC2xp@K zBWehdhN_4XY|tZ!1wkw^!`X;s%o;(Yk!q$AG=>)%6A{ivV@A{jB282gCD^D(&=dqs zi5bpDQ^u?rM4G8)DnWC2p*a!ZY&2&?Eg;fD6;XmsdIT*&(2|(pY_w#|T0x|hYNisj zh8J2B5zaS)W7ZBL?Nl?Bpgp|Mo``TZ+B2dK5b2EkFQIv(=3eb%#iIRYW&ws~$lQ5cD8sI9oj!v-cqK zo@%DB)%RhsgV?h!SkmBj^Q!Uc?M%qZeb=8zQ|`GnJqZywHb;a5nld zqP`I68xTcwib_b{!_igq>vW`LyXf+-Cq>?_hujZl=tpM9ndryN-X9|U1G8(dRR_Qe z@HGN_z{FcTfDsLZ$Us#@33lia3UPdF|&UHkxv4%6J$7Hb%FQ)(eT1(BEnldnh|{pkxz+;{pD+q9>Ew8j3H(?6Jr>& zu@D){BNzuSj3Xkv0pl3aXAt>J714uZuO7j85R4~gc*DjsW}idkbJYwE4kZT@;Drf9 zgg0OUBl-d&U#KEVuuqR*A_yiDGrVCF8M8?cnWUP*)j0mu5%$7lcwsUT;SHF~h^9bf ziYlT6`}GK>f?z5!!y7i0F`EXFX{wo;gX!?XbRxnVFr5*736U>V5hXaFM=%2fGl&`9 zuo;ZmOo+@>%~XO}@WL!2!W%G)5zU6kY*j=F4(bui0l^$%hBs^uV>TBeb5%2yU>>|M zkBIOF%wt6JAu?YTQGy@!2o``~0WrfHwtzAF3L;;rW-7tg@WR(bgg4-8M)VCtzEMS# z;E*1{w;=eInBfikmNEMdBHyWI>PlP)FDxV?ya5Xt(f1Jfo`~4K2<~se$gY?4}$%~3~$(e#_Rw@4ya}-!9jT8AQ9mW zILL^8gvgIX#Ga8(=n)(O!69OXH|!8&_7g;Y;t?E%7Y-8<-hji5=x2!htcqw3PU;aP zf*_HY;SEb<%#J|hh-#+h;3&Lsl!)*K9A!kuAaYC0+C-- zGk9mJ=>MMR1iWy9i0}rSU_>V&a#9shg422gr$BIunBfgO#h9Ij$Z6FKKEfTRhG+B) z&w%I*F~po_7{jv=Im;NHqK0Sn49|h+95KY!=NQBD5IL_k^v}Bt$$+-FGJ)qW2juX zUV#^`5D}JNVMM<}2`=gpTm`{ZVuo$6GG>23kzrF ziYUP)J%Sq`xIxUY?G484CPZ$kX39^lw;+0pD6sYxqxcgde-Z_IcKS8x^yHVw+c5ez zal)Rr8K*lCx#M>tzyBw{14kx&0LEW^--Xxi65T!AV{|xjkLZ&BrLFY1tSxI#{y^E5 z`!M=Gae9b*jMHBb`OEM0h*T;Brhfo0JRqVcxW|b8hRENli01!_&#V4;PJg||lRhL) z&v1`%`UfKa_?@0J(?5b29ud(?++#$KA@W!i(dmEpC1Q&@42@qYo47rOrX z<>}hL9f`DD^EHvF$h+n%rlyU2?XP@(#+iRf2<^DX5Wa%QD_+`ghF=qr6ZaU=e-Qak zXS1$LrVa0mH^kqKds=^+vx_`4wD()E{3+YPz2-Ox)L>`t4T5T?LAhR_2M z4Q+#4Hu=F=pWq30KYFeG31v!+{tZ zPG=s5mmrFMpObKB{&2R$)Cb=2yhxp z60=IU$C#CZNGa6}a^U}nYQyO&O+;02j}euDNEuZ`bMOzj`5lJh(h)xbSQR30MbRS_k4q(^|$Sb><;!ac^UB1B-TH7ilc0ZvyXBC3OXjHoh1 zDyt$&@K}!kr?Cn#tA~4xSyhNsRn62K;B-|Zq6WCfh^j-Rx+kzZ1xW|~)g-Bi1OeMhSsz*f4agPzz zhe&-@Lw$ZWSv!cd zQ_cLJ&22b|?TMl%?lFoE5b2;Q==5)rUP1?^$4Tr+%zEJ-W7Y{GorqbIOXxUwA&!Xp z;2tCD3=z06Oj9%J?%MBY=))B_vmz9$h4!97OwK1AMEMU=p%M}TwRikpCs{>|}U zLX)EaCw>4?jKn=gF%TjHRRx{ip|=ci;s+74QMkvL4Ti{I)eLrla-D$_KZJ-z;~pdW z03si765vdFUI`=sCw?d~8-sg{*)WI^@OpgHPempUofqRVE=Mec^HB$+2?k5n@EZk#6UqIvwRYVDr=@H=EPb6k@aE~#Y z1d&Oq84xJP0?z$pBASPLjA#l(rl=xH;MF@B;M`9oW(#nSF`EXFX{wn@fO9{ch`z=> zM)V~_zEnk&AY6|C=Y9q;`xf^YvzZW?shX(-IQO%NXd&(~qS+9ct%@i?gdPFT{TyPp z2=^GXxe%GFnyCah_w$Ho3GOkX`4E|}iYP&HJp!Ej1;lJA?lERxLF6mdOeMg%|C)%F z;~pdW1|r|6B1(`#?~H_V|1B|FiF=IMcM$nbHB$+2?iUi#YTRQ)-$UekRYVDVdIUK4 zi-_4;++)lZLu9dPrV`-XFCn7!xW|ZofXEN3h!RBV5#Zb}C1x9Ok1<;Yk!7lxN`P~} zoQUFaj}fha$O=_N2~z42;M}hyW}9)3FEiv1UdyLsSh^*rg;M}h#qMf+Mh&DiE1BW2B9s$n%Mq;)b_ZYKH5ZS~dz`2hn zqP@7sh!P-@z#&MZM}Tv`nV9XzJ;rPcM7A&l%Jl)x{Z=A6h?VeZxW^do zfyf@lkp2*DMS6yKzwIT4M{$oa+y{|;+D#@`rFiG;CyL{^$0!a!^IzF%zlQ*&;D&;KN;c7Clb*W++##XAaX<%QG%>m0{qD+K!CG;l$c$` zJ;v-9M2-=&z~>TW(c{D)C!%Y($B2G`$SE9++!5KLgZIfL8s5F zH$7f?zY(*CxW|}XhR9`Nro8!(>G86=LKKg1k5T*%k>6DXoj#x5^my4_C1y`>k1_iL zB7dl6$`Ody+%=+jhI@?SIz+Ck3Oap$z3K6qyFtvJ;~ryn6CyWNGi7?b;BFDcOWb1= ze?sI>zk=Q~{|JSM(u2S&?>4b~jeCsc9f;h~LIl3J$1CqH5xv1ZMsyD%_f!!jh}I*( zEAKuw^I36^G5ZT5f2n405OyYiPGG}}?*S3nagP!G4UxZ95hW;~M}QaKLt^H{J;v-G zi2S3PsRVfaJt87E?lGdr5P7VMC_zCz0=)j75VJ7cW6YjH3?j&Xi_ZTx5L|m$w|CC^d#bPJp~cv#63pjgNRQRQGya$0`g_8zj(q9E6*ND%yQ!% zW0n#kDOEF-09Kwo6%pmdJw}uoBB@moB`B#!fLC4`VwNBG7_+nxNvoQv1bF48Bcf>B zV?^m8l3o>2f>L?}c;z8tRuK0XvkVZ);5SphthM8nmysw6;~t~P1d&Xtf=*vrJ3aYn z-hWoJE1lqrf&44Xc;)3Jy7IWk=yE|MmtR*=QyOV4uYF9L58oADF~ch_ zH!-V%dyH8gh~!Z>M@ax)c6o`S8tyTQd=SZ}Drf>KBuzkIdc5rN6SEq)$CyPy1V95n zztEy1J6?9tL{tm+7*PR;6i`K!prRfDUUmhESsmPC%nCuIkZPt9;FVXHi0a`UBPs%s zBC3cIRMI2BE3YUqYk+%k{C9}J;tyUL`tcftLCUQyil5mTH+ofDg%)+s)!O))gveig0jS{HSRHHF%XGS z%~XPN@IpBvYKwb}2p>A-RS_kqrbkc#1Qm!`d)#BpDnbO_Al_c7mEeU+MAQ-Y7*S=2 zR8~clpt>FbK0vDwvpC#i%&J19s%oa@03V~(h^PzhF{0`asjiABK@B|ue2ms0X5Da) zF{=rYnyQ&{vcLyuEu!dwdyJwsL~5%FI(<#O>G1(thnV%mJ;tmqMCz($Y69>9T91f& z;T|KZ50Uz+h!WJ&Bftk}17g+(_ZYK=5NSxvG#?@Du@H?Vihj7qC>lYek*c86*VdaJ zAI^=5*#O*Q%$h)?iE0*=;2T5@>*yIa1yNICI0W|?!)6d^rZo&)1L1Q(b0QjwdyJ?B zL|PEhTczRFy1oWbAIE=AAiYH^yf5O@MN8s89QPRiRuE~W>#u)nccwHPNE+*t(3`cw zuq1cG3%qOLb5LtSI0E+=!Zr|T!%G`J2el=lk+{c*+Cik9&Suqb7)H108kogmVQmo|K^izA{jxW|Y(Lj*pe`+t{a?}%ot zFPS!cTI@pn$Kf91-xVTVb^T@2R$ne{_4U$*&$ZnM;dtC*2)je1dw@`L(*`>}-S!}& z3Ao3I-h;?{0TDbf$v4H94KB2lk2v_;+LI`!;U1%WA0qD)B|gXDvQb5Z&#k?P=u6yV zM7<%>+b@F8a>K=>XD-wJ&*})C<2Pe?;T?4&T;5ly9UeiH76g1=J;SGgPNapTiHT(HBpR$t*BgD?;x z0|N+J?m_UvAR_t(_ZZP&hzt&hD0g6Q;x~gKMEM==G0G1h@&QpMSpxXYU?>rNk9&-0 z7(|BoMVuuN`z}i$RxXvXda1foV%%deKZMAKfvjj#iBIz*i0B90V?-Z8S2*b4Y7Iy-(R7)3-YaE}pv0+CMwB7N@0 zg7c_m={DBm#;5wx1Ys5KF$kYR3M#QX_}wYeU_bP!A@W;<|?F~e^dU-AfMzzZ{oXcz7=qL~nx$suT=M=%Qn zvxwOq++)n}djY&H!DWPU5rhFH42=S`ieGV$QQ#B! z3ROX;@1UJNyy^zuRrRy)O3hbJ6|wJ>Tead?J%i~~L&uVWlu`W@C=&)eGDdfWPW6K!K`U)pAQ z6CJ4?xgGhS?d=%p_ypQLjuVd4(B5^ta=h^-I@3DyI-{U{-#NnhF|;S0*PJ(@eeFu_ ziu5MB^0~^o%0oNNwa~Q~+U>3*uH(?YbcefBcoW?P-4)$cpl$2!?S^^XSKa@(pLi2J z;hxN%Y|u{d%=df^?Jdv0o|oRlu#{mr!}37;e%OdGm@n*AvWR3pZ(_2jWaW}ogm!GQ zS;^)?dnVbj;a%YU2HNZ1C*FU(iQ(nL8-zE4womxS;iJ8Y5eFmA zMqGgQVRBn?r#CTqrsM^a7lF1`@>a>)LOUe+XUQi(`!Yp%3gAwWKSfN63f@GY-Iv;z z4%*(nkv_n@$_&t!NLeFgZD^;b z{66IpZ(^znsT!tg4DEtct5U6n_IRq_Q(f~WrY@MeVrs}w8b_KmY0^VmEKRjEHKFaE zW@wrZp}m*pby|xzF>SiE`O-#1J3sBpv}>UKDeZ-{ze4*eT|_#cH!)r7bnmC@<4sIo zIDO^x)u3IIes}tP-b7Ri)k1ZljY9*`5NM~O@6aM>_oLJ3oHsE;l?+WXG>3LbhR-s< z_GcWQac;&1(8g!{G2>xquVs9k@tHRo3(TJ-F3Z3y@OqX-SvF*ztfR6{%Q^$v6zxhO zQMS*r&B-<&+QZo{X8R4=$Jw3PVZQ98v)9gE58BSz2W9^N+9lZ&vTudk57wemt<@^;AEFYiET7v|lNHy+x3kxO`guE9#Tkvkdzr2ZsN)@VCs3ElH3*9gDw>PnHMByBT zVZRsdQ~1-uP1=?fjkwNUgU=&%c1?T$fY8ey@^Fr70p)^)_>93 zMcWtc1nsP%D~hg$_UEEkio!Z7mabTVVuhitUo5T|YMM7Qa;-)^UlfB}$Yi4Q;a$Jxc(8iG?K+N&tU}vnB49 z0RECWOO`1K`6=0|WS^3dpOQ;TZY#MH+KVM0l>En=SSoL+@}(+4+pg4rQiGvgUTRmV zz0h7R^{5o=r_#}-E0>0KQTn6O(@W2U_GsxpO5gA%ma&ydS0)3rv1PiJ=>hH7GV{uO z1?`D4H_P1iCYE)T%~&=Iv}4Q8D+}?mTgx6Rd%~L-`JUxr`^qmYpHLph&z8Si9=5MS z&I)BJ!1h&WRiRG>*uDx&Dr~C&+gIUYg$EU2`zq$GSiT}`U&VG62ULXZtGK-4u8OdI z6)#tOR1vnXQgo%tm0cCZP&`fD}My- z`pQ36hVx71o0VTy{?D6OrFfOvRp7X-@?MpZRp5B45?|%#Do3HcQ{_!nn>Vp)>8kas z#zNb>>gcMlT~)VMJysRAx9VTj?A2gh9{v zyouE-Rc}_kCA5R9PpCc#+P&4!R=)u4(;D6y$-Rj+s?}&!qb;<F4lnK zu*Qp;DQc$lCf2M~vt7-O(0){NdQI4WH4oRkT=S|ou~vp!g=-aqwpXoBYK?(*N39dJ zPJ0t;N7T+y8`gL24z&l>hVxME8MT+yUJ32*wV%}f*PB=;O`WJZ1)=R+XK0-dp`BT0 zd7V|zUas?~4&<|L+Pcwo3qjkd?vT2W&$_efuBZ#^z3!E|kLy13Ce}+`FMquP(8ksK zpx$t3XV+UwD|N_SBzSe|7zJ&>pS-M}1gl4GK1>+Mous#~WO4aLb$6(9sYz z%mi)MhQk}e{)lzOW{idP6k9H~Q7q&!_Vd`UW50uTXY9#X$YY~qjj}e%0d1v5%^E=- z8%=7ou+d^@_cl7)2=drCdE=ao^FZ6N@!-Zop`F=yd1Kg~##b9ZZT#Gu*d$exd`;l^ zZPKa9kS4G_O=dM&(FC@q$sbLgHG%cfG+omIP2u=$+O_HMrohv5Ueh&A;rMNOv+2vG zus)h)Y*wTh9KX%pYc{eOtdC}2H`~w*j^Ac?n!RZb>!W$r<|Ue!hPHR}(am9fG+)>} zq4`#5|7u}x0qdhh&K6}_!1`{{zs0x~us&KWX|b&ZtnU{8v~;(G_0ckK%knK@eYYIk zazaa3A1#-++|?4+cgv@(ysaRgt)g31ZUyVR)v#8RTfzEhwYt^5R9%AO@}sd(0<%zMw{8tCbs##%{6ag zTT9zCZPP>Bpl#>2-Jt!n?VPsrp*`OAdRy2}?Huh;JJ?U{8n^4-t|zo(+RbgZ0NP*L z-DvlxH?h65eTMd#p>5K>NBj4o9pC<|_TNH#y8Z3;_q>T6!a8K>kR93<9eQ=>3+==X z-*s37?fDM(JN)fU>=@B8N5|aIw&~cf<3MPqc3j+XDYUr#zkVL))R# zpiZ!kJI&~{tP`x`PQQ10(h1gaT$;G3I9SJVo#Tea!8(qc6SpdEEwtC;p2xlNCc;zg z3w16EZTHS2I)4o9g3jwYZ-n;G&ab;zyop^hcPZATB((2$8P(-eXus{Usmo?)@BLqU z=K&vev9;m(Z^~}i0D)bQ-UETqdnZ8Xz4smnH3=bvP(lk$L`4KdL@c19B4P(bMa2qs z>=nD%xrmA)_dVbwqZA?8BwOC!_jz`CAe-Ge&zy5+h~79WF4%b>u3}u{xMp}vh|7pu zhQ}>&yW$?j<4@y5#ygw`#z&5CKE4$mlgBR~zY>pkjNd!{2|ON~5H=y)d0;|^2}380 zz~lM}cTd3nnDEtvKPQ}W9>D)JeC>F=ulNb^bK~*8;y1+K6Oa88|3&;~96H863 zGZFiGV*JE;6Bpod)5QBGK8VL}CjK?aavqpeZc>9ujqx~fQu-wLIO)bo_fLY4la5R} zH5oomE;G5_en^3KWl+>^had~ymt_momo>P*4wPl=y0Zwg+2%Joxr zOo8uHzME=I#pj+{acbkK_}o(yre;jV=bpM{>aMBy+*5y=7BUT=ds^hQ=F{-GrzKBY zJ`JCH+8xvOPQ&M(b}S(*0iQdedP3`jws=fUxFX>yJl>tKFX3rC{+3uUF~WHuu~uTc zMAU=CIf+*%uEFE>#3vK?TLP0|mPtsFK@IC3o^up7N zIuA^*Gd*^CCp^xZe$Di?c)V}=v(r(}r~j4gN-pj^kX$#pLvm+4rYEmS#(qe?H+g^Z zb9nrHMxhya{TcOUbez!zkMn0-I|KV+#?Bef%y=G;CsT^16muR(sh`p*r7Ip6q^wQ3 z4v!C}ypVFxd0?hBv-r%Ccl=i>08sOkOW%gaXVTwG|Im40{?z%4<}bnHE%P6qzuS3WL6rr~7PQ3UkOc_~ zrsMJ21=|*2KQ4HF!G{YzaUNKhxNynB<#^n>aQDK!&I608Eo!-_4IYOtn!YFnj~_2O zw&+*qfyM5{)fd;q1#_5IS(u=xUAAL)SG34mQ7ujh{sjSZdtY!kMAz~VcE~l1IwMuD=e>! z$6?Epme0WBjmz&}{tzBNUVdyj-nR;J?@WBJAFpb@^2PjF^VLVG zq8IV%`a9?)b6@1w=&zF{yp*pombCaKd@J+YUFz4JUKHn}r-97DOD|P3mp+2|F>>>Jp!sBKdbz5di=W2)M7jNa zjB;Bymp_vEvGU@3nT4>As-Fj+&isUV_5I9G*;zHrqfcpm(!BhhX4Rdq8t37sH9v7) ze_vyhHqGOYY<}$g_}-@8eN^*&`1Ixq256Z^kDR{3>7`=wd11`O@rL)3SwbtTc3!YF=JI&U`^j9QN-EY%mPjv?J_dF4 zqW7iWn;f6K?R{llF-5A*UbbZBvU%fsGcR7#RaY-uJ#z)U_5GQv7^%8@=_;Bl>CNvk zSpQYSnY+i=R8KEnP;*he{e7C6j#jTcNA2i~uK&(bA*<^3Anv%illvAN8? z^q$QP*i#Mkq1855+}GZ>x$522U>{p`bLD;Uy`NtFzyIdwN;T96SKrKlufG4x({7|1 z?xQI%)8NaW!Mxq zW&`1~>TUb?32}}}4uAxkNe-0HYYa>&0g_@f&4Kip&59kZQUfU4X2t{UbL&d}_W;&k zr3F~x&EyB-XaAP~FR3{JD1a$JpniU{{->&W0cwG1LLje!X~P0FKY(q}M(7`lTNvPL zq1Qux;)Bj-;6{!|e4Q1-V^*DTbJ~)wP2rlHF-6woUq6mN zQ!S$~nZlUTa9y&bIfppWY6Zplhd8D@T$_K&BWn|4{EI-R|3c0RQ!DAvSq^EB&KwCM z)he#hIoC+9lN=SeMrZFgSs(c)^Y6bS)m2pKyegSGah=YuldKbt9GO=2SF35&1+6m8 z;#ytUtbf}zO0A(?|7n*tOpgp}xn>u&W_sOZgy5R}_s*2{l7BLbf23MZ)h=2!Q#Y>L z#p@>P_Ro=H1FgFx>rC^wc9&+}zwH~VHqyRJwoe;)W<)8kHgOHJwT5~fWn|$RUiwa! z^^<=v!kqbw)n;llRm`@ET1Wl!3paBubF`LvJ!N}yEwjJ9&#}#KrJ6ZbQ|qa>`&O>0 zN7huYt89C&Y0kI(S=+z4x}Bn-JjYn^-L;~Zt=eyW}8 zYHPi9IeCz4o+oRr*ImjA*F5*j$~nr*!&E)bRM)!eGP8?opQmfD*I&vF*FNvc%{j`> z9;%<`>TCUV`Ps`Hco2Q`{Q)zBTmr(B*1BbK(^_(Rq=w#hm1S**Zu0dX`(oYqpBsF1n08&)j%bZghU6 zoG~}vQ_jv&)?Vb+@w%;}w~sDw2bm+U%#qHMlsV?e`^wxo%H7M{N?yB_^maN^_FAh~ znJcf()xY!gI`ifA`TA$hDyc)vnNQ?Q=S@Zp=FEFX4at-FPv*aV-9x>_t@e+lF_+03 zpIdh40oiWM+dq}|#$1{2$^7qxU#;HZuJfr~Cz+I;r|&-AWBz#U!J()k>s-C)% z8iUIR+=4#210Ii3%Amts`fi1lJjy@D z(DNy`rq6Fpb9*wMzP~*spZ^?&KIbm=i(RUB>Y2f)y!w)P^_#rv+{%!|y!uBKmYm8z znFCXE^)us$|_)+HD@AIv5E~T9L_U}@Dj*@1@~^yhvxnC|r6MgGeF*3lp=-dI z{{VrLKK%W|hI(BB^)d5@En}=;mI#)Jzqf_iIzs6My)eq9ZXxs{FvrUCwaUy^(#mqM zWUyoyB}0_SYAI1x0s28d{^f^ut?p(p3@ z#B4eAgr}JcwNj(?M6jf=q+Fn+=(2L=?_Q#;qV$En{D&{v89DvX7q+4cwIcm{MoV(D z#IVF%M2XR5Mz^No^oHJCq&M0fX;JisElRhci+Rj!RWVixmK>IxODH+I?C76lD@A|k z&n5b!9g@~Xf7rS%re*#6&loMN3`-D8P&P`CE<^hCRgNCfqilMlU6PhYkJ!@w-L5X> z*O{%YpH+b+i6toqCCMyHbcto@Qp(V|{;c^w&9Kg@#OlQAl*8(zE0i9>tI#Pr(DR#bdb+ha+V>qwMQpHl`p;Bd*D|*Fpm7UUbzOVV`&>qFA#j54Os--KJ9^h-x zFZ$(SzqDgA%+oJ+$Mbc%obb%SKE|ra62=mi3nfgKG2JR_(=&ROOP*=hq-D}Gw#=Ng z#{c?SqjlD0Nn=UN#geAWnr@->=^K5^W#6=O(n{$YTj_tbLr?s^(NY_-#IeNXL5b64 zPPf*^^p4);k$2iXX|eQufnu;l5or(14w`bYor*gx%{v|jqh z)_bvS)02PBXu&O60$Bp{p#K5IOKGMg0_E9@2t(rcvRbOg*&5b{AwCq@xNR~)1D3Q8M>ek(nUeZf1@lv}f zEu3Dmh37^~&hBd(t-Lc!CQGIll}ueWbxZF`Kk28J`KcY1)=od!+Oyk+bMxzr7T=vE zlqJ*)OQ+j8y%985EB~_PIJp%Nluk_W+ zebvs&C_rC13gon1=f&3>BSC+bSe95HD6zWC>d{~zy`{H4;;nX9Mg)4x5g{*Hyr;g0 zF)9pZ$z{p)p^~f1t{xeN(qH=PWBzJ~Wptpw934E>*7Ndpj1giuOE62Y50+qEhV>{h zk{;7zAN5$fEF%Ry=17s3qkyNsmoZw5W=UpA_TiGO%kr5KBi0&ApXsxY`}}XG2;JffnL*VKk-_-EyqK8&Eui?;4l9e$Hj>(*?yB&f6+6ipTn{{59k}}$@H6k z`%&rEdqW(T(S&~cPg~Zx<>O&xj3`rC!db%ou!PGtH%FBOdQQ*%)N}2+j4bq=Ba1(e zIGLl%bSsG^oh99mOS&%W`nDyRzSDO<_gy3@LvulInA zKJ=fXPaupu|Ne}|2sDo^fGr>ZTYzo@dK8+^eZYMXp!-1Y1sRFB4>%J2dt3;lUmK&* zLbe39gaB>{x-IAtX)*T$_d|g12fZg`RN{W%s1!(}(fK}W=ExLdEn$mbi(rd5?ST1j zel6p^;J)C#$aFye%kA739HGuPRsIm?PL4?icPCj$r@kfF8xTUsyu}saIt8vl=7WTDF+~EHBwzW`3Q2 zl_PUBThD#NeZ$f0q8-p98uyKV)kOBV+|8#ks%>D)x#)63Ept~(Us+#sWZTI7!~MgN z?UEhPqZ{`RYpSo*eQ$c7#t65GE$EWVk2j@~?urpVJK555t(%e66@?qf^Lw{pm>;eA^pKXPJ@s84Y}azAoJ z&36a%sLK7w8l4|Kf#36=-Wen7ezwSbFOSsopLz!BdYGf@v)q^5mmFQa#sNLTa$mAm z2Wo%v#?Nhxvd^<+dQG|XMpgKp^1gJNBkhaapWL4uX}!(?J=$`A=6!u+PvV;YmjlL# zdyp;E>&oYUrH{WK7+c&NbzkN_$MK(k(c{4FlsY-FW8Tfp;Mz!%pvYc!6v z-r~OHzU64_GY*)0_Z{wCpUImq_6fdc&(90y{(X=8m;0B!*XJBC_wWbY!#l5x}pUtB$_7T2k&(9OGpHC?#_cD7DYnhKbVEi@l zr)o>D%&~Hf?w-DWhHAo zkG8(!9_JqCcxmA5@tL9d|bo=N2rw_U17+=?W-3qdYx3q_25WtV< zuCxB+6u>Ef7XSh2fO!%47wbSkI>1ity`4HQbE8iMtON8RFTLaU@-E-9E(mRkBLPPO z9t{H8fxpKB)&lN>fZhijQx2{EcUg;wT>qP$Mf%|~#@68SvM~?`O6dWlyQqX}5IA9(@in3nN zl?%Ay&25kGE$_xMeH3B6$h$SC-&|{7b-*~1xH)2Q#NdcQ2QI<^^Jr3>b%V}agfqU{ zBKf{OJKpId3hRbv*Oi`fJ^k4Md(QngjyaV$ny@Y9pe=Db=6pN)!y0BC zccN@nSW{S2SX1bL2OQAH9@Z508Gq=L{0#Z;v2pyV%29=F$^&hR+dBWZwKwFzJO)Lv zwy?Iaw$K3&I-rk3tS#&}-q7#(9{k5c<5*OKqYK-X2iq3Qg#VO@oaE9x9@S)xVU1yp zp#!<#fIcR%#<1_?q+juC>CgEbFpf*LIm)n&O<{4Ow$ob69ieKpr@tk5#NW z-q{z}ubCHrbHF%WHRh^Wc@yP9+KVcW~Yw#O}-y)El+>t-ImTCxVQ2C)XwfqZa4AH!IK*q8jR$MW;| zhSSDztTjg=w!wU8gDe%kQ7UpfPv)^KhP8;bh_#3gFjkFQV1F64l5 zOl!x{h;1<++v0^ZyhT zHt7Xz(wnyn-&@|5bMqM2nYD?viM5Fic##A8ILF$QcRhjqmupQ2{@VfLSl5-K6WgX2 zwM}l{|K7fVutw(bt~+ZKYZPk~9q>X2^f8Y$ihU~(`Z7PG?|E(<_j+=aVjK0sHp;T% zdu1gza%LX;db3usR@SYZhx39q<7M^s$gN%eVUv=LhC5P#iFhhXXlkvCaBGn+=q$$?V1d8+goc`mwas4%% zBN#_8j$m}a2OThvk|SBi=&%nu%(2RU#;Tm;QXeT<$LK>&JmS~VpZs*dI9iV8NXC(j zBN-j=VF$8~m{GQ|tY>uDhh5Ikv4G#(d&W|I)MP#Lo}6%hFc)+ndkz>!&Nz-}9ML$U z(E&ejz&v_RU|plre&94moa~J_{(PSW&pXFieZ*zm^UnNm-!Lz9!1E3mN8L1zd>r{W^3j0+a=<+D&SCwd`vK%W$0^T` zQ@*&S`smC0M<0CAU%qF0n-d3&Bk(+qfE)oi0@8s1bih0c&u1Ov9tglakdrZjU+X_( zs6G<24*E|{xj&gpI&f(Y7)RrU90@rRawMb!0qlTzL|)8#$h{E2dx4|WrHxYlx?cLI z%z8*4{MB)OF1mfO4j4z~B^(hsB638e19U){N9Sd%i`*036Lf$MoOVDTp;;Gs%(&QN z2LBvg@plJ|qx1@nj2ss@F395Dd|9#1Ntb=dYQE*^n+_b z2k5}L959aLYdKx-&-FT2>mlPvLI(oR0ewVg-3+|kbH6j^ zbRc^U7)SLD96331@|Z>k=)grgU>?~wvVLCly0KknuU&K9xNiRDfIhmje$s7!bDN)s zPUp4*#u0uKM^KKSJigHZI&jGjm`C}|tfQB_e!1P|`1%~B=zwoHppW#dqrQXQjvN)dZ&YATn3Mc)Kp*v4Pw8KN_{Z-_ z@BGOD~9mpF8 zjH`xS9C{jII@^Kew91KD%Hti}6Si&={~577ZS zkZ%r{_4p~)<9y2l=ZWmi6I?g0o4+}bRg)ua`&pA&lQ|#J0XmTH4oF=-rJStEbTQvu z^tYLZpNDgNb{sH%#Nt_w$}CH4O>}?`c!dMzHOBL-&0dj{?6g>Z4M#IN;C~M2>kQUr z|I01+D|1Q*eAfY+z3^N1@cO4zjO|5^&K#Y2q@@FNz^fd{y55Mg9b}F6s@!n&@!ipf zxnu4;>43iGV2!3%p7e^ZMW5(^XB;qoisNOD(j29E)TIM-z$+avuRUI6t@g?saV+u7 zSi*JWI{LZ;`uc;lnlAgg%Y6TI*q=S;jlvopI63G3X0GXg|2SY=r+mawoTE68(sY0h_@o2o zwaO=~*DI{$^e87D@oVW19mrn?jBA!pIhu1c=MkF@&;g%z zz`SnxoHgC2bII{2f5#)PKiA(|9MIP;tm$;pTb$(kpo?@M`wke_FJE$0=cvx3Hyxk@ ze&K+54f8c?yI794D*dKjCo?7a@zrYt;3p6*K*r6zCInJ1NrZOalLb# zqdrG{9_{G>9S8^q%xj+CSo;Ga=N!56f8=5gm;-NcKwtN;_R~ji@R9F<9@2rlalp9t zIlS$Q*NahN1D!M)x1oi~>1Uf(m0^R|AZN#3ynZwgF2Vaj) z(E;Ccz_>mN8FQ8!4rE;;MFu(88`v9og+K@B03G<-0ezjs-oW`I zH|7t%CcUBqzUhE*tyF+V2aXIJ8|eTYpaX^j=JirIdj#Du+~C;fn`0mI#=Lpj0e#KH z9znM}?G|5;PSFA1cfh!AD#W7%j}kme&;dF?2hQO@*0obqPy~Ag9XW?190`4YBxDYm zLr*xMubisf=3HFKnLi+1spK1qulHnbmaoBaBTF? zv5|RYUN6-FeJ#bFL3b|I9sYSbLk9xS0pohAIFA}UYVfE*2j~DDxCjT#YpN3L9dza* zoZ*NWcq1lr&YYji0exM?-a$Xk~{x=)fg7kac|( z8B~Tngzj8|JLein$T+IffxvS>Ut_U{1YYjB-41MYps%;sOZ+3B+?UKF9iRjG;Xvj!SF4~(Jeu%m z!lMZtpaXOu2M%OicSQ$PVNan;IdCaIMk0Psj^cE{`y9~MUhFB}mmBUE=7bK=0bg^# zW{+rX53hep#ROI5QH4hp9#!Z79iRgqa3Jd%EHWsHy@gJBz$srFulRm>B%lMiHh3>}~YbRZWTFt5$(ve(eD zTyTuzV9v%tt{>OWUmVcaXY4g}+FzXJ=b+1U!2299uF>lAXv3ook2Z9G4$y&IbRg?G zEjFkjdk$U8Mb|iTdf&*&oG>T(;egq98nf@P@38OC0Xjej^1y+t-V+tnl)Z<}<$-hg zF=O$2a<-=f-sgb+kplJ}@5>GM3v)sT=zzaEVEl+da~^$o^x@Hm4$uKQkcSSK*KaM^ zgXmr!y63NB9X}V3EOg+~9MIQr>_L~dZuE@nMF;2r9mu%@#&uk49))-m;!%hW&;dG- z4-S~uaxv^hbTA(r*$KK?h`Q^T4Ug-cG z@I?oVYrU>KI`QblqZ1vV19ZTP9LT!fiwf$_9z{33$W31y`S_lBRG|Z&cR*kBu}67+ zZRso5ln&4VI*>C5jO)IhJWBB>#iJA*paXQk3mwS1_KOVa&0a-Ez0gsPqd6N#xqe(f ze{n!x|FKumX@7B=pMx&b0snKrxCZRYqZN-{)cxi(Tc& z?0+LObIP1%$APTA6%{m)eT#jIeTxpz0XpCV4(PwqV&CHIlbzXzUqf%`03FC{2QvS9 zt6$Jy9=SMb`M{`^*IR_&k7bz-c&7vU*u~!Eo%!LuVP5C}9iRheI}l_KZ)p$50j&Nh zwJvBVPhUKJ@$^Lp=l~t?AqUJK+8E9rMt6P4T~4KEPo-QFu1O#|pl=e{!{~n?`p?fy z@9BVVJ7D}U$4DN_Rn6=*@x>v2j~DD@GS?7 z9|Vcx5sjmn507RnJ-$_Xm@nolw;a&NH1;$)mRpYTb?FuzpaXg3z(0RLWCBlXJgxDx zMhEBs9q-7K3 zOjOWRp5!>e`OyT&D&+lDh&f`8^1=aqnq!ZnZ+YPxzXv^|19TuS9SAi~bZ7pzLpKH` z@KDD?9S?PMfDX_BKXkzSw+NEh>*%;2I-Zw9B)=CAEp)(p9ncq<>~-FoBkmvOh7QmH zI*>C5GXE`u)SzS@?Rd1~(T)z#0XpEv4w%=ODeQT4-H%=8c$~BGnCr*&^A`v7wI+KW zo%R=}`8nt^9iRi}b0G72vsO?lk9s`n@u)`!=l~rE00;DOkA08h(fP(Ba=JkW=zu>t zaQ1(6C5}aL-*%YC9!U2C$bAm(zBRZrU(8o-IiN2@*#qfVZaK!+rCW4>4tT2r zng2FKYS4Th1$h+YQIHPM0Xh(X4w%=X3)u^~2Lf;pc038Tm2h8izCG3gZ3jw?rII4TksLot47y0Rc zzBXk~q=)(GA-^~MqXTrn8yv{IK8*=l#-k#SiaaXP0Xjej=zub>QCF}xa!+ti&;dF? z2k5|Q2lRC+dn2zhyx}T??|~lD0XpCf4j9*}D|vL}$jFhA4$uKQKnF4%$huyQ3|hq= znYk|BFuw3TaEzt{bbt=zzXST3l|3^5bHV+<9MAzeKnJ|b0pq&$Djp?yl;kxF9iRhr zfDWAHK-RTuRM2Yn%Cpvoqn&q+cFYI!K?mqSemS78U)d|^V17Bs?@RaS03Gml2aIdj zH9T7KXvymrIzR{L03A551Lk$?TK3HIu9LTqK74;1&*=aipaXg1fWDSx&&-?krq^6& zIzR{LfbTkBT+goOQIkhaUdzw{IzR{Lz<)ZBbxj)^w1K_zKi7+6qVJB0%pG$_2k3w& z9mwjRZG$$lf3kma=A;93fDX`si*_KZheii&Vh_FOb@SvL!`I?mOb6%y9q?TT^p6g) zhx%>~x&N3uIzR{LK>j#jvqv1Thu1%)S_N(9QItnfUgOXKIzR{Lz$H77b*&o}bTfPD zC9fYx!2B5jx$azdIzR`!%>jMA%U()1z0FO&A38|~=zy;{koj+n#s=NWqbZN3yxyS$ zbbt=ffowaVkEiUX90Pr24CMQyt8{=4c%uV2qT>Hg|0L2@9#OMBmUv@o`JPyE=l~s{ z19|U&`BO=^v#+wR^2&z}&;dF?2XgFyz5-@n&HK5Avn1D?4$uKQ;C~Ke{FbVNRJ-IzR`q<3QGxaAeS3?62&vyb7WNbbt=f0gpMLuZG!QIiqD~M&sAe z8#+J-=)k!h$h;zMAGDoESdWb@)a~55ab37Bbbt;7ngjY6%N|Sj1I>MYUOG<)=s<2e zfd2&lN2mYA*G54*c$DQ)mVXOF2j~DDpaULvKp$t>XF1m8_E^W)r(<-04g{hD#*ua> zkF*{iV**hrerA?ZIzR{Lz}XJyV=a5_*=s{zxF&Rf4$uKQ;0Xu*KH9n;RVwH$^@~y} zOchrJRCU!zja7}+4XTMcq?%gcs+kq5np^W!3+qAE()v!dw^dM`ZG%-e+aA^3c2xBU zs-b!Yja9vZHmcr1ud6=61ysM_v8sRY9yKWBpc)*yQVj_`rbgH+tC5bwYE;-SYP55J z8WUb$jV)MBjVm}q#T9&9O(=Lo#TP2BrbSFp2}S-?N$wLWx%g_8QnIc}E4@g~E_17z zQ}$^!zg#V~pxj2au)ISpDxazrm;YR4ROqXgRM@AMR;;a-RotYOS1O=ZR7z8qSNc+| ztlVE+QTYb7s`97m$|`@TtE#%y)zxaL)zvnrYodbGny3VIZPdGJZS_uSUG<05`Wlth zbu~7r4bi35&CwgxEj3H3TWfAmTWVdVZm+do-BJ4`wXJTjy0h*wbyq!yy1U*=wY`40 zx~KkCYDa?zb#H?;YG*^Yy077Sb$_E0>VZZZ)q{=8sD~PFRu4C+pdM*5UF~Y}l-k`i zR_$r}ta`NBY_+%9AL_B@JJjPX#;7M+y4Ajx>(!I3N~ot=ZB$RUE~ECh-mIQ!Q$ao3 z=2rDwOcnKf%~2-tKgtdZ)8Zz1z8;dav`F>isT*)CXPOQXh34tUm7gw)&*o zK=oPoE7j*c_Ny;?{-M6?m9D<(bxM8Rdy)F4Pmns&r@#8P&s*xdz5~?vecx6;^c$jn z?DxLbJqu)bE3TR40bSs6U20 zp-v5LZKQt%73)S%t>DYZV?l%!(NMp;ctuD68nW! zuCPi@_`oU^Kg=o@|DIKT;&7|N#E-0slSW&WCw**Hn>^Brn*5f+IH_#5;i^o;U#h#ZZ0nRG;uKi0ZLum>M1chbM=3`U3oJCasH#}R z1{M;$5G)AH5j+_z7|b4g2rLAwK=9*WpkHN};RdiGUD-Tx1Q2?w0SY^kJU=_itI+lY~0*iF~0ah6- z%JBtQ6|ibyRly>`YJ^3ARRyaaChJlStY(<3OB7gife5hbV70?efYku2RiHIkG+5mN zQD8N}>J-=jRtv0tfyH38!Ri(G2CNQP!vb%B)dg$dOaiM1*4Q}|tUg#H=Vq`5U`?GX zz#4)zasCF@2&}pDQ?SNh&BA+wH34fG-W;qcSc~vQV9mf&SX;1;g*t$>1M5)eak%P7cLVDkAwG8p z>lJY~SP!ti5$nKug7t}z&(RC4e}sIF-eCQ(ijE?Ezy`vVibeW@4Jfh%tRL9mA_-vq z!3GsA1vUU|XwhJ>fnY<5b_N>+HoRzku)$!%irxk`1Z-r{tHFkXjd1k=8wNJo)dFld z*eKV%U?afBx~>Ns2{y*{8Q3VWIM+*Hqrt|x#pf|#6WrqSSg`TMN`Q?6n^?>S76%qz ztRvWXu*t>hf=vLMRBR4dJlND?abOd{rW99TlfV*+9RZsRHm!Ix*c7m&;>EzGf+ZH; z0X7XRx%dXK1hDDFKLASvODX;=SQ6Nb%Ob$0gQXTf0hSCl^Rj7RGr-a=8w8dDHmgK? zu$f?UO4I^N1)E*sDX>{!^Ga+7O9Pu*vMbnZu=yn$g3SR-FF6xzF4)47qrm2YEhxDK zEFEld$t%I;gDoogHrN8NB_*E(TL_j>Y5>?Guw|v%fGq}FT1x!O09#Q?{96LHyz~uV zOTku_UJAAh?DEntfGr1GRr&$26<}AC{uS(Uu&YWR23rYsWtsk9SAeZ9(;93Q*wtnB zf?Wx=rp)bNSAktq<_Or;U~9`90$UAsZCT0XHDK$@N-o!ctt%^^_gb(GW##j(1-q{7 zCt&NqHkN%6Y(3cZ#6l??74drD0t_Ry(PS$TD*p21n^=<&WxtzS-Ca{~z zJpy(k*sbMm0ox3AOSw_klfJ;W@DT!5*q8>+%5Dt_rd) z4}v{Xu^ZS!V0$Vy0(%&2cg0k&N5J-091XS$?9qz5!FGc^UU3W99o(6lq z(p_Nt!Jexe1ojNri>$`Hm8EyT1onDm>D@1by;enf_bXtBsz~pC73_^FQafJ*d#j4n&ey@-j1(u| z0DC7=oIC{fcBJgzH^JVEl>Pe_*t?O}gS`#*L1YHlJ7Diutq1ll*hf`MgS`j#Vb$Sa z?}L3(wIkREU>{e#AM8W0PpfVM`v~lCHF5W2u+OWByPtr4RxKIqFxZ#XhJ$?y_C>Xa zz&-=}y4p=(pM!l>O+5Gl>_|27;7hP?qAGxW1@>K30kE&ZzKxQa{SDX;QBt#yfPEiz z1=zP>KSj+1`wr~Ks0YBl2Rj;dBiIjMKSv!0`w{F|)F)s+f&H&~MX;a2j#qbr9R>TP zdK}pQz<#UV6YLn+uhp*x`vvSo_1R#@!G5p)I@qsZe^%cM_8ZtA)lY!^4)#~|&%sWB zovaa~!i)S7ane#XYN$w@qPnY7HIl(jg4t>eRMAELQr#`9#uH$tz=CURQPD*eSWu0h zRd`VgEVRa(U^cLj=oVl>V23t|1y&f$U2_vy1emMl_h3c9 zir0J%tSDHqTFt>+U?pmm19O92R%`QD_Ltd*kxd4YTXD{0<3hcAHYh2 zm8CX-7CSOz@qDZ1Xdla zcHO7IYJkWv1g1y;XaELd%@diCxBs{_`s-Zfx#!5Y;26s#Ut z<9g46)dy=-zYbUfu%`80U=6{V)Q-sN(H3w_epaED5u$Tsyfwcr{(_kW4E3kGAFx3`q4c4~7Ltt&dVjEl!76aD4!4a^w zU>zI04Au^;L&GLu?ZG-XEDaV5)~TW7w*y$$hLYcoU|kwYemjA6Zz%cg4A!lo)S|t?g`eX(PLn}!1_131*|t%zeY#F`hX2= z^cGlOumO$Rfb|0#+_*AWf3QJ~Q@{p*4Q)IaY#`W>#!rF`0vq1=Hn729!x|q48v-`6 z@q1uH!A3M`4>k;Jbdzde!@)*1SqnA-Y;2P>u#sS6ntTB^3M{V43t*$c#x*SkHU?}$ zlfS^mf{kw)4>k^LV$*J5abWRHH-U`@o7{9E*aWaiO}_z)2b1Do4Iay}buehbO@ z9I*73;>%pHg)POGd0-1#iZAJ4i(85>^T8Iil&@U?wxp$e?Lx4Omg37Iuw^a9m&IU9 zTZu0jU@KaQFH69dw-R5Lf~{;NzAOW~yp{N}9Bfr9@nr?r6|KaV%fYT{CBCc#yRx)Sj7b{*KJHg|$;0K1{h39#$IHn;f*Y$Mo>F`d9} z0J}LR8f+8TO)>MpZUnnEW;EDluv=nY0J{lnYs@`hH-l}7`3vk8u-juk1-ljOwzl2C zwt#JGTL)|_*d1*bg53soSKBzS+rjQ^`x4k4VB6c?2eu9D?shh?JHd9e{SxdhuzT9| z0=pY*XS)Vq+rjQ_CvMyWc7Ho@V+YuM?Zm5l!5(ZUUhM>XpuKo?AK1g~#H;(k9%?U6 zJ^;3>y*T+G*dy&%fIS4Zr~Op0hrxEYe-rExu)XbfgY5!)G`0ZPZm`GO{{XfJ?6KHE zV2^_Bi){h67wn1HRbY>SJr$b-_Bhy+vG0OC0k%K(F|d7LPj@H;_9WP|u}8t40(+*z zFtDe=p6}2GY(Lm@9ae)q1NLHv6tHK(Ug+>4*mGb9J3I;YJlKJbMZsPGd%44LuouBz z>NpDQ0NAS?+k+hhd!?h)mzTg^?`=#Nz+MG=qf>pb*TCNDR2=Me zus1tpfV~0sPN#UVLtt-rIt2D6*n6FJfxQLxZfEJ2Z-af%S^DKWVDEQM1$!6lqs~LY z-UIuv^W9+YgMHHZYOoK$KJNS**oR=BcK!hDBe26=YJq(W_IZ~gV4r|})@2UZVX!Z| zj0F1>?29hj!9D}~y31;?&%wUxBKznIup?b$AAJe-P1o9BUx9tswJ6xvVBdC?ee@03 z4_##+9Rd5ktMt`x!G7v0ef2xAAG`hv_C46quJ42W0QPgYnqWVI9qSeW_7m9uy3Gdr z8SHqs5nxBbe(AOY?0;atbz1{=4D8qL;=wOqC%TCT$H9K@z7yH~{t+Ztbm}Wx!5>1@}}c+NHpP zdSaiuEU?g?*yk=ASV%9_aaRzSqZjJ9D;Uh)3wy>D0#=|G_KYhOEUeefV0N(ZUQ56n zV9s9HGp;bOLcOqOTm`@i_O1lx1dHe$3KkAlxHtBUs~}j>-q={>4uws3xg1Nv-^eF)52D_}!EU;o=rTPp5D-Kq&4?J*P23DpI zJaCl&E8XXJu##Zq`g{mh3ao5j%vY|`U={jezH*fTE8iC$xXOZ6>I)BC<-jWTg$J(k zU{(6U16KvG%6(B!T@}Hq_C-B)RRW9bhxy7?87!(F<||hfuxkBeog=|&^pkb23Rb-z z<||h z)Kwd-UVqG2t~y{1`(wUx)dg!X0QJ;W53F&2)Kgb|uto!#fHeSXI-oRIL$D?TP)}Wr zz?u(0J#{q(Yc^mvSQD_818xLs3f5vE>Zz+4SnC0(r>^E;tp=iBx>|t63`DIl|l5c;L76Ik~_=$Ed}VBH2|AGx}K^&EtKkl?)$U3kAU_*z@1{(-AWC&(&*C4RrLoj>027?V7>INGEHgd>s zU_-%13>^bD3~cn!4q(HU2$lpkV?0qfN zEU;v-nIk5H%>YXq(Gx5MY}SaIz-EHY8Ib{&3O0MhcVM%?=8bq2EDdb#$ckXI!RC() z0hZ-CD@wL=y|TIz^)mMp69w6Z0%_DJlATlYsaAH zxvl|QKL$O|wFYe681y{XwO|{@py#>Pf?YS}Ua)mw8^>G=wjS*IF@J(x2exUJ9}_WQt|j+eE6671P{S^KBJo{2}_cRdaEd_4NTYd_d?@h8Ea0edn2FxazTFHFR2 z=6Vk7;6%)3uIIrHOk4o=0@%wF$AP^F_R_=$!481EI&lNoL9kaQSzs@Ly*}{^u$RGJ zo75QW6|h5-N`bu!_QoXXGp~WYHA(u+>tJtAl0NeW*gKP?&m01Kd$RPIH^JVUBz@*B zuy-dn1bZ9ogUKbp-T`}m@*=Qz!9JQi9_&4^4=0Oj?}L3ZSzP-7?Bglo+J|7DP8Qcb z0y{iKKJUk1pX0A7qFtYWeKtit?_sbnr^x616zq#B(pNtN`+AD>)z87cnkue+0d{1H zxb`L3H&ey6ufV>WDz1GE_U%-0?HjNkriyDvz`ma{Z(x5UTm|+!*k1|BU?;#%COi%HN5sh>m2d~xpJ1mFBfw6A*%FR{ z{iV7GS&5hvU8lf;6EP>c68Wrxgz(NyK!E9h5iTlBVz#NI&z=FZ-NkzayzzQV( z0u~Aumed~14i=tN4a@=NOhR9Ehk+GJLSJ@MI@oGy2HT=PcI5q5Ugm@ zaj-&QMW*8%>MjiCo{n>0zun~rm++XYr)I?kbPH`ry##leb! zm70D6tTi^nnNk}p3M@M1IbTuv_tIu-7^n}fAVMIUsx0Et-;#PLLYRu0gIi5KIo1CYd;I_y4!+voCSB??Z7(B`UR{#Sm#;q zg2jS$N^1w!0jz6URj`g=UD7b~yE}n(Ps7ab?hMu~P2BAQ)-z4q?F!Z-?KoIBu-<9! zfprJ#HCx>60oHf6xZ4w~&unq67g+z<;#zO8ezV23K41f9i)($s2FyW^clQGuJO@4A z-5+ewoC9D3z=qDb7i=Kdkh!Q~?m=L~=b(nU2ZIfpI~r^V*vPrDU_-%1%tP&T4+9%L z7q!zp9BkA)%;@eBU}NWDMt6?{8#7Pb7zGwLPuv&{HZC1C%smEdLON=gdo0-abj(BU zabOeEF%P-pz~a-lfsF^7oW2Td0@$SV55eNWrlvm$HW6&f{3T$Mz!K(91e**tZT@bs zDPT$SZv>kPmbjoL*fg-@1r@*&z@{&l4weX(vS0vM64;Cdm~-6I!BQ7s&T%J$&0O#a z*bK0=1^dBLz-BF64mJ~P&cZ2RsbI4g?gg6#HgDn0U}<1;7qtPK4K{yKWw1G5>5Edp z=7KF;G#G3i*n&mBf~A8kUi3cLe6U4}Yl1BRTe3I;Y#~_2;@Mz}z?Ll@0k#-y>0Xjt3OX0kE}T*DWmzwhnCLQVVQ7*!4>XfL#Z+X=yXC4PZAcy$S4k zu+2*|z&3*2xbzU%4PZAf-37J@?51Uyi`_SZ-MS2Ov3oPvEz1(YZUWo7tRL9TU|W`L z1-k|8_GK%;ZUwt-+0S5Gz_u-W6KpHk9m^|&-3E5oay!`VV0SK`0d@!2_T_`Xwt?Nf z{2{PA!FDXa9_%i#dzMQs?*`ksTynV`>|Ui-py4kLB=K9*-4OWmN^g zgCE*a)$oGV@mK?o_={*&3y*d1SQn4=@z?;5jqunQk4^E|4391F*bnQXw{Y)JUfOg8jy zHZpuvCL0A78u59=SNP}a)9>ZXuaEuf*C+I^-4Ch)c;_9$yN34)?;k!Sd?dd1Si}kU zQ%V(i)KWoLIIncZTF%RzZ7t_)XCuqG$l1bjra0?c&TE`&EayH6&qzpjHnp5fovkhB zILB*BUFF!U)YTGJOSneD8VT1TShXb7mQY7RT?zFh)R)jeLPG?#R>C?7>m^(#VFQ9y zL!MnP&uYrEjS_BgfIyOBse96ODHIzkc7e#A|w=%P*j3Tf?Gl{3B@H` zCZPm^qXtrIm6TtWl2BSg83|=2l#@_iLInvGB~+47O+sY}RU|}8sEVLc5FAw;_@N$$ zBTPApIZ$$1I#A|f9H?RSAVHLwFsjw^VTFXtC9ITig@jcSu9R?m_WIaD#+R5^j{RS;9>cZkBM1gj*$Sk+4<5Z4z#maEF9#67H06mxQ||Y?pA4gdGy@ zMQ|3DP)L5cQ^I``?w9a@ga;)&Bw>$)hb25BVV8v65+0SXSHfcw9+&Whgnbg8l<<^< zrzPx{@Qj3KB|InLc?mB_cu~Ru2?r&-B;jQVuSj@R!fO&)BND!q@STM3CHx@a zM+rYk_*ueH3ICIDOu{b`j!XDe!fz6OmvBPD9}@nQa8klw5>6pFl>|$IO+t`_U1T{c*UVjNmvgrm&NR(d=c48;T%P;%MFDJ;ezIf(%%JDRU zbA+-QSr}`sMzDP>;Zq4;NjM_m2MI?d{3_v3gdj^oD1x;{o`p#$B*7)2goLsZDoKcx zP(wm333U;yb@Hr%gr*W&NQjZpUP5OH-6Zsu&`-i(1Z$%_8zy12gmDrkN|+)cNx}>X zX%gm2ScqWVB+oJ=ER%4#gjEvcLkFGy2&doB2KnU;5;h}PTjkj;5>7w6L!NDyaIb{> zB|IcykA%l0JcVH0DbJpf@VtZr5?+?@nuJ3V-j?v5gbyWrf?%C~<%GGjd{&m=v;lKtQtCEP0EHVJo0xJSZH2@govg<$QM zXOBwQC*f%cl8<1?NAN2W-jE=v2!3CJ$ZtI-&pwy%l>|vZup}V(sDxi6{3hWfLWoU5 z2!i#ZJS!kU5)dK@2ysb}1cXQeLL>npl7J9NK!~ipC2u1{5)e{Lf+QfMfrQ2qnn`FW zp^b!g5;`JSugkM861q$1C84i`K@x^a7$sq>1W7>1WCZI?d6p<4S;8y{l7J9NK#1&= z5ZNRlvPnWNm#_-KdPkmJEn$rWNkzy82{%ZPof0COBxI|EJ0wU_tf>+{lwar3Y8p%N{&Js zAz0tbv!)VSNr;iqUV`K(RMHbF=?U#4p}&Md2-Z<~HdMk038N*9lQ2QTBnb%;rb|eX zFbl!@MV`%(kS<}NgbWEQBwQh3wS;RWte0>-g7up`lN^OgjzVvjaHj-GN~k0yRFV?< zhy>Z8p-&)KC*|4G5+o_1vS&hHmhhT{LlWMV@PUNG5@gTVlsuD-6M96#=@t4(p8Ze4 zaS6Xm_*23u1iKBvl89I?C?2;L~WX3L;u}fy`%OqTmV3Sf{UnN2IkzMwYeVv325@a9QB}aD2kzI0R zmmJxoc-Xf~xL3mc5+0JUOTwcP9+&W>1WA>m5;65f^|*|N*-vCHnU zOQP(OD7z%eRz{vlw(OEEyJX8I>ui&Cwo>I;H3>B&)R9nMLL&)HCA5&xT7s;&O;+5R zE6-%vZQUjGkCI~e0jD=!V(FmmsnQU zS}MQ1M#5SN*Gt$W;T8#7C7fPZSyS765*|dbR?4&8681`XQo?=-riEoZd@0XOz;b*nUoprrSUJ`^ uu2YU134B~d9mjvONxR+cv`LdTExnJlO;eimq(@4DUJytrlD1e8ADi8mX6eiBvIlKN zMC1|y5fM@35)ly*OCTvy!FmfS2qJjjCyIEB7x#Mpxwr#GvNV~d_13^f+4 zQAawH^hznWwIZ2>OeKq+8Z+b8Pkwm5^NSsS4Hn8QRR-O8*Hy*n zLUfsIn63o#QVmc}7bLuN%E>48IVpCSO3CdlI=!5YE?J(z4;)6m4yt5;$Qj)@_H(*>%F+$;sAcaRR*RNEw`8virdSY~Eh-xAX>UFErx z&93knwzwr`V5V|!bBy*DHoBtDX5~uE#XQ9(BpQvDl$dWcS7L$D z_DC!=T3VvXXnQ3VnVdO)8Y*%gw)z%Z4fgdX(Tv5aGUrPyF&aCuvZM9llW0M!a=Soc zsnPaJEHm0$C6*iQZ4xVt_I8Ptrl#+ZSY@<#N*rgj%OqAC?FxxCMthgUTBE&NVx7^h zk!Um8dnDEy?Y$Dm8|{4(8;tgTi4#n@9~eGp!&ZyLi8x6$;zJS}4ftV+O-8#_Vzbe1 zm)K&ok4S7a+D9c$HrmG|PBBG&T%z4*pO84!XrGig&1j#J=rG!+1xBw=XVS$DYSLMz zXWOD(bZN|%iY}MuEI&SlMC>RY;vTeZ`{tb;TN(xCl(*Ute@^-V9EzbI53`icVm_T@ z7&@+Ej)Z`g=+3+z!QnXb`mDgTrgG84UD+Oq2k=-N)%YB@D8E7NnOsRl^v`pGl~I$Z zEBVD3zJM>WlgdUv&g&zB_W4Q-PAH3Du%9wwYUhTlpzixw1jK zsVu$`XTjg(M(Nj7l^4ZRjDVIMB8sO4s+vqAza7Ujc$R_CcdXndqIfQj=asqK2YL%& zAAGN}4@{zN-w$H=K7Obwb#9#6j~R>nN@=eseoE3$+UliqIXA`pe$G9&+%P{`=lIJQ zet}=HDLyo`SCIRSI_6j`8vR`izr_pO!~DjnjafzhVibRf<3-i7#z40Z?a)KzFtf+; zQkqIkKo^?tI3{vE@=@E?JBP3=Q9 z^F4+i73n`2|BKWA6#;P;msZ6ZNoTk?GYPM?JDtxLy;gnTY?E{paWsgCK(RLKAHp6;ErO={=c5v6Sa& zxq6d6G}kbUx~G?VyWISaM3+ZHT}PI0CA$*&w0a&)tlj1od$OrB68S{0%g$t&k?lOj zF3%g356JZ@(T>C7JE%5z<3w#1|JR=%*%+^Jr5+A|)DYtMA^lrc)DFbqYw(}3}- zPMrs+)u}kIC1bgk4A)vRSZm2pttA7smJG>SG9YWoaI7VRv6c+QS~3u8$uO)XqbH|; z(jz#Q$v~+k!=#oBl3FrEYRLepCBvhZ z431hdG-}Dfs3pUqmW+H_GVW=~sHY`ko|cSwS~A{g$!Mn~W1W_abXqdbX~`(3C1V_A z3mA5>jV+(br&c}*%2CY^Vf#TU5iyOwqjlmqp$0@62b_U7@QH82R=6_=kGI0pu)|XF zt{_}vg=gR_3%olB*IMCO)@q*}geO?x*;e?RAY5mK=U8DU2-jQTxj5I-=B^+-(F!+O z;ZzWwWQFHj;qD;ZV1*Z0;hrEo*$OYT!si9yDOR}23VT8L7%RNUI#ih;Jk<&}Bg^Fz zTvhoXJZ&UAxGCkhx|UcoDF!o{{+gMzpk$de`+}Lw7?}xcu+$142*NY1@G>iWVGy2W zg_m35i-PcME4;!AUmS$zSmBk{ala%8&$Ysyw(a|9fTKJ;dNH{+92Fyh1;y~bwPNM6<%+JuMfh_R`_@;d_xdkY=t*i z;TwbSu~zs5>)gI62rse1C*p&a&EV!B++u|{TC06a5N@@?o2>9{L3pVZ-fV^M2*S&) z@D?k4XAoXtg|}MayMpjaD}1sQzB>r7vcjiW$N8QhyxI!4Tj6_y@ER+8sujL32(Pum zr&;0qgYY^l++l?e2H`d<`~dn)$Q^YUqj;=G^;6A#_{;zvJ%l6FzTAhe4dCl0X#h_i z!MFOcJGH{K7{Y|V;9xuseZQ~yTjbi4l|q+W^jz*M+5jtMU{TmkFGF7D$LLw zX6OksoEK*BjA3L)WoYx%*M}Ky2s7Mh40;&Hgbd?N&4)#N_u>ID{*ai^kDJ5tx+TnTTXUai7`9r)WW8GN z2s7LnX1FWNaJMn2hD3wyU}WP3C9mDSRI}My$Y8(Sd2g!*p>C zW{88BDW1hF@iJydrejXzM9hus#=J-#jghM{KXMlqL>|S$$a83lyo5znW6)eR2aBuL z;n=E9EUDUumZ~ezT6H^?Ry~a6RZn9@)eBfzU4>QE)3Lhx1gxp9Lg8i_!i!5_vzaX!EZpkCFJWJFYVP2Uvl`tUH$MF zEci8pKRj6qekNcV&Dn;UP=#YtXrZ zV?qOu5Q1MO_`?H~;CBoD@MT=^(-D7on;`g^h#Id3cpI*Mc-#^E*u*rRjs-s_QDbNn g>x-Zj7GD)XR zGFc`~`%)@`0xGL4qJpw0C@3JSpaKH2C@LbNAOb4jf`a0Lh(G;*&ppp_pJ#5xmQ?2>gVs2qJJKZ{vo63&gJyn=kn$AV6GGR41BEz})rTjuJy?A$ad^oq5D@Lpe zVMV6%W3BivVnu|t+F!+<#qsQPR#=+`6w$hno1Dh6Y&J(8cA%@&sya^1qJ7`t1{ zEsD;|VX<-PMz*JCT_hvghawfx$mvizk?z@-*xGP6BF02zSwk#ZR#9Fa67fV&PZ#(* zW6VDg1Ai6s`w|4;~GD)-jg5D_(KlAEK+eMBq|fxw5qQf^48yY{c$&;Vf_(K|hPU9yY^W=**|2Fz-p7}eeAD`Cv?T;&Y z#lNrFnP)z=D;yHs?`ZE(yKwD?!y12H<5z0@_K+uE&HV5x*hy3ne`k#BH*5SMjlaXT z1OJB-Vb{-ai)Md_`O42WT|VN;@73j*ujD&*`KTvYPC#=pS)3e^wN^YeI} zfHL0+tg2mJzzyHg``HVu;d^>NYk~Dc&+-bg2`_?1%DtJC9n$zwZ(?K`2e{RYYgL9qCzK<2#X_`Ypi`ohDMmiS(*JHNG9`*}jVC zY~PObY+vJRkv^+M`iLFrS>9U#B2J`N{&*2RqDA_w7U?5)q-TFrL}!2ONYC~)z7y$L z!Heh-Ez)PTNFQ+`y>f^nz3L!4(sKnGUyJlvEz(DvNUu87TLB_Yq*wO6h#t`*eO8O~ z5j)b;3X|nXuU43d7U{EEq>tEi0%Un> z&3tyn6s{g%6A8}RytYFz8Z)J$+E5N+A0z~Z^V$j!wO0U^S9^Mv z*H(ae-qSPRUIAzV&ue@7sI~&kC%i}>)mDJ{A&sxC0P_hi(nswTfbH|1o&rZyTLI>^ z6(Fju0Q1@k5Y<+IdEV=@|Mm*N?e$iMsI~&k^Il&?#Hh9c%=2EK`PvFFudM)4dj(+o zY6akWwH08V_xfx{TLI>Iug`pK1(?@XfT*?t%nx}hKvY`+<`dou5Y<+Id2I!V+A9DB zf_ZJPAJtZX`5|uwi0UiAJn!|{QEdg7*H(b2wgSxCdwn&K+6pi~GpI*C~;PVdXHQYBHS;=!r_79XW-7p+C4RPP2l=n_=RAHzRO^QY&(0d1U-bA}b^dLSzfb4i@%VkrXMdh1 zKKpZ4m%r!9=XCykn_srEz41b!K6!iUe%<-g>-SFPo=CJOj*0S%gDssRT^SWsSCj20 zd-gOX8u}-iR@cO;W|H% z9_VOY-?6t2dbw;}s3t8tW-hniI0^eh{S_6F$JWP=it@osZOidJ>%$e1y7d<;D$2^w zRb3tFN%w3cy~%7{*_QrY>sqhvTRa)wP=Dr1a^&P-%dr~BU8|}Zgf^G4)Q@mTBn zCzty7$&OQ3JGYLXO|-Yy#3~}U*5BQMcHN>*a9c_CjM_GF_2K%wCC?Me6E$ve_-=wd>p4hla}puG67aU6ZG_70>U! zk}Bk%u553*+}VWw-#MAxS{bW4yRW@66sb5@JXUoj6jj z+^TJ%{bQNlvZeF%#qOz7n}^!lFZ3L(DBl{(HnoKs5{<`duC$Hc8eC0y zTU$}}%y3yx&xJ@C#xL7mo~+EKXBxU^bp82@wtjYdXltUSW2U})=GOhx^5E6v0UGB(rc;(xj^0VuND&Meu zs=iB=_ojQM)i^YDU>s&TFb?5J@?OWx2G~99>18V%yKOhM`XfEPJqwX_b(9<~KNoK3 znZ4S5z3*J(o$1Ep?Nj$Rted)!oH>vFn!oDw*Z$B}eSThQn;3uQhGVl--+8S*!sB7V<(>8Uv*_aaPefPjfz0h{b_1^`mL<9`dZs!VrNss7~?QK)GOkMM|WBpQn}pyTjzU4ucUDZZ;n*P z5;N@>hl*X>7LV1Gg)1Jf;&#P$#hNy+@5~(zHy=B7wQZK{jT`ONMSIG6SKH%Kv9@Ap z=u~6sdT(v>_CkGEY)xW!lKZh~=VlQp<`1pDFjJoz%ZKl6qx#zH`p}Q_Jy$xf7Y?mH zK69aCGPkK^d0->jH|4Z%W{s%moI6~5@Xp}I)b-12SKrxvNwxF9gfrhpMHRJ^=38#9 zywd`_#+E((rt*&5;q@)YtFN@>M=%Z;$BL)C`kQ*zcif)ZjCp*ad!E{x^Xx`XC0jac zE^~bvU)48#v2*tFw&pv^-*xNVc_jMw6%P*%9NT>f#3jT{)*oPfvAH2sL-XQ7``wXqiFA7v;&x`s&h5b6jjFzF;t2Tn zH$?U{bQVq~8)1edIGwtcoLFvY=zN;``Gz-s z4Gu047jK-plv+Hzb~;jX?aAxCT?5p<9uL2Xp6W|&%%)VXcUUe{ zdts0I^MvP5yXudthl<;)u5?bEzdydbry+H{KipiuTU6YSH3k} zcD8Q+uC2R7x%wOL7nM7=-8$QUwr#L%EZ!74w{~snkT*V)l@O7^rE>; z7jSa5eKEgH9-Fyv9tmT8ZtR>q zd`+%HoIV1(d=0xo$&o)5!1KMeRqIoW2*W#frM>HPMSs)oO?$6T4a;M#mqc8xj~lzk z@@vcMn#u@=-8))0bWfJ;Oq@S`sqGH-F&C<^pN#Bpj>I>0wU;$DoULBJb1ByosuTV= z5#DpTZMLj0du(PS*44@83%l2MULV?qIN2`}9H){`=hwDO&0;1% z>GOLwb&vHWTegRKdaGl%;!R^0J7+E;UbbHDEYu}--rc-8T()NG;<4T9pPcL;#C}#( z&LAEft6JX$|C(>KUP@lScnIxBd+hZJ@qO=wnTv??VKtw}`fCwKFrR1EHqyLqDm#UC z)>C^NKliG3l?|Es>52w7F0^d0=liv`nM}CJ%*VLX{HK1Lso!@qf2pP8l)}%Eo35YiDz6je)NkX*PF*^fJG`y9uE~Fm_C%;XN2}NGz0-ex z*VLZ0{~9=yWLI8lU+TSoatix0C9mS^wqj&!I_l{op3Yp@S13!Xc`(zz{^0SdYwb5s zuT#&tQyaVHa$Y^|HR`FO^=;rP=KG13byb(zCUYn5ZEsCiQv0?QHXgW+{lzh~e=&Dx zb#yEF>F`xQi5gG8c^&En-V(H*UYzQ=hko6+bn^bL?WeDHE|v|M`RR&_YP|Z-VSf(4 z%i2{tXuZcc>}@LB>a}Y(j~Dk_sB);6aB!lfqvmQ`F&`%U(fuj#ME- zpJ*q>AO6Lr_GH>rJe$7Oelvf6!|~Pz#E~I0KV1PlUF*7@8!W#wy{YSFeyz*`C&j}j z8l!~^2Ny?%TQD9mw_ge;1`w~>mU=hICithzElae|!Ry7^y~{Q0yT?x3cy+HsmGf!U zuEyi793L?b-H12++X;XDC*-=p#)Ff`?x&7dUlMgAYTZsP_HHXqQGA$5Hp3r<7iV9z zcJK;~(_XB*PcEHYTU>70fPUDm`c=gXT!$KBSpPYmtsQJkgx1kD@7GAbit*Szb`f|4 zZmJdTueQ&g#6FeuH!A(EvCC_lmkYpSx?-N^;h|~lSN2ZQJjkkfu(-VEN^0@++Iy;= z4Q@S0*3A-*54htWL7cvcc}e{}b-1>rzN!)ZMf1VN|L$w;Gx_jAZcm@mD~{B*oIi#9 z#Ia%6ze4!Necjc4xsz*gUwSFIq~-g60!?-Ihsrjek z&;HXHhy2&&b!oLe?Yc30b>EGvVaE5ZuEzRV!XMk^dB%9=`G|4P z4t3<3hF8~b7Zpb?*OnhWeYFAd_PDEkP*~k3s7w4d?q z-%ekn`?q_9SF9^)J#*KUp>49M)ZV_E>598*9D8w}(vs=CeRWgI_ErJBW8I#?edOYy zmK(F!XJWlh4AMBM`zR4txKwyTfAsDnd5#C+i!66-HT56%JKVk*M$#_=xm+;eD z|Co>Uh4zIa?yieEAGlnNeWuz^9Nvb!!6kM7gY{mlG4eM6=UbH=?Ss!Fo>#FwUjJb) z#<)iuMmkW|H!W z_}jNM5}rVNt4hkTFLBD(r6Y7-hxo461?1tVeT2^q-8Xxa=;tuSzYW+ocT7%I4@}Ko zYRiobO6;doq1ISSXW>F}t~c4zQMiaa)%`8&X0Nu7U!?sM?iaQDsBNtxI@3Rh`#d{d z3~Wq(mrtLUI?P%DF zb)caG^S%Z9qOQ;e|8*1cb}G*HO_tX;F>Vn@54bojoKWjN;}r3q?hChyD9_9FU1K9% z_a(S#`S(^QwqCDREy;CQvo1@q-u|L=L&7M3V+qvE?^%Qrpp7H$K-?F`c z`FpZUX1V+p$7yO$I->MjoH&j3L-}jxE7ba7_Y>mpI=i2as`a|*z_yw--HYST1U`CO z7Ac+~FNS_)e%9kh6@NGTZ^v1`vHo#c7LgSfh)I$^*COqx&6}{ z4?!OLu_G$}*l_{-G5@tYeh%JgJ+td|@J{Pc+U`f%=cu^vzXtx;?$OrE$m^(e!^VXg z2VZ*}yK}dOo%T5Q7tc6fvnc^ws(w)S%hOl7m&y)sKk zhw*!q)=4MMs(lvrmpq=lUbhM!Z+o5qKYTrKr4#r$cz(By2j?1b&ercPOl>uR|$xCwFW+Um~Tlt1elsBc2tI(2{Xd}|}-3GV9(7f~KA zu3M${r`We#>7K>D2Kia$x6%G|{k_RO*E*IFZ};1FXn)Fi+)Z8A^V?|OA!;(TKcaa$ zJaB%`df<@vJ%tS8pZ7iWopUPBwm#wPV{Z22{tx++iF}yXKmYuSsd@%3buJ!TOY0il zFT@tq`nUex_QJ)~brmOo-!)IFalFI(@38Bix=%RLX|IcIbYEWI#q z!>I@NGg8CVcD0Y{ynXr71mfC($*WigPhEL3wA0LQDr>jn9PbO~%l7%NaUZyu_PtuW zIX@L{GV`$?@41Bi0guOg{zUoebot)7TU|VE+2PgENWWO4_G2`T{(X69m)bujXZ!8_ zIPyqXujsxj?cN{k;rxKYbGl+k@u$Mm=c_IqC$lL0)45`>5mCM};;v z+&h07csqvtK+UEuJXhg;J+84nrN;Uv?R|aqG_4Dhy|n`rM|qqve@1F$`dck3-&O0z)kBRJkQZ($yQuDWcz=DRed*Zddts8p^PhEDwNCSW z{pE0TXVvAl`IBAE^!x|oqV(YRz5S41D%dw&y43!PWiQKGwJM-oX1jx659yIG!s%XuWBNUBq+W zHQo2BcGCUU_%rE#!GBHnFYFiLZOif?_D36eo>IRbrM#7cj{@Q0Lf7QgVH+RU8Yy2^ z#CUo0lki-t@?qZmR5(h_UA6CXZ2KynOUi$R?{d31-$3`Hv<}gI4S;}>PTZA{Vqy~1-@n(NKguI|KrIN_N3-@PBE`~lVv z-!;~cgqJr^c?Vj*67K!7nt%6rKXJfkpXBBl*LBBFQQiXi57>)4aUS>M>$1HH4}8B7 zs%+x++VVY4`x-c2pTP4QUb3k6iT3zWevtC4 zh)d4++4)qJPpDGk$Ir{i4$n{Ln$}S*Pp~Jg?#IO_luQYJ7kkx zFXzSF{qHU8m({*FIz@S8cfaiN>lJ?^=Vwl@l|tng!UxY2&Yk>rY;7ZOzInF4XUmS7 zsx6bpfb%gse-If?O_c4n^WR4|pPgyIK3er(7xMXK^|KfEkC9!@pCOM`f8ge^J#u+B z_CIy~8=|y-C;RELCyH6J4|~Yp5A|P3qEj~Gxkxy=7eB&jU){4H%9{@0G4;q)59KRF zbn9Sw6!~|xj^X~4^KuvmTF3NjC+~;68pb6xZ0G$DSK!B`olSNg$i7Cr9hUQ|ACPxL z+@Cy5?|0aFD9T@|{DhN-sz*D~Up$|ApJ3Nx=e4+;`jghJ7P3eADV4X0qkfg=ar=Gu zSyAc80Z*Kda`v& z@0`0@IkAlKKpsGXZ$DSZed+;YIp+;pFSX|u!}$k3FLU=V$S2@={^V?9=lI1#jUDtn zqZjL&$|J)c?=9K+^1=l>k3sqCyUPB}%RPAhe{o;Y$$w+NtMVGOPT;4CN#~c0eRt-j^W*tq zZ((LGKb<>0SIie?7n}W;z0=vn#fVjfpD(Vg7qM!DRcBBZ)*451E<1iJJC$qhDHNug zBUY`jY63+OYc+lcsmcv{XZvT1&|3!)MdGKH0sZE4xp7FW7gjk@!fFl*OfD2=$bK$6 zJ6agX4>!vrc5Qmdfa3HerU>%3u_fA>s+nBoL0Lc=kpWA8xd=Zu&Vt$VQsyc zy`62H&dyHZx2U%Zw{oqga>W~kiR0PXiRs*8^FX0+YiTZGZG-)lMI+V@VTD;q3?GjeZy~NmgA`_F7naR1SEQIz5E52~sWnjd7VmXMko0R!qD2<0(ST`XpcIh$TyKwQDB=$)B3 zQ(S1HSuwF#%+SxfbF-Nn`OHj!HC-T9VtPV(0Ey!5+<0ah-MZcGgYm*N{b(E!x-~yD zvsBEEP3KzsXD4!ZauXxDd3e$BXp)})6a~A<|6sj0@)Qjwl)ttwle5Yjmz$?1!%aVz z{f4a1f-6hhN>b#G07mIz_D<2?cbVMm1N+?dIZmn**v6O+pm znY{m!NuS25EzIN=rgEMDi39D_#Y%v# zogRj}u#lg~?s_vsNIS7sMwPZ;UmUvR6{`! zC)DXv>%To=+zB7FM!;4W!saG(x3Dxjl|vZe`Z=UjDqrl8;)~na={$O!rWAKFb%;Kt z{9LLduBLKeG>ajXlO ziTonP7{Ef0U1(M?mIYa;5UiTTVqqc2GZfVXI4r}KZ4^O5<`*;Ql&RU=1Sv%A*3MzH z?e0^Pv07ay>@sj!aDi~WN|j9(7RFIGp&OnkmWMRQS}_l_qIs&AflHA=zb17yuBK1) z`~t#xyYfwuZA9{*II!m0bfB~Ei#Cc?ZSJJvrr7HO)h1QB8a%pWXOyRE60mh!zOaM_ zvxHJm*R}ySys$l7I*xL8J2lx;)+ux*R79yQK8+2Mn%GM-h!C0O1zKDYjIhVi*e=fVefN2%rzcDkaWi1tseIO2>kV;LZiD)figm((4WcSVSFmZZ0=#`^H^B zMPqk?9TkPWdNU-5ew)NJoyfrVIkiHoc2Z0Hp_k{F>OK{5oZj=PBi5*3OzN~ipntd_ z_7smR&u0sZs%ACO6ar?l#qk@;A51v4Vqpf73%OaeH>$K0s-2F-u0p|}RuyS&QqWOM z7g}NJ02)Dd#l|07($KDyys$0RHNf1)LD#u#SC_0!F4Agbw|d!gnTNf4A-qKzc+oF2Y67zn)=>-xZ)&^7 zz3N$1)s!#^nK7qZu(f0NU7JdY%V{VOew3^?Rt|?JF?Tb|Fh}oc>Lr%oo~LUr=a%S! z!|O%rE(KOzelfRInVMoln)84yw_goEwyW$ZAj1l5-BF;r0ZKdWVYli;Ly&4;fwd0? zdwI)yBscC}w5y96!lN3jyh;MV?(pIq;;AYPGp#0pvy-EqRv`phFb>yM2;nPC5{iDd zQCfH1X0w3Z2TloZ?>#Ga)KI~!fxg#-`>L_&!uTyLnAqZ}nM={Vv9wHK*PiDFRaHz| z_Xm~HN?z|Xt0rw>a#FRa##cl$xX#CMVzl3cs&xsUu9`xxZ6t;K%-lk59N)F#jVA&d zEyxP?RY%gJ>CCCVQ<;JO!9Lo_^39^U(b|hUf(t&z!2vJTaC+<}c5B`LGY;KsL`Sj3 zK3`Zs46bo+c4yRww$Rc6?>5`M4~7cl?E7ewoLvODRSUPB8*E2#wPw&MgJeS8vhzK> zBf3Ttb@LsNt<@6&j__K)u$?A=be%65;E1mah}*dW$aC@_*X&3p{F1q5$W$wvNO3qq zwSFO#KnlHNXHXn5y*KS5SB}yj50IlGSB}yx50IlG$f4Jr6pSON_qtOC$#~E4(MSkoe*J0y$&4CRHawiZn6a}4)x@~)GC@+8t8 zdU+~Po>Jves+K*d?m62(a3qsH-h&A`indnTj0^pH(c$hzW-vY4e-7nfjbzRYk5cCy zO`jbY1;o`HPxtorjf|+ip|vW=L$8+bk_KMNz=J0xy88^g{RSQqes#JpeS_(qfj)R> z;KD}(7hW2;@YBGBrv@&3HE`jrfeU|qZ9SD9IT`Fv;syJYc)|W8Ua&uj7wk{s1^bhD z!Tuy3{Hs3F+j}b0lO8;o>FFOux-Z5IMb|KWakMXUzW)g2_`SvT3G9jrbk9GaYy@xhtHlF%?$S)=^yUv#f+%x?@jj} z@5>~qli=Gb`&#R>YMn(v%EzEtoX{ogp3@DDWX`AIQ=KE$m)1g_D@a`KF~^?jS3B~p zwv`o+yH~GTAA(9-6vO5<&>6B?yU;&qHk0jA8>P(|7|e`Z^14NhA{<3e)z}imLi1=` zZO-Yz0kqa>*GTW+k<0-4-xJ_~=6EtPnjS@@;-))V6p8JYJKaVsui?(X5tll`85Fp3 zCf$2dG5pv^lN<)M5Y;=Ep4AvL)%-wnAmH>HUvUdn<59+XHp-Q>hH^H=eZk5u;+3e4 zc%~KNEBlY01-@-OI~O*dolAx1ME@Z09EjsV9>tv?kK#^{moo4u?gZs1?gV)hcY-{M z<2uiasRfGTrCf^RI+tQ6#ql67*q`&qa`;&OV z{v=+oKZzIYPvVh(1Exe)uF>=XdoT75;G&8ydeZQg zwszQ;scU6T6(JO7&YvDWf~cYNoT;JYI6Nr1(bJ>p0Seq0IWpm1JH1dn+=mU{C}zC9 zO^T7*_8f}aGfHe^mrSVb43r;i>TAt!hat9|0xfq{z{7zveA>B0UpnM*x^%N~Cz0<|uT9@H=K zJW;ZRz?TKbwWKO=7DKfufG9oqewdV=4*Q{y-vAZB@N%vbNwi|t#yRpK9n z^*G-cE-cMb)~$7#J91Qj};1dh_jHL6V^-gx>tCHt=~ez zEHYp^$EP@YcP_Vbq3*t|>Nwaf#XpOGsTBVt{QGH(s4BDylPNd5h|gE2$H#Mvi+T0LV83oZ zpt_>f+E863dSSJ&%FqMCI;I=qhH5SU?^s?NT1UN8kNJbXyiu6w&5qy5VXABn4onHc zF+U=#1M&3_uAf48py#1l@3H*;MnaF7W-nG5NeDplav?XLnTdur`+bIh?GC8Y*^d>e zQf0#FxgE5(`?XPQYlAA)#@eO#4=!zKP^HpX)oLg3^sqR+l;Je~4LskAhFbkrAZA-3 z1?mL`q8+cW4#w3ZCQ4Uk7NVhm6DYUUL6xdw$<$rOr7aDrRJs#@oh@W0mXUzUaM~L+ z9`xIQkZl80sf`1$fhSd7N*7t@Xo!No1}zBLHbB*tG`hVFQ0K}(& zYexa3K>?8PDd5^s0BKMFDtrpKb`(Gw6aWFA0ew@(4rj)D;iNer;AK-abc zk)<^x17lCuj)HOQlNe544c2LSUqm z-bfQ^Pza24(i>?a4GMvgPI@Cvq(K40>BU-1sOJQ_*&F$!apY4NUT?XFf#>@TP`N#@ zM3#Dx3Lt^59R(v2QUN5;wWDA}LMng+x^@(dNJs^cK-Z3f5ecaP66o4dFd`upKmuJm z3PvQP0!W~1N5P1MQ~(Kd?I;+Lkizil6O67M1>?x?#c)>J%X|h8F!1m@8u|sl5t6Zu z5Lr6cvKI2I53yd^fJ1!YVdS76q>Do~+j`Y63NYk~WU>xav zfsv+bN5MGK`vN0P*N%d5r1u3znywuM<4Erdj5J+43dWJ%9~f!6wiSph9k~60k)~@$ z!8p?U10zk>j)HNd_XkFrt{nyANbe7fG+jFi#*yA17-_n86pSOiKQPjC?I;*WdVgS~ z>Do~+j`aS(NYk~WU>xcFfsv+bN5MGK9T-kJaLPGsDl^_rp*~uMn|ggFlALXb$WjD! z1Q0;ij)D;Z9RUQ;wWDA}Kt})pbnPe@5zrAp09`u@Mg(*O5J1 zj)HNdI|Cz4*N%d5q&qR3G32ghGkCb4id$V1K;TlJdp;4 zz`%EU15czu0izqIoCR_$cziGeHATl|Zs7sHiG2Y&0CKe<&jcVua952A(`PCZ1M zbbtVVJsLdP&G2Z)Q2TW>98jUDo*)j|H5?Fa(h1_AUBdyM-+BF;yZPE$ipk2cO z(Iy=XwbXuLfz{xx!Cujj(QZaYdk`7Ka7WCH3`$A*dY>4M4$%g0DM9Ji(U3ufCY>NM zC{yXyV@3w$CjIqj$e=<~JwaqpzS6D7j10<9`s>kcjk(QrV8rh0-npv0wHj~NG)s`S^R;eZNF^#pN1=}WgBGY%+W>90q_0Tr6+3F3f~ zm~K6098lWQUyp_ZDm2tXsmU5VQS&`eEBki95J@?e6KygS1P7%vT^%zxC`ajYm>8~( z861?R^y_HgphA;xL2yv&(yhk~4oX(~>(RhLg{FE43(ix)nP@pZ{@3?zl+SdlHDiS` zn0_4%D^zHzHi#9IuSv@||uyW>`>$(_fDU3o10#6NCk2J>7cDu%JArza9+-RA{Ovhy%)fy7icG zK-o@zJsJ+E&{R(l2b2MI>oMbi5}m$!h~elEZK#LRp6Zt|lMA_AW<04M-D7os^W5xlcQ~mX5IG{pPJwY6(l&gKOO|(fThy%){y1tolK-p8jZyFA$&{R(l z2b58D>oMbiQl|cTG#pT&sh%JXD0k}CW5xlcNPYDX!_gtyP!Huu{W=;BsL-Sn!~x|| z-FnP8pv4)70L?Ut|))I-;NTpy-{>&3zBUC zv?zwFV?;}`Er1rqaCMAmNwx*hq8P4@5iQBK09q8o)iI(a*%m;HVz@d+v?SXCXi*GT z$B33>TL3MJ;p!OCl57j0MKN3*BU+MefP#)n#c*|uQ6ovoOLzOHe(>&W|2`csrlmZU zmH{A?)m-B|2hxlY-u@_P4ziAK=4@z^5}v;H5X03mV<(smO%lV^F=K}kp8k5kaCOYs zp@gSj2Mkxoj2%jN`gOo?bqKHq*SM`JzDNl6`JY^#t_PPy7icGK&eiDJsJ+E&{R(l2bAx0 z>oMbiQl0*KG#pT&sU8fq_FDK1j`Ix~(STu2h9)WB>91G=hB+CUq}-=p$6Ihzp~2Z; zGBl|rLlte(2?B!>piW1clc7nm<1&nAIGv`&4lt!(iA0tpx?XP!a zmoqT-M9`Q9KGHII1Zb(xYfz5B?z7y?T=6b<8h+p4Z=;4pb2>Ij*;l`ghD0hfc@ab+ zrC?ozfHvq*a@ALlmU&H@Gp|WXwEA^4BvPTN9w4!j-$aIve2(yeYiW*ktabuEPl|EGTF%Q?{syt?7{LBj|sntTXigi^7t4`z%|7B)gY zWbfpo74yMLHNcRhsnQ@|C@I zG#r?-u1QL=`gOFxL4_vYf;gZ|tLvK?2b5&>*Q4Qp3QhF{aX^_?w;nSND9P%tN5cUX zn(7JSfHJLaJ!TwGlGR_2h65@z)Dz6QCbg`qqD?wM98jj!@y(odO;VE8=bM&wRfVQ{ zf;gZ|t6Ps52b5U#*Q4RUoOMl7lGU%H;eZNFz6EhWnO4^~GY%-p>aRz`0Tr6+3F3e< zt!_PL98i+gUyp_ZDm2s+%(^DEtgE6;Izb#zrq%JyoOMl7lGW#%mUUHyrh0-npiHY< zj~NG)WcAmh;eZNF^#pN1nO3(RGY%-p>aRz`0Tr6+3F3eH2dQ8_RWV#0BMwr*e5zu&Iz}9%g85X%aCMA0NCoq$is9-QagYk;Qx(J2 zG2?);q&nVGTG~|6hVh~Fr(eg52Pt!IG!@K^Du&~m`AyMOFgL0gu8tW8!Q5y{ds9@= zruGElK}vg5RM94#Ks-okZ;C3~q!Wk-DeX;BMVoX2@gPOXQnwGxI0)uOQ(A6R(S~}0 zxzUuC8&$MPCx`|g(}*l z6U2d*3Qd_)p{ZahR56_PP@$~oqsHxCjjo(Ja3P>3!wca>@}-DFUb2hR1^RS4HRJ>`D|{XF|AY+R3Ew3h z{2HZvAvcF+Jhr3%LDkqt%7`q!6-B}@x5IO8Wi=W8f$+1arXNIpbZj9%fe%wp(TA*8 z@94jzwZu6hr%Zj1IhwsOmMP-%P8c9h3H5H&>Md25;pc^)PnG=$#t`FJJ~^GA!#9dl zRr%TR>7|KWD-una@f+FM+1&IZ2B?B$V0nw*vQb)wUle{Z*?$R;NG^K5A=$p8)FHg0 z=NCgojb25i3Nrli@GGc>S7Pw!d(^$@0sOSi{W6#PLF!8Z*7x_5)OOAAw!!n(`8t^G zgAD(4_|@dr%+!_T60 z8~ElD9ote{!fTe{H?azRQi6)r_r%!QYTq?P-@>B5WH)Q-#)93fmcaad$b1QtefkJ{ z8BEyqI>yl4eO}M{4f(IUIbt{d9pQIUh77oYDMzXjB&51&)D zG3Kl9z~d|2K~c2yeQfIeK$x#wO;CIiTvGuH3ctZ!^8pxNxIMOjUZfL4!p@i4aoCv6 zgzSge_(#x<3%3_=fLqS?@bMk}B{73P2B(mf#H2j*5Rt%{O>U2=II2FXPMxfp6BZ~U2!}RR^rFKp<4+PhO)paAgpJ9pGd zLu3&LCQalf+z#PpV|<4U<7+UvQgwk2kl}v~e}@L|-_#`Zx<5k?R4A^xqXZ7dL~}$9`XDQDi^4 zB3c6SD?);X9ZmN6gC^r!oA!|zUg&uQ&txPLiBc-eYu_VyLd7w!3E z3flp=I_0_Q*LAPHKd#8gn#fw}g>`sU#_xpFx43_+e?UpIjI8HQ+~9N~j@qz0G4p-y z#L`|YALu(es+Mt#o>MV8@5cXC=LKDmk;fxV)O+~yDfgc1MM>|KmZ0~xa_?<>pgL}Z zx${fZJD|Rk)$!gCb~wf5!XiGGhTAF}gX>&CXtxS$kv)jMGq=>zkCzK@lj1rYU7{ssg(CZ<*kfHL3W*z>t;9(Id*J&DM>|$Wb zO#jg#XZY}Urdb{N;hfi%Y0jaK6FYooban4MC#=hU-uE#{Le@8yxaAz>#U4=-?wl0I zI5NFlisMYZQi^`2UM0l|rhZC_lT5u@iUFp6Mv7BRy;h1rrd}__X{LToiZe{TQHmj^ zenE<1rrs>Y2vff##VAv6mEtT@ZVm#zbeHgrrs~bWu|^z ziYrWgK#HqOeMpLHOnq323{xMK;yP0wlOoI1C!`o->bIpBXX;Z@OfdC(QskKWv=oy} zeMX8Yramjh4W>RPMV_fYk>Vy(Uy$M!Q(u%~nyD{IF~ihXq?l#uFQh0i^;Ie6nEJXD z^GyA<6bnrKtrUw){hbs=roJh~5>x*m#cig(EyXfZ|18BFrv6omyG;F?6i+kt?@~O2 zssE7T9#j7*#WNKZwWPSu6h2M=15A}m@hqmoQv4uOQ7N9yRHYQpVMb1x#&{;)P5-F2#$O+APJ3nQE5e zB}{FT;-yUOkmARgdP0hqG1Vf)%bD6E#VeR&oMP9 z#m_T!Mv6BwH7v!Om>QMh7nnLH#V;~-L5epsbxDf1Fm*+WUt;Q-6u->Wbt&G;)R+`+ zV`@T*w=*><#jh}RLyC7WbyJFWGBqv5yO^4l;@wQmN%0=07NmGDQ$;C$m8siOypO3n zQoNt3r=|EcrtV4c>rCC3;y0LjmJ}ag>e*6!kf|S%;zLY5SBl?c>iJT9n5iF?;v-DG zK#Gqt^&%;Li>a4L@iC@;T#An~^>Qgb!PG0I_#{)WlH#|S`Y9=XhpAUf@hPT$MvC8M z>a|k*9#gNE;`f>QIVnEP)ElMv1EzjKiqA0hW-0!Vsb7-fvrN5Jia%oN?NWS>sdq^6 z$4tFTia%lMJyLw0sb7`i3rxLVia%xQ*QNL(Qy-Ax&zSm<6klTM!%}>isgFwW6{bEW z#h)|v2`T=9so$33FPZw36klcP_oVn5Q=gXN>r8z{ioas&vr_yuQ=gOKZB#hqUlp6blMK-gd(27kYOTi|pT}iMnAn2Z^$d#@r z<~3lKsfn-_JbQ6vqv~WXI+F2`#GEES$VFw14sd(~Yjm#TBZ$#)kB=ngSThbi`o-%x zBh-9nMskHsrXFTF93{yz+gFmYPncXu(tq$IOYSh(RC`$c9J5CkZGUvpvnc$l2Cbua}k z-5!sNN+3PNNp+AdJ824?j#2G=+lRN^Irf$%SMXI$O?4(Li<)+dwg*a-r^+LALU7KT z0B0MfS+6>3g+b@_mc@1&z+{`!4&Y^3)4Z`|xhc-Lo4{@hs^fau+zLafVgsGx`_PI> zk`DJ}LDT%PE2eX9A6l<_6!1gMdAr&bdQdw!_@PzPF~J&kRzNRF`k}MJSd*}Wuob4G zeJC+|X_ljP%)j25huM*Hz+mnlN6Oz2Q+!v)xOyw7d5B?7NA&}RY%r)9Vumv;u}@x= z5A2V?681pvJ?uTuv4^d4?upDiL=UXW!=*7uxaT*s8RH1rGApl2+G)>h$`}`ehd@8N z=n9)p{n%s58mzGS42rI>`3#D#u=xy%uCVzGimtHv42rIB^Q4PD^yaBlc!is%QsEVD zo=S!7{xt?K4GZk^3O7%smRGoWDivPg=BZS8g_|c`nC=HwxOobSJ|cd}>LcQpL?02q zB>IT>CDBL3FNr=Peo1tNel0mHoa4eK!(Id@d(#=>EMN+0bo4hLr_C~^kmks&9MT*q zS~ArFVT$`CL}8!LCucd+J})4r?O;ty07=`YnX^gL+N6ZML(W;y6n0C_K4(!=?|Da} zvy5pc;X5gv#Z0+A=K%GU4Y}v4uk4e)96qQrZ>f8b*WO|5YCKJ0$#7;nduAGZ|55HN zXIhEf6W&?GG~(L9?+@+??>zVi`{X|+p5;tC>)`3}ENPl@_M!4C3t)G|0wz>>N6fAT*pIdv~P-% zcr(U%!3*zW=N4wO)2*}F85~~UI;j5i7Qnt!#QTo9g~{xAu3K8?tn+yFBZgN$YBlv9 z{soYFL~f5e2RJnVF>`{XU^}n0|25En^>ueXtU}@*z^uPNP3Pb`vVy zJ4;!sVjmXPhUP53i8Q%1+w4HFxxG0%k)12jOXY{WR~8L#7MGfI9JPPmB4Zzo{T5y; zjD4&o9Q!z)%o-iz&b3um#Xebv&WzAM0`rCoM{*1K>~#KVYH%cmpQLQQnZ2EDokr7J z^Ru@Lw{oom*_pA4?5SKai^*3kEZmL6exH83HeJ+s!g{Xmf~^XH8-x!Z(g|x0RRVJ-#OjSrL!&C%=uPyDWP0|{(#<8$hR!VDvDJiWSQ`OR%WNMYP zrkJXg)(xgsODoURTC8N6Vd@_G<+3+erlFD6P3sobyk1%}Of^btmMw0QR)ML-Y+C#@f1>X?7XRVC8;Ve7fns1wq99y>cAt>-guP+C92s%ND2qg*;Htsi6FsI*?d za_6M=LZ&WA>qRVgNm?&vxhv9o2~*dk^-?aqF0CJD-k7vr#?*wgUe2YH(s~6`H>CAS zrfy2>CzzU+)~i@!R$4#Fyg6z86jKY*`e`mLO6%3kyDhEPFm*>-Kf~11()wAZ?n&#l zOx^zCb-pm>=mDXF>%FCqnOU!$Pw0@bXpODsDnfgg-y^VE$T3T;s-fN`wD@^^YwBEtg z>!kHgrrsc}cQN(z(t0=RzDZi|VcsuF>%Gi-i?n`~sb7}X`!VElmb8A0 zsgFzRV@!QgS|4ZXcck?RrhZpipJeLyrS;oP{eiT8hp9i5)~A^IBWe9EQ-3V2-(%|Y z()xX-{#06@X6nzR^#@FSSz4cA>d&S1hfMvYv_8w!*QE7FJVt*dt06d+}>|U z>ra^adue^1sc%W^3oQ4K()v@T{z+P2kk)?X;OxRBOgGF2w6uQF93t*Dj}_J zDF5Ph()v49TYQbQ{+@a3r1edfYmnBrnA#w%f8f%M()vfH9+TF$xwJ`I|HRZ5Y5g-( zTc!0cOl_CezcRH`THj%6m$d$kt?ZW8cbV5Jt$$~#U0UB`DkZJ|V7YzL`hQGyNb5hj z^nkSfiz#e@ET*26*s9Z#7e6dTh^e#`WlZ%-QOUbe zF?CvsN~VS+ews;(TYN-fY*cM$rKn=+ycE?;U6i7RsmoHVV(O|C38peq)H0QoqK>I? zDOR)PoD^%AHzmbdrt(s(sD&SDh7aav^Tk8-dnfHi z!@e=W4dOW&zZ1V(8NVIJcTOtvGjr4V@qBUmu8iM{eHiz*@n=3#mHnta62}i^9&_C5 zyThh>@q@Aabnf&V-F+^ijXx-?Cbx|bkWwvvPAvZH_z$58-QGA^1Wt=gC~b80E8{;wsCkvJ_Ii8lo_uk!yYxm3Ht3eQ#oWc=dfVM;pBQzJ)2g`rgc?c=dfNQ+V}#8&i1oeLGWl^?e6x;MMn?%)_hi zPcVhdN6Iy?}~8h7t09Ma%Q`6P4Df_$M)@ z-hI#LjfKLpx*v`IPNmfn|74|gg8pfxe~!>U$LOCV{j-n$>7;+s^iMbab4b}U5s_c=iT;j+8Hzqe_=VjxL6p+FV_&Qz8JHH<9~(?uQT7=yjc9pXs?TN zhpm+UJQn{-9QX2Dkzgy4m_!Ppf3`SU7(g0iAv=v8+8qCCB{aSUkIu^YUsc8`t)@8c z#wE=!BreqdeUr?8>-hbe*?$}V2F>ihLjd*qLB_wy0Tegf_0354E-f}sE#$Ir-b>S| zS>g?%bGu){aps?MI~)JU__r(3!~X;fl#Us0+#i?>ru#uREohr_hZu@9#P}0;#trh3 zIPRDe`j|L*jQIB|v{^1dem(4+rIox9Mbs0s&?#09^XzFKv)j@Izj+nLiY^ z%j*C-ogQh()_x@G#*8ST3>o>NOogtidXj=P*9kH|94pQ;4_eT3QPnY330 zSs}xfvRuNzH^sLw)g+e7Rh}3RMnuN30&y0OZcj8j_GlTyWzbBwlvT32GW58_M-C{n z+nZfl%<->~Jy~}WLp&jCD`iO5>FFAT(TH3ltYQ7zKmThKbKs4?K(4ElYh^uh0hRUC z9moaD(wqv(MtjZ5&df=xnl*QW8e z+6C}zZkZtKXF$`>fV%dnIt5=ZWZ7umsekRv33L?3s2tzY(?i)~@*qN)d=g&uNO`!j zztY+yp9g*FBd|6pxtbA=;zCylkg`vm7 zMAPABGcwXk4BekcPMzWPrj->LUI<`-7lPIU;YEwz3V zO8JZ2QSSijowZh&x*{;6OCtg1H5!Hd&+E8R??dL5r_itcU+%wcY;TgkK@sxi9Y4L&YhFACrIw|dhO%fYo9cq1K9#PoHI<{tT=y)moLMKGAoUeUWE!c|v^~6X%y<>y8h_<%@WHPI#(yf`iIR z9nDWqH%H`O>Yv{83g~7|ek~@yD!+~i6@F$VDBPAkN=(6BMIYAo0G}sNDs*xdLOO`Vn?uc!s_|{R6s6-3a0D13Jm>MSB#`+3VeiraF`M8TdACVW~)4 zsW-D}^!bCuY>W0N0W|e~i)wh3y$2WBHW)^9JYfK4u-a_gc6fUlH5OWOX*f4Eh*zJ0 z0wlV<9*X>Y*)e;8u%-KzddxOJkW6VN*k z>jZlryv~^hD*mF$eY3P{LSGExwG|hlfl}2aXJS>StA_Bnk4JvQ_u1W*njg4jWW1s= zXDeawTqz!L>y9s96UaWwRb9lw5kL-P=%&4sp?*b6dyx4^74CxY2{nd1{;u__FJ@(a~xa;cozk2W03emb(Qx;8e-sZ=mWWyl^*# zyr>NIvG`nYwLFJ6&?X{P3y5uFNa6Tj1K`f9DpoC3RxMWDMyAdAt~z}vf9_T>Q;byI z!FH7EkyTHlfmL^_o`F|5Y5NjZi4hQf_xB;~af1DM7F=J%i)}es^=#I~4M&LfJgf_% zHqe_-Q&0XDj}>kg0;W;+aW4C@k}_;;Kgnfy&=Jt{g>!ZE_3}byIh#lLS>Yy}_ufwC z(<-p_m*I)8TCA&Hp^voBDt!4IOTVhb7X-zCcO{Dv9nBb!0q_DG;O4=JAbW~pMWf|5 zpa~>V0h&&K5EcF9bao;Ypwj{cwg!iFI*T+=&HC{6i zDCti+&JYFm2-6{#ejn)QLMq3fKmm^+9bHM~B^ai238|o@RdnDW6`&3Dr=*P?`|*kd zkIfhH(gIUo!fOdkeWk<^Jl6j%m*E~D;AAHr^m7@u{}xl&{s*M+I>3i`tiB;br#MpK z^$a|7rj6RSWN4Uq|A<#qnD|Fg!Zj}LduJxj6c^f#1}lH{j2-c zy?^zInsD{WS}Trw|LQ(OGy( z2wzh)l}ggqbOa;0gBH>sRPJ|&j)e@klk(gtusd_8d%o7HA$M-EJ4LXTYOPfUchGXU zgO?LFaM$5wnn0cC6gWdCpwgexF2wK$eA@5%^ep!22jRf8Ypn$NbdP=dVX&TCYt zB^&q(#3~o4>MY8EsL`+CM!ylPH`Q9J zsnNkIQ5RahA1{LNNZsq$J$yIZc~7mi zhCF;bd-y)E-d}62HF=0?;2{FcUGDD>QZE8P+>0RoKjy9jPKw%XXLn|H_wI6cyK`+% z4h6+Rv2ZjI8%;z(KomqoJm4r&j*f^}5XBCP*io_ZM@5u!pooeMyJDe;4aMHO*!bS$ z&E|G?b0Ig&`TOK|=1nHglV>uSWG3?_n<@ftEA}I>Oe{2{)C{0MRb`u+dc@hvJeaM_ zgW1XwrV?i>^I*0z4`wUlDwT?2@P1+)2h#z~D^&-K>ELbz<9FUW;Qoo$W*R&X&vPp{ z!(!StcE(Tuo^g6fEx~pBUd;Lt4PJook7;lgT03ZP4qC7>BgiJCkO+(*`?)!cfe~a= zPdvtq6tykkHRe?;1fDjoLc$*z2rfE;z(@sQQ)XQy)B)@FQZv9{@*1-4Oh1SXjrBha z4XrN~4R`D7h~5Qmy?jv0576LTt}fqV>Hv)Dz(|E-6A}F%`-R!m4AAPXLoRS@2(k$_ zM8i|`Ogw?|ft8BX)t;UU%{+0W^r1~7uHAPHk&Y8+qb4Zk3hn3UqP8#3m1X0#v8 zKP4X~mj>teqrnGJ$!RpW46V~?a3xwWYt%SVGN173F8ohby380`Ln>FB#g&9FMRe&)tf^5bBV_*c?Gy%rI2(pQH zjDZnkQv?`O+*k=A#2CX?X_&i#dGor-Z#Ec-DM?hNEuGw?~#=r=& zIRuQQx6M}YX7(bIUJq{Z*tBl|CvvoI0w;2;m0Q4x9Ie}6?Gswy^cg@4oIYRWpU?B} zV!uq7Ae2XQj%OUWy2gkYU0GnV-6LF{KfhI z%O*|om%!O1+%J+AT&htu)6}AEJdpn&I40&V1y6I7z6`w2(Sq^tC;B_MrDJp@tS-WK zP)&ocU>&WY!Pn7x3|1WB(Z^xM5n4~s;G1~#DOhoYX;0JOJDBz?tUbcC=V@>Yro8}5 zjMC(# zF(b(4m9Xa6jm0LDFa}1D%^>j@GlFa)31jR^vDqVxfstC{4U`7BzR%ihkuuk zf)8Hm!FJ$G&aZ70T=G&6!Z3Lg9)wXj^&mVWU5{sYT-w3b@GP_d4|Y#K2v4Us;K3g0 z2jO`K-0Y!wMqxlsDU&@|@0GYU_~_Pm+NjAx6FV@3qbI|IN8)(bF_mL0VZ(vwDd6*q zGwml;jf1a8(SG2|Dg0h|3L6fir)5R^M+d;uLEp;Btk+HWB`2*5sPVdjJn#`VIxu<$ ztO$q>g0&%7K&_d>(ZTSzQaN_~sX?NtnT@f9U9X%^LG(bAlJadS1N-Q|Ql_!Z< zZH2>cp}Dg zmDrtv`6C^E=m`mDslx;w0FmIU`Zcf(o9G?-z8;`6fMRim}`i_Tth>a)D)9ot|1C@ z4STbsBQWW5NV>u$`>=B;!ONRC?M_v&f555WK@yIFQ<#0~N!_81m5L^nmI<`ajn2!8 zUK71G>GK&h+>!j})u2JnPj)t`Il$ZHf~@HE(Hp4cV1IEFwB1At=kRd!78>n9`?Cvr z8%SOl%?4+0L+`f3m|Ix%PM0)_F7hmE5kLHfr=5I>(mc=@!QI)Q@g8brqsIGa^hgx+ zKM=IUC5@wtsFjNcAEeP^@E~|*MZq&`Uv@Bx2ba@mCp@?k4z6;^e(YcY9$Z7CU2}G^ z^Lz{ru8n4QcS#d=ycmx^Nu$T(@%3>0X_xHJ4wmA<=VTzK{lU=F)&g(JNBdtlPT%le(P4$+6RU2pwaCp{4)^#xl0a0;fW!H%@d~5f(riL z1oS*iA2Il6G?-(CvrYxKrPjV!^iMSUJzlC`py*#+(iDpZy?90n;gDnlFZBO6V;BE- zdI^V9Ykw?Z7mfbOPc9b755`)qO#xHoRC5R|@$-yWh(e&9IXle=VX}B^x9B$bdJW9;RLXH4IL)i}o zdzX%3k3(Ze#*Sk7kET{jyaMoC(!FN%@IDapsfC)yWAD!pr?_(9D@$N!tP`vii?L}2 zHaUtd35*o!?1__A4op#8hq}`rWZJ@GTw4^`gT}gH<-li&7<`sE1S^42I&=s!`MyoF_kr#4V8C39x7ER3f-bIZE8M?2A`Q7B&o|CP7^=6#Edy z!}QyXjTEUUsNJMxY~EI!(rkHDkc)a^-z-uYMb)tn7^#QErDb0;xJ0Oy1LemI=7}?| zYTOWZ>wsTu1^jX{^F4soe8c#KP9;mPZZ?J``KYS-aIxHOv!R1`YMC%39D^+zp0)}S zK17qpOc^|6$|Pu;!^5$;FzEq5eLR>YP8v0=vU2!vSXu|a1U?D&>>5056nD3$v1{Qa zH#RSJ9lPJ)I^(UG-WJ$*HC|PsC9w&`6jAUIK49U!cuV?07(cq8V)%>`WZx68C@>E4 zR6VRppIA9`)TGM6m9Wfo;$ZH~G?;sorL(3tq{CamihWdZPkMeBK)R!f#nkG7))H#< zLF)lf#wPo@GG+wXoIl3E2(qbsj48@(L#=*Dvl5`_(}G-xaej0QEGed>G%dyk2&%O-a02>`(EY~WwzaZ*zJhHO6?dn&db zelRxnG|Y9vMzFAt-NcHq;n=g_RST2Ei3IkR1UaA2i9HwF09MWm@SD4_7h%J~tjpPe z^fJ5!DCd;<+g0q17<{?fEB!TR(#ccCodO#X zhGXwTr#z(UoKvb`;<0iB+byuzyVyvicc8HkV;^P5K8S6Pkki3SX3Dq(4BP+|3teEx z!Pt)2rwjpJHLs(ZFCyfO2pI$$O=0|-2!Xk6xyJ#2LmX2zqP%nEC~()0eGfDK@;ShJ zkiA94e$0yf5c>(Avz`b**Wt6Pxmx^5x#nW(R41xzD#WnFOCEw1If zSnuP;v)vN6l#;VZ1?;=xHh?>Ra7*eoWEabI_l^*7*$56Ur*30R**8Llv6NQS-5*m9 zh!D7QgM(XBw<)GHi;&?gr44lt#*{-MWCTlTOWl^3QXU~ASxP(Vw!xIP5i%-iGN3>F zb~ao~7-90|jlk3RmFtk@9^oDdH;_D*_>=&v;PK+Z&lxvxkAYq;Eem^^!#o|cNZjoN zEt}2z$K5V$1ypyLpLcFDCVR8AO`6O{?BSBISB9dxXG1le z5Fuwr2<&GQVfEJ?1{wA_v8E4asa-0ES4Bt7bRPli3>B~FIABT*B~ zM7n3Yq$LBx<~~y+WLkur6Cu+hl?BBX)Y;u&w&MmY29u2 zq&+{~b76!|@9&bb@LT4*EO&-GGuxe!^$~njVLN3OrqROc&#-$@fDA~iqfDBEWm~{x zd^51m!|ugUzB@ZYW>DH5s{+=#x|g}66+7AV`;}chykD=(A_eYMa1*hQI|c4F5po`- zN6-$eI!P%SOIo{7)#p>%2@l)|2X1mn87xhz61r}QKQt%Ji)xa3H7_=*U*lG0v?dj<|X>yo3`fvY0q z>Ii{zo=a(O#JvoMUvbIN?C?BF`yl8INZsg?V_5375po@+Cu8+!!G@QF;pI*a0~{bx9|dhc^i(|dH5~iKC7s!^ z+ahFPgxnq>cSOjY)EbJt!7p%4=NqkbV(N%Rw)nT z4qfiwko1pBy3&Qz8p$OTkW>lfHTP^mkTVrn`Jn>aCC4$QF`TI&3`r4}bYo6eo(>>o z*>@6I4w6wo=DOr~)?#4lwN|jF_b7-V*adKbOS&`g-4SvRrPaKy3*vB~)FmhI+r(3) z<*j8OR8WR24I%U1E;-SK(b-%786F3#g`T?@POHO8FzaZJ^kTlRG zeOY_*UXoTdUabXZA|A%Ig0oz53d8@2_@R&lW74S#e2o)f!3e~Ugv_H{(vRW)Mf?~@ z8tan&3Vc$N7?1b~ka?m@P6K>y5b^MZssO%F4S+j~Eak811=Fc@KDL4xY3C$wb6PMH zInM`z3tVzK;|w9^EJ(W8B?HqnwN9$jOA!y_L;;KwXE1y=;;)1x*v?>(0-sc;a}hre zGGFVGGZ{V)@z+Dr0+$R{;FId~CdA(inQw8)Sq$$Yejy~??ve^tCl6trz=xQNu}G^nz;Gk&8RN6s)1v z<(TC$YF&la<9shAl@j>EnU>tGa$M4e5bSxk;E8OI^JIiPOf7VdEO?q)=-OBSZZ8jG zr9DqAbWALGfm-NoSnyJWfM|3QEO?b#=+;;8IjP@7LF*%GtwrnO2w6d`Cou9UwbrBcIklce>q}~FKpe{Qn_3^D^)IzP z=2ju0)~9F%sr3a~c7#+@>uZd_4qCV=Rv~;Rwb_&>EzIE;wvbZmN6eHLA*-qN8%AQ( z+KE;{gsh2>N2!Hg9)%?l0v8^gIturqHac|_mQfo&*B0(gZTu)&*eF8QMhLh!4dxRX zg-s%4U4%RlAy2}Fw)~P7!XoH1@gQtVx{MD7g$FZdn|=}URD`ULkf*7QpHT~2MaVM| z@+`IS%V}XdYU5|p!uApJ9JPy4@R8ImMeAs4>ME*V2(fzE8eB( zvd1qxj^EIQ-SR_)$Gc<*yP*%|H+12NkkkV<5M@373-HneOLm&TT|0>u_U7Ib8K@|?BHhvT;tbi97 zujb?x-!-y_qHI`gQ3$IohB4V~P&Rb;h0xtsGTAQ$NFy)XFg6L!S9{lRjYY0;0IYJ! zaK_ahxh6u=B$td}TrX3*HP-kvntNm}`6#xpmuLO{t(T*0FT3)Kq0&djA!7!cyJ}nor4Ff z;oxeQOkm)Ruu(JKF>9&a4|A@g_5ie=q`6lhW<6k@cF9B_BrhNU?u;`q+XiY6M(ahI zdo=>!^`H=54<@lfU~U%r$hRZp9hy6jzb6#J?@|=L?UKptS!`2;Y>tpEuyr#MzYAM8 zqXnxB-$v_$Utb$Ou2u_LisxbUOG?W{d~45B`9$rSe3T5}tFN~>AcQTQ2x zJ_pbjE}05#m~6(5=IaRA8X@medkEIb_tdUL>qlziYeC`9sgEpeY96Bte?{uwfckfr zOk+>R+hG4`tct&=JsR2mq4qemc16g05%PY7d=McY(%f5lB^NpQp`wsW&S91O5zV~~ zQ?ns8$0gHQ>UNsD5L5FZHR_UcSt^V}pG3%x2>CQZK7-w^`B@dksXc+0Rs_BCWVFg) z2W&jLH*GlG?iD0+#Cm%+(%}j&R|18lHtd#^R5n zxesCfW8mPiF1d*1$E7z#ogt}<3$N6W{}asLjgqZsb%*V@(K?aZ)9_S#M#$%|7dIyN zruMm*d@{9Xq6OXX7u3EGBmE=fOKRhzSP{%geMN1204f?3A<#a+oAew0Exf3L=C0uH zCq?jxT?CKV7lTS0ABBoWP#YhGibh4qw-NGPgnS<%Kftc|ye$+}MaYj4@>7KT3>$Z& zw8^k>H(D_D^Gk&M8X@3_`YR^QfPK5sg4^BQG^G5vDuwyq`bE%EbRz>i_zl+-VcvW;gweg{<=mwY+j|2jdKrj-p zA^{ur3CAK9GQVcn0M|yMJ7HUMwCIMl``wxS0kfe^Lvp{;0HBoL-HKDQMukANo9SdLbyOVZ_VRkVr^ zS4Gfq7D2~3n+;cMvDtz9RMA?OTmr*Y0G@$TdJR7Gv9;$lR8Jz+Q-E9Vl1mvCF0(3n z7LuNG$s9(N9SP*n+~@Jud)n72`ZY*;-6fZ^q!&@in~?ODORiwI$t##^ z6C`bR$(1bEYnba@NZRI-t5~j$nCk;b`p_j;vs`asF6ao0pd-A7<=TX~z$vN-oTBEk zTw5^LSCI6z3zI(!sf|y+Mc>hI?{FV>$NxZWd=4)9iQ2dXqX=eWPN?}J$tP3fte)_a zOHBLnNz;^rHM6id4-?o~^c!qlT=aV+K&g$3JBt3Kx!d@YLJ`cx6v14~wQLN;&VS!Jq&=@nRf0BrkQ47>UNh!UDodn*>)oZ9$iP<(JCkW0z; zc&3L@8($NO%c+g83B|1=0jLywQz(XqXM9sA2B+q)5Y&O%_`*+~uwQq;>c;LqPFzJg*f1S?Q9y*>&6}5@t8&-O z9TsoH-0wl|_g(S;Yc3nHxqJjk+gm#T3{|?gmNm18#lIr~d~+y<>u?xMZ!0pr-kiG)01Dkh{4{9#`p2s^3E}_o0yc zFqf=j#dX8tT0v54mpnliM#J-Iv=3hsQF1t>f`>t_TrAREvsxrE+nHDpk+N8%C0i`Q z@EvGLhms>*@?^wenUBTVdB$j&8KGY;3zq!45}2A@@lxd0J7Mt!uiKl0KOG zWXRpuCC@-{G0|H4K~jGgrt9Fv4PGGN5vl}+>6F{LP0g)Wat2btI9&qc^mB}=1eI4n z(hwJB@X{Mn(%X1RB@)26TLR;l4P@)Gz={yHlGcTp+16_Q|&$v6@MJCXa*ZE9x$s5$cnc$K)X>3+#0xRroDD0hR2%ZVI!fRe^ zHcHqEsqeZlodxB$!V=!6PFu7-qz+E2mTU(E+;iq%uLuxvJzuyc0Zu#6A zC;T}*4kK+GM%r!c`EEbz;52L;ya>x`A>wY!G#=q65Qo`>luoT(O{0(JU>WeOKMvpe z--8z8;OuQY3cjbc6aeQ&<7|_&*y=dEX{6HE^jPsCq%Q{g5|_Ns`iZ2^<+b~z*Hpq@ z$j|^7%3SgRs|0wL-7Sg7DIwknNni+%!w~)Mu^|v5h0Bq zj>p?a0!^udbGmVG0Icmg;$09w8m}Y#WZizeA;vpW2d9DKovDMP&>U`@)7GbZs50U9EQy}44d28EjyOqc=3K|R7tOv z@zb!P2LSGLmwe2c(|E)UO7cmsIA_%0p(88CjjJ3pDI5o{-@r7eg(P=A{)!Eoz*S8d zKc;e6_g)=nydpj%JAPIi*51ZFFWX7E!f|L`4!@0Pd<4`+e0Y2$b*7*I_^F6s#WWfp zgG6Jga}FM;qRtGoCQ#>mv?j646KQ-3W}Zr&i|_#a0>yCFA55YbJHBK znC%Yu_{t8@_#(!zFn$+x{)dNPfBhR+^Z|@6rlHMP$P(&2glP{@=Ml8Pc_pPd_9IQ< z__FNy!>l-*Vv8@QA+~E1q^+b5&aA~@fr340)VY;3z6K9H3cr&G7751JQU_<);_D#O z_=#1MX&in^p5dRO4$i8@VL^d26rNRqfNlN@$6$=ZdA2xwRE1wz7y;X|&^X&Q77o5d z9h`8BzXB^e$5g_R*YL>e)WHe3_(q@{GG*cppzQ9y*%F*@q1PeLx+Ym5YBwoj0+fK2EDBHWGy6J6J7Do;ZZYKV!U~#y^MO zhy)92;Y;eggW#{(fhF*hk$B)c>TJOSKd_=Jm|ixO51D?Z&Ne*sD|J3V3w-M3*1x<7 z;U(Ic9siSEqV1ULZx)5Cvjd~MSoBfqe9oh#K^BF&{|ciHi$ZmOi_r*+LIwYTQP{5H z&p6cT<^PQK-n@FdAb~sJ)#Sh5ao5WHt6TMoXx(3$0Qb3ZeyW-VNFKq+YHAYvO2W zLpc4|ywbhXyR4eW`cfPlN?~j$g|XoiHblWA8LYn=K4n~!+6&<8f#fh%xNpx|gx2viv>#e0(9i*B^`Ieqax6WGhFV}6xL_A27cmx=eT{()tSg7n z(vz{EzBF_wW z@Oi0p3XR>xKUtSfgGO+UOFo5Z|Ik3xG=s+O#)C8A;Q223j2%1^4_-t=6=+>dWB2h- z2c?%lwo6^|ImK|dhmV4pT+bSx#1f=_wDkJY1+e0%^adC>*fwss;0uf(+szGQUZkJww*p99u&h@bst|HF$u{Eq1XO`8H?M)}* zTp!ywQ^dJGwhUFoxjwe`RK&SHw%}C6xjwcLq=<8UY&RDX=la+xOA+V#*nWp1&h@d4 z4l&Lwt0mjaP{g@Dwtb+8bA4yK?>AmUsf+Xzd< zxjweXlZbPDY`Z5B=la-&Pa@9sv7MeU&Md1XTY@j*Tp!!^NyNE6wpEjebA4>rCK2cQ z*qU|`=la;rO(M?qv2B+`oaIPe`B0kR!g=ah=_B2Y@xS^bA4G(R*N{-$2Rj2ajuW8QWkNpkL`znab{U9+13;y z&h@cfB1D|)V;eSzIM>IvLlAMUk8K(&;#?owm_Wq2KDLd3h;w~xMYV`?eQepYh;w~x zjWNcVWwm6>jYXX6V+)Q&oaI`V}pi>bA4>s5OJ=L4ICoQ^|7Ht#JN5;c!)UH z$A%9PXZp(7ZkasJEr=)daSP%JecXb0LLavvp3uiFh$r-M3*rfV+=6&QAGaW$(8n!^ zC-ia4DwpF2w;(R{F$>~SAG07X^)U8ATISW3*u5Avmh?@G0Q5K z;|I4OF7+`B;!+>8ATISW3*u5Avmh?@F$>~SAG07X^)U~SAG07X^)U8ATH~V zSrC`{m<4fJf6Rio)WkB=X%w36co zx8S(c$H$LWa{S4;|I6kxU4@uezcO~2e;t3 ztUo?}w36cox2#rj{NNVEW&QE-qm>*#xCO^${qgaml^j2~1;=Im@$sXT96z`P$7TI7 zD^|1fp4ez3+~7iR-c0k>s@bKIZ3Pi-FpF=-?QtFtH<<0&p_{uVh8tW;bGC#XnD}dO z8O#-?uPCQEzvh7RVz2?Mx2>Y%nFT+^c{f_H$aXba*HZchTJvdMbF>!FyuN7NNb^Rb zbu-O72d!Ia-sNa5q zTQv6xv|tg!S9o+Y&E1LCR+=XiY@>OFnD2d>w>MfJ(!Ar*+D`M%MC%ipHx8{&Y2F2B zeNOZ4MC(hMw*sxNX`ZOHZ)x5enD#x*dmF7EY2Jru{Y>+|L+e+X_Xk?P)4YGt+DY@X z(fW(#yJ-DG^Gng%Mf3OLR#|}NAB>ho^N&T#q0vv!3ezZFnX)VzMdq>`8q33@xip67 zTLv5T9fD~w8f%AE0gauARuPSzf>sHQ4MMAw#wMWEfX1ev)sV)fqXm2J&E##ZtTBzv z;Wb{iAB|mx*8VhhIa&wO*cE6srLil~YEENUA@*PzyBX79`@GxGYDr^@(1H%4pvkbx zNtF}fr)c3rM30KGLxxqrCr9`(?3&vhzVKF!t~|7FBG)j?1}>R3d3p^w8}_^EAp3)a z&kbhnQd2~@4EmD!3i_UvlSft!JHBGvFj&0Rq(@cN=qcknB$Xg0@{&@7E(D%3eSBqy zfwdh)T90CZ?p!fuOkem&1S=nZDQllyc6iwl`Jpm6k=Phs8A;M<*->S%fa1%tqv1{j7LsL%I^y$R&*aX2DGqkPhe32PXYO)F$oeI z{z9fwpOqA6=YMfZe0EZtm3Ilbl-Khdq4zQo zzdR`)_oVRND{%LTdRQ#N|A}yk z2=5p99!SAIDAJdT@F5W{6S#*({1Fi@7vTyKt`y-ak-u8RSBv->5k4xy$3(bRgpZ4G zoxnXI;!le3DUrTjginj`84*4!!skTzya+dl@C6aRD8iRS__7FJ5#g&Md`*O}i|`E* zZWQ60B794PZ;SAqqbWf2>%u7yD)@rXuLlO1n_tuC_+nwwm9yHcu0g{ z5k^FqCBkeG<|LgzT-N{<>A51z6Jfpxqauun5Y}|FelAcT!onmzsLw!=NG}#)Ny_oK zNG}!PUP;H9o(4&A##fdSZ5V z`I?G&GZ8iqv`CC|frCNsA$%O}6gV_+7}QgzK+8Zm4_gIV^RP{zEf3oT4(DO}z!5y` z5IB;DM+J`N;W2?@dDt<~iHDs7U3l0va2$kgpc{_&f#XHkU4$oy@I(>z5MfUdo+QFv zBJ3@~J|a9>gndPLiU>~?VLuV}7vX6l93VpRd=eNa;^H|aAf8hK;yES2pHtvG&Jy`5 zL^wo*Lq#}Dgq0#3F2WHa94W$4B0O7!qeVDIgkwcGPJ~q=952ENBAh6~Ng|vq!YLx0 zD#B?ZJV%7nMR=|VXNd4T5zZ9h`69ePgcpkNA`#9K;l(1HEy7Dgc&P~Ii10EIUM|8b zM0lkLuM*+aBD_X~b455$gx8AjIuXtn;q@Y1Ai^6&c%uk!65-7vyhVh!itsiOE)?PI zBD_O{cZzV42=5Z%-6Fh4g!hW@J`pY!;r~RqM1=Q?@BtA%D8i*8d`N`LMEI}>9}(el z5v~y7N)fISVYLWXi*Sty9~I$aB3vuN$3?hKgina@NfACJ!u2A2T7=Jt@L3T)C&K4N zxIu(3i10-bz9hnzMfi#cUlrkNB79whZ-{WC2;UUpTOxd0gzt!OlL$A9aEl1Hitt?# zZWG~qB79$jABgZn5q>1X?IQeGgrA6ThX_9v;b$WJT!deU@JkVXCBm;o_>Bm^Wug5A z$qIZI_?`sIIzlgc9=vH;5FY$k;BP{DG;dZN*wwSe^TcWK@baM3tRNU}ULDM-4#uj3 zMLnB0Yf&96?cd^I09a+LQ_dlQe~23n{2UH8D(eghA=n{}kltmir)~ty4ml{eSFi!3 z=8%1ZWx-=3+cqx{s=PLHUgrKn?cqK-8e)ya>jKRu#4OHo~P zqPm)k>gGq(Umj7%OHti*qQFnm^z!)<^|wdViBeP#ohWeGG!@m$M@qWb7W zoop`3&)pZ8Qr-4etPu4IUZ5{q^SNnQKy-U@^$&9dqfS8qE6R|0$*O! zHs$N`o$C>Gh7>hOCklLsO-1>tsf8XUK{}RZ3CAb)rU?i}F=dUQr{Zs8KpmXPb-i^E?$;$_)ztqyH8oj^nxYdm)m)UXn(~U8CPkg26E)pj zl&^+qIT6XHhFWqHd6)Zq$jo$y}75H{`%dkEolas9SWRZZ#L> z=Vdgo$|LGFDQclk)a~^ws@fy!4k_wRov20ssi?c8sJnHd?x|-{t35S!uM~BkPSj#^ zQA_;v=#P6u-7iHwpcD0=xhP)`dFwo)mP%0%=|n9v7xjprn(~TTE=8@-iGtk*>UHe% zidrQ_RqI5-b_f5Vs5Mg5qdHNry@IJIUys92d)m}mDe7^ZDA?GcUPV3U5%q)=^`uS| z>?mO>%2${0yhqe}De7sRDA>uuRFtpF=N0v=6!n}=6l|hVucBV?)YJwk>II!B*uA4( zMZN41^^z3zvQ89i9AYZUSDSjxBkENt>NTAx*s{b_l&?1B74?P`wNWPuc2B8SQEzx^ z>MbeiZJj9CmBmz)ugmwQN7N=MYO_w%mUT9UCu+O7C|_;rBaf($rKnGIqIQ^z@^$&VqCS+*f>5%rxE^}S9M>=9M3qQ3Ho`caDd zNhb<+sxlSjt4)3D5%r4{^{Y-4?3ZOK%Gc%diuzrO`a>rQcI~QHQQv!N>Q5=^FP$jZ zJFH$s{p1n#j}-Nov6}!78UY{l5V~8`md?xCGWW9fH}>Uu zL`g4eOXp>6nR{9L6P51~b*Q|2hv_a~OY_Uu%EuRnVALb3wG`DxC#tQvC|{2*F^{Nr zQq;X&)l`8;)KOB@(K=Dbn2YM@r%ko;i0ULob=HaM zVlL`9Kca?sM0Jy*j@OCmZY(P3$9Fh5*(2%%De6R>s2;|mtdsoIlvh+QDXOe20D2)EZAim%hW6 z&Ue_VgYWR=elFi*9#PVF*wXn9TXpaq_9beqN0js(wsgM3RvmnYeTnjTFIv)f*wXn9 zTXpaq_9e>WlV?faVN2&bY}LVc*q5j$J(o}V4qH0kVXF?l!@fj4#wv8bT0n)0|*S}UZel{!(Yj79mYDX*w% zDQdM&)EZ+^{%UH2r=dS8MLnhywbodaznb!jdR&THrxW#ru_%8v^`fVyo|K}V(urDc zEXrR^c||=fMLnYv^{lZde>L@zr>35hqMp}@+F&foUrl*My&y%ss1x;)u_%8v<#A}X zUY4R>(TRH1Sd_n-@``#*ih5lq>J4L2{%YzKPn+5(MZKvL^_HLS5^|loCj!x7j zV^RKU>UB>|ZI+_8=tONb7v*QkFY$_cSBl!E6ZM|CC|_^L9)EP}eJSb#ov07ZMfrMk z@rwFLirTId^|84qUp2MS)22R=qIT#+eQGYsS50|EeI`YHt`qfzxhP*X*X4WLbNBr&Mg5@@wbNXbpEaYzD@ytfTRPuitDb#_$tF)tN#9{h=R0iG!FSl# z2cyl&qTp8$#MYU%&Ue_ZgYU4fHsuv1eTQwG@33v|J8Xyj+X-QNMX= z>KG~NSe>Yj^(^Xlk0|LoZ0mf7ZFApY+t=m$!y~Gztf}L4HPx-2Ys$0hw|%@6)mk@W(M4c{04b+J`!&sEBnhJQ9{Mv)0s55n< z1{;g=H6RB(OMdOMq^Js=s3FFpe0jtM@;#Sts1!9!C#uq1l%J`f6j9P2-PZY|+vfi0 zzGhugM2(U)b+)diMw{1^pDF8rXMvbKMv5A%6E)6Ul&|ery`rk5sPQ^c6U;^VdG8A} z_B8Z~Qq&}!sLAG{{JhPih?*irP1T8-W-e-pk7xA2{+^mTM~a%R6LoGqi#o_7YK9bb zo=((Eb5XvwQ1Oa7Uy8awC+b3TQNFr_rk3OmzOD1zx9i}!@2m6d>=7kB_idf$zFh~;eP1=@6(v3QZJp=7ZSJ{m`B}^pINnoJ z(sSR|dG6cw?71H}!6Qm~?%O)geY*~x`+h!y1bTQxNzZ*-=ecj!v*&)Gmq(QJ+_!a} z`*s~X_kGn=ACD;Mxo_({_w71(?)&+)78vLeB|Z0To#(!7?zwM2=;tBt438+e>$k1j z_1iYz_1pIKjP4aBcm1|?yMEi|yMFt7Z6D;RDY@&nt=sk6HsAHzpQtlEqU5gMwrUx6Pff{Pzir*F-?sU#-~MXKD@yMAZR>XZw#|3__E%G$EmUl|>$k1j_1iYz_1j-f zc}2-xzir*F-?sU#-}Xj7!^|*Gn|f2eA-|=2Lw?)%4cXq5xv0%j)E1qnt>&V9)l{XY zrldc*t@B5>&Hd5+)s$D1^hdXK{^+*3Kf1p*HQZBE(jVQ{`J>zB{^Q^c1H=U^8%|-d@(a-kO z)E`pRPMxSf%|-dDDX*x%q^Q4jqW&=!DAb5VZgr&4Olm7)rCq6*DL`EdbA5mh8b73)Nm{HLPgQdFr<)LzD-oH9RmU#aKr zlm6(A&L7<|_eXac`w_L5N7TNuruNg-R1@=>Iv{gV2TD-~=|nX(7u7s-QPRuW(Ro=r z=3ds0pASaC2A<2;Qr1+tuBKWU*OcXJlhKAAQLUw@HabyljYatzX1t=Lm$jqwvUcj= zW$kCxTF@)%2w77dbTxIPaZUMJN|z$)C@Jb_ov34sMLB*xLZ*n4Ue=Dz%i1ybvbKC} z@$0>O(#zV>d09K=Ue^BZzP&wnpY*bJbY9kuxtFy+QH?yJq?fg$^Rjl#y{vt$FbaA_ zNiST#j?T;4G550eS5qGMH%EF|J323G z$K1=>pQwX9mrr_GJ323G$K1<$Pl%FU){f50+A;UCcKq!69rU=rIiuxM!Wi9C!dT;{ z1YfR7LC^0vIOC+KDxIkD#-f~weqJ2fdD_$@DQdD#)Rg~J)Kn>InoiU?|EZ|yQq;LR zQ8WHiQRhifGj*cQ|4&6-AVpoM6LnENi#puX&}T_e7wbgL{!c|+B1K)Q6E&xvMYZ?T z)MZlCl%lTEiMqO;MIGU(scWRDxjIqv{!>xcN>SJ8M9r^fQ5`%rb-fg| zKqu;k|5VhCQq)a4Q8(AKs3Sc!b&C{rt4`Ey|EZ{jQq=7_QFqj{sG~eJb*B`yNGIy9 zdKPuGN7UU?)IB;;_tvwhV?3hnlcE;uME$RxMIGxAwM2@#UnlB;dKT5uBkDmZYN<}t zL-j1Gi$~NlDe7UJs7LBqR9BBE>1FNcysRB_FKd5qGsk&ENiSGUe=Dz%i1ybvi2v+vzW(`Ue=Dz z%i1ybvi2wHL{CjgFKb8VW$l=IS^E>^Sz+WzFKb8VW$l=IS^E>^`TagedRaRd09K=Ue^9Z_4c%>H{>w0Q8&!ISL5*HtR%fsb^7rJ)*WsQSa(RZL4Qdr+P%aCq=!l6ZJtoi|XeQ^`R8?kxtb1dKT5+ zBkE%*>Jy!)9rY~gG>@oHrKrzzqCT%@Q3E`pzL286)QS44o<*JR5%skc^^H!{xAiQ_ zvu4!!PKx?oC+dfK7Ufx<>HH`~{iGB1b3Kb1B{* ziSn#k3rTJ*4wT51IR;`>QF>5|xnj zM-S=z(L;6cNB8BI;1$(Cb_r#=E}@}um*DRW*(+*qDQX{`s7C*(sK!#%zB*C+{imXu zNKyOiL>=&-ijtoDA)V)bs1Ba{d!V5=lQq>`S5qyFYsz1j;8`FRI#`N2L?`M{V^O|- z2q5Scb(j>@QYWh1T$Hb6PhL^2q^Q<9QEkjc`Pl&{rKZ|SQSEf14mTF%uT70he#Hv4 zm!gi)iR$p5ijq6Yhjcs1hs<}9-xD<@cajh3c9IX7?A5>kog*iJt0c2aR}+wIE2jCIP3{ga*absx5go4 zzQ$osh>~j@Lb^2$A@em3dqR|4;}FuVaR`~OaR~W(L!RjA5(dZ~{d8TAKG3*F_a|zS zN7NZo)F7RxGmS<0dvuxX5j9wfI!h<2!dR5Qn(~SoB1H|=i5gbVqNaFis#1y?Uc0D3 zXhdiv36^yvgd9PF@Q;vCvj%HIV;=-7Sk{@vNdW$z&B==~M`&EA3ewDvEew1tj_$poRAER4t;PRdc3S3vUp-TGl6vhNcl(&r5hN^gOY6N7PZA`;rnYLB1V7IG<^8tWC|lr}+O zo8fN@Kc)9WABX}clQ8@vB(E71SZbF#rJ*&UFVw{zk2z(H=7l~CeaYK$Ug)FHSG?G~ z&~{cVV+?%^7Q0S)p-;eaxU~bU5EoS%3VjHIK7zmP@b@wNeFA?wxWKQ~E%bY}u=E!C z4Xckt3;l*u{t)_6w4XCT3saMg=e#DgQ%&0%bIJ3~4*e{uIXlD(VAY%*`UNa@zS*H) z!LmhL`iU1FvjGx?%u&b|g$%4c{i!~;f7Bw3&h6jOE@cA>TWZqu29!9nh&;0ho>`&+ zC7lNegzd1Cb~83_(Qr*T+q6J-Zc{o;054V*sZPE7lqb@<7(~c&7QX|(2h3%YX*7Y0=NON+5enq_EveK*@p|^ z%w)4?%>kNzxBx<^R>&5G4A3;frOLA_GdsJ6;l0J#T}UGEkC15MrY;HH-x+R8c4J1HtqdQv0UpX%hdVNpiLuH$vHz1mPTHFZo>Ek_qCmJ)7>M|d znoQUg36BTDu5~2r9zH=q*aHcB0b!3i67~-FQ4sb;!hS&5w~mDU!>1_-Pe;N*KzMo` z3C|1Yqs3T!zc({UaBodAW!jW|(91|X^Agn^di9lFYN5V;gN5Z+`d17#` zd1q|CD%|c7xOWZS|H)Z_79i+YmOFf{c!(lr@hO7Idh@X1Q>17_g9O7K!M@F`00GBfb0O7J6Q;C@Q*3NvtjC3uw?_%tPW zwHbJT68xwc_;e+Btr>Wr61>g~e1;PIq#1aS61?6Fe5Mloj2U>a68xMQ_$(!OgBiF& z34YNGJVXh8*$g~X34YZKJWL6G-3(l*1aCA04_AWUG6RoLg5NO%k5qy;n}J6u!CTG1 zXDh+m%)q0S;P=hIW0c?z&A?-o;O%DMaZ2zfX5cC%_)|0RcqRCAGw=i@_)9bJL?!rZ zGw>uO_**mZWF`1}Gw>88_(wDFR3-RlGw?Je_*XOVIZE*FX5i^c@J=)Exk~U~X5bl0 z@IPkY^OWFSX5g7Ba3o*`K3@s8%)l2Y!HyaDLM1qC2EIrM&N2hfQi5~Lz!xjQxn|(m zN^rgz_!1>JW(K}g2`(@L&ryPl%)pl^!6jzk%a!0#Gw>Bka04^&l}d0!Gw@YP@IGeX ztCir!X5ed-;Qh?NbCuxz&A{`N-~-LT*DAqH&A`_w!OhLU^OfL(&A`_y!H1fG7bw9k z&A>M(!L7`|H!8tx%)mD(!R^ezH!H#I&A_)P!5z%Nw<^I$nSpOpf{!r+FI0j%nt^Xu zf;*dm?@)rfnt|_Bg1ec47b(Hr&A@jl!6%x5?^c3)nt|_8f_s^P?^S~Pn1Sz8g8Q0* z7c0T1nt}hP1ot-sFHwRAn1SzCf(M#`A5ek^nSmcvf(M&{mny*(X5fdE;Gt&VWlC_R z8Ter(c!U}F5hZw(8F;x8JlYJrLJ1yg241NISDArVDZvxWz|~6dBs1`8C3uP%c#RS~ z%?$jg5Tq@M1IYMkRQO8Td^l z_yIHUTT1X!Gw|C=@G>*-J4)~)X5dXq@Cq~VW+ix)8F-5lyxI)BRSAC74E(MVyw(i7 zO$lCS27XToe$ov5z7o9N4E%u-{EQj+LnZh*Gw?@B@CGyRb|v^lGw{bs@XKc4Pn6(S z&A>a9;MdK-pDMu{&A^{2!Ec#?KUad^F#~_01aCG2f2jm-H3NU81aC6~f2{<+ZwCHG z3I5Ow{H+qa-3T1{SnVCSz`u833B5a#049U#cnZ&VceOHRZh-P=2kZT$};rH)_fy8Bl(!rhFg+%J0;aOEaMSUQM|y z1Ii!Nl#gUU`J4$pa&-ojzo;o6&4BV(HRak2D1TE^uFHV(cQxgc z8BqSArd*!^M?s3|vQKp9X|zLf!GP)+$x29%bXa&rchwwiKl29%DPa$5$JAvNXu8Bm7Rlpkh5 z8BtSi&ww&ZP5DU%l-X*^Pcxv*QB!`N0VP#aewhJfuA1`e3@G!|l;37RnXjh&J_E|A zn)1gCC}V2MpEICz)s(+xKv|%s{5=E8LN(>i3@D4#lz(MFS*)h~Cj-h7HRY}hDC0`X zNFW2sQZ=QO0p(t5N+$!#25QQ129#xL%B&118>%UDGN9aBO_`eklqDHZHc?ZSW!o^1uuzTc|0UWs|+a1)s$^Aplqe4Y?lFLYc*y23@F>EDLZ69*;Y+?R0fpo)Rf0$KzX>DvSS96 z?bVc>GoU;|P1!XA$_{GEZW&M>siy3n0p(F@$`do7JX%fJGXu(F)Ret4pgdMh*(U?a zj%v!j8BlgoQ=XauWoI>I{|qR*s3`|zK-pDIIWPmtGNA0CrW}<4WluHb=nN=NQd5r2fU=jGvMK}0-fGGT8Bq37 zQ%=f&@?ZGuWI)+ZO*u0I%KmD~3o@WQO-*@G29yKT zlow|}dAgeNk_;#ZswwAWKzW9m^70HQ2dOEq%z*MtHRaVAP!3j8&dq@GEH&k|8BkWJ zDd%TEIYdplAOp&wYRVfkpd6;Ayg38PN;T!J8Bh*aQ!dPaa)g@ljtnSAswo#`KsicH zd3OesXR9gi&46;WnsRXllw;JCOERDwtEPM)1Ilq~%B2}lR;ekMWk5MzP5DR$loQmH zD>9&*sHR+%0p%n$nsRLhlvCA|>oTC6rlx!{1IlyMl0yX998BkuRrrekTXeep$u|b)>UG!{ABPoY=ivWg0tpk%@aS6awEy&zf9C^dDe~9 zS+|@7!Sbv-mS^3wJZp(nowam%*7Cxv6)mc>9-UL2weFhgto1FLKbEzHkmXtLS7&Xn z&ieeRtS_sxzB#x$>xZYZeyS-x4}S`XWRs)FG2%D-*pKam$gx>Jlm7f@H~C8|-LkF~ zzqHaV>pJ!;IDE7HtRN&uApw371~mU7_VV|q`JY-eSF1E1ou>I;rRLH62SO5>`40tT z{hFqooUU3+m`#k<5|T5N;Gh|JkP>X0fzMQeLuTN?N^rysJS00Sy>(~j)Lg3MpMp%i zHHIm{xn|%>B{<&%>jWiuf3uP&W*?xa{iX(BQTqqN zxld7&G_M=UROKZ+*qns5gK5gTsO8tFQY-QtrGl1qQ!rhrpp^j$$Uj%9z~rZ|lJ12W zN)q#*z~VR5c}kKa3{FERIUG*sd?m?|btAbzNpf`ENG?>899uV%iP9k4Nz%of zgf;Vvl_ba2jbyfx^?yeYUPc$F_@Eqm6($frlnX=?wX5h<}=ibKvoOGjI zp_I>m>uk4=(Bw*`f>X^Eu-d;$SqJ?MNC14b5^d{>1IkNwy#YAs zmVHpE;06N{xMWL};G4|A4=KU7n1PomYyCDe@WaZIZ#M%!q6FV*241cN-(?0~p#O7Ipl@M}u&yJq0mmEiZxz;7tQADDqRD#0I_f!|buKQ;rur3CLV1HY{Ve`W@L zNBJc9g#lPR39`9|O-cn{8IS;Yv$FsG#tghg3I5Iuyj2PQ!3_Ma@|=@C`|3u^ZA$Pj zW+lI;l>M6-_RxwO7Nd%;1888?Qa8cQcL?tN%C*qNVcm;a!B1sK33I5PSAh^ z+WaR-Gw@eRuxkeXT6Lf2 z6qW$$YS z{#glbVg~+22|mCK{HqdtkQw+lCAgUx_;)3^g&Ft{<)u2r47^iW@?mD+Kb7EeGw@$Z zaBDO0-^z1tYX<&D2|nBm{I62>5oX|BO7M|J-~dsAk2V7bl;?b`891l}cQON8N^lo5 zu&q4j zhw7R;UM_P8%(0e>We$zt?haWiau&jpfgroj6U!W|$8ebgUm)NF*y0B0*GiSW${jUj zXy()cdnx<1MF!xcF}#72;DM{|F8%aYY$>O?^?5!kOQa6%)R8Ar}515mH zr%9lZQpr+t5>~N|mF;7h0SSQjRX&bCVg}w%30`3aZlaXE$_%`}61>_Be1H=Cs2TV` zC3vkF_#kD4tuq5RRhImu8Mv7eyxssD?HE2R=jk*j;Od-bjlkrzoaYqa4F+K1hK~*( zBfyogHVisT(x};h9#1!089r(Q$#1rn^c(DQ_gIlv)mr40Sme>H$jz(5SMHf2 zqop}p!j4!X_5iHLg%?jUc6rVR@TlHwdCn(g)j6M4=X_c7;2u3HI<@vk;cu&RerR5n zoI6G?sy+MM>YS9%yB0aBtPAVrQAo~KSnSLG8=Ld4SO7dWXB!y^g1bU$t_2yQa3~6i zQ8<@hbAA)&GFzO>ak_IkIy$3vadI(xmIwJ9wSpR`yS@PCc10My}Q{ zJ`7JK4k;uhG#D5cxF9f#2E}tn7h>;%2N4UNJOW{A6Zl`SYnakqfnmf+Bqk2*B4KZ0 zFr4)hWG?Fr%^Y9wdh<4SG{j0sh&H3m;TEw;8EruZKnb%*gdPlOPGAgaOb>xHm`4h% zr6g3v?w`O~-Xa5H?Ky?J1#cO8sJ1n>G-{1~{I$kDQNz~Qr%tW0Pt>qA_VL*o`xv*z zKIW~ll~HSiqW^!i#y+0b*jl#6HnKIgm94Rzd22j8BxXTL8@RCo&~kHN6tZv>N_}VO z&o$sO-yCSpFjR=C6VbNY*M)7s?%0l?9mL?`)kcr5rX5qY4NPIXG*w%ty08t}9b4zR zunpcFTbH`9RqT$fD?Lus+kD<-5z-`SygOde!>}&+VYvFDV-+20DG4SzRNgt(bg4~t$3R_wmJgF|)#-*^OooTPSXq%A2mZq(DU9?S2VN282r!LygNnuOVc5+>` z%}8NO)7G~xY%_Pqc1m5?F5Vs6sdZtSvpcqa6lT23I>HV2E$l1AZpTOAL2rO~=Bs(= zijixgwSW1bg8(!*>G_joul>0)C+Pu{|-8#2lL5;0kE zHuiKqhM$~W%B{7ZJF8zyGD&1SpSuZo?#9F1O<;3(8<&^iFmqHgE8TQwFmV$h$652b z)sY8rzOcxoXCqT|ttRqFbz}}`wa9!r&*&V`+QMN}Dme)%Be#2$1QbxwT@c7di&C=D z5mH`_r zXLGkAO*Vr3fNrWh%tmYFY=lusgN>4ztl^I^@+$UJ>o`;Hv~-)k9HgSUuBF=|rO5kd zYSWCtat$#KwPPNi^-L$`C$W;5X51u)@Pbg&)F#QR4i>5!m&j|rB-XrGUXwbkL_1`f zsV$S%7xgSuohGds5s@&psq(6VP6nt?$*cNw@-$bN^yQ91g0E*RVbYiTb@DS@m|m{E zFj@UN!t@FkrdP2ry#m7YDifxSX$sSuGGTgGE=(AeG=ynWAp36)X8-A_*xzX_6Q|!TzF22sot6{!let_J^wJvOiSKg#D*W*#A8_`@hH8|AX4Iztyk9 z{vUGo{|K}Hhrs?HG4}sBP4?d=WB)JY?2l1NgZ;nEWGz{kYAxBp2Q~~&La43PzAEya zk>}H^i;dn=tycI@GP2XVNm|UhwkX`*QEXa!*>-GK?dKBrL?S=%x!jHC@&}m9-E1!R z$cHS-(vnPvyd<+B|5*DWi!Z8XDI)HC&QJ4Y{B(d5_hK!NF?L1s z79yVVlgEhf;wkREBJzt(@QTQ;QrW*Ypv5S!M+PGZn#?sa7%{!Ex^uk-s>>|HcIW3kd!f8Ao+a@DFX3GLNei zI4trxR#s#}@Z2zF@D*v(dqqa{UV-R6k86~95{(iKrK0zWjOdMfuZV^@y|WO#q1cFK zF?wfndizxPl|d@}sehotpGsSWKb4URe+m&iwF-~sq$2oJir^8y3dg-yL~}X8^Dx14 zf#7+J;Q0!I2dVH?nJ~CVg|AAR!&ha*;j1zuctI+HugZwSaqkt;LQe1qCU_wboO&8b zG^!wYkP2U&3Bf%oe0ACcU!4)bS7%1>SSo_A&WPZ+_ljto6WqWAj|0ICMsSl8+^52? z3{v4$nGjr5;ZhKjMjs{`gq0LWptDqY7MML4FtdN4+fF8D0~RuH!||-USZ^3ME`@k`oXA> zHjFlghE1gn<#(u}jm0kV2LMvqGT_=%aMk{7bdu7Zp36ns z3WD>qp|}J`1xJ*#pB0BHqIdac<02^@g;V@^nA+{~`oaPF&xZUmXB4;##ZH>q&!%>d z6t4de{bzRq_3JpRTqk3d<7&?;s3(m?+i_Mo9AMYB&4v#nIK`%LX2>2O39wNK%%qI>}%y;5xs-7HPJ8^wxY zDL3(jt9^*4W^kUGA>*kNYR^-sC*Y|{&Ql#QPgMd>bznSoVzeU)8RLQcfx=f6$K|a#w~iBEwy1B1Xi~Eq?Cu`Xo;DRugVlt_0o1FC_JJ|lwaUtN;X^8yak ze?j2u1%dA`13xew@V}-4e?AAl0YxyA7+T7Yjn5 zt38@7L2Nrd)o5-@F`9}0mqzoqFq%90Xzo&t=59V3j}YD)jHM`q2U(Yvnhn&0_sPIN zkPi4mslfk-gFg>c7}Yctu$F<|e#iyytQxv*951dK-Z&{p7C`TSS;MIan)^wS^h5FW z90ZMC6Yz%fMjwt&w%4HBY;ST;`_@=8Iu!;0XHDWII8%?PEOB~s48}f3)zH{A3H z!^b+C>}ib-M%zir{N*rVeetmbQ(MfJup?@r>u=87~{p%t!_dSdxkX zXJrDdEETlbnLs0{pv{TSwS}V}m=aX9ThcIPF3pWq+Zb=ak=__}*E0Gzl12CjwFl?b z+Wxj-+ffzK`P}|qfbH-3V1F-QJw1_PU`>ohau)IptcftNg?L~KS$B(SKQIfnGqA;c zU`z187Q?`nu%4Et9N3k$9@sKGFo<@98C(8u4QvG;*h)OG6)>=stfwdWz|ON-u|iuDwN{=H7}Dd&T$? zmZPMg@Xs+iNJ+(9w$DJ5YEKh+Fqq(d($6t^Nr4M7@-4Q!^L=X28*3>@kc)vPVQpWb~9xsO|=jtRUe$8lNB1IaI)(7c6gwZbqA+{$GPw|+nzgq=IzYM3OBC>=YoC# z62U;{!Z$MT-wEJ%27|}9(F4Kna`ukl3*h8B2ap@)>>VZfLQMU7#fcrwUlKhH{&olN z?ME2(rOaNq2haKlBO$G6B^$Alx-tFjX?;YfjedRT0(~TtQJNfPJvjb<0iR=7TMCZ(chpf zThG!OMt_GgIJgfDbBwFdFqv`nha-Afw}9y7XR0Q-L2p#+Z|d*xQ@v$cPNsTec^Y~HG>cE$fG)9;PtoH;_Xsgp z^ZlUEI?cg}5Y|V7))}oW)W_(}_0f7?eJp67n?fh)V?&emF`@PP=x{>6iD{uepeR5K z#X^o2iiMdL8m{HVvX~a?uQiNiQ!S*w17$f-ma9JlWw}rW>wCDNqnW}DC7LOgmx;$D zRnm+Y54Y7PScxh09?g@nLUzeSxR0ujSFK$5k}1@bM=C^Kf;%j3uCrJa%kp>yXNs~m zUg15VN-!1=9Kk@TfX49M4j6&_7(o=}@x~}AO#fzeJYy5K@6vlXQ?2)qO|@D3-2&=K zBe5c99~7g}lFmK|iVY}$-9oI`an6JWS!@t$hS&f;OYuBSP;6vl`09&3LFJ#pmzbfZ z!Zs1uYeEY4iV3MD0I=NCBRZ2N80X06Qc#Q&6d^y9{iGZ|L6H_saK}!DaDKGl#`P&15WIr}iw4dIA=&%UQf0X7Ref;`JDd zAC`&Uyq%3go(v#X-w_zSp(QXH*c!100b1t{g;f|482b)|!_ccY8)138!#GzuLn2q* zVaOkL5Ea`U#${5N{#m!uDOnDsJ+-XLznfH&zgvcwDr+(IL{nzvN4onr&qx5mOV%P5vII!pN4$ZaTC zE3=HFl?`KYe^w8DmSRB^HS{b)?xzq%b(V3s91+-J#g3udESgdmHbHGG&>n~-gta2` zgz#m3wsJ26AltE>8%rGvK--gS1eNW#f}tL#Kon2PY~v_tO*)%V$!>7Al6Ax$PFMFp zePl3!-uRcK zNj_tW6G=XTSU?J75F0BY%3N-948_w!f?r{d(N^69o%euQnUnSkI7gN1O)z|Bt0J8Q z2i#1BRmW^KYd$vh_yBi8HAW%9 z*KjxZ?_J^P;m7z+eW#XpNS~->(Oopp;Y?FCyCqq+caJ&g4rx8L99|jkx5d(Iw~^IO zzf{W;+TphTUp$?jp%wTVV*tUw3P4x})kf6Ar_a=e>$CJL_1R%fpA~Md&&ism&(5mR zXJ+lv=ddO2I;{|>k{9a;8}}@5N7j#>1RM9Tz7@(kL0OLe3T)<2hO+E%Hz+#=%JRa; zKv`!f%MCvUWv4<}L3kpRb%C;cx)wSHQ}zw9mR155D5I&-a85Y*$*|I+#k$tse6q%2 zpZvv6kxVcq*&p9LFjNHG_G`1`e1Dy0#xPEo3Q@(ui`aH%MZQ)P=Jo~W$RF<{BL6!$nS*Bdz$fG_t*4Ivm zG}kYWeYrfIUwe79aB<{u5SPcnSRMy~JPu~^cmbD3Wsb(!B{F%uJV+kd6$+ayY0Kgj zj`ZjYAy|dd?Q)3cK?e(g3-x>j8-n@7GoFJW1}>WOjiGV|5f;t)svP^w3(4(zar-gf z7%lGty|`fN^A)zB$k_80`h(pO!^{1ArEFd0J*A${*qL5^fhpjudwJ|in{_Yuv+k9g zb+4{H>stLftUHXeE=>~4U5vwkbs;@0xEP10$+{zDtUFrHx)_x-mXR@>bwi-|fo|F> zz;EM%6#oLnh9cro{DMzrfx>?x?h_Um=gIj^ut*oEIMWwEw7}&H?G=YFv{zzdExv#< zpNTP+^To}z=L@S}hc9m7d~qx0i(7y%Ze@HiK25%uDC3KJ2X-B3bZersr{3V${y#utae_C~Ds&we&bFNqgRxDCb?|5P24K@eF^V zBC0~1=_M+K!#n~V^&a}!;1PIOpRX^BghGeHMmPZ;f!^UE;Y+!t%{&5UD=lqdU;Y0J zkHA9k2rSau>Wf2f>Wf0Z=u5IL))!~puP@A6t6RAssYl>!*hM@-cMRcM)I{ z=f$Q&S&se??DQXnvg~jI%4R@WUg#i{JqBgDVQ_!MWDLZ}LE~0R^OGW%Yc#nWTo3ue_aMJj2JJti7*%M@qy z;?lHC@tT3iP|H-TEkrIXQ!HE5{^V|;8kyB5xPg|L+I>=17TrKlRgn=#*ylji1yZQg zjjih~^h&)WU!0g5sH1Xm^1FeoRHxJp)De{Mi%fwx2L=8TRp69o99h%fjy-ShrQi0; z+Vfo2{=tPDoOYGO_=TJpzK{dO1{6?POEWEeOqLctCQl2mV^q?RwM|^?Uj+qBGg&`u z+5fU2^W{c&>D-F^zg%I&iAK(H#qp0nSOKS8eb|{~?O~bI`Muh&t+*!=d!MhZoAKHT zcV1$f*|dJ(&@wdC&Q!OVU6G4@R2Q3xD^$m6kUJ~3B?l*R)mJFA16*07x$vwLMk{7N zwp9{1jB!}0h|*^Vw32Yzm8#HJVKcKbh3OyLCXRBY!pvqj`Wkra%L4|)i+n3H$Uz6h zPMw2J8?N1=P2k$=Seoo+f+CzgN610vM#aaNo?4*|(O2pVbt|(ieE@I*#Gq~meHPZP z(dxxM1ARuXTW)q(UEeHY_0Ks2eh9C}(=)N@K@9k$BL0tFp^bg%XR5E#V5%pTH-zL@ zI-XSc#YC0zq{{MQ%b)W|ZtR=jX!IoHFk-O}PE`4K!BOS39u}A<6(NH@5Ac(UNHA7; z70hjCt+&<}m}s9K)^lM0RtFZvR-CC;(OB!gnK9KNEuC=d0B$^_9qtdTc8+2KBCc^t zMPTRXg+ekX{YmDzq|wxUfs?;yoO}v!@=nUhkZ>_CwhPL#wVz8+q_H} zeeCd*BBx>ODtao`K|53H$>+X;DwLjzxzBPH3Vvx>w{kU86#~ckvHgtjl|c9dmI~2U zI|S8M%Lw{Q?N>{jDVoG+ihuflBt~Bu=LZUq=pPEG5%jw=b=pSzvj60usZ*tHW>fbk zD3+mER97iHroOpZrPv41xe;#^;@r%WIWZ^8i1}CTiHUn6F`B;LBIZF%Oi1D%JIILn zKZlt55L*sD4J%wBg}upY<5sDmX-UnM z+8Aw|C^h41AvIS1XDT)0w48W0lbS2Edhr}vYCh)^{kdeK+Vgm|5YT^ZaqF;w&TTpnqm3h%)W2*8&I|>gQjqym}^odc0RZ9P~e0{G{WbqW& z_bTIR>70vOhN?`2yvo!jNa0$%)JZ!_>&5XEm6$>l1wjuG-G&pLFDsed2bFzrUHEBCx)~F)tXb&{u*#WHa)+o+% zeapw1RBT9BcgNBT*Xsi%EO53(qv>hmSSdhCS>ZtOX;n}r^&!>TXyUh$EqQ&K6BLZ5 zczwrciXWb~(G+h`dwI2bchrAFF0YNSyfy@RZN%iYF`v4Q_Bvl3B(G~z$!k+Ibw~QA z&XYV7WldX~is7*+tyOqH|5d|xtuTkp_#7T(&tbJA6k4@RD4N%P4z1puIc&k_uqB?u z7BGhp0tz~}g3sZ4nkEQT!pA{#m{jDaW8!x-eR!L1TjFih(-?0HGXrmQ?;8-NjhuaQ zyj|cv88blq1ousEJiAH7m1U+VSApN+B-o1df^~J2cBgg^UtdSk3TVD&WXBi0E zq;ZqDz}*)?D_EEzhe5m({6DPU5u`(tj9qBbfnFf;m5g0Ff)4G#*ySEAFMcAFWkb+x z!+1w1qx;H_ISYL(W1*Az#43ezT?+qS9P*Dko6&d|^{hrG;u%?&!g(bq*mWvf>)%wc z>jdHK%7yc^^o8^E+6$-EyCa<4xNx3c zw8(^%PfRcW#6W`Vh;Y$%z0qE};Kk1YM_UyBgxgH(6?cJ{O!4%U>)F#Kb_(suA zs}f{;K%i^`nlxhq=m6UX7C%4O2S)2*_S&Fuda!#E)~zCTqb2W|_+XNUZl$ohDnYl3 zHYgqwVJ|-5hne*aDvMD#D%+rZBD^X-q;4{P88raKA>JUJF>$N1K^ejU(_s;VUB&@o zTtNyDF$zgx@D-g6%ExdUxL6A&E3{gaF50FxPg+&nVgb~N(yHPC<_3j-jd8{?F6O%h zdYjri@;-zE1wiM&(yBhp*Ga1uPT?}N!7D@YtEiwmvc&5>&(e4xS&I(~toMRZ4&CB< z!@1&!$w*M6h+q;~u0~;di3F%o+>(l43kvOe<8a}OsYbE2XQwZXd<{lODJ&kp)F`r2 zi7KteOFkSQ4)0|E_xw{^Ad~7xB6usQ);h-m0M2sqmlU)erm;{K^;FH@u*0 z$hlM)1OngCl2(9smmE+QLg6blcsh6=urShwE&bz8*5WYzXhvpU*P& z7qU*!YqH1aFJ{lzUt&hbgRp`(0u%2>W^}~C#2d|wj@Q7%8^cVz)nMX{WhUNUD7y*D za=>xI5orRN zEsE9et7)4XuX6sfF71k_L;v0RKvE(rUTH`f^)^LoL`(#E7(i*R` zE9XdSWJ$HgX#F1jen(4aZ^5<9|8HrDDYeiNSP0omYWk}ngd6ov`fG6e@^vP7mjN$R z!Mh)XA`HP0_2LhJP=qupc>jU2Y>f)ugHV>GQNeo%$}GW~1Z6q;{ZRHWl;!I;K)uOO zMo+V=9D&lSWCArMZVOc50hkm+)AHlN0`*850`+D}fns}t_;l!E29~QgRhO5*>lmL2 zf3w9FH%r%3(F%A|d20zIyb-{jE5eqC?64JBtSrw)ATHN$1`8haKF_{J2LFM7El9=} zCF9GI@h5RVZz;}#XaHV(75r7D1?Y-2DfgBtK0(N4^p;{z5?=$GhR=nenA+V^6e2Ic zIM#ZqPgPXs#>rbOogY^-0A`(SbutCV>%DCp2H;RVM>SjZoy{Ig76EqAvvMtsv3$p9 zBS#Wg7;PV)OHZG_qexzZ^!Ynpwu*0HMl{cP%Lo3hujUIjft(B@u;v{m#9nPu?8wDz zQkxX3k9akAlOo!KZhqp^FgQ!%HUuA6*x zec7UGd^U_`LH1B#>+qg}P~uMDJ)?`X``A^y`}d4`B0oF3Es>v{o%O5f?X2HdZl1ie z^uBSb6je5-g1UcS5gZh0zz6oecYhOq&8908Y)4R?4a|RK8yL|mvss}?{p`0{F$b*n zo0wTQE5nWXz&86B#@+W?V`O8CzwOyXexP`;*N$xD59MTIygpC`j6&Eq^wh}^Vv;{l z+{vdK+yLC<;RhmHf1ucG`P1 z?Qz3-VG^zfSA_gz`Sf`zG&u$BNZo z&|+y@v7!BG>~-{=MIxcy=OV6ThdXq*0pT`qzbs-wkKyJox>PgxNg z?lh5?2H9ON*WU`groSE9tG^R|UVk_Iy}l{?Wc|JD7xedY9@RJJUaxhaqQb`~xV<4MWb<_=nV}&)NuOA3<4u z)+#9bm>TujyP<3gloe)w1ZAHl2065>1Rx*y1gD z{R7M!4=q1YjRZg6tbd|fzXiwtCn=68B6NfFy*ob? zMue0SpD0!|w!H4K=)G64O1G-=&(pBHpD{;mRXA#+^Vp{#mU^7!dUQ3=2peo zjA&eMRm9kcLa|k~(l=-hquq;UGa276Qc8aHn$AY%oUql@7E297ai0!V<#($XFNm{h zYR^d_i{igkc`M%X0K|mbZd(mQ3fpI*d}74Xue?Q(b6#{8Y++1}wyE)7s0_mF{RV%3 zq_NZgRG}b6+JCAzQ(>f^0bR~aqswiI%?!J1!`{?8N}=J+8jz@I5XOxQfy ziuQi!&wF1}LOJ6xWFl}!?26tMeR zvBrwneU)|&gB?oKj_ZaUK4Ee_J3Nmw44CmPSk74WePbLWrIcuAexu}AW-$l*fxc1Q zP6_k_eWS?h73c^0MiFW*`hmVll_U=6E`wgp`aAYpC6>VlUFz_%1X zGTuJkf%}#&&mfK>ztR62-;y@}pZS&`_Ej1t;Y2-1DYs#e(YIzN^iRO|vnBgZ{Zj~y-3Ulu&7?d2-w`=q|2pyxeE+WRh*s*~#P;gn#)s?y zz?Z{(NJb&}azgptwLBvNW!d@1X$_4ilx5}5hO!ux<>ucFWpOCWDS))Rh5=>y1(254 zFrh530Q^Np5tJ1cfWOE{Kv@BV^5z-EP!^3hg|ZSTgNTgy5XWB>A0qJ=8KrUCUzBqM zc#9w+BkK{6Tfe`^C=c`(i2nuEbyXc+vQu19Fvx9=zugqcKr_u>m+s+Cd&^> zi$Ov8-HP;n26eEpjh~30-|vJ`*{yJ1{Ihq`%3ipWY^8PkNh-JzhqXF0nr*_2x&e5#MJP>*GL*f(Yz9T>s0-)Jh;Cd@a64iy}=+&l@O z(RH%@if6J!-L>E7CGAbrUHes+-(aq|eizfOzGWp^l-GxiWZ&rWHvuPFWw9p?y6igR@&~hgv~| z`yhyLzkWbJ5UQ{L!UULR5P={Py^|YfTP2Va`zdZ-^AB-S zKs=dL1=Rf02h$043Mbjy)*R+vzM4X)6R-ETx1MxeIw-Q>Y8ZHk#Z}X{dNuubt%?4J zc9#C9Hb(zTo3H<^y`djuvtnJP`o*EF_KS?N9h~cMaP^NRh}3#lMf*6!1#*O~=Xo3g ziI=BBnj+Uv{2cZqchZxeBcve=dvgqX%P>5VV|W#?8lC%gRng9%qfV;(Y-CJGqd9;$ znhuRaI@8Fu^%m_8UJoxCIzpozN28q#jZPd5NGHnBXk(#q3f0B|7=+k$8x;m2gh3mQ zK^qwcojC^LR2f}F3}Euu4H?f=g%wZX$fhccFic~rx)vU??&WDKY-Sq6n8`RDpQMJe z6pnfDD$>ccAB_(jNS5MGq&*PtEAyc&G>|cz)MI3%?j{?^nZiJ_6)%INF_3J9>sB_9 z?92wzT{e)O!a#Bq>vkFg$x);MkPRd!vw@r?8%QrZ$C<8YVz;OZ>rIfl#Lk#OKT#@Nb0 zV~oRv)zgD-$ZG^xo(Tu8v-4XMxbx$1*ZJUveQ=qT?Z9=8ik=NTD&laT_rcBb(jm@{ zRvoyGGq@(u8O-6n;)9!QB*1J(^o>qqONzw`m3APbu`w`^k;8q%2RFw@2X=(*;A;?r z21puj5d#HCn#5!Qk{s?PAKY9K-_@`nKcYRMEd~pEr}n3I5N-mVqW96yh5ydbm+33v zzdwgUp=_|U&j<|+4Tk^D3sr^I!hin=7lfmZ;`TjnIG7ZiCbrh4n8&S)ul!?9il8PU!oPwQ?k35m*cxsP|xF6xOC{^^EuF21+{!o2AWAmaTmU zo23uv21-8{%07g$T)h*NeMC1<`bsGK7|QbX=}@)>%JM?lQ1%Iw73zDTY%7!%ga$*| zr%)CRoepK&pezzv3uQEkX*@I+%4ibPSQv7W8lOX%8Tt*%zJM}=E>e!s6h1|gS;P2} zFVT0|)?XiME8*EMfqlyMMIQUKz|`)LIuB%4L;+fS`#30SeT*HRo19PpH#v>3xCy-t z7GIh%97=cggST7J}QrO(OJ%CtI;iqVdwSIJr5DA5m@&C^n#g zl6WsCv4;!T^%QrXB;kTWRXzio3w&F-LJ1fAYl06juXHDHpUAxnRG73x0FB zfM&P)$5U%z?o93Pd}{x&r?xGh+P1Q({gaE`N?Yv4TAQwef@K_0#UrKObVXEwk}~Ox zpm`a~M>5v<%R4WBv3cS7F|}anG&T9Wm@tjhx)Y@nu%0H>DgTmmT7$Hw(6lmBf^?cr zX3EskY1Te7WeAg)m^?G3i8E6|u>l1joo0cASl2?#C2rMBE*!2Vya`v)S4xx%KIr}mY9TD>Ux=_E*nYxRLs&q!7NRJm<6zY;QuzW zSc7z!g`Rw|b>E~XU+Jy;=8?5$7EEGdHsj246lRuYz$`~G5;x~07QK^ZMOxm;xFOH! zBwP05hzXE)(rn>n0!Zrz?A(fD7`*J8trbkr)?tEwW!bkdcV_lDKC|u8UiQu7`DlKD zH$kWob8Yjac>?@(V1A_hq{I(wD13c1+{NtV`hUz*{3KzS$&zLlN{F7?Ah152Lu{6i z_dg~gUyhAED3ZQ zBp6@`Q@c|N2P`o6bUu_&oX*q0EFAL=l?O|~!T~)$df_hJ1k)Di6w7zCl0Y(WkW=%Z zInXNu1DOmA=3FDO+b;C82A2Uyll0Rl zfJfJqs6r+UOv4gosw1(c+z#`-@)as^=UT7l%(Y%mrb$O|5s=JviE0bxpKH{;*2)~o z=Xw-kH7GXBQEaYnaOPV3&1SWi6_Z!0NS8??rvj&>R1s1uT&De|XfHccqP;Aek{kJyTx`>%LKMGJ#S0()8Nt0*n4|3(sW8Xj85s>TGKS5_SZ7A` z^KI!nQk)T-cQ;g)Vn(ELSf;odE}hCU#U&JRD$C%Uws2e;mjYn~^4vZ`#BQj})NYdl z_04*jJL~$9&aCT4%4Yp0KI;-egzg`ccJH5d)IA8|I4+1c<7poU(|$9X_FEi_3La^* zVreSHX>Wv8Qn})~e&HUk{x5eap{0IW(Y)0hZ?BaS{x4TpOodZay;qnMw7Xz&)U*oo zHu!QfOG2>$1$6bfJ?DD6_kLhP>rl02b3F9Asw>iiy`9%(LyuT+%sc2Tuw<6mI{brn zH!;;<>nfu%gZr~i1}e-u`C#wDgS`_5dl&2d?&xHDu$yg1_1vn$&tSOX+~Yg(p+<_$ zYT=$_Av_G?S*#lwS4kOHG@KhL{8o{dl7$Dv@rFZ<5NpkKgiM<&6S8}p@#+;2VNCZ8 zaN{t=cpIy@%^I&~r_fm8IAO+#Xv;KCe`C?u7$>EqkpCgn*cdCX*&u+DjS(gP;FSDB zM#+0QC10~BsZU8s$tDWpi0XU~+cZ%;K_jwF6GgTbkt|IVD+s$2YsX&W3z?xN3R=bt z*mc@j0K`VBcYnpjs)?!HC7mpB4QiseQ51n`{R#Gqu+#rGS-3M`j+?l1tWR;~Sf3)B z3f^3FCPWDr0PQd&&Mf3X*pWlaM^Lsy^-)rsp?T~VQkH~C(k4Srdk4Srd zk4STVAp?~onS#UR2xE*?+C($|h<`8_N1(arz~`caY%U&f>@WQy+jk5pV3GAKWTp)r ztH_f;HEDE);JP|iK`~Lvj#X}fkQe$vze~uRRAWv`np3c~bgW|Wj5MHb)9KnGZ7KIF zvQUhr3csT7J@e49jL_5%v=rQlQ<)!V8n_c5vHd__ImFk#k`aFzH^L;g_pzonL&`IL zlhZ=Uvcg)K(`_rPmH8;P!lr{2_9(N$W;k*fI^XhUh8hRRp~wMkRrygYt0ek4_%LT0 zhv(o4IZk!S3GzAed;z|8@;AsLMC?Izy-BP|V;p6hG>~2=A2O_FV!Jb>?I`yPDUf|_ z)(k~Hs|mFMJ+&KB&-8H_Ig zZUpPy+WA*lz1ur~>S>3a{{l&W=0bMn!)$nd<})&7euKH(Huqw+cc$Gry?tooM*!ql0+v7SarMXd=O|n_n zD@Zo#o82!6?t6e#h(!%MN|j47=-h1-%YlyO9M0Xsz$#WKX$!4V>j;Wrp_bI1L|u4-GB!mc-349`X>b6^~@(h|L9srEzf)k%CfZPT77dBRd3p}P_`P%aNPQ z+>tQ9V!u3Nez&$jbAH*$e%a;z5@Np?Ag$2i2e&-SX|X43DEsY4_qQDWTlRddAPat8 ztQl42en4(d()@*0|JALY*SyO7%g9Zd|LfWE#UgEnZnUf^(m(+eh2gNPG7CO(sZ`S6 zw4X^f{Ky`}vwqGcIrMk9r^9}Khvd=U=_7X5?*;TLw-O$5W4|vah4goNO~(2?O22aH z{TBB7JtRhdry07f-{I{a`a9f6VZUEWO!|8fDYAc0(68LeVp7b0?@Ws6?zaiK3S7FDCls=tNO#_m>3v<=8|~Tlbd|^vm&yqW11DW$c%#qK;KXCxgv2 zv8w1)kUgV;ov)y%tG)0Tr?Xs^w)howbBjws%R0r~6Gc5N*oA+tEvOp^JI4pQ8_sL$ zg6_srfg;d7UC@VFpbNiB7WKAJrpR;1zID?$L+GP#qUcOc( z|6QW!a;r(?hP4GpNt+B4nq1>HX<;>CJeV6Wn+~t_Vd*j)hTtsN2fy-C1S~k*0!>-4 z!UB!>Bv-*C=Lj9Zyk6^);^;Jy>?^?FNcQz2d7X=7n~ab=SLgtcyxv9fScIf2&F+vL zO7_DKgt!vd52wAOlpNtAc^tsIiT+g=jfIIUx;0reK3O!Ors#GD=y@#bu`@k)2BP8@ z{{Ad6y3>l&tG}Rb0F}F3RE~#@{aN&{y6C=OR0gnY%??mMD*s6qJ>;N0P|yqQwrg{OC;nH9XE=hrbWThP%%nw7o{IJYLrVAi4 zoc>i8JsFJ4r78G<;sR+qoIFMDx__CVxcJ;$CLjsS@sx|rX@Cg?@5EoOE?N_e&E@!x za0=$QB6x1D@XpQCE&|=4^VjHKb=MzaRM3RDx(P!C{Vl4TK(nk zTU*fGr@)Pq70b-k%=7AKCjeD#g92NzrvNG#m0{i$;5iqSvjf#`;LKhlOd+4yYrK56 z-X&~rAnNz@uezuvn6Sfx_zW$-%!069vkS7Ut`(Fqkmf~~H0St+hSm6W#*t`#_-L*( z8lz(1)0f=QoC_nNsfvE7F4`D8n(GBx*h);vCL_Fa^O`$1=cO^XBfY%wy4!w$(B6_* z{x)C`HAe}92WtM;rRMoQYD!hW4Z#w4gI5CIa7jBD$od!kt1fycn6x(rNg&#W;JF0foxC&5D-hf`4ms8>3?fGyt5!3yDKf%<^URu`8` z0gn#!ue#{7U|eqbXA0p~0ViPL&#lfWnJ*8J2Sj53zHPifYykF!3+&1afx*Q%qXA+d zfcB*e?dpu7-R8w@hYRf*3mTFRnXJOyP5~>2p=ddJ6OamvjwCy)%F z{p>;;7XS^}lRjxQwfhCd0?_uk&~EWTLkcSZ)_=U1?RQ~~XWp24q#kpV{6gv>H_2h- zFvm?2y|9WqI&zcD%kdY?vE${aiA;JnGDQcE?IYDihcs~Q&u97VI6pmzhZBdKP2d8m zPwLZ76FRAnIz5~mF7GsvBk42&skD8aKIG{Xc=IjqFcNVDF_ADV%1~#`?G}|i!%mb4 z^-JCQ6Rr9_MTE32C&$#ljRR!s7c_eJM54@sPZiN!U>>fgf7J;{tRCQGFttZKTZd$1 zfN#7F5dN-%0@4i#l6@z1bfvFtQ%T$Dp0omfH4FFmmYQn-hI=jwOxM!B)2r+t^Si7GbZ3rI#;cY}3Fh+RNqA6 zSXW#pgW9;TD)L=!^JL<j^_VIZB*h(U`6SQ(=H` zDjC^do#-f82NoI;Ae`ew@o(P{DghI`NI(iE_#}6Nr&+w>T@+8n3j?wR5~thCaw5^q z1@dSxke)IiaDkky?TJJm7sz8wDw>gIOe*@4W=JZIB1btI0t}bJQSL$pbeqV`m&5>} zw@0cIgB=TkJ+hIrAwM|)PKJD^JBcCQhH%_tnI8Gca|UDuHM!c`ywiC|<3O{LYzlDL(nIZMWvIcv0K! zX3`wdy#;|785(brWVww4>3*AcV0StLOF?&foZ;G=Fkufm4W)FS;%zb=HwmQsEN_#? zQ4>t}`ChuONt^Cf>Cycu58bI!VNBnWK->`!{|VxT4i;8c5Qshk;#&d6iNzqxbFaf@#EqfZ7a@sHw@{natmvNFW#N9FbPJURt#!Z5a+P zleP$l;|Q#imdHd(v(QnrsZ}dpID=qfo;n=QZM9-`V}Yl3GxZd-BkdTfuab5M)#J(W zGE|>q8xM)jp{UYn7h{aI=NNkjx3N(jc6Bt8t)0@1lf4kry6gzf4u868n5G%@s3y6UaVIPINI1V;2b0m zm86ml_)SuY2Hb&kkPUc4ssU3O^i1%Ej0T)#JE6P-h6QygUy3$lFkqjozU3MZkEf8; z6Um8;KJSnd5q&z6jxzeZPzzaoA(gCB24}pA)#FLzB!=21auPzV6X_&FttQpf1;}Pi z8dFEH%N7(?je-blFJ;NCE!4m*9uCDKc``Yf4fB0+G8*P7rdoypeO3g<$hS}d z7R+hnG=}RZEv`7uCJz=$^a34HI1pXC5@t69;9Bug6l@QFuhqi+m}d}*HY0XK=fbBj4pW+ zy7VHw7_MKDUI^FTq_>MJ&?OJ^%WH~jm|nX0RK(ZrqWwe)714+EVW@pe`XJQKA?LWL ziDdk5EmXvRQ>h5HL+eZWGE}}NeGw|>l5=fTlHN^EKhlpi*hTuG2IrCUWVpYPiUk5x z#v5s{07Jh&>Cdp)P5L8j29NNN;{tL4Lu4Ph z03mWAxzI&KB+FZ=$P%D1-b$A&7m2%C$^#V$5Ru0WQzGA4_=e2HZ7>5E@n zeX)q?3&zkx$Pk9&Z)6BU@e*>0i=wcTe3u2Z1@BEG@bWh-oI}Y_2J#Ow6oI^yTq*^5 zf^>5l8He@dyGAo<&BULH#9yv|W{Id0eg2ut$Yl)4gXA)V6TObB^R0B#?7%?62L`-Go{ zrmk@5cO$ux4YP>ch=w_ujCO~~$T5bDVfBj17*ua88SB==zM0(2I;l%;MxES3ZgD$d(|jwrmDM|p z+=}XrC*yfNe3e)G*k~!84&gd2)NC%TNe_BOuK!q(K+ZlEo`0+Zd); z!&8Cw#T$IAczZV5n9<^Pay#pxA-Ns(a0j`=q6NFDB}P4btV&cMq`?4sD6-5PiJ9$V zMXo|ovwW<`RTu%`XymfS)9DDu79m&%grl(wASnQ_A`gq3+Iy#fuwzsE#1m^$jG|qh z5uiz;UAB7S`-)MtOLaN`KJ@}X(Jl~R#N-^VDMTUau^8^|!YNX5OTTw_n_^cdqzKWr z8Lg!}UpNIist14d@mz0HWQG=U4*_h2wii^;Hbp`{Dodg&-kzsKIUd63ZfD`z!Alt( zU>v6z(zdf`Petv{B5Xy(gfPJE#&JrVi(83sPgT^$HMgnGH5+i({5Bi}TWsG5L@{8( zH4ED@1vU&%MyvxX@}chW3RQniD+(xV>aSi`EHZ zR)^(pBALjvY+EuBY1uo;oqWXs11@?1{(i!fvqKS|LUX7K%hV3V zj*eAM6d&i3=@m9G+F_!&om;%orXD=#325I%?qX=SCwC#V?z5!v@ z@*Z*zYgtL|K`rkk_xf9&;8?+hvl7J}TvT3nNe`&pNA6<)JCgel!28Mln1WF60rCK= z*NHrU>iviO$Ers|7Z`#Mk_TD6Q^$c9Z4;6B z&Nxbegdgee6d7K{K)vq_x$^eO#J4Q?R5@*3-D!Kvnl>JX_ZUaZ zC(x^U_Am{qBy&HPLYrXv!6*P>olGV(*6L3tBi5QireM~BdQ-_%R&OAgit0T=9&zho z-1n+>E?^7*#A#$2gE)vxLlCEv=?o$^tfLb}(5kH&3`~f$-J8NHi3`TS-V`aM0PRP~ zqYUi}$fF4D8DxepVstV`ICB zJchxjd_xxGjUK)8s?|h7gS>sQ#3^x?q(-)s^z9uKBbVUrPh?2`pm9 zhO@{lHs&E@78>(xGCO$8Ke3zT!EzQexUuzJpnTJf00!(5qtKUg(h zF9UJ|2Xdnetz-9F>mbv&b7cux!Zmv zv+{BBI0HF>JdQxlBl8516MZ0m!2z`pV$A4eqdA|z&t^oU|{}3o5SFG6rQnS%#o2C(8vWix?F29J}@> zJFc+fmz}+Y4RZxq!C)>SD-g_;WTgOeg^k%tcYvP(W}O{Ic#=HHpgcvML{Oe0PYF=q zhCY3@2l3Y59^S%?u!^i=FxQe*2(=t$0010BpRiH>WDA zNEHM5JgGt;*N`;~r1S6;7wiAw>vc2|9-{AUvOP_nW{_&g(+JX9vQ|Lu72kjl;VY^P zWK$c{jRK}gl4S5-CrJc<9a$HMsjhi31>3^L^cnIDgY*V@20?n3JS$)dH>bs^(RDmE zj*OxWsOnOK9x{#qE$u|igOA6)E=^f_hb0;5f(kR+0)g7(^5EA#P%z~xcafgub=JJ+ zLi^T&hVB`li{Yl8EnL*#mkXerps{vO6u)nQq?ZdIfkAW{{i`ni2sF1plZ~n8V2%j9 z?P_jQIKcEgudn%IcSO4c`UE?`^n4*D3(VCP8vr<~cc%lO!0Uqh#0Bsp0|2w~DOl!y z8(A+@Tri^7u8OzI+I5qf0fHd}J;*P1QA4QsbLav7wlyM&DM+LMK)Vf?+G9wzyBP0 zi7~=USN0Y`>DQ3*b)+fXwzQ7VKHq_A3@_r|yZ8EDI#H{r-k+NSyvvm*h!ozY=zW;Mlgx z#C4`#Dx8|QIFx!Wx0d9)IQ$PbXXN7ghcdhuckE9Y9m)k$&&8o!7zofI#&Iar zp#N{_Uv){51P6lm8V(M&ph~RPI^M}l@X0I;rNa$%y#R_`09ok(s3*{(Z=%GF5-GH@ zAA@3GIb$V5I84}3001{iq%bcX3=U_JZ4UbY06V<}gqai;z^-F^^JEEl96{T^LSA7) zUYERrg#1A5mxv z&=T!sEl%{cz<4)N9j-A}I4pqp@C=&5RW0xuRGliPOal=Y`EG`;yCo+HwM}iU6fi_Q z0NT^4OFGNQa+;bfruM1|IGEcaE;>yo8_Z+k0uMa(gtV#L|T)Ebd*3E&8V=& zXsU>E5rv|uBF8if7nzR7*HmGqi^FTG*tbx#tmI4)Zcph5z4&&Q*Q9WJh;T2E*B02b zsWC`i(=z&BC$BT5eHM8gDeeD~|GG+B?E6LqM8{1ElN*C-!DhB(={wSsc&x-Z&xMsM z0{l*I=9fSQQ2LrwT$sORiepld=bEuNGZ`ZTY+-laOmQAA&R;Xty(EjyZ;&?_ozEd} zAUeNE-VCO5GqvWT3;0{)Ee7#i@)m;lHhEhHQ6+DQ66bIj$Q@(kX8sD>Sa^rL!}{t^ z-a&o6OWtLDiJJ{*90^jZN2NHR-j^sD;M!Y;4~I=;6T{(rvI*hv9(m6hFGQ8V6gtZt z=Gx|p?G*JlK-W&%c^H0?uj}{8`>g8=$or`4&1AFHH4A8gQP+j;sa=7)Zjmx*rQ||; z)XBAl#a7qI)~2CY&h1v77TMHW3f8r2b+^R(TgbCma*+ibb{~bMAV5RtUv&v2R0;Gv zR~QAZ+&We_b!nBreNHPL=>zfsqs0~E14N4t$%j5x@Wvy3L_T6IuOc6zmLHRk{Vh>E z5>SLw030rOvR&9MB?X~}%!&hL6It&2d@l2w`emsEM)Yh{bTvVcP zF(Nt@&wrcL^KU;G0IsgW`WBiN#Q_vVqm^8T!5y0#oSTrpkeWDXaHX(O zIsmMv{Lr3bqzj;lLpIoWM8Cu%X{T_diK}iqh2mhA6Qso~87;!@B3-4tuvJF^iIOqy zP>x847RP&zUP{Kg0Gg!(puHEsO)h}uQevKgH_yk2X79-}(K+Ib)F;7s$zIkCQ z_GsYV8Sf6Ir9}&e(MxWFUhfbtJ?WK(Jbo5pV1kmfKpWK=5bXnBNP_Be`-nb}U2>T#4xGqCuT%yGvB7!hZE91bs0cwv6!r{h z)yQDXJy2EtrnH9?kf&D;RoF~b8l$8&MV_o=E}3AH&t4|%w>_x-ZIzCQp6C_PyIsC+ zoeqGGp6d=J_qYI#Ne945UR(KI7eHG9fECHDO4DxYodl01_>Atep#eecKpcAoNe9}= zUh25J2i(C`G61lY(BZvM6z#8JUB5hv~`( zMGQ`o@+93H#=$a;&xF6(Vk`L(ig<$4S#|U*NJr;%uWaa@Qyfy$4Oht|0bf&_Egz;x zXj7XhuPR~;>6oQesd9t;&K9zTnU9mn7GyqtLOyZqe<2iK@2m<76i@Y_>T+rC^jud|Khj7Bsdd`{uo?!lfdr@ve%idQ1-Hd1auhLe6X*{g|tgI{OCA zGsOg52h&gU4%vQ4i0b<;0xXF_I^Cw&8Xu%U1l zi1=PF$HD_wZo5SQF39s|Pmg1%X5ja_(ex^d!AOQt+ zphW4i=grjO#7!oib+2L3oVq-S$gRLzQ&6b3dus%+XeAv#)27s0fxK115W1_5z=SPM zcSSexYw2L2kDCBZ+ava`3>tw99(?xZvJ}C~-2i!dlVIS}Q~r*+F(N7FkJl zAQt(Gd?jI#9;sO*wvA765C@=fr(}`XHdGt2NDsx_d03?6I&f$TEYdS=7EwJYidls9 z@ox>#FAG&wVfMZP9qGZtAzzD6wa4f#gGB4?{&!E7zkD1chr z3X-Z3RD-t%0c{jar?VAyoQFx6j0;TCD{Us}rQk)*B>Uxh1Puy}1B(W#;SL+v!~u$$ zAsOkF37ed)a8cS8>}r=ydIYh_x8z&KCTqyIh)upD-$~e{cN%Qcl8@KbB#0Vl;3?^q zjJ8D85uJLc&nA9d(kE>;>60d#$aG09hi$QmLYwr-giU&5A)9&7dE!kk7`X@@BcbTo11j@@YD6erSue(tCSWwWx6x}TG^WNYWeNEl_ zq;HA+1Ry<*>I*jMLHbu+^0wqS%KN4-oW4*+00ymaC}KV0D=~kMgxW&fPJgBU2Wks} z82yb7QX7Fq`ADOQ`WshETZ*Q2e^nSb3sZrJCB}o^h^79jP!(?{s*`(|UK+0S9-ass zuJoZYpk#n5v;}k!=M%tpo|GtzoPp=J1B~KqE)q>Ls8JjavFd zMw{(Q+6+{vI5uJ`0AI>r!*vbkO$xRI#)UAkfeIEAcUl7tMFbb63yrecDZ^rq8Vlu) zOYrjzP~C*48&!x+j1I*dbG|CCq7_>4J^7xkoO{XlXyx2Vc3LZ^=b&lptllqVH>$UX z>~Ti|uA@%LlHU_0f4IuIA9VD&bGh$F@*{)s7x@vv*h}`JzN$;$1v$^f|Q`@@Mih23eZz19<_y$40LSmptfz+(-5?khx?Z0=b{;7eE&JKwjv% zx0)=WhrdASQpmjp6g)rH1IdC#zRR{zUcuB7e!dzS!fdfHMTUYmgTh z&EMp22C^>s8-YAX4tl!&ANe1vcNqB}s&|MSl6O4>cTI1n#=(7CdN}++_^id=uT<*V zD@4~A=*IMm1CPURI+W-lB2XHF(hzIWlzs^=)i;$(}z+KloqiTC(|#X zMFL6^a+I#{Xb*S3O71{76$6xF)gcfB`Qs%=cQR*hW zDIA13=X8WgIkYWjaL=G$0$c(m#D_^8D6PXK>oL%0(Juk?VNi0I3p#0b;e2p)pt#Z=N_%;Fs1H!;vmW};FQJFS zq2zF(heYW)F5(x_+mcux1HuiUNdpG%T>2$|YX~I`G4-sW!qUnSzXmJ(fa~rl@~!E^ z*>2B`iz;E4>H|GX5Y}(e267OE_}Z z<2yRFK<-8_azkBO4uwfym=d`w<;aZ=LJsX6t&_@tXIpjgwQo1B@n+9s>!nv&=+cek zWw3WCq<__=!?6WhbUUZkEkUoX^NqDj@R4{-X#Z0>+O~ibrA|Z`OyU(xY~2gjE}UCr zaNun=E3r%I?Jm8qvf!jepxcDQNS8pj2{(tjCra;d2{a6d1EzAUL3Qcf5(3?hHKP;w z89<;1WCNST2llW#u;Cz(aM&3u#TNZUMKEq;FrTuCSo)apcoJv~;i$)Yhg-7mcOl*B zfdt&mVr=`=pj2QY6^3#;V1^Z=Gl2?qF}7obs*CcsC70X~GIf*oChxK(fkO%h_0Tn3#a zC>&r=JMw@^Fc=20R`jpBbhd;+A7&Xq9cAjj7b#aMlLg6e5t{5t(os6cl^8IZV&mvv zb?JNwLR0YO#*r9A6gfgug$OAZp{YXP6HsV@i_k(q1{Q|c%Iea^5`-SXmU>1AO%o!3 zU4*6ykrRN>5*MMxu=<@s|EfzN6Hs6<`E)FI86otjKnWM2M+Hd)gzV%)l!ulAb)KSs z)upQ?2+hD2se@2}l1oB+XW31ZuCoRW50)1$&p=Vn75Lp9!(7kZ+|p-UqS6_L&3vq1 zb?JJ^7#_zjv69vOcK!MoIJeo@D~ol%VEsN}4b5HD4Lj ze3PX4LJx-n_XRZvUnQSDJocp?egs|#YQ9y{e3^%PlCh71ntzU)V-w;l$BE`9yV93q zvxe$^6K;_C?ZEFbOk~!q@Q%pr5Y!ypcYy?X(xbwX#_2)L_u=MvM85`%=qU`7j>rfc z(O)u{;Fz);o`_1T@Gu$7o&k84Wl3O`!CiYF%+;8e7|dQlFzFR}M-|kdv6qVJ_ajmB7+I{mwlvL>m8<95d^aW z!$iYO;{6~Urg>OU^J8#xJj`|hD6PZRL84s{ypzC}Sk@W*S9^ngJzdsYcYkl80z3lB zJMq7QVD`c=T>^v(F|w2Z(HTL_&&AC#0R{x16v4bhQ7St>2&S;1#4v{jz>H#rM`1<+ zCra1{Vwl$iz>IlGS283B&k=a+h;(smiL&Jj62JS|8Fp)~)S~8wckzte6x94?Nplku zg!K-mG5+3#_qS2+Mc&@cK|#&$!o6d9LV`=LEQS&uda}KZ6}|=zkVfF-Xha<#We?CV z!2v=YwT)eW3X4uFd<_~kfghT%Mi0_2p%L}fHgy`Y*TjXeF4*(9I|%BT25?6}lOq_o zN%TtqcO;Y?>41ZG?zHEmwv^lt})Z^sC;nSKd`IUY)mcL+nDRfsgIF5BW2>TM2>i9%ghaY-R&coj-r z#obCF*dSC_87dBNaas?k-A_s$FWkQJnmorF06aW^iuA;*J)`1h^h==P2~ctZqoTR4 z#$1;)t8Lb&hhCMe(HHbfXw(5pIyj`~Tzn#wp2%A4pkG3Zj!@E(wXiZKlzoF4`7l*t zHeh6?1Lz^yNeujV^h*HW2}(L4@X^sV(Xq*5F!*@@PUtXoe2mozJy$!Kb+VIw37wn* zC8zLF<1~r@`#S0L2p6uP=5T3EDzj{;^z5xO!{P_}C17zXl$AB+>!IW;G zNZut9x`9e{xPsdN50Vr5Ou*nwhTY%vOTdnvadyYUIs}CNi4(dZyGrLFG|oy%*98_- zS)PU0XOmCBF78?N%UVCz7baN)ON=Fw0KLvE~;ACDJ^77B}~yfRVl zJ`Pp*f<3Z+fPFtUGP=O^6GnC(l$?i0c5?G%Ie1|hiTlHk{aHh*O#2HB2SCXH+z^Dx zUB)WXz2O|HP~LFna#s;3cLM>5feb;aTL%gVo)0DGGX(Q#{vRrIiB*7O-iAcgfN)je zXYdVUg)C;}XSzp%co40O-qPhqv>;n4^Gm^Vyz~H)-xf36r<|cX&M7^_C!#~GOzjS7 z|Ix-SUnPaNg87L2DWgM2D=y)SBRZO$j!2Gf8~8@#zS%8~NO%hzx>vor zTB}2WrIXn@?V-0;WngiJ4yVcGz&S8yB65SJGgkPJc-&0e;_M}%){0!pzUk&~p_g~V z2((FuIsuH)CT;4pNs~ITJ%JI%MdUJ~j>tQ0jGLvT^-(96^9~hl|AY6TV-#6A3-_@1 zv&(x>x$-{2PGh9s`3Lh5UMKDfZ=gm27O+} z@EJwF1bi-slFKnZqrLc~$Q9>$V2;OUTZ~ag+XT4+I=O-&FqVD^2wVvzS7HQUw&3bB z4?T18Cf4p@`X#g* z2PNY??F6h(RA?*2*(ZACk>-73w5B@XX4d-@`X%&!3zXb~dk0!ittp?DET6&Y(GlnO zWTy>(*pR7w-^w7*q+bH$@lY}zLk4;Po zpyakd=nH~3KAnut(#2JH)g#m?J^k0oYa_(pMEp&q_I8H*Li#1(eg~A?fpO0|0qWgQayN!*tz*oNoP@{Lg+06>lU}OD#o7uji?45nx~OyaCxt}VP`j&~k34YY zxg?R?cJcBNqu4z_m3tV)o}^y_#qNcYdp#5b$y${x2d`{=9-oV@IM|fW#eLBFJ_dOW z{SqKkoqB&Dpq;M9V!P69pv)MT{ zAE=ORix2bx7|a7~pzG+DFi@(#{}VXSYI~rrcf)dPahJw=gspXvLKq7kftAE7m}A8e zoQ|Vj`3N2aEFWYec%FUu zy-dG^p6HVGa9~dxIjz{sW0X+f3XJ<*foCWV{X{~XfunFaAtnO~lNoxi(=P!%x~5GD zL=W^am$yeN4ZEo@PMF zjKH3@28^U<;7A?=7>_ad+vt}7pV|sD1L4y*5WSQ-3o|TTtC)VA1u$kY_+Qd50sd?# znT_FFdkp`IqDmM;Epc&s-b?j@qoDbF8Exci1ci&ARtWV0iStLGA|IHJ%G<%&f9$gd2c?np3flvOuq!k3!r2{AmjtK6k#bn2gB#Q_XNOr zg2DflehKiYwYLz%xAta!-aA)i)eGEoZVJ0cc$gw|t}5!r16P%X+{>ls8uIk!V#LI` zDofivcs)1J?pXx%Tf}JlJN*)9yBJCqduR(>`e(BIFTw8V7ijlTdv*zfe2{(#ke5Qq z(m=@nOKJC<_ix)h=cR4;oQG8-UqqI{V3yH=5{-Td16>X!%Yz0=biS55r#iK_d-|t6 zg8qRcpqqphYy@HY^?%ws3&1FjE{@M^lc^*z0 z>v}U~ZjE-{&9JfAWIr|4V%ZM|3D>mm5;OH0cRGP~B1}EGQ7u+a^nziFW>4-K zSJFcBO18qrR+D{Cs>QOu4P=|9eS?PmmP*%+UWK;9#&(l^FRI0|zXN24(mvjM=@d0a z%Jr?4=AFV$9KF+I*@tSeEbju@rL>IqF0?GS*0fA7V|JS?`%x{HmYi4bs+K}(_?>Lh*8u1*+J|$Xga6>)nXlV2;`8mCyY(Zg9$Ek(6hR!@MOP>wMk zPtvfa9K-hSxNVC43bnm*aH8|pNpyMAbUJ0I7VC8Awc;t|MV616^3&LH+H_Dws>M3! z49FSNK{2oI&2RFb#lEwq<0?}v)^X=R&Z&-z^>%XCcmKFtq%+dX&-11p0;m?NhYKJV zlszau!nufj7fr`irCO}xE`eN99j7|8j_-Kcq@1m;?|2j^@|XMZZ1-jKciD6<)u|Ti zT4-*D zi*>{ekQ*^aDCei!yMA%l{H*Ow9Dmbfy9w1|*`^ouzgV*Uj=yji^YWsb=`Ke-Y`0+d zmZ{HXREyOoy)6D!IczPXhV3?X+%_H5nrg8Q`VHha?{rty(?fld&G5zelEX=}xs+=kh1WpUQJl zWURli?=RDFJ*gJ!xW^!mRmZ8W!Sc^-#(q)U^PRtisEnPS@0|Xq8GC{=dty54-c*Zq z)=xp6D$iPx+n!sTS+F=OE8j$Hl%{*LOW(5qrv9*-VR09Q&i>p6~i21&Tb_ zQ=JE${)+lxKjeCPBj$zay82Ts)^)uEd1<A%`KCEO{OGy6SaZmb@=}-}QbVOFqSYs`=EECEv=vjeMKR zQrhNeyQl3XOX)79yOZv|ETylLzHR#UD6ggeBmG~plp$}1vKcC%9GT(U46|e@W2%ha z8U0Xh%6Ks25n0N#B-7?hTVyHo^vugLuau=Mo3k9sa#WVG*38-}Yg<{$RybSbY=N?r zJ!|%&*^A3kj!HQi=4gWQiNB4%y)5}J@L%sACQCW>Iel}cMH!LvNY3N3lq*B70=WvK zJe})Cu3NH{yHoD3a}PoJERS8DRI-#ObDqL^ilN+;=U^V3N8S>7tLLqS@_62>d2zk@ z>gH>guLH_o@;%A-T$b{W%>QkEoPYiw^54t??3kmI_uVSifK+ zlwTDLEjV753h_d2g*;IP73yDTAj%1a78F{Ha(AIKh0e=T;bny*3U5Pss_^x~zsOS2 ztVN3!#q|{(Uvz%aMJP8HJyaCqP^?9<9>sd2+*|Biv5T@)I!oyyrN2b^bLmH=AInl1 zW0`Da{84r+GqB8Hl#|OWF0&Nn)-uP+oRp=qx5_>(`$Co~l&nyrLT!{m75Z1e`Bd0a z;b?^uvQ)8q#bFgk$Wo=iN=+-Zkfq9{D%Y%BN0zD-s}fkHI?C}?=2yY_RJmE@ag}GX z6p%HbXaLSLpnJfu02~((9&k9|7|MSF<-pXk6j(E`RUqaq@Y}%UfvZs74}2Z?pDa}^ zQMGzijBnM^RcBV6gYr(*msMZOQnkF*%2tDa)VW{hbse;;>smKM-ORF7uX4Rc_26Ii zpEs~?;2=v4YBgxxpq(r=Db%D=lK_+@G{ei-W_0!%-d!{werpSsLjyGVRFpC|ix}HL@?tO(PGEgrALa9OXAE9m)cuDvYX( za`dQ~qc9$$){WXTYQHRv=A+$4!*51sAN}R%k|;-vo;e!(M{gc|Y&7OG#1P^ik{e}} zkmez+P%a7y55aYZoDaDhg7_SheN3q_Wl=UA({oH8lsm_q8w0-?^C;9N6!8*TD>Nvy zBgzq>GecoF^rz52L!ZdfSb1#vv6)bI7(00EFqFr}ULOm;9OpGI*SNg0G|zip?s@r8 z)|l6J9^!l6{CQ#XaJ}>1&i9yal%@Fv=LgKMhBA2mtofLig?AVJyYQ_nEo!-_@1g-H zr!QKyXf4Xai>@w0d@a7Q_}Su@va}@gk}sFwI+rwA(qjqye98DFiX|6Fu0FN;tSqf*yr%n_ zUb3{I)`p-B=x^h&jng+`|HdsFPi{OTOJROt`N9gKtQXcP4E_*yJM2~1zp}I`Xw%o5 zhM=6kDQpwQW3%t(yqgQ4th>46<}R`n-ZH#zIIcf@X879h^|BOEI-*`gLzDv|#z(-P zBA##2Z*h{PExERo+fotbnk{>`9FV20c3XY6ra{?u>sMO`$;f(BGc=dphsIc8Zy}#`K z2KyVMoV$O+e#FK8e-5}DfWIGXc(Cii9w;{+JbV!C4$V2V{t)8gaI?d`4#VFMA3l8b zFy{G4k0T?GgrIzRR6d$omX0<&+Vv=oJG$@a<)et7W9g3-K2{9nH^*iin~n17vA>Qz zm8Ii_jt3sEj`HsDe~-hDPWYY3cLL*oqV|dQCpw{ga#D8^aegw#$aUUQ_WBgJ~idkbd=XmJv{~gIBhuXe;V;~`n%IxPGg)-|8)A#)A0W@ z!_G`UgX=!C`OL91h_f?y&ir%cjVzrlcedf#CMYA$o;Z6N<->FA9Q^X!7v~C{D~fXF zxwYrkqda-;mvgse>AWrebhIDJ$>*1yUy1VQ`Jd03$f zE-pv;@DjTOdzZ>yYH$hTe5wDXahE2dym0B>rH8V_Z2ZbGoAv+k=Wp2##&t|$5=7^E z`7M(pw{0S~b-v%c%(;a@jnc`}aDB_JU%f}J*mxxaz>Km$$v=9)J%%A zq@1ZFdjau@q1s7xc9b)eq%R`jF*TLdP0F*ToVg@_A@7f|5v+bvpDpE#C5wxB$E@Mr zkM8xdv4+WE)|4}sY%b^>vlsQb=qT1Wxy+t&29woA(G!I4eEmgXIGi<2P7|q|%w%_A z@d?Z3$!#{3GnydaeO{Gwn<6eY_S4a99_x@2rdT=6DdvLTze4-7PAO&fl^&3yF8Uo_ z5cQtbIMyX4d4bXsQrv~V!yBUB1M_FyQkpj?Jt9S3{5!lNDn|@wJyN1qC_N*^4!}FS zBPwS!WxZ0WcPKq1MGu1Vg=0F_CnfuX(kD{nw}kQg8hAJRxgi`h5Am9$++=}uyh zEVz?~OEqS}!lf*`l+vxlK)u7QXrSnKIb&YY;~SB9oW!m<8zmg<-43R7GBH^1aWWb# zU6i9a8R@4R;b^GPqf6^pi14-d`UE!U+kjen6pFHnVz6aE)}|5N&)7`O!ZAPt;3^+m0+>DUC}dI@tq zrTdA&OQ8GF;F&)xjJ)Hc1vnj>B)l-;Ua0g$F@PW7i8O%b7rK$&=+u(#2zh!oML6V# zIi%7l#UOs5Q_>(>cwsEnVbg?fezCwpLH$U+s`l3lY_9Ov zkLRySpA`f95q(zew-4ET;kO^xZ)VYp>W=h@4QL}76beV95^}& zyG%EI?jFb%3qSreeysFmG030Dm!teSLKo%FRoN2Z&!5hpl|C&7`V;yz4Yc_=fhgB5 z#g+-z{yYGc+;L4@jqDyF}1fSI{T}M@){D1y0nWgWshx zeOs32VtYjVSYP}oV@OPp6~>S{j+U`~B95#xj+C(^Cdo=;i6+VXAbQl_6{^Dyh>)`0 zkWz+~m?$d_E1D?t5Ao3tlA3P(Y_73GBD$jvmK_sumNeo_8EazFl1Qwn;*GatCq%p@op@8moS3*I6mv9jsy9Re*eMZu zNh|b};U^|9iG`m=2)1QsLb;t@)d8T${DMgOVVA4H%g z{XkU)tC-Ma5Uezzjue@$m+23f<8c~|KlH0F%&v&&O&-y!j9@XT$s~elQdJ+XjA2(r z$R?kVRfesY*kly8G_f{O3vlG0l>S-7ZSsm+W$cQ{O=hthcj>iR$Zm)bPJSV*3}Z3D z$uNu~mty)-Nd*0dn3RhBBH}oC#<4P%#Uv-wSf)vi{bn@Y;iACyVZVyNPQHPy3~n*e z$vC**5#Yax08iclt_*T9*~vV}Ee3j8c2@*?@(*-nu!{*#0l{u5;C1=feG%{}BjA-m zFD5;O1U*fX8F^||S5 zB_hFyTbFnFpE=10XA!IDdsoruuc(-FP2`=7PP{%6N#e_2a$6`&N1he_m$?nBb-L$o%rP)jFa+a$Mnk_kvBW0zZ)Z7Rf**D zzNBN`Z%#hKaYXWock(egkK*RXlz^gcege6ZxcL$J$DCi{TblEba2}C|5|)QBUXjn~ z;Z>O8PAIj=LLv*rH~T2tnKO}aAd!g@oQcSh@PQY;rew}W(a-6)ii9K*k}}aGq;5`1 z!ihvu`kPq!T$vle1a4`KrOw zh#V$zn5BI5q1>FugmZ~J_Hpx=>1K?6ek6a?4+TVjl{cM8WFnD$Xu^8eapq(u984s$ zkDkm-j%U6(Q{}XBJiW+iBB#A8H~l~R%y~^XnaFFOCa+;!ZB4(sV*aDOF3)&IkafE0&s6FK%WCAxAvt4MSr(fz-PEI!AZlbvulk?cNsvWuJW@HqoL=uw|%7YR=! zy!a%nkI}}Q^n}xir1x2p9yzV)w{7usE>d3f>sf!1^+eYD7#S_THq4n%IG)ISpDpv5 zoRczLboNue)XgPwpvZyo&0im@ojDH*=M#DG^X5SsZ*?w=d=)G;Sq5xJ&%}cZrHIx6wJZ zG{0+@nHLgyQRKyh=CY67-kckSGb-ZrV-K>h7r#KajmnRBUlAWCbD0+rDKdT|Cp_%a zj#KpO8D5MR6HfVQ2U|FE{Kq%iF{xHgJE+*OB{7Wwntu`F_3;*5_uhYAN3 zIn?TMs5*}};$=l1O`JR-^7H%0-JDB>lZsqwmAO=%PY3eyBA>oLu0`%kyfHH8RN<&1 zr&?`JRp-^IyrRgfiI+1(zK-A6Q*MoX4t^A`EF3m|gC?9SamOjfX>;-b;k1c686p_s zKmO)BS>d$ePS&dLWR*d!{1j^nuPX9w{Nr6YjG~@6;}&zXFq~Hx&YL)sAe{fh$34b@ zJMo&rfj@j8g%c*;*u^;ULta}rapFyc2!j7_?9DIXgcFOGa7pGRoI2>uKh21rD06&m zdc3;_uPd_h|CbrmgDkc`?|7Osvv6dQnUid0rlb)!JD2D6MRxwY*+gXTk3Zh#3@w~l zWauQFp;cKr>W?~{;tfTX{`gr#Wa7_1rZI2V<>ZZpQ-A&m5KjMT#@u`hBAi;>f+YD{ z5Ob1HKA|z4Hx>E%)8r2GaEtQuj&JnMi0uR3TsZgV9em;JpMJc}HzmTk#Z5`FxhXLx z4%?_7L5cdQ(hR(%Na3G8rI<%wl%H>`&1qaXxJcv4E{#(nNkyqV@(;Hwm3|)3pSKoi z{qv<7k=8%&SesM3aB`8_lVxhBgyNu`-lKj1wh?bDGW_SwIwH$|-tjhPdEw|H%O~3` zZ%QiaOdplw{dthc@t-&6h#dd<$J?Ceg|mx1pS<%t<~PopHpul+={}fu5b6H&ryr5> zKmVAUQ@(I`k@Ay$%BKWl7jugrmF@fTP9ocX{>&q?ed3I{IpYhb7a2cAWPD0A(SNSZ zpLY?-K5-I{Ncf2}?&gFq9A6~-6qE2N*(ksM(TjHzc|URTkI4IpH}2-#FPvZG{uGt_ zRX6=TMDkC(BqSDq#2b6_0w4lFEC4BP0Z_jPc*}c|Io0`PZkoeo(j7YGp$Vu48U3j`&k*bf~I6zfFd=P0pGSjQZg z*9s97VyzHsMU)RHUQ`Sci-mP0DzRW#$2^!93=tS&!4M0E!Utl%$QUBl4eQ8PV%@Nw zc`&aXA~+OzLpZ4QIA~(d1zvPSnEt$Zbv{fi9>OOQ(-*C^Z}S2o0z@nz;>CxC4@55_ zwfQ$<5fO`swI=e!J}>h^B7#ICi6r*qi2ki3aVg)?TF-;UdSV^ZBErKu=fS+Dh(Hl* zigyla!p- z8qPH)fWrAC5kMkhhT)phQ4flXE83bBPJ6=6tpYDiKsk)se03yki2ZE}ts` zO9Ym+IcQQoA7yaO7r`ZhD=9m(HJ*EPfZ=hXg(AR2fLWuHCiQcQ4l)+Z7mFYhL6+1V z+FH*)CeW($B_hy7pjoSZ$fV@F$@N@gg0e2(CW2A~WpZ`&q;_4(z}z7MQv_yGbKvBB zzA?dBo$nICDS|UOJ9|>RHf4bB5dkU!G$}f9azE#oAYI1yi69k0n%o^esa{`9pl0I- zM4*a5O{$KZ63&}~^(}K0ftnH~TU=w(O~&}Ma!=?lWU*}gkXTfc?mUVZOc`@$URXu2 ziocmE{vNlL`+)Lqf=}m1#QK^ta@u#C9OjzjY)r<+|+8FNt;8I;KU0hnR;C^#SwREP`3A&EoZP688aH z`a*EzKl)nmF#dyBqQ%nip-Y1}&U$>uyiALLPU0zA1eNs!RbtLX?3dD4#5yh9A~D@j z^!@St&%9QPpcZSjcuAd1d_eWmdKSMbmh6w0GR5*E#xk*efR^p5Q9q~mvj}eCkcsV( zqW_QUgXa5k5!}h-o=gPD#|@CAJf6|t-^k2wh{ap@MN;--^^(e&Oz7yc5d@l<(d>6oD@sF|iy`^!xdJ z&wQgV0$<$di+A!;kPk$^tLM-E5R3ljPrPEW6Jws3K44z>MewJfq@S1$C;GOYgr|JB zZy5hmtpCHS@iI zNCGKv9T352UBQ@G^P&2&%T@fTxFrytkyzd+`b~V_Gv5}7L?CVp#9IU@*au?2Rq$Ng z7bJde7VD#!gT(X!^Syyc1}S)5NK6M5eOpfgRK0a@g1;2E2-Y(@B2vU$B$f}DZxcj9 z5Vr~9Ed=2M3~wbw=v=0o{^U+A{z}{@h_xxP)+W)fb@`t8UO^-Uu}+A41>plGA5h*e z1n_^v{epGnY_W!l`AAG3pnC@M-|zfSBnRP)iRp}@Z|n0v^NR|R9K;Q!cu^sIAeIl< z=$u-{yczjc+&@@f{uXPhn3Kfz0rNeCNDyNEh_!wswquI^ts^;_o{u(tsQC{o=U1LF zM<3}hL%|G8&oVQa5ic~-}69Lfc(uH7Y+_gFo9aQpJCzWvuI zC$I+g;P$_=hB|kq*LkrhK=v&OmwD3`D%x?fQK$(p80$MmT(v1X~-pzO(-r&@$^ z8EcX1SCo%gONaDK?~sMHa=`gG^k%IczC*c!wQ=|jP?l#M9lt?2iFI<^gYqEj?D&}Jk*m7MB~aF6UFE?jC$VnwPblxP z?oM7z@05o1aB7IMGwbQJ5@iJI<#Y$-L)P0F`e>mj@eV4O^zSmLy&KCRiVBh&YVS2xpY-yTuOrNF}Tb2g%lV&tq zo(A)i<~&=G)|Tnh8rjOU0Vo@?RcVLeza4CK+DB|ny7X*qx~A;=bQ4f+VXM-eVe8Yq zWb3~uz&3o*o^AYMHVgaW0^5|{j)kSq!`7#-%=GE2vGDZkQ0`+98M3l183wVf8E{=0 z{$SfPu4X$j&0#w;k7K*CjAr^Qv)P`kmDt{Fx!At!Y1#f9nCl$=>|l=j>`+e54(IY_ zM{*Zu`rI|xu{?h4c-{i+M7}_FGJhAQ&p(u%DNuvy3$$iu3l?YR3jWQ`7plheg<7%; zg~u~};f3sCkzPz+WF)&(Bn;&tcDZODrY}00{qW^PrvGv=`|-;&C~vVV#nUi-@x1J( z;w@12VpoeVMEO0tRy>?tE3uUQTyhh;R`NO1mwe5xmny{crK+$SrGin;U^h#hLwTFs zDvdcTy^H-?dLPP*>~FYCkZl)b|4mYc%vl-tep<<7AO!~P9~j|Sdk|5f#1`l=b&o2moZ z+o~rytCo@TYW8rbP+v+&~>Mgllb&N&z@40>T>nMNascPVS zYUJY%H4s-ddUJgZI`Rzca6do-MjauxS%2;XUVgBu#9 zWBNw9xUo?Slx?|Jqa`Rea_>gBP~PP}jXjyZaW?MTxB<#e+^_LWl&g7~#y_Hb$kR3P zX8I;sdHN>)JbhDto}pf5K~1>0l1+qdL}+D|~ah!^gF<2!WW zMLNtzxt160fN|*X2QStU`LE+v{$&^B(=Ii6i7rD>PUa=M>_&Nxm+JDC>ASk|(p{^g zY{koT#W;3d$IEuThVoBdt_Q}iM=xH!2l8N#H@rg6Vocw&8n4(BzSHw5uhc6i)AuUP zEBC^A_8P>i^x4k?`Y~RmUwNkQSA_@m&&{h2@aKU8aDD^2@M>Sx=G6z*;ME2WV)}s- zdCjl;^IC)Y@tT9+$AiLo?ZNYTogwph?IFjQe#kXmcW7#+ADV&J8(JS_N8Vs4^5oD6 z-f-w$-e~AU-e`C^-gx+Ylt+2vZ?f?wBj)qQBaZNBsAM z|MBpF@wNDX@raG_OZnjOk5RtmLndHtm{5oho6s5M5I%eY^3H@q{F{kxOh54pK4M~R zlnr?B#BnHR^N|yO<)bF$V){w>`M60K?@5FB_(>=E#K~#+q{-cxesUi^c{0v%@;*Lg zGOl;>OFnf9){!Z7__Qg(D97;WQ!b(Wm47=Gu|3tB&zRaCWnVsXD$aT8YCdb~OQxS@ z$7fF~jIubNJFO|o?tJ029Vn0SMblpM#nX%N@1}pnmrUQnmrZ}cSAAQEul}|#U-Ruz zzIKL=ubWYcub(l8Z!)FcQ5wmvkEwf$tw%Iu({p_KV z%HaA>ypXb2z^PDA*1z3v~Op-ho{3;n1 z7Lkk#$4OobZ%E#Y8cIHke~^5aq><7r>n5dL2H#$GKuWg^i*(TcWG#uZnjOe(%i0M~Vk+Q8Cg>sgZeHF%R z)ji37btk4@JwVE}rnZ!OZ3ijO_eG_=>l#S;*7ue2uRkW`UjK_!V8cVH;KsaCkxh-I zqMK7o#Wo+3zKkd!6_2Qc2mTcqlHjZ%%h1EgB}R!Oz@7nADjpC;Aa|5U1f zu%^`D;3}!%p{Y`%!}X-bhj&X&j&zWk9{E#hcC@C{{OC5R#W8QG<*|WMt78|W*2i;6 zZH^-s9$zW7J&qiE{Du^C;(^ruluqh;W`NY~>^iCYxk*ybi^HVe7q3ZuE)|pdUOFiC zyPO{P1r-=`Z^QrMVJt7}#M&|gpUUd8j;Oiw-mE|CfSL=hgL~rks5$ZcY$xuQ+cG_O zV>ehk)O74A=d2BCwzfG~D(_jcKl8TrVClVQv&PKJb_&=WFkjn2U~|EIJhy_)154xi z9oT#@KSM6C1z_n6MzDooX}zw4EdopLbrftd*caXpz`g^^=zS4v30MZ7nqW)8GW!$* zTLzZNw<*|iu&lln!B&7}N!tr-C0O>fO~F=yWlMJ-Y&DpFx(i@yz;dK-54IL8SNd9D z--G2${}|*cPzDnYMs!1uK?mG1xY+qM28MZ3io!c`DcrurIS51=|T$GD{fP zF0c|=+k))|E1k7E*dDM_*#g1#f|boy5Nsbf}iUb`h+8?k8ZE z!0P2G26h>&VV;a&KY%sJLu2|QSmQi2rdPlk<*fzw6Ij!{UxHl)Ym%4z>Ka({yyRCu zgEh<70qi^4|X{!3uL zfwe0z8SD;NhXP-N-34o3;2_vNuucWmf!zn|Sg;Y;1F$Xy%Yi)v>s)X=*zaK73ib#4 z1FUNyPq0T|Jqo@B`xC5tp@Cq3f%PiX7VI%t&q9mAo`Cf!G!E=3SnopT!JdKjE3^~r zIauGq+rVCc4Jf<>>?K(L!oPt14K}dw39wgSUlk>Pc?~wGDEZ4jU|$zq1oki3kfLM3 z{sS9alzj3H*s!AHlW)O>7VFJY`7p3=iZx^DeK^?gVi&QRT7Hm}M zOkj3kBTGL9vj+<)eHBaxHoA;ISSqm4GM-=#U}MS*2GfI$E7Km#5o~OkrC>7HgfbJs zoWRDHISJ+rHmOVmSZc6|WnX}~fK4fT6U-HCa)sJpZeY_Y6bEw$n_2R0YfzY)<7mV18ipE0+LE z12(Tpb+EKx3#$|XO9!@~3dY&z3$VpiFwQ>d!4_3{29^PANtNqh8Nt2_z#REx0$Ub< zIr7O2wlsjwB@5V!06LefV9NuJfn@_*6|e~`JJ`y=)L=Ql)&#r)L+r5CfygC3Il;aU zL@x2k1-3SD6t+Tk z0k*4dYOs=EJL@$CD+RWv9`e0UX|UZ59Kgze?W_M3tSs2x2JOJgfgNa21FSsQ{w4un z6~GQPDF9Xx>|m3*V3oj*G#Ld}8SHQ?y0$7{$6C>~1%MrGjkU}t5bQ*2tYtn`!H&1l zgH;1N)%qD&b+D6d`h(Q~JJY5WSWU3gZDk$_DjD8V6DM!4wwYi2JF`X1HsyY-5Q8> z!KWSAZv(L|_ymF79&`n)J=onr2f#Xj-3fLF>j-v##D8F&!0rWygLMXb7`zay3)q9; zpTW9<{SkZwtQ*+xBh!O*2m5oRBUlfxMkIaLlml2luxFzxgY^e{IVvC60I(OM$WOlldo_yubRgK@qxOS+4ffBdwP1t5 zUXMmD_8AQJ-zel_pCMrXjxGr{6zuKjtYE{y-i)5ZWS`-(Kj))|GJl_MSYyscp9C8L zW;1#NSTL9rk{fI!m|ch)*eEdDkXB%$!E_-Nz(T<6L$-pA0dokM2NnvJD&zs!STM(s z(_rJk^kd3`jR$iYlNoFRm^`Kr*hH|@V;X`@0&^a75o|J;>zJ)zQ@~t8?ZKvkxsQ1O zHVw=zv?JJbFwf9xVBdmygwnOm05gWtwao-GggybA1?C-k8EiI~*Vs&8bHIGZrUIJ_ z<}-E}*gUW_W7~qw2lE^I3)lj%bYl;JEd)zDE-%<3u=L|Rz!rmjF)tt3cVHRkd4eqg z%P_A!*ix{}^8&$^fn}N(4z?UD>%7@uE5NeMH-fDM%RcWPuvK8$=2rt-4dy>TFW4He z9P{Ubtp&?9e;C;JU^y4Q1zQJ}XW_44>%np_8UVHdEZ?H0U>m{mE?Nr~23BCvWUx(O z`4?RW+YDA{(SERSu!4(Uf<=H8S$q|23s~VLCBe3W6h}ft>&g zToDX*60G`)4q&Iis;zhhb{eeail4#GfYn&}80;)q?Uk3n&Vkih)eY=CSlv~%!7hN+ zS+xu7B3S)Zi@`2|)muFi>@rxx)q}u(0Bf-NEZC1=jaP35y8_l|O)s#Yz?!b94|Wx- z$p#viYhcYc(75~z)@&o$yAIZJBiXwF)?(usu$y45H*Ny^1*}zAL9kn3ZNt34eg$h2 z))nkFSWs9ku;0Mih5ZY52dqQbO|ZLQ?Kcepy9d^3Q){sMU>!G+pFRNVvWfikAz0_l z1;Bm>>$cel_6Jzk&0WAAf%Vv26YNj0?&0Kre}VN1C;xj4)-!xP*b}fm;nTpLg7uDQ z2=)xDUqo@R=U{y!CV{;G8xYY4>?K(LElyy6gAI&$4E74_t1T75UV{zVk{#?Hu&=iq z0Q(ng$d(mg|A7tOng;9**s!e}>@C>Pt%I2C%fPVHhKrH*Ebbd=nh=3uLIba9p}LGVB>a#gE@kY z-MJl12Ai;R0hklm_+5j+oWUmTY6X@WY~rpvU@l-&b{z+E1)IEk6qp;>wB4P++`*>q z!MON(fPK3gIkV8y_;9-9sJCD@K*L%@oI zZ9n!DtOVGuV?ThE1lxJMI#?;NJ;(Ebl?K~=968&!4A{Qo$l1PS!Ssuad|A|gu6~GRis18;U?BGc~SS7F{Cmw-S20MJR99R{wV<)qK1%MqrISVWh?8M2z zU{%46pUMhW4eZn@N3iN(Cr>p4s{wZAR2i_EV5d(_2df2k?$lRcwZYDwLO%7a19ssQ z@~LlKu=A&Jf8bjW?9yr6ANbY>yLg&>yaCt`r^&|~f?Yn1_1Cu%*p<^*e|;N+{dk6a ztqIuGGvsSc!G1b}dl27dU_YP1J&12}uxn@DfVBX-apo3SOR(!_n}D?f`{isYu-0HV z&z=Tr1NQ6LFtD~@x6Wbh@ofk8+gYqVzCmEO&lLr04|eyQA6N&lJLlGebp*SAZW>r8 zuzTljgLMXbc%%p`)diJ6amu z(GklXO;vX^!$L<}EqAmvx}zU0cQjqy(M$^+owMB0IdezO0hT+Oq3Vdw)$YhSr@13} zgu?4+jM%N^B=?x=_5j^?O4`p!Z}oh*0MDY~QKmOGlK z?r4dHjs{xpXkc_li!FDwK;6+Y3muKM+|k(Rjy7BFXpy?3RTes0W4WU>(H*@bj=ocO zwAw;PyDfLL+uV^`bGH^zDX1iq@PEb}a`>Ba>QYrdtd^-CLu8}q4CG+Sq}-HA9VGJU z$SmsC(W2$$YRk0~X8DDiIX|nRdt+qTVVU`^&T3)NR9GU6kjI$|s zD91T6Z@9Z!w7gDjIWo1!+p?cU%Nx{|BXfDYEvL6=IZSOiGI___a%qc}H>)kLNZ1Sp zShO6Ww!AW7mg`%zyj5*EGO5HF4GS^o-om2g?P|-BStQ<;J6N>5Q*C)o!bYQ~Ma#R@ zme(fC@(_!b_o^+gPnhM=7A@~rTi%c`%abfxKB%_5F=3WxS+smuZ8P3oGntm1Qm`%<>(Jmd~m!J0;BWbBmVG zt1YKakY&$si{pGzZMkm3Ebp;s`Lfz_y#!e{G_yDwKdLSFN|@y!iDMujLf3t*J{fNyZbUaShW1F+H%6~zKm`bEx%D)-jtvjG#V{g_G4YbW6`pQ+OkW+ z&iN~gmJMplt_ibj@pZSKm)f#h!Yq%lc+Ng*%kBxYyvU+uKec7ggjrr?(Q;a~WkbR& zTfEEl`$BEmm@vybEWMZOmqBgWD?ygMn59=hewoykGbGHiqeaVE)Rr?Q%(ACN%h}YH zGbPNjk44Kl)Rr?R%<>l&E$38Q&XO?8)h+r)ZnfnC3A5bD;yLG4TP~O&%ifkpBfr{m zn}k`;Z1J26sx7xoh-JNBA-}?mn?C+_#|OUjA+|2ZcE8fhbnk`Fz5OZyh2cBe&di0m zG6&|)JhA1#yij_h^hN21GA+t?{Xb=47c@E_9FwWnPr|Q5Ha1 z2qjK|6-8MLWpR`xP?kbj8f96Owd#+HP#3Q9-p*W*9OK1}utz*lRou?PHb#`$B1ODvVc0f(aw#~n^MoOC#i z|Bgqo*KwH~DvvX_Lk-8uGvzt*+-Np8@>qF;M!U@#?T%}-JFU^~sz$pTaoagpi`&k* zmPWfa8tvL^wCk;ySWXkUHmp1;@=z9-$g+ zvId)}!8FzYk7XL|)@ZOW4YpN-9nfH>)Xd?4$ECPA!sB+_`x}q@8tm`5%u^TFo~NwA zTs2r0&#dNLjGE~l%F|yxM-B%(^JugypwX^~M!Vt~?aFGjtEkZ~C~n^H+#1)fJa=jw zyI-T-VU2btHOA$v#`#^;IQB=4cGoo8-PCAzTch1Qjds7Q+wsSqZ{o&`!B&Im)y(05 zp=DejGIZ2n-QteDLE|3Opm7gs7#w%(4a3#ffpZzH(Z@KAV<%}GJ1_3M85V2UTdu*@ zXs`_$EL?pqIOiQ2?e=Q4JEXzl+#|!@8I5)qHP{smc3sWnnTA^$V|7>E4*mYF!5*s_ z>^;}8r*RKr(6|RN+QhYI)Wx-Dlr`G9XteWGw{tjP^ieZ;rZKI?u^BbmWz}exQ{4`I zBQAl;Hy|IY#OJkAf*EV=9YpkSkT%hVWYFAU;4y>M#bqWJDa*4f9yR_eUAe+OoN4}*CMo=pk#g}*gd@a^BV8$%)z@ho8{y3 zY5A&r!?~JsE$24Q?VWo&_je9<4sl-UywZ7#^A6|Z&ZqHi!T^^+F2h`cT|!*O;kEv1 zmkllvE<0TgxEymi<8sgCg{zILyK6?*0EUMX1gtLTjI9T?R&Q{ zw=Hga+zz>&ay#$#qubAJcijGPd+qkd-Ok;?-Pzs4-N!whdnWf1?&aJoxmR znR{#ZAotGh-QD}R4{#suKGHqZeS-T`_ZjYU-4}WUcvSaj@6p+#r$=9pK_0;#p&pYx zW_m2}Smv?DBg|u~#{rL19+y0Bd))W<+f(N$d%AjN@$|vdjo<<*I zT4P3IR%1?MK4T$duS&*1V@+c{VW_OsS!yKNgI+7k{%Gp zA9Z$|zI?yoLew22R4xoc(GTaPyJ z$tibjPBnbe$z257cqQB$z6NXW$w}Z+db0BJKDR^Ctg7$I{HW7g@3E>Bj5(dJl^2_%z=&A~8v;7MBUG?zB#k<2Gq;IxoCEruz%0&Om( z&E;fy71h>IZ5`DpYMnOWdYukayCcMo(P0(kO5EurZJwqk=csmpYL}_@Bh{|bN!}v) zjpPB&g`Q*Oa#gbTiZ=1^DR)kVP3JTuSY6g-Pw6`TmE0WeEZAjXZv?B>3X;0FDq$5cu zlFlSuNV<}ABk4}kgQO=(FOuFQeMtI}^ds@NpUrrGstq9diewvY zWH`w;BqJdBZDfe)0&fxfg(R3{B*`d}(GbTT_KO$~q0KQQ6G%cy#*&O98Ba2iWD?0_ zk|`upNv4tD5A8DkEy)a$nIyAFW|PbznM*Q{WIo9Pl7%FTNEVZPN3w)uDakUDUe zR+6kDSxvHrWG%_}B>$}mvWsLl$sUru zB>PDAlN=y9NOFkeFv$^;qa?>jj+2}qIZ1Mgv;B00JJt3BQ@@T>n@OFAQf(H=0@@r&wXszDhHAq}CXob_Tq2o42GUcL3nW)b z&XWwHz2hLO{73SJI{#E!(CL`RZ}#DPRl;z%NsIFUG$q$Y78aV2phaVPO0@gy;j7)iWHyh(gWd`bLB z(vS=x8BCIvBpt~YBqkYpsuMv{pnGf5VbtR&e71S zkQ5{-L{gZf2uV?rVkBRZ6elS`Qj(+;NokTYBxOm;k(4K?KvI#U5=mu}DkK3Ufh1K) zs*zMDsX7EZF2WCzJ^l6@ox zNsf>lCpkrO79!Q5+69u!Bv(kTk=!7;Me-ZTJ(7ncrfaKDwZ|kcNM4crOY#NYasHAjwRUjRe1J!)$Xyq^4BMM^cca7)dFTvLqEqDwELA z+0sDR)`Cbas8*Mx0ZC($W+W|1+K>d1bR_9Q(j6kTrdltOz9a)kz9tz$GMt2F(3WP< zmS)hFW>9KJHJV0SnnqiiL0g(ZTbe;znn7EdL0g(ZTbe;znn5W&Ne9|oPqLY03(0np zT_k%+4v-usIYx34B6X(P8Ip@6S4e2`Y-#drY4U7o@@#4HY-#drO_SG+YBYJa&q!X9 zye9b%V#i2qNbE@*Nt_{4PpY|+c#s%Ld`M{W>@tyLC!r~`D?m~hBK4sfO_^N@lF}qJ zWp*@Wb~I&nG-Y-)Wp*@Mb~Ia3f2z@x+0m5Q(UjTIl-bdg+0m5Q(RJ9F&Z-~PzJf>t zsWymYD9JY@BS}I?#*$1RnM^W`WClbUOtsl0^GFtwd`Gg3WF^TOl652-Nob;^VN|2p zvZL9uquH{f*|MYAvZL9uquH{f*|MXFvO5ovMo{e%$&VygNv@OpLUNnrF3AIuKS=(9 zNLffs*YT9t3zAnP|B}3g*h?gKB&kSf^6X8MM=okllV?wpXHS!7Pm^b#hU5#9j3m^D zJx!y1PKZSQY@dfDKS?2yq9nyhN|BT$p$WC83ALvQl_&!2X;$rNR_$q4?P*r+o07C3 zX-(1&B2lDB6e-eNk_9A-NtTlMldK?FOR}ECH1;&?5)HdV!!FUVOEl~f4ZB26DACwU zH1-mWy<{4D8g_|>U7}%^XxJqhc8P{vDnLSGFVWabH1?8d>}kX$8gYq6T%r+|XvA%3 z#3dRM8ya>SJ&6;E3yC|4fyA4{k0c#Q28cw1Xp@;F8wp*i4V}16K9a&D#Yjq!lqR8Z zmda2qfTS8pZ4w$?8ya1kRwQjnC`fF&k@SSv54In|SbMBi_IvR%O;=7=p6e>w5wXV8uT-TFoeRO@fZUEK3(T(7`QB+H#OUrbb@bXZXjbw~2lKbufQ(`T2ExE1@YW9EGKW6rC?B6o`hxBUkHAw`$c-%>~ zGgP~1e~IY=bb(w~osKwUf0*fPb#_eWNJhWZ73aEAWHcwe(%eLg@MgNUp7y;M{v?wF M^Q+1jCWW#80SD`%`2YX_ literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class b/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class new file mode 100644 index 0000000000000000000000000000000000000000..91dce2fdf4dcd0c928622e55285954d5bfcdcc39 GIT binary patch literal 7501 zcma)B3wT^b75-;8WxLzkCQaJ3wzl-KZPT4X0+TX*UfK0mb!@EUv%Z@^ zT%fsDds#W-_>MqR)Jy`$2&@d@Th1%`Ud9VH75a;w?`|&!ULjvjk1lTVopL#W@dC47 z8kayypv3?dm>MFBPG-Ne&rNSE6#R4o69pP0q68WR#woc0*V~m3h-;>bVr!fVP3KC5 zeroM3?Dn!jUjkD(UZd*-k{qAB-CxMM6n2Lm$VNK_tc<_kE*x-6B~QvH1iqSvy_H;! z9(8;9j9?Ks`IN!ln^7PwT_={b7YAD=06?3UMQl2vaV*Duq#maLnxrNIM^?`7?hbFQ5ou~Bl*vHLl?QlYp%ko=Tt|0;p!ckGfd+F5L< zURP~2#0Q=0sarKy5=cprlg*Z-?U9+2Yk`_0QmN|ZvsKlR0wojtY&o#A6~~v(*OX|p zrbJDv9282fopl1oX0ciJUe0^2P|CP=pW_GNd=>ipy+Gtwa}bfZ-&Gl=Y!3(fWm!y-D8%>=$QBdyd6>{(Stl{-C5X-EwW?pv#?d0 zxJBTYbza^J)-&+7jaguwi+52WU8n>u_tmjsc(0S~61aoAa@+RJz1>^V0&}a8sg6FE z?FaFpBtC#U*-B4P@-mD9$JNYe9iSmI($+`t(G+ccOkiePwdv8S?2m=p@bMHH@Ck0i zutQz>Vnt@dPjNX^p}JBzc~25|;}G{&RT$<-m0p$3y-7^M0Mn^cEcyp64B^xiYd#}; zRE2G3{OhciqRv$XN==%$FU5urGq8l7%JvfYJoATPk0(Xw0CxyrGUAhq3-s*eBqMM~--)CN^4nbJ0T>D`XKfsUJ=@2v$ z1Bm;vJWLoQ3i?D6KfzBK-a^M^?3O7tNZ{uwJSm4L9hsn!SUl1WjSbQBR8 zQq=#efY{AVShJgW`gKcr$M48_rBdK`sAC-wf5USrwBmVzj*)>dE045494d$Kj}*J~ z&zdDFB?t{~AZM$2Y?u;A z_IUg9PEaZFoY}BR9Y-6P2Hn#t{d?WgPG_%AL34M3r}7hwYqppE2-nU%VOge9#jiuFTYQ#($Stmh3A&7JnB>2Bd-Wud7sU7<#Ppw09At( z47Clshb%&~%;w~pWu8`)xmZzVVnvyU6=lX%l=)WCdBc>sR+X7)6=j}Plv!3$=2%6U zMipfeRg@`IQD#2gcM{}dSVljX|3;OW@{}GEo}x^5iZalGJ1Upf1ixIrg2+l;oQ;gt6Mz9+NPc?$ukTcA4UliPG1h*Sk*x6C=G$VM45$s37 z(~aPz=;y|b?&o3@JYy_)IGp9VuRDxJN>L*-U((2Olnnz|i5i(T)(AaVX#}4e10(5WY8nKCL%)6wj_F@F{rw5Po(TPjW1OF^FG<&^h-gbPgVc&iPtr>W+$HtE zm(>$oUQcjEJ;9ar1Xr~m5@OVz5izxAuC6Dzrk>!sdV=e%rH-+@zn#GJs$W8o}J#6doLU5iHCg(f_N$#{bI z&F9e~8Zkw*@mHh`Xcap!O?a3tF2)RT2WE-~F-ts+*|8Mn#Fk-h>~zeF?Z^DsrAWta z!NS-BSQL94i(}8CJ z#YBD^__hTxiCl~p8c81&f|pdrQNj1`Udi)k0HzXk^Avo4y-BbYzK`(?BKW3E0grEj z!^a|XwBWliKRlK3*-(CXN)mjJrV0<3e5sN~nb!nggZW`@6@1F&hgU5=5XlcOnu1Rb yfAwUQTgb)IJ@6DU7H#)EH{P_pgyqSIfH~)F_W_E9P zcJ}FS@3~)5l&R_0s!B$4XLmmQi)`%fj5M`&HRy_}DnsiwHFd_Ci}Il)*3lYm&aa9! zM(cJ|x7Bwy$8<$gl^jE5X>3b(Q%9_{b4P34(pYD#OIOlVMQ?7}m=FJSMOT$9dj*p_ z>!Qt3RT);rh5U|KLvyUIE58PdYnmEcqg~w{u@Y5D+qk1E)~RN`9Z*9pG1WI|wYsHz zN$xN;%~v~TOYU&B+?Sn}o1ytnQ`JCaba+}=Tj|fu$t_p4>{4}P?y+jAHY&5g2jvk_ zKA;@RkK^S_vY@=tUVgk)-exbKZIy4cm!DvjpJtVp<*H_RnywNbsJATFXO;J{mupt} z0DHOLDjzP&p!HE+?NfNxqLr?holiC?YGRdZKOZ_f>F2`u#c zHk>#sQ*Ei$edXgbb6Zxb`i{z-+jy7#b)X%)T}O{*-(jjEf{ zax#}M8dB79;>gO(E$VEX2s1Ow)No^O*4VnLxV^If#F4pCEmJRGO}XVhU&heBrKL+| zwAX@ufoAIWnpe1XTl0`(8)6Hp=1m#|6JmaJET2G&LIu8I#am~GC(c+@Thds)A~UnV zA4=0oLOI9yeZCRnGBYzP)L_l5A@e2=D{9Ej42?S`8q@|XsbASPuyAW*c;cpNv{xhS zWrvn%YiDtLZL4O~Z6369`lRY9^|h0sedTGs$y@sN${eZs!f9Ku12oeImOKrLZNYf^h+D~CAZI}w0=1it!oRL zGe?D*{3AB1VJ(!Cr|K<@D|Sw=uAb64yLWvt)>kI#o0^tWChFThad6?*>Rp2eG-AEr zrzIisQ^7p7uNi2^_g%SYHP%0PUh80JU-m}wS7RvGY#+4WVJB?b$>4Sd&1yJt*WfWm zJ(=m|@$~ZEc>@=&FWLb8g6*E*YIoh{h0WWr-O#?u0JX1nbg6ISmeJ7PxdSspY2BGy zs?yT5^6-u_RfqDO(|fHcXj=yX-Ur&kKIrS?au6N z#fQ=ESbw&C;t*)>8qwZJIMavyS+;gw+p6OJX=xSy^0LxdT4%UvEX2pwaXFb=7ESeq zmgf!Zy%zXv3y+&$s;w+9teV#=P4f*)JGHN`th7{{ooU$_SQ5%k>sPV3pft^wc3j_F zt+;FRE^S8d^;0^ry&=)wacThjvwyEaMV+&!W4rS(&UcK1IL{i^w={RfsJ15Tzii>x zrD{61V`5HGEVe5<2!5>=ex0k08`s!-^^}d3S$(N}C3V!F1JZLx4w@009mtzky^hx( zN~iiOb4vp)l?(H>v(+UVYj+)k{Zu3DrD>C*^IC?MY^Yqp=D|3G_KccK?HQFB)rw<{ zOLxwl1pc1AU{2=9+=-{A`A3CvqsRDis`IulTvxQAGLSd0W#BBpRhYQaw4#Q2yN;PZ zdHs~e$bum&TLwjl;l%0w`T3D48`m`;-|40whleK4fc7_(XMvw{N;b}(j>n75 z2N~Y*+0KD zWVQ?E;faH0Y^d{vm-vPhbv5nE9+0uVsA1i%%>zpPJZ?r$8eY->xD~xC)!wyPL*~Og zdva6%iH)rTXZeN}Kc%j7>BN=QYo~OUriIFSub$OCJ6ttCe|1sY?EZ7+!#MSg za_Ti~S<3BYIqa<}+5zB{hOc0=d0H8r9<@ARmZl+U>q2@sDDQL?Dadx^jSTn^~43o z!aOp|mpgOkw&wLSIxBZ=hVeJGf%`2D^s(KhjzNl*Us3mWHc*)_}fsPl?U_6tfm^6PoaHHHNJ4Jt2{7y4U`9RAYN#G zuNpe-q$b`!(@rW)%fxaVFA#rNj(#t0*Q#Ou=Hm+5w`N*5@Y}}L&dAj&UF8tBQ0^O3 zkhhJ;H=I}C!VdTWpCOqz&K%{?KfnjBBj7xX;~3_D;ji)mFrLwm_Hu};@&V*WJ`ceB zi+%)ujjRGc2Eo5n&iw^EhMV<)J?sZxcni!U8!8&|RzW`tKdG6ndQdNF>5+dXm%8k) znFetm*Zu)2_79(5rgVya%O(F!-CjxKqcb|%5A}mzmmogAycDj#pdT9BvhoJ>T3@gs zR#v6MID~%7m6wZtrgkCUY`h+8iBLcD{)G5}d2iw-tk>SpR{6A(Z2cU-euMK0&QG~o zg@Y$vr$T)3{%L3#R>bEA_`%W0;~D1f%3Vd<`V7MJ2lU^tsTiL;4y)Ja&Ew}E&I9AE zsnp(1IPY-3n|e4tN_D$EjF&#pUuM0WUx9;Pt2WJf2qrANkrxVxW{J67W(y-zd zh#!h0m`8a34VpN=H;x|~N3Ej$TWbp;UcoOAx8i(b!^1oS=bLR+t4msHAxEKqCLhg&8}p>aQ{VtadYQ(aS6 zd0R_+Q*&%ldskCiYiFJ_TizV)?9`QBa2qKxPFMP7D*X&(d$ewIv@w=f*4EaX zrz=^i(#Lg3SNg*JD1KamTVC1P1-JpA!bMfdbK&zEI@($g9*edvYpZI4n`+T!T^Xb* zePu^fWrWNCRAU1Vg`0N>wwK!6VKmBAS=m(IwMkb-s7h~VnW~IBDY`Y9-yCgigd2Wa z+cwAYt7Bc8+Un;=TkD%+oq1JlZJWE>b>$eapIB8_MyX1G^i?HO+yu<)*jm@Tc~gA{ zcxkMvgv=~-jiplG&=6^8Z;XP{1XW4z*lHF)hd9(?pfVZmF>;ky9^S>IyNys0fST}l zfvNtb1K#un&qm}i!?=%gIk;F?75tqk#}&z+qIpYz^#&V6IoRm=)NJG zmlthqYt1Xrl`1$&_iPt;#Oh-Wd8Hj4ZQDvaJKO5O&O%^sKdLK>p%-l`s^V*EgTAUV zV!Nyx!wc^8;!S9N0~&}&Vy%%a5TlkB3>(nt)m-1%6~SA=pwMDhz%l1m=)ktx0I}^| z2#PBMy$rkFrY2N#7rC{X+v2pK2(_9zBb`n4u~~4Xox`&^{uiGT`I+KF{gA{ zX{5TMI#N}+umT4TjnZY^?ai^Nps>nOaBP(|!!O!+5`=L{awW%u>ENPaFchjE=3w+-4|(6U;fBi1153UX_B((k}|lE%C_^X zSXf$CRRIhorNB{A3M?h1z*ABROeLkjRZ5%P7{S>7u(20N!7wg&1%an zycdBec&d-kz#?cK_Nypaw6F?VYqYDTeBqo(75Lv$pb5=jQnRdd8O&7FbOVJmv1qyB zHY~ClZgd=$q9cq>0V<12%TMG5&e(@083ouvsNTq0RzpW#JXaMFPco1AaOK?P5Z@x6jf{wABg^ACvvMKCvuhrAm*KqQF2i}p zT~;J1!+FQ8hx3lR4Cftp8P4POGHV`>FU5I0z7*&2_)_30DFvpIQk=)*E#N#JUyAd% zy%gt8oX6c|ZhxYl+n-qG_9vFP{fT96e`1;2pICbi7Z!bK5^ zcT8~t1s01d%Oi#5wdGZi>4llHQecahc5q$B^V}Lg1XFQj<)Wo?VAkL`V`y+anjW~` zvPH{Et8n6mo2r4?|&w+u$SxJ(KmZ83(@g-ospiyV1kS!H#_(nwXsJg{E@ zr=g6cDcZO;Q#-?4Tj@nbIof2fV1pNJjZtzAtmvHY5@j_x{G zl^1O;k2W{g!0k(2g;_YXv8}DEv#TT8t|}MV86>!gX#X(@W}8|Y?IjN2vK{TQ#0Ty4 z1=Ju|!qjSYVOXtF7xf9K;MKHfdwcT^xHSunK2+-fyi~2pQWO=U!r#!;TF=xK>O8at z0W;VI$90QKyIYrmr}A_a&W?KZqB+Z}D)L|*rMoJ-F4VF{T^mwYtLxy5=DY#NcKzx}uYJ*cw~6Qb#j2s%}JTb#Uske!J5hay16s)EMico>!F}=ZD40TPn+jl_|THUNRhrttYPeX${RH`!1 zZipIcYx&_=Zd2RQJ6m8RfiE|;)t5)>HpL+PN4h&FF3Mq~=!60FK|R-xleo+C03B!* zIr-}9cG) zAS<*%ir0oyTzXeCzi*58nu6*Nop3lV;2_1r;cRHH46;HSq!^!GHbtAeg6gkbhCt6S1fs+cM2e$k$Qu9;#GhOVwFgd5!8oX!6W_fMJ&vj&Zva4)05D37s%?=KR3CI% z0!71;G_nd^k%f5yKrz1RLI@Re9lpKMPdaNxJ;RVRx(Z#plRw0H7 z4kT>u)@XB6eWWA0Em9v;|LUsR3N4O_3#~#|Xkp%{S{hn~5GEn4wtX`^>I$kKxGJ;) z3N_>1RpbgN%!>+9lmH+)%nCb#>OY(n7FltGq6F`XqarJgP?P{5F2dMCdIlC$|KqCB z3ZWut2o~ftC`tej7gifPg1(@u zMk{WLFxKMYrpOgHm^a!ejhiBf2CI!wV}`3nD{xRXzQ(B#9rj5O^P)x+B>)HqW_tt* zbq;iyuwrMbGotq*pk?!`OZ>+0ED|)6%qi3osdN6OaQW`x|AtZFF5uEDo7b|p7Pr}y~I#aFC zK~VyLc%YMaTT2T(wuCy}CamC@Dh-}#E|QoRO++!i&S?-2I-dl#HwAqsI6aC74YV|F zra^FMQAFZ>4BLen9x#y70Gb9d;Q(0Sf`=qTUEwm#3KtY50EmJ9*fLmcv9YoBWgN?4KB8^w?5X=-nApb>u-0Nv*HbblGeE5ZMqe2C`tg+g34A` zC01BXmxk5!=|N?i3u8srbZKNwFAgf(T^K8rrb|O<`i!8m!-cV;X}UC;rbAS)`ns-W zbSVEt>ieO~gcU-l9Pg51R|sKV^dX88KtWJxa8^=m1qzB1Okq%IbYZMmDVD}caZyll zjfY|@AW)Rl1HGQk*EZF6N1Ndq)b|TltyY8-OCzKhV!$5Km^a)Z4Ub|709%!ClD*z# z!3q}Cm5_#Ta8zkUO0hIjiXj$kRl>A&tIL8FH>fMA5<tQeRfje!}i7{I(ygER(aK)*U_u(})%NhrCxe1_HKD8>V3LZ{km zz`US@q67dv>Ht`sJyY7*God>j0IR3*kfa7zPtUY^8bt}f)zdSro<>muaP{;|tEW+v z09-vi)9PsyB>-1X&$N0PMG3&w(=)A}Mo|KA_4G`ur%~)1_xq_}3iM}h+m#_Nfc*#X z&M}u|80bfdUf)vJ3-#>%>5Ti2+%Lf$nu;puog{ zEWfr*jFL4i9Cu)xH~78+ z6u9F63rvhW4hr0HfCVN-9tQ>PIKToEBaZ{To9c)iEHE%AOX2|Up*k_PIKYE4j5`kS zzN%S|JPzWzmptxapk%Cs+Z>Cnv7AD1VA`45_mS#ZFjO{nL4Uz30Gpzna6hHzKo_CpYlk%q zz3d>U%0s|&IMaTlor@Kp2an_JHsFb7b3Kg1xUxK^T}Y6NM78|M0+H>F>Si8PFCo>R zh-Niz>JZJE=o-I=7%u^|-vptqfeBHsVGNo(&GM|%kTYkE5z+XcYgb_7;Ws|KzYyCB zFG<1bk*2O4u-2h&Geix44F;0s}Kg| z@rO`3*7OmdIh{HFJ_@e-q{W#*F7kC9D*6s?$Y+4_xExSGm^#?}2Wr=cxKu$#g4n8WE5 z-Vw1^0<9{yT4kE#A=E>Td(u@M(;m_u#`Zn}HPp4WHZ(QD;xJeM6lvV1Dx0l#l;eHu z64SD^N1RnA=_ylRa?Hg9MiE>Sz~7Ee2(&DC!4A%=ogH;>)v+alFBCyxORTAJTU}R2 zbELhknU4v6>Ng7Md;-7bv7i~^Aj8!na9WqdY5(tSW7>1tZ_&%ogO^R8P_=NPG)rt= z<%23#R|hXq*1-ZG@Jl@obBJuK5Q6Y!8n1sa)!~sfSD$ZnU80zf9CMuoRONd|$domv zCAFG9kQ~GD?!z$Rb+B+F!Icu=D=P2chNu z2;PmydDZMCD1knCoBHG(Q=Q0hb&oRxXB;;`L|vviXzt<80W!l(`#}2;8~8WQ*qX`V zDvB>iHQw@-__5OAES%X-Oc*UL{e&Tb-40E5@PQ`7!bI_6pf&Y)V8*mhwSQnMKZ9!? zw^eurI@;abl?Okxw6Wu0+3cVmHGl!L7>uiA+85ft(e9T#81bDscs~^hsml7Ee39IY z1I}}F1zxSgo78Y^pJu!WL@)FS0zkFVqUyw&xg$e`Y2Rqyq8Gk{Cvi>^hHv3F;lLh_ zVq!=OTIC%wy3V5-=>c6G#4Q63&y9CbsgZzWjm4JT;Q@*F18B%=yVN5wo z`2k8J;K!r!@-Zy#1OnD;!p3{YOgUTmAu2=l{S4*2=970|ySlq#xMUv2`3mMA?H>~c zy|LUVTz|mM7H*?dnpeVfx6pIIs9q_NOjW7()c6O-c8mK^yXyLM(=aS9R1GxOUTet2xD%j2`u636IKTS z2Yfx6DVHigMN=#AMwHl%#7Sxu*{bEy!(m{|8In|r)-F?ihSuN>0SHM^>@*i4bMSbW z_B(+SiNqX#$D1jaD?dkb^@cetcA9G-b9lFfR|rF2Vh&1?-4)6&&>UQV6FV$+nrk6* zaPec~T@Z*7-h^Ahl&ffF+R2owN!rDfYe+hs zDc6$pJ*Heo()XEiJxM=c$_*s_kSV_+=|@btk)-pO@@tYVV9HG-UBr}|N%}EUZXxL> zOu3b$pEBh(l77aN-;nfkrrb`_FPL%%Nxx*uog`h&l-(p<%aprFx}GU}Nct61_LB5# zrtBl>W~S^X=~kv3An7+uxtpXrm~szEyP0w?Nqd-bA4&U|a*(70Ou3(=dzkV7N%t}3 zL6Yug%0nbQ$drdkdYCDXkn|{19wq5q^Ftk1WC^_j;oza{BUOnIK9KQrZbB>jacFOc+Cru?3yx0v!GN$)V_ zC6eA_%F85uz?46b^f#uwLej@f`6EexXUeN2{evlgBI%z@d5xscneu0n{>_xvN%{{{ z{zB4!neqln|6|HuN&1#4Z*nP3Vai)1`Iz!HNq(lhLsEb#?~)W`%6lY*neskKj42d%xVfJf?h3(rBi9LDE>J{F|ilO!<jr1(@6R?Q>T-3GgFI6x|OLjNcs&^XOeUWQ)iL1o2exv?P2P%B<*AB zaU>mJ>hUDq!_?U%-N)1uNV*?3+$ZTlrk0WPFjLD(dX%YiNP3*96(l_=&Y}E0L+dQc zcV?koTj-3%PqaNLRV^Z=(RkXEDOp>wkm9Hw6s@gaNbi^gdiX*vX$|i|%hHgthnIWB z#x!Imp;E#oq9u0|`BjPA7occvLPM1%RI?f|LDodD=H9X@B4q$9h0GIVg$6w;D*lC`}SDNUAySr5Bz5kS@qv4K<}-;9gYWSuY6 z%sskDQ`V<;P2=s6v3Apm1 z$+yxXRoRuIV8B&rsCaOKd(6uMP8h~f&mEPZ)9oXEoFtfpDNkcw=u%URewPKiP~^Lu z9n$A~ZotjYNK-aog+0{7J<&)}HhzR6ZVz_Idd(fw4r$K1s!iZQ+kR_@tQz)8qHWkn zGePvCrZaRB^ff9Q5td*$ioM*ZZn++w$DHRoc{dw+Mli_zV`w=WBAeg&?pM|sRNlp4 z&K}i0Dv4m=BSaomV2LY^U2vf@%YNtoN-kr`WJ)?Oy7$iWuA1QD)4p3A-Ze;Y@#$7gaPjF@O>pt)R!wm6=~hi}@#$7g z@Z-s@ddMG7@yZE)JjE*~`0*64Ec`2-ylk;RoD=+binpBL$5Xs=f*()u$_aiv*_HA4 zK!P7nZdH%*i&j0xFRFTsUsUxNzo_aleo@t9{Gw_CzsBvcNb|xl$+ZY#>v&vpeXI|ZP&*aVVH%Faz( z$=Vx|6lK$H+?J7~D)XMTlO*ZLt|S~AOp==HUZ1h=WMV_+c9e-Z*-wW(Rc4*)dSY$u zVafYbHZ4iEx+G?@&UfyBNqVv~vAHoOsmOZVwqIt?p0Kvj?3t5ucTLih{YY|ex=EU{ zAt(0YOsoJ`N2DN&Dr@J?p82>p^h|7RF5l;qbYvqO=$PAodeSQMq$Pe!9im3@?Bftx zb3N6#*prsH*Kvp%#gC#aSQ%ri&=MbcVM>j%43>5TU}*=ww_+Z~SDcu#Tv>q!VNr+u zAYY)#l$FXVJh+`HwIrR)l+`5dWXc+nb}?lwNvAVq9ZBC~%6gK%&y)yBKVZrRs_chM ziBj2*n6i8DKDMAFZg(nQkFnQ{_IzhKH{ zl77jQX0m)WQ(8#6mMN_yUC)#@l77XMc9MS0lr1FP%#;q2Ze>a*NxxxA7fE+8rJJPP zOxa4(9;R#~X&+OzlXQS7J4m{RDJPS3A5%^t>3*i{BoJyP@X38#-9%agDBt0%x z@7UgH!_78g9ng!XD`#LwJ%y`otS;uO{z{mCpg#vz%>|x?CHan{b?|)<0M`Vz;9*$o z9yqqCwW;fP=aShKEbv0$_hDs0;6+%ZWo@mwY!iHg2;V)>122b_ae)`Z$~^ot5&x9p zpE>v^AO95MpK18#c>FU1|CFG;e*7Cp4c)DI)>bsQ+z&U*Ghf}KX6k{rfeEZZ3cM3| z7nXmT$ky04gy0KfHW0jy&;Tz6n(@v<8kXMX(aV8q6NFEo3mg6sglJ$JN}s@TR(kVA zd}m1ye2T9CILdJM*uZC@z&`^2RF%=jaDwV$9j(#k{LZ#+*v7G`wV^G)hKp5At>B{1 zgGvb30ot}J6}!Mz;-VyQ@t5Ji7lHr4!oj8%`VJdznmgJK5E}*Cw{sOmEb!mJ*I}Ua zKTnh@ft?=s7G5$m==bpLH(gg$CD-&}4_fFE-51hT9o7Q}uvvAmntHk|)_MR+z7AKy z^fWyX23tDByFt&XsO#WLW*ozg)%A2(Hdo&k5qk|UvAsOmbI+g~tVQY0I&4c_`O7d& z@1^$+>rC%ss~V5!dM3W))fUN%;v!tz8gl1LG)Ia?w%#|aXX*W5hUG!44}cYZ*z!(V z#J<>CzngNEbQ;ie^g&qVVE3Ragk`zg^Wbl$(HGraP0jh`QTQmIJ{%?sGjPmu9xAyZ zeS|&|j@vgt7Lly$un3rKgRQNX#v0%oW>FXf$BvaK8gDYxwKX@xx02vfh50SrT{s`* zuLN{^te&GGo<{31XZ%BlMZ;4q-;_0Vb(V;MZ8K35+hXf^YQMTvA0GzB6Wr}Dg0l^u zLUdTsw3d2fidzX@Isqr)n+n_WKz2@B)8NcS7GSN@I9CZS5uDz-)OFaBdyw=;$f$MVZ6q;8gdNVGuhzG_cA^pcXTq)t#o&F*WB(IEXBTWOiSqHcR_u_E*0A}4zYQlAJ{Y}yh zaD`3MjdA)kN#Ld&XfJM(D13yItHJMeUR zXB<*Wc>Z1%g%4%8zA~Itm{w1Wg=9L0r3uO<*}UU?_qQd)8AK>W@{EX3iAfcCIfkRlL4;sZM%|4-ZWgnf-KkzUMmdthOUOk1^IkguO7^RVNGv( z@&b6T2sN|PgPFl>kOIGlH#39%pho?{uu>fy0579g!s}(W+IWOmP2*V>%n1&H!5)Ou zcyMJ?N30S^(kpgGU}5PT@#b*}3l0qq1IGv9cg_Ga_Ke|!Gd({O2XjM8c5ozIfMBO* z2cg;H?EBIf032@!vVW!=I(JBLG}bW&JYB|uEm+I~Zv~!2U(M_j2+qm~ zJgF&)qT?TksVus_s)=@wBXu|p4* zLf^voFKlJ-Vu$?}h=78^Cihp;OKbzw%Lk4QF+Yo%tj`(+%Y$>m!LnclG#Y*>;kkpF zI=8!(|Nfi;E?OF#pQWflcqJWnu5ceVU1|=txSK^DZ%M?qw}XFMVy#_p$EhsZ8KX{u z(?hS|iDBrYD!3;|eY6nomp#wa)A(EyT*B1vlT;JdU)TT6)UzoIXXk8VlO@~NW%MAt z+j1VMtcKfTdGJ|!^Fp5m*Ww)cdT6#N$O_meI#vT>H{S0VCthJox;>7 zNII3N&ysW+Q=cd445q$B(wR(sg`~5X`e%~PX6hRxox{|3NII9P?~`;s1iV3y-{e>U zL0_*2FJ$V+q;WA*KPBlBrhZP+rA+;jq|2E4KawtI>UShv!F+y_u4F!)q^p>Zk#r67 z^&#mx=Icw+4a_%yq#K!U2uU|F-*A#{VZJ<)ZezYNB;C$@6G^(0`SMA+i}|LKw3qpc zN!rhR$C7k6^UWsdUYLK3NU?9;r3Vi(-yG6;fcYv(dWiX|NP2|%7LoKA^DQIk3Fcc# z(o@X0mZWExFGA9D%vVp+^UT*s(hJPjOwx`#;}VZPT%f_M4-_>}<`noTY`f%*PQhsv1mZIb3N-+Ls@Wxfwdn$LV6le7S4Mx?+e zWcUJZ8(+fVA@EMPGQ<8l1^pXSdva-+60o$VA^Do z&SY8vNoT=x1v)buUs+t*RJRGQkMz*laK$H1+wOyS{S!JT6#8N4NBE4UwTtdDcR)wN zb$TTWofkSEZZn52fT4$9Z)~>ig28>9(QpIKxL&Z`zG`YQ?pZIz4cSUq=%UcYVW{KB z8G)~Xr}KVmUbH^i-i6yJ!Hw*=XI-|-AM>u7acZKg_t2%GpTcEZ=(0Y6(9htC%zj}d zhh&6)jz19ND>K?+T>BK@wNL05SzsOR=!_=+N*h|)S|8gUtA`uy;P0zo=gRoIca~Rd z%H03gghE$`V0%0UU)n3{ZfdTd3)jtfNp0}4RS7%f!8KAHJdUtb!NJ#uZU}>sU#Z5o zHf<2AV%{Bk=+|(Ey9K|pS!K|)8XV7CTBH4Uyl^rL-5k0l9J(oVD}-B|tH3i=O`BtS z=r_3M1#J1((HUc*JJibb(Cwi+WwdR#Iv2Ip0rD*EFsY7P>$5Kze9T=s|ao z7a2j$LJw24J^~~j%~JfKE16zMyqvYSK9{8g5I&3Gzk{L| zvJ^cYUTnc%BKXUo`-dzgi0~5#{wfsxDN6~(!)IFX*9ra?(0wCI2_w9k;BP_E+gVCF z!Us49c!7m~kMQq<@&{Q8L;Om@e*{GzXDPiTc$@P+CHy}?`LisgH{#b2{&Oh$B1`Eb z!P~s|AHshH%Kyz$G7ujj{5MeaZI+TL!CUSNs~jKp^$CQvEF}x^=Wu*D07ZJ1k}bho z{tJf*pAO0_OX-XF^9kPviZZg4ej!*waWX%pg|pqBEVMis?njpT18hK+(jP5dMV1CZ z(cmm)09rbQEDejZWcf5af-L0%Y-E-)5G~zAmPSF*=qx1%E$!l$4&iZemMrgvCy=Fy z0GpJh3_?qHk)&Tl=e5+W$m@iOxg^2K$vB1M^fM!WfiZPY5#SOQUKd`Ur3?#4 z9FK;@7HiIFY>IRmQ91Rp-Sq8tc5e1b(e5PbNMigL&WpH=Z33O;;zLpkJv z&u}P*T<}2*<&XO z4MfTz7yQ5><&X=0t&noa1;0v2Ipl)h6{H+;!H)(~4!PhL04axD@JoM`LoWEOKFT2% z{16|{q2R-B>QN54;J5QAhg|U6ca%de_+dNBAs75g9p#V*tz-;1Lh za=}l(Q4YD_cingn1s{I0jdI8ZKf^{joE+3w}F{a>xZg490UP`0yKFltV7~0WZoS7yRfJ<&X>R;Ym5Rg^<6_z^0~As76@6wjgH!*54X4!Pi0p(ux3@Ow{`LoWF3Cdwff z{6-VykPCifiE_vVzo0}pp7G|F8FC2 z${`p0?hWOT3x3pwa>xb0SVKAFf}f+I9CE>L%}@@x;D=-=hg|S0F_Z&A;~#+0X|e-0 zkOvkb4-({ohsc8jd0-;)AVD6uh&)J;2R0%P66Ar8$b$rVU?lP&K^{1XJV=lSRwB>& z;bcsCl(YhzjzymH!wFgBIX|3|MV|A+Nm=AMKb)3Dp7X!oCoSH?R^TWwmnjcwbPwZTty{)9R1 zR|WhEPd_Prb2z;zy_p5x4}1XE4(YA<05ndO>67U27N$=lsgvo)k<`ufa+0<&eKAQp zn7*2%Q<%Pb>35TK4qQy-)yF!;W0Dv> z41vc(#r7X=;vt0bFeO$`YO-q)Sj_44AF0l`hYPzCz zo2#Sk%kXg%gcq*4UD(~SG1ehUvZ`Q_LGudOgd8>XQ&>*VQ&>#TQ&>vRQ&>pPQ&>jNQ&>dLQ&>XJQ&>RHQ&>LFQ&>FD zQ&>9BQ&>39Q&=|7Q&=?5Q&=+3Q&=$1Q&=v~Q&=p|Q&=j`Q&ezQDsGz+(wUN6!cMEWa{-YC*vi}WUu-Yn8vM0%@8ZxiWnM0&eO z?-1#oBHb<0yF|K2qqdA36VZ2(x*iFv`C*3>9ZnzPNcsT>GLA}ok(90>F-7QqDWs7>B}PhgGgTy z=^sVH8x6K%^gv^lu{l zNTeT&^b?W(U8J9i^dBPqOr-x5>Ayt!xk$ed>Ayw#rAYrH(yv7NUy*(-(*KF{8eyw2w$LM4BnmERkl5 zw693}iL}2+2Z(f_NOMFwNTh>BIz*&HMLJBR!$mqmq`4v;Dbiy^nkUjxA{{N#F(Mr+ z(s3dkFVYDjohZ^tBAqPKe34EOX@N)!MOq}%sUn>w(&-{C7U>L;&J^h^k(P+`Sdktl z(&I%sTcjt5v{a;JA}tr`9FbOF>T7^kWMIi1T(n&VQL_`yka*8$(mm>OMX8!FexJIk zdg9|s+Qd6{tLw*Ss~aZlQ|tGsC+$;Pt0#<~xKHg^Iq?nvXz4gPrz`3=N|vrx>FSR3 z%b_3uud*o0Bk4F}j{wVQ%2>5i?Sj&DWu)4zZiRCM)TYi?w*mSJkkeFkzLEi?V4ap% zQah6&^@M}esV1piiAcdSZLg%xNQP8{gVgs-QfDS2_5Gtt>MWDg4-%1rC;eVMbxty# zYIJz&M<%Ir6On?Y1xJz8`6j6g5|M&c4qi!JoQ$V7IXv}alhh@NNd4rflDgC+_0vS8 zV4a6oPhFmjr>Y-#j)#~un z!zQUm5|MiJsFHfjB=vYAQcrj%^;9yRYIAt%X_M45iAX(rR7pK&lKO2TQqOxQ^+Gb9 zYIk_*_a>die3Z#2#|W&B=v_xq+r3MS5mJgg`0N-Z`qI-Ze?Rmx$E+-bsC!jHkLCp8A_f>Z3%YK0d0X zJ~2uCJrOBbBZ@ctwZq}5|C*$} zPDJW|N0rn!CaG@|k^0UvDW95*r%twe%I7mk`LqP2@WmRBfqo=NrJ1AxiAd?*NrjT} z)F}>6g-ufFiAb@dN~)Jhs&^t%eY}&(OvY0?9iGZENo6M@)%U29>SvPbpNP}|@1$~) z@zkjfPYp6j4NgRA$WbLV)Fd@55vk$cN#!QvsnZ;u8flU`CK0K;qe^O&NosT=Qe(W6 z8kdZxPIq`}yh&<8B2p8NDyc~(smX~*<$EVpkc_9!aCoZFBvq7%)YPL&YMM!EdLmNA z-bu|&##7&OcxskOsw5GqV~;AS<4jV=Cn7c5JE_uSJawkSQ)MQp@otTJJ)lnr?ZIW7;h}0s_qAtfZo?2>>s!2p@ z*-<66+$6Ok5vi5lN!2FfsUJ8zwb~@LCK0K%N0rn%lhpb|q$1u)MU(N=*$z)_G)dJZ zB2|A>NySW34T(rKdMDMCjHiC+@YG2rsm+N3AJ znTS-^Q6<%FlG>Vx)Hd&=wkPAMa~+=AVUjvI5h>V+!{Z6rm(=>H^Bkm3HA(GCMCvr} zq)t!9Q|CKKoneytULsPkJ&9LOeLope7dS|rWs>?qB2s62Cv{FTq%L%j`jJWM+(e|# zJF2A4H%VQPh}4DNNnMnTr!I1M>SB}Bj}wuCZEC#6)K8Kjb+Logr6#GLCL(p2cTzt~ zhSZN8q%Jo}{X7vV*s{l~r>;zf)Flp5zcfi*m53DV9&{8*U1O5EHW4Y<$jB?H8|7iAcfrPF_jfmW-z^b$IGGCaK#Kk%FD3jv}c$O;WoP zk%CRHypr0JjHiC;@YG(D)V@Td_IoFFAQ@7ZIY`}YlDa1mDcJVQtEcWuhSbj-qz;;- z?oUMO0nen=50fGFa|fvhO;QgfA_ZHOdGyqgAoYkz>d{1`V3V|?Na}Hu)DwwF!M1E3 zN%=y_bl(+@?t984^>iXquoav~Qfg99+nuDIHAy{}h!pGy=aE!$p8AEuQ_q{EewT<8 z>`Uj7RC1njlKQ<#>cvE)Uh+)Jm()$OD;=JC*(CLcM5JEvPAaJrvXj&wO;WEWA_W@+ zdh9-5QV$`Wq+T;g{W%dS*sIVZspKY4C#k=fq~1tG3U*2KNGiFQ`lTbL-ZV+Qm53B< z*yxp1QZeNu^^QsE-9)5d??|ttl8PxOsrOA%A0#3L+gN%em0V0YN&U?v^-&^HAA2X2 z)M@5wM@)TUlKOihQlEMzmE39O8V9L=n4~^SL<)8e_1JyBoMf&Nu62<5mr3gLM5JI7 zQ?I0wx^!`p`nO5y%S5DLKUI&Uk~<;a?C{iACaM1>A_ZH!dL)%xOgTyY&m{FtB2uu+ ztVdGnXUW8rlhk(xDNRX03b(gCdZaXS^`e$&^&;-8>ycD)R|yVJY3AxhEz#;l+~U_O zDK(kyyTu;pTF~siP@?XG-G;rAN@_}Ql1ev8u|%X`<71Dck_&Vvsoo~3K8Z-d9?VCP zRHjKPD-kK!4%#EBIn1!CaHmmNWmuA9!dE!lNo(Z zQsz2OEzvqp+^^dsspJCPNouI+sbPscHT8Z<3mwh!kvr?U9sLmdpwH zK?kXFlhm98OopOrtF+oUlM@bT z>u|3sZzfl{O|I7>aVCLf-EE#t#<8r|V!~tvY>vgh=r(@v!~@z%a+LAml?IXbs#Co3-Zn8ipLuI=t4z3BAT>RfU-nSLbzW<@%Bp7S23P+%n2i?-64i^ zP`eW(oN9yGZm3KXaeX^)QZEe@Ge9K+4r0^x_t3O^<@Lrl?SR=Ij;0+jn|7aeP{fqg zv4|DNRpUzA7aD{^A-5&9DP!-&wAxXC|iuZs9t3tW&* znA&_mdsA+9DruSR4QsCnH-|N>0Notc{tObfH>|x5l3&EqpLpe&et=|vat5enfC9$T zTk^KOD<|QpZSQIC%LC{mxzYFlGFlciTNb3283AN#2ejd1?UT5{IAP+@1KK~mR)_-+ zr$HQ+M#SQiwc%{ApnlQkzeLz;U4=K~IM&dNA zkv_B!_58S#uFm^zsLlgl(o#^u)-q{p`*>?@h7_Fb4cu2c1pNc#4)QVt{R90u@qy_d zD!1qgOyzr$OR_!w;U2)&C7E)T#3OtBx!yc7(tnJgUk<|(2WH0jJ^oQoDEj#Q{&6TG z8QSR<9%QA*{W75@Wr!$J{p0-;BnBsu!6{&H(qS4b@E1x9P9=lIU~uYT8l2&uDKS_= z29F1WC5LHnw*Lf)!7?&f0S3zs)8JhHJc+?dGFSx$D-Y9PwSS?+;9@dZ0|pl#rom3@*xbiR!uJNyx7+g;VqhN6TVH(`%uag*zk-<%1Fm{**oBSt93^tR&HZa(H zm3Hn*m;-+xB0h=le6`kal&5z@H=4yd-(kidr+SVg!o4c{5$wmE;goC z{U`e+KS%fabG@6k?gQ|>u2tnK>9lpKr)f*MS_(eR8~7S2_zZ90Yo*{by@9Wjg3s~> zzFrDG+Z*@>Dfk?3;9p6>=XwL*CI z{(}_!kvH%wQt&6~6#S((@at0WSKh#X zk%GVW27W^d{>B^luTt=L-oS6lz-g*C@LN)_<_-L|6rAP_{Eif?djr2K1&6$W-;;vV zy@B7Cf_r%be;@_-@do}-3eNNf{+kq>?G5~q6x`1n_+u$}fH&|bQgDtp@ZY82!QQ~1 zO2I?Df&U=|5BCQCObX8R2L7iMe2h1+?5W+=J!!MOfn`sV_oS721N)>kmwN+iQgDSguwM$E=M9`D1y_0l2c+N=y@7Qp zxY`>yCla4GmyZ{QJ9@M+$_ zxl-^M-oPWJ;4{5}kCB4U@&?Y6g3tB_9wh~z;|)Ao3O?5xc#IT$zBlk#DfmKf;Biv$ z#ooZ@e1kXeR4MpIZ{TTC@J-&p)1}~Byn&0Q;M=@`XGp=fdjrpug75SOo+Sm} zx1(VOoO`e&8$=}LN zo|S^h=jA5PPQm2wb$xU9Bg2_M2Oz?U*sllNWtVAa+5cvVDhhWlQ*Sc@=dwPTT(FjmfYlRDVTg)Zu0gNOui#Gd1neH z-<6xZD+QD9$xZG}!Q}gLllxOJ`GMTz-6@#-P;T{prAInWX zl!D1m&lq`7gQ2=Tk8G zx!mLnDVY31Zt}$xO#WML^5qmveknKkN(v_bBRBbK3MRjjn|v(=lmC^Qd_4t|U&~Ft zk%Gzp$xXhQg2`{>Cf`oMCcj9*q%Jr4WeO&Pa+6=BU@{~(`E?2=!*Y|~q+l{# zZt}YnOfsp-G&Kd2z2qjf6ioJ(n@mf=WFNUnJq42)a+9GHOlHbWrl(*sOK!4P3MRAV zCi|pdvaj4^W(p?z$xUXbV6wm5WWN+l4v?E1kb=p9a+5hJn9Pxz9Grs5L2{ErQ!qJL zZgO}ECWpvP=B8kBsNCc+DVQ84H#sT=lf&gE$E09#gxut~6invIO-@L`fV6sqdvN{Em zMRJpiQZPAHZgNQqCa1|w)}&x^y4>XQ6igP&O|DGA%OdcmUS(k#zYS>`cMrT)D~a6im*Oo7|Ry$@y}VJ5n%NDK~ja3MLoGO`e*9 z$rI%!PfNjMmE7bRDVVI5n>;fGlMCf0&q~4MBDu-4Q!u$$Zt|QIOfHd|JU0cCOXVid zPr+o3+~kERm|P||d2tFRm&;9Fl7h(9SxyidzFxezGd2b3P zPm-HFn1ad8a+43FV6s_m@}U$=w#ZFBl7h)rxyi>;Fxe(I`9umP+vO&oO5UVW6EL>B zx4z)AC&2f(w{K1#B&UjvHJq1xKYdpX&zCk%Bi$!EqnOtB`{0q~HtPHP4lT>!odu`*z+uDL5tt zU*fKLz7*Ub1;>42uTlzbl!7mF*StUq-XsNI?gpPI1vg2-SGd7dQt(MqaNH*VtEJ%0 zQt(yoniopJ&C(#b#tmL11-D4S*SW!qrQlX6_y#w4i4@!>1;>4GaH$mBE(PD@uDM1E z-XaCx;s!61f;*((+uY#gQgEjfe7hUGLJIDZg70*LS4zR%Qt(}F@G2>Is}#J~4X%}f zw@JbK-Qd+y@OCNqZZ~+16ud(Uj{8RAS}FKsDfpnf=5HY}Qt)GLa8wFDO$vU(4c;gPpB{Kpavk=x8(bd`&M5T{3_KGD-WPbz z4W`c}J1!qHO5xh`w-RsE*H%3YA83Nlr1cqpud<+a z{Qkg8d;Oy(JaVHFnD7Yvh*3dvfHK7VbXqS3K9x5>SA28yz#r^ataiR5#7ES!{F8gE z5`3FR{7dqf8`OYa!HR>!YALb%6zQy&wKrg zk64wfdaM#Y3Wrq|VwJD&^{+f)RYrQO5Ihv;X*g`aqZA)}GZ}hS&D2+22W_ zvuDjA?(^L3{3J#WNr*G~!yuK++zHjU`<>*Cb-%Pdj z4HReSQ+eM^llDz9g!fE`3-9#YH+LSYZ=B=iPS1UFr{})8^RW8n&co}QS;_Z}y`~(! z#O#}6?R`@MeRC}Do8zQ?Gdr$tc6;ud-G}NM=eXJJxo>uR?wj3*)i=8juWwFBzHjU` z<>;km-;~+=rWE?7jQ35s**7Q9`9@{XFBOh4vnQjX=jl5G)aSX>*CkN5pBMIIRQ9a7 z01Q{T40rde?l?8=$%yu>xxh)`-?@-<79F6-jymsThgxzQ#H2V(A+xskU zD|Z=#2BaPa&6?!BZLcXuUu$}Mo!#4O!Q1P&x7SO(?Hn}w59Mv=pxN))+xtCxd;ej1 zd;j5iJCeM&?KS1-8%%FU?cUx1-i~r_Z#2BEwker-ovxPb)*E;0%@A2>2ldukZMVJ! zS2tXlYFn+ zYJwT(BA78K(AlOd;KD_*9#TKf0KW^TfY>>>1B>9fqN2N#^Z(MdrKkivOZn)lKb)538Fm40;@1Z*GS3UUu-a~cVuX_S|@3?ypr{nHD zypFr~@H+0MShnJML!axLbI~-D-ARrnqu^9frYg9KCj5Mp@4>io?x$ zN8`Q>xJl{h7UO*x^Ly6ZZ68$kB?=tJ53~C+B0bxT`(bvUtzTX@2h{654XC@!eu*kU zK0i$wKf%eft>@YgxX-@!+9&CIL|;wP_uBhv5A@Yu-dA@^`|4gtUmZMDUpen^9Q52* z2R--ILC<}4@UZ&o;NkVveTV9+gBgd@SN7T`=?Bfey5HVc2cfU-=Y92n{vh3tS6+p2 zrNJ%X7z~t0ck55VZQtKjP1vVDe?Wg>f_6}Uai9LmjY_C`;y(Sg2OiY39@Jmot-q!1 z)8E~ve_-CXeD z+c~-K-1n}`Om=6(vI-`qHhhC_Bbd_*mX$f-Tik+xpBD>)=>>DP9IFMvOAz)5!U^sJ zh3~~khvKrcG8f^l@E4Z4fdvWoSRK^It(ZGSe5c!4MenKOyWIDs9jjtq?sz@!_@V8N zAE$lCdyQe-&a6A$YxL*%JLm($f>9Noy$l-;LXz-rlGZ6n>ud?sJ_mC9csZ@h{~JKP zcvjfUTCsh65Ve97M6LE^5Z5OQB2&2>d-*w&D(@g>WdAT0ed3H^i+4IvpyOzxCg=wCh zC^LI;nrGLRnY}d4v+KyrUY_RJb!BF+O!Mq|GP76P%r>TUHmEN%eQnyOH;|eBt5XNkZ?&DC(n-9D%=GPPpWakv`p&dZZzePS zJInN!Cvi=Z&Am-?`#E?L|2~yDAIZ$wZ9hkC>!*dxoV`)&w1u~5t1xE$MbOyF7>+kv z@{ieQtL<{RyuoFERFbwvlD4M#cL8mpgF9pTb)kAJ{kov76KnZ(!H}Q%5PC*ZP>srM{8NeXgwEzQW=L)V?JIPa9V;tuR_asIw!42F*g;wCk zDY%2XRYCOR0Un}V8}Q)ljDT;%+ehycc~73;DJrxDPfo!LysQeMCvWf;?b?AiXXgVx zRy%1=?c_cAg0HC10em?HKk&0Eh@SkxU$pB4{+wL^1X%4PPwnMB0f4B`1%Oisgg{Y2 z+f6JAES@ZoMYQVySvb2O2(sEqo;t{T3Wi`&p%(;m3RxkmRYBZS2!x1sy&;6N3kAGD zQ0>u*Bu^dXJ%vG-sL&U}IE8GG&8i@J$`08@yZ(@!v&#WFtag&8PV$~|0zMdqeKG)Y zatgU1msLUZ6b|8{-5?0(>>?n-YA1Q>Ebl22@cA?JGz20!g($#ZccrL^o}xi~M?pIj ztfvt}LJXMSRIrI&7kN*yU_QwV2mUOR8*E+=}u-UaOt7r>^pz@8cD427+BlBb@=EZo`1a^5QfMMQ;(P=r%RfCQ_8xTm5}RJ5B6MLD}-P|Rv4 zdFmzasW=oD6~2MuoI(jGAu0&2(w<5}NzrZ^l;rG60bcm&yhnDDr#|x0D-ESZg&9zq zQz!#vtP0|u%0gMuZWff~?8-qotDWSjue_)7P+nA+1LZk|3Q)nSAbP3@6-B#wP?58% z1eL6IlBa(1o+?9SQDFg8<`k+x6{~{i=>zycv|9upaCTLps?|>N)L-6HHK-;kEP-mA zLUpKaRS-SZfEuFRGN{4X)r6W>JIT{$@}6ozEm2_w)Z!EpAGxDw)LPJqv zJv8JbK7n4mQ$(FWRBS1a!7WB6FK`vE@Y?Ak(GtDVKwP#ag~+sjYj6LJ0?_=KC^4%(UL zo6kq)TekMlUNqeY?K#s9(7|eIaWzclPPQX-6zA`Uj@F%&IbQVnyLTApj z3v{uXT3ih`=HgE2=3RA#uHyW|(3P9t4Z2z9ORl;@chU4HbmvTaKo6^_#nlKIS3RMp zIR7~Gb4AnSn4+ zlsO9nIhjE)NJeIKGMVX;%wQNS%KQ$4Ihi3aL`LSTWHL)6na|;KQRX~+&dCggp)xXK z>}Bw#dKe57=U;?j-2CA%T%51HES?3-Ei(c}h^ALz1ZO%DMp{iRX&7tt=IYpTBKQKn z5GDSAFF1)W;Y;&s&6fx54U5b;`zAN9WE6}NWp2VKPG&TWwvoAQk@;F)<}3J0l(`FE zaWZ3I3@;-*w8)H?ml+FVMVWgrmXjF=<9Hbi_1EyVX!iiV=IqA9c&nYo)dYE06JUZU z@dzex5))yfRYE+GPJ&6I-4mF^*-eJYRy&KUiSn+dz!Xv9Zl zqI*A>&$(X!3zEABTlei#b?+kU-C24v5xp;jg`)Q?u#oe<2o@#xp4G;?C!3h6dySlX zyXO-vIh$tl`wX7mb)jN0FNVe93bVmtZiP!=i8=R}m>k9s7k+KijWLdwmQxg63QI-N za9GNTE`wz$h?Yx1)Yd({A?2Vhq>o!Y*>rxt0)9@di?!@|IV=~Kmj{+}%Ub~}tjlxe zUCuD3u(-V9j#t7;Q8GWQo8Ju*G6$lf+qRPU5W8leiVOioPqtR?hb}*kz7X(;ehuuFQ418e)*bD@jPPz$LqAF zc%FS=gnXE0d^S(u#pWCHI2055Sn6edGO+*>v#pl}Y13MeOsfdhpWVV1rcG?2y_gH0 zS9LXQ7q%#ET8r$pgn_74$5_&6a{^kD(izhlvL(sXdWmYbMYl9*vnPpKGANHppn!>G_&G~6r3imv^XtBc% zzyZ;HQ#io6KL`g!_b;#TAMr)J%vjZN5u0yB4#6Q&v?UzkL=VGZUex^iPa9k56ut~= zmOcVUMCrD0gp)oBN6q1)`!HL@ekm;0(s9f9jMJU7__q>{CLDufqPKQ%jPrIJjyp`w z^3*ea0#1mc9pD5fdJ;~iAez>UFHb$=KfzC;`%dr^=l*B-nNN;Q#+Rp_@l$Y06zu}1 zIMLH^nirMH`0|v#H*3!LFYt>f-3@->q<@89&Ec}o_;O>KGQK=n#_=yO;N8L*I3s%N z0cSXGXW^{FKVTP7evv%aDfxO2p4%#nT)SUJ>!?)k|^CDE^*SA;j%eg_8DK1wv4YxmT~;M4w&&P za7FYs0IqP}uEJG^$yu3t#;?IOQFIVo<3#^}KT;4)YsOcmp7HB&U35PLu5<2hzzse* zHW^=;ddB~RKSj}@@FypF6K?XNG8tc)dd6?TEm3+n+~TBf!)@&VHZ5dygEaTsm+jt?m)zcSDCX`?=R6<5*yScri^&R$M*H;kVEzpP9y~D6GrNH;WU7Ozuz?_f`?pa9>F7XXzi z{ReysccyS5*IVDP*vW^H-jl*Rp~vu8Tz^e?%&q?kJdxHVA5;!-g-YAOY0N$b#d&V|4cs!$5r~BdJ~R6>#yl=2qr^- zA<__oV<|%|LmeE47$z7dv$Y@ zxgK*piQ^xxPhFo2CbuZJqHZN{Omu7M)&|FkZVTO(;JD50klRrl|8@6p_YzF*x!eo6 zC*auDy^ni;9LKrObzgwvaraB^S8@E?!{FgAm^_MkRP(5bV=IrI9=&l~I9B&;=Gg+r zUY;X7zr=Bq=Z~HTaXjz&m*)e)XOm zaQ%K&{hIhS$MI9Yk$$6a+~Ie`@3>&{clP)52OO*VH}S`x`%my+;J+Bh6aJU|ui^M_ zfJXqvJ)m?zVgS}dz{r590W)ws5^z4?l3)Tq2!|*fOF#`s#Bnf;he|VleJA_^05j!Pf;-)`+Y{vKA9eA-*BGLLzZ29#TD|7LJ=k_J=3$7s4(Jrff&DozI5*$UZguvg|7b zQ;xVC<#JTSaa4{OIc5tcd|EgvJQl}J;RC~m;CL(i-w2gpiYOCNI|A1mF*9OS#9F}= zX^0GpM1PUZBfCaoz9P>>-i^e5iYgFQKB^LqW25Fo&ByVdX!mGO!4#bs-7*^MJo;Gl z#po-7DJEA;p%|>|n87jQV=#U(cVbzrS}?_yi>({m0LSlRPsW}SOt}McN9M-9%iTTq z(A*;gQ(V`$A#uZS{66kv9R9pO)&hA75Ita@oUE~@J~W(UVb^*`UPddhQn_z|0bHoJ2PiTD}yXm^b7@@l5AT&~V zq;!=_Cu@?{MQKY2YmbTC1eP&`IHw(pxp1u2EVi zr8zyXkxO^=bR0@4oKo6rrt`H*>!tK(gtc;IkeC5ND}`4ohdLQ#&Cx& zfkG{XTPl+V8Eoy+`l(zp;@T}`lfXXAfT5SdFO^T@47vwtA5=yec@JDUHO;`OkkTQQ zRr3tK7im9KUYTJpT$#1V1gVkIBb8gLOtL3wUsQIPX-{1FwaG-OlF}uWVcSf$H)(%V zj+t?9ma;6w+GWDjN$E3}XExR$lkQR4CzWYt-XmA8oicGMrF2SV+a;6lRoX9=@B6S< zu8h0A2dS0PE0uGP_hiq~zNxI=r#*A!-RnI{wUlnD%zM9Qdzbc4<^DeIoh$pk?_uht z^h@R6|2>U?6bEX9_c;cZb|}FHyvL=$m&5xW2P_F!@e5BS*r4~kB>1vWVsU`J87Gy- z5T!IM-w&jVh!PL;_a(U!8LE_sSR(vcM2U&HOeiLnQYplSE2Uy76{%dLTlA4iY;0m9 z#fQ$iN^Gp{L~(i9R^~6WC$KM-(n(f2Qu&zMs{|XZ#7H(q_Hi1c#K~ct>|-@fiB*cR zvW-^=8?VGG)p$uUqsyKWujH3KijVz2yu*|(g%gz$OBNpca7oAXr*q7g#}GDIiCdcE zM)9NAQHv^ZOWuxBeaVentA3-D+$)uwRCZF!PE+Fd%JGw8NUf{H@6}pYYGm}YqRAtMQ(tYiv%a^Yb z-`8Kh6koMi!se&=CbJbv6~B=x<||o=@tdh+Yc-qC$yL}YrJCPZHS-m%#QDutG{spX zo};m<&4qoLtx*d5jTSav+)Aw9Y;jYpE%(tOY@JftZ@jem@>b&g=F6MnZNASopTN7b z^-7h$l`7{eU5WYIsdW2lugsE^YJY3h&R4t=_qSK^_Eo=!ZBnZKtyVo>`AY2HZsk+# zxtsVcO6kA#(&x)xiT~R#fBOqSceYLGf_Ksdd?zS5csHG3-wl=74y7C3SvT+7q;cPEm4_K01YRf^STjFDNzG9;H>%O{?(jqU0t0v-Ss%*c~I_a);`1Voqlm6O=^22{Kp%*)-bWytOBEFN99Hq}r zvUZbnO**V}Q@ZUYzN3^prQeRS@2W(0ROza8-Bo;NDY;7Don_x$t=Vyt1lX|W8^Vtkt^Im;MrX1$=9KaA?depb3I!*m5<2z8vU&iY|`z~zF&MIA)A-j<8L?wqAvlA(Y z+*>ZcE3KGeTaj-^C65`m9jzBg>8+XbN>^s+uH-vY$z{gwOlx;aZ{b{2x--LfC*Pq; zJ~MuY+IMLpyR39+rsz_>QH;BzJrzgX1)%#cCqwU)J>&}Gi4X^ovh?Ib9S&)HRcHPY?vwKQ+XZr5uJ6y?k=I?O( zE>C0+lrDcSx}5KHCFk!)r`vVA%8NZxy8XTBcE014yuUvkPkFcenOXCPVjI~LrSadZ z#+RDEBK?_R)}H;X}N)SwR z8c=HB{W}FnHSqFOV3^97lM@@n7}kRy)3QjGz?!h4Y&t8(eqqH`0jz|oJ}ar3#7e17 zu+mPRtc+6)R@UirR?f-9%BxkZg1Qu|sP4fksh6a(nh#>hUbV?c^#u>sK&Z|d3ZvPF!hY6Bt7DC| zl~@z)2-Z})hc(kVv*x-Y>?2)A)#TZ0Gt#L$PeGhAZrU8}JU zt{YiLw=mYpZ4~S5_KC%H(9c?X+fvh^x(a0 zMu>sU3_Z$bWt+t2WN*gi=7?nTa+YE9bB<*Ta-Lxeb49R4xq7fAxlC+nxCdJnsbb5c z?z0s!SJ=wjr`YN|5o}GKK5T8C{cK&{ENp$=4s1i-?JOyuJKLDA8QYX^4cnYw#kS;6 zWLxvkXWR1MWZUBkvK<9hu$=|(vt9A6m??fN`#ydu+Y^7735IEm=`OQ>boZHyzMb$F zbJCq>LHhQr4pZr|F7zFc)9BSKtG*+0YJFYgIw9wxFUi96oso0a4??aBa$0>mUtHq zFOUmyD}mgX$YpbjKyDOrVQy`Z8;x8Jx0=X(g@3aS*wM$Q3o_KyDFoC5-OKEk>@m zu_|&)kSk@3M{X%{C5>Z{TZUX2V{hb^BUjp(gxm_`${FV%w-ULs#wW z*WNb-xu22i&b}1;Uy$el&5hwp6U zenYOi??dE%N3NIeIpoeE*VB*kdmg#oew5z}$bIV99J!0g_4TWQ+$H4t_>DsDGIIU> zdLnlPxqg1fk-LiA0KaX>T|@3Oe?aaJPvjN{V+|R+kXsgv zHDvHcZfWp!4?!+Ja{I$OAQy++j}a>53Ltkd{7>WxB6lEy@)nQW;RwoGA>yzb z+(NDfa#vy-AXgK)KVr)uR|~mov8RwrMD9lHcgWR7?s{&#S25H?c80FtB>5RxM9dOK<;i_XXF|pcPEbYK1A+b9O*Se?ymy*k!y_Hg91UwH9_uv z!D`4gMeb3-LdZ2k?qR$ea?O!@Qt&ZyA0hWRelT(^ko!BnJ#sCPdm5jFTr1?B$In5o zHFD1wi$9{Sr>@VK5pLMtsSMNUwUf(rW^}p1jHqmKsNBt7dCjXSA8@GL!(Msqt0|v! zsNBn5dEKii|K?D+x4rWES5v;~P`R(Y@`hJazT;52zrAwOt0_Nms64=4dE+Z7>s1bw z2iYrcdNpOeL**g%%9~$J+1H`+PVj&`U#(q4Jnt0~7jRQ}Rl zdHbs<>kXp}qwz#V=Q?jZq0uQ#h}vS9#2D$~SvZ9P{FcCv_HwV?i9_aV(5u5gd!+ zSPVz}MUj=nu{4fla4d&oc^vU#&nn@FH$LnG9IJ`z^kg+yEtbf1hM9QmgySq64fu0C z{xfuEu7=sjuVP`UT1=&?qD2|RqS|8G;@T40QuwbJak`1Rsk-SBhp&iB(rwmlv2a^n z+U=IH`%%X3u#DYt8M{+5c4uVl&dbYVC5-WuMCBn#&(5x;s$`)zni|LQOivOPxxnPlq4UAzq(U zLL)kCN{4t+Q3=iHumv8{l|UtYL5HL15KrGKA(#%oA{a*;o_JNlY&x7rhj_MB2}|j4 z1s&okP9=OxhnwjT&r2#{8y)TxcBzC|DnU?^pcFxAf-(eU3CayH77;8a zSVFKAK~D6+A6$C2@RuQZwSVOQDK~;=itt0rBU_HSGf+T{C1e*vp6Ko;a zO0bP!JHZZuodmlGz9TRZd{6KL!ES;*1bYeg5&TH7pWpz&L4rdBL)3#AJ4~;R5F8~q zMsS?q1i?vyp9p>?I7M)p;1_~l5mX5TMd}CHU0kQ^tA`bR+0O z(4C+&K}UkF1f2*v5PU|{1`rG+=tEp@f_?;j3HlTCBBpS+6C5BoNN|YYFu@T7mrn@V5ws`hK+ut(6G3N!E(p#?362pQCpbZH z62YYnz50n>wWU`-6PzMAP4ElBuLNfZ&LX&cOs{?;_?_S!!FhrU1Q!V|5nLv?LU5Jf z8o?g~*9mSA{7G<=;1vB_ zf#AXjR0K{0Y61;`GeK*DRs=2t0)du5N1!J#5Euzu3ET+W2|Nfq3A_lr3492A3H%8B z2?7X!AdnynK@dSOK~{ngf>44mf@}oY333qRB*;Y&P7py5Nf1R4O%Ov6OOTr&4?$jn zd<6Lk;s^>56eNfzC`3@0pa?+%K~aKY1jPwT5R@b+MNpcc3_)3fas=fGDiBm8s6|jG#He zM+7Yp@Z-lGOcS611eXJheN4UD20>LpRgtM?AUNG4cu4Ss;2FWc2x=99hCm?D6SyI$ zX45Mpfj5C40T2Wcgb-vS$Vm`E5RIT(K(BHW3Lbpg2J(g7O4a5LAl^RuHTv zSWmE#U>m_sg1!Vl5bPy5NN|MUB*7_yvjpb|E)!fM7)WrF;10n9g2x2U30@#L(axP{ z=T5E!9tf(T^vZ|8pMdu36he@LAe>Jv>n zm8K)Ta@OGajqU|Bbn(}8(R5X5de9GAXj-Z?ZSa-)srqlGp}P!CNlhu0rY!xmf~KNM zQ-ywdTKx-CUsYdY>JxMgy+|;NE~yLX)kb=?O}(9I@@ev`GzDqKO7$wHzNx;&)N})+ k$)?G!(&QphAG-d2M3=D^1T7KN4b%;pVJ`k2t9EAWe;d*nGynhq literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class b/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class index c8378277ad72944ceaa7c5fc3981c15e81a9bc65..ed1638bd216cd4bf8d4015d38699cda687d1fe5b 100644 GIT binary patch literal 9465 zcma)?34B~d9moH(+0D9}NwZDbrlm*PW=qoqnjUE>O)naHq)l5&)3gnhY?b$$2spjU9>}u)^!pX*=wvdPJyI`Kf`CPu3f_-MuLnTq8`RS`t*= z^`MhZ!m2;LClPlK`e`zHtGtX6kJ*PJ>BE-eB;pq8`|?4E=XRrBbY*ODBpHDrVl346 z*y-4z5(7sWDElRO`~2-_ZKLp(b<>Vj;P90@X$+!ac!Z?vQG;08afH0(7Zo!hThlszX|$wR(kj0aQ%2kl(;AljD8F!HM#gi>e6vu-4w zi`tQR*&UFQI#~Ke(AJS0hG<_R6|-}3OAc%lp`AWa3(u1Zot$$McIQCUPQ+2Yz)-xZ z%uVKy8*#hWz_uxF#qhf1B8LSWaiSNA&_emr^x$CDLdYn}Bx1=(GMYW4`X3=T?9XK* zjujp4aFodR$+5CI+l}P=KPbFM<8eoLDc*=)D%7CGK`Rw6niXz@S>Xm|Tn!321VjiT zP}j~yl1?-h860F35KgTlu?T8IiEJc`;c5*IS}`{(iqtquCzACo zL@+v9M1P^Avuekx!By;D`MAM^BU{Eujx2F2?J$C6za&zTcnqD3{wXg&yyXRmp+1k` z_Yg$cJ%F-%(F$pA9dRuug>eUqx_C00pCK_{6b42~F$RY0N6`>Gqo9K>=?m%$;Ih}Z!&qT{fjM>3 zBH{2IoR+A--pOgH(%!|XOKI=sv`lI5;j~<7@8xuc(%#2uh0?C$bf(hY&uOL7KESD4 zX&>aYN@+K7TCKDXaayCa4|7_pw2yFFr?lHSou#yoa$2vnk1<+2juw``Nt}9AJ3ql` zgYxr9P8*f>DNdV|_GwO=mG&7shN0*zTJ)EAQZw1Lq-^P@cZ%}V4lM_pi@8Z2IpsG*?`TYQWkA8q| zFI46iByueyZGIS_3G^eRyl5t4M zsEPgv?|CfWc0c_YE15#j`Cn+Z7z$qC4 ziIhqQoybLwYj?_ZABca_zk)P{{*6>u>|L{Q@%f|k>`D4>5Ka1DNw?28CKB6p2!!Ao?yWM3$QxOvia^SPNCrHMP4)1 zNVFlqCa@4PPH9jwW&2rUkTr=|!o}vxQB!Pf@i}mIl1&c6*_0p)i1E}o_K|)z4b9J& z@5s6Gm0;7w!cHrd!OaY?8EjUN%@F>YOCv0q5dCaUkj)iwHsvi!rYk=S2iZJPJ8{g+ zgPgr9aUd0Sa}IL0w@0S#2IMJgdoH=(a{8lK4U0}s<6~$b>LkSdXkloZRsXst2brialNU*G~Q}i zLW?oAdc{W^HHt+8v__Hpr9|eJ5_w-rWPK@-^QA<3mlDZcN~Crvk=Ug~T9*<@T}q^M zDUr~nL^_ue$y`dLaw(C>r9{G(5_uM1k!{dDh__K>TUm}=DdhqdEcD+}vb2Xw9sXbJi!Rh zGQv?EZZN_vMmVO!AtOAS;)V_z)Zs=WJl6;x)Zr#0+-ig`)Zs}+IBbM%9iD82=NaLY z4mTU&Q;l#&ho>6h`9|2$;b}&=%?P_XJlzN{Fv5p*c!m*fH@=cbba+mci ze3}uyM2B09@agnc!`Qx5hvyjKPPz>9jXn)suEVWk;nCUt?U;_17<>H+-AQ;2w$Va9Y**JBYdq6FEqj{jPUh3+-Zc*G{QIN z@FF9;(g@$E!%K~Dw-G+7!(B#rl@Y#KhnE@Q)kgRh9bRFC*BIejb$F!_UTcJJ)8SP{ zc%2cxLx)!z;j@hJojSb62(LH7cj@q2Biv)0QSR2^bz|Yt8Rg@c6gC(mxJP%geykI~ z8;$V2I^1J~HyPpkbaL*Wpb@xYq~|>F{PFyu}DVq{CZ`@Kz%{qQhH_aGw!= zM2Gu~@HS)OJEp_ijqr9lZb*EO>hMk@e2#ILKCZ+4W8sp-x6|n43Ej!=*K~5O(aDp# zlY!TCvdj1@Jgqy~JJtzam}lqW>LyNg6Sum_VP!J*H$76R;^Imbm$V;e-hB@< z|1e$JKE(JCn|Pcxp=R-LT{8}wYsX=8{WxrH7>CV`L!mUlakjTy&r7Iy+7? z*h!knUZq){5Vd%)Q|alVR!={LJr~hD&n-0H^EkD6UZRc~KP{~3pw5~dw5TRaOKXl& zSIu!+R`VjQ@Yc{u?|fS2-9oFqNm}E*j@Eh~q;=k>XubDk>haalM&Cl(B z&d2E4Pzd65+_WR*2G9u{*9mC&M93z{Nsv<@n<0^s@n<4Bfv^?q#};5GG!Hy1f?m%U zwiJ=X8BXi^8IJqn3@3fKU`fevzK08zcnqg{xZtZ-?mo&dZ~5)ca7c+VET5&Z9K{8nm2y{-;VgO|!!a~2*zIFD;6w%X zgK%gdE{`fWzFe*|oIaxrJ64RaRfhu>VTUCe!;UI0SR&y_OH|;~gy9Gp a7i_HIcu+h8n*a=Fi@4xRkFmv~ul^4qeCpBw literal 9634 zcma)?34Gi|702HsyIFQSZPKJ|T6(0V8=9uj^rkeuXnLhhTiPZqAhK+C|7q9!_h64w zL=+VP5s_O!L_|as5hx@TDp(Pb!xK+bP(1NI@dV^IGudnMmJR*ze{W{q_x)#PXXed+ zCeOV7$YVsbL@X85>}GNu_&?-kBB4mu4FLn${FiDkQz@l?!pcBHbgWFiwRPjb; zhgENKZ!DTU;G>D?t@1oUGU5(|k_Vl1Iu>C!r=hT#>Oa)%8f$#hy-P13Gn ziT$npQ^NTD2E~16H7$gT-4D68(Cs=3J#^i=c}qUL$;Of(+OFPK<93ge_C8{Z7rWu zlGd9Re@4L8q(!{-UIvrXF9Cw99B;mbBYwUy;;nynaVnA}W~ZQ*e1xsA=kU?j5Gc0oSl`#PAt-28VKu5?-zn)E^i4l~oxX*)?9QfRk*uI) zC0$+tWcDZU^&EXC0AJq~G_|ep>T*-GN7B>u{Q!CB2UxuF4eCy$a%xZVJZ5MCHJQ4S zKlam)=qKp*LScTVqBl9(=0!h^qn{!chEpl`0!c4XUjR8jS1l@F>#SBg?vrb`+W49lDg}~2zCE$Y28hxuGjDV^gH^4a&}e#+Mlol=bdRQAN_@E znBJOc2Y>TZ6a5|D^H{#^K6(XPoI<7Z*&6znpZ-bz7Bsu9ySVP=Ey}lYuy3aS24Md` zL1HfkPRR&}B}`!GKvYU+-44AW1o0ZZ9-v9|e+0c^@AAgQ_YbeQF9{K#CQ(z;t*XQ) zJP1eDlIRoIY}dBwaU+fk2%qqm^u$ItmP$F%pihh`?TLK0>IpH{FQgcU^)}yq#l;j{ zgNkrWiAEd!V!UWV>?y634&FX7F(4+Xx&({O*Q2J`+TwfQ>?JWd0B2JILaOo9IP#S~ zF%8Yn=kLg6^^_1Z)Q-=})s>s+7cF8|K(r`-&80OgSrC097!a+ho=tg+lI6-L<^)8W zDjh#!XLD&pZ%>yF;`NAF&h}hhgrrH3;cwmI1Y z$>{0fbU5x{{2;W;?nJ^#>+c{3$@&f0!zR_n%9vsow>z0jN1ToLhC=af_371}aPhkC zM1K;qTIbM0EUg}V-7Td?wS9orsCEHbVh^Atb^ux;{%eWouO$M#mI(7&BFJlr5U(Wy zyp{;>S|Ye>iO{Yk0=t$7>slhHYl)DqB|^8Bh`9K?oCm!I^=(vfSLY+@YKfSuB_ght zh__lI+G>edt0f|>mWZ=jBFbus7^@{Btd@wcS|Yk?iP)+oBCD2&t6CzeYKiz*sNV+E z4^dL*BSvb82&pCFqn3z{S|T=TiO8rW;-Z#_idrJ_X^FU3@UPmB=vS6T3@l3{5`tSs z0>5YEmOo#2a;YJodfrVo>+{D7OS$M#PC$Mmk zh2u6nk%e1XIBCPpEPNshpJ&69S$GZ$XKZ*13%9Xw&W5M5@LU!?--f5La61cMV8hc{ zcpeL1Xu~sD_#_s-$c9^3_+)w~Gqx|b;aM!)LGQ+TV=qIO*zoL;@bIet9xO+T*y>+u zI|+_-0(dbCUv9&#EWCt;udv}cEWDJ3ue9Md7GB1}SJ`ko3!lQmSKIJB7GBQ6*V^!W z7Cx1Queae27GA-^H`?$57Vc!>n{0S73$JA1TWoj<3$J3~TWxqL3$JG3+iZ9_3$J0} z+iiFS3$JD2J8XC*3!lcqciQkO7GB4~ciHf27VcuOg@p%gcry!cW#J<>yoH5( zSomQZ-paz;Soo+7_ptDGb_@Ne4R2@R9rPFzHILcwP8QzD4%5eNxOXI65;b?RPM)xx z^u4K*-K>)*Z6|x))JZSm71^X%$L`}gz4%2@cW)9J- zLxP4xZLuE0J4pLSVG}Fbcq+IVsBRK3npCV!vS?H3P3KiN$y7JVRW~`my2%CAO)ji% za#8zH;XCt)2n^E2?T1DEVKL#Tn1qbxA#wchuO+4)6VnIjlIq?rEt)jQ3cuFnB{r1? z#ucNmxf0bq;V|(7Ow2x}2G~`ju(^5^HrI~A=K4|C+&BuGn?_-S$zQeYw~oT*wo&x+ z?L|K$rp0hK-%;J<&gv$2RX4dCCK#Ws7@sF%d=An*MW&&}9&p38ySHfLtzdFr(WFuv zAE<8fV0Dwh>Ly33n><|I96%-!Dgl|Lt%^jp;uqm1CgY>wa@r0f6WO2ZZ z=qN-THRqms0HbnQi4_z?y0Zwzig)n(pT>?X!hg6ioqYM|S3nD+$kB3`BmVhsK! zWIi>ET{KzbXo|Rrri!C9O}t3cajrk3CP*zcI8dzFMYC(t6s);{T5BGrIW;d(8~)6u zy|$I+)ppbT+BkL8UPB9N2WfHb^R%S)HCpPKMaw-KXoV+6D?L}zD$jki+VdQ(@w`H7 zy>+zC+fH5HZM4ywqD|iGXfsC17Vq=4)%z;-)V0v|y5+R9u8Vr>da19@p*?j6>5RIY z@rO0))NqoC#>1zEh|Bb>Xve0f17%)8&o(qbEI^{2yyQnmNIb`(@#7(zASXahf^3FF zV8?&s#X>wir_6giP;$#~eT7mmUJg~tOxMjox8$N*( zZ9H%Qsz3hq@qxg7De|x>6S!f8h7Uf0dsRGe9wczlj0e7H(4Fdm!xn+-WjydPEO1YY z2R=^q!KlCm`B?&Y<9Oh}QQ)o>1vrwz{e^nq6GPxm78(vt^v8nU^b1^xBM*mWf^b@h zyB=kSjh?`vE*{uu35*#O;LBg&+7=HSlHt}#J#aWFaKQ`>dntiyU`L20s>9v@zex0} diff --git a/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class b/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class index 418be0fb4fecba5117119b4e954da584d1a88685..8b506a8c226aad0676419992a9cf79de0c8f672c 100644 GIT binary patch literal 341453 zcmcd!2YejG)t|lH)9u}jBujFWZ7{-eFR~=tl5N1qaub%^BzK$hSvtwGPhD~WW72!R z^xjA>goK2I0O=tiy@!O503jqKA-$0hAbju5o1NWRt=F3a`v=y%H}huZKX2ZYotyHF z|K9OA#@MowhYePm9~rBGf0_J9XQp#BpJ0Z;F6uneJCe)S*Yx&}=7#&T`I^>TPqy<^ z+d$V?K9^vo!73e*9l4>g-r-!+$f^F$9l4R*XoAHJmdN)Wu7Q6EmM~bEC;cTOo!NZW zU>COvqGmYPozHcS*0iH{dv8yFc64kwx7uLw!>2}bBgVuPMMkpkh!ItCDp$S-vLhopbmC6G=%`JaY#YPko`YVsF& zy#CFue{HcxezWU8t9>ykw5184|)AZT>sh$9{Fos{~_|P zDl3EXR+y+~)57wWd*r7J|ClJR*MFAlUt8gkU+DS|dHw5M|JsQj`PHufkk`N2^{<`e zk>Bk44|)CDUH{t29{K&Q|B%iM_m8fsUG=jUH>7kziBDEt*!LP zr(ORcuYZN>UpvhsKi%~o^7_wm{cERtIKjigqcKvHF^2l#? z{f8X?BCwx!@?V1O_hKoJ{`+13A;%xvb*Gz7?MzSl$6Ws*um6bjPws8%Ke+nP-Yqju z+vPQ$`u@a-!j2T^>yR1u%X^o}vNe6n?8q1DOkFT7&)>wYntjtyq9B3T7 zZg#S2Nt4yJea?(M#RsOP;DREcFrjqD!C|@n0`g|?$QJGX$Vg= z8>>dA$9t!&HCFe>*O%>Dd~o&A++@DIW@cm8?8%VM#YwZTJ71Q)xF|MMRN1s-dR;2s zd)Yj|b##4EZPUEzjYoU0xwO3MlB9WEthX$?$C!MuC_iP(fo1D5tE%@D&s;rwf67ABLGM%;`Q#V_B!wyDXQRF-V1%9^p_m3;S->5WGw6(@VE4j9RHh}U*ereI08QEAfZBqaB_Zk+lTpt@TGcC1MRmJ@<3XJv7Xh=?q?<}vi4jU;mxw6_w^!4mIy<&0O(*89i zT@6c$VzE_Cl~py_(o`Zowqr|^xo+r69bZ$zM_Ugr z?b^Epag;kaW|+0vhMKFFcIB=+26obrFPooinVn6DacF3xQM`A{qLcZ`X@_!Wrf=+@ z9#5OoQ+wCeHpOG{gXK+eu%|QAHx0~K)s5*dI^d)~$w_~Kxm={**K%gol;W#v59M~1 zm2FR>ehyZEeirXfRc&8b(KrVA_Rf*{)^0W`Fke2S{!mL%_0+ySb%VL9PR}WYavgTc zH8+(tv0PhPd-|s}bg!8_qoHq4{YdVLi6>hx0-T#2oNX0NMTm3Oi6s};^=&@0u%U17 z(r!p^?!eSlpx@aOrG6{tGztA~DA~6(*Sv$DSTqCD+3!zh`c$w-J)J#RPwU-u4371* zq3^)z&b^aQ@9NuIcWCof6HjhAxU?V2Ie(s8&U9PdqQ=twP@lUjdu?;m4C|*n z88>I9=P$5gvGN6FWwq^w-M(tZ#w8cmcUP1pS1zcUZ7O+4r?x|;Q#CJ^#&o8xoE(o| z7jItMwB6jA-n$Uesa{Z7wtZ(qEV;9KYRQ3k+-y%*Zf-JnH`ldpEQWSGp=kN!*xIH& z=B$b`VXtcsY#f-n8uZ#W*{z>cZga`$4cM>s6?IL4dKziI`t*ikC}*Qn&bcYW+*jYV zrVh)~*weOU5u{TO>GZkj7|EgblKhE92Wm%mOS{|;cY(QH*!9TfEsHjlK>Nu+{R+D)<+6Q%-I-{2>5awHRvl_VJ?(ST zpCt5Mn`^m>>S>#cze<$9sCr}D!KEWmzm-dz`rT}#H?OKbv8b{>mpd~n0d|ph?4l#S zeR~_Um*(>7xdXx;`=%(p8AaU(%TG@(o>o7y<|-^lqg#&JN@~C5d}GaCVV{*XZhjM5 zCeJv*FK#%#X2ry*&~AF#P)`Tla#TpW*?8s{;yLc(G0OW7E*)(zU$nbz+OqDAJ7$~| z?J48x$FM~Iabn4VhNHb?=hwLLTh?Md_dtJKe4zf&=8_pF7EN0i8nLQQ+r7=VK%2%F08t;EE&Ii($Jwe7+x}YRg;bFb649%s|Ist z%toj`=zq%QSGnaD{a)+78#@fl|;;P+C_Ac$~ zDLK8O_~M4i@#ONDxwdIjJk!$DR8<@+Pwj15e4tj%J5aCHQm@-PjFjlt53Ydz3vrb? zxVD?h57r;b6`k_MtFUJ`#dG_MP76C~DcUZ|lU-7M zl20p(RZ{%$u#G>hqvFSQrCC5`N$DDyZ%LnB6r}(D$DKRgT4}F_H%Hl zE7vl=2l{Q1PTrIMOiJJFr^?}@ao_5`y=N9GdDMS}$hWR{bIF0-&BofbRmDT|wr`JH z@zQJOkRC*T+qE6$151n|%%`ze(~t; z;(f|LHg|bz1B|anx2{^Wv2W_K!^i4KztbnJYwX+80QS15u?FTB=F0hrLFjLLO8D*p zutUgqs2Tg4@)-?_LC-QjIZvsN)mFC7g?zC;nGExZ?w&19|1~Qy+bHR2zv^^%|BS}m zMjY29e%T)a{_ybP7NcbIVd!5EtmAHCVH_)&vAcgyZP&)h zGa6yOK=ZAGMrGR^u#0_lUHi|ZVSZIV+H+>%+^q*2VZ5;_ni9*7=FW_q*fJvsf5p^n zc(^^=@aumS^i!axeXB;-Oygju(BH>WRkIE(ABFkEiM9jvIptqexns%xRWSd*tY^uz z`a^9+V!Vd(P&-82Qct^NJM6}CI`g%#axXd%QtlP!DmU~`q2)dX_3A74o`!Md-hY;I z?+-3F^eesFi!*hH_HUUnW%1Q8Z(qT)mrlDJ#)%n?i}$V`g?3ME^WdJg14~ED zCT$+ya}dVs*+yE-bLD&)Ke_p^{4Pa3HrbuWww#_*v#&M>{W8wOK&}k>g{32#i>jdU$GFsX_jZjQNw6sfD^byepTTAy z%^uIz;JqqL$8xQ|bnTagmbrG1w$su+x!TWw2tBlwKOP0j2EA1vZD*u;I%4$OvG& zQecy;!KV0@_N%M2{R92gwF%Y?c>1$_z5PAS1F*t>aX@fm`zOho zE#3%V)w$vBY$vYN$9e~#-c-D`V`ysNUy|$Z%4EB`hBJf1xlA8;D4CrQf1JcH!0+nI zW(JRqX1YMNN_uRxH(#?WoA2#{IP(L%FKg}X@63;N<-{);7=Lv26(Gy;hX-W)GQIsC zc380Z(?=#ZJUjpZQO003=SH*o8lI`rw zjeuQd$MOPad0+1c=(eXn*X4Q^=T3HJ`rs#;v5_3cn$q1noayT9?90gLqzDL^h9O{A zfq_~wP`_tM213rB3WaD6%lhKJGHCkRm|q1pH4`Z6ala%SX6Z}(^pbjwFZ2cYQ)Phd+u zELpS(jnvz&)(#Bhq1G+%hPFJxBQKkv&mIuX;jxj-a4t*05nu7TrjDje+xoUlYs;4P zm^|1)K3mfChL1a4s3SPB)$N&`Fpw-0oig>(j_4$hs2b5gw%ps* zJHnH7VL1?hbcNR4JK|G(;&L?SarfJ=}9hpr~`!3hI z70`>Y9Xp!#X4b9W*0BjnjXoPUfpAm%rVJQ7cRbo#_JQHr$P$@e+p*T0u)|Tp$axbk zM(MR3O&c>CwzjT=Do{M7HW7IYs>`%&S+{y%QS6T3yrh`%9@fMds<+IGC?t!ElnLQyC59A+B4gBbfEG!H0^Bd z023GOys5c)eS5pm&C&or(CRq3x&XiW06#!7F7EOGzZC&~FoUY_;#IFzKp5Z) z7z2C(Wq>c>4Dbb{0lt7Wz!%U4_yS(7tZhy0oBjGkKfgZF&#zDP^Xn7+{Q5*czdq5= zuTS&?d?o9eo7*yLo3?DutZnINhv@@(2)dN$y&dZ_yIa;_>mnaf2hxWUSl`_2h@?d% zsv0mc!ENxypfsqBP@a^=mYoCyKu{Vx)^BXty2XLi-n4FqqD51tgai%=zIa_*Q)cbX z4Nhl}BECJ-0u7cs3|c(qA!OS#(4=8ju%W5F0~&6}`W-uVZtKYGSii1i$NFYy5ydUd zP0gFuXX;Q%fNg^0JvuA#dSNG}d0;Cp^GZm~c@t{S>}~=~6^_{YCQp~A1ksl?=A9ci9E0oqLS9|l8b(vPszbil;nuDahqp1UWDk{1Y3wvT&az}0GGWIbZpJ+Y+s+**1EGDuq0aBch*5K2NMCH zT)S}?X*Uil?4|@cw9zeVF-831);v@%kKXMtA)j^i03p7AxGVVkn7mm(bS3^H`E*^ zp?F6NB|Fx`gs%fyyqqQ_5w>hYX-ShRQj#N0bhNas-;rruzY)@355v%e9lJ6cwry<6 zY~2PyqCF^7AtA|2I?G*+Mdf5#+yG>_7y zl7|NdMn^`6vx5eEr58cSTBY}65|V{AE3c0hvE$TWE@)TwtOGD?x!>)y`fXedRn(IkrCK-GmEJ0nx*wmUSEoL^;l?2&n=&%S zVQ5mh{t?*O+ay+>dJpGw23z4x-xoDB)h;8K0xfidU4jM-w$Ymq71UGm|0U%kMlWjT zD6}Hb<&lA|<}9qQf$3lBub6Qb4y`0XaX@_9+4IK^+^2bnI@R^k@g|I+pf(I+P0C#g zw2e_6F$7C6K#lJKU{rGLr_VOP%)RA>U>O^z@v&k2a`T4RXY|+*EMo&TJ~oVW-n@X7 z(m;)uhB4494Xl&~YP>Xzj$UbCr8H3Er5kl=V5KxrLZ z2Ye}kppz2D8LwP4BupiDa?Cbv^2LTgCpM4)vB8|uxC)!6V-U9SabF4`;G_U#Knh@D z6P%Jbi}tqhDPJ-m zey-`PgWrZ=eb_dB=u5)2n7TlVsRJv}@^lRZg97q|`i2Gl?C_`>wtwbJ!ZnV%K;x+M z83*!?>I03V4ys%O=~@E@jR#rpvj*g44oC(>fGRIVvmecmW%`D*ux{OL8^6=Dt#?fX z$$(URCQ|R32$BI2zz#V6k~W;{fnW2n!}zN&PuFPb1C6GBnay_l;<$EGA80rAU1=_;0-5EO>wZ~a-7kX*PQn*N ze+GU$$=R_vzWA;wpk#m!eWtL?H3cLCB0zmp=U6K{#~AFM(8}o=$Fe}kTE=pydo6-%78n$e15~^g!L^Cyfi|%mYF!Mh;-_#sw#FCVwGWgG z$Pg@`5+@`h@XeafWpbUJ@|S7YtT1fH;CooZR7QwYE3<}T$7>E|ZwVf4#wzC3^K#Sno2L=V?09CF< zaIIlQpf#+3I@Th%)sI2rb7=5YKk`ybNCrfJ>h$K&;MO#f0TFyP-Qd;MO#f0TG}&-Oqk7cldnOl;GBULtxD}V9jF}q;}cZvDf<2 zaE$?_13>tUp}{o>DS2tG4ubj<|GfCyj$eQ_aN-~xkWVdCwU!Ths5rrP zQ0un?^iXkv?V#3g2k4>V1lvKa-wx12#R;~9TBzzc&Itx>bF#l^9+N=1Aa(dnqSj*) zNC(C7n?$Y0B#;h@<2Q*~k4YdM6vuB8wH}i|Iv@_NnQGOG9*zo;4vOP930zWDae_?( zS5EbOJSKsGLHYPi0#{R2KEWn|>!*4?9+SYppnRaJ^*A0oz}3{CIDR|8MO1|?*bZ=! zRL{p_2N)QXkKYb(4OQh6YzMehs^{ae0}Kqv2UknAIOyTzgLF_Fza8LWsfrV92e>?{ z=i{*h3=GQ0ZwI(Qs`3f816&W)^YPdL1_tHhw*y=aRrv(l0j_`Q`FQLA1B3GM+X1eL zs(ga&09Qfvd^~o5fkFBB?EqIsRX)LXfNP;zKIq}ZK{_BGTnp9XcFfkGahz949drE7r36O@(H#JT(Z>j@z@0h2IPaQmg#)g2prKG%jV(t zEfaoP*AhVqCu5|867d@fE@-Ma!G?lMn0h`QL&3nHeEf!j%bF^mU_-%$Og$fupSje<~ge!j;mXRKOy{ur7~MX6PWLZT`)lmdA{65j7|+zZv1$sVaG}8R3ekUUH8a zVPH@`elrpasB+B+>7Y1%Gs2Zog)P{Oa4l5F=CK$I49W+LB0(#q!?soAPrze7xKJ99 z04{lInWBdS6zQNiU?JY)tbMjs;!nk6P`F+ilnPkL1laV}m+8xn9HWD=kWz&|C67_z zLTXS-U>|xJJjR1-sX=l4#)C_!s@%cGgNvqmJ|5%2z@U7e3np0&rGFfb@&zWo^aVz&&Ojz!E35@{xwzMA@dRRcx-h`!6v-<2oDt} z&|vD8Lhb8uT+xArLJiRIw+3MH0qYRrXlE{I8fDkd0acF zTN-EwbxVDAAUu@b0_~t~DO9z%ws|-=g7*Z-F4uzNb9(l!d5AbckbUM+x70NcK?lU~ zFRa#i7FGov6vuBKo`uyqq=Vx4&BL>>T8DH{9KU&Z7FO$!4vOP956{AC9nwK@{N{lx zs7|#7ucp@Ff~i(Np4C(l7?h9SJUpwZb-}Btb+}-v=i{-1;MLSRTrkz+car~x%i>fM4uxa3Ws-BOh=fJ?AeEgfN0VAH@gR6QS$X#_8@*5P`p9>>#jU|%oGfH?jI);iAutDuA8`0c>6z*>iNP#nJ<;G(L7EqH;o4%bsP9e5U4MPN`qemlTL zRh3V$9pHMZo{z^4Ffb?|za8MBs>&zW4sbnH&&Oj27#Ng~-wtq5Rpk?G2e_W9=i{*h z3=GJ}zrb4OSzr}(P#nJ<;G(L74e2yopi&2i)$+M)KOE?q*D@cDJ>w}R?g@b7TE+96 z3p7@P2)AyrK9Od&^+|{`3Qs8DQ6E^3tid%&d9VPE`XtAkMBoyxdFsj`aVL^{yOF%g zC8dNRySZ+5q0zYYY3nlxJ!bB~lc zng#fF_Q>JPC>(8r+HoU6z887&9Uq-r-?P4tnf(AN5Gv8?&i4+&`7Du@b8A%gWN)VP zNVdN}mmh%&ilYpqJWEeGP?}pmvF^e2e+s6H5M6ArfnnZwKzM3K6N8LqxEYO)z^(hN z`!NSt97y1;Jk3q5@D-#^C8}$A_W8V?*^7B(&VaVkMeCf5lo+`6E9=(?^ydXl6P)$4mi4Pw?JPcaPLCK2f1QaxIr#rAmj0g z@kyZl_++7h{D{x*?l0$^$VyeB_9yxLjtV`wt~Um;gM0We7NKe#?_JGPB;@Zl)<~f zz_Tyc+jF9GbU2?G9LS3{A!ZnkCyghtsSQ2yUkmyO4l#A{H?@Bvh+ zbVAv}K&gB@S{02-95U$dgo7fWmo9AbVA-xG7~u+PuP|wYHi#i`cuRJu)W8y4HRJsQ4NU^xZbb}FV&L@p<+Y*ZV#y6fF#4R^C^JG z*Tk>H%4-sh&{cm1f7il(6_0|5S^^)alXX-l>yD_t>xKQ=DihE|D@c7m73~B++ z+)U9yIJ$+8(Wz$%fkx9wO6+o!2$u~?C1##sC63pk)w+H|hZx48_MD7Cc}LEd^865Z zyf=OnwFl!LX-}aTr@iqZpuK+5-oRO-!vI0b9~Zp=q7PGa_`-z=-sp*ekxsZ=8@|k3 z2851Nw+7RKMBg#-HX!V4{s z^Ibgt!uX3)AopUCDBUdTPn3MCS9A6p_FPQ#R_V#9oZazRR&A8KS5A9!mGUVm1Px;PwT)I2=DRz18G~AmEp< zmtx8v6y35XNKg7kO8Ubv2@stK%!n%diNf`yoV|>_9Fw~l4;7jFLai%&q1WN()Ytpwm#BYn_CBH>?1@aIr}J4Y0hpYs+hBn5mn0B$B8QA>=vRbIQs-qlQ{b%QByd(m8eS2K1I}Y z&Tb>>BF=6nY9?oQ5LLz5r-_=y*=LBF&Dm#(n#vY=ZRX#*%ydf%-I)-s^RQQ zMAdS3CsFmBeVM4`oPC9;2F~sxY9(i1B??UWYeZen+1H6$!`U~8YU1phL^X5vEuz+Q z_HCjza`qjfS~&YIQJXpY9#L(aeV?eUoc(~P?VSCPsCLeNMAS~s?j~wCXFn!tFK0g? zYCmW95Ot8VpAwbf>|Ua>oc)ZbPR@Q#RF1Rzi0a|&exiCgdw{58oc)5RKF%H_YJjs} z5;erxLqv^m_A8>sIQunGCpdeUs8gK%hNx>f`z=w|arQf+uIKC#qMps!?}>UYXMZ5- z`JDZcs26hfC!$`=*`JAeDQABn>gAmMm8e&6_BWzl#o6D9dJSj)AnJ9T{gbFSaP}xs zZ{qAMHwAUCEH^$<5^5cO+rTtw7wxN$L2zvISCqJGbf zONja-H>!yGGdC_J>aX0GMbzK9QBBl8xiOole{o|DQIBzBE>VwjV;)gYa$`PGPjO>` zpb`c*77}H0V-ZntZY(A$!Hp$ECAm>URGJ%0i7MtsEm5W1s3WS38}&q0aAO%!len>* zs43i7K~yC-8i<Jp%W^!W{QB~YnP1G!ITt?JvZd^{(Ty9)J)O;(z!P}jAS;Ow&qy0^HK+^i5eyjzo`W}ZdLl?X%+ z_jJlT<|&y_q0k~?O8z2>S&3g4AgJz>r%Xe|+yX2NDk7xjzkNPDQE@jhUP>QH%qjBO zAd1xR3i}AD;m!6D#PGuVNMcTEfmIKBaWxlcYTB*&lwnnnhDi=C(Lo#Tjz4VTJ>4V{G%Wkxc{qol`;q_&o)w&W6@uh~ zhE&gE5hN7UtNP!NI0ruW(*1MbQ+M&710UTzPC{qZF#d{sE)g|JIcp`juUSx9LBlOQ zTp=I1AhDqF%6Z?SWgW=`O`jYYy#Jh}0xPKvU)2yVWsuO405dzw0~!<|s2K7sh&u7E z28jh#z7$i>ZIEP;&3PrAnZvo{oT)=l$K_3r>P0LdodcwJ%7Z`#b)8P4o)7hE+6nSA<1Lnfbo(U8ffUo>R$ z=@$)|eELO0KAyay=lpmYFC6mmG+sF5<7vFG)Nf$t<*^0A9P;rrKIM>)r}4reA5Y_j zLq49o!uUN9^6}&sjcC7^YDD`*(TMhoq7m&EMI+iTibk|w6b;eqxaX3nU${76E&^{G z;VVic5Y(mN<45$M5Xl5}X^u>Im*z;}kSPX;pne~Pu-m5>nn*5ap68SE%wU6t0F;*R zIZ={9W0MeapLrs|pl)~E>rW&aq&@dhD3S@9Noa3Hkyy}LpYw!NctYxBsc=l*;qYvk zxkKIAP`l4jiTVucmI7X_B4k08uRmr*azP`pdgF>jf@<9J^wrrl;l7AC-D zM~?Ehk8?&o;o;j|6P}DECB{ zFUfPZk!`|Y*!F?PUYyj$7EaDu*i{(#Q_eOM^)uRI;)rRl$1n86cLRdokLRqFwPDf^ zaJH4G2RYkD)I+#U&Bb!IwA|ap@x6G?wo~kfIcq1dzvZlhs7E;4Nz@-W+eOr$INMFs zUpU)C)ZaMUOVmF&+eg%+ob4y--*Ur_JavYr8^jq4$ol|0h^2X)v#Uw=NzO7vJ;m7} zLD}$=aF!^Ov%^HiIqM`U!C4nkNzQUar8(;+s+hALqDnbCLR1-Ny+l=Tc9f_|oE;-- z3TJtuDmm*TYC32AL|w$$08ukJ8zicVvmv5paW+iUY|ciAn#@~HwLeQjc1qj_VjuSl^g z@Xsv#(};go!N~{f8op?Ru${P?&O1(UTHTIZ&lWh5QJt`N zf|^vDb-Y)@Q+D?5q`k}D14fv*2NedV^HlV~Z0E6T4?K@&!$Wm$bjMpnzdC6jv@-^q z4ST9o298Ac@IW8zsO}hOg~tcs9YUy=$#ymcG2j%Zv6I_fm}!L#8`9=Dm{oT*GB7sW znd|NE9;j&-WNU9fR7;P|lDLu5^L(3p6|V(%bwRZrP1#3m*pfTbNpk(k!F+FL?`Sh@ zBkj%SwhoTMYc(TKEI7qpr9huWN|bUSY4_W(wYCVe>Vz%gD?Ao?mWX<8^5s8!*d9qi zT98EE-C(;8&J4M`;&txq`e*^wxUux?JUetna_}^weLMv<4f}w(qZc%rgnbG&%qhd` z>mAAFdwcrfoQ5(!=$6PfPQxxzB`F@{fa76fBRRBC=&?xXdf1Vzg!*$QFz7G^J;xse zjl7eBp6?H;hfaxtUgQs227MC+z0@DH9J)6O`agfr3h3`B=vDrp2I%%E2)6X<;2UAI zNZf}F1Ge&(JBo7$nuPr(IP-P5cN8{Zd%HSPy8RaWtttD>_S?W3HC_;T-IDhxYVw$WCtdlzyW1d?IPz zV#9IlRBs)JI^ONZ6l-$%j){db>#2a2h+^ zHIT`UU}3g)Yo|TVOUtuAZ+{_WUt`1mU|(H;`EMf)e|cP3{Wu>O2VGNuUI9mih3?4Z zJXqP%e|(@bi#=RNb{O6fU4ODOCpx@@{dGveQ43A$681M?n=wdwUE}titcMf1EOg?Vm_w*u&7y zc{fWnOt0qlPwjhC_BU*paH@`NEwsmkeIF!%HBB$bZugv{f7*R2&1CEc>|dnp`|Sr| zFoVii>=}~ISsSaN9S^~!k`Pa?)jDpBkd}V~$<|3Ra9!g8__ffj8YfBa4W*OA;`K@N;a$bmaubs8h$rq(VPgffG}vNs>44&+g9zM?l@&W-0#dXITDjx8r) zKMpx8mpOpzA{H@MaO3$RW|D#23MmJ!Pp*L*FCw|P!FG6096#-PqpubFfn);eEolP` zm_G`Ifa`j0jAD?3yE23vxIVd+-1t9|D+f93pRr!S)#d7za^p25HwDf`;$2Eb z!T^BqNkY}WktAoJB$x@#3@Z`bG%m{(LL_o6&}YZwrx$}^W%)d81P4v*$*WQ^p2 zh;w9>z^a+?_r_BslRrNk#I6h^T|fr*`6MwZR{i{;JMInRR-uKO8)$0@_ES@aO3^d(ZKvZ zDJEn%s2XgW3$Rc~DoYxslP^iW6ubMEapS|3C43x|desiE6(^FfgjxqeJc5jmns)Kz ztD(nCzAE_|ZhVX)z7DF|iRgK#IFWnjog24ODQ@t8%53P(=b^gbW5d1FKva4p`;0K==38=p6EFL{Q>&fY-T^wr5$s3a&hPia|CYyD@>KzSeH`{C{EZ`Ay zi_La%<8y@aRw!tGAlsD@cX%H@HJBY4!Fs(7zMPVy$=g%OMQ9awlJsYw4)NJ@&6QOCN1EAJ55h}hJo#r**k5e657uHy;_o)w&yDYr0&!uM zy#JlDpTK^q)KOjAK-X9vR=AQdbuCkhlfFW2PbQO3B>&6pw#0v+j#I3(C}m7Y{KsUB zCGd{{Hb$Sp?YZGzSUkB#EFY$d;An^Y!9w3fHLcmc!(G|7+-SBt+X=JoQ!o#OJ~Eph z_4pa=1>T`sMg@T*16`Zowwioyq`Gxr;MmyU>ha^b$485ZU%RUVt8pC2=4?LS4hwdx zc`B7kr&7rjheE?77*Fm}Q8$eBiz;6VD%zYXEoVk*g1Dr`AFNdRv^#*@$wAO>U#@>N zo3B}$9m!E8!3W?2sq$3viByHn4#4_4Rnuf#QeDN39|#LbReDBradSczpsKwm)Cs8%rc#J5R zSO1r&dLA=~TFzq@Q4KtnAZjI#rHES1W5q;W&SPant>LjrL^bhPB~i^hb`eqQd8~@4 zjXXA+s1_buK-6ZNb=eH22i-P$TZYn;r8E1}Az)j|lZtCsI4TgMk}>Z6dWh znc9`w!()pn>3!VZVYg%JH~@xna6;l9F?AWg$mF*UG@e7{5D(^Np1wieZQ+*=nyNwq zohbkVMa%P89pUNW_O*nk7w{Y{XJ#sEvpybMPT~FBK11Py5I$7SEDZ1Gu|^6XV^>h%b9k(osORz6CZb-zV{Jsi zbf*Ny%d!6K@TpAoVYq*br^E#1n$$~qYzGOwoX2((^$NT~s4vS?uM%B<>eW1UfI?mi zr}g4HQR}bgu?+dW5q|t31Aa67_(RlNd8~^<-_Bz_MBTt+M~QkDjDeVOAF=O+p0zs* zx0677<*D~mo*%$*5(+;^GB@%Vtx%+H;<4l8_fZ}@MbyW5>@-ogz{IY%AJW1Lo_Ok$ z0LQ)|bt{iuPvN)0xF(h!c6x4_ z(s+~lQtD2q?$nogjMghscj4t3V2-d7#ZzA+Fkj~}TBS&R6K&&V@S_~*`#U^F>jtUs z@puIZ|A5D6jUe?S9-~!&)Q{mOJBo1+{ESD`y*x%={;8ky*jq?V_oMbf({CsCL2kd0 zOz$Buys8MmM(`nOjqz2jTh-jJa#u> zox)@H5LL-zKO<^7kAEcoQD}MTi?D9)=CS)J;1X`#Zryl6fceuHGLnsb}Nq z>hx@sn!{rcQOtP;Yx7Kw=+;d&cz_g*^5!<*}H@ zen(Udw_h*nGhJI+l&&jh9P9H>6bQr8Ux{kq_IpTdC5WvmXT>P?4+?})>0d;x;r0he ztO>-{ma`HNW36IkI}Ph1MPvOV@RJfxZxpROy-BotSc~E5tH@_FkNtC9zL|*lp#k9L4rh;HSMd*#&FiJpEZRpU-iV#_KeUUKQA{^$h2- zu-@vpJpCo{{gS@ZX2aa1fjoT|?5hw%Li%gmJWQFu7o}%`q7FV})8E2OUX}i~%|^JH zBeCys^9WHtfGru6$d7C`%FScs{S$6~jY{%UD9OF$tO85YPl5Mw`(X-v00Mte&L-mI ztXOu)UA@PlQ|9T1sKfk~&A?iRC?LmmL?6^ zJkIT>gcwhNm|e~)QH(}x4!dQ>p#8BJhutzQLPflkn>1|mGH%jf%`14)qC_S^B9qJ6 zG)&}G0y2lqGAAgJ>9FgG61j+*ucy$N+Wa~?)V_)DFuxV&KEVWg|UIxaq}ihe;GG#CTayYZy~CYo3voW zS8q;nAQ#qS~#iFsEuj3|-^?UciZ+lBkbxtC^^q zxwV0)k8^7?QJ>(}7NTzD)^?(9<5mYzcW`SrQJ>+~KB7Lyt%F2;fm?@&`VzM~iTX0^ zOQW*g#jS4g`x>`;iTVb&@=pjOE!ln_g=tnk*WWXGg!6yHS7GuB{uo?nV{=&7 zO5yK8upgtl_ayF1^sEp$zX9#y{7L>__{oPq1;6YM4#3*q=-6<-{I$zqyS$O)Pxq?( zQFDmUU#4JH&s}JeN$_H$I0jIQP5fmMe)OYX7J-Q2(<;OP5yJ;mhyx;q&!G?pL<}D~ zAr6QbK4C%}5HWm}L~uyN@Qo4TfQaEsBE$g^!*@Z510sg6e-MXQ@GTGG5DUK2K^$Vi zw>XGHEcmhpafk)q&ma!5;L8|-Ln4OnTo8v?@C6Iv5DUIjK^$Vi7bu8BEcl)Tafk(9 zjUW!O;2RLcAr^e;fjGp1?=}#JSnzcQ!66aDw-$&)Ecj$Cafk&Upd}8m;4`ztAr^cz zmN>+MPs0+2Snxqt;t&fy+e#c_!ADq$LoE2bs^E}_;UlWVAr^cRl{mzL51$f;SnwHB z;t&fyNJ<=H!DmN_LoE1+C~=4dp9&=ovEaj>#32@Z!BcQZ#PFR?;t&hIx=9>j!M8Pu zLo9fsFmZ?l-@qgevEWOW#32@Zw~{!-g0E8&hgk4kN#YO-z8EPuBx3k3ByorZUwI@B zvEXBk#32@Zl94#Xf)6Ybhgk3#MdA<(K8i>jV!@XUi9;;-ej#y)1z#f+91<~nXOK9= zg6{DXh(j#+{vL6N1z*`C4zb{ydBhzTh(j#+fE;m%1)qr{4zb{)Z^R*%l@1mpV)!Z>g&`JvdyP26f-k8N2ZULR zFQ_GG7Y9(l0}9Cl1w7!8JW#*`63GJvJYbPLP{0Ek$pZyE;E_B~zyl)50|h)_k~~nr z11iZ2e7MVmc%;l)+)E;Pfe&|#NM7K>?H!UA_^?x!yugRuvg8Fm?3g7l@L|_1d4Uf* zXUPkE*gZ>L;KP2Ic%;l)?4l(v@L?w{d4UhRX~_$G*ilPf;KQz3@&X@r){+a!|q)20v~qhk{9@}OP9RBhn>3Q z1wQQ7B`@${$1Zt+54(2B3w+q86OWWxi`~2A1wQQHB`@${7cY5%4?B6u3w+qkOJ3l^ zj$ZNtA9nSU7x=KVm%PA--M!=mKJ4d-N6M_lE?@EjA9nhZ7x=K-m%PA-9lzuSKJ5A> zFYsaKFL{9vyMM_Gd^i9|Uf{zaK=J|~_Wi^oW!B;_AbEig2Lj0pd^i+HUf{#QK=J|~ z4hNDK_;5gwyugP;g5(80926uk@Zqo^d4Uhd1LBb~YjJ3hyugQpgX9H193CVu@ZkU< zd4Ugy2+0e4I7mod;KN};@&X?Y6p|PCaHx>Hz=vZ5@kp7qI9y0x;KKn!@&X?Y8Il+H zaL|yvz=y+zt9`#qJ#t%UOukaxSyuybR@CqMNz$<)6nc}HIN?(j0b!z+&6of1NAqBkBA5y?8 z{UHUs(jQX5D||=+ukaxSyuybR@CqMNrg#F6@QLw5JZ~p?p+7Z#)FB1(3LjFyD||=+ zukaxSyuybR@CqMNz$<)60k7~OWs0ZS2#**)>eTolsM7uFBTuXwB}%>xYnattxe>Y3 zAxHZeU}tB8_X|;OJaG0yK=o1i5>Cn%-!(;uU@aw+ZA+gTQB2n^vgS{po`Dc1V zgtlFR_E~6%Ww^UL!q`yq!&J!+N`6#YRB|``&XX6LJ3P>N$xlkYSI#aixd(m;ZHJ#g zvhY<6KUrGM;;onBcHEHKmL2TC9V58G5DqwP8S6Wo8rP4KpswKige&?rf}h8rf}h0rf}g@rf}g* zrf}gzrf}grrf}gjrf}iRrEuZIrEuZArEm{P7tUG=9!^>c7tUD<7fx9U7tUA;7fx6T z7tU7-7fx3S7tU4+7fx0R7tU1*7fw|Q7tT})7fw_P7tT`(7fw?O7tT@&7fwwR&2*QQ;3xo@A z4hR<>2@oz^=`UQki(j~Kk-l)@3Vh+h-SxtSOXr0Pcg2HSju)v5_f67$vvl7g-M32j zZPIIVA>Ap+4@0RX+r2Ag!zE8UEm+l9o`$6e`NV+#l_rub?NxC1A?nkA2 zvvfZu-H%K67U_OMx}TKpt3&YSpO@|zr29qbeo4A_ zO83js{fcz&lI~Zf`!(r)UAo_p?l-0TE$Mz+y5EuRccuG1>3(0jKalPZrTZi4-Ywl9 zOZO+zy+^t~mF~UL{h4%sF5Ua2d%tuaknS&}`=E4xDcy&p`zz`GTDlKQ_czl0t#p4U z-AAPRd+Gi`x_^}JpQQU|>HbB!f0gdvr2BX2{zJO|lLAqtq zEthVEbSFx8l5{6acZzhUO1DzF)1*6Hx-+DEk#sMX?o8=kBHb$KUMk&L(yf;6Z0XLC z?p*24lkR-!E|Bg*=`ND)V(BiCZjE%8O1D=z~X z!{19Fw6RVKlJ`017sDMFlnX^g$h0piYE= zIvE|*HHCnBP}9`43e@Q^Q1IhWR83v~^g%sKfqHfrDEKKnDyV{N>LE>2&sCtF7X}J` zm5&Olpz8aT2I>V0)C0iahzhD8n|fFS^)dzO+tZFi^0MGAgLo6$0uJ4bX{>YZVrV7E(DO}(cOP=C@uy;p&HUl=I(i9IT)4;BKdQv>xO z1?t8yP#=yC>LX7d)JGMlo5MhTEIO!Lo<68gC{Uja0|on)qE_E+g@EePs_%9M>W(l_ zpN!+AZnLT&?IkI1NA)x z>ic1!U^`<}P(Lc9^_|c_-K{|VI1JQJE-0vb6sVtufx0(3sGk?2sZ*M!?o*)d4+Hf; zbWjD^)HNEYUno!yhJpHJbWjELQ`c&s9#Wuw6$a|p7ZlXP3e<1HK>ap4s7DI1sneRK zey>3NAq>d`_#ozX!3OM&`# z7%15D9aU407Xs>f4b&3~)RSSL{(C_|J>`Iku@F#r`Z=nm3R+8emRD1;m;z;nfwC?r zsJH@E6b3309aKSU3D4FvWh+q0Fi>z*A!_wK1EA6h6b}OhrzRqTij@@7`ktd{s#JlR z5C*C&I;iqOKs{FjRiQvl32IqiVA9OA)sEQftsg4%?|^$ z;DUl$s6Z_W1GP9hsG34F^;%6+OBJZvFi>^p8Pw}EQ1uGbvM^A~&oijkYoJyrPz_M{lD@-R?WL0(Es5s7!QF*+Q!C9a`%(e!LjRJLT7^u_HK^0_E z@6>GSItA)X7^v%`gDOZ-W=9X!Tl;xK^0`^I;giQ zP;UzZ1y{X91$9Fq)8Y4P)%Q*X>Rn-=-hG}yeLw^C9tG;XVW8f3oH}e* zK6su%eMkePHVVeVHVWc(o#)l2Zqz{Cq%`%BFim|lI;f8oV(1^!Kz&?+x+M(MC!&M8 z_34B9lmc~I7^vGXD5yIWs85H1g6rO*+SD_ksn042ENr77UbK5&t4{}|HVVeVHVWdMzvmUyEt;m(M!{IvMnSxOI4Y=u z`l(N9pwvdeSlC8EypK2{DC3$!Z0c4G)DM-R|0vAR?~V*AR#2DlDGk(*6{w$tfx0I; zsDi3b2lZ10>fSI=KZ_2kps$(RG)?_nfx0gY)cw&x{h|acd)I-rh74#dj z4(eA5)UU%pJscfWLDhG=R(-!wpne+$>UYsW{l1Xu(?R_~f%;<@s6RyqRgk9c&@}aD z1?n$hp#B;iR6&~3LH$jE`g<6te?$jW&}aLnHBJ3ffqFCy)W4#GDo9g0sDCR^kA;Ey zPh?O=K_`s9plRxH1?q_~P*0v`P+!tO{a1l{Dg+c>avyb;P>`nX^nx-C2b38L17)6P zP+!(SSqfA<3{=s12K5yUR6>EW!$2j^GpM^XP$>l}9R`Y@XHZ|&Kou)cC1IdSqk}5w zjKlXdP!klWvM^BP(Loh-zE20G_Ia9N`#kaCh=^T+Ii-+Uf(~k`(o|)brlv&(WfW9> z-`A>7?ejFl_IcuS8WA;B*w@StG*A~SP0b9`)FqKY6{e{lX`reUs7u2@&58`FFq_gr zRVz@l!$8f63@TR8QjiX6t^zeL4AlI{pq>d$El{8qhJjiX8B}5ODP2>G6{sa)plYIn zDyU1iTQhXEBi0Pt5sS~%MC}p^vMC*u+7WAp?TEz}b0UH&tV_^AsU5Lq*p66yyeA^4 z!aC0%Yt^TA#F}9{V(}fJsGtg}J{^?W5o?C+h{Y$3qJk=D(M$)mMzy{x!&)D_u5?~O z-J@0CS_P^(4Ai>lplS-4y6B+RD^MH4Ky8c;s-PdXf2wI}lLFNe2I{Klpl&EcQ#vTM zci0TuJB$x(omZQ>SJTuMrKzo9nu52!B7!msI&iOp+O9zD2m{p~8C0wwoBElisSX8d zXBenm(Loio6r_XNtw8Mw1GP6YsKTZ$_i36^yR6NyUDo)nTU47WXw^jrrFL1HVY{sH z{kZcA>V8dAhg9`t!>aFabWjD|>!O3|RG_-TK;@!?Drn~UfTpQ#1*#_u)RE|*3euDg zs#k$J8V2fEWKgk!2IOC8no_q^ntfrQ`Y$M`0i~(IFi`NSSj5&BD`-I0ZmBef6{wLg zQ1HOn1q3ywKphVQ1#hiI1ZAEoWa{!u&8E~YYcp(@H9j^O5maHnwm+nSQoF3puwB;p z?qx(!g|$8%l-gx&hV8P(_co(~DriUSuQW}mUDjsUE^B=HGb*TpTAvO|?Xot*c3I<- zqY*(F1>NWQYfV#Xm$ezT%Nk!gjS8xuZ6!J=waeNJ+hvW9u0{k^n4#;SUZMJ_SBCXd zuZj%Hd`%(!ly)7f`C0|)bzz`h9~o4vpw_2@dV>P>#xPKCiVmuv)~ADdvjX*&Fi>xe z49Y0zrmo*;t?z9L)Z4>Ay(2oPf@YpNs2dchcZPv_S7cCTLD#YBpwxA&X4rMC_zrT^ zF5wr2v_2iw2b88h7^bNYMF&;TRwW(OjSAF8B}4z%x^VA|A+$h(J)Z(q;%Bk zD`?GA2lX)p>f>RcZix=6Ae+)bsf%mPu#0Q)q3x)eD#)gEP-;KA8MYrC-~5gU$|z{7 zl6LF2srI9rVf)eX`SFOL3Y#V9pwxbJGi*OPK6@S!lv&U(4%$`ZrrM8ghV4hk7uX|$ zD(qua2lW-z`tAyAeP4|X$|&e6a_xR}^J@y!*TX=4BQmJMY)S|9O$F*(VW7Sp8I<|m zLdHJr(sonrM>oUvqnpw9qZejVIw-Xt-3;50ZbsjaZWJ_i`J*=Wsr~3?*nV{Lf7p*+ z(4v_RO6^BC!}g<_|HFRtg68Pjo%^QRk8XzTM>nJIM>h)^kpHYzpW2UZhV4f;qwhyA z%%*fuYCpOewjbU6ANHd^1DaC%(ao^^=;r^hAHATdi>|3hROk8ou+H-j(L2vS71DYB zO|vPrAKeVwk8Vcak8b|`>4W-*($qi0H1%j?O%?V8)ju>%{Y!!RcNnP0B7=$*bk)+X!dLlZgf_|>mK|QHJ{WlEMQx_7H#T-zU5dzAJT~JV_0%e7Pibn=zB?@VM zTJ>4B0+kE{m5L0iuq^;OsI&sb!$1{B24$5NqN#s*Tc4$NSzBSdtgYy~tgVSpAJinJ zsmWoQni5%4g?-KFno_&0t*~9zR`gxgh3(1HL8)EVR@g3UEBY>Lqo5zQbx>-TwH3C@ z+KRr*+A8Qa-N!XUpQUW7I?SeKN4BZLW(iMdpynu0bHhN*iwvr;>ie$-YQ6%sAPm&P z$e;@AJatfu6sW~vpq5-vP&EqF(lAi9=NZ&fTJ_Z_Q1xM;mR(R#%N3{29?k>b+rPO2?KTL zf`ZB_P=~`nb)IKXwx+2r1u7Q?syi~Mf|jfeu7T=NppJxr>WvJlpv8S3sG|zhu`p2i z$e^tLLdHH_Qv(XrU>K;O$e;@P?lX$D>Qj4%t+2hrR`k8Y1%3A!B^oHTci0NsJ8VVY zJ6zBLhY!?AReh(zs_&Y})%Q$*x>kWY9R}*U^9-s~tG+V|)b(MYo^?S%JzIf#P8g`? zo@Y=KG)+BEfqH%zs25yNP%l)VUK9rE#pfARnWm|iC{QmA1NE{C3hLzw)c=Kndc}DL zRjz63l?v3W!a%(`GN{77`zkb0uTh|08wToikwF#q-KT?6cUfCucUfEK`7Uci2c_<^ zw!-eRw*H5^tPA-O(wL}KpSsK13cJhN`XBDHeg;6jL)p{~VK(*7^K4U-G)=urfqHis zsP|k@P->U86}HRT`X6>#7gT+dHBG5q)>haqYwLg5W&I3*QoF3JuwB+x^j+44^;1(c zO{rbhR>&@E!@Ak}nB3>NipAhR#)=k9zsO+tlO!r-E~cTM=`JGbe|* z;mHBKCx8bujCedyEpa6_A-pb{(G}id1ZZ z-~2o%;+NqiAdU?@N>2C7Jasw|4n13>fP-vaoz5dJNK ze~SgcWx*EO7z}K@g)T>ZI2O8GB)KxaO4`o>z=CK}ROZ{_YlD+rMpCN0srY45&8awM zfND;~F9!E z=tFaBi-5^kvQ(Z;*0yF1vWdsiAe)w2#Ik9rO~#g*VN618Lc(x6YkLeV%L2N^%i3AI zTQV$OAa}8Lm4$sagne&u+XKU%M;Dslo&YQiVy)dU0o-9>yK9aEx`VATY;^75xH}JS^Cft+!4vLH2FQ$asNA)>|i<^T^}YNuK7{ z$FyV<)0MQ|`s6-r$~Rh{VTY_S;ju?qNi5EQD-(B@T%IVhSf8~{5eQCo3%&rssaGgC z-8w@cIMXdS2ZA%NP;jnwouKyZg!a2Eu3T%q8**4+ZZ zy>7wxA-MMn1v9K42n6@L1rI=Q{}l>;V*OMgc+f5Q1q2UXq2OWbm!8Ghcg9@y2J1xg(!TouZb>pnn6{3YN?T;EkbK-6 zd7hAb(j0ldkbK%4d4Z7ptvT{bLh@O26K$(PKLSBl7y#2k5*kQ`=? zyjn<(Fh_n(NRBi|eqBhmnIo?ek{#yAZwSfJ=E!df$+70hYlUQ&Ir2IoIo=%kEg?Cp zIr4fTIlDRX1|d1o964P`&S{RkQAo~hj=V`o&TEdmSxC-rj=V)kE@+OtRY)#uj=W7s zE^3bawvb%h9C^EtoMeu?Lr5-Vj=WPyE@O`Tj*wi=9C??JT)`aqT_L%WIr45HIoTX} zkC0r|9C@#hoMMi=Pe`s|j{KgGT+1B!eIdDyIdX=OT+bZ&10gxp9Qi{bxuH4oej&M$ zIr2wBauajpkA>uB=Ew(xE_6P2+1#+BmXHR&oW2;OGut$j{LWfJkK2YypX)W9QlHf z{IWUnKSJ_CbL4-84O zWQ&mera5w$ki59IkHVi-foU;7m|0H zBRhoTUFOJ6A$hksa8IaWx{Fh|ZJB!6g*>=KecGDnURk`I_8#|z1y znjznIq>Al8>4rCkn~O%#o>(eB2y4r;vQo966Ve zeA*m2w~+j;IdUE$`K&o|ULpAhbL4zN@=xZ-`Gw?P%#jNS$-kK+7Zj4unIjhxlK(VE zE-WPfZH`<-NWNf>TvSN@*BrT+kbKb`xww#g$sD z(j2+8kZdzYE+Zs6%#q6q$<%Hx|bL8?uvdbK~f{+|Ih0T#`2+2jwk!uRc#m$jx z3CT&O$WbN5ZwDT``nLn4N{JKs zAxNf(B`<~`SzRo7DFn$HLdi%Hf@DpxWLOB2wZxM6D7@J>)cs#0kE$(}j0{1tj#$zb zf@EE>q$32$dSc1w5G3o1C1XR7OchJILXd1AmW&TUvY}WqYY38QV#(|wNH!8nCWau{ zSS*<{1j#01$=o4GHWf?e4MDP*STcVIlFh}E1w)W*A(kv0f@DjvWYG{LTZtu$halNn zESVI7WE-($sSqUFiY3d0AlXhVSuO<0_F~BjAxL%*OI8X&vZGisIRwd0V#%r@NOl%W zri38bMJ!n(1j(*q$yy;ub`wk12|=>ESh8LSl0C$dsUb-A6iYS?L9&-vvQY?=uILP_bl>5G03*C3}S+d5>7KPY9C3#ghF(ki1tcIUoed5n{wmlOae>5KB%DLGm%NSn}l%B&Uca7lt7DoLF*k2$EC9l1oF7d|oWMECk7EV#yUDNWLJJTor=k zbg|@XAxO>;ORfn)@AxO>X6-)jQg5)}} z)kh5F|H>CI1dVa+6r{LI{$Z#ghMqAh|^> zc`*dZtzyYbAxLf$N=A_oB;OWGhJ_%xT`U<9g5(adWMl}EJH?W=5G3CbOFBZ3+$ENb z4ngu=v1DurlDox{t`H>mh$Z7gklZVl%o>8^KCxu>5G3CdOD2XO`My{(X9$uRV#(Yg zNPZxe%o~E_hhoY6AxQ2QOBM`4@*}Zi;SeN07E2ZlLGplDvUmuRpNJ)su3nNfh|<39 z-uDYG>!bL0+y{O+z5fqoq(y!1`L29D`3v?1`I(a&M;#WBCBN0?Z@HH^z zewsz!Y{`$f87#ZMhCk{Uev+f5P~@bE7U)D;2}Mp{nMiA)i1}ZTi#mhuv=ut^dlM}I zxt);wqd9VWA^B%>=f0!e87LxxmNA4mdpEpPDDkT47j@&Kk zU%`~UXpY=NXj$?@eTG?w2Ky@cd2bL8GavgFtQ{F~iJNRBjTxv!8c`B^}J z%l(98hdImrh2&^+RQLxk^>x;Zj=1p zrJ>obx+Kk3O+c=0!ZL}sK4qQkA@|3xb+RA(%b(P_8T+X%{Q6s#q^+cG=cJ9c+8eA- zmV9?Pi7ff(pyza+cI2enF0zti?>$-(a12%}l-|HHqJtV)LB(aYwNjN&=Eh)%6^Np^g3JTq;y-?b+%sN>9)S;l@1$z(6>^&l|H#1Xv zGc&U{US@BCz}~D(?aj)}-eWR*j|=S0&eY!Q%e1@@M^ z(lUvc<(b)gMrLn{z}|{X?XAen-g7d0&kO9W%+%h>%}s1y;B3|zP8KDarC!5bJci48 z4KEj%+~TUAiODTGljTGvS9neO<GzzBe(9|33M%#KCiSZ+92h z`0OE*uSvJ9U1v-8X7R(WuIOpHZOcyEHsD%1$3M5H+ji}=&C{J(*XWaZ{`vl}u8qA# zK6zKx#yy5M?(u8mm!{kJr7N>GewkSt_j57oB%OocW!$n<`?L%UTvSnN* zR`0(7c8Iba)a_i3^Umf+FLIJd+bP>=>~x|?Zrd5sh|hxuMWOg@W)3)O&H>}D)B(e< zw*$WSI^c(34)`%M2mEZt0Vl3B0#00y2smMgfM2{0_%)aVe#^`O=gc|a3M1fz>pDb$ z(E)#W9q?x`2mIxAfZqyrUNCb{x*7!puJO_5NnOqnu22`e_TI*n566W-Gh@#ASM2bM zg65p!ai^_T?u(C*6Uiw<82!)d#Y-M9HWMY1%bE1bZZY4h)7PU{r}e$EhiSdChX?7E zJ;K|o@3EU;WA%_>tn88EULCWB>lcVKt_P&~(QX%v>lxR;fG`VrT+bLh;P86D>G8lr zf^oG+XXb%eQy%!%HTudt@U3gmwfDfc1`lNMdcYOT194sti07+4LF@t1eEt43a0)Cqu6ad3#kjSg(qBdu3dA?ZpHM@n=D^jqC2uybbcZZ1&<_dy;va z6zD~Jshu{_JpRR1@7ialUkqL>?e$_AsTYaGR>N~MH9YBe5^s5*kYV|f-1~uz_VP)a z?3M9f3jV8+w9Z~P-JZH3>R?h*y1gN8v!-^oY_vB{w>M9)x7ciN7fyECKHL!X1^+XK zAl=@{GZ3g;dD87&)9pRe?R`8~F|Mwz{5~Jp2PD`BdPK%3xK|YbAZV~%E z>+GYp+VAhY(f&ZX{UObKcUK;r`7sIhu^#5U4N=E~GJE(lANDa%24(j2XO8nRPwSbs zg=p;~y4J#h#@3GaF~7t8h&jHPcmGSfHR0;*DgThVM5A<;Y}DqvUUxZl z8!}fvS1GwA`#SqFS2P#4Q#%)4LG3zW2X%Ob$EMqHBg;Ej{ah90!fO)jZ}{5(qo@7$ zwF&lhKKN%1UY}s!;DdkF4`+&#I(fS`Qm3w6(KOoKu6ej$#qK29?@zaH(Y01>?ha+)?HP(r>Ix=7yY%FYebNns&>7sZkduD>1l4G=yS&xnj*bjAR_N$ozK;IG zCu=sEjYsBrnoSp(*=crnWa7r@MfB+(Z3!RcN<@=9cQ5S!dSd4C7DpT*x?bavthD8h ztUGNj6CBw*Eor$S3KkqW(jAE@IcN^n7)MT;L)Vx@n#ddD$juvrb&68T&&x}x?!25d zr|&$i!4JCdU|QE;kEL8R7gxwnbLkXv)7<)QI|^zlW5gI9W{lfc&YJTs*M<^)oFE3tw*cts5NK} zFEzW58fKu@q%}D;mDbczYtdR>YEB>i{^ige^bL-RkoYjQZ*RfJ*s)wbeiw3j-Kd%{WpgXT2ZRk7CJD8INgNY59 z;d(O4yF2sJo^_SgCD#E7j^@7hI(S$8MIr)4rud6!SGHp}*rLsfJm)Xc($|t$vm#Ud zMOyhpTxLa{_ZMmH6Nwj!SOa}B&0nOAPb8~QMBvyL{6*UOM6#O|neH#r&L@)S7ICom ztg5G^(KH@!U1^#w-Wt(HJl?Q)J8~y&ar7Z1-O)e6F~BF2(;(BBHs&&eXk(pB6WYWe zGt47%k54AIL8d8f%4P1QO?5KOXfuP%eIA+neKL8`ndjGe`qZ2@=PILVbDc^H+QOhR zmaAaic_+qfS5e=@a6Amj>6&Cq+LB8?LR;!2ThUeq$;SdD=LASrPiakCbFIf|Yn@gb z+JKW`fCsynY6?dCpDcj@k!VQj*^(#F~k8PDt{KhxdV z?zB5^#7x><*N7gphrSVb<-#}0^W(_mAgbPBo^QCHhhcWij#%h;n|Hk@?a8gqr9E|4 zd(mD7tDwxse=q5+zv3z{H-3nV_oltM_$#!xPP`B8Q@9=b}q!f1T(6IzTVV@7x%N{}tC*skCFMu@MhR&-BFVKst~& zVi_H%Ys4TrD6kPL4bpLBhE&_H6>;PR>8bWL-gtS%l^3UZE&&~@xZ?-Y!Mu5|(ZRar z4WUDf&ExOMal%kKloQs_p*q4aio2$s&AK~3+(Yl-=es~U(R8#?h*^HeKQS!kTTO9?9eccH7YocjNFU^8_t6J+W*?#t1)9xRXXm%k zQ^wFSobw?aqvMRFW8EAqkq9(n>RJ*cE{u!J5?A9Og9lyRz4AD+#MN7Rw!dyq>6v!C z73oXzOI)L*XFB#{_wBj0>f5}dRUb#{?lPfWab%iQ#D2Y-axyzbxQ@Udz3!P zjeS8M)ft;WCwPrrzm z(y0c?O97Irjgrfqco1QmgV&Ey1zh>8<;$pe@v*yirO(snSv#DBKCf%XG&+s9gI!Y@ zf^IE;-#)0~3-kr97)D>vDNd);-HPt(2g4p_t*e(jlHEI#8FU60ji57hqA$`H^`e5E z$y(QgQfcG%Xl<}J;M|RvNoVp#MADhMM$DqK0vlo2m97o8;`p^9j!cy{*t0pFO=t6F z*ywCsGv-i4fwq~{=LuL}Bb78R#5nae>8ZLs@mg0doThD(*q#`+kwq5bb0PRg^_01E zE^nfP&eb(>9-ZfFq9<(iEnOFECt|pSSeMC81WlMv=kq2+)A_n4ET9Vl2g`67yUx{L z>H_0ft#bvtnDQ>Z>s%#u&SE=C%~=ljKJ_K~5^rfNeM#5Sm+8xaE%ohF-;%3h4{E#t zvOY)}(CtCj%O$=0%U9?tysa+!imt5-DMnt4J%8&PT&?5|HQdD5;A$Z~lgIwk`e@nU z8X!H}7}gtH{iJ8I{UzTu;uDibb@}U{&aC2{rfrIGr@0}H%#<58>@+t7yMJIKWP%1#&QhG;Qe>>VQiU1Ykey1bdbU1WNI4t(g%w?*H`-#-_x5J7f` zxCv-|!?G;lJxcZjdjS2-akeN{(TMwfZrWmo_=#*t-G zXE_WzM4bAr{M4)3Awu$Lsbs(oaic59eK!B?h&fF@xikoBaL>dNd zlS_WVVLz1aEQGcdW9_P*vYM{u$|dM(o$_n+HD5U3{B&n2Z+_q8_l^Kld7Zw_Rm#xU zbt-G<8m~LB5_%R)ZAbV9eS>q#(KmFQH|d+4FqDqEWbtH;%8T-Z|TlnPuCkP*9fq@MR03u1Kq&2YS9fkt#q31wv7GcMa}F+x{;q+ zhi=rJx`}Qwm`x2ZyHy{5>_)w_q32yPXJaJha9ljH^evh}79;yn4!Jx|#Q{1>LOc-xj)s_s`B>FLbu{#?ek!c9~&pP_#A5d-^*f z!|omMHg0|^-OA0krCW98x6y5S^Buf;yQF$f_XDrD>DyedD}7t1x1DY`=;xskhu;|I$<(+3l(-Pn1}C`9Pu)y@bcu^2aI8 ztlpOImbTpf5pVfB^c~*vf%F|+%XiUTL0Y~ivzB}Aafw^L$6U+z$Xo8-MZ8Pjs zWS_Z~?~}INIb4ug-ZR{^!$p=i5wTZh0}|2u($k$I1*d2DozC88!D)t9AYAzaAJud-OdX3pU(~ zaNp!awtkxYx+f=x6-YiS#qwsR!x7z*9e` zpYu~E(a&|K9-@cbr(%HI&(OZ0U-0vuq+jUHJ4_GjCEW|9;V#X=U=Q03cOMSAYRX5+ z@Vw%nOa1`Cc#V3HUtEbt-pOw4RZsbne#txbEd5f~v9IV?ykpvaLLW{CU0tLNbw1~f zgM<1VEPup_eX4tWj?g3A=JWK3&gM~iRPRjpsbABt`Kd3^uXU#$qsRQl=NtMBKW_&8 zMt9zEdR#9lxRv*LutyJu@%fy8?Sj~s#^*_&2f6Gvj?d@(#UQb!^J%XuKM!yv79+QR zPS6v)-!th6UB6G#llp$UPd!CX@l$8hQ@T@6)6;&gJVVd$^XAesy7RuJ-|8g=t~_Mg zm4{5b@{nm)9x~_3LjkU=p7I_2j(2!I{Z7~6v-GUD!``cl@9Fpa)R*Y@x>J9kKk!qv z%c;cyR~Ls}?4u&O=O37PKhht$)>8VTPU|Q7Q=r+O>CgPsW%Os=slU))3}#manEg^< z_E-8V*Lscqs?++7{^m8y@~Cz>^*jBYpS_0ut~>i2J!i1IF2M3vddr>{9R8qxaIN+9 z51rPZ^iQGXzvy55>~#8WmJ(+HY zt9H0P*?k@CE*AU50#Bm<(0{n}JM=RYa_x&Cz9}D_%6W)sd(f{#Qd_e!FYsDpc$=wS65iI9N0lM<{gN#qzkMT!b;#AA; zaV0oE_Bp7y!9kblW!|(;=w)xyvg}T=kloZmc=On%57UNcMYiwu-FNyX$bBdGhtD8n zfslop_>3JHjD!IR)A_)@)6WOr@Gnh}^z0M{x|?q=wZT@}ulZ515XG&ZWk&|hb)|Qi5(e8E+8(w^=N$iFJ5TYzx;bjzfQZ~n?+ONz>H(6 z(JX%A465-!;zdnKz#kGgiN#EUfs_?URzp)90ZlnAY)UpTvvF1C%xnhL>_D>Xn!-Ms zhg2IKi~n36ujarxIXIs+Jcogw2qe+V$AgtfeMUJG>~nZ_O z1h*vDt;~)Ly39?byt@8@de+Q9m4-xVE?g>p1paPHzUKfq^bNyL=*Yn&^5uA!#uO>S(=v4wz z$*ZSb&|&=9=v3yU+U&?cN(Pe5NuFIwbp3$k;d|lozy_rXS8c$K460RuR24Oaxw#rA zrLiLeDFsN1p(#xRn(~9NDa^OkxoUHEWKgXEq=u*|%z-sIsU6~82SwKYmko^I1LG!1z<~VU=%wt7-$8gm9G=-ERhhcyYXMy)6CX5 zvo%+FfE^iB+5lbF*XEk-=;SARWAB(NOQF>*L6uLNzvJI&!s#*^xo56Oc}NHQw#cKs$5BBkah) z=mMmRo8etpIH@cC(3O)OWk&{5Hz3{gB=@~T{yZ7^mrcL!ocb6$GEjQ}=@CG6cGf%l z?;y7wozEH1ly88%`wcd+d-CQy&W;St=>?>h*I|YWwZDVBZEC#d`?srye0k*ex`$iNr?WPq1}NoBYbcRuK(V&8p|-!pLsLT4bi@hm$s z*cb$4kk^J`2+s%E6FH{1zh%VhkMqIq3*tL#_?tE+x`1uIg zHKp$ZZs!eO{Dmip>;sXpKf?43<{Z>Bk*rb8_H^MMH1i(bg}Lm=&;_;>4fhTjzL?JE zpZ{D1VD_KkK{?y4&lk7kURb-Ax8x;uWM~On;zo#Da?x~4F8a5GkKss2kK|@w zVMhkDY~dSa7(;!$--o~6$C-=Rk%4(Xko(;Y*59IR?D0BV3m@RrCG5yR9Svl3Ahnm? z{g+%#r0#b<&E^cQ;k~cLxDvgO{vo1$Gg0&mSCnC7AmakO!(OfP&SeYXH$KFT zaxC>kEZdYk!i}tEM+PI~fs79{qK{Y@VK2^$jd&v#ol0b>$`xg7pZwi$yWiJP`3E)Z zJ|eX%{=%&|aM*9Ah}&u$rOQD+!e|^Mwm*B6`|ovjWboevAQJ-pXBZ@lnL%PZxyQJX zH`tNE$V4C$1B@8viN#`akZ@xRj?SVVBukJ_S_lToFqL5U$_L3}c91M2jyx$JPs3DV zd(X$Y1J|-6g99f4nH1?$|kxXM`~;>bjKG>G%IB_h~X&9KU`t?#qE&zsqi zq0du*ObP6><}S8VeU4MNvLgd^Dv+rGRO9Tm1_>l@iuG*@#H-wVmvL%ZT|=+fTUOIk z6NB-LT;4D>*$(@8?wz;Uk-bKe z1fEq6fvHaek-;48zsmUsbz~fQO72HVP)C{`CToxnUK*FV8F11J?!b50k->p40(mje zfre!+%FHOugwRZGm0JO?vtzbf0t(&fdSj+y9vOqXy@`?zR!*fy_^SR9`7Z8KIT~?=L4P386U7C17iV@ z1#Z8vHPXXi*QzgZ#(s8WV7v_EWgkNyN6}`lS}oD~PV%Q+{Q4Oe^0>f@aDO~TuN)KP z)jelcI7qwlXP3LL@Ronfjtnhd2xOtSC~z71j5%8R(!PuP*c>|!8`-Gk!! z>Sz6R4!cxd!kM43BLj0OkfrVhi>|lX73Zs*`Z+r?P?rH&7DzSZ_1J51y}i$GClY%V z*V~rZU{{@nod~;BUe5dc1v@hIc?FOafqm9?BJ4VHC8vJLjttaQKvo4%jR`hOkg0BZ zC$i6PCz2&t&m~J-7SqWSgJJf1n_U2}=H5BNjtt&;4ajQ&-ZAb(TxQldc9r-#H}W+* zG8kC{WKEzEL&Unw41s4Sg22>g5LYlq`>%2SLG8MVOF5V6QOaWadYfGUzrp?Y4LdUU z?@b_Y2Kvvi5s5Q1NbDkUEjMz49T|+Q1F|l_h;g38nH(gx5y5oO4^rHfTyOhNrMRmY zq&U-q6I^er7oy1Q@w*W2t;c_XKN$BqoNO+YpUxWs$C&8|2%bL#i($Uxl! zWJ@5`kTVjl$Mtr?)m(2Un7-a-m&#jtpMPXWhCXitvMsRB+A7DcBj4uKpV^Utx*f>& z0IG5JW(^WZrdK)t>+P(;E(0a2TvpRl6N6#)dV2>vu!DQ&S9WCZ&Q2gZ1H5Bg<+7Pc zpzI>?9d6`zc4RQJ3&^fOBZi30W@ZS)*W1~GIof}f^S|ECb~RUW*-Q^pR@2wp>;m{* z?!Z6Tk->qxf$R=+pkbNIZf2C&HR2v_xS0eLUbgOcm*9Hy_ga|H3aah-#of_22Z&L!wC z=yYb9TSi=TT%Nf6sN2T%iyMe~ZrrN4*HQlz z_rG{z%ZRTU-#ES*>Q(Vu2Z zo&){Okuyih9A!|?&9N#6_=(AhX^Blx4@`V0@nO_&Cccxn+m=C#(WaKJcz1NnJ z^ShiEa{gz_$d#C@M6Ob(pU5>U*IZjh?v&h3bGJY}H21jNkJ>WwY|8U~9*j?3XWra- z;kUd!^4^{As8+<$pgv z_yuYgXjPys>XQZjDDbx}qhSAnqYI9)WfaO%D1V_ssJ9mSu+Yc0j3PaX+*<_tMY|Qf zr|1aO&lP>S=ptK2vCoQ~F7}-*qjZu zUy0GErmk)mm80IX1QhMR-*o{+=X(`Dc`O9 zJ>}8P@(ataEx#W1@$$cy|I?OH!C4`91^BB%a)q=C7>^1)D%@KEIu)x_Y*eu+>eUsu zRosF4P{r>m{($;Yr7V@=Z5fsRt{hd_VaupopmK%El~FgY+@*4NTSjt9a?@mtOLG6@ z(aG>z^4jEG$?$*j(d3_#(Z4Fit5mB}19gWg1FH-{y|~I-Rnk!(sB)qT;=XEusuik2 zuj;s}&sCjf%cz!8t!XvrRohwZlWGTT87W;;hNU1bQnsahl7fF%pI&`=^;M`ptA4in zkG6~&t!oUZfq774dX42ZfY)@@EK;*L>drNX*Tg)lIko1Jn#)k1uK7>Ri?$5>q(zxp zn1{9Qtu?9EQ>fplwY%0nTSo1)+TCjRM7_NBw%X`_?eA(|tbN&*QRmS*FV>lj`nx(8 z>)_vY8`kYww+HHn>rSgX1N9emf2#YdEu&u5dd=&#LOreCtMyi({T{WkRn z)4Ss3xyDg((*@meN(@^(oIHut^)Vmsf(eNuc#ZNks?-Scxl!vz0~*0!joxeYb))09jKhL3H#Oeh_<${=Nm`R`P2iU%`a>ka?^!}z#H=TldS<|gex7#wB zIhy5bRuJ{9W~-a6L4C1#T=T59jOII_xZ82}! z?QeIo9oo@;W&7>z-$8x6{a@`b*fKig>QJsjMO#M4EFBAXEQY#C$DSSg*fKf|>hwsb z38?pXI@t-lF0ow-bt#JazAlryJZsD7x}j@E*ZsDPZu7gn+3hXV`@5a&hV!~z?w+-K z4qHa|&D}rh{)sK4N4XvidNe{kq{pK@CZc||$Ce&%+cJ92?YXAsTGR)7e&6#aTSl*Q zy`y?NY#F^f_8!(7aocBhpV#`lf%;0cgotN#7_4?_KH z|AqaR*fIt@I^e|th_?Y-27El=Q(MNs!vlXF_?st7Aud)eRGu*DIN%DrEF22!ry{@iJs@~u(>$`n3 zZ0mR86-dfW=)K+pH_N`!3pH+%7xbREnQbt7qt;FIhTbDLyB$Wa)VaxC(R=1rXp7N1 z^=<+0=sk3+v`6oy(j@g3@sj2#?V6+EEz~ZpZERa`tF=qpHiQi%jczfQ>D_iKwoSXs z=IFq0W7Hx|Zb1j?op`IZFTjz_Zc#_-op~#_(a)hZNsC+9p?as@>g^0?j|)8Wy$NY` zi+fe?+1sJ5dhgaJZEgeaY94m)ItG(=w@I6g?aoI!+(zxz+Rk=Uw_Cfl-4@A5I^AY2 z*Sr08Y&((*9yhrk_TERj+=kxQkHGEPe*GxqBi(M(QP7XX?c9e5ZBDqS#W>RAHXacD zpxo~L&`*Y)K6gNWv_7$2$eq%k@F?H=P>o5yJ7kpfBXuYBNk3Z6 z$bdU&wDco(r}axeYU9YDJ8abSBX=kEO+R|G$dEg5^t2IluhqrLusgJmT0hzPeJA%3 zcO2ZC`+Q{h9Xyo!;k?uP$#0W-Ms+k9afgqpeq`^4zUoK!MKbCx7+r0IwI%2NyQI%r zzu6LWH}%=OB-J6K@1mjBhT9$H!^uN;S>KKQFG7(LIZ=n04(eFQ201V&I`6irc4B#a_`Bq<+>BPlSNrmAR? zMw33Gl%M1g#t#KE{-v>hY2oI6$9Di(rTmqtzcin* z_c)cmf=^NAEB0R`d&d($7-DnZU~_*Yx;1%Cg`25x(}$e$nYobTq2~)bED4U>Jlyb7 zdQGxMMV{%%)1uG4NR%XRD&Jj^?==6h1w;An3TCfo@zB53U7xH|(Ransr$wN91{Wdg zl@G7VhngSROjbU;@|n#1$Nu9FT|J-Es87;WG+uQyY7yz4*#*fa<;#$Ksri%5aOKOZ zpW(iljtf7}OfPXKylMP8*>aanG4n4b>nD%$lFV<+OZc^I_s?dJCfigvNj#(}$e$oWya$kn;<>y(;V^-jju$KJ=9L zB+iqDo<97-!pVCo{3IR>7Jga?YIj~Ulozkki<&3dJy+#Li4%iPW-U(fq?CUZAN%6H z#^gg4krHQW{>rS@?mQ_^N*rk_Dw&u0Pu+Rm2}W=ZBOj^Yl=w8Wpw$0e3sB`vi8D{pN+Qei9cuI8+(skP8m-jz7_szaBJ27epS^FBmA za#%&M#K~6^xq6Nk#md7H2Zt2J%+nFb+1D(z z*(m7~cRq4lMYzQ2p+vNZt3|o;xWwVtG|Jfs`0cxYB_~y|OMEX1*ibPo;FZ@UPQT^> z&qhqQdpWJbUE=vrLtDnzLSA`Z;`r+l@@zDWyP9uRr}U*i1h7X57W z{B}EM$yqfCB;#-`f<2f9n+Vzy;~&&0+@w)pBc!DyH42hJxUMNlnCLLxl#3*R2VzSrUr za!E}t$(Y^D3FU8Fn_z0RB!hL!OfWWbk-kah`~1>$3%-#DUy2a=*MQ$F4Vmjh$8T1T zWOm)t&8bFAILc##hUM{sNT2m ziKrGi!7yrGyVYuK?x~Rz3>t@SwGq?Wqb+)#XO)#KeB-GmpI{s{m)(lBHUZV>2?p+# zo`5Wxv_%kKQ{kD1BP}+y`IHRhtvLVmZPMnV8bQeb-jW+p{RjpuiVigyC1a^~+pT)6 zO-MD0l0m%XCnSq3(IOeG=A~pvZ`HZz-!5%#s*#iocD3B0|KwC-OT3z?l7ZFybvxDi9Gq2+ z>>V_+`dq9=Rx+@+T`tygi!mo>S2I^Kz?#2q$J&>hD_RoO2;YGttk2PEge3!f+vaF3 z=S1?K>N^(Yc@f3^h4If?a;hmU8F9^Vw{xvs2CGq)4DxM1tyy&1JyV}R8od+TGPNKyCq zrdSHA87~=p{Y<%&j5GoQRfpB+Zh=7}kWmIO6 z1jL<~1!R5FvV)2SNif_s*?~of-%ZC3mU1ddNa8{^q3%>%OB5<1Bmr?(B?=bhfj1}H zSt_V}AqkH=H7^9~mzFbBR7is2uFDxbS|m3s>RT$Q>>&x1V6*H_{u|36+V^rKtLRYC z5s)#pHAY2;Bsc;*b|>cx|GpVNn_g9A5J`~u`|WP~w|<>TQBk6zM4C0V^+rXBBuJ#5 zyPI-~aowq*GKwTv?xvUs)>r-dQ%gmQik3{XsJ0HNXpsa;Q2V1_m+GmgQBh+$t7_|$iW*7KnD%6-bNF`R8`r5+m2o7&b32Xcjcluay=thU zM@7#SXIX9CQqdy`o-6j~jhz2C+m?R)YHewxGLR&QZuU6c>h`rPq#{TXKq?F24a{Is z?Ds=O4J=JmGLpnnFgL2dxx-9LNGggXK@@Z{swi?tk(QJ^-)L3D(o7{KNj#~L3BJB* z{?QVXiX=%Osl=4YPDzU-?Wb2+a&mv^RuM}Jm7gSGrFl)&ndd1jN2zF%1e3~9CUX>< zZILV|*<10i1sxmZ`ChPg764(l^JJ8TM(FtM?3J6*b}e10h?2$L%@~#2*{01uW%<6M zsG6mXN?ejSyPb#pX0@FqFZU+~i&)yJ$WoDYP4|}C(x@U!5?I&N+cztR+zh+eyIU{l%c8f7;Yb@(dli|paJC&^8;^ioMq5_kGZs*bNLsfqlh zB{~&xl7Lf*?iwaK7J>Th+!#wAmFXmbCz`Da3oYYm*-k~BB#mAEN$}n95s~GJI}!Ij7wc#lq|%=x0`J6u zzm@u=r9c&dk^odG@H$+2=w|?a0}XF&;!{{l5R3T11POT zy1P@T=i`9iSsqeZR1&Cqzp3Nvdr2hnua-$wgh~QbWzw6NNm<15Y--q(j#b%I60D*b zuCN=MRke(&qEr&3Dx==yjLI@XB!AAS-=#%EnE!>VYN1gpxhw@8L%*+H<4t!SB`60Ib5RYJY- z2{o9{wPdRzRuZr(+1^6QmPK;lwsxY*wvyltHuKfrZcZlFGOmhRNzkf{dy8dUmMH|= z+)9>7D)CBUSS8n+lUy_NyOw-aLg5 z6~&SuR_XW_y{yyEI9%f4H@uLNy`S2dqO!6ip!I%J$2aeCE;HY2nOQ}$B#>2Rz6~-n zi*lZw4W9yhHHs#?~^lie^bLs|m*_`W1%H$715G_R>}G{O4cmm{kPSfEYnrCmISw%457}swKBSvu~k${f?8$l z+bm6g)sB8wpmb-D|8V+6^&OP zjaTA3ng2yN(+%gp-Z3f4cJMMOVp*UvugFmEOGmH! zC+H?=AH*tRd08c4NgQhvUe(ukGa+%m5Y~@{mWWjZ3ta_J?=5wF{i0are-W-92iz0G zuY|ahG2ZRRrucQsLY0q2Zd1{G!)CL@{X$qD&Fomq$tsG4?ov^FTST!wFOTJUd5C4P z%FB|F_Rj(8-`8iSA#uMD7L5VR&F=4~D{Wb-qFLxSwPzMZ&h@|~?ia!```T_pMYGUt z0A-$2__fW^GXINkneW}V=Dgoqw@jsIk@r+k->^w7ala6j1vSI9G_4|9=sFeAw_QZL zFA(+LXSYISYe{ei%M9vo*KQjkala7G%f7dd%ifo|^Rb=0`kuCV0wm8dcDuGMl+)T1i=Y+mV zk+@$7oAtMr#8q?)-3ZXEC)IhOMYzoWBHXO6{kP$rENfI27dceL`3;-r688&XvvJPO z(=xe=aG@(zgx~fNF4&e=w7jVjx+LDOBzdTFuYU6)ala70Qa@`+T}8RjodB=Yqw4&t zi*%X)MfjEaIB=W3PGxnGV^zH0u=y@=zYxCCcxUHpnO#M?(4{KU@0dszY}+eY)~f_B ziTkTbCW>?An;MDxh49t-S4;9L+J$Zfc(tBYyeo@%ng2!j)%wD`}rOR{WIQ7`nb%J!i|*p+Z4?ia#WqANOA+vBLH7rGaq$ZHC_ zvi*x0f64qW!p-OfI|rYjyBKBneu8d`O8Fu$tKh$3lV9R~Asj5Q&HhbG`zrE@9$ z$3{LbbKR-m{nOawJIgke{UwvYY&KEng|;1%xL*igD_?6XfQo*hn*m-cPb;0^vqR>8 z5q_JJo_9 znGe@8`6w;<=1AgxA$+a4|58%>N?%TKmxdGNF@Yms%A>j#u;H zhUEi^`-Skeo)1h0~Hftx0Y`-SlJ@}IUy zsM#QNJHYGZd8KQd5iqr&_i(z6WG7Li2yu||s8dN-G8*;Mq#N0a`Xkbv z{6(THHqygV7Ii(+(=r(KIMU0q1oc|dJ1mk!g*i#zurE>nMEZr#B~jt8k^bRtqJEbQ z2;YbLD>5)*I*E#Sl?;hki+VR1X01lx05P2eIA?mltlQBn7|3aRMg%4s2lgY8qqkfS* z8@m_vmt;y7CyC0EmpqrH73#iZYL=O(SCHqke1-aFGR>8bM7b)E7hL^NKS-v#R-)cU zUUdCNqT<5I%(yD3n~+&?=u_MjGCS@YGAF(QnHRs5%+LBPc`54*@=ErtWMN`CvM6yC zSxgI%B{@%!rMVs@ujW}zmgl)dR^)9>R_0wwR^>fUR_AL@))x4ftSfktyj7?TSzqW? zvY|**l3rvF*;s5p*;M=}*<7L<*;3*V*_zaxyqz?TY)@KEb|ig8c9twm-YMCZ>?*m0 zyjv;{*_GsqAd>Vc87SUz7diTqLSoA@WhV z4ygN)1LfP0Ps-0CpO*iM9IW^<`MlEiP`u0}rNY2!L zg?wA*3-VpP3FK`3|H${LPm&)R#E~BxEFeEMEJl8AxQ;|M+(>?Dh}cZCkzX6xNmQd8 zdjkH8`n_`LXKHL)1qqrruM|VqX&ncEHy|!3ld!4bk`t-77>GO;wuAkN7 z>Q~MZ-|r(F|6_^mA7@GEU*D22V3Z~6z=f8Cfgf114NkLU9X!&KeaO$2Y(o<*IfkZN zvJX9BNf`PM;_w(DaYrrhhZP}_F;?4Y5*8Lua>qoHM#K^}lGtLRfJKD$AbDeKz{0~8 z0J8&&411Ckh;ab3hDQQ(0<(qv1}qv_RCrHdF~A(*je*4ivxlDtmIYXJ_z7SxV9tov zz~X?#MpOqD4=g6)B(MZvu80qTWd)YS+7VbbVDZ+vz_J62v;GAv2e7QxZ-6BNORzl; zi~`GU8v`sSux$3+z;Xdgv_}HV4J?N}6<8i%IqhYD8Ps**^qU z09amoIg&5y!W{N&+kHH~_2^uwu^6z)Ay4a@Ge{23QFv^L<%hrJT(7<$#rR?gLgH zSQ+P9U=@Isj%MRg5m-4V8;?rB%0`z5RvB1@=v=^(ft8PD<68w-rRc7}ssgJR&1_Ty zmK@D&qyVcNjggJ14y0<1Q$8ZoKB>Hw=AGZR={ zV6|c%1y&DO&6oqg>I172vjtcxu-dUsU=4uPi}?#!Ltu4d>jFyymKs|USR-KdV+R9k z46I>nTVPFqHE?|itSPWYu6Kbo1C|z-A6Ro>P2wEDS^#StHxO7$V9nxM18W7WY253; zS_5klHycfWF>;kNPLM*VZz&gcW0M-py$Ao8qbqCfZ;eKE}fOSq-2dpQsZV3y3^#ay4 zYZYL2iTD8JAe%bHaG{1t9yYB%g*9z z1hAnw$^aV)Y#?B2vCz#afLDzOr<(ZEI~J`C(ZVD~5X z2lf!K`x18p8v|@~;u>IMfjvO01A7?QL$nC6aljs=_X2wa*jU;b*mz)La{dSGQDEb8 zo&h!i*u%L>0ecMC_*~h6O$7ExuDQS-2R0$s~Xdo*_oU{3&>n7b;lCxJbd`%z#| z0h^S2FtEwM9?!$_!PCH=%)|1*Gr*q6%jUwfz$WKqb72awr}B;h_8hQh@^%9@71+~x z_W*ky*p$3)0GkHv*?ft>UH~>VUl_3Iz@E#u5ZDZ0)ABt7>_uSD=Q{^%Ca~%Gjslwn z?1lVkz-9w`F@JerbAZjr&)PQ^*sT1lee;0LEYKF%d|-15)C9Hw*z5v-1A7VByaLC8 zy$oz_!7;#I0k)uEUtkM?%`a34*dkyr7m5M47}!gNJ_fb~*up}afh`60N)guISAi`q z!uq=m*rK8%fGr2Mv}hM#D}XI2x(L`xV9Sa=3v3mzSBrfIY&EbI#XbS{8nETXI{&IGPYl^detONFXi6mfe0eiDVR$%Lay-{K` zunoZ0mFNX59oX6uEEjJCw!Q?*#hZY=RpK{bn}Ma5_zKt-U>lNh0ow{}Q<4?fHeef* zSggGbY)cZ0we7$*mmCXh2e54=`vKbtY-`C3VDA9iUUEIKUBKQhl?v=#U^`2d0k#|1 zj#8I^?E$u{)LCGAfxT0D6R>^2c9&iZ>^)%bmSKK=AK2b9%+DFX_LLhB>;qu$l^X=? zLty*Ltpv6oSVp-Sz&--@emU0WkAZzyj=dx$6)yri4eXoB4q#`1ovidHuy28#s9YJ?cfd|p&Ijx)uv3-01N$D>x0Ta?{Q&Gt zGMoE90y~?`=KfE>zDs6v;b&k!B(u5j3$X8#+5G(#*iXr9{{9B+$7B{SzXSUvnZ?UF zU_V!>0qhT8zf~y;>`!37Rv7~9FJR}Yv;+1xu-~hs13M4w&ngRnT>$n+6}Hy?1MKfA zY_0tl*k4syKmG%Dp(^XgMPTQvP6PHoVE=Xkad2 z&YB~E#Q}@0*&bLtu$Y?5fF%HP)qDn6R$y6bUIdm6SbWXnz_J62t5qIY4q#bpWdoK7 zETPs@z$mcnwT1%A2`pQ!eZX=7ORTjTSZ-iBYWD<|2UyP9^?~IDMr-c?mJe9&+Dm}t z2bQb$Wncw><*j`RSV3TU>dXdK2w46)4+AR#*~R0xM9r2e4wm3fHX% ztT?bjb!Px80jy}<2Z1F4D^mAYU?qVSulpIWQoxGUYXz({u%vpGfRzDOqTUK%Wr3Bd zHw9QZU?uBE0V@xzOuZk0RRC7H{t#dlft9P@0$3$rW$S+ctTM0)_1^%N46J-=E?`xF zRjPj(SXE#ZQ<>drz>-s$-4tMzQ`vY_2UazejYkb&RZ@=ts|hS6bqBCoz^XN1<53$} zjRtHy>Hw?WU;wbXz-l#U0<0denhmxAs}HPBgN49Sfz@vCJFo`8>NWTrSVLfS8>RtE z1D4vbB(O%n>Ngw*tTC{L4SNA=0<1y9uYffL)~MljV9kJ~rIiBK99WYy7qAw<8mF=G zXbG%Y8XJ#Rz?!B_1J)W?i?sWJwE@;VjkTpMuvTfTE$x7{Y*YnUdthxE!+A*I#1#D6~=F`c*9&i5+u&04N+5S~v&j5R({RLpp0-N0aD6lEO zp6XB$*mJ<1>5v21RA5hcEC%d(U{g9eflUMUY{x#pUH~?=V?$umfj!r00_uSDcVcas32b^N)|OeoUg%O3*lb`gc5wik18hc@XMxQHHml3Mz~%v)*>yj#`M~CM zT?=dhu-V<-0`?NHdEI6Mdl}f=Zp_9jz!r34HWmV#-#rJgMZjL}_8+jtz+US939u!= z7IxnNY$>o;dNcy|DzL>pN&#C2Y*CMiz?K7B+G7B)6~LDCcpKPCV9R9PrzOWwyNg=U~7P_?Ck*d2C&z9{Q~SwV5@txwQMc0HND#cTLmU4vL#_5yon@GM~afbAYU7T9~h-W~iOu=j!O z9sCWj3}AbP)&%weu=j=*0QMoUeS{3l7qKy76Co}~?8mVOh$Z$2?#Ct&3;u_PMM+z5 z2a>#rLqZ~BkE48s#F1FyLTSfo*>L05P7+a5)VW9=k{3s~s3rvN{eI4P}@k+!5ihI->AjxCiUu=;_6Jda$7aY?J^S zBfusIurmVeM*;S`06Qeb25X(0okyG}oIg5$cV39LMBAftL>Gy!7u_VfO>~#& zKGB0>PZJVrwUDs=wl=o57JG3Nw&qd)T5RLl(R-};mK8s;;x|@2%!2Ptu;L{YmMW~M%8F{NNMS{FR@7icO;*%GL0)FXE38<^ zibbqgjKWfh9W7x;$?Rw;D_&*AGFB{S#R^ueWW_2JmdfmCH7j0Y#p|qC!-_Xp@g^(Q zvSJ-8-eSdiR%~EJIx9A^ViPMivtkP?wz6UyE8b?sc2?|Q#ZFed!-`$3c$XEsS+R!| zds*=??rf8N?C3pKyw8dZR(!yU4_UFF6(6zUV^$ns#V4%zlog+$uvBD41@_N_toWQ2 zhgk6iD-N^bOI93X#aFC2!iuA;_?i{pu;Mr?PO#!6D^9WEG%L=q;#*dH$BMJ8_?{I% zu;NEn{KSf%S@8=ier3gPtoWT3=UDLvEB<7~U#$3>73W!TfffI-;$K$$$BK)r_#Z1S zvEnic3t@$Y6=AFhXGH`ntgMJ+MHDM+tgy4f!3rlUqFE8cida@;VTFqoajb}EMFK0b zvLYKRva=!wD-u~jS&@?!xmb~#6?s^ZmlgR~k)IU>SWyr~#0dINXGK3&^kKyiR`h2@Useod#Q+o$pGO=bq!asRS5`b=D@n+MC?ej(!&j0P^*IV# zHDWz%{gPOZSdWtbcWB=sS5|Qxz@PKH_hd#H1=0Ych@x_(xy_X`?RAe_Y3{9WZqqck zX_}hm-nsXx*IlmMDM*rFkQfCO1r3VIp3nQwhwpg~_qosg{m!`@F1J`|ltEdPLwUT2 z^SFSExP;5Nf-i9u6;Kf`p%NsUZ5Q9*F!5D&}7>2hn93wCiqc9p{Fc#zRHpXKD-oZpn!n>G^DVU0Bn2s5kiCK6L zvoQznV=m_51I)()EX0RcgvIy>ORyBnupBF}605KpYp@pUupS%mF*afoHe(C6VjH$& z2Xt5I7>s@yacmryac`9*X;|!9lC;mRg*u^b5*B8p-{A-Rj9>8^{>0z-HzO}WUPf3V z-Gkz|9}nVTl*HpGg(vZJMp!95i|0`W*8z`w{w<_XqyMKe(HbOA#}|G3h=$ z0Nu(x0^Q2#R!+Ba&)_+f&IrSC(y$yVpc1O025O-$>Z1{wWrQ zAN0=%=cGX>fJWssDmM-jFbPvI9kVjRMQIM^VF4Dwip?#@Dy+o@=vKHQX<1Iog4&0# z@HM`{w-|#v_#Qvu7yJ%o5C3JP0XYH64Yq8NotN$73Rj-n{5mMH6;FY6qkX zp`595hN1~IP1j>1wqQGUVLu9C-KWPhLeZ_P`&6e>eM@yARr~ZhZr~@DMLp&j!j~7C`EcJpOGZ^;FUDQK?jXB8dy)!VnjGMTz)e67ys8B(`* zA}T5(3hub0A|ji(;)**WA}S)A8}7)bsQ8^TXYSlPH@CN!2jvINoHKJ~=09i7EO*{4 z_dS327a3!V3qN46F+D>gB$&uMw1}Q2eX|$+4kY`R`hP|?&`}7j|^s47%YD9#Bg@V7#GVkk}D4xu|<206AfE3 zGmLmFv-(Kp9HSvNHeOfMV8ys$$G3qMo;<5NjBi2v{-g%9srSat0A2mS@7$NxOnf4cPF76_fR4e87${|h0V zebQgxSt$HV5l^qzzufh|)azgA`WILp{MD}ibg%ys*MFhczsB`n>Gfak`Zs(1SGfNB zy#6a)|6cM>j#yCM2K2AXoD1ce9{1o}0bYBuKz->{|?uGrPqI#>)-74-{bo4^ZM^|{d>LsY1jW! zuYbn%FGzUsx4Zt+z5ZF(f1%gE%k^LB_3w85o4x*rUH^Sv|6bR>*X!T!`d{kxKjQiq z*dF{tuK#qe|A_0q(CdFp`kNCgr|s;YR5QHp)YNrjrsc(!=S{Bb+qc3pnoEt$&YHo} zq;Y%zO#I4ZKv7N zbf|Cgyw0u(Wp;y6dvt1i@|>B*iddqu>3nGU$GTFJ>lRI|iWMB$(6wmlidA#tjUacS zF*UwxLTTQzgL`HVAM4$+tiOB0>h)tb)Er#5;pDnmE%~ua>L+I^GOI9B)m*f1Mq6cRY3w4iw6UvjfA!G5ypD+n>+0gKOjRD7C&H(Vv`kykd1Px-7Q>tK zrtMg0@cxFSOW_;$;M-g@?x=)#?s=-hPr}+$;r7h zV@9kbnW|J^wy?ep=oAxcqZrom6yd|Er_T^140i5GoQ>CTddzbYV&rNop zmx*KlUVLP&QLw9J!SSA5lMn2H`s~}2Z<_5!Ro&jYDPs$gbIYd2@)A`iYkH@~^Ua~; zjw~+i>yrzMWOQJ7#VvE^e$##jRP% z(hQGHM*G=WRlRD%$)$idIX*sqY^8b7NSVnK=NYNquI(q6j@iF#Xd|Y-v&Kn(mXm%{ zyj!HdtK{U`g_BntT(x1r%+k_vsGk$FKtEe&jjJo&KC8bQ^4+r0$#-mQ7TIlfRS92L zzN?}myXa>UD3X4!pZHuyQ&Usg!EeWRSbcCljlqQR&Fo~QNMgz^?}B`vPr!=Yp}fIWORUf7JD_j7_T^?ml(ij`GPh2O6=yHoNIf ztSqY;v%eyHIIrW_f@z?yOI&?r%$jW1R;Y*lmA$JrtS*I$h>c4o8jI`d>donyn)3Y> zokzA~{md**#;1?pvNd6vV_Qp0Gv~#|%o?sK*t;UTadv6(k*#%W;z}OU$;@)n*=UXz z=^UA#OfCl_icQJ8bbRGDNT;S1+T)yy%;LH0%cs_)lJWS2N|?_qgmzgtB^fuz3n4u zM!dRn-Klmg&p`8(X*&x*ACS)E1#UXUnc35J^zE!U*tJO7~17Me;9#`k7 z`YnxNIr7TZHSZJnmM?Vi<)i&9m|UIBQofyTzFS0lYA7j_cD{0=YoB?Y`$|quD40?` zw5kNlv&1dW+__zayDJVhmW(?t?4q12ebqHo_cxx(Uso`t_COZwsdBGdj>*ks&`!MV z;ZirhIy<|u@Z{Ptd!hUrcunu5#a*c9a^XH_0>Trg4+pz5>yxJsAB*YdyW!n#`umo2pdHkgCS1KONs4-Itv#7nzNZT9 zwsgyCx4x&wg*{%h@02;IZx{BD#Yt!Usa#_e3A@`_eWH89xI>Ge{}J)mQ2e?~DmJmW zXJW52-`JaP##@d0(#%YA!K~8KEo-6QSXjDa(XNW#u0j}3WNT%_ z>I&@FO1G?&xJqZo#)|f|yr&!6gIPb_DenZBR^#}USyU#*hxjGVxVLa@X+v#CL+#1! zebcHt&E>BB^XavntCsR3Gp8)e%Jz383*$mzqcLVr?wl;_9}=vNCGX?*7UmX54idU8U`UOApP{Ip^kPbXnH#vWfVby;kxDwp6( z&6U&-(>Nx|JJE<^f9SEtoi(NAEFm}4wf5q*3ynO~+wA^*lMgh;Qq*oPT-?>WuX+T= zPqIhFBmUaq_Djz@*0itkxH-3YS$T6scGU)cY)qq(Oix){Q$7XspVxS#Wy<2=ja06@ zYzrUeyN!f!rxeE~PF}FSa4+>I;9t-T{aoM9%538Xp@%}UlVx4aEeoLiRL7>1U8(-K zE}q=l4CAa{Zr1qWb-k3%QBVFwl)l?fHRc%y7tW~ZT{S_;qyAGOy~#^D*DYEw6TY{K z6W!yIa~oo&)i;*(Ao|;??u~_eC)PC}-f4+NyQ_NY;wPxx!2Gg&N^O5b6^si;lKRUj zD@QhN7@kg?Vs}<}5^6gudH?3yj?%H8zK9r56N>}e*GPJ7p zB#ci1_&4y%@Ng)fPyc|gr~&lUyRY^@a~{~~{)(Zxc=6Unduk8vntegnqAAtN-)!!l z*tf5;w{^zwj)L74T@5&1PlEDLJ4D=4PlshYtj2QEJQLgD>C3%+QAoM>oT=PP&rt5A zqszTu@2GP3ou=Gj81(@tVD(e^Stvs-2LeH_D z8Hf+QPxdV7>Yh-Rm}Mk}yDuDv?F;?aF09je=s${JetbT*H^2q$vErhAc}5j|-<&tG zU_Yb_^9vX!ioJ4jJSlFUzG48z5&F)lhkQ_pj_i#gh??87?cGJLc zcYohdna(!!WQK+ktN>OS!{a5`7=w)sh-|QPotOie_QRR3Y+2`Ee{W;oa9e*`D04JZ-jnI;f_2!V{fD#V z&Dr5Y{T=HweH}g7p|Ym_{=*{!2{r}N4;M|aX$H$9c>|VXX>GP_@MwF_;X@sRWeIkU z!IFvvowy<$ot^2h5dr8R^K1UnMa9@QMpTmgA2I$o8hY`#kKRVDV>+barsC9{{3^ z!OG8=wku9KBr%P_p-KcSa_jHxgx@oeO$zVyVCERuuj?I`()pbuJw2oz5H1jUa;1uu z?p(hyB8CdUEHGC4p=|qMXnsvjbt_NMz!;G()UfzT24NLu+S{{3V3(PZ9)Yu@w|fY5 z+truta6JpM$J^7r@N>(^P!?lN?Cc&)ceJ9a#S)l>u?qq74~t!%)H?0Y)W9hu=wXI~lsjYH#b zecJm62hrOn2vNtQ+4p99)5kD!dgxGh=WrHu%ZG;hq3H-uV8?h^vgjg@k8EVV8pr$& zjtr#-vl)Vh2ntr$wbiAY*EFY_8e7(2!-Sgd$&|N^4D@6dgW2rVJT7Q*hl))HFM^-m zR^;Y`ZPISbbftIn4?=m2MgTW>RCZXs;)gBrscZ4VC!m_Ie>9Jae?ubwHiOc>TAKacx2D%a?YmslCO|L3wr;K4m0rDObK80-HTtYu55je=>(ekk zbH}5#aW@#QjVzJ*^=37cPS>rkhep~4Wlc$sosBRD zDN;Ap{sR-}`t&Wnb3h=8A@B<{H z;=&|il;6?-KbRwp_2OI8Qdi%!1`r1L0>%JeKpEf*I0JkEX@Dqfsm(a*0>^z-Wz{rvhwKfgZF&#zDP^Xn7+0AJzihKA;JeO=4ObbVu6D@+i`L(pT0 z-qp4yy`yn8wl4A!bs&8xfi(>cj!3?UL{$SOCb+fU7?cLJ5z3R&XxT(cex);gU*iul%aBQ#jKfLsNmrqg09%pdJvuA&dSNG}d0;Cp_DV?2 zc@t_)@2CSzV;!+Ib)GIy38F7)%t=q^RrY-2WMtt->h)&rt%8&kg=%vP=u}yW4Ad)4 zdQ!SrMlOAtTGFk%UA2f>1fZa)F;W7(pmU0z6-xZ(^%|X)I zR@VkS6&2lyg*~w>xuZ7patrQM9QvXnoJs*Go9h}j3J=}(p-7GgmJqUcSU1%qd5ZP{ z#Q_0FZ^TgvMd2Zg;z=tP(jF_Pq(~POSy{Xgl@?F5u=rHt+HGLp(w-eg+Oxw7doFHl z0eklK<9_X@A&0_rZcne>ysj?2X)^?g_Lx}RxINvnW(VjRDNqJZx?n=)^a(}C zv~60uwiQ888y54#ZB0$Ppkg>gX|8K&+??KB?_=xrQ0S<=!k|GfyH;m6>ny0(D-0?v z!3~kL&R0eb*vrB>o^LddFpN ztsCqW-YSy1ADyIEr#`#k#y(?z%Ghh9p-E-?hF~9VomgM$KG>5r*ivu$zNn$8W{iU= z&_X-dC1}84>%0k3K|LjZAt`5#PSj2pv?9>uq5h7B46LAm>Cg06%qRz3-hXYa2&JgO05v*xHNrE-VWcY*cH7-YYldLIm+2{hh)e;f(J8>VsHXrJUZbY~A~FS_ zMyCLyD6OdihJo((G(fmYPXHuj0zi#UV3{ugK=5Wg0g#Xh05v*+<z(%|gke3mV9GycIn1xV7dlmea z0;{dI@eN-Rt_`7ZKoVdVTAr@SR0Wz$6<7c)fM*7W)gbtNUlOjlpm0E*K69yZ%>~JT z2w(&nNY_590_~#;s$7fUS_1|J!k4FOG$=e8d3A-&cIa`cUAsXtAP$&9QTI@KsJkPZ zgu+E~=N=3}#|l(OuK14m6GGnnRB#gJ<9%uPDI#mf zCi~*Mrm#5B6c+nT0eNX`NCspG^-Y~)rR*GIrM^5}<5(PM9E*L%fxMGvpm8jQ>esa5 zS_TFMfP}i&BDiL;IM6H>L&a+mT${k4(K#%ES{FmD`03b=LFIVkW3Vg|k^%9-0w&`W zWeC0id$Q?ld%OH47k=Cyv}3*!FL7-L$$<0#z=Xi`Ah8R4;9R3x5@=LQz*IzH9sMKl zW#a({iNSZTR#Ml(Fj@dIFe5UU{@&j1;WQ)xU!z(QuFWk8w7Df^vA ztVM9Ee`#R#FZESF@{X1QtADAl^&#&>2(0O)zM4kfi4a)ROMNwsyb~d?rfYmPjl7J2 zr2Bm29yp!?K6fN z*BFoth~P7Z8rK+*42S?V?u=i9VsamQs}H1W9yNjHQR6cYffnn#V#Jdk%H1e!;U z&peQKA_SVpGM{-MFC!p1S`Ev<27=ojoH%hhWk&GGNC(>&wwK8x#%D7g$2@_zLB{ z)0dcQK+6IRXqnG|kayq*8qhMI0U_^12sEH&J_ADDi4bT&%Y6ofyo`Y4XoV~XOYqhi z@=k<6BUuhruSIaJ0)ql_@L9!j*D8<)Td&l;Ay)_`O{1fMl5cdY@* zaibT|Dxl5_JuR{lJ(A=h=%6@I?Rp&WP;r0`iUT#T#{mx&2k4+UQ2BZs@KAAp4vGV{ zt;Ycm6$j{`I8fnw9Pm(afDVcSb*{$&4;2UKpg2&;dK~ajaexkr1NE%O0S^@i=%6@I z)p{K8P;r9opwe##=;6dcIv}4)sOmV*0|sm}>B|zsRP9>-$`7#I}CZwI(=s`3f816&x@^YPdL1_tHhw*y=( zRrv(l0WOc~`FQLA1B3GM+W{__s(ga&0M|qHd^~o5fkFBB?EsfcRX)LXfNP+7J{~*3 zz<_*k4OEMR9!@?;2gUK*0j_|mIKg&+Yo2;O9y`FmpnUvxfa{g!*kFUfWltyjX0NlTW0B z;`l8Gmq{HZAsrOQZ#lRcs^SD&4z6+P*gTelfkF9zad?!{VVl?b6Y-c5E`bIm0>+_d z?6DkN_6&;Sw;WvUR0RyS99+uO^YK^?1_tE=#-PXXSPHIs2E~E8*W-8$0~bC6;^3O5 z76(0?@*o`)$8Q+8&Z*)A8wRdy>iKvK0|SHd@f!xNcB*`W4FlIV^_?HkU~cp0?XeAv z5R|vyHgFwOlXuFer}STyUvW-%Z7#Ng~-(GNSROJ(FFSsx&);e%S7;V5df9=oN zV?ih$lrva_n3TxFg=sokXq!*@)AE=RF0lrs)wG2kP8_5I^1&rj zJ&wnWFfb^N-;BhvsvP!^4vGUtq37eV7+gjTiUUTGptVq_kmvjfc+3ZvRf7`nn-4CT zDuo1_4=#jy4|w+4R?MHX$DmL=C}*&cBIrbV)4iFY!*o;>Qi2;)btQO=3fESHQUd$X z<9Lh*msf-0_>BiwRaLozjRzM`wS3USiGy@NK4NJVXW@>)58Bpve=;6>LiwO%{Pu*) ztSakZd%}fP9j?coFfb?|uo69v$Aoa1H7JhXgm86LVGA}PTu;^W@fZvS2IT{_ugCG2 z2Cl9K#qpa4E~+YQ!KQ)BsCqsg(+FN;t@5w23J;l&phsh?s(`BY<|8~*oIpFMs_@x? z@KA9A?Vzdxs#;u1EO!FRF4uycy?XYpd5AbckbUM+RpFY4po8N0%%iHpH4i}t#qpU( zRfTIFf)0w~GmokY*E|Fr6vt;CRTZvz2s$W^&pfIsT=NigKpg+lYn5l|RnS3k{N~|V zZ>>T)D30GeJnOAhNC(A%YS-+*v))>TbWj|>9eCDTtB?+g1Jy2mQg(Vm=g(Lc$Q$RkPeFDHx17cY!%W$ar~y?S%R%XIw+3cG(1bNRY(WK@h`zvd6r-W z9TdlJ8o2E0^a8<4uvNI?s_ELZ1SVtXW&w+%ur8%9~=O}Qow1h1o3|G8@Tm3>voKD2Z#=42YL*4&YZ^6Wh1XN zGN3b#qc9{l#|0N2ja&CvU%;Hc2*o=HzteYR(_LB6^SC*UyFChUZdNjfGXUSt96FdD zhNECmJ8mS%ce*Fv(b2i}HS6n`8SLOUpc1Xlp6&rS&m^*P?orAd?@qTL%JlVRdxk*g zag>3S&(l*5l;+lVtnXs_-vcv5h%PqxC4SCmKzL3@6N8MVxfzX)z^xxy_hSw}hRVZR zY#QpC;44U-;#1ey?Dl!Rv=`aPoB{1*7p-%WP-5WLL)Om_>ch}d4h}44>fQGR9IdV-=nDYF%8R0OsV z#T5^tza`P%$zpXK8kEIa;A_8UXfJt~K3>jcLJ~4xCow4Q5?8Z&LOSQR5n1>@TYtgA z{}m5r9nBui!XdECVE6C|d0AFMT&aZFCdpr12nP4|_(h?l&r(wV2NtG`9!_XAq9yl0ihX!HEIeR3HmurD% zZ??PZSo`o`PkNxgM>G;KeQ-Q!fPsB%=+Og)QRFKTXmL0|i)X!TJbqrh4AnjhDpu)) zvW1aT`FOM{TA4Uk(AN%ULqIPb*av{AyPjZ`^F;%WFHqueUQ39tcdIVUNCLuq!-BzH z^%5oJHu8X6l@0>Jumgx;qsYUuqZ$%Ja06fm-a981LdAyq-4am00ZE2s=TiWWFODz4 z%7dvTv`Sa~Y5YM4J6b&bA!-SHpiY)kozyCE0w=^Hb`=8gs0JeQQpx4eDFh|V;}^zP zVFBS%PAH(;wZpVZT+ZNJvl*brMon4R)o%>77N2~mNno`@ku^L}WH_iV?}>A}o(RZz zd`)~UmU10Tg8Zp=WW^nmW$B8L#bUPkgNS8)H z2HSr+UF6o|fbz7e!09{ePJqdN+_@BsF1M2a0BV;DRgbHh4>r}qSBqnk+TdkN5zu0#TYsY-(}R0n0;2QyK>SEP%Zm?kcAT9^vRHhW zvrE`Xq>jSZq;nA`Tt^B3+*>1^J2*MJl$}E1i$TH>F6+7Y1eR-LIE&ZEKs(>g<0s>n zra%rh%Rr)ZHK#vO@-17z*(=#)m?#{rfkdUZH&GtHf|7fUm`%zHJV{F~NOi9#XP2{A zVS=v*5%(@oJ;gUridT!O0rM1>fI>BE<#zlL^ieQl5#9|c;Z;Iz z1wkadDwMM~u&Xhtn{gS6E-Uq=^(jj0)53a0G)PQ0N%F9 zz9wuN@Z%M#e%qGbnBd#kwV2?ygl#+idW!c^ir;|?Z9w~F_%97NQp2r5=`wL^pmXhS zx-5GH)&}OtYj5O&#oX-%+oSuvgsUc)`t(t-oEw1&5w6N@=j`p&Gu_YGbwoYD**l1O zkhANFdWf@k67?`=?;`3KoZUdwBb?nx)T5leo2bV)dk;}haQ0rJp5p9%ME#bt_Y?Jd z&OSiY)0};fs6TOb6H$NR>_bHTjk6CE^$cepA?jJqK1$R-Ir|t<&vEu~qW;6#Cy08U zvzrB#$2j{WQ8CUwMU=(ar-{nr>=vSI&OSp_inCjZ;+%b!s6x(eBdUnA&kN7_-A&Xq&OT4n49@N$>RisgK-5gmzDQIVXI~;}HfLWZY7S># zA!;6HUnOb*XZI4dh_kN|Rl(WUiK^o48$>PU?3+X_!h}yu}{X{i!_G6-2ID3Go&7A#&sI8nm zNK_kVKP75AXAcpzle3=@wVShtiQ3EA&xzX4*)NDXz}YW}I>^~0M0IfXE226%dz7d{ zoc)@pi#U6Xs2`9^qIeUtzVa|R-)KSiUOVn}Ben-^Boc*4tlbrp5 zs8gIhP1I$a{gJ3warP&ouHfv?L|w_*Ux<1gXMZK?D$f2!)YY8*ov1f)_6$+iaP|+P z-pbjtL|x0-{}FW^Xa6MXdd~hu)Vnx)j;I?s`!`YV;p{&|y^pj167>Pjo+s)i&i+T# zhq=Ls`Y1f$OVr1?5hLnmco~JLPjSN{>K1OqiMo{=c|_gDjRaA*bHgU;PHrTLx|TBE>L)168QAE_YxKT{hecUJ^>bu++OVszdF^;Go za$`JE_j6+cQ4erqB2f==V-ishabq%34|8J*QNQ5ERH7c?#x$ZH<;HZP9^=LgqMqQ! zIYd3hjdO|mEjLPu`aL&h67@7U&Liqi+$baJFWi_#)Ze%pP}3$7nvKI=kkD3j-#H1+I*p)v4LZr47b1t3Q|m8cI`Z6SQ?~Zl7rjmN#^`88F@*4n52GpJxR_9NK?#V zy;mVe7p;sgS`}TiI=ZM-Rg_{aiJt1x=%O_wI`0g6l~*{w5Mim?XemqWMiZ9$jV3HL z98Fm2IGV83ax`J7=QC9_UiVxPt@cnfqWz+1MEgb2i1v%35$zX6Bib*DMzmiPm3j^8 zx9D{P=jj7d>bXI7j=yx`Mb{(}G%WibN;rd{dlf$ko)(;XR)OS#hE&gM3nUcOtNI^d zI0HWS*7`HxQ$<6Y#`tS{5r$z7D-f4lIX_Qlsx=$pI zXyK5Lr_sV8A5Wu&rG5iDFOMw{=8%u4(J6;~JdG9(`FI*F9P;tx6~^y@kdG(7Xhi$P zR3q9iibk|w6pd)VC>qgzQ8c3cqG*U-N4+;h{lbiZxd=QCgwGI>Kv0*4uLseKJR}p; zr8zR;U790>L#7xYg8F?F!fv0QI3l^Ad7e+sGlLBp0#I5$h(t*SjZH$xeJ6O z&nJ;+koMeHl}ILNCZRpHL}Ec}ea;(9;R&gynZhx7hr`ol<_>kIL+!rjBX9fC3950=+fk?2g!`n_=`raqO_5yC%-a6|6-fp)Ir%PCxB$$K zNFd0n+*hnlkH`PGRd{M^#hX_o6V$>1j(Q3!l2m;pDfumRh8*Q@A7_wS8!5-lk)-5W z#~E^zA4OHLGsfAW1^cnZ)7<6ZudH*nhOLFI9|_p{QR0a%A6w^a9b1pVu5D@kw>gwovS!bJj{=f5}-JQNQAB8&SXJY&%hpbGC!1Cpp_m)NeT3Mbz&&+fCFT zINL)Mygnhe6Uk#}c-%o8x`4d*vVB;Zzi_snWdFulny6h4|+@{Id-ItiV6B@y}fRvjG1r!9V5rrwY>>SC)Zy=sQRH z%2bu&owpj_izL35AE*BZWF(--0~pHqpuZv8=z;B_N>V(o0SCcGhO%g(&=rwT zKWw#DLVej|7<7<=;LMI5R0W+C1&#QFs-d@`pyU3a#n9j+Ab{!M-|WUuC}$ z4AwcKiU*E8BTd47GsN`2G{Wt-03iDs`>lRJaN0aB9$?e+6DP2^{dW60%n$bQj?wF& z0=jl8B5dFFg+cFvhdEE%ySSx=_PdF+0sDEA?QnQGi!VTO`+eXG`NIC)0y-PGc`yrm z+o6el5VDgSJEfm!P#;R#H`yPCZO`4k)Hd}XIhCeqd z434k(Y7R~)O;zrXH*g#Xo??!yF?+LPuokmF+ipNDWqE^<-qmH)o^2k z|e^bkR_bNf;I*D3o~_G5q%Y)zD9w9PH!#>Is3 zHy{TVDCEHPm1Q|MUP*FKgB;kKkONnjtE%9}6(sjpkXtI{!1c*ha^v+R_bkZ4i5HO` zxIVcmZoG-){ta?)p@)zI*Cz)9%zn{2k_--nsaAw@GkBYlzJ=0*FnSqp6Uik_ZAD;?aa?trfMFe}8oB$-SxE13dAFT)8bOlv(iOaz>r+0K(ZSpWxRl7-OO z!U9;i*r=9B7C}>_vrEDQQwPbC{A6)*EKv4BIBS#~53dP3?N!;w>J#{J*WLnu`np<& zVR~1VNKS-aR84}yM6u&ePEIB#C8t1#IRFoKH1xwqhokR+jC(DwvFu~b2TW7FEqly&zwVFuIh0z&A zpc7aY(5rY_x12);4L8a8$p!hzdC7&)0(W!|W*edQ=roOk27On{LxwAOvOHM`4)>JH7|Er{niQLq1gkE0jV@T& zRj6#`ZOK}gb0?v<8W)5=kz9$B#m}UY7baKPtkGs0VN~}@g3UBQb5b^grH3;iU>s|b z$<@iVFcdiA?$iMyt%uKD70DAKqHahg80_=lFg}P3w|G!xn=d)ikliF zwm!Kz1&M7*0T?Jjlg&2SY%|WLUSYE>(3Z;D`(f%L7XIKsv4d44sW_#~QJ*2<({5;s zyOQt)a#eDVr@v?(ISvYd&kgrjK6;6gr<2M3$phTDp1K*h$tEc#BRHiq*k%`Cu8>rj zXp)%hNM@m%Pj+(S-IV1as7s?MIVGQ=sl+Hf!a^ zN2nAR`)BrRyL)<|x=un1QMwZrCIUpIok}JzO}>&FH&YUqgVkAgr@-&kaPkbQuPlQ{ zEKhqv_(d0o+H&$W$tz(VnS8Cy+F+H6hO?_|whb1lhrkerlP5n&iQdGGdngEI`_?g7oZ-ojQqaewst#rbdGZrflAF2lB@%~8 zdAx(7nGHIamgGe0(%8Q7ZbtQ#E6z-P_{a{>gNllIUx^}y@2Fa9 zF26xj%d!D@go`J?MK$qlo9%`*OOp7m&GvBPt5h>TfCWtQ{!z-lAN#p6PMtLOcZ~GF zf>H7Ts3@gx=_~5v!DR9$$)9q2W#Z3hJU<(gmwdP=@n@4UmcTy-*eHEMwq^&rVJ+ff zu^N~B6&!(Z=kWBYP~Md3J=l?H&JJffGwtyCb0U%aHT1EWo?(xl!LIZU{W2;D9O~~_ z57)f(WQWR{`uh)$46GPEAMp5S5%EiLMPN0K0@;x1>1l=aFQ~f5lTW0Qk0qakLO%ue z0s}o2b?r!>sPYO>(fZ_XOPG=Tow&@zAFNdRqD?q^d;s*@o9!FU^pw|UhO$&i@J;k+ z@((Gfqo-}Q7uKPvn*NL{l=Hapb+UlJd1eIShJi#94&B^GfpF;Ndqlyi^iDDqICOJA z`N5%^pAZFyZXOa;3J%@;oG3VS^C(ep=;m>v;Ly!)iGo8nPZI@)ZvILX9J+aiC^&TU ze?-Bdo9BpvLpT2=Y8;O-q9*W|Mbso7vx%C*A!qzNO-PV(K$`fyQqgU_7biB@nMx>l@@95Ps>PsV*dNK?=aEv{?_2 z%_2On;Pzp{QxA9=N|>3dwOKEZ&7tsh-0q|BMhM?f!YmB$>g2HvM8QkwE zek2hFoEqZn5K$vMwu3^C@z`#nPVm@1qAr0k6f-_REUZG>of#Nxp}q3dWt8XTIL<<; z+DYaL9_u9PN*?Pb>UBKUL)29~)=$*cFfr`zgS7A>B%XQ`z_G7My_v@bDf}%kV2U*$ zo_ZT)bS;n3azg4lz<~?46!m(F`cCM$UDXYD_uxfDFXeob#+%d)sT;96-pymj3F&+B zk_j+JSe)Uh_Y;^8@Yp33dK20PoJ8#)eSd_f;lOJd-S6!=|kUq*r7hrl0{uoMQqmjdtS_NyuI0SNp_ z3CqVonp3A9;xU?+rXJ?8n<>ICc#NiSsYiJ1R`Pq4$L=8NF&?8SR_X~JquEpHDITNI zI`vzeio=97dxZW!o3m1y7o~om`U6(@(>zAwMe0vH_ASEt7asc#QGesH?-TV5kAEr)s2OF3~^Zf=L()%#l@^=v%#-_-Lc^*?nkrpySA}D--O@&@+}_w8Re13W4|EE=Ju7MKJ!y!^78Xb z7{~hjH3b&(*b_t*ar;^lD*>^wC9D9&enWvUD*c|QN!)%XiA@2qsU@rs#8{J970#al z%SR)9L+}d?&p%hR^88ZK?qMy5=buMDWjyvrN^7?K4(n)#d->t2HJ(2QMF#Wd^4MQU zWIl}L&ZpWjxS24^^B0l~3|SU_F7W&cN*9Kxzf+`Yp1J`#*<@ZmEa=4!p5Xa4B(jXh zo+S|&gHleqLl^V>3!q6t#w&U3UnH=K$Noc99gqEwC|Fk*>siNEpD6ijDEYO4;k`V6 zJ%z(+MZe7kY<7g3F-o$9n{lExbCZVq{H@$9Aip+l(r}-@ottCHZzne=5Vf0|lZo2P z&1ppK*BX#+N-ug=Mhz(Wn*0N(+YC3)p-kK11Bv{y+?+{%UEHJrI=`EnG!*9_<|Ylg z`Munv!8O01n>3Q8|`;P>&ZU`)^@xoaeoOL0|sZ-Qus-3t|aOd zw{IiK%Rut-5>|v_Gz{lo!OaE|yOP^?komq2#9m**icxGW1zyd~Mxx%t?K?^A8W4L+ z2`fRdCJMaPYm*(YAkXu!BlCF&H)*`ihtX>+_G?{(*$k}KIxf$@L43dD-)OTzZqh)W z|6bUCAclne_j7X_W%5C7fujmOg!4aynH8!eyr+bX!!py5pZ_Ip(vYA3 z6>dLBV)ugB*GkxU6r)){{x`Wv<9+_OVLJ`M`3^Ua5ti?9lNRUmf57dZQzActM4(b9 zU?P{2*iX3mDx!W0J8>wHpK(GoTh6L}*AKF-Z+hTle%{~)nK5F1m%rl8nYD6oW^-ymunx1S@i2_QDHgiS@UZ&TnD zZhn`jY25xFiOm49b4u7W6#D@M&g97$1(reJtP(aIjqWHn@2Bv&-25p~^SSvjQ46{G zOQOncc8r^k5>v&^Cy83jO&WvvQf|@+!k2NA1_}#u9QER!CPtJ7UjO5Z9CxD^VZk*4v4?nOoE=@K14zdIf$9x2XN{Te(H;m%}n%UQf2KYxof7x5Kws zauSD?J7)8{U@n2b;=m4q&TiNbGTytOuhgk3tPvQ^@KF3KM zV!?Mci9;;-Vy57bh~Zn9#32@Z@sc>ig6~%nhgk3-O5zX;J~2rgV!?+bi9;;-EF^J= z1s{AQ4zb`I7re56ruNW}0dM&b|)KCDO_V!`JVi9;-SPcCtY1)n!04zb{4g~TBi ze3Fnj#DcF05{Fpu%|PN13%&p-I3!~DwjXhb1z+$Z4zb|Vd&D6Yd|;0_#DdS|5r4-xt`0yNYhy|aK6C4sTd?1cE#DY)15rfT7JQzIIK+YvZxM%B@Odrb5DPw*MH~=jB|egspw12`-~ol?fdU?INFFHQ z0g2>+0v@nP9w^`ejpTs>9`HyWDBuB+QeKJ2h1FYsZPEqQ?t`)cBmGAps$ zmb}1+9k=8KKJ2lpd4UhRc*zTV*vU&?;KOcS@&X@r^pY3&u&bB6z=xf^$qRhg{Yzfp!vR3@0v`?m zk{9@}?_r1wI@cBrovc@F01C4+jXz3w$_4NM7K>K|=BZ9}W|e7x-|X zki5W$Lxto8J{%*6N6M_k;X?8P9}XCj7x-|_dJ6BO_cK0yKR;1d+^4n9Ev@8A;@@D4sf0q@`w6z~o{ zK>_dJ6O<_)@*{j={1A`yNgnkl9^jKa>Q6kbCwbJLcsNh;sJ|*Teh3P9g%2s<6+WbZ zSNMcl#;X?{|g%2s<6+WcK>`@g@*FW(3;Bpdpsw?%o5Vq43SA!Z#JdYHQ(J;8&C$v30@&ofp2X@ahsaqwrez zov{^uV93DNGyEWEHT2`}f(5O(U9>qf(1!alK;3v6r)8w~V0KXYlr+KK@t*DQa0^OE z&mt=L=FA{`zQZ!@5d0v~2#FqyN9|Vk-EOV{$a5n z9R!PDaeR1a7&gODn&3626>`ip_VoZ3+?EHwata@S&q`U0S@189+3eS>1dlDk_L34j zpD0{7iYQz-h$vh*Kgf*2>wu227LeQI7fuEW7tRF=7fuBV7tRC<7f${O7tZ|&7f$^N_keWa#Gl~dyq|F4w4ZR{teLY6>3&HbN&f0piFr2ALt{!O}nm+mvt{fBg)mG1vZ_n*@Jmvo<# z?!Tq`AL;&Ay3b4Zf8^pt*VwM$mv(Yv(lw=PNjEOtJn1H+YfCpN-IR3mrOTyTAl*Xg zj*)JWbc>~1BHgjl9VgxK(w!jPiPD`U-O19OBHgLdohIGs(w!mQbEJE&bW5c>Q@ZC# zw@kXTq&r)>=Sz2vbmvNUo^13nx=W>7Bi&`v zT`t{P>8?OGb}t;Vy}($>VukO3T0RLQDQ?bOc(<{Uv8MU+ZZ}$*7kq=o7u<5I(Kc_a zv3>sS#_rpV1GgI;&GY9ixZOCkW5F#D!7RKU{^m2|zpNx-)F+Jo!gqp49vr!0?6Jak z!QXQs3eZ$6u895#Aj42Il{3yogJ3U2^9ZWtG`A^M&4n{w%7duFM70?=(=aRiIuM1`2*-iwf!uxq$k;2I^`B>WyKb-V`0wHMxNLg9hp? z3e;P}K*8RFsG53vE};IXfx1qCdPf*2_`x$OsCVT8s$Bzhg93G97^rtg2ld_;59)mi z)ceCgeIPohn_fJq4=GR|4g&?dN1|5W$8rJHp;h0<6{t^yfx0<5sGMv{2lYt>>QiB$ zJ{=v@XL8Y0m!_#(6{ydKfx0a^sM}vWs5=y>JHtTT6&+Mgn(EOsb+-cb`7luToMlkG z8mKQQP+trK^`)~6s!s#;Wd-UhVW7Sm9aK(}yg?1ry$aOV!a#jJI;d~vV(7;-P~TFZ zz8wbYzLyo$cND1ahJpHCbWlIYMN=mgUlx{W2GuI;m;u5e4d3VW41JXH=Vd2|)c? zfqE}6hcHl2M+fz%TtK~21NCPG z>MvoS{`#_l`kMmv_b^b;L76c?If!A)xS#aKz3tX5`ZPUggzPEarfUnPH&dxN=lb@mxT?S_74* zKqbOJ+0j8Ia{+aQ1}ddM<%fad(LojD0_rsys6qv5Oc4N(Lqhg1=Q;_P*WACXRL@x z=P6KSVW8lEP1JrWCs1$KK+RU5&JP1M=PZM|P6IVpftnWv3XUC}RZYD^1GPYbS{Mcj zPC%ViP}ggq$`z=JFi>z9D=Mh!TnznP8mPqz)RHhzOQVBYmJ6sGG*HVGsM;`4E24v1 z`Qkxcs6ed>1NDmNpz2>ds0IaUbr>i(q!-nu*1dR8>lLWRFi;z!gKB#5pqdq^mM~D8 zURF?>6{sy?pteQ_)s~B<-mA5~Z3@)(Fi>!KGpbGHWav7moeI>hFi>!MG%Bc^Y)S{U zM}gWK25R5S3TnRsl@0@S;AI7sQJ@Znfr1MJqE=r{hWa3{Mmy@PGplRx;($ujqO&veWpgyR9I-x*a90ux==%8{M z`*ctz6{t(YK%I&XDyQnZNz>FT6{yR?KwTak)T?uuy6B*;P@rBD1`6(Vh-&Ds%LUYj zG)=u;fx0RT)ElCM%Bf4xL8l>SG$HcPUUegn_#8EQ9*E2I}1k)O*4}z4t7G z`h*5bZ4``!Z4|@{5~H@hoHh!6Mgyfb3dX`V3gTUjQ9h>^DcSHwuS1zD#)eK#26pV#! z6vQh=&uaDQpwvdeSlC8EyzTU?g8HncDYa2B7Pe6kFJ6rbDyM$xa~deMQ7{&^Q4nup zjR?xf>D8Es14=7MS2?OK|dC;I7%T3hHYbsQ*)-{uu`9 zUuPNA*ELYjDNz3o1NEP?4C)&isQ)TZ&xe8f-&qFrO)n^uIiO4<1QcElAJwLEI^*y| z4V0-sSz(~!(Lv>OzE20G_Ia9N`#kZ={D_(|Q@P9%bWr(9Q#?#l1(87+IaS|}wCYp) zJk79up7@YJL`~)PHFLiPs#s~NBurCdBZJCKQx9mM#wk$a!$3`l3@SI9(m_pBpeBWZ znj9HaET^R)9n=&BYHAp$X^}y_6q=f@K+OmPbxveZxy`3^O`WSim4<LIQAmMBn5 z!$8$U2Q@R7sf!M3nF6&u3{-7&P&xgu{WDEdD-@^;!a%Kz4l1YLkabXM@30xRcNm`* zI;)2Mu%@XxrK$QbO*KRYW#n|=UI(>Wfm#y=YHegtv7Bt`=bEP0DNyUfKs81OmD8e` z4r+q}wJ{7-Q)E!NOJd#-t*ZLk z!m4jubWk~6V5EcEu0ZVw1GO_csGMe=ztS|dOM%)Q25L`qP&wUzql4P3KU88MezB zU#g1=DyQ9xk89PZc3GQYyR7liyr`gZn!4zq)Gli?Y?n1Y))x_!k<;CaPiUG_yR6Ny zUDo(+U_?;na4xM+2Q{L)gri|y!m-Gpa@&`ngHl&#nqgOG;v0$)HI-ZI(?MOLG<7me zQU&bNsmm0o%fmpuDmthuUOcGRC{S01fqHFZP_dl)DP2>qQ=ncS2I{Kl zpmOS`bWm?lpso%B^~T7cjGXSDdP=jYHz`nW4g+;fbWl0Xr*u&2l2J44l2Lr%G-8)v z=5)!Z4(d9ksdt2F>iWo_VmWQV(LudafqGXMs2ie#%4q|R4(dh)>fK?W;H}As)tB3V z{2R^C->X2qFANksdl?Z_Zfl-8s1GPm9}EKpFX%=DmD?;q2c>pdn_;`G@iE_spmH;G z9n?paral&?sgFkom6M_Cpgy5M-5dt$laWCgIo)NgU9fF_N`d-x7^qt!gUW3_rGxs6 z0(EN`sLw_QWqvM~sf%{&w|Tn)bw?PeJ0pXNMM~!nfK;mQ`-IL=GPRcuZMy9Mr2UA*_00In+nvo z!a#jHGAJXb`P9?efP9|<^_?(K-;E3^H=EKyeNTbnP!C52mD|)s2laCW>K9?4eiB<1NCHdP``QcpwupFGi;Z&8GV;^ZZGrv zUDK4>Wo?G-vNogdvX13+tI|I-P->U88Me#XjK0e{w_iqeP->U88Me#XjK0hIr2wUN zS({hpn)^ z!`2JfJDk&|uIIJtQ+tQ4u)V`p^u5EmX-WsB_6}QNdxxzTuy;5oP5n>Pl-fINh3y@- zUclbrmjIO7J8XsR9kyP;-r-z88BEiZ+BH0Y=!L|wqC&A;haDj znx@p=VJmF!uoZppuysKWW1nGapjN6`!i8b8gjJDe2|0BMK2Wbvpz6Xv)xWHu8WgD2 zVW8HWWl)w@eQOn{bzz{^zpS7d6{rnipf;XmP;pIDO$tg!aXy23ymiVP~J z?>?hI1J$iST@(iDaAZ(9EpYfi^(auiVW9e6R#5#4)Ib=hBWD>@p;mo^3e->-sNt6t zl-fINh3y@-qVFBf&8Eg^no@g*t+2hr)(hA>oXhb{LkFey4qIV+hpp&)hjY_Zk*29r z%BEf!W>c4)Wt-ALU9LdADh$-C&oZcDO;cAWP_GFCb!B8wxqbJQXrNxJK)o&u)axUI z%I&*P2X&PK^@cD|SHG;F-l#ymDGbz`&oZd7TJ>F{K)odl)LUOxP;XP9t_=hA_OlFX zoTe$Y%i0RtWo^BHUDi1*1?iyFE^8}nm$mf*c3I~HYP_Z?waeNH+huJ<-({U!m!N}E zyR5CSUDnnM*kzrQrY2~bQoF3JkX_b>b(8fWxuLn1#o#~2^5#vw)B5<$K*b8*i99pl zFMU)_APMUe7KTHZ^rn$J@Ey)f3BtL82HY!O# zdFLl1Cpik`UDn+)$u-P`|DcHTrY^YC`cg2=b4f&%JV7PLXx8W121p8Zkc^=YzytO0 zW$P=WbC`Cg_06a`d=+&oa=6#}mYc&@A%}ZK4&S!!3(VpBFIf&huzo0W(9Gk3;0#8a z2Le~-L7;zPJt&hbhtgsB;`8pbejc16CjnA>;dLM!vwjM?{e|_*QMkay9t%!oG_FUW z$`r0ggfbrwPV%W2k>qcJll=XQNb(QX)1#_n!{4_-?3eI;_(c%TFKDMO*@e*lMZqep1fTB$f z&SG@Y#>y=0_&C&_DBAe=6et?@icqAnP@Hk_Z@ehd)c7=+;V?_Ue~cB*gA6BIljD=~ z?u^e4&UQUXDvcJ#r^nA1wpWiGsK36-5@qg$6~Qr zI*oC)lQA?xr$Iu-jd844>;*i7SG*;7wxkVS5P4I4^XbffJed9VVCwP(lPtkWM%eSp=8SJ(Hzk9x4=J8Yiu&OTZL)t2rS+1Xr`uwpB>@__Eq*MTMvli%NcauVEU{r0&ATmr$v0tAenN1Z@W%gV?>YdZD8Ba`NyuFq7eX6aDAE#oCv*tCcS7$a6e$9t zU`G+GC|#r%K~PFUHFU6{sEDE>DkzE~B4Xo*{JyuBz1zK;xh!1h^Z)&Qb9~wFdoyp| zyq(?Ky9-$$5M1aITmr#`S1GtOWSKy4g-h@?2(GwF!POya1cGZ_f^R}_?Nth{57{6P z+~gA648cuTDYzwMt3YtOOE3+B+pkh^XUHyr;2xLYehBWlO2Gpm2L*!fxCGya;5%0- zcqrt9^pmsanlU~lWZZhJT?^O$wmOVzfp)DI@}XABLu>$P?{YZgqx5r(M>=0h$OP-s zp8EhUNj6hhwmz{`w%9Bo`BQ7;*+TMX*2r^&+aQ8u?Qpxq~(GQ6agLHS%Xdau;jl&xPb9 zYvf}>a(8RwFNEZt*2rH9$-S+SzY>!BS|cA9lKWdDe=Q^rv_?K5BoDSm{zgb1YK{D@ zkUY#9`8y$bgf;R>A^Bcwki5nkIg60I)*3lT zNPfc_Iao+uZ;c!xByY4v&MG9QSR;oD$(yZ_?LzWaYh;Izyxkf(Oh|sq8aZ4@-f4{- zAtdj%MvfGc_gW)I3Ca7dk+TWO2d$BvLh?J-$k9Ubd)CO=h2%rl$T33lht|kBgyfH` zk#h>kpI9U35|Tf)M$RoHe`bxGM@T+qjm(AQFRhXD3dzTBnMd|mlcvj ztdYwJ$)VQB<%ML2HF5;zi>xm^}0+6gPmdqJ|WCO8e?f@hkiY0jf zl8Iu;d;v%{5=#~cK(et|GByCoCSu9L0Z29#OBM}4vYA-2SOAjE#gZigkZd8AEERxc zOR;2p0Ftf5l4SyrY%P{77l33Nv1Ek+B-@H5D+M6gPApj^0Lk`Z$!Y;eb`VR}2tcx< zSh8jSlAXkowF8jsES9VrfMgf3Wc>gnyNV?n1|XRvmTVM&WH+&7lK>>UizS-{AlXAK z*&+bRo?^*X0Z8@|OSTC>vbR{WT>z4O#F8BXknAg#>=b}xKe1$&03`d1C6fY>93YnL z9)RRPv1HExBnOEldj}vnSS;B$0LdX@$^HRI4i!rd3_vnjEIBv;$zfv2p#ew^7fTKc zKyrjwazp@=lJmrp2Lq6tFP3~K0LfRxlJ5l| zxj-y=C;-V<#gZQeAh}R1`B4Cpi^P(j1R%LsEcs~wl1s#rp9LVfR4jQc0Lf)y$u9$t zTrQS89)RQuvE+#WBv*7X^{>14{DRA-Q0+VJeZQRE`-d``gua{pUHL}x`}76*8IzlZ9ukm0 zv_@_rB!6U$+%ojz^smh~cKcHcWY^d5hkk;eDPa*xn+f+c(28o8Iy^95_<-a_(4Yvevc@?X}-eTC$ItdaW($(O8= z`wPjJt&s-^$ycnA2a3pc$&Uwmr{^FcImnvl!9sF~HS!Q4In)|?sF3WiMot!zB|nAe z9k5|Sa-=oS!-eE**2p7-FvgD^7y{Br7kett& z=dnU^0c+&@gydLjdENlE;yd`GC zk-1rZ`b9SFciAFY(EnKOP?jYz)Luch9WIpq3vJm$o{+l4ue6cNLgcbyO334x=5o5! zC4R?^T-G6%l~O{cWtz(wQkVFpH*#5&TvkpAc`?&m&Xu~vZ^4nv>g2LYO30i{bGb!dF6i*w|%6uGRP60$baT&74} z;y3BYWodF*BPC>0rn%f9b%|fCBbQakWkO2G_DplRSLzbKYez22k;|GXA$u~-<-1as z_~kotS&>}UN(p%xmz5d$dqC!IlEB}p4E?Rj z$lqj{zlR0>UdzzmYZ>`_MCR`?fxp!m`dgimzsF_%rU?A4$(Blu4d||46$p-sMcNPEK*&QQI zwXfM_Ukh9>=lJIvsrHS#?9&WK);GsQ`|)App8In{ANz`8vPss*R8t>Qz4~~}avzU5 zGwS29jQY6QJ#SvAg2;(d5ETG^)R>kLt|z7}XimsQz}3>K}ij z`ZuFd{m=TSe!d=~`q?z9%kEMA=WkS3+@ms|c^x)EMf^q3ZS&jyzi54sUt>G6xc!OO zu_M?wijJ(}Gw)evgUm0`XN^&Ggz8ar*ricqHhbyxTPZ1G}Tce#!+&sqihh{W#5$&`o8vO zOhKxnV){g&aTZ8*R7rKzNOjao-wiptI}3SY;HVelsGly9oD%w>RgoUvA`LtuAGt&v zO*S}MZg;d!+U#hP>S(XK@98XHaNi-u(J`GlEhY3*zsz3V%uXKWXMUNzy_uao%wtBT z{RQ;4i=nrDyqR4+%&)McnCi)S*T3`&6K7v%QH(R=>k=H8!w`@j>D}q;*{(SH`zAPT zEl+qhE6)DT%2IER!KBr?3~f^#L(90gso@F1JXqVPI)?3X3`=#4q~j7oc!+l7C>~-s zG%L^QI&{n~$Cy;dIFs-Ea^Lr37aZf5m>xBx*w@+sHBX^DRP*#84>fqQbGv)@e8L%S z*pfL1I7>@C*-vh8JmQSdgdNejN@rf|G!D^ zzhiog;~5Y9oen=2<9OZ!pE6EoLO2iC`t>3YH}orlN4WYm4OgplAHmT&)$y{ScZ0R6 zB~B&BOl`!GJW^Ah%_9xUQ9Q~$;*U{1=9)w^nl;-`o^kx(8Xh#}$Z zm_E!$vTD7_#zq zC66{Z&Cav?I$iB@ij0;z9pNnL&#C(cgmbvFvHZZb?%u`l7_E12@EAkya_}6!z1!gG zofC^g+P#rhyEnpLVOSgE*yx$WGwGAKg=W|pZkT~l&Jyx5;(~i+@LTreq#zg1xL`;5 z^S-0QE=O9bV^6AM{|3hvTD=ZWHFd2|x9&mXrI~Y-pZh5eqpW9|MmcNAhwyHU<2_Ft zesSeGQr#JA9L#9#oF`d^JJN>`gCHDoMi_!O+Fycf_ZlatW|uwXy%rC2w7h%j z$LSrO;KX}Uh7PBD%E$9*3jgqY28H}QzowwwxhU1F!;-2GlPm{!+O7IezLMSg`P$XXtEsUfx63JyqZpv_qqL1;e2gc}35m z>7H=AM&POvucYx~cqIeBGOz66>#nNsD%znrc@@K9`?dbxr|Azh~$ucqnb z=G6>3)p_-FotP{(PaV3T7hJ6b)ZjHVD(5u})C8X3riOT^7fsZfyrxFY$7>p>wRkNz z)#0K3Wun&RwKZx1UfV#e!|S-Iksj(lCTd+?SEI)Ax&~@JUe8U9_E0aGsP%b$jar!3 zH&7e!25xFj5B0Jh+=jfN#wyAi8d!-uF`cECi$=VWc3d&u$Z%X^-q>@TdorgACKG34 z)5T<{dw1rhO?Q?v6xVt&VZ}ZDy`l}(TO`<5~5^fQ@&8o<=-Xi+7adL`1$g0S5 z-Xf(uJqfWY^1Qc5oJS;7C=%iulNY>2;yoe`p@<-`FM5lV_K1XA6`A2JQpO_^=@JR6 zsGXFX@FrTmRpw0$`PP&-)$$D|Z^y;BZDBPTOAV_N6IRzFlg%X4j5pI{>hop>ndZE? zNv2V{Ok{EqP0mOv`kcRvsB_;p`7@NFP%x-bzzx!&@0tTJzQ> zl@6K;)}4D{%yt&{ER3*@kbF#+Y{T1VlAU=QgJfIY)+E`@M{GkH}9=^ z9m9JYy!PRJOkP2`5C7pQ9gp{g&I)qpYc=t{9M4`Mm+t3%4dVTHKTrJ4ivBLOHO2nC zzoz&A?{82Xzz3MRYZmP<@1`sA138`#LpLY!fd zE$~D6P_27Y_)tUll6kVZd)gy18ete8rV*av!wiJse7K8%`?TJc*V?&bGt?x*v64em$rQAYQIxnJZQYPl1GrAHcqzQ|eD z5Og}B#3zjAqqWXG%SRhJH-?WfcMd@hdqE?N zF5TeJ?x8141Mxs{+0^n z??L{cHW#b;gNC`7#3%XA-|Je!PUe#}!a6?LKzN8hBm5D!vyZi;3fo|e$Z}_*)L|G+K>BTF&nDj`vdJtm+P?_ilcAfz zULvRgkMc*gPN(um4V`|BKV}XoE$PR!kUq{I*9cqq;|9VL{0a9clTAH~W=rH<+v;`b zPWhpRTr`Zr^;oufWQOcs9?hmmB^{J+rVco}Ud_RN?(my3dAYV*_T2KMRh@o$FojRi zg1MbfF$D8T{-hR6{gP*=&t86|QIakX!dB^$Pw}TT$=&=ZgXB~`)g-y!M{<>q+$!GX8CdrR{Bv<=Lj@Koh<4ZNUkwUt_;T;5q3mt4jP{;pY_^lR9r3{u3hQ#{CTY($N2Mxe!Re6 z(E35wRHmd`uRUt(SMf#uqNeyIf6<^ggU@g&x~?BgdzkgkKJrXo(8+Ppnl?;IyRGJRJ%lh4#Tae~h@bYd2t<=Y9Gmcj;qS5qitAMpuu z`CP4wC;41M7w7SLo-U@Rt+AqQ@V65&T|#WgU?+ku%;)p9E_~1D8@licf5msQOqa16 zoCBpHFwfNnr@xCS_sMsIGu{v^+EMDkO5dk0;0v^#p5_Y-J$;qG>f2M#K6Rs96?;(g z4UkQK%79@Hx=AkS-d`@{3$?!f#1|U+x`;0_O|0qmONz6tJfNnV7%9%y(j&Dch$mY; zd%+avAnDQOv`%pjkRD0P+s%H8u_hwjAui=hwb7sFOAVu6#+UgnCf5#eIbW_3F7V|B!V12^9WK)e zaC0<~BmyU*smo!so_aU)IHUC=fQZq2UbE43(I zc6`EX{58$pzx*|WyVZQP z=8hhSG)>wTr~HD$u{JgAe{redjQSOyu!gT81WrV`568dTQtb?$IXbDuEv9pM}N4UOaAZx}dl@;6;$a=oDt9_h0q+$y+NvYxNk zw6gK_2CWTzgVFyS-SbAiQ9C-CZ!{deiElD_>WMo8Z=13Qy6ra`O~}Rw_?*dB%S7 zW8Lj$zF9kz^Ua1sx9}|{w*`FMZa3y1-KYyqMtd zG-qC{FvH%)eRvq^oR9iWkveV0;}f>>t=jlX@U4dNZR6WqR_7fPIZwTVO{ zdI*o$^0!mM&boWPPug?Ga;@jP`EIS}_4sZ>&-d^>etNz?qn@YV;}Z9LzqOw4m-l?N z*7Lo5uh#Phe6OMB`}jUTJwK39&(qJ^;+`L{*7F1Mo^Q~4zMt>cdY;Jl8+v|#AMn%j zgBkTa{kE34=LfCz{Ghbw;Y|dUr;r{ksco2TyXfiUWe23EI7>c z2!ykc?_2fnn~HC}nD7>!_mXqs6lzW7khe-pk4kRKDj#^O7~a>W=b+*f4)TLqF0|nX z4Y}|(e_P81dN0#;lM{!&!{5;kZO7j+9QrPQ*L5gPT!u%`quF79&u(eYpeMY?-_sO3 z@b?Ug@ALOP&S_GO74xum@)1`|+Jt#N-+S2fAU(ZXy-*wRA$~}6+KC@BIQ@Ws;Bo3M zUmuw?dVrs*X?(~()HJ&A4-FcJ`C);^$37bI2_Nx~G=38Q$iV-Yf9&Q@bKS6tPxyp? zq8-|ue_}ZF2tVR`=%@Ts?a-e5Q^TQ0`BB%Qn4n~>_n-04wBvg7&kV?ZAK_#k&495L=-wYNBNk?-2We96Dmd=BAX8hn1mzcL2Xb?9+^Tst(G zA2%HOHUHXceopWc+Hu4A3Bz&U@NbNgf?Ii?`g`laG(VqepSTvs()@nXr+zNG&GYlA z_F#}$GrXTWl%M*95*uGve7@!1YU3Wszcq~eJN}(<+^$1U@{`)3qxea~p{MvMuTXx^ zzt@f%!@oBi_XGdIC@Bc#QOlt`YB`igEr;@`wNM`Q31xi3X?|K8@O}KWVZcA~AKe3X zUtRpff6@*e&wnx;dWN6T4o!cvBK$$0tBcQ_^idJR`yV(r{LFvWv?lYP4O+kOUwqx3 zZua?&J9jqv!Mo94_z+n%1-YfMSf8``gwlQaP*)2Pm|}Dd^~^Y<(YO5 zTBZAo|D_4e2L2};+M4E zFXERBz5gHopP~2RamG`?*Uq}qQviLODtw98TgqSi{kVx1!^`}#){ABQvY{9M@&8=C z&^})mzS2im{(O-6Ug+1_TU_E&tKEr;318(2PythbuJ9{b*H-f@?yhCqmtbT2xQ%Ju zGd{pZ`)<#DrxSkeJGnl21|b`SY?_PL>6OVz79d$%PH4O66@U{?`BM(|lbDHhJ_P!L z1xXwz?c8Ub6B$SB4Nt^kT@iD=sf!^6q1(7=f}39J>6K|n!9Z}mi3k7mikYG<ZS3J8VZU|ixsXbZhE31tO>izxl03F$=(q)_}JR3mMpS0<7jh~4Bp&8LWbXFN@~ z9@~Vf15Agex{F?!RKtLTiMkSwKZI+fJ@m>%iU1N}>dFD1uACHhB@)a?P4#VhWm1g- z5@qNLeKM>srbi2BHvBQ0MtqlEnTSpxPB$^xbqn+TbYe9A7_AXMpjRehb|Bf^MC52z zVzBNjma`?=tA>~eK7qj9c^&8RYWzn5zG4LIu_3JRbGW9D5kQ}D?9!ZaHvZsc+ z6aJJl+WRDpNzVz5oSObodS%kj1tgby+_>s9MmjhCm|G)$POnVFJV5feiRqF4B0bU^ zf8-kRD|%%j<^_`1P4tfR_m(65{WU~7AAIN2`t>!vGW9Dzko=}df9EIC-+M1a5a@p~=oHg@{6eoxK8gb=?&-hwR>V2?viQN7-Lov{L7Q+Ss(Z3ZfLlV-Jx{Mp zx+Q^>bnAL2>uF1qRSFuVH2n+o%A_9$1R?Z1K(1ZrV6gG{L%c@1NUuz!(m+bPJ7t=z z(^e*{4ESX$LY|X+^&R zI2AO#OZ3X5R}n}>x1N5bgCJJIA1Z02%k;`bstlyEYoM;TkRtF+q4-RS@$(x$3Qt^B zz^p>55wt_7Vp6RNq^hVZ)$oUE8i{rT)l8)7K&qR%;_&IpPr|O$0JDasO6TYrCe;KW z38Jpl#2;#EBsvAxG?8insb%U)v`<&g2)j}n%-WhNoz7~TRO`Hww>uai1@9UdX8vtqGQq{g5#(ffQh(9#cNL0KVnn;O25=~tx z?9-KByt<;@@^z~>f8AZYMWC-)oKD(6HSq7NE4G{ zQy@(>MeRYg^cvj^XfusL1*DmY(Hux~JuD9GyA-f~S^#aKF{muGFfm#JY3X4Y_dvh; zdGZmAq} zFuCmrq@&v{I_mz|c{IBqROSCC; z4N3Szl18E>o@63*1Jcb%GQ81>>Ftg`ch{)2(7T(cJ%HdM&U5C|sNwk9BG2{PML+lB z!Uvg;ly93{w~5i6o^aVy>kd_jo~G{f0@BMJFw;5pqMyew%{N0YI(tdCGwxpWhNs?I zFR0}7Hua(pkUl;^F@K=wqI0CwiTOdii_YQFBMtXvFFIp9yCZk5_C;6vYTcyT)z{R` zen9%UgQYL3{y_U{46052O^g9R2DlkmRHj>0fBIci^rax${Vz=6K-Qu7AZkXZAT(nP=pf7{rZ?M)Es*{6FeHj8|h|fgQJC2_0 z{?qSc?b^c%@G=xiLp3i{EQgxBBm+ryj~Me1(Z=M!Pde(?qJ~l9`_yH3RXiX2`qT7X zSm_@Vj5-b1?Od1W5goLP?ubt5rFIzlI85t5Ri9y|{tpK-+|z$!-~V+MmUqYW;NQQd zw~w*8k4O^tWCXm8(0W33X@sdKBY}(*_vDi0o?P&-H6Se42xtnN;&I3Rm@QDsRZ00F)SG4;i;`?D?lhYIS zK?pslIiYIzpvlQ3Ad`HZm=gAil_|iW@=%#_hMM~)e_Gn%^~Fp+Ieq0Ca{7wpS^Ce< zhx#0*Nt%opP1fQ^)poKeeh&e8$Txn*NwP63lk_lz9@d;tA${27G))2w&9qtDW0qU*%--eZIpB-nr#~893XSFQQ}P$_ubUFK<8=< zs^fD_jCnxjx#B|S$n<^je4z6+29@vmCdMm3Uhy!Dc@%E-iq#fw93;Il=DK!Hji9d? z2zGs7#HbwM?_svHpzBxt3(&g-TF}{RUog5dmdrA=MmmL*RHh}LVBU*mWu5{ zliNi=78%?c&Z~>@r^OnLO3Y#tZ3&PiE}H0Cdnx|BRHIViSZbm!1G3DQYAWiHnXwI- z;4XS?v=Y^DZQtmGj#g2(8ha zP<2^ja`HNm*L|Is5;mKaDM;UiATN#8Bb&cKd!OIDb2{5K`BxUn|iE6x3T8|*D*8)hjeZ47w8-Q%^4Pg2nWQx}wB--+|cC??MoA)42 z{{wOFK_ZPOIrp{pM)ZH9Ha0r>Y&4B+6Oc`=v3Xx>r{GU18jT8giiwsAB-JM*?rZJM z`159sN(FqgiMj>I7GJ8VW@OKdlbrWuN%m{G*3NGEEVmWo+NzD2%JNpzn70Ah<~wHn zEVmth-mX!p*lssbcL3SpLp8777(a<*`7GystsUd<5>Rpx7h`#8Vlu2=YrlmEyro5l zO6gms=%fKj^NEi6ESJMd0o@6qothIWr8`Ydb^+Pt>%^3?Ijl^9_*y%Mzd(DR<-C(R z$F*F=<*+?f(L*c@QtA4T058J zYwcWqqHaFVAx{1V;y%x1H=pO|$F3r_1TSLQn+Ijo8y= zJv*5tCQFel#q4QWdS@A#Wi;BUS>|SW1?}%aK|xvVX+bT5dIa@Gdot*cpug;C!L@^1 z2e(7}Uhr4JC+uk<^+MW(bVU1g$hnZ;?P>P=?N8gEv8Opg9Jw4EZ5c-$M}4&SIv#O6 zjyA<{!0`^+OJNaV+3aayMZ+qGRYN;4Y<$>6w9kgU8nzhihhg7@owTQgHwf<#-Wlzb z@LAz=(Y_hJJA5D7a}g{e$etFFHzGcwEZS}n!y-naof0uC0>?!hiugL>TYFlh9lz+4 zA8o_Pj*(r^J{0+Ug)t?W6if4YH>>_c%Xs9<`@M zJEHSO7eL!Kx^MIVw6mgDMz2QuQ}n;lm+fiUt7LDSy&2k-*|%ihj`qXs-(*L>v;P%i zj|sP@#f*)4BIYTy^J89*dBdKTqfm|tIVz)_m1AWN=;XMNGdL%HlQd_eoSkzfp`Dj= zP0n@pv|O>d%IB(tHZ9kOxjsgFE;q}K@#fB*yJYTow6k)r%ng2?N_i6VG(kHc&$vAI zqg|UPEzfRy8o!5E;nmT0Ps~5bo>m~Gz<~mopMrM$_6FisuzSJb1@A?>uHepsd+cekw%F{kInh2HJ1=$t z+Am{&i9KgeD^$Kv{X&UoQwkj@1b*RKgC9x%ddQ(~8e8{;EB##NiU(mN;ckD_OT>+map7&MmpR z(L&s@N0$h_Oyz2{EP(RRk2dV#EO`Y zirp&?uLzw=l`A!>)D-QiN?R-KK>JChQ+P&uIkRJh=0{%RnJt#_^K7FR<&9Uv>mDqs5Thw z!fJ0;+lcm1wXdro@2eNAUamUys!yywt@^X}v>MfFG_3)>8gJG3pvFh`w1ln+Llck} z30o6BNWi~qK2vjX&1Gmmt$C&<^lOFHimg=yZJ%1>YTb`^X06q=)}sBnHmi+1tbI@I z8ntVo?OA(F?Qv)?)(NWo79{R;K5KI-3B|LOYApgmImr~1Fx(;7G$ z6l_o!?Z5^PG?C4KXi?}=2HMXXoo)1+J*{zEf3T-D>)C8fGsLUe$!32yL*6x?)_h^}C1`gv|ET#9 zds>S^EvmGrj`sByyIbtDr?t%9vP8=`v>&%T-SUh*tyPa!qg$artv+e>W2>L-X|2Or z$F{~iwQkh9TWgG?P4zad+F;$a8QW%Ro9XtnwlB6_(e^d8f3^#67iCXtU$uRU_N~#* zZ~ta{GC|4#Z&_0$lJ87Oht=qnC$GUxGPwT$A`_Arr(0vkV-Q#$VZ|rG3>-Ox}6ZN>~_@2{yK8JRF&jUSCH+n7WwY3-Kuh)rQfAspx zp4R(vpX_~d+SB^<>ocLx1NOAOOZsl^yUm`~FSK9&ezEqn{!RP$?BBO0jLK9W(`;~0CjZWw1Eo;BEAFn5By@_aeLaJlY{;qgt!lGI=JUx@P<4+5f|#{h2N0A!WuCRz|Ty3 zerh_@goStrj;tD|2+Nu-P8=i88`u8raz@-_joz2pz34^>(cgm7yFeXo%fbX~qk`=3 zdS}oL$7KAdHpHH15fU+@puc0h!r6{R`4KdVW^|ly*rzaO2HHk_E62Khq=#cT%WlDg z(TmmN1+kyWa#(a`ba*u!U#D4KWVx=wsqPrn6Up)f%X5`nGe4H)y#~InaRtBVeyx1` zV*JP25Nfde*VqNU8?I2)W(5P#@zyF7pq5!LmKDhaJzbN+o>_W^X}Bkox~O;4H7&8M zcqZ!V+7yD!)-{BpWF~i6@3t!>$t>95Ml zU*{p|!*ZoV5mxaA_|tt-C~uTMcSx(T$~S0;`Y`p-R=t6Kb>9@?8|~K}>bk7@4IZ*_ z*f+zsaVK7pCESG38zXSD{F|dt>n26P7>S$N2Xi#)+{9=YBXYC*VU9|@n;aEmWNwAN zn4{C+7Kn~9LbpnPj8Q7X5^s?x>5$kq!VzI32 zZ5DE4*l)+aqqyMhCfA$2V_CP`F#5(BxLx~ioP}7{<2IcI<4oMnV+hvQglkz$V!dwT z2{BH}?LH3UG8w`8+~%{Q&x~uA)RFbO1ID9|iFP4(%6Ni8J3mt@25&@t-cr1STk zJVxAcaBc2m*~mM1Dvi^5r;k&+O`1NdNBjLa_+lJ z#;lK+CTV57XzGRXkju^LEg? zm^h)h-n=lrpbyBFWKXEP(eg%LPgG`AOkBA`F$t6AkL#-iY>Dhil|t?mGNzG=izkgJ zF52GK{e0+Dl{KcUF=md6jX86CvuB#h9-r(nW{`@HZwC2h(K9NGgjrj3_ zi@U%qWs6kGm{P`=HYzsew4vA-ALyIMmZ z16?b)7~7;`cug_X<47x6#qjD^GR2Sn)82GV|C~lcma4MxnzK>QNY~0P!nUYb1{6y@ zp0vVMEU$fqdsaFw{L)u?sXO6GJSs}ExKWhwYum1$%^uHosC1G< zO0OaMQzj}>l0do7cXi0+QPAyZ_8qId8^pZr(m|n&dQxTH{ z%#>oLG+WR1s5FyA%{$GEsivYP37Su;d8OMvm2Q&AiPFuOaw>9?zzI{%EA0-bw39?n zmUhO}Q_+(IPnvqh^ve>&-d5=+iJ-sq(^F8t^ZKre;x$H5k0jl5RZ)}#(eGl`^Azut zYG1`iU%c0hy{|G-5==c_8MXSIClyIaAT4DjMOpi)yYy#*k(|TX2P!!wG0i9`jepk@ zR7Fz~Ov?#MQN@R_rfI(=Uy~hH=_!e*G5xH()>BkPR1(muN>NjqR%3Xm7D*fU+q5@J zLl%<2@oO0orK-N2KcXTlnS^VJEOGQgpdu>?>{S;6eJ0#*`xRkFRoY6Ts|V{^T0M1D zbS1&P=G3Lx(4GcNe;y*1eXcTC669;iTq8%%VijRYfCI{6igYkN)`he46_JvAj zNvw^Dd9APYgjP|O1UcY@rkOF8=V9zCmC=%5Uuzb7^YpA%k(LBHQ?i<(ZrC?}t+xe0Gs1|`_9x@}@{b|rb(BCmWqh{eI%>vDkUXs)-NG9RB zmLz?RXb+&ezu4m!wIU>wp~vfbx5oPPtD23QJR8P3rDj7i88@U(>Fds1uYOZ2L^3IQ zylzzMsawU^?`l?Vky$a;FEuNYNx7l*OJ9%LO%eCL>kqYJB$K1Z>qfW6diJN9om*^n zjCD=Tj%0FfN?p^}sj}&00Z5zxrxYvm}|Mo4%T8wnFq3g&(6y(biQ8`=44@k|{Ih_sx8*uPrrGl8L${ z))r+*aQgbfw+GPoT1;mDsl_Fkvzxh~ynX8nOwE>LvTm6LMl+Yyv&cN3Uz%aVH}a^@ zmka05JKb;gzg^2MT+Ntpwg|l0Gvw{x>%7+0mPIW#$>e#5?pFA>zTniXNha-q?LqF-IzgJnyrfodc z;uFl{wS@OZacBXy&@RVI+U#oEBA7jbZq#gCs~^3Lsu`3_;4MFc#^=|X*}~LHluYEc zu8CUs+nj1f?|>OK z)?78Ck_o+SYOY>GLbM+=ND0O5I(j1tZ~vCIWmoG}GQE1#Zl_k?C#hMLOzLg7W-0sd z6`1%T5^ddj-cFuw%b}L8WR`EIC2Q=fzI@fpN+$NUT)s5Jj`Sr=-(|ZjG-?|D-=_bP zdk0%CwUQ+hZd@I=+iT-xQ64qJci;?DM(Q6CDW}(?RIYU zHLYe@GRe37nx^cOTvp{*OItGQxAT%V_FZ4zYNjOEnfN{0l z?yvRLu4Y>@*>}upr%c8B%gLdvxc2Tw2U{Vv!X=Y_yRT~R{_Cq;&A4R3@2FKyvyaPi z*Gh+Vy_;FmRz$6L$@F`#mpkF#`kGg>E}8T@Zp~BHYCi}_XLxPh(;K3AkfDw39<}r( zS#T#Tb3B?(B--a~Cj9RRT#O$X3vugzMEnWq~9K z?)Yjz*(|zSSX$KuNlM&F>)+p4^xB{@L6Qh}MQxxAk=#`*t4f3Ns^3K*`4@z zsvP<^!Btk7p)$i%DfRP;$_z`%-^b1RaFj2g2>``H{ix|OLdhYDno?T zQa{J243Q*=Flu*0{m{o~KG!6uN+L-VJzjTnYdq)FQkkMM#c%c0&pj$rB#GiTdUsQu zF`t9#sLCQqn7b(_G8(J#TvShGjLH~G)l@$xsf>{%jHM`Mv^MXgznjlZ4OFF(B+i{Q z=b1GY<2fo(Wsb_6tE#U0xk_b@Byp}PnwhnxZwDRYIjfzmv8p_h1iBsO@@Dl>uRbb! zB*~+y51zA@WoIze97mk~o!E_RO;r(+E9z) z%+_2LBS|i)l#!p)^w{VHNoA2FiBv)Ivoq4OC?tJ{`o^1Lww9_cNm5FWnri*m zC%rbQOp+v$s!bMZ6RonWruvlry?h;QtyPJVWR@yT{!5cFK6;r_*(6CORi-SKDatCl zcd7DxZ&(dmTUD?mIc8jt>UGA&i;9-((|pBj?NwH(tje?^t)C86R!Nd7(;|I0)j52N z{>R!^=_cDcs&XaCth*^8GIOk+lVN>ZXO&$lyE45*dorw;t*go~m0_8lVN?(Gt(VF$ zNrGLMsAuMx=vLQqZ^KI3x~VcI$+BC05^sn8>7`6%nIy?nDZ7fBsqe25z=BdoPq19c#qEMM9NxU068>0Gfr(*8+y1Li~sj?@@ zzB_gDZ-sH`rB7v_B>7b7%jC-pW7gwWN%6#Ga;Rf6@(`cseAqTbRY6H28sny3U!O~m zD=b`Ppd|m8s)X0E64Hv+-cO@y*h?#hNw#EF3?<2^3Sj0JK<}99TSJwFk|b0G@j4eo z%1HMXv6udw!A9F~RTm{G>Ai;4zpqc7)N7;4L`fp5+IRzMV|snmc8v58RZ2qrRXw~u^-vU7y+*2Rlq937kvFJDitA*uZIr5$lGGHfXN6tA+DWz2_54GeZH&rF zm6f;5xj{dRtE`kHV8|&y$8Kt zRZ&TzidMJ6Zd^6hE2+v*NrI|MdJ`)tRRX+s>3$B_wJo(p+a6E_Rg$l&c;2|;DT}pU zR8^Krl2jGdn_N^WbG^5zU2T(8Rh1;HY^5vw##URsvZ_p#B&w>cw?Jj3svy|5R$ z3alh=RUy5xh16fX^&+dXRg$c#$lfAFma^D)8~cc=vXaF0x9Zj3ZhQsSE3L{{Ny4g1 zdka-sst|&0ZDreIs^CiUR~6M8UsN-Sxn6Wt)=H9A72R8`=u$>|Z*xDiJ)x?uB!M%k z0P62Irz%tB)j!Gdq{?2Ey|>+&M&CQA?3E<%Z8xKL)49OwlQC0O36^B>-INr!<5=}F ztTI@Vz^V-2f|qc{m8Ma;wai zB(|#Dw_)X`DkIo-SFz1f1zeKnsxaSLh52gcLoebgyCuo3iui3>#Ay|HZ^JjJ-{zI2 zxyth!kmu|QD{h;kHWHE~yqXi2I`-N&9g@%sVT!T7K~PyM3=u$;iPx5iR}(i`>_s@~ z2GOsoI(lh8tXj-APgPt|pj7VOkhLoby%5&dgkE)3<_g24GWV9vTzrt#{lnI8Utz^; zuc+cH$zgr5tM>YBAS9s|!p3>f3$V&wVWe!zU4F6SdWvndYo)qr0TIGoxRt;`gi8< zE+nBB!lL+7P1e6JZi&idVcgUnS(G`MjY&c;gk`?<9frzeVb}o5BB$`otIe|5i*Q-o zy}n0onJUeq=&6LhAq!d(dLb-JXu|dKtg=}cI+e}0RW@r6r5V0o?g!fnRi!0~?XN1R zzh%zWLlSx+oKej6O06`t*?n7Qw_qDy z$+k`va!IaVP2o_-UfYI65_%zgwK3L1I00U5MAh+EpXIXHi}0(BukW_}O;ycB zfmOMFL)N+^^g{S*bDfUYE4s>ZVMtY$-w|0Z*rr#uZBT_>lJnP6NEGMlHZqdX3*l>x ztzO(!rVGOg@LD6Qc-FIB7JCtXt#S3X5}=glAS9y>Doiwe3*VUlee)25v|Vkc3_cXVw}Z z9sLZTvR@c#mHl^g_6wd{h_`1(MJU;mlqOq^F+|)G82$T&;q;VigE36Dr&G zs1t)^OqmL>1csb)t~0jq6#Ml(uUFB?-L{zTPp@ zPZnxL2*VHXde4B;-z5vZ5Wn8>^1iHi!*sHekJNL(xuReQZn7u4jF-WM!dQ z!dd?;$I$-51_aGzp+T>+fkAJg-OC0A9Yp&D8yx&R3k_bvl7rWw-OYxFRAnPV)}TGY zMrLi!Mr0k!LbE=}Muk4eLPMWpqwNDwD95ld_7t?+*f{&IX#dA1I0mtaj@Q`(j^EjX zVLjNSumfyzcn$VY_`~es@SoTt5gpm15j$CE#6I>|#4l*Cu*V}yu+Yc^_C#bqwBy*6 z$OUNMWKTwZj`nBvR8$NLjVjEhMm>Y}MK(QZFWRH*nQV3znk^rDHd`ySeb{r^W}scp zp3n9f+B570XMPsyEXQ7S_C^?g*NP?3NNvbD}2U|RGQB|t^5N! zTD1cEyy_};tXeGlqS{>cWp%`}dLDMXMm`o=qb&P6p%x2GXv0p_9LYj!KFYqWiTSB{ zh<#V9D?3^1Bs*2775l#KX7)q<0qk_cX!c{nSJ+R9CD@t74eaMewb?I?-e#eV4zaV1 z!&zwKg6!8Ou`IMn8Fs$OQFfu}J?vuh$Jn1O-(Y{Y+|2%MRi9mI^&Y$2>N30BCZ7G* zHi=zs`vkkv?h5;_eJLC3u#8>l@S)AtafFR^oWm}6eA5=x@jF{k=V)7Sm%6r~F3Gl# zu0PmC!h_oZ`w&=Ea7|!`fkg(N0QM0uXYf0~J_eR8q$99TfMpM< z1MCQ}=#bxmeF`i`$XCFQ0*kRf1MD+kx$NVCeGV+Ag9AGTERQ1y*cZTZJL&`b5?EeG zJg~2TamVApjswf@7y;~SVEG*H06PJ!pkpJjZ-5mD%LeRQV1*q20Q(MDY*;m5CxI0S zD-7%uu)<*zfqf6`p0NJFegIZ9Y%#FYz>0@W2lgYdVqqtN{RFIJ*dbtNfRzaE4D4rM zapCoV{Q|61_*`ITft3z_9N4eG;=}g=I|r<6_&Q*}0V@*`1nfMp^5JKJ{SK^LL|I@L zfK`mh1MClA6(U9gy9lguL|0&c0;?23KK=q$HG+Kn4XjGUx4`}ZRz2c9VE+QE7MUN| zC144WS%LizSdGXoz%B!;6;;onpd)abR7uUj&vH zSeKZmfaL?$EoL;Z{J@f8-T+nrSdW;wzzPEEo})6bSYW+!6a-cXSkD~P=fc4H>gl!b0z^R25dmihQNvg>z{KSuoA!q<(vboB(Q;ZY&4E2t@LpgofK4ly1gs^nrwi@@)(Y4&1z!i&8rbyMoWR-ud#>OW zU~Pdt8@m8lJ76!wJ_W2ju;*jX0qX#4M(iD+mkLq;x&WJ1 zi2BzR*v!Ihfh7T(Q#b)wH(;|1UjWt}*u28Wf%O13x5#*4J%PPaqz|xOz~&b%1gtl( zSBr)L>jP{-(f5J%1-7VYDzJXQ78axN_6N447>#!Tu*Jnk02>HwS@ABw1_4`I{8eCs zfvqS$71$79%S)UBHWb*Z5+49d2DY+f2Vld1tu9#`*l=L4m0SyK1hCgj&IUFT*qV|w zj(dTvD@o%R1#E4p62L|Sd$UwDura{iC^Z(?SYR7U^#pbwu=S--izCMY+f)j*IC4C& zjit^4n*c1e)Mvo%2bL0-2iQblTjH_+djQzxILfsLfo+SUT$==JYy1RYlY#As?+ff9 zVB6yl0(%%(TKsxoj{tkCbbVlt0^3zO9@t~Rc9y;b>~UawN`DXR31GX+qyU=&Y+sp$ zz@7xQw=Bi^DPRZ6QkkyZk_4(|{c;zXI5FVDFZH0oXIZ-YHLgeiqpK z<*Col0ei0k&C&C~KBz!*^a8L$71jfL5!m4h^MTC(_F;wdz+M9OafL5|y$tN5ij?;= zfgPzxc|Qx-ClzU(&jxn1BCYc|z&@==eVz;K^NQ5xdB8ra)D+l!U|&?K2<#PL$13dr zwgA{yl~w?I71)=RP6JyA?CVM&0b2y@c;#%s76bdH(m%kK06S476xdQ=-&H;jY#Fd` zt5gKG9N4KU`GKtfcCt!0U@L+BP$d!ADq!DNrM3SWupg_^+FuRqbX8glYk-}pN^9YD zU_Vu*^}80>FI8#%t^@XSRmzt)fc;vP^5sonXRFl!wjS7T)rtb!0PI|~!N4{G`@LE_ zV4HxQueK3b3a~$_EdZ7Z>_Ro1Ya=%U`?DI(wUJwZU93*y*b40L>NJjR!2YWKEU@js z{;fU%*bZR-)Sz*^1?+z{XdG$4F4g!5*iK;o)z}Vf7qH6-!&yY+Zu=1%OX$psMeYH1 zCE+7rdx2$1NMZ4j`&d((t>!Xd`+)`5oC@p!u%Mb}fgJ>vwdO~_-Ub#@s|c`nfZ1zh z1@WgL*k{0U)oBOpb6`2^tN?Zl zSe`o5fPDchcbyZ!z66%H&R$?&0poQi06PvWf8FlDz6O@BE**CQSi!n<+&91q)T;~Z zTVRFi6$SPku-JO{0Xqq-NWHGWP5~=i?=Z0Mf!$MY6R;nE6|G+x*lA$J>*oRXBd}ui zp8@t0u#)vh0XqY%MEzfY{R}Lw{$XIh04vp?FtD@0N;e1r_A9XX29trE16H;{Utqrh zE7RaxVCR9AZ?GTO@4(76tN`o+u!;?H0{a74g@%KGT?AISVRK-A0;|+;2e7|@Rc*Kk z*x$gaG&~RNA7IrRehTbgVAT?v0J{V%Au%4<|A5s z6jIh!0c+A2^AQyeta)S1M^pr`W{r^tQIWt}Hbx#qMFDHk zg!+;VSnI~r7bmb*O-bcj(>(vZ-A5{og&t{i^6$aL)*$H4pfc0*^1XxjE{hB`s>>gl!n;!vI4A_9? zTYwb@*1tt{U?qSJYLOpUNnit8>;qN`*pL>hfW-kD+%gVWJh0@JQNT(A8`|;=urk1g zxBLKDSzyCjQJl*G8`+BDTprknRzCx)0BlsN4}nz#c5iFch^R`y#1bZeUP zD!}e*O>62wp6H168`T)tCU5pwF34`=T5*{1DoFEd0=gTJ=bL{u(rUS?LvKN2keC|)R*?ao=>U*tOKwa zNgP;5U@s=k1J()H%SjIb>kRCrZeIcG0&G^dUBJ2mo7sI2uq0q}x~~A%4cP4N$w)#AYe;-p}s^72DYLX>PyrRV9R^`1#Bp=RlU9hmJDoV zpPayk0bAYsA7I0Qz1HUeU?YIN-lrF^k-*mU-3IJlVC(w63Tzaxwf$m&jRy8+zaU^^ zfW6Vb53sSoHuO&fb|0|y18M;q2W-=TLcqoY+c;n>unE9Y2Xp~;Kd_Vm>wrxJwq?K! zU=IM>JdoDggTS^8r1drl*w%r^flUUsW8iLJ4*}agh}P=Ez|scMT73lATZ5@Dj{@5@ znELV?vRel1l@d3T!`P!{UP1 z1i#LhGc0O4?kd`%X5(IK471^XxXB&2EovrXZ{j6mS)*QooyMYB6m!Bla9B>rZsl0<>9}BkEPO;lRW2UpUReLg3R_tgQ*N+3Gp44}|^F z@s;Da<7>w^`0pzh7FI2+x{l$Mc3fDZ0Ba$@+6%BG0hT7f_6e|e1=wK$cGMROj}Txv z1Xz9nHZlAGJqCEC#UT7K0X9v*ogu(B39z>W*nR=_i2(c77mHv5%r3y30xXXJDeH-h}pF88R474-wNL!{z>?^ z5iG(U;f%-=Q7EE#)FQ?rKd`YZd+ZJD4Q-ArF!tJ^=WO-WL_n+5XM%4UM-?m zmFU%CGE2xTC9{moaxyE(tc0;uq*trRyhdg>{(9%pNj($=n}&l(BvEYCo9+WDb&fo6I|8 z-X-%MnfJ*YBJ%;656K*cv6UxNj{f-(nUBeQLgomWPsto5^Cg+j$b3%b7@04~d`0Fs znXk#5AoC5GZ^?W|<|LU@WWFc!1DVrgekAh~nKNX5Ci4rKvt)iHbB@e!WX_ZMoy-L? ze~`II=1($zk@=glb=ihG6l)R!UTVcskIfN ze-{% zYDT67nZ9I3k{LjzADLt_1IhF!GmOk2nBaGU-({>T{j)p$b6N0m#+rlzYho|OLJoy| zz(Nj(e8fTvkts~32$`Z}?jci*%uX`9$m}Mwhs<6w`^fAkbAU{7G9}2ABvXn^9GM+t z;>o0uDNUvfnX+Wcktt860-1_r-Xc?pOl2}v$W$d$jZAeiHOM58sY#|5nc8IPkf}?i z9+~=N8jxv7CXq}dGL6YJA=8vhGcwJ|v>?-xOe-?2$+RKUmP|V`?a6c?(~(RkGM&kE zA=8yi5}9sfx|7*XW*eCvWO|b6MW#2IK4kim8APTZnf_!3kQqp3Fqt7_hLTApGmOk| zG9$>0By%sBQDjDw8AE0)nfu6$BQu`N1Ty!NnMmdVG7plOL}oIXhsZok<`FWFl6j2G z<7A#7Glk5PWS$~3mCVy*rjeOW<{2{2l6j8I^JHEi^CFoUWL_fkGMSlVW|5gqW)7LT zWag2XPv#Xe3&^}mW+9nHWEPWILS`wMWn`9j$TS{+JDZ4{Z&WbP%?kxU!zC>vt?e! z#xjhJX{%*kHmlX_g&`Zu@seTQqP$at@`ry!iJIKs{qyPfJWuEJJlF3&r@PaEkuVy@ zz&Mx?kS5YZNPx+Z2vcDi%z#;t1jzwuA*I56NP|U?4jGUM%OM+92c(U(7II+&<}Y)toMb#R0iXS_;b`3s%4?$bogR9yY<|fb^5L zLLpF;Qj}7Zmco8G0Egg6KpvB-p$2M!%9P5K%9P545z7mB4ex*v%V#KpZ}1&{z%Td> ze_RUlf$91LV7h*Ax_e0s)=!7okPM8|FMxE&0OseJpOljr zqR#;qx@Vz#7P`-ad?)~($QK8MS@~VC2g-mU`bwyR<4_0n&=8Qp3uicN0v5V&gHGsz ztH8qaQDD6YpBc{*@b}>%Jb`EM65haj_yk`9+N0N;%i`-RGoS-u6Jw=TCRT1GVpUcx zRzo^x&0;O2Ry!}&LAq#NVpm8}yD4^ulx-`WtqI#G%Y{C>C)Uq}ZtD^2C8gUEXIWgW zwK}nS&NbL6v9qK^o8oMaB{`cEwox{d4b@M!R)08*;r`-mgtH1eC|1cUyhWU)SgNx$ h-n7_ui0$UWM)qObc(y_);sM*W!^Jkb@YghR?mviMf6)K{ diff --git a/target/scala-2.12/classes/lsu/lsu_main$.class b/target/scala-2.12/classes/lsu/lsu_main$.class new file mode 100644 index 0000000000000000000000000000000000000000..f06a676f5bbbccc1d51d1f9b6da5537868089624 GIT binary patch literal 3844 zcmbtX30D(W7`-nnffxZnRNR+XLtNrot)W%{t=NFJL0W5DIwUVRI?Tk$M8US!ZrXjb z`|=ZdP8UUwoYNoBAJxr#c&S_IZV+BAxoK(l8r5FI`}cs6@HA<&*(kY+}pO-{>v#nCM@ z=V-PgAWkuJH=zV`OeDrNd$KIhbv|1SnR9I2oaF4TkfCns&VW^rtRw5yn70grWz%MmveREF7NyPExq9sSe4`T;({;5w7_cj*qfg0nzcnojXBj+mgg=3nzPzDw zIU>-I>>VQxeePo%tFSVL2zmq>y`s94y*0~fQm+Zu#-tydNMvf6#<33Tm!KIN=+n8N z6R0HxX=pRDFvJuDmIof@)6b}s(u;;4Rh632IAIlL1mYp@OmIWsMdAEW7wwh zOA0Jo^qyW7TLo4mYrvqQHo0sT*c6Ua(>9Ks*rg(+UD!{>(T%zI55qCS`iSeWC{)7R|Fmk#h3Ep|U6vK;nnMJ?C*3?QRgNo2K z-wX50Puo|abrO#Wfo?gaJ7Yw{uqG2+8m(eD2{vT`YZc6t>zWq(1Xj^=QMYZ!NFOsz z%hB9jLSCl(NnB8qb@C?UUSK5PYc-c}nE@;{y@reT4db{3Lj{^5B}?3M9D{1r9bS+C zIZB;{QjFxHo-|*sXoixMHQ9fq8Cg!*+3TKJ?26i@#?Xi!#oIO|41~McZDvYuTTrUI zH!%EbcwOn=8v^V6?(upftk_D#qj-}nO$OcO8M#`$3U9@518>K%8Cw*;-{tah&B{KP zrN>wXKNyC-6#rymynXoLU?ATgK;C78rwLVM! z5B(Q3hxfI!Ap6C=@F6~m;RAfkUigGto8h){sEjy1!>vvTe9mfe`lP8j6`Ndd^uAEq zv$`oqDpM2E9#sm#1<6|cE*sOR8hrK#V}r6}%e>~u0zZnps?TV)HYK?saIcRKnWnS{ z46R(2e2nF+ik+7ybmg$4KfutN$M@|y_31Zc^7BLvnMI3D?2cd$*Se9(HuK!7$i~*~ zR2wL-5w(4~&)l78^QAl1O`BG%z)FtX=13Q>>MuHn$UUt7&3z#MvDP<8^QugmQund( zSKdVM70=CTP)K~u`?zO-O>TTDCblpi<^3?NBg#6p{XTk?^To4QcozO_<#{Vo^yuZA zz&D%)e9NPW+bc^G*p3~Xv?##tdIPK>Fd}fd#&y|FEImZhbnO*<2m5|u*u^P7T=23Q zXx+hq`p|m3Rxx*Rpx$B*hKo7q7Sn}8K0ejeyMs(U`FN;5K?M5nM~~Xr{q@_(tkqx390t$b!*Nx$2ywQ^ zL{7}}|2mrZ1CqbvnK=w|!btW3^1$%+SrkWjx_G#8`;MJGjk7RkVOLXCItx+6Hopt@ z(@zYmQHH~K9qhS-b!%f`s9jfM5RF0+|;0r(@!7jpgJjeK=6-(H=J@}r_ z5k&C=uWNZXjuxCj4x>1WF}%QI6ra*QhaYKiR8YSZ-rVT1(v=FK0CoGGS_N*OY*30T V)(Vi_+>3C?<&#hh5cr8+@DGCGkJA7E literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class b/target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class new file mode 100644 index 0000000000000000000000000000000000000000..7ee9785978966f7e883d54162cd02ea2a118947b GIT binary patch literal 730 zcmZ`%U279T6g@YeCQX_&*4CWyrkg6%$g__XV5LIBj#i8LH4U10AV}4!S0^O)m~6 zMTlT~?5jw%lhoL7sN2uHu}ze34^!jYFg6d1$O=m2crXPD3e7mRIuX=*3+x?1UX4c4 zM6lZ0?Omw%svRlww*AVx(7x?dP(ZPS49bG)LT3>b!PZ>eOB0OZ(AXv+Zq1}02(qo+ z(+ZYRE2E0KV0}^e^Z0`fPB>Z-4MFbYsCz8f==}#oHLJK*!d0vhY|q0nomiabvRj<5 z@Fe5~PX&$EBDUkC-Eh)!xJAMjaiE<+q0vX_(9_AW@*-9my_jyFsw8yzyjUGr<-hBz z(LAsBwLOo6*D6s%O{XcXJc!f8*N34asSVtVbxlO}t~rb8`?P`snw#U(^B(6lPZ_M> z3QDYOF?-A?j7xi8u=EWppRxXN3fksgaGyluHqVtA4A-&2OgPz1QaOq~V}`N5{~LMv zwYUG3Y~Qi@iM1^5Om`{ZGU3{+X->%YsXoD7Hst9m3t8+i$sms=<1+uujJsEye!)G~ F@DHACp3VRO literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/lsu_main.class b/target/scala-2.12/classes/lsu/lsu_main.class new file mode 100644 index 0000000000000000000000000000000000000000..8100ee87caf3164db855a422bf7218328a8eec98 GIT binary patch literal 773 zcmZuvT~E_s6n;*-uIngca|liW-GBtVppr17&S*LYMlytLfrOyZckAmcDXr<=5%3rI zXS~o0F1+vu_@j)cLr|klPM-Ii^PKN~|MB%3fHf=<>|ii-SY96sKQuvv{E;{jP9Va* zv(r72J!L{CSj<@&^h6*CbIsAiiRIgX{Z1z_cl>@R)G(Gcg3&!wazOZ)rh|tqLAs^Q zuC~fL9F~GzK)9huwPr=XTOO1-0}FI>sT;h6U^RsgRidY;=C1ak_ zx;hpi+mP>L*%L~7taPGb+>@Jrz=5UqMJxOM!0!gq4Z}!@q#kF;T;3e3(2(N43D9{7 zyav|iSes-d#>^KK?w+IgIicV-i@`fWo~b+whyI6Lx**?SvW6*?8LvX8N1;3=XHPzrfu(@4=#Vbow?o^gz+X%=&U3>Mg+8^BLeo}hmK literal 0 HcmV?d00001