IMC DONE

el2_ifu_mem_ctl.anno.json

@@ -34,6 +34,19 @@
       "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_test",
+    "sources":[
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_en",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_tag_array",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wr_valid",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wrdata",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_write_stall",

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -128,6 +128,7 @@ class mem_ctl_bundle extends Bundle with el2_lib{
   val scan_mode = Input(Bool())
   val valids = Output(UInt())
   val tagv_mb_in = Output(UInt())
+  val test = Output(UInt())
 }
 class el2_ifu_mem_ctl extends Module with el2_lib {
   val io = IO(new mem_ctl_bundle)
@@ -712,7 +713,9 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
     }
     val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
     val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
-      Mux((ICACHE_STATUS_BITS == 1).B, io.ic_debug_wr_data(4), io.ic_debug_wr_data(6, 4)), way_status_new)
+      if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new)
+
+  io.test := way_status_new_w_debug
     val way_status_new_ff = withClock(io.free_clk) {
       RegNext(way_status_new_w_debug, 0.U)
     }