Aligner done
This commit is contained in:
waleed-lm
parent
bd59d56b53
commit
9ec833c6da
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@ -20,13 +20,6 @@
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"~RVCExpander|RVCExpander>io_in"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~RVCExpander|RVCExpander>io_legal",
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"sources":[
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"~RVCExpander|RVCExpander>io_in"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~RVCExpander|RVCExpander>io_out_bits",
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@ -48,12 +41,6 @@
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"~RVCExpander|RVCExpander>io_in"
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]
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},
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{
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"class":"logger.LogLevelAnnotation",
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"globalLogLevel":{
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}
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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2694
RVCExpander.fir
2694
RVCExpander.fir
File diff suppressed because it is too large
Load Diff
649
RVCExpander.v
649
RVCExpander.v
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@ -7,11 +7,10 @@ module RVCExpander(
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output [4:0] io_out_rs1,
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output [4:0] io_out_rs2,
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output [4:0] io_out_rs3,
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output io_rvc,
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output io_legal
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output io_rvc
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);
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wire _T_3 = |io_in[12:5]; // @[RVC.scala 58:29]
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wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[RVC.scala 58:20]
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wire _T_3 = |io_in[12:5]; // @[el2_ifu_compress.scala 49:29]
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wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 49:20]
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wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58]
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wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58]
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wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
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@ -19,386 +18,264 @@ module RVCExpander(
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wire [27:0] _T_36 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
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wire [6:0] _T_50 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 29:58]
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wire [26:0] _T_58 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
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wire [26:0] _T_80 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
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wire [26:0] _T_111 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58]
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wire [27:0] _T_138 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58]
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wire [26:0] _T_169 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58]
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wire [26:0] _T_200 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h27}; // @[Cat.scala 29:58]
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wire [6:0] _T_211 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
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wire [11:0] _T_213 = {_T_211,io_in[6:2]}; // @[Cat.scala 29:58]
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wire [31:0] _T_219 = {_T_211,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
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wire [9:0] _T_228 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
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wire [20:0] _T_243 = {_T_228,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58]
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wire [31:0] _T_306 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h1,7'h6f}; // @[Cat.scala 29:58]
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wire [31:0] _T_321 = {_T_211,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
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wire _T_332 = |_T_213; // @[RVC.scala 95:29]
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wire [6:0] _T_333 = _T_332 ? 7'h37 : 7'h3f; // @[RVC.scala 95:20]
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wire [14:0] _T_336 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
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wire [31:0] _T_339 = {_T_336,io_in[6:2],12'h0}; // @[Cat.scala 29:58]
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wire [31:0] _T_343 = {_T_339[31:12],io_in[11:7],_T_333}; // @[Cat.scala 29:58]
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wire _T_351 = io_in[11:7] == 5'h0; // @[RVC.scala 97:14]
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wire _T_353 = io_in[11:7] == 5'h2; // @[RVC.scala 97:27]
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wire _T_354 = _T_351 | _T_353; // @[RVC.scala 97:21]
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wire [6:0] _T_361 = _T_332 ? 7'h13 : 7'h1f; // @[RVC.scala 91:20]
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wire [2:0] _T_364 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
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wire [31:0] _T_379 = {_T_364,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_361}; // @[Cat.scala 29:58]
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wire [31:0] _T_386_bits = _T_354 ? _T_379 : _T_343; // @[RVC.scala 97:10]
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wire [4:0] _T_386_rd = _T_354 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 97:10]
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wire [4:0] _T_386_rs2 = _T_354 ? _T_14 : _T_14; // @[RVC.scala 97:10]
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wire [4:0] _T_386_rs3 = _T_354 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 97:10]
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wire [25:0] _T_397 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
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wire [30:0] _GEN_172 = {{5'd0}, _T_397}; // @[RVC.scala 104:23]
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wire [30:0] _T_409 = _GEN_172 | 31'h40000000; // @[RVC.scala 104:23]
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wire [31:0] _T_422 = {_T_211,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
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wire [2:0] _T_426 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58]
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wire _T_428 = io_in[6:5] == 2'h0; // @[RVC.scala 108:30]
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wire [30:0] _T_429 = _T_428 ? 31'h40000000 : 31'h0; // @[RVC.scala 108:22]
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wire [6:0] _T_431 = io_in[12] ? 7'h3b : 7'h33; // @[RVC.scala 109:22]
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wire [2:0] _GEN_1 = 3'h1 == _T_426 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
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wire [2:0] _GEN_2 = 3'h2 == _T_426 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
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wire [2:0] _GEN_3 = 3'h3 == _T_426 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
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wire [2:0] _GEN_4 = 3'h4 == _T_426 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
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wire [2:0] _GEN_5 = 3'h5 == _T_426 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
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wire [2:0] _GEN_6 = 3'h6 == _T_426 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
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wire [2:0] _GEN_7 = 3'h7 == _T_426 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
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wire [24:0] _T_441 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_431}; // @[Cat.scala 29:58]
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wire [30:0] _GEN_173 = {{6'd0}, _T_441}; // @[RVC.scala 110:43]
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wire [30:0] _T_442 = _GEN_173 | _T_429; // @[RVC.scala 110:43]
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wire [31:0] _T_443_0 = {{6'd0}, _T_397}; // @[RVC.scala 112:19 RVC.scala 112:19]
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wire [31:0] _T_443_1 = {{1'd0}, _T_409}; // @[RVC.scala 112:19 RVC.scala 112:19]
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wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_443_1 : _T_443_0; // @[RVC.scala 27:14]
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wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_422 : _GEN_9; // @[RVC.scala 27:14]
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wire [31:0] _T_443_3 = {{1'd0}, _T_442}; // @[RVC.scala 112:19 RVC.scala 112:19]
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wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_443_3 : _GEN_10; // @[RVC.scala 27:14]
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wire [31:0] _T_533 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
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wire [4:0] _T_542 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
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wire [12:0] _T_551 = {_T_542,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58]
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wire [31:0] _T_600 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
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wire [31:0] _T_667 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
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wire _T_673 = |io_in[11:7]; // @[RVC.scala 118:27]
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wire [6:0] _T_674 = _T_673 ? 7'h3 : 7'h1f; // @[RVC.scala 118:23]
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wire [25:0] _T_683 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
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wire [28:0] _T_699 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
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wire [27:0] _T_714 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_674}; // @[Cat.scala 29:58]
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wire [27:0] _T_729 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
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wire [24:0] _T_739 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
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wire [24:0] _T_750 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
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wire [24:0] _T_761 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
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wire [24:0] _T_763 = {_T_761[24:7],7'h1f}; // @[Cat.scala 29:58]
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wire [24:0] _T_766 = _T_673 ? _T_761 : _T_763; // @[RVC.scala 139:33]
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wire _T_772 = |io_in[6:2]; // @[RVC.scala 140:27]
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wire [31:0] _T_743_bits = {{7'd0}, _T_739}; // @[RVC.scala 26:19 RVC.scala 27:14]
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wire [31:0] _T_770_bits = {{7'd0}, _T_766}; // @[RVC.scala 26:19 RVC.scala 27:14]
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wire [31:0] _T_773_bits = _T_772 ? _T_743_bits : _T_770_bits; // @[RVC.scala 140:22]
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wire [4:0] _T_773_rd = _T_772 ? io_in[11:7] : 5'h0; // @[RVC.scala 140:22]
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wire [4:0] _T_773_rs1 = _T_772 ? 5'h0 : io_in[11:7]; // @[RVC.scala 140:22]
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wire [4:0] _T_773_rs2 = _T_772 ? io_in[6:2] : io_in[6:2]; // @[RVC.scala 140:22]
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wire [4:0] _T_773_rs3 = _T_772 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 140:22]
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wire [24:0] _T_779 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
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wire [24:0] _T_781 = {_T_761[24:7],7'h73}; // @[Cat.scala 29:58]
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wire [24:0] _T_782 = _T_781 | 25'h100000; // @[RVC.scala 142:46]
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wire [24:0] _T_785 = _T_673 ? _T_779 : _T_782; // @[RVC.scala 143:33]
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wire [31:0] _T_755_bits = {{7'd0}, _T_750}; // @[RVC.scala 26:19 RVC.scala 27:14]
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wire [31:0] _T_789_bits = {{7'd0}, _T_785}; // @[RVC.scala 26:19 RVC.scala 27:14]
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wire [31:0] _T_792_bits = _T_772 ? _T_755_bits : _T_789_bits; // @[RVC.scala 144:25]
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wire [4:0] _T_792_rd = _T_772 ? io_in[11:7] : 5'h1; // @[RVC.scala 144:25]
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wire [4:0] _T_792_rs1 = _T_772 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 144:25]
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wire [31:0] _T_794_bits = io_in[12] ? _T_792_bits : _T_773_bits; // @[RVC.scala 145:10]
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wire [4:0] _T_794_rd = io_in[12] ? _T_792_rd : _T_773_rd; // @[RVC.scala 145:10]
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wire [4:0] _T_794_rs1 = io_in[12] ? _T_792_rs1 : _T_773_rs1; // @[RVC.scala 145:10]
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wire [4:0] _T_794_rs2 = io_in[12] ? _T_773_rs2 : _T_773_rs2; // @[RVC.scala 145:10]
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wire [4:0] _T_794_rs3 = io_in[12] ? _T_773_rs3 : _T_773_rs3; // @[RVC.scala 145:10]
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wire [8:0] _T_798 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
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wire [28:0] _T_810 = {_T_798[8:5],io_in[6:2],5'h2,3'h3,_T_798[4:0],7'h27}; // @[Cat.scala 29:58]
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wire [7:0] _T_818 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58]
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wire [27:0] _T_830 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h23}; // @[Cat.scala 29:58]
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wire [27:0] _T_850 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h27}; // @[Cat.scala 29:58]
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wire [4:0] _T_898 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58]
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wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[RVC.scala 26:19 RVC.scala 27:14]
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wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[RVC.scala 26:19 RVC.scala 27:14]
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wire [31:0] _GEN_17 = 5'h1 == _T_898 ? _T_44_bits : _T_24_bits; // @[RVC.scala 203:12]
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wire [4:0] _GEN_18 = 5'h1 == _T_898 ? _T_14 : _T_14; // @[RVC.scala 203:12]
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wire [4:0] _GEN_19 = 5'h1 == _T_898 ? _T_30 : 5'h2; // @[RVC.scala 203:12]
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wire [4:0] _GEN_21 = 5'h1 == _T_898 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 203:12]
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wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[RVC.scala 26:19 RVC.scala 27:14]
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wire [31:0] _GEN_22 = 5'h2 == _T_898 ? _T_66_bits : _GEN_17; // @[RVC.scala 203:12]
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wire [4:0] _GEN_23 = 5'h2 == _T_898 ? _T_14 : _GEN_18; // @[RVC.scala 203:12]
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wire [4:0] _GEN_24 = 5'h2 == _T_898 ? _T_30 : _GEN_19; // @[RVC.scala 203:12]
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wire [4:0] _GEN_26 = 5'h2 == _T_898 ? io_in[31:27] : _GEN_21; // @[RVC.scala 203:12]
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wire [31:0] _T_88_bits = {{5'd0}, _T_80}; // @[RVC.scala 26:19 RVC.scala 27:14]
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wire [31:0] _GEN_27 = 5'h3 == _T_898 ? _T_88_bits : _GEN_22; // @[RVC.scala 203:12]
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wire [4:0] _GEN_28 = 5'h3 == _T_898 ? _T_14 : _GEN_23; // @[RVC.scala 203:12]
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wire [4:0] _GEN_29 = 5'h3 == _T_898 ? _T_30 : _GEN_24; // @[RVC.scala 203:12]
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wire [4:0] _GEN_31 = 5'h3 == _T_898 ? io_in[31:27] : _GEN_26; // @[RVC.scala 203:12]
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wire [31:0] _T_119_bits = {{5'd0}, _T_111}; // @[RVC.scala 26:19 RVC.scala 27:14]
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wire [31:0] _GEN_32 = 5'h4 == _T_898 ? _T_119_bits : _GEN_27; // @[RVC.scala 203:12]
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wire [4:0] _GEN_33 = 5'h4 == _T_898 ? _T_14 : _GEN_28; // @[RVC.scala 203:12]
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wire [4:0] _GEN_34 = 5'h4 == _T_898 ? _T_30 : _GEN_29; // @[RVC.scala 203:12]
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wire [4:0] _GEN_36 = 5'h4 == _T_898 ? io_in[31:27] : _GEN_31; // @[RVC.scala 203:12]
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wire [31:0] _T_146_bits = {{4'd0}, _T_138}; // @[RVC.scala 26:19 RVC.scala 27:14]
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wire [31:0] _GEN_37 = 5'h5 == _T_898 ? _T_146_bits : _GEN_32; // @[RVC.scala 203:12]
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wire [4:0] _GEN_38 = 5'h5 == _T_898 ? _T_14 : _GEN_33; // @[RVC.scala 203:12]
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wire [4:0] _GEN_39 = 5'h5 == _T_898 ? _T_30 : _GEN_34; // @[RVC.scala 203:12]
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wire [4:0] _GEN_41 = 5'h5 == _T_898 ? io_in[31:27] : _GEN_36; // @[RVC.scala 203:12]
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wire [31:0] _T_177_bits = {{5'd0}, _T_169}; // @[RVC.scala 26:19 RVC.scala 27:14]
|
||||
wire [31:0] _GEN_42 = 5'h6 == _T_898 ? _T_177_bits : _GEN_37; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_43 = 5'h6 == _T_898 ? _T_14 : _GEN_38; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_44 = 5'h6 == _T_898 ? _T_30 : _GEN_39; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_46 = 5'h6 == _T_898 ? io_in[31:27] : _GEN_41; // @[RVC.scala 203:12]
|
||||
wire [31:0] _T_208_bits = {{5'd0}, _T_200}; // @[RVC.scala 26:19 RVC.scala 27:14]
|
||||
wire [31:0] _GEN_47 = 5'h7 == _T_898 ? _T_208_bits : _GEN_42; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_48 = 5'h7 == _T_898 ? _T_14 : _GEN_43; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_49 = 5'h7 == _T_898 ? _T_30 : _GEN_44; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_51 = 5'h7 == _T_898 ? io_in[31:27] : _GEN_46; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_52 = 5'h8 == _T_898 ? _T_219 : _GEN_47; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_53 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_48; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_54 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_49; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_55 = 5'h8 == _T_898 ? _T_14 : _GEN_48; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_56 = 5'h8 == _T_898 ? io_in[31:27] : _GEN_51; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_57 = 5'h9 == _T_898 ? _T_306 : _GEN_52; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_58 = 5'h9 == _T_898 ? 5'h1 : _GEN_53; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_59 = 5'h9 == _T_898 ? io_in[11:7] : _GEN_54; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_60 = 5'h9 == _T_898 ? _T_14 : _GEN_55; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_61 = 5'h9 == _T_898 ? io_in[31:27] : _GEN_56; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_62 = 5'ha == _T_898 ? _T_321 : _GEN_57; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_63 = 5'ha == _T_898 ? io_in[11:7] : _GEN_58; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_64 = 5'ha == _T_898 ? 5'h0 : _GEN_59; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_65 = 5'ha == _T_898 ? _T_14 : _GEN_60; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_66 = 5'ha == _T_898 ? io_in[31:27] : _GEN_61; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_67 = 5'hb == _T_898 ? _T_386_bits : _GEN_62; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_68 = 5'hb == _T_898 ? _T_386_rd : _GEN_63; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_69 = 5'hb == _T_898 ? _T_386_rd : _GEN_64; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_70 = 5'hb == _T_898 ? _T_386_rs2 : _GEN_65; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_71 = 5'hb == _T_898 ? _T_386_rs3 : _GEN_66; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_72 = 5'hc == _T_898 ? _GEN_11 : _GEN_67; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_73 = 5'hc == _T_898 ? _T_30 : _GEN_68; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_74 = 5'hc == _T_898 ? _T_30 : _GEN_69; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_75 = 5'hc == _T_898 ? _T_14 : _GEN_70; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_76 = 5'hc == _T_898 ? io_in[31:27] : _GEN_71; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_77 = 5'hd == _T_898 ? _T_533 : _GEN_72; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_78 = 5'hd == _T_898 ? 5'h0 : _GEN_73; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_79 = 5'hd == _T_898 ? _T_30 : _GEN_74; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_80 = 5'hd == _T_898 ? _T_14 : _GEN_75; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_81 = 5'hd == _T_898 ? io_in[31:27] : _GEN_76; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_82 = 5'he == _T_898 ? _T_600 : _GEN_77; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_83 = 5'he == _T_898 ? _T_30 : _GEN_78; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_84 = 5'he == _T_898 ? _T_30 : _GEN_79; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_85 = 5'he == _T_898 ? 5'h0 : _GEN_80; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_86 = 5'he == _T_898 ? io_in[31:27] : _GEN_81; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_87 = 5'hf == _T_898 ? _T_667 : _GEN_82; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_88 = 5'hf == _T_898 ? 5'h0 : _GEN_83; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_89 = 5'hf == _T_898 ? _T_30 : _GEN_84; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_90 = 5'hf == _T_898 ? 5'h0 : _GEN_85; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_91 = 5'hf == _T_898 ? io_in[31:27] : _GEN_86; // @[RVC.scala 203:12]
|
||||
wire [31:0] _T_688_bits = {{6'd0}, _T_683}; // @[RVC.scala 26:19 RVC.scala 27:14]
|
||||
wire [31:0] _GEN_92 = 5'h10 == _T_898 ? _T_688_bits : _GEN_87; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_93 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_88; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_94 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_89; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_95 = 5'h10 == _T_898 ? io_in[6:2] : _GEN_90; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_96 = 5'h10 == _T_898 ? io_in[31:27] : _GEN_91; // @[RVC.scala 203:12]
|
||||
wire [31:0] _T_703_bits = {{3'd0}, _T_699}; // @[RVC.scala 26:19 RVC.scala 27:14]
|
||||
wire [31:0] _GEN_97 = 5'h11 == _T_898 ? _T_703_bits : _GEN_92; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_98 = 5'h11 == _T_898 ? io_in[11:7] : _GEN_93; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_99 = 5'h11 == _T_898 ? 5'h2 : _GEN_94; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_100 = 5'h11 == _T_898 ? io_in[6:2] : _GEN_95; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_101 = 5'h11 == _T_898 ? io_in[31:27] : _GEN_96; // @[RVC.scala 203:12]
|
||||
wire [31:0] _T_718_bits = {{4'd0}, _T_714}; // @[RVC.scala 26:19 RVC.scala 27:14]
|
||||
wire [31:0] _GEN_102 = 5'h12 == _T_898 ? _T_718_bits : _GEN_97; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_103 = 5'h12 == _T_898 ? io_in[11:7] : _GEN_98; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_104 = 5'h12 == _T_898 ? 5'h2 : _GEN_99; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_105 = 5'h12 == _T_898 ? io_in[6:2] : _GEN_100; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_106 = 5'h12 == _T_898 ? io_in[31:27] : _GEN_101; // @[RVC.scala 203:12]
|
||||
wire [31:0] _T_733_bits = {{4'd0}, _T_729}; // @[RVC.scala 26:19 RVC.scala 27:14]
|
||||
wire [31:0] _GEN_107 = 5'h13 == _T_898 ? _T_733_bits : _GEN_102; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_108 = 5'h13 == _T_898 ? io_in[11:7] : _GEN_103; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_109 = 5'h13 == _T_898 ? 5'h2 : _GEN_104; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_110 = 5'h13 == _T_898 ? io_in[6:2] : _GEN_105; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_111 = 5'h13 == _T_898 ? io_in[31:27] : _GEN_106; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_112 = 5'h14 == _T_898 ? _T_794_bits : _GEN_107; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_113 = 5'h14 == _T_898 ? _T_794_rd : _GEN_108; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_114 = 5'h14 == _T_898 ? _T_794_rs1 : _GEN_109; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_115 = 5'h14 == _T_898 ? _T_794_rs2 : _GEN_110; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_116 = 5'h14 == _T_898 ? _T_794_rs3 : _GEN_111; // @[RVC.scala 203:12]
|
||||
wire [31:0] _T_814_bits = {{3'd0}, _T_810}; // @[RVC.scala 26:19 RVC.scala 27:14]
|
||||
wire [31:0] _GEN_117 = 5'h15 == _T_898 ? _T_814_bits : _GEN_112; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_118 = 5'h15 == _T_898 ? io_in[11:7] : _GEN_113; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_119 = 5'h15 == _T_898 ? 5'h2 : _GEN_114; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_120 = 5'h15 == _T_898 ? io_in[6:2] : _GEN_115; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_121 = 5'h15 == _T_898 ? io_in[31:27] : _GEN_116; // @[RVC.scala 203:12]
|
||||
wire [31:0] _T_834_bits = {{4'd0}, _T_830}; // @[RVC.scala 26:19 RVC.scala 27:14]
|
||||
wire [31:0] _GEN_122 = 5'h16 == _T_898 ? _T_834_bits : _GEN_117; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_123 = 5'h16 == _T_898 ? io_in[11:7] : _GEN_118; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_124 = 5'h16 == _T_898 ? 5'h2 : _GEN_119; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_125 = 5'h16 == _T_898 ? io_in[6:2] : _GEN_120; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_126 = 5'h16 == _T_898 ? io_in[31:27] : _GEN_121; // @[RVC.scala 203:12]
|
||||
wire [31:0] _T_854_bits = {{4'd0}, _T_850}; // @[RVC.scala 26:19 RVC.scala 27:14]
|
||||
wire [31:0] _GEN_127 = 5'h17 == _T_898 ? _T_854_bits : _GEN_122; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_128 = 5'h17 == _T_898 ? io_in[11:7] : _GEN_123; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_129 = 5'h17 == _T_898 ? 5'h2 : _GEN_124; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_130 = 5'h17 == _T_898 ? io_in[6:2] : _GEN_125; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_131 = 5'h17 == _T_898 ? io_in[31:27] : _GEN_126; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_132 = 5'h18 == _T_898 ? io_in : _GEN_127; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_133 = 5'h18 == _T_898 ? io_in[11:7] : _GEN_128; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_134 = 5'h18 == _T_898 ? io_in[19:15] : _GEN_129; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_135 = 5'h18 == _T_898 ? io_in[24:20] : _GEN_130; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_136 = 5'h18 == _T_898 ? io_in[31:27] : _GEN_131; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_137 = 5'h19 == _T_898 ? io_in : _GEN_132; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_138 = 5'h19 == _T_898 ? io_in[11:7] : _GEN_133; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_139 = 5'h19 == _T_898 ? io_in[19:15] : _GEN_134; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_140 = 5'h19 == _T_898 ? io_in[24:20] : _GEN_135; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_141 = 5'h19 == _T_898 ? io_in[31:27] : _GEN_136; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_142 = 5'h1a == _T_898 ? io_in : _GEN_137; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_143 = 5'h1a == _T_898 ? io_in[11:7] : _GEN_138; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_144 = 5'h1a == _T_898 ? io_in[19:15] : _GEN_139; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_145 = 5'h1a == _T_898 ? io_in[24:20] : _GEN_140; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_146 = 5'h1a == _T_898 ? io_in[31:27] : _GEN_141; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_147 = 5'h1b == _T_898 ? io_in : _GEN_142; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_148 = 5'h1b == _T_898 ? io_in[11:7] : _GEN_143; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_149 = 5'h1b == _T_898 ? io_in[19:15] : _GEN_144; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_150 = 5'h1b == _T_898 ? io_in[24:20] : _GEN_145; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_151 = 5'h1b == _T_898 ? io_in[31:27] : _GEN_146; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_152 = 5'h1c == _T_898 ? io_in : _GEN_147; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_153 = 5'h1c == _T_898 ? io_in[11:7] : _GEN_148; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_154 = 5'h1c == _T_898 ? io_in[19:15] : _GEN_149; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_155 = 5'h1c == _T_898 ? io_in[24:20] : _GEN_150; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_156 = 5'h1c == _T_898 ? io_in[31:27] : _GEN_151; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_157 = 5'h1d == _T_898 ? io_in : _GEN_152; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_158 = 5'h1d == _T_898 ? io_in[11:7] : _GEN_153; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_159 = 5'h1d == _T_898 ? io_in[19:15] : _GEN_154; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_160 = 5'h1d == _T_898 ? io_in[24:20] : _GEN_155; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_161 = 5'h1d == _T_898 ? io_in[31:27] : _GEN_156; // @[RVC.scala 203:12]
|
||||
wire [31:0] _GEN_162 = 5'h1e == _T_898 ? io_in : _GEN_157; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_163 = 5'h1e == _T_898 ? io_in[11:7] : _GEN_158; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_164 = 5'h1e == _T_898 ? io_in[19:15] : _GEN_159; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_165 = 5'h1e == _T_898 ? io_in[24:20] : _GEN_160; // @[RVC.scala 203:12]
|
||||
wire [4:0] _GEN_166 = 5'h1e == _T_898 ? io_in[31:27] : _GEN_161; // @[RVC.scala 203:12]
|
||||
wire _T_900 = ~io_in[13]; // @[RVC.scala 204:18]
|
||||
wire _T_902 = ~io_in[12]; // @[RVC.scala 204:31]
|
||||
wire _T_903 = _T_900 & _T_902; // @[RVC.scala 204:29]
|
||||
wire _T_905 = _T_903 & io_in[11]; // @[RVC.scala 204:42]
|
||||
wire _T_907 = _T_905 & io_in[1]; // @[RVC.scala 204:54]
|
||||
wire _T_909 = ~io_in[0]; // @[RVC.scala 204:65]
|
||||
wire _T_910 = _T_907 & _T_909; // @[RVC.scala 204:63]
|
||||
wire _T_917 = _T_903 & io_in[6]; // @[RVC.scala 205:32]
|
||||
wire _T_919 = _T_917 & io_in[1]; // @[RVC.scala 205:43]
|
||||
wire _T_922 = _T_919 & _T_909; // @[RVC.scala 205:52]
|
||||
wire _T_923 = _T_910 | _T_922; // @[RVC.scala 204:76]
|
||||
wire _T_925 = ~io_in[15]; // @[RVC.scala 206:8]
|
||||
wire _T_928 = _T_925 & _T_900; // @[RVC.scala 206:19]
|
||||
wire _T_931 = ~io_in[1]; // @[RVC.scala 206:43]
|
||||
wire _T_932 = io_in[11] >> _T_931; // @[RVC.scala 206:42]
|
||||
wire _T_934 = _T_928 & _T_932; // @[RVC.scala 206:32]
|
||||
wire _T_935 = _T_923 | _T_934; // @[RVC.scala 205:65]
|
||||
wire _T_942 = _T_903 & io_in[5]; // @[RVC.scala 207:32]
|
||||
wire _T_944 = _T_942 & io_in[1]; // @[RVC.scala 207:41]
|
||||
wire _T_947 = _T_944 & _T_909; // @[RVC.scala 207:50]
|
||||
wire _T_948 = _T_935 | _T_947; // @[RVC.scala 206:54]
|
||||
wire _T_955 = _T_903 & io_in[10]; // @[RVC.scala 208:32]
|
||||
wire _T_958 = _T_955 & _T_931; // @[RVC.scala 208:42]
|
||||
wire _T_960 = _T_958 & io_in[0]; // @[RVC.scala 208:54]
|
||||
wire _T_961 = _T_948 | _T_960; // @[RVC.scala 207:63]
|
||||
wire _T_968 = _T_928 & io_in[6]; // @[RVC.scala 209:32]
|
||||
wire _T_971 = _T_968 & _T_931; // @[RVC.scala 209:41]
|
||||
wire _T_972 = _T_961 | _T_971; // @[RVC.scala 208:64]
|
||||
wire _T_976 = io_in[15] & _T_902; // @[RVC.scala 209:65]
|
||||
wire _T_979 = _T_976 & _T_931; // @[RVC.scala 209:78]
|
||||
wire _T_981 = _T_979 & io_in[0]; // @[RVC.scala 209:90]
|
||||
wire _T_982 = _T_972 | _T_981; // @[RVC.scala 209:54]
|
||||
wire _T_989 = _T_903 & io_in[9]; // @[RVC.scala 210:32]
|
||||
wire _T_991 = _T_989 & io_in[1]; // @[RVC.scala 210:41]
|
||||
wire _T_994 = _T_991 & _T_909; // @[RVC.scala 210:50]
|
||||
wire _T_995 = _T_982 | _T_994; // @[RVC.scala 209:100]
|
||||
wire _T_999 = _T_902 & io_in[6]; // @[RVC.scala 211:19]
|
||||
wire _T_1002 = _T_999 & _T_931; // @[RVC.scala 211:28]
|
||||
wire _T_1004 = _T_1002 & io_in[0]; // @[RVC.scala 211:40]
|
||||
wire _T_1005 = _T_995 | _T_1004; // @[RVC.scala 210:63]
|
||||
wire _T_1012 = _T_928 & io_in[5]; // @[RVC.scala 212:32]
|
||||
wire _T_1015 = _T_1012 & _T_931; // @[RVC.scala 212:41]
|
||||
wire _T_1016 = _T_1005 | _T_1015; // @[RVC.scala 211:50]
|
||||
wire _T_1023 = _T_903 & io_in[8]; // @[RVC.scala 213:32]
|
||||
wire _T_1025 = _T_1023 & io_in[1]; // @[RVC.scala 213:41]
|
||||
wire _T_1028 = _T_1025 & _T_909; // @[RVC.scala 213:50]
|
||||
wire _T_1029 = _T_1016 | _T_1028; // @[RVC.scala 212:54]
|
||||
wire _T_1033 = _T_902 & io_in[5]; // @[RVC.scala 214:19]
|
||||
wire _T_1036 = _T_1033 & _T_931; // @[RVC.scala 214:28]
|
||||
wire _T_1038 = _T_1036 & io_in[0]; // @[RVC.scala 214:40]
|
||||
wire _T_1039 = _T_1029 | _T_1038; // @[RVC.scala 213:63]
|
||||
wire _T_1046 = _T_928 & io_in[10]; // @[RVC.scala 215:32]
|
||||
wire _T_1049 = _T_1046 & _T_931; // @[RVC.scala 215:42]
|
||||
wire _T_1050 = _T_1039 | _T_1049; // @[RVC.scala 214:50]
|
||||
wire _T_1057 = _T_903 & io_in[7]; // @[RVC.scala 215:82]
|
||||
wire _T_1059 = _T_1057 & io_in[1]; // @[RVC.scala 215:91]
|
||||
wire _T_1062 = _T_1059 & _T_909; // @[RVC.scala 215:100]
|
||||
wire _T_1063 = _T_1050 | _T_1062; // @[RVC.scala 215:55]
|
||||
wire _T_1066 = io_in[12] & io_in[11]; // @[RVC.scala 216:16]
|
||||
wire _T_1068 = ~io_in[10]; // @[RVC.scala 216:28]
|
||||
wire _T_1069 = _T_1066 & _T_1068; // @[RVC.scala 216:26]
|
||||
wire _T_1072 = _T_1069 & _T_931; // @[RVC.scala 216:39]
|
||||
wire _T_1074 = _T_1072 & io_in[0]; // @[RVC.scala 216:51]
|
||||
wire _T_1075 = _T_1063 | _T_1074; // @[RVC.scala 215:113]
|
||||
wire _T_1082 = _T_928 & io_in[9]; // @[RVC.scala 216:88]
|
||||
wire _T_1085 = _T_1082 & _T_931; // @[RVC.scala 216:97]
|
||||
wire _T_1086 = _T_1075 | _T_1085; // @[RVC.scala 216:61]
|
||||
wire _T_1093 = _T_903 & io_in[4]; // @[RVC.scala 217:32]
|
||||
wire _T_1095 = _T_1093 & io_in[1]; // @[RVC.scala 217:41]
|
||||
wire _T_1098 = _T_1095 & _T_909; // @[RVC.scala 217:50]
|
||||
wire _T_1099 = _T_1086 | _T_1098; // @[RVC.scala 216:110]
|
||||
wire _T_1102 = io_in[13] & io_in[12]; // @[RVC.scala 217:74]
|
||||
wire _T_1105 = _T_1102 & _T_931; // @[RVC.scala 217:84]
|
||||
wire _T_1107 = _T_1105 & io_in[0]; // @[RVC.scala 217:96]
|
||||
wire _T_1108 = _T_1099 | _T_1107; // @[RVC.scala 217:63]
|
||||
wire _T_1115 = _T_928 & io_in[8]; // @[RVC.scala 218:32]
|
||||
wire _T_1118 = _T_1115 & _T_931; // @[RVC.scala 218:41]
|
||||
wire _T_1119 = _T_1108 | _T_1118; // @[RVC.scala 217:106]
|
||||
wire _T_1126 = _T_903 & io_in[3]; // @[RVC.scala 218:81]
|
||||
wire _T_1128 = _T_1126 & io_in[1]; // @[RVC.scala 218:90]
|
||||
wire _T_1131 = _T_1128 & _T_909; // @[RVC.scala 218:99]
|
||||
wire _T_1132 = _T_1119 | _T_1131; // @[RVC.scala 218:54]
|
||||
wire _T_1135 = io_in[13] & io_in[4]; // @[RVC.scala 219:16]
|
||||
wire _T_1138 = _T_1135 & _T_931; // @[RVC.scala 219:25]
|
||||
wire _T_1140 = _T_1138 & io_in[0]; // @[RVC.scala 219:37]
|
||||
wire _T_1141 = _T_1132 | _T_1140; // @[RVC.scala 218:112]
|
||||
wire _T_1148 = _T_903 & io_in[2]; // @[RVC.scala 219:74]
|
||||
wire _T_1150 = _T_1148 & io_in[1]; // @[RVC.scala 219:83]
|
||||
wire _T_1153 = _T_1150 & _T_909; // @[RVC.scala 219:92]
|
||||
wire _T_1154 = _T_1141 | _T_1153; // @[RVC.scala 219:47]
|
||||
wire _T_1161 = _T_928 & io_in[7]; // @[RVC.scala 220:32]
|
||||
wire _T_1164 = _T_1161 & _T_931; // @[RVC.scala 220:41]
|
||||
wire _T_1165 = _T_1154 | _T_1164; // @[RVC.scala 219:105]
|
||||
wire _T_1168 = io_in[13] & io_in[3]; // @[RVC.scala 220:65]
|
||||
wire _T_1171 = _T_1168 & _T_931; // @[RVC.scala 220:74]
|
||||
wire _T_1173 = _T_1171 & io_in[0]; // @[RVC.scala 220:86]
|
||||
wire _T_1174 = _T_1165 | _T_1173; // @[RVC.scala 220:54]
|
||||
wire _T_1177 = io_in[13] & io_in[2]; // @[RVC.scala 221:16]
|
||||
wire _T_1180 = _T_1177 & _T_931; // @[RVC.scala 221:25]
|
||||
wire _T_1182 = _T_1180 & io_in[0]; // @[RVC.scala 221:37]
|
||||
wire _T_1183 = _T_1174 | _T_1182; // @[RVC.scala 220:96]
|
||||
wire _T_1187 = io_in[14] & _T_900; // @[RVC.scala 221:58]
|
||||
wire _T_1190 = _T_1187 & _T_931; // @[RVC.scala 221:71]
|
||||
wire _T_1191 = _T_1183 | _T_1190; // @[RVC.scala 221:47]
|
||||
wire _T_1193 = ~io_in[14]; // @[RVC.scala 222:8]
|
||||
wire _T_1196 = _T_1193 & _T_902; // @[RVC.scala 222:19]
|
||||
wire _T_1199 = _T_1196 & _T_931; // @[RVC.scala 222:32]
|
||||
wire _T_1201 = _T_1199 & io_in[0]; // @[RVC.scala 222:44]
|
||||
wire _T_1202 = _T_1191 | _T_1201; // @[RVC.scala 221:84]
|
||||
wire _T_1206 = io_in[15] & _T_900; // @[RVC.scala 222:65]
|
||||
wire _T_1208 = _T_1206 & io_in[12]; // @[RVC.scala 222:78]
|
||||
wire _T_1210 = _T_1208 & io_in[1]; // @[RVC.scala 222:88]
|
||||
wire _T_1213 = _T_1210 & _T_909; // @[RVC.scala 222:97]
|
||||
wire _T_1214 = _T_1202 | _T_1213; // @[RVC.scala 222:54]
|
||||
wire _T_1222 = _T_928 & _T_902; // @[RVC.scala 223:32]
|
||||
wire _T_1224 = _T_1222 & io_in[1]; // @[RVC.scala 223:45]
|
||||
wire _T_1227 = _T_1224 & _T_909; // @[RVC.scala 223:54]
|
||||
wire _T_1228 = _T_1214 | _T_1227; // @[RVC.scala 222:110]
|
||||
wire _T_1235 = _T_928 & io_in[12]; // @[RVC.scala 223:94]
|
||||
wire _T_1238 = _T_1235 & _T_931; // @[RVC.scala 223:104]
|
||||
wire _T_1239 = _T_1228 | _T_1238; // @[RVC.scala 223:67]
|
||||
wire _T_1246 = _T_1187 & _T_909; // @[RVC.scala 224:29]
|
||||
assign io_out_bits = 5'h1f == _T_898 ? io_in : _GEN_162; // @[RVC.scala 203:12]
|
||||
assign io_out_rd = 5'h1f == _T_898 ? io_in[11:7] : _GEN_163; // @[RVC.scala 203:12]
|
||||
assign io_out_rs1 = 5'h1f == _T_898 ? io_in[19:15] : _GEN_164; // @[RVC.scala 203:12]
|
||||
assign io_out_rs2 = 5'h1f == _T_898 ? io_in[24:20] : _GEN_165; // @[RVC.scala 203:12]
|
||||
assign io_out_rs3 = 5'h1f == _T_898 ? io_in[31:27] : _GEN_166; // @[RVC.scala 203:12]
|
||||
assign io_rvc = io_in[1:0] != 2'h3; // @[RVC.scala 201:12]
|
||||
assign io_legal = _T_1239 | _T_1246; // @[RVC.scala 204:14]
|
||||
wire [27:0] _T_78 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_109 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_136 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_167 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_194 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_205 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
|
||||
wire [11:0] _T_207 = {_T_205,io_in[6:2]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_213 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire _T_221 = |io_in[11:7]; // @[el2_ifu_compress.scala 73:24]
|
||||
wire [6:0] _T_222 = _T_221 ? 7'h1b : 7'h1f; // @[el2_ifu_compress.scala 73:20]
|
||||
wire [31:0] _T_233 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],_T_222}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_249 = {_T_205,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire _T_260 = |_T_207; // @[el2_ifu_compress.scala 86:29]
|
||||
wire [6:0] _T_261 = _T_260 ? 7'h37 : 7'h3f; // @[el2_ifu_compress.scala 86:20]
|
||||
wire [14:0] _T_264 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_267 = {_T_264,io_in[6:2],12'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_271 = {_T_267[31:12],io_in[11:7],_T_261}; // @[Cat.scala 29:58]
|
||||
wire _T_279 = io_in[11:7] == 5'h0; // @[el2_ifu_compress.scala 88:14]
|
||||
wire _T_281 = io_in[11:7] == 5'h2; // @[el2_ifu_compress.scala 88:27]
|
||||
wire _T_282 = _T_279 | _T_281; // @[el2_ifu_compress.scala 88:21]
|
||||
wire [6:0] _T_289 = _T_260 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 82:20]
|
||||
wire [2:0] _T_292 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_307 = {_T_292,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_289}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_314_bits = _T_282 ? _T_307 : _T_271; // @[el2_ifu_compress.scala 88:10]
|
||||
wire [4:0] _T_314_rd = _T_282 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 88:10]
|
||||
wire [4:0] _T_314_rs2 = _T_282 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 88:10]
|
||||
wire [4:0] _T_314_rs3 = _T_282 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 88:10]
|
||||
wire [25:0] _T_325 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _GEN_172 = {{5'd0}, _T_325}; // @[el2_ifu_compress.scala 95:23]
|
||||
wire [30:0] _T_337 = _GEN_172 | 31'h40000000; // @[el2_ifu_compress.scala 95:23]
|
||||
wire [31:0] _T_350 = {_T_205,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [2:0] _T_354 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58]
|
||||
wire _T_356 = io_in[6:5] == 2'h0; // @[el2_ifu_compress.scala 99:30]
|
||||
wire [30:0] _T_357 = _T_356 ? 31'h40000000 : 31'h0; // @[el2_ifu_compress.scala 99:22]
|
||||
wire [6:0] _T_359 = io_in[12] ? 7'h3b : 7'h33; // @[el2_ifu_compress.scala 100:22]
|
||||
wire [2:0] _GEN_1 = 3'h1 == _T_354 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_2 = 3'h2 == _T_354 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_3 = 3'h3 == _T_354 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_4 = 3'h4 == _T_354 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_5 = 3'h5 == _T_354 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_6 = 3'h6 == _T_354 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_7 = 3'h7 == _T_354 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_369 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_359}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _GEN_173 = {{6'd0}, _T_369}; // @[el2_ifu_compress.scala 101:43]
|
||||
wire [30:0] _T_370 = _GEN_173 | _T_357; // @[el2_ifu_compress.scala 101:43]
|
||||
wire [31:0] _T_371_0 = {{6'd0}, _T_325}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19]
|
||||
wire [31:0] _T_371_1 = {{1'd0}, _T_337}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19]
|
||||
wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_371_1 : _T_371_0; // @[el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_350 : _GEN_9; // @[el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_371_3 = {{1'd0}, _T_370}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19]
|
||||
wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_371_3 : _GEN_10; // @[el2_ifu_compress.scala 18:14]
|
||||
wire [9:0] _T_383 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
|
||||
wire [20:0] _T_398 = {_T_383,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_461 = {_T_398[20],_T_398[10:1],_T_398[11],_T_398[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_470 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
||||
wire [12:0] _T_479 = {_T_470,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_528 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_595 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_602 = _T_221 ? 7'h3 : 7'h1f; // @[el2_ifu_compress.scala 109:23]
|
||||
wire [25:0] _T_611 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_627 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_642 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_602}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_657 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],_T_602}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_667 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_678 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_689 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_691 = {_T_689[24:7],7'h1f}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_694 = _T_221 ? _T_689 : _T_691; // @[el2_ifu_compress.scala 130:33]
|
||||
wire _T_700 = |io_in[6:2]; // @[el2_ifu_compress.scala 131:27]
|
||||
wire [31:0] _T_671_bits = {{7'd0}, _T_667}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_698_bits = {{7'd0}, _T_694}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_701_bits = _T_700 ? _T_671_bits : _T_698_bits; // @[el2_ifu_compress.scala 131:22]
|
||||
wire [4:0] _T_701_rd = _T_700 ? io_in[11:7] : 5'h0; // @[el2_ifu_compress.scala 131:22]
|
||||
wire [4:0] _T_701_rs1 = _T_700 ? 5'h0 : io_in[11:7]; // @[el2_ifu_compress.scala 131:22]
|
||||
wire [4:0] _T_701_rs2 = _T_700 ? io_in[6:2] : io_in[6:2]; // @[el2_ifu_compress.scala 131:22]
|
||||
wire [4:0] _T_701_rs3 = _T_700 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 131:22]
|
||||
wire [24:0] _T_707 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_709 = {_T_689[24:7],7'h73}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_710 = _T_709 | 25'h100000; // @[el2_ifu_compress.scala 133:46]
|
||||
wire [24:0] _T_713 = _T_221 ? _T_707 : _T_710; // @[el2_ifu_compress.scala 134:33]
|
||||
wire [31:0] _T_683_bits = {{7'd0}, _T_678}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_717_bits = {{7'd0}, _T_713}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_720_bits = _T_700 ? _T_683_bits : _T_717_bits; // @[el2_ifu_compress.scala 135:25]
|
||||
wire [4:0] _T_720_rd = _T_700 ? io_in[11:7] : 5'h1; // @[el2_ifu_compress.scala 135:25]
|
||||
wire [4:0] _T_720_rs1 = _T_700 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 135:25]
|
||||
wire [31:0] _T_722_bits = io_in[12] ? _T_720_bits : _T_701_bits; // @[el2_ifu_compress.scala 136:10]
|
||||
wire [4:0] _T_722_rd = io_in[12] ? _T_720_rd : _T_701_rd; // @[el2_ifu_compress.scala 136:10]
|
||||
wire [4:0] _T_722_rs1 = io_in[12] ? _T_720_rs1 : _T_701_rs1; // @[el2_ifu_compress.scala 136:10]
|
||||
wire [4:0] _T_722_rs2 = io_in[12] ? _T_701_rs2 : _T_701_rs2; // @[el2_ifu_compress.scala 136:10]
|
||||
wire [4:0] _T_722_rs3 = io_in[12] ? _T_701_rs3 : _T_701_rs3; // @[el2_ifu_compress.scala 136:10]
|
||||
wire [8:0] _T_726 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_738 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [7:0] _T_746 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_758 = {_T_746[7:5],io_in[6:2],5'h2,3'h2,_T_746[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_778 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_826 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_17 = 5'h1 == _T_826 ? _T_44_bits : _T_24_bits; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_18 = 5'h1 == _T_826 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_19 = 5'h1 == _T_826 ? _T_30 : 5'h2; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_21 = 5'h1 == _T_826 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_22 = 5'h2 == _T_826 ? _T_66_bits : _GEN_17; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_23 = 5'h2 == _T_826 ? _T_14 : _GEN_18; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_24 = 5'h2 == _T_826 ? _T_30 : _GEN_19; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_26 = 5'h2 == _T_826 ? io_in[31:27] : _GEN_21; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_86_bits = {{4'd0}, _T_78}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_27 = 5'h3 == _T_826 ? _T_86_bits : _GEN_22; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_28 = 5'h3 == _T_826 ? _T_14 : _GEN_23; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_29 = 5'h3 == _T_826 ? _T_30 : _GEN_24; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_31 = 5'h3 == _T_826 ? io_in[31:27] : _GEN_26; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_117_bits = {{5'd0}, _T_109}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_32 = 5'h4 == _T_826 ? _T_117_bits : _GEN_27; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_33 = 5'h4 == _T_826 ? _T_14 : _GEN_28; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_34 = 5'h4 == _T_826 ? _T_30 : _GEN_29; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_36 = 5'h4 == _T_826 ? io_in[31:27] : _GEN_31; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_144_bits = {{4'd0}, _T_136}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_37 = 5'h5 == _T_826 ? _T_144_bits : _GEN_32; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_38 = 5'h5 == _T_826 ? _T_14 : _GEN_33; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_39 = 5'h5 == _T_826 ? _T_30 : _GEN_34; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_41 = 5'h5 == _T_826 ? io_in[31:27] : _GEN_36; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_175_bits = {{5'd0}, _T_167}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_42 = 5'h6 == _T_826 ? _T_175_bits : _GEN_37; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_43 = 5'h6 == _T_826 ? _T_14 : _GEN_38; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_44 = 5'h6 == _T_826 ? _T_30 : _GEN_39; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_46 = 5'h6 == _T_826 ? io_in[31:27] : _GEN_41; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_202_bits = {{4'd0}, _T_194}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_47 = 5'h7 == _T_826 ? _T_202_bits : _GEN_42; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_48 = 5'h7 == _T_826 ? _T_14 : _GEN_43; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_49 = 5'h7 == _T_826 ? _T_30 : _GEN_44; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_51 = 5'h7 == _T_826 ? io_in[31:27] : _GEN_46; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_52 = 5'h8 == _T_826 ? _T_213 : _GEN_47; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_53 = 5'h8 == _T_826 ? io_in[11:7] : _GEN_48; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_54 = 5'h8 == _T_826 ? io_in[11:7] : _GEN_49; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_55 = 5'h8 == _T_826 ? _T_14 : _GEN_48; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_56 = 5'h8 == _T_826 ? io_in[31:27] : _GEN_51; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_57 = 5'h9 == _T_826 ? _T_233 : _GEN_52; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_58 = 5'h9 == _T_826 ? io_in[11:7] : _GEN_53; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_59 = 5'h9 == _T_826 ? io_in[11:7] : _GEN_54; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_60 = 5'h9 == _T_826 ? _T_14 : _GEN_55; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_61 = 5'h9 == _T_826 ? io_in[31:27] : _GEN_56; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_62 = 5'ha == _T_826 ? _T_249 : _GEN_57; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_63 = 5'ha == _T_826 ? io_in[11:7] : _GEN_58; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_64 = 5'ha == _T_826 ? 5'h0 : _GEN_59; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_65 = 5'ha == _T_826 ? _T_14 : _GEN_60; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_66 = 5'ha == _T_826 ? io_in[31:27] : _GEN_61; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_67 = 5'hb == _T_826 ? _T_314_bits : _GEN_62; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_68 = 5'hb == _T_826 ? _T_314_rd : _GEN_63; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_69 = 5'hb == _T_826 ? _T_314_rd : _GEN_64; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_70 = 5'hb == _T_826 ? _T_314_rs2 : _GEN_65; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_71 = 5'hb == _T_826 ? _T_314_rs3 : _GEN_66; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_72 = 5'hc == _T_826 ? _GEN_11 : _GEN_67; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_73 = 5'hc == _T_826 ? _T_30 : _GEN_68; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_74 = 5'hc == _T_826 ? _T_30 : _GEN_69; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_75 = 5'hc == _T_826 ? _T_14 : _GEN_70; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_76 = 5'hc == _T_826 ? io_in[31:27] : _GEN_71; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_77 = 5'hd == _T_826 ? _T_461 : _GEN_72; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_78 = 5'hd == _T_826 ? 5'h0 : _GEN_73; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_79 = 5'hd == _T_826 ? _T_30 : _GEN_74; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_80 = 5'hd == _T_826 ? _T_14 : _GEN_75; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_81 = 5'hd == _T_826 ? io_in[31:27] : _GEN_76; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_82 = 5'he == _T_826 ? _T_528 : _GEN_77; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_83 = 5'he == _T_826 ? _T_30 : _GEN_78; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_84 = 5'he == _T_826 ? _T_30 : _GEN_79; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_85 = 5'he == _T_826 ? 5'h0 : _GEN_80; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_86 = 5'he == _T_826 ? io_in[31:27] : _GEN_81; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_87 = 5'hf == _T_826 ? _T_595 : _GEN_82; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_88 = 5'hf == _T_826 ? 5'h0 : _GEN_83; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_89 = 5'hf == _T_826 ? _T_30 : _GEN_84; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_90 = 5'hf == _T_826 ? 5'h0 : _GEN_85; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_91 = 5'hf == _T_826 ? io_in[31:27] : _GEN_86; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_616_bits = {{6'd0}, _T_611}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_92 = 5'h10 == _T_826 ? _T_616_bits : _GEN_87; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_93 = 5'h10 == _T_826 ? io_in[11:7] : _GEN_88; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_94 = 5'h10 == _T_826 ? io_in[11:7] : _GEN_89; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_95 = 5'h10 == _T_826 ? io_in[6:2] : _GEN_90; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_96 = 5'h10 == _T_826 ? io_in[31:27] : _GEN_91; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_631_bits = {{3'd0}, _T_627}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_97 = 5'h11 == _T_826 ? _T_631_bits : _GEN_92; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_98 = 5'h11 == _T_826 ? io_in[11:7] : _GEN_93; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_99 = 5'h11 == _T_826 ? 5'h2 : _GEN_94; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_100 = 5'h11 == _T_826 ? io_in[6:2] : _GEN_95; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_101 = 5'h11 == _T_826 ? io_in[31:27] : _GEN_96; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_646_bits = {{4'd0}, _T_642}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_102 = 5'h12 == _T_826 ? _T_646_bits : _GEN_97; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_103 = 5'h12 == _T_826 ? io_in[11:7] : _GEN_98; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_104 = 5'h12 == _T_826 ? 5'h2 : _GEN_99; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_105 = 5'h12 == _T_826 ? io_in[6:2] : _GEN_100; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_106 = 5'h12 == _T_826 ? io_in[31:27] : _GEN_101; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_661_bits = {{3'd0}, _T_657}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_107 = 5'h13 == _T_826 ? _T_661_bits : _GEN_102; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_108 = 5'h13 == _T_826 ? io_in[11:7] : _GEN_103; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_109 = 5'h13 == _T_826 ? 5'h2 : _GEN_104; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_110 = 5'h13 == _T_826 ? io_in[6:2] : _GEN_105; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_111 = 5'h13 == _T_826 ? io_in[31:27] : _GEN_106; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_112 = 5'h14 == _T_826 ? _T_722_bits : _GEN_107; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_113 = 5'h14 == _T_826 ? _T_722_rd : _GEN_108; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_114 = 5'h14 == _T_826 ? _T_722_rs1 : _GEN_109; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_115 = 5'h14 == _T_826 ? _T_722_rs2 : _GEN_110; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_116 = 5'h14 == _T_826 ? _T_722_rs3 : _GEN_111; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_742_bits = {{3'd0}, _T_738}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_117 = 5'h15 == _T_826 ? _T_742_bits : _GEN_112; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_118 = 5'h15 == _T_826 ? io_in[11:7] : _GEN_113; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_119 = 5'h15 == _T_826 ? 5'h2 : _GEN_114; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_120 = 5'h15 == _T_826 ? io_in[6:2] : _GEN_115; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_121 = 5'h15 == _T_826 ? io_in[31:27] : _GEN_116; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_762_bits = {{4'd0}, _T_758}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_122 = 5'h16 == _T_826 ? _T_762_bits : _GEN_117; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_123 = 5'h16 == _T_826 ? io_in[11:7] : _GEN_118; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_124 = 5'h16 == _T_826 ? 5'h2 : _GEN_119; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_125 = 5'h16 == _T_826 ? io_in[6:2] : _GEN_120; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_126 = 5'h16 == _T_826 ? io_in[31:27] : _GEN_121; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_782_bits = {{3'd0}, _T_778}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_127 = 5'h17 == _T_826 ? _T_782_bits : _GEN_122; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_128 = 5'h17 == _T_826 ? io_in[11:7] : _GEN_123; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_129 = 5'h17 == _T_826 ? 5'h2 : _GEN_124; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_130 = 5'h17 == _T_826 ? io_in[6:2] : _GEN_125; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_131 = 5'h17 == _T_826 ? io_in[31:27] : _GEN_126; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_132 = 5'h18 == _T_826 ? io_in : _GEN_127; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_133 = 5'h18 == _T_826 ? io_in[11:7] : _GEN_128; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_134 = 5'h18 == _T_826 ? io_in[19:15] : _GEN_129; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_135 = 5'h18 == _T_826 ? io_in[24:20] : _GEN_130; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_136 = 5'h18 == _T_826 ? io_in[31:27] : _GEN_131; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_137 = 5'h19 == _T_826 ? io_in : _GEN_132; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_138 = 5'h19 == _T_826 ? io_in[11:7] : _GEN_133; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_139 = 5'h19 == _T_826 ? io_in[19:15] : _GEN_134; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_140 = 5'h19 == _T_826 ? io_in[24:20] : _GEN_135; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_141 = 5'h19 == _T_826 ? io_in[31:27] : _GEN_136; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_142 = 5'h1a == _T_826 ? io_in : _GEN_137; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_143 = 5'h1a == _T_826 ? io_in[11:7] : _GEN_138; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_144 = 5'h1a == _T_826 ? io_in[19:15] : _GEN_139; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_145 = 5'h1a == _T_826 ? io_in[24:20] : _GEN_140; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_146 = 5'h1a == _T_826 ? io_in[31:27] : _GEN_141; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_147 = 5'h1b == _T_826 ? io_in : _GEN_142; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_148 = 5'h1b == _T_826 ? io_in[11:7] : _GEN_143; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_149 = 5'h1b == _T_826 ? io_in[19:15] : _GEN_144; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_150 = 5'h1b == _T_826 ? io_in[24:20] : _GEN_145; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_151 = 5'h1b == _T_826 ? io_in[31:27] : _GEN_146; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_152 = 5'h1c == _T_826 ? io_in : _GEN_147; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_153 = 5'h1c == _T_826 ? io_in[11:7] : _GEN_148; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_154 = 5'h1c == _T_826 ? io_in[19:15] : _GEN_149; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_155 = 5'h1c == _T_826 ? io_in[24:20] : _GEN_150; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_156 = 5'h1c == _T_826 ? io_in[31:27] : _GEN_151; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_157 = 5'h1d == _T_826 ? io_in : _GEN_152; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_158 = 5'h1d == _T_826 ? io_in[11:7] : _GEN_153; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_159 = 5'h1d == _T_826 ? io_in[19:15] : _GEN_154; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_160 = 5'h1d == _T_826 ? io_in[24:20] : _GEN_155; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_161 = 5'h1d == _T_826 ? io_in[31:27] : _GEN_156; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_162 = 5'h1e == _T_826 ? io_in : _GEN_157; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_163 = 5'h1e == _T_826 ? io_in[11:7] : _GEN_158; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_164 = 5'h1e == _T_826 ? io_in[19:15] : _GEN_159; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_165 = 5'h1e == _T_826 ? io_in[24:20] : _GEN_160; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_166 = 5'h1e == _T_826 ? io_in[31:27] : _GEN_161; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_out_bits = 5'h1f == _T_826 ? io_in : _GEN_162; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_out_rd = 5'h1f == _T_826 ? io_in[11:7] : _GEN_163; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_out_rs1 = 5'h1f == _T_826 ? io_in[19:15] : _GEN_164; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_out_rs2 = 5'h1f == _T_826 ? io_in[24:20] : _GEN_165; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_out_rs3 = 5'h1f == _T_826 ? io_in[31:27] : _GEN_166; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_rvc = io_in[1:0] != 2'h3; // @[el2_ifu_compress.scala 193:12]
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -0,0 +1,48 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_ifu_fb_consume1",
|
||||
"sources":[
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_exu_flush_final",
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_i0_brp_br_error",
|
||||
"sources":[
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_i0_brp_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_ifu_pmu_instr_aligned",
|
||||
"sources":[
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_ifu_fb_consume2",
|
||||
"sources":[
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_exu_flush_final",
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"el2_ifu_aln_ctl"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,883 @@
|
|||
module el2_ifu_compress(
|
||||
input [31:0] io_in,
|
||||
output [31:0] io_out_bits,
|
||||
output [4:0] io_out_rd,
|
||||
output [4:0] io_out_rs1,
|
||||
output [4:0] io_out_rs2,
|
||||
output [4:0] io_out_rs3,
|
||||
output io_rvc
|
||||
);
|
||||
wire _T_3 = |io_in[12:5]; // @[el2_ifu_compress.scala 49:29]
|
||||
wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 49:20]
|
||||
wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58]
|
||||
wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58]
|
||||
wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_30 = {2'h1,io_in[9:7]}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_36 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_50 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_58 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_80 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_111 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_138 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_169 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_200 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_211 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
|
||||
wire [11:0] _T_213 = {_T_211,io_in[6:2]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_219 = {_T_211,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [9:0] _T_228 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
|
||||
wire [20:0] _T_243 = {_T_228,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_306 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h1,7'h6f}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_321 = {_T_211,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire _T_332 = |_T_213; // @[el2_ifu_compress.scala 86:29]
|
||||
wire [6:0] _T_333 = _T_332 ? 7'h37 : 7'h3f; // @[el2_ifu_compress.scala 86:20]
|
||||
wire [14:0] _T_336 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_339 = {_T_336,io_in[6:2],12'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_343 = {_T_339[31:12],io_in[11:7],_T_333}; // @[Cat.scala 29:58]
|
||||
wire _T_351 = io_in[11:7] == 5'h0; // @[el2_ifu_compress.scala 88:14]
|
||||
wire _T_353 = io_in[11:7] == 5'h2; // @[el2_ifu_compress.scala 88:27]
|
||||
wire _T_354 = _T_351 | _T_353; // @[el2_ifu_compress.scala 88:21]
|
||||
wire [6:0] _T_361 = _T_332 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 82:20]
|
||||
wire [2:0] _T_364 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_379 = {_T_364,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_361}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_386_bits = _T_354 ? _T_379 : _T_343; // @[el2_ifu_compress.scala 88:10]
|
||||
wire [4:0] _T_386_rd = _T_354 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 88:10]
|
||||
wire [4:0] _T_386_rs2 = _T_354 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 88:10]
|
||||
wire [4:0] _T_386_rs3 = _T_354 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 88:10]
|
||||
wire [25:0] _T_397 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _GEN_172 = {{5'd0}, _T_397}; // @[el2_ifu_compress.scala 95:23]
|
||||
wire [30:0] _T_409 = _GEN_172 | 31'h40000000; // @[el2_ifu_compress.scala 95:23]
|
||||
wire [31:0] _T_422 = {_T_211,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [2:0] _T_426 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58]
|
||||
wire _T_428 = io_in[6:5] == 2'h0; // @[el2_ifu_compress.scala 99:30]
|
||||
wire [30:0] _T_429 = _T_428 ? 31'h40000000 : 31'h0; // @[el2_ifu_compress.scala 99:22]
|
||||
wire [6:0] _T_431 = io_in[12] ? 7'h3b : 7'h33; // @[el2_ifu_compress.scala 100:22]
|
||||
wire [2:0] _GEN_1 = 3'h1 == _T_426 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_2 = 3'h2 == _T_426 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_3 = 3'h3 == _T_426 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_4 = 3'h4 == _T_426 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_5 = 3'h5 == _T_426 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_6 = 3'h6 == _T_426 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_7 = 3'h7 == _T_426 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_441 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_431}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _GEN_173 = {{6'd0}, _T_441}; // @[el2_ifu_compress.scala 101:43]
|
||||
wire [30:0] _T_442 = _GEN_173 | _T_429; // @[el2_ifu_compress.scala 101:43]
|
||||
wire [31:0] _T_443_0 = {{6'd0}, _T_397}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19]
|
||||
wire [31:0] _T_443_1 = {{1'd0}, _T_409}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19]
|
||||
wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_443_1 : _T_443_0; // @[el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_422 : _GEN_9; // @[el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_443_3 = {{1'd0}, _T_442}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19]
|
||||
wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_443_3 : _GEN_10; // @[el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_533 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_542 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
||||
wire [12:0] _T_551 = {_T_542,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_600 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_667 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
|
||||
wire _T_673 = |io_in[11:7]; // @[el2_ifu_compress.scala 109:27]
|
||||
wire [6:0] _T_674 = _T_673 ? 7'h3 : 7'h1f; // @[el2_ifu_compress.scala 109:23]
|
||||
wire [25:0] _T_683 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_699 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_714 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_674}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_729 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_739 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_750 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_761 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_763 = {_T_761[24:7],7'h1f}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_766 = _T_673 ? _T_761 : _T_763; // @[el2_ifu_compress.scala 130:33]
|
||||
wire _T_772 = |io_in[6:2]; // @[el2_ifu_compress.scala 131:27]
|
||||
wire [31:0] _T_743_bits = {{7'd0}, _T_739}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_770_bits = {{7'd0}, _T_766}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_773_bits = _T_772 ? _T_743_bits : _T_770_bits; // @[el2_ifu_compress.scala 131:22]
|
||||
wire [4:0] _T_773_rd = _T_772 ? io_in[11:7] : 5'h0; // @[el2_ifu_compress.scala 131:22]
|
||||
wire [4:0] _T_773_rs1 = _T_772 ? 5'h0 : io_in[11:7]; // @[el2_ifu_compress.scala 131:22]
|
||||
wire [4:0] _T_773_rs2 = _T_772 ? io_in[6:2] : io_in[6:2]; // @[el2_ifu_compress.scala 131:22]
|
||||
wire [4:0] _T_773_rs3 = _T_772 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 131:22]
|
||||
wire [24:0] _T_779 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_781 = {_T_761[24:7],7'h73}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_782 = _T_781 | 25'h100000; // @[el2_ifu_compress.scala 133:46]
|
||||
wire [24:0] _T_785 = _T_673 ? _T_779 : _T_782; // @[el2_ifu_compress.scala 134:33]
|
||||
wire [31:0] _T_755_bits = {{7'd0}, _T_750}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_789_bits = {{7'd0}, _T_785}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_792_bits = _T_772 ? _T_755_bits : _T_789_bits; // @[el2_ifu_compress.scala 135:25]
|
||||
wire [4:0] _T_792_rd = _T_772 ? io_in[11:7] : 5'h1; // @[el2_ifu_compress.scala 135:25]
|
||||
wire [4:0] _T_792_rs1 = _T_772 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 135:25]
|
||||
wire [31:0] _T_794_bits = io_in[12] ? _T_792_bits : _T_773_bits; // @[el2_ifu_compress.scala 136:10]
|
||||
wire [4:0] _T_794_rd = io_in[12] ? _T_792_rd : _T_773_rd; // @[el2_ifu_compress.scala 136:10]
|
||||
wire [4:0] _T_794_rs1 = io_in[12] ? _T_792_rs1 : _T_773_rs1; // @[el2_ifu_compress.scala 136:10]
|
||||
wire [4:0] _T_794_rs2 = io_in[12] ? _T_773_rs2 : _T_773_rs2; // @[el2_ifu_compress.scala 136:10]
|
||||
wire [4:0] _T_794_rs3 = io_in[12] ? _T_773_rs3 : _T_773_rs3; // @[el2_ifu_compress.scala 136:10]
|
||||
wire [8:0] _T_798 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_810 = {_T_798[8:5],io_in[6:2],5'h2,3'h3,_T_798[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [7:0] _T_818 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_830 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_850 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_898 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_17 = 5'h1 == _T_898 ? _T_44_bits : _T_24_bits; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_18 = 5'h1 == _T_898 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_19 = 5'h1 == _T_898 ? _T_30 : 5'h2; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_21 = 5'h1 == _T_898 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_22 = 5'h2 == _T_898 ? _T_66_bits : _GEN_17; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_23 = 5'h2 == _T_898 ? _T_14 : _GEN_18; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_24 = 5'h2 == _T_898 ? _T_30 : _GEN_19; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_26 = 5'h2 == _T_898 ? io_in[31:27] : _GEN_21; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_88_bits = {{5'd0}, _T_80}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_27 = 5'h3 == _T_898 ? _T_88_bits : _GEN_22; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_28 = 5'h3 == _T_898 ? _T_14 : _GEN_23; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_29 = 5'h3 == _T_898 ? _T_30 : _GEN_24; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_31 = 5'h3 == _T_898 ? io_in[31:27] : _GEN_26; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_119_bits = {{5'd0}, _T_111}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_32 = 5'h4 == _T_898 ? _T_119_bits : _GEN_27; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_33 = 5'h4 == _T_898 ? _T_14 : _GEN_28; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_34 = 5'h4 == _T_898 ? _T_30 : _GEN_29; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_36 = 5'h4 == _T_898 ? io_in[31:27] : _GEN_31; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_146_bits = {{4'd0}, _T_138}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_37 = 5'h5 == _T_898 ? _T_146_bits : _GEN_32; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_38 = 5'h5 == _T_898 ? _T_14 : _GEN_33; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_39 = 5'h5 == _T_898 ? _T_30 : _GEN_34; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_41 = 5'h5 == _T_898 ? io_in[31:27] : _GEN_36; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_177_bits = {{5'd0}, _T_169}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_42 = 5'h6 == _T_898 ? _T_177_bits : _GEN_37; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_43 = 5'h6 == _T_898 ? _T_14 : _GEN_38; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_44 = 5'h6 == _T_898 ? _T_30 : _GEN_39; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_46 = 5'h6 == _T_898 ? io_in[31:27] : _GEN_41; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_208_bits = {{5'd0}, _T_200}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_47 = 5'h7 == _T_898 ? _T_208_bits : _GEN_42; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_48 = 5'h7 == _T_898 ? _T_14 : _GEN_43; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_49 = 5'h7 == _T_898 ? _T_30 : _GEN_44; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_51 = 5'h7 == _T_898 ? io_in[31:27] : _GEN_46; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_52 = 5'h8 == _T_898 ? _T_219 : _GEN_47; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_53 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_48; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_54 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_49; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_55 = 5'h8 == _T_898 ? _T_14 : _GEN_48; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_56 = 5'h8 == _T_898 ? io_in[31:27] : _GEN_51; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_57 = 5'h9 == _T_898 ? _T_306 : _GEN_52; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_58 = 5'h9 == _T_898 ? 5'h1 : _GEN_53; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_59 = 5'h9 == _T_898 ? io_in[11:7] : _GEN_54; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_60 = 5'h9 == _T_898 ? _T_14 : _GEN_55; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_61 = 5'h9 == _T_898 ? io_in[31:27] : _GEN_56; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_62 = 5'ha == _T_898 ? _T_321 : _GEN_57; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_63 = 5'ha == _T_898 ? io_in[11:7] : _GEN_58; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_64 = 5'ha == _T_898 ? 5'h0 : _GEN_59; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_65 = 5'ha == _T_898 ? _T_14 : _GEN_60; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_66 = 5'ha == _T_898 ? io_in[31:27] : _GEN_61; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_67 = 5'hb == _T_898 ? _T_386_bits : _GEN_62; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_68 = 5'hb == _T_898 ? _T_386_rd : _GEN_63; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_69 = 5'hb == _T_898 ? _T_386_rd : _GEN_64; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_70 = 5'hb == _T_898 ? _T_386_rs2 : _GEN_65; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_71 = 5'hb == _T_898 ? _T_386_rs3 : _GEN_66; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_72 = 5'hc == _T_898 ? _GEN_11 : _GEN_67; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_73 = 5'hc == _T_898 ? _T_30 : _GEN_68; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_74 = 5'hc == _T_898 ? _T_30 : _GEN_69; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_75 = 5'hc == _T_898 ? _T_14 : _GEN_70; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_76 = 5'hc == _T_898 ? io_in[31:27] : _GEN_71; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_77 = 5'hd == _T_898 ? _T_533 : _GEN_72; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_78 = 5'hd == _T_898 ? 5'h0 : _GEN_73; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_79 = 5'hd == _T_898 ? _T_30 : _GEN_74; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_80 = 5'hd == _T_898 ? _T_14 : _GEN_75; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_81 = 5'hd == _T_898 ? io_in[31:27] : _GEN_76; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_82 = 5'he == _T_898 ? _T_600 : _GEN_77; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_83 = 5'he == _T_898 ? _T_30 : _GEN_78; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_84 = 5'he == _T_898 ? _T_30 : _GEN_79; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_85 = 5'he == _T_898 ? 5'h0 : _GEN_80; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_86 = 5'he == _T_898 ? io_in[31:27] : _GEN_81; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_87 = 5'hf == _T_898 ? _T_667 : _GEN_82; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_88 = 5'hf == _T_898 ? 5'h0 : _GEN_83; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_89 = 5'hf == _T_898 ? _T_30 : _GEN_84; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_90 = 5'hf == _T_898 ? 5'h0 : _GEN_85; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_91 = 5'hf == _T_898 ? io_in[31:27] : _GEN_86; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_688_bits = {{6'd0}, _T_683}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_92 = 5'h10 == _T_898 ? _T_688_bits : _GEN_87; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_93 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_88; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_94 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_89; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_95 = 5'h10 == _T_898 ? io_in[6:2] : _GEN_90; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_96 = 5'h10 == _T_898 ? io_in[31:27] : _GEN_91; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_703_bits = {{3'd0}, _T_699}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_97 = 5'h11 == _T_898 ? _T_703_bits : _GEN_92; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_98 = 5'h11 == _T_898 ? io_in[11:7] : _GEN_93; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_99 = 5'h11 == _T_898 ? 5'h2 : _GEN_94; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_100 = 5'h11 == _T_898 ? io_in[6:2] : _GEN_95; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_101 = 5'h11 == _T_898 ? io_in[31:27] : _GEN_96; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_718_bits = {{4'd0}, _T_714}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_102 = 5'h12 == _T_898 ? _T_718_bits : _GEN_97; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_103 = 5'h12 == _T_898 ? io_in[11:7] : _GEN_98; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_104 = 5'h12 == _T_898 ? 5'h2 : _GEN_99; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_105 = 5'h12 == _T_898 ? io_in[6:2] : _GEN_100; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_106 = 5'h12 == _T_898 ? io_in[31:27] : _GEN_101; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_733_bits = {{4'd0}, _T_729}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_107 = 5'h13 == _T_898 ? _T_733_bits : _GEN_102; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_108 = 5'h13 == _T_898 ? io_in[11:7] : _GEN_103; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_109 = 5'h13 == _T_898 ? 5'h2 : _GEN_104; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_110 = 5'h13 == _T_898 ? io_in[6:2] : _GEN_105; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_111 = 5'h13 == _T_898 ? io_in[31:27] : _GEN_106; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_112 = 5'h14 == _T_898 ? _T_794_bits : _GEN_107; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_113 = 5'h14 == _T_898 ? _T_794_rd : _GEN_108; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_114 = 5'h14 == _T_898 ? _T_794_rs1 : _GEN_109; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_115 = 5'h14 == _T_898 ? _T_794_rs2 : _GEN_110; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_116 = 5'h14 == _T_898 ? _T_794_rs3 : _GEN_111; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_814_bits = {{3'd0}, _T_810}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_117 = 5'h15 == _T_898 ? _T_814_bits : _GEN_112; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_118 = 5'h15 == _T_898 ? io_in[11:7] : _GEN_113; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_119 = 5'h15 == _T_898 ? 5'h2 : _GEN_114; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_120 = 5'h15 == _T_898 ? io_in[6:2] : _GEN_115; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_121 = 5'h15 == _T_898 ? io_in[31:27] : _GEN_116; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_834_bits = {{4'd0}, _T_830}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_122 = 5'h16 == _T_898 ? _T_834_bits : _GEN_117; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_123 = 5'h16 == _T_898 ? io_in[11:7] : _GEN_118; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_124 = 5'h16 == _T_898 ? 5'h2 : _GEN_119; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_125 = 5'h16 == _T_898 ? io_in[6:2] : _GEN_120; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_126 = 5'h16 == _T_898 ? io_in[31:27] : _GEN_121; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _T_854_bits = {{4'd0}, _T_850}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
|
||||
wire [31:0] _GEN_127 = 5'h17 == _T_898 ? _T_854_bits : _GEN_122; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_128 = 5'h17 == _T_898 ? io_in[11:7] : _GEN_123; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_129 = 5'h17 == _T_898 ? 5'h2 : _GEN_124; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_130 = 5'h17 == _T_898 ? io_in[6:2] : _GEN_125; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_131 = 5'h17 == _T_898 ? io_in[31:27] : _GEN_126; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_132 = 5'h18 == _T_898 ? io_in : _GEN_127; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_133 = 5'h18 == _T_898 ? io_in[11:7] : _GEN_128; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_134 = 5'h18 == _T_898 ? io_in[19:15] : _GEN_129; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_135 = 5'h18 == _T_898 ? io_in[24:20] : _GEN_130; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_136 = 5'h18 == _T_898 ? io_in[31:27] : _GEN_131; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_137 = 5'h19 == _T_898 ? io_in : _GEN_132; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_138 = 5'h19 == _T_898 ? io_in[11:7] : _GEN_133; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_139 = 5'h19 == _T_898 ? io_in[19:15] : _GEN_134; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_140 = 5'h19 == _T_898 ? io_in[24:20] : _GEN_135; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_141 = 5'h19 == _T_898 ? io_in[31:27] : _GEN_136; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_142 = 5'h1a == _T_898 ? io_in : _GEN_137; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_143 = 5'h1a == _T_898 ? io_in[11:7] : _GEN_138; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_144 = 5'h1a == _T_898 ? io_in[19:15] : _GEN_139; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_145 = 5'h1a == _T_898 ? io_in[24:20] : _GEN_140; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_146 = 5'h1a == _T_898 ? io_in[31:27] : _GEN_141; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_147 = 5'h1b == _T_898 ? io_in : _GEN_142; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_148 = 5'h1b == _T_898 ? io_in[11:7] : _GEN_143; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_149 = 5'h1b == _T_898 ? io_in[19:15] : _GEN_144; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_150 = 5'h1b == _T_898 ? io_in[24:20] : _GEN_145; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_151 = 5'h1b == _T_898 ? io_in[31:27] : _GEN_146; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_152 = 5'h1c == _T_898 ? io_in : _GEN_147; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_153 = 5'h1c == _T_898 ? io_in[11:7] : _GEN_148; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_154 = 5'h1c == _T_898 ? io_in[19:15] : _GEN_149; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_155 = 5'h1c == _T_898 ? io_in[24:20] : _GEN_150; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_156 = 5'h1c == _T_898 ? io_in[31:27] : _GEN_151; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_157 = 5'h1d == _T_898 ? io_in : _GEN_152; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_158 = 5'h1d == _T_898 ? io_in[11:7] : _GEN_153; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_159 = 5'h1d == _T_898 ? io_in[19:15] : _GEN_154; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_160 = 5'h1d == _T_898 ? io_in[24:20] : _GEN_155; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_161 = 5'h1d == _T_898 ? io_in[31:27] : _GEN_156; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [31:0] _GEN_162 = 5'h1e == _T_898 ? io_in : _GEN_157; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_163 = 5'h1e == _T_898 ? io_in[11:7] : _GEN_158; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_164 = 5'h1e == _T_898 ? io_in[19:15] : _GEN_159; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_165 = 5'h1e == _T_898 ? io_in[24:20] : _GEN_160; // @[el2_ifu_compress.scala 195:12]
|
||||
wire [4:0] _GEN_166 = 5'h1e == _T_898 ? io_in[31:27] : _GEN_161; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_out_bits = 5'h1f == _T_898 ? io_in : _GEN_162; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_out_rd = 5'h1f == _T_898 ? io_in[11:7] : _GEN_163; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_out_rs1 = 5'h1f == _T_898 ? io_in[19:15] : _GEN_164; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_out_rs2 = 5'h1f == _T_898 ? io_in[24:20] : _GEN_165; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_out_rs3 = 5'h1f == _T_898 ? io_in[31:27] : _GEN_166; // @[el2_ifu_compress.scala 195:12]
|
||||
assign io_rvc = io_in[1:0] != 2'h3; // @[el2_ifu_compress.scala 193:12]
|
||||
endmodule
|
||||
module el2_ifu_aln_ctl(
|
||||
input clock,
|
||||
input reset,
|
||||
input io_scan_mode,
|
||||
input io_ifu_async_error_start,
|
||||
input io_iccm_rd_ecc_double_err,
|
||||
input io_ic_access_fault_f,
|
||||
input [1:0] io_ic_access_fault_type_f,
|
||||
input [7:0] io_ifu_bp_fghr_f,
|
||||
input [31:0] io_ifu_bp_btb_target_f,
|
||||
input [11:0] io_ifu_bp_poffset_f,
|
||||
input [1:0] io_ifu_bp_hist0_f,
|
||||
input [1:0] io_ifu_bp_hist1_f,
|
||||
input [1:0] io_ifu_bp_pc4_f,
|
||||
input [1:0] io_ifu_bp_way_f,
|
||||
input [1:0] io_ifu_bp_valid_f,
|
||||
input [1:0] io_ifu_bp_ret_f,
|
||||
input io_exu_flush_final,
|
||||
input io_dec_i0_decode_d,
|
||||
input [31:0] io_ifu_fetch_data_f,
|
||||
input [1:0] io_ifu_fetch_val,
|
||||
input [31:0] io_ifu_fetch_pc,
|
||||
output io_ifu_i0_valid,
|
||||
output io_ifu_i0_icaf,
|
||||
output [1:0] io_ifu_i0_icaf_type,
|
||||
output io_ifu_i0_icaf_f1,
|
||||
output io_ifu_i0_dbecc,
|
||||
output [31:0] io_ifu_i0_instr_bits,
|
||||
output [4:0] io_ifu_i0_instr_rd,
|
||||
output [4:0] io_ifu_i0_instr_rs1,
|
||||
output [4:0] io_ifu_i0_instr_rs2,
|
||||
output [4:0] io_ifu_i0_instr_rs3,
|
||||
output [31:0] io_ifu_i0_pc,
|
||||
output io_ifu_i0_pc4,
|
||||
output io_ifu_fb_consume1,
|
||||
output io_ifu_fb_consume2,
|
||||
output [6:0] io_ifu_i0_bp_index,
|
||||
output [7:0] io_ifu_i0_bp_fghr,
|
||||
output [4:0] io_ifu_i0_bp_btag,
|
||||
output io_ifu_pmu_instr_aligned,
|
||||
output [15:0] io_ifu_i0_cinst,
|
||||
output io_i0_brp_valid,
|
||||
output [11:0] io_i0_brp_toffset,
|
||||
output [1:0] io_i0_brp_hist,
|
||||
output io_i0_brp_br_error,
|
||||
output io_i0_brp_br_start_error,
|
||||
output io_i0_brp_bank,
|
||||
output [31:0] io_i0_brp_prett,
|
||||
output io_i0_brp_way,
|
||||
output io_i0_brp_ret,
|
||||
output [30:0] io_test_out,
|
||||
input [31:0] io_test_in
|
||||
);
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [31:0] _RAND_0;
|
||||
reg [31:0] _RAND_1;
|
||||
reg [31:0] _RAND_2;
|
||||
reg [31:0] _RAND_3;
|
||||
reg [31:0] _RAND_4;
|
||||
reg [31:0] _RAND_5;
|
||||
reg [31:0] _RAND_6;
|
||||
reg [31:0] _RAND_7;
|
||||
reg [31:0] _RAND_8;
|
||||
reg [63:0] _RAND_9;
|
||||
reg [63:0] _RAND_10;
|
||||
reg [63:0] _RAND_11;
|
||||
reg [31:0] _RAND_12;
|
||||
reg [31:0] _RAND_13;
|
||||
reg [31:0] _RAND_14;
|
||||
reg [31:0] _RAND_15;
|
||||
reg [31:0] _RAND_16;
|
||||
reg [31:0] _RAND_17;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire [31:0] decompressed_io_in; // @[el2_ifu_aln_ctl.scala 100:28]
|
||||
wire [31:0] decompressed_io_out_bits; // @[el2_ifu_aln_ctl.scala 100:28]
|
||||
wire [4:0] decompressed_io_out_rd; // @[el2_ifu_aln_ctl.scala 100:28]
|
||||
wire [4:0] decompressed_io_out_rs1; // @[el2_ifu_aln_ctl.scala 100:28]
|
||||
wire [4:0] decompressed_io_out_rs2; // @[el2_ifu_aln_ctl.scala 100:28]
|
||||
wire [4:0] decompressed_io_out_rs3; // @[el2_ifu_aln_ctl.scala 100:28]
|
||||
wire decompressed_io_rvc; // @[el2_ifu_aln_ctl.scala 100:28]
|
||||
reg error_stall; // @[el2_ifu_aln_ctl.scala 90:28]
|
||||
reg [1:0] f0val; // @[el2_ifu_aln_ctl.scala 91:22]
|
||||
wire _T = error_stall | io_ifu_async_error_start; // @[el2_ifu_aln_ctl.scala 92:34]
|
||||
wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_aln_ctl.scala 92:64]
|
||||
wire error_stall_in = _T & _T_1; // @[el2_ifu_aln_ctl.scala 92:62]
|
||||
wire _T_3 = ~error_stall; // @[el2_ifu_aln_ctl.scala 94:39]
|
||||
wire i0_shift = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 94:37]
|
||||
wire _T_7 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 98:58]
|
||||
wire _T_9 = _T_7 & f0val[0]; // @[el2_ifu_aln_ctl.scala 98:68]
|
||||
reg [1:0] rdptr; // @[el2_ifu_aln_ctl.scala 125:22]
|
||||
wire _T_248 = rdptr == 2'h0; // @[el2_ifu_aln_ctl.scala 178:32]
|
||||
reg q1off; // @[el2_ifu_aln_ctl.scala 132:22]
|
||||
wire _T_251 = _T_248 & q1off; // @[Mux.scala 27:72]
|
||||
wire _T_249 = rdptr == 2'h1; // @[el2_ifu_aln_ctl.scala 178:57]
|
||||
reg q2off; // @[el2_ifu_aln_ctl.scala 131:22]
|
||||
wire _T_252 = _T_249 & q2off; // @[Mux.scala 27:72]
|
||||
wire _T_254 = _T_251 | _T_252; // @[Mux.scala 27:72]
|
||||
wire _T_250 = rdptr == 2'h2; // @[el2_ifu_aln_ctl.scala 178:83]
|
||||
reg q0off; // @[el2_ifu_aln_ctl.scala 133:22]
|
||||
wire _T_253 = _T_250 & q0off; // @[Mux.scala 27:72]
|
||||
wire q1ptr = _T_254 | _T_253; // @[Mux.scala 27:72]
|
||||
wire _T_257 = ~q1ptr; // @[el2_ifu_aln_ctl.scala 182:26]
|
||||
wire [1:0] q1sel = {q1ptr,_T_257}; // @[Cat.scala 29:58]
|
||||
wire [2:0] qren = {_T_250,_T_249,_T_248}; // @[Cat.scala 29:58]
|
||||
reg [31:0] q1; // @[Reg.scala 27:20]
|
||||
reg [31:0] q0; // @[Reg.scala 27:20]
|
||||
wire [63:0] _T_317 = {q1,q0}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_324 = qren[0] ? _T_317 : 64'h0; // @[Mux.scala 27:72]
|
||||
reg [31:0] q2; // @[Reg.scala 27:20]
|
||||
wire [63:0] _T_320 = {q2,q1}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_325 = qren[1] ? _T_320 : 64'h0; // @[Mux.scala 27:72]
|
||||
wire [63:0] _T_327 = _T_324 | _T_325; // @[Mux.scala 27:72]
|
||||
wire [63:0] _T_323 = {q0,q2}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_326 = qren[2] ? _T_323 : 64'h0; // @[Mux.scala 27:72]
|
||||
wire [63:0] qeff = _T_327 | _T_326; // @[Mux.scala 27:72]
|
||||
wire [31:0] q1eff = qeff[63:32]; // @[el2_ifu_aln_ctl.scala 225:29]
|
||||
wire [15:0] _T_523 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72]
|
||||
wire [15:0] _T_524 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72]
|
||||
wire [15:0] q1final = _T_523 | _T_524; // @[Mux.scala 27:72]
|
||||
wire _T_243 = _T_248 & q0off; // @[Mux.scala 27:72]
|
||||
wire _T_244 = _T_249 & q1off; // @[Mux.scala 27:72]
|
||||
wire _T_246 = _T_243 | _T_244; // @[Mux.scala 27:72]
|
||||
wire _T_245 = _T_250 & q2off; // @[Mux.scala 27:72]
|
||||
wire q0ptr = _T_246 | _T_245; // @[Mux.scala 27:72]
|
||||
wire _T_256 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 180:26]
|
||||
wire [1:0] q0sel = {q0ptr,_T_256}; // @[Cat.scala 29:58]
|
||||
wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 225:42]
|
||||
wire [31:0] _T_513 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [15:0] _T_514 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _GEN_12 = {{16'd0}, _T_514}; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_515 = _T_513 | _GEN_12; // @[Mux.scala 27:72]
|
||||
wire [15:0] q0final = _T_515[15:0]; // @[el2_ifu_aln_ctl.scala 294:11]
|
||||
wire [31:0] _T_11 = {q1final,q0final}; // @[Cat.scala 29:58]
|
||||
wire [15:0] _T_12 = f0val[0] ? q0final : 16'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_13 = _T_9 ? _T_11 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _GEN_13 = {{16'd0}, _T_12}; // @[Mux.scala 27:72]
|
||||
wire [31:0] aligndata = _GEN_13 | _T_13; // @[Mux.scala 27:72]
|
||||
wire first2B = ~decompressed_io_rvc; // @[el2_ifu_aln_ctl.scala 112:17]
|
||||
reg [54:0] _T_762; // @[Reg.scala 27:20]
|
||||
wire [53:0] misc1 = _T_762[53:0]; // @[el2_ifu_aln_ctl.scala 374:9]
|
||||
reg [54:0] _T_764; // @[Reg.scala 27:20]
|
||||
wire [53:0] misc0 = _T_764[53:0]; // @[el2_ifu_aln_ctl.scala 375:9]
|
||||
wire [107:0] _T_265 = {misc1,misc0}; // @[Cat.scala 29:58]
|
||||
wire [107:0] _T_272 = qren[0] ? _T_265 : 108'h0; // @[Mux.scala 27:72]
|
||||
reg [54:0] _T_760; // @[Reg.scala 27:20]
|
||||
wire [53:0] misc2 = _T_760[53:0]; // @[el2_ifu_aln_ctl.scala 373:9]
|
||||
wire [107:0] _T_268 = {misc2,misc1}; // @[Cat.scala 29:58]
|
||||
wire [107:0] _T_273 = qren[1] ? _T_268 : 108'h0; // @[Mux.scala 27:72]
|
||||
wire [107:0] _T_275 = _T_272 | _T_273; // @[Mux.scala 27:72]
|
||||
wire [107:0] _T_271 = {misc0,misc2}; // @[Cat.scala 29:58]
|
||||
wire [107:0] _T_274 = qren[2] ? _T_271 : 108'h0; // @[Mux.scala 27:72]
|
||||
wire [107:0] misceff = _T_275 | _T_274; // @[Mux.scala 27:72]
|
||||
wire [52:0] misc1eff = misceff[107:55]; // @[el2_ifu_aln_ctl.scala 191:25]
|
||||
wire f1icaf = misc1eff[51]; // @[el2_ifu_aln_ctl.scala 195:21]
|
||||
wire [54:0] misc0eff = misceff[54:0]; // @[el2_ifu_aln_ctl.scala 192:25]
|
||||
wire f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 202:21]
|
||||
wire [1:0] _T_23 = {f1icaf,f0icaf}; // @[Cat.scala 29:58]
|
||||
wire _T_24 = f0val[1] & f0icaf; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_25 = _T_9 ? _T_23 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _GEN_14 = {{1'd0}, _T_24}; // @[Mux.scala 27:72]
|
||||
wire [1:0] alignicaf = _GEN_14 | _T_25; // @[Mux.scala 27:72]
|
||||
wire _T_27 = |alignicaf; // @[el2_ifu_aln_ctl.scala 115:52]
|
||||
wire _T_29 = decompressed_io_rvc & _T_27; // @[Mux.scala 27:72]
|
||||
wire _T_30 = first2B & alignicaf[0]; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_535 = f0val[1] ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
||||
reg [1:0] f1val; // @[el2_ifu_aln_ctl.scala 128:22]
|
||||
wire [1:0] _T_534 = {f1val[0],1'h1}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_536 = _T_9 ? _T_534 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] alignval = _T_535 | _T_536; // @[Mux.scala 27:72]
|
||||
wire _T_35 = decompressed_io_rvc & alignval[1]; // @[Mux.scala 27:72]
|
||||
wire _T_36 = first2B & alignval[0]; // @[Mux.scala 27:72]
|
||||
wire shift_2B = i0_shift & first2B; // @[el2_ifu_aln_ctl.scala 119:27]
|
||||
wire shift_4B = i0_shift & decompressed_io_rvc; // @[el2_ifu_aln_ctl.scala 120:27]
|
||||
wire _T_43 = ~f0val[0]; // @[el2_ifu_aln_ctl.scala 121:80]
|
||||
wire _T_45 = _T_43 & f0val[0]; // @[el2_ifu_aln_ctl.scala 121:90]
|
||||
wire _T_46 = shift_2B & f0val[0]; // @[Mux.scala 27:72]
|
||||
wire _T_47 = shift_4B & _T_45; // @[Mux.scala 27:72]
|
||||
wire f0_shift_2B = _T_46 | _T_47; // @[Mux.scala 27:72]
|
||||
wire _T_52 = f0val[0] & _T_7; // @[el2_ifu_aln_ctl.scala 122:31]
|
||||
wire f1_shift_2B = _T_52 & shift_4B; // @[el2_ifu_aln_ctl.scala 122:43]
|
||||
reg [1:0] wrptr; // @[el2_ifu_aln_ctl.scala 124:22]
|
||||
reg [1:0] f2val; // @[el2_ifu_aln_ctl.scala 127:22]
|
||||
wire _T_449 = f1_shift_2B & f1val[1]; // @[Mux.scala 27:72]
|
||||
wire _T_448 = ~f1_shift_2B; // @[el2_ifu_aln_ctl.scala 281:53]
|
||||
wire [1:0] _T_450 = _T_448 ? f1val : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _GEN_15 = {{1'd0}, _T_449}; // @[Mux.scala 27:72]
|
||||
wire [1:0] sf1val = _GEN_15 | _T_450; // @[Mux.scala 27:72]
|
||||
wire sf1_valid = sf1val[0]; // @[el2_ifu_aln_ctl.scala 247:22]
|
||||
wire _T_54 = ~sf1_valid; // @[el2_ifu_aln_ctl.scala 135:42]
|
||||
wire f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 246:20]
|
||||
wire _T_56 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 135:55]
|
||||
wire ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 256:30]
|
||||
wire _T_61 = _T_54 & f2_valid; // @[el2_ifu_aln_ctl.scala 136:53]
|
||||
wire _T_62 = _T_61 & ifvalid; // @[el2_ifu_aln_ctl.scala 136:65]
|
||||
wire _T_66 = sf1_valid & _T_56; // @[el2_ifu_aln_ctl.scala 137:30]
|
||||
wire _T_67 = _T_66 & ifvalid; // @[el2_ifu_aln_ctl.scala 137:42]
|
||||
wire fetch_to_f1 = _T_62 | _T_67; // @[el2_ifu_aln_ctl.scala 136:77]
|
||||
wire _T_76 = sf1_valid & f2_valid; // @[el2_ifu_aln_ctl.scala 139:53]
|
||||
wire f2_wr_en = _T_76 & ifvalid; // @[el2_ifu_aln_ctl.scala 139:65]
|
||||
wire _T_90 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 147:24]
|
||||
wire _T_91 = _T_90 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:32]
|
||||
wire _T_92 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 147:49]
|
||||
wire _T_93 = _T_92 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:57]
|
||||
wire _T_94 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 147:74]
|
||||
wire _T_95 = _T_94 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:82]
|
||||
wire [2:0] qwen = {_T_91,_T_93,_T_95}; // @[Cat.scala 29:58]
|
||||
wire _T_149 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 157:34]
|
||||
wire _T_153 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 158:34]
|
||||
wire _T_159 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 160:26]
|
||||
wire _T_161 = _T_159 & _T_1; // @[el2_ifu_aln_ctl.scala 160:35]
|
||||
wire [1:0] _T_164 = _T_153 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_166 = _T_161 ? wrptr : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _GEN_18 = {{1'd0}, _T_149}; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_167 = _GEN_18 | _T_164; // @[Mux.scala 27:72]
|
||||
wire [1:0] wrptr_in = _T_167 | _T_166; // @[Mux.scala 27:72]
|
||||
wire _T_172 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 162:26]
|
||||
wire _T_174 = _T_172 & _T_250; // @[el2_ifu_aln_ctl.scala 162:35]
|
||||
wire _T_176 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 162:74]
|
||||
wire _T_180 = _T_172 & _T_249; // @[el2_ifu_aln_ctl.scala 163:35]
|
||||
wire _T_182 = q2off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 163:74]
|
||||
wire _T_186 = _T_172 & _T_248; // @[el2_ifu_aln_ctl.scala 164:35]
|
||||
wire _T_188 = _T_174 & _T_176; // @[Mux.scala 27:72]
|
||||
wire _T_189 = _T_180 & _T_182; // @[Mux.scala 27:72]
|
||||
wire _T_190 = _T_186 & q2off; // @[Mux.scala 27:72]
|
||||
wire _T_191 = _T_188 | _T_189; // @[Mux.scala 27:72]
|
||||
wire q2off_in = _T_191 | _T_190; // @[Mux.scala 27:72]
|
||||
wire _T_195 = ~qwen[1]; // @[el2_ifu_aln_ctl.scala 166:26]
|
||||
wire _T_197 = _T_195 & _T_249; // @[el2_ifu_aln_ctl.scala 166:35]
|
||||
wire _T_199 = q1off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 166:74]
|
||||
wire _T_203 = _T_195 & _T_248; // @[el2_ifu_aln_ctl.scala 167:35]
|
||||
wire _T_205 = q1off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 167:74]
|
||||
wire _T_209 = _T_195 & _T_250; // @[el2_ifu_aln_ctl.scala 168:35]
|
||||
wire _T_211 = _T_197 & _T_199; // @[Mux.scala 27:72]
|
||||
wire _T_212 = _T_203 & _T_205; // @[Mux.scala 27:72]
|
||||
wire _T_213 = _T_209 & q1off; // @[Mux.scala 27:72]
|
||||
wire _T_214 = _T_211 | _T_212; // @[Mux.scala 27:72]
|
||||
wire q1off_in = _T_214 | _T_213; // @[Mux.scala 27:72]
|
||||
wire _T_218 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 170:26]
|
||||
wire _T_220 = _T_218 & _T_248; // @[el2_ifu_aln_ctl.scala 170:35]
|
||||
wire _T_222 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 170:76]
|
||||
wire _T_226 = _T_218 & _T_250; // @[el2_ifu_aln_ctl.scala 171:35]
|
||||
wire _T_228 = q0off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 171:76]
|
||||
wire _T_232 = _T_218 & _T_249; // @[el2_ifu_aln_ctl.scala 172:35]
|
||||
wire _T_234 = _T_220 & _T_222; // @[Mux.scala 27:72]
|
||||
wire _T_235 = _T_226 & _T_228; // @[Mux.scala 27:72]
|
||||
wire _T_236 = _T_232 & q0off; // @[Mux.scala 27:72]
|
||||
wire _T_237 = _T_234 | _T_235; // @[Mux.scala 27:72]
|
||||
wire q0off_in = _T_237 | _T_236; // @[Mux.scala 27:72]
|
||||
wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f[31:1],io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58]
|
||||
wire f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 194:25]
|
||||
wire [1:0] f1ictype = misc1eff[50:49]; // @[el2_ifu_aln_ctl.scala 196:26]
|
||||
wire [30:0] f1prett = misc1eff[48:18]; // @[el2_ifu_aln_ctl.scala 197:25]
|
||||
wire [11:0] f1poffset = misc1eff[19:8]; // @[el2_ifu_aln_ctl.scala 198:27]
|
||||
wire [7:0] f1fghr = misc1eff[7:0]; // @[el2_ifu_aln_ctl.scala 199:24]
|
||||
wire f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 201:25]
|
||||
wire [1:0] f0ictype = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 203:26]
|
||||
wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 204:25]
|
||||
wire [11:0] f0poffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 205:27]
|
||||
wire [7:0] f0fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 206:24]
|
||||
wire [5:0] _T_295 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58]
|
||||
wire [11:0] brdata_in = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_295}; // @[Cat.scala 29:58]
|
||||
reg [11:0] brdata1; // @[Reg.scala 27:20]
|
||||
reg [11:0] brdata0; // @[Reg.scala 27:20]
|
||||
wire [23:0] _T_303 = {brdata1,brdata0}; // @[Cat.scala 29:58]
|
||||
reg [11:0] brdata2; // @[Reg.scala 27:20]
|
||||
wire [23:0] _T_306 = {brdata2,brdata1}; // @[Cat.scala 29:58]
|
||||
wire [23:0] _T_309 = {brdata0,brdata2}; // @[Cat.scala 29:58]
|
||||
wire [23:0] _T_310 = qren[0] ? _T_303 : 24'h0; // @[Mux.scala 27:72]
|
||||
wire [23:0] _T_311 = qren[1] ? _T_306 : 24'h0; // @[Mux.scala 27:72]
|
||||
wire [23:0] _T_312 = qren[2] ? _T_309 : 24'h0; // @[Mux.scala 27:72]
|
||||
wire [23:0] _T_313 = _T_310 | _T_311; // @[Mux.scala 27:72]
|
||||
wire [23:0] brdataeff = _T_313 | _T_312; // @[Mux.scala 27:72]
|
||||
wire [11:0] brdata0eff = brdataeff[11:0]; // @[el2_ifu_aln_ctl.scala 216:43]
|
||||
wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 216:61]
|
||||
wire [11:0] _T_334 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72]
|
||||
wire [5:0] _T_335 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72]
|
||||
wire [11:0] _GEN_19 = {{6'd0}, _T_335}; // @[Mux.scala 27:72]
|
||||
wire [11:0] brdata0final = _T_334 | _GEN_19; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_342 = q1sel[0] ? brdata1eff : 12'h0; // @[Mux.scala 27:72]
|
||||
wire [5:0] _T_343 = q1sel[1] ? brdata1eff[11:6] : 6'h0; // @[Mux.scala 27:72]
|
||||
wire [11:0] _GEN_20 = {{6'd0}, _T_343}; // @[Mux.scala 27:72]
|
||||
wire [11:0] brdata1final = _T_342 | _GEN_20; // @[Mux.scala 27:72]
|
||||
wire [1:0] f0ret = {brdata0final[6],brdata0final[0]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f0brend = {brdata0final[7],brdata0final[1]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f0way = {brdata0final[8],brdata0final[2]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f0pc4 = {brdata0final[9],brdata0final[3]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f0hist0 = {brdata0final[10],brdata0final[4]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f0hist1 = {brdata0final[11],brdata0final[5]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f1ret = {brdata1final[6],brdata1final[0]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f1brend = {brdata1final[7],brdata1final[1]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f1way = {brdata1final[8],brdata1final[2]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f1pc4 = {brdata1final[9],brdata1final[3]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f1hist0 = {brdata1final[10],brdata1final[4]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] f1hist1 = {brdata1final[11],brdata1final[5]}; // @[Cat.scala 29:58]
|
||||
wire consume_fb1 = _T_54 & f1val[0]; // @[el2_ifu_aln_ctl.scala 251:32]
|
||||
wire _T_378 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 253:39]
|
||||
wire _T_379 = f0val[0] & _T_378; // @[el2_ifu_aln_ctl.scala 253:37]
|
||||
wire _T_382 = f0val[0] & consume_fb1; // @[el2_ifu_aln_ctl.scala 254:37]
|
||||
wire _T_405 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 271:28]
|
||||
wire _T_406 = ~_T_76; // @[el2_ifu_aln_ctl.scala 271:43]
|
||||
wire _T_407 = _T_405 & _T_406; // @[el2_ifu_aln_ctl.scala 271:41]
|
||||
wire _T_418 = ~_T_61; // @[el2_ifu_aln_ctl.scala 276:43]
|
||||
wire _T_431 = f2_wr_en & _T_1; // @[el2_ifu_aln_ctl.scala 278:38]
|
||||
wire _T_433 = ~f2_wr_en; // @[el2_ifu_aln_ctl.scala 279:6]
|
||||
wire _T_435 = _T_433 & _T_406; // @[el2_ifu_aln_ctl.scala 279:19]
|
||||
wire _T_437 = _T_435 & _T_418; // @[el2_ifu_aln_ctl.scala 279:34]
|
||||
wire _T_439 = _T_437 & _T_1; // @[el2_ifu_aln_ctl.scala 279:49]
|
||||
wire [1:0] _T_441 = _T_431 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_442 = _T_439 ? f2val : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] f2val_in = _T_441 | _T_442; // @[Mux.scala 27:72]
|
||||
wire _T_454 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 283:38]
|
||||
wire _T_457 = _T_76 & _T_1; // @[el2_ifu_aln_ctl.scala 284:38]
|
||||
wire _T_463 = _T_407 & _T_54; // @[el2_ifu_aln_ctl.scala 285:54]
|
||||
wire _T_465 = _T_463 & _T_1; // @[el2_ifu_aln_ctl.scala 285:69]
|
||||
wire [1:0] _T_467 = _T_454 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_468 = _T_457 ? f2val : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_469 = _T_465 ? sf1val : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_470 = _T_467 | _T_468; // @[Mux.scala 27:72]
|
||||
wire [1:0] f1val_in = _T_470 | _T_469; // @[Mux.scala 27:72]
|
||||
wire _T_475 = ~shift_2B; // @[el2_ifu_aln_ctl.scala 287:52]
|
||||
wire _T_476 = ~shift_4B; // @[el2_ifu_aln_ctl.scala 287:64]
|
||||
wire _T_477 = _T_475 & _T_476; // @[el2_ifu_aln_ctl.scala 287:62]
|
||||
wire _T_479 = shift_2B & f0val[1]; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_480 = _T_477 ? f0val : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _GEN_26 = {{1'd0}, _T_479}; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_481 = _GEN_26 | _T_480; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_542 = f0dbecc ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] _T_548 = {f1dbecc,f0dbecc}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_549 = f0val[1] ? _T_542 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_550 = _T_9 ? _T_548 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] aligndbecc = _T_549 | _T_550; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_561 = {f1brend[0],f0brend[0]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_562 = f0val[1] ? f0brend : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_563 = _T_9 ? _T_561 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] alignbrend = _T_562 | _T_563; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_574 = {f1pc4[0],f0pc4[0]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_575 = f0val[1] ? f0pc4 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_576 = _T_9 ? _T_574 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] alignpc4 = _T_575 | _T_576; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_587 = {f1ret[0],f0ret[0]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_588 = f0val[1] ? f0ret : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_589 = _T_9 ? _T_587 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] alignret = _T_588 | _T_589; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_600 = {f1way[0],f0way[0]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_601 = f0val[1] ? f0way : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_602 = _T_9 ? _T_600 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] alignway = _T_601 | _T_602; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_613 = {f1hist1[0],f0hist1[0]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_614 = f0val[1] ? f0hist1 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_615 = _T_9 ? _T_613 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] alignhist1 = _T_614 | _T_615; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_626 = {f1hist0[0],f0hist0[0]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_627 = f0val[1] ? f0hist0 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_628 = _T_9 ? _T_626 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] alignhist0 = _T_627 | _T_628; // @[Mux.scala 27:72]
|
||||
wire [30:0] secondpc = f0val[1] ? 31'h1 : 31'h0; // @[Mux.scala 27:72]
|
||||
wire _T_645 = decompressed_io_rvc & _T_7; // @[el2_ifu_aln_ctl.scala 324:39]
|
||||
wire _T_647 = _T_645 & f0val[0]; // @[el2_ifu_aln_ctl.scala 324:51]
|
||||
wire _T_649 = ~alignicaf[0]; // @[el2_ifu_aln_ctl.scala 324:64]
|
||||
wire _T_650 = _T_647 & _T_649; // @[el2_ifu_aln_ctl.scala 324:62]
|
||||
wire _T_652 = ~aligndbecc[0]; // @[el2_ifu_aln_ctl.scala 324:80]
|
||||
wire _T_653 = _T_650 & _T_652; // @[el2_ifu_aln_ctl.scala 324:78]
|
||||
wire icaf_eff = alignicaf[1] | aligndbecc[1]; // @[el2_ifu_aln_ctl.scala 326:31]
|
||||
wire _T_658 = decompressed_io_rvc & icaf_eff; // @[el2_ifu_aln_ctl.scala 328:32]
|
||||
wire _T_660 = |aligndbecc; // @[el2_ifu_aln_ctl.scala 330:52]
|
||||
wire _T_662 = decompressed_io_rvc & _T_660; // @[Mux.scala 27:72]
|
||||
wire _T_663 = first2B & aligndbecc[0]; // @[Mux.scala 27:72]
|
||||
wire [7:0] _T_672 = secondpc[9:2] ^ secondpc[17:10]; // @[el2_lib.scala 182:42]
|
||||
wire [7:0] secondpc_hash = _T_672 ^ secondpc[25:18]; // @[el2_lib.scala 182:76]
|
||||
wire [4:0] _T_683 = secondpc[14:10] ^ secondpc[19:15]; // @[el2_lib.scala 175:111]
|
||||
wire [4:0] secondbrtag_hash = _T_683 ^ secondpc[24:20]; // @[el2_lib.scala 175:111]
|
||||
wire _T_685 = first2B & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 340:30]
|
||||
wire _T_687 = decompressed_io_rvc & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 340:58]
|
||||
wire _T_688 = _T_685 | _T_687; // @[el2_ifu_aln_ctl.scala 340:47]
|
||||
wire _T_692 = _T_35 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 340:100]
|
||||
wire _T_695 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 342:29]
|
||||
wire _T_697 = decompressed_io_rvc & alignret[1]; // @[el2_ifu_aln_ctl.scala 342:55]
|
||||
wire _T_700 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 344:33]
|
||||
wire _T_706 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 345:34]
|
||||
wire _T_708 = decompressed_io_rvc & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 345:62]
|
||||
wire _T_709 = _T_706 | _T_708; // @[el2_ifu_aln_ctl.scala 345:51]
|
||||
wire _T_711 = first2B & alignhist0[0]; // @[el2_ifu_aln_ctl.scala 346:14]
|
||||
wire _T_713 = decompressed_io_rvc & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 346:42]
|
||||
wire _T_714 = _T_711 | _T_713; // @[el2_ifu_aln_ctl.scala 346:31]
|
||||
wire _T_716 = decompressed_io_rvc & _T_9; // @[el2_ifu_aln_ctl.scala 348:37]
|
||||
wire [30:0] _T_721 = _T_716 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 350:25]
|
||||
wire _T_733 = first2B & alignpc4[0]; // @[el2_ifu_aln_ctl.scala 356:29]
|
||||
wire _T_735 = decompressed_io_rvc & alignpc4[1]; // @[el2_ifu_aln_ctl.scala 356:55]
|
||||
wire i0_brp_pc4 = _T_733 | _T_735; // @[el2_ifu_aln_ctl.scala 356:44]
|
||||
wire _T_736 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 358:42]
|
||||
wire _T_737 = _T_736 & first2B; // @[el2_ifu_aln_ctl.scala 358:56]
|
||||
wire _T_738 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 358:89]
|
||||
wire _T_739 = io_i0_brp_valid & _T_738; // @[el2_ifu_aln_ctl.scala 358:87]
|
||||
wire _T_740 = _T_739 & decompressed_io_rvc; // @[el2_ifu_aln_ctl.scala 358:101]
|
||||
wire [7:0] _T_745 = _T_700 ? 8'h0 : secondpc_hash; // @[el2_ifu_aln_ctl.scala 361:28]
|
||||
el2_ifu_compress decompressed ( // @[el2_ifu_aln_ctl.scala 100:28]
|
||||
.io_in(decompressed_io_in),
|
||||
.io_out_bits(decompressed_io_out_bits),
|
||||
.io_out_rd(decompressed_io_out_rd),
|
||||
.io_out_rs1(decompressed_io_out_rs1),
|
||||
.io_out_rs2(decompressed_io_out_rs2),
|
||||
.io_out_rs3(decompressed_io_out_rs3),
|
||||
.io_rvc(decompressed_io_rvc)
|
||||
);
|
||||
assign io_ifu_i0_valid = _T_35 | _T_36; // @[el2_ifu_aln_ctl.scala 116:19]
|
||||
assign io_ifu_i0_icaf = _T_29 | _T_30; // @[el2_ifu_aln_ctl.scala 115:18]
|
||||
assign io_ifu_i0_icaf_type = _T_653 ? f1ictype : f0ictype; // @[el2_ifu_aln_ctl.scala 324:23]
|
||||
assign io_ifu_i0_icaf_f1 = _T_658 & _T_9; // @[el2_ifu_aln_ctl.scala 328:21]
|
||||
assign io_ifu_i0_dbecc = _T_662 | _T_663; // @[el2_ifu_aln_ctl.scala 330:19]
|
||||
assign io_ifu_i0_instr_bits = decompressed_io_out_bits; // @[el2_ifu_aln_ctl.scala 104:23]
|
||||
assign io_ifu_i0_instr_rd = decompressed_io_out_rd; // @[el2_ifu_aln_ctl.scala 104:23]
|
||||
assign io_ifu_i0_instr_rs1 = decompressed_io_out_rs1; // @[el2_ifu_aln_ctl.scala 104:23]
|
||||
assign io_ifu_i0_instr_rs2 = decompressed_io_out_rs2; // @[el2_ifu_aln_ctl.scala 104:23]
|
||||
assign io_ifu_i0_instr_rs3 = decompressed_io_out_rs3; // @[el2_ifu_aln_ctl.scala 104:23]
|
||||
assign io_ifu_i0_pc = 32'h0; // @[el2_ifu_aln_ctl.scala 320:16]
|
||||
assign io_ifu_i0_pc4 = decompressed_io_rvc; // @[el2_ifu_aln_ctl.scala 117:17]
|
||||
assign io_ifu_fb_consume1 = _T_379 & _T_1; // @[el2_ifu_aln_ctl.scala 253:22]
|
||||
assign io_ifu_fb_consume2 = _T_382 & _T_1; // @[el2_ifu_aln_ctl.scala 254:22]
|
||||
assign io_ifu_i0_bp_index = _T_745[6:0]; // @[el2_ifu_aln_ctl.scala 361:22]
|
||||
assign io_ifu_i0_bp_fghr = _T_716 ? f1fghr : f0fghr; // @[el2_ifu_aln_ctl.scala 363:21]
|
||||
assign io_ifu_i0_bp_btag = _T_700 ? 5'h0 : secondbrtag_hash; // @[el2_ifu_aln_ctl.scala 365:21]
|
||||
assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 96:28]
|
||||
assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 108:19]
|
||||
assign io_i0_brp_valid = _T_688 | _T_692; // @[el2_ifu_aln_ctl.scala 340:19]
|
||||
assign io_i0_brp_toffset = _T_716 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 348:21]
|
||||
assign io_i0_brp_hist = {_T_709,_T_714}; // @[el2_ifu_aln_ctl.scala 345:18]
|
||||
assign io_i0_brp_br_error = _T_737 | _T_740; // @[el2_ifu_aln_ctl.scala 358:22]
|
||||
assign io_i0_brp_br_start_error = _T_35 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 352:29]
|
||||
assign io_i0_brp_bank = _T_700 ? 1'h0 : secondpc[1]; // @[el2_ifu_aln_ctl.scala 354:29]
|
||||
assign io_i0_brp_prett = {{1'd0}, _T_721}; // @[el2_ifu_aln_ctl.scala 350:19]
|
||||
assign io_i0_brp_way = _T_700 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 344:17]
|
||||
assign io_i0_brp_ret = _T_695 | _T_697; // @[el2_ifu_aln_ctl.scala 342:17]
|
||||
assign io_test_out = 31'h0; // @[el2_ifu_aln_ctl.scala 368:15]
|
||||
assign decompressed_io_in = _GEN_13 | _T_13; // @[el2_ifu_aln_ctl.scala 102:22]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifndef RANDOM
|
||||
`define RANDOM $random
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
integer initvar;
|
||||
`endif
|
||||
`ifndef SYNTHESIS
|
||||
`ifdef FIRRTL_BEFORE_INITIAL
|
||||
`FIRRTL_BEFORE_INITIAL
|
||||
`endif
|
||||
initial begin
|
||||
`ifdef RANDOMIZE
|
||||
`ifdef INIT_RANDOM
|
||||
`INIT_RANDOM
|
||||
`endif
|
||||
`ifndef VERILATOR
|
||||
`ifdef RANDOMIZE_DELAY
|
||||
#`RANDOMIZE_DELAY begin end
|
||||
`else
|
||||
#0.002 begin end
|
||||
`endif
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_0 = {1{`RANDOM}};
|
||||
error_stall = _RAND_0[0:0];
|
||||
_RAND_1 = {1{`RANDOM}};
|
||||
f0val = _RAND_1[1:0];
|
||||
_RAND_2 = {1{`RANDOM}};
|
||||
rdptr = _RAND_2[1:0];
|
||||
_RAND_3 = {1{`RANDOM}};
|
||||
q1off = _RAND_3[0:0];
|
||||
_RAND_4 = {1{`RANDOM}};
|
||||
q2off = _RAND_4[0:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
q0off = _RAND_5[0:0];
|
||||
_RAND_6 = {1{`RANDOM}};
|
||||
q1 = _RAND_6[31:0];
|
||||
_RAND_7 = {1{`RANDOM}};
|
||||
q0 = _RAND_7[31:0];
|
||||
_RAND_8 = {1{`RANDOM}};
|
||||
q2 = _RAND_8[31:0];
|
||||
_RAND_9 = {2{`RANDOM}};
|
||||
_T_762 = _RAND_9[54:0];
|
||||
_RAND_10 = {2{`RANDOM}};
|
||||
_T_764 = _RAND_10[54:0];
|
||||
_RAND_11 = {2{`RANDOM}};
|
||||
_T_760 = _RAND_11[54:0];
|
||||
_RAND_12 = {1{`RANDOM}};
|
||||
f1val = _RAND_12[1:0];
|
||||
_RAND_13 = {1{`RANDOM}};
|
||||
wrptr = _RAND_13[1:0];
|
||||
_RAND_14 = {1{`RANDOM}};
|
||||
f2val = _RAND_14[1:0];
|
||||
_RAND_15 = {1{`RANDOM}};
|
||||
brdata1 = _RAND_15[11:0];
|
||||
_RAND_16 = {1{`RANDOM}};
|
||||
brdata0 = _RAND_16[11:0];
|
||||
_RAND_17 = {1{`RANDOM}};
|
||||
brdata2 = _RAND_17[11:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
`ifdef FIRRTL_AFTER_INITIAL
|
||||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge clock) begin
|
||||
if (reset) begin
|
||||
error_stall <= 1'h0;
|
||||
end else begin
|
||||
error_stall <= error_stall_in;
|
||||
end
|
||||
if (reset) begin
|
||||
f0val <= 2'h0;
|
||||
end else begin
|
||||
f0val <= _T_481;
|
||||
end
|
||||
if (reset) begin
|
||||
rdptr <= 2'h0;
|
||||
end else begin
|
||||
rdptr <= wrptr_in;
|
||||
end
|
||||
if (reset) begin
|
||||
q1off <= 1'h0;
|
||||
end else begin
|
||||
q1off <= q1off_in;
|
||||
end
|
||||
if (reset) begin
|
||||
q2off <= 1'h0;
|
||||
end else begin
|
||||
q2off <= q2off_in;
|
||||
end
|
||||
if (reset) begin
|
||||
q0off <= 1'h0;
|
||||
end else begin
|
||||
q0off <= q0off_in;
|
||||
end
|
||||
if (reset) begin
|
||||
q1 <= 32'h0;
|
||||
end else if (qwen[1]) begin
|
||||
q1 <= io_ifu_fetch_data_f;
|
||||
end
|
||||
if (reset) begin
|
||||
q0 <= 32'h0;
|
||||
end else if (qwen[0]) begin
|
||||
q0 <= io_ifu_fetch_data_f;
|
||||
end
|
||||
if (reset) begin
|
||||
q2 <= 32'h0;
|
||||
end else if (qwen[2]) begin
|
||||
q2 <= io_ifu_fetch_data_f;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_762 <= 55'h0;
|
||||
end else if (qwen[1]) begin
|
||||
_T_762 <= misc_data_in;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_764 <= 55'h0;
|
||||
end else if (qwen[0]) begin
|
||||
_T_764 <= misc_data_in;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_760 <= 55'h0;
|
||||
end else if (qwen[2]) begin
|
||||
_T_760 <= misc_data_in;
|
||||
end
|
||||
if (reset) begin
|
||||
f1val <= 2'h0;
|
||||
end else begin
|
||||
f1val <= f1val_in;
|
||||
end
|
||||
if (reset) begin
|
||||
wrptr <= 2'h0;
|
||||
end else begin
|
||||
wrptr <= wrptr_in;
|
||||
end
|
||||
if (reset) begin
|
||||
f2val <= 2'h0;
|
||||
end else begin
|
||||
f2val <= f2val_in;
|
||||
end
|
||||
if (reset) begin
|
||||
brdata1 <= 12'h0;
|
||||
end else if (qwen[1]) begin
|
||||
brdata1 <= brdata_in;
|
||||
end
|
||||
if (reset) begin
|
||||
brdata0 <= 12'h0;
|
||||
end else if (qwen[0]) begin
|
||||
brdata0 <= brdata_in;
|
||||
end
|
||||
if (reset) begin
|
||||
brdata2 <= 12'h0;
|
||||
end else if (qwen[2]) begin
|
||||
brdata2 <= brdata_in;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -10,6 +10,33 @@
|
|||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume1"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||
"sources":[
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_iccm_access_bf",
|
||||
"sources":[
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf",
|
||||
|
|
@ -37,52 +64,7 @@
|
|||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_testin"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_test1",
|
||||
"sources":[
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_testin"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_iccm_access_bf",
|
||||
"sources":[
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_testin"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||
"sources":[
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_testin"
|
||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ circuit el2_ifu_ifc_ctrl :
|
|||
module el2_ifu_ifc_ctrl :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<31>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, flip testin : UInt<1>, test1 : UInt}
|
||||
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<31>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
|
||||
|
||||
wire fetch_addr_bf : UInt<32>
|
||||
fetch_addr_bf <= UInt<1>("h00")
|
||||
|
|
@ -33,7 +33,7 @@ circuit el2_ifu_ifc_ctrl :
|
|||
sel_next_addr_bf <= UInt<1>("h00")
|
||||
wire miss_f : UInt<1>
|
||||
miss_f <= UInt<1>("h00")
|
||||
wire miss_a : UInt<1> @[el2_ifu_ifc_ctrl.scala 56:20]
|
||||
wire miss_a : UInt<1> @[el2_ifu_ifc_ctrl.scala 53:20]
|
||||
wire flush_fb : UInt<1>
|
||||
flush_fb <= UInt<1>("h00")
|
||||
wire mb_empty_mod : UInt<1>
|
||||
|
|
@ -45,220 +45,212 @@ circuit el2_ifu_ifc_ctrl :
|
|||
wire fetch_bf_en : UInt<1>
|
||||
fetch_bf_en <= UInt<1>("h00")
|
||||
wire line_wrap : UInt<1>
|
||||
line_wrap <= io.testin
|
||||
wire fetch_addr_next_1 : UInt<1>
|
||||
fetch_addr_next_1 <= UInt<1>("h00")
|
||||
line_wrap <= UInt<1>("h00")
|
||||
wire state : UInt<2>
|
||||
state <= UInt<1>("h00")
|
||||
io.ifc_fetch_addr_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 67:23]
|
||||
io.ifc_fetch_addr_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 68:24]
|
||||
io.ifc_fetch_req_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 69:22]
|
||||
io.ifu_pmu_fetch_stall <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 70:26]
|
||||
io.ifc_fetch_uncacheable_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 71:31]
|
||||
io.ifc_fetch_req_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 72:23]
|
||||
io.ifc_fetch_req_bf_raw <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 73:27]
|
||||
io.ifc_iccm_access_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 74:25]
|
||||
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 75:30]
|
||||
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 76:24]
|
||||
reg dma_iccm_stall_any_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 78:37]
|
||||
dma_iccm_stall_any_f <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 78:37]
|
||||
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 79:36]
|
||||
reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 80:20]
|
||||
_T <= miss_f @[el2_ifu_ifc_ctrl.scala 80:20]
|
||||
miss_a <= _T @[el2_ifu_ifc_ctrl.scala 80:10]
|
||||
node _T_1 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 82:23]
|
||||
node _T_2 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 82:46]
|
||||
node _T_3 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 82:68]
|
||||
node _T_4 = or(_T_2, _T_3) @[el2_ifu_ifc_ctrl.scala 82:66]
|
||||
node _T_5 = and(_T_1, _T_4) @[el2_ifu_ifc_ctrl.scala 82:43]
|
||||
sel_last_addr_bf <= _T_5 @[el2_ifu_ifc_ctrl.scala 82:20]
|
||||
node _T_6 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 83:23]
|
||||
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 83:43]
|
||||
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 83:64]
|
||||
node _T_9 = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 83:88]
|
||||
sel_btb_addr_bf <= _T_9 @[el2_ifu_ifc_ctrl.scala 83:20]
|
||||
node _T_10 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 84:23]
|
||||
node _T_11 = and(_T_10, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 84:43]
|
||||
node _T_12 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 84:66]
|
||||
node _T_13 = and(_T_11, _T_12) @[el2_ifu_ifc_ctrl.scala 84:64]
|
||||
node _T_14 = and(_T_13, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 84:89]
|
||||
sel_next_addr_bf <= _T_14 @[el2_ifu_ifc_ctrl.scala 84:20]
|
||||
node _T_15 = bits(fetch_addr_next, 6, 6) @[el2_ifu_ifc_ctrl.scala 88:31]
|
||||
node _T_16 = bits(io.ifc_fetch_addr_f, 6, 6) @[el2_ifu_ifc_ctrl.scala 88:74]
|
||||
node _T_17 = xor(_T_15, _T_16) @[el2_ifu_ifc_ctrl.scala 88:53]
|
||||
line_wrap <= _T_17 @[el2_ifu_ifc_ctrl.scala 88:13]
|
||||
node _T_18 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 90:44]
|
||||
node _T_19 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 90:72]
|
||||
node _T_20 = mux(_T_18, UInt<1>("h00"), _T_19) @[el2_ifu_ifc_ctrl.scala 90:27]
|
||||
fetch_addr_next_1 <= _T_20 @[el2_ifu_ifc_ctrl.scala 90:21]
|
||||
node _T_21 = add(io.ifc_fetch_addr_f, UInt<2>("h02")) @[el2_ifu_ifc_ctrl.scala 92:45]
|
||||
node _T_22 = tail(_T_21, 1) @[el2_ifu_ifc_ctrl.scala 92:45]
|
||||
node _T_23 = cat(_T_22, fetch_addr_next_1) @[Cat.scala 29:58]
|
||||
fetch_addr_next <= _T_23 @[el2_ifu_ifc_ctrl.scala 92:19]
|
||||
node _T_24 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 96:56]
|
||||
node _T_25 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 97:46]
|
||||
node _T_26 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 98:45]
|
||||
node _T_27 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 99:46]
|
||||
node _T_28 = mux(_T_24, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_29 = mux(_T_25, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_30 = mux(_T_26, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_31 = mux(_T_27, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_32 = or(_T_28, _T_29) @[Mux.scala 27:72]
|
||||
node _T_33 = or(_T_32, _T_30) @[Mux.scala 27:72]
|
||||
node _T_34 = or(_T_33, _T_31) @[Mux.scala 27:72]
|
||||
wire _T_35 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_35 <= _T_34 @[Mux.scala 27:72]
|
||||
io.ifc_fetch_addr_bf <= _T_35 @[el2_ifu_ifc_ctrl.scala 96:24]
|
||||
node _T_36 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 102:88]
|
||||
reg _T_37 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_36 : @[Reg.scala 28:19]
|
||||
_T_37 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
||||
io.ifc_fetch_addr_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 64:23]
|
||||
io.ifc_fetch_addr_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 65:24]
|
||||
io.ifc_fetch_req_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 66:22]
|
||||
io.ifu_pmu_fetch_stall <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 67:26]
|
||||
io.ifc_fetch_uncacheable_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 68:31]
|
||||
io.ifc_fetch_req_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 69:23]
|
||||
io.ifc_fetch_req_bf_raw <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 70:27]
|
||||
io.ifc_iccm_access_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 71:25]
|
||||
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 72:30]
|
||||
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 73:24]
|
||||
reg dma_iccm_stall_any_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 75:37]
|
||||
dma_iccm_stall_any_f <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 75:37]
|
||||
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 76:36]
|
||||
reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 77:20]
|
||||
_T <= miss_f @[el2_ifu_ifc_ctrl.scala 77:20]
|
||||
miss_a <= _T @[el2_ifu_ifc_ctrl.scala 77:10]
|
||||
node _T_1 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 79:23]
|
||||
node _T_2 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 79:46]
|
||||
node _T_3 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 79:68]
|
||||
node _T_4 = or(_T_2, _T_3) @[el2_ifu_ifc_ctrl.scala 79:66]
|
||||
node _T_5 = and(_T_1, _T_4) @[el2_ifu_ifc_ctrl.scala 79:43]
|
||||
sel_last_addr_bf <= _T_5 @[el2_ifu_ifc_ctrl.scala 79:20]
|
||||
node _T_6 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 80:23]
|
||||
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 80:43]
|
||||
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 80:64]
|
||||
node _T_9 = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 80:88]
|
||||
sel_btb_addr_bf <= _T_9 @[el2_ifu_ifc_ctrl.scala 80:20]
|
||||
node _T_10 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 81:23]
|
||||
node _T_11 = and(_T_10, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 81:43]
|
||||
node _T_12 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 81:66]
|
||||
node _T_13 = and(_T_11, _T_12) @[el2_ifu_ifc_ctrl.scala 81:64]
|
||||
node _T_14 = and(_T_13, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 81:89]
|
||||
sel_next_addr_bf <= _T_14 @[el2_ifu_ifc_ctrl.scala 81:20]
|
||||
node _T_15 = add(io.ifc_fetch_addr_f, UInt<2>("h02")) @[el2_ifu_ifc_ctrl.scala 84:42]
|
||||
node _T_16 = tail(_T_15, 1) @[el2_ifu_ifc_ctrl.scala 84:42]
|
||||
node _T_17 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 85:25]
|
||||
node _T_18 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 85:53]
|
||||
node _T_19 = mux(_T_17, UInt<1>("h00"), _T_18) @[el2_ifu_ifc_ctrl.scala 85:8]
|
||||
node _T_20 = or(_T_16, _T_19) @[el2_ifu_ifc_ctrl.scala 84:48]
|
||||
fetch_addr_next <= _T_20 @[el2_ifu_ifc_ctrl.scala 84:19]
|
||||
node _T_21 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 89:56]
|
||||
node _T_22 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 90:46]
|
||||
node _T_23 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 91:45]
|
||||
node _T_24 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 92:46]
|
||||
node _T_25 = mux(_T_21, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_26 = mux(_T_22, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_27 = mux(_T_23, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_28 = mux(_T_24, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_29 = or(_T_25, _T_26) @[Mux.scala 27:72]
|
||||
node _T_30 = or(_T_29, _T_27) @[Mux.scala 27:72]
|
||||
node _T_31 = or(_T_30, _T_28) @[Mux.scala 27:72]
|
||||
wire _T_32 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_32 <= _T_31 @[Mux.scala 27:72]
|
||||
io.ifc_fetch_addr_bf <= _T_32 @[el2_ifu_ifc_ctrl.scala 89:24]
|
||||
node _T_33 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 95:88]
|
||||
reg _T_34 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_33 : @[Reg.scala 28:19]
|
||||
_T_34 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
io.ifc_fetch_addr_f <= _T_37 @[el2_ifu_ifc_ctrl.scala 102:23]
|
||||
node _T_38 = not(idle) @[el2_ifu_ifc_ctrl.scala 104:30]
|
||||
io.ifc_fetch_req_bf_raw <= _T_38 @[el2_ifu_ifc_ctrl.scala 104:27]
|
||||
reg _T_39 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 106:32]
|
||||
_T_39 <= io.ifc_fetch_addr_bf @[el2_ifu_ifc_ctrl.scala 106:32]
|
||||
io.ifc_fetch_req_f <= _T_39 @[el2_ifu_ifc_ctrl.scala 106:22]
|
||||
io.test1 <= io.ifc_fetch_addr_bf @[el2_ifu_ifc_ctrl.scala 107:12]
|
||||
node _T_40 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 109:91]
|
||||
node _T_41 = not(_T_40) @[el2_ifu_ifc_ctrl.scala 109:70]
|
||||
node _T_42 = and(fb_full_f_ns, _T_41) @[el2_ifu_ifc_ctrl.scala 109:68]
|
||||
node _T_43 = not(_T_42) @[el2_ifu_ifc_ctrl.scala 109:53]
|
||||
node _T_44 = and(io.ifc_fetch_req_bf_raw, _T_43) @[el2_ifu_ifc_ctrl.scala 109:51]
|
||||
node _T_45 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 110:5]
|
||||
node _T_46 = and(_T_44, _T_45) @[el2_ifu_ifc_ctrl.scala 109:114]
|
||||
node _T_47 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 110:18]
|
||||
node _T_48 = and(_T_46, _T_47) @[el2_ifu_ifc_ctrl.scala 110:16]
|
||||
node _T_49 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 110:39]
|
||||
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctrl.scala 110:37]
|
||||
io.ifc_fetch_req_bf <= _T_50 @[el2_ifu_ifc_ctrl.scala 109:23]
|
||||
node _T_51 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 112:34]
|
||||
node _T_52 = and(io.ifc_fetch_req_f, _T_51) @[el2_ifu_ifc_ctrl.scala 112:32]
|
||||
node _T_53 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 112:49]
|
||||
node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 112:47]
|
||||
miss_f <= _T_54 @[el2_ifu_ifc_ctrl.scala 112:10]
|
||||
node _T_55 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 114:35]
|
||||
goto_idle <= _T_55 @[el2_ifu_ifc_ctrl.scala 114:13]
|
||||
node _T_56 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 116:39]
|
||||
node _T_57 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 116:63]
|
||||
node _T_58 = and(_T_56, _T_57) @[el2_ifu_ifc_ctrl.scala 116:61]
|
||||
node _T_59 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 116:76]
|
||||
node _T_60 = and(_T_58, _T_59) @[el2_ifu_ifc_ctrl.scala 116:74]
|
||||
node _T_61 = not(miss_a) @[el2_ifu_ifc_ctrl.scala 116:86]
|
||||
node _T_62 = and(_T_60, _T_61) @[el2_ifu_ifc_ctrl.scala 116:84]
|
||||
mb_empty_mod <= _T_62 @[el2_ifu_ifc_ctrl.scala 116:16]
|
||||
node _T_63 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 118:38]
|
||||
node _T_64 = and(io.exu_flush_final, _T_63) @[el2_ifu_ifc_ctrl.scala 118:36]
|
||||
node _T_65 = and(_T_64, idle) @[el2_ifu_ifc_ctrl.scala 118:67]
|
||||
leave_idle <= _T_65 @[el2_ifu_ifc_ctrl.scala 118:14]
|
||||
node _T_66 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 120:29]
|
||||
node _T_67 = not(_T_66) @[el2_ifu_ifc_ctrl.scala 120:23]
|
||||
node _T_68 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 120:40]
|
||||
node _T_69 = and(_T_67, _T_68) @[el2_ifu_ifc_ctrl.scala 120:33]
|
||||
node _T_70 = and(_T_69, miss_f) @[el2_ifu_ifc_ctrl.scala 120:44]
|
||||
node _T_71 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 120:55]
|
||||
node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctrl.scala 120:53]
|
||||
node _T_73 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 121:11]
|
||||
node _T_74 = not(mb_empty_mod) @[el2_ifu_ifc_ctrl.scala 121:17]
|
||||
node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctrl.scala 121:15]
|
||||
node _T_76 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 121:33]
|
||||
node _T_77 = and(_T_75, _T_76) @[el2_ifu_ifc_ctrl.scala 121:31]
|
||||
node next_state_1 = or(_T_72, _T_77) @[el2_ifu_ifc_ctrl.scala 120:67]
|
||||
node _T_78 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 123:23]
|
||||
node _T_79 = and(_T_78, leave_idle) @[el2_ifu_ifc_ctrl.scala 123:34]
|
||||
node _T_80 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 123:56]
|
||||
node _T_81 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 123:62]
|
||||
node _T_82 = and(_T_80, _T_81) @[el2_ifu_ifc_ctrl.scala 123:60]
|
||||
node next_state_0 = or(_T_79, _T_82) @[el2_ifu_ifc_ctrl.scala 123:48]
|
||||
node _T_83 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
|
||||
reg _T_84 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 125:19]
|
||||
_T_84 <= _T_83 @[el2_ifu_ifc_ctrl.scala 125:19]
|
||||
state <= _T_84 @[el2_ifu_ifc_ctrl.scala 125:9]
|
||||
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 127:12]
|
||||
node _T_85 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 129:38]
|
||||
node _T_86 = and(io.ifu_fb_consume1, _T_85) @[el2_ifu_ifc_ctrl.scala 129:36]
|
||||
node _T_87 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 129:61]
|
||||
node _T_88 = or(_T_87, miss_f) @[el2_ifu_ifc_ctrl.scala 129:81]
|
||||
node _T_89 = and(_T_86, _T_88) @[el2_ifu_ifc_ctrl.scala 129:58]
|
||||
node _T_90 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 130:25]
|
||||
node _T_91 = or(_T_89, _T_90) @[el2_ifu_ifc_ctrl.scala 129:92]
|
||||
fb_right <= _T_91 @[el2_ifu_ifc_ctrl.scala 129:12]
|
||||
node _T_92 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 132:39]
|
||||
node _T_93 = or(_T_92, miss_f) @[el2_ifu_ifc_ctrl.scala 132:59]
|
||||
node _T_94 = and(io.ifu_fb_consume2, _T_93) @[el2_ifu_ifc_ctrl.scala 132:36]
|
||||
fb_right2 <= _T_94 @[el2_ifu_ifc_ctrl.scala 132:13]
|
||||
node _T_95 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 133:56]
|
||||
node _T_96 = not(_T_95) @[el2_ifu_ifc_ctrl.scala 133:35]
|
||||
node _T_97 = and(io.ifc_fetch_req_f, _T_96) @[el2_ifu_ifc_ctrl.scala 133:33]
|
||||
node _T_98 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 133:80]
|
||||
node _T_99 = and(_T_97, _T_98) @[el2_ifu_ifc_ctrl.scala 133:78]
|
||||
fb_left <= _T_99 @[el2_ifu_ifc_ctrl.scala 133:11]
|
||||
node _T_100 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 136:6]
|
||||
node _T_101 = and(_T_100, fb_right) @[el2_ifu_ifc_ctrl.scala 136:16]
|
||||
node _T_102 = bits(_T_101, 0, 0) @[el2_ifu_ifc_ctrl.scala 136:28]
|
||||
node _T_103 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 136:62]
|
||||
node _T_104 = cat(UInt<1>("h00"), _T_103) @[Cat.scala 29:58]
|
||||
node _T_105 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 137:6]
|
||||
node _T_106 = and(_T_105, fb_right2) @[el2_ifu_ifc_ctrl.scala 137:16]
|
||||
node _T_107 = bits(_T_106, 0, 0) @[el2_ifu_ifc_ctrl.scala 137:29]
|
||||
node _T_108 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 137:63]
|
||||
node _T_109 = cat(UInt<2>("h00"), _T_108) @[Cat.scala 29:58]
|
||||
node _T_110 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 138:6]
|
||||
node _T_111 = and(_T_110, fb_left) @[el2_ifu_ifc_ctrl.scala 138:16]
|
||||
node _T_112 = bits(_T_111, 0, 0) @[el2_ifu_ifc_ctrl.scala 138:27]
|
||||
node _T_113 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 138:51]
|
||||
node _T_114 = cat(_T_113, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_115 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 139:6]
|
||||
node _T_116 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 139:18]
|
||||
node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctrl.scala 139:16]
|
||||
node _T_118 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 139:30]
|
||||
node _T_119 = and(_T_117, _T_118) @[el2_ifu_ifc_ctrl.scala 139:28]
|
||||
node _T_120 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 139:43]
|
||||
node _T_121 = and(_T_119, _T_120) @[el2_ifu_ifc_ctrl.scala 139:41]
|
||||
node _T_122 = bits(_T_121, 0, 0) @[el2_ifu_ifc_ctrl.scala 139:53]
|
||||
node _T_123 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 139:73]
|
||||
node _T_124 = mux(io.exu_flush_final, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_125 = mux(_T_102, _T_104, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_126 = mux(_T_107, _T_109, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_127 = mux(_T_112, _T_114, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_128 = mux(_T_122, _T_123, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_129 = or(_T_124, _T_125) @[Mux.scala 27:72]
|
||||
node _T_130 = or(_T_129, _T_126) @[Mux.scala 27:72]
|
||||
node _T_131 = or(_T_130, _T_127) @[Mux.scala 27:72]
|
||||
node _T_132 = or(_T_131, _T_128) @[Mux.scala 27:72]
|
||||
wire _T_133 : UInt<4> @[Mux.scala 27:72]
|
||||
_T_133 <= _T_132 @[Mux.scala 27:72]
|
||||
fb_write_ns <= _T_133 @[el2_ifu_ifc_ctrl.scala 135:15]
|
||||
reg _T_134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 142:26]
|
||||
_T_134 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 142:26]
|
||||
fb_full_f_ns <= _T_134 @[el2_ifu_ifc_ctrl.scala 142:16]
|
||||
node _T_135 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 144:17]
|
||||
idle <= _T_135 @[el2_ifu_ifc_ctrl.scala 144:8]
|
||||
node _T_136 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 145:16]
|
||||
wfm <= _T_136 @[el2_ifu_ifc_ctrl.scala 145:7]
|
||||
node _T_137 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 147:30]
|
||||
fb_full_f_ns <= _T_137 @[el2_ifu_ifc_ctrl.scala 147:16]
|
||||
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 148:26]
|
||||
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 148:26]
|
||||
node _T_138 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 151:26]
|
||||
node _T_139 = or(_T_138, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 151:47]
|
||||
node _T_140 = not(_T_139) @[el2_ifu_ifc_ctrl.scala 151:5]
|
||||
node _T_141 = and(fb_full_f, _T_140) @[el2_ifu_ifc_ctrl.scala 150:75]
|
||||
node _T_142 = or(_T_141, dma_stall) @[el2_ifu_ifc_ctrl.scala 151:70]
|
||||
node _T_143 = and(io.ifc_fetch_req_bf_raw, _T_142) @[el2_ifu_ifc_ctrl.scala 150:60]
|
||||
node _T_144 = or(wfm, _T_143) @[el2_ifu_ifc_ctrl.scala 150:33]
|
||||
io.ifu_pmu_fetch_stall <= _T_144 @[el2_ifu_ifc_ctrl.scala 150:26]
|
||||
node _T_145 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_146 = bits(_T_145, 31, 28) @[el2_lib.scala 203:25]
|
||||
node iccm_acc_in_region_bf = eq(_T_146, UInt<4>("h0e")) @[el2_lib.scala 203:47]
|
||||
node _T_147 = bits(_T_145, 31, 16) @[el2_lib.scala 206:14]
|
||||
node iccm_acc_in_range_bf = eq(_T_147, UInt<16>("h0ee00")) @[el2_lib.scala 206:29]
|
||||
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 157:25]
|
||||
node _T_148 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 158:78]
|
||||
node _T_149 = cat(_T_148, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_150 = dshr(io.dec_tlu_mrac_ff, _T_149) @[el2_ifu_ifc_ctrl.scala 158:53]
|
||||
node _T_151 = bits(_T_150, 0, 0) @[el2_ifu_ifc_ctrl.scala 158:53]
|
||||
node _T_152 = not(_T_151) @[el2_ifu_ifc_ctrl.scala 158:34]
|
||||
io.ifc_fetch_uncacheable_bf <= _T_152 @[el2_ifu_ifc_ctrl.scala 158:31]
|
||||
io.ifc_fetch_addr_f <= _T_34 @[el2_ifu_ifc_ctrl.scala 95:23]
|
||||
node _T_35 = not(idle) @[el2_ifu_ifc_ctrl.scala 97:30]
|
||||
io.ifc_fetch_req_bf_raw <= _T_35 @[el2_ifu_ifc_ctrl.scala 97:27]
|
||||
reg _T_36 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 99:32]
|
||||
_T_36 <= io.ifc_fetch_addr_bf @[el2_ifu_ifc_ctrl.scala 99:32]
|
||||
io.ifc_fetch_req_f <= _T_36 @[el2_ifu_ifc_ctrl.scala 99:22]
|
||||
node _T_37 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 101:91]
|
||||
node _T_38 = not(_T_37) @[el2_ifu_ifc_ctrl.scala 101:70]
|
||||
node _T_39 = and(fb_full_f_ns, _T_38) @[el2_ifu_ifc_ctrl.scala 101:68]
|
||||
node _T_40 = not(_T_39) @[el2_ifu_ifc_ctrl.scala 101:53]
|
||||
node _T_41 = and(io.ifc_fetch_req_bf_raw, _T_40) @[el2_ifu_ifc_ctrl.scala 101:51]
|
||||
node _T_42 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 102:5]
|
||||
node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctrl.scala 101:114]
|
||||
node _T_44 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 102:18]
|
||||
node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctrl.scala 102:16]
|
||||
node _T_46 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 102:39]
|
||||
node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctrl.scala 102:37]
|
||||
io.ifc_fetch_req_bf <= _T_47 @[el2_ifu_ifc_ctrl.scala 101:23]
|
||||
node _T_48 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 104:34]
|
||||
node _T_49 = and(io.ifc_fetch_req_f, _T_48) @[el2_ifu_ifc_ctrl.scala 104:32]
|
||||
node _T_50 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 104:49]
|
||||
node _T_51 = and(_T_49, _T_50) @[el2_ifu_ifc_ctrl.scala 104:47]
|
||||
miss_f <= _T_51 @[el2_ifu_ifc_ctrl.scala 104:10]
|
||||
node _T_52 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 106:35]
|
||||
goto_idle <= _T_52 @[el2_ifu_ifc_ctrl.scala 106:13]
|
||||
node _T_53 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 108:39]
|
||||
node _T_54 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 108:63]
|
||||
node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctrl.scala 108:61]
|
||||
node _T_56 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 108:76]
|
||||
node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctrl.scala 108:74]
|
||||
node _T_58 = not(miss_a) @[el2_ifu_ifc_ctrl.scala 108:86]
|
||||
node _T_59 = and(_T_57, _T_58) @[el2_ifu_ifc_ctrl.scala 108:84]
|
||||
mb_empty_mod <= _T_59 @[el2_ifu_ifc_ctrl.scala 108:16]
|
||||
node _T_60 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 110:38]
|
||||
node _T_61 = and(io.exu_flush_final, _T_60) @[el2_ifu_ifc_ctrl.scala 110:36]
|
||||
node _T_62 = and(_T_61, idle) @[el2_ifu_ifc_ctrl.scala 110:67]
|
||||
leave_idle <= _T_62 @[el2_ifu_ifc_ctrl.scala 110:14]
|
||||
node _T_63 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 112:29]
|
||||
node _T_64 = not(_T_63) @[el2_ifu_ifc_ctrl.scala 112:23]
|
||||
node _T_65 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 112:40]
|
||||
node _T_66 = and(_T_64, _T_65) @[el2_ifu_ifc_ctrl.scala 112:33]
|
||||
node _T_67 = and(_T_66, miss_f) @[el2_ifu_ifc_ctrl.scala 112:44]
|
||||
node _T_68 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 112:55]
|
||||
node _T_69 = and(_T_67, _T_68) @[el2_ifu_ifc_ctrl.scala 112:53]
|
||||
node _T_70 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 113:11]
|
||||
node _T_71 = not(mb_empty_mod) @[el2_ifu_ifc_ctrl.scala 113:17]
|
||||
node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctrl.scala 113:15]
|
||||
node _T_73 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 113:33]
|
||||
node _T_74 = and(_T_72, _T_73) @[el2_ifu_ifc_ctrl.scala 113:31]
|
||||
node next_state_1 = or(_T_69, _T_74) @[el2_ifu_ifc_ctrl.scala 112:67]
|
||||
node _T_75 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 115:23]
|
||||
node _T_76 = and(_T_75, leave_idle) @[el2_ifu_ifc_ctrl.scala 115:34]
|
||||
node _T_77 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 115:56]
|
||||
node _T_78 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 115:62]
|
||||
node _T_79 = and(_T_77, _T_78) @[el2_ifu_ifc_ctrl.scala 115:60]
|
||||
node next_state_0 = or(_T_76, _T_79) @[el2_ifu_ifc_ctrl.scala 115:48]
|
||||
node _T_80 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
|
||||
reg _T_81 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 117:19]
|
||||
_T_81 <= _T_80 @[el2_ifu_ifc_ctrl.scala 117:19]
|
||||
state <= _T_81 @[el2_ifu_ifc_ctrl.scala 117:9]
|
||||
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 119:12]
|
||||
node _T_82 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 121:38]
|
||||
node _T_83 = and(io.ifu_fb_consume1, _T_82) @[el2_ifu_ifc_ctrl.scala 121:36]
|
||||
node _T_84 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 121:61]
|
||||
node _T_85 = or(_T_84, miss_f) @[el2_ifu_ifc_ctrl.scala 121:81]
|
||||
node _T_86 = and(_T_83, _T_85) @[el2_ifu_ifc_ctrl.scala 121:58]
|
||||
node _T_87 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 122:25]
|
||||
node _T_88 = or(_T_86, _T_87) @[el2_ifu_ifc_ctrl.scala 121:92]
|
||||
fb_right <= _T_88 @[el2_ifu_ifc_ctrl.scala 121:12]
|
||||
node _T_89 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 124:39]
|
||||
node _T_90 = or(_T_89, miss_f) @[el2_ifu_ifc_ctrl.scala 124:59]
|
||||
node _T_91 = and(io.ifu_fb_consume2, _T_90) @[el2_ifu_ifc_ctrl.scala 124:36]
|
||||
fb_right2 <= _T_91 @[el2_ifu_ifc_ctrl.scala 124:13]
|
||||
node _T_92 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 125:56]
|
||||
node _T_93 = not(_T_92) @[el2_ifu_ifc_ctrl.scala 125:35]
|
||||
node _T_94 = and(io.ifc_fetch_req_f, _T_93) @[el2_ifu_ifc_ctrl.scala 125:33]
|
||||
node _T_95 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 125:80]
|
||||
node _T_96 = and(_T_94, _T_95) @[el2_ifu_ifc_ctrl.scala 125:78]
|
||||
fb_left <= _T_96 @[el2_ifu_ifc_ctrl.scala 125:11]
|
||||
node _T_97 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 128:6]
|
||||
node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctrl.scala 128:16]
|
||||
node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctrl.scala 128:28]
|
||||
node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 128:62]
|
||||
node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58]
|
||||
node _T_102 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 129:6]
|
||||
node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctrl.scala 129:16]
|
||||
node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctrl.scala 129:29]
|
||||
node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 129:63]
|
||||
node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58]
|
||||
node _T_107 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 130:6]
|
||||
node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctrl.scala 130:16]
|
||||
node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctrl.scala 130:27]
|
||||
node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 130:51]
|
||||
node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_112 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 131:6]
|
||||
node _T_113 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 131:18]
|
||||
node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctrl.scala 131:16]
|
||||
node _T_115 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 131:30]
|
||||
node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctrl.scala 131:28]
|
||||
node _T_117 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 131:43]
|
||||
node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctrl.scala 131:41]
|
||||
node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctrl.scala 131:53]
|
||||
node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 131:73]
|
||||
node _T_121 = mux(io.exu_flush_final, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_124 = mux(_T_109, _T_111, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_125 = mux(_T_119, _T_120, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_126 = or(_T_121, _T_122) @[Mux.scala 27:72]
|
||||
node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
|
||||
node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
|
||||
node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
|
||||
wire _T_130 : UInt<4> @[Mux.scala 27:72]
|
||||
_T_130 <= _T_129 @[Mux.scala 27:72]
|
||||
fb_write_ns <= _T_130 @[el2_ifu_ifc_ctrl.scala 127:15]
|
||||
reg _T_131 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 134:26]
|
||||
_T_131 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 134:26]
|
||||
fb_full_f_ns <= _T_131 @[el2_ifu_ifc_ctrl.scala 134:16]
|
||||
node _T_132 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 136:17]
|
||||
idle <= _T_132 @[el2_ifu_ifc_ctrl.scala 136:8]
|
||||
node _T_133 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 137:16]
|
||||
wfm <= _T_133 @[el2_ifu_ifc_ctrl.scala 137:7]
|
||||
node _T_134 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 139:30]
|
||||
fb_full_f_ns <= _T_134 @[el2_ifu_ifc_ctrl.scala 139:16]
|
||||
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 140:26]
|
||||
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 140:26]
|
||||
node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 143:26]
|
||||
node _T_136 = or(_T_135, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 143:47]
|
||||
node _T_137 = not(_T_136) @[el2_ifu_ifc_ctrl.scala 143:5]
|
||||
node _T_138 = and(fb_full_f, _T_137) @[el2_ifu_ifc_ctrl.scala 142:75]
|
||||
node _T_139 = or(_T_138, dma_stall) @[el2_ifu_ifc_ctrl.scala 143:70]
|
||||
node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[el2_ifu_ifc_ctrl.scala 142:60]
|
||||
node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctrl.scala 142:33]
|
||||
io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctrl.scala 142:26]
|
||||
node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 203:25]
|
||||
node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 203:47]
|
||||
node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 206:14]
|
||||
node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 206:29]
|
||||
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 149:25]
|
||||
node _T_145 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 150:78]
|
||||
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_147 = dshr(io.dec_tlu_mrac_ff, _T_146) @[el2_ifu_ifc_ctrl.scala 150:53]
|
||||
node _T_148 = bits(_T_147, 0, 0) @[el2_ifu_ifc_ctrl.scala 150:53]
|
||||
node _T_149 = not(_T_148) @[el2_ifu_ifc_ctrl.scala 150:34]
|
||||
io.ifc_fetch_uncacheable_bf <= _T_149 @[el2_ifu_ifc_ctrl.scala 150:31]
|
||||
|
||||
|
|
|
|||
|
|
@ -27,9 +27,7 @@ module el2_ifu_ifc_ctrl(
|
|||
output io_ifc_fetch_req_bf_raw,
|
||||
output io_ifc_iccm_access_bf,
|
||||
output io_ifc_region_acc_fault_bf,
|
||||
output io_ifc_dma_access_ok,
|
||||
input io_testin,
|
||||
output [30:0] io_test1
|
||||
output io_ifc_dma_access_ok
|
||||
);
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [31:0] _RAND_0;
|
||||
|
|
@ -38,76 +36,76 @@ module el2_ifu_ifc_ctrl(
|
|||
reg [31:0] _RAND_3;
|
||||
reg [31:0] _RAND_4;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 78:37]
|
||||
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 79:36]
|
||||
wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 82:23]
|
||||
wire _T_2 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 82:46]
|
||||
wire _T_3 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 82:68]
|
||||
wire _T_4 = _T_2 | _T_3; // @[el2_ifu_ifc_ctrl.scala 82:66]
|
||||
wire sel_last_addr_bf = _T_1 & _T_4; // @[el2_ifu_ifc_ctrl.scala 82:43]
|
||||
wire _T_7 = _T_1 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 83:43]
|
||||
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 83:64]
|
||||
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 83:88]
|
||||
wire _T_12 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 84:66]
|
||||
wire _T_13 = _T_7 & _T_12; // @[el2_ifu_ifc_ctrl.scala 84:64]
|
||||
wire sel_next_addr_bf = _T_13 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 84:89]
|
||||
wire fetch_addr_next_1 = io_testin ? 1'h0 : io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctrl.scala 90:27]
|
||||
wire [30:0] _T_19 = io_ifc_fetch_addr_f + 31'h2; // @[el2_ifu_ifc_ctrl.scala 92:45]
|
||||
wire [31:0] fetch_addr_next = {_T_19,fetch_addr_next_1}; // @[Cat.scala 29:58]
|
||||
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 75:37]
|
||||
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 76:36]
|
||||
wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 79:23]
|
||||
wire _T_2 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 79:46]
|
||||
wire _T_3 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 79:68]
|
||||
wire _T_4 = _T_2 | _T_3; // @[el2_ifu_ifc_ctrl.scala 79:66]
|
||||
wire sel_last_addr_bf = _T_1 & _T_4; // @[el2_ifu_ifc_ctrl.scala 79:43]
|
||||
wire _T_7 = _T_1 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 80:43]
|
||||
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 80:64]
|
||||
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 80:88]
|
||||
wire _T_12 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 81:66]
|
||||
wire _T_13 = _T_7 & _T_12; // @[el2_ifu_ifc_ctrl.scala 81:64]
|
||||
wire sel_next_addr_bf = _T_13 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 81:89]
|
||||
wire [30:0] _T_16 = io_ifc_fetch_addr_f + 31'h2; // @[el2_ifu_ifc_ctrl.scala 84:42]
|
||||
wire [30:0] _GEN_1 = {{30'd0}, io_ifc_fetch_addr_f[0]}; // @[el2_ifu_ifc_ctrl.scala 84:48]
|
||||
wire [30:0] _T_20 = _T_16 | _GEN_1; // @[el2_ifu_ifc_ctrl.scala 84:48]
|
||||
wire [30:0] _T_25 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_26 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_27 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] fetch_addr_next = {{1'd0}, _T_20}; // @[el2_ifu_ifc_ctrl.scala 84:19]
|
||||
wire [31:0] _T_28 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_29 = _T_25 | _T_26; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_30 = _T_29 | _T_27; // @[Mux.scala 27:72]
|
||||
wire [31:0] _GEN_1 = {{1'd0}, _T_30}; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_31 = _GEN_1 | _T_28; // @[Mux.scala 27:72]
|
||||
wire _T_33 = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 102:88]
|
||||
wire [31:0] _GEN_2 = {{1'd0}, _T_30}; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_31 = _GEN_2 | _T_28; // @[Mux.scala 27:72]
|
||||
wire _T_33 = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 95:88]
|
||||
reg [30:0] _T_34; // @[Reg.scala 27:20]
|
||||
reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 125:19]
|
||||
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 144:17]
|
||||
reg [30:0] _T_36; // @[el2_ifu_ifc_ctrl.scala 106:32]
|
||||
wire _T_37 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 109:91]
|
||||
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctrl.scala 109:70]
|
||||
reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 117:19]
|
||||
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 136:17]
|
||||
reg [30:0] _T_36; // @[el2_ifu_ifc_ctrl.scala 99:32]
|
||||
wire _T_37 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 101:91]
|
||||
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctrl.scala 101:70]
|
||||
wire [3:0] fb_write_ns = {{3'd0}, io_exu_flush_final}; // @[Mux.scala 27:72]
|
||||
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 147:30]
|
||||
wire _T_39 = fb_full_f_ns & _T_38; // @[el2_ifu_ifc_ctrl.scala 109:68]
|
||||
wire _T_40 = ~_T_39; // @[el2_ifu_ifc_ctrl.scala 109:53]
|
||||
wire _T_41 = io_ifc_fetch_req_bf_raw & _T_40; // @[el2_ifu_ifc_ctrl.scala 109:51]
|
||||
wire _T_42 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 110:5]
|
||||
wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctrl.scala 109:114]
|
||||
wire _T_44 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 110:18]
|
||||
wire _T_45 = _T_43 & _T_44; // @[el2_ifu_ifc_ctrl.scala 110:16]
|
||||
wire _T_46 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 110:39]
|
||||
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 114:35]
|
||||
wire _T_61 = io_exu_flush_final & _T_46; // @[el2_ifu_ifc_ctrl.scala 118:36]
|
||||
wire leave_idle = _T_61 & idle; // @[el2_ifu_ifc_ctrl.scala 118:67]
|
||||
wire _T_68 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 120:55]
|
||||
wire _T_76 = _T_68 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 123:34]
|
||||
wire _T_79 = state[0] & _T_68; // @[el2_ifu_ifc_ctrl.scala 123:60]
|
||||
wire next_state_0 = _T_76 | _T_79; // @[el2_ifu_ifc_ctrl.scala 123:48]
|
||||
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 139:30]
|
||||
wire _T_39 = fb_full_f_ns & _T_38; // @[el2_ifu_ifc_ctrl.scala 101:68]
|
||||
wire _T_40 = ~_T_39; // @[el2_ifu_ifc_ctrl.scala 101:53]
|
||||
wire _T_41 = io_ifc_fetch_req_bf_raw & _T_40; // @[el2_ifu_ifc_ctrl.scala 101:51]
|
||||
wire _T_42 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 102:5]
|
||||
wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctrl.scala 101:114]
|
||||
wire _T_44 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 102:18]
|
||||
wire _T_45 = _T_43 & _T_44; // @[el2_ifu_ifc_ctrl.scala 102:16]
|
||||
wire _T_46 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 102:39]
|
||||
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 106:35]
|
||||
wire _T_61 = io_exu_flush_final & _T_46; // @[el2_ifu_ifc_ctrl.scala 110:36]
|
||||
wire leave_idle = _T_61 & idle; // @[el2_ifu_ifc_ctrl.scala 110:67]
|
||||
wire _T_68 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 112:55]
|
||||
wire _T_76 = _T_68 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 115:34]
|
||||
wire _T_79 = state[0] & _T_68; // @[el2_ifu_ifc_ctrl.scala 115:60]
|
||||
wire next_state_0 = _T_76 | _T_79; // @[el2_ifu_ifc_ctrl.scala 115:48]
|
||||
wire [1:0] _T_80 = {next_state_0,next_state_0}; // @[Cat.scala 29:58]
|
||||
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 145:16]
|
||||
reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 148:26]
|
||||
wire _T_136 = _T_37 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 151:47]
|
||||
wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctrl.scala 151:5]
|
||||
wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctrl.scala 150:75]
|
||||
wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 151:70]
|
||||
wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctrl.scala 150:60]
|
||||
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 137:16]
|
||||
reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 140:26]
|
||||
wire _T_136 = _T_37 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 143:47]
|
||||
wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctrl.scala 143:5]
|
||||
wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctrl.scala 142:75]
|
||||
wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 143:70]
|
||||
wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctrl.scala 142:60]
|
||||
wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_146 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _T_147 = io_dec_tlu_mrac_ff >> _T_146; // @[el2_ifu_ifc_ctrl.scala 158:53]
|
||||
assign io_ifc_fetch_addr_f = _T_34; // @[el2_ifu_ifc_ctrl.scala 67:23 el2_ifu_ifc_ctrl.scala 102:23]
|
||||
assign io_ifc_fetch_addr_bf = _T_31[30:0]; // @[el2_ifu_ifc_ctrl.scala 68:24 el2_ifu_ifc_ctrl.scala 96:24]
|
||||
assign io_ifc_fetch_req_f = _T_36[0]; // @[el2_ifu_ifc_ctrl.scala 69:22 el2_ifu_ifc_ctrl.scala 106:22]
|
||||
assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctrl.scala 70:26 el2_ifu_ifc_ctrl.scala 150:26]
|
||||
assign io_ifc_fetch_uncacheable_bf = ~_T_147[0]; // @[el2_ifu_ifc_ctrl.scala 71:31 el2_ifu_ifc_ctrl.scala 158:31]
|
||||
assign io_ifc_fetch_req_bf = _T_45 & _T_46; // @[el2_ifu_ifc_ctrl.scala 72:23 el2_ifu_ifc_ctrl.scala 109:23]
|
||||
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 73:27 el2_ifu_ifc_ctrl.scala 104:27]
|
||||
assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 74:25 el2_ifu_ifc_ctrl.scala 157:25]
|
||||
assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 75:30]
|
||||
assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 76:24]
|
||||
assign io_test1 = io_ifc_fetch_addr_bf; // @[el2_ifu_ifc_ctrl.scala 107:12]
|
||||
wire [30:0] _T_147 = io_dec_tlu_mrac_ff >> _T_146; // @[el2_ifu_ifc_ctrl.scala 150:53]
|
||||
assign io_ifc_fetch_addr_f = _T_34; // @[el2_ifu_ifc_ctrl.scala 64:23 el2_ifu_ifc_ctrl.scala 95:23]
|
||||
assign io_ifc_fetch_addr_bf = _T_31[30:0]; // @[el2_ifu_ifc_ctrl.scala 65:24 el2_ifu_ifc_ctrl.scala 89:24]
|
||||
assign io_ifc_fetch_req_f = _T_36[0]; // @[el2_ifu_ifc_ctrl.scala 66:22 el2_ifu_ifc_ctrl.scala 99:22]
|
||||
assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctrl.scala 67:26 el2_ifu_ifc_ctrl.scala 142:26]
|
||||
assign io_ifc_fetch_uncacheable_bf = ~_T_147[0]; // @[el2_ifu_ifc_ctrl.scala 68:31 el2_ifu_ifc_ctrl.scala 150:31]
|
||||
assign io_ifc_fetch_req_bf = _T_45 & _T_46; // @[el2_ifu_ifc_ctrl.scala 69:23 el2_ifu_ifc_ctrl.scala 101:23]
|
||||
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 70:27 el2_ifu_ifc_ctrl.scala 97:27]
|
||||
assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 71:25 el2_ifu_ifc_ctrl.scala 149:25]
|
||||
assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 72:30]
|
||||
assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 73:24]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,383 @@
|
|||
package ifu
|
||||
import lib._
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
|
||||
class el2_ifu_aln_ctl extends Module with el2_lib {
|
||||
val io = IO(new Bundle{
|
||||
val scan_mode = Input(Bool())
|
||||
val ifu_async_error_start = Input(Bool())
|
||||
val iccm_rd_ecc_double_err = Input(Bool())
|
||||
val ic_access_fault_f = Input(Bool())
|
||||
val ic_access_fault_type_f = Input(UInt(2.W))
|
||||
val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W))
|
||||
val ifu_bp_btb_target_f = Input(UInt(32.W))
|
||||
val ifu_bp_poffset_f = Input(UInt(12.W))
|
||||
val ifu_bp_hist0_f = Input(UInt(2.W))
|
||||
val ifu_bp_hist1_f = Input(UInt(2.W))
|
||||
val ifu_bp_pc4_f = Input(UInt(2.W))
|
||||
val ifu_bp_way_f = Input(UInt(2.W))
|
||||
val ifu_bp_valid_f = Input(UInt(2.W))
|
||||
val ifu_bp_ret_f = Input(UInt(2.W))
|
||||
val exu_flush_final = Input(Bool())
|
||||
val dec_i0_decode_d = Input(Bool())
|
||||
val ifu_fetch_data_f = Input(UInt(32.W))
|
||||
val ifu_fetch_val = Input(UInt(2.W))
|
||||
val ifu_fetch_pc = Input(UInt(32.W))
|
||||
val ifu_i0_valid = Output(Bool())
|
||||
val ifu_i0_icaf = Output(Bool())
|
||||
val ifu_i0_icaf_type = Output(UInt(2.W))
|
||||
val ifu_i0_icaf_f1 = Output(Bool())
|
||||
val ifu_i0_dbecc = Output(Bool())
|
||||
val ifu_i0_instr = Output(new ExpandedInstruction)
|
||||
val ifu_i0_pc = Output(UInt(32.W))
|
||||
val ifu_i0_pc4 = Output(Bool())
|
||||
val ifu_fb_consume1 = Output(Bool())
|
||||
val ifu_fb_consume2 = Output(Bool())
|
||||
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO).W))
|
||||
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
|
||||
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
|
||||
val ifu_pmu_instr_aligned = Output(Bool())
|
||||
val ifu_i0_cinst = Output(UInt(16.W))
|
||||
val i0_brp = Output(new el2_br_pkt_t)
|
||||
})
|
||||
val MHI = 46+BHT_GHR_SIZE // 54
|
||||
val MSIZE = 47+BHT_GHR_SIZE // 55
|
||||
|
||||
val error_stall_in = WireInit(Bool(),0.U)
|
||||
val alignval = WireInit(UInt(2.W), 0.U)
|
||||
val q0final = WireInit(UInt(16.W), 0.U)
|
||||
val q1final = WireInit(UInt(16.W), 0.U)
|
||||
val wrptr_in = WireInit(UInt(2.W), init = 0.U)
|
||||
val rdptr_in = WireInit(UInt(2.W), init = 0.U)
|
||||
|
||||
val f2val_in = WireInit(UInt(2.W), init = 0.U)
|
||||
val f1val_in = WireInit(UInt(2.W), init = 0.U)
|
||||
val f0val_in = WireInit(UInt(2.W), init = 0.U)
|
||||
|
||||
val q2off_in = WireInit(UInt(1.W), init = 0.U)
|
||||
val q1off_in = WireInit(UInt(1.W), init = 0.U)
|
||||
val q0off_in = WireInit(UInt(1.W), init = 0.U)
|
||||
|
||||
val sf0_valid = WireInit(Bool(), init = 0.U)
|
||||
val sf1_valid = WireInit(Bool(), init = 0.U)
|
||||
|
||||
val f2_valid = WireInit(Bool(), init = 0.U)
|
||||
val ifvalid = WireInit(Bool(), init = 0.U)
|
||||
val shift_f2_f1 = WireInit(Bool(), init = 0.U)
|
||||
val shift_f2_f0 = WireInit(Bool(), init = 0.U)
|
||||
val shift_f1_f0 = WireInit(Bool(), init = 0.U)
|
||||
|
||||
val f0icaf = WireInit(Bool(), init = 0.U)
|
||||
val f1icaf = WireInit(Bool(), init = 0.U)
|
||||
|
||||
val sf0val = WireInit(UInt(2.W), 0.U)
|
||||
val sf1val = WireInit(UInt(2.W), 0.U)
|
||||
|
||||
val misc0 = WireInit(UInt(MHI.W), 0.U)
|
||||
val misc1 = WireInit(UInt(MHI.W), 0.U)
|
||||
val misc2 = WireInit(UInt(MHI.W), 0.U)
|
||||
|
||||
val brdata1 = WireInit(UInt(12.W), init = 0.U)
|
||||
val brdata0 = WireInit(UInt(12.W), init = 0.U)
|
||||
val brdata2 = WireInit(UInt(12.W), init = 0.U)
|
||||
|
||||
|
||||
|
||||
val error_stall = RegNext(error_stall_in, init = 0.U)
|
||||
val f0val = RegNext(f0val_in, init = 0.U)
|
||||
error_stall_in := (error_stall | io.ifu_async_error_start) & ~io.exu_flush_final
|
||||
|
||||
val i0_shift = io.dec_i0_decode_d & ~error_stall
|
||||
|
||||
io.ifu_pmu_instr_aligned := i0_shift
|
||||
|
||||
val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final)))
|
||||
|
||||
val decompressed = Module(new el2_ifu_compress(32, true))
|
||||
|
||||
decompressed.io.in := aligndata
|
||||
|
||||
decompressed.io.out <> io.ifu_i0_instr
|
||||
|
||||
|
||||
// 16-bit compressed instruction from the aligner to the dec for tracer
|
||||
io.ifu_i0_cinst := aligndata(15,0)
|
||||
|
||||
// Checking if its a 32-bit instruction or not
|
||||
val first4B = decompressed.io.rvc
|
||||
val first2B = ~first4B
|
||||
val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
|
||||
|
||||
io.ifu_i0_icaf := Mux1H(Seq(first4B -> alignicaf.orR, first2B -> alignicaf(0)))
|
||||
io.ifu_i0_valid := Mux1H(Seq(first4B -> alignval(1), first2B -> alignval(0)))
|
||||
io.ifu_i0_pc4 := first4B
|
||||
|
||||
val shift_2B = i0_shift & first2B
|
||||
val shift_4B = i0_shift & first4B
|
||||
val f0_shift_2B = Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (~f0val(0) & f0val(0))))
|
||||
val f1_shift_2B = f0val(0) & ~f0val(1) & shift_4B
|
||||
|
||||
val wrptr = RegNext(wrptr_in, init = 0.U)
|
||||
val rdptr = RegNext(wrptr_in, init = 0.U)
|
||||
|
||||
val f2val = RegNext(f2val_in, init = 0.U)
|
||||
val f1val = RegNext(f1val_in, init = 0.U)
|
||||
|
||||
|
||||
val q2off = RegNext(q2off_in, init = 0.U)
|
||||
val q1off = RegNext(q1off_in, init = 0.U)
|
||||
val q0off = RegNext(q0off_in, init = 0.U)
|
||||
|
||||
val fetch_to_f0 = ~sf0_valid & ~sf1_valid & ~f2_valid & ifvalid
|
||||
val fetch_to_f1 = (~sf0_valid & ~sf1_valid & f2_valid & ifvalid) |
|
||||
(~sf0_valid & sf1_valid & ~f2_valid & ifvalid) |
|
||||
( sf0_valid & ~sf1_valid & ~f2_valid & ifvalid)
|
||||
val fetch_to_f2 = (~sf0_valid & sf1_valid & f2_valid & ifvalid) |
|
||||
( sf0_valid & sf1_valid & ~f2_valid & ifvalid)
|
||||
|
||||
val f2_wr_en = fetch_to_f2
|
||||
val f1_shift_wr_en = fetch_to_f1 | shift_f2_f1 | f1_shift_2B
|
||||
val f0_shift_wr_en = fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
|
||||
|
||||
val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
|
||||
val qwen = Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
|
||||
|
||||
rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & ~io.exu_flush_final).asBool -> 1.U,
|
||||
(qren(1) & io.ifu_fb_consume1 & ~io.exu_flush_final).asBool -> 2.U,
|
||||
(qren(2) & io.ifu_fb_consume1 & ~io.exu_flush_final).asBool -> 0.U,
|
||||
(qren(0) & io.ifu_fb_consume2 & ~io.exu_flush_final).asBool -> 2.U,
|
||||
(qren(1) & io.ifu_fb_consume2 & ~io.exu_flush_final).asBool -> 0.U,
|
||||
(qren(2) & io.ifu_fb_consume2 & ~io.exu_flush_final).asBool -> 1.U,
|
||||
(~io.ifu_fb_consume1 & ~io.ifu_fb_consume2 & ~io.exu_flush_final).asBool -> rdptr))
|
||||
|
||||
wrptr_in := Mux1H(Seq((qwen(0) & ~io.exu_flush_final).asBool -> 1.U,
|
||||
(qwen(1) & ~io.exu_flush_final).asBool -> 2.U,
|
||||
(qwen(2) & ~io.exu_flush_final).asBool -> 0.U,
|
||||
(~ifvalid & ~io.exu_flush_final).asBool->wrptr))
|
||||
|
||||
q2off_in := Mux1H(Seq((~qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
|
||||
(~qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
|
||||
(~qwen(2) & (rdptr===0.U)).asBool->q2off))
|
||||
|
||||
q1off_in := Mux1H(Seq((~qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
|
||||
(~qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
|
||||
(~qwen(1) & (rdptr===2.U)).asBool->q1off))
|
||||
|
||||
q0off_in := Mux1H(Seq((~qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
|
||||
(~qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
|
||||
(~qwen(0) & (rdptr===1.U)).asBool -> q0off))
|
||||
|
||||
val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
|
||||
(rdptr===1.U)->q1off,
|
||||
(rdptr===2.U)->q2off))
|
||||
|
||||
val q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
|
||||
|
||||
val q0sel = Cat(q0ptr, ~q0ptr)
|
||||
|
||||
val q1sel = Cat(q1ptr, ~q1ptr)
|
||||
|
||||
val misc_data_in = Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
|
||||
io.ifu_bp_btb_target_f(31,1), io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
|
||||
|
||||
val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
|
||||
qren(1).asBool()->Cat(misc2, misc1),
|
||||
qren(2).asBool()->Cat(misc0, misc2)))
|
||||
|
||||
val misc1eff = misceff(misceff.getWidth-1,MHI+1)
|
||||
val misc0eff = misceff(MHI, 0)
|
||||
|
||||
val f1dbecc = misc1eff(misc1eff.getWidth-1)
|
||||
f1icaf := misc1eff(misc1eff.getWidth-2)
|
||||
val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
|
||||
val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
|
||||
val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
|
||||
val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
|
||||
|
||||
val f0dbecc = misc0eff(misc0eff.getWidth-1)
|
||||
f0icaf := misc0eff(misc0eff.getWidth-2)
|
||||
val f0ictype = misc0eff(misc0eff.getWidth-3,misc0eff.getWidth-4)
|
||||
val f0prett = misc0eff(misc0eff.getWidth-5,misc0eff.getWidth-35)
|
||||
val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
|
||||
val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
|
||||
|
||||
val brdata_in = Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
|
||||
io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
|
||||
io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
|
||||
|
||||
val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
|
||||
qren(1).asBool->Cat(brdata2,brdata1),
|
||||
qren(2).asBool->Cat(brdata0,brdata2)))
|
||||
|
||||
val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
|
||||
|
||||
val q0 = WireInit(UInt(32.W), init = 0.U)
|
||||
val q1 = WireInit(UInt(32.W), init = 0.U)
|
||||
val q2 = WireInit(UInt(32.W), init = 0.U)
|
||||
|
||||
val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
|
||||
qren(1).asBool->Cat(q2,q1),
|
||||
qren(2).asBool->Cat(q0,q2)))
|
||||
val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
|
||||
val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
|
||||
|
||||
val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
|
||||
|
||||
val f0ret = Cat(brdata0final(6),brdata0final(0))
|
||||
val f0brend = Cat(brdata0final(7),brdata0final(1))
|
||||
val f0way = Cat(brdata0final(8),brdata0final(2))
|
||||
val f0pc4 = Cat(brdata0final(9),brdata0final(3))
|
||||
val f0hist0 = Cat(brdata0final(10),brdata0final(4))
|
||||
val f0hist1 = Cat(brdata0final(11),brdata0final(5))
|
||||
|
||||
val f1ret = Cat(brdata1final(6),brdata1final(0))
|
||||
val f1brend = Cat(brdata1final(7),brdata1final(1))
|
||||
val f1way = Cat(brdata1final(8),brdata1final(2))
|
||||
val f1pc4 = Cat(brdata1final(9),brdata1final(3))
|
||||
val f1hist0 = Cat(brdata1final(10),brdata1final(4))
|
||||
val f1hist1 = Cat(brdata1final(11),brdata1final(5))
|
||||
|
||||
|
||||
|
||||
f2_valid := f2val(0)
|
||||
sf1_valid := sf1val(0)
|
||||
sf0_valid := sf0val(0)
|
||||
|
||||
val consume_fb0 = ~sf0val(0) & f0val(0)
|
||||
val consume_fb1 = ~sf1val(0) & f1val(0)
|
||||
|
||||
io.ifu_fb_consume1 := consume_fb0 & ~consume_fb1 & ~io.exu_flush_final
|
||||
io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & ~io.exu_flush_final
|
||||
|
||||
ifvalid := io.ifu_fetch_val(0)
|
||||
|
||||
shift_f1_f0 := ~sf0_valid & sf1_valid
|
||||
shift_f2_f0 := ~sf0_valid & ~sf1_valid & f2_valid
|
||||
shift_f2_f1 := ~sf0_valid & sf1_valid & f2_valid
|
||||
|
||||
val f0pc = WireInit(UInt(31.W), 0.U)
|
||||
val f2pc = WireInit(UInt(31.W), 0.U)
|
||||
|
||||
val f0pc_plus1 = f0pc + 1.U
|
||||
|
||||
val sf1pc = (Fill(31, f1_shift_2B) & f0pc_plus1) | (Fill(31, ~f1_shift_2B) & f0pc)
|
||||
|
||||
val f1pc_in = Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
|
||||
shift_f2_f1.asBool->f2pc,
|
||||
(~fetch_to_f1 & ~shift_f2_f1).asBool -> sf1pc))
|
||||
|
||||
val f0pc_in = Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
|
||||
shift_f2_f0.asBool->f2pc,
|
||||
shift_f1_f0.asBool->sf1pc,
|
||||
(~fetch_to_f0 & ~shift_f2_f0 & ~shift_f1_f0).asBool->f0pc_plus1))
|
||||
|
||||
f2val_in := Mux1H(Seq((fetch_to_f2 & ~io.exu_flush_final).asBool->io.ifu_fetch_val,
|
||||
(~fetch_to_f2 & ~shift_f2_f1 & ~shift_f2_f0 & ~io.exu_flush_final).asBool->f2val))
|
||||
|
||||
sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), ~f1_shift_2B.asBool->f1val))
|
||||
|
||||
f1val_in := Mux1H(Seq((fetch_to_f1 & ~io.exu_flush_final).asBool -> io.ifu_fetch_val,
|
||||
(shift_f2_f1 & ~io.exu_flush_final).asBool->f2val,
|
||||
(~fetch_to_f1 & ~shift_f2_f1 & ~shift_f1_f0 & ~io.exu_flush_final).asBool->sf1val))
|
||||
|
||||
f0val := Mux1H(Seq(shift_2B.asBool -> f0val(1), (~shift_2B & ~shift_4B).asBool -> f0val))
|
||||
|
||||
f0val_in := Mux1H(Seq((fetch_to_f0 & ~io.exu_flush_final).asBool->io.ifu_fetch_val,
|
||||
(shift_f2_f0 & ~io.exu_flush_final).asBool->f2val,
|
||||
(shift_f1_f0 & ~io.exu_flush_final).asBool()->sf1val,
|
||||
(~fetch_to_f0 & ~shift_f2_f0 & ~shift_f1_f0 & ~io.exu_flush_final).asBool->sf0val))
|
||||
|
||||
q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16)))
|
||||
|
||||
q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
|
||||
|
||||
alignval := Mux1H(Seq(f0val(1).asBool->3.U, (~f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))
|
||||
|
||||
val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (~f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc)))
|
||||
|
||||
val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (~f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0))))
|
||||
|
||||
val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (~f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0))))
|
||||
|
||||
val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (~f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0))))
|
||||
|
||||
val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (~f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0))))
|
||||
|
||||
val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (~f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0))))
|
||||
|
||||
val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (~f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0))))
|
||||
|
||||
val alignfromf1 = ~f0val(1) & f0val(0)
|
||||
|
||||
val f1pc = WireInit(UInt(31.W), init = 0.U)
|
||||
|
||||
val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (~f0val(1) & f0val(0)).asBool->f1pc))
|
||||
|
||||
io.ifu_i0_pc := f0pc
|
||||
|
||||
val firstpc = f0pc
|
||||
|
||||
io.ifu_i0_icaf_type := Mux((first4B & ~f0val(1) & f0val(0) & ~alignicaf(0) & ~aligndbecc(0)).asBool, f1ictype, f0ictype)
|
||||
|
||||
val icaf_eff = alignicaf(1) | aligndbecc(1)
|
||||
|
||||
io.ifu_i0_icaf_f1 := first4B & icaf_eff & alignfromf1
|
||||
|
||||
io.ifu_i0_dbecc := Mux1H(Seq(first4B->aligndbecc.orR, first2B->aligndbecc(0)))
|
||||
|
||||
val firstpc_hash = el2_btb_addr_hash(f0pc)
|
||||
|
||||
val secondpc_hash = el2_btb_addr_hash(secondpc)
|
||||
|
||||
val firstbrtag_hash = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(firstpc) else el2_btb_tag_hash(firstpc)
|
||||
|
||||
val secondbrtag_hash = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(secondpc) else el2_btb_tag_hash(secondpc)
|
||||
|
||||
io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
|
||||
|
||||
io.i0_brp.ret := (first2B & alignret(0)) | (first4B & alignret(1))
|
||||
|
||||
io.i0_brp.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
|
||||
io.i0_brp.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
|
||||
(first2B & alignhist0(0)) | (first4B & alignhist0(1)))
|
||||
|
||||
io.i0_brp.toffset := Mux((first4B & alignfromf1).asBool, f1poffset, f0poffset)
|
||||
|
||||
io.i0_brp.prett := Mux((first4B & alignfromf1).asBool, f1prett, f0prett)
|
||||
|
||||
io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0))
|
||||
|
||||
io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(1), secondpc(1))
|
||||
|
||||
val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
|
||||
|
||||
io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & ~i0_brp_pc4 & first4B)
|
||||
|
||||
|
||||
io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
|
||||
|
||||
io.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr)
|
||||
|
||||
io.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
|
||||
|
||||
brdata2 := RegEnable(brdata_in, 0.U, qwen(2))
|
||||
brdata1 := RegEnable(brdata_in, 0.U, qwen(1))
|
||||
brdata0 := RegEnable(brdata_in, 0.U, qwen(0))
|
||||
|
||||
misc2 := RegEnable(misc_data_in, 0.U, qwen(2))
|
||||
misc1 := RegEnable(misc_data_in, 0.U, qwen(1))
|
||||
misc0 := RegEnable(misc_data_in, 0.U, qwen(0))
|
||||
|
||||
q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2))
|
||||
q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1))
|
||||
q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0))
|
||||
|
||||
f2pc := RegEnable(io.ifu_fetch_pc, 0.U, f2_wr_en.asBool)
|
||||
f2pc := RegEnable(f1pc_in, 0.U, f1_shift_wr_en.asBool)
|
||||
f2pc := RegEnable(f0pc_in, 0.U, f0_shift_wr_en.asBool)
|
||||
}
|
||||
object ifu_aln extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl()))
|
||||
}
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
package ifu
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import lib.ExpandedInstruction
|
||||
|
||||
class ExpandedInstruction extends Bundle {
|
||||
val bits = UInt(32.W)
|
||||
val rd = UInt(5.W)
|
||||
val rs1 = UInt(5.W)
|
||||
val rs2 = UInt(5.W)
|
||||
val rs3 = UInt(5.W)
|
||||
}
|
||||
|
||||
class RVCDecoder(x: UInt, xLen: Int) {
|
||||
def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
|
||||
val res = Wire(new ExpandedInstruction)
|
||||
res.bits := bits
|
||||
res.rd := rd
|
||||
res.rs1 := rs1
|
||||
res.rs2 := rs2
|
||||
res.rs3 := rs3
|
||||
res
|
||||
}
|
||||
|
||||
def rs1p = Cat(1.U(2.W), x(9,7))
|
||||
def rs2p = Cat(1.U(2.W), x(4,2))
|
||||
def rs2 = x(6,2)
|
||||
def rd = x(11,7)
|
||||
def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W))
|
||||
def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W))
|
||||
def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W))
|
||||
def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W))
|
||||
def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W))
|
||||
def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W))
|
||||
def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W))
|
||||
def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W))
|
||||
def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W))
|
||||
def addiImm = Cat(Fill(7, x(12)), x(6,2))
|
||||
def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W))
|
||||
def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W))
|
||||
def shamt = Cat(x(12), x(6,2))
|
||||
def x0 = 0.U(5.W)
|
||||
def ra = 1.U(5.W)
|
||||
def sp = 2.U(5.W)
|
||||
|
||||
def q0 = {
|
||||
def addi4spn = {
|
||||
val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
|
||||
inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
|
||||
}
|
||||
def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def flw = {
|
||||
if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
||||
else ld
|
||||
}
|
||||
def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def fsw = {
|
||||
if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
||||
else sd
|
||||
}
|
||||
Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)
|
||||
}
|
||||
|
||||
def q1 = {
|
||||
def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p)
|
||||
def addiw = {
|
||||
val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W))
|
||||
inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
|
||||
}
|
||||
def jal = {
|
||||
if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p)
|
||||
else addiw
|
||||
}
|
||||
def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p)
|
||||
def addi16sp = {
|
||||
val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W))
|
||||
inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
|
||||
}
|
||||
def lui = {
|
||||
val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W))
|
||||
val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)
|
||||
Mux(rd === x0 || rd === sp, addi16sp, me)
|
||||
}
|
||||
def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p)
|
||||
def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0)
|
||||
def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0)
|
||||
def arith = {
|
||||
def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W))
|
||||
def srai = srli | (1 << 30).U
|
||||
def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W))
|
||||
def rtype = {
|
||||
val funct = VecInit(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))
|
||||
val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U)
|
||||
val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W))
|
||||
Cat(rs2p, rs1p, funct, rs1p, opc) | sub
|
||||
}
|
||||
inst(VecInit(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)
|
||||
}
|
||||
Seq(addi, jal, li, lui, arith, j, beqz, bnez)
|
||||
}
|
||||
|
||||
def q2 = {
|
||||
val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W))
|
||||
def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2)
|
||||
def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2)
|
||||
def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2)
|
||||
def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
|
||||
def flwsp = {
|
||||
if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
|
||||
else ldsp
|
||||
}
|
||||
def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
|
||||
def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
|
||||
def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
|
||||
def fswsp = {
|
||||
if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
|
||||
else sdsp
|
||||
}
|
||||
def jalr = {
|
||||
val mv = inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2)
|
||||
val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2)
|
||||
val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W))
|
||||
val reserved = Cat(jr >> 7, 0x1F.U(7.W))
|
||||
val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)
|
||||
val jr_mv = Mux(rs2.orR, mv, jr_reserved)
|
||||
val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W))
|
||||
val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U
|
||||
val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)
|
||||
val jalr_add = Mux(rs2.orR, add, jalr_ebreak)
|
||||
Mux(x(12), jalr_add, jr_mv)
|
||||
}
|
||||
Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)
|
||||
}
|
||||
|
||||
def q3 = Seq.fill(8)(passthrough)
|
||||
|
||||
def passthrough = inst(x)
|
||||
|
||||
def decode = {
|
||||
val s = VecInit(q0 ++ q1 ++ q2 ++ q3)
|
||||
s(Cat(x(1,0), x(15,13)))
|
||||
}
|
||||
|
||||
|
||||
|
||||
def changed_q0 = {
|
||||
def addi4spn = {
|
||||
val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
|
||||
inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
|
||||
}
|
||||
def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def flw = {
|
||||
if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
||||
else ld
|
||||
}
|
||||
def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
||||
def fsw = {
|
||||
if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
||||
else sd
|
||||
}
|
||||
addi4spn
|
||||
}
|
||||
|
||||
def ret_q0 = VecInit(q0)
|
||||
def ret_q1 = q1
|
||||
def ret_q2 = q2
|
||||
def ret_q3 = q3
|
||||
}
|
||||
|
||||
class el2_ifu_compress( val XLen: Int, val usingCompressed: Boolean) extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val in = Input(UInt(32.W))
|
||||
val out = Output(new ExpandedInstruction)
|
||||
val rvc = Output(Bool())
|
||||
//val legal = Output(Bool())
|
||||
//val waleed_out = Output(UInt(32.W))
|
||||
//val q1_Out = Output(new ExpandedInstruction)
|
||||
//val q2_Out = Output(new ExpandedInstruction)
|
||||
//val q3_Out = Output(new ExpandedInstruction)
|
||||
})
|
||||
if (usingCompressed) {
|
||||
io.rvc := io.in(1,0) =/= 3.U
|
||||
val inst = new RVCDecoder(io.in, XLen)
|
||||
io.out := inst.decode
|
||||
/*io.legal := (!io.in(13))&(!io.in(12))&(io.in(11))&io.in(1)&(!io.in(0)) |
|
||||
(!io.in(13))&(!io.in(12))&(io.in(6))&io.in(1)&(!io.in(0)) |
|
||||
(!io.in(15))&(!io.in(13))&io.in(11)(!io.in(1)) |
|
||||
(!io.in(13))&(!io.in(12))&io.in(5)&io.in(1)&(!io.in(0)) |
|
||||
(!io.in(13))&(!io.in(12))&io.in(10)&(!io.in(1))&io.in(0) |
|
||||
(!io.in(15))&(!io.in(13))&io.in(6)&(!io.in(1)) | io.in(15)&(!io.in(12))&(!io.in(1))&io.in(0) |
|
||||
(!io.in(13))&(!io.in(12))&io.in(9)&io.in(1)&(!io.in(0)) |
|
||||
(!io.in(12))&io.in(6)&(!io.in(1))&io.in(0) |
|
||||
(!io.in(15))&(!io.in(13))&io.in(5)&(!io.in(1)) |
|
||||
(!io.in(13))&(!io.in(12))&io.in(8)&io.in(1)&(!io.in(0)) |
|
||||
(!io.in(12))&io.in(5)&(!io.in(1))&io.in(0) |
|
||||
(!io.in(15))&(!io.in(13))&io.in(10)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(7)&io.in(1)&(!io.in(0)) |
|
||||
io.in(12)&io.in(11)&(!io.in(10))&(!io.in(1))&io.in(0) | (!io.in(15))&(!io.in(13))&io.in(9)&(!io.in(1)) |
|
||||
(!io.in(13))&(!io.in(12))&io.in(4)&io.in(1)&(!io.in(0)) | io.in(13)&io.in(12)&(!io.in(1))&io.in(0) |
|
||||
(!io.in(15))&(!io.in(13))&io.in(8)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(3)&io.in(1)&(!io.in(0)) |
|
||||
io.in(13)&io.in(4)&(!io.in(1))&io.in(0) | (!io.in(13))&(!io.in(12))&io.in(2)&io.in(1)&(!io.in(0)) |
|
||||
(!io.in(15))&(!io.in(13))&io.in(7)&(!io.in(1)) | io.in(13)&io.in(3)&(!io.in(1))&io.in(0) |
|
||||
io.in(13)&io.in(2)&(!io.in(1))&io.in(0) | io.in(14)&(!io.in(13))&(!io.in(1)) |
|
||||
(!io.in(14))&(!io.in(12))&(!io.in(1))&io.in(0) | io.in(15)&(!io.in(13))&io.in(12)&io.in(1)&(!io.in(0)) |
|
||||
(!io.in(15))&(!io.in(13))&(!io.in(12))&io.in(1)&(!io.in(0)) | (!io.in(15))&(!io.in(13))&io.in(12)&(!io.in(1)) |
|
||||
io.in(14)&(!io.in(13))&(!io.in(0))
|
||||
io.waleed_out := Mux(io.legal,io.out.bits,0.U)*/
|
||||
} else {
|
||||
io.rvc := false.B
|
||||
io.out := new RVCDecoder(io.in, XLen).passthrough
|
||||
}
|
||||
}
|
||||
|
|
@ -56,8 +56,8 @@ val io = IO(new Bundle{
|
|||
val goto_idle = WireInit(Bool(), init = 0.U)
|
||||
val leave_idle = WireInit(Bool(), init = 0.U)
|
||||
val fetch_bf_en = WireInit(Bool(), init = 0.U)
|
||||
val line_wrap = WireInit(Bool(), init = io.testin)
|
||||
val fetch_addr_next_1 = WireInit(Bool(), init = 0.U)
|
||||
val line_wrap = WireInit(Bool(), init = 0.U)
|
||||
//val fetch_addr_next_1 = WireInit(Bool(), init = 0.U)
|
||||
val state = WireInit(UInt(2.W), init = 0.U)
|
||||
val idle_E :: fetch_E :: stall_E :: wfm_E :: Nil = Enum(4)
|
||||
|
||||
|
|
@ -81,12 +81,8 @@ val io = IO(new Bundle{
|
|||
sel_next_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & ~io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||
|
||||
|
||||
// Checking the end of cache line wrapping
|
||||
//line_wrap := fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO)
|
||||
|
||||
fetch_addr_next_1 := Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0))
|
||||
|
||||
fetch_addr_next := Cat(io.ifc_fetch_addr_f+2.U,fetch_addr_next_1)
|
||||
fetch_addr_next := (io.ifc_fetch_addr_f+2.U) |
|
||||
Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0))
|
||||
|
||||
|
||||
// TODO: Make an assertion for the 1H-Mux under here
|
||||
|
|
@ -154,6 +150,3 @@ val io = IO(new Bundle{
|
|||
io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
|
||||
}
|
||||
|
||||
object ifu_ifc extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl()))
|
||||
}
|
||||
|
|
@ -1,5 +1,324 @@
|
|||
package include
|
||||
import chisel3._
|
||||
|
||||
class el2_bundle {
|
||||
|
||||
// use this for instance declaration val io = IO(Output(new el2_trace_pkt_t))
|
||||
class el2_trace_pkt_t extends Bundle{
|
||||
val rv_i_valid_ip = UInt(2.W)
|
||||
val rv_i_insn_ip = UInt(32.W)
|
||||
val rv_i_address_ip = UInt(32.W)
|
||||
val rv_i_exception_ip = UInt(2.W)
|
||||
val rv_i_ecause_ip = UInt(5.W)
|
||||
val rv_i_interrupt_ip = UInt(2.W)
|
||||
val rv_i_tval_ip = UInt(32.W)
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
object el2_inst_pkt_t extends Enumeration{
|
||||
val NULL = "b0000".U(4.W)
|
||||
val MUL = "b0001".U(4.W)
|
||||
val LOAD = "b0010".U(4.W)
|
||||
val STORE = "b0011".U(4.W)
|
||||
val ALU = "b0100".U(4.W)
|
||||
val CSRREAD = "b0101".U(4.W)
|
||||
val CSRWRITE = "b0110".U(4.W)
|
||||
val CSRRW = "b0111".U(4.W)
|
||||
val EBREAK = "b1000".U(4.W)
|
||||
val ECALL = "b1001".U(4.W)
|
||||
val FENCE = "b1010".U(4.W)
|
||||
val FENCEI = "b1011".U(4.W)
|
||||
val MRET = "b1100".U(4.W)
|
||||
val CONDBR = "b1101".U(4.W)
|
||||
val JAL = "b1110".U(4.W)
|
||||
val BITMANIPU = "b1111".U(4.W)
|
||||
}
|
||||
|
||||
|
||||
class el2_load_cam_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
val wb = UInt(1.W)
|
||||
val tag = UInt(3.W)
|
||||
val rd = UInt(5.W)
|
||||
}
|
||||
|
||||
class el2_rets_pkt_t extends Bundle {
|
||||
val pc0_call = UInt(1.W)
|
||||
val pc0_ret = UInt(1.W)
|
||||
val pc0_pc4 = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_br_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
val toffset = UInt(12.W)
|
||||
val hist = UInt(2.W)
|
||||
val br_error = UInt(1.W)
|
||||
val br_start_error = UInt(1.W)
|
||||
val bank = UInt(1.W)
|
||||
val prett = UInt(32.W) // predicted ret target //[31:1] in swerv
|
||||
val way = UInt(1.W)
|
||||
val ret = UInt(1.W)
|
||||
}
|
||||
|
||||
|
||||
class el2_br_tlu_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
val hist = UInt(2.W)
|
||||
val br_error = UInt(1.W)
|
||||
val br_start_error = UInt(1.W)
|
||||
val way = UInt(1.W)
|
||||
val middle = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_predict_pkt_t extends Bundle {
|
||||
val misp = UInt(1.W)
|
||||
val ataken = UInt(1.W)
|
||||
val boffset = UInt(1.W)
|
||||
val pc4 = UInt(1.W)
|
||||
val hist = UInt(2.W)
|
||||
val toffset = UInt(12.W)
|
||||
val valid = UInt(1.W)
|
||||
val br_error = UInt(1.W)
|
||||
val br_start_error = UInt(1.W)
|
||||
val prett = UInt(32.W) //[31:1] in swerv
|
||||
val pcall = UInt(1.W)
|
||||
val pret = UInt(1.W)
|
||||
val pja = UInt(1.W)
|
||||
val way = UInt(1.W)
|
||||
}
|
||||
|
||||
|
||||
class el2_trap_pkt_t extends Bundle {
|
||||
val legal = UInt(1.W)
|
||||
val icaf = UInt(1.W)
|
||||
val icaf_f1 = UInt(1.W)
|
||||
val icaf_type = UInt(2.W)
|
||||
val fence_i = UInt(1.W)
|
||||
val i0trigger = UInt(4.W)
|
||||
val pmu_i0_itype = el2_inst_pkt_t //pmu-instructiontype
|
||||
val pmu_i0_br_unpred = UInt(1.W) //pmu
|
||||
val pmu_divide = UInt(1.W)
|
||||
val pmu_lsu_misaligned = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_dest_pkt_t extends Bundle {
|
||||
val i0rd = UInt(5.W)
|
||||
val i0load = UInt(1.W)
|
||||
val i0store = UInt(1.W)
|
||||
val i0div = UInt(1.W)
|
||||
val i0v = UInt(1.W)
|
||||
val i0valid = UInt(1.W)
|
||||
val csrwen = UInt(1.W)
|
||||
val csrwonly = UInt(1.W)
|
||||
val csrwaddr = UInt(12.W)
|
||||
}
|
||||
|
||||
class el2_class_pkt_t extends Bundle {
|
||||
val mul = UInt(1.W)
|
||||
val load = UInt(1.W)
|
||||
val alu = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_reg_pkt_t extends Bundle {
|
||||
val rs1 = UInt(5.W)
|
||||
val rs2 = UInt(5.W)
|
||||
val rd = UInt(5.W)
|
||||
}
|
||||
|
||||
|
||||
class el2_alu_pkt_t extends Bundle {
|
||||
val land = UInt(1.W)
|
||||
val lor = UInt(1.W)
|
||||
val lxor = UInt(1.W)
|
||||
val sll = UInt(1.W)
|
||||
val srl = UInt(1.W)
|
||||
val sra = UInt(1.W)
|
||||
val beq = UInt(1.W)
|
||||
val bne = UInt(1.W)
|
||||
val blt = UInt(1.W)
|
||||
val bge = UInt(1.W)
|
||||
val add = UInt(1.W)
|
||||
val sub = UInt(1.W)
|
||||
val slt = UInt(1.W)
|
||||
val unsign = UInt(1.W)
|
||||
val jal = UInt(1.W)
|
||||
val predict_t = UInt(1.W)
|
||||
val predict_nt = UInt(1.W)
|
||||
val csr_write = UInt(1.W)
|
||||
val csr_imm = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_lsu_pkt_t extends Bundle {
|
||||
val fast_int = UInt(1.W)
|
||||
val by = UInt(1.W)
|
||||
val half = UInt(1.W)
|
||||
val word = UInt(1.W)
|
||||
val dword = UInt(1.W) // for dma
|
||||
val load = UInt(1.W)
|
||||
val store = UInt(1.W)
|
||||
val unsign = UInt(1.W)
|
||||
val dma = UInt(1.W) // dma pkt
|
||||
val store_data_bypass_d = UInt(1.W)
|
||||
val load_ldst_bypass_d = UInt(1.W)
|
||||
val store_data_bypass_m = UInt(1.W)
|
||||
val valid = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_lsu_error_pkt_t extends Bundle {
|
||||
val exc_valid = UInt(1.W)
|
||||
val single_ecc_error = UInt(1.W)
|
||||
val inst_type = UInt(1.W) //0: Load, 1: Store
|
||||
val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault
|
||||
val mscause = UInt(4.W)
|
||||
val addr = UInt(32.W)
|
||||
}
|
||||
|
||||
class el2_dec_pkt_t extends Bundle {
|
||||
val alu = UInt(1.W)
|
||||
val rs1 = UInt(1.W)
|
||||
val rs2 = UInt(1.W)
|
||||
val imm12 = UInt(1.W)
|
||||
val rd = UInt(1.W)
|
||||
val shimm5 = UInt(1.W)
|
||||
val imm20 = UInt(1.W)
|
||||
val pc = UInt(1.W)
|
||||
val load = UInt(1.W)
|
||||
val store = UInt(1.W)
|
||||
val lsu = UInt(1.W)
|
||||
val add = UInt(1.W)
|
||||
val sub = UInt(1.W)
|
||||
val land = UInt(1.W)
|
||||
val lor = UInt(1.W)
|
||||
val lxor = UInt(1.W)
|
||||
val sll = UInt(1.W)
|
||||
val sra = UInt(1.W)
|
||||
val srl = UInt(1.W)
|
||||
val slt = UInt(1.W)
|
||||
val unsign = UInt(1.W)
|
||||
val condbr = UInt(1.W)
|
||||
val beq = UInt(1.W)
|
||||
val bne = UInt(1.W)
|
||||
val bge = UInt(1.W)
|
||||
val blt = UInt(1.W)
|
||||
val jal = UInt(1.W)
|
||||
val by = UInt(1.W)
|
||||
val half = UInt(1.W)
|
||||
val word = UInt(1.W)
|
||||
val csr_read = UInt(1.W)
|
||||
val csr_clr = UInt(1.W)
|
||||
val csr_set = UInt(1.W)
|
||||
val csr_write = UInt(1.W)
|
||||
val csr_imm = UInt(1.W)
|
||||
val presync = UInt(1.W)
|
||||
val postsync = UInt(1.W)
|
||||
val ebreak = UInt(1.W)
|
||||
val ecall = UInt(1.W)
|
||||
val mret = UInt(1.W)
|
||||
val mul = UInt(1.W)
|
||||
val rs1_sign = UInt(1.W)
|
||||
val rs2_sign = UInt(1.W)
|
||||
val low = UInt(1.W)
|
||||
val div = UInt(1.W)
|
||||
val rem = UInt(1.W)
|
||||
val fence = UInt(1.W)
|
||||
val fence_i = UInt(1.W)
|
||||
val pm_alu = UInt(1.W)
|
||||
val legal = UInt(1.W)
|
||||
}
|
||||
|
||||
|
||||
class el2_mul_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
val rs1_sign = UInt(1.W)
|
||||
val rs2_sign = UInt(1.W)
|
||||
val low = UInt(1.W)
|
||||
val bext = UInt(1.W)
|
||||
val bdep = UInt(1.W)
|
||||
val clmul = UInt(1.W)
|
||||
val clmulh = UInt(1.W)
|
||||
val clmulr = UInt(1.W)
|
||||
val grev = UInt(1.W)
|
||||
val shfl = UInt(1.W)
|
||||
val unshfl = UInt(1.W)
|
||||
val crc32_b = UInt(1.W)
|
||||
val crc32_h = UInt(1.W)
|
||||
val crc32_w = UInt(1.W)
|
||||
val crc32c_b = UInt(1.W)
|
||||
val crc32c_h = UInt(1.W)
|
||||
val crc32c_w = UInt(1.W)
|
||||
val bfp = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_div_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
val unsign = UInt(1.W)
|
||||
val rem = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_ccm_ext_in_pkt_t extends Bundle {
|
||||
val TEST1 = UInt(1.W)
|
||||
val RME = UInt(1.W)
|
||||
val RM = UInt(4.W)
|
||||
|
||||
val LS = UInt(1.W)
|
||||
val DS = UInt(1.W)
|
||||
val SD = UInt(1.W)
|
||||
val TEST_RNM = UInt(1.W)
|
||||
val BC1 = UInt(1.W)
|
||||
val BC2 = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_dccm_ext_in_pkt_t extends Bundle {
|
||||
val TEST1 = UInt(1.W)
|
||||
val RME = UInt(1.W)
|
||||
val RM = UInt(4.W)
|
||||
val LS = UInt(1.W)
|
||||
val DS = UInt(1.W)
|
||||
val SD = UInt(1.W)
|
||||
val TEST_RNM = UInt(1.W)
|
||||
val BC1 = UInt(1.W)
|
||||
val BC2 = UInt(1.W)
|
||||
}
|
||||
|
||||
|
||||
class el2_ic_data_ext_in_pkt_t extends Bundle {
|
||||
val TEST1 = UInt(1.W)
|
||||
val RME = UInt(1.W)
|
||||
val RM = UInt(4.W)
|
||||
val LS = UInt(1.W)
|
||||
val DS = UInt(1.W)
|
||||
val SD = UInt(1.W)
|
||||
val TEST_RNM = UInt(1.W)
|
||||
val BC1 = UInt(1.W)
|
||||
val BC2 = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_ic_tag_ext_in_pkt_t extends Bundle {
|
||||
val TEST1 = UInt(1.W)
|
||||
val RME = UInt(1.W)
|
||||
val RM = UInt(4.W)
|
||||
val LS = UInt(1.W)
|
||||
val DS = UInt(1.W)
|
||||
val SD = UInt(1.W)
|
||||
val TEST_RNM = UInt(1.W)
|
||||
val BC1 = UInt(1.W)
|
||||
val BC2 = UInt(1.W)
|
||||
}
|
||||
|
||||
class el2_trigger_pkt_t extends Bundle {
|
||||
val select = UInt(1.W)
|
||||
val match_ = UInt(1.W)
|
||||
val store = UInt(1.W)
|
||||
val load = UInt(1.W)
|
||||
val execute = UInt(1.W)
|
||||
val m = UInt(1.W)
|
||||
val tdata2 = UInt(32.W)
|
||||
}
|
||||
|
||||
class el2_cache_debug_pkt_t extends Bundle {
|
||||
val icache_wrdata = UInt(71.W) // {dicad1[1:0], dicad0h[31:0], dicad0[31:0]}
|
||||
val icache_dicawics = UInt(17.W) // Arraysel:24, Waysel:21:20, Index:16:3
|
||||
val icache_rd_valid = UInt(1.W)
|
||||
val icache_wr_valid = UInt(1.W)
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ class rvdffsc extends Module with el2_lib {
|
|||
val clear = Input(Bool())
|
||||
val out = Output(UInt())
|
||||
})
|
||||
io.out := RegEnable(io.din & repl(io.din.getWidth, io.clear), 0.U, io.en)
|
||||
io.out := RegEnable(io.din & Fill(io.din.getWidth, ~io.clear), 0.U, io.en)
|
||||
}
|
||||
|
||||
class rvdffs extends Module with el2_lib {
|
||||
|
|
|
|||
|
|
@ -170,8 +170,9 @@ trait param {
|
|||
}
|
||||
|
||||
trait el2_lib extends param{
|
||||
|
||||
def el2_btb_tag_hash(pc : UInt) =
|
||||
(VecInit.tabulate(3)(i => pc(BTB_ADDR_HI+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE)+1))).reduce(_^_)
|
||||
VecInit.tabulate(3)(i => pc(BTB_ADDR_HI+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE)+1)).reduce(_^_)
|
||||
|
||||
def el2_btb_tag_hash_fold(pc : UInt) =
|
||||
pc(BTB_ADDR_HI+(2*BTB_BTAG_SIZE),BTB_ADDR_HI+BTB_BTAG_SIZE+1)^pc(BTB_ADDR_HI+BTB_BTAG_SIZE,BTB_ADDR_HI+1)
|
||||
|
|
|
|||
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Loading…
Reference in New Issue